diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/arm_common_tables.h b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/arm_common_tables.h
new file mode 100644
index 0000000000..dfea7460e9
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/arm_common_tables.h
@@ -0,0 +1,121 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_common_tables.h
+ * Description: Extern declaration for common tables
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
+#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
+#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
+#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
+#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
+#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
+#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
+#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /* ARM_COMMON_TABLES_H */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/arm_const_structs.h b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/arm_const_structs.h
new file mode 100644
index 0000000000..80a3e8bbe7
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/arm_const_structs.h
@@ -0,0 +1,66 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_const_structs.h
+ * Description: Constant structs that are initialized for user convenience.
+ * For example, some can be given as arguments to the arm_cfft_f32() function.
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/arm_math.h b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/arm_math.h
new file mode 100644
index 0000000000..d6b5b2b1ce
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/arm_math.h
@@ -0,0 +1,7157 @@
+/******************************************************************************
+ * @file arm_math.h
+ * @brief Public header file for CMSIS DSP LibraryU
+ * @version V1.5.3
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ \mainpage CMSIS DSP Software Library
+ *
+ * Introduction
+ * ------------
+ *
+ * This user manual describes the CMSIS DSP software library,
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.
+ *
+ * The library is divided into a number of functions each covering a specific category:
+ * - Basic math functions
+ * - Fast math functions
+ * - Complex math functions
+ * - Filters
+ * - Matrix functions
+ * - Transforms
+ * - Motor control functions
+ * - Statistical functions
+ * - Support functions
+ * - Interpolation functions
+ *
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+ * 32-bit integer and 32-bit floating-point values.
+ *
+ * Using the Library
+ * ------------
+ *
+ * The library installer contains prebuilt versions of the libraries in the Lib folder.
+ * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)
+ * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)
+ * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)
+ * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)
+ * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)
+ * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)
+ * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)
+ * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)
+ * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)
+ * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)
+ * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)
+ * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)
+ * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)
+ * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)
+ * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian)
+ * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian)
+ * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit)
+ * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions)
+ * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
+ *
+ * The library functions are declared in the public file arm_math.h which is placed in the Include folder.
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+ * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+ * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or
+ * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+ * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
+ * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions.
+ *
+ *
+ * Examples
+ * --------
+ *
+ * The library ships with a number of examples which demonstrate how to use the library functions.
+ *
+ * Toolchain Support
+ * ------------
+ *
+ * The library has been developed and tested with MDK version 5.14.0.0
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+ *
+ * Building the Library
+ * ------------
+ *
+ * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP_Lib\\Source\\ARM folder.
+ * - arm_cortexM_math.uvprojx
+ *
+ *
+ * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above.
+ *
+ * Preprocessor Macros
+ * ------------
+ *
+ * Each library project have different preprocessor macros.
+ *
+ * - UNALIGNED_SUPPORT_DISABLE:
+ *
+ * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+ *
+ * - ARM_MATH_BIG_ENDIAN:
+ *
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+ *
+ * - ARM_MATH_MATRIX_CHECK:
+ *
+ * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+ *
+ * - ARM_MATH_ROUNDING:
+ *
+ * Define macro ARM_MATH_ROUNDING for rounding on support functions
+ *
+ * - ARM_MATH_CMx:
+ *
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+ * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+ * ARM_MATH_CM7 for building the library on cortex-M7.
+ *
+ * - ARM_MATH_ARMV8MxL:
+ *
+ * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library
+ * on Armv8-M Mainline target.
+ *
+ * - __FPU_PRESENT:
+ *
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries.
+ *
+ * - __DSP_PRESENT:
+ *
+ * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions.
+ *
+ *
+ * CMSIS-DSP in ARM::CMSIS Pack
+ * -----------------------------
+ *
+ * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories:
+ * |File/Folder |Content |
+ * |------------------------------|------------------------------------------------------------------------|
+ * |\b CMSIS\\Documentation\\DSP | This documentation |
+ * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) |
+ * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions |
+ * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library |
+ *
+ *
+ * Revision History of CMSIS-DSP
+ * ------------
+ * Please refer to \ref ChangeLog_pg.
+ *
+ * Copyright Notice
+ * ------------
+ *
+ * Copyright (C) 2010-2015 Arm Limited. All rights reserved.
+ */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures. For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ *
+ * typedef struct
+ * {
+ * uint16_t numRows; // number of rows of the matrix.
+ * uint16_t numCols; // number of columns of the matrix.
+ * float32_t *pData; // points to the data of the matrix.
+ * } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data. The array is of size numRows X numCols
+ * and the values are arranged in row order. That is, the
+ * matrix element (i, j) is stored at:
+ *
+ * pData[i*numCols + j]
+ *
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function arm_mat_init_f32(), arm_mat_init_q31()
+ * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure. For example:
+ *
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns
+ * specifies the number of columns, and pData points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices. For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns. If the size check fails the functions return:
+ *
+ * ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return
+ *
+ * ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ *
+ * ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined
+ * and size checking is enabled. By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster. With size checking disabled the functions always
+ * return ARM_MATH_SUCCESS.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+/* Compiler specific diagnostic adjustment */
+#if defined ( __CC_ARM )
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+#elif defined ( __ICCARM__ )
+
+#elif defined ( __TI_ARM__ )
+
+#elif defined ( __CSMC__ )
+
+#elif defined ( __TASKING__ )
+
+#else
+ #error Unknown compiler
+#endif
+
+
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+ #include "core_cm7.h"
+ #define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM4)
+ #include "core_cm4.h"
+ #define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM3)
+ #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+ #include "core_cm0.h"
+ #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+ #include "core_cm0plus.h"
+ #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MBL)
+ #include "core_armv8mbl.h"
+ #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MML)
+ #include "core_armv8mml.h"
+ #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1))
+ #define ARM_MATH_DSP
+ #endif
+#else
+ #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML"
+#endif
+
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+ /**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31 (0x100)
+#define DELTA_Q15 0x5
+#define INDEX_MASK 0x0000003F
+#ifndef PI
+ #define PI 3.14159265358979f
+#endif
+
+ /**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define FAST_MATH_TABLE_SIZE 512
+#define FAST_MATH_Q31_SHIFT (32 - 10)
+#define FAST_MATH_Q15_SHIFT (16 - 10)
+#define CONTROLLER_Q31_SHIFT (32 - 9)
+#define TABLE_SPACING_Q31 0x400000
+#define TABLE_SPACING_Q15 0x80
+
+ /**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+ /* 1.31(q31) Fixed value of 2/360 */
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING 0xB60B61
+
+ /**
+ * @brief Macro for Unaligned Support
+ */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+ #define ALIGN4
+#else
+ #if defined (__GNUC__)
+ #define ALIGN4 __attribute__((aligned(4)))
+ #else
+ #define ALIGN4 __align(4)
+ #endif
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /**
+ * @brief Error status returned by some functions in the library.
+ */
+
+ typedef enum
+ {
+ ARM_MATH_SUCCESS = 0, /**< No error */
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
+ } arm_status;
+
+ /**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+ typedef int8_t q7_t;
+
+ /**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+ typedef int16_t q15_t;
+
+ /**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+ typedef int32_t q31_t;
+
+ /**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+ typedef int64_t q63_t;
+
+ /**
+ * @brief 32-bit floating-point type definition.
+ */
+ typedef float float32_t;
+
+ /**
+ * @brief 64-bit floating-point type definition.
+ */
+ typedef double float64_t;
+
+ /**
+ * @brief definition to read/write two 16 bit values.
+ */
+#if defined ( __CC_ARM )
+ #define __SIMD32_TYPE int32_t __packed
+ #define CMSIS_UNUSED __attribute__((unused))
+ #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED __attribute__((unused))
+ #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __GNUC__ )
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED __attribute__((unused))
+ #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ICCARM__ )
+ #define __SIMD32_TYPE int32_t __packed
+ #define CMSIS_UNUSED
+ #define CMSIS_INLINE
+
+#elif defined ( __TI_ARM__ )
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED __attribute__((unused))
+ #define CMSIS_INLINE
+
+#elif defined ( __CSMC__ )
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED
+ #define CMSIS_INLINE
+
+#elif defined ( __TASKING__ )
+ #define __SIMD32_TYPE __unaligned int32_t
+ #define CMSIS_UNUSED
+ #define CMSIS_INLINE
+
+#else
+ #error Unknown compiler
+#endif
+
+#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))
+#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))
+#define __SIMD64(addr) (*(int64_t **) & (addr))
+
+#if !defined (ARM_MATH_DSP)
+ /**
+ * @brief definition to pack two 16 bit values.
+ */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
+
+#endif /* !defined (ARM_MATH_DSP) */
+
+ /**
+ * @brief definition to pack four 8 bit values.
+ */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
+
+#endif
+
+
+ /**
+ * @brief Clips Q63 to Q31 values.
+ */
+ CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+ }
+
+ /**
+ * @brief Clips Q63 to Q15 values.
+ */
+ CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+ }
+
+ /**
+ * @brief Clips Q31 to Q7 values.
+ */
+ CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+ }
+
+ /**
+ * @brief Clips Q31 to Q15 values.
+ */
+ CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+ }
+
+ /**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+
+ CMSIS_INLINE __STATIC_INLINE q63_t mult32x64(
+ q63_t x,
+ q31_t y)
+ {
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+ (((q63_t) (x >> 32) * y)));
+ }
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+ */
+
+ CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31(
+ q31_t in,
+ q31_t * dst,
+ q31_t * pRecipTable)
+ {
+ q31_t out;
+ uint32_t tempVal;
+ uint32_t index, i;
+ uint32_t signBits;
+
+ if (in > 0)
+ {
+ signBits = ((uint32_t) (__CLZ( in) - 1));
+ }
+ else
+ {
+ signBits = ((uint32_t) (__CLZ(-in) - 1));
+ }
+
+ /* Convert input sample to 1.31 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 24);
+ index = (index & INDEX_MASK);
+
+ /* 1.31 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0U; i < 2U; i++)
+ {
+ tempVal = (uint32_t) (((q63_t) in * out) >> 31);
+ tempVal = 0x7FFFFFFFu - tempVal;
+ /* 1.31 with exp 1 */
+ /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
+ out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1U);
+ }
+
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15(
+ q15_t in,
+ q15_t * dst,
+ q15_t * pRecipTable)
+ {
+ q15_t out = 0;
+ uint32_t tempVal = 0;
+ uint32_t index = 0, i = 0;
+ uint32_t signBits = 0;
+
+ if (in > 0)
+ {
+ signBits = ((uint32_t)(__CLZ( in) - 17));
+ }
+ else
+ {
+ signBits = ((uint32_t)(__CLZ(-in) - 17));
+ }
+
+ /* Convert input sample to 1.15 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 8);
+ index = (index & INDEX_MASK);
+
+ /* 1.15 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0U; i < 2U; i++)
+ {
+ tempVal = (uint32_t) (((q31_t) in * out) >> 15);
+ tempVal = 0x7FFFu - tempVal;
+ /* 1.15 with exp 1 */
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);
+ /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1);
+ }
+
+
+/*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+#if !defined (ARM_MATH_DSP)
+
+ /*
+ * @brief C custom defined QADD8 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB8 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */
+ q31_t r = 0, s = 0;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHADD16 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB16 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSUB16 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QASX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHASX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSAX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSAX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSDX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+ /*
+ * @brief C custom defined SMUADX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined QADD for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE int32_t __QADD(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE int32_t __QSUB(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined SMLAD for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLADX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLSDX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALD for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALDX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUAD for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSD for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SXTB16 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16(
+ uint32_t x)
+ {
+ return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
+ ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) ));
+ }
+
+ /*
+ * @brief C custom defined SMMLA for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA(
+ int32_t x,
+ int32_t y,
+ int32_t sum)
+ {
+ return (sum + (int32_t) (((int64_t) x * y) >> 32));
+ }
+
+#endif /* !defined (ARM_MATH_DSP) */
+
+
+ /**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q7;
+
+ /**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] S points to an instance of the Q7 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q7(
+ const arm_fir_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 FIR filter.
+ * @param[in,out] S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ */
+ void arm_fir_init_q7(
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] S points to an instance of the Q15 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR filter.
+ * @param[in,out] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+ * numTaps is not a supported value.
+ */
+ arm_status arm_fir_init_q15(
+ arm_fir_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] S points to an instance of the Q31 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR filter.
+ * @param[in,out] S points to an instance of the Q31 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_q31(
+ arm_fir_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] S points to an instance of the floating-point FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_f32(
+ const arm_fir_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_f32(
+ arm_fir_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q15;
+
+ /**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q31;
+
+ /**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_casd_df1_inst_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float32_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f32;
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float64_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f64;
+
+ /**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q15_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q31_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q31;
+
+
+ /**
+ * @brief Floating-point matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Q31, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+
+ /**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+
+ /**
+ * @brief Q31 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix scaling.
+ * @param[in] pSrc points to the input matrix
+ * @param[in] scale scale factor
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_q31(
+ arm_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t * pData);
+
+
+ /**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_q15(
+ arm_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t * pData);
+
+
+ /**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_f32(
+ arm_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t * pData);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+ typedef struct
+ {
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+#if !defined (ARM_MATH_DSP)
+ q15_t A1;
+ q15_t A2;
+#else
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+ q15_t state[3]; /**< The state array of length 3. */
+ q15_t Kp; /**< The proportional gain. */
+ q15_t Ki; /**< The integral gain. */
+ q15_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+ typedef struct
+ {
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ q31_t A2; /**< The derived gain, A2 = Kd . */
+ q31_t state[3]; /**< The state array of length 3. */
+ q31_t Kp; /**< The proportional gain. */
+ q31_t Ki; /**< The integral gain. */
+ q31_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+ typedef struct
+ {
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ float32_t A2; /**< The derived gain, A2 = Kd . */
+ float32_t state[3]; /**< The state array of length 3. */
+ float32_t Kp; /**< The proportional gain. */
+ float32_t Ki; /**< The integral gain. */
+ float32_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_f32;
+
+
+
+ /**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ */
+ void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S);
+
+
+ /**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ */
+
+ void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S);
+
+
+ /**
+ * @brief Initialization function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the q15 PID Control structure
+ */
+ void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S);
+
+
+ /**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+ typedef struct
+ {
+ uint32_t nValues; /**< nValues */
+ float32_t x1; /**< x1 */
+ float32_t xSpacing; /**< xSpacing */
+ float32_t *pYData; /**< pointer to the table of Y values */
+ } arm_linear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ float32_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q31_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q15_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q7_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q7;
+
+
+ /**
+ * @brief Q7 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q15(
+ arm_cfft_radix2_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q31(
+ arm_cfft_radix2_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q31(
+ const arm_cfft_radix2_instance_q31 * S,
+ q31_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+ void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc);
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_f32(
+ const arm_cfft_radix2_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q15_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_q15;
+
+void arm_cfft_q15(
+ const arm_cfft_instance_q15 * S,
+ q15_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_q31;
+
+void arm_cfft_q31(
+ const arm_cfft_instance_q31 * S,
+ q31_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_f32;
+
+ void arm_cfft_f32(
+ const arm_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q15;
+
+ arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst);
+
+ /**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q31;
+
+ arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint16_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_f32;
+
+ arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_f32(
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+typedef struct
+ {
+ arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
+ uint16_t fftLenRFFT; /**< length of the real sequence */
+ float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
+ } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+ arm_rfft_fast_instance_f32 * S,
+ uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+ arm_rfft_fast_instance_f32 * S,
+ float32_t * p, float32_t * pOut,
+ uint8_t ifftFlag);
+
+ /**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ float32_t normalize; /**< normalizing factor. */
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ float32_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.
+ */
+ arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize);
+
+
+ /**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q31_t normalize; /**< normalizing factor. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ q31_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q31;
+
+
+ /**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31 * S,
+ arm_rfft_instance_q31 * S_RFFT,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q31 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q15_t normalize; /**< normalizing factor. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ q15_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15 * S,
+ arm_rfft_instance_q15 * S_RFFT,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q15 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer);
+
+
+ /**
+ * @brief Floating-point vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_f32(
+ float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q7(
+ q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q15(
+ q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q31(
+ q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result);
+
+
+ /**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result);
+
+
+ /**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q7(
+ q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q15(
+ q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q31(
+ q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_f32(
+ float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q7(
+ q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q15(
+ q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q31(
+ q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point FIR decimator.
+ * @param[in] S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR decimator.
+ * @param[in,out] S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+ arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+ arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q31(
+ arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+ arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+ } arm_fir_interpolate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+ arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+ arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+ arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
+ } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+ /**
+ * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f64;
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f32(
+ const arm_biquad_cascade_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_stereo_df2T_f32(
+ const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f64(
+ const arm_biquad_cascade_df2T_instance_f64 * S,
+ float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_stereo_df2T_init_f32(
+ arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f64(
+ arm_biquad_cascade_df2T_instance_f64 * S,
+ uint8_t numStages,
+ float64_t * pCoeffs,
+ float64_t * pState);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pkCoeffs,
+ float32_t * pvCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pkCoeffs,
+ q31_t * pvCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ */
+ void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pkCoeffs,
+ q15_t * pvCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that controls filter coefficient updates. */
+ } arm_lms_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_init_f32(
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q15(
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q15(
+ const arm_lms_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q31(
+ const arm_lms_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q31(
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that control filter coefficient updates. */
+ float32_t energy; /**< saves previous frame energy. */
+ float32_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q31_t *recipTable; /**< points to the reciprocal initial value table. */
+ q31_t energy; /**< saves previous frame energy. */
+ q31_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< Number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q15_t *recipTable; /**< Points to the reciprocal initial value table. */
+ q15_t energy; /**< saves previous frame energy. */
+ q15_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q15;
+
+
+ /**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+ void arm_correlate_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+ void arm_correlate_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+ void arm_correlate_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+ void arm_correlate_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_correlate_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q7;
+
+
+ /**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cos output.
+ */
+ void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCosVal);
+
+
+ /**
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cosine output.
+ */
+ void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal);
+
+
+ /**
+ * @brief Floating-point complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * S points to an instance of the PID control data structure. in
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ *
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ * A0 = Kp + Ki + Kd
+ * A1 = (-Kp ) - (2 * Kd )
+ * A2 = Kd
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ */
+ CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32(
+ arm_pid_instance_f32 * S,
+ float32_t in)
+ {
+ float32_t out;
+
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
+ out = (S->A0 * in) +
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @brief Process function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+ CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31(
+ arm_pid_instance_q31 * S,
+ q31_t in)
+ {
+ q63_t acc;
+ q31_t out;
+
+ /* acc = A0 * x[n] */
+ acc = (q63_t) S->A0 * in;
+
+ /* acc += A1 * x[n-1] */
+ acc += (q63_t) S->A1 * S->state[0];
+
+ /* acc += A2 * x[n-2] */
+ acc += (q63_t) S->A2 * S->state[1];
+
+ /* convert output to 1.31 format to add y[n-1] */
+ out = (q31_t) (acc >> 31U);
+
+ /* out += y[n-1] */
+ out += S->state[2];
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+
+ /**
+ * @brief Process function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+ CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15(
+ arm_pid_instance_q15 * S,
+ q15_t in)
+ {
+ q63_t acc;
+ q15_t out;
+
+#if defined (ARM_MATH_DSP)
+ __SIMD32_TYPE *vstate;
+
+ /* Implementation of PID controller */
+
+ /* acc = A0 * x[n] */
+ acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ vstate = __SIMD32_CONST(S->state);
+ acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);
+#else
+ /* acc = A0 * x[n] */
+ acc = ((q31_t) S->A0) * in;
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc += (q31_t) S->A1 * S->state[0];
+ acc += (q31_t) S->A2 * S->state[1];
+#endif
+
+ /* acc += y[n-1] */
+ acc += (q31_t) S->state[2] << 15;
+
+ /* saturate the output */
+ out = (q15_t) (__SSAT((acc >> 15), 16));
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+ /**
+ * @} end of PID group
+ */
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f32(
+ const arm_matrix_instance_f32 * src,
+ arm_matrix_instance_f32 * dst);
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f64(
+ const arm_matrix_instance_f64 * src,
+ arm_matrix_instance_f64 * dst);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents
+ * in the two-phase orthogonal stator axis Ialpha and Ibeta.
+ * When Ialpha is superposed with Ia as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta
+ * can be calculated using only Ia and Ib.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where Ia and Ib are the instantaneous stator phases and
+ * pIalpha and pIbeta are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup clarke
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point Clarke transform
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32(
+ float32_t Ia,
+ float32_t Ib,
+ float32_t * pIalpha,
+ float32_t * pIbeta)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+ }
+
+
+ /**
+ * @brief Clarke transform for Q31 version
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31(
+ q31_t Ia,
+ q31_t Ib,
+ q31_t * pIalpha,
+ q31_t * pIbeta)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+ /* pIbeta is calculated by adding the intermediate products */
+ *pIbeta = __QADD(product1, product2);
+ }
+
+ /**
+ * @} end of clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q31(
+ q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where pIa and pIb are the instantaneous stator phases and
+ * Ialpha and Ibeta are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Clarke transform
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] pIa points to output three-phase coordinate a
+ * @param[out] pIb points to output three-phase coordinate b
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pIa,
+ float32_t * pIb)
+ {
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+ *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
+ }
+
+
+ /**
+ * @brief Inverse Clarke transform for Q31 version
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] pIa points to output three-phase coordinate a
+ * @param[out] pIb points to output three-phase coordinate b
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pIa,
+ q31_t * pIb)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+ /* pIb is calculated by subtracting the products */
+ *pIb = __QSUB(product2, product1);
+ }
+
+ /**
+ * @} end of inv_clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q15(
+ q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where Ialpha and Ibeta are the stator vector components,
+ * pId and pIq are rotor vector components and cosVal and sinVal are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Park transform
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_park_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pId,
+ float32_t * pIq,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+ *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+ }
+
+
+ /**
+ * @brief Park transform for Q31 version
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_park_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pId,
+ q31_t * pIq,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Ialpha * cosVal) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * sinVal) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Ialpha * sinVal) */
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * cosVal) */
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+ /* Calculate pId by adding the two intermediate products 1 and 2 */
+ *pId = __QADD(product1, product2);
+
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+ *pIq = __QSUB(product4, product3);
+ }
+
+ /**
+ * @} end of park group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q7_to_float(
+ q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where pIalpha and pIbeta are the stator vector components,
+ * Id and Iq are rotor vector components and cosVal and sinVal are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Park transform
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32(
+ float32_t Id,
+ float32_t Iq,
+ float32_t * pIalpha,
+ float32_t * pIbeta,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+ *pIalpha = Id * cosVal - Iq * sinVal;
+
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+ *pIbeta = Id * sinVal + Iq * cosVal;
+ }
+
+
+ /**
+ * @brief Inverse Park transform for Q31 version
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31(
+ q31_t Id,
+ q31_t Iq,
+ q31_t * pIalpha,
+ q31_t * pIbeta,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Id * cosVal) */
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * sinVal) */
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Id * sinVal) */
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * cosVal) */
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+ *pIalpha = __QSUB(product1, product2);
+
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+ *pIbeta = __QADD(product4, product3);
+ }
+
+ /**
+ * @} end of Inverse park group
+ */
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_float(
+ q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ *
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ * where x0, x1 are nearest values of input x
+ * y0, y1 are nearest values to output y
+ *
+ *
+ * \par
+ * This set of functions implements Linear interpolation process
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
+ * sample of data and each call to the function returns a single processed value.
+ * S points to an instance of the Linear Interpolate function data structure.
+ * x is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+ /**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+ CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32(
+ arm_linear_interp_instance_f32 * S,
+ float32_t x)
+ {
+ float32_t y;
+ float32_t x0, x1; /* Nearest input values */
+ float32_t y0, y1; /* Nearest output values */
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */
+ int32_t i; /* Index variable */
+ float32_t *pYData = S->pYData; /* pointer to output table */
+
+ /* Calculation of index */
+ i = (int32_t) ((x - S->x1) / xSpacing);
+
+ if (i < 0)
+ {
+ /* Iniatilize output for below specified range as least output value of table */
+ y = pYData[0];
+ }
+ else if ((uint32_t)i >= S->nValues)
+ {
+ /* Iniatilize output for above specified range as last output value of table */
+ y = pYData[S->nValues - 1];
+ }
+ else
+ {
+ /* Calculation of nearest input values */
+ x0 = S->x1 + i * xSpacing;
+ x1 = S->x1 + (i + 1) * xSpacing;
+
+ /* Read of nearest output values */
+ y0 = pYData[i];
+ y1 = pYData[i + 1];
+
+ /* Calculation of output */
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+ }
+
+ /* returns output value */
+ return (y);
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q31 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q31 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31(
+ q31_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q31_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (q31_t)0xFFF00000) >> 20);
+
+ if (index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if (index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* shift left by 11 to keep fract in 1.31 format */
+ fract = (x & 0x000FFFFF) << 11;
+
+ /* Read two nearest output values from the index in 1.31(q31) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+ /* Convert y to 1.31 format */
+ return (y << 1U);
+ }
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q15 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15(
+ q15_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q63_t y; /* output */
+ q15_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (int32_t)0xFFF00000) >> 20);
+
+ if (index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if (index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+ y = ((q63_t) y0 * (0xFFFFF - fract));
+
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+ y += ((q63_t) y1 * (fract));
+
+ /* convert y to 1.15 format */
+ return (q15_t) (y >> 20);
+ }
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q7 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+ CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7(
+ q7_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q7_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ uint32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ if (x < 0)
+ {
+ return (pYData[0]);
+ }
+ index = (x >> 20) & 0xfff;
+
+ if (index >= (nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index and are in 1.7(q7) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+ y = ((y0 * (0xFFFFF - fract)));
+
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+ y += (y1 * fract);
+
+ /* convert y to 1.7(q7) format */
+ return (q7_t) (y >> 20);
+ }
+ }
+
+ /**
+ * @} end of LinearInterpolate group
+ */
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+ float32_t arm_sin_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q31_t arm_sin_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q15_t arm_sin_q15(
+ q15_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+ float32_t arm_cos_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q31_t arm_cos_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q15_t arm_cos_q15(
+ q15_t x);
+
+
+ /**
+ * @ingroup groupFastMath
+ */
+
+
+ /**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ *
+ * x1 = x0 - f(x0)/f'(x0)
+ *
+ * where x1 is the current estimate,
+ * x0 is the previous estimate, and
+ * f'(x0) is the derivative of f() evaluated at x0.
+ * For the square root function, the algorithm reduces to:
+ *
+ * x0 = in/2 [initial guess]
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]
+ *
+ */
+
+
+ /**
+ * @addtogroup SQRT
+ * @{
+ */
+
+ /**
+ * @brief Floating-point square root function.
+ * @param[in] in input value.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+ CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32(
+ float32_t in,
+ float32_t * pOut)
+ {
+ if (in >= 0.0f)
+ {
+
+#if (__FPU_USED == 1) && defined ( __CC_ARM )
+ *pOut = __sqrtf(in);
+#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+ *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined(__GNUC__)
+ *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
+ __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
+#else
+ *pOut = sqrtf(in);
+#endif
+
+ return (ARM_MATH_SUCCESS);
+ }
+ else
+ {
+ *pOut = 0.0f;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+ }
+
+
+ /**
+ * @brief Q31 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q31(
+ q31_t in,
+ q31_t * pOut);
+
+
+ /**
+ * @brief Q15 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q15(
+ q15_t in,
+ q15_t * pOut);
+
+ /**
+ * @} end of SQRT group
+ */
+
+
+ /**
+ * @brief floating-point Circular write function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const int32_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+
+ /**
+ * @brief floating-point Circular Read function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ int32_t * dst,
+ int32_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == (int32_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular write function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q15_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular Read function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q15_t * dst,
+ q15_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == (q15_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular write function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q7_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular Read function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q7_t * dst,
+ q7_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == (q7_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Floating-point complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult);
+
+
+ /**
+ * @brief Q31 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult);
+
+
+ /**
+ * @brief Floating-point complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult);
+
+
+ /**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q15(
+ q15_t * pSrcCmplx,
+ q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q31(
+ q31_t * pSrcCmplx,
+ q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_f32(
+ float32_t * pSrcCmplx,
+ float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] result is output pointer
+ * @param[in] index is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * result,
+ uint32_t * index);
+
+
+ /**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[in] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q31(
+ float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q15(
+ float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q7(
+ float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q15(
+ q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q7(
+ q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_float(
+ q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q31(
+ q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q7(
+ q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function f(x, y) is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * Algorithm
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ *
+ * typedef struct
+ * {
+ * uint16_t numRows;
+ * uint16_t numCols;
+ * float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ *
+ *
+ * \par
+ * where numRows specifies the number of rows in the table;
+ * numCols specifies the number of columns in the table;
+ * and pData points to an array of size numRows*numCols values.
+ * The data table pTable is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers.
+ *
+ * \par
+ * Let (x, y) specify the desired interpolation point. Then define:
+ *
+ * XF = floor(x)
+ * YF = floor(y)
+ *
+ * \par
+ * The interpolated output point is computed as:
+ *
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ *
+ * Note that the coordinates (x, y) contain integer and fractional components.
+ * The integer components specify which portion of the table to use while the
+ * fractional components control the interpolation processor.
+ *
+ * \par
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+ */
+
+ /**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+
+ /**
+ *
+ * @brief Floating-point bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate.
+ * @param[in] Y interpolation coordinate.
+ * @return out interpolated value.
+ */
+ CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32(
+ const arm_bilinear_interp_instance_f32 * S,
+ float32_t X,
+ float32_t Y)
+ {
+ float32_t out;
+ float32_t f00, f01, f10, f11;
+ float32_t *pData = S->pData;
+ int32_t xIndex, yIndex, index;
+ float32_t xdiff, ydiff;
+ float32_t b1, b2, b3, b4;
+
+ xIndex = (int32_t) X;
+ yIndex = (int32_t) Y;
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* Calculation of index for two nearest points in X-direction */
+ index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+ /* Read two nearest points in X-direction */
+ f00 = pData[index];
+ f01 = pData[index + 1];
+
+ /* Calculation of index for two nearest points in Y-direction */
+ index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+ /* Read two nearest points in Y-direction */
+ f10 = pData[index];
+ f11 = pData[index + 1];
+
+ /* Calculation of intermediate values */
+ b1 = f00;
+ b2 = f01 - f00;
+ b3 = f10 - f00;
+ b4 = f00 - f01 - f10 + f11;
+
+ /* Calculation of fractional part in X */
+ xdiff = X - xIndex;
+
+ /* Calculation of fractional part in Y */
+ ydiff = Y - yIndex;
+
+ /* Calculation of bi-linear interpolated output */
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+ /* return to application */
+ return (out);
+ }
+
+
+ /**
+ *
+ * @brief Q31 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31(
+ arm_bilinear_interp_instance_q31 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q31_t out; /* Temporary output */
+ q31_t acc = 0; /* output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q31_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q31_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* shift left xfract by 11 to keep 1.31 format */
+ xfract = (X & 0x000FFFFF) << 11U;
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + (int32_t)nCols * (cI) ];
+ x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* shift left yfract by 11 to keep 1.31 format */
+ yfract = (Y & 0x000FFFFF) << 11U;
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ];
+ y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* Convert acc to 1.31(q31) format */
+ return ((q31_t)(acc << 2));
+ }
+
+
+ /**
+ * @brief Q15 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15(
+ arm_bilinear_interp_instance_q15 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q15_t x1, x2, y1, y2; /* Nearest output values */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ int32_t rI, cI; /* Row and column indices */
+ q15_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U);
+ acc = ((q63_t) out * (0xFFFFF - yfract));
+
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U);
+ acc += ((q63_t) out * (xfract));
+
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U);
+ acc += ((q63_t) out * (yfract));
+
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U);
+ acc += ((q63_t) out * (yfract));
+
+ /* acc is in 13.51 format and down shift acc by 36 times */
+ /* Convert out to 1.15 format */
+ return ((q15_t)(acc >> 36));
+ }
+
+
+ /**
+ * @brief Q7 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7(
+ arm_bilinear_interp_instance_q7 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q7_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q7_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+ out = ((x1 * (0xFFFFF - xfract)));
+ acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
+ out = ((x2 * (0xFFFFF - yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y1 * (0xFFFFF - xfract)));
+ acc += (((q63_t) out * (yfract)));
+
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y2 * (yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+ return ((q7_t)(acc >> 40));
+ }
+
+ /**
+ * @} end of BilinearInterpolate group
+ */
+
+
+/* SMMLAR */
+#define multAcc_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMLSR */
+#define multSub_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMULR */
+#define mult_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+/* SMMLA */
+#define multAcc_32x32_keep32(a, x, y) \
+ a += (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMLS */
+#define multSub_32x32_keep32(a, x, y) \
+ a -= (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMUL */
+#define mult_32x32_keep32(a, x, y) \
+ a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM )
+ /* Enter low optimization region - place directly above function definition */
+ #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("push") \
+ _Pragma ("O1")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+ #define LOW_OPTIMIZATION_EXIT \
+ _Pragma ("pop")
+ #else
+ #define LOW_OPTIMIZATION_EXIT
+ #endif
+
+ /* Enter low optimization region - place directly above function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __GNUC__ )
+ #define LOW_OPTIMIZATION_ENTER \
+ __attribute__(( optimize("-O1") ))
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __ICCARM__ )
+ /* Enter low optimization region - place directly above function definition */
+ #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define LOW_OPTIMIZATION_EXIT
+
+ /* Enter low optimization region - place directly above function definition */
+ #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TI_ARM__ )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __CSMC__ )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TASKING__ )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/* Compiler specific diagnostic adjustment */
+#if defined ( __CC_ARM )
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+
+#elif defined ( __ICCARM__ )
+
+#elif defined ( __TI_ARM__ )
+
+#elif defined ( __CSMC__ )
+
+#elif defined ( __TASKING__ )
+
+#else
+ #error Unknown compiler
+#endif
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_armcc.h b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_armcc.h
new file mode 100644
index 0000000000..a4c67e0268
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_armcc.h
@@ -0,0 +1,865 @@
+/**************************************************************************//**
+ * @file cmsis_armcc.h
+ * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+ #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
+ (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
+ #define __ARM_ARCH_6M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
+ #define __ARM_ARCH_7M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+ #define __ARM_ARCH_7EM__ 1
+#endif
+
+ /* __ARM_ARCH_8M_BASE__ not applicable */
+ /* __ARM_ARCH_8M_MAIN__ not applicable */
+
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE static __forceinline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __declspec(noreturn)
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT __packed struct
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION __packed union
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); */
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() do {\
+ __schedule_barrier();\
+ __isb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+ __schedule_barrier();\
+ __dsb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+ __schedule_barrier();\
+ __dmb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+ #define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+ return result;
+}
+#endif
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+#else
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+#else
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+#else
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXB(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXH(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXW(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32U) ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_armclang.h b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_armclang.h
new file mode 100644
index 0000000000..a1722f87a8
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_armclang.h
@@ -0,0 +1,1869 @@
+/**************************************************************************//**
+ * @file cmsis_armclang.h
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR() ((uint32_t)0U)
+#endif
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __set_FPSCR __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x) ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF);
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF);
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF);
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV(value) __builtin_bswap32(value)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __builtin_arm_rbit
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_compiler.h b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_compiler.h
new file mode 100644
index 0000000000..adfd3c2504
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_compiler.h
@@ -0,0 +1,266 @@
+/**************************************************************************//**
+ * @file cmsis_compiler.h
+ * @brief CMSIS compiler generic header file
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include
+
+/*
+ * Arm Compiler 4/5
+ */
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+ #include
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+ #include
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed))
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed))
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __packed__
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __packed__
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __packed__
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __packed__ T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __align(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+ #include
+
+ #ifndef __ASM
+ #define __ASM _asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ // NO RETURN is automatically detected hence no warning here
+ #define __NO_RETURN
+ #endif
+ #ifndef __USED
+ #warning No compiler specific solution for __USED. __USED is ignored.
+ #define __USED
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __weak
+ #endif
+ #ifndef __PACKED
+ #define __PACKED @packed
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT @packed struct
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION @packed union
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ @packed struct T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+
+#else
+ #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_gcc.h b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_gcc.h
new file mode 100644
index 0000000000..cd374afaef
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_gcc.h
@@ -0,0 +1,2085 @@
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS compiler GCC header file
+ * @version V5.0.4
+ * @date 09. April 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+ #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_get_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ return __builtin_arm_get_fpscr();
+#else
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#endif
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ __builtin_arm_set_fpscr(fpscr);
+#else
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP() __ASM volatile ("nop")
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI() __ASM volatile ("wfi")
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE() __ASM volatile ("wfe")
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV() __ASM volatile ("sev")
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (int16_t)__builtin_bswap16(value);
+#else
+ int16_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return result;
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ __extension__ \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_iccarm.h b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_iccarm.h
new file mode 100644
index 0000000000..931db1d514
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_iccarm.h
@@ -0,0 +1,935 @@
+/**************************************************************************//**
+ * @file cmsis_iccarm.h
+ * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version V5.0.7
+ * @date 19. June 2018
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2018 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+ #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+ #define __ICCARM_V8 1
+#else
+ #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+ #if __ICCARM_V8
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #elif (__VER__ >= 7080000)
+ /* Needs IAR language extensions */
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #else
+ #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+ #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+ #if __ARM_ARCH == 6
+ #define __ARM_ARCH_6M__ 1
+ #elif __ARM_ARCH == 7
+ #if __ARM_FEATURE_DSP
+ #define __ARM_ARCH_7EM__ 1
+ #else
+ #define __ARM_ARCH_7M__ 1
+ #endif
+ #endif /* __ARM_ARCH */
+ #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+ !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+ #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+ #define __ARM_ARCH_6M__ 1
+ #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+ #define __ARM_ARCH_7M__ 1
+ #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+ #define __ARM_ARCH_7EM__ 1
+ #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #else
+ #error "Unknown target."
+ #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+ #define __IAR_M0_FAMILY 1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+ #define __IAR_M0_FAMILY 1
+#else
+ #define __IAR_M0_FAMILY 0
+#endif
+
+
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+
+#ifndef __NO_RETURN
+ #if __ICCARM_V8
+ #define __NO_RETURN __attribute__((__noreturn__))
+ #else
+ #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+ #endif
+#endif
+
+#ifndef __PACKED
+ #if __ICCARM_V8
+ #define __PACKED __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED __packed
+ #endif
+#endif
+
+#ifndef __PACKED_STRUCT
+ #if __ICCARM_V8
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_STRUCT __packed struct
+ #endif
+#endif
+
+#ifndef __PACKED_UNION
+ #if __ICCARM_V8
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_UNION __packed union
+ #endif
+#endif
+
+#ifndef __RESTRICT
+ #define __RESTRICT restrict
+#endif
+
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+
+#ifndef __FORCEINLINE
+ #define __FORCEINLINE _Pragma("inline=forced")
+#endif
+
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+ return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+ *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+ return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+ *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef __USED
+ #if __ICCARM_V8
+ #define __USED __attribute__((used))
+ #else
+ #define __USED _Pragma("__root")
+ #endif
+#endif
+
+#ifndef __WEAK
+ #if __ICCARM_V8
+ #define __WEAK __attribute__((weak))
+ #else
+ #define __WEAK _Pragma("__weak")
+ #endif
+#endif
+
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+ #define __ICCARM_INTRINSICS_VERSION__ 0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+ #if defined(__CLZ)
+ #undef __CLZ
+ #endif
+ #if defined(__REVSH)
+ #undef __REVSH
+ #endif
+ #if defined(__RBIT)
+ #undef __RBIT
+ #endif
+ #if defined(__SSAT)
+ #undef __SSAT
+ #endif
+ #if defined(__USAT)
+ #undef __USAT
+ #endif
+
+ #include "iccarm_builtin.h"
+
+ #define __disable_fault_irq __iar_builtin_disable_fiq
+ #define __disable_irq __iar_builtin_disable_interrupt
+ #define __enable_fault_irq __iar_builtin_enable_fiq
+ #define __enable_irq __iar_builtin_enable_interrupt
+ #define __arm_rsr __iar_builtin_rsr
+ #define __arm_wsr __iar_builtin_wsr
+
+
+ #define __get_APSR() (__arm_rsr("APSR"))
+ #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
+ #define __get_CONTROL() (__arm_rsr("CONTROL"))
+ #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
+
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ #define __get_FPSCR() (__arm_rsr("FPSCR"))
+ #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
+ #else
+ #define __get_FPSCR() ( 0 )
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #define __get_IPSR() (__arm_rsr("IPSR"))
+ #define __get_MSP() (__arm_rsr("MSP"))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __get_MSPLIM() (0U)
+ #else
+ #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
+ #endif
+ #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
+ #define __get_PSP() (__arm_rsr("PSP"))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __get_PSPLIM() (0U)
+ #else
+ #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
+ #endif
+
+ #define __get_xPSR() (__arm_rsr("xPSR"))
+
+ #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
+ #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
+ #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
+ #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
+ #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __set_MSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
+ #endif
+ #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
+ #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __set_PSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
+ #endif
+
+ #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
+ #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
+ #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
+ #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
+ #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
+ #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
+ #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
+ #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
+ #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
+ #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
+ #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
+ #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
+ #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
+ #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __TZ_get_PSPLIM_NS() (0U)
+ #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+ #else
+ #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
+ #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+ #endif
+
+ #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
+ #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+ #define __NOP __iar_builtin_no_operation
+
+ #define __CLZ __iar_builtin_CLZ
+ #define __CLREX __iar_builtin_CLREX
+
+ #define __DMB __iar_builtin_DMB
+ #define __DSB __iar_builtin_DSB
+ #define __ISB __iar_builtin_ISB
+
+ #define __LDREXB __iar_builtin_LDREXB
+ #define __LDREXH __iar_builtin_LDREXH
+ #define __LDREXW __iar_builtin_LDREX
+
+ #define __RBIT __iar_builtin_RBIT
+ #define __REV __iar_builtin_REV
+ #define __REV16 __iar_builtin_REV16
+
+ __IAR_FT int16_t __REVSH(int16_t val)
+ {
+ return (int16_t) __iar_builtin_REVSH(val);
+ }
+
+ #define __ROR __iar_builtin_ROR
+ #define __RRX __iar_builtin_RRX
+
+ #define __SEV __iar_builtin_SEV
+
+ #if !__IAR_M0_FAMILY
+ #define __SSAT __iar_builtin_SSAT
+ #endif
+
+ #define __STREXB __iar_builtin_STREXB
+ #define __STREXH __iar_builtin_STREXH
+ #define __STREXW __iar_builtin_STREX
+
+ #if !__IAR_M0_FAMILY
+ #define __USAT __iar_builtin_USAT
+ #endif
+
+ #define __WFE __iar_builtin_WFE
+ #define __WFI __iar_builtin_WFI
+
+ #if __ARM_MEDIA__
+ #define __SADD8 __iar_builtin_SADD8
+ #define __QADD8 __iar_builtin_QADD8
+ #define __SHADD8 __iar_builtin_SHADD8
+ #define __UADD8 __iar_builtin_UADD8
+ #define __UQADD8 __iar_builtin_UQADD8
+ #define __UHADD8 __iar_builtin_UHADD8
+ #define __SSUB8 __iar_builtin_SSUB8
+ #define __QSUB8 __iar_builtin_QSUB8
+ #define __SHSUB8 __iar_builtin_SHSUB8
+ #define __USUB8 __iar_builtin_USUB8
+ #define __UQSUB8 __iar_builtin_UQSUB8
+ #define __UHSUB8 __iar_builtin_UHSUB8
+ #define __SADD16 __iar_builtin_SADD16
+ #define __QADD16 __iar_builtin_QADD16
+ #define __SHADD16 __iar_builtin_SHADD16
+ #define __UADD16 __iar_builtin_UADD16
+ #define __UQADD16 __iar_builtin_UQADD16
+ #define __UHADD16 __iar_builtin_UHADD16
+ #define __SSUB16 __iar_builtin_SSUB16
+ #define __QSUB16 __iar_builtin_QSUB16
+ #define __SHSUB16 __iar_builtin_SHSUB16
+ #define __USUB16 __iar_builtin_USUB16
+ #define __UQSUB16 __iar_builtin_UQSUB16
+ #define __UHSUB16 __iar_builtin_UHSUB16
+ #define __SASX __iar_builtin_SASX
+ #define __QASX __iar_builtin_QASX
+ #define __SHASX __iar_builtin_SHASX
+ #define __UASX __iar_builtin_UASX
+ #define __UQASX __iar_builtin_UQASX
+ #define __UHASX __iar_builtin_UHASX
+ #define __SSAX __iar_builtin_SSAX
+ #define __QSAX __iar_builtin_QSAX
+ #define __SHSAX __iar_builtin_SHSAX
+ #define __USAX __iar_builtin_USAX
+ #define __UQSAX __iar_builtin_UQSAX
+ #define __UHSAX __iar_builtin_UHSAX
+ #define __USAD8 __iar_builtin_USAD8
+ #define __USADA8 __iar_builtin_USADA8
+ #define __SSAT16 __iar_builtin_SSAT16
+ #define __USAT16 __iar_builtin_USAT16
+ #define __UXTB16 __iar_builtin_UXTB16
+ #define __UXTAB16 __iar_builtin_UXTAB16
+ #define __SXTB16 __iar_builtin_SXTB16
+ #define __SXTAB16 __iar_builtin_SXTAB16
+ #define __SMUAD __iar_builtin_SMUAD
+ #define __SMUADX __iar_builtin_SMUADX
+ #define __SMMLA __iar_builtin_SMMLA
+ #define __SMLAD __iar_builtin_SMLAD
+ #define __SMLADX __iar_builtin_SMLADX
+ #define __SMLALD __iar_builtin_SMLALD
+ #define __SMLALDX __iar_builtin_SMLALDX
+ #define __SMUSD __iar_builtin_SMUSD
+ #define __SMUSDX __iar_builtin_SMUSDX
+ #define __SMLSD __iar_builtin_SMLSD
+ #define __SMLSDX __iar_builtin_SMLSDX
+ #define __SMLSLD __iar_builtin_SMLSLD
+ #define __SMLSLDX __iar_builtin_SMLSLDX
+ #define __SEL __iar_builtin_SEL
+ #define __QADD __iar_builtin_QADD
+ #define __QSUB __iar_builtin_QSUB
+ #define __PKHBT __iar_builtin_PKHBT
+ #define __PKHTB __iar_builtin_PKHTB
+ #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #define __CLZ __cmsis_iar_clz_not_active
+ #define __SSAT __cmsis_iar_ssat_not_active
+ #define __USAT __cmsis_iar_usat_not_active
+ #define __RBIT __cmsis_iar_rbit_not_active
+ #define __get_APSR __cmsis_iar_get_APSR_not_active
+ #endif
+
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+ #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+ #endif
+
+ #ifdef __INTRINSICS_INCLUDED
+ #error intrinsics.h is already included previously!
+ #endif
+
+ #include
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #undef __CLZ
+ #undef __SSAT
+ #undef __USAT
+ #undef __RBIT
+ #undef __get_APSR
+
+ __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+ {
+ if (data == 0U) { return 32U; }
+
+ uint32_t count = 0U;
+ uint32_t mask = 0x80000000U;
+
+ while ((data & mask) == 0U)
+ {
+ count += 1U;
+ mask = mask >> 1U;
+ }
+ return count;
+ }
+
+ __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+ {
+ uint8_t sc = 31U;
+ uint32_t r = v;
+ for (v >>= 1U; v; v >>= 1U)
+ {
+ r <<= 1U;
+ r |= v & 1U;
+ sc--;
+ }
+ return (r << sc);
+ }
+
+ __STATIC_INLINE uint32_t __get_APSR(void)
+ {
+ uint32_t res;
+ __asm("MRS %0,APSR" : "=r" (res));
+ return res;
+ }
+
+ #endif
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #undef __get_FPSCR
+ #undef __set_FPSCR
+ #define __get_FPSCR() (0)
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #pragma diag_suppress=Pe940
+ #pragma diag_suppress=Pe177
+
+ #define __enable_irq __enable_interrupt
+ #define __disable_irq __disable_interrupt
+ #define __NOP __no_operation
+
+ #define __get_xPSR __get_PSR
+
+ #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+ __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+ {
+ return __LDREX((unsigned long *)ptr);
+ }
+
+ __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+ {
+ return __STREX(value, (unsigned long *)ptr);
+ }
+ #endif
+
+
+ /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+ #if (__CORTEX_M >= 0x03)
+
+ __IAR_FT uint32_t __RRX(uint32_t value)
+ {
+ uint32_t result;
+ __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
+ return(result);
+ }
+
+ __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
+ }
+
+
+ #define __enable_fault_irq __enable_fiq
+ #define __disable_fault_irq __disable_fiq
+
+
+ #endif /* (__CORTEX_M >= 0x03) */
+
+ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+ {
+ return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+ }
+
+ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+ __IAR_FT uint32_t __get_MSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,MSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_MSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR MSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __get_PSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_PSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
+ {
+ __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR PSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_SP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,SP_NS" : "=r" (res));
+ return res;
+ }
+ __IAR_FT void __TZ_set_SP_NS(uint32_t value)
+ {
+ __asm volatile("MSR SP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
+ }
+
+ #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+ __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+ {
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+ }
+
+ __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+ {
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+ }
+#endif
+
+#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+ __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+ {
+ __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+ {
+ __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+ {
+ __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+ }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+
+ __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+ {
+ __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+ {
+ __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+ {
+ __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_version.h b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_version.h
new file mode 100644
index 0000000000..660f612aa3
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_version.h
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file cmsis_version.h
+ * @brief CMSIS Core(M) Version definitions
+ * @version V5.0.2
+ * @date 19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/* CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
+#endif
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/core_cm4.h b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/core_cm4.h
new file mode 100644
index 0000000000..7d56873532
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/core_cm4.h
@@ -0,0 +1,2129 @@
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V5.0.8
+ * @date 04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M4
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (4U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000U
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/mpu_armv7.h b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/mpu_armv7.h
new file mode 100644
index 0000000000..be73de161f
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/mpu_armv7.h
@@ -0,0 +1,270 @@
+/******************************************************************************
+ * @file mpu_armv7.h
+ * @brief CMSIS MPU API for Armv7-M MPU
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+ (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
+ ((Region) & MPU_RBAR_REGION_Msk) | \
+ (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+*
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
+ ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
+ (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
+ (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
+ (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
+ ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
+ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
+ (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+ ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+* - TEX: 000b
+* - Shareable
+* - Non-cacheable
+* - Non-bufferable
+*/
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+* - TEX: 000b (if non-shareable) or 010b (if shareable)
+* - Shareable or non-shareable
+* - Non-cacheable
+* - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+* - TEX: 1BBb (reflecting outer cacheability rules)
+* - Shareable or non-shareable
+* - Cacheable or non-cacheable (reflecting inner cacheability rules)
+* - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+ uint32_t RBAR; //!< The region base address register value (RBAR)
+ uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+ __DSB();
+ __ISB();
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+ __DSB();
+ __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+ MPU->RNR = rnr;
+ MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+ MPU->RNR = rnr;
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+ uint32_t i;
+ for (i = 0U; i < len; ++i)
+ {
+ dst[i] = src[i];
+ }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+ while (cnt > MPU_TYPE_RALIASES) {
+ orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+ table += MPU_TYPE_RALIASES;
+ cnt -= MPU_TYPE_RALIASES;
+ }
+ orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/n32g43x.h b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/n32g43x.h
new file mode 100644
index 0000000000..e6e33955b0
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/n32g43x.h
@@ -0,0 +1,7744 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_H__
+#define __N32G43X_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup N32G43x_Library_Basic
+ * @{
+ */
+
+#if !defined USE_STDPERIPH_DRIVER
+/*
+ * Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+#define USE_STDPERIPH_DRIVER
+#endif
+
+/*
+ * In the following line adjust the value of External High Speed oscillator (HSE)
+ used in your application
+
+ Tip: To avoid modifying this file each time you need to use different HSE, you
+ can define the HSE value in your toolchain compiler preprocessor.
+ */
+#if !defined HSE_VALUE
+#define HSE_VALUE (8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+/*
+ * In the following line adjust the External High Speed oscillator (HSE) Startup
+ Timeout value
+ */
+#define HSE_STARTUP_TIMEOUT ((uint16_t)0x2000) /*!< Time out for HSE start up */
+#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */
+#define MSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for MSI start up */
+
+#define MSI_VALUE_L0 (100000) /*!< L0 Value of the Multi oscillator in Hz*/
+#define MSI_VALUE_L1 (200000) /*!< L1 Value of the Multi oscillator in Hz*/
+#define MSI_VALUE_L2 (400000) /*!< L2 Value of the Multi oscillator in Hz*/
+#define MSI_VALUE_L3 (800000) /*!< L3 Value of the Multi oscillator in Hz*/
+#define MSI_VALUE_L4 (1000000) /*!< L4 Value of the Multi oscillator in Hz*/
+#define MSI_VALUE_L5 (2000000) /*!< L5 Value of the Multi oscillator in Hz*/
+#define MSI_VALUE_L6 (4000000) /*!< L6 Value of the Multi oscillator in Hz*/
+
+#define HSI_VALUE (16000000) /*!< Value of the Internal oscillator in Hz*/
+
+#define __N32G43x_STDPERIPH_VERSION_MAIN (0x00) /*!< [31:24] main version */
+#define __N32G43x_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
+#define __N32G43x_STDPERIPH_VERSION_SUB2 (0x07) /*!< [15:8] sub2 version */
+#define __N32G43x_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
+
+/**
+ * @brief N32G43x Standard Peripheral Library version number
+ */
+#define __N32G43x_STDPERIPH_VERSION \
+ ((__N32G43x_STDPERIPH_VERSION_MAIN << 24) | (__N32G43x_STDPERIPH_VERSION_SUB1 << 16) \
+ | (__N32G43x_STDPERIPH_VERSION_SUB2 << 8) | (__N32G43x_STDPERIPH_VERSION_RC))
+
+/*
+ * Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#ifdef N32G43X
+#define __MPU_PRESENT 1 /*!< N32G43x devices does not provide an MPU */
+#define __FPU_PRESENT 1 /*!< FPU present */
+#endif /* N32G43x */
+#define __NVIC_PRIO_BITS 4 /*!< N32G43x uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @brief N32G43x Interrupt Number Definition
+ */
+typedef enum IRQn
+{
+ /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+
+ /****** N32G43x specific Interrupt Numbers ********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_IRQn = 2, /*!< RTC Tamper interrupt or Timestamp through EXTI line 19 */
+ RTC_IRQn = 3, /*!< RTC wakeup timer through EXTI line 20 */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA_Channel1_IRQn = 11, /*!< DMA Channel 1 global Interrupt */
+ DMA_Channel2_IRQn = 12, /*!< DMA Channel 2 global Interrupt */
+ DMA_Channel3_IRQn = 13, /*!< DMA Channel 3 global Interrupt */
+ DMA_Channel4_IRQn = 14, /*!< DMA Channel 4 global Interrupt */
+ DMA_Channel5_IRQn = 15, /*!< DMA Channel 5 global Interrupt */
+ DMA_Channel6_IRQn = 16, /*!< DMA Channel 6 global Interrupt */
+ DMA_Channel7_IRQn = 17, /*!< DMA Channel 7 global Interrupt */
+ DMA_Channel8_IRQn = 18, /*!< DMA Channel 8 global Interrupt */
+ ADC_IRQn = 19, /*!< ADC global Interrupt */
+ USB_HP_IRQn = 20, /*!< USB Device High Priority Interrupts */
+ USB_LP_IRQn = 21, /*!< USB Device Low Priority Interrupts */
+ COMP_1_2_IRQn = 22, /*!< COMP1 & COMP2 global Interrupt through EXTI line 21/22 */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+ TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
+ TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
+ TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ UART4_IRQn = 47, /*!< UART4 global Interrupt */
+ UART5_IRQn = 48, /*!< UART5 global Interrupt */
+ LPUART_IRQn = 49, /*!< LPUART global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ TIM6_IRQn = 51, /*!< TIM6 global Interrupt */
+ TIM7_IRQn = 52, /*!< TIM7 global Interrupt */
+ CAN_TX_IRQn = 53, /*!< CAN TX Interrupt */
+ CAN_RX0_IRQn = 54, /*!< CAN RX0 Interrupt */
+ CAN_RX1_IRQn = 55, /*!< CAN RX1 Interrupt */
+ CAN_SCE_IRQn = 56, /*!< CAN SCE Interrupt */
+ LPUART_WKUP_IRQn = 57, /*!< LPUART wakeup interrupt through EXTI line 23 */
+ LPTIM_WKUP_IRQn = 58, /*!< LPTIMER wakeup interrupt through EXTI line 24 */
+ SAC_IRQn = 60, /*!< SAC global Interrupt */
+ MMU_IRQn = 61, /*!< MMU global Interrupt */
+ TSC_IRQn = 62, /*!< TSC global Interrupt */
+ RAMC_PERR_IRQn = 63, /*!< RAM parity error interrupt */
+ TIM9_IRQn = 64, /*!< TIM9 global interrupt */
+ UCDR_IRQn = 65, /*!< UCDR error interrupt */
+} IRQn_Type;
+
+#include "core_cm4.h"
+#include "system_n32g43x.h"
+#include
+#include
+
+typedef int32_t s32;
+typedef int16_t s16;
+typedef int8_t s8;
+
+typedef const int32_t sc32; /*!< Read Only */
+typedef const int16_t sc16; /*!< Read Only */
+typedef const int8_t sc8; /*!< Read Only */
+
+typedef __IO int32_t vs32;
+typedef __IO int16_t vs16;
+typedef __IO int8_t vs8;
+
+typedef __I int32_t vsc32; /*!< Read Only */
+typedef __I int16_t vsc16; /*!< Read Only */
+typedef __I int8_t vsc8; /*!< Read Only */
+
+typedef uint32_t u32;
+typedef uint16_t u16;
+typedef uint8_t u8;
+
+typedef const uint32_t uc32; /*!< Read Only */
+typedef const uint16_t uc16; /*!< Read Only */
+typedef const uint8_t uc8; /*!< Read Only */
+
+typedef __IO uint32_t vu32;
+typedef __IO uint16_t vu16;
+typedef __IO uint8_t vu8;
+
+typedef __I uint32_t vuc32; /*!< Read Only */
+typedef __I uint16_t vuc16; /*!< Read Only */
+typedef __I uint8_t vuc8; /*!< Read Only */
+typedef enum
+{
+ RESET = 0,
+ SET = !RESET
+} FlagStatus,
+ INTStatus;
+
+typedef enum
+{
+ DISABLE = 0,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/* N32G43x Standard Peripheral Library old definitions (maintained for legacy purpose) */
+#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT
+#define HSE_Value HSE_VALUE
+#define HSI_Value HSI_VALUE
+
+/**
+ * @brief Analog to Digital Converter
+ */
+typedef struct
+{
+ __IO uint32_t STS;
+ __IO uint32_t CTRL1;
+ __IO uint32_t CTRL2;
+ __IO uint32_t SAMPT1;
+ __IO uint32_t SAMPT2;
+ __IO uint32_t JOFFSET1;
+ __IO uint32_t JOFFSET2;
+ __IO uint32_t JOFFSET3;
+ __IO uint32_t JOFFSET4;
+ __IO uint32_t WDGHIGH;
+ __IO uint32_t WDGLOW;
+ __IO uint32_t RSEQ1;
+ __IO uint32_t RSEQ2;
+ __IO uint32_t RSEQ3;
+ __IO uint32_t JSEQ;
+ __IO uint32_t JDAT1;
+ __IO uint32_t JDAT2;
+ __IO uint32_t JDAT3;
+ __IO uint32_t JDAT4;
+ __IO uint32_t DAT;
+ __IO uint32_t DIFSEL;
+ __IO uint32_t CALFACT;
+ __IO uint32_t CTRL3;
+ __IO uint32_t SAMPT3;
+} ADC_Module;
+
+/**
+ * @brief OPAMP
+ */
+typedef struct
+{
+ __IO uint32_t CS1;
+ __IO uint32_t RES1[3];
+ __IO uint32_t CS2;
+ __IO uint32_t RES2[3];
+ __IO uint32_t LOCK;
+} OPAMP_Module;
+
+/**
+ * @brief COMP_Single
+ */
+typedef struct
+{
+ __IO uint32_t CTRL;
+ __IO uint32_t FILC;
+ __IO uint32_t FILP;
+} COMP_SingleType;
+
+/**
+ * @brief COMP
+ */
+typedef struct
+{
+ __IO uint32_t INTEN;
+ __IO uint32_t LPCKSEL;
+ __IO uint32_t WINMODE;
+ __IO uint32_t LOCK;
+ COMP_SingleType Cmp1;
+ __IO uint32_t RES;
+ COMP_SingleType Cmp2;
+ __IO uint32_t CMP2OSEL;
+ __IO uint32_t VREFSCL;
+ __IO uint32_t TEST;
+ __IO uint32_t INTSTS;
+} COMP_Module;
+
+/**
+ * @brief AFEC
+ */
+
+typedef struct
+{
+ __IO uint32_t TRIMR0;
+ __IO uint32_t TRIMR1;
+ __IO uint32_t TRIMR2;
+ __IO uint32_t TRIMR3;
+ __IO uint32_t TRIMR4;
+ __IO uint32_t TRIMR5;
+ __IO uint32_t TRIMR6;
+ __IO uint32_t TRIMR7;
+ __IO uint32_t TRIMR8;
+ //uint32_t RESERVED0;
+ __IO uint32_t TESTR0;
+ __IO uint32_t TESTR1;
+} AFEC_Module;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TMI;
+ __IO uint32_t TMDT;
+ __IO uint32_t TMDL;
+ __IO uint32_t TMDH;
+} CAN_TxMailBox_Param;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RMI;
+ __IO uint32_t RMDT;
+ __IO uint32_t RMDL;
+ __IO uint32_t RMDH;
+} CAN_FIFOMailBox_Param;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1;
+ __IO uint32_t FR2;
+} CAN_FilterRegister_Param;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCTRL;
+ __IO uint32_t MSTS;
+ __IO uint32_t TSTS;
+ __IO uint32_t RFF0;
+ __IO uint32_t RFF1;
+ __IO uint32_t INTE;
+ __IO uint32_t ESTS;
+ __IO uint32_t BTIM;
+ uint32_t RESERVED0[88];
+ CAN_TxMailBox_Param sTxMailBox[3];
+ CAN_FIFOMailBox_Param sFIFOMailBox[2];
+ uint32_t RESERVED1[12];
+ __IO uint32_t FMC;
+ __IO uint32_t FM1;
+ uint32_t RESERVED2;
+ __IO uint32_t FS1;
+ uint32_t RESERVED3;
+ __IO uint32_t FFA1;
+ uint32_t RESERVED4;
+ __IO uint32_t FA1;
+ uint32_t RESERVED5[8];
+ CAN_FilterRegister_Param sFilterRegister[14];
+} CAN_Module;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t CRC32DAT; /*!< CRC data register */
+ __IO uint8_t CRC32IDAT; /*!< CRC independent data register*/
+ uint8_t RESERVED0;
+ uint16_t RESERVED1;
+ __IO uint32_t CRC32CTRL; /*!< CRC control register */
+ __IO uint32_t CRC16CTRL;
+ __IO uint8_t CRC16DAT;
+ uint8_t RESERVED2;
+ uint16_t RESERVED3;
+ __IO uint16_t CRC16D;
+ uint16_t RESERVED4;
+ __IO uint8_t LRC;
+ uint8_t RESERVED5;
+ uint16_t RESERVED6;
+} CRC_Module;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CTRL;
+ __IO uint32_t SOTTR;
+ __IO uint32_t DR12CH;
+ __IO uint32_t DL12CH;
+ __IO uint32_t DR8CH;
+ __IO uint32_t DATO;
+
+} DAC_Module;
+/**
+ * @brief USB
+ */
+
+typedef struct
+{
+ __IO uint32_t EP0;
+ __IO uint32_t EP1;
+ __IO uint32_t EP2;
+ __IO uint32_t EP3;
+ __IO uint32_t EP4;
+ __IO uint32_t EP5;
+ __IO uint32_t EP6;
+ __IO uint32_t EP7;
+ __IO uint32_t Reserve20h;
+ __IO uint32_t Reserve24h;
+ __IO uint32_t Reserve28h;
+ __IO uint32_t Reserve2Ch;
+ __IO uint32_t Reserve30h;
+ __IO uint32_t Reserve34h;
+ __IO uint32_t Reserve38h;
+ __IO uint32_t Reserve3Ch;
+ __IO uint32_t CTRL;
+ __IO uint32_t STS;
+ __IO uint32_t FN;
+ __IO uint32_t ADDR;
+ __IO uint32_t BUFTAB;
+} USB_Module;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t ID;
+ __IO uint32_t CTRL;
+} DBG_Module;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CHCFG;
+ __IO uint32_t TXNUM;
+ __IO uint32_t PADDR;
+ __IO uint32_t MADDR;
+ __IO uint32_t CHSEL;
+
+} DMA_ChannelType;
+
+typedef struct
+{
+ __IO uint32_t INTSTS;
+ __IO uint32_t INTCLR;
+ __IO DMA_ChannelType DMA_Channel[8];
+} DMA_Module;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMASK; /*offset 0x00*/
+ __IO uint32_t EMASK; /*offset 0x04*/
+ __IO uint32_t RT_CFG; /*offset 0x08*/
+ __IO uint32_t FT_CFG; /*offset 0x0C*/
+ __IO uint32_t SWIE; /*offset 0x10*/
+ __IO uint32_t PEND; /*offset 0x14*/
+ __IO uint32_t TS_SEL; /*offset 0x18*/
+} EXTI_Module;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t AC;
+ __IO uint32_t KEYR;
+ __IO uint32_t OPTKEY;
+ __IO uint32_t STS;
+ __IO uint32_t CTRL;
+ __IO uint32_t ADD;
+ __IO uint32_t OB2;
+ __IO uint32_t OB;
+ __IO uint32_t WRP;
+ __IO uint32_t RESERVED0;
+ __IO uint32_t RESERVED1;
+ __IO uint32_t RESERVED2;
+ __IO uint32_t CAHR;
+} FLASH_Module;
+
+/**
+ * @brief Option Bytes Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t USER_RDP;
+ __IO uint32_t Data1_Data0;
+ __IO uint32_t WRP1_WRP0;
+ __IO uint32_t WRP3_WRP2;
+ __IO uint32_t USER2_RDP2;
+} OB_Module;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t PMODE; /*offset 0x00*/
+ __IO uint32_t POTYPE; /*offset 0x04*/
+ __IO uint32_t SR; /*offset 0x08*/
+ __IO uint32_t PUPD; /*offset 0x0C*/
+ __IO uint32_t PID; /*offset 0x10*/
+ __IO uint32_t POD; /*offset 0x14*/
+ __IO uint32_t PBSC; /*offset 0x18*/
+ __IO uint32_t PLOCK; /*offset 0x1C*/
+ __IO uint32_t AFL; /*offset 0x20*/
+ __IO uint32_t AFH; /*offset 0x24*/
+ __IO uint32_t PBC; /*offset 0x28*/
+ __IO uint32_t DS; /*offset 0x2C*/
+
+} GPIO_Module;
+
+/**
+ * @brief Alternate Function I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t RMP_CFG;
+ __IO uint32_t EXTI_CFG[4];
+} AFIO_Module;
+/**
+ * @brief Inter Integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint16_t CTRL1;
+ uint16_t RESERVED0;
+ __IO uint16_t CTRL2;
+ uint16_t RESERVED1;
+ __IO uint16_t OADDR1;
+ uint16_t RESERVED2;
+ __IO uint16_t OADDR2;
+ uint16_t RESERVED3;
+ __IO uint16_t DAT;
+ uint16_t RESERVED4;
+ __IO uint16_t STS1;
+ uint16_t RESERVED5;
+ __IO uint16_t STS2;
+ uint16_t RESERVED6;
+ __IO uint16_t CLKCTRL;
+ uint16_t RESERVED7;
+ __IO uint16_t TMRISE;
+ uint16_t RESERVED8;
+} I2C_Module;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KEY;
+ __IO uint32_t PREDIV; /*!< IWDG PREDIV */
+ __IO uint32_t RELV;
+ __IO uint32_t STS;
+} IWDG_Module;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CTRL1;
+ __IO uint32_t CTRL2;
+ __IO uint32_t CTRL3;
+ __IO uint32_t STS1;
+ __IO uint32_t STS2;
+ __IO uint32_t STSCLR;
+} PWR_Module;
+
+/**
+ * @brief Low-Power Timer
+ */
+typedef struct
+{
+ __IO uint32_t INTSTS;
+ __IO uint32_t INTCLR;
+ __IO uint32_t INTEN;
+ __IO uint32_t CFG;
+ __IO uint32_t CTRL;
+ __IO uint32_t COMPx;
+ __IO uint32_t ARR;
+ __IO uint32_t CNT;
+
+} LPTIM_Module;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CTRL;
+ __IO uint32_t CFG;
+ __IO uint32_t CLKINT;
+ __IO uint32_t APB2PRST;
+ __IO uint32_t APB1PRST;
+ __IO uint32_t AHBPCLKEN;
+ __IO uint32_t APB2PCLKEN;
+ __IO uint32_t APB1PCLKEN;
+ __IO uint32_t LDCTRL;
+ __IO uint32_t CTRLSTS;
+ __IO uint32_t AHBPRST;
+ __IO uint32_t CFG2;
+ __IO uint32_t CFG3;
+ __IO uint32_t RDCTRL;
+ __IO uint32_t Reserve0;
+ __IO uint32_t Reserve1;
+ __IO uint32_t PLLHSIPRE;
+ __IO uint32_t SRAM_CTRLSTS;
+} RCC_Module;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TSH; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DATE; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CTRL; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t INITSTS; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRE; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WKUPT; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t reserved0; /*!< Reserved */
+ __IO uint32_t ALARMA; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALARMB; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WRP; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SUBS; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SCTRL; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TST; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSD; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSS; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALIB; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TMPCFG; /*!< RTC tamper configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASS; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSS; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ __IO uint32_t OPT; /*!< RTC option register, Address offset: 0x4C */
+ __IO uint32_t BKP1R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP4R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP5R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP8R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP9R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP12R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP13R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP16R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP17R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP20R; /*!< RTC backup register 19, Address offset: 0x9C */
+ __IO uint32_t TSCWKUPCTRL; /*!< TSC register 1, Address offset: 0xA0 */
+ __IO uint32_t TSCWKUPCNT; /*!< TSC register 2, Address offset: 0xA4 */
+} RTC_Module;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint16_t CTRL1;
+ uint16_t RESERVED0;
+ __IO uint16_t CTRL2;
+ uint16_t RESERVED1;
+ __IO uint16_t STS;
+ uint16_t RESERVED2;
+ __IO uint16_t DAT;
+ uint16_t RESERVED3;
+ __IO uint16_t CRCPOLY;
+ uint16_t RESERVED4;
+ __IO uint16_t CRCRDAT;
+ uint16_t RESERVED5;
+ __IO uint16_t CRCTDAT;
+ uint16_t RESERVED6;
+ __IO uint16_t I2SCFG;
+ uint16_t RESERVED7;
+ __IO uint16_t I2SPREDIV;
+ uint16_t RESERVED8;
+} SPI_Module;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CTRL1;
+ __IO uint32_t CTRL2;
+ __IO uint16_t SMCTRL;
+ uint16_t RESERVED1;
+ __IO uint16_t DINTEN;
+ uint16_t RESERVED2;
+ __IO uint32_t STS;
+ __IO uint16_t EVTGEN;
+ uint16_t RESERVED3;
+ __IO uint16_t CCMOD1;
+ uint16_t RESERVED4;
+ __IO uint16_t CCMOD2;
+ uint16_t RESERVED5;
+ __IO uint32_t CCEN;
+ __IO uint16_t CNT;
+ uint16_t RESERVED6;
+ __IO uint16_t PSC;
+ uint16_t RESERVED7;
+ __IO uint16_t AR;
+ uint16_t RESERVED8;
+ __IO uint16_t REPCNT;
+ uint16_t RESERVED9;
+ __IO uint16_t CCDAT1;
+ uint16_t RESERVED10;
+ __IO uint16_t CCDAT2;
+ uint16_t RESERVED11;
+ __IO uint16_t CCDAT3;
+ uint16_t RESERVED12;
+ __IO uint16_t CCDAT4;
+ uint16_t RESERVED13;
+ __IO uint16_t BKDT;
+ uint16_t RESERVED14;
+ __IO uint16_t DCTRL;
+ uint16_t RESERVED15;
+ __IO uint16_t DADDR;
+ uint16_t RESERVED16;
+ uint32_t RESERVED17;
+ __IO uint16_t CCMOD3;
+ uint16_t RESERVED18;
+ __IO uint16_t CCDAT5;
+ uint16_t RESERVED19;
+ __IO uint16_t CCDAT6;
+ uint16_t RESERVED20;
+} TIM_Module;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint16_t STS;
+ uint16_t RESERVED0;
+ __IO uint16_t DAT;
+ uint16_t RESERVED1;
+ __IO uint16_t BRCF;
+ uint16_t RESERVED2;
+ __IO uint16_t CTRL1;
+ uint16_t RESERVED3;
+ __IO uint16_t CTRL2;
+ uint16_t RESERVED4;
+ __IO uint16_t CTRL3;
+ uint16_t RESERVED5;
+ __IO uint16_t GTP;
+ uint16_t RESERVED6;
+} USART_Module;
+
+/**
+ * @brief Low-power Universal Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint16_t STS;
+ uint16_t RESERVED0;
+ __IO uint8_t INTEN;
+ uint8_t RESERVED1;
+ uint16_t RESERVED2;
+ __IO uint16_t CTRL;
+ uint16_t RESERVED3;
+ __IO uint16_t BRCFG1;
+ uint16_t RESERVED4;
+ __IO uint8_t DAT;
+ uint8_t RESERVED5;
+ uint16_t RESERVED6;
+ __IO uint8_t BRCFG2;
+ uint8_t RESERVED7;
+ uint16_t RESERVED8;
+ __IO uint32_t WUDAT;
+} LPUART_Module;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CTRL;
+ __IO uint32_t CFG;
+ __IO uint32_t STS;
+} WWDG_Module;
+
+/**
+ * @brief Touch Sensor Controller
+ */
+typedef struct
+{
+ __IO uint32_t CTRL;
+ __IO uint32_t CHNEN;
+ __IO uint32_t STS;
+ __IO uint32_t RESERVED;
+ __IO uint32_t ANA_CTRL;
+ __IO uint32_t ANA_SEL;
+ __IO uint32_t RESR[3];
+// __IO uint32_t RESR0;
+// __IO uint32_t RESR1;
+// __IO uint32_t RESR2;
+ __IO uint32_t THRHD[24];
+// __IO uint32_t THRHD0;
+// __IO uint32_t THRHD1;
+// __IO uint32_t THRHD2;
+// __IO uint32_t THRHD3;
+// __IO uint32_t THRHD4;
+// __IO uint32_t THRHD5;
+// __IO uint32_t THRHD6;
+// __IO uint32_t THRHD7;
+// __IO uint32_t THRHD8;
+// __IO uint32_t THRHD9;
+// __IO uint32_t THRHD10;
+// __IO uint32_t THRHD11;
+// __IO uint32_t THRHD12;
+// __IO uint32_t THRHD13;
+// __IO uint32_t THRHD14;
+// __IO uint32_t THRHD15;
+// __IO uint32_t THRHD16;
+// __IO uint32_t THRHD17;
+// __IO uint32_t THRHD18;
+// __IO uint32_t THRHD19;
+// __IO uint32_t THRHD20;
+// __IO uint32_t THRHD21;
+// __IO uint32_t THRHD22;
+// __IO uint32_t THRHD23;
+
+} TSC_Module;
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+#define UCID_BASE ((uint32_t)0x1FFFF7C0) /*!< UCID Address : 0x1FFF_F7C0 */
+#define UCID_LENGTH ((uint32_t)0x10) /*!< UCID Length : 16Bytes */
+#define UID_BASE ((uint32_t)0x1FFFF7F0) /*!< UID Address : 0x1FFF_F7F0 */
+#define UID_LENGTH ((uint32_t)0x0C) /*!< UID Length : 12Bytes */
+#define DBGMCU_ID_BASE ((uint32_t)0x1FFFF7FC) /*!< DBGMCU_ID Address */
+#define DBGMCU_ID_LENGTH ((uint8_t)0x04) /*!< DBGMCU_ID Length : 4 Bytes */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE (PERIPH_BASE)
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x18000)
+
+/* APB1 */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
+#define AFEC_BASE (APB1PERIPH_BASE + 0x1800)
+#define OPAMP_BASE (APB1PERIPH_BASE + 0x2000)
+#define COMP_BASE (APB1PERIPH_BASE + 0x2400)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define TSC_BASE (APB1PERIPH_BASE + 0x3400)
+#define TIM9_BASE (APB1PERIPH_BASE + 0x3C00)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define LPTIM_BASE (APB1PERIPH_BASE + 0x4C00)
+#define LPUART_BASE (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define USB_BASE (APB1PERIPH_BASE + 0x5C00)
+#define USB_SRAM_BASE (APB1PERIPH_BASE + 0x6000)
+#define CAN_BASE (APB1PERIPH_BASE + 0x6400)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+
+/* APB2 */
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+#define SPI2_BASE (APB2PERIPH_BASE + 0x3C00)
+#define UART4_BASE (APB2PERIPH_BASE + 0x5000)
+#define UART5_BASE (APB2PERIPH_BASE + 0x5400)
+
+/* AHB */
+#define DMA_BASE (AHBPERIPH_BASE + 0x8000)
+#define DMA_CH1_BASE (AHBPERIPH_BASE + 0x8008)
+#define DMA_CH2_BASE (AHBPERIPH_BASE + 0x801C)
+#define DMA_CH3_BASE (AHBPERIPH_BASE + 0x8030)
+#define DMA_CH4_BASE (AHBPERIPH_BASE + 0x8044)
+#define DMA_CH5_BASE (AHBPERIPH_BASE + 0x8058)
+#define DMA_CH6_BASE (AHBPERIPH_BASE + 0x806C)
+#define DMA_CH7_BASE (AHBPERIPH_BASE + 0x8080)
+#define DMA_CH8_BASE (AHBPERIPH_BASE + 0x8094)
+#define ADC_BASE (AHBPERIPH_BASE + 0x8800)
+#define RCC_BASE (AHBPERIPH_BASE + 0x9000)
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0xA000) /*!< Flash registers base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+#define CRC_BASE (AHBPERIPH_BASE + 0xB000)
+#define SAC_BASE (AHBPERIPH_BASE + 0xC000)
+#define SAC_SRAM_BASE (AHBPERIPH_BASE + 0xC400)
+#define MMU_BASE (AHBPERIPH_BASE + 0xCC00)
+
+#define DBG_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+#define TIM2 ((TIM_Module*)TIM2_BASE)
+#define TIM3 ((TIM_Module*)TIM3_BASE)
+#define TIM4 ((TIM_Module*)TIM4_BASE)
+#define TIM5 ((TIM_Module*)TIM5_BASE)
+#define TIM6 ((TIM_Module*)TIM6_BASE)
+#define TIM7 ((TIM_Module*)TIM7_BASE)
+#define AFEC ((AFEC_Module*)AFEC_BASE)
+#define OPAMP ((OPAMP_Module*)OPAMP_BASE)
+#define COMP ((COMP_Module*)COMP_BASE)
+#define RTC ((RTC_Module*)RTC_BASE)
+#define WWDG ((WWDG_Module*)WWDG_BASE)
+#define IWDG ((IWDG_Module*)IWDG_BASE)
+#define TSC ((TSC_Module*)TSC_BASE)
+#define TIM9 ((TIM_Module*)TIM9_BASE)
+#define USART2 ((USART_Module*)USART2_BASE)
+#define USART3 ((USART_Module*)USART3_BASE)
+#define LPTIM ((LPTIM_Module*)LPTIM_BASE)
+#define LPUART ((LPUART_Module*)LPUART_BASE)
+#define I2C1 ((I2C_Module*)I2C1_BASE)
+#define I2C2 ((I2C_Module*)I2C2_BASE)
+#define USB ((USB_Module*)USB_BASE)
+#define CAN ((CAN_Module*)CAN_BASE)
+#define PWR ((PWR_Module*)PWR_BASE)
+#define DAC ((DAC_Module*)DAC_BASE)
+#define AFIO ((AFIO_Module*)AFIO_BASE)
+#define EXTI ((EXTI_Module*)EXTI_BASE)
+#define GPIOA ((GPIO_Module*)GPIOA_BASE)
+#define GPIOB ((GPIO_Module*)GPIOB_BASE)
+#define GPIOC ((GPIO_Module*)GPIOC_BASE)
+#define GPIOD ((GPIO_Module*)GPIOD_BASE)
+#define TIM1 ((TIM_Module*)TIM1_BASE)
+#define SPI1 ((SPI_Module*)SPI1_BASE)
+#define TIM8 ((TIM_Module*)TIM8_BASE)
+#define USART1 ((USART_Module*)USART1_BASE)
+#define SPI2 ((SPI_Module*)SPI2_BASE)
+#define UART4 ((USART_Module*)UART4_BASE)
+#define UART5 ((USART_Module*)UART5_BASE)
+#define DMA ((DMA_Module*)DMA_BASE)
+#define DMA_CH1 ((DMA_ChannelType*)DMA_CH1_BASE)
+#define DMA_CH2 ((DMA_ChannelType*)DMA_CH2_BASE)
+#define DMA_CH3 ((DMA_ChannelType*)DMA_CH3_BASE)
+#define DMA_CH4 ((DMA_ChannelType*)DMA_CH4_BASE)
+#define DMA_CH5 ((DMA_ChannelType*)DMA_CH5_BASE)
+#define DMA_CH6 ((DMA_ChannelType*)DMA_CH6_BASE)
+#define DMA_CH7 ((DMA_ChannelType*)DMA_CH7_BASE)
+#define DMA_CH8 ((DMA_ChannelType*)DMA_CH8_BASE)
+#define ADC ((ADC_Module*)ADC_BASE)
+#define RCC ((RCC_Module*)RCC_BASE)
+#define FLASH ((FLASH_Module*)FLASH_R_BASE)
+#define OBT ((OB_Module*)OB_BASE)
+#define CRC ((CRC_Module*)CRC_BASE)
+
+#define DBG ((DBG_Module*)DBG_BASE)
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRC_CRC32DAT register *********************/
+#define CRC32_DAT_DAT ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/******************* Bit definition for CRC_CRC32IDAT register ********************/
+#define CRC32_IDAT_IDAT ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CRC32CTRL register ********************/
+#define CRC32_CTRL_RESET ((uint8_t)0x01) /*!< RESET bit */
+
+/******************** Bit definition for CRC16_CR register ********************/
+#define CRC16_CTRL_LITTLE ((uint8_t)0x02)
+#define CRC16_CTRL_BIG ((uint8_t)0xFD)
+
+#define CRC16_CTRL_RESET ((uint8_t)0x04)
+#define CRC16_CTRL_NO_RESET ((uint8_t)0xFB)
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CTRL1 register ********************/
+#define PWR_CTRL1_LPMSEL ((uint16_t)0x0007) /*!< no low power mode entered */
+#define PWR_CTRL1_STOP2 ((uint16_t)0x0002) /*!< stop2 mode */
+#define PWR_CTRL1_STANDBY ((uint16_t)0x0003) /*!< standby mode */
+
+
+#define PWR_CTRL1_DRBP ((uint16_t)0x0100) /*!< Access to RTC and Backup registers enabled */
+
+#define PWR_CTRL1_MRSEL ((uint16_t)0x0600) /*!< vddd Range Mask */
+#define PWR_CTRL1_MRSEL_bit0 ((uint16_t)0x0200) /*!< vddd Range MRSEL bit0 */
+#define PWR_CTRL1_MRSEL_bit1 ((uint16_t)0x0400) /*!< vddd Range MRSEL bit1 */
+#define PWR_CTRL1_MRSEL2 ((uint16_t)0x0400) /*!< vddd Range2=1.0 V */
+#define PWR_CTRL1_MRSEL1 ((uint16_t)0x0600) /*!< vddd Range1=1.1 V */
+#define PWR_CTRL1_LPREN ((uint16_t)0x4000) /*!< When this bit is set, MR is turned off and LPR is used to run the main power domain. */
+#define PWR_CTRL1_MRSELMASK ((uint16_t)0x0600) /*!< MR voltage mask */
+/******************** Bit definition for PWR_CTRL2 register ********************/
+#define PWR_CTRL2_PVDEN ((uint16_t)0x0001) /*!< Power voltage detector enable */
+#define PWR_CTRL2_PLS1 ((uint16_t)0x0000) /*!< voltage threshold around 2.1 V */
+#define PWR_CTRL2_PLS2 ((uint16_t)0x0002) /*!< voltage threshold around 2.25 V */
+#define PWR_CTRL2_PLS3 ((uint16_t)0x0004) /*!< voltage threshold around 2.4 V */
+#define PWR_CTRL2_PLS4 ((uint16_t)0x0006) /*!< voltage threshold around 2.55 V */
+#define PWR_CTRL2_PLS5 ((uint16_t)0x0008) /*!< voltage threshold around 2.7 V */
+#define PWR_CTRL2_PLS6 ((uint16_t)0x000A) /*!< voltage threshold around 2.85 V */
+#define PWR_CTRL2_PLS7 ((uint16_t)0x000C) /*!< voltage threshold around 2.95 V */
+#define PWR_CTRL2_PLS8 ((uint16_t)0x000E) /*!< external input analog voltage PVD_IN (compared internally to VREFINT) */
+
+#define PWR_CTRL2_PVDFLTEN ((uint16_t)0x0010) /*!< Power voltage detector filter enable */
+
+
+/******************** Bit definition for PWR_CTRL3 register ********************/
+#define PWR_CTRL3_WKUP0EN ((uint16_t)0x0001) /*!< When this bit is set, WKUP0 pin is enable and triggers a wakeup from standby mode. */
+#define PWR_CTRL3_WKUP1EN ((uint16_t)0x0002) /*!< When this bit is set, WKUP1 pin is enable and triggers a wakeup from standby mode. */
+#define PWR_CTRL3_WKUP2EN ((uint16_t)0x0004) /*!< When this bit is set, WKUP2 pin is enable and triggers a wakeup from standby mode. */
+#define PWR_CTRL3_WKUP0PS ((uint16_t)0x0010) /*!< falling edge wake up */
+#define PWR_CTRL3_WKUP1PS ((uint16_t)0x0020) /*!< falling edge wake up */
+#define PWR_CTRL3_WKUP2PS ((uint16_t)0x0040) /*!< falling edge wake up */
+#define PWR_CTRL3_BGDTLPR ((uint16_t)0x0100) /*!< BANDGAP/BG_Buffer/IBIAS duty on in LPRUN */
+#define PWR_CTRL3_BGDTSTP2 ((uint16_t)0x0200) /*!< BANDGAP/BG_Buffer/IBIAS duty on in stop2 */
+#define PWR_CTRL3_BGDTSTBY ((uint16_t)0x0400) /*!< BANDGAP/BG_Buffer/IBIAS duty on in standby */
+#define PWR_CTRL3_RAM1RET ((uint16_t)0x1000) /*!< SRAM1 is powered by the LPR in stop2 mode */
+#define PWR_CTRL3_RAM2RET ((uint16_t)0x2000) /*!< SRAM2 is powered by the LPR in standby mode */
+#define PWR_CTRL3_IWKUPLEN ((uint16_t)0x4000) /*!< internal wakeup line enable */
+
+#define PWR_CTRL3_PBDTLPR ((uint32_t)0x10000) /*!< PVDBOR duty on in LP RUN */
+#define PWR_CTRL3_PBDTSTP2 ((uint32_t)0x20000) /*!< PVDBOR duty on in STOP2 */
+#define PWR_CTRL3_PBDTSTBY ((uint32_t)0x40000) /*!< PVDBOR is iduty on standby */
+#define PWR_CTRL3_PSTSTBY ((uint32_t)0x100000) /*!< PAD in HI-Z state */
+#define PWR_CTRL3_PSTSTP2 ((uint32_t)0x200000) /*!< PAD in HI-Z state */
+
+#define PWR_CTRL3_RAMRETMASK ((uint16_t)0x3000) /*!< SRAM1 and SRAM2 ENABLE */
+#define PWR_CTRL1_LPMSELMASK ((uint16_t)0x0007) /*!< Low power mode selection */
+#define PWR_CTRL2_PLSMASK ((uint16_t)0x000E) /*!< Low power mode selection */
+/******************** Bit definition for PWR_STS1 register ********************/
+#define PWR_STS1_WKUPF0 ((uint16_t)0x0001) /*!< This bit is set when a wakeup event is detected on wakeup pin, WKUP1. */
+#define PWR_STS1_WKUPF1 ((uint16_t)0x0002) /*!< This bit is set when a wakeup event is detected on wakeup pin, WKUP2. */
+#define PWR_STS1_WKUPF2 ((uint16_t)0x0004) /*!< This bit is set when a wakeup event is detected on wakeup pin, WKUP3. */
+#define PWR_STS1_STBYF ((uint16_t)0x0100) /*!< the device entered the standby mode */
+#define PWR_STS1_IWKUPF ((uint16_t)0x8000) /*!< This bit is set when a wakeup is detected on the internal wakeup line. */
+
+/******************** Bit definition for PWR_STS2 register ********************/
+#define PWR_STS2_LPRUNF ((uint16_t)0x0001) /*!< MCU is in low power run mode */
+#define PWR_STS2_MRF ((uint16_t)0x0002) /*!< voltage scaling ready */
+#define PWR_STS2_PVDO ((uint16_t)0x0004) /*!< Power voltage detector output */
+
+/******************** Bit definition for PWR_STSCLR register ********************/
+#define PWR_STSCLR_CLRWKUP0 ((uint16_t)0x0001) /*!< Setting this bit clears the WKPF1 flag in the PWR_STS1 register */
+#define PWR_STSCLR_CLRWKUP1 ((uint16_t)0x0002) /*!< Setting this bit clears the WKPF2 flag in the PWR_STS1 register */
+#define PWR_STSCLR_CLRWKUP2 ((uint16_t)0x0004) /*!< Setting this bit clears the WKPF3 flag in the PWR_STS1 register */
+#define PWR_STSCLR_CLRSTBY ((uint16_t)0x0100) /*!< Setting this bit clears the SBF flag in the PWR_STS1 register */
+
+
+
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for RCC_CTRL register ********************/
+#define RCC_CTRL_HSIEN ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
+#define RCC_CTRL_HSIRDF ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
+#define RCC_CTRL_HSITRIM ((uint32_t)0x0000007C) /*!< Internal High Speed clock trimming */
+#define RCC_CTRL_HSICAL ((uint32_t)0x0000FF80) /*!< Internal High Speed clock Calibration */
+#define RCC_CTRL_HSEEN ((uint32_t)0x00010000) /*!< External High Speed clock enable */
+#define RCC_CTRL_HSERDF ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
+#define RCC_CTRL_HSEBP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
+#define RCC_CTRL_CLKSSEN ((uint32_t)0x00080000) /*!< Clock Security System enable */
+#define RCC_CTRL_PLLEN ((uint32_t)0x01000000) /*!< PLL enable */
+#define RCC_CTRL_PLLRDF ((uint32_t)0x02000000) /*!< PLL clock ready flag */
+
+/******************* Bit definition for RCC_CFG register *******************/
+/*!< SW configuration */
+#define RCC_CFG_SCLKSW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFG_SCLKSW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFG_SCLKSW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFG_SCLKSW_MSI ((uint32_t)0x00000000) /*!< MSI selected as system clock */
+#define RCC_CFG_SCLKSW_HSI ((uint32_t)0x00000001) /*!< HSI selected as system clock */
+#define RCC_CFG_SCLKSW_HSE ((uint32_t)0x00000002) /*!< HSE selected as system clock */
+#define RCC_CFG_SCLKSW_PLL ((uint32_t)0x00000003) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFG_SCLKSTS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFG_SCLKSTS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFG_SCLKSTS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFG_SCLKSTS_MSI ((uint32_t)0x00000000) /*!< MSI oscillator used as system clock */
+#define RCC_CFG_SCLKSTS_HSI ((uint32_t)0x00000004) /*!< HSI oscillator used as system clock */
+#define RCC_CFG_SCLKSTS_HSE ((uint32_t)0x00000008) /*!< HSE oscillator used as system clock */
+#define RCC_CFG_SCLKSTS_PLL ((uint32_t)0x0000000C) /*!< PLL used as system clock */
+
+/*!< AHBPRES configuration */
+#define RCC_CFG_AHBPRES ((uint32_t)0x000000F0) /*!< AHBPRES[3:0] bits (AHB prescaler) */
+#define RCC_CFG_AHBPRES_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFG_AHBPRES_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFG_AHBPRES_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFG_AHBPRES_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFG_AHBPRES_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFG_AHBPRES_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFG_AHBPRES_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFG_AHBPRES_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFG_AHBPRES_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFG_AHBPRES_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFG_AHBPRES_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFG_AHBPRES_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFG_AHBPRES_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< APB1PRES configuration */
+#define RCC_CFG_APB1PRES ((uint32_t)0x00000700) /*!< APB1PRES[2:0] bits (APB1 prescaler) */
+#define RCC_CFG_APB1PRES_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_CFG_APB1PRES_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define RCC_CFG_APB1PRES_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+#define RCC_CFG_APB1PRES_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFG_APB1PRES_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFG_APB1PRES_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFG_APB1PRES_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFG_APB1PRES_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< APB2PRES configuration */
+#define RCC_CFG_APB2PRES ((uint32_t)0x00003800) /*!< APB2PRES[2:0] bits (APB2 prescaler) */
+#define RCC_CFG_APB2PRES_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define RCC_CFG_APB2PRES_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+#define RCC_CFG_APB2PRES_2 ((uint32_t)0x00002000) /*!< Bit 2 */
+
+#define RCC_CFG_APB2PRES_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFG_APB2PRES_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFG_APB2PRES_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFG_APB2PRES_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFG_APB2PRES_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+/*!< PLLSRC configuration */
+#define RCC_CFG_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
+
+#define RCC_CFG_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI clock selected as PLL entry clock source */
+#define RCC_CFG_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */
+
+/*!< PLLXTPRE configuration */
+#define RCC_CFG_PLLHSEPRES ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
+
+#define RCC_CFG_PLLHSEPRES_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
+#define RCC_CFG_PLLHSEPRES_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFG_PLLMULFCT ((uint32_t)0x083C0000) /*!< PLLMUL[4:0] bits (PLL multiplication factor) */
+#define RCC_CFG_PLLMULFCT_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFG_PLLMULFCT_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define RCC_CFG_PLLMULFCT_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+#define RCC_CFG_PLLMULFCT_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+#define RCC_CFG_PLLMULFCT_4 ((uint32_t)0x08000000) /*!< Bit 4 */
+
+#define RCC_CFG_PLLMULFCT2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFG_PLLMULFCT3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
+#define RCC_CFG_PLLMULFCT4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
+#define RCC_CFG_PLLMULFCT5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
+#define RCC_CFG_PLLMULFCT6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
+#define RCC_CFG_PLLMULFCT7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
+#define RCC_CFG_PLLMULFCT8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
+#define RCC_CFG_PLLMULFCT9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
+#define RCC_CFG_PLLMULFCT10 ((uint32_t)0x00200000) /*!< PLL input clock*10 */
+#define RCC_CFG_PLLMULFCT11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
+#define RCC_CFG_PLLMULFCT12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
+#define RCC_CFG_PLLMULFCT13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
+#define RCC_CFG_PLLMULFCT14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
+#define RCC_CFG_PLLMULFCT15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
+#define RCC_CFG_PLLMULFCT16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
+#define RCC_CFG_PLLMULFCT16N ((uint32_t)0x003C0000) /*!< PLL input clock*16 */
+#define RCC_CFG_PLLMULFCT17 ((uint32_t)0x08000000) /*!< PLL input clock*17 */
+#define RCC_CFG_PLLMULFCT18 ((uint32_t)0x08040000) /*!< PLL input clock*18 */
+#define RCC_CFG_PLLMULFCT19 ((uint32_t)0x08080000) /*!< PLL input clock*19 */
+#define RCC_CFG_PLLMULFCT20 ((uint32_t)0x080C0000) /*!< PLL input clock*20 */
+#define RCC_CFG_PLLMULFCT21 ((uint32_t)0x08100000) /*!< PLL input clock*21 */
+#define RCC_CFG_PLLMULFCT22 ((uint32_t)0x08140000) /*!< PLL input clock*22 */
+#define RCC_CFG_PLLMULFCT23 ((uint32_t)0x08180000) /*!< PLL input clock*23 */
+#define RCC_CFG_PLLMULFCT24 ((uint32_t)0x081C0000) /*!< PLL input clock*24 */
+#define RCC_CFG_PLLMULFCT25 ((uint32_t)0x08200000) /*!< PLL input clock*25 */
+#define RCC_CFG_PLLMULFCT26 ((uint32_t)0x08240000) /*!< PLL input clock*26 */
+#define RCC_CFG_PLLMULFCT27 ((uint32_t)0x08280000) /*!< PLL input clock*27 */
+#define RCC_CFG_PLLMULFCT28 ((uint32_t)0x082C0000) /*!< PLL input clock*28 */
+#define RCC_CFG_PLLMULFCT29 ((uint32_t)0x08300000) /*!< PLL input clock*29 */
+#define RCC_CFG_PLLMULFCT30 ((uint32_t)0x08340000) /*!< PLL input clock*30 */
+#define RCC_CFG_PLLMULFCT31 ((uint32_t)0x08380000) /*!< PLL input clock*31 */
+#define RCC_CFG_PLLMULFCT32 ((uint32_t)0x083C0000) /*!< PLL input clock*32 */
+
+/*!< USBPRES configuration */
+#define RCC_CFG_USBPRES ((uint32_t)0x00C00000) /*!< USB Device prescaler */
+#define RCC_CFG_USBPRES_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define RCC_CFG_USBPRES_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define RCC_CFG_USBPRES_PLLDIV1_5 ((uint32_t)0x00000000) /*!< PLL clock is divided by 1.5 */
+#define RCC_CFG_USBPRES_PLLDIV1 ((uint32_t)0x00400000) /*!< PLL clock is not divided */
+#define RCC_CFG_USBPRES_PLLDIV2 ((uint32_t)0x00800000) /*!< PLL clock is divided by 2 */
+#define RCC_CFG_USBPRES_PLLDIV3 ((uint32_t)0x00C00000) /*!< PLL clock is divided by 3 */
+
+/*!< MCO configuration */
+#define RCC_CFG_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define RCC_CFG_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define RCC_CFG_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define RCC_CFG_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define RCC_CFG_MCO_NOCLK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFG_MCO_LSI ((uint32_t)0x01000000) /*!< LSI clock selected as MCO source */
+#define RCC_CFG_MCO_LSE ((uint32_t)0x02000000) /*!< LSE clock selected as MCO source */
+#define RCC_CFG_MCO_MSI ((uint32_t)0x03000000) /*!< MSI clock selected as MCO source */
+#define RCC_CFG_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFG_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFG_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFG_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock selected as MCO source */
+
+/*!< MCOPRE configuration */
+#define RCC_CFG_MCOPRES ((uint32_t)0xF0000000) /*!< MCOPRE[3:0] bits ( PLL prescaler set and cleared by
+ software to generate MCOPRE clock.) */
+#define RCC_CFG_MCOPRES_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define RCC_CFG_MCOPRES_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+#define RCC_CFG_MCOPRES_2 ((uint32_t)0x40000000) /*!< Bit 2 */
+#define RCC_CFG_MCOPRES_3 ((uint32_t)0x80000000) /*!< Bit 3 */
+
+#define RCC_CFG_MCOPRES_PLLDIV1 ((uint32_t)0x00000000) /*!< PLL clock is not divided */
+#define RCC_CFG_MCOPRES_PLLDIV2 ((uint32_t)0x10000000) /*!< PLL clock is divided by 2 */
+#define RCC_CFG_MCOPRES_PLLDIV3 ((uint32_t)0x20000000) /*!< PLL clock is divided by 3 */
+#define RCC_CFG_MCOPRES_PLLDIV4 ((uint32_t)0x30000000) /*!< PLL clock is divided by 4 */
+#define RCC_CFG_MCOPRES_PLLDIV5 ((uint32_t)0x40000000) /*!< PLL clock is divided by 5 */
+#define RCC_CFG_MCOPRES_PLLDIV6 ((uint32_t)0x50000000) /*!< PLL clock is divided by 6 */
+#define RCC_CFG_MCOPRES_PLLDIV7 ((uint32_t)0x60000000) /*!< PLL clock is divided by 7 */
+#define RCC_CFG_MCOPRES_PLLDIV8 ((uint32_t)0x70000000) /*!< PLL clock is divided by 8 */
+#define RCC_CFG_MCOPRES_PLLDIV9 ((uint32_t)0x80000000) /*!< PLL clock is divided by 9 */
+#define RCC_CFG_MCOPRES_PLLDIV10 ((uint32_t)0x90000000) /*!< PLL clock is divided by 10 */
+#define RCC_CFG_MCOPRES_PLLDIV11 ((uint32_t)0xA0000000) /*!< PLL clock is divided by 11 */
+#define RCC_CFG_MCOPRES_PLLDIV12 ((uint32_t)0xB0000000) /*!< PLL clock is divided by 12 */
+#define RCC_CFG_MCOPRES_PLLDIV13 ((uint32_t)0xC0000000) /*!< PLL clock is divided by 13 */
+#define RCC_CFG_MCOPRES_PLLDIV14 ((uint32_t)0xD0000000) /*!< PLL clock is divided by 14 */
+#define RCC_CFG_MCOPRES_PLLDIV15 ((uint32_t)0xE0000000) /*!< PLL clock is divided by 15 */
+#define RCC_CFG_MCOPRES_PLLDIV16 ((uint32_t)0xF0000000) /*!< PLL clock is divided by 16 */
+
+/*!<****************** Bit definition for RCC_CLKINT register ********************/
+#define RCC_CLKINT_LSIRDIF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
+#define RCC_CLKINT_LSERDIF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
+#define RCC_CLKINT_HSIRDIF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
+#define RCC_CLKINT_HSERDIF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
+#define RCC_CLKINT_PLLRDIF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
+#define RCC_CLKINT_BORIF ((uint32_t)0x00000020) /*!< BOR Interrupt flag */
+#define RCC_CLKINT_MSIRDIF ((uint32_t)0x00000040) /*!< MSI Ready Interrupt flag */
+#define RCC_CLKINT_CLKSSIF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
+#define RCC_CLKINT_LSIRDIEN ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
+#define RCC_CLKINT_LSERDIEN ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
+#define RCC_CLKINT_HSIRDIEN ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
+#define RCC_CLKINT_HSERDIEN ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
+#define RCC_CLKINT_PLLRDIEN ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
+#define RCC_CLKINT_BORIEN ((uint32_t)0x00002000) /*!< BOR Interrupt Enable */
+#define RCC_CLKINT_MSIRDIEN ((uint32_t)0x00004000) /*!< MSI Ready Interrupt Enable */
+#define RCC_CLKINT_MSIRDICLR ((uint32_t)0x00008000) /*!< MSI Ready Interrupt Clear */
+#define RCC_CLKINT_LSIRDICLR ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
+#define RCC_CLKINT_LSERDICLR ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
+#define RCC_CLKINT_HSIRDICLR ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
+#define RCC_CLKINT_HSERDICLR ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
+#define RCC_CLKINT_PLLRDICLR ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
+#define RCC_CLKINT_BORICLR ((uint32_t)0x00200000) /*!< BOR Interrupt Clear */
+#define RCC_CLKINT_CLKSSICLR ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
+#define RCC_CLKINT_LSESSIF ((uint32_t)0x01000000) /*!< LSE Security System Interrupt flag */
+#define RCC_CLKINT_LSESSIEN ((uint32_t)0x02000000) /*!< LSE ecurity System Interrupt Enable */
+#define RCC_CLKINT_LSESSICLR ((uint32_t)0x04000000) /*!< LSE ecurity System Interrupt Clear */
+
+/***************** Bit definition for RCC_APB2PRST register *****************/
+#define RCC_APB2PRST_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */
+#define RCC_APB2PRST_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */
+#define RCC_APB2PRST_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */
+#define RCC_APB2PRST_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */
+#define RCC_APB2PRST_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */
+#define RCC_APB2PRST_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */
+#define RCC_APB2PRST_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */
+#define RCC_APB2PRST_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */
+#define RCC_APB2PRST_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
+#define RCC_APB2PRST_UART4RST ((uint32_t)0x00020000) /*!< UART4 reset */
+#define RCC_APB2PRST_UART5RST ((uint32_t)0x00040000) /*!< UART5 reset */
+#define RCC_APB2PRST_SPI2RST ((uint32_t)0x00080000) /*!< SPI2 reset */
+
+/***************** Bit definition for RCC_APB1PRST register *****************/
+#define RCC_APB1PRST_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
+#define RCC_APB1PRST_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
+#define RCC_APB1PRST_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
+#define RCC_APB1PRST_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
+#define RCC_APB1PRST_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
+#define RCC_APB1PRST_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
+#define RCC_APB1PRST_COMPRST ((uint32_t)0x00000040) /*!< COMP reset */
+#define RCC_APB1PRST_TIM9RST ((uint32_t)0x00000200) /*!< Timer 9 reset */
+#define RCC_APB1PRST_TSCRST ((uint32_t)0x00000400) /*!< TSC reset */
+#define RCC_APB1PRST_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
+#define RCC_APB1PRST_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
+#define RCC_APB1PRST_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
+#define RCC_APB1PRST_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
+#define RCC_APB1PRST_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
+#define RCC_APB1PRST_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */
+#define RCC_APB1PRST_UCDRRST ((uint32_t)0x01000000) /*!< UCDR reset */
+#define RCC_APB1PRST_CANRST ((uint32_t)0x02000000) /*!< CAN reset */
+#define RCC_APB1PRST_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
+#define RCC_APB1PRST_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
+#define RCC_APB1PRST_OPARST ((uint32_t)0x80000000) /*!< OPA interface reset */
+
+/****************** Bit definition for RCC_AHBPCLKEN register ******************/
+#define RCC_AHBPCLKEN_DMAEN ((uint32_t)0x00000001) /*!< DMA clock enable */
+#define RCC_AHBPCLKEN_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
+#define RCC_AHBPCLKEN_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
+#define RCC_AHBPCLKEN_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
+#define RCC_AHBPCLKEN_RNGCEN ((uint32_t)0x00000200) /*!< RNGC clock enable */
+#define RCC_AHBPCLKEN_SACEN ((uint32_t)0x00000800) /*!< SAC clock enable */
+#define RCC_AHBPCLKEN_ADCEN ((uint32_t)0x00001000) /*!< ADC clock enable */
+
+/****************** Bit definition for RCC_APB2PCLKEN register *****************/
+#define RCC_APB2PCLKEN_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */
+#define RCC_APB2PCLKEN_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */
+#define RCC_APB2PCLKEN_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */
+#define RCC_APB2PCLKEN_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */
+#define RCC_APB2PCLKEN_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */
+#define RCC_APB2PCLKEN_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */
+#define RCC_APB2PCLKEN_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
+#define RCC_APB2PCLKEN_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */
+#define RCC_APB2PCLKEN_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
+#define RCC_APB2PCLKEN_UART4EN ((uint32_t)0x00020000) /*!< UART4 clock enable */
+#define RCC_APB2PCLKEN_UART5EN ((uint32_t)0x00040000) /*!< UART5 clock enable */
+#define RCC_APB2PCLKEN_SPI2EN ((uint32_t)0x00080000) /*!< SPI2 clock enable */
+
+/***************** Bit definition for RCC_APB1PCLKEN register ******************/
+#define RCC_APB1PCLKEN_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
+#define RCC_APB1PCLKEN_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
+#define RCC_APB1PCLKEN_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
+#define RCC_APB1PCLKEN_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */
+#define RCC_APB1PCLKEN_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
+#define RCC_APB1PCLKEN_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
+#define RCC_APB1PCLKEN_COMPEN ((uint32_t)0x00000040) /*!< COMP clock enable */
+#define RCC_APB1PCLKEN_COMPFILTEN ((uint32_t)0x00000080) /*!< COMPFILT clock enable */
+#define RCC_APB1PCLKEN_AFECEN ((uint32_t)0x00000100) /*!< AFEC clock enable */
+#define RCC_APB1PCLKEN_TIM9EN ((uint32_t)0x00000200) /*!< Timer 9 clock enable */
+#define RCC_APB1PCLKEN_TSCEN ((uint32_t)0x00000400) /*!< TSC clock enable */
+#define RCC_APB1PCLKEN_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
+#define RCC_APB1PCLKEN_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
+#define RCC_APB1PCLKEN_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
+#define RCC_APB1PCLKEN_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
+#define RCC_APB1PCLKEN_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
+#define RCC_APB1PCLKEN_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */
+#define RCC_APB1PCLKEN_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
+#define RCC_APB1PCLKEN_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
+#define RCC_APB1PCLKEN_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
+#define RCC_APB1PCLKEN_OPAMPEN ((uint32_t)0x80000000) /*!< OPAMP interface clock enable */
+
+/******************* Bit definition for RCC_LDCTRL register *******************/
+#define RCC_LDCTRL_LSEEN ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
+#define RCC_LDCTRL_LSERD ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
+#define RCC_LDCTRL_LSEBP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
+
+#define RCC_LDCTRL_LSECLKSSEN ((uint32_t)0x00000008) /*!< LSE Security System enable */
+#define RCC_LDCTRL_LSECLKSSF ((uint32_t)0x00000010) /*!< LSE Security System failure detection */
+#define RCC_LDCTRL_LSXSEL ((uint32_t)0x00000020) /*!< LSXSEL bits (TSC clock source selection) */
+
+#define RCC_LDCTRL_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_LDCTRL_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_LDCTRL_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< RTC congiguration */
+#define RCC_LDCTRL_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_LDCTRL_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_LDCTRL_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_LDCTRL_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 32 used as RTC clock */
+
+#define RCC_LDCTRL_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
+#define RCC_LDCTRL_LDSFTRST ((uint32_t)0x00010000) /*!< Low power domain software reset */
+#define RCC_LDCTRL_BORRSTF ((uint32_t)0x10000000) /*!< BOR reset flag */
+#define RCC_LDCTRL_LDEMCRSTF ((uint32_t)0x40000000) /*!< Low power EMC reset flag */
+
+/******************* Bit definition for RCC_CTRLSTS register ********************/
+#define RCC_CTRLSTS_LSIEN ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
+#define RCC_CTRLSTS_LSIRD ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
+#define RCC_CTRLSTS_MSIEN ((uint32_t)0x00000004) /*!< Internal Multi Speed oscillator enable */
+#define RCC_CTRLSTS_MSIRD ((uint32_t)0x00000008) /*!< Internal Multi Speed oscillator Ready */
+
+#define RCC_CTRLSTS_MSIRANGE ((uint32_t)0x00000070) /*!< Internal Multi Speed oscillator Clock Range */
+#define RCC_CTRLSTS_MSIRANGE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CTRLSTS_MSIRANGE_1 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define RCC_CTRLSTS_MSIRANGE_2 ((uint32_t)0x00000040) /*!< Bit 0 */
+
+#define RCC_CTRLSTS_MSIRANGE_100KHz ((uint32_t)0x00000000) /*!< Internal Multi Speed oscillator output 100KHz */
+#define RCC_CTRLSTS_MSIRANGE_200KHz ((uint32_t)0x00000010) /*!< Internal Multi Speed oscillator output 200KHz */
+#define RCC_CTRLSTS_MSIRANGE_400KHz ((uint32_t)0x00000020) /*!< Internal Multi Speed oscillator output 400KHz */
+#define RCC_CTRLSTS_MSIRANGE_800KHz ((uint32_t)0x00000030) /*!< Internal Multi Speed oscillator output 800KHz */
+#define RCC_CTRLSTS_MSIRANGE_1MHz ((uint32_t)0x00000040) /*!< Internal Multi Speed oscillator output 1MHz */
+#define RCC_CTRLSTS_MSIRANGE_2MHz ((uint32_t)0x00000050) /*!< Internal Multi Speed oscillator output 2MHz */
+#define RCC_CTRLSTS_MSIRANGE_4MHz ((uint32_t)0x00000060) /*!< Internal Multi Speed oscillator output 4MHz */
+
+#define RCC_CTRLSTS_MSICAL ((uint32_t)0x00007F80) /*!< Internal Multi Speed clock Calibration */
+#define RCC_CTRLSTS_MSITRIM ((uint32_t)0x007F8000) /*!< Internal Multi Speed clock trimming */
+#define RCC_CTRLSTS_RAMRSTF ((uint32_t)0x00800000) /*!< RAM reset flag */
+#define RCC_CTRLSTS_RMRSTF ((uint32_t)0x01000000) /*!< Remove reset flag */
+#define RCC_CTRLSTS_MMURSTF ((uint32_t)0x02000000) /*!< MMU reset flag */
+#define RCC_CTRLSTS_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
+#define RCC_CTRLSTS_PORRSTF ((uint32_t)0x08000000) /*!< POR reset flag */
+#define RCC_CTRLSTS_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
+#define RCC_CTRLSTS_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
+#define RCC_CTRLSTS_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
+#define RCC_CTRLSTS_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
+
+/******************* Bit definition for RCC_AHBPRST register ****************/
+#define RCC_AHBRST_RNGCRST ((uint32_t)0x00000200) /*!< RNGC reset */
+#define RCC_AHBRST_SACRST ((uint32_t)0x00000800) /*!< SAC reset */
+#define RCC_AHBRST_ADCRST ((uint32_t)0x00001000) /*!< ADC reset */
+
+/******************* Bit definition for RCC_CFG2 register ******************/
+/*!< ADCHPRE configuration */
+#define RCC_CFG2_ADCHPRES ((uint32_t)0x0000000F) /*!< ADCHPRE[3:0] bits */
+#define RCC_CFG2_ADCHPRES_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFG2_ADCHPRES_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RCC_CFG2_ADCHPRES_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RCC_CFG2_ADCHPRES_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define RCC_CFG2_ADCHPRES_DIV1 ((uint32_t)0x00000000) /*!< HCLK clock divided by 1 */
+#define RCC_CFG2_ADCHPRES_DIV2 ((uint32_t)0x00000001) /*!< HCLK clock divided by 2 */
+#define RCC_CFG2_ADCHPRES_DIV4 ((uint32_t)0x00000002) /*!< HCLK clock divided by 4 */
+#define RCC_CFG2_ADCHPRES_DIV6 ((uint32_t)0x00000003) /*!< HCLK clock divided by 6 */
+#define RCC_CFG2_ADCHPRES_DIV8 ((uint32_t)0x00000004) /*!< HCLK clock divided by 8 */
+#define RCC_CFG2_ADCHPRES_DIV10 ((uint32_t)0x00000005) /*!< HCLK clock divided by 10 */
+#define RCC_CFG2_ADCHPRES_DIV12 ((uint32_t)0x00000006) /*!< HCLK clock divided by 12 */
+#define RCC_CFG2_ADCHPRES_DIV16 ((uint32_t)0x00000007) /*!< HCLK clock divided by 16 */
+#define RCC_CFG2_ADCHPRES_DIV32 ((uint32_t)0x00000008) /*!< HCLK clock divided by 32 */
+#define RCC_CFG2_ADCHPRES_OTHERS ((uint32_t)0x00000008) /*!< HCLK clock divided by 32 */
+
+/*!< ADCPLLPRES configuration */
+#define RCC_CFG2_ADCPLLPRES ((uint32_t)0x000001F0) /*!< ADCPLLPRES[4:0] bits */
+#define RCC_CFG2_ADCPLLPRES_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFG2_ADCPLLPRES_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFG2_ADCPLLPRES_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFG2_ADCPLLPRES_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+#define RCC_CFG2_ADCPLLPRES_4 ((uint32_t)0x00000100) /*!< Bit 4 */
+
+#define RCC_CFG2_ADCPLLCLK_DISABLE ((uint32_t)0xFFFFFEFF) /*!< ADC PLL clock Disable */
+#define RCC_CFG2_ADCPLLPRES_DIV1 ((uint32_t)0x00000100) /*!< PLL clock divided by 1 */
+#define RCC_CFG2_ADCPLLPRES_DIV2 ((uint32_t)0x00000110) /*!< PLL clock divided by 2 */
+#define RCC_CFG2_ADCPLLPRES_DIV4 ((uint32_t)0x00000120) /*!< PLL clock divided by 4 */
+#define RCC_CFG2_ADCPLLPRES_DIV6 ((uint32_t)0x00000130) /*!< PLL clock divided by 6 */
+#define RCC_CFG2_ADCPLLPRES_DIV8 ((uint32_t)0x00000140) /*!< PLL clock divided by 8 */
+#define RCC_CFG2_ADCPLLPRES_DIV10 ((uint32_t)0x00000150) /*!< PLL clock divided by 10 */
+#define RCC_CFG2_ADCPLLPRES_DIV12 ((uint32_t)0x00000160) /*!< PLL clock divided by 12 */
+#define RCC_CFG2_ADCPLLPRES_DIV16 ((uint32_t)0x00000170) /*!< PLL clock divided by 16 */
+#define RCC_CFG2_ADCPLLPRES_DIV32 ((uint32_t)0x00000180) /*!< PLL clock divided by 32 */
+#define RCC_CFG2_ADCPLLPRES_DIV64 ((uint32_t)0x00000190) /*!< PLL clock divided by 64 */
+#define RCC_CFG2_ADCPLLPRES_DIV128 ((uint32_t)0x000001A0) /*!< PLL clock divided by 128 */
+#define RCC_CFG2_ADCPLLPRES_DIV256 ((uint32_t)0x000001B0) /*!< PLL clock divided by 256 */
+#define RCC_CFG2_ADCPLLPRES_DIV256N ((uint32_t)0x000001C0) /*!< PLL clock divided by 256 */
+
+/*!< ADC1MPRE configuration */
+#define RCC_CFG2_ADC1MPRES ((uint32_t)0x0001F000) /*!< ADC1MPRE[4:0] bits */
+#define RCC_CFG2_ADC1MPRES_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define RCC_CFG2_ADC1MPRES_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define RCC_CFG2_ADC1MPRES_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+#define RCC_CFG2_ADC1MPRES_3 ((uint32_t)0x00008000) /*!< Bit 3 */
+#define RCC_CFG2_ADC1MPRES_4 ((uint32_t)0x00010000) /*!< Bit 4 */
+
+#define RCC_CFG2_ADC1MPRES_DIV1 ((uint32_t)0x00000000) /*!< ADC1M source clock is divided by 1 */
+#define RCC_CFG2_ADC1MPRES_DIV2 ((uint32_t)0x00001000) /*!< ADC1M source clock is divided by 2 */
+#define RCC_CFG2_ADC1MPRES_DIV3 ((uint32_t)0x00002000) /*!< ADC1M source clock is divided by 3 */
+#define RCC_CFG2_ADC1MPRES_DIV4 ((uint32_t)0x00003000) /*!< ADC1M source clock is divided by 4 */
+#define RCC_CFG2_ADC1MPRES_DIV5 ((uint32_t)0x00004000) /*!< ADC1M source clock is divided by 5 */
+#define RCC_CFG2_ADC1MPRES_DIV6 ((uint32_t)0x00005000) /*!< ADC1M source clock is divided by 6 */
+#define RCC_CFG2_ADC1MPRES_DIV7 ((uint32_t)0x00006000) /*!< ADC1M source clock is divided by 7 */
+#define RCC_CFG2_ADC1MPRES_DIV8 ((uint32_t)0x00007000) /*!< ADC1M source clock is divided by 8 */
+#define RCC_CFG2_ADC1MPRES_DIV9 ((uint32_t)0x00008000) /*!< ADC1M source clock is divided by 9 */
+#define RCC_CFG2_ADC1MPRES_DIV10 ((uint32_t)0x00009000) /*!< ADC1M source clock is divided by 10 */
+#define RCC_CFG2_ADC1MPRES_DIV11 ((uint32_t)0x0000A000) /*!< ADC1M source clock is divided by 11 */
+#define RCC_CFG2_ADC1MPRES_DIV12 ((uint32_t)0x0000B000) /*!< ADC1M source clock is divided by 12 */
+#define RCC_CFG2_ADC1MPRES_DIV13 ((uint32_t)0x0000C000) /*!< ADC1M source clock is divided by 13 */
+#define RCC_CFG2_ADC1MPRES_DIV14 ((uint32_t)0x0000D000) /*!< ADC1M source clock is divided by 14 */
+#define RCC_CFG2_ADC1MPRES_DIV15 ((uint32_t)0x0000E000) /*!< ADC1M source clock is divided by 15 */
+#define RCC_CFG2_ADC1MPRES_DIV16 ((uint32_t)0x0000F000) /*!< ADC1M source clock is divided by 16 */
+#define RCC_CFG2_ADC1MPRES_DIV17 ((uint32_t)0x00010000) /*!< ADC1M source clock is divided by 17 */
+#define RCC_CFG2_ADC1MPRES_DIV18 ((uint32_t)0x00011000) /*!< ADC1M source clock is divided by 18 */
+#define RCC_CFG2_ADC1MPRES_DIV19 ((uint32_t)0x00012000) /*!< ADC1M source clock is divided by 19 */
+#define RCC_CFG2_ADC1MPRES_DIV20 ((uint32_t)0x00013000) /*!< ADC1M source clock is divided by 20 */
+#define RCC_CFG2_ADC1MPRES_DIV21 ((uint32_t)0x00014000) /*!< ADC1M source clock is divided by 21 */
+#define RCC_CFG2_ADC1MPRES_DIV22 ((uint32_t)0x00015000) /*!< ADC1M source clock is divided by 22 */
+#define RCC_CFG2_ADC1MPRES_DIV23 ((uint32_t)0x00016000) /*!< ADC1M source clock is divided by 23 */
+#define RCC_CFG2_ADC1MPRES_DIV24 ((uint32_t)0x00017000) /*!< ADC1M source clock is divided by 24 */
+#define RCC_CFG2_ADC1MPRES_DIV25 ((uint32_t)0x00018000) /*!< ADC1M source clock is divided by 25 */
+#define RCC_CFG2_ADC1MPRES_DIV26 ((uint32_t)0x00019000) /*!< ADC1M source clock is divided by 26 */
+#define RCC_CFG2_ADC1MPRES_DIV27 ((uint32_t)0x0001A000) /*!< ADC1M source clock is divided by 27 */
+#define RCC_CFG2_ADC1MPRES_DIV28 ((uint32_t)0x0001B000) /*!< ADC1M source clock is divided by 28 */
+#define RCC_CFG2_ADC1MPRES_DIV29 ((uint32_t)0x0001C000) /*!< ADC1M source clock is divided by 29 */
+#define RCC_CFG2_ADC1MPRES_DIV30 ((uint32_t)0x0001D000) /*!< ADC1M source clock is divided by 30 */
+#define RCC_CFG2_ADC1MPRES_DIV31 ((uint32_t)0x0001E000) /*!< ADC1M source clock is divided by 31 */
+#define RCC_CFG2_ADC1MPRES_DIV32 ((uint32_t)0x0001F000) /*!< ADC1M source clock is divided by 32 */
+
+/*!< ADC1MSEL configuration */
+#define RCC_CFG2_ADC1MSEL ((uint32_t)0x00020000) /*!< ADC1M clock source select */
+
+#define RCC_CFG2_ADC1MSEL_HSI ((uint32_t)0x00000000) /*!< HSI clock selected as ADC1M input clock */
+#define RCC_CFG2_ADC1MSEL_HSE ((uint32_t)0x00020000) /*!< HSE clock selected as ADC1M input clock */
+
+/*!< RNGCPRE configuration */
+#define RCC_CFG2_RNGCPRES ((uint32_t)0x1F000000) /*!< RNGCPRE[4:0] bits */
+#define RCC_CFG2_RNGCPRES_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define RCC_CFG2_RNGCPRES_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define RCC_CFG2_RNGCPRES_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define RCC_CFG2_RNGCPRES_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define RCC_CFG2_RNGCPRES_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+
+#define RCC_CFG2_RNGCPRES_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK source clock is divided by 1 */
+#define RCC_CFG2_RNGCPRES_DIV2 ((uint32_t)0x01000000) /*!< SYSCLK source clock is divided by 2 */
+#define RCC_CFG2_RNGCPRES_DIV3 ((uint32_t)0x02000000) /*!< SYSCLK source clock is divided by 3 */
+#define RCC_CFG2_RNGCPRES_DIV4 ((uint32_t)0x03000000) /*!< SYSCLK source clock is divided by 4 */
+#define RCC_CFG2_RNGCPRES_DIV5 ((uint32_t)0x04000000) /*!< SYSCLK source clock is divided by 5 */
+#define RCC_CFG2_RNGCPRES_DIV6 ((uint32_t)0x05000000) /*!< SYSCLK source clock is divided by 6 */
+#define RCC_CFG2_RNGCPRES_DIV7 ((uint32_t)0x06000000) /*!< SYSCLK source clock is divided by 7 */
+#define RCC_CFG2_RNGCPRES_DIV8 ((uint32_t)0x07000000) /*!< SYSCLK source clock is divided by 8 */
+#define RCC_CFG2_RNGCPRES_DIV9 ((uint32_t)0x08000000) /*!< SYSCLK source clock is divided by 9 */
+#define RCC_CFG2_RNGCPRES_DIV10 ((uint32_t)0x09000000) /*!< SYSCLK source clock is divided by 10 */
+#define RCC_CFG2_RNGCPRES_DIV11 ((uint32_t)0x0A000000) /*!< SYSCLK source clock is divided by 11 */
+#define RCC_CFG2_RNGCPRES_DIV12 ((uint32_t)0x0B000000) /*!< SYSCLK source clock is divided by 12 */
+#define RCC_CFG2_RNGCPRES_DIV13 ((uint32_t)0x0C000000) /*!< SYSCLK source clock is divided by 13 */
+#define RCC_CFG2_RNGCPRES_DIV14 ((uint32_t)0x0D000000) /*!< SYSCLK source clock is divided by 14 */
+#define RCC_CFG2_RNGCPRES_DIV15 ((uint32_t)0x0E000000) /*!< SYSCLK source clock is divided by 15 */
+#define RCC_CFG2_RNGCPRES_DIV16 ((uint32_t)0x0F000000) /*!< SYSCLK source clock is divided by 16 */
+#define RCC_CFG2_RNGCPRES_DIV17 ((uint32_t)0x10000000) /*!< SYSCLK source clock is divided by 17 */
+#define RCC_CFG2_RNGCPRES_DIV18 ((uint32_t)0x11000000) /*!< SYSCLK source clock is divided by 18 */
+#define RCC_CFG2_RNGCPRES_DIV19 ((uint32_t)0x12000000) /*!< SYSCLK source clock is divided by 19 */
+#define RCC_CFG2_RNGCPRES_DIV20 ((uint32_t)0x13000000) /*!< SYSCLK source clock is divided by 20 */
+#define RCC_CFG2_RNGCPRES_DIV21 ((uint32_t)0x14000000) /*!< SYSCLK source clock is divided by 21 */
+#define RCC_CFG2_RNGCPRES_DIV22 ((uint32_t)0x15000000) /*!< SYSCLK source clock is divided by 22 */
+#define RCC_CFG2_RNGCPRES_DIV23 ((uint32_t)0x16000000) /*!< SYSCLK source clock is divided by 23 */
+#define RCC_CFG2_RNGCPRES_DIV24 ((uint32_t)0x17000000) /*!< SYSCLK source clock is divided by 24 */
+#define RCC_CFG2_RNGCPRES_DIV25 ((uint32_t)0x18000000) /*!< SYSCLK source clock is divided by 25 */
+#define RCC_CFG2_RNGCPRES_DIV26 ((uint32_t)0x19000000) /*!< SYSCLK source clock is divided by 26 */
+#define RCC_CFG2_RNGCPRES_DIV27 ((uint32_t)0x1A000000) /*!< SYSCLK source clock is divided by 27 */
+#define RCC_CFG2_RNGCPRES_DIV28 ((uint32_t)0x1B000000) /*!< SYSCLK source clock is divided by 28 */
+#define RCC_CFG2_RNGCPRES_DIV29 ((uint32_t)0x1C000000) /*!< SYSCLK source clock is divided by 29 */
+#define RCC_CFG2_RNGCPRES_DIV30 ((uint32_t)0x1D000000) /*!< SYSCLK source clock is divided by 30 */
+#define RCC_CFG2_RNGCPRES_DIV31 ((uint32_t)0x1E000000) /*!< SYSCLK source clock is divided by 31 */
+#define RCC_CFG2_RNGCPRES_DIV32 ((uint32_t)0x1F000000) /*!< SYSCLK source clock is divided by 32 */
+
+/*!< TIMCLK_SEL configuration */
+#define RCC_CFG2_TIMCLKSEL ((uint32_t)0x20000000) /*!< Timer1/8 clock source select */
+
+#define RCC_CFG2_TIMCLKSEL_TIM18CLK ((uint32_t)0x00000000) /*!< Timer1/8 clock selected as tim1/8_clk input clock */
+#define RCC_CFG2_TIMCLKSEL_SYSCLK ((uint32_t)0x20000000) /*!< Timer1/8 clock selected as sysclk input clock */
+
+/******************* Bit definition for RCC_CFG3 register ******************/
+/*!< UCDREN configuration */
+#define RCC_CFG3_UCDREN ((uint32_t)0x00000080) /*!< UCDR enable */
+
+#define RCC_CFG3_UCDREN_ENABLE ((uint32_t)0x00000080) /*!< UCDREN enable */
+#define RCC_CFG3_UCDREN_DISABLE ((uint32_t)0x00000000) /*!< UCDREN disable */
+
+/*!< USBXTALESS configuration */
+#define RCC_CFG3_USBXTALESS ((uint32_t)0x00000100) /*!< UCDR enable */
+
+#define RCC_CFG3_USBXTALESS_LESSMODE ((uint32_t)0x00000100) /*!< USB Crystalless mode */
+#define RCC_CFG3_USBXTALESS_MODE ((uint32_t)0x00000000) /*!< USB Crystal mode */
+
+/*!< UCDR300MSEL configuration */
+#define RCC_CFG3_UCDR300MSEL ((uint32_t)0x00000200) /*!< UCDR 300M Clock source */
+
+#define RCC_CFG3_UCDR300MSEL_PLLVCO ((uint32_t)0x00000200) /*!< PLL VCO selected as UCDR 300M Clock source */
+#define RCC_CFG3_UCDR300MSEL_OSC300M ((uint32_t)0x00000000) /*!< OSC300M selected as UCDR 300M Clock source */
+
+/*!< TRNG1MPRE configuration */
+#define RCC_CFG3_TRNG1MPRES ((uint32_t)0x0000F800) /*!< TRNG1MPRE[4:0] bits */
+#define RCC_CFG3_TRNG1MPRES_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define RCC_CFG3_TRNG1MPRES_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+#define RCC_CFG3_TRNG1MPRES_2 ((uint32_t)0x00002000) /*!< Bit 2 */
+#define RCC_CFG3_TRNG1MPRES_3 ((uint32_t)0x00004000) /*!< Bit 3 */
+#define RCC_CFG3_TRNG1MPRES_4 ((uint32_t)0x00008000) /*!< Bit 4 */
+
+#define RCC_CFG3_TRNG1MPRES_VAL2 ((uint32_t)0x00000800) /*!< TRNG 1M source clock is divided by 2 */
+#define RCC_CFG3_TRNG1MPRES_VAL3 ((uint32_t)0x00001000) /*!< TRNG 1M source clock is divided by 4 */
+#define RCC_CFG3_TRNG1MPRES_VAL4 ((uint32_t)0x00001800) /*!< TRNG 1M source clock is divided by 6 */
+#define RCC_CFG3_TRNG1MPRES_VAL5 ((uint32_t)0x00002000) /*!< TRNG 1M source clock is divided by 8 */
+#define RCC_CFG3_TRNG1MPRES_VAL6 ((uint32_t)0x00002800) /*!< TRNG 1M source clock is divided by 10 */
+#define RCC_CFG3_TRNG1MPRES_VAL7 ((uint32_t)0x00003000) /*!< TRNG 1M source clock is divided by 12 */
+#define RCC_CFG3_TRNG1MPRES_VAL8 ((uint32_t)0x00003800) /*!< TRNG 1M source clock is divided by 14 */
+#define RCC_CFG3_TRNG1MPRES_VAL9 ((uint32_t)0x00004000) /*!< TRNG 1M source clock is divided by 16 */
+#define RCC_CFG3_TRNG1MPRES_VAL10 ((uint32_t)0x00004800) /*!< TRNG 1M source clock is divided by 18 */
+#define RCC_CFG3_TRNG1MPRES_VAL11 ((uint32_t)0x00005000) /*!< TRNG 1M source clock is divided by 20 */
+#define RCC_CFG3_TRNG1MPRES_VAL12 ((uint32_t)0x00005800) /*!< TRNG 1M source clock is divided by 22 */
+#define RCC_CFG3_TRNG1MPRES_VAL13 ((uint32_t)0x00006000) /*!< TRNG 1M source clock is divided by 24 */
+#define RCC_CFG3_TRNG1MPRES_VAL14 ((uint32_t)0x00006800) /*!< TRNG 1M source clock is divided by 26 */
+#define RCC_CFG3_TRNG1MPRES_VAL15 ((uint32_t)0x00007000) /*!< TRNG 1M source clock is divided by 28 */
+#define RCC_CFG3_TRNG1MPRES_VAL16 ((uint32_t)0x00007800) /*!< TRNG 1M source clock is divided by 30 */
+#define RCC_CFG3_TRNG1MPRES_VAL17 ((uint32_t)0x00008000) /*!< TRNG 1M source clock is divided by 32 */
+#define RCC_CFG3_TRNG1MPRES_VAL18 ((uint32_t)0x00008800) /*!< TRNG 1M source clock is divided by 34 */
+#define RCC_CFG3_TRNG1MPRES_VAL19 ((uint32_t)0x00009000) /*!< TRNG 1M source clock is divided by 36 */
+#define RCC_CFG3_TRNG1MPRES_VAL20 ((uint32_t)0x00009800) /*!< TRNG 1M source clock is divided by 38 */
+#define RCC_CFG3_TRNG1MPRES_VAL21 ((uint32_t)0x0000A000) /*!< TRNG 1M source clock is divided by 40 */
+#define RCC_CFG3_TRNG1MPRES_VAL22 ((uint32_t)0x0000A800) /*!< TRNG 1M source clock is divided by 42 */
+#define RCC_CFG3_TRNG1MPRES_VAL23 ((uint32_t)0x0000B000) /*!< TRNG 1M source clock is divided by 44 */
+#define RCC_CFG3_TRNG1MPRES_VAL24 ((uint32_t)0x0000B800) /*!< TRNG 1M source clock is divided by 46 */
+#define RCC_CFG3_TRNG1MPRES_VAL25 ((uint32_t)0x0000C000) /*!< TRNG 1M source clock is divided by 48 */
+#define RCC_CFG3_TRNG1MPRES_VAL26 ((uint32_t)0x0000C800) /*!< TRNG 1M source clock is divided by 50 */
+#define RCC_CFG3_TRNG1MPRES_VAL27 ((uint32_t)0x0000D000) /*!< TRNG 1M source clock is divided by 52 */
+#define RCC_CFG3_TRNG1MPRES_VAL28 ((uint32_t)0x0000D800) /*!< TRNG 1M source clock is divided by 54 */
+#define RCC_CFG3_TRNG1MPRES_VAL29 ((uint32_t)0x0000E000) /*!< TRNG 1M source clock is divided by 56 */
+#define RCC_CFG3_TRNG1MPRES_VAL30 ((uint32_t)0x0000E800) /*!< TRNG 1M source clock is divided by 58 */
+#define RCC_CFG3_TRNG1MPRES_VAL31 ((uint32_t)0x0000F000) /*!< TRNG 1M source clock is divided by 60 */
+#define RCC_CFG3_TRNG1MPRES_VAL32 ((uint32_t)0x0000F800) /*!< TRNG 1M source clock is divided by 62 */
+
+/*!< TRNG1MSEL configuration */
+#define RCC_CFG3_TRNG1MSEL ((uint32_t)0x00020000) /*!< TRNG_1M clock source select */
+
+#define RCC_CFG3_TRNG1MSEL_HSI ((uint32_t)0x00000000) /*!< HSI clock selected as TRNG_1M input clock */
+#define RCC_CFG3_TRNG1MSEL_HSE ((uint32_t)0x00020000) /*!< HSE clock selected as TRNG_1M input clock */
+
+/*!< TRNG1MEN configuration */
+#define RCC_CFG3_TRNG1MEN ((uint32_t)0x00040000) /*!< TRNG_1M clock enable */
+
+#define RCC_CFG3_TRNG1MEN_DISABLE ((uint32_t)0x00000000) /*!< TRNG_1M clock disable */
+#define RCC_CFG3_TRNG1MEN_ENABLE ((uint32_t)0x00040000) /*!< TRNG_1M clock enable */
+
+/******************* Bit definition for RCC_RDCTRL register ******************/
+/*!< LPTIMSEL congiguration */
+#define RCC_RDCTRL_LPTIMSEL ((uint32_t)0x00000007) /*!< LPTIMSEL[2:0] bits (LPTIM clock source selection) */
+#define RCC_RDCTRL_LPTIMSEL_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_RDCTRL_LPTIMSEL_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RCC_RDCTRL_LPTIMSEL_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define RCC_RDCTRL_LPTIMSEL_APB1 ((uint32_t)0x00000000) /*!< APB1 clock used as LPTIM clock */
+#define RCC_RDCTRL_LPTIMSEL_LSI ((uint32_t)0x00000001) /*!< LSI oscillator clock used as LPTIM clock */
+#define RCC_RDCTRL_LPTIMSEL_HSI ((uint32_t)0x00000002) /*!< HSI oscillator clock used as LPTIM clock */
+#define RCC_RDCTRL_LPTIMSEL_LSE ((uint32_t)0x00000003) /*!< LSE oscillator clock used as LPTIM clock */
+#define RCC_RDCTRL_LPTIMSEL_COMP1 ((uint32_t)0x00000004) /*!< COMP1 output used as LPTIM clock */
+#define RCC_RDCTRL_LPTIMSEL_COMP2 ((uint32_t)0x00000005) /*!< COMP1 output used as LPTIM clock */
+
+/*!< LPUARTSEL congiguration */
+#define RCC_RDCTRL_LPUARTSEL ((uint32_t)0x00000018) /*!< LPUARTSEL[1:0] bits (LPUART clock source selection) */
+#define RCC_RDCTRL_LPUARTSEL_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define RCC_RDCTRL_LPUARTSEL_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+
+#define RCC_RDCTRL_LPUARTSEL_APB1 ((uint32_t)0x00000000) /*!< APB1 clock used as LPUART clock */
+#define RCC_RDCTRL_LPUARTSEL_SYSCLK ((uint32_t)0x00000008) /*!< SYSCLK used as LPUART clock */
+#define RCC_RDCTRL_LPUARTSEL_HSI ((uint32_t)0x00000010) /*!< HSI oscillator clock used as LPUART clock */
+#define RCC_RDCTRL_LPUARTSEL_LSE ((uint32_t)0x00000018) /*!< LSE oscillator clock used as LPUART clock */
+
+#define RCC_RDCTRL_LPTIMEN ((uint32_t)0x00000040) /*!< LPTIM clock enable */
+#define RCC_RDCTRL_LPUARTEN ((uint32_t)0x00000080) /*!< LPUART clock enable */
+#define RCC_RDCTRL_LPTIMRST ((uint32_t)0x00000400) /*!< LPTIM reset */
+#define RCC_RDCTRL_LPUARTRST ((uint32_t)0x00000800) /*!< LPUART reset */
+
+/******************* Bit definition for RCC_PLLHSIPRE register ******************/
+/*!< PLLHSIPRE configuration */
+#define RCC_PLLHSIPRE_PLLHSIPRE ((uint32_t)0x00000001) /*!< HSI divider for PLL entry */
+
+#define RCC_PLLHSIPRE_PLLHSIPRE_HSI ((uint32_t)0x00000000) /*!< HSI clock not divided for PLL entry */
+#define RCC_PLLHSIPRE_PLLHSIPRE_HSI_DIV2 ((uint32_t)0x00000001) /*!< HSI clock divided by 2 for PLL entry */
+
+/*!< PLLSRCDIV configuration */
+#define RCC_PLLHSIPRE_PLLSRCDIV ((uint32_t)0x00000002) /*!< PLL source clock for PLL entry */
+
+#define RCC_PLLHSIPRE_PLLSRCDIV_DISABLE ((uint32_t)0x00000000) /*!< PLL source clock not divided for PLL entry */
+#define RCC_PLLHSIPRE_PLLSRCDIV_ENABLE ((uint32_t)0x00000002) /*!< PLL source clock divided by 2 for PLL entry */
+
+/******************* Bit definition for RCC_SRAM_CTRLSTS register ******************/
+#define RCC_SRAM_CTRLSTS_ERR1EN ((uint32_t)0x00000001) /*!< SRAM1 Parity Error Interrupt Enable */
+#define RCC_SRAM_CTRLSTS_ERR1RSTEN ((uint32_t)0x00000002) /*!< SRAM1 Parity Error Reset Enable */
+#define RCC_SRAM_CTRLSTS_ERR1STS ((uint32_t)0x00000004) /*!< SRAM1 Parity Error Status */
+#define RCC_SRAM_CTRLSTS_ERR2EN ((uint32_t)0x00000008) /*!< SRAM2 Parity Error Interrupt Enable */
+#define RCC_SRAM_CTRLSTS_ERR2RSTEN ((uint32_t)0x00000010) /*!< SRAM2 Parity Error Reset Enable */
+#define RCC_SRAM_CTRLSTS_ERR2STS ((uint32_t)0x00000020) /*!< SRAM2 Parity Error Status */
+
+/******************************************************************************/
+/* */
+/* SystemTick */
+/* */
+/******************************************************************************/
+
+/***************** Bit definition for SysTick_CTRL register *****************/
+#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
+#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
+#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
+#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
+
+/***************** Bit definition for SysTick_LOAD register *****************/
+#define SysTick_LOAD_RELOAD \
+ ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/***************** Bit definition for SysTick_VAL register ******************/
+#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
+
+/***************** Bit definition for SysTick_CALIB register ****************/
+#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
+#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
+#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/* */
+/* Nested Vectored Interrupt Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for NVIC_ISER register *******************/
+#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */
+#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ICER register *******************/
+#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */
+#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ISPR register *******************/
+#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */
+#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ICPR register *******************/
+#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */
+#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_IABR register *******************/
+#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */
+#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_PRI0 register *******************/
+#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
+#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
+#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
+#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
+
+/****************** Bit definition for NVIC_PRI1 register *******************/
+#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
+#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
+#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
+#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
+
+/****************** Bit definition for NVIC_PRI2 register *******************/
+#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
+#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
+#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
+#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
+
+/****************** Bit definition for NVIC_PRI3 register *******************/
+#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
+#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
+#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
+#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
+
+/****************** Bit definition for NVIC_PRI4 register *******************/
+#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
+#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
+#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
+#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
+
+/****************** Bit definition for NVIC_PRI5 register *******************/
+#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
+#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
+#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
+#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
+
+/****************** Bit definition for NVIC_PRI6 register *******************/
+#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
+#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
+#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
+#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
+
+/****************** Bit definition for NVIC_PRI7 register *******************/
+#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
+#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
+#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
+#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
+
+/****************** Bit definition for SCB_CPUID register *******************/
+#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
+#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
+#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
+#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
+#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
+
+/******************* Bit definition for SCB_ICSR register *******************/
+#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active INTSTS number field */
+#define SCB_ICSR_RETTOBASE \
+ ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending INTSTS number field */
+#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
+#define SCB_ICSR_ISRPREEMPT \
+ ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
+#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
+#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
+#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
+#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
+
+/******************* Bit definition for SCB_VTOR register *******************/
+#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
+#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
+
+/*!<***************** Bit definition for SCB_AIRCR register *******************/
+#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
+#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
+#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
+
+#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
+#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+/* prority group configuration */
+#define SCB_AIRCR_PRIGROUP0 \
+ ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define SCB_AIRCR_PRIGROUP1 \
+ ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP2 \
+ ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP3 \
+ ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP4 \
+ ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP5 \
+ ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP6 \
+ ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP7 \
+ ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
+#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/******************* Bit definition for SCB_SCR register ********************/
+#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */
+#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */
+#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */
+
+/******************** Bit definition for SCB_CCR register *******************/
+#define SCB_CCR_NONBASETHRDENA \
+ ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define SCB_CCR_USERSETMPEND \
+ ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a \
+ Main exception */
+#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */
+#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */
+#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */
+#define SCB_CCR_STKALIGN \
+ ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/******************* Bit definition for SCB_SHPR register ********************/
+#define SCB_SHPR_PRI_N \
+ ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define SCB_SHPR_PRI_N1 \
+ ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define SCB_SHPR_PRI_N2 \
+ ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define SCB_SHPR_PRI_N3 \
+ ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/****************** Bit definition for SCB_SHCSR register *******************/
+#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
+#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
+#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
+#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
+#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
+#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
+#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
+#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
+#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
+#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
+#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
+#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
+#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
+#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
+
+/******************* Bit definition for SCB_CFSR register *******************/
+/*!< MFSR */
+#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */
+#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */
+#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */
+#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */
+#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED \
+ ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO \
+ ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/******************* Bit definition for SCB_HFSR register *******************/
+#define SCB_HFSR_VECTTBL \
+ ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
+#define SCB_HFSR_FORCED \
+ ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
+
+/******************* Bit definition for SCB_DFSR register *******************/
+#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */
+#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */
+#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */
+#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */
+#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */
+
+/******************* Bit definition for SCB_MMFAR register ******************/
+#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */
+
+/******************* Bit definition for SCB_BFAR register *******************/
+#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */
+
+/******************* Bit definition for SCB_afsr register *******************/
+#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */
+
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_INTSTS register ********************/
+#define DMA_INTSTS_GLBF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
+#define DMA_INTSTS_TXCF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
+#define DMA_INTSTS_HTXF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
+#define DMA_INTSTS_ERRF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
+#define DMA_INTSTS_GLBF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
+#define DMA_INTSTS_TXCF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
+#define DMA_INTSTS_HTXF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
+#define DMA_INTSTS_ERRF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
+#define DMA_INTSTS_GLBF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
+#define DMA_INTSTS_TXCF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
+#define DMA_INTSTS_HTXF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
+#define DMA_INTSTS_ERRF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
+#define DMA_INTSTS_GLBF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
+#define DMA_INTSTS_TXCF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
+#define DMA_INTSTS_HTXF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
+#define DMA_INTSTS_ERRF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
+#define DMA_INTSTS_GLBF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
+#define DMA_INTSTS_TXCF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
+#define DMA_INTSTS_HTXF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
+#define DMA_INTSTS_ERRF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
+#define DMA_INTSTS_GLBF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
+#define DMA_INTSTS_TXCF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
+#define DMA_INTSTS_HTXF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
+#define DMA_INTSTS_ERRF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
+#define DMA_INTSTS_GLBF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
+#define DMA_INTSTS_TXCF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
+#define DMA_INTSTS_HTXF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
+#define DMA_INTSTS_ERRF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
+#define DMA_INTSTS_GLBF8 ((uint32_t)0x10000000) /*!< Channel 7 Global interrupt flag */
+#define DMA_INTSTS_TXCF8 ((uint32_t)0x20000000) /*!< Channel 7 Transfer Complete flag */
+#define DMA_INTSTS_HTXF8 ((uint32_t)0x40000000) /*!< Channel 7 Half Transfer flag */
+#define DMA_INTSTS_ERRF8 ((uint32_t)0x80000000) /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_INTCLR register *******************/
+#define DMA_INTCLR_CGLBF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
+#define DMA_INTCLR_CTXCF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
+#define DMA_INTCLR_CERRF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
+#define DMA_INTCLR_CGLBF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
+#define DMA_INTCLR_CTXCF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
+#define DMA_INTCLR_CERRF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
+#define DMA_INTCLR_CGLBF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
+#define DMA_INTCLR_CTXCF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
+#define DMA_INTCLR_CERRF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
+#define DMA_INTCLR_CGLBF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
+#define DMA_INTCLR_CTXCF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
+#define DMA_INTCLR_CERRF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
+#define DMA_INTCLR_CGLBF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
+#define DMA_INTCLR_CTXCF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
+#define DMA_INTCLR_CERRF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
+#define DMA_INTCLR_CGLBF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
+#define DMA_INTCLR_CTXCF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
+#define DMA_INTCLR_CERRF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
+#define DMA_INTCLR_CGLBF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
+#define DMA_INTCLR_CTXCF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
+#define DMA_INTCLR_CERRF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
+#define DMA_INTCLR_CGLBF8 ((uint32_t)0x10000000) /*!< Channel 7 Global interrupt clear */
+#define DMA_INTCLR_CTXCF8 ((uint32_t)0x20000000) /*!< Channel 7 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF8 ((uint32_t)0x40000000) /*!< Channel 7 Half Transfer clear */
+#define DMA_INTCLR_CERRF8 ((uint32_t)0x80000000) /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CHCFG1 register *******************/
+#define DMA_CHCFG1_CHEN ((uint16_t)0x0001) /*!< Channel enable*/
+#define DMA_CHCFG1_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG1_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG1_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG1_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CHCFG1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CHCFG1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG1_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */
+#define DMA_CHCFG1_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG1_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/******************* Bit definition for DMA_CHCFG2 register *******************/
+#define DMA_CHCFG2_CHEN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CHCFG2_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG2_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG2_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG2_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CHCFG2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CHCFG2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG2_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CHCFG2_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG2_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/******************* Bit definition for DMA_CHCFG3 register *******************/
+#define DMA_CHCFG3_CHEN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CHCFG3_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG3_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG3_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG3_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CHCFG3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CHCFG3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG3_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CHCFG3_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG3_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/*!<****************** Bit definition for DMA_CHCFG4 register *******************/
+#define DMA_CHCFG4_CHEN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CHCFG4_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG4_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG4_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG4_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CHCFG4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CHCFG4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG4_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CHCFG4_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG4_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CHCFG5 register *******************/
+#define DMA_CHCFG5_CHEN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CHCFG5_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG5_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG5_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG5_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CHCFG5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CHCFG5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG5_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CHCFG5_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG5_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
+
+/******************* Bit definition for DMA_CHCFG6 register *******************/
+#define DMA_CHCFG6_CHEN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CHCFG6_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG6_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG6_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG6_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CHCFG6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CHCFG6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG6_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CHCFG6_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG6_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/******************* Bit definition for DMA_CHCFG7 register *******************/
+#define DMA_CHCFG7_CHEN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CHCFG7_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG7_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG7_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG7_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG7_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CHCFG7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CHCFG7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG7_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CHCFG7_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG7_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
+
+/******************* Bit definition for DMA_CHCFG8 register *******************/
+#define DMA_CHCFG8_CHEN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CHCFG8_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG8_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG8_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG8_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG8_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG8_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG8_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG8_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG8_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CHCFG8_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CHCFG8_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG8_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG8_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG8_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CHCFG8_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG8_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG8_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
+
+/****************** Bit definition for DMA_TXNUM1 register ******************/
+#define DMA_TXNUM1_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_TXNUM2 register ******************/
+#define DMA_TXNUM2_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_TXNUM3 register ******************/
+#define DMA_TXNUM3_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_TXNUM4 register ******************/
+#define DMA_TXNUM4_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_TXNUM5 register ******************/
+#define DMA_TXNUM5_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_TXNUM6 register ******************/
+#define DMA_TXNUM6_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_TXNUM7 register ******************/
+#define DMA_TXNUM7_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_TXNUM8 register ******************/
+#define DMA_TXNUM8_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_PADDR1 register *******************/
+#define DMA_PADDR1_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_PADDR2 register *******************/
+#define DMA_PADDR2_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_PADDR3 register *******************/
+#define DMA_PADDR3_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_PADDR4 register *******************/
+#define DMA_PADDR4_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_PADDR5 register *******************/
+#define DMA_PADDR5_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_PADDR6 register *******************/
+#define DMA_PADDR6_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_PADDR7 register *******************/
+#define DMA_PADDR7_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_PADDR8 register *******************/
+#define DMA_PADDR8_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_MADDR1 register *******************/
+#define DMA_MADDR1_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_MADDR2 register *******************/
+#define DMA_MADDR2_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_MADDR3 register *******************/
+#define DMA_MADDR3_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_MADDR4 register *******************/
+#define DMA_MADDR4_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_MADDR5 register *******************/
+#define DMA_MADDR5_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_MADDR6 register *******************/
+#define DMA_MADDR6_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_MADDR7 register *******************/
+#define DMA_MADDR7_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_MADDR8 register *******************/
+#define DMA_MADDR8_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for ADC_STS register ********************/
+#define ADC_STS_AWDG ((uint8_t)0x01) /*!< Analog watchdog flag */
+#define ADC_STS_ENDC ((uint8_t)0x02) /*!< End of conversion */
+#define ADC_STS_JENDC ((uint8_t)0x04) /*!< Injected channel end of conversion */
+#define ADC_STS_JSTR ((uint8_t)0x08) /*!< Injected channel Start flag */
+#define ADC_STS_STR ((uint8_t)0x10) /*!< Regular channel Start flag */
+#define ADC_STS_ENDCA ((uint8_t)0x20) /*!< Regular channel any end flag */
+#define ADC_STS_JENDCA ((uint8_t)0x40) /*!< Injected channel any end flag */
+
+
+/******************* Bit definition for ADC_CTRL1 register ********************/
+#define ADC_CTRL1_AWDGCH ((uint32_t)0x0000001F) /*!< AWDG_CH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CTRL1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_CTRL1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_CTRL1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_CTRL1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_CTRL1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_CTRL1_ENDCIEN ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */
+#define ADC_CTRL1_AWDGIEN ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */
+#define ADC_CTRL1_JENDCIEN ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */
+#define ADC_CTRL1_SCANMD ((uint32_t)0x00000100) /*!< Scan mode */
+#define ADC_CTRL1_AWDGSGLEN ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */
+#define ADC_CTRL1_AUTOJC ((uint32_t)0x00000400) /*!< Automatic injected group conversion */
+#define ADC_CTRL1_DREGCH ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */
+#define ADC_CTRL1_DJCH ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */
+
+#define ADC_CTRL1_DCTU ((uint32_t)0x0000E000) /*!< DISC_NUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CTRL1_DCTU_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define ADC_CTRL1_DCTU_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define ADC_CTRL1_DCTU_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+
+#define ADC_CTRL1_AWDGEJCH ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */
+#define ADC_CTRL1_AWDGERCH ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
+
+/******************* Bit definition for ADC_CTRL2 register ********************/
+#define ADC_CTRL2_ON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */
+#define ADC_CTRL2_CTU ((uint32_t)0x00000002) /*!< Continuous Conversion */
+#define ADC_CTRL2_ENCAL ((uint32_t)0x00000004) /*!< A/D Calibration */
+#define ADC_CTRL2_ENDMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */
+#define ADC_CTRL2_ALIG ((uint32_t)0x00000800) /*!< Data Alignment */
+
+#define ADC_CTRL2_EXTJSEL \
+ ((uint32_t)0x00007000) /*!< INJ_EXT_SEL[2:0] bits (External event select for injected group) */
+#define ADC_CTRL2_EXTJSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_CTRL2_EXTJSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_CTRL2_EXTJSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_CTRL2_EXTJTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */
+
+#define ADC_CTRL2_EXTRSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CTRL2_EXTRSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define ADC_CTRL2_EXTRSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define ADC_CTRL2_EXTRSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+
+#define ADC_CTRL2_EXTRTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */
+#define ADC_CTRL2_SWSTRJCH ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */
+#define ADC_CTRL2_SWSTRRCH ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */
+#define ADC_CTRL2_TEMPEN ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */
+
+/****************** Bit definition for ADC_SAMPT1 register *******************/
+#define ADC_SAMPT1_SAMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SAMPT1_SAMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define ADC_SAMPT1_SAMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SAMPT1_SAMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define ADC_SAMPT1_SAMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SAMPT1_SAMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+
+#define ADC_SAMPT1_SAMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SAMPT1_SAMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+
+#define ADC_SAMPT1_SAMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SAMPT1_SAMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_SAMPT1_SAMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SAMPT1_SAMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+
+#define ADC_SAMPT1_SAMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SAMPT1_SAMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+
+#define ADC_SAMPT1_SAMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SAMPT1_SAMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+
+/****************** Bit definition for ADC_SAMPT2 register *******************/
+#define ADC_SAMPT2_SAMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SAMPT2_SAMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SAMPT2_SAMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SAMPT2_SAMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SAMPT2_SAMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SAMPT2_SAMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SAMPT2_SAMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SAMPT2_SAMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SAMPT2_SAMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SAMPT2_SAMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SAMPT2_SAMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */
+
+/****************** Bit definition for ADC_JOFFSET1 register *******************/
+#define ADC_JOFFSET1_OFFSETJCH1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFFSET2 register *******************/
+#define ADC_JOFFSET2_OFFSETJCH2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFFSET3 register *******************/
+#define ADC_JOFFSET3_OFFSETJCH3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFFSET4 register *******************/
+#define ADC_JOFFSET4_OFFSETJCH4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_WDGHIGH register ********************/
+#define ADC_WDGHIGH_HTH ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_WDGLOW register ********************/
+#define ADC_WDGLOW_LTH ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_RSEQ1 register *******************/
+#define ADC_RSEQ1_SEQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_RSEQ1_SEQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_RSEQ1_SEQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_RSEQ1_SEQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_RSEQ1_SEQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_RSEQ1_SEQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_RSEQ1_SEQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_RSEQ1_SEQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_RSEQ1_SEQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_RSEQ1_SEQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_RSEQ1_SEQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_RSEQ1_SEQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_RSEQ1_SEQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_RSEQ1_SEQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_RSEQ1_SEQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_RSEQ1_SEQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_RSEQ1_SEQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_RSEQ1_SEQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_RSEQ1_SEQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_RSEQ1_SEQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_RSEQ1_SEQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_RSEQ1_SEQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_RSEQ1_SEQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_RSEQ1_SEQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_RSEQ1_LEN ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */
+#define ADC_RSEQ1_LEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_RSEQ1_LEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_RSEQ1_LEN_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_RSEQ1_LEN_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+/******************* Bit definition for ADC_RSEQ2 register *******************/
+#define ADC_RSEQ2_SEQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_RSEQ2_SEQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_RSEQ2_SEQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_RSEQ2_SEQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_RSEQ2_SEQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_RSEQ2_SEQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_RSEQ2_SEQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_RSEQ2_SEQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_RSEQ2_SEQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_RSEQ2_SEQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_RSEQ2_SEQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_RSEQ2_SEQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_RSEQ2_SEQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_RSEQ2_SEQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_RSEQ2_SEQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_RSEQ2_SEQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_RSEQ2_SEQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_RSEQ2_SEQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_RSEQ2_SEQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_RSEQ2_SEQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_RSEQ2_SEQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_RSEQ2_SEQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_RSEQ2_SEQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_RSEQ2_SEQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_RSEQ2_SEQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_RSEQ2_SEQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_RSEQ2_SEQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_RSEQ2_SEQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_RSEQ2_SEQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+#define ADC_RSEQ2_SEQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */
+
+#define ADC_RSEQ2_SEQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_RSEQ2_SEQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */
+#define ADC_RSEQ2_SEQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define ADC_RSEQ2_SEQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */
+#define ADC_RSEQ2_SEQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */
+#define ADC_RSEQ2_SEQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */
+
+/******************* Bit definition for ADC_RSEQ3 register *******************/
+#define ADC_RSEQ3_SEQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_RSEQ3_SEQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_RSEQ3_SEQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_RSEQ3_SEQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_RSEQ3_SEQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_RSEQ3_SEQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_RSEQ3_SEQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_RSEQ3_SEQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_RSEQ3_SEQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_RSEQ3_SEQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_RSEQ3_SEQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_RSEQ3_SEQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_RSEQ3_SEQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_RSEQ3_SEQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_RSEQ3_SEQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_RSEQ3_SEQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_RSEQ3_SEQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_RSEQ3_SEQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_RSEQ3_SEQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_RSEQ3_SEQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_RSEQ3_SEQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_RSEQ3_SEQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_RSEQ3_SEQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_RSEQ3_SEQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_RSEQ3_SEQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_RSEQ3_SEQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_RSEQ3_SEQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_RSEQ3_SEQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_RSEQ3_SEQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+#define ADC_RSEQ3_SEQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */
+
+#define ADC_RSEQ3_SEQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_RSEQ3_SEQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */
+#define ADC_RSEQ3_SEQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define ADC_RSEQ3_SEQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */
+#define ADC_RSEQ3_SEQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */
+#define ADC_RSEQ3_SEQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */
+
+/******************* Bit definition for ADC_JSEQ register *******************/
+#define ADC_JSEQ_JSEQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSEQ_JSEQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_JSEQ_JSEQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_JSEQ_JSEQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_JSEQ_JSEQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_JSEQ_JSEQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_JSEQ_JSEQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSEQ_JSEQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_JSEQ_JSEQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_JSEQ_JSEQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_JSEQ_JSEQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_JSEQ_JSEQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_JSEQ_JSEQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSEQ_JSEQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_JSEQ_JSEQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_JSEQ_JSEQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_JSEQ_JSEQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_JSEQ_JSEQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_JSEQ_JSEQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSEQ_JSEQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_JSEQ_JSEQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_JSEQ_JSEQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_JSEQ_JSEQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_JSEQ_JSEQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_JSEQ_JLEN ((uint32_t)0x00300000) /*!< INJ_LEN[1:0] bits (Injected Sequence length) */
+#define ADC_JSEQ_JLEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_JSEQ_JLEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+/******************* Bit definition for ADC_JDAT1 register *******************/
+#define ADC_JDAT1_JDAT ((uint16_t)0xFFFF) /*!< Injected data */
+
+/******************* Bit definition for ADC_JDAT2 register *******************/
+#define ADC_JDAT2_JDAT ((uint16_t)0xFFFF) /*!< Injected data */
+
+/******************* Bit definition for ADC_JDAT3 register *******************/
+#define ADC_JDAT3_JDAT ((uint16_t)0xFFFF) /*!< Injected data */
+
+/******************* Bit definition for ADC_JDAT4 register *******************/
+#define ADC_JDAT4_JDAT ((uint16_t)0xFFFF) /*!< Injected data */
+
+/******************** Bit definition for ADC_DAT register ********************/
+#define ADC_DAT_DAT ((uint32_t)0x0000FFFF) /*!< Regular data */
+
+///******************** Bit definition for ADC_DIFSEL register ********************/
+//#define ADC_DIFSEL_DIFSEL ((uint32_t)0x000FFFFE) /*!< Differential data */
+//#define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000002) /*!< Differential_1 data */
+//#define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000004) /*!< Differential_2 data */
+//#define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000008) /*!< Differential_3 data */
+//#define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000010) /*!< Differential_4 data */
+//#define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000020) /*!< Differential_5 data */
+//#define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000040) /*!< Differential_6 data */
+//#define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000080) /*!< Differential_7 data */
+//#define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000100) /*!< Differential_8 data */
+//#define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000200) /*!< Differential_9 data */
+//#define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000400) /*!< Differential_10 data */
+//#define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000800) /*!< Differential_11 data */
+//#define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00001000) /*!< Differential_12 data */
+//#define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00002000) /*!< Differential_13 data */
+//#define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00004000) /*!< Differential_14 data */
+//#define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00008000) /*!< Differential_15 data */
+//#define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00010000) /*!< Differential_16 data */
+//#define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00020000) /*!< Differential_17 data */
+//#define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00040000) /*!< Differential_18 data */
+//#define ADC_DIFSEL_DIFSEL_18 ((uint32_t)0x00080000) /*!< Differential_19 data */
+
+///******************** Bit definition for ADC_CALFACT register ********************/
+//#define ADC_CALFACT_CALFACTS ((uint32_t)0x0000007F) /*!< Calibration factors in single data */
+//#define ADC_CALFACT_CALFACTS_0 ((uint32_t)0x00000001) /*!< Calibration factors_0 in single data */
+//#define ADC_CALFACT_CALFACTS_1 ((uint32_t)0x00000002) /*!< Calibration factors_1 in single data */
+//#define ADC_CALFACT_CALFACTS_2 ((uint32_t)0x00000004) /*!< Calibration factors_2 in single data */
+//#define ADC_CALFACT_CALFACTS_3 ((uint32_t)0x00000008) /*!< Calibration factors_3 in single data */
+//#define ADC_CALFACT_CALFACTS_4 ((uint32_t)0x00000010) /*!< Calibration factors_4 in single data */
+//#define ADC_CALFACT_CALFACTS_5 ((uint32_t)0x00000020) /*!< Calibration factors_5 in single data */
+//#define ADC_CALFACT_CALFACTS_6 ((uint32_t)0x00000040) /*!< Calibration factors_6 in single data */
+
+//#define ADC_CALFACT_CALFACTD ((uint32_t)0x007F0000) /*!< Calibration factors in differential data */
+//#define ADC_CALFACT_CALFACTD_0 ((uint32_t)0x00010000) /*!< Calibration factors_0 in differential data */
+//#define ADC_CALFACT_CALFACTD_1 ((uint32_t)0x00020000) /*!< Calibration factors_1 in differential data */
+//#define ADC_CALFACT_CALFACTD_2 ((uint32_t)0x00040000) /*!< Calibration factors_2 in differential data */
+//#define ADC_CALFACT_CALFACTD_3 ((uint32_t)0x00080000) /*!< Calibration factors_3 in differential data */
+//#define ADC_CALFACT_CALFACTD_4 ((uint32_t)0x00100000) /*!< Calibration factors_4 in differential data */
+//#define ADC_CALFACT_CALFACTD_5 ((uint32_t)0x00200000) /*!< Calibration factors_5 in differential data */
+//#define ADC_CALFACT_CALFACTD_6 ((uint32_t)0x00400000) /*!< Calibration factors_6 in differential data */
+
+///******************** Bit definition for ADC_CTRL3 register ********************/
+//#define ADC_CTRL3_RES ((uint32_t)0x00000003) /*!< Resolution data */
+//#define ADC_CTRL3_RES_0 ((uint32_t)0x00000001) /*!< Resolution_0 data */
+//#define ADC_CTRL3_RES_1 ((uint32_t)0x00000002) /*!< Resolution_1 data */
+
+//#define ADC_CTRL3_CALDIF ((uint32_t)0x00000004) /*!< Differential mode for calibration enable */
+//#define ADC_CTRL3_CALALD ((uint32_t)0x00000008) /*!< Differential mode for calibration auto reload enable */
+//#define ADC_CTRL3_CKMOD ((uint32_t)0x00000010) /*!< Clock mode selection */
+//#define ADC_CTRL3_RDY ((uint32_t)0x00000020) /*!< Ready flag */
+//#define ADC_CTRL3_PDRDY ((uint32_t)0x00000040) /*!< Powerdown ready flag */
+//#define ADC_CTRL3_BPCAL ((uint32_t)0x00000080) /*!< Bypass calibration */
+//#define ADC_CTRL3_ENDCAIEN ((uint32_t)0x00000100) /*!< Interrupt enable for any regular channels */
+//#define ADC_CTRL3_JENDCAIEN ((uint32_t)0x00000200) /*!< Interrupt enable for any injected channels */
+//#define ADC_CTRL3_DPWMOD ((uint32_t)0x00000400) /*!< Deep Power Mode */
+//#define ADC_CTRL3_VBATMEN ((uint32_t)0x00000800) /*!< Vbat monitor enable */
+
+///******************** Bit definition for ADC_SAMPT3 register ********************/
+//#define ADC_SAMPT3_SAMP18 ((uint32_t)0x00000007) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
+//#define ADC_SAMPT3_SAMP18_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+//#define ADC_SAMPT3_SAMP18_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+//#define ADC_SAMPT3_SAMP18_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+//#define ADC_SAMPT3_SAMPSEL ((uint32_t)0x00000008) /*!< Sample time selection */
+
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DAC_CTRL register ********************/
+#define DAC_CTRL_CHEN ((uint32_t)0x00000001) /*!< DAC channel enable */
+#define DAC_CTRL_BEN ((uint32_t)0x00000002) /*!< DAC channel output buffer enable */
+#define DAC_CTRL_TEN ((uint32_t)0x00000004) /*!< DAC channel Trigger enable */
+
+#define DAC_CTRL_TSEL ((uint32_t)0x00000038) /*!< TSEL[2:0] (DAC channel Trigger selection) */
+#define DAC_CTRL_TSEL_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define DAC_CTRL_TSEL_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define DAC_CTRL_TSEL_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define DAC_CTRL_WEN ((uint32_t)0x000000C0) /*!< WEN[1:0] (DAC channel noise/triangle wave generation enable) */
+#define DAC_CTRL_WEN_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define DAC_CTRL_WEN_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define DAC_CTRL_MASEL ((uint32_t)0x00000F00) /*!< MASEL [3:0] (DAC channel Mask/Amplitude selector) */
+#define DAC_CTRL_MASEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DAC_CTRL_MASEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define DAC_CTRL_MASEL_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define DAC_CTRL_MASEL_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define DAC_CTRL_DMAEN ((uint32_t)0x00001000) /*!< DAC channel DMA enable */
+
+
+
+/***************** Bit definition for DAC_SOTTR register ******************/
+#define DAC_SOTTR_TREN ((uint8_t)0x01) /*!< DAC channel software trigger */
+
+
+/***************** Bit definition for DAC_DR12CH register ******************/
+#define DAC_DR12CH_DACCHD ((uint16_t)0x0FFF) /*!< DAC channel 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DL12CH register ******************/
+#define DAC_DL12CH_DACCHD ((uint16_t)0xFFF0) /*!< DAC channel 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DR8CH register ******************/
+#define DAC_DR8CH_DACCHD ((uint8_t)0xFF) /*!< DAC channel 8-bit Right aligned data */
+
+
+
+
+/******************* Bit definition for DAC_DATO register *******************/
+#define DAC_DATO_DACCHDO ((uint16_t)0x0FFF) /*!< DAC channel data output */
+
+
+
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for TIM_CTRL1 register ********************/
+#define TIM_CTRL1_CNTEN ((uint32_t)0x00000001) /*!< Counter enable */
+#define TIM_CTRL1_UPDIS ((uint32_t)0x00000002) /*!< Update disable */
+#define TIM_CTRL1_UPRS ((uint32_t)0x00000004) /*!< Update request source */
+#define TIM_CTRL1_ONEPM ((uint32_t)0x00000008) /*!< One pulse mode */
+#define TIM_CTRL1_DIR ((uint32_t)0x00000010) /*!< Direction */
+
+#define TIM_CTRL1_CAMSEL ((uint32_t)0x00000060) /*!< CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CTRL1_CAMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define TIM_CTRL1_CAMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+
+#define TIM_CTRL1_ARPEN ((uint32_t)0x00000080) /*!< Auto-reload preload enable */
+
+#define TIM_CTRL1_CLKD ((uint32_t)0x00000300) /*!< CKD[1:0] bits (clock division) */
+#define TIM_CTRL1_CLKD_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define TIM_CTRL1_CLKD_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define TIM_CTRL1_IOMBKPEN ((uint32_t)0x00000400) /*!< Break_in selection from IOM/COMP */
+#define TIM_CTRL1_C1SEL ((uint32_t)0x00000800) /*!< Channel 1 selection from IOM/COMP */
+#define TIM_CTRL1_C2SEL ((uint32_t)0x00001000) /*!< Channel 2 selection from IOM/COMP */
+#define TIM_CTRL1_C3SEL ((uint32_t)0x00002000) /*!< Channel 3 selection from IOM/COMP */
+#define TIM_CTRL1_C4SEL ((uint32_t)0x00004000) /*!< Channel 4 selection from IOM/COMP */
+#define TIM_CTRL1_CLRSEL ((uint32_t)0x00008000) /*!< OCxRef selection from ETR/COMP */
+
+#define TIM_CTRL1_LBKPEN ((uint32_t)0x00010000) /*!< LOCKUP as bkp Enable*/
+#define TIM_CTRL1_PBKPEN ((uint32_t)0x00020000) /*!< PVD as bkp Enable */
+
+/******************* Bit definition for TIM_CTRL2 register ********************/
+#define TIM_CTRL2_CCPCTL ((uint32_t)0x00000001) /*!< Capture/Compare Preloaded Control */
+#define TIM_CTRL2_CCUSEL ((uint32_t)0x00000004) /*!< Capture/Compare Control Update Selection */
+#define TIM_CTRL2_CCDSEL ((uint32_t)0x00000008) /*!< Capture/Compare DMA Selection */
+
+#define TIM_CTRL2_MMSEL ((uint32_t)0x00000070) /*!< MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CTRL2_MMSEL_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define TIM_CTRL2_MMSEL_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define TIM_CTRL2_MMSEL_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+
+#define TIM_CTRL2_TI1SEL ((uint32_t)0x00000080) /*!< TI1 Selection */
+#define TIM_CTRL2_OI1 ((uint32_t)0x00000100) /*!< Output Idle state 1 (OC1 output) */
+#define TIM_CTRL2_OI1N ((uint32_t)0x00000200) /*!< Output Idle state 1 (OC1N output) */
+#define TIM_CTRL2_OI2 ((uint32_t)0x00000400) /*!< Output Idle state 2 (OC2 output) */
+#define TIM_CTRL2_OI2N ((uint32_t)0x00000800) /*!< Output Idle state 2 (OC2N output) */
+#define TIM_CTRL2_OI3 ((uint32_t)0x00001000) /*!< Output Idle state 3 (OC3 output) */
+#define TIM_CTRL2_OI3N ((uint32_t)0x00002000) /*!< Output Idle state 3 (OC3N output) */
+#define TIM_CTRL2_OI4 ((uint32_t)0x00004000) /*!< Output Idle state 4 (OC4 output) */
+
+#define TIM_CTRL2_OI5 ((uint32_t)0x00010000) /*!< Output Idle state 5 (OC5 output) */
+#define TIM_CTRL2_OI6 ((uint32_t)0x00040000) /*!< Output Idle state 6 (OC6 output) */
+
+/******************* Bit definition for TIM_SMCTRL register *******************/
+#define TIM_SMCTRL_SMSEL ((uint16_t)0x0007) /*!< SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCTRL_SMSEL_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_SMCTRL_SMSEL_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define TIM_SMCTRL_SMSEL_2 ((uint16_t)0x0004) /*!< Bit 2 */
+
+#define TIM_SMCTRL_TSEL ((uint16_t)0x0070) /*!< TS[2:0] bits (Trigger selection) */
+#define TIM_SMCTRL_TSEL_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_SMCTRL_TSEL_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_SMCTRL_TSEL_2 ((uint16_t)0x0040) /*!< Bit 2 */
+
+#define TIM_SMCTRL_MSMD ((uint16_t)0x0080) /*!< Master/slave mode */
+
+#define TIM_SMCTRL_EXTF ((uint16_t)0x0F00) /*!< ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCTRL_EXTF_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_SMCTRL_EXTF_1 ((uint16_t)0x0200) /*!< Bit 1 */
+#define TIM_SMCTRL_EXTF_2 ((uint16_t)0x0400) /*!< Bit 2 */
+#define TIM_SMCTRL_EXTF_3 ((uint16_t)0x0800) /*!< Bit 3 */
+
+#define TIM_SMCTRL_EXTPS ((uint16_t)0x3000) /*!< ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCTRL_EXTPS_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_SMCTRL_EXTPS_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define TIM_SMCTRL_EXCEN ((uint16_t)0x4000) /*!< External clock enable */
+#define TIM_SMCTRL_EXTP ((uint16_t)0x8000) /*!< External trigger polarity */
+
+/******************* Bit definition for TIM_DINTEN register *******************/
+#define TIM_DINTEN_UIEN ((uint16_t)0x0001) /*!< Update interrupt enable */
+#define TIM_DINTEN_CC1IEN ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt enable */
+#define TIM_DINTEN_CC2IEN ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt enable */
+#define TIM_DINTEN_CC3IEN ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt enable */
+#define TIM_DINTEN_CC4IEN ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt enable */
+#define TIM_DINTEN_COMIEN ((uint16_t)0x0020) /*!< COM interrupt enable */
+#define TIM_DINTEN_TIEN ((uint16_t)0x0040) /*!< Trigger interrupt enable */
+#define TIM_DINTEN_BIEN ((uint16_t)0x0080) /*!< Break interrupt enable */
+#define TIM_DINTEN_UDEN ((uint16_t)0x0100) /*!< Update DMA request enable */
+#define TIM_DINTEN_CC1DEN ((uint16_t)0x0200) /*!< Capture/Compare 1 DMA request enable */
+#define TIM_DINTEN_CC2DEN ((uint16_t)0x0400) /*!< Capture/Compare 2 DMA request enable */
+#define TIM_DINTEN_CC3DEN ((uint16_t)0x0800) /*!< Capture/Compare 3 DMA request enable */
+#define TIM_DINTEN_CC4DEN ((uint16_t)0x1000) /*!< Capture/Compare 4 DMA request enable */
+#define TIM_DINTEN_COMDEN ((uint16_t)0x2000) /*!< COM DMA request enable */
+#define TIM_DINTEN_TDEN ((uint16_t)0x4000) /*!< Trigger DMA request enable */
+
+/******************** Bit definition for TIM_STS register ********************/
+#define TIM_STS_UDITF ((uint32_t)0x00000001) /*!< Update interrupt Flag */
+#define TIM_STS_CC1ITF ((uint32_t)0x00000002) /*!< Capture/Compare 1 interrupt Flag */
+#define TIM_STS_CC2ITF ((uint32_t)0x00000004) /*!< Capture/Compare 2 interrupt Flag */
+#define TIM_STS_CC3ITF ((uint32_t)0x00000008) /*!< Capture/Compare 3 interrupt Flag */
+#define TIM_STS_CC4ITF ((uint32_t)0x00000010) /*!< Capture/Compare 4 interrupt Flag */
+#define TIM_STS_COMITF ((uint32_t)0x00000020) /*!< COM interrupt Flag */
+#define TIM_STS_TITF ((uint32_t)0x00000040) /*!< Trigger interrupt Flag */
+#define TIM_STS_BITF ((uint32_t)0x00000080) /*!< Break interrupt Flag */
+#define TIM_STS_CC1OCF ((uint32_t)0x00000200) /*!< Capture/Compare 1 Overcapture Flag */
+#define TIM_STS_CC2OCF ((uint32_t)0x00000400) /*!< Capture/Compare 2 Overcapture Flag */
+#define TIM_STS_CC3OCF ((uint32_t)0x00000800) /*!< Capture/Compare 3 Overcapture Flag */
+#define TIM_STS_CC4OCF ((uint32_t)0x00001000) /*!< Capture/Compare 4 Overcapture Flag */
+
+#define TIM_STS_CC5ITF ((uint32_t)0x00010000) /*!< Capture/Compare 5 interrupt Flag */
+#define TIM_STS_CC6ITF ((uint32_t)0x00020000) /*!< Capture/Compare 6 interrupt Flag */
+
+/******************* Bit definition for TIM_EVTGEN register ********************/
+#define TIM_EVTGEN_UDGN ((uint8_t)0x01) /*!< Update Generation */
+#define TIM_EVTGEN_CC1GN ((uint8_t)0x02) /*!< Capture/Compare 1 Generation */
+#define TIM_EVTGEN_CC2GN ((uint8_t)0x04) /*!< Capture/Compare 2 Generation */
+#define TIM_EVTGEN_CC3GN ((uint8_t)0x08) /*!< Capture/Compare 3 Generation */
+#define TIM_EVTGEN_CC4GN ((uint8_t)0x10) /*!< Capture/Compare 4 Generation */
+#define TIM_EVTGEN_CCUDGN ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation */
+#define TIM_EVTGEN_TGN ((uint8_t)0x40) /*!< Trigger Generation */
+#define TIM_EVTGEN_BGN ((uint8_t)0x80) /*!< Break Generation */
+
+/****************** Bit definition for TIM_CCMOD1 register *******************/
+#define TIM_CCMOD1_CC1SEL ((uint16_t)0x0003) /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMOD1_CC1SEL_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_CCMOD1_CC1SEL_1 ((uint16_t)0x0002) /*!< Bit 1 */
+
+#define TIM_CCMOD1_OC1FEN ((uint16_t)0x0004) /*!< Output Compare 1 Fast enable */
+#define TIM_CCMOD1_OC1PEN ((uint16_t)0x0008) /*!< Output Compare 1 Preload enable */
+
+#define TIM_CCMOD1_OC1M ((uint16_t)0x0070) /*!< OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMOD1_OC1M_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMOD1_OC1M_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMOD1_OC1M_2 ((uint16_t)0x0040) /*!< Bit 2 */
+
+#define TIM_CCMOD1_OC1CEN ((uint16_t)0x0080) /*!< Output Compare 1Clear Enable */
+
+#define TIM_CCMOD1_CC2SEL ((uint16_t)0x0300) /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMOD1_CC2SEL_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_CCMOD1_CC2SEL_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define TIM_CCMOD1_OC2FEN ((uint16_t)0x0400) /*!< Output Compare 2 Fast enable */
+#define TIM_CCMOD1_OC2PEN ((uint16_t)0x0800) /*!< Output Compare 2 Preload enable */
+
+#define TIM_CCMOD1_OC2M ((uint16_t)0x7000) /*!< OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMOD1_OC2M_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMOD1_OC2M_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMOD1_OC2M_2 ((uint16_t)0x4000) /*!< Bit 2 */
+
+#define TIM_CCMOD1_OC2CEN ((uint16_t)0x8000) /*!< Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMOD1_IC1PSC ((uint16_t)0x000C) /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMOD1_IC1PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */
+#define TIM_CCMOD1_IC1PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */
+
+#define TIM_CCMOD1_IC1F ((uint16_t)0x00F0) /*!< IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMOD1_IC1F_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMOD1_IC1F_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMOD1_IC1F_2 ((uint16_t)0x0040) /*!< Bit 2 */
+#define TIM_CCMOD1_IC1F_3 ((uint16_t)0x0080) /*!< Bit 3 */
+
+#define TIM_CCMOD1_IC2PSC ((uint16_t)0x0C00) /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMOD1_IC2PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define TIM_CCMOD1_IC2PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define TIM_CCMOD1_IC2F ((uint16_t)0xF000) /*!< IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMOD1_IC2F_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMOD1_IC2F_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMOD1_IC2F_2 ((uint16_t)0x4000) /*!< Bit 2 */
+#define TIM_CCMOD1_IC2F_3 ((uint16_t)0x8000) /*!< Bit 3 */
+
+/****************** Bit definition for TIM_CCMOD2 register *******************/
+#define TIM_CCMOD2_CC3SEL ((uint16_t)0x0003) /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMOD2_CC3SEL_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_CCMOD2_CC3SEL_1 ((uint16_t)0x0002) /*!< Bit 1 */
+
+#define TIM_CCMOD2_OC3FEN ((uint16_t)0x0004) /*!< Output Compare 3 Fast enable */
+#define TIM_CCMOD2_OC3PEN ((uint16_t)0x0008) /*!< Output Compare 3 Preload enable */
+
+#define TIM_CCMOD2_OC3MD ((uint16_t)0x0070) /*!< OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMOD2_OC3MD_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMOD2_OC3MD_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMOD2_OC3MD_2 ((uint16_t)0x0040) /*!< Bit 2 */
+
+#define TIM_CCMOD2_OC3CEN ((uint16_t)0x0080) /*!< Output Compare 3 Clear Enable */
+
+#define TIM_CCMOD2_CC4SEL ((uint16_t)0x0300) /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMOD2_CC4SEL_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_CCMOD2_CC4SEL_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define TIM_CCMOD2_OC4FEN ((uint16_t)0x0400) /*!< Output Compare 4 Fast enable */
+#define TIM_CCMOD2_OC4PEN ((uint16_t)0x0800) /*!< Output Compare 4 Preload enable */
+
+#define TIM_CCMOD2_OC4MD ((uint16_t)0x7000) /*!< OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMOD2_OC4MD_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMOD2_OC4MD_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMOD2_OC4MD_2 ((uint16_t)0x4000) /*!< Bit 2 */
+
+#define TIM_CCMOD2_OC4CEN ((uint16_t)0x8000) /*!< Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMOD2_IC3PSC ((uint16_t)0x000C) /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMOD2_IC3PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */
+#define TIM_CCMOD2_IC3PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */
+
+#define TIM_CCMOD2_IC3F ((uint16_t)0x00F0) /*!< IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMOD2_IC3F_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMOD2_IC3F_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMOD2_IC3F_2 ((uint16_t)0x0040) /*!< Bit 2 */
+#define TIM_CCMOD2_IC3F_3 ((uint16_t)0x0080) /*!< Bit 3 */
+
+#define TIM_CCMOD2_IC4PSC ((uint16_t)0x0C00) /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMOD2_IC4PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define TIM_CCMOD2_IC4PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define TIM_CCMOD2_IC4F ((uint16_t)0xF000) /*!< IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMOD2_IC4F_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMOD2_IC4F_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMOD2_IC4F_2 ((uint16_t)0x4000) /*!< Bit 2 */
+#define TIM_CCMOD2_IC4F_3 ((uint16_t)0x8000) /*!< Bit 3 */
+
+/****************** Bit definition for TIM_CCMOD3 register *******************/
+#define TIM_CCMOD3_OC5FEN ((uint16_t)0x0004) /*!< Output Compare 5 Fast enable */
+#define TIM_CCMOD3_OC5PEN ((uint16_t)0x0008) /*!< Output Compare 5 Preload enable */
+
+#define TIM_CCMOD3_OC5MD ((uint16_t)0x0070) /*!< OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMOD3_OC5MD_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMOD3_OC5MD_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMOD3_OC5MD_2 ((uint16_t)0x0040) /*!< Bit 2 */
+
+#define TIM_CCMOD3_OC5CEN ((uint16_t)0x0080) /*!< Output Compare 5Clear Enable */
+
+#define TIM_CCMOD3_OC6FEN ((uint16_t)0x0400) /*!< Output Compare 6 Fast enable */
+#define TIM_CCMOD3_OC6PEN ((uint16_t)0x0800) /*!< Output Compare 6 Preload enable */
+
+#define TIM_CCMOD3_OC6MD ((uint16_t)0x7000) /*!< OC6M[2:0] bits (Output Compare 6 Mode) */
+#define TIM_CCMOD3_OC6MD_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMOD3_OC6MD_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMOD3_OC6MD_2 ((uint16_t)0x4000) /*!< Bit 2 */
+
+#define TIM_CCMOD3_OC6CEN ((uint16_t)0x8000) /*!< Output Compare 6 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+/******************* Bit definition for TIM_CCEN register *******************/
+#define TIM_CCEN_CC1EN ((uint32_t)0x00000001) /*!< Capture/Compare 1 output enable */
+#define TIM_CCEN_CC1P ((uint32_t)0x00000002) /*!< Capture/Compare 1 output Polarity */
+#define TIM_CCEN_CC1NEN ((uint32_t)0x00000004) /*!< Capture/Compare 1 Complementary output enable */
+#define TIM_CCEN_CC1NP ((uint32_t)0x00000008) /*!< Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCEN_CC2EN ((uint32_t)0x00000010) /*!< Capture/Compare 2 output enable */
+#define TIM_CCEN_CC2P ((uint32_t)0x00000020) /*!< Capture/Compare 2 output Polarity */
+#define TIM_CCEN_CC2NEN ((uint32_t)0x00000040) /*!< Capture/Compare 2 Complementary output enable */
+#define TIM_CCEN_CC2NP ((uint32_t)0x00000080) /*!< Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCEN_CC3EN ((uint32_t)0x00000100) /*!< Capture/Compare 3 output enable */
+#define TIM_CCEN_CC3P ((uint32_t)0x00000200) /*!< Capture/Compare 3 output Polarity */
+#define TIM_CCEN_CC3NEN ((uint32_t)0x00000400) /*!< Capture/Compare 3 Complementary output enable */
+#define TIM_CCEN_CC3NP ((uint32_t)0x00000800) /*!< Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCEN_CC4EN ((uint32_t)0x00001000) /*!< Capture/Compare 4 output enable */
+#define TIM_CCEN_CC4P ((uint32_t)0x00002000) /*!< Capture/Compare 4 output Polarity */
+
+#define TIM_CCEN_CC5EN ((uint32_t)0x00010000) /*!< Capture/Compare 5 output enable */
+#define TIM_CCEN_CC5P ((uint32_t)0x00020000) /*!< Capture/Compare 5 output Polarity */
+#define TIM_CCEN_CC6EN ((uint32_t)0x00100000) /*!< Capture/Compare 6 output enable */
+#define TIM_CCEN_CC6P ((uint32_t)0x00200000) /*!< Capture/Compare 6 output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!< Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!< Prescaler Value */
+
+/******************* Bit definition for TIM_AR register ********************/
+#define TIM_AR_AR ((uint16_t)0xFFFF) /*!< actual auto-reload Value */
+
+/******************* Bit definition for TIM_REPCNT register ********************/
+#define TIM_REPCNT_REPCNT ((uint8_t)0xFF) /*!< Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCDAT1 register *******************/
+#define TIM_CCDAT1_CCDAT1 ((uint16_t)0xFFFF) /*!< Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCDAT2 register *******************/
+#define TIM_CCDAT2_CCDAT2 ((uint16_t)0xFFFF) /*!< Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCDAT3 register *******************/
+#define TIM_CCDAT3_CCDAT3 ((uint16_t)0xFFFF) /*!< Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCDAT4 register *******************/
+#define TIM_CCDAT4_CCDAT4 ((uint16_t)0xFFFF) /*!< Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_CCDAT5 register *******************/
+#define TIM_CCDAT5_CCDAT5 ((uint16_t)0xFFFF) /*!< Capture/Compare 5 Value */
+
+/******************* Bit definition for TIM_CCDAT6 register *******************/
+#define TIM_CCDAT6_CCDAT6 ((uint16_t)0xFFFF) /*!< Capture/Compare 6 Value */
+
+/******************* Bit definition for TIM_BKDT register *******************/
+#define TIM_BKDT_DTGN ((uint16_t)0x00FF) /*!< DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BKDT_DTGN_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_BKDT_DTGN_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define TIM_BKDT_DTGN_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define TIM_BKDT_DTGN_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define TIM_BKDT_DTGN_4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define TIM_BKDT_DTGN_5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define TIM_BKDT_DTGN_6 ((uint16_t)0x0040) /*!< Bit 6 */
+#define TIM_BKDT_DTGN_7 ((uint16_t)0x0080) /*!< Bit 7 */
+
+#define TIM_BKDT_LCKCFG ((uint16_t)0x0300) /*!< LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BKDT_LCKCFG_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_BKDT_LCKCFG_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define TIM_BKDT_OSSI ((uint16_t)0x0400) /*!< Off-State Selection for Idle mode */
+#define TIM_BKDT_OSSR ((uint16_t)0x0800) /*!< Off-State Selection for Run mode */
+#define TIM_BKDT_BKEN ((uint16_t)0x1000) /*!< Break enable */
+#define TIM_BKDT_BKP ((uint16_t)0x2000) /*!< Break Polarity */
+#define TIM_BKDT_AOEN ((uint16_t)0x4000) /*!< Automatic Output enable */
+#define TIM_BKDT_MOEN ((uint16_t)0x8000) /*!< Main Output enable */
+
+/******************* Bit definition for TIM_DCTRL register ********************/
+#define TIM_DCTRL_DBADDR ((uint16_t)0x001F) /*!< DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCTRL_DBADDR_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_DCTRL_DBADDR_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define TIM_DCTRL_DBADDR_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define TIM_DCTRL_DBADDR_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define TIM_DCTRL_DBADDR_4 ((uint16_t)0x0010) /*!< Bit 4 */
+
+#define TIM_DCTRL_DBLEN ((uint16_t)0x1F00) /*!< DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCTRL_DBLEN_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_DCTRL_DBLEN_1 ((uint16_t)0x0200) /*!< Bit 1 */
+#define TIM_DCTRL_DBLEN_2 ((uint16_t)0x0400) /*!< Bit 2 */
+#define TIM_DCTRL_DBLEN_3 ((uint16_t)0x0800) /*!< Bit 3 */
+#define TIM_DCTRL_DBLEN_4 ((uint16_t)0x1000) /*!< Bit 4 */
+
+/******************* Bit definition for TIM_DADDR register *******************/
+#define TIM_DADDR_BURST ((uint16_t)0xFFFF) /*!< DMA register for burst accesses */
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_INTSTS register *******************/
+#define LPTIM_INTSTS_CMPM ((uint32_t)0x00000001) /*!< Compare match */
+#define LPTIM_INTSTS_ARRM ((uint32_t)0x00000002) /*!< Autoreload match */
+#define LPTIM_INTSTS_EXTRIG ((uint32_t)0x00000004) /*!< External trigger edge event */
+#define LPTIM_INTSTS_CMPUPD ((uint32_t)0x00000008) /*!< Compare register update OK */
+#define LPTIM_INTSTS_ARRUPD ((uint32_t)0x00000010) /*!< Autoreload register update OK */
+#define LPTIM_INTSTS_UP ((uint32_t)0x00000020) /*!< Counter direction change down to up */
+#define LPTIM_INTSTS_DOWN ((uint32_t)0x00000040) /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_INTCLR register *******************/
+#define LPTIM_INTCLR_CMPMCF ((uint32_t)0x00000001) /*!< Compare match Clear Flag */
+#define LPTIM_INTCLR_ARRMCF ((uint32_t)0x00000002) /*!< Autoreload match Clear Flag */
+#define LPTIM_INTCLR_EXTRIGCF ((uint32_t)0x00000004) /*!< External trigger edge event Clear Flag */
+#define LPTIM_INTCLR_CMPUPDCF ((uint32_t)0x00000008) /*!< Compare register update OK Clear Flag */
+#define LPTIM_INTCLR_ARRUPDCF ((uint32_t)0x00000010) /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_INTCLR_UPCF ((uint32_t)0x00000020) /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_INTCLR_DOWNCF ((uint32_t)0x00000040) /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_INTEN register ********************/
+#define LPTIM_INTEN_CMPMIE ((uint32_t)0x00000001) /*!< Compare match Interrupt Enable */
+#define LPTIM_INTEN_ARRMIE ((uint32_t)0x00000002) /*!< Autoreload match Interrupt Enable */
+#define LPTIM_INTEN_EXTRIGIE ((uint32_t)0x00000004) /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_INTEN_CMPUPDIE ((uint32_t)0x00000008) /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_INTEN_ARRUPDIE ((uint32_t)0x00000010) /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_INTEN_UPIE ((uint32_t)0x00000020) /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_INTEN_DOWNIE ((uint32_t)0x00000040) /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFG register *******************/
+#define LPTIM_CFG_CLKSEL ((uint32_t)0x00000001) /*!< Clock selector */
+
+#define LPTIM_CFG_CLKPOL ((uint32_t)0x00000006) /*!< CLKP[1:0] bits (Clock polarity) */
+#define LPTIM_CFG_CLKPOL_0 ((uint32_t)0x00000002) /*!< 0x00000002 */
+#define LPTIM_CFG_CLKPOL_1 ((uint32_t)0x00000004) /*!< 0x00000004 */
+
+#define LPTIM_CFG_CLKFLT ((uint32_t)0x00000018) /*!< CFGDFFEXT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFG_CLKFLT_0 ((uint32_t)0x00000008) /*!< 0x00000008 */
+#define LPTIM_CFG_CLKFLT_1 ((uint32_t)0x00000010) /*!< 0x00000010 */
+
+#define LPTIM_CFG_TRIGFLT ((uint32_t)0x000000C0) /*!< CFGDFFTRG[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFG_TRIGFLT_0 ((uint32_t)0x00000040) /*!< 0x00000040 */
+#define LPTIM_CFG_TRIGFLT_1 ((uint32_t)0x00000080) /*!< 0x00000080 */
+
+#define LPTIM_CFG_CLKPRE ((uint32_t)0x00000E00) /*!< CLKPRE[2:0] bits (Clock prescaler) */
+#define LPTIM_CFG_CLKPRE_0 ((uint32_t)0x00000200) /*!< 0x00000200 */
+#define LPTIM_CFG_CLKPRE_1 ((uint32_t)0x00000400) /*!< 0x00000400 */
+#define LPTIM_CFG_CLKPRE_2 ((uint32_t)0x00000800) /*!< 0x00000800 */
+
+#define LPTIM_CFG_TRGSEL ((uint32_t)0x0000E000) /*!< TRGS[2:0]] bits (Trigger selector) */
+#define LPTIM_CFG_TRGSEL_0 ((uint32_t)0x00002000) /*!< 0x00002000 */
+#define LPTIM_CFG_TRGSEL_1 ((uint32_t)0x00004000) /*!< 0x00004000 */
+#define LPTIM_CFG_TRGSEL_2 ((uint32_t)0x00008000) /*!< 0x00008000 */
+
+#define LPTIM_CFG_TRGEN ((uint32_t)0x00060000) /*!< TRGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFG_TRGEN_0 ((uint32_t)0x00020000) /*!< 0x00020000 */
+#define LPTIM_CFG_TRGEN_1 ((uint32_t)0x00040000) /*!< 0x00040000 */
+
+#define LPTIM_CFG_TIMOUTEN ((uint32_t)0x00080000) /*!< Timout enable */
+#define LPTIM_CFG_WAVE ((uint32_t)0x00100000) /*!< Waveform shape */
+#define LPTIM_CFG_WAVEPOL ((uint32_t)0x00200000) /*!< Waveform shape polarity */
+#define LPTIM_CFG_RELOAD ((uint32_t)0x00400000) /*!< Reg update mode */
+#define LPTIM_CFG_CNTMEN ((uint32_t)0x00800000) /*!< Counter mode enable */
+#define LPTIM_CFG_ENC ((uint32_t)0x01000000) /*!< Encoder mode enable */
+#define LPTIM_CFG_NENC ((uint32_t)0x02000000) /*!< NONEncoder mode enable */
+/****************** Bit definition for LPTIM_CTRL register ********************/
+#define LPTIM_CTRL_LPTIMEN ((uint32_t)0x000000001) /*!< LPTIMer enable */
+#define LPTIM_CTRL_SNGMST ((uint32_t)0x000000002) /*!< Timer start in single mode */
+#define LPTIM_CTRL_TSTCM ((uint32_t)0x000000004) /*!< Timer start in continuous mode */
+
+/****************** Bit definition for LPTIM_CMPT register *******************/
+#define LPTIM_COMP_CMPVAL ((uint16_t)0xFFFF) /*!< Compare register */
+
+/****************** Bit definition for LPTIM_AUTRLD register *******************/
+#define LPTIM_ARR_ARRVAL ((uint16_t)0xFFFF) /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNTVAL ((uint16_t)0xFFFF) /*!< Counter register */
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TSH register *******************/
+#define RTC_TSH_APM ((uint32_t)0x00400000)
+#define RTC_TSH_HOT ((uint32_t)0x00300000)
+#define RTC_TSH_HOT_0 ((uint32_t)0x00100000)
+#define RTC_TSH_HOT_1 ((uint32_t)0x00200000)
+#define RTC_TSH_HOU ((uint32_t)0x000F0000)
+#define RTC_TSH_HOU_0 ((uint32_t)0x00010000)
+#define RTC_TSH_HOU_1 ((uint32_t)0x00020000)
+#define RTC_TSH_HOU_2 ((uint32_t)0x00040000)
+#define RTC_TSH_HOU_3 ((uint32_t)0x00080000)
+#define RTC_TSH_MIT ((uint32_t)0x00007000)
+#define RTC_TSH_MIT_0 ((uint32_t)0x00001000)
+#define RTC_TSH_MIT_1 ((uint32_t)0x00002000)
+#define RTC_TSH_MIT_2 ((uint32_t)0x00004000)
+#define RTC_TSH_MIU ((uint32_t)0x00000F00)
+#define RTC_TSH_MIU_0 ((uint32_t)0x00000100)
+#define RTC_TSH_MIU_1 ((uint32_t)0x00000200)
+#define RTC_TSH_MIU_2 ((uint32_t)0x00000400)
+#define RTC_TSH_MIU_3 ((uint32_t)0x00000800)
+#define RTC_TSH_SCT ((uint32_t)0x00000070)
+#define RTC_TSH_SCT_0 ((uint32_t)0x00000010)
+#define RTC_TSH_SCT_1 ((uint32_t)0x00000020)
+#define RTC_TSH_SCT_2 ((uint32_t)0x00000040)
+#define RTC_TSH_SCU ((uint32_t)0x0000000F)
+#define RTC_TSH_SCU_0 ((uint32_t)0x00000001)
+#define RTC_TSH_SCU_1 ((uint32_t)0x00000002)
+#define RTC_TSH_SCU_2 ((uint32_t)0x00000004)
+#define RTC_TSH_SCU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_DATE register *******************/
+#define RTC_DATE_YRT ((uint32_t)0x00F00000)
+#define RTC_DATE_YRT_0 ((uint32_t)0x00100000)
+#define RTC_DATE_YRT_1 ((uint32_t)0x00200000)
+#define RTC_DATE_YRT_2 ((uint32_t)0x00400000)
+#define RTC_DATE_YRT_3 ((uint32_t)0x00800000)
+#define RTC_DATE_YRU ((uint32_t)0x000F0000)
+#define RTC_DATE_YRU_0 ((uint32_t)0x00010000)
+#define RTC_DATE_YRU_1 ((uint32_t)0x00020000)
+#define RTC_DATE_YRU_2 ((uint32_t)0x00040000)
+#define RTC_DATE_YRU_3 ((uint32_t)0x00080000)
+#define RTC_DATE_WDU ((uint32_t)0x0000E000)
+#define RTC_DATE_WDU_0 ((uint32_t)0x00002000)
+#define RTC_DATE_WDU_1 ((uint32_t)0x00004000)
+#define RTC_DATE_WDU_2 ((uint32_t)0x00008000)
+#define RTC_DATE_MOT ((uint32_t)0x00001000)
+#define RTC_DATE_MOU ((uint32_t)0x00000F00)
+#define RTC_DATE_MOU_0 ((uint32_t)0x00000100)
+#define RTC_DATE_MOU_1 ((uint32_t)0x00000200)
+#define RTC_DATE_MOU_2 ((uint32_t)0x00000400)
+#define RTC_DATE_MOU_3 ((uint32_t)0x00000800)
+#define RTC_DATE_DAT ((uint32_t)0x00000030)
+#define RTC_DATE_DAT_0 ((uint32_t)0x00000010)
+#define RTC_DATE_DAT_1 ((uint32_t)0x00000020)
+#define RTC_DATE_DAU ((uint32_t)0x0000000F)
+#define RTC_DATE_DAU_0 ((uint32_t)0x00000001)
+#define RTC_DATE_DAU_1 ((uint32_t)0x00000002)
+#define RTC_DATE_DAU_2 ((uint32_t)0x00000004)
+#define RTC_DATE_DAU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_CTRL register *******************/
+#define RTC_CTRL_COEN ((uint32_t)0x00800000)
+#define RTC_CTRL_OUTSEL ((uint32_t)0x00600000)
+#define RTC_CTRL_OUTSEL_0 ((uint32_t)0x00200000)
+#define RTC_CTRL_OUTSEL_1 ((uint32_t)0x00400000)
+#define RTC_CTRL_OPOL ((uint32_t)0x00100000)
+#define RTC_CTRL_CALOSEL ((uint32_t)0x00080000)
+#define RTC_CTRL_BAKP ((uint32_t)0x00040000)
+#define RTC_CTRL_SU1H ((uint32_t)0x00020000)
+#define RTC_CTRL_AD1H ((uint32_t)0x00010000)
+#define RTC_CTRL_TSIEN ((uint32_t)0x00008000)
+#define RTC_CTRL_WTIEN ((uint32_t)0x00004000)
+#define RTC_CTRL_ALBIEN ((uint32_t)0x00002000)
+#define RTC_CTRL_ALAIEN ((uint32_t)0x00001000)
+#define RTC_CTRL_TSEN ((uint32_t)0x00000800)
+#define RTC_CTRL_WTEN ((uint32_t)0x00000400)
+#define RTC_CTRL_ALBEN ((uint32_t)0x00000200)
+#define RTC_CTRL_ALAEN ((uint32_t)0x00000100)
+
+#define RTC_CTRL_HFMT ((uint32_t)0x00000040)
+#define RTC_CTRL_BYPS ((uint32_t)0x00000020)
+#define RTC_CTRL_REFCLKEN ((uint32_t)0x00000010)
+#define RTC_CTRL_TEDGE ((uint32_t)0x00000008)
+#define RTC_CTRL_WKUPSEL ((uint32_t)0x00000007)
+#define RTC_CTRL_WKUPSEL_0 ((uint32_t)0x00000001)
+#define RTC_CTRL_WKUPSEL_1 ((uint32_t)0x00000002)
+#define RTC_CTRL_WKUPSEL_2 ((uint32_t)0x00000004)
+
+/******************** Bits definition for RTC_INITSTS register ******************/
+#define RTC_INITSTS_RECPF ((uint32_t)0x00010000)
+#define RTC_INITSTS_TAM3F ((uint32_t)0x00008000)
+#define RTC_INITSTS_TAM2F ((uint32_t)0x00004000)
+#define RTC_INITSTS_TAM1F ((uint32_t)0x00002000)
+#define RTC_INITSTS_TISOVF ((uint32_t)0x00001000)
+#define RTC_INITSTS_TISF ((uint32_t)0x00000800)
+#define RTC_INITSTS_WTF ((uint32_t)0x00000400)
+#define RTC_INITSTS_ALBF ((uint32_t)0x00000200)
+#define RTC_INITSTS_ALAF ((uint32_t)0x00000100)
+#define RTC_INITSTS_INITM ((uint32_t)0x00000080)
+#define RTC_INITSTS_INITF ((uint32_t)0x00000040)
+#define RTC_INITSTS_RSYF ((uint32_t)0x00000020)
+#define RTC_INITSTS_INITSF ((uint32_t)0x00000010)
+#define RTC_INITSTS_SHOPF ((uint32_t)0x00000008)
+#define RTC_INITSTS_WTWF ((uint32_t)0x00000004)
+#define RTC_INITSTS_ALBWF ((uint32_t)0x00000002)
+#define RTC_INITSTS_ALAWF ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_PRE register *****************/
+#define RTC_PRE_DIVA ((uint32_t)0x007F0000)
+#define RTC_PRE_DIVS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_WKUPT register *****************/
+#define RTC_WKUPT_WKUPT ((uint32_t)0x0000FFFF)
+
+
+/******************** Bits definition for RTC_ALARMA register ***************/
+#define RTC_ALARMA_MASK4 ((uint32_t)0x80000000)
+#define RTC_ALARMA_WKDSEL ((uint32_t)0x40000000)
+#define RTC_ALARMA_DTT ((uint32_t)0x30000000)
+#define RTC_ALARMA_DTT_0 ((uint32_t)0x10000000)
+#define RTC_ALARMA_DTT_1 ((uint32_t)0x20000000)
+#define RTC_ALARMA_DTU ((uint32_t)0x0F000000)
+#define RTC_ALARMA_DTU_0 ((uint32_t)0x01000000)
+#define RTC_ALARMA_DTU_1 ((uint32_t)0x02000000)
+#define RTC_ALARMA_DTU_2 ((uint32_t)0x04000000)
+#define RTC_ALARMA_DTU_3 ((uint32_t)0x08000000)
+#define RTC_ALARMA_MASK3 ((uint32_t)0x00800000)
+#define RTC_ALARMA_APM ((uint32_t)0x00400000)
+#define RTC_ALARMA_HOT ((uint32_t)0x00300000)
+#define RTC_ALARMA_HOT_0 ((uint32_t)0x00100000)
+#define RTC_ALARMA_HOT_1 ((uint32_t)0x00200000)
+#define RTC_ALARMA_HOU ((uint32_t)0x000F0000)
+#define RTC_ALARMA_HOU_0 ((uint32_t)0x00010000)
+#define RTC_ALARMA_HOU_1 ((uint32_t)0x00020000)
+#define RTC_ALARMA_HOU_2 ((uint32_t)0x00040000)
+#define RTC_ALARMA_HOU_3 ((uint32_t)0x00080000)
+#define RTC_ALARMA_MASK2 ((uint32_t)0x00008000)
+#define RTC_ALARMA_MIT ((uint32_t)0x00007000)
+#define RTC_ALARMA_MIT_0 ((uint32_t)0x00001000)
+#define RTC_ALARMA_MIT_1 ((uint32_t)0x00002000)
+#define RTC_ALARMA_MIT_2 ((uint32_t)0x00004000)
+#define RTC_ALARMA_MIU ((uint32_t)0x00000F00)
+#define RTC_ALARMA_MIU_0 ((uint32_t)0x00000100)
+#define RTC_ALARMA_MIU_1 ((uint32_t)0x00000200)
+#define RTC_ALARMA_MIU_2 ((uint32_t)0x00000400)
+#define RTC_ALARMA_MIU_3 ((uint32_t)0x00000800)
+#define RTC_ALARMA_MASK1 ((uint32_t)0x00000080)
+#define RTC_ALARMA_SET ((uint32_t)0x00000070)
+#define RTC_ALARMA_SET_0 ((uint32_t)0x00000010)
+#define RTC_ALARMA_SET_1 ((uint32_t)0x00000020)
+#define RTC_ALARMA_SET_2 ((uint32_t)0x00000040)
+#define RTC_ALARMA_SEU ((uint32_t)0x0000000F)
+#define RTC_ALARMA_SEU_0 ((uint32_t)0x00000001)
+#define RTC_ALARMA_SEU_1 ((uint32_t)0x00000002)
+#define RTC_ALARMA_SEU_2 ((uint32_t)0x00000004)
+#define RTC_ALARMA_SEU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_ALARMB register ***************/
+#define RTC_ALARMB_MASK4 ((uint32_t)0x80000000)
+#define RTC_ALARMB_WKDSEL ((uint32_t)0x40000000)
+#define RTC_ALARMB_DTT ((uint32_t)0x30000000)
+#define RTC_ALARMB_DTT_0 ((uint32_t)0x10000000)
+#define RTC_ALARMB_DTT_1 ((uint32_t)0x20000000)
+#define RTC_ALARMB_DTU ((uint32_t)0x0F000000)
+#define RTC_ALARMB_DTU_0 ((uint32_t)0x01000000)
+#define RTC_ALARMB_DTU_1 ((uint32_t)0x02000000)
+#define RTC_ALARMB_DTU_2 ((uint32_t)0x04000000)
+#define RTC_ALARMB_DTU_3 ((uint32_t)0x08000000)
+#define RTC_ALARMB_MASK3 ((uint32_t)0x00800000)
+#define RTC_ALARMB_APM ((uint32_t)0x00400000)
+#define RTC_ALARMB_HOT ((uint32_t)0x00300000)
+#define RTC_ALARMB_HOT_0 ((uint32_t)0x00100000)
+#define RTC_ALARMB_HOT_1 ((uint32_t)0x00200000)
+#define RTC_ALARMB_HOU ((uint32_t)0x000F0000)
+#define RTC_ALARMB_HOU_0 ((uint32_t)0x00010000)
+#define RTC_ALARMB_HOU_1 ((uint32_t)0x00020000)
+#define RTC_ALARMB_HOU_2 ((uint32_t)0x00040000)
+#define RTC_ALARMB_HOU_3 ((uint32_t)0x00080000)
+#define RTC_ALARMB_MASK2 ((uint32_t)0x00008000)
+#define RTC_ALARMB_MIT ((uint32_t)0x00007000)
+#define RTC_ALARMB_MIT_0 ((uint32_t)0x00001000)
+#define RTC_ALARMB_MIT_1 ((uint32_t)0x00002000)
+#define RTC_ALARMB_MIT_2 ((uint32_t)0x00004000)
+#define RTC_ALARMB_MIU ((uint32_t)0x00000F00)
+#define RTC_ALARMB_MIU_0 ((uint32_t)0x00000100)
+#define RTC_ALARMB_MIU_1 ((uint32_t)0x00000200)
+#define RTC_ALARMB_MIU_2 ((uint32_t)0x00000400)
+#define RTC_ALARMB_MIU_3 ((uint32_t)0x00000800)
+#define RTC_ALARMB_MASK1 ((uint32_t)0x00000080)
+#define RTC_ALARMB_SET ((uint32_t)0x00000070)
+#define RTC_ALARMB_SET_0 ((uint32_t)0x00000010)
+#define RTC_ALARMB_SET_1 ((uint32_t)0x00000020)
+#define RTC_ALARMB_SET_2 ((uint32_t)0x00000040)
+#define RTC_ALARMB_SEU ((uint32_t)0x0000000F)
+#define RTC_ALARMB_SEU_0 ((uint32_t)0x00000001)
+#define RTC_ALARMB_SEU_1 ((uint32_t)0x00000002)
+#define RTC_ALARMB_SEU_2 ((uint32_t)0x00000004)
+#define RTC_ALARMB_SEU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_WRP register ******************/
+#define RTC_WRP_PKEY ((uint32_t)0x000000FF)
+
+/******************** Bits definition for RTC_SUBS register ******************/
+#define RTC_SUBS_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_SCTRL register ***************/
+#define RTC_SCTRL_SUBF ((uint32_t)0x00007FFF)
+#define RTC_SCTRL_AD1S ((uint32_t)0x80000000)
+
+/******************** Bits definition for RTC_TST register *****************/
+#define RTC_TST_APM ((uint32_t)0x00400000)
+#define RTC_TST_HOT ((uint32_t)0x00300000)
+#define RTC_TST_HOT_0 ((uint32_t)0x00100000)
+#define RTC_TST_HOT_1 ((uint32_t)0x00200000)
+#define RTC_TST_HOU ((uint32_t)0x000F0000)
+#define RTC_TST_HOU_0 ((uint32_t)0x00010000)
+#define RTC_TST_HOU_1 ((uint32_t)0x00020000)
+#define RTC_TST_HOU_2 ((uint32_t)0x00040000)
+#define RTC_TST_HOU_3 ((uint32_t)0x00080000)
+#define RTC_TST_MIT ((uint32_t)0x00007000)
+#define RTC_TST_MIT_0 ((uint32_t)0x00001000)
+#define RTC_TST_MIT_1 ((uint32_t)0x00002000)
+#define RTC_TST_MIT_2 ((uint32_t)0x00004000)
+#define RTC_TST_MIU ((uint32_t)0x00000F00)
+#define RTC_TST_MIU_0 ((uint32_t)0x00000100)
+#define RTC_TST_MIU_1 ((uint32_t)0x00000200)
+#define RTC_TST_MIU_2 ((uint32_t)0x00000400)
+#define RTC_TST_MIU_3 ((uint32_t)0x00000800)
+#define RTC_TST_SET ((uint32_t)0x00000070)
+#define RTC_TST_SET_0 ((uint32_t)0x00000010)
+#define RTC_TST_SET_1 ((uint32_t)0x00000020)
+#define RTC_TST_SET_2 ((uint32_t)0x00000040)
+#define RTC_TST_SEU ((uint32_t)0x0000000F)
+#define RTC_TST_SEU_0 ((uint32_t)0x00000001)
+#define RTC_TST_SEU_1 ((uint32_t)0x00000002)
+#define RTC_TST_SEU_2 ((uint32_t)0x00000004)
+#define RTC_TST_SEU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSD register *****************/
+#define RTC_TSD_YRT ((uint32_t)0x00F00000)
+#define RTC_TSD_YRT_0 ((uint32_t)0x00100000)
+#define RTC_TSD_YRT_1 ((uint32_t)0x00200000)
+#define RTC_TSD_YRT_2 ((uint32_t)0x00400000)
+#define RTC_TSD_YRT_3 ((uint32_t)0x00800000)
+#define RTC_TSD_YRU ((uint32_t)0x000F0000)
+#define RTC_TSD_YRU_0 ((uint32_t)0x00010000)
+#define RTC_TSD_YRU_1 ((uint32_t)0x00020000)
+#define RTC_TSD_YRU_2 ((uint32_t)0x00040000)
+#define RTC_TSD_YRU_3 ((uint32_t)0x00080000)
+
+#define RTC_TSD_WDU ((uint32_t)0x0000E000)
+#define RTC_TSD_WDU_0 ((uint32_t)0x00002000)
+#define RTC_TSD_WDU_1 ((uint32_t)0x00004000)
+#define RTC_TSD_WDU_2 ((uint32_t)0x00008000)
+#define RTC_TSD_MOT ((uint32_t)0x00001000)
+#define RTC_TSD_MOU ((uint32_t)0x00000F00)
+#define RTC_TSD_MOU_0 ((uint32_t)0x00000100)
+#define RTC_TSD_MOU_1 ((uint32_t)0x00000200)
+#define RTC_TSD_MOU_2 ((uint32_t)0x00000400)
+#define RTC_TSD_MOU_3 ((uint32_t)0x00000800)
+#define RTC_TSD_DAT ((uint32_t)0x00000030)
+#define RTC_TSD_DAT_0 ((uint32_t)0x00000010)
+#define RTC_TSD_DAT_1 ((uint32_t)0x00000020)
+#define RTC_TSD_DAU ((uint32_t)0x0000000F)
+#define RTC_TSD_DAU_0 ((uint32_t)0x00000001)
+#define RTC_TSD_DAU_1 ((uint32_t)0x00000002)
+#define RTC_TSD_DAU_2 ((uint32_t)0x00000004)
+#define RTC_TSD_DAU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSSS register ****************/
+#define RTC_TSSS_SSE ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CALIB register *****************/
+#define RTC_CALIB_CP ((uint32_t)0x00008000)
+#define RTC_CALIB_CW8 ((uint32_t)0x00004000)
+#define RTC_CALIB_CW16 ((uint32_t)0x00002000)
+#define RTC_CALIB_CM ((uint32_t)0x000001FF)
+#define RTC_CALIB_CM_0 ((uint32_t)0x00000001)
+#define RTC_CALIB_CM_1 ((uint32_t)0x00000002)
+#define RTC_CALIB_CM_2 ((uint32_t)0x00000004)
+#define RTC_CALIB_CM_3 ((uint32_t)0x00000008)
+#define RTC_CALIB_CM_4 ((uint32_t)0x00000010)
+#define RTC_CALIB_CM_5 ((uint32_t)0x00000020)
+#define RTC_CALIB_CM_6 ((uint32_t)0x00000040)
+#define RTC_CALIB_CM_7 ((uint32_t)0x00000080)
+#define RTC_CALIB_CM_8 ((uint32_t)0x00000100)
+
+/******************** Bits definition for RTC_TMPCFG register ****************/
+
+#define RTC_TMPCFG_TP3MF ((uint32_t)0x01000000)
+#define RTC_TMPCFG_TP3NOE ((uint32_t)0x00800000)
+#define RTC_TMPCFG_TP3INTEN ((uint32_t)0x00400000)
+#define RTC_TMPCFG_TP2MF ((uint32_t)0x00200000)
+#define RTC_TMPCFG_TP2NOE ((uint32_t)0x00100000)
+#define RTC_TMPCFG_TP2INTEN ((uint32_t)0x00080000)
+#define RTC_TMPCFG_TP1MF ((uint32_t)0x00040000)
+#define RTC_TMPCFG_TP1NOE ((uint32_t)0x00020000)
+#define RTC_TMPCFG_TP1INTEN ((uint32_t)0x00010000)
+#define RTC_TMPCFG_TPPUDIS ((uint32_t)0x00008000)
+#define RTC_TMPCFG_TPPRCH ((uint32_t)0x00006000)
+#define RTC_TMPCFG_TPPRCH_0 ((uint32_t)0x00002000)
+#define RTC_TMPCFG_TPPRCH_1 ((uint32_t)0x00004000)
+#define RTC_TMPCFG_TPFLT ((uint32_t)0x00001800)
+#define RTC_TMPCFG_TPFLT_0 ((uint32_t)0x00000800)
+#define RTC_TMPCFG_TPFLT_1 ((uint32_t)0x00001000)
+#define RTC_TMPCFG_TPFREQ ((uint32_t)0x00000700)
+#define RTC_TMPCFG_TPFREQ_0 ((uint32_t)0x00000100)
+#define RTC_TMPCFG_TPFREQ_1 ((uint32_t)0x00000200)
+#define RTC_TMPCFG_TPFREQ_2 ((uint32_t)0x00000400)
+#define RTC_TMPCFG_TPTS ((uint32_t)0x00000080)
+#define RTC_TMPCFG_TP3TRG ((uint32_t)0x00000040)
+#define RTC_TMPCFG_TP3EN ((uint32_t)0x00000020)
+#define RTC_TMPCFG_TP2TRG ((uint32_t)0x00000010)
+#define RTC_TMPCFG_TP2EN ((uint32_t)0x00000008)
+#define RTC_TMPCFG_TPINTEN ((uint32_t)0x00000004)
+#define RTC_TMPCFG_TP1TRG ((uint32_t)0x00000002)
+#define RTC_TMPCFG_TP1EN ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_ALRMASS register *************/
+#define RTC_ALRMASS_MASKSSB ((uint32_t)0x0F000000)
+#define RTC_ALRMASS_MASKSSB_0 ((uint32_t)0x01000000)
+#define RTC_ALRMASS_MASKSSB_1 ((uint32_t)0x02000000)
+#define RTC_ALRMASS_MASKSSB_2 ((uint32_t)0x04000000)
+#define RTC_ALRMASS_MASKSSB_3 ((uint32_t)0x08000000)
+#define RTC_ALRMASS_SSV ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_ALRMBSS register *************/
+#define RTC_ALRMBSS_MASKSSB ((uint32_t)0x0F000000)
+#define RTC_ALRMBSS_MASKSSB_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBSS_MASKSSB_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBSS_MASKSSB_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBSS_MASKSSB_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBSS_SSV ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_OPT register *******************/
+#define RTC_OPT_TYPE ((uint32_t)0x00000001)
+/******************** Bits definition for RTC_TSCWKUPCTRL register *******************/
+#define RTC_TSCWKUPCTRL_WKUPOFF ((uint32_t)0x00000008)
+#define RTC_TSCWKUPCTRL_WKUPCNF ((uint32_t)0x00000004)
+#define RTC_TSCWKUPCTRL_WKUPEN ((uint32_t)0x00000001)
+/******************** Bits definition for RTC_TSCWKUPCNT register *******************/
+#define RTC_TSCWKUPCNT_CNT ((uint32_t)0x00003FFF)
+/******************** Bits definition for RTC_BKP1 register ****************/
+#define RTC_BKP1 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP2 register ****************/
+#define RTC_BKP2 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP3 register ****************/
+#define RTC_BKP3 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP4 register ****************/
+#define RTC_BKP4 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP5 register ****************/
+#define RTC_BKP5 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP6 register ****************/
+#define RTC_BKP6 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP7 register ****************/
+#define RTC_BKP7 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP8 register ****************/
+#define RTC_BKP8 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP9 register ****************/
+#define RTC_BKP9 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP10 register ****************/
+#define RTC_BKP10 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP11 register ***************/
+#define RTC_BKP11 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP12register ***************/
+#define RTC_BKP12 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP13 register ***************/
+#define RTC_BKP13 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP14 register ***************/
+#define RTC_BKP14 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP15 register ***************/
+#define RTC_BKP15 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP16 register ***************/
+#define RTC_BKP16 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP17register ***************/
+#define RTC_BKP17 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP18 register ***************/
+#define RTC_BKP18 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP19 register ***************/
+#define RTC_BKP19 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP20 register ***************/
+#define RTC_BKP20 ((uint32_t)0xFFFFFFFF)
+
+
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for IWDG_KEY register ********************/
+#define IWDG_KEY_KEYV ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PREDIV register ********************/
+#define IWDG_PREDIV_PD ((uint8_t)0x07) /*!< PD[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */
+#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */
+#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */
+
+/******************* Bit definition for IWDG_RELV register *******************/
+#define IWDG_RELV_REL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_STS register ********************/
+#define IWDG_STS_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */
+#define IWDG_STS_CRVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CTRL register ********************/
+#define WWDG_CTRL_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CTRL_T0 ((uint8_t)0x01) /*!< Bit 0 */
+#define WWDG_CTRL_T1 ((uint8_t)0x02) /*!< Bit 1 */
+#define WWDG_CTRL_T2 ((uint8_t)0x04) /*!< Bit 2 */
+#define WWDG_CTRL_T3 ((uint8_t)0x08) /*!< Bit 3 */
+#define WWDG_CTRL_T4 ((uint8_t)0x10) /*!< Bit 4 */
+#define WWDG_CTRL_T5 ((uint8_t)0x20) /*!< Bit 5 */
+#define WWDG_CTRL_T6 ((uint8_t)0x40) /*!< Bit 6 */
+
+#define WWDG_CTRL_ACTB ((uint8_t)0x80) /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFG register *******************/
+#define WWDG_CFG_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFG_W0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define WWDG_CFG_W1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define WWDG_CFG_W2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define WWDG_CFG_W3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define WWDG_CFG_W4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define WWDG_CFG_W5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define WWDG_CFG_W6 ((uint16_t)0x0040) /*!< Bit 6 */
+
+#define WWDG_CFG_TIMERB ((uint16_t)0x0180) /*!< TIMERB[1:0] bits (Timer Base) */
+#define WWDG_CFG_TIMERB0 ((uint16_t)0x0080) /*!< Bit 0 */
+#define WWDG_CFG_TIMERB1 ((uint16_t)0x0100) /*!< Bit 1 */
+
+#define WWDG_CFG_EWINT ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_STS register ********************/
+#define WWDG_STS_EWINTF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Flexible Static Memory Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for XFMC_BCR1 register *******************/
+#define XFMC_BK1CSCTRL1_MBEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
+#define XFMC_BK1CSCTRL1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
+
+#define XFMC_BK1CSCTRL1_MTYPE ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
+#define XFMC_BK1CSCTRL1_MTYPE_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define XFMC_BK1CSCTRL1_MTYPE_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define XFMC_BK1CSCTRL1_MDBW ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
+#define XFMC_BK1CSCTRL1_MDBW_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK1CSCTRL1_MDBW_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define XFMC_BK1CSCTRL1_ACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
+#define XFMC_BK1CSCTRL1_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
+#define XFMC_BK1CSCTRL1_WAITDIR ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
+#define XFMC_BK1CSCTRL1_WRAPEN ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
+#define XFMC_BK1CSCTRL1_WCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
+#define XFMC_BK1CSCTRL1_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
+#define XFMC_BK1CSCTRL1_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
+#define XFMC_BK1CSCTRL1_EXTEN ((uint32_t)0x00004000) /*!< Extended mode enable */
+#define XFMC_BK1CSCTRL1_WAITASYNC ((uint32_t)0x00008000) /*!< Asynchronous wait */
+#define XFMC_BK1CSCTRL1_BURSTWREN ((uint32_t)0x00080000) /*!< Write burst enable */
+
+/****************** Bit definition for XFMC_BCR2 register *******************/
+#define XFMC_BK1CSCTRL2_MBEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
+#define XFMC_BK1CSCTRL2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
+
+#define XFMC_BK1CSCTRL2_MTYPE ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
+#define XFMC_BK1CSCTRL2_MTYPE_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define XFMC_BK1CSCTRL2_MTYPE_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define XFMC_BK1CSCTRL2_MDBW ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
+#define XFMC_BK1CSCTRL2_MDBW_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK1CSCTRL2_MDBW_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define XFMC_BK1CSCTRL2_ACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
+#define XFMC_BK1CSCTRL2_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
+#define XFMC_BK1CSCTRL2_WAITDIR ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
+#define XFMC_BK1CSCTRL2_WRAPEN ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
+#define XFMC_BK1CSCTRL2_WCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
+#define XFMC_BK1CSCTRL2_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
+#define XFMC_BK1CSCTRL2_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
+#define XFMC_BK1CSCTRL2_EXTEN ((uint32_t)0x00004000) /*!< Extended mode enable */
+#define XFMC_BK1CSCTRL2_WAITASYNC ((uint32_t)0x00008000) /*!< Asynchronous wait */
+#define XFMC_BK1CSCTRL2_BURSTWREN ((uint32_t)0x00080000) /*!< Write burst enable */
+
+/****************** Bit definition for XFMC_BTR1 register ******************/
+#define XFMC_BK1TM1_ADDBLD ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define XFMC_BK1TM1_ADDBLD_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_BK1TM1_ADDBLD_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_BK1TM1_ADDBLD_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_BK1TM1_ADDBLD_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define XFMC_BK1TM1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define XFMC_BK1TM1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK1TM1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define XFMC_BK1TM1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define XFMC_BK1TM1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define XFMC_BK1TM1_DATABLD ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define XFMC_BK1TM1_DATABLD_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_BK1TM1_DATABLD_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_BK1TM1_DATABLD_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_BK1TM1_DATABLD_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define XFMC_BK1TM1_BUSRECOVERY ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define XFMC_BK1TM1_BUSRECOVERY_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define XFMC_BK1TM1_BUSRECOVERY_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define XFMC_BK1TM1_BUSRECOVERY_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define XFMC_BK1TM1_BUSRECOVERY_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+
+#define XFMC_BK1TM1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define XFMC_BK1TM1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define XFMC_BK1TM1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define XFMC_BK1TM1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define XFMC_BK1TM1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define XFMC_BK1TM1_DATAHLD ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define XFMC_BK1TM1_DATAHLD_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_BK1TM1_DATAHLD_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_BK1TM1_DATAHLD_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_BK1TM1_DATAHLD_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define XFMC_BK1TM1_ACCMODE ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define XFMC_BK1TM1_ACCMODE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define XFMC_BK1TM1_ACCMODE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for XFMC_BTR2 register *******************/
+#define XFMC_BK1TM2_ADDBLD ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define XFMC_BK1TM2_ADDBLD_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_BK1TM2_ADDBLD_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_BK1TM2_ADDBLD_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_BK1TM2_ADDBLD_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define XFMC_BK1TM2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define XFMC_BK1TM2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK1TM2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define XFMC_BK1TM2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define XFMC_BK1TM2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define XFMC_BK1TM2_DATABLD ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define XFMC_BK1TM2_DATABLD_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_BK1TM2_DATABLD_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_BK1TM2_DATABLD_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_BK1TM2_DATABLD_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define XFMC_BK1TM2_BUSRECOVERY ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define XFMC_BK1TM2_BUSRECOVERY_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define XFMC_BK1TM2_BUSRECOVERY_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define XFMC_BK1TM2_BUSRECOVERY_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define XFMC_BK1TM2_BUSRECOVERY_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+
+#define XFMC_BK1TM2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define XFMC_BK1TM2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define XFMC_BK1TM2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define XFMC_BK1TM2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define XFMC_BK1TM2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define XFMC_BK1TM2_DATAHLD ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define XFMC_BK1TM2_DATAHLD_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_BK1TM2_DATAHLD_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_BK1TM2_DATAHLD_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_BK1TM2_DATAHLD_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define XFMC_BK1TM2_ACCMODE ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define XFMC_BK1TM2_ACCMODE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define XFMC_BK1TM2_ACCMODE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for XFMC_BWTR1 register ******************/
+#define XFMC_BK1WTM1_ADDBLD ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define XFMC_BK1WTM1_ADDBLD_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_BK1WTM1_ADDBLD_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_BK1WTM1_ADDBLD_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_BK1WTM1_ADDBLD_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define XFMC_BK1WTM1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define XFMC_BK1WTM1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK1WTM1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define XFMC_BK1WTM1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define XFMC_BK1WTM1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define XFMC_BK1WTM1_DATABLD ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define XFMC_BK1WTM1_DATABLD_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_BK1WTM1_DATABLD_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_BK1WTM1_DATABLD_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_BK1WTM1_DATABLD_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define XFMC_BK1WTM1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define XFMC_BK1WTM1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define XFMC_BK1WTM1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define XFMC_BK1WTM1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define XFMC_BK1WTM1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define XFMC_BK1WTM1_DATAHLD ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define XFMC_BK1WTM1_DATAHLD_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_BK1WTM1_DATAHLD_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_BK1WTM1_DATAHLD_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_BK1WTM1_DATAHLD_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define XFMC_BK1WTM1_ACCMODE ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define XFMC_BK1WTM1_ACCMODE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define XFMC_BK1WTM1_ACCMODE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for XFMC_BWTR2 register ******************/
+#define XFMC_BK1WTM2_ADDBLD ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define XFMC_BK1WTM2_ADDBLD_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_BK1WTM2_ADDBLD_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_BK1WTM2_ADDBLD_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_BK1WTM2_ADDBLD_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define XFMC_BK1WTM2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define XFMC_BK1WTM2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK1WTM2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define XFMC_BK1WTM2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define XFMC_BK1WTM2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define XFMC_BK1WTM2_DATABLD ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define XFMC_BK1WTM2_DATABLD_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_BK1WTM2_DATABLD_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_BK1WTM2_DATABLD_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_BK1WTM2_DATABLD_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define XFMC_BK1WTM2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define XFMC_BK1WTM2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define XFMC_BK1WTM2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1*/
+#define XFMC_BK1WTM2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define XFMC_BK1WTM2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define XFMC_BK1WTM2_DATAHLD ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define XFMC_BK1WTM2_DATAHLD_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_BK1WTM2_DATAHLD_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_BK1WTM2_DATAHLD_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_BK1WTM2_DATAHLD_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define XFMC_BK1WTM2_ACCMODE ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define XFMC_BK1WTM2_ACCMODE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define XFMC_BK1WTM2_ACCMODE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for XFMC_PCR2 register *******************/
+#define XFMC_BK2CTRL_WAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */
+#define XFMC_BK2CTRL_BANKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */
+#define XFMC_BK2CTRL_MEMTYPE ((uint32_t)0x00000008) /*!< Memory type */
+
+#define XFMC_BK2CTRL_BUSWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define XFMC_BK2CTRL_BUSWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK2CTRL_BUSWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define XFMC_BK2CTRL_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */
+
+#define XFMC_BK2CTRL_CRDLY ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define XFMC_BK2CTRL_CRDLY_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define XFMC_BK2CTRL_CRDLY_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define XFMC_BK2CTRL_CRDLY_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+#define XFMC_BK2CTRL_CRDLY_3 ((uint32_t)0x00001000) /*!< Bit 3 */
+
+#define XFMC_BK2CTRL_ARDLY ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */
+#define XFMC_BK2CTRL_ARDLY_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define XFMC_BK2CTRL_ARDLY_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define XFMC_BK2CTRL_ARDLY_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+#define XFMC_BK2CTRL_ARDLY_3 ((uint32_t)0x00010000) /*!< Bit 3 */
+
+#define XFMC_BK2CTRL_ECCPGS ((uint32_t)0x000E0000) /*!< ECCPS[1:0] bits (ECC page size) */
+#define XFMC_BK2CTRL_ECCPGS_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define XFMC_BK2CTRL_ECCPGS_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define XFMC_BK2CTRL_ECCPGS_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+
+/****************** Bit definition for XFMC_PCR3 register *******************/
+#define XFMC_BK3CTRL_WAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */
+#define XFMC_BK3CTRL_BANKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */
+#define XFMC_BK3CTRL_MEMTYPE ((uint32_t)0x00000008) /*!< Memory type */
+
+#define XFMC_BK3CTRL_BUSWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define XFMC_BK3CTRL_BUSWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK3CTRL_BUSWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define XFMC_BK3CTRL_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */
+
+#define XFMC_BK3CTRL_CRDLY ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define XFMC_BK3CTRL_CRDLY_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define XFMC_BK3CTRL_CRDLY_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define XFMC_BK3CTRL_CRDLY_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+#define XFMC_BK3CTRL_CRDLY_3 ((uint32_t)0x00001000) /*!< Bit 3 */
+
+#define XFMC_BK3CTRL_ARDLY ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */
+#define XFMC_BK3CTRL_ARDLY_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define XFMC_BK3CTRL_ARDLY_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define XFMC_BK3CTRL_ARDLY_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+#define XFMC_BK3CTRL_ARDLY_3 ((uint32_t)0x00010000) /*!< Bit 3 */
+
+#define XFMC_BK3CTRL_ECCPGS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */
+#define XFMC_BK3CTRL_ECCPGS_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define XFMC_BK3CTRL_ECCPGS_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define XFMC_BK3CTRL_ECCPGS_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+
+/******************* Bit definition for XFMC_SR2 register *******************/
+//#define XFMC_SR2_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */
+//#define XFMC_SR2_ILS ((uint8_t)0x02) /*!< Interrupt Level status */
+//#define XFMC_SR2_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */
+//#define XFMC_SR2_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable
+// bit */ #define XFMC_SR2_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection
+// Enable bit */ #define XFMC_SR2_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge
+// detection Enable bit */
+#define XFMC_STS2_FIFOEMPT ((uint8_t)0x40) /*!< DATFIFO empty */
+
+/******************* Bit definition for XFMC_SR3 register *******************/
+//#define XFMC_SR3_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */
+//#define XFMC_SR3_ILS ((uint8_t)0x02) /*!< Interrupt Level status */
+//#define XFMC_SR3_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */
+//#define XFMC_SR3_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable
+// bit */ #define XFMC_SR3_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection
+// Enable bit */ #define XFMC_SR3_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge
+// detection Enable bit */
+#define XFMC_STS3_FIFOEMPT ((uint8_t)0x40) /*!< DATFIFO empty */
+
+/****************** Bit definition for XFMC_PMEM2 register ******************/
+#define XFMC_CMEMTM2_SET ((uint32_t)0x000000FF) /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define XFMC_CMEMTM2_SET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_CMEMTM2_SET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_CMEMTM2_SET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_CMEMTM2_SET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define XFMC_CMEMTM2_SET_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define XFMC_CMEMTM2_SET_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define XFMC_CMEMTM2_SET_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define XFMC_CMEMTM2_SET_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define XFMC_CMEMTM2_WAIT ((uint32_t)0x0000FF00) /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define XFMC_CMEMTM2_WAIT_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_CMEMTM2_WAIT_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_CMEMTM2_WAIT_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_CMEMTM2_WAIT_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define XFMC_CMEMTM2_WAIT_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define XFMC_CMEMTM2_WAIT_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define XFMC_CMEMTM2_WAIT_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define XFMC_CMEMTM2_WAIT_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define XFMC_CMEMTM2_HLD ((uint32_t)0x00FF0000) /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define XFMC_CMEMTM2_HLD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define XFMC_CMEMTM2_HLD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define XFMC_CMEMTM2_HLD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define XFMC_CMEMTM2_HLD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define XFMC_CMEMTM2_HLD_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define XFMC_CMEMTM2_HLD_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define XFMC_CMEMTM2_HLD_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define XFMC_CMEMTM2_HLD_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+
+#define XFMC_CMEMTM2_HIZ ((uint32_t)0xFF000000) /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define XFMC_CMEMTM2_HIZ_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_CMEMTM2_HIZ_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_CMEMTM2_HIZ_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_CMEMTM2_HIZ_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define XFMC_CMEMTM2_HIZ_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define XFMC_CMEMTM2_HIZ_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define XFMC_CMEMTM2_HIZ_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define XFMC_CMEMTM2_HIZ_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/****************** Bit definition for XFMC_PMEM3 register ******************/
+#define XFMC_CMEMTM3_SET ((uint32_t)0x000000FF) /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define XFMC_CMEMTM3_SET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_CMEMTM3_SET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_CMEMTM3_SET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_CMEMTM3_SET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define XFMC_CMEMTM3_SET_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define XFMC_CMEMTM3_SET_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define XFMC_CMEMTM3_SET_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define XFMC_CMEMTM3_SET_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define XFMC_CMEMTM3_WAIT ((uint32_t)0x0000FF00) /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define XFMC_CMEMTM3_WAIT_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_CMEMTM3_WAIT_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_CMEMTM3_WAIT_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_CMEMTM3_WAIT_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define XFMC_CMEMTM3_WAIT_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define XFMC_CMEMTM3_WAIT_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define XFMC_CMEMTM3_WAIT_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define XFMC_CMEMTM3_WAIT_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define XFMC_CMEMTM3_HLD ((uint32_t)0x00FF0000) /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define XFMC_CMEMTM3_HLD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define XFMC_CMEMTM3_HLD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define XFMC_CMEMTM3_HLD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define XFMC_CMEMTM3_HLD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define XFMC_CMEMTM3_HLD_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define XFMC_CMEMTM3_HLD_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define XFMC_CMEMTM3_HLD_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define XFMC_CMEMTM3_HLD_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+
+#define XFMC_CMEMTM3_HIZ ((uint32_t)0xFF000000) /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define XFMC_CMEMTM3_HIZ_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_CMEMTM3_HIZ_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_CMEMTM3_HIZ_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_CMEMTM3_HIZ_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define XFMC_CMEMTM3_HIZ_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define XFMC_CMEMTM3_HIZ_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define XFMC_CMEMTM3_HIZ_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define XFMC_CMEMTM3_HIZ_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/****************** Bit definition for XFMC_PATT2 register ******************/
+#define XFMC_ATTMEMTM2_SET ((uint32_t)0x000000FF) /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define XFMC_ATTMEMTM2_SET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_ATTMEMTM2_SET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_ATTMEMTM2_SET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_ATTMEMTM2_SET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define XFMC_ATTMEMTM2_SET_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define XFMC_ATTMEMTM2_SET_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define XFMC_ATTMEMTM2_SET_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define XFMC_ATTMEMTM2_SET_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define XFMC_ATTMEMTM2_WAIT ((uint32_t)0x0000FF00) /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define XFMC_ATTMEMTM2_WAIT_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_ATTMEMTM2_WAIT_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_ATTMEMTM2_WAIT_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_ATTMEMTM2_WAIT_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define XFMC_ATTMEMTM2_WAIT_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define XFMC_ATTMEMTM2_WAIT_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define XFMC_ATTMEMTM2_WAIT_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define XFMC_ATTMEMTM2_WAIT_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define XFMC_ATTMEMTM2_HLD ((uint32_t)0x00FF0000) /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define XFMC_ATTMEMTM2_HLD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define XFMC_ATTMEMTM2_HLD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define XFMC_ATTMEMTM2_HLD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define XFMC_ATTMEMTM2_HLD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define XFMC_ATTMEMTM2_HLD_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define XFMC_ATTMEMTM2_HLD_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define XFMC_ATTMEMTM2_HLD_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define XFMC_ATTMEMTM2_HLD_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+
+#define XFMC_ATTMEMTM2_HIZ ((uint32_t)0xFF000000) /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define XFMC_ATTMEMTM2_HIZ_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_ATTMEMTM2_HIZ_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_ATTMEMTM2_HIZ_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_ATTMEMTM2_HIZ_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define XFMC_ATTMEMTM2_HIZ_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define XFMC_ATTMEMTM2_HIZ_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define XFMC_ATTMEMTM2_HIZ_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define XFMC_ATTMEMTM2_HIZ_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/****************** Bit definition for XFMC_PATT3 register ******************/
+#define XFMC_ATTMEMTM3_SET ((uint32_t)0x000000FF) /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define XFMC_ATTMEMTM3_SET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_ATTMEMTM3_SET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_ATTMEMTM3_SET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_ATTMEMTM3_SET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define XFMC_ATTMEMTM3_SET_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define XFMC_ATTMEMTM3_SET_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define XFMC_ATTMEMTM3_SET_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define XFMC_ATTMEMTM3_SET_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define XFMC_ATTMEMTM3_WAIT ((uint32_t)0x0000FF00) /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define XFMC_ATTMEMTM3_WAIT_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_ATTMEMTM3_WAIT_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_ATTMEMTM3_WAIT_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_ATTMEMTM3_WAIT_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define XFMC_ATTMEMTM3_WAIT_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define XFMC_ATTMEMTM3_WAIT_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define XFMC_ATTMEMTM3_WAIT_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define XFMC_ATTMEMTM3_WAIT_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define XFMC_ATTMEMTM3_HLD ((uint32_t)0x00FF0000) /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define XFMC_ATTMEMTM3_HLD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define XFMC_ATTMEMTM3_HLD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define XFMC_ATTMEMTM3_HLD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define XFMC_ATTMEMTM3_HLD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define XFMC_ATTMEMTM3_HLD_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define XFMC_ATTMEMTM3_HLD_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define XFMC_ATTMEMTM3_HLD_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define XFMC_ATTMEMTM3_HLD_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+
+#define XFMC_ATTMEMTM3_HIZ ((uint32_t)0xFF000000) /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define XFMC_ATTMEMTM3_HIZ_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_ATTMEMTM3_HIZ_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_ATTMEMTM3_HIZ_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_ATTMEMTM3_HIZ_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define XFMC_ATTMEMTM3_HIZ_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define XFMC_ATTMEMTM3_HIZ_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define XFMC_ATTMEMTM3_HIZ_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define XFMC_ATTMEMTM3_HIZ_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/****************** Bit definition for XFMC_ECCR2 register ******************/
+#define XFMC_ECCR2 ((uint32_t)0xFFFFFFFF) /*!< ECC result */
+
+/****************** Bit definition for XFMC_ECCR3 register ******************/
+#define XFMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!< ECC result */
+
+/******************************************************************************/
+/* */
+/* USB Device FS */
+/* */
+/******************************************************************************/
+
+/*!< Endpoint-specific registers */
+/******************* Bit definition for USB_EP0R register *******************/
+#define USB_EP0_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP0_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP0_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP0_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP0_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP0_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP0_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP0_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP0_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP0_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP0_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP0_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP0_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP0_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP0_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP0_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP1R register *******************/
+#define USB_EP1_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP1_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP1_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP1_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP1_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP1_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP1_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP1_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP1_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP1_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP1_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP1_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP1_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP1_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP1_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP1_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP2R register *******************/
+#define USB_EP2_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP2_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP2_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP2_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP2_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP2_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP2_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP2_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP2_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP2_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP2_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP2_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP2_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP2_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP2_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP2_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP3R register *******************/
+#define USB_EP3_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP3_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP3_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP3_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP3_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP3_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP3_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP3_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP3_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP3_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP3_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP3_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP3_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP3_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP3_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP3_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP4R register *******************/
+#define USB_EP4_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP4_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP4_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP4_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP4_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP4_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP4_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP4_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP4_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP4_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP4_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP4_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP4_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP4_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP4_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP4_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP5R register *******************/
+#define USB_EP5_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP5_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP5_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP5_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP5_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP5_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP5_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP5_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP5_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP5_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP5_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP5_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP5_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP5_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP5_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP5_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP6R register *******************/
+#define USB_EP6_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP6_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP6_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP6_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP6_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP6_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP6_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP6_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP6_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP6_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP6_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP6_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP6_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP6_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP6_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP6_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP7R register *******************/
+#define USB_EP7_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP7_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP7_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP7_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP7_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP7_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP7_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP7_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP7_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP7_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP7_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP7_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP7_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP7_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP7_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP7_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/*!< Common registers */
+/******************* Bit definition for USB_CNTR register *******************/
+#define USB_CTRL_FRST ((uint16_t)0x0001) /*!< Force USB Reset */
+#define USB_CTRL_PD ((uint16_t)0x0002) /*!< Power down */
+#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power mode */
+#define USB_CTRL_FSUSPD ((uint16_t)0x0008) /*!< Force suspend */
+#define USB_CTRL_RESUM ((uint16_t)0x0010) /*!< Resume request */
+#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Interrupt Mask */
+#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Interrupt Mask */
+#define USB_CTRL_RSTM ((uint16_t)0x0400) /*!< RESET Interrupt Mask */
+#define USB_CTRL_SUSPDM ((uint16_t)0x0800) /*!< Suspend mode Interrupt Mask */
+#define USB_CTRL_WKUPM ((uint16_t)0x1000) /*!< Wakeup Interrupt Mask */
+#define USB_CTRL_ERRORM ((uint16_t)0x2000) /*!< Error Interrupt Mask */
+#define USB_CTRL_PMAOM ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun Interrupt Mask */
+#define USB_CTRL_CTRSM ((uint16_t)0x8000) /*!< Correct Transfer Interrupt Mask */
+
+/******************* Bit definition for USB_ISTR register *******************/
+#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< Endpoint Identifier */
+#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< Direction of transaction */
+#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame */
+#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame */
+#define USB_STS_RST ((uint16_t)0x0400) /*!< USB RESET request */
+#define USB_STS_SUSPD ((uint16_t)0x0800) /*!< Suspend mode request */
+#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< Wake up */
+#define USB_STS_ERROR ((uint16_t)0x2000) /*!< Error */
+#define USB_STS_PMAO ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun */
+#define USB_STS_CTRS ((uint16_t)0x8000) /*!< Correct Transfer */
+
+/******************* Bit definition for USB_FNR register ********************/
+#define USB_FN_FNUM ((uint16_t)0x07FF) /*!< Frame Number */
+#define USB_FN_LSTSOF ((uint16_t)0x1800) /*!< Lost SOF */
+#define USB_FNR_LCK ((uint16_t)0x2000) /*!< Locked */
+#define USB_FN_RXDM_STS ((uint16_t)0x4000) /*!< Receive Data - Line Status */
+#define USB_FN_RXDP_STS ((uint16_t)0x8000) /*!< Receive Data + Line Status */
+
+/****************** Bit definition for USB_DADDR register *******************/
+#define USB_ADDR_ADDR ((uint8_t)0x7F) /*!< ADD[6:0] bits (Device Address) */
+#define USB_ADDR_ADDR0 ((uint8_t)0x01) /*!< Bit 0 */
+#define USB_ADDR_ADDR1 ((uint8_t)0x02) /*!< Bit 1 */
+#define USB_ADDR_ADDR2 ((uint8_t)0x04) /*!< Bit 2 */
+#define USB_ADDR_ADDR3 ((uint8_t)0x08) /*!< Bit 3 */
+#define USB_ADDR_ADDR4 ((uint8_t)0x10) /*!< Bit 4 */
+#define USB_ADDR_ADDR5 ((uint8_t)0x20) /*!< Bit 5 */
+#define USB_ADDR_ADDR6 ((uint8_t)0x40) /*!< Bit 6 */
+
+#define USB_ADDR_EFUC ((uint8_t)0x80) /*!< Enable Function */
+
+/****************** Bit definition for USB_BTABLE register ******************/
+#define USB_BUFTAB_BUFTAB ((uint16_t)0xFFF8) /*!< Buffer Table */
+
+/*!< Buffer descriptor table */
+/***************** Bit definition for USB_ADDR0_TX register *****************/
+#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_TX register *****************/
+#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_TX register *****************/
+#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_TX register *****************/
+#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_TX register *****************/
+#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_TX register *****************/
+#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_TX register *****************/
+#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_TX register *****************/
+#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_TX register ****************/
+#define USB_CNT0_TX_CNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */
+
+/***************** Bit definition for USB_COUNT1_TX register ****************/
+#define USB_CNT1_TX_CNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */
+
+/***************** Bit definition for USB_COUNT2_TX register ****************/
+#define USB_CNT2_TX_CNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */
+
+/***************** Bit definition for USB_COUNT3_TX register ****************/
+#define USB_CNT3_TX_CNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */
+
+/***************** Bit definition for USB_COUNT4_TX register ****************/
+#define USB_CNT4_TX_CNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */
+
+/***************** Bit definition for USB_COUNT5_TX register ****************/
+#define USB_CNT5_TX_CNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */
+
+/***************** Bit definition for USB_COUNT6_TX register ****************/
+#define USB_CNT6_TX_CNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */
+
+/***************** Bit definition for USB_COUNT7_TX register ****************/
+#define USB_CNT7_TX_CNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
+#define USB_CNT0_TX_0_CNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
+
+/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
+#define USB_CNT0_TX_1_CNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
+
+/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
+#define USB_CNT1_TX_0_CNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
+
+/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
+#define USB_CNT1_TX_1_CNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
+
+/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
+#define USB_CNT2_TX_0_CNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
+
+/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
+#define USB_CNT2_TX_1_CNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
+
+/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
+#define USB_CNT3_TX_0_CNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */
+
+/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
+#define USB_CNT3_TX_1_CNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */
+
+/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
+#define USB_CNT4_TX_0_CNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
+
+/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
+#define USB_CNT4_TX_1_CNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
+
+/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
+#define USB_CNT5_TX_0_CNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
+
+/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
+#define USB_CNT5_TX_1_CNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
+
+/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
+#define USB_CNT6_TX_0_CNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
+
+/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
+#define USB_CNT6_TX_1_CNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
+
+/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
+#define USB_CNT7_TX_0_CNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
+
+/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
+#define USB_CNT7_TX_1_CNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_ADDR0_RX register *****************/
+#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_RX register *****************/
+#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_RX register *****************/
+#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_RX register *****************/
+#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_RX register *****************/
+#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_RX register *****************/
+#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_RX register *****************/
+#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_RX register *****************/
+#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_RX register ****************/
+#define USB_CNT0_RX_CNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT0_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT0_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT0_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT0_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT0_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT0_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT1_RX register ****************/
+#define USB_CNT1_RX_CNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT1_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT1_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT1_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT1_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT1_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT1_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT2_RX register ****************/
+#define USB_CNT2_RX_CNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT2_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT2_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT2_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT2_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT2_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT2_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT3_RX register ****************/
+#define USB_CNT3_RX_CNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT3_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT3_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT3_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT3_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT3_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT3_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT4_RX register ****************/
+#define USB_CNT4_RX_CNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT4_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT4_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT4_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT4_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT4_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT4_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT5_RX register ****************/
+#define USB_CNT5_RX_CNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT5_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT5_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT5_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT5_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT5_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT5_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT6_RX register ****************/
+#define USB_CNT6_RX_CNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT6_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT6_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT6_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT6_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT6_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT6_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT7_RX register ****************/
+#define USB_CNT7_RX_CNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT7_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT7_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT7_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT7_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT7_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT7_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
+#define USB_CNT0_RX_0_CNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT0_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT0_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT0_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT0_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT0_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT0_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
+#define USB_CNT0_RX_1_CNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT0_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT0_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define USB_CNT0_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT0_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT0_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT0_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
+#define USB_CNT1_RX_0_CNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT1_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT1_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT1_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT1_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT1_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT1_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
+#define USB_CNT1_RX_1_CNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT1_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT1_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_CNT1_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT1_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT1_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT1_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
+#define USB_CNT2_RX_0_CNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT2_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT2_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT2_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT2_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT2_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT2_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
+#define USB_CNT2_RX_1_CNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT2_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT2_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_CNT2_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT2_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT2_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT2_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
+#define USB_CNT3_RX_0_CNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT3_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT3_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT3_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT3_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT3_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT3_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
+#define USB_CNT3_RX_1_CNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT3_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT3_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_CNT3_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT3_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT3_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT3_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
+#define USB_CNT4_RX_0_CNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT4_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT4_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT4_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT4_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT4_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT4_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
+#define USB_CNT4_RX_1_CNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT4_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT4_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_CNT4_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT4_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT4_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT4_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
+#define USB_CNT5_RX_0_CNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT5_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT5_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT5_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT5_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT5_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT5_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
+#define USB_CNT5_RX_1_CNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT5_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT5_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_CNT5_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT5_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT5_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT5_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
+#define USB_CNT6_RX_0_CNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT6_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT6_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT6_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT6_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT6_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT6_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
+#define USB_CNT6_RX_1_CNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT6_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT6_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_CNT6_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT6_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT6_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT6_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
+#define USB_CNT7_RX_0_CNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT7_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT7_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT7_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT7_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT7_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT7_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
+#define USB_CNT7_RX_1_CNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT7_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT7_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_CNT7_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT7_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT7_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT7_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+
+/*!< CAN control and status registers */
+/******************* Bit definition for CAN_MCTRL register ********************/
+#define CAN_MCTRL_INIRQ ((uint16_t)0x0001) /*!< Initialization Request */
+#define CAN_MCTRL_SLPRQ ((uint16_t)0x0002) /*!< Sleep Mode Request */
+#define CAN_MCTRL_TXFP ((uint16_t)0x0004) /*!< Transmit DATFIFO Priority */
+#define CAN_MCTRL_RFLM ((uint16_t)0x0008) /*!< Receive DATFIFO Locked Mode */
+#define CAN_MCTRL_NART ((uint16_t)0x0010) /*!< No Automatic Retransmission */
+#define CAN_MCTRL_AWKUM ((uint16_t)0x0020) /*!< Automatic Wakeup Mode */
+#define CAN_MCTRL_ABOM ((uint16_t)0x0040) /*!< Automatic Bus-Off Management */
+#define CAN_MCTRL_TTCM ((uint16_t)0x0080) /*!< Time Triggered Communication Mode */
+#define CAN_MCTRL_MRST ((uint16_t)0x8000) /*!< CAN software master reset */
+#define CAN_MCTRL_DBGF ((uint32_t)0x00010000) /*!< CAN Debug freeze */
+
+/******************* Bit definition for CAN_MSTS register ********************/
+#define CAN_MSTS_INIAK ((uint16_t)0x0001) /*!< Initialization Acknowledge */
+#define CAN_MSTS_SLPAK ((uint16_t)0x0002) /*!< Sleep Acknowledge */
+#define CAN_MSTS_ERRINT ((uint16_t)0x0004) /*!< Error Interrupt */
+#define CAN_MSTS_WKUINT ((uint16_t)0x0008) /*!< Wakeup Interrupt */
+#define CAN_MSTS_SLAKINT ((uint16_t)0x0010) /*!< Sleep Acknowledge Interrupt */
+#define CAN_MSTS_TXMD ((uint16_t)0x0100) /*!< Transmit Mode */
+#define CAN_MSTS_RXMD ((uint16_t)0x0200) /*!< Receive Mode */
+#define CAN_MSTS_LSMP ((uint16_t)0x0400) /*!< Last Sample Point */
+#define CAN_MSTS_RXS ((uint16_t)0x0800) /*!< CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSTS register ********************/
+#define CAN_TSTS_RQCPM0 ((uint32_t)0x00000001) /*!< Request Completed Mailbox0 */
+#define CAN_TSTS_TXOKM0 ((uint32_t)0x00000002) /*!< Transmission OK of Mailbox0 */
+#define CAN_TSTS_ALSTM0 ((uint32_t)0x00000004) /*!< Arbitration Lost for Mailbox0 */
+#define CAN_TSTS_TERRM0 ((uint32_t)0x00000008) /*!< Transmission Error of Mailbox0 */
+#define CAN_TSTS_ABRQM0 ((uint32_t)0x00000080) /*!< Abort Request for Mailbox0 */
+#define CAN_TSTS_RQCPM1 ((uint32_t)0x00000100) /*!< Request Completed Mailbox1 */
+#define CAN_TSTS_TXOKM1 ((uint32_t)0x00000200) /*!< Transmission OK of Mailbox1 */
+#define CAN_TSTS_ALSTM1 ((uint32_t)0x00000400) /*!< Arbitration Lost for Mailbox1 */
+#define CAN_TSTS_TERRM1 ((uint32_t)0x00000800) /*!< Transmission Error of Mailbox1 */
+#define CAN_TSTS_ABRQM1 ((uint32_t)0x00008000) /*!< Abort Request for Mailbox 1 */
+#define CAN_TSTS_RQCPM2 ((uint32_t)0x00010000) /*!< Request Completed Mailbox2 */
+#define CAN_TSTS_TXOKM2 ((uint32_t)0x00020000) /*!< Transmission OK of Mailbox 2 */
+#define CAN_TSTS_ALSTM2 ((uint32_t)0x00040000) /*!< Arbitration Lost for mailbox 2 */
+#define CAN_TSTS_TERRM2 ((uint32_t)0x00080000) /*!< Transmission Error of Mailbox 2 */
+#define CAN_TSTS_ABRQM2 ((uint32_t)0x00800000) /*!< Abort Request for Mailbox 2 */
+#define CAN_TSTS_CODE ((uint32_t)0x03000000) /*!< Mailbox Code */
+
+#define CAN_TSTS_TMEM ((uint32_t)0x1C000000) /*!< TME[2:0] bits */
+#define CAN_TSTS_TMEM0 ((uint32_t)0x04000000) /*!< Transmit Mailbox 0 Empty */
+#define CAN_TSTS_TMEM1 ((uint32_t)0x08000000) /*!< Transmit Mailbox 1 Empty */
+#define CAN_TSTS_TMEM2 ((uint32_t)0x10000000) /*!< Transmit Mailbox 2 Empty */
+
+#define CAN_TSTS_LOWM ((uint32_t)0xE0000000) /*!< LOW[2:0] bits */
+#define CAN_TSTS_LOWM0 ((uint32_t)0x20000000) /*!< Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSTS_LOWM1 ((uint32_t)0x40000000) /*!< Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSTS_LOWM2 ((uint32_t)0x80000000) /*!< Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RFF0 register *******************/
+#define CAN_RFF0_FFMP0 ((uint8_t)0x03) /*!< DATFIFO 0 Message Pending */
+#define CAN_RFF0_FFULL0 ((uint8_t)0x08) /*!< DATFIFO 0 Full */
+#define CAN_RFF0_FFOVR0 ((uint8_t)0x10) /*!< DATFIFO 0 Overrun */
+#define CAN_RFF0_RFFOM0 ((uint8_t)0x20) /*!< Release DATFIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RFF1 register *******************/
+#define CAN_RFF1_FFMP1 ((uint8_t)0x03) /*!< DATFIFO 1 Message Pending */
+#define CAN_RFF1_FFULL1 ((uint8_t)0x08) /*!< DATFIFO 1 Full */
+#define CAN_RFF1_FFOVR1 ((uint8_t)0x10) /*!< DATFIFO 1 Overrun */
+#define CAN_RFF1_RFFOM1 ((uint8_t)0x20) /*!< Release DATFIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_INTE register *******************/
+#define CAN_INTE_TMEITE ((uint32_t)0x00000001) /*!< Transmit Mailbox Empty Interrupt Enable */
+#define CAN_INTE_FMPITE0 ((uint32_t)0x00000002) /*!< DATFIFO Message Pending Interrupt Enable */
+#define CAN_INTE_FFITE0 ((uint32_t)0x00000004) /*!< DATFIFO Full Interrupt Enable */
+#define CAN_INTE_FOVITE0 ((uint32_t)0x00000008) /*!< DATFIFO Overrun Interrupt Enable */
+#define CAN_INTE_FMPITE1 ((uint32_t)0x00000010) /*!< DATFIFO Message Pending Interrupt Enable */
+#define CAN_INTE_FFITE1 ((uint32_t)0x00000020) /*!< DATFIFO Full Interrupt Enable */
+#define CAN_INTE_FOVITE1 ((uint32_t)0x00000040) /*!< DATFIFO Overrun Interrupt Enable */
+#define CAN_INTE_EWGITE ((uint32_t)0x00000100) /*!< Error Warning Interrupt Enable */
+#define CAN_INTE_EPVITE ((uint32_t)0x00000200) /*!< Error Passive Interrupt Enable */
+#define CAN_INTE_BOFITE ((uint32_t)0x00000400) /*!< Bus-Off Interrupt Enable */
+#define CAN_INTE_LECITE ((uint32_t)0x00000800) /*!< Last Error Code Interrupt Enable */
+#define CAN_INTE_ERRITE ((uint32_t)0x00008000) /*!< Error Interrupt Enable */
+#define CAN_INTE_WKUITE ((uint32_t)0x00010000) /*!< Wakeup Interrupt Enable */
+#define CAN_INTE_SLKITE ((uint32_t)0x00020000) /*!< Sleep Interrupt Enable */
+
+/******************** Bit definition for CAN_ESTS register *******************/
+#define CAN_ESTS_EWGFL ((uint32_t)0x00000001) /*!< Error Warning Flag */
+#define CAN_ESTS_EPVFL ((uint32_t)0x00000002) /*!< Error Passive Flag */
+#define CAN_ESTS_BOFFL ((uint32_t)0x00000004) /*!< Bus-Off Flag */
+
+#define CAN_ESTS_LEC ((uint32_t)0x00000070) /*!< LEC[2:0] bits (Last Error Code) */
+#define CAN_ESTS_LEC_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define CAN_ESTS_LEC_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define CAN_ESTS_LEC_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+
+#define CAN_ESTS_TXEC ((uint32_t)0x00FF0000) /*!< Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESTS_RXEC ((uint32_t)0xFF000000) /*!< Receive Error Counter */
+
+/******************* Bit definition for CAN_BTIM register ********************/
+#define CAN_BTIM_BRTP ((uint32_t)0x000003FF) /*!< Baud Rate Prescaler */
+#define CAN_BTIM_TBS1 ((uint32_t)0x000F0000) /*!< Time Segment 1 */
+#define CAN_BTIM_TBS2 ((uint32_t)0x00700000) /*!< Time Segment 2 */
+#define CAN_BTIM_RSJW ((uint32_t)0x03000000) /*!< Resynchronization Jump Width */
+#define CAN_BTIM_LBM ((uint32_t)0x40000000) /*!< Loop Back Mode (Debug) */
+#define CAN_BTIM_SLM ((uint32_t)0x80000000) /*!< Silent Mode */
+
+/*!< Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TMI0_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
+#define CAN_TMI0_RTRQ ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_TMI0_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_TMI0_EXTID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
+#define CAN_TMI0_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TMDT0_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_TMDT0_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */
+#define CAN_TMDT0_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TMDL0_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_TMDL0_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_TMDL0_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_TMDL0_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TMDH0_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_TMDH0_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_TMDH0_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_TMDH0_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TMI1_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
+#define CAN_TMI1_RTRQ ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_TMI1_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_TMI1_EXTID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
+#define CAN_TMI1_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TMDT1_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_TMDT1_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */
+#define CAN_TMDT1_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TMDL1_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_TMDL1_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_TMDL1_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_TMDL1_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TMDH1_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_TMDH1_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_TMDH1_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_TMDH1_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TMI2_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
+#define CAN_TMI2_RTRQ ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_TMI2_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_TMI2_EXTID ((uint32_t)0x001FFFF8) /*!< Extended identifier */
+#define CAN_TMI2_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TMDT2_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_TMDT2_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */
+#define CAN_TMDT2_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TMDL2_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_TMDL2_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_TMDL2_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_TMDL2_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TMDH2_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_TMDH2_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_TMDH2_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_TMDH2_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RMI0_RTRQ ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_RMI0_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_RMI0_EXTID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
+#define CAN_RMI0_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RMDT0_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_RMDT0_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */
+#define CAN_RMDT0_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RMDL0_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_RMDL0_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_RMDL0_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_RMDL0_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RMDH0_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_RMDH0_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_RMDH0_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_RMDH0_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RMI1_RTRQ ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_RMI1_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_RMI1_EXTID ((uint32_t)0x001FFFF8) /*!< Extended identifier */
+#define CAN_RMI1_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RMDT1_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_RMDT1_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */
+#define CAN_RMDT1_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RMDL1_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_RMDL1_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_RMDL1_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_RMDL1_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RMDH1_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_RMDH1_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_RMDH1_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_RMDH1_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/*!< CAN filter registers */
+/******************* Bit definition for CAN_FMC register ********************/
+#define CAN_FMC_FINITM ((uint8_t)0x01) /*!< Filter Init Mode */
+
+/******************* Bit definition for CAN_FM1 register *******************/
+#define CAN_FM1_FB ((uint16_t)0x3FFF) /*!< Filter Mode */
+#define CAN_FM1_FB0 ((uint16_t)0x0001) /*!< Filter Init Mode bit 0 */
+#define CAN_FM1_FB1 ((uint16_t)0x0002) /*!< Filter Init Mode bit 1 */
+#define CAN_FM1_FB2 ((uint16_t)0x0004) /*!< Filter Init Mode bit 2 */
+#define CAN_FM1_FB3 ((uint16_t)0x0008) /*!< Filter Init Mode bit 3 */
+#define CAN_FM1_FB4 ((uint16_t)0x0010) /*!< Filter Init Mode bit 4 */
+#define CAN_FM1_FB5 ((uint16_t)0x0020) /*!< Filter Init Mode bit 5 */
+#define CAN_FM1_FB6 ((uint16_t)0x0040) /*!< Filter Init Mode bit 6 */
+#define CAN_FM1_FB7 ((uint16_t)0x0080) /*!< Filter Init Mode bit 7 */
+#define CAN_FM1_FB8 ((uint16_t)0x0100) /*!< Filter Init Mode bit 8 */
+#define CAN_FM1_FB9 ((uint16_t)0x0200) /*!< Filter Init Mode bit 9 */
+#define CAN_FM1_FB10 ((uint16_t)0x0400) /*!< Filter Init Mode bit 10 */
+#define CAN_FM1_FB11 ((uint16_t)0x0800) /*!< Filter Init Mode bit 11 */
+#define CAN_FM1_FB12 ((uint16_t)0x1000) /*!< Filter Init Mode bit 12 */
+#define CAN_FM1_FB13 ((uint16_t)0x2000) /*!< Filter Init Mode bit 13 */
+
+/******************* Bit definition for CAN_FS1 register *******************/
+#define CAN_FS1_FSC ((uint16_t)0x3FFF) /*!< Filter Scale Configuration */
+#define CAN_FS1_FSC0 ((uint16_t)0x0001) /*!< Filter Scale Configuration bit 0 */
+#define CAN_FS1_FSC1 ((uint16_t)0x0002) /*!< Filter Scale Configuration bit 1 */
+#define CAN_FS1_FSC2 ((uint16_t)0x0004) /*!< Filter Scale Configuration bit 2 */
+#define CAN_FS1_FSC3 ((uint16_t)0x0008) /*!< Filter Scale Configuration bit 3 */
+#define CAN_FS1_FSC4 ((uint16_t)0x0010) /*!< Filter Scale Configuration bit 4 */
+#define CAN_FS1_FSC5 ((uint16_t)0x0020) /*!< Filter Scale Configuration bit 5 */
+#define CAN_FS1_FSC6 ((uint16_t)0x0040) /*!< Filter Scale Configuration bit 6 */
+#define CAN_FS1_FSC7 ((uint16_t)0x0080) /*!< Filter Scale Configuration bit 7 */
+#define CAN_FS1_FSC8 ((uint16_t)0x0100) /*!< Filter Scale Configuration bit 8 */
+#define CAN_FS1_FSC9 ((uint16_t)0x0200) /*!< Filter Scale Configuration bit 9 */
+#define CAN_FS1_FSC10 ((uint16_t)0x0400) /*!< Filter Scale Configuration bit 10 */
+#define CAN_FS1_FSC11 ((uint16_t)0x0800) /*!< Filter Scale Configuration bit 11 */
+#define CAN_FS1_FSC12 ((uint16_t)0x1000) /*!< Filter Scale Configuration bit 12 */
+#define CAN_FS1_FSC13 ((uint16_t)0x2000) /*!< Filter Scale Configuration bit 13 */
+
+/****************** Bit definition for CAN_FFA1 register *******************/
+#define CAN_FFA1_FAF ((uint16_t)0x3FFF) /*!< Filter DATFIFO Assignment */
+#define CAN_FFA1_FAF0 ((uint16_t)0x0001) /*!< Filter DATFIFO Assignment for Filter 0 */
+#define CAN_FFA1_FAF1 ((uint16_t)0x0002) /*!< Filter DATFIFO Assignment for Filter 1 */
+#define CAN_FFA1_FAF2 ((uint16_t)0x0004) /*!< Filter DATFIFO Assignment for Filter 2 */
+#define CAN_FFA1_FAF3 ((uint16_t)0x0008) /*!< Filter DATFIFO Assignment for Filter 3 */
+#define CAN_FFA1_FAF4 ((uint16_t)0x0010) /*!< Filter DATFIFO Assignment for Filter 4 */
+#define CAN_FFA1_FAF5 ((uint16_t)0x0020) /*!< Filter DATFIFO Assignment for Filter 5 */
+#define CAN_FFA1_FAF6 ((uint16_t)0x0040) /*!< Filter DATFIFO Assignment for Filter 6 */
+#define CAN_FFA1_FAF7 ((uint16_t)0x0080) /*!< Filter DATFIFO Assignment for Filter 7 */
+#define CAN_FFA1_FAF8 ((uint16_t)0x0100) /*!< Filter DATFIFO Assignment for Filter 8 */
+#define CAN_FFA1_FAF9 ((uint16_t)0x0200) /*!< Filter DATFIFO Assignment for Filter 9 */
+#define CAN_FFA1_FAF10 ((uint16_t)0x0400) /*!< Filter DATFIFO Assignment for Filter 10 */
+#define CAN_FFA1_FAF11 ((uint16_t)0x0800) /*!< Filter DATFIFO Assignment for Filter 11 */
+#define CAN_FFA1_FAF12 ((uint16_t)0x1000) /*!< Filter DATFIFO Assignment for Filter 12 */
+#define CAN_FFA1_FAF13 ((uint16_t)0x2000) /*!< Filter DATFIFO Assignment for Filter 13 */
+
+/******************* Bit definition for CAN_FA1 register *******************/
+#define CAN_FA1_FAC ((uint16_t)0x3FFF) /*!< Filter Active */
+#define CAN_FA1_FAC0 ((uint16_t)0x0001) /*!< Filter 0 Active */
+#define CAN_FA1_FAC1 ((uint16_t)0x0002) /*!< Filter 1 Active */
+#define CAN_FA1_FAC2 ((uint16_t)0x0004) /*!< Filter 2 Active */
+#define CAN_FA1_FAC3 ((uint16_t)0x0008) /*!< Filter 3 Active */
+#define CAN_FA1_FAC4 ((uint16_t)0x0010) /*!< Filter 4 Active */
+#define CAN_FA1_FAC5 ((uint16_t)0x0020) /*!< Filter 5 Active */
+#define CAN_FA1_FAC6 ((uint16_t)0x0040) /*!< Filter 6 Active */
+#define CAN_FA1_FAC7 ((uint16_t)0x0080) /*!< Filter 7 Active */
+#define CAN_FA1_FAC8 ((uint16_t)0x0100) /*!< Filter 8 Active */
+#define CAN_FA1_FAC9 ((uint16_t)0x0200) /*!< Filter 9 Active */
+#define CAN_FA1_FAC10 ((uint16_t)0x0400) /*!< Filter 10 Active */
+#define CAN_FA1_FAC11 ((uint16_t)0x0800) /*!< Filter 11 Active */
+#define CAN_FA1_FAC12 ((uint16_t)0x1000) /*!< Filter 12 Active */
+#define CAN_FA1_FAC13 ((uint16_t)0x2000) /*!< Filter 13 Active */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F0B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F0B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F0B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F0B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F0B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F0B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F0B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F0B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F0B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F0B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F0B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F0B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F0B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F0B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F0B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F0B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F0B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F0B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F0B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F0B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F0B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F0B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F0B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F0B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F0B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F0B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F0B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F0B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F0B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F0B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F0B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F1B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F1B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F1B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F1B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F1B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F1B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F1B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F1B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F1B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F1B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F1B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F1B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F1B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F1B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F1B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F1B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F1B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F1B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F1B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F1B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F1B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F1B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F1B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F1B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F1B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F1B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F1B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F1B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F1B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F1B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F1B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F2B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F2B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F2B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F2B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F2B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F2B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F2B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F2B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F2B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F2B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F2B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F2B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F2B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F2B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F2B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F2B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F2B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F2B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F2B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F2B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F2B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F2B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F2B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F2B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F2B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F2B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F2B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F2B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F2B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F2B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F2B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F3B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F3B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F3B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F3B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F3B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F3B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F3B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F3B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F3B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F3B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F3B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F3B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F3B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F3B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F3B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F3B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F3B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F3B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F3B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F3B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F3B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F3B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F3B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F3B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F3B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F3B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F3B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F3B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F3B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F3B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F3B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F4B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F4B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F4B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F4B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F4B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F4B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F4B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F4B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F4B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F4B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F4B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F4B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F4B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F4B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F4B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F4B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F4B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F4B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F4B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F4B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F4B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F4B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F4B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F4B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F4B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F4B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F4B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F4B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F4B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F4B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F4B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F5B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F5B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F5B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F5B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F5B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F5B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F5B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F5B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F5B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F5B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F5B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F5B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F5B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F5B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F5B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F5B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F5B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F5B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F5B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F5B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F5B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F5B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F5B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F5B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F5B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F5B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F5B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F5B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F5B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F5B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F5B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F6B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F6B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F6B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F6B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F6B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F6B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F6B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F6B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F6B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F6B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F6B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F6B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F6B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F6B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F6B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F6B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F6B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F6B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F6B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F6B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F6B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F6B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F6B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F6B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F6B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F6B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F6B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F6B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F6B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F6B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F6B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F7B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F7B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F7B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F7B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F7B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F7B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F7B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F7B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F7B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F7B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F7B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F7B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F7B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F7B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F7B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F7B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F7B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F7B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F7B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F7B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F7B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F7B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F7B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F7B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F7B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F7B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F7B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F7B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F7B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F7B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F7B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F8B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F8B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F8B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F8B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F8B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F8B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F8B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F8B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F8B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F8B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F8B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F8B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F8B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F8B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F8B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F8B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F8B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F8B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F8B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F8B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F8B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F8B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F8B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F8B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F8B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F8B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F8B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F8B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F8B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F8B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F8B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F9B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F9B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F9B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F9B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F9B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F9B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F9B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F9B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F9B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F9B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F9B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F9B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F9B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F9B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F9B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F9B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F9B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F9B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F9B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F9B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F9B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F9B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F9B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F9B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F9B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F9B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F9B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F9B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F9B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F9B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F9B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F10B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F10B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F10B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F10B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F10B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F10B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F10B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F10B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F10B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F10B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F10B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F10B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F10B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F10B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F10B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F10B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F10B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F10B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F10B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F10B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F10B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F10B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F10B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F10B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F10B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F10B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F10B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F10B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F10B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F10B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F10B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F11B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F11B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F11B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F11B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F11B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F11B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F11B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F11B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F11B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F11B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F11B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F11B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F11B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F11B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F11B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F11B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F11B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F11B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F11B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F11B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F11B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F11B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F11B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F11B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F11B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F11B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F11B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F11B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F11B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F11B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F11B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F12B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F12B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F12B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F12B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F12B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F12B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F12B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F12B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F12B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F12B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F12B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F12B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F12B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F12B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F12B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F12B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F12B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F12B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F12B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F12B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F12B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F12B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F12B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F12B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F12B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F12B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F12B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F12B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F12B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F12B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F12B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F13B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F13B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F13B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F13B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F13B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F13B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F13B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F13B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F13B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F13B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F13B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F13B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F13B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F13B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F13B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F13B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F13B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F13B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F13B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F13B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F13B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F13B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F13B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F13B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F13B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F13B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F13B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F13B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F13B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F13B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F13B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F0B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F0B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F0B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F0B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F0B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F0B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F0B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F0B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F0B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F0B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F0B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F0B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F0B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F0B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F0B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F0B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F0B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F0B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F0B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F0B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F0B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F0B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F0B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F0B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F0B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F0B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F0B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F0B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F0B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F0B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F0B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F1B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F1B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F1B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F1B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F1B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F1B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F1B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F1B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F1B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F1B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F1B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F1B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F1B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F1B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F1B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F1B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F1B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F1B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F1B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F1B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F1B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F1B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F1B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F1B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F1B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F1B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F1B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F1B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F1B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F1B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F1B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F2B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F2B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F2B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F2B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F2B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F2B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F2B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F2B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F2B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F2B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F2B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F2B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F2B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F2B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F2B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F2B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F2B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F2B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F2B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F2B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F2B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F2B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F2B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F2B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F2B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F2B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F2B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F2B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F2B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F2B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F2B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F3B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F3B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F3B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F3B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F3B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F3B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F3B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F3B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F3B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F3B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F3B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F3B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F3B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F3B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F3B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F3B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F3B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F3B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F3B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F3B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F3B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F3B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F3B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F3B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F3B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F3B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F3B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F3B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F3B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F3B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F3B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F4B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F4B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F4B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F4B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F4B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F4B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F4B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F4B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F4B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F4B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F4B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F4B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F4B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F4B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F4B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F4B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F4B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F4B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F4B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F4B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F4B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F4B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F4B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F4B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F4B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F4B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F4B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F4B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F4B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F4B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F4B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F5B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F5B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F5B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F5B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F5B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F5B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F5B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F5B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F5B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F5B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F5B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F5B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F5B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F5B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F5B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F5B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F5B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F5B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F5B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F5B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F5B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F5B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F5B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F5B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F5B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F5B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F5B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F5B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F5B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F5B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F5B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F6B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F6B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F6B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F6B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F6B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F6B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F6B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F6B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F6B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F6B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F6B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F6B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F6B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F6B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F6B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F6B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F6B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F6B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F6B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F6B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F6B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F6B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F6B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F6B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F6B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F6B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F6B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F6B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F6B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F6B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F6B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F7B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F7B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F7B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F7B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F7B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F7B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F7B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F7B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F7B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F7B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F7B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F7B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F7B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F7B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F7B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F7B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F7B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F7B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F7B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F7B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F7B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F7B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F7B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F7B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F7B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F7B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F7B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F7B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F7B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F7B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F7B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F8B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F8B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F8B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F8B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F8B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F8B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F8B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F8B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F8B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F8B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F8B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F8B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F8B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F8B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F8B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F8B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F8B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F8B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F8B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F8B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F8B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F8B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F8B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F8B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F8B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F8B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F8B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F8B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F8B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F8B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F8B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F9B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F9B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F9B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F9B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F9B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F9B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F9B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F9B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F9B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F9B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F9B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F9B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F9B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F9B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F9B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F9B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F9B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F9B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F9B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F9B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F9B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F9B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F9B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F9B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F9B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F9B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F9B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F9B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F9B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F9B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F9B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F10B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F10B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F10B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F10B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F10B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F10B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F10B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F10B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F10B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F10B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F10B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F10B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F10B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F10B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F10B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F10B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F10B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F10B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F10B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F10B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F10B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F10B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F10B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F10B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F10B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F10B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F10B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F10B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F10B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F10B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F10B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F11B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F11B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F11B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F11B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F11B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F11B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F11B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F11B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F11B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F11B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F11B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F11B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F11B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F11B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F11B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F11B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F11B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F11B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F11B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F11B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F11B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F11B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F11B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F11B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F11B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F11B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F11B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F11B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F11B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F11B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F11B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F12B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F12B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F12B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F12B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F12B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F12B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F12B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F12B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F12B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F12B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F12B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F12B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F12B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F12B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F12B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F12B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F12B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F12B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F12B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F12B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F12B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F12B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F12B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F12B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F12B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F12B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F12B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F12B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F12B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F12B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F12B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F13B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F13B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F13B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F13B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F13B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F13B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F13B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F13B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F13B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F13B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F13B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F13B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F13B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F13B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F13B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F13B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F13B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F13B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F13B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F13B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F13B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F13B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F13B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F13B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F13B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F13B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F13B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F13B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F13B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F13B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F13B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for SPI_CTRL1 register ********************/
+#define SPI_CTRL1_CLKPHA ((uint16_t)0x0001) /*!< Clock Phase */
+#define SPI_CTRL1_CLKPOL ((uint16_t)0x0002) /*!< Clock Polarity */
+#define SPI_CTRL1_MSEL ((uint16_t)0x0004) /*!< Master Selection */
+
+#define SPI_CTRL1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CTRL1_BR0 ((uint16_t)0x0008) /*!< Bit 0 */
+#define SPI_CTRL1_BR1 ((uint16_t)0x0010) /*!< Bit 1 */
+#define SPI_CTRL1_BR2 ((uint16_t)0x0020) /*!< Bit 2 */
+
+#define SPI_CTRL1_SPIEN ((uint16_t)0x0040) /*!< SPI Enable */
+#define SPI_CTRL1_LSBFF ((uint16_t)0x0080) /*!< Frame Format */
+#define SPI_CTRL1_SSEL ((uint16_t)0x0100) /*!< Internal slave select */
+#define SPI_CTRL1_SSMEN ((uint16_t)0x0200) /*!< Software slave management */
+#define SPI_CTRL1_RONLY ((uint16_t)0x0400) /*!< Receive only */
+#define SPI_CTRL1_DATFF ((uint16_t)0x0800) /*!< Data Frame Format */
+#define SPI_CTRL1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */
+#define SPI_CTRL1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */
+#define SPI_CTRL1_BIDIROEN ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */
+#define SPI_CTRL1_BIDIRMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CTRL2 register ********************/
+#define SPI_CTRL2_RDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */
+#define SPI_CTRL2_TDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */
+#define SPI_CTRL2_SSOEN ((uint8_t)0x04) /*!< SS Output Enable */
+#define SPI_CTRL2_ERRINTEN ((uint8_t)0x20) /*!< Error Interrupt Enable */
+#define SPI_CTRL2_RNEINTEN ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CTRL2_TEINTEN ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_STS register ********************/
+#define SPI_STS_RNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */
+#define SPI_STS_TE ((uint8_t)0x02) /*!< Transmit buffer Empty */
+#define SPI_STS_CHSIDE ((uint8_t)0x04) /*!< Channel side */
+#define SPI_STS_UNDER ((uint8_t)0x08) /*!< Underrun flag */
+#define SPI_STS_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */
+#define SPI_STS_MODERR ((uint8_t)0x20) /*!< Mode fault */
+#define SPI_STS_OVER ((uint8_t)0x40) /*!< Overrun flag */
+#define SPI_STS_BUSY ((uint8_t)0x80) /*!< Busy flag */
+
+/******************** Bit definition for SPI_DAT register ********************/
+#define SPI_DAT_DAT ((uint16_t)0xFFFF) /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPOLY register ******************/
+#define SPI_CRCPOLY_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_CRCRDAT register ******************/
+#define SPI_CRCRDAT_CRCRDAT ((uint16_t)0xFFFF) /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_CRCTDAT register ******************/
+#define SPI_CRCTDAT_CRCTDAT ((uint16_t)0xFFFF) /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFG register *****************/
+#define SPI_I2SCFG_CHBITS ((uint16_t)0x0001) /*!< Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFG_TDATLEN ((uint16_t)0x0006) /*!< TDATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFG_TDATLEN0 ((uint16_t)0x0002) /*!< Bit 0 */
+#define SPI_I2SCFG_TDATLEN1 ((uint16_t)0x0004) /*!< Bit 1 */
+
+#define SPI_I2SCFG_CLKPOL ((uint16_t)0x0008) /*!< steady state clock polarity */
+
+#define SPI_I2SCFG_STDSEL ((uint16_t)0x0030) /*!< STDSEL[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFG_STDSEL0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define SPI_I2SCFG_STDSEL1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define SPI_I2SCFG_PCMFSYNC ((uint16_t)0x0080) /*!< PCM frame synchronization */
+
+#define SPI_I2SCFG_MODCFG ((uint16_t)0x0300) /*!< MODCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFG_MODCFG0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define SPI_I2SCFG_MODCFG1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define SPI_I2SCFG_I2SEN ((uint16_t)0x0400) /*!< I2S Enable */
+#define SPI_I2SCFG_MODSEL ((uint16_t)0x0800) /*!< I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPREDIV register *******************/
+#define SPI_I2SPREDIV_LDIV ((uint16_t)0x00FF) /*!< I2S Linear prescaler */
+#define SPI_I2SPREDIV_ODD_EVEN ((uint16_t)0x0100) /*!< Odd factor for the prescaler */
+#define SPI_I2SPREDIV_MCLKOEN ((uint16_t)0x0200) /*!< Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CTRL1 register ********************/
+#define I2C_CTRL1_EN ((uint16_t)0x0001) /*!< Peripheral Enable */
+#define I2C_CTRL1_SMBMODE ((uint16_t)0x0002) /*!< SMBus Mode */
+#define I2C_CTRL1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */
+#define I2C_CTRL1_ARPEN ((uint16_t)0x0010) /*!< ARP Enable */
+#define I2C_CTRL1_PECEN ((uint16_t)0x0020) /*!< PEC Enable */
+#define I2C_CTRL1_GCEN ((uint16_t)0x0040) /*!< General Call Enable */
+#define I2C_CTRL1_NOEXTEND ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */
+#define I2C_CTRL1_STARTGEN ((uint16_t)0x0100) /*!< Start Generation */
+#define I2C_CTRL1_STOPGEN ((uint16_t)0x0200) /*!< Stop Generation */
+#define I2C_CTRL1_ACKEN ((uint16_t)0x0400) /*!< Acknowledge Enable */
+#define I2C_CTRL1_ACKPOS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */
+#define I2C_CTRL1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */
+#define I2C_CTRL1_SMBALERT ((uint16_t)0x2000) /*!< SMBus Alert */
+#define I2C_CTRL1_SWRESET ((uint16_t)0x8000) /*!< Software Reset */
+
+/******************* Bit definition for I2C_CTRL2 register ********************/
+#define I2C_CTRL2_CLKFREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CTRL2_CLKFREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define I2C_CTRL2_CLKFREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define I2C_CTRL2_CLKFREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define I2C_CTRL2_CLKFREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define I2C_CTRL2_CLKFREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define I2C_CTRL2_CLKFREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */
+
+#define I2C_CTRL2_ERRINTEN ((uint16_t)0x0100) /*!< Error Interrupt Enable */
+#define I2C_CTRL2_EVTINTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */
+#define I2C_CTRL2_BUFINTEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */
+#define I2C_CTRL2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */
+#define I2C_CTRL2_DMALAST ((uint16_t)0x1000) /*!< DMA Last Transfer */
+
+/******************* Bit definition for I2C_OADDR1 register *******************/
+#define I2C_OADDR1_ADDR1_7 ((uint16_t)0x00FE) /*!< Interface Address */
+#define I2C_OADDR1_ADDR8_9 ((uint16_t)0x0300) /*!< Interface Address */
+
+#define I2C_OADDR1_ADDR0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define I2C_OADDR1_ADDR1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define I2C_OADDR1_ADDR2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define I2C_OADDR1_ADDR3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define I2C_OADDR1_ADDR4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define I2C_OADDR1_ADDR5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define I2C_OADDR1_ADDR6 ((uint16_t)0x0040) /*!< Bit 6 */
+#define I2C_OADDR1_ADDR7 ((uint16_t)0x0080) /*!< Bit 7 */
+#define I2C_OADDR1_ADDR8 ((uint16_t)0x0100) /*!< Bit 8 */
+#define I2C_OADDR1_ADDR9 ((uint16_t)0x0200) /*!< Bit 9 */
+
+#define I2C_OADDR1_ADDRMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OADDR2 register *******************/
+#define I2C_OADDR2_DUALEN ((uint8_t)0x01) /*!< Dual addressing mode enable */
+#define I2C_OADDR2_ADDR2 ((uint8_t)0xFE) /*!< Interface address */
+
+/******************** Bit definition for I2C_DAT register ********************/
+#define I2C_DAT_DATA ((uint8_t)0xFF) /*!< 8-bit Data Register */
+
+/******************* Bit definition for I2C_STS1 register ********************/
+#define I2C_STS1_STARTBF ((uint16_t)0x0001) /*!< Start Bit (Master mode) */
+#define I2C_STS1_ADDRF ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */
+#define I2C_STS1_BSF ((uint16_t)0x0004) /*!< Byte Transfer Finished */
+#define I2C_STS1_ADDR10F ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */
+#define I2C_STS1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */
+#define I2C_STS1_RXDATNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */
+#define I2C_STS1_TXDATE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */
+#define I2C_STS1_BUSERR ((uint16_t)0x0100) /*!< Bus Error */
+#define I2C_STS1_ARLOST ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */
+#define I2C_STS1_ACKFAIL ((uint16_t)0x0400) /*!< Acknowledge Failure */
+#define I2C_STS1_OVERRUN ((uint16_t)0x0800) /*!< Overrun/Underrun */
+#define I2C_STS1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */
+#define I2C_STS1_TIMOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */
+#define I2C_STS1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */
+
+/******************* Bit definition for I2C_STS2 register ********************/
+#define I2C_STS2_MSMODE ((uint16_t)0x0001) /*!< Master/Slave */
+#define I2C_STS2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */
+#define I2C_STS2_TRF ((uint16_t)0x0004) /*!< Transmitter/Receiver */
+#define I2C_STS2_GCALLADDR ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */
+#define I2C_STS2_SMBDADDR ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */
+#define I2C_STS2_SMBHADDR ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */
+#define I2C_STS2_DUALFLAG ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */
+#define I2C_STS2_PECVAL ((uint16_t)0xFF00) /*!< Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CLKCTRL register ********************/
+#define I2C_CLKCTRL_CLKCTRL ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CLKCTRL_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */
+#define I2C_CLKCTRL_FSMODE ((uint16_t)0x8000) /*!< I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TMRISE_TMRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for USART_STS register *******************/
+#define USART_STS_PEF ((uint16_t)0x0001) /*!< Parity Error */
+#define USART_STS_FEF ((uint16_t)0x0002) /*!< Framing Error */
+#define USART_STS_NEF ((uint16_t)0x0004) /*!< Noise Error Flag */
+#define USART_STS_OREF ((uint16_t)0x0008) /*!< OverRun Error */
+#define USART_STS_IDLEF ((uint16_t)0x0010) /*!< IDLE line detected */
+#define USART_STS_RXDNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */
+#define USART_STS_TXC ((uint16_t)0x0040) /*!< Transmission Complete */
+#define USART_STS_TXDE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */
+#define USART_STS_LINBDF ((uint16_t)0x0100) /*!< LIN Break Detection Flag */
+#define USART_STS_CTSF ((uint16_t)0x0200) /*!< CTS Flag */
+
+/******************* Bit definition for USART_DAT register *******************/
+#define USART_DAT_DATV ((uint16_t)0x01FF) /*!< Data value */
+
+/****************** Bit definition for USART_BRCF register *******************/
+#define USART_BRCF_DIV_Decimal ((uint16_t)0x000F) /*!< Fraction of USARTDIV */
+#define USART_BRCF_DIV_Integer ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CTRL1 register *******************/
+#define USART_CTRL1_SDBRK ((uint16_t)0x0001) /*!< Send Break */
+#define USART_CTRL1_RCVWU ((uint16_t)0x0002) /*!< Receiver wakeup */
+#define USART_CTRL1_RXEN ((uint16_t)0x0004) /*!< Receiver Enable */
+#define USART_CTRL1_TXEN ((uint16_t)0x0008) /*!< Transmitter Enable */
+#define USART_CTRL1_IDLEIEN ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */
+#define USART_CTRL1_RXDNEIEN ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */
+#define USART_CTRL1_TXCIEN ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */
+#define USART_CTRL1_TXDEIEN ((uint16_t)0x0080) /*!< PE Interrupt Enable */
+#define USART_CTRL1_PEIEN ((uint16_t)0x0100) /*!< PE Interrupt Enable */
+#define USART_CTRL1_PSEL ((uint16_t)0x0200) /*!< Parity Selection */
+#define USART_CTRL1_PCEN ((uint16_t)0x0400) /*!< Parity Control Enable */
+#define USART_CTRL1_WUM ((uint16_t)0x0800) /*!< Wakeup method */
+#define USART_CTRL1_WL ((uint16_t)0x1000) /*!< Word length */
+#define USART_CTRL1_UEN ((uint16_t)0x2000) /*!< USART Enable */
+
+/****************** Bit definition for USART_CTRL2 register *******************/
+#define USART_CTRL2_ADDR ((uint16_t)0x000F) /*!< Address of the USART node */
+#define USART_CTRL2_LINBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */
+#define USART_CTRL2_LINBDIEN ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */
+#define USART_CTRL2_LBCLK ((uint16_t)0x0100) /*!< Last Bit Clock pulse */
+#define USART_CTRL2_CLKPHA ((uint16_t)0x0200) /*!< Clock Phase */
+#define USART_CTRL2_CLKPOL ((uint16_t)0x0400) /*!< Clock Polarity */
+#define USART_CTRL2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */
+
+#define USART_CTRL2_STPB ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CTRL2_STPB_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USART_CTRL2_STPB_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USART_CTRL2_LINMEN ((uint16_t)0x4000) /*!< LIN mode enable */
+
+/****************** Bit definition for USART_CTRL3 register *******************/
+#define USART_CTRL3_ERRIEN ((uint16_t)0x0001) /*!< Error Interrupt Enable */
+#define USART_CTRL3_IRDAMEN ((uint16_t)0x0002) /*!< IrDA mode Enable */
+#define USART_CTRL3_IRDALP ((uint16_t)0x0004) /*!< IrDA Low-Power */
+#define USART_CTRL3_HDMEN ((uint16_t)0x0008) /*!< Half-Duplex Selection */
+#define USART_CTRL3_SCNACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */
+#define USART_CTRL3_SCMEN ((uint16_t)0x0020) /*!< Smartcard mode enable */
+#define USART_CTRL3_DMARXEN ((uint16_t)0x0040) /*!< DMA Enable Receiver */
+#define USART_CTRL3_DMATXEN ((uint16_t)0x0080) /*!< DMA Enable Transmitter */
+#define USART_CTRL3_RTSEN ((uint16_t)0x0100) /*!< RTS Enable */
+#define USART_CTRL3_CTSEN ((uint16_t)0x0200) /*!< CTS Enable */
+#define USART_CTRL3_CTSIEN ((uint16_t)0x0400) /*!< CTS Interrupt Enable */
+
+/****************** Bit definition for USART_GTP register ******************/
+#define USART_GTP_PSCV ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTP_PSCV_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define USART_GTP_PSCV_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define USART_GTP_PSCV_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define USART_GTP_PSCV_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define USART_GTP_PSCV_4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define USART_GTP_PSCV_5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define USART_GTP_PSCV_6 ((uint16_t)0x0040) /*!< Bit 6 */
+#define USART_GTP_PSCV_7 ((uint16_t)0x0080) /*!< Bit 7 */
+
+#define USART_GTP_GTV ((uint16_t)0xFF00) /*!< Guard time value */
+
+/******************************************************************************/
+/* */
+/* Low-power Universal Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for LPUART_STS register ******************/
+#define LPUART_STS_PEF ((uint16_t)0x0001) /*!< Parity Check Error Flag */
+#define LPUART_STS_TXC ((uint16_t)0x0002) /*!< TX Complete Flag */
+#define LPUART_STS_FIFO_OV ((uint16_t)0x0004) /*!< FIFO Overflow Flag */
+#define LPUART_STS_FIFO_FU ((uint16_t)0x0008) /*!< FIFO Full Flag */
+#define LPUART_STS_FIFO_HF ((uint16_t)0x0010) /*!< FIFO Half Full Flag */
+#define LPUART_STS_FIFO_NE ((uint16_t)0x0020) /*!< FIFO Non-Empty Flag */
+#define LPUART_STS_CTS ((uint16_t)0x0040) /*!< Clear to Send (Hardware Flow Control) Flag */
+#define LPUART_STS_WUF ((uint16_t)0x0080) /*!< Wakeup from Stop mode Flag */
+#define LPUART_STS_NF ((uint16_t)0x0100) /*!< Noise Detected Flag */
+
+/****************** Bit definition for LPUART_INTEN register ******************/
+#define LPUART_INTEN_PEIE ((uint8_t)0x01) /*!< Parity Check Error Interrupt Enable */
+#define LPUART_INTEN_TXCIE ((uint8_t)0x02) /*!< TX Complete Interrupt Enable */
+#define LPUART_INTEN_FIFO_OVIE ((uint8_t)0x04) /*!< FIFO Overflow Interrupt Enable */
+#define LPUART_INTEN_FIFO_FUIE ((uint8_t)0x08) /*!< FIFO Full Interrupt Enable*/
+#define LPUART_INTEN_FIFO_HFIE ((uint8_t)0x10) /*!< FIFO Half Full Interrupt Enable */
+#define LPUART_INTEN_FIFO_NEIE ((uint8_t)0x20) /*!< FIFO Non-Empty Interrupt Enable */
+#define LPUART_INTEN_WUFIE ((uint8_t)0x40) /*!< Wakeup Interrupt Enable */
+
+/****************** Bit definition for LPUART_CTRL register ******************/
+#define LPUART_CTRL_PSEL ((uint16_t)0x0001) /*!< Odd Parity Bit Enable */
+#define LPUART_CTRL_TXEN ((uint16_t)0x0002) /*!< TX Enable */
+#define LPUART_CTRL_FLUSH ((uint16_t)0x0004) /*!< Flush Receiver FIFO Enable */
+#define LPUART_CTRL_PCDIS ((uint16_t)0x0008) /*!< Parity Control Disable */
+#define LPUART_CTRL_LOOPBACK ((uint16_t)0x0010) /*!< Loop Back Self-Test */
+#define LPUART_CTRL_DMA_TXEN ((uint16_t)0x0020) /*!< DMA TX Request Enable */
+#define LPUART_CTRL_DMA_RXEN ((uint16_t)0x0040) /*!< DMA RX Request Enable */
+#define LPUART_CTRL_WUSTP ((uint16_t)0x0080) /*!< LPUART Wakeup Enable in Stop mode */
+#define LPUART_CTRL_RTS_THSEL ((uint16_t)0x0300) /*!< RTS Threshold Selection */
+#define LPUART_CTRL_CTSEN ((uint16_t)0x0400) /*!< Hardware Flow Control TX Enable */
+#define LPUART_CTRL_RTSEN ((uint16_t)0x0800) /*!< Hardware Flow Control RX Enable */
+#define LPUART_CTRL_WUSEL ((uint16_t)0x3000) /*!< Wakeup Event Selection */
+#define LPUART_CTRL_SMPCNT ((uint16_t)0x4000) /*!< Specify the Sampling Method */
+
+/****************** Bit definition for LPUART_BRCFG1 register ******************/
+#define LPUART_BRCFG1_INTEGER ((uint16_t)0xFFFF) /*!< Baud Rate Parameter Configeration Register1: Fraction */
+
+/****************** Bit definition for LPUART_DAT register ******************/
+#define LPUART_DAT_DAT ((uint8_t)0xFF) /*!< Data Register */
+
+/****************** Bit definition for LPUART_BRCFG2 register ******************/
+#define LPUART_BRCFG2_DECIMAL ((uint8_t)0xFF) /*!< Baud Rate Parameter Configeration Register2: Mantissa */
+
+/****************** Bit definition for LPUART_WUDAT register ******************/
+#define LPUART_WUDAT_WUDAT ((uint32_t)0xFFFFFFFF) /*!< Data Register */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBG_ID register *****************/
+#define DBG_ID_DEV ((uint32_t)0x00000FFF) /*!< Device Identifier */
+
+#define DBG_ID_REV ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBG_ID_REV_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define DBG_ID_REV_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define DBG_ID_REV_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define DBG_ID_REV_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define DBG_ID_REV_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define DBG_ID_REV_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define DBG_ID_REV_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define DBG_ID_REV_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+#define DBG_ID_REV_8 ((uint32_t)0x01000000) /*!< Bit 8 */
+#define DBG_ID_REV_9 ((uint32_t)0x02000000) /*!< Bit 9 */
+#define DBG_ID_REV_10 ((uint32_t)0x04000000) /*!< Bit 10 */
+#define DBG_ID_REV_11 ((uint32_t)0x08000000) /*!< Bit 11 */
+#define DBG_ID_REV_12 ((uint32_t)0x10000000) /*!< Bit 12 */
+#define DBG_ID_REV_13 ((uint32_t)0x20000000) /*!< Bit 13 */
+#define DBG_ID_REV_14 ((uint32_t)0x40000000) /*!< Bit 14 */
+#define DBG_ID_REV_15 ((uint32_t)0x80000000) /*!< Bit 15 */
+
+/****************** Bit definition for DBG_CTRL register *******************/
+#define DBG_CTRL_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
+#define DBG_CTRL_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
+#define DBG_CTRL_STDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
+
+#define DBG_CTRL_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBG_CTRL_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBG_CTRL_TIM1_STOP ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */
+#define DBG_CTRL_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */
+#define DBG_CTRL_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */
+#define DBG_CTRL_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */
+#define DBG_CTRL_CAN_STOP ((uint32_t)0x00004000) /*!< Debug CAN stopped when Core is halted */
+#define DBG_CTRL_I2C1SMBUS_TO ((uint32_t)0x00008000) /*!< SMBUS I2C1 timeout mode stopped when Core is halted */
+#define DBG_CTRL_I2C2SMBUS_TO ((uint32_t)0x00010000) /*!< SMBUS I2C2 timeout mode stopped when Core is halted */
+#define DBG_CTRL_TIM8_STOP ((uint32_t)0x00020000) /*!< TIM8 counter stopped when core is halted */
+#define DBG_CTRL_TIM5_STOP ((uint32_t)0x00040000) /*!< TIM5 counter stopped when core is halted */
+#define DBG_CTRL_TIM6_STOP ((uint32_t)0x00080000) /*!< TIM6 counter stopped when core is halted */
+#define DBG_CTRL_TIM7_STOP ((uint32_t)0x00100000) /*!< TIM7 counter stopped when core is halted */
+#define DBG_CTRL_TIM9_STOP ((uint32_t)0x00200000) /*!< TIM9 counter stopped when core is halted*/
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_AC register ******************/
+#define FLASH_AC_LATENCY ((uint32_t)0x00000003) /*!< LATENCY[2:0] bits (Latency) */
+#define FLASH_AC_LATENCY_0 ((uint32_t)0x00000000) /*!< Bit 0 = 0 */
+#define FLASH_AC_LATENCY_1 ((uint32_t)0x00000001) /*!< Bit 0 = 1 */
+#define FLASH_AC_LATENCY_2 ((uint32_t)0x00000002) /*!< Bit 0 = 0; Bit 1 = 1 */
+#define FLASH_AC_LATENCY_3 ((uint32_t)0x00000003) /*!< Bit 0 = 1; Bit 1 = 1 */
+
+#define FLASH_AC_PRFTBFEN ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
+#define FLASH_AC_PRFTBFSTS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
+#define FLASH_AC_ICAHRST ((uint32_t)0x00000040) /*!< Icache Reset */
+#define FLASH_AC_ICAHEN ((uint32_t)0x00000080) /*!< Icache Enable */
+#define FLASH_AC_LVMF ((uint32_t)0x00000100) /*!< Flash low power work mode status */
+#define FLASH_AC_LVMEN ((uint32_t)0x00000200) /*!< Flash low power work mode Enable */
+#define FLASH_AC_SLMF ((uint32_t)0x00000400) /*!< Flash sleep mode status */
+#define FLASH_AC_SLMEN ((uint32_t)0x00000800) /*!< Flash sleep mode Enable */
+
+/****************** Bit definition for FLASH_KEY register ******************/
+#define FLASH_KEY_FKEY ((uint32_t)0xFFFFFFFF) /*!< FLASH Key */
+
+/***************** Bit definition for FLASH_OPTKEY register ****************/
+#define FLASH_OPTKEY_OPTKEY ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
+
+/****************** Bit definition for FLASH_STS register *******************/
+#define FLASH_STS_BUSY ((uint8_t)0x01) /*!< Busy */
+#define FLASH_STS_PGERR ((uint8_t)0x04) /*!< Programming Error */
+#define FLASH_STS_PVERR ((uint8_t)0x08) /*!< Programming Verify ERROR after program */
+#define FLASH_STS_WRPERR ((uint8_t)0x10) /*!< Write Protection Error */
+#define FLASH_STS_EOP ((uint8_t)0x20) /*!< End of operation */
+#define FLASH_STS_EVERR ((uint8_t)0x40) /*!< Erase Verify ERROR after page erase */
+
+/******************* Bit definition for FLASH_CTRL register *******************/
+#define FLASH_CTRL_PG ((uint16_t)0x0001) /*!< Programming */
+#define FLASH_CTRL_PER ((uint16_t)0x0002) /*!< Page Erase */
+#define FLASH_CTRL_MER ((uint16_t)0x0004) /*!< Mass Erase */
+#define FLASH_CTRL_OPTPG ((uint16_t)0x0010) /*!< Option Byte Programming */
+#define FLASH_CTRL_OPTER ((uint16_t)0x0020) /*!< Option Byte Erase */
+#define FLASH_CTRL_START ((uint16_t)0x0040) /*!< Start */
+#define FLASH_CTRL_LOCK ((uint16_t)0x0080) /*!< Lock */
+#define FLASH_CTRL_SMPSEL ((uint16_t)0x0100) /*!< Flash Program Option Select */
+#define FLASH_CTRL_OPTWE ((uint16_t)0x0200) /*!< Option Bytes Write Enable */
+#define FLASH_CTRL_ERRITE ((uint16_t)0x0400) /*!< Error Interrupt Enable */
+#define FLASH_CTRL_FERRITE ((uint16_t)0x0800) /*!< EVERR PVERR Error Interrupt Enable */
+#define FLASH_CTRL_EOPITE ((uint16_t)0x1000) /*!< End of operation Interrupt Enable */
+
+/******************* Bit definition for FLASH_ADD register *******************/
+#define FLASH_ADD_FADD ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OB2 register *******************/
+#define FLASH_OB2_BOR_LEV ((uint32_t)0x00000700) /*!< BOR_LEV[2:0] */
+#define FLASH_OB2_nBOOT1 ((uint32_t)0x00800000) /*!< nBOOT1 */
+#define FLASH_OB2_nSWBOOT0 ((uint32_t)0x04000000) /*!< nSWBOOT0 */
+#define FLASH_OB2_nBOOT0 ((uint32_t)0x08000000) /*!< nBOOT1 */
+
+/****************** Bit definition for FLASH_OB register *******************/
+#define FLASH_OB_OBERR ((uint16_t)0x0001) /*!< Option Byte Error */
+#define FLASH_OB_RDPRT1 ((uint16_t)0x0002) /*!< Read Protection */
+
+#define FLASH_OB_USER ((uint16_t)0x03FC) /*!< User Option Bytes */
+#define FLASH_OB_WDG_SW ((uint16_t)0x0004) /*!< WDG_SW */
+#define FLASH_OB_NRST_STOP2 ((uint16_t)0x0008) /*!< nRST_STOP2 */
+#define FLASH_OB_NRST_STDBY ((uint16_t)0x0010) /*!< nRST_STDBY */
+#define FLASH_OB_NRST_PD ((uint16_t)0x0020) /*!< nRST_PD */
+
+#define FLASH_OB_DATA0_MSK ((uint32_t)0x0003FC00) /*!< Data0 Mask */
+#define FLASH_OB_DATA1_MSK ((uint32_t)0x03FC0000) /*!< Data1 Mask */
+#define FLASH_OB_RDPRT2 ((uint32_t)0x80000000) /*!< Read Protection Level 2 */
+
+/****************** Bit definition for FLASH_WRP register ******************/
+#define FLASH_WRP_WRPT ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
+
+/****************** Bit definition for FLASH_CAHR register ******************/
+#define FLASH_CAHR_LOCKSTRT_MSK ((uint32_t)0x000F) /*!< LOCKSTRT Mask */
+#define FLASH_CAHR_LOCKSTOP_MSK ((uint32_t)0x00F0) /*!< LOCKSTOP Mask */
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for OptionByte USER ******************/
+#define FLASH_RDP_RDP1 ((uint32_t)0x000000FF) /*!< Read protection option byte */
+#define FLASH_RDP_NRDP1 ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
+
+/****************** Bit definition for OptionByte USER ******************/
+#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
+#define FLASH_USER_NUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
+
+/****************** Bit definition for OptionByte Data0 *****************/
+#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!< User data storage option byte */
+#define FLASH_Data0_NData0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */
+
+/****************** Bit definition for OptionByte Data1 *****************/
+#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */
+#define FLASH_Data1_NData1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */
+
+/****************** Bit definition for OptionByte WRP0 ******************/
+#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP0_NWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for OptionByte WRP1 ******************/
+#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP1_NWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for OptionByte WRP2 ******************/
+#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP2_NWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for OptionByte WRP3 ******************/
+#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP3_NWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for OptionByte RDP2 *******************/
+#define FLASH_RDP_RDP2 ((uint32_t)0x000000FF) /*!< Read protection level 2 option byte */
+#define FLASH_RDP_NRDP2 ((uint32_t)0x0000FF00) /*!< Read protection level 2 complemented option byte */
+
+/****************** Bit definition for OptionByte USER2 ******************/
+#define FLASH_USER_USER2 ((uint32_t)0x00FF0000) /*!< User option byte */
+#define FLASH_USER_NUSER2 ((uint32_t)0xFF000000) /*!< User complemented option byte */
+
+/******************************************************************************/
+/* */
+/* General Purpose and Alternate Function I/O */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for GPIO_PMODE register *******************/
+
+
+#define GPIO_PMODE0_Pos (0)
+#define GPIO_PMODE0_Msk (0x3 << GPIO_PMODE0_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE0 GPIO_PMODE0_Msk
+#define GPIO_PMODE0_0 (0x0 << GPIO_PMODE0_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE0_1 (0x1 << GPIO_PMODE0_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE0_2 (0x2 << GPIO_PMODE0_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE0_3 (0x3 << GPIO_PMODE0_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE1_Pos (2)
+#define GPIO_PMODE1_Msk (0x3 << GPIO_PMODE1_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE1 GPIO_PMODE1_Msk
+#define GPIO_PMODE1_0 (0x0 << GPIO_PMODE1_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE1_1 (0x1 << GPIO_PMODE1_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE1_2 (0x2 << GPIO_PMODE1_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE1_3 (0x3 << GPIO_PMODE1_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE2_Pos (4)
+#define GPIO_PMODE2_Msk (0x3 << GPIO_PMODE2_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE2 GPIO_PMODE2_Msk
+#define GPIO_PMODE2_0 (0x0 << GPIO_PMODE2_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE2_1 (0x1 << GPIO_PMODE2_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE2_2 (0x2 << GPIO_PMODE2_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE2_3 (0x3 << GPIO_PMODE2_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE3_Pos (6)
+#define GPIO_PMODE3_Msk (0x3 << GPIO_PMODE3_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE3 GPIO_PMODE3_Msk
+#define GPIO_PMODE3_0 (0x0 << GPIO_PMODE3_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE3_1 (0x1 << GPIO_PMODE3_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE3_2 (0x2 << GPIO_PMODE3_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE3_3 (0x3 << GPIO_PMODE3_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE4_Pos (8)
+#define GPIO_PMODE4_Msk (0x3 << GPIO_PMODE4_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE4 GPIO_PMODE4_Msk
+#define GPIO_PMODE4_0 (0x0 << GPIO_PMODE4_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE4_1 (0x1 << GPIO_PMODE4_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE4_2 (0x2 << GPIO_PMODE4_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE4_3 (0x3 << GPIO_PMODE4_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE5_Pos (10)
+#define GPIO_PMODE5_Msk (0x3 << GPIO_PMODE5_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE5 GPIO_PMODE5_Msk
+#define GPIO_PMODE5_0 (0x0 << GPIO_PMODE5_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE5_1 (0x1 << GPIO_PMODE5_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE5_2 (0x2 << GPIO_PMODE5_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE5_3 (0x3 << GPIO_PMODE5_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE6_Pos (12)
+#define GPIO_PMODE6_Msk (0x3 << GPIO_PMODE6_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE6 GPIO_PMODE6_Msk
+#define GPIO_PMODE6_0 (0x0 << GPIO_PMODE6_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE6_1 (0x1 << GPIO_PMODE6_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE6_2 (0x2 << GPIO_PMODE6_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE6_3 (0x3 << GPIO_PMODE6_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE7_Pos (14)
+#define GPIO_PMODE7_Msk (0x3 << GPIO_PMODE7_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE7 GPIO_PMODE7_Msk
+#define GPIO_PMODE7_0 (0x0 << GPIO_PMODE7_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE7_1 (0x1 << GPIO_PMODE7_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE7_2 (0x2 << GPIO_PMODE7_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE7_3 (0x3 << GPIO_PMODE7_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE8_Pos (16)
+#define GPIO_PMODE8_Msk (0x3 << GPIO_PMODE8_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE8 GPIO_PMODE8_Msk
+#define GPIO_PMODE8_0 (0x0 << GPIO_PMODE8_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE8_1 (0x1 << GPIO_PMODE8_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE8_2 (0x2 << GPIO_PMODE8_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE8_3 (0x3 << GPIO_PMODE8_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE9_Pos (18)
+#define GPIO_PMODE9_Msk (0x3 << GPIO_PMODE9_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE9 GPIO_PMODE9_Msk
+#define GPIO_PMODE9_0 (0x0 << GPIO_PMODE9_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE9_1 (0x1 << GPIO_PMODE9_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE9_2 (0x2 << GPIO_PMODE9_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE9_3 (0x3 << GPIO_PMODE9_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE10_Pos (20)
+#define GPIO_PMODE10_Msk (0x3 << GPIO_PMODE10_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE10 GPIO_PMODE10_Msk
+#define GPIO_PMODE10_0 (0x0 << GPIO_PMODE10_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE10_1 (0x1 << GPIO_PMODE10_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE10_2 (0x2 << GPIO_PMODE10_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE10_3 (0x3 << GPIO_PMODE10_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE11_Pos (22)
+#define GPIO_PMODE11_Msk (0x3 << GPIO_PMODE11_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE11 GPIO_PMODE11_Msk
+#define GPIO_PMODE11_0 (0x0 << GPIO_PMODE11_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE11_1 (0x1 << GPIO_PMODE11_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE11_2 (0x2 << GPIO_PMODE11_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE11_3 (0x3 << GPIO_PMODE11_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE12_Pos (24)
+#define GPIO_PMODE12_Msk (0x3 << GPIO_PMODE12_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE12 GPIO_PMODE12_Msk
+#define GPIO_PMODE12_0 (0x0 << GPIO_PMODE12_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE12_1 (0x1 << GPIO_PMODE12_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE12_2 (0x2 << GPIO_PMODE12_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE12_3 (0x3 << GPIO_PMODE12_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE13_Pos (26)
+#define GPIO_PMODE13_Msk (0x3 << GPIO_PMODE13_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE13 GPIO_PMODE13_Msk
+#define GPIO_PMODE13_0 (0x0 << GPIO_PMODE13_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE13_1 (0x1 << GPIO_PMODE13_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE13_2 (0x2 << GPIO_PMODE13_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE13_3 (0x3 << GPIO_PMODE13_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE14_Pos (28)
+#define GPIO_PMODE14_Msk (0x3 << GPIO_PMODE14_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE14 GPIO_PMODE14_Msk
+#define GPIO_PMODE14_0 (0x0 << GPIO_PMODE14_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE14_1 (0x1 << GPIO_PMODE14_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE14_2 (0x2 << GPIO_PMODE14_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE14_3 (0x3 << GPIO_PMODE14_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE15_Pos (30)
+#define GPIO_PMODE15_Msk (0x3 << GPIO_PMODE15_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE15 GPIO_PMODE15_Msk
+#define GPIO_PMODE15_0 (0x0 << GPIO_PMODE15_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE15_1 (0x1 << GPIO_PMODE15_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE15_2 (0x2 << GPIO_PMODE15_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE15_3 (0x3 << GPIO_PMODE15_Pos) /*!< 0x00000003 */
+
+
+
+
+/****************** Bit definition for GPIO_POTYPER register *****************/
+#define GPIO_POTYPE_POT_0 (0x00000001)
+#define GPIO_POTYPE_POT_1 (0x00000002)
+#define GPIO_POTYPE_POT_2 (0x00000004)
+#define GPIO_POTYPE_POT_3 (0x00000008)
+#define GPIO_POTYPE_POT_4 (0x00000010)
+#define GPIO_POTYPE_POT_5 (0x00000020)
+#define GPIO_POTYPE_POT_6 (0x00000040)
+#define GPIO_POTYPE_POT_7 (0x00000080)
+#define GPIO_POTYPE_POT_8 (0x00000100)
+#define GPIO_POTYPE_POT_9 (0x00000200)
+#define GPIO_POTYPE_POT_10 (0x00000400)
+#define GPIO_POTYPE_POT_11 (0x00000800)
+#define GPIO_POTYPE_POT_12 (0x00001000)
+#define GPIO_POTYPE_POT_13 (0x00002000)
+#define GPIO_POTYPE_POT_14 (0x00004000)
+#define GPIO_POTYPE_POT_15 (0x00008000)
+
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPD0_Pos (0)
+#define GPIO_PUPD0_Msk (0x3 << GPIO_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD0 GPIO_PUPD0_Msk
+#define GPIO_PUPD0_0 (0x0 << GPIO_PUPD0_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD0_1 (0x1 << GPIO_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD0_2 (0x2 << GPIO_PUPD0_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD1_Pos (2)
+#define GPIO_PUPD1_Msk (0x3 << GPIO_PUPD1_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD1 GPIO_PUPD1_Msk
+#define GPIO_PUPD1_0 (0x0 << GPIO_PUPD1_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD1_1 (0x1 << GPIO_PUPD1_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD1_2 (0x2 << GPIO_PUPD1_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD2_Pos (4)
+#define GPIO_PUPD2_Msk (0x3 << GPIO_PUPD2_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD2 GPIO_PUPD2_Msk
+#define GPIO_PUPD2_0 (0x0 << GPIO_PUPD2_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD2_1 (0x1 << GPIO_PUPD2_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD2_2 (0x2 << GPIO_PUPD2_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD3_Pos (6)
+#define GPIO_PUPD3_Msk (0x3 << GPIO_PUPD3_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD3 GPIO_PUPD3_Msk
+#define GPIO_PUPD3_0 (0x0 << GPIO_PUPD3_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD3_1 (0x1 << GPIO_PUPD3_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD3_2 (0x2 << GPIO_PUPD3_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD4_Pos (8)
+#define GPIO_PUPD4_Msk (0x3 << GPIO_PUPD4_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD4 GPIO_PUPD4_Msk
+#define GPIO_PUPD4_0 (0x0 << GPIO_PUPD4_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD4_1 (0x1 << GPIO_PUPD4_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD4_2 (0x2 << GPIO_PUPD4_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD5_Pos (10)
+#define GPIO_PUPD5_Msk (0x3 << GPIO_PUPD5_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD5 GPIO_PUPD5_Msk
+#define GPIO_PUPD5_0 (0x0 << GPIO_PUPD5_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD5_1 (0x1 << GPIO_PUPD5_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD5_2 (0x2 << GPIO_PUPD5_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD6_Pos (12)
+#define GPIO_PUPD6_Msk (0x3 << GPIO_PUPD6_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD6 GPIO_PUPD6_Msk
+#define GPIO_PUPD6_0 (0x0 << GPIO_PUPD6_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD6_1 (0x1 << GPIO_PUPD6_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD6_2 (0x2 << GPIO_PUPD6_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD7_Pos (14)
+#define GPIO_PUPD7_Msk (0x3 << GPIO_PUPD7_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD7 GPIO_PUPD7_Msk
+#define GPIO_PUPD7_0 (0x0 << GPIO_PUPD7_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD7_1 (0x1 << GPIO_PUPD7_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD7_2 (0x2 << GPIO_PUPD7_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD8_Pos (16)
+#define GPIO_PUPD8_Msk (0x3 << GPIO_PUPD8_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD8 GPIO_PUPD8_Msk
+#define GPIO_PUPD8_0 (0x0 << GPIO_PUPD8_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD8_1 (0x1 << GPIO_PUPD8_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD8_2 (0x2 << GPIO_PUPD8_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD9_Pos (18)
+#define GPIO_PUPD9_Msk (0x3 << GPIO_PUPD9_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD9 GPIO_PUPD9_Msk
+#define GPIO_PUPD9_0 (0x0 << GPIO_PUPD9_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD9_1 (0x1 << GPIO_PUPD9_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD9_2 (0x2 << GPIO_PUPD9_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD10_Pos (20)
+#define GPIO_PUPD10_Msk (0x3 << GPIO_PUPD10_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD10 GPIO_PUPD10_Msk
+#define GPIO_PUPD10_0 (0x0 << GPIO_PUPD10_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD10_1 (0x1 << GPIO_PUPD10_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD10_2 (0x2 << GPIO_PUPD10_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD11_Pos (22)
+#define GPIO_PUPD11_Msk (0x3 << GPIO_PUPD11_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD11 GPIO_PUPD11_Msk
+#define GPIO_PUPD11_0 (0x0 << GPIO_PUPD11_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD11_1 (0x1 << GPIO_PUPD11_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD11_2 (0x2 << GPIO_PUPD11_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD12_Pos (24)
+#define GPIO_PUPD12_Msk (0x3 << GPIO_PUPD12_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD12 GPIO_PUPD12_Msk
+#define GPIO_PUPD12_0 (0x0 << GPIO_PUPD12_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD12_1 (0x1 << GPIO_PUPD12_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD12_2 (0x2 << GPIO_PUPD12_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD13_Pos (26)
+#define GPIO_PUPD13_Msk (0x3 << GPIO_PUPD13_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD13 GPIO_PUPD13_Msk
+#define GPIO_PUPD13_0 (0x0 << GPIO_PUPD13_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD13_1 (0x1 << GPIO_PUPD13_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD13_2 (0x2 << GPIO_PUPD13_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD14_Pos (28)
+#define GPIO_PUPD14_Msk (0x3 << GPIO_PUPD14_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD14 GPIO_PUPD14_Msk
+#define GPIO_PUPD14_0 (0x0 << GPIO_PUPD14_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD14_1 (0x1 << GPIO_PUPD14_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD14_2 (0x2 << GPIO_PUPD14_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD15_Pos (30)
+#define GPIO_PUPD15_Msk (0x3 << GPIO_PUPD15_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD15 GPIO_PUPD15_Msk
+#define GPIO_PUPD15_0 (0x0 << GPIO_PUPD15_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD15_1 (0x1 << GPIO_PUPD15_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD15_2 (0x2 << GPIO_PUPD15_Pos) /*!< 0x00000002 */
+
+
+/*!<****************** Bit definition for GPIO_IDR register *******************/
+#define GPIO_PID_PID0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */
+#define GPIO_PID_PID1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */
+#define GPIO_PID_PID2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */
+#define GPIO_PID_PID3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */
+#define GPIO_PID_PID4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */
+#define GPIO_PID_PID5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */
+#define GPIO_PID_PID6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */
+#define GPIO_PID_PID7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */
+#define GPIO_PID_PID8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */
+#define GPIO_PID_PID9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */
+#define GPIO_PID_PID10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */
+#define GPIO_PID_PID11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */
+#define GPIO_PID_PID12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */
+#define GPIO_PID_PID13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */
+#define GPIO_PID_PID14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */
+#define GPIO_PID_PID15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */
+
+/******************* Bit definition for GPIO_POD register *******************/
+#define GPIO_POD_POD0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */
+#define GPIO_POD_POD1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */
+#define GPIO_POD_POD2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */
+#define GPIO_POD_POD3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */
+#define GPIO_POD_POD4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */
+#define GPIO_POD_POD5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */
+#define GPIO_POD_POD6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */
+#define GPIO_POD_POD7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */
+#define GPIO_POD_POD8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */
+#define GPIO_POD_POD9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */
+#define GPIO_POD_POD10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */
+#define GPIO_POD_POD11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */
+#define GPIO_POD_POD12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */
+#define GPIO_POD_POD13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */
+#define GPIO_POD_POD14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */
+#define GPIO_POD_POD15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */
+
+/****************** Bit definition for GPIO_BSRR register *******************/
+#define GPIO_PBSC_PBS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */
+#define GPIO_PBSC_PBS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */
+#define GPIO_PBSC_PBS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */
+#define GPIO_PBSC_PBS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */
+#define GPIO_PBSC_PBS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */
+#define GPIO_PBSC_PBS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */
+#define GPIO_PBSC_PBS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */
+#define GPIO_PBSC_PBS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */
+#define GPIO_PBSC_PBS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */
+#define GPIO_PBSC_PBS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */
+#define GPIO_PBSC_PBS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */
+#define GPIO_PBSC_PBS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */
+#define GPIO_PBSC_PBS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */
+#define GPIO_PBSC_PBS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */
+#define GPIO_PBSC_PBS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */
+#define GPIO_PBSC_PBS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */
+
+#define GPIO_PBSC_PBC0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */
+#define GPIO_PBSC_PBC1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */
+#define GPIO_PBSC_PBC2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */
+#define GPIO_PBSC_PBC3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */
+#define GPIO_PBSC_PBC4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */
+#define GPIO_PBSC_PBC5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */
+#define GPIO_PBSC_PBC6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */
+#define GPIO_PBSC_PBC7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */
+#define GPIO_PBSC_PBC8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */
+#define GPIO_PBSC_PBC9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */
+#define GPIO_PBSC_PBC10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */
+#define GPIO_PBSC_PBC11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */
+#define GPIO_PBSC_PBC12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */
+#define GPIO_PBSC_PBC13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */
+#define GPIO_PBSC_PBC14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */
+#define GPIO_PBSC_PBC15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */
+
+/******************* Bit definition for GPIO_BRR register *******************/
+#define GPIO_PBC_PBC0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */
+#define GPIO_PBC_PBC1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */
+#define GPIO_PBC_PBC2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */
+#define GPIO_PBC_PBC3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */
+#define GPIO_PBC_PBC4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */
+#define GPIO_PBC_PBC5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */
+#define GPIO_PBC_PBC6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */
+#define GPIO_PBC_PBC7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */
+#define GPIO_PBC_PBC8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */
+#define GPIO_PBC_PBC9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */
+#define GPIO_PBC_PBC10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */
+#define GPIO_PBC_PBC11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */
+#define GPIO_PBC_PBC12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */
+#define GPIO_PBC_PBC13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */
+#define GPIO_PBC_PBC14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */
+#define GPIO_PBC_PBC15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */
+
+/****************** Bit definition for GPIO_LCKR register *******************/
+#define GPIO_PLOCK_PLOCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */
+#define GPIO_PLOCK_PLOCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */
+#define GPIO_PLOCK_PLOCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */
+#define GPIO_PLOCK_PLOCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */
+#define GPIO_PLOCK_PLOCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */
+#define GPIO_PLOCK_PLOCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */
+#define GPIO_PLOCK_PLOCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */
+#define GPIO_PLOCK_PLOCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */
+#define GPIO_PLOCK_PLOCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */
+#define GPIO_PLOCK_PLOCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */
+#define GPIO_PLOCK_PLOCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */
+#define GPIO_PLOCK_PLOCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */
+#define GPIO_PLOCK_PLOCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */
+#define GPIO_PLOCK_PLOCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */
+#define GPIO_PLOCK_PLOCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */
+#define GPIO_PLOCK_PLOCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */
+#define GPIO_PLOCK_PLOCKK ((uint32_t)0x00010000) /*!< Lock key */
+
+/****************** Bit definition for GPIO_AFL register *******************/
+#define GPIO_AFL_AFSEL0 ((uint32_t)0x0000000F) /*!< Port x AFL bit (0..3) */
+#define GPIO_AFL_AFSEL1 ((uint32_t)0x000000F0) /*!< Port x AFL bit (4..7) */
+#define GPIO_AFL_AFSEL2 ((uint32_t)0x00000F00) /*!< Port x AFL bit (8..11) */
+#define GPIO_AFL_AFSEL3 ((uint32_t)0x0000F000) /*!< Port x AFL bit (12..15) */
+#define GPIO_AFL_AFSEL4 ((uint32_t)0x000F0000) /*!< Port x AFL bit (16..19) */
+#define GPIO_AFL_AFSEL5 ((uint32_t)0x00F00000) /*!< Port x AFL bit (20..23) */
+#define GPIO_AFL_AFSEL6 ((uint32_t)0x0F000000) /*!< Port x AFL bit (24..27) */
+#define GPIO_AFL_AFSEL7 ((uint32_t)0xF0000000) /*!< Port x AFL bit (27..31) */
+
+/****************** Bit definition for GPIO_AFH register *******************/
+#define GPIO_AFH_AFSEL8 ((uint32_t)0x0000000F) /*!< Port x AFH bit (0..3) */
+#define GPIO_AFH_AFSEL9 ((uint32_t)0x000000F0) /*!< Port x AFH bit (4..7) */
+#define GPIO_AFH_AFSEL10 ((uint32_t)0x00000F00) /*!< Port x AFH bit (8..11) */
+#define GPIO_AFH_AFSEL11 ((uint32_t)0x0000F000) /*!< Port x AFH bit (12..15) */
+#define GPIO_AFH_AFSEL12 ((uint32_t)0x000F0000) /*!< Port x AFH bit (16..19) */
+#define GPIO_AFH_AFSEL13 ((uint32_t)0x00F00000) /*!< Port x AFH bit (20..23) */
+#define GPIO_AFH_AFSEL14 ((uint32_t)0x0F000000) /*!< Port x AFH bit (24..27) */
+#define GPIO_AFH_AFSEL15 ((uint32_t)0xF0000000) /*!< Port x AFH bit (27..31) */
+
+
+/******************* Bit definition for GPIO_DS register ******************/
+#define GPIO_DS0_Pos (0)
+#define GPIO_DS0_Msk (0x3 << GPIO_DS0_Pos) /*!< 0x00000003 */
+#define GPIO_DS0 GPIO_DS0_Msk
+#define GPIO_DS0_0 (0x0 << GPIO_DS0_Pos) /*!< 0x00000000 */
+#define GPIO_DS0_1 (0x1 << GPIO_DS0_Pos) /*!< 0x00000001 */
+#define GPIO_DS0_2 (0x2 << GPIO_DS0_Pos) /*!< 0x00000002 */
+#define GPIO_DS0_3 (0x3 << GPIO_DS0_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS1_Pos (2)
+#define GPIO_DS1_Msk (0x3 << GPIO_DS1_Pos) /*!< 0x00000003 */
+#define GPIO_DS1 GPIO_DS1_Msk
+#define GPIO_DS1_0 (0x0 << GPIO_DS1_Pos) /*!< 0x00000000 */
+#define GPIO_DS1_1 (0x1 << GPIO_DS1_Pos) /*!< 0x00000001 */
+#define GPIO_DS1_2 (0x2 << GPIO_DS1_Pos) /*!< 0x00000002 */
+#define GPIO_DS1_3 (0x3 << GPIO_DS1_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS2_Pos (4)
+#define GPIO_DS2_Msk (0x3 << GPIO_DS2_Pos) /*!< 0x00000003 */
+#define GPIO_DS2 GPIO_DS2_Msk
+#define GPIO_DS2_0 (0x0 << GPIO_DS2_Pos) /*!< 0x00000000 */
+#define GPIO_DS2_1 (0x1 << GPIO_DS2_Pos) /*!< 0x00000001 */
+#define GPIO_DS2_2 (0x2 << GPIO_DS2_Pos) /*!< 0x00000002 */
+#define GPIO_DS2_3 (0x3 << GPIO_DS2_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS3_Pos (6)
+#define GPIO_DS3_Msk (0x3 << GPIO_DS3_Pos) /*!< 0x00000003 */
+#define GPIO_DS3 GPIO_DS3_Msk
+#define GPIO_DS3_0 (0x0 << GPIO_DS3_Pos) /*!< 0x00000000 */
+#define GPIO_DS3_1 (0x1 << GPIO_DS3_Pos) /*!< 0x00000001 */
+#define GPIO_DS3_2 (0x2 << GPIO_DS3_Pos) /*!< 0x00000002 */
+#define GPIO_DS3_3 (0x3 << GPIO_DS3_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS4_Pos (8)
+#define GPIO_DS4_Msk (0x3 << GPIO_DS4_Pos) /*!< 0x00000003 */
+#define GPIO_DS4 GPIO_DS4_Msk
+#define GPIO_DS4_0 (0x0 << GPIO_DS4_Pos) /*!< 0x00000000 */
+#define GPIO_DS4_1 (0x1 << GPIO_DS4_Pos) /*!< 0x00000001 */
+#define GPIO_DS4_2 (0x2 << GPIO_DS4_Pos) /*!< 0x00000002 */
+#define GPIO_DS4_3 (0x3 << GPIO_DS4_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS5_Pos (10)
+#define GPIO_DS5_Msk (0x3 << GPIO_DS5_Pos) /*!< 0x00000003 */
+#define GPIO_DS5 GPIO_DS5_Msk
+#define GPIO_DS5_0 (0x0 << GPIO_DS5_Pos) /*!< 0x00000000 */
+#define GPIO_DS5_1 (0x1 << GPIO_DS5_Pos) /*!< 0x00000001 */
+#define GPIO_DS5_2 (0x2 << GPIO_DS5_Pos) /*!< 0x00000002 */
+#define GPIO_DS5_3 (0x3 << GPIO_DS5_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS6_Pos (12)
+#define GPIO_DS6_Msk (0x3 << GPIO_DS6_Pos) /*!< 0x00000003 */
+#define GPIO_DS6 GPIO_DS6_Msk
+#define GPIO_DS6_0 (0x0 << GPIO_DS6_Pos) /*!< 0x00000000 */
+#define GPIO_DS6_1 (0x1 << GPIO_DS6_Pos) /*!< 0x00000001 */
+#define GPIO_DS6_2 (0x2 << GPIO_DS6_Pos) /*!< 0x00000002 */
+#define GPIO_DS6_3 (0x3 << GPIO_DS6_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS7_Pos (14)
+#define GPIO_DS7_Msk (0x3 << GPIO_DS7_Pos) /*!< 0x00000003 */
+#define GPIO_DS7 GPIO_DS7_Msk
+#define GPIO_DS7_0 (0x0 << GPIO_DS7_Pos) /*!< 0x00000000 */
+#define GPIO_DS7_1 (0x1 << GPIO_DS7_Pos) /*!< 0x00000001 */
+#define GPIO_DS7_2 (0x2 << GPIO_DS7_Pos) /*!< 0x00000002 */
+#define GPIO_DS7_3 (0x3 << GPIO_DS7_Pos) /*!< 0x00000003 */
+
+
+#define GPIO_DS8_Pos (16)
+#define GPIO_DS8_Msk (0x3 << GPIO_DS8_Pos) /*!< 0x00000003 */
+#define GPIO_DS8 GPIO_DS8_Msk
+#define GPIO_DS8_0 (0x0 << GPIO_DS8_Pos) /*!< 0x00000000 */
+#define GPIO_DS8_1 (0x1 << GPIO_DS8_Pos) /*!< 0x00000001 */
+#define GPIO_DS8_2 (0x2 << GPIO_DS8_Pos) /*!< 0x00000002 */
+#define GPIO_DS8_3 (0x3 << GPIO_DS8_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS9_Pos (18)
+#define GPIO_DS9_Msk (0x3 << GPIO_DS9_Pos) /*!< 0x00000003 */
+#define GPIO_DS9 GPIO_DS9_Msk
+#define GPIO_DS9_0 (0x0 << GPIO_DS9_Pos) /*!< 0x00000000 */
+#define GPIO_DS9_1 (0x1 << GPIO_DS9_Pos) /*!< 0x00000001 */
+#define GPIO_DS9_2 (0x2 << GPIO_DS9_Pos) /*!< 0x00000002 */
+#define GPIO_DS9_3 (0x3 << GPIO_DS9_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS10_Pos (20)
+#define GPIO_DS10_Msk (0x3 << GPIO_DS10_Pos) /*!< 0x00000003 */
+#define GPIO_DS10 GPIO_DS10_Msk
+#define GPIO_DS10_0 (0x0 << GPIO_DS10_Pos) /*!< 0x00000000 */
+#define GPIO_DS10_1 (0x1 << GPIO_DS10_Pos) /*!< 0x00000001 */
+#define GPIO_DS10_2 (0x2 << GPIO_DS10_Pos) /*!< 0x00000002 */
+#define GPIO_DS10_3 (0x3 << GPIO_DS10_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS11_Pos (22)
+#define GPIO_DS11_Msk (0x3 << GPIO_DS11_Pos) /*!< 0x00000003 */
+#define GPIO_DS11 GPIO_DS11_Msk
+#define GPIO_DS11_0 (0x0 << GPIO_DS11_Pos) /*!< 0x00000000 */
+#define GPIO_DS11_1 (0x1 << GPIO_DS11_Pos) /*!< 0x00000001 */
+#define GPIO_DS11_2 (0x2 << GPIO_DS11_Pos) /*!< 0x00000002 */
+#define GPIO_DS11_3 (0x3 << GPIO_DS11_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS12_Pos (24)
+#define GPIO_DS12_Msk (0x3 << GPIO_DS12_Pos) /*!< 0x00000003 */
+#define GPIO_DS12 GPIO_DS12_Msk
+#define GPIO_DS12_0 (0x0 << GPIO_DS12_Pos) /*!< 0x00000000 */
+#define GPIO_DS12_1 (0x1 << GPIO_DS12_Pos) /*!< 0x00000001 */
+#define GPIO_DS12_2 (0x2 << GPIO_DS12_Pos) /*!< 0x00000002 */
+#define GPIO_DS12_3 (0x3 << GPIO_DS12_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS13_Pos (26)
+#define GPIO_DS13_Msk (0x3 << GPIO_DS13_Pos) /*!< 0x00000003 */
+#define GPIO_DS13 GPIO_DS13_Msk
+#define GPIO_DS13_0 (0x0 << GPIO_DS13_Pos) /*!< 0x00000000 */
+#define GPIO_DS13_1 (0x1 << GPIO_DS13_Pos) /*!< 0x00000001 */
+#define GPIO_DS13_2 (0x2 << GPIO_DS13_Pos) /*!< 0x00000002 */
+#define GPIO_DS13_3 (0x3 << GPIO_DS13_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS14_Pos (28)
+#define GPIO_DS14_Msk (0x3 << GPIO_DS14_Pos) /*!< 0x00000003 */
+#define GPIO_DS14 GPIO_DS14_Msk
+#define GPIO_DS14_0 (0x0 << GPIO_DS14_Pos) /*!< 0x00000000 */
+#define GPIO_DS14_1 (0x1 << GPIO_DS14_Pos) /*!< 0x00000001 */
+#define GPIO_DS14_2 (0x2 << GPIO_DS14_Pos) /*!< 0x00000002 */
+#define GPIO_DS14_3 (0x3 << GPIO_DS14_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS15_Pos (30)
+#define GPIO_DS15_Msk (0x3 << GPIO_DS15_Pos) /*!< 0x00000003 */
+#define GPIO_DS15 GPIO_DS15_Msk
+#define GPIO_DS15_0 (0x0 << GPIO_DS15_Pos) /*!< 0x00000000 */
+#define GPIO_DS15_1 (0x1 << GPIO_DS15_Pos) /*!< 0x00000001 */
+#define GPIO_DS15_2 (0x2 << GPIO_DS15_Pos) /*!< 0x00000002 */
+#define GPIO_DS15_3 (0x3 << GPIO_DS15_Pos) /*!< 0x00000003 */
+
+/******************* Bit definition for GPIO_SR register *******************/
+#define GPIO_SR_SR0 ((uint16_t)0x0001) /*!< Slew rate bit 0 */
+#define GPIO_SR_SR1 ((uint16_t)0x0002) /*!< Slew rate bit 1 */
+#define GPIO_SR_SR2 ((uint16_t)0x0004) /*!< Slew rate bit 2 */
+#define GPIO_SR_SR3 ((uint16_t)0x0008) /*!< Slew rate bit 3 */
+#define GPIO_SR_SR4 ((uint16_t)0x0010) /*!< Slew rate bit 4 */
+#define GPIO_SR_SR5 ((uint16_t)0x0020) /*!< Slew rate bit 5 */
+#define GPIO_SR_SR6 ((uint16_t)0x0040) /*!< Slew rate bit 6 */
+#define GPIO_SR_SR7 ((uint16_t)0x0080) /*!< Slew rate bit 7 */
+#define GPIO_SR_SR8 ((uint16_t)0x0100) /*!< Slew rate bit 8 */
+#define GPIO_SR_SR9 ((uint16_t)0x0200) /*!< Slew rate bit 9 */
+#define GPIO_SR_SR10 ((uint16_t)0x0400) /*!< Slew rate bit 10 */
+#define GPIO_SR_SR11 ((uint16_t)0x0800) /*!< Slew rate bit 11 */
+#define GPIO_SR_SR12 ((uint16_t)0x1000) /*!< Slew rate bit 12 */
+#define GPIO_SR_SR13 ((uint16_t)0x2000) /*!< Slew rate bit 13 */
+#define GPIO_SR_SR14 ((uint16_t)0x4000) /*!< Slew rate bit 14 */
+#define GPIO_SR_SR15 ((uint16_t)0x8000) /*!< Slew rate bit 15 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for AFIO_RMP_CFG register *****************/
+#define AFIO_RMP_CFG_SPI1_NSS ((uint16_t)0x0800) /*!< AFIO_RMP_CFG bit 11 */
+#define AFIO_RMP_CFG_SPI2_NSS ((uint16_t)0x0400) /*!< AFIO_RMP_CFG bit 10 */
+#define AFIO_RMP_CFG_ADC_ETRI ((uint16_t)0x0200) /*!< AFIO_RMP_CFG bit 9 */
+#define AFIO_RMP_CFG_ADC_ETRR ((uint16_t)0x0100) /*!< AFIO_RMP_CFG bit 8 */
+#define AFIO_RMP_CFG_EXTI_ETRI ((uint16_t)0x00F0) /*!< AFIO_RMP_CFG bit (4..7) */
+#define AFIO_RMP_CFG_EXTI_ETRR ((uint16_t)0x000F) /*!< AFIO_RMP_CFG bit (0..3) */
+
+/***************** Bit definition for AFIO_EXTICR1 register *****************/
+#define AFIO_EXTI_CFG1_EXTI0 ((uint16_t)0x0003) /*!< EXTI 0 configuration */
+#define AFIO_EXTI_CFG1_EXTI1 ((uint16_t)0x0030) /*!< EXTI 1 configuration */
+#define AFIO_EXTI_CFG1_EXTI2 ((uint16_t)0x0300) /*!< EXTI 2 configuration */
+#define AFIO_EXTI_CFG1_EXTI3 ((uint16_t)0x3000) /*!< EXTI 3 configuration */
+
+/*!< EXTI0 configuration */
+#define AFIO_EXTI_CFG1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
+#define AFIO_EXTI_CFG1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
+#define AFIO_EXTI_CFG1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
+#define AFIO_EXTI_CFG1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
+
+/*!< EXTI1 configuration */
+#define AFIO_EXTI_CFG1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
+#define AFIO_EXTI_CFG1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
+#define AFIO_EXTI_CFG1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
+#define AFIO_EXTI_CFG1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
+
+/*!< EXTI2 configuration */
+#define AFIO_EXTI_CFG1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
+#define AFIO_EXTI_CFG1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
+#define AFIO_EXTI_CFG1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
+#define AFIO_EXTI_CFG1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
+
+/*!< EXTI3 configuration */
+#define AFIO_EXTI_CFG1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
+#define AFIO_EXTI_CFG1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
+#define AFIO_EXTI_CFG1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
+#define AFIO_EXTI_CFG1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
+
+/***************** Bit definition for AFIO_EXTICR2 register *****************/
+#define AFIO_EXTI_CFG2_EXTI4 ((uint16_t)0x0003) /*!< EXTI 4 configuration */
+#define AFIO_EXTI_CFG2_EXTI5 ((uint16_t)0x0030) /*!< EXTI 5 configuration */
+#define AFIO_EXTI_CFG2_EXTI6 ((uint16_t)0x0300) /*!< EXTI 6 configuration */
+#define AFIO_EXTI_CFG2_EXTI7 ((uint16_t)0x3000) /*!< EXTI 7 configuration */
+
+/*!< EXTI4 configuration */
+#define AFIO_EXTI_CFG2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
+#define AFIO_EXTI_CFG2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
+#define AFIO_EXTI_CFG2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
+#define AFIO_EXTI_CFG2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
+
+/*!< EXTI5 configuration */
+#define AFIO_EXTI_CFG2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
+#define AFIO_EXTI_CFG2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
+#define AFIO_EXTI_CFG2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
+#define AFIO_EXTI_CFG2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
+
+/*!< EXTI6 configuration */
+#define AFIO_EXTI_CFG2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
+#define AFIO_EXTI_CFG2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
+#define AFIO_EXTI_CFG2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
+#define AFIO_EXTI_CFG2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
+
+/*!< EXTI7 configuration */
+#define AFIO_EXTI_CFG2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
+#define AFIO_EXTI_CFG2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
+#define AFIO_EXTI_CFG2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
+#define AFIO_EXTI_CFG2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
+
+/***************** Bit definition for AFIO_EXTICR3 register *****************/
+#define AFIO_EXTI_CFG3_EXTI8 ((uint16_t)0x0003) /*!< EXTI 8 configuration */
+#define AFIO_EXTI_CFG3_EXTI9 ((uint16_t)0x0030) /*!< EXTI 9 configuration */
+#define AFIO_EXTI_CFG3_EXTI10 ((uint16_t)0x0300) /*!< EXTI 10 configuration */
+#define AFIO_EXTI_CFG3_EXTI11 ((uint16_t)0x3000) /*!< EXTI 11 configuration */
+
+/*!< EXTI8 configuration */
+#define AFIO_EXTI_CFG3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
+#define AFIO_EXTI_CFG3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
+#define AFIO_EXTI_CFG3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
+#define AFIO_EXTI_CFG3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
+
+/*!< EXTI9 configuration */
+#define AFIO_EXTI_CFG3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
+#define AFIO_EXTI_CFG3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
+#define AFIO_EXTI_CFG3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
+#define AFIO_EXTI_CFG3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
+
+/*!< EXTI10 configuration */
+#define AFIO_EXTI_CFG3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
+#define AFIO_EXTI_CFG3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
+#define AFIO_EXTI_CFG3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
+#define AFIO_EXTI_CFG3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
+
+/*!< EXTI11 configuration */
+#define AFIO_EXTI_CFG3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
+#define AFIO_EXTI_CFG3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
+#define AFIO_EXTI_CFG3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
+#define AFIO_EXTI_CFG3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
+
+/***************** Bit definition for AFIO_EXTICR4 register *****************/
+#define AFIO_EXTI_CFG4_EXTI12 ((uint16_t)0x0003) /*!< EXTI 12 configuration */
+#define AFIO_EXTI_CFG4_EXTI13 ((uint16_t)0x0030) /*!< EXTI 13 configuration */
+#define AFIO_EXTI_CFG4_EXTI14 ((uint16_t)0x0300) /*!< EXTI 14 configuration */
+#define AFIO_EXTI_CFG4_EXTI15 ((uint16_t)0x3000) /*!< EXTI 15 configuration */
+
+/*!< EXTI12 configuration */
+#define AFIO_EXTI_CFG4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
+#define AFIO_EXTI_CFG4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
+#define AFIO_EXTI_CFG4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
+#define AFIO_EXTI_CFG4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
+
+/*!< EXTI13 configuration */
+#define AFIO_EXTI_CFG4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
+#define AFIO_EXTI_CFG4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
+#define AFIO_EXTI_CFG4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
+#define AFIO_EXTI_CFG4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
+
+/*!< EXTI14 configuration */
+#define AFIO_EXTI_CFG4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
+#define AFIO_EXTI_CFG4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
+#define AFIO_EXTI_CFG4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
+#define AFIO_EXTI_CFG4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
+
+/*!< EXTI15 configuration */
+#define AFIO_EXTI_CFG4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
+#define AFIO_EXTI_CFG4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
+#define AFIO_EXTI_CFG4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
+#define AFIO_EXTI_CFG4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMASK_IMASK0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMASK_IMASK1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMASK_IMASK2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMASK_IMASK3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMASK_IMASK4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMASK_IMASK5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMASK_IMASK6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMASK_IMASK7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMASK_IMASK8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMASK_IMASK9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMASK_IMASK10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMASK_IMASK11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMASK_IMASK12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMASK_IMASK13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMASK_IMASK14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMASK_IMASK15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMASK_IMASK16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMASK_IMASK17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMASK_IMASK18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMASK_IMASK19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMASK_IMASK20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMASK_IMASK21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMASK_IMASK22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
+#define EXTI_IMASK_IMASK23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
+#define EXTI_IMASK_IMASK24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */
+#define EXTI_IMASK_IMASK25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
+#define EXTI_IMASK_IMASK26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
+#define EXTI_IMASK_IMASK27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMASK_EMASK0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMASK_EMASK1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMASK_EMASK2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMASK_EMASK3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMASK_EMASK4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMASK_EMASK5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMASK_EMASK6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMASK_EMASK7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMASK_EMASK8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMASK_EMASK9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMASK_EMASK10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMASK_EMASK11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMASK_EMASK12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMASK_EMASK13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMASK_EMASK14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMASK_EMASK15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMASK_EMASK16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMASK_EMASK17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMASK_EMASK18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+#define EXTI_EMASK_EMASK19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMASK_EMASK20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMASK_EMASK21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMASK_EMASK22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
+#define EXTI_EMASK_EMASK23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
+#define EXTI_EMASK_EMASK24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */
+#define EXTI_EMASK_EMASK25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
+#define EXTI_EMASK_EMASK26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
+#define EXTI_EMASK_EMASK27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
+
+
+/****************** Bit definition for EXTI_RT_CFG register *******************/
+#define EXTI_EMASK_RT_CFG_RT_CFG0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_EMASK_RT_CFG_RT_CFG1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_EMASK_RT_CFG_RT_CFG2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_EMASK_RT_CFG_RT_CFG3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_EMASK_RT_CFG_RT_CFG4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_EMASK_RT_CFG_RT_CFG5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_EMASK_RT_CFG_RT_CFG6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_EMASK_RT_CFG_RT_CFG7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_EMASK_RT_CFG_RT_CFG8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_EMASK_RT_CFG_RT_CFG9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_EMASK_RT_CFG_RT_CFG10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_EMASK_RT_CFG_RT_CFG11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_EMASK_RT_CFG_RT_CFG12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_EMASK_RT_CFG_RT_CFG13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_EMASK_RT_CFG_RT_CFG14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_EMASK_RT_CFG_RT_CFG15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_EMASK_RT_CFG_RT_CFG16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_EMASK_RT_CFG_RT_CFG17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_EMASK_RT_CFG_RT_CFG18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_EMASK_RT_CFG_RT_CFG19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_EMASK_RT_CFG_RT_CFG20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_EMASK_RT_CFG_RT_CFG21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_EMASK_RT_CFG_RT_CFG22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
+#define EXTI_EMASK_RT_CFG_RT_CFG23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
+#define EXTI_EMASK_RT_CFG_RT_CFG24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
+#define EXTI_EMASK_RT_CFG_RT_CFG25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
+#define EXTI_EMASK_RT_CFG_RT_CFG26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
+#define EXTI_EMASK_RT_CFG_RT_CFG27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
+
+
+
+/****************** Bit definition for EXTI_FT_CFG register *******************/
+#define EXTI_EMASK_FT_CFG_FT_CFG0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_EMASK_FT_CFG_FT_CFG1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_EMASK_FT_CFG_FT_CFG2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_EMASK_FT_CFG_FT_CFG3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_EMASK_FT_CFG_FT_CFG4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_EMASK_FT_CFG_FT_CFG5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_EMASK_FT_CFG_FT_CFG6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_EMASK_FT_CFG_FT_CFG7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_EMASK_FT_CFG_FT_CFG8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_EMASK_FT_CFG_FT_CFG9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_EMASK_FT_CFG_FT_CFG10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_EMASK_FT_CFG_FT_CFG11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_EMASK_FT_CFG_FT_CFG12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_EMASK_FT_CFG_FT_CFG13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_EMASK_FT_CFG_FT_CFG14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_EMASK_FT_CFG_FT_CFG15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_EMASK_FT_CFG_FT_CFG16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_EMASK_FT_CFG_FT_CFG17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_EMASK_FT_CFG_FT_CFG18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_EMASK_FT_CFG_FT_CFG19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_EMASK_FT_CFG_FT_CFG20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_EMASK_FT_CFG_FT_CFG21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_EMASK_FT_CFG_FT_CFG22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
+#define EXTI_EMASK_FT_CFG_FT_CFG23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
+#define EXTI_EMASK_FT_CFG_FT_CFG24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
+#define EXTI_EMASK_FT_CFG_FT_CFG25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
+#define EXTI_EMASK_FT_CFG_FT_CFG26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
+#define EXTI_EMASK_FT_CFG_FT_CFG27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
+
+/****************** Bit definition for EXTI_SWIE register ******************/
+#define EXTI_SWIE_SWIE0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIE_SWIE1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIE_SWIE2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIE_SWIE3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIE_SWIE4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIE_SWIE5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIE_SWIE6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIE_SWIE7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIE_SWIE8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIE_SWIE9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIE_SWIE10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIE_SWIE11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIE_SWIE12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIE_SWIE13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIE_SWIE14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIE_SWIE15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIE_SWIE16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIE_SWIE17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIE_SWIE18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
+#define EXTI_SWIE_SWIE19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIE_SWIE20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIE_SWIE21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIE_SWIE22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
+#define EXTI_SWIE_SWIE23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
+#define EXTI_SWIE_SWIE24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
+#define EXTI_SWIE_SWIE25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
+#define EXTI_SWIE_SWIE26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
+#define EXTI_SWIE_SWIE27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
+
+/******************* Bit definition for EXTI_PEND register ********************/
+#define EXTI_PEND_PEND0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
+#define EXTI_PEND_PEND1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
+#define EXTI_PEND_PEND2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
+#define EXTI_PEND_PEND3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
+#define EXTI_PEND_PEND4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
+#define EXTI_PEND_PEND5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
+#define EXTI_PEND_PEND6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
+#define EXTI_PEND_PEND7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
+#define EXTI_PEND_PEND8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
+#define EXTI_PEND_PEND9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
+#define EXTI_PEND_PEND10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
+#define EXTI_PEND_PEND11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
+#define EXTI_PEND_PEND12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
+#define EXTI_PEND_PEND13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
+#define EXTI_PEND_PEND14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
+#define EXTI_PEND_PEND15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
+#define EXTI_PEND_PEND16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
+#define EXTI_PEND_PEND17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
+#define EXTI_PEND_PEND18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
+#define EXTI_PEND_PEND19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PEND_PEND20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PEND_PEND21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PEND_PEND22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
+#define EXTI_PEND_PEND23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
+#define EXTI_PEND_PEND24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
+#define EXTI_PEND_PEND25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
+#define EXTI_PEND_PEND26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
+#define EXTI_PEND_PEND27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
+
+/******************************************************************************/
+/* */
+/* TSC Registers */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for TSC_CTRL register ****************/
+#define TSC_CTRL_TM2_ETR_CH1_Msk ((uint32_t)0x2000)
+#define TSC_CTRL_TM2_ETR_CH1_Pos (13U)
+#define TSC_CTRL_TM2_ETR_CH1 (TSC_CTRL_TM2_ETR_CH1_Msk) /*!FLASH
+
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ /* section information for finsh shell */
+ . = ALIGN(4);
+ __fsymtab_start = .;
+ KEEP(*(FSymTab))
+ __fsymtab_end = .;
+
+ . = ALIGN(4);
+ __vsymtab_start = .;
+ KEEP(*(VSymTab))
+ __vsymtab_end = .;
+
+ /* section information for initial. */
+ . = ALIGN(4);
+ __rt_init_start = .;
+ KEEP(*(SORT(.rti_fn*)))
+ __rt_init_end = .;
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data goes into FLASH */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >FLASH
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH
+
+ /* used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(4);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(4);
+ } >RAM
+
+
+
+ /* Remove information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/startup/startup_n32g43x.s b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/startup/startup_n32g43x.s
new file mode 100644
index 0000000000..ac31cd6e13
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/startup/startup_n32g43x.s
@@ -0,0 +1,371 @@
+; ****************************************************************************
+; Copyright (c) 2019, Nations Technologies Inc.
+;
+; All rights reserved.
+; ****************************************************************************
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; - Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the disclaimer below.
+;
+; Nations' name may not be used to endorse or promote products derived from
+; this software without specific prior written permission.
+;
+; DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+; DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+; OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; ****************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00001500
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000300
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; RTC Tamper interrupt or Timestamp through EXTI line 19 interrupt
+ DCD RTC_WKUP_IRQHandler ; RTC_WKUP
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA_Channel1_IRQHandler ; DMA Channel 1
+ DCD DMA_Channel2_IRQHandler ; DMA Channel 2
+ DCD DMA_Channel3_IRQHandler ; DMA Channel 3
+ DCD DMA_Channel4_IRQHandler ; DMA Channel 4
+ DCD DMA_Channel5_IRQHandler ; DMA Channel 5
+ DCD DMA_Channel6_IRQHandler ; DMA Channel 6
+ DCD DMA_Channel7_IRQHandler ; DMA Channel 7
+ DCD DMA_Channel8_IRQHandler ; DMA Channel 8
+ DCD ADC_IRQHandler ; ADC
+ DCD USB_HP_IRQHandler ; USB High Priority
+ DCD USB_LP_IRQHandler ; USB Low Priority
+ DCD COMP_1_2_IRQHandler ; COMP1 & COMP2 through EXTI line 21/22
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
+ DCD TIM8_BRK_IRQHandler ; TIM8 Break
+ DCD TIM8_UP_IRQHandler ; TIM8 Update
+ DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD LPUART_IRQHandler ; LPUART
+ DCD TIM5_IRQHandler ; TIM5
+ DCD TIM6_IRQHandler ; TIM6
+ DCD TIM7_IRQHandler ; TIM7
+ DCD CAN_TX_IRQHandler ; CAN TX
+ DCD CAN_RX0_IRQHandler ; CAN RX0
+ DCD CAN_RX1_IRQHandler ; CAN RX1
+ DCD CAN_SCE_IRQHandler ; CAN SCE
+ DCD LPUART_WKUP_IRQHandler ; LPUART_WKUP
+ DCD LPTIM_WKUP_IRQHandler ; LPTIM_WKUP
+ DCD 0 ; Reserved
+ DCD SAC_IRQHandler ; SAC
+ DCD MMU_IRQHandler ; MMU
+ DCD TSC_IRQHandler ; TSC
+ DCD RAMC_PERR_IRQHandler ; RAMC ERR
+ DCD TIM9_IRQHandler ; TIM9
+ DCD UCDR_IRQHandler ; UCDR ERR
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ IMPORT SystemInit
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_IRQHandler [WEAK]
+ EXPORT TAMPER_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA_Channel1_IRQHandler [WEAK]
+ EXPORT DMA_Channel2_IRQHandler [WEAK]
+ EXPORT DMA_Channel3_IRQHandler [WEAK]
+ EXPORT DMA_Channel4_IRQHandler [WEAK]
+ EXPORT DMA_Channel5_IRQHandler [WEAK]
+ EXPORT DMA_Channel6_IRQHandler [WEAK]
+ EXPORT DMA_Channel7_IRQHandler [WEAK]
+ EXPORT DMA_Channel8_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT USB_HP_IRQHandler [WEAK]
+ EXPORT USB_LP_IRQHandler [WEAK]
+ EXPORT COMP_1_2_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTCAlarm_IRQHandler [WEAK]
+ EXPORT USBWakeUp_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_IRQHandler [WEAK]
+ EXPORT TIM8_UP_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT LPUART_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT TIM6_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT CAN_TX_IRQHandler [WEAK]
+ EXPORT CAN_RX0_IRQHandler [WEAK]
+ EXPORT CAN_RX1_IRQHandler [WEAK]
+ EXPORT CAN_SCE_IRQHandler [WEAK]
+ EXPORT LPUART_WKUP_IRQHandler [WEAK]
+ EXPORT LPTIM_WKUP_IRQHandler [WEAK]
+ EXPORT SAC_IRQHandler [WEAK]
+ EXPORT MMU_IRQHandler [WEAK]
+ EXPORT TSC_IRQHandler [WEAK]
+ EXPORT RAMC_PERR_IRQHandler [WEAK]
+ EXPORT TIM9_IRQHandler [WEAK]
+ EXPORT UCDR_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA_Channel1_IRQHandler
+DMA_Channel2_IRQHandler
+DMA_Channel3_IRQHandler
+DMA_Channel4_IRQHandler
+DMA_Channel5_IRQHandler
+DMA_Channel6_IRQHandler
+DMA_Channel7_IRQHandler
+DMA_Channel8_IRQHandler
+ADC_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+COMP_1_2_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+USBWakeUp_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+LPUART_IRQHandler
+TIM5_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+CAN_TX_IRQHandler
+CAN_RX0_IRQHandler
+CAN_RX1_IRQHandler
+CAN_SCE_IRQHandler
+LPUART_WKUP_IRQHandler
+LPTIM_WKUP_IRQHandler
+SAC_IRQHandler
+MMU_IRQHandler
+TSC_IRQHandler
+RAMC_PERR_IRQHandler
+TIM9_IRQHandler
+UCDR_IRQHandler
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/startup/startup_n32g43x_EWARM.s b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/startup/startup_n32g43x_EWARM.s
new file mode 100644
index 0000000000..e9a39bed20
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/startup/startup_n32g43x_EWARM.s
@@ -0,0 +1,523 @@
+; ****************************************************************************
+; Copyright (c) 2019, Nations Technologies Inc.
+;
+; All rights reserved.
+; ****************************************************************************
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; - Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the disclaimer below.
+;
+; Nations name may not be used to endorse or promote products derived from
+; this software without specific prior written permission.
+;
+; DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+; DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+; OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; ****************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; RTC Tamper interrupt or Timestamp through EXTI line 19 interrupt
+ DCD RTC_WKUP_IRQHandler ; RTC_WKUP
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD DMA_Channel8_IRQHandler ; DMA Channel 8
+ DCD ADC_IRQHandler ; ADC
+ DCD USB_HP_IRQHandler ; USB High Priority
+ DCD USB_LP_IRQHandler ; USB Low Priority
+ DCD COMP_1_2_IRQHandler ; COMP1 & COMP2 through EXTI line 21/22
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
+ DCD TIM8_BRK_IRQHandler ; TIM8 Break
+ DCD TIM8_UP_IRQHandler ; TIM8 Update
+ DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD LPUART_IRQHandler ; LPUART
+ DCD TIM5_IRQHandler ; TIM5
+ DCD TIM6_IRQHandler ; TIM6
+ DCD TIM7_IRQHandler ; TIM7
+ DCD CAN_TX_IRQHandler ; CAN TX
+ DCD CAN_RX0_IRQHandler ; CAN RX0
+ DCD CAN_RX1_IRQHandler ; CAN RX1
+ DCD CAN_SCE_IRQHandler ; CAN SCE
+ DCD LPUART_WKUP_IRQHandler ; LPUART_WKUP
+ DCD LPTIM_WKUP_IRQHandler ; LPTIM_WKUP
+ DCD LCD_IRQHandler ; LCD
+ DCD SAC_IRQHandler ; SAC
+ DCD MMU_IRQHandler ; MMU
+ DCD TSC_IRQHandler ; TSC
+ DCD RAMC_PERR_IRQHandler ; RAMC ERR
+ DCD TIM9_IRQHandler ; TIM9
+ DCD UCDR_IRQHandler ; UCDR ERR
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+ PUBWEAK TAMPER_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TAMPER_IRQHandler
+ B TAMPER_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel1_IRQHandler
+ B DMA_Channel1_IRQHandler
+
+ PUBWEAK DMA_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel2_IRQHandler
+ B DMA_Channel2_IRQHandler
+
+ PUBWEAK DMA_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel3_IRQHandler
+ B DMA_Channel3_IRQHandler
+
+ PUBWEAK DMA_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel4_IRQHandler
+ B DMA_Channel4_IRQHandler
+
+ PUBWEAK DMA_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel5_IRQHandler
+ B DMA_Channel5_IRQHandler
+
+ PUBWEAK DMA_Channel6_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel6_IRQHandler
+ B DMA_Channel6_IRQHandler
+
+ PUBWEAK DMA_Channel7_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel7_IRQHandler
+ B DMA_Channel7_IRQHandler
+
+ PUBWEAK DMA_Channel8_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel8_IRQHandler
+ B DMA_Channel8_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK USB_HP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USB_HP_IRQHandler
+ B USB_HP_IRQHandler
+
+ PUBWEAK USB_LP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USB_LP_IRQHandler
+ B USB_LP_IRQHandler
+
+ PUBWEAK COMP_1_2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+COMP_1_2_IRQHandler
+ B COMP_1_2_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTCAlarm_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTCAlarm_IRQHandler
+ B RTCAlarm_IRQHandler
+
+ PUBWEAK USBWakeUp_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USBWakeUp_IRQHandler
+ B USBWakeUp_IRQHandler
+
+ PUBWEAK TIM8_BRK_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_BRK_IRQHandler
+ B TIM8_BRK_IRQHandler
+
+ PUBWEAK TIM8_UP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_UP_IRQHandler
+ B TIM8_UP_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_TRG_COM_IRQHandler
+ B TIM8_TRG_COM_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK LPUART_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+LPUART_IRQHandler
+ B LPUART_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK TIM6_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM6_IRQHandler
+ B TIM6_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK CAN_TX_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN_TX_IRQHandler
+ B CAN_TX_IRQHandler
+
+ PUBWEAK CAN_RX0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN_RX0_IRQHandler
+ B CAN_RX0_IRQHandler
+
+ PUBWEAK CAN_RX1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN_RX1_IRQHandler
+ B CAN_RX1_IRQHandler
+
+ PUBWEAK CAN_SCE_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN_SCE_IRQHandler
+ B CAN_SCE_IRQHandler
+
+ PUBWEAK LPUART_WKUP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+LPUART_WKUP_IRQHandler
+ B LPUART_WKUP_IRQHandler
+
+ PUBWEAK LPTIM_WKUP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+LPTIM_WKUP_IRQHandler
+ B LPTIM_WKUP_IRQHandler
+
+ PUBWEAK LCD_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+LCD_IRQHandler
+ B LCD_IRQHandler
+
+ PUBWEAK SAC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SAC_IRQHandler
+ B SAC_IRQHandler
+
+ PUBWEAK MMU_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MMU_IRQHandler
+ B MMU_IRQHandler
+
+ PUBWEAK TSC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TSC_IRQHandler
+ B TSC_IRQHandler
+
+ PUBWEAK RAMC_PERR_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RAMC_PERR_IRQHandler
+ B RAMC_PERR_IRQHandler
+
+ PUBWEAK TIM9_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM9_IRQHandler
+ B TIM9_IRQHandler
+
+ PUBWEAK UCDR_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UCDR_IRQHandler
+ B UCDR_IRQHandler
+
+
+ END
+
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/startup/startup_n32g43x_gcc.s b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/startup/startup_n32g43x_gcc.s
new file mode 100644
index 0000000000..2c7059ddc5
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/startup/startup_n32g43x_gcc.s
@@ -0,0 +1,450 @@
+/**
+ ****************************************************************************
+ Copyright (c) 2019, Nations Technologies Inc.
+
+ All rights reserved.
+ ****************************************************************************
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ - Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the disclaimer below.
+
+ Nations' name may not be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+ DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************
+ **/
+
+/**
+******************************************************************************
+* @file startup_n32g43x_gcc.s
+******************************************************************************
+*/
+
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+ Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl entry
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_IRQHandler /* PVD through EXTI Line detection */
+ .word TAMPER_IRQHandler /* Tamper */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA_Channel1_IRQHandler /* DMA1 Channel 1 */
+ .word DMA_Channel2_IRQHandler /* DMA1 Channel 2 */
+ .word DMA_Channel3_IRQHandler /* DMA1 Channel 3 */
+ .word DMA_Channel4_IRQHandler /* DMA1 Channel 4 */
+ .word DMA_Channel5_IRQHandler /* DMA1 Channel 5 */
+ .word DMA_Channel6_IRQHandler /* DMA1 Channel 6 */
+ .word DMA_Channel7_IRQHandler /* DMA1 Channel 7 */
+ .word DMA_Channel8_IRQHandler /* DMA1 Channel 8 */
+ .word ADC_IRQHandler /* ADC */
+ .word USB_HP_IRQHandler /* USB High Priority */
+ .word USB_LP_IRQHandler /* USB Low Priority */
+ .word COMP_1_2_IRQHandler /* COMP1 & COMP2 through EXTI line 21/22 */
+ .word EXTI9_5_IRQHandler /* EXTI Line 9..5 */
+ .word TIM1_BRK_IRQHandler /* TIM1 Break */
+ .word TIM1_UP_IRQHandler /* TIM1 Update */
+ .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */
+ .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
+ .word USBWakeUp_IRQHandler /* USB Wakeup from suspend */
+ .word TIM8_BRK_IRQHandler /* TIM8 Break */
+ .word TIM8_UP_IRQHandler /* TIM8 Update */
+ .word TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word LPUART_IRQHandler /* LPUART */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word TIM6_IRQHandler /* TIM6 */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word CAN_TX_IRQHandler /* CAN TX */
+ .word CAN_RX0_IRQHandler /* CAN RX0 */
+ .word CAN_RX1_IRQHandler /* CAN RX1 */
+ .word CAN_SCE_IRQHandler /* CAN SCE */
+ .word LPUART_WKUP_IRQHandler /* LPUART_WKUP */
+ .word LPTIM_WKUP_IRQHandler /* LPTIM_WKUP */
+ .word LCD_IRQHandler /* LCD */
+ .word SAC_IRQHandler /* SAC */
+ .word MMU_IRQHandler /* MMU */
+ .word TSC_IRQHandler /* TSC */
+ .word RAMC_PERR_IRQHandler /* RAMC ERR */
+ .word TIM9_IRQHandler /* TIM9 */
+ .word UCDR_IRQHandler /* UCDR ERR */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA_Channel1_IRQHandler
+ .thumb_set DMA_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA_Channel2_IRQHandler
+ .thumb_set DMA_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA_Channel3_IRQHandler
+ .thumb_set DMA_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA_Channel4_IRQHandler
+ .thumb_set DMA_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA_Channel5_IRQHandler
+ .thumb_set DMA_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA_Channel6_IRQHandler
+ .thumb_set DMA_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA_Channel7_IRQHandler
+ .thumb_set DMA_Channel7_IRQHandler,Default_Handler
+
+ .weak DMA_Channel8_IRQHandler
+ .thumb_set DMA_Channel8_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak USB_HP_IRQHandler
+ .thumb_set USB_HP_IRQHandler,Default_Handler
+
+ .weak USB_LP_IRQHandler
+ .thumb_set USB_LP_IRQHandler,Default_Handler
+
+ .weak COMP_1_2_IRQHandler
+ .thumb_set COMP_1_2_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTCAlarm_IRQHandler
+ .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_IRQHandler
+ .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_IRQHandler
+ .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_IRQHandler
+ .thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_IRQHandler
+ .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak LPUART_IRQHandler
+ .thumb_set LPUART_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak TIM6_IRQHandler
+ .thumb_set TIM6_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak CAN_TX_IRQHandler
+ .thumb_set CAN_TX_IRQHandler,Default_Handler
+
+ .weak CAN_RX0_IRQHandler
+ .thumb_set CAN_RX0_IRQHandler,Default_Handler
+
+ .weak CAN_RX1_IRQHandler
+ .thumb_set CAN_RX1_IRQHandler,Default_Handler
+
+ .weak CAN_SCE_IRQHandler
+ .thumb_set CAN_SCE_IRQHandler,Default_Handler
+
+ .weak LPUART_WKUP_IRQHandler
+ .thumb_set LPUART_WKUP_IRQHandler,Default_Handler
+
+ .weak LPTIM_WKUP_IRQHandler
+ .thumb_set LPTIM_WKUP_IRQHandler,Default_Handler
+
+ .weak LCD_IRQHandler
+ .thumb_set LCD_IRQHandler,Default_Handler
+
+ .weak SAC_IRQHandler
+ .thumb_set SAC_IRQHandler,Default_Handler
+
+ .weak MMU_IRQHandler
+ .thumb_set MMU_IRQHandler,Default_Handler
+
+ .weak TSC_IRQHandler
+ .thumb_set TSC_IRQHandler,Default_Handler
+
+ .weak RAMC_PERR_IRQHandler
+ .thumb_set RAMC_PERR_IRQHandler,Default_Handler
+
+ .weak TIM9_IRQHandler
+ .thumb_set TIM9_IRQHandler,Default_Handler
+
+ .weak UCDR_IRQHandler
+ .thumb_set UCDR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/system_n32g43x.c b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/system_n32g43x.c
new file mode 100644
index 0000000000..5d73468ce7
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/system_n32g43x.c
@@ -0,0 +1,615 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file system_n32g43x.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x.h"
+
+/* Uncomment the line corresponding to the desired System clock (SYSCLK)
+ frequency (after reset the HSI is used as SYSCLK source)
+
+ IMPORTANT NOTE:
+ ==============
+ 1. After each device reset the HSI is used as System clock source.
+
+ 2. Please make sure that the selected System clock doesn't exceed your
+ device's maximum frequency.
+
+ 3. If none of the define below is enabled, the HSI is used as System clock
+ source.
+
+ 4. The System clock configuration functions provided within this file assume
+ that:
+ - For Low, Medium and High density Value line devices an external 8MHz
+ crystal is used to drive the System clock.
+ - For Low, Medium and High density devices an external 8MHz crystal is
+ used to drive the System clock.
+ - For Connectivity line devices an external 25MHz crystal is used to
+ drive the System clock. If you are using different crystal you have to adapt
+ those functions accordingly.
+ */
+
+#define SYSCLK_USE_MSI 0
+#define SYSCLK_USE_HSI 1
+#define SYSCLK_USE_HSE 2
+#define SYSCLK_USE_HSI_PLL 3
+#define SYSCLK_USE_HSE_PLL 4
+
+#ifndef SYSCLK_FREQ
+#define SYSCLK_FREQ 108000000
+#endif
+
+/*
+* SYSCLK_SRC *
+** SYSCLK_USE_MSI **
+** SYSCLK_USE_HSI **
+** SYSCLK_USE_HSE **
+** SYSCLK_USE_HSI_PLL **
+** SYSCLK_USE_HSE_PLL **
+*/
+#ifndef SYSCLK_SRC
+#define SYSCLK_SRC SYSCLK_USE_HSE_PLL
+#endif
+
+#define PLL_DIV2_DISABLE 0x00000000
+#define PLL_DIV2_ENABLE 0x00000002
+
+#if SYSCLK_SRC == SYSCLK_USE_MSI
+
+ #if (SYSCLK_FREQ == MSI_VALUE_L0)
+ #define MSI_CLK 0
+ #elif (SYSCLK_FREQ == MSI_VALUE_L1)
+ #define MSI_CLK 1
+ #elif (SYSCLK_FREQ == MSI_VALUE_L2)
+ #define MSI_CLK 2
+ #elif (SYSCLK_FREQ == MSI_VALUE_L3)
+ #define MSI_CLK 3
+ #elif (SYSCLK_FREQ == MSI_VALUE_L4)
+ #define MSI_CLK 4
+ #elif (SYSCLK_FREQ == MSI_VALUE_L5)
+ #define MSI_CLK 5
+ #elif (SYSCLK_FREQ == MSI_VALUE_L6)
+ #define MSI_CLK 6
+ #else
+ #error SYSCL_FREQ must be set to MSI_VALUE_Lx(x=0~6)
+ #endif
+
+#elif SYSCLK_SRC == SYSCLK_USE_HSI
+
+ #if SYSCLK_FREQ != HSI_VALUE
+ #error SYSCL_FREQ must be set to HSI_VALUE
+ #endif
+
+#elif SYSCLK_SRC == SYSCLK_USE_HSE
+
+ #ifndef HSE_VALUE
+ #error HSE_VALUE must be defined!
+ #endif
+
+ #if SYSCLK_FREQ != HSE_VALUE
+ #error SYSCL_FREQ must be set to HSE_VALUE
+ #endif
+
+#elif SYSCLK_SRC == SYSCLK_USE_HSI_PLL
+
+ #ifndef HSI_VALUE
+ #error HSI_VALUE must be defined!
+ #endif
+
+ #if ((SYSCLK_FREQ % (HSI_VALUE / 2)) == 0) && (SYSCLK_FREQ / (HSI_VALUE / 2) >= 2) \
+ && (SYSCLK_FREQ / (HSI_VALUE / 2) <= 32)
+
+ #define PLLSRC_DIV 2
+ #define PLL_DIV PLL_DIV2_DISABLE
+ #define PLL_MUL (SYSCLK_FREQ / (HSI_VALUE / 2))
+
+ #elif (SYSCLK_FREQ % HSI_VALUE == 0) && (SYSCLK_FREQ / HSI_VALUE >= 2) && (SYSCLK_FREQ / HSI_VALUE <= 32)
+
+ #define PLLSRC_DIV 1
+ #define PLL_DIV PLL_DIV2_DISABLE
+ #define PLL_MUL (SYSCLK_FREQ / HSI_VALUE)
+
+ #elif ((SYSCLK_FREQ % (HSI_VALUE / 4)) == 0) && (SYSCLK_FREQ / (HSI_VALUE / 4) >= 2) \
+ && (SYSCLK_FREQ / (HSI_VALUE / 4) <= 32)
+
+ #define PLLSRC_DIV 2
+ #define PLL_DIV PLL_DIV2_ENABLE
+ #define PLL_MUL (SYSCLK_FREQ / (HSI_VALUE / 4))
+
+ #else
+ #error Cannot make a PLL multiply factor to SYSCLK_FREQ.
+ #endif
+
+#elif SYSCLK_SRC == SYSCLK_USE_HSE_PLL
+
+ #ifndef HSE_VALUE
+ #error HSE_VALUE must be defined!
+ #endif
+
+ #if ((SYSCLK_FREQ % (HSE_VALUE / 2)) == 0) && (SYSCLK_FREQ / (HSE_VALUE / 2) >= 2) \
+ && (SYSCLK_FREQ / (HSE_VALUE / 2) <= 32)
+
+ #define PLLSRC_DIV 2
+ #define PLL_DIV PLL_DIV2_DISABLE
+ #define PLL_MUL (SYSCLK_FREQ / (HSE_VALUE / 2))
+
+ #elif (SYSCLK_FREQ % HSE_VALUE == 0) && (SYSCLK_FREQ / HSE_VALUE >= 2) && (SYSCLK_FREQ / HSE_VALUE <= 32)
+
+ #define PLLSRC_DIV 1
+ #define PLL_DIV PLL_DIV2_DISABLE
+ #define PLL_MUL (SYSCLK_FREQ / HSE_VALUE)
+
+ #elif ((SYSCLK_FREQ % (HSE_VALUE / 4)) == 0) && (SYSCLK_FREQ / (HSE_VALUE / 4) >= 2) \
+ && (SYSCLK_FREQ / (HSE_VALUE / 4) <= 32)
+
+ #define PLLSRC_DIV 2
+ #define PLL_DIV PLL_DIV2_ENABLE
+ #define PLL_MUL (SYSCLK_FREQ / (HSE_VALUE / 4))
+
+ #else
+ #error Cannot make a PLL multiply factor to SYSCLK_FREQ.
+ #endif
+
+#else
+#error wrong value for SYSCLK_SRC
+#endif
+
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */
+
+/*******************************************************************************
+ * Clock Definitions
+ *******************************************************************************/
+uint32_t SystemCoreClock = SYSCLK_FREQ; /*!< System Clock Frequency (Core Clock) */
+
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint32_t MSIClockTable[7] = {MSI_VALUE_L0, MSI_VALUE_L1, MSI_VALUE_L2, MSI_VALUE_L3,
+ MSI_VALUE_L4, MSI_VALUE_L5, MSI_VALUE_L6};
+
+static void SetSysClock(void);
+
+#ifdef DATA_IN_ExtSRAM
+static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the Embedded Flash Interface, the PLL and update the
+ * SystemCoreClock variable.
+ * @note This function should be used only after reset.
+ */
+void SystemInit(void)
+{
+ /* FPU settings
+ * ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
+
+ /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+ /* Set MSIEN bit */
+ RCC->CTRLSTS |= (uint32_t)0x00000004;
+
+ /* Reset SW, HPRE, PPRE1, PPRE2 and MCO bits */
+ RCC->CFG &= (uint32_t)0xF8FFC000;
+
+ /* Reset HSEON, CLKSSEN and PLLEN bits */
+ RCC->CTRL &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CTRL &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL, MCOPRES and USBPRES bits */
+ RCC->CFG &= (uint32_t)0x0700FFFF;
+
+ /* Reset CFG2 register */
+ RCC->CFG2 = 0x00007000;
+
+ /* Reset CFG3 register */
+ RCC->CFG3 = 0x00003800;
+
+ /* Reset RDCTRL register */
+ RCC->RDCTRL = 0x00000000;
+
+ /* Reset PLLHSIPRE register */
+ RCC->PLLHSIPRE = 0x00000000;
+
+ /* Disable all interrupts and clear pending bits */
+ RCC->CLKINT = 0x04BF8000;
+
+ /* Enable ex mode */
+ RCC->APB1PCLKEN |= RCC_APB1PCLKEN_PWREN;
+ RCC->APB1PCLKEN &= (uint32_t)(~RCC_APB1PCLKEN_PWREN);
+
+ /* Enable ICACHE and Prefetch Buffer */
+ FLASH->AC |= (uint32_t)(FLASH_AC_ICAHEN | FLASH_AC_PRFTBFEN);
+
+ /* Checks whether the Low Voltage Mode status is SET or RESET */
+ if ((FLASH->AC & FLASH_AC_LVMF) != RESET)
+ {
+ /* FLASH Low Voltage Mode Disable */
+ FLASH->AC &= (uint32_t)(~FLASH_AC_LVMEN);
+ }
+
+#ifdef DATA_IN_ExtSRAM
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM */
+
+ /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+ /* Configure the Flash Latency cycles and enable prefetch buffer */
+ SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or
+ * configure other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any
+ * configuration based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is MSI, SystemCoreClock will contain the
+ * MSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the
+ * HSI_VALUE(**)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the
+ * HSE_VALUE(***)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the
+ * HSE_VALUE(***) or HSI_VALUE(**) multiplied by the PLL factors.
+ *
+ * (*) MSI_VALUE is a constant defined in n32g43x.h file (default value
+ * 4 MHz, 100KHz/200KHz/400KHz/800KHz/1MHz/2MHz/4MHz ) but the real
+ * value may vary depending on the variations in voltage and temperature.
+ *
+ * (**) HSI_VALUE is a constant defined in n32g43x.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (***) HSE_VALUE is a constant defined in n32g43x.h file (default value
+ * 8 MHz or 25 MHz, depedning on the product used), user has to
+ * ensure that HSE_VALUE is same as the real frequency of the crystal used.
+ * Otherwise, this function may have wrong result.
+ *
+ * - The result of this function could be not correct when using
+ * fractional value for HSE crystal.
+ */
+void SystemCoreClockUpdate(void)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0, plldiv2 = 0;
+ uint8_t msi_clk = 0;
+
+ /* Get SYSCLK source
+ * -------------------------------------------------------*/
+ tmp = RCC->CFG & RCC_CFG_SCLKSTS;
+
+ /* Get MSI clock
+ * -------------------------------------------------------*/
+ msi_clk = (uint8_t) ((RCC->CTRLSTS & RCC_CTRLSTS_MSIRANGE)>>4);
+
+ switch (tmp)
+ {
+ case 0x00: /* MSI used as system clock */
+ SystemCoreClock = MSIClockTable[msi_clk];
+ break;
+ case 0x04: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x08: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x0C: /* PLL used as system clock */
+
+ /* Get PLL clock source and multiplication factor
+ * ----------------------*/
+ pllmull = RCC->CFG & RCC_CFG_PLLMULFCT;
+ pllsource = RCC->CFG & RCC_CFG_PLLSRC;
+ plldiv2 = RCC->PLLHSIPRE & RCC_PLLHSIPRE_PLLSRCDIV;
+
+ if ((pllmull & RCC_CFG_PLLMULFCT_4) == 0)
+ {
+ pllmull = (pllmull >> 18) + 2; // PLLMUL[4]=0
+ }
+ else
+ {
+ pllmull = ((pllmull >> 18) - 496) + 1; // PLLMUL[4]=1
+ }
+
+ if (pllsource == 0x00)
+ {
+ /* HSI selected as PLL clock entry */
+ if ((RCC->PLLHSIPRE & RCC_PLLHSIPRE_PLLSRCDIV) != (uint32_t)RESET)
+ { /* HSI oscillator clock divided by 2 */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ SystemCoreClock = HSI_VALUE * pllmull;
+ }
+ }
+ else
+ {
+ /* HSE selected as PLL clock entry */
+ if ((RCC->CFG & RCC_CFG_PLLHSEPRES) != (uint32_t)RESET)
+ { /* HSE oscillator clock divided by 2 */
+ SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ SystemCoreClock = HSE_VALUE * pllmull;
+ }
+ }
+
+ if (plldiv2 == 0x02)
+ {
+ /* PLL source clock divided by 2 selected as PLL clock entry */
+ SystemCoreClock >>= 1;
+ }
+
+ break;
+
+ default:
+ SystemCoreClock = MSIClockTable[msi_clk];
+ break;
+ }
+
+ /* Compute HCLK clock frequency ----------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFG & RCC_CFG_AHBPRES) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/**
+ * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1
+ * prescalers.
+ */
+static void SetSysClock(void)
+{
+ uint32_t rcc_cfg = 0;
+ uint32_t rcc_pllhsipre = 0;
+ uint32_t StartUpCounter = 0;
+
+#if (SYSCLK_SRC == SYSCLK_USE_MSI)
+ uint8_t i=0;
+ bool MSIStatus = 0;
+ /* Config MSI */
+ RCC->CTRLSTS &= 0xFFFFFF8F;
+ /*Delay for while*/
+ for(i=0;i<0x30;i++);
+ RCC->CTRLSTS |= (((uint32_t)MSI_CLK) << 4);
+ /*Delay for while*/
+ for(i=0;i<0x30;i++);
+ /* Enable MSI */
+ RCC->CTRLSTS |= ((uint32_t)RCC_CTRLSTS_MSIEN);
+
+ /* Wait till MSI is ready and if Time out is reached exit */
+ do
+ {
+ MSIStatus = RCC->CTRLSTS & RCC_CTRLSTS_MSIRD;
+ StartUpCounter++;
+ } while ((MSIStatus == 0) && (StartUpCounter != MSI_STARTUP_TIMEOUT));
+
+ MSIStatus = ((RCC->CTRLSTS & RCC_CTRLSTS_MSIRD) != RESET);
+ if (!MSIStatus)
+ {
+ /* If MSI fails to start-up, the application will have wrong clock
+ * configuration. User can add here some code to deal with this error */
+ SystemCoreClock = MSI_VALUE_L6;
+ return;
+ }
+
+#elif ((SYSCLK_SRC == SYSCLK_USE_HSI) || (SYSCLK_SRC == SYSCLK_USE_HSI_PLL))
+
+ bool HSIStatus = 0;
+ /* Enable HSI */
+ RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
+
+ /* Wait till HSI is ready and if Time out is reached exit */
+ do
+ {
+ HSIStatus = RCC->CTRL & RCC_CTRL_HSIRDF;
+ StartUpCounter++;
+ } while ((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));
+
+ HSIStatus = ((RCC->CTRL & RCC_CTRL_HSIRDF) != RESET);
+ if (!HSIStatus)
+ {
+ /* If HSI fails to start-up, the application will have wrong clock
+ * configuration. User can add here some code to deal with this error */
+ SystemCoreClock = MSI_VALUE_L6;
+ return;
+ }
+
+#elif ((SYSCLK_SRC == SYSCLK_USE_HSE) || (SYSCLK_SRC == SYSCLK_USE_HSE_PLL))
+
+ bool HSEStatus = 0;
+ /* Enable HSE */
+ RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CTRL & RCC_CTRL_HSERDF;
+ StartUpCounter++;
+ } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ HSEStatus = ((RCC->CTRL & RCC_CTRL_HSERDF) != RESET);
+ if (!HSEStatus)
+ {
+ /* If HSE fails to start-up, the application will have wrong clock
+ * configuration. User can add here some code to deal with this error */
+ SystemCoreClock = MSI_VALUE_L6;
+ return;
+ }
+#endif
+
+ /* If the system clock is greater than 64MHz, the voltage range of the main voltage regulator
+ must be configured as 1.1V */
+ if (SYSCLK_FREQ >= 64000000)
+ {
+ /* Enables PWR peripheral clock */
+ RCC->APB1PCLKEN |= RCC_APB1_PERIPH_PWR;
+ /* Check PWR->CTRL1.MRSEL configuration */
+ if ((PWR->CTRL1 & ((uint32_t)PWR_CTRL1_MRSEL)) == ((uint32_t)PWR_CTRL1_MRSEL2))
+ {
+ /* Config 1.1V */
+ PWR->CTRL1 |= PWR_CTRL1_MRSEL1;
+ }
+ }
+
+ /* Flash wait state
+ 0: HCLK <= 32M
+ 1: HCLK <= 64M
+ 2: HCLK <= 96M
+ 3: HCLK <= 128M
+ */
+ FLASH->AC &= (uint32_t)((uint32_t)~FLASH_AC_LATENCY);
+ FLASH->AC |= (uint32_t)((SYSCLK_FREQ - 1) / 32000000);
+
+ /* HCLK = SYSCLK */
+ RCC->CFG |= (uint32_t)RCC_CFG_AHBPRES_DIV1;
+
+ /* PCLK2 max 54M */
+ if (SYSCLK_FREQ > 54000000)
+ {
+ RCC->CFG |= (uint32_t)RCC_CFG_APB2PRES_DIV2;
+ }
+ else
+ {
+ RCC->CFG |= (uint32_t)RCC_CFG_APB2PRES_DIV1;
+ }
+
+ /* PCLK1 max 27M */
+ if (SYSCLK_FREQ > 54000000)
+ {
+ RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV4;
+ }
+ else if (SYSCLK_FREQ > 27000000)
+ {
+ RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV2;
+ }
+ else
+ {
+ RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV1;
+ }
+
+#if SYSCLK_SRC == SYSCLK_USE_MSI
+ /* Select MSI as system clock source */
+ RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW));
+ RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_MSI;
+
+ /* Wait till MSI is used as system clock source */
+ while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x00)
+ {
+ }
+#elif SYSCLK_SRC == SYSCLK_USE_HSI
+ /* Select HSI as system clock source */
+ RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW));
+ RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_HSI;
+
+ /* Wait till HSI is used as system clock source */
+ while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x04)
+ {
+ }
+#elif SYSCLK_SRC == SYSCLK_USE_HSE
+ /* Select HSE as system clock source */
+ RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW));
+ RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_HSE;
+
+ /* Wait till HSE is used as system clock source */
+ while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x08)
+ {
+ }
+#elif SYSCLK_SRC == SYSCLK_USE_HSI_PLL || SYSCLK_SRC == SYSCLK_USE_HSE_PLL
+
+ /* clear bits */
+ RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_PLLSRC | RCC_CFG_PLLHSEPRES | RCC_CFG_PLLMULFCT));
+ RCC->PLLHSIPRE &= (uint32_t)((uint32_t) ~(RCC_PLLHSIPRE_PLLHSIPRE | RCC_PLLHSIPRE_PLLSRCDIV));
+
+ /* set PLL source */
+ rcc_cfg = RCC->CFG;
+ rcc_cfg |= (SYSCLK_SRC == SYSCLK_USE_HSI_PLL ? RCC_CFG_PLLSRC_HSI : RCC_CFG_PLLSRC_HSE);
+ /* PLL DIV */
+ rcc_pllhsipre = RCC->PLLHSIPRE;
+
+ #if SYSCLK_SRC == SYSCLK_USE_HSI_PLL
+ rcc_pllhsipre |= (PLLSRC_DIV == 1 ? RCC_PLLHSIPRE_PLLHSIPRE_HSI : RCC_PLLHSIPRE_PLLHSIPRE_HSI_DIV2);
+ #elif SYSCLK_SRC == SYSCLK_USE_HSE_PLL
+ rcc_cfg |= (PLLSRC_DIV == 1 ? RCC_CFG_PLLHSEPRES_HSE : RCC_CFG_PLLHSEPRES_HSE_DIV2);
+ #endif
+
+ /* set PLL DIV */
+ rcc_pllhsipre |= (PLL_DIV == PLL_DIV2_DISABLE ? RCC_PLLHSIPRE_PLLSRCDIV_DISABLE : RCC_PLLHSIPRE_PLLSRCDIV_ENABLE);
+
+ /* set PLL multiply factor */
+ #if PLL_MUL <= 16
+ rcc_cfg |= (PLL_MUL - 2) << 18;
+ #else
+ rcc_cfg |= ((PLL_MUL - 17) << 18) | (1 << 27);
+ #endif
+
+ RCC->CFG = rcc_cfg;
+ RCC->PLLHSIPRE = rcc_pllhsipre;
+
+ /* Enable PLL */
+ RCC->CTRL |= RCC_CTRL_PLLEN;
+
+ /* Wait till PLL is ready */
+ while ((RCC->CTRL & RCC_CTRL_PLLRDF) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW));
+ RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x0C)
+ {
+ }
+#endif
+}
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/system_n32g43x.h b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/system_n32g43x.h
new file mode 100644
index 0000000000..88ae5f8226
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/system_n32g43x.h
@@ -0,0 +1,59 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file system_n32g43x.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __SYSTEM_N32G43X_H__
+#define __SYSTEM_N32G43X_H__
+
+#include
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup N32G43X_System
+ * @{
+ */
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_N32G43X_H__ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/SConscript b/bsp/n32/libraries/N32G43x_Firmware_Library/SConscript
new file mode 100644
index 0000000000..24ba3e9f43
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/SConscript
@@ -0,0 +1,63 @@
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+
+src = Split('''
+CMSIS/device/system_n32g43x.c
+n32g43x_std_periph_driver/src/n32g43x_gpio.c
+n32g43x_std_periph_driver/src/n32g43x_rcc.c
+n32g43x_std_periph_driver/src/n32g43x_exti.c
+n32g43x_std_periph_driver/src/misc.c
+''')
+
+if GetDepend(['RT_USING_SERIAL']):
+ src += ['n32g43x_std_periph_driver/src/n32g43x_usart.c']
+
+if GetDepend(['RT_USING_I2C']):
+ src += ['n32g43x_std_periph_driver/src/n32g43x_i2c.c']
+
+if GetDepend(['RT_USING_SPI']):
+ src += ['n32g43x_std_periph_driver/src/n32g43x_spi.c']
+
+if GetDepend(['RT_USING_CAN']):
+ src += ['n32g43x_std_periph_driver/src/n32g43x_can.c']
+
+if GetDepend(['RT_USING_ADC']):
+ src += ['n32g43x_std_periph_driver/src/n32g43x_adc.c']
+
+if GetDepend(['RT_USING_DAC']):
+ src += ['n32g43x_std_periph_driver/src/n32g43x_dac.c']
+
+if GetDepend(['RT_USING_HWTIMER']):
+ src += ['n32g43x_std_periph_driver/src/n32g43x_tim.c']
+
+if GetDepend(['RT_USING_RTC']):
+ src += ['n32g43x_std_periph_driver/src/n32g43x_rtc.c']
+ src += ['n32g43x_std_periph_driver/src/n32g43x_pwr.c']
+ src += ['n32g43x_std_periph_driver/src/n32g43x_flash.c']
+
+if GetDepend(['RT_USING_WDT']):
+ src += ['n32g43x_std_periph_driver/src/n32g43x_iwdg.c']
+ src += ['n32g43x_std_periph_driver/src/n32g43x_wwdg.c']
+
+if GetDepend(['RT_USING_BSP_USB']):
+ path += [cwd + '/n32g43x_usbfs_driver/inc']
+ src += [cwd + '/n32g43x_usbfs_driver/src']
+
+path = [
+ cwd + '/CMSIS/device',
+ cwd + '/CMSIS/core',
+ cwd + '/n32g43x_std_periph_driver/inc',]
+
+CPPDEFINES = ['USE_STDPERIPH_DRIVER']
+
+
+
+group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_aes.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_aes.h
new file mode 100644
index 0000000000..0b7044eeb6
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_aes.h
@@ -0,0 +1,119 @@
+/*****************************************************************************
+* NationS Microcontroller Software Support
+* ----------------------------------------------------------------------------
+* Copyright (c) 2020, NationS Corporation
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* - Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the disclaimer below.
+*
+* NationS's name may not be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ****************************************************************************/
+/*****************************************************************************
+* File Name: n32g43x_aes.h
+* Function: Declaring AES algorithm library API
+* version: V1.2.0
+* Author: zhang.zhenshan
+* date: 2020-4-8
+* ****************************************************************************/
+
+#ifndef __N32G43X_AES_H__
+#define __N32G43X_AES_H__
+
+#include
+
+#define AES_ECB (0x11111111)
+#define AES_CBC (0x22222222)
+#define AES_CTR (0x33333333)
+
+#define AES_ENC (0x44444444)
+#define AES_DEC (0x55555555)
+
+enum
+{
+ AES_Crypto_OK = 0x0, //AES opreation success
+ AES_Init_OK = 0x0, //AES Init opreation success
+ AES_Crypto_ModeError = 0x5a5a5a5a, //Working mode error(Neither ECB nor CBC nor CTR)
+ AES_Crypto_EnOrDeError, //En&De error(Neither encryption nor decryption)
+ AES_Crypto_ParaNull, // the part of input(output/iv) Null
+ AES_Crypto_LengthError, // if Working mode is ECB or CBC,the length of input message must be 4 times and cannot be zero;
+ //if Working mode is CTR,the length of input message cannot be zero; othets: return AES_Crypto_LengthError
+
+ AES_Crypto_KeyLengthError, //the keyWordLen must be 4 or 6 or 8; othets:return AES_Crypto_KeyLengthError
+ AES_Crypto_UnInitError, //AES uninitialized
+};
+
+typedef struct
+{
+ uint32_t *in; // the part of input to be encrypted or decrypted
+ uint32_t *iv; // the part of initial vector
+ uint32_t *out; // the part of out
+ uint32_t *key; // the part of key
+ uint32_t keyWordLen; // the length(by word) of key
+ uint32_t inWordLen; // the length(by word) of plaintext or cipher
+ uint32_t En_De; // 0x44444444- encrypt, 0x55555555 - decrypt
+ uint32_t Mode; // 0x11111111 - ECB, 0x22222222 - CBC, 0x33333333 - CTR
+}AES_PARM;
+
+ /**
+ * @brief AES_Init
+ * @return AES_Init_OK, AES Init success; othets: AES Init fail
+ * @note
+ */
+
+uint32_t AES_Init(AES_PARM *parm);
+
+/**
+ * @brief AES crypto
+ * @param[in] parm pointer to AES context and the detail please refer to struct AES_PARM in AES.h
+ * @return AES_Crypto_OK, AES crypto success; othets: AES crypto fail(reference to the definition by enum variation)
+ * @note 1.Please refer to the demo in user guidance before using this function
+ * 2.Input and output can be the same buffer
+ * 3. IV can be NULL when ECB mode
+ * 4. If Working mode is ECB or CBC,the length of input message must be 4 times and cannot be zero;
+ * if Working mode is CTR,the length of input message cannot be zero;
+ * 5. If the input is in byte, make sure align by word.
+ */
+uint32_t AES_Crypto(AES_PARM *parm);
+
+/**
+ * @brief AES close
+ * @return none
+ * @note if you want to close AES algorithm, this function can be recalled.
+ */
+void AES_Close(void);
+
+/**
+ * @brief Get AES lib version
+ * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
+ * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
+ * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
+ * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
+ * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
+ * @return none
+ * @1.You can recall this function to get AES lib information
+ */
+void AES_Version(uint8_t *type, uint8_t *customer, uint8_t date[3], uint8_t *version);
+
+
+
+
+#endif
+
+
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_algo_common.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_algo_common.h
new file mode 100644
index 0000000000..ef04302522
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_algo_common.h
@@ -0,0 +1,154 @@
+/*****************************************************************************
+* NationS Microcontroller Software Support
+* ----------------------------------------------------------------------------
+* Copyright (c) 2020, NationS Corporation
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* - Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the disclaimer below.
+*
+* NationS's name may not be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+* DISCLAIMED. IN NO EVENT SHALL NATIONZ BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ****************************************************************************/
+/*****************************************************************************
+* File Name: Common.h
+* Function: Defining the public functions used by other algorithm lib
+* version: V1.2.0
+* Author: huang.jinshang
+* date: 2020-01-06
+* ****************************************************************************/
+
+#ifndef _N32G43X_ALGO_COMMON_H_
+#define _N32G43X_ALGO_COMMON_H_
+
+#include
+
+
+enum{
+ Cpy_OK=0,//copy success
+ SetZero_OK = 0,//set zero success
+ XOR_OK = 0, //XOR success
+ Reverse_OK = 0, //Reverse success
+ Cmp_EQUAL = 0, //Two big number are equal
+ Cmp_UNEQUAL = 1, //Two big number are not equal
+
+};
+
+/**
+ * @brief disturb the sequence order
+ * @param[in] order pointer to the sequence to be disturbed
+ * @param[in] rand pointer to random number
+ * @param[in] the length of order
+ * @return RandomSort_OK: disturb order success; Others: disturb order fail;
+ * @note
+ */
+uint32_t RandomSort(uint8_t *order, const uint8_t *rand, uint32_t len);
+
+/**
+ * @brief Copy data by byte
+ * @param[in] dst pointer to destination data
+ * @param[in] src pointer to source data
+ * @param[in] byte length
+ * @return Cpy_OK: success; others: fail.
+ * @note 1. dst and src cannot be same
+ */
+uint32_t Cpy_U8( uint8_t *dst, uint8_t *src, uint32_t byteLen);
+
+/**
+ * @brief Copy data by word
+ * @param[in] dst pointer to destination data
+ * @param[in] src pointer to source data
+ * @param[in] word length
+ * @return Cpy_OK: success; others: fail.
+ * @note 1. dst and src must be aligned by word
+ */
+uint32_t Cpy_U32( uint32_t *dst, const uint32_t *src, uint32_t wordLen);
+
+ /**
+ * @brief XOR
+ * @param[in] a pointer to one data to be XORed
+ * @param[in] b pointer to another data to be XORed
+ * @param[in] the length of order
+ * @return XOR_OK: operation success; Others: operation fail;
+ * @note
+ */
+uint32_t XOR_U8(uint8_t *a, uint8_t *b, uint8_t *c, uint32_t byteLen);
+
+ /**
+ * @brief XORed two u32 arrays
+ * @param[in] a pointer to one data to be XORed
+ * @param[in] b pointer to another data to be XORed
+ * @param[in] the length of order
+ * @return XOR_OK: operation success; Others: operation fail;
+ * @note
+ */
+uint32_t XOR_U32(uint32_t *a,uint32_t *b,uint32_t *c,uint32_t wordLen);
+
+/**
+ * @brief set zero by byte
+ * @param[in] dst pointer to the address to be set zero
+ * @param[in] byte length
+ * @return SetZero_OK: success; others: fail.
+ * @note
+ */
+uint32_t SetZero_U8(uint8_t *dst, uint32_t byteLen);
+
+/**
+ * @brief set zero by word
+ * @param[in] dst pointer to the address to be set zero
+ * @param[in] word length
+ * @return SetZero_OK: success; others: fail.
+ * @note
+ */
+uint32_t SetZero_U32(uint32_t *dst, uint32_t wordLen);
+
+/**
+ * @brief reverse byte order of every word, the words stay the same
+ * @param[in] dst pointer to the destination address
+ * @param[in] src pointer to the source address
+ * @param[in] word length
+ * @return Reverse_OK: success; others: fail.
+ * @note 1.dst and src can be same
+ */
+uint32_t ReverseBytesInWord_U32(uint32_t *dst, const uint32_t *src, uint32_t wordLen);
+
+/**
+ * @brief compare two big number
+ * @param[in] a pointer to one big number
+ * @param[in] word length of a
+ * @param[in] b pointer to another big number
+ * @param[in] word length of b
+ * @return Cmp_UNEQUAL:a!=b;Cmp_EQUAL: a==b.
+ *
+ */
+int32_t Cmp_U32(const uint32_t *a, uint32_t aWordLen, const uint32_t *b, uint32_t bWordLen);
+
+/**
+ * @brief compare two big number
+ * @param[in] a pointer to one big number
+ * @param[in] word length of a
+ * @param[in] b pointer to another big number
+ * @param[in] word length of b
+ * @return Cmp_UNEQUAL:a!=b;Cmp_EQUAL: a==b.
+ *
+ */
+int32_t Cmp_U8(const uint8_t *a, uint32_t aByteLen, const uint8_t *b, uint32_t bByteLen);
+
+
+#endif
+
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_des.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_des.h
new file mode 100644
index 0000000000..b71b0fa06a
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_des.h
@@ -0,0 +1,115 @@
+/*****************************************************************************
+* Nations Microcontroller Software Support
+* ----------------------------------------------------------------------------
+* Copyright (c) 2020, Nations Corporation
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* - Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the disclaimer below.
+*
+* Nations's name may not be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY Nations "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+* DISCLAIMED. IN NO EVENT SHALL Nations BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ****************************************************************************/
+/*****************************************************************************
+* File Name: Dn32g43x_des.h
+* Function: Declaring DES algorithm library API
+* version: V1.2.0
+* Author: zhang.zhenshan
+* date: 2020-4-8
+* ****************************************************************************/
+
+
+#ifndef _N32G43X_DES_H_
+#define _N32G43X_DES_H_
+
+#include
+
+#define DES_ECB (0x11111111)
+#define DES_CBC (0x22222222)
+
+
+#define DES_ENC (0x33333333)
+#define DES_DEC (0x44444444)
+
+#define DES_KEY (0x55555555)
+#define TDES_2KEY (0x66666666)
+#define TDES_3KEY (0x77777777)
+
+enum DES
+{
+ DES_Crypto_OK = 0x0, //DES/TDES opreation success
+ DES_Init_OK = 0x0, //DES/TDES Init opreation success
+ DES_Crypto_ModeError = 0x5a5a5a5a, //Working mode error(Neither ECB nor CBC)
+ DES_Crypto_EnOrDeError, //En&De error(Neither encryption nor decryption)
+ DES_Crypto_ParaNull, // the part of input(output/iv) Null
+ DES_Crypto_LengthError, //the length of input message must be 2 times and cannot be zero
+ DES_Crypto_KeyError, //keyMode error(Neither DES_KEY nor TDES_2KEY nor TDES_3KEY)
+ DES_Crypto_UnInitError, //DES/TDES uninitialized
+};
+
+typedef struct
+{
+ uint32_t *in; // the part of input to be encrypted or decrypted
+ uint32_t *iv; // the part of initial vector
+ uint32_t *out; // the part of out
+ uint32_t *key; // the part of key
+ uint32_t inWordLen; // the length(by word) of plaintext or cipher
+ uint32_t En_De; // 0x33333333- encrypt, 0x44444444 - decrypt
+ uint32_t Mode; // 0x11111111 - ECB, 0x22222222 - CBC
+ uint32_t keyMode; //TDES key mode: 0x55555555-key,0x66666666-2key, 0x77777777-3key
+}DES_PARM;
+
+ /**
+ * @brief DES_Init
+ * @return DES_Init_OK, DES/TDES Init success; othets: DES/TDES Init fail
+ * @note
+ */
+uint32_t DES_Init(DES_PARM *parm);
+
+/**
+ * @brief DES crypto
+ * @param[in] parm pointer to DES/TDES context and the detail please refer to struct DES_PARM in DES.h
+ * @return DES_Crypto_OK, DES/TDES crypto success; othets: DES/TDES crypto fail(reference to the definition by enum variation)
+ * @note 1.Please refer to the demo in user guidance before using this function
+ * 2.Input and output can be the same buffer
+ * 3. IV can be NULL when ECB mode
+ * 4. The word lengrh of message must be as times as 2.
+ * 5. If the input is in byte, make sure align by word.
+ */
+uint32_t DES_Crypto(DES_PARM *parm);
+
+/**
+ * @brief DES close
+ * @return none
+ * @note if you want to close DES algorithm, this function can be recalled.
+ */
+void DES_Close(void);
+
+/**
+ * @brief Get DES/TDES lib version
+ * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
+ * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
+ * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
+ * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
+ * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
+ * @return none
+ * @1.You can recall this function to get DES/TDES lib information
+ */
+void DES_Version(uint8_t *type, uint8_t *customer, uint8_t date[3], uint8_t *version);
+
+#endif
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_hash.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_hash.h
new file mode 100644
index 0000000000..0124539250
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_hash.h
@@ -0,0 +1,213 @@
+/*****************************************************************************
+* Nationz Microcontroller Software Support
+* ----------------------------------------------------------------------------
+* Copyright (c) 2020, Nationz Corporation
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* - Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the disclaimer below.
+*
+* Nationz's name may not be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+* DISCLAIMED. IN NO EVENT SHALL NATIONZ BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ****************************************************************************/
+/*****************************************************************************
+* File Name: HASH.h
+* Function: Declaring HASH algorithm library API
+* version: V1.2.0
+* Author: zhang.zhenshan
+* date: 2020-4-8
+* ****************************************************************************/
+
+#ifndef _N32G43X_HASH_H_
+#define _N32G43X_HASH_H_
+
+#include
+
+#define ALG_SHA1 (uint16_t)(0x0004)
+#define ALG_SHA224 (uint16_t)(0x000A)
+#define ALG_SHA256 (uint16_t)(0x000B)
+//#define ALG_MD5 (u16)(0x000C)
+#define ALG_SM3 (uint16_t)(0x0012)
+
+enum
+{
+ HASH_SEQUENCE_TRUE = 0x0105A5A5,//save IV
+ HASH_SEQUENCE_FALSE = 0x010A5A5A, //not save IV
+ HASH_Init_OK = 0,//hash init success
+ HASH_Start_OK = 0,//hash update success
+ HASH_Update_OK = 0,//hash update success
+ HASH_Complete_OK = 0,//hash complete success
+ HASH_Close_OK = 0,//hash close success
+ HASH_ByteLenPlus_OK = 0,//byte length plus success
+ HASH_PadMsg_OK = 0,//message padding success
+ HASH_ProcMsgBuf_OK = 0, //message processing success
+ SHA1_Hash_OK = 0,//sha1 operation success
+ SM3_Hash_OK = 0,//sm3 operation success
+ SHA224_Hash_OK = 0,//sha224 operation success
+ SHA256_Hash_OK = 0,//sha256 operation success
+ //MD5_Hash_OK = 0,//MD5 operation success
+
+ HASH_Init_ERROR = 0x01044400,//hash init error
+ HASH_Start_ERROR, //hash start error
+ HASH_Update_ERROR, //hash update error
+ HASH_ByteLenPlus_ERROR,//hash byte plus error
+};
+
+struct _HASH_CTX_;
+
+typedef struct
+{
+ const uint16_t HashAlgID;//choice hash algorithm
+ const uint32_t * const K, KLen;//K and word length of K
+ const uint32_t * const IV, IVLen;//IV and word length of IV
+ const uint32_t HASH_SACCR, HASH_HASHCTRL;//relate registers
+ const uint32_t BlockByteLen, BlockWordLen; //byte length of block, word length of block
+ const uint32_t DigestByteLen, DigestWordLen; //byte length of digest,word length of digest
+ const uint32_t Cycle; //interation times
+ uint32_t (* const ByteLenPlus)(uint32_t *, uint32_t); //function pointer
+ uint32_t (* const PadMsg)(struct _HASH_CTX_ *); //function pointer
+}HASH_ALG;
+
+
+typedef struct _HASH_CTX_
+{
+ const HASH_ALG *hashAlg;//pointer to HASH_ALG
+ uint32_t sequence; // TRUE if the IV should be saved
+ uint32_t IV[16];
+ uint32_t msgByteLen[4];
+ uint8_t msgBuf[128+4];
+ uint32_t msgIdx;
+}HASH_CTX;
+
+extern const HASH_ALG HASH_ALG_SHA1[1];
+extern const HASH_ALG HASH_ALG_SHA224[1];
+extern const HASH_ALG HASH_ALG_SHA256[1];
+//extern const HASH_ALG HASH_ALG_MD5[1];
+extern const HASH_ALG HASH_ALG_SM3[1];
+
+/**
+ * @brief Hash init
+ * @param[in] ctx pointer to HASH_CTX struct
+ * @return HASH_Init_OK, Hash init success; othets: Hash init fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ */
+uint32_t HASH_Init(HASH_CTX *ctx);
+
+/**
+ * @brief Hash start
+ * @param[in] ctx pointer to HASH_CTX struct
+ * @return HASH_Start_OK, Hash start success; othets: Hash start fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ * 2.HASH_Init() should be recalled before use this function
+ */
+uint32_t HASH_Start(HASH_CTX *ctx);
+
+/**
+ * @brief Hash update
+ * @param[in] ctx pointer to HASH_CTX struct
+ * @param[in] in pointer to message
+ * @param[out] out pointer tohash result,digest
+ * @return HASH_Update_OK, Hash update success; othets: Hash update fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ * 2.HASH_Init() and HASH_Start() should be recalled before use this function
+ */
+uint32_t HASH_Update(HASH_CTX *ctx, uint8_t *in, uint32_t byteLen);
+
+/**
+ * @brief Hash complete
+ * @param[in] ctx pointer to HASH_CTX struct
+ * @param[out] out pointer tohash result,digest
+ * @return HASH_Complete_OK, Hash complete success; othets: Hash complete fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ * 2.HASH_Init(), HASH_Start() and HASH_Update() should be recalled before use this function
+ */
+uint32_t HASH_Complete(HASH_CTX *ctx, uint8_t *out);
+
+/**
+ * @brief Hash close
+ * @return HASH_Close_OK, Hash close success; othets: Hash close fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ */
+uint32_t HASH_Close(void);
+
+/**
+ * @brief SM3 Hash for 256bits digest
+ * @param[in] in pointer to message
+ * @param[in] byte length of in
+ * @param[out] out pointer tohash result,digest
+ * @return SM3_Hash_OK, SM3 hash success; othets: SM3 hash fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ */
+uint32_t SM3_Hash(uint8_t *in,uint32_t byteLen, uint8_t* out);
+
+
+/**
+ * @brief SHA1 Hash
+ * @param[in] in pointer to message
+ * @param[in] byte length of in
+ * @param[out] out pointer tohash result,digest
+ * @return SHA1_Hash_OK, SHA1 hash success; othets: SHA1 hash fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ */
+uint32_t SHA1_Hash(uint8_t*in, uint32_t byteLen, uint8_t*out);
+
+/**
+ * @brief SHA224 Hash
+ * @param[in] in pointer to message
+ * @param[in] byte length of in
+ * @param[out] out pointer tohash result,digest
+ * @return SHA224_Hash_OK, SHA224 hash success; othets: SHA224 hash fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ */
+uint32_t SHA224_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
+
+
+/**
+ * @brief SHA256 Hash
+ * @param[in] in pointer to message
+ * @param[in] byte length of in
+ * @param[out] out pointer tohash result,digest
+ * @return SHA256_Hash_OK, SHA256 hash success; othets: SHA256 hash fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ */
+uint32_t SHA256_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
+
+/**
+ * @brief MD5 Hash
+ * @param[in] in pointer to message
+ * @param[in] byte length of in
+ * @param[in] out pointer tohash result,digest
+ * @return MD5_Hash_OK, MD5 hash success; othets: MD5 hash fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ */
+//u32 MD5_Hash(u8* in,u32 byteLen, u8* out);
+
+/**
+ * @brief Get HASH lib version
+ * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
+ * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
+ * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
+ * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
+ * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
+ * @return none
+ * @1.You can recall this function to get RSA lib information
+ */
+void HASH_Version(uint8_t*type, uint8_t*customer, uint8_t date[3], uint8_t *version);
+
+
+#endif
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_rng.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_rng.h
new file mode 100644
index 0000000000..00dbf6574c
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_rng.h
@@ -0,0 +1,83 @@
+/*****************************************************************************
+* NationS Microcontroller Software Support
+* ----------------------------------------------------------------------------
+* Copyright (c) 2020, NationS Corporation
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* - Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the disclaimer below.
+*
+* NationS's name may not be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+* DISCLAIMED. IN NO EVENT SHALL NATIONZ BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ****************************************************************************/
+/*****************************************************************************
+* File Name: n32g43x_rng.h
+* Function: Declaring RNG algorithm library API
+* version: V1.2.0
+* Author: zhang.zhenshan
+* date: 2020-4-8
+* ****************************************************************************/
+
+#ifndef _N32G43X_RNG_H_
+#define _N32G43X_RNG_H_
+
+#include
+
+enum{
+ RNG_OK = 0x5a5a5a5a,
+ LENError = 0x311ECF50, //RNG generation of key length error
+ ADDRNULL = 0x7A9DB86C, // This address is empty
+};
+
+
+//u32 RNG_init(void);
+/**
+ * @brief Get pseudo random number
+ * @param[out] rand pointer to random number
+ * @param[in] the wordlen of random number
+ * @param[in] the seed, can be NULL
+ * @return RNG_OK:get random number success; othets: get random number fail
+ * @note
+ */
+uint32_t GetPseudoRand_U32(uint32_t *rand, uint32_t wordLen,uint32_t seed[2]);
+
+
+/**
+ * @brief Get true random number
+ * @param[out] rand pointer to random number
+ * @param[in] the wordlen of random number
+ * @return RNG_OK:get random number success; othets: get random number fail
+ * @note
+ */
+uint32_t GetTrueRand_U32(uint32_t *rand, uint32_t wordLen);
+
+/**
+ * @brief Get RNG lib version
+ * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
+ * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
+ * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
+ * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
+ * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
+ * @return none
+ * @1.You can recall this function to get RSA lib information
+ */
+void RNG_Version(uint8_t *type, uint8_t *customer, uint8_t date[3], uint8_t *version);
+
+#endif
+
+
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/misc.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/misc.h
new file mode 100644
index 0000000000..bb7ec2abe7
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/misc.h
@@ -0,0 +1,228 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file misc.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __MISC_H__
+#define __MISC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup MISC
+ * @{
+ */
+
+/** @addtogroup MISC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief NVIC Init Structure definition
+ */
+
+typedef struct
+{
+ uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
+ This parameter can be a value of @ref IRQn_Type
+ (For the complete N32G43x Devices IRQ Channels list, please
+ refer to n32g43x.h file) */
+
+ uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
+ specified in NVIC_IRQChannel. This parameter can be a value
+ between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+ uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
+ in NVIC_IRQChannel. This parameter can be a value
+ between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+ FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
+ will be enabled or disabled.
+ This parameter can be set either to ENABLE or DISABLE */
+} NVIC_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup NVIC_Priority_Table
+ * @{
+ */
+
+/**
+@code
+ The table below gives the allowed values of the pre-emption priority and subpriority according
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
+ ============================================================================================================================
+ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
+ ============================================================================================================================
+ NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption
+priority | | | 4 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption
+priority | | | 3 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption
+priority | | | 2 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption
+priority | | | 1 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption
+priority | | | 0 bits for subpriority
+ ============================================================================================================================
+@endcode
+*/
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup Vector_Table_Base
+ * @{
+ */
+
+#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
+#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || ((VECTTAB) == NVIC_VectTab_FLASH))
+/**
+ * @}
+ */
+
+/** @addtogroup System_Low_Power
+ * @{
+ */
+
+#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || ((LP) == NVIC_LP_SLEEPDEEP) || ((LP) == NVIC_LP_SLEEPONEXIT))
+/**
+ * @}
+ */
+
+/** @addtogroup Preemption_Priority_Group
+ * @{
+ */
+
+#define NVIC_PriorityGroup_0 \
+ ((uint32_t)0x700) /*!< 0 bits for pre-emption priority \
+ 4 bits for subpriority */
+#define NVIC_PriorityGroup_1 \
+ ((uint32_t)0x600) /*!< 1 bits for pre-emption priority \
+ 3 bits for subpriority */
+#define NVIC_PriorityGroup_2 \
+ ((uint32_t)0x500) /*!< 2 bits for pre-emption priority \
+ 2 bits for subpriority */
+#define NVIC_PriorityGroup_3 \
+ ((uint32_t)0x400) /*!< 3 bits for pre-emption priority \
+ 1 bits for subpriority */
+#define NVIC_PriorityGroup_4 \
+ ((uint32_t)0x300) /*!< 4 bits for pre-emption priority \
+ 0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP) \
+ (((GROUP) == NVIC_PriorityGroup_0) || ((GROUP) == NVIC_PriorityGroup_1) || ((GROUP) == NVIC_PriorityGroup_2) \
+ || ((GROUP) == NVIC_PriorityGroup_3) || ((GROUP) == NVIC_PriorityGroup_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup SysTick_clock_source
+ * @{
+ */
+
+#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) \
+ (((SOURCE) == SysTick_CLKSource_HCLK) || ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Exported_Functions
+ * @{
+ */
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitType* NVIC_InitStruct);
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState Cmd);
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MISC_H__ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_adc.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_adc.h
new file mode 100644
index 0000000000..43f9dcdafe
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_adc.h
@@ -0,0 +1,545 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_adc.h
+ * @author Nations
+ * @version V1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43x_ADC_H__
+#define __N32G43x_ADC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+#include
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+#define VREF1P2_CTRL (*(uint32_t*)(0x40001800+0x24))
+#define _EnVref1p2() do{VREF1P2_CTRL|=(0x1<<13);}while (0);
+#define _DisVref1p2() do{VREF1P2_CTRL&=~(0x1<<13);}while (0);
+
+#define VREF2P0_CTRL (*(uint32_t*)(0x40001800+0x24))
+#define _EnVref2p0() do{VREF2P0_CTRL|=(0x1<<20);}while (0);
+#define _DisVref2p0() do{VREF2P0_CTRL&=~(0x1<<20);}while (0);
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/** @addtogroup ADC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief ADC Init structure definition
+ */
+typedef struct
+{
+
+ FunctionalState MultiChEn; /*!< Specifies whether the conversion is performed in
+ Scan (multichannels) or Single (one channel) mode.
+ This parameter can be set to ENABLE or DISABLE */
+
+ FunctionalState ContinueConvEn; /*!< Specifies whether the conversion is performed in
+ Continuous or Single mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t ExtTrigSelect; /*!< Defines the external trigger used to start the analog
+ to digital conversion of regular channels. This parameter
+ can be a value of @ref
+ ADC_external_trigger_sources_for_regular_channels_conversion */
+
+ uint32_t DatAlign; /*!< Specifies whether the ADC data alignment is left or right.
+ This parameter can be a value of @ref ADC_data_align */
+
+ uint8_t ChsNumber; /*!< Specifies the number of ADC channels that will be converted
+ using the sequencer for regular channel group.
+ This parameter must range from 1 to 16. */
+} ADC_InitType;
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Exported_Constants
+ * @{
+ */
+
+#define IsAdcModule(PERIPH) (((PERIPH) == ADC))
+
+#define IsAdcDmaModule(PERIPH) (((PERIPH) == ADC))
+
+
+
+/** @addtogroup ADC_external_trigger_sources_for_regular_channels_conversion
+ * @{
+ */
+
+#define ADC_EXT_TRIGCONV_T1_CC1 ((uint32_t)0x00000000)
+#define ADC_EXT_TRIGCONV_T1_CC2 ((uint32_t)0x00020000)
+#define ADC_EXT_TRIGCONV_T1_CC3 ((uint32_t)0x00040000)
+#define ADC_EXT_TRIGCONV_T2_CC2 ((uint32_t)0x00060000)
+#define ADC_EXT_TRIGCONV_T3_TRGO ((uint32_t)0x00080000)
+#define ADC_EXT_TRIGCONV_T4_CC4 ((uint32_t)0x000A0000)
+#define ADC_EXT_TRIGCONV_EXT_INT11_TIM8_TRGO ((uint32_t)0x000C0000)
+#define ADC_EXT_TRIGCONV_NONE ((uint32_t)0x000E0000)
+
+
+#define IsAdcExtTrig(REGTRIG) \
+ (((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC2) \
+ || ((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC3) || ((REGTRIG) == ADC_EXT_TRIGCONV_T2_CC2) \
+ || ((REGTRIG) == ADC_EXT_TRIGCONV_T3_TRGO) || ((REGTRIG) == ADC_EXT_TRIGCONV_T4_CC4) \
+ || ((REGTRIG) == ADC_EXT_TRIGCONV_EXT_INT11_TIM8_TRGO) || ((REGTRIG) == ADC_EXT_TRIGCONV_NONE))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_data_align
+ * @{
+ */
+
+#define ADC_DAT_ALIGN_R ((uint32_t)0x00000000)
+#define ADC_DAT_ALIGN_L ((uint32_t)0x00000800)
+#define IsAdcDatAlign(ALIGN) (((ALIGN) == ADC_DAT_ALIGN_R) || ((ALIGN) == ADC_DAT_ALIGN_L))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_channels
+ * @{
+ */
+
+#define ADC_CH_0 ((uint8_t)0x00)
+#define ADC_CH_1 ((uint8_t)0x01)
+#define ADC_CH_2 ((uint8_t)0x02)
+#define ADC_CH_3 ((uint8_t)0x03)
+#define ADC_CH_4 ((uint8_t)0x04)
+#define ADC_CH_5 ((uint8_t)0x05)
+#define ADC_CH_6 ((uint8_t)0x06)
+#define ADC_CH_7 ((uint8_t)0x07)
+#define ADC_CH_8 ((uint8_t)0x08)
+#define ADC_CH_9 ((uint8_t)0x09)
+#define ADC_CH_10 ((uint8_t)0x0A)
+#define ADC_CH_11 ((uint8_t)0x0B)
+#define ADC_CH_12 ((uint8_t)0x0C)
+#define ADC_CH_13 ((uint8_t)0x0D)
+#define ADC_CH_14 ((uint8_t)0x0E)
+#define ADC_CH_15 ((uint8_t)0x0F)
+#define ADC_CH_16 ((uint8_t)0x10)
+#define ADC_CH_17 ((uint8_t)0x11)
+#define ADC_CH_18 ((uint8_t)0x12)
+
+#define ADC_CH_VREFINT ((uint8_t)ADC_CH_0)
+#define ADC_CH_TEMP_SENSOR ((uint8_t)ADC_CH_17)
+#define ADC_CH_VREFBUF ((uint8_t)ADC_CH_18)
+
+#define IsAdcChannel(CHANNEL) \
+ (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) \
+ || ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) \
+ || ((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9) || ((CHANNEL) == ADC_CH_10) || ((CHANNEL) == ADC_CH_11) \
+ || ((CHANNEL) == ADC_CH_12) || ((CHANNEL) == ADC_CH_13) || ((CHANNEL) == ADC_CH_14) || ((CHANNEL) == ADC_CH_15) \
+ || ((CHANNEL) == ADC_CH_16) || ((CHANNEL) == ADC_CH_17) || ((CHANNEL) == ADC_CH_18))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_sampling_time
+ * @{
+ */
+
+#define ADC_SAMP_TIME_1CYCLES5 ((uint8_t)0x00)
+#define ADC_SAMP_TIME_7CYCLES5 ((uint8_t)0x01)
+#define ADC_SAMP_TIME_13CYCLES5 ((uint8_t)0x02)
+#define ADC_SAMP_TIME_28CYCLES5 ((uint8_t)0x03)
+#define ADC_SAMP_TIME_41CYCLES5 ((uint8_t)0x04)
+#define ADC_SAMP_TIME_55CYCLES5 ((uint8_t)0x05)
+#define ADC_SAMP_TIME_71CYCLES5 ((uint8_t)0x06)
+#define ADC_SAMP_TIME_239CYCLES5 ((uint8_t)0x07)
+#define IsAdcSampleTime(TIME) \
+ (((TIME) == ADC_SAMP_TIME_1CYCLES5) || ((TIME) == ADC_SAMP_TIME_7CYCLES5) || ((TIME) == ADC_SAMP_TIME_13CYCLES5) \
+ || ((TIME) == ADC_SAMP_TIME_28CYCLES5) || ((TIME) == ADC_SAMP_TIME_41CYCLES5) \
+ || ((TIME) == ADC_SAMP_TIME_55CYCLES5) || ((TIME) == ADC_SAMP_TIME_71CYCLES5) \
+ || ((TIME) == ADC_SAMP_TIME_239CYCLES5))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_external_trigger_sources_for_injected_channels_conversion
+ * @{
+ */
+
+#define ADC_EXT_TRIG_INJ_CONV_T1_TRGO ((uint32_t)0x00000000)
+#define ADC_EXT_TRIG_INJ_CONV_T1_CC4 ((uint32_t)0x00001000)
+#define ADC_EXT_TRIG_INJ_CONV_T2_TRGO ((uint32_t)0x00002000)
+#define ADC_EXT_TRIG_INJ_CONV_T2_CC1 ((uint32_t)0x00003000)
+#define ADC_EXT_TRIG_INJ_CONV_T3_CC4 ((uint32_t)0x00004000)
+#define ADC_EXT_TRIG_INJ_CONV_T4_TRGO ((uint32_t)0x00005000)
+#define ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4 ((uint32_t)0x00006000)
+#define ADC_EXT_TRIG_INJ_CONV_NONE ((uint32_t)0x00007000)
+
+
+#define IsAdcExtInjTrig(INJTRIG) \
+ (((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T1_TRGO) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T1_CC4) \
+ || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T2_TRGO) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T2_CC1) \
+ || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T3_CC4) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T4_TRGO) \
+ || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_NONE))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_injected_channel_selection
+ * @{
+ */
+
+#define ADC_INJ_CH_1 ((uint8_t)0x14)
+#define ADC_INJ_CH_2 ((uint8_t)0x18)
+#define ADC_INJ_CH_3 ((uint8_t)0x1C)
+#define ADC_INJ_CH_4 ((uint8_t)0x20)
+#define IsAdcInjCh(CHANNEL) \
+ (((CHANNEL) == ADC_INJ_CH_1) || ((CHANNEL) == ADC_INJ_CH_2) || ((CHANNEL) == ADC_INJ_CH_3) \
+ || ((CHANNEL) == ADC_INJ_CH_4))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_analog_watchdog_selection
+ * @{
+ */
+
+#define ADC_ANALOG_WTDG_SINGLEREG_ENABLE ((uint32_t)0x00800200)
+#define ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE ((uint32_t)0x00400200)
+#define ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE ((uint32_t)0x00C00200)
+#define ADC_ANALOG_WTDG_ALLREG_ENABLE ((uint32_t)0x00800000)
+#define ADC_ANALOG_WTDG_ALLINJEC_ENABLE ((uint32_t)0x00400000)
+#define ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE ((uint32_t)0x00C00000)
+#define ADC_ANALOG_WTDG_NONE ((uint32_t)0x00000000)
+
+#define IsAdcAnalogWatchdog(WATCHDOG) \
+ (((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEREG_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE) \
+ || ((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLREG_ENABLE) \
+ || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLINJEC_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE) \
+ || ((WATCHDOG) == ADC_ANALOG_WTDG_NONE))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_interrupts_definition
+ * @{
+ */
+
+#define ADC_INT_ENDC ((uint16_t)0x0220)
+#define ADC_INT_AWD ((uint16_t)0x0140)
+#define ADC_INT_JENDC ((uint16_t)0x0480)
+
+#define IsAdcInt(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))
+
+#define IsAdcGetInt(IT) (((IT) == ADC_INT_ENDC) || ((IT) == ADC_INT_AWD) || ((IT) == ADC_INT_JENDC))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_flags_definition
+ * @{
+ */
+
+#define ADC_FLAG_AWDG ((uint8_t)0x01)
+#define ADC_FLAG_ENDC ((uint8_t)0x02)
+#define ADC_FLAG_JENDC ((uint8_t)0x04)
+#define ADC_FLAG_JSTR ((uint8_t)0x08)
+#define ADC_FLAG_STR ((uint8_t)0x10)
+#define ADC_FLAG_EOC_ANY ((uint8_t)0x20)
+#define ADC_FLAG_JEOC_ANY ((uint8_t)0x40)
+#define IsAdcClrFlag(FLAG) ((((FLAG) & (uint8_t)0x80) == 0x00) && ((FLAG) != 0x00))
+#define IsAdcGetFlag(FLAG) \
+ (((FLAG) == ADC_FLAG_AWDG) || ((FLAG) == ADC_FLAG_ENDC) || ((FLAG) == ADC_FLAG_JENDC) || ((FLAG) == ADC_FLAG_JSTR) \
+ || ((FLAG) == ADC_FLAG_STR) || ((FLAG) == ADC_FLAG_EOC_ANY) || ((FLAG) == ADC_FLAG_JEOC_ANY))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_thresholds
+ * @{
+ */
+#define IsAdcValid(THRESHOLD) ((THRESHOLD) <= 0xFFF)
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_injected_offset
+ * @{
+ */
+
+#define IsAdcOffsetValid(OFFSET) ((OFFSET) <= 0xFFF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_injected_length
+ * @{
+ */
+
+#define IsAdcInjLenValid(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_injected_rank
+ * @{
+ */
+
+#define IsAdcInjRankValid(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_regular_length
+ * @{
+ */
+
+#define IsAdcSeqLenValid(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_regular_rank
+ * @{
+ */
+
+#define IsAdcReqRankValid(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_regular_discontinuous_mode_number
+ * @{
+ */
+
+#define IsAdcSeqDiscNumberValid(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
+
+/**
+ * @}
+ */
+
+/************************** fllowing bit seg in ex register **********************/
+/**@addtogroup ADC_channels_ex_style
+ * @{
+ */
+
+
+#define ADC_CH_0 ((uint8_t)0x00)
+#define ADC_CH_1_PA0 ((uint8_t)0x01)
+#define ADC_CH_2_PA1 ((uint8_t)0x02)
+#define ADC_CH_3_PA2 ((uint8_t)0x03)
+#define ADC_CH_4_PA3 ((uint8_t)0x04)
+#define ADC_CH_5_PA4 ((uint8_t)0x05)
+#define ADC_CH_6_PA5 ((uint8_t)0x06)
+#define ADC_CH_7_PA6 ((uint8_t)0x07)
+#define ADC_CH_8_PA7 ((uint8_t)0x08)
+#define ADC_CH_9_PB0 ((uint8_t)0x09)
+#define ADC_CH_10_PB1 ((uint8_t)0x0A)
+#define ADC_CH_11_PC0 ((uint8_t)0x0B)
+#define ADC_CH_12_PC1 ((uint8_t)0x0C)
+#define ADC_CH_13_PC2 ((uint8_t)0x0D)
+#define ADC_CH_14_PC3 ((uint8_t)0x0E)
+#define ADC_CH_15_PC4 ((uint8_t)0x0F)
+#define ADC_CH_16_PC5 ((uint8_t)0x10)
+#define ADC_CH_17 ((uint8_t)0x11)
+#define ADC_CH_18 ((uint8_t)0x12)
+/**
+ * @}
+ */
+
+/**@addtogroup ADC_dif_sel_ch_definition
+ * @{
+ */
+#define aDC_DIFSEL_CHS_MASK ((uint32_t)0x0007FFFF)
+#define ADC_DIFSEL_CHS_0 ((uint32_t)0x00000001)
+#define ADC_DIFSEL_CHS_1 ((uint32_t)0x00000002)
+#define ADC_DIFSEL_CHS_2 ((uint32_t)0x00000004)
+#define ADC_DIFSEL_CHS_3 ((uint32_t)0x00000008)
+#define ADC_DIFSEL_CHS_4 ((uint32_t)0x00000010)
+#define ADC_DIFSEL_CHS_5 ((uint32_t)0x00000020)
+#define ADC_DIFSEL_CHS_6 ((uint32_t)0x00000040)
+#define ADC_DIFSEL_CHS_7 ((uint32_t)0x00000080)
+#define ADC_DIFSEL_CHS_8 ((uint32_t)0x00000100)
+#define ADC_DIFSEL_CHS_9 ((uint32_t)0x00000200)
+#define ADC_DIFSEL_CHS_10 ((uint32_t)0x00000400)
+#define ADC_DIFSEL_CHS_11 ((uint32_t)0x00000800)
+#define ADC_DIFSEL_CHS_12 ((uint32_t)0x00001000)
+#define ADC_DIFSEL_CHS_13 ((uint32_t)0x00002000)
+#define ADC_DIFSEL_CHS_14 ((uint32_t)0x00004000)
+#define ADC_DIFSEL_CHS_15 ((uint32_t)0x00008000)
+#define ADC_DIFSEL_CHS_16 ((uint32_t)0x00010000)
+#define ADC_DIFSEL_CHS_17 ((uint32_t)0x00020000)
+#define ADC_DIFSEL_CHS_18 ((uint32_t)0x00040000)
+/**
+ * @}
+ */
+
+/**@addtogroup ADC_calfact_definition
+ * @{
+ */
+#define ADC_CALFACT_CALFACTD_MSK ((uint32_t)0x3FL << 16)
+#define ADC_CALFACT_CALFACTS_MSK ((uint32_t)0x3FL << 0)
+/**
+ * @}
+ */
+
+/**@addtogroup ADC_ctrl3_definition
+ * @{
+ */
+#define ADC_CTRL3_DPWMOD_MSK ((uint32_t)0x01L << 10)
+#define ADC_CTRL3_JENDCAIEN_MSK ((uint32_t)0x01L << 9)
+#define ADC_CTRL3_ENDCAIEN_MSK ((uint32_t)0x01L << 8)
+#define ADC_CTRL3_BPCAL_MSK ((uint32_t)0x01L << 7)
+#define ADC_CTRL3_CKMOD_MSK ((uint32_t)0x01L << 4)
+#define ADC_CTRL3_CALALD_MSK ((uint32_t)0x01L << 3)
+#define ADC_CTRL3_CALDIF_MSK ((uint32_t)0x01L << 2)
+#define ADC_CTRL3_RES_MSK ((uint32_t)0x03L << 0)
+#define ADC_SAMPT3_SAMPSEL_MSK ((uint32_t)0x01L << 3)
+typedef enum
+{
+ ADC_CTRL3_CKMOD_AHB = 0,
+ ADC_CTRL3_CKMOD_PLL = 1,
+} ADC_CTRL3_CKMOD;
+typedef enum
+{
+ ADC_CTRL3_RES_12BIT = 3,
+ ADC_CTRL3_RES_10BIT = 2,
+ ADC_CTRL3_RES_8BIT = 1,
+ ADC_CTRL3_RES_6BIT = 0,
+} ADC_CTRL3_RES;
+typedef struct
+{
+ FunctionalState DeepPowerModEn;
+ FunctionalState JendcIntEn;
+ FunctionalState EndcIntEn;
+ ADC_CTRL3_CKMOD ClkMode;
+ FunctionalState CalAtuoLoadEn;
+ bool DifModCal;
+ ADC_CTRL3_RES ResBit;
+ bool Samp303Style;
+} ADC_InitTypeEx;
+/**
+ * @}
+ */
+
+/**@addtogroup ADC_bit_num_definition
+ * @{
+ */
+#define ADC_RST_BIT_12 ((uint32_t)0x03)
+#define ADC_RST_BIT_10 ((uint32_t)0x02)
+#define ADC_RST_BIT_8 ((uint32_t)0x01)
+#define ADC_RESULT_BIT_6 ((uint32_t)0x00)
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_flags_ex_definition
+ * @{
+ */
+#define ADC_FLAG_RDY ((uint8_t)0x20)
+#define ADC_FLAG_PD_RDY ((uint8_t)0x40)
+#define IS_ADC_GET_READY(FLAG) (((FLAG) == ADC_FLAG_RDY) || ((FLAG) == ADC_FLAG_PD_RDY))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Exported_Functions
+ * @{
+ */
+
+void ADC_DeInit(ADC_Module* ADCx);
+void ADC_Init(ADC_Module* ADCx, ADC_InitType* ADC_InitStruct);
+void ADC_InitStruct(ADC_InitType* ADC_InitStruct);
+void ADC_Enable(ADC_Module* ADCx, FunctionalState Cmd);
+void ADC_EnableDMA(ADC_Module* ADCx, FunctionalState Cmd);
+void ADC_ConfigInt(ADC_Module* ADCx, uint16_t ADC_IT, FunctionalState Cmd);
+void ADC_StartCalibration(ADC_Module* ADCx);
+FlagStatus ADC_GetCalibrationStatus(ADC_Module* ADCx);
+void ADC_EnableSoftwareStartConv(ADC_Module* ADCx, FunctionalState Cmd);
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_Module* ADCx);
+void ADC_ConfigDiscModeChannelCount(ADC_Module* ADCx, uint8_t Number);
+void ADC_EnableDiscMode(ADC_Module* ADCx, FunctionalState Cmd);
+void ADC_ConfigRegularChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_EnableExternalTrigConv(ADC_Module* ADCx, FunctionalState Cmd);
+uint16_t ADC_GetDat(ADC_Module* ADCx);
+void ADC_EnableAutoInjectedConv(ADC_Module* ADCx, FunctionalState Cmd);
+void ADC_EnableInjectedDiscMode(ADC_Module* ADCx, FunctionalState Cmd);
+void ADC_ConfigExternalTrigInjectedConv(ADC_Module* ADCx, uint32_t ADC_ExternalTrigInjecConv);
+void ADC_EnableExternalTrigInjectedConv(ADC_Module* ADCx, FunctionalState Cmd);
+void ADC_EnableSoftwareStartInjectedConv(ADC_Module* ADCx, FunctionalState Cmd);
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_Module* ADCx);
+void ADC_ConfigInjectedChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_ConfigInjectedSequencerLength(ADC_Module* ADCx, uint8_t Length);
+void ADC_SetInjectedOffsetDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
+uint16_t ADC_GetInjectedConversionDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel);
+void ADC_ConfigAnalogWatchdogWorkChannelType(ADC_Module* ADCx, uint32_t ADC_AnalogWatchdog);
+void ADC_ConfigAnalogWatchdogThresholds(ADC_Module* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
+void ADC_ConfigAnalogWatchdogSingleChannel(ADC_Module* ADCx, uint8_t ADC_Channel);
+void ADC_EnableTempSensorVrefint(FunctionalState Cmd);
+FlagStatus ADC_GetFlagStatus(ADC_Module* ADCx, uint8_t ADC_FLAG);
+void ADC_ClearFlag(ADC_Module* ADCx, uint8_t ADC_FLAG);
+INTStatus ADC_GetIntStatus(ADC_Module* ADCx, uint16_t ADC_IT);
+void ADC_ClearIntPendingBit(ADC_Module* ADCx, uint16_t ADC_IT);
+
+void ADC_InitEx(ADC_Module* ADCx, ADC_InitTypeEx* ADC_InitStructEx);
+FlagStatus ADC_GetFlagStatusNew(ADC_Module* ADCx, uint8_t ADC_FLAG_NEW);
+void ADC_SetBypassCalibration(ADC_Module* ADCx, FunctionalState en);
+void ADC_SetConvResultBitNum(ADC_Module* ADCx, uint32_t ResultBitNum);
+
+void ADC_ConfigClk(ADC_CTRL3_CKMOD ADC_ClkMode, uint32_t RCC_ADCHCLKPrescaler);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32G43X_ADC_H__ */
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_can.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_can.h
new file mode 100644
index 0000000000..ea82c7a66a
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_can.h
@@ -0,0 +1,670 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_can.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_CAN_H__
+#define __N32G43X_CAN_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CAN
+ * @{
+ */
+
+/** @addtogroup CAN_Exported_Types
+ * @{
+ */
+
+#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN))
+
+/**
+ * @brief CAN init structure definition
+ */
+
+typedef struct
+{
+ uint16_t BaudRatePrescaler; /*!< Specifies the length of a time quantum.
+ It ranges from 1 to 1024. */
+
+ uint8_t OperatingMode; /*!< Specifies the CAN operating mode.
+ This parameter can be a value of
+ @ref CAN_operating_mode */
+
+ uint8_t RSJW; /*!< Specifies the maximum number of time quanta
+ the CAN hardware is allowed to lengthen or
+ shorten a bit to perform resynchronization.
+ This parameter can be a value of
+ @ref CAN_synchronisation_jump_width */
+
+ uint8_t TBS1; /*!< Specifies the number of time quanta in Bit
+ Segment 1. This parameter can be a value of
+ @ref CAN_time_quantum_in_bit_segment_1 */
+
+ uint8_t TBS2; /*!< Specifies the number of time quanta in Bit
+ Segment 2.
+ This parameter can be a value of
+ @ref CAN_time_quantum_in_bit_segment_2 */
+
+ FunctionalState TTCM; /*!< Enable or disable the time triggered
+ communication mode. This parameter can be set
+ either to ENABLE or DISABLE. */
+
+ FunctionalState ABOM; /*!< Enable or disable the automatic bus-off
+ management. This parameter can be set either
+ to ENABLE or DISABLE. */
+
+ FunctionalState AWKUM; /*!< Enable or disable the automatic wake-up mode.
+ This parameter can be set either to ENABLE or
+ DISABLE. */
+
+ FunctionalState NART; /*!< Enable or disable the no-automatic
+ retransmission mode. This parameter can be
+ set either to ENABLE or DISABLE. */
+
+ FunctionalState RFLM; /*!< Enable or disable the Receive DATFIFO Locked mode.
+ This parameter can be set either to ENABLE
+ or DISABLE. */
+
+ FunctionalState TXFP; /*!< Enable or disable the transmit DATFIFO priority.
+ This parameter can be set either to ENABLE
+ or DISABLE. */
+} CAN_InitType;
+
+/**
+ * @brief CAN filter init structure definition
+ */
+
+typedef struct
+{
+ uint16_t Filter_HighId; /*!< Specifies the filter identification number (MSBs for a 32-bit
+ configuration, first one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t Filter_LowId; /*!< Specifies the filter identification number (LSBs for a 32-bit
+ configuration, second one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t FilterMask_HighId; /*!< Specifies the filter mask number or identification number,
+ according to the mode (MSBs for a 32-bit configuration,
+ first one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t FilterMask_LowId; /*!< Specifies the filter mask number or identification number,
+ according to the mode (LSBs for a 32-bit configuration,
+ second one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t Filter_FIFOAssignment; /*!< Specifies the DATFIFO (0 or 1) which will be assigned to the filter.
+ This parameter can be a value of @ref CAN_filter_FIFO */
+
+ uint8_t Filter_Num; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
+
+ uint8_t Filter_Mode; /*!< Specifies the filter mode to be initialized.
+ This parameter can be a value of @ref CAN_filter_mode */
+
+ uint8_t Filter_Scale; /*!< Specifies the filter scale.
+ This parameter can be a value of @ref CAN_filter_scale */
+
+ FunctionalState Filter_Act; /*!< Enable or disable the filter.
+ This parameter can be set either to ENABLE or DISABLE. */
+} CAN_FilterInitType;
+
+/**
+ * @brief CAN Tx message structure definition
+ */
+
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter can be a value between 0 to 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+ uint8_t IDE; /*!< Specifies the type of identifier for the message that
+ will be transmitted. This parameter can be a value
+ of @ref CAN_identifier_type */
+
+ uint8_t RTR; /*!< Specifies the type of frame for the message that will
+ be transmitted. This parameter can be a value of
+ @ref CAN_remote_transmission_request */
+
+ uint8_t DLC; /*!< Specifies the length of the frame that will be
+ transmitted. This parameter can be a value between
+ 0 to 8 */
+
+ uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
+ to 0xFF. */
+} CanTxMessage;
+
+/**
+ * @brief CAN Rx message structure definition
+ */
+
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter can be a value between 0 to 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+ uint8_t IDE; /*!< Specifies the type of identifier for the message that
+ will be received. This parameter can be a value of
+ @ref CAN_identifier_type */
+
+ uint8_t RTR; /*!< Specifies the type of frame for the received message.
+ This parameter can be a value of
+ @ref CAN_remote_transmission_request */
+
+ uint8_t DLC; /*!< Specifies the length of the frame that will be received.
+ This parameter can be a value between 0 to 8 */
+
+ uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
+ 0xFF. */
+
+ uint8_t FMI; /*!< Specifies the index of the filter the message stored in
+ the mailbox passes through. This parameter can be a
+ value between 0 to 0xFF */
+} CanRxMessage;
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup CAN_sleep_constants
+ * @{
+ */
+
+#define CAN_InitSTS_Failed ((uint8_t)0x00) /*!< CAN initialization failed */
+#define CAN_InitSTS_Success ((uint8_t)0x01) /*!< CAN initialization OK */
+
+/**
+ * @}
+ */
+
+/** @addtogroup OperatingMode
+ * @{
+ */
+
+#define CAN_Normal_Mode ((uint8_t)0x00) /*!< normal mode */
+#define CAN_LoopBack_Mode ((uint8_t)0x01) /*!< loopback mode */
+#define CAN_Silent_Mode ((uint8_t)0x02) /*!< silent mode */
+#define CAN_Silent_LoopBack_Mode ((uint8_t)0x03) /*!< loopback combined with silent mode */
+
+#define IS_CAN_MODE(MODE) \
+ (((MODE) == CAN_Normal_Mode) || ((MODE) == CAN_LoopBack_Mode) || ((MODE) == CAN_Silent_Mode) \
+ || ((MODE) == CAN_Silent_LoopBack_Mode))
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup CAN_operating_mode
+ * @{
+ */
+#define CAN_Operating_InitMode ((uint8_t)0x00) /*!< Initialization mode */
+#define CAN_Operating_NormalMode ((uint8_t)0x01) /*!< Normal mode */
+#define CAN_Operating_SleepMode ((uint8_t)0x02) /*!< sleep mode */
+
+#define IS_CAN_OPERATING_MODE(MODE) \
+ (((MODE) == CAN_Operating_InitMode) || ((MODE) == CAN_Operating_NormalMode) || ((MODE) == CAN_Operating_SleepMode))
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup CAN_Mode_Status
+ * @{
+ */
+
+#define CAN_ModeSTS_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */
+#define CAN_ModeSTS_Success ((uint8_t)!CAN_ModeSTS_Failed) /*!< CAN entering the specific mode Succeed */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_synchronisation_jump_width
+ * @{
+ */
+
+#define CAN_RSJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_RSJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_RSJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_RSJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+
+#define IS_CAN_RSJW(SJW) \
+ (((SJW) == CAN_RSJW_1tq) || ((SJW) == CAN_RSJW_2tq) || ((SJW) == CAN_RSJW_3tq) || ((SJW) == CAN_RSJW_4tq))
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_time_quantum_in_bit_segment_1
+ * @{
+ */
+
+#define CAN_TBS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_TBS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_TBS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_TBS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+#define CAN_TBS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */
+#define CAN_TBS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */
+#define CAN_TBS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */
+#define CAN_TBS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */
+#define CAN_TBS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */
+#define CAN_TBS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */
+#define CAN_TBS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */
+#define CAN_TBS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */
+#define CAN_TBS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */
+#define CAN_TBS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */
+#define CAN_TBS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */
+#define CAN_TBS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */
+
+#define IS_CAN_TBS1(BS1) ((BS1) <= CAN_TBS1_16tq)
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_time_quantum_in_bit_segment_2
+ * @{
+ */
+
+#define CAN_TBS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_TBS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_TBS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_TBS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+#define CAN_TBS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */
+#define CAN_TBS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */
+#define CAN_TBS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */
+#define CAN_TBS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */
+
+#define IS_CAN_TBS2(BS2) ((BS2) <= CAN_TBS2_8tq)
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_clock_prescaler
+ * @{
+ */
+
+#define IS_CAN_BAUDRATEPRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_filter_number
+ * @{
+ */
+#define IS_CAN_FILTER_NUM(NUMBER) ((NUMBER) <= 13)
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_filter_mode
+ * @{
+ */
+
+#define CAN_Filter_IdMaskMode ((uint8_t)0x00) /*!< identifier/mask mode */
+#define CAN_Filter_IdListMode ((uint8_t)0x01) /*!< identifier list mode */
+
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_Filter_IdMaskMode) || ((MODE) == CAN_Filter_IdListMode))
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_filter_scale
+ * @{
+ */
+
+#define CAN_Filter_16bitScale ((uint8_t)0x00) /*!< Two 16-bit filters */
+#define CAN_Filter_32bitScale ((uint8_t)0x01) /*!< One 32-bit filter */
+
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_Filter_16bitScale) || ((SCALE) == CAN_Filter_32bitScale))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_filter_FIFO
+ * @{
+ */
+
+#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter DATFIFO 0 assignment for filter x */
+#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter DATFIFO 1 assignment for filter x */
+#define IS_CAN_FILTER_FIFO(DATFIFO) (((DATFIFO) == CAN_FilterFIFO0) || ((DATFIFO) == CAN_FilterFIFO1))
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Tx
+ * @{
+ */
+
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_identifier_type
+ * @{
+ */
+
+#define CAN_Standard_Id ((uint32_t)0x00000000) /*!< Standard Id */
+#define CAN_Extended_Id ((uint32_t)0x00000004) /*!< Extended Id */
+#define IS_CAN_ID(IDTYPE) (((IDTYPE) == CAN_Standard_Id) || ((IDTYPE) == CAN_Extended_Id))
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_remote_transmission_request
+ * @{
+ */
+
+#define CAN_RTRQ_Data ((uint32_t)0x00000000) /*!< Data frame */
+#define CAN_RTRQ_Remote ((uint32_t)0x00000002) /*!< Remote frame */
+#define IS_CAN_RTRQ(RTR) (((RTR) == CAN_RTRQ_Data) || ((RTR) == CAN_RTRQ_Remote))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_transmit_constants
+ * @{
+ */
+
+#define CAN_TxSTS_Failed ((uint8_t)0x00) /*!< CAN transmission failed */
+#define CAN_TxSTS_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */
+#define CAN_TxSTS_Pending ((uint8_t)0x02) /*!< CAN transmission pending */
+#define CAN_TxSTS_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_receive_FIFO_number_constants
+ * @{
+ */
+
+#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN DATFIFO 0 used to receive */
+#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN DATFIFO 1 used to receive */
+
+#define IS_CAN_FIFO(DATFIFO) (((DATFIFO) == CAN_FIFO0) || ((DATFIFO) == CAN_FIFO1))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_sleep_constants
+ * @{
+ */
+
+#define CAN_SLEEP_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
+#define CAN_SLEEP_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_wake_up_constants
+ * @{
+ */
+
+#define CAN_WKU_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
+#define CAN_WKU_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
+
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup CAN_Error_Code_constants
+ * @{
+ */
+
+#define CAN_ERRCode_NoErr ((uint8_t)0x00) /*!< No Error */
+#define CAN_ERRCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */
+#define CAN_ERRCode_FormErr ((uint8_t)0x20) /*!< Form Error */
+#define CAN_ERRCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */
+#define CAN_ERRCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */
+#define CAN_ERRCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */
+#define CAN_ERRCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */
+#define CAN_ERRCode_SWSetErr ((uint8_t)0x70) /*!< Software Set Error */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_flags
+ * @{
+ */
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagSTS()
+ and CAN_ClearFlag() functions. */
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagSTS() function. */
+
+/* Transmit Flags */
+#define CAN_FLAG_RQCPM0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
+#define CAN_FLAG_RQCPM1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
+#define CAN_FLAG_RQCPM2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
+
+/* Receive Flags */
+#define CAN_FLAG_FFMP0 ((uint32_t)0x12000003) /*!< DATFIFO 0 Message Pending Flag */
+#define CAN_FLAG_FFULL0 ((uint32_t)0x32000008) /*!< DATFIFO 0 Full Flag */
+#define CAN_FLAG_FFOVR0 ((uint32_t)0x32000010) /*!< DATFIFO 0 Overrun Flag */
+#define CAN_FLAG_FFMP1 ((uint32_t)0x14000003) /*!< DATFIFO 1 Message Pending Flag */
+#define CAN_FLAG_FFULL1 ((uint32_t)0x34000008) /*!< DATFIFO 1 Full Flag */
+#define CAN_FLAG_FFOVR1 ((uint32_t)0x34000010) /*!< DATFIFO 1 Overrun Flag */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */
+#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
+/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible.
+ In this case the SLAK bit can be polled.*/
+
+/* Error Flags */
+#define CAN_FLAG_EWGFL ((uint32_t)0x10F00001) /*!< Error Warning Flag */
+#define CAN_FLAG_EPVFL ((uint32_t)0x10F00002) /*!< Error Passive Flag */
+#define CAN_FLAG_BOFFL ((uint32_t)0x10F00004) /*!< Bus-Off Flag */
+#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */
+
+#define IS_CAN_GET_FLAG(FLAG) \
+ (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOFFL) || ((FLAG) == CAN_FLAG_EPVFL) \
+ || ((FLAG) == CAN_FLAG_EWGFL) || ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FFOVR0) \
+ || ((FLAG) == CAN_FLAG_FFULL0) || ((FLAG) == CAN_FLAG_FFMP0) || ((FLAG) == CAN_FLAG_FFOVR1) \
+ || ((FLAG) == CAN_FLAG_FFULL1) || ((FLAG) == CAN_FLAG_FFMP1) || ((FLAG) == CAN_FLAG_RQCPM2) \
+ || ((FLAG) == CAN_FLAG_RQCPM1) || ((FLAG) == CAN_FLAG_RQCPM0) || ((FLAG) == CAN_FLAG_SLAK))
+
+#define IS_CAN_CLEAR_FLAG(FLAG) \
+ (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCPM2) || ((FLAG) == CAN_FLAG_RQCPM1) \
+ || ((FLAG) == CAN_FLAG_RQCPM0) || ((FLAG) == CAN_FLAG_FFULL0) || ((FLAG) == CAN_FLAG_FFOVR0) \
+ || ((FLAG) == CAN_FLAG_FFULL1) || ((FLAG) == CAN_FLAG_FFOVR1) || ((FLAG) == CAN_FLAG_WKU) \
+ || ((FLAG) == CAN_FLAG_SLAK))
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_interrupts
+ * @{
+ */
+
+#define CAN_INT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
+
+/* Receive Interrupts */
+#define CAN_INT_FMP0 ((uint32_t)0x00000002) /*!< DATFIFO 0 message pending Interrupt*/
+#define CAN_INT_FF0 ((uint32_t)0x00000004) /*!< DATFIFO 0 full Interrupt*/
+#define CAN_INT_FOV0 ((uint32_t)0x00000008) /*!< DATFIFO 0 overrun Interrupt*/
+#define CAN_INT_FMP1 ((uint32_t)0x00000010) /*!< DATFIFO 1 message pending Interrupt*/
+#define CAN_INT_FF1 ((uint32_t)0x00000020) /*!< DATFIFO 1 full Interrupt*/
+#define CAN_INT_FOV1 ((uint32_t)0x00000040) /*!< DATFIFO 1 overrun Interrupt*/
+
+/* Operating Mode Interrupts */
+#define CAN_INT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
+#define CAN_INT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
+
+/* Error Interrupts */
+#define CAN_INT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
+#define CAN_INT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
+#define CAN_INT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
+#define CAN_INT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
+#define CAN_INT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/
+
+/* Flags named as Interrupts : kept only for FW compatibility */
+#define CAN_INT_RQCPM0 CAN_INT_TME
+#define CAN_INT_RQCPM1 CAN_INT_TME
+#define CAN_INT_RQCPM2 CAN_INT_TME
+
+#define IS_CAN_INT(IT) \
+ (((IT) == CAN_INT_TME) || ((IT) == CAN_INT_FMP0) || ((IT) == CAN_INT_FF0) || ((IT) == CAN_INT_FOV0) \
+ || ((IT) == CAN_INT_FMP1) || ((IT) == CAN_INT_FF1) || ((IT) == CAN_INT_FOV1) || ((IT) == CAN_INT_EWG) \
+ || ((IT) == CAN_INT_EPV) || ((IT) == CAN_INT_BOF) || ((IT) == CAN_INT_LEC) || ((IT) == CAN_INT_ERR) \
+ || ((IT) == CAN_INT_WKU) || ((IT) == CAN_INT_SLK))
+
+#define IS_CAN_CLEAR_INT(IT) \
+ (((IT) == CAN_INT_TME) || ((IT) == CAN_INT_FF0) || ((IT) == CAN_INT_FOV0) || ((IT) == CAN_INT_FF1) \
+ || ((IT) == CAN_INT_FOV1) || ((IT) == CAN_INT_EWG) || ((IT) == CAN_INT_EPV) || ((IT) == CAN_INT_BOF) \
+ || ((IT) == CAN_INT_LEC) || ((IT) == CAN_INT_ERR) || ((IT) == CAN_INT_WKU) || ((IT) == CAN_INT_SLK))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Legacy
+ * @{
+ */
+#define CANINITSTSFAILED CAN_InitSTS_Failed
+#define CANINITSTSOK CAN_InitSTS_Success
+#define CAN_FilterFIFO0 CAN_Filter_FIFO0
+#define CAN_FilterFIFO1 CAN_Filter_FIFO1
+#define CAN_ID_STD CAN_Standard_Id
+#define CAN_ID_EXT CAN_Extended_Id
+#define CAN_RTRQ_DATA CAN_RTRQ_Data
+#define CAN_RTRQ_REMOTE CAN_RTRQ_Remote
+#define CANTXSTSFAILE CAN_TxSTS_Failed
+#define CANTXSTSOK CAN_TxSTS_Ok
+#define CANTXSTSPENDING CAN_TxSTS_Pending
+#define CAN_STS_NO_MB CAN_TxSTS_NoMailBox
+#define CANSLEEPFAILED CAN_SLEEP_Failed
+#define CANSLEEPOK CAN_SLEEP_Ok
+#define CANWKUFAILED CAN_WKU_Failed
+#define CANWKUOK CAN_WKU_Ok
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions
+ * @{
+ */
+/* Function used to set the CAN configuration to the default reset state *****/
+void CAN_DeInit(CAN_Module* CANx);
+
+/* Initialization and Configuration functions *********************************/
+uint8_t CAN_Init(CAN_Module* CANx, CAN_InitType* CAN_InitParam);
+void CAN_InitFilter(CAN_FilterInitType* CAN_InitFilterStruct);
+void CAN_InitStruct(CAN_InitType* CAN_InitParam);
+void CAN_DebugFreeze(CAN_Module* CANx, FunctionalState Cmd);
+void CAN_EnTTComMode(CAN_Module* CANx, FunctionalState Cmd);
+
+/* Transmit functions *********************************************************/
+uint8_t CAN_TransmitMessage(CAN_Module* CANx, CanTxMessage* TxMessage);
+uint8_t CAN_TransmitSTS(CAN_Module* CANx, uint8_t TransmitMailbox);
+void CAN_CancelTransmitMessage(CAN_Module* CANx, uint8_t Mailbox);
+
+/* Receive functions **********************************************************/
+void CAN_ReceiveMessage(CAN_Module* CANx, uint8_t FIFONum, CanRxMessage* RxMessage);
+void CAN_ReleaseFIFO(CAN_Module* CANx, uint8_t FIFONum);
+uint8_t CAN_PendingMessage(CAN_Module* CANx, uint8_t FIFONum);
+
+/* Operation modes functions **************************************************/
+uint8_t CAN_OperatingModeReq(CAN_Module* CANx, uint8_t CAN_OperatingMode);
+uint8_t CAN_EnterSleep(CAN_Module* CANx);
+uint8_t CAN_WakeUp(CAN_Module* CANx);
+
+/* Error management functions *************************************************/
+uint8_t CAN_GetLastErrCode(CAN_Module* CANx);
+uint8_t CAN_GetReceiveErrCounter(CAN_Module* CANx);
+uint8_t CAN_GetLSBTransmitErrCounter(CAN_Module* CANx);
+
+/* Interrupts and flags management functions **********************************/
+void CAN_INTConfig(CAN_Module* CANx, uint32_t CAN_INT, FunctionalState Cmd);
+FlagStatus CAN_GetFlagSTS(CAN_Module* CANx, uint32_t CAN_FLAG);
+void CAN_ClearFlag(CAN_Module* CANx, uint32_t CAN_FLAG);
+INTStatus CAN_GetIntStatus(CAN_Module* CANx, uint32_t CAN_INT);
+void CAN_ClearINTPendingBit(CAN_Module* CANx, uint32_t CAN_INT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32G43X_CAN_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_comp.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_comp.h
new file mode 100644
index 0000000000..b42c844369
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_comp.h
@@ -0,0 +1,282 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_comp.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_COMP_H__
+#define __N32G43X_COMP_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+#include
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup COMP
+ * @{
+ */
+
+/** @addtogroup COMP_Exported_Constants
+ * @{
+ */
+typedef enum
+{
+ COMP1 = 0,
+ COMP2 = 1,
+} COMPX;
+
+// COMPx_CTRL
+#define COMP1_CTRL_PWRMODE_MASK (0x01L << 21)
+#define COMP1_CTRL_INPDAC_MASK (0x01L << 20)
+#define COMP_CTRL_OUT_MASK (0x01L << 19)
+#define COMP_CTRL_BLKING_MASK (0x03L << 16)
+typedef enum
+{
+ COMP_CTRL_BLKING_NO = (0x0L << 16),
+ COMP_CTRL_BLKING_TIM1_OC5 = (0x1L << 16),
+ COMP_CTRL_BLKING_TIM8_OC5 = (0x2L << 16),
+} COMP_CTRL_BLKING;
+#define COMPx_CTRL_HYST_MASK (0x03L << 14)
+typedef enum
+{
+ COMP_CTRL_HYST_NO = (0x0L << 14),
+ COMP_CTRL_HYST_LOW = (0x1L << 14),
+ COMP_CTRL_HYST_MID = (0x2L << 14),
+ COMP_CTRL_HYST_HIGH = (0x3L << 14),
+} COMP_CTRL_HYST;
+
+#define COMP_POL_MASK (0x01L << 13)
+#define COMP_CTRL_OUTSEL_MASK (0x0FL << 9)
+typedef enum
+{
+ // comp1 out trig
+ COMP1_CTRL_OUTSEL_NC = (0x0L << 9),
+ COMP1_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 9),
+ COMP1_CTRL_OUTSEL_TIM1_OCrefclear = (0x2L << 9),
+ COMP1_CTRL_OUTSEL_TIM1_IC1 = (0x3L << 9),
+ COMP1_CTRL_OUTSEL_TIM2_IC1 = (0x4L << 9),
+ COMP1_CTRL_OUTSEL_TIM2_OCrefclear = (0x5L << 9),
+ COMP1_CTRL_OUTSEL_TIM3_IC1 = (0x6L << 9),
+ COMP1_CTRL_OUTSEL_TIM3_OCrefclear = (0x7L << 9),
+ COMP1_CTRL_OUTSEL_TIM4_OCrefclear = (0x8L << 9),
+ COMP1_CTRL_OUTSEL_TIM5_IC1 = (0x9L << 9),
+ COMP1_CTRL_OUTSEL_TIM8_IC1 = (0xAL << 9),
+ COMP1_CTRL_OUTSEL_TIM8_OCrefclear = (0xBL << 9),
+ COMP1_CTRL_OUTSEL_TIM9_OCrefclear = (0xCL << 9),
+ COMP1_CTRL_OUTSEL_TIM8_BKIN = (0xDL << 9),
+ COMP1_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xEL << 9),
+ COMP1_CTRL_OUTSEL_LPTIM_ETR = (0xFL << 9),
+ // comp2 out trig
+ COMP2_CTRL_OUTSEL_NC = (0x0L << 9),
+ COMP2_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 9),
+ COMP2_CTRL_OUTSEL_TIM1_OCrefclear = (0x2L << 9),
+ COMP2_CTRL_OUTSEL_TIM1_IC1 = (0x3L << 9),
+ COMP2_CTRL_OUTSEL_TIM2_OCrefclear = (0x4L << 9),
+ COMP2_CTRL_OUTSEL_TIM3_OCrefclear = (0x5L << 9),
+ COMP2_CTRL_OUTSEL_TIM4_IC1 = (0x6L << 9),
+ COMP2_CTRL_OUTSEL_TIM4_OCrefclear = (0x7L << 9),
+ COMP2_CTRL_OUTSEL_TIM5_IC1 = (0x8L << 9),
+ COMP2_CTRL_OUTSEL_TIM8_IC1 = (0x9L << 9),
+ COMP2_CTRL_OUTSEL_TIM8_OCrefclear = (0xAL << 9),
+ COMP2_CTRL_OUTSEL_TIM9_IC1 = (0xBL << 9),
+ COMP2_CTRL_OUTSEL_TIM9_OCrefclear = (0xCL << 9),
+ COMP2_CTRL_OUTSEL_TIM8_BKIN = (0xDL << 9),
+ COMP2_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xEL << 9),
+ COMP2_CTRL_OUTSEL_LPTIM_ETR = (0xFL << 9),
+} COMP_CTRL_OUTTRIG;
+
+#define COMP_CTRL_INPSEL_MASK (0x0FL<<5)
+typedef enum {
+ //comp1 inp sel
+ COMP1_CTRL_INPSEL_FLOAT = ((uint32_t)0x00000000),
+ COMP1_CTRL_INPSEL_PA0 = ((uint32_t)0x00000100),
+ COMP1_CTRL_INPSEL_PA2 = ((uint32_t)0x00000140),
+ COMP1_CTRL_INPSEL_PA12 = ((uint32_t)0x00000160),
+ COMP1_CTRL_INPSEL_PB3 = ((uint32_t)0x00000180),
+ COMP1_CTRL_INPSEL_PB4 = ((uint32_t)0x000001A0),
+ COMP1_CTRL_INPSEL_PB10 = ((uint32_t)0x000001C0),
+ COMP1_CTRL_INPSEL_PD5 = ((uint32_t)0x000001E0),
+ COMP1_CTRL_INPSEL_PA1_DAC1 = ((uint32_t)0x00000120),
+ //comp2 inp sel
+ COMP2_CTRL_INPSEL_FLOAT = ((uint32_t)0x00000000),
+ COMP2_CTRL_INPSEL_PA1_DAC1_PA4= ((uint32_t)0x00000100),
+ COMP2_CTRL_INPSEL_PA3 = ((uint32_t)0x00000120),
+ COMP2_CTRL_INPSEL_PA6 = ((uint32_t)0x00000140),
+ COMP2_CTRL_INPSEL_PA7 = ((uint32_t)0x00000160),
+ COMP2_CTRL_INPSEL_PA11 = ((uint32_t)0x00000180),
+ COMP2_CTRL_INPSEL_PA15 = ((uint32_t)0x000001A0),
+ COMP2_CTRL_INPSEL_PB7 = ((uint32_t)0x000001C0),
+ COMP2_CTRL_INPSEL_PD7 = ((uint32_t)0x000001E0),
+}COMP_CTRL_INPSEL;
+
+
+#define COMP_CTRL_INMSEL_MASK (0x07L<<1)
+typedef enum {
+ //comp1 inm sel
+ COMP1_CTRL_INMSEL_DAC1_PA4 = ((uint32_t)0x00000002),
+ COMP1_CTRL_INMSEL_PA0 = ((uint32_t)0x00000004),
+ COMP1_CTRL_INMSEL_PA5 = ((uint32_t)0x00000006),
+ COMP1_CTRL_INMSEL_PB5 = ((uint32_t)0x00000008),
+ COMP1_CTRL_INMSEL_PD4 = ((uint32_t)0x0000000A),
+ COMP1_CTRL_INMSEL_VREF_VC1 = ((uint32_t)0x0000000C),
+ COMP1_CTRL_INMSEL_VREF_VC2 = ((uint32_t)0x0000000E),
+ COMP1_CTRL_INMSEL_NC = ((uint32_t)0x00000000),
+ //comp2 inm sel
+ COMP2_CTRL_INMSEL_PA2 = ((uint32_t)0x00000002),
+ COMP2_CTRL_INMSEL_PA5 = ((uint32_t)0x00000004),
+ COMP2_CTRL_INMSEL_PA6 = ((uint32_t)0x00000006),
+ COMP2_CTRL_INMSEL_PB3 = ((uint32_t)0x00000008),
+ COMP2_CTRL_INMSEL_PD6 = ((uint32_t)0x0000000A),
+ COMP2_CTRL_INMSEL_DAC1_PA4 = ((uint32_t)0x0000000C),
+ COMP2_CTRL_INMSEL_VREF_VC2 = ((uint32_t)0x0000000E),
+ COMP2_CTRL_INMSEL_NC = ((uint32_t)0x00000000),
+}COMP_CTRL_INMSEL;
+
+#define COMP_CTRL_EN_MASK (0x01L << 0)
+
+//COMPx_FILC
+#define COMP_FILC_SAMPW_MASK (0x1FL<<6)//Low filter sample window size. Number of samples to monitor is SAMPWIN+1.
+#define COMP_FILC_THRESH_MASK (0x1FL<<1)//For proper operation, the value of THRESH must be greater than SAMPWIN / 2.
+#define COMP_FILC_FILEN_MASK (0x01L<<0)//Filter enable.
+
+//COMPx_FILP
+#define COMP_FILP_CLKPSC_MASK (0xFFFFL)//Prescale number .
+
+//COMP_WINMODE @addtogroup COMP_WINMODE_CMPMD
+#define COMP_WINMODE_CMP12MD (0x01L <<0)//1: Comparators 1 and 2 can be used in window mode.
+
+//COMP_INTEN @addtogroup COMP_INTEN_CMPIEN
+#define COMP_INTEN_CMPIEN_MSK (0x3L << 0) // This bit control Interrput enable of COMP.
+#define COMP_INTEN_CMP2IEN (0x01L << 1)
+#define COMP_INTEN_CMP1IEN (0x01L << 0)
+
+//COMP_INTSTS @addtogroup COMP_INTSTS_CMPIS
+#define COMP_INTSTS_INTSTS_MSK (0x3L << 0) // This bit control Interrput enable of COMP.
+#define COMP_INTSTS_CMP2IS (0x01L << 1)
+#define COMP_INTSTS_CMP1IS (0x01L << 0)
+
+//COMP_VREFSCL @addtogroup COMP_VREFSCL
+#define COMP_VREFSCL_VV2TRM_MSK (0x3FL << 8) // Vref2 Voltage scaler triming value.
+#define COMP_VREFSCL_VV2EN_MSK (0x01L << 7)
+#define COMP_VREFSCL_VV1TRM_MSK (0x3FL << 1) // Vref1 Voltage scaler triming value.
+#define COMP_VREFSCL_VV1EN_MSK (0x01L << 0)
+
+//COMP_LOCK @addtogroup COMP_LOCK
+#define COMP_LOCK_CMP2LK (0x1L << 1) // Vref1 Voltage scaler triming value.
+#define COMP_LOCK_CMP1LK (0x1L << 0)
+
+//COMP_LPCKSEL @addtogroup COMP_LPCKSEL
+#define COMP_LKCKSEL_LPCLKSEL (0x1L << 0)
+
+//COMP_OSEL @addtogroup COMP_OSEL
+#define COMP_OSEL_CMP2XO (0x1L << 0)
+
+/**
+ * @}
+ */
+
+/**
+ * @brief COMP Init structure definition
+ */
+
+typedef struct
+{
+ // ctrl
+ bool LowPoweMode; // only COMP1 have this bit
+ bool InpDacConnect; // only COMP1 have this bit
+
+ COMP_CTRL_BLKING Blking; /*see @ref COMP_CTRL_BLKING */
+
+ COMP_CTRL_HYST Hyst;
+
+ bool PolRev; // out polarity reverse
+
+ COMP_CTRL_OUTTRIG OutTrig;
+ COMP_CTRL_INPSEL InpSel;
+ COMP_CTRL_INMSEL InmSel;
+
+ bool En;
+
+ // filter
+ uint8_t SampWindow; // 5bit
+ uint8_t Thresh; // 5bit ,need > SampWindow/2
+ bool FilterEn;
+
+ // filter psc
+ uint16_t ClkPsc;
+} COMP_InitType;
+
+/** @addtogroup COMP_Exported_Functions
+ * @{
+ */
+
+void COMP_DeInit(void);
+void COMP_StructInit(COMP_InitType* COMP_InitStruct);
+void COMP_Init(COMPX COMPx, COMP_InitType* COMP_InitStruct);
+void COMP_Enable(COMPX COMPx, FunctionalState en);
+void COMP_SetInpSel(COMPX COMPx, COMP_CTRL_INPSEL VpSel);
+void COMP_SetInmSel(COMPX COMPx, COMP_CTRL_INMSEL VmSel);
+void COMP_SetOutTrig(COMPX COMPx, COMP_CTRL_OUTTRIG OutTrig);
+uint32_t COMP_GetIntSts(void); // return see @COMP_INTSTS_CMPIS
+void COMP_SetRefScl(uint8_t Vv2Trim, bool Vv2En, uint8_t Vv1Trim, bool Vv1En); // parma range see @COMP_VREFSCL
+FlagStatus COMP_GetOutStatus(COMPX COMPx);
+FlagStatus COMP_GetIntStsOneComp(COMPX COMPx);
+void COMP_SetLock(uint32_t Lock); // see @COMP_LOCK_CMPLK
+void COMP_SetIntEn(uint32_t IntEn); // see @COMP_INTEN_CMPIEN
+void COMP_CMP2XorOut(bool En);
+void COMP_StopOrLowpower32KClkSel(bool En);
+void COMP_WindowModeEn(bool En);
+void COMP_SetFilterPrescaler(COMPX COMPx , uint16_t FilPreVal);
+void COMP_SetFilterControl(COMPX COMPx , uint8_t FilEn, uint8_t TheresNum , uint8_t SampPW);
+void COMP_SetHyst(COMPX COMPx , COMP_CTRL_HYST HYST);
+void COMP_SetBlanking(COMPX COMPx , COMP_CTRL_BLKING BLK);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32G43X_ADC_H */
+/**
+ * @}
+ */
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_crc.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_crc.h
new file mode 100644
index 0000000000..1e419b8353
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_crc.h
@@ -0,0 +1,105 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_crc.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_CRC_H__
+#define __N32G43X_CRC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CRC
+ * @{
+ */
+
+/** @addtogroup CRC_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Exported_Functions
+ * @{
+ */
+
+void CRC32_ResetCrc(void);
+uint32_t CRC32_CalcCrc(uint32_t Data);
+uint32_t CRC32_CalcBufCrc(uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t CRC32_GetCrc(void);
+void CRC32_SetIDat(uint8_t IDValue);
+uint8_t CRC32_GetIDat(void);
+
+uint16_t CRC16_CalcBufCrc(uint8_t pBuffer[], uint32_t BufferLength);
+uint16_t CRC16_CalcCRC(uint8_t Data);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32G43X_CRC_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_dac.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_dac.h
new file mode 100644
index 0000000000..35f1904d52
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_dac.h
@@ -0,0 +1,293 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_dac.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_DAC_H__
+#define __N32G43X_DAC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DAC
+ * @{
+ */
+
+/** @addtogroup DAC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief DAC Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t Trigger; /*!< Specifies the external trigger for the selected DAC channel.
+ This parameter can be a value of @ref DAC_trigger_selection */
+
+ uint32_t WaveGen; /*!< Specifies whether DAC channel noise waves or triangle waves
+ are generated, or whether no wave is generated.
+ This parameter can be a value of @ref DAC_wave_generation */
+
+ uint32_t
+ LfsrUnMaskTriAmp; /*!< Specifies the LFSR mask for noise wave generation or
+ the maximum amplitude triangle generation for the DAC channel.
+ This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
+
+ uint32_t BufferOutput; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+ This parameter can be a value of @ref DAC_output_buffer */
+} DAC_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup DAC_trigger_selection
+ * @{
+ */
+
+#define DAC_TRG_NONE \
+ ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register \
+ has been loaded, and not by external trigger */
+#define DAC_TRG_T6_TRGO \
+ ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel \
+ */
+#define DAC_TRG_T8_TRGO \
+ ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel \
+ only in High-density devices*/
+#define DAC_TRG_T7_TRGO \
+ ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel \
+ */
+#define DAC_TRG_T5_TRGO \
+ ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel \
+ */
+#define DAC_TRG_T2_TRGO \
+ ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel \
+ */
+#define DAC_TRG_T4_TRGO \
+ ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel \
+ */
+#define DAC_TRG_EXT_IT9 \
+ ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRG_SOFTWARE ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER) \
+ (((TRIGGER) == DAC_TRG_NONE) || ((TRIGGER) == DAC_TRG_T6_TRGO) || ((TRIGGER) == DAC_TRG_T8_TRGO) \
+ || ((TRIGGER) == DAC_TRG_T7_TRGO) || ((TRIGGER) == DAC_TRG_T5_TRGO) || ((TRIGGER) == DAC_TRG_T2_TRGO) \
+ || ((TRIGGER) == DAC_TRG_T4_TRGO) || ((TRIGGER) == DAC_TRG_EXT_IT9) || ((TRIGGER) == DAC_TRG_SOFTWARE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_wave_generation
+ * @{
+ */
+
+#define DAC_WAVEGEN_NONE ((uint32_t)0x00000000)
+#define DAC_WAVEGEN_NOISE ((uint32_t)0x00000040)
+#define DAC_WAVEGEN_TRIANGLE ((uint32_t)0x00000080)
+#define IS_DAC_GENERATE_WAVE(WAVE) \
+ (((WAVE) == DAC_WAVEGEN_NONE) || ((WAVE) == DAC_WAVEGEN_NOISE) || ((WAVE) == DAC_WAVEGEN_TRIANGLE))
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_lfsrunmask_triangleamplitude
+ * @{
+ */
+
+#define DAC_UNMASK_LFSRBIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_UNMASK_LFSRBITS1_0 \
+ ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS2_0 \
+ ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS3_0 \
+ ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS4_0 \
+ ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS5_0 \
+ ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS6_0 \
+ ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS7_0 \
+ ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS8_0 \
+ ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS9_0 \
+ ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS10_0 \
+ ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_UNMASK_LFSRBITS11_0 \
+ ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TRIAMP_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TRIAMP_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
+#define DAC_TRIAMP_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
+#define DAC_TRIAMP_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
+#define DAC_TRIAMP_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
+#define DAC_TRIAMP_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
+#define DAC_TRIAMP_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
+#define DAC_TRIAMP_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
+#define DAC_TRIAMP_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
+#define DAC_TRIAMP_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TRIAMP_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TRIAMP_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) \
+ (((VALUE) == DAC_UNMASK_LFSRBIT0) || ((VALUE) == DAC_UNMASK_LFSRBITS1_0) || ((VALUE) == DAC_UNMASK_LFSRBITS2_0) \
+ || ((VALUE) == DAC_UNMASK_LFSRBITS3_0) || ((VALUE) == DAC_UNMASK_LFSRBITS4_0) \
+ || ((VALUE) == DAC_UNMASK_LFSRBITS5_0) || ((VALUE) == DAC_UNMASK_LFSRBITS6_0) \
+ || ((VALUE) == DAC_UNMASK_LFSRBITS7_0) || ((VALUE) == DAC_UNMASK_LFSRBITS8_0) \
+ || ((VALUE) == DAC_UNMASK_LFSRBITS9_0) || ((VALUE) == DAC_UNMASK_LFSRBITS10_0) \
+ || ((VALUE) == DAC_UNMASK_LFSRBITS11_0) || ((VALUE) == DAC_TRIAMP_1) || ((VALUE) == DAC_TRIAMP_3) \
+ || ((VALUE) == DAC_TRIAMP_7) || ((VALUE) == DAC_TRIAMP_15) || ((VALUE) == DAC_TRIAMP_31) \
+ || ((VALUE) == DAC_TRIAMP_63) || ((VALUE) == DAC_TRIAMP_127) || ((VALUE) == DAC_TRIAMP_255) \
+ || ((VALUE) == DAC_TRIAMP_511) || ((VALUE) == DAC_TRIAMP_1023) || ((VALUE) == DAC_TRIAMP_2047) \
+ || ((VALUE) == DAC_TRIAMP_4095))
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_output_buffer
+ * @{
+ */
+
+#define DAC_BUFFOUTPUT_ENABLE ((uint32_t)0x00000002)
+#define DAC_BUFFOUTPUT_DISABLE ((uint32_t)0x00000000)
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_BUFFOUTPUT_ENABLE) || ((STATE) == DAC_BUFFOUTPUT_DISABLE))
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_data_alignment
+ * @{
+ */
+
+#define DAC_ALIGN_R_12BIT ((uint32_t)0x00000000)
+#define DAC_ALIGN_L_12BIT ((uint32_t)0x00000004)
+#define DAC_ALIGN_R_8BIT ((uint32_t)0x00000008)
+#define IS_DAC_ALIGN(ALIGN) \
+ (((ALIGN) == DAC_ALIGN_R_12BIT) || ((ALIGN) == DAC_ALIGN_L_12BIT) || ((ALIGN) == DAC_ALIGN_R_8BIT))
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_wave_generation
+ * @{
+ */
+
+#define DAC_WAVE_NOISE ((uint32_t)0x00000040)
+#define DAC_WAVE_TRIANGLE ((uint32_t)0x00000080)
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NOISE) || ((WAVE) == DAC_WAVE_TRIANGLE))
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_data
+ * @{
+ */
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Functions
+ * @{
+ */
+
+void DAC_DeInit(void);
+void DAC_Init(DAC_InitType* DAC_InitStruct);
+void DAC_ClearStruct(DAC_InitType* DAC_InitStruct);
+void DAC_Enable(FunctionalState Cmd);
+
+void DAC_DmaEnable(FunctionalState Cmd);
+void DAC_SoftTrgEnable(FunctionalState Cmd);
+void DAC_SoftwareTrgEnable(FunctionalState Cmd);
+void DAC_WaveGenerationEnable(uint32_t DAC_Wave, FunctionalState Cmd);
+void DAC_SetChData(uint32_t DAC_Align, uint16_t Data);
+uint16_t DAC_GetOutputDataVal(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32G43X_DAC_H__ */
+ /**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_dbg.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_dbg.h
new file mode 100644
index 0000000000..8ba541746d
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_dbg.h
@@ -0,0 +1,124 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_dbg.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43x_DBG_H__
+#define __N32G43x_DBG_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DBG
+ * @{
+ */
+
+/** @addtogroup DBGMCU_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Exported_Constants
+ * @{
+ */
+
+#define DBG_SLEEP ((uint32_t)0x00000001)
+#define DBG_STOP ((uint32_t)0x00000002)
+#define DBG_STDBY ((uint32_t)0x00000004)
+#define DBG_IWDG_STOP ((uint32_t)0x00000100)
+#define DBG_WWDG_STOP ((uint32_t)0x00000200)
+#define DBG_TIM1_STOP ((uint32_t)0x00000400)
+#define DBG_TIM2_STOP ((uint32_t)0x00000800)
+#define DBG_TIM3_STOP ((uint32_t)0x00001000)
+#define DBG_TIM4_STOP ((uint32_t)0x00002000)
+#define DBG_CAN_STOP ((uint32_t)0x00004000)
+#define DBG_I2C1SMBUS_TIMEOUT ((uint32_t)0x00008000)
+#define DBG_I2C2SMBUS_TIMEOUT ((uint32_t)0x00010000)
+#define DBG_TIM8_STOP ((uint32_t)0x00020000)
+#define DBG_TIM5_STOP ((uint32_t)0x00040000)
+#define DBG_TIM6_STOP ((uint32_t)0x00080000)
+#define DBG_TIM7_STOP ((uint32_t)0x00100000)
+#define DBG_TIM9_STOP ((uint32_t)0x00200000)
+
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH)&0xFFC000F8) == 0x00) && ((PERIPH) != 0x00))
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Exported_Functions
+ * @{
+ */
+
+void GetUCID(uint8_t *UCIDbuf);
+void GetUID(uint8_t *UIDbuf);
+void GetDBGMCU_ID(uint8_t *DBGMCU_IDbuf);
+uint32_t DBG_GetRevNum(void);
+uint32_t DBG_GetDevNum(void);
+void DBG_ConfigPeriph(uint32_t DBG_Periph, FunctionalState Cmd);
+
+uint32_t DBG_GetFlashSize(void);
+uint32_t DBG_GetSramSize(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32G43x_DBG_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_dma.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_dma.h
new file mode 100644
index 0000000000..3f5a9f3093
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_dma.h
@@ -0,0 +1,469 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_dma.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_DMA_H__
+#define __N32G43X_DMA_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @{
+ */
+
+/** @addtogroup DMA_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief DMA Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t PeriphAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
+
+ uint32_t MemAddr; /*!< Specifies the memory base address for DMAy Channelx. */
+
+ uint32_t Direction; /*!< Specifies if the peripheral is the source or destination.
+ This parameter can be a value of @ref DMA_data_transfer_direction */
+
+ uint32_t BufSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
+ The data unit is equal to the configuration set in PeriphDataSize
+ or MemDataSize members depending in the transfer direction. */
+
+ uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register is incremented or not.
+ This parameter can be a value of @ref DMA_peripheral_incremented_mode */
+
+ uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
+ This parameter can be a value of @ref DMA_memory_incremented_mode */
+
+ uint32_t PeriphDataSize; /*!< Specifies the Peripheral data width.
+ This parameter can be a value of @ref DMA_peripheral_data_size */
+
+ uint32_t MemDataSize; /*!< Specifies the Memory data width.
+ This parameter can be a value of @ref DMA_memory_data_size */
+
+ uint32_t CircularMode; /*!< Specifies the operation mode of the DMAy Channelx.
+ This parameter can be a value of @ref DMA_circular_normal_mode.
+ @note: The circular buffer mode cannot be used if the memory-to-memory
+ data transfer is configured on the selected Channel */
+
+ uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
+ This parameter can be a value of @ref DMA_priority_level */
+
+ uint32_t Mem2Mem; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
+ This parameter can be a value of @ref DMA_memory_to_memory */
+} DMA_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Constants
+ * @{
+ */
+
+#define IS_DMA_ALL_PERIPH(PERIPH) \
+ (((PERIPH) == DMA_CH1) || ((PERIPH) == DMA_CH2) || ((PERIPH) == DMA_CH3) || ((PERIPH) == DMA_CH4) \
+ || ((PERIPH) == DMA_CH5) || ((PERIPH) == DMA_CH6) || ((PERIPH) == DMA_CH7) || ((PERIPH) == DMA_CH8))
+
+/** @addtogroup DMA_data_transfer_direction
+ * @{
+ */
+
+#define DMA_DIR_PERIPH_DST ((uint32_t)0x00000010)
+#define DMA_DIR_PERIPH_SRC ((uint32_t)0x00000000)
+#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PERIPH_DST) || ((DIR) == DMA_DIR_PERIPH_SRC))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_peripheral_incremented_mode
+ * @{
+ */
+
+#define DMA_PERIPH_INC_ENABLE ((uint32_t)0x00000040)
+#define DMA_PERIPH_INC_DISABLE ((uint32_t)0x00000000)
+#define IS_DMA_PERIPH_INC_STATE(STATE) (((STATE) == DMA_PERIPH_INC_ENABLE) || ((STATE) == DMA_PERIPH_INC_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_memory_incremented_mode
+ * @{
+ */
+
+#define DMA_MEM_INC_ENABLE ((uint32_t)0x00000080)
+#define DMA_MEM_INC_DISABLE ((uint32_t)0x00000000)
+#define IS_DMA_MEM_INC_STATE(STATE) (((STATE) == DMA_MEM_INC_ENABLE) || ((STATE) == DMA_MEM_INC_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_peripheral_data_size
+ * @{
+ */
+
+#define DMA_PERIPH_DATA_SIZE_BYTE ((uint32_t)0x00000000)
+#define DMA_PERIPH_DATA_SIZE_HALFWORD ((uint32_t)0x00000100)
+#define DMA_PERIPH_DATA_SIZE_WORD ((uint32_t)0x00000200)
+#define IS_DMA_PERIPH_DATA_SIZE(SIZE) \
+ (((SIZE) == DMA_PERIPH_DATA_SIZE_BYTE) || ((SIZE) == DMA_PERIPH_DATA_SIZE_HALFWORD) \
+ || ((SIZE) == DMA_PERIPH_DATA_SIZE_WORD))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_memory_data_size
+ * @{
+ */
+
+#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
+#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
+#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) \
+ (((SIZE) == DMA_MemoryDataSize_Byte) || ((SIZE) == DMA_MemoryDataSize_HalfWord) \
+ || ((SIZE) == DMA_MemoryDataSize_Word))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_circular_normal_mode
+ * @{
+ */
+
+#define DMA_MODE_CIRCULAR ((uint32_t)0x00000020)
+#define DMA_MODE_NORMAL ((uint32_t)0x00000000)
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_MODE_CIRCULAR) || ((MODE) == DMA_MODE_NORMAL))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_priority_level
+ * @{
+ */
+
+#define DMA_PRIORITY_VERY_HIGH ((uint32_t)0x00003000)
+#define DMA_PRIORITY_HIGH ((uint32_t)0x00002000)
+#define DMA_PRIORITY_MEDIUM ((uint32_t)0x00001000)
+#define DMA_PRIORITY_LOW ((uint32_t)0x00000000)
+#define IS_DMA_PRIORITY(PRIORITY) \
+ (((PRIORITY) == DMA_PRIORITY_VERY_HIGH) || ((PRIORITY) == DMA_PRIORITY_HIGH) \
+ || ((PRIORITY) == DMA_PRIORITY_MEDIUM) || ((PRIORITY) == DMA_PRIORITY_LOW))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_memory_to_memory
+ * @{
+ */
+
+#define DMA_M2M_ENABLE ((uint32_t)0x00004000)
+#define DMA_M2M_DISABLE ((uint32_t)0x00000000)
+#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_ENABLE) || ((STATE) == DMA_M2M_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_interrupts_definition
+ * @{
+ */
+
+#define DMA_INT_TXC ((uint32_t)0x00000002)
+#define DMA_INT_HTX ((uint32_t)0x00000004)
+#define DMA_INT_ERR ((uint32_t)0x00000008)
+#define IS_DMA_CONFIG_INT(IT) ((((IT)&0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
+
+#define DMA_INT_GLB1 ((uint32_t)0x00000001)
+#define DMA_INT_TXC1 ((uint32_t)0x00000002)
+#define DMA_INT_HTX1 ((uint32_t)0x00000004)
+#define DMA_INT_ERR1 ((uint32_t)0x00000008)
+#define DMA_INT_GLB2 ((uint32_t)0x00000010)
+#define DMA_INT_TXC2 ((uint32_t)0x00000020)
+#define DMA_INT_HTX2 ((uint32_t)0x00000040)
+#define DMA_INT_ERR2 ((uint32_t)0x00000080)
+#define DMA_INT_GLB3 ((uint32_t)0x00000100)
+#define DMA_INT_TXC3 ((uint32_t)0x00000200)
+#define DMA_INT_HTX3 ((uint32_t)0x00000400)
+#define DMA_INT_ERR3 ((uint32_t)0x00000800)
+#define DMA_INT_GLB4 ((uint32_t)0x00001000)
+#define DMA_INT_TXC4 ((uint32_t)0x00002000)
+#define DMA_INT_HTX4 ((uint32_t)0x00004000)
+#define DMA_INT_ERR4 ((uint32_t)0x00008000)
+#define DMA_INT_GLB5 ((uint32_t)0x00010000)
+#define DMA_INT_TXC5 ((uint32_t)0x00020000)
+#define DMA_INT_HTX5 ((uint32_t)0x00040000)
+#define DMA_INT_ERR5 ((uint32_t)0x00080000)
+#define DMA_INT_GLB6 ((uint32_t)0x00100000)
+#define DMA_INT_TXC6 ((uint32_t)0x00200000)
+#define DMA_INT_HTX6 ((uint32_t)0x00400000)
+#define DMA_INT_ERR6 ((uint32_t)0x00800000)
+#define DMA_INT_GLB7 ((uint32_t)0x01000000)
+#define DMA_INT_TXC7 ((uint32_t)0x02000000)
+#define DMA_INT_HTX7 ((uint32_t)0x04000000)
+#define DMA_INT_ERR7 ((uint32_t)0x08000000)
+#define DMA_INT_GLB8 ((uint32_t)0x10000000)
+#define DMA_INT_TXC8 ((uint32_t)0x20000000)
+#define DMA_INT_HTX8 ((uint32_t)0x40000000)
+#define DMA_INT_ERR8 ((uint32_t)0x80000000)
+
+
+#define IS_DMA_CLR_INT(IT) ((IT) != 0x00)
+
+#define IS_DMA_GET_IT(IT) \
+ (((IT) == DMA_INT_GLB1) || ((IT) == DMA_INT_TXC1) || ((IT) == DMA_INT_HTX1) || ((IT) == DMA_INT_ERR1) \
+ || ((IT) == DMA_INT_GLB2) || ((IT) == DMA_INT_TXC2) || ((IT) == DMA_INT_HTX2) || ((IT) == DMA_INT_ERR2) \
+ || ((IT) == DMA_INT_GLB3) || ((IT) == DMA_INT_TXC3) || ((IT) == DMA_INT_HTX3) || ((IT) == DMA_INT_ERR3) \
+ || ((IT) == DMA_INT_GLB4) || ((IT) == DMA_INT_TXC4) || ((IT) == DMA_INT_HTX4) || ((IT) == DMA_INT_ERR4) \
+ || ((IT) == DMA_INT_GLB5) || ((IT) == DMA_INT_TXC5) || ((IT) == DMA_INT_HTX5) || ((IT) == DMA_INT_ERR5) \
+ || ((IT) == DMA_INT_GLB6) || ((IT) == DMA_INT_TXC6) || ((IT) == DMA_INT_HTX6) || ((IT) == DMA_INT_ERR6) \
+ || ((IT) == DMA_INT_GLB7) || ((IT) == DMA_INT_TXC7) || ((IT) == DMA_INT_HTX7) || ((IT) == DMA_INT_ERR7) \
+ || ((IT) == DMA_INT_GLB8) || ((IT) == DMA_INT_TXC8) || ((IT) == DMA_INT_HTX8) || ((IT) == DMA_INT_ERR8))
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_flags_definition
+ * @{
+ */
+#define DMA_FLAG_GL1 ((uint32_t)0x00000001)
+#define DMA_FLAG_TC1 ((uint32_t)0x00000002)
+#define DMA_FLAG_HT1 ((uint32_t)0x00000004)
+#define DMA_FLAG_TE1 ((uint32_t)0x00000008)
+#define DMA_FLAG_GL2 ((uint32_t)0x00000010)
+#define DMA_FLAG_TC2 ((uint32_t)0x00000020)
+#define DMA_FLAG_HT2 ((uint32_t)0x00000040)
+#define DMA_FLAG_TE2 ((uint32_t)0x00000080)
+#define DMA_FLAG_GL3 ((uint32_t)0x00000100)
+#define DMA_FLAG_TC3 ((uint32_t)0x00000200)
+#define DMA_FLAG_HT3 ((uint32_t)0x00000400)
+#define DMA_FLAG_TE3 ((uint32_t)0x00000800)
+#define DMA_FLAG_GL4 ((uint32_t)0x00001000)
+#define DMA_FLAG_TC4 ((uint32_t)0x00002000)
+#define DMA_FLAG_HT4 ((uint32_t)0x00004000)
+#define DMA_FLAG_TE4 ((uint32_t)0x00008000)
+#define DMA_FLAG_GL5 ((uint32_t)0x00010000)
+#define DMA_FLAG_TC5 ((uint32_t)0x00020000)
+#define DMA_FLAG_HT5 ((uint32_t)0x00040000)
+#define DMA_FLAG_TE5 ((uint32_t)0x00080000)
+#define DMA_FLAG_GL6 ((uint32_t)0x00100000)
+#define DMA_FLAG_TC6 ((uint32_t)0x00200000)
+#define DMA_FLAG_HT6 ((uint32_t)0x00400000)
+#define DMA_FLAG_TE6 ((uint32_t)0x00800000)
+#define DMA_FLAG_GL7 ((uint32_t)0x01000000)
+#define DMA_FLAG_TC7 ((uint32_t)0x02000000)
+#define DMA_FLAG_HT7 ((uint32_t)0x04000000)
+#define DMA_FLAG_TE7 ((uint32_t)0x08000000)
+#define DMA_FLAG_GL8 ((uint32_t)0x10000000)
+#define DMA_FLAG_TC8 ((uint32_t)0x20000000)
+#define DMA_FLAG_HT8 ((uint32_t)0x40000000)
+#define DMA_FLAG_TE8 ((uint32_t)0x80000000)
+
+#define IS_DMA_CLEAR_FLAG(FLAG) ((FLAG) != 0x00)
+
+#define IS_DMA_GET_FLAG(FLAG) \
+ (((FLAG) == DMA_FLAG_GL1) || ((FLAG) == DMA_FLAG_TC1) || ((FLAG) == DMA_FLAG_HT1) || ((FLAG) == DMA_FLAG_TE1) \
+ || ((FLAG) == DMA_FLAG_GL2) || ((FLAG) == DMA_FLAG_TC2) || ((FLAG) == DMA_FLAG_HT2) \
+ || ((FLAG) == DMA_FLAG_TE2) || ((FLAG) == DMA_FLAG_GL3) || ((FLAG) == DMA_FLAG_TC3) \
+ || ((FLAG) == DMA_FLAG_HT3) || ((FLAG) == DMA_FLAG_TE3) || ((FLAG) == DMA_FLAG_GL4) \
+ || ((FLAG) == DMA_FLAG_TC4) || ((FLAG) == DMA_FLAG_HT4) || ((FLAG) == DMA_FLAG_TE4) \
+ || ((FLAG) == DMA_FLAG_GL5) || ((FLAG) == DMA_FLAG_TC5) || ((FLAG) == DMA_FLAG_HT5) \
+ || ((FLAG) == DMA_FLAG_TE5) || ((FLAG) == DMA_FLAG_GL6) || ((FLAG) == DMA_FLAG_TC6) \
+ || ((FLAG) == DMA_FLAG_HT6) || ((FLAG) == DMA_FLAG_TE6) || ((FLAG) == DMA_FLAG_GL7) \
+ || ((FLAG) == DMA_FLAG_TC7) || ((FLAG) == DMA_FLAG_HT7) || ((FLAG) == DMA_FLAG_TE7) \
+ || ((FLAG) == DMA_FLAG_GL8) || ((FLAG) == DMA_FLAG_TC8) || ((FLAG) == DMA_FLAG_HT8) \
+ || ((FLAG) == DMA_FLAG_TE8))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Buffer_Size
+ * @{
+ */
+
+#define IS_DMA_BUF_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_remap_request_definition
+ * @{
+ */
+#define DMA_REMAP_ADC1 ((uint32_t)0x00000000)
+#define DMA_REMAP_USART1_TX ((uint32_t)0x00000001)
+#define DMA_REMAP_USART1_RX ((uint32_t)0x00000002)
+#define DMA_REMAP_USART2_TX ((uint32_t)0x00000003)
+#define DMA_REMAP_USART2_RX ((uint32_t)0x00000004)
+#define DMA_REMAP_USART3_TX ((uint32_t)0x00000005)
+#define DMA_REMAP_USART3_RX ((uint32_t)0x00000006)
+#define DMA_REMAP_UART4_TX ((uint32_t)0x00000007)
+#define DMA_REMAP_UART4_RX ((uint32_t)0x00000008)
+#define DMA_REMAP_UART5_TX ((uint32_t)0x00000009)
+#define DMA_REMAP_UART5_RX ((uint32_t)0x0000000A)
+#define DMA_REMAP_LPUART_TX ((uint32_t)0x0000000B)
+#define DMA_REMAP_LPUART_RX ((uint32_t)0x0000000C)
+#define DMA_REMAP_SPI1_TX ((uint32_t)0x0000000D)
+#define DMA_REMAP_SPI1_RX ((uint32_t)0x0000000E)
+#define DMA_REMAP_SPI2_TX ((uint32_t)0x0000000F)
+#define DMA_REMAP_SPI2_RX ((uint32_t)0x00000010)
+#define DMA_REMAP_I2C1_TX ((uint32_t)0x00000011)
+#define DMA_REMAP_I2C1_RX ((uint32_t)0x00000012)
+#define DMA_REMAP_I2C2_TX ((uint32_t)0x00000013)
+#define DMA_REMAP_I2C2_RX ((uint32_t)0x00000014)
+#define DMA_REMAP_DAC1 ((uint32_t)0x00000015)
+#define DMA_REMAP_TIM1_CH1 ((uint32_t)0x00000016)
+#define DMA_REMAP_TIM1_CH2 ((uint32_t)0x00000017)
+#define DMA_REMAP_TIM1_CH3 ((uint32_t)0x00000018)
+#define DMA_REMAP_TIM1_CH4 ((uint32_t)0x00000019)
+#define DMA_REMAP_TIM1_COM ((uint32_t)0x0000001A)
+#define DMA_REMAP_TIM1_UP ((uint32_t)0x0000001B)
+#define DMA_REMAP_TIM1_TRIG ((uint32_t)0x0000001C)
+#define DMA_REMAP_TIM2_CH1 ((uint32_t)0x0000001D)
+#define DMA_REMAP_TIM2_CH2 ((uint32_t)0x0000001E)
+#define DMA_REMAP_TIM2_CH3 ((uint32_t)0x0000001F)
+#define DMA_REMAP_TIM2_CH4 ((uint32_t)0x00000020)
+#define DMA_REMAP_TIM2_UP ((uint32_t)0x00000021)
+#define DMA_REMAP_TIM3_CH1 ((uint32_t)0x00000022)
+#define DMA_REMAP_TIM3_CH3 ((uint32_t)0x00000023)
+#define DMA_REMAP_TIM3_CH4 ((uint32_t)0x00000024)
+#define DMA_REMAP_TIM3_UP ((uint32_t)0x00000025)
+#define DMA_REMAP_TIM3_TRIG ((uint32_t)0x00000026)
+#define DMA_REMAP_TIM4_CH1 ((uint32_t)0x00000027)
+#define DMA_REMAP_TIM4_CH2 ((uint32_t)0x00000028)
+#define DMA_REMAP_TIM4_CH3 ((uint32_t)0x00000029)
+#define DMA_REMAP_TIM4_UP ((uint32_t)0x0000002A)
+#define DMA_REMAP_TIM5_CH1 ((uint32_t)0x0000002B)
+#define DMA_REMAP_TIM5_CH2 ((uint32_t)0x0000002C)
+#define DMA_REMAP_TIM5_CH3 ((uint32_t)0x0000002D)
+#define DMA_REMAP_TIM5_CH4 ((uint32_t)0x0000002E)
+#define DMA_REMAP_TIM5_UP ((uint32_t)0x0000002F)
+#define DMA_REMAP_TIM5_TRIG ((uint32_t)0x00000030)
+#define DMA_REMAP_TIM6_UP ((uint32_t)0x00000031)
+#define DMA_REMAP_TIM7_UP ((uint32_t)0x00000032)
+#define DMA_REMAP_TIM8_CH1 ((uint32_t)0x00000033)
+#define DMA_REMAP_TIM8_CH2 ((uint32_t)0x00000034)
+#define DMA_REMAP_TIM8_CH3 ((uint32_t)0x00000035)
+#define DMA_REMAP_TIM8_CH4 ((uint32_t)0x00000036)
+#define DMA_REMAP_TIM8_COM ((uint32_t)0x00000037)
+#define DMA_REMAP_TIM8_UP ((uint32_t)0x00000038)
+#define DMA_REMAP_TIM8_TRIG ((uint32_t)0x00000039)
+#define DMA_REMAP_TIM9_CH1 ((uint32_t)0x0000003A)
+#define DMA_REMAP_TIM9_TRIG ((uint32_t)0x0000003B)
+#define DMA_REMAP_TIM9_CH3 ((uint32_t)0x0000003C)
+#define DMA_REMAP_TIM9_CH4 ((uint32_t)0x0000003D)
+#define DMA_REMAP_TIM9_UP ((uint32_t)0x0000003E)
+
+
+#define IS_DMA_REMAP(FLAG) \
+ (((FLAG) == DMA_REMAP_ADC1) || ((FLAG) == DMA_REMAP_USART1_TX) || ((FLAG) == DMA_REMAP_USART1_RX) \
+ || ((FLAG) == DMA_REMAP_USART2_TX) || ((FLAG) == DMA_REMAP_USART2_RX) || ((FLAG) == DMA_REMAP_USART3_TX) \
+ || ((FLAG) == DMA_REMAP_USART3_RX) || ((FLAG) == DMA_REMAP_UART4_TX) || ((FLAG) == DMA_REMAP_UART4_RX) \
+ || ((FLAG) == DMA_REMAP_UART5_TX) || ((FLAG) == DMA_REMAP_UART5_RX) || ((FLAG) == DMA_REMAP_LPUART_TX) \
+ || ((FLAG) == DMA_REMAP_LPUART_RX) || ((FLAG) == DMA_REMAP_SPI1_TX) || ((FLAG) == DMA_REMAP_SPI1_RX) \
+ || ((FLAG) == DMA_REMAP_SPI2_TX) || ((FLAG) == DMA_REMAP_SPI2_RX) || ((FLAG) == DMA_REMAP_I2C1_TX) \
+ || ((FLAG) == DMA_REMAP_I2C1_RX) || ((FLAG) == DMA_REMAP_I2C2_TX) || ((FLAG) == DMA_REMAP_I2C2_RX) \
+ || ((FLAG) == DMA_REMAP_DAC1) || ((FLAG) == DMA_REMAP_TIM1_CH1) || ((FLAG) == DMA_REMAP_TIM1_CH2) \
+ || ((FLAG) == DMA_REMAP_TIM1_CH3) || ((FLAG) == DMA_REMAP_TIM1_CH4) || ((FLAG) == DMA_REMAP_TIM1_COM) \
+ || ((FLAG) == DMA_REMAP_TIM1_UP) || ((FLAG) == DMA_REMAP_TIM1_TRIG)|| ((FLAG) == DMA_REMAP_TIM2_CH1) \
+ || ((FLAG) == DMA_REMAP_TIM2_CH2) || ((FLAG) == DMA_REMAP_TIM2_CH3) || ((FLAG) == DMA_REMAP_TIM2_CH4) \
+ || ((FLAG) == DMA_REMAP_TIM2_UP) || ((FLAG) == DMA_REMAP_TIM3_CH1) || ((FLAG) == DMA_REMAP_TIM3_CH3) \
+ || ((FLAG) == DMA_REMAP_TIM3_CH4) || ((FLAG) == DMA_REMAP_TIM3_UP) || ((FLAG) == DMA_REMAP_TIM3_TRIG) \
+ || ((FLAG) == DMA_REMAP_TIM4_CH1) || ((FLAG) == DMA_REMAP_TIM4_CH2) || ((FLAG) == DMA_REMAP_TIM4_CH3) \
+ || ((FLAG) == DMA_REMAP_TIM4_UP) || ((FLAG) == DMA_REMAP_TIM5_CH1) || ((FLAG) == DMA_REMAP_TIM5_CH2) \
+ || ((FLAG) == DMA_REMAP_TIM5_CH3) || ((FLAG) == DMA_REMAP_TIM5_CH4) || ((FLAG) == DMA_REMAP_TIM5_UP) \
+ || ((FLAG) == DMA_REMAP_TIM5_TRIG)|| ((FLAG) == DMA_REMAP_TIM6_UP) || ((FLAG) == DMA_REMAP_TIM7_UP) \
+ || ((FLAG) == DMA_REMAP_TIM8_CH1) || ((FLAG) == DMA_REMAP_TIM8_CH2) || ((FLAG) == DMA_REMAP_TIM8_CH3) \
+ || ((FLAG) == DMA_REMAP_TIM8_CH4) || ((FLAG) == DMA_REMAP_TIM8_COM) || ((FLAG) == DMA_REMAP_TIM8_UP) \
+ || ((FLAG) == DMA_REMAP_TIM8_TRIG)|| ((FLAG) == DMA_REMAP_TIM9_CH1) || ((FLAG) == DMA_REMAP_TIM9_TRIG) \
+ || ((FLAG) == DMA_REMAP_TIM9_CH3) || ((FLAG) == DMA_REMAP_TIM9_CH4) || ((FLAG) == DMA_REMAP_TIM9_UP))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Functions
+ * @{
+ */
+
+void DMA_DeInit(DMA_ChannelType* DMAChx);
+void DMA_Init(DMA_ChannelType* DMAChx, DMA_InitType* DMA_InitParam);
+void DMA_StructInit(DMA_InitType* DMA_InitParam);
+void DMA_EnableChannel(DMA_ChannelType* DMAChx, FunctionalState Cmd);
+void DMA_ConfigInt(DMA_ChannelType* DMAChx, uint32_t DMAInt, FunctionalState Cmd);
+void DMA_SetCurrDataCounter(DMA_ChannelType* DMAChx, uint16_t DataNumber);
+uint16_t DMA_GetCurrDataCounter(DMA_ChannelType* DMAChx);
+FlagStatus DMA_GetFlagStatus(uint32_t DMAFlag, DMA_Module* DMAy);
+void DMA_ClearFlag(uint32_t DMAFlag, DMA_Module* DMAy);
+INTStatus DMA_GetIntStatus(uint32_t DMA_IT, DMA_Module* DMAy);
+void DMA_ClrIntPendingBit(uint32_t DMA_IT, DMA_Module* DMAy);
+void DMA_RequestRemap(uint32_t DMA_REMAP, DMA_Module* DMAy, DMA_ChannelType* DMAChx, FunctionalState Cmd);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32G43X_DMA_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_exti.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_exti.h
new file mode 100644
index 0000000000..32233c33ab
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_exti.h
@@ -0,0 +1,232 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_exti.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_EXTI_H__
+#define __N32G43X_EXTI_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup EXTI
+ * @{
+ */
+
+/** @addtogroup EXTI_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief EXTI mode enumeration
+ */
+
+typedef enum
+{
+ EXTI_Mode_Interrupt = 0x00,
+ EXTI_Mode_Event = 0x04
+} EXTI_ModeType;
+
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
+
+/**
+ * @brief EXTI Trigger enumeration
+ */
+
+typedef enum
+{
+ EXTI_Trigger_Rising = 0x08,
+ EXTI_Trigger_Falling = 0x0C,
+ EXTI_Trigger_Rising_Falling = 0x10
+} EXTI_TriggerType;
+
+#define IS_EXTI_TRIGGER(TRIGGER) \
+ (((TRIGGER) == EXTI_Trigger_Rising) || ((TRIGGER) == EXTI_Trigger_Falling) \
+ || ((TRIGGER) == EXTI_Trigger_Rising_Falling))
+/**
+ * @brief EXTI Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
+ This parameter can be any combination of @ref EXTI_Lines */
+
+ EXTI_ModeType EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
+ This parameter can be a value of @ref EXTI_ModeType */
+
+ EXTI_TriggerType EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+ This parameter can be a value of @ref EXTI_ModeType */
+
+ FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
+ This parameter can be set either to ENABLE or DISABLE */
+} EXTI_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup EXTI_Lines
+ * @{
+ */
+
+#define EXTI_LINE0 ((uint32_t)0x00001) /*!< External interrupt line 0 */
+#define EXTI_LINE1 ((uint32_t)0x00002) /*!< External interrupt line 1 */
+#define EXTI_LINE2 ((uint32_t)0x00004) /*!< External interrupt line 2 */
+#define EXTI_LINE3 ((uint32_t)0x00008) /*!< External interrupt line 3 */
+#define EXTI_LINE4 ((uint32_t)0x00010) /*!< External interrupt line 4 */
+#define EXTI_LINE5 ((uint32_t)0x00020) /*!< External interrupt line 5 */
+#define EXTI_LINE6 ((uint32_t)0x00040) /*!< External interrupt line 6 */
+#define EXTI_LINE7 ((uint32_t)0x00080) /*!< External interrupt line 7 */
+#define EXTI_LINE8 ((uint32_t)0x00100) /*!< External interrupt line 8 */
+#define EXTI_LINE9 ((uint32_t)0x00200) /*!< External interrupt line 9 */
+#define EXTI_LINE10 ((uint32_t)0x00400) /*!< External interrupt line 10 */
+#define EXTI_LINE11 ((uint32_t)0x00800) /*!< External interrupt line 11 */
+#define EXTI_LINE12 ((uint32_t)0x01000) /*!< External interrupt line 12 */
+#define EXTI_LINE13 ((uint32_t)0x02000) /*!< External interrupt line 13 */
+#define EXTI_LINE14 ((uint32_t)0x04000) /*!< External interrupt line 14 */
+#define EXTI_LINE15 ((uint32_t)0x08000) /*!< External interrupt line 15 */
+#define EXTI_LINE16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */
+#define EXTI_LINE17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the USB Device/USB OTG FS Wakeup from suspend event */
+#define EXTI_LINE18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the RTC Alarm event */
+#define EXTI_LINE19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the RTC Time stamp event */
+#define EXTI_LINE20 ((uint32_t)0x100000) /*!< External interrupt line 20 Connected to the RTC Wakeup event */
+#define EXTI_LINE21 ((uint32_t)0x200000) /*!< External interrupt line 21 Connected to the COMP1 Global interrupt */
+#define EXTI_LINE22 ((uint32_t)0x400000) /*!< External interrupt line 22 Connected to the COMP2 Global interrupt */
+#define EXTI_LINE23 ((uint32_t)0x800000) /*!< External interrupt line 23 Connected to the LPUART Global interrupt */
+#define EXTI_LINE24 ((uint32_t)0x1000000) /*!< External interrupt line 24 Connected to the LPTIM Global interrupt */
+#define EXTI_LINE25 ((uint32_t)0x2000000) /*!< External interrupt line 25 Connected to the TSC Global interrupt */
+
+
+
+
+
+
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xF0000000) == 0x00) && ((LINE) != (uint16_t)0x00))
+#define IS_GET_EXTI_LINE(LINE) \
+ (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) \
+ || ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) \
+ || ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) \
+ || ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) \
+ || ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) \
+ || ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) \
+ || ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25))
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_TSSEL_Line
+ * @{
+ */
+#define EXTI_TSSEL_LINE_MASK ((uint32_t)0x00000)
+#define EXTI_TSSEL_LINE0 ((uint32_t)0x00000) /*!< External interrupt line 0 */
+#define EXTI_TSSEL_LINE1 ((uint32_t)0x00001) /*!< External interrupt line 1 */
+#define EXTI_TSSEL_LINE2 ((uint32_t)0x00002) /*!< External interrupt line 2 */
+#define EXTI_TSSEL_LINE3 ((uint32_t)0x00003) /*!< External interrupt line 3 */
+#define EXTI_TSSEL_LINE4 ((uint32_t)0x00004) /*!< External interrupt line 4 */
+#define EXTI_TSSEL_LINE5 ((uint32_t)0x00005) /*!< External interrupt line 5 */
+#define EXTI_TSSEL_LINE6 ((uint32_t)0x00006) /*!< External interrupt line 6 */
+#define EXTI_TSSEL_LINE7 ((uint32_t)0x00007) /*!< External interrupt line 7 */
+#define EXTI_TSSEL_LINE8 ((uint32_t)0x00008) /*!< External interrupt line 8 */
+#define EXTI_TSSEL_LINE9 ((uint32_t)0x00009) /*!< External interrupt line 9 */
+#define EXTI_TSSEL_LINE10 ((uint32_t)0x0000A) /*!< External interrupt line 10 */
+#define EXTI_TSSEL_LINE11 ((uint32_t)0x0000B) /*!< External interrupt line 11 */
+#define EXTI_TSSEL_LINE12 ((uint32_t)0x0000C) /*!< External interrupt line 12 */
+#define EXTI_TSSEL_LINE13 ((uint32_t)0x0000D) /*!< External interrupt line 13 */
+#define EXTI_TSSEL_LINE14 ((uint32_t)0x0000E) /*!< External interrupt line 14 */
+#define EXTI_TSSEL_LINE15 ((uint32_t)0x0000F) /*!< External interrupt line 15 */
+
+#define IS_EXTI_TSSEL_LINE(LINE) \
+ (((LINE) == EXTI_TSSEL_LINE0) || ((LINE) == EXTI_TSSEL_LINE1) || ((LINE) == EXTI_TSSEL_LINE2) \
+ || ((LINE) == EXTI_TSSEL_LINE3) || ((LINE) == EXTI_TSSEL_LINE4) || ((LINE) == EXTI_TSSEL_LINE5) \
+ || ((LINE) == EXTI_TSSEL_LINE6) || ((LINE) == EXTI_TSSEL_LINE7) || ((LINE) == EXTI_TSSEL_LINE8) \
+ || ((LINE) == EXTI_TSSEL_LINE9) || ((LINE) == EXTI_TSSEL_LINE10) || ((LINE) == EXTI_TSSEL_LINE11) \
+ || ((LINE) == EXTI_TSSEL_LINE12) || ((LINE) == EXTI_TSSEL_LINE13) || ((LINE) == EXTI_TSSEL_LINE14) \
+ || ((LINE) == EXTI_TSSEL_LINE15))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Exported_Functions
+ * @{
+ */
+
+void EXTI_DeInit(void);
+void EXTI_InitPeripheral(EXTI_InitType* EXTI_InitStruct);
+void EXTI_InitStruct(EXTI_InitType* EXTI_InitStruct);
+void EXTI_TriggerSWInt(uint32_t EXTI_Line);
+FlagStatus EXTI_GetStatusFlag(uint32_t EXTI_Line);
+void EXTI_ClrStatusFlag(uint32_t EXTI_Line);
+INTStatus EXTI_GetITStatus(uint32_t EXTI_Line);
+void EXTI_ClrITPendBit(uint32_t EXTI_Line);
+void EXTI_RTCTimeStampSel(uint32_t EXTI_TSSEL_Line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32G43X_EXTI_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_flash.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_flash.h
new file mode 100644
index 0000000000..48d8c3949a
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_flash.h
@@ -0,0 +1,513 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_flash.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_FLASH_H__
+#define __N32G43X_FLASH_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @{
+ */
+
+/** @addtogroup FLASH_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief FLASH Status
+ */
+
+typedef enum
+{
+ FLASH_BUSY = 1,
+ FLASH_RESERVED,
+ FLASH_ERR_PG,
+ FLASH_ERR_PV,
+ FLASH_ERR_WRP,
+ FLASH_COMPL,
+ FLASH_ERR_EV,
+ FLASH_ERR_RDP2,
+ FLASH_ERR_ADD,
+ FLASH_TIMEOUT
+} FLASH_STS;
+
+/**
+ * @brief FLASH_SMPSEL
+ */
+
+typedef enum
+{
+ FLASH_SMP1 = 0,
+ FLASH_SMP2
+} FLASH_SMPSEL;
+
+/**
+ * @brief FLASH_HSICLOCK
+ */
+
+typedef enum
+{
+ FLASH_HSICLOCK_ENABLE = 0,
+ FLASH_HSICLOCK_DISABLE
+} FLASH_HSICLOCK;
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup Flash_Latency
+ * @{
+ */
+
+#define FLASH_LATENCY_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
+#define FLASH_LATENCY_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */
+#define FLASH_LATENCY_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */
+#define FLASH_LATENCY_3 ((uint32_t)0x00000003) /*!< FLASH Three Latency cycles */
+#define IS_FLASH_LATENCY(LATENCY) \
+ (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || ((LATENCY) == FLASH_LATENCY_2) \
+ || ((LATENCY) == FLASH_LATENCY_3))
+/**
+ * @}
+ */
+
+/** @addtogroup Prefetch_Buffer_Enable_Disable
+ * @{
+ */
+
+#define FLASH_PrefetchBuf_EN ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */
+#define FLASH_PrefetchBuf_DIS ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */
+#define IS_FLASH_PREFETCHBUF_STATE(STATE) (((STATE) == FLASH_PrefetchBuf_EN) || ((STATE) == FLASH_PrefetchBuf_DIS))
+/**
+ * @}
+ */
+
+/** @addtogroup iCache_Enable_Disable
+ * @{
+ */
+
+#define FLASH_iCache_EN ((uint32_t)0x00000080) /*!< FLASH iCache Enable */
+#define FLASH_iCache_DIS ((uint32_t)0x00000000) /*!< FLASH iCache Disable */
+#define IS_FLASH_ICACHE_STATE(STATE) (((STATE) == FLASH_iCache_EN) || ((STATE) == FLASH_iCache_DIS))
+/**
+ * @}
+ */
+
+/** @addtogroup Low Voltage Mode
+ * @{
+ */
+
+#define FLASH_LVM_EN ((uint32_t)0x00000200) /*!< FLASH Low Voltage Mode Enable */
+#define FLASH_LVM_DIS ((uint32_t)0x00000000) /*!< FLASH Low Voltage Mode Disable */
+#define IS_FLASH_LVM(STATE) (((STATE) == FLASH_LVM_EN) || ((STATE) == FLASH_LVM_DIS))
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH Sleep Mode
+ * @{
+ */
+
+#define FLASH_SLM_EN ((uint32_t)0x00000800) /*!< FLASH Sleep Mode Enable */
+#define FLASH_SLM_DIS ((uint32_t)0x00000000) /*!< FLASH Sleep Mode Disable */
+#define IS_FLASH_SLM(STATE) (((STATE) == FLASH_SLM_EN) || ((STATE) == FLASH_SLM_DIS))
+/**
+ * @}
+ */
+
+/** @addtogroup SMPSEL_SMP1_SMP2
+ * @{
+ */
+
+#define FLASH_SMPSEL_SMP1 ((uint32_t)0x00000000) /*!< FLASH SMPSEL SMP1 */
+#define FLASH_SMPSEL_SMP2 ((uint32_t)0x00000100) /*!< FLASH SMPSEL SMP2 */
+#define IS_FLASH_SMPSEL_STATE(STATE) (((STATE) == FLASH_SMPSEL_SMP1) || ((STATE) == FLASH_SMPSEL_SMP2))
+/**
+ * @}
+ */
+
+/* Values to be used with N32G43x devices */
+#define FLASH_WRP_Pages0to1 \
+ ((uint32_t)0x00000001) /*!< N32G43x devices: \
+ Write protection of page 0 to 1 */
+#define FLASH_WRP_Pages2to3 \
+ ((uint32_t)0x00000002) /*!< N32G43x devices: \
+ Write protection of page 2 to 3 */
+#define FLASH_WRP_Pages4to5 \
+ ((uint32_t)0x00000004) /*!< N32G43x devices: \
+ Write protection of page 4 to 5 */
+#define FLASH_WRP_Pages6to7 \
+ ((uint32_t)0x00000008) /*!< N32G43x devices: \
+ Write protection of page 6 to 7 */
+#define FLASH_WRP_Pages8to9 \
+ ((uint32_t)0x00000010) /*!< N32G43x devices: \
+ Write protection of page 8 to 9 */
+#define FLASH_WRP_Pages10to11 \
+ ((uint32_t)0x00000020) /*!< N32G43x devices: \
+ Write protection of page 10 to 11 */
+#define FLASH_WRP_Pages12to13 \
+ ((uint32_t)0x00000040) /*!< N32G43x devices: \
+ Write protection of page 12 to 13 */
+#define FLASH_WRP_Pages14to15 \
+ ((uint32_t)0x00000080) /*!< N32G43x devices: \
+ Write protection of page 14 to 15 */
+#define FLASH_WRP_Pages16to17 \
+ ((uint32_t)0x00000100) /*!< N32G43x devices: \
+ Write protection of page 16 to 17 */
+#define FLASH_WRP_Pages18to19 \
+ ((uint32_t)0x00000200) /*!< N32G43x devices: \
+ Write protection of page 18 to 19 */
+#define FLASH_WRP_Pages20to21 \
+ ((uint32_t)0x00000400) /*!< N32G43x devices: \
+ Write protection of page 20 to 21 */
+#define FLASH_WRP_Pages22to23 \
+ ((uint32_t)0x00000800) /*!< N32G43x devices: \
+ Write protection of page 22 to 23 */
+#define FLASH_WRP_Pages24to25 \
+ ((uint32_t)0x00001000) /*!< N32G43x devices: \
+ Write protection of page 24 to 25 */
+#define FLASH_WRP_Pages26to27 \
+ ((uint32_t)0x00002000) /*!< N32G43x devices: \
+ Write protection of page 26 to 27 */
+#define FLASH_WRP_Pages28to29 \
+ ((uint32_t)0x00004000) /*!< N32G43x devices: \
+ Write protection of page 28 to 29 */
+#define FLASH_WRP_Pages30to31 \
+ ((uint32_t)0x00008000) /*!< N32G43x devices: \
+ Write protection of page 30 to 31 */
+#define FLASH_WRP_Pages32to33 \
+ ((uint32_t)0x00010000) /*!< N32G43x devices: \
+ Write protection of page 32 to 33 */
+#define FLASH_WRP_Pages34to35 \
+ ((uint32_t)0x00020000) /*!< N32G43x devices: \
+ Write protection of page 34 to 35 */
+#define FLASH_WRP_Pages36to37 \
+ ((uint32_t)0x00040000) /*!< N32G43x devices: \
+ Write protection of page 36 to 37 */
+#define FLASH_WRP_Pages38to39 \
+ ((uint32_t)0x00080000) /*!< N32G43x devices: \
+ Write protection of page 38 to 39 */
+#define FLASH_WRP_Pages40to41 \
+ ((uint32_t)0x00100000) /*!< N32G43x devices: \
+ Write protection of page 40 to 41 */
+#define FLASH_WRP_Pages42to43 \
+ ((uint32_t)0x00200000) /*!< N32G43x devices: \
+ Write protection of page 42 to 43 */
+#define FLASH_WRP_Pages44to45 \
+ ((uint32_t)0x00400000) /*!< N32G43x devices: \
+ Write protection of page 44 to 45 */
+#define FLASH_WRP_Pages46to47 \
+ ((uint32_t)0x00800000) /*!< N32G43x devices: \
+ Write protection of page 46 to 47 */
+#define FLASH_WRP_Pages48to49 \
+ ((uint32_t)0x01000000) /*!< N32G43x devices: \
+ Write protection of page 48 to 49 */
+#define FLASH_WRP_Pages50to51 \
+ ((uint32_t)0x02000000) /*!< N32G43x devices: \
+ Write protection of page 50 to 51 */
+#define FLASH_WRP_Pages52to53 \
+ ((uint32_t)0x04000000) /*!< N32G43x devices: \
+ Write protection of page 52 to 53 */
+#define FLASH_WRP_Pages54to55 \
+ ((uint32_t)0x08000000) /*!< N32G43x devices: \
+ Write protection of page 54 to 55 */
+#define FLASH_WRP_Pages56to57 \
+ ((uint32_t)0x10000000) /*!< N32G43x devices: \
+ Write protection of page 56 to 57 */
+#define FLASH_WRP_Pages58to59 \
+ ((uint32_t)0x20000000) /*!< N32G43x devices: \
+ Write protection of page 58 to 59 */
+#define FLASH_WRP_Pages60to61 \
+ ((uint32_t)0x40000000) /*!< N32G43x devices: \
+ Write protection of page 60 to 61 */
+#define FLASH_WRP_Pages62to63 \
+ ((uint32_t)0x80000000) /*!< N32G43x devices:
+ Write protection of page 62 to 63 */
+
+#define FLASH_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
+
+#define IS_FLASH_WRP_PAGE(PAGE) (1) //(((PAGE) <= FLASH_WRP_AllPages))
+
+#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0801FFFF))
+
+#define IS_OB_DATA_ADDRESS(ADDRESS) ((ADDRESS) == 0x1FFFF804)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_RDP1
+ * @{
+ */
+
+#define OB_RDP1_ENABLE ((uint8_t)0x00) /*!< Enable RDP1 */
+#define OB_RDP1_DISABLE ((uint8_t)0xA5) /*!< DISABLE RDP1 */
+#define IS_OB_RDP1_SOURCE(SOURCE) (((SOURCE) == OB_RDP1_ENABLE) || ((SOURCE) == OB_RDP1_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_IWatchdog
+ * @{
+ */
+
+#define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */
+#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_nRST_STOP
+ * @{
+ */
+
+#define OB_STOP2_NORST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */
+#define OB_STOP2_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
+#define IS_OB_STOP2_SOURCE(SOURCE) (((SOURCE) == OB_STOP2_NORST) || ((SOURCE) == OB_STOP2_RST))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_nRST_STDBY
+ * @{
+ */
+
+#define OB_STDBY_NORST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NORST) || ((SOURCE) == OB_STDBY_RST))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_nRST_PD
+ * @{
+ */
+
+#define OB_PD_NORST ((uint8_t)0x08) /*!< No reset generated when entering in PowerDown */
+#define OB_PD_RST ((uint8_t)0x00) /*!< Reset generated when entering in PowerDown */
+#define IS_OB_PD_SOURCE(SOURCE) (((SOURCE) == OB_PD_NORST) || ((SOURCE) == OB_PD_RST))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_RDP2
+ * @{
+ */
+
+#define OB_RDP2_ENABLE ((uint8_t)0x33) /*!< Enable RDP2 */
+#define OB_RDP2_DISABLE ((uint8_t)0x00) /*!< Disable RDP2 */
+#define IS_OB_RDP2_SOURCE(SOURCE) (((SOURCE) == OB_RDP2_ENABLE) || ((SOURCE) == OB_RDP2_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_nBOOT0
+ * @{
+ */
+
+#define OB2_NBOOT0_SET ((uint8_t)0x01) /*!< Set nBOOT0 */
+#define OB2_NBOOT0_CLR ((uint8_t)0x00) /*!< Clear nBOOT0 */
+#define IS_OB2_NBOOT0_SOURCE(SOURCE) (((SOURCE) == OB2_NBOOT0_SET) || ((SOURCE) == OB2_NBOOT0_CLR))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_nBOOT1
+ * @{
+ */
+
+#define OB2_NBOOT1_SET ((uint8_t)0x02) /*!< Set nBOOT1 */
+#define OB2_NBOOT1_CLR ((uint8_t)0x00) /*!< Clear nBOOT1 */
+#define IS_OB2_NBOOT1_SOURCE(SOURCE) (((SOURCE) == OB2_NBOOT1_SET) || ((SOURCE) == OB2_NBOOT1_CLR))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_nSWBOOT0
+ * @{
+ */
+
+#define OB2_NSWBOOT0_SET ((uint8_t)0x04) /*!< Set nSWBOOT0 */
+#define OB2_NSWBOOT0_CLR ((uint8_t)0x00) /*!< Clear nSWBOOT0 */
+#define IS_OB2_NSWBOOT0_SOURCE(SOURCE) (((SOURCE) == OB2_NSWBOOT0_SET) || ((SOURCE) == OB2_NSWBOOT0_CLR))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_BOR_LEV
+ * @{
+ */
+
+#define OB2_BOR_LEV0 ((uint8_t)0x00) /*!< BOR_LEV[2:0] L0 */
+#define OB2_BOR_LEV1 ((uint8_t)0x10) /*!< BOR_LEV[2:0] L1 */
+#define OB2_BOR_LEV2 ((uint8_t)0x20) /*!< BOR_LEV[2:0] L2 */
+#define OB2_BOR_LEV3 ((uint8_t)0x30) /*!< BOR_LEV[2:0] L3 */
+#define OB2_BOR_LEV4 ((uint8_t)0x40) /*!< BOR_LEV[2:0] L4 */
+#define OB2_BOR_LEV5 ((uint8_t)0x50) /*!< BOR_LEV[2:0] L5 */
+#define OB2_BOR_LEV6 ((uint8_t)0x60) /*!< BOR_LEV[2:0] L6 */
+#define OB2_BOR_LEV7 ((uint8_t)0x70) /*!< BOR_LEV[2:0] L7 */
+#define IS_OB2_BOR_LEV_SOURCE(SOURCE) (((SOURCE) == OB2_BOR_LEV0) || ((SOURCE) == OB2_BOR_LEV1) \
+ || ((SOURCE) == OB2_BOR_LEV2) || ((SOURCE) == OB2_BOR_LEV3) \
+ || ((SOURCE) == OB2_BOR_LEV4) || ((SOURCE) == OB2_BOR_LEV5) \
+ || ((SOURCE) == OB2_BOR_LEV6) || ((SOURCE) == OB2_BOR_LEV7))
+
+
+/**
+ * @}
+ */
+/** @addtogroup FLASH_Interrupts
+ * @{
+ */
+#define FLASH_INT_ERRIE ((uint32_t)0x00000400) /*!< PGERR WRPERR ERROR error interrupt source */
+#define FLASH_INT_FERR ((uint32_t)0x00000800) /*!< EVERR PVERR interrupt source */
+#define FLASH_INT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */
+
+#define IS_FLASH_INT(IT) ((((IT) & (uint32_t)0xFFFFE3FF) == 0x00000000) && (((IT) != 0x00000000)))
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Flags
+ * @{
+ */
+#define FLASH_FLAG_BUSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */
+#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */
+#define FLASH_FLAG_PVERR ((uint32_t)0x00000008) /*!< FLASH Program Verify ERROR flag after program */
+#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */
+#define FLASH_FLAG_EVERR ((uint32_t)0x00000040) /*!< FLASH Erase Verify ERROR flag after page erase */
+#define FLASH_FLAG_OBERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */
+
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF83) == 0x00000000) && ((FLAG) != 0x00000000))
+#define IS_FLASH_GET_FLAG(FLAG) \
+ (((FLAG) == FLASH_FLAG_BUSY) || ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_PVERR) \
+ || ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_EVERR) \
+ || ((FLAG) == FLASH_FLAG_OBERR))
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_STS_CLRFLAG
+ * @{
+ */
+#define FLASH_STS_CLRFLAG (FLASH_FLAG_PGERR | FLASH_FLAG_PVERR | FLASH_FLAG_WRPERR | FLASH_FLAG_EOP |FLASH_FLAG_EVERR)
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Exported_Functions
+ * @{
+ */
+
+/*------------ Functions used for N32G43x devices -----*/
+void FLASH_SetLatency(uint32_t FLASH_Latency);
+void FLASH_PrefetchBufSet(uint32_t FLASH_PrefetchBuf);
+void FLASH_iCacheRST(void);
+void FLASH_iCacheCmd(uint32_t FLASH_iCache);
+void FLASH_LowVoltageModeCmd(uint32_t FLASH_LVM);
+FlagStatus FLASH_GetLowVoltageModeSTS(void);
+void FLASH_FLASHSleepModeCmd(uint32_t FLASH_SLM);
+FlagStatus FLASH_GetFLASHSleepModeSTS(void);
+FLASH_HSICLOCK FLASH_ClockInit(void);
+void FLASH_Unlock(void);
+void FLASH_Lock(void);
+FLASH_STS FLASH_EraseOnePage(uint32_t Page_Address);
+FLASH_STS FLASH_MassErase(void);
+FLASH_STS FLASH_EraseOB(void);
+FLASH_STS FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+FLASH_STS FLASH_ProgramOBData(uint32_t Address, uint32_t Data);
+FLASH_STS FLASH_EnWriteProtection(uint32_t FLASH_Pages);
+FLASH_STS FLASH_ReadOutProtectionL1(FunctionalState Cmd);
+FLASH_STS FLASH_ReadOutProtectionL2_ENABLE(void);
+FLASH_STS FLASH_ConfigALLOptionByte(uint8_t OB_RDP1, uint8_t OB_IWDG, uint8_t OB_STOP2,
+ uint8_t OB_STDBY, uint8_t OB_PD, uint8_t OB_Data0,
+ uint8_t OB_Data1, uint32_t WRP_Pages, uint8_t OB_RDP2,
+ uint8_t OB2_nBOOT0, uint8_t OB2_nBOOT1, uint8_t OB2_nSWBOOT0,
+ uint8_t OB2_BOR_LEV);
+FLASH_STS FLASH_ConfigUserOB(uint8_t OB_IWDG, uint8_t OB_STOP2, uint8_t OB_STDBY, uint8_t OB_PD);
+FLASH_STS FLASH_ConfigUserOB2(uint8_t OB2_nBOOT0, uint8_t OB2_nBOOT1, uint8_t OB2_nSWBOOT0, uint8_t OB2_BOR_LEV);
+uint32_t FLASH_GetUserOB(void);
+uint32_t FLASH_GetWriteProtectionOB(void);
+FlagStatus FLASH_GetReadOutProtectionSTS(void);
+FlagStatus FLASH_GetReadOutProtectionL2STS(void);
+FlagStatus FLASH_GetPrefetchBufSTS(void);
+void FLASH_SetSMPSELStatus(uint32_t FLASH_smpsel);
+FLASH_SMPSEL FLASH_GetSMPSELStatus(void);
+void FLASH_INTConfig(uint32_t FLASH_INT, FunctionalState Cmd);
+FlagStatus FLASH_GetFlagSTS(uint32_t FLASH_FLAG);
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);
+FLASH_STS FLASH_GetSTS(void);
+FLASH_STS FLASH_WaitForLastOpt(uint32_t Timeout);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32G43X_FLASH_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_gpio.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_gpio.h
new file mode 100644
index 0000000000..5e261a918d
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_gpio.h
@@ -0,0 +1,660 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_gpio.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_GPIO_H__
+#define __N32G43X_GPIO_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/** @addtogroup GPIO_Exported_Types
+ * @{
+ */
+
+#define IS_GPIO_ALL_PERIPH(PERIPH) \
+ (((PERIPH) == GPIOA) || ((PERIPH) == GPIOB) || ((PERIPH) == GPIOC) || ((PERIPH) == GPIOD))
+
+
+#define GPIO_GET_INDEX(PERIPH) (((PERIPH) == (GPIOA))? 0 :\
+ ((PERIPH) == (GPIOB))? 1 :\
+ ((PERIPH) == (GPIOC))? 2 :3)
+#define GPIO_GET_PERIPH(INDEX) (((INDEX)==((uint8_t)0x00))? GPIOA :\
+ ((INDEX)==((uint8_t)0x01))? GPIOB :\
+ ((INDEX)==((uint8_t)0x02))? GPIOC : GPIOD )
+
+
+/**
+ * @brief Output Maximum frequency selection
+ */
+
+typedef enum
+{
+ GPIO_Slew_Rate_High = 0,
+ GPIO_Slew_Rate_Low
+} GPIO_SpeedType;
+#define IS_GPIO_SLEW_RATE(_RATE_) \
+ (((_RATE_) == GPIO_Slew_Rate_High) || ((_RATE_) == GPIO_Slew_Rate_Low))
+
+/**
+ * @brief driver strength config
+ */
+
+typedef enum
+{
+ GPIO_DC_2mA = 0x00,
+ GPIO_DC_4mA = 0x10,
+ GPIO_DC_8mA = 0x01,
+ GPIO_DC_12mA= 0x11
+}GPIO_CurrentType;
+
+#define IS_GPIO_CURRENT(CURRENT) \
+ (((CURRENT) == GPIO_DC_2mA) ||((CURRENT) == GPIO_DC_4mA) \
+ || ((CURRENT) == GPIO_DC_8mA)||((CURRENT) == GPIO_DC_12mA))
+/**
+ * @brief Configuration Mode enumeration
+ */
+
+
+/** @brief GPIO_mode_define Mode definition
+ * @brief GPIO Configuration Mode
+ * Values convention: 0xW0yz00YZ
+ * - W : GPIO mode or EXTI Mode
+ * - y : External IT or Event trigger detection
+ * - z : IO configuration on External IT or Event
+ * - Y : Output type (Push Pull or Open Drain)
+ * - Z : IO Direction mode (Input, Output, Alternate or Analog)
+ * @{
+ */
+
+typedef enum
+{
+ GPIO_Mode_Input = 0x00000000, /*!< Input Floating Mode */
+ GPIO_Mode_Out_PP = 0x00000001, /*!< Output Push Pull Mode */
+ GPIO_Mode_Out_OD = 0x00000011, /*!< Output Open Drain Mode */
+ GPIO_Mode_AF_PP = 0x00000002, /*!< Alternate Function Push Pull Mode */
+ GPIO_Mode_AF_OD = 0x00000012, /*!< Alternate Function Open Drain Mode */
+
+ GPIO_Mode_Analog = 0x00000003, /*!< Analog Mode */
+
+ GPIO_Mode_IT_Rising = 0x10110000, /*!< External Interrupt Mode with Rising edge trigger detection */
+ GPIO_Mode_IT_Falling = 0x10210000, /*!< External Interrupt Mode with Falling edge trigger detection */
+ GPIO_Mode_IT_Rising_Falling = 0x10310000, /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+
+ GPIO_Mode_EVT_Rising = 0x10120000, /*!< External Event Mode with Rising edge trigger detection */
+ GPIO_Mode_EVT_Falling = 0x10220000, /*!< External Event Mode with Falling edge trigger detection */
+ GPIO_Mode_EVT_Rising_Falling = 0x10320000
+}GPIO_ModeType;
+
+
+
+/**
+ * @}
+ */
+#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_Mode_Input) ||\
+ ((__MODE__) == GPIO_Mode_Out_PP) ||\
+ ((__MODE__) == GPIO_Mode_Out_OD) ||\
+ ((__MODE__) == GPIO_Mode_AF_PP) ||\
+ ((__MODE__) == GPIO_Mode_AF_OD) ||\
+ ((__MODE__) == GPIO_Mode_IT_Rising) ||\
+ ((__MODE__) == GPIO_Mode_IT_Falling) ||\
+ ((__MODE__) == GPIO_Mode_IT_Rising_Falling) ||\
+ ((__MODE__) == GPIO_Mode_EVT_Rising) ||\
+ ((__MODE__) == GPIO_Mode_EVT_Falling) ||\
+ ((__MODE__) == GPIO_Mode_EVT_Rising_Falling) ||\
+ ((__MODE__) == GPIO_Mode_Analog))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @brief GPIO_pull_define Pull definition
+ * @brief GPIO Pull-Up or Pull-Down Activation
+ * @{
+ */
+
+typedef enum
+{
+ GPIO_No_Pull = 0x00000000, /*!< No Pull-up or Pull-down activation */
+ GPIO_Pull_Up = 0x00000001, /*!< Pull-up activation */
+ GPIO_Pull_Down = 0x00000002 /*!< Pull-down activation */
+}GPIO_PuPdType;
+/**
+ * @}
+ */
+
+#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_No_Pull) || ((__PULL__) == GPIO_Pull_Up) || \
+ ((__PULL__) == GPIO_Pull_Down))
+/**
+ * @}
+ */
+
+/**
+ * @brief GPIO Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_pins_define */
+
+ GPIO_CurrentType GPIO_Current; /*!.
+ This paramter can be a value of @ref GPIO_CurrentType*/
+
+ GPIO_SpeedType GPIO_Slew_Rate; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIO_SpeedType */
+
+ GPIO_PuPdType GPIO_Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+ This parameter can be a value of @ref GPIO_pull_define */
+
+ GPIO_ModeType GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIO_ModeType */
+
+ uint32_t GPIO_Alternate; /*!< Peripheral to be connected to the selected pins
+ This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
+} GPIO_InitType;
+
+/**
+ * @brief Bit_SET and Bit_RESET enumeration
+ */
+
+typedef enum
+{
+ Bit_RESET = 0,
+ Bit_SET
+} Bit_OperateType;
+
+#define IS_GPIO_BIT_OPERATE(OPERATE) (((OPERATE) == Bit_RESET) || ((OPERATE) == Bit_SET))
+
+/**
+ * @}
+ */
+
+
+
+
+/** @addtogroup GPIO_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup GPIO_pins_define
+ * @{
+ */
+
+#define GPIO_PIN_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
+#define GPIO_PIN_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
+#define GPIO_PIN_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
+#define GPIO_PIN_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
+#define GPIO_PIN_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
+#define GPIO_PIN_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
+#define GPIO_PIN_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
+#define GPIO_PIN_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
+#define GPIO_PIN_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
+#define GPIO_PIN_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
+#define GPIO_PIN_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
+#define GPIO_PIN_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
+#define GPIO_PIN_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
+#define GPIO_PIN_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
+#define GPIO_PIN_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
+#define GPIO_PIN_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
+#define GPIO_PIN_ALL ((uint16_t)0xFFFF) /*!< All pins selected */
+
+#define GPIOA_PIN_AVAILABLE ((uint16_t)0xFFFF)
+#define GPIOB_PIN_AVAILABLE ((uint16_t)0xFFFF)
+#define GPIOC_PIN_AVAILABLE ((uint16_t)0xFFFF)
+#define GPIOD_PIN_AVAILABLE ((uint16_t)0xFFFF)
+
+#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
+
+#define IS_GET_GPIO_PIN(PIN) \
+ (((PIN) == GPIO_PIN_0) || ((PIN) == GPIO_PIN_1) || ((PIN) == GPIO_PIN_2) || ((PIN) == GPIO_PIN_3) \
+ || ((PIN) == GPIO_PIN_4) || ((PIN) == GPIO_PIN_5) || ((PIN) == GPIO_PIN_6) || ((PIN) == GPIO_PIN_7) \
+ || ((PIN) == GPIO_PIN_8) || ((PIN) == GPIO_PIN_9) || ((PIN) == GPIO_PIN_10) || ((PIN) == GPIO_PIN_11) \
+ || ((PIN) == GPIO_PIN_12) || ((PIN) == GPIO_PIN_13) || ((PIN) == GPIO_PIN_14) || ((PIN) == GPIO_PIN_15))
+
+
+#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) \
+ ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \
+ (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \
+ (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \
+ (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))))
+
+
+
+
+
+/**
+ * @}
+ */
+
+
+
+
+/** @addtogroup GPIO_Port_Sources
+ * @{
+ */
+
+#define GPIOA_PORT_SOURCE ((uint8_t)0x00)
+#define GPIOB_PORT_SOURCE ((uint8_t)0x01)
+#define GPIOC_PORT_SOURCE ((uint8_t)0x02)
+#define GPIOD_PORT_SOURCE ((uint8_t)0x03)
+
+#define IS_GPIO_REMAP_PORT_SOURCE(PORTSOURCE) \
+ (((PORTSOURCE) == GPIOA_PORT_SOURCE) || ((PORTSOURCE) == GPIOB_PORT_SOURCE) || ((PORTSOURCE) == GPIOC_PORT_SOURCE) \
+ || ((PORTSOURCE) == GPIOD_PORT_SOURCE))
+
+
+#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) \
+ (((PORTSOURCE) == GPIOA_PORT_SOURCE) || ((PORTSOURCE) == GPIOB_PORT_SOURCE) || ((PORTSOURCE) == GPIOC_PORT_SOURCE) \
+ || ((PORTSOURCE) == GPIOD_PORT_SOURCE))
+
+#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) \
+ (((PORTSOURCE) == GPIOA_PORT_SOURCE) || ((PORTSOURCE) == GPIOB_PORT_SOURCE) || ((PORTSOURCE) == GPIOC_PORT_SOURCE) \
+ || ((PORTSOURCE) == GPIOD_PORT_SOURCE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Pin_sources
+ * @{
+ */
+
+#define GPIO_PIN_SOURCE0 ((uint8_t)0x00)
+#define GPIO_PIN_SOURCE1 ((uint8_t)0x01)
+#define GPIO_PIN_SOURCE2 ((uint8_t)0x02)
+#define GPIO_PIN_SOURCE3 ((uint8_t)0x03)
+#define GPIO_PIN_SOURCE4 ((uint8_t)0x04)
+#define GPIO_PIN_SOURCE5 ((uint8_t)0x05)
+#define GPIO_PIN_SOURCE6 ((uint8_t)0x06)
+#define GPIO_PIN_SOURCE7 ((uint8_t)0x07)
+#define GPIO_PIN_SOURCE8 ((uint8_t)0x08)
+#define GPIO_PIN_SOURCE9 ((uint8_t)0x09)
+#define GPIO_PIN_SOURCE10 ((uint8_t)0x0A)
+#define GPIO_PIN_SOURCE11 ((uint8_t)0x0B)
+#define GPIO_PIN_SOURCE12 ((uint8_t)0x0C)
+#define GPIO_PIN_SOURCE13 ((uint8_t)0x0D)
+#define GPIO_PIN_SOURCE14 ((uint8_t)0x0E)
+#define GPIO_PIN_SOURCE15 ((uint8_t)0x0F)
+
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) \
+ (((PINSOURCE) == GPIO_PIN_SOURCE0) || ((PINSOURCE) == GPIO_PIN_SOURCE1) || ((PINSOURCE) == GPIO_PIN_SOURCE2) \
+ || ((PINSOURCE) == GPIO_PIN_SOURCE3) || ((PINSOURCE) == GPIO_PIN_SOURCE4) || ((PINSOURCE) == GPIO_PIN_SOURCE5) \
+ || ((PINSOURCE) == GPIO_PIN_SOURCE6) || ((PINSOURCE) == GPIO_PIN_SOURCE7) || ((PINSOURCE) == GPIO_PIN_SOURCE8) \
+ || ((PINSOURCE) == GPIO_PIN_SOURCE9) || ((PINSOURCE) == GPIO_PIN_SOURCE10) || ((PINSOURCE) == GPIO_PIN_SOURCE11) \
+ || ((PINSOURCE) == GPIO_PIN_SOURCE12) || ((PINSOURCE) == GPIO_PIN_SOURCE13) || ((PINSOURCE) == GPIO_PIN_SOURCE14) \
+ || ((PINSOURCE) == GPIO_PIN_SOURCE15))
+
+/**
+ * @}
+ */
+
+
+
+/** @defgroup GPIOx_Alternate_function_selection Alternate function selection
+ * @{
+ */
+
+/*
+ * Alternate function AF0
+ */
+#define GPIO_AF0_SW_JTAG ((uint8_t)0x00) /* SPI1 Alternate Function mapping */
+#define GPIO_AF0_SPI1 ((uint8_t)0x00) /* SPI1 Alternate Function mapping */
+#define GPIO_AF0_LPTIM ((uint8_t)0x00) /* LPTIM Alternate Function mapping */
+#define GPIO_AF0_SPI2 ((uint8_t)0x00) /* SPI2 Alternate Function mapping */
+#define GPIO_AF0_TIM8 ((uint8_t)0x00) /* TIM8 Alternate Function mapping */
+#define GPIO_AF0_USART1 ((uint8_t)0x00) /* USART1 Alternate Function mapping */
+#define GPIO_AF0_USART3 ((uint8_t)0x00) /* USART3 Alternate Function mapping */
+#define GPIO_AF0_LPUART ((uint8_t)0x00) /* LPUART Alternate Function mapping */
+#define GPIO_AF0_USART2 ((uint8_t)0x00) /* USART2 Alternate Function mapping */
+
+/**
+ *
+ */
+
+/*
+ * Alternate function AF1
+ */
+#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */
+#define GPIO_AF1_USART1 ((uint8_t)0x01) /* USART1 Alternate Function mapping */
+#define GPIO_AF1_I2C2 ((uint8_t)0x01) /* I2C2 Alternate Function mapping */
+#define GPIO_AF1_CAN ((uint8_t)0x01) /* CAN Alternate Function mapping */
+#define GPIO_AF1_SPI2 ((uint8_t)0x01) /* SPI2 Alternate Function mapping */
+#define GPIO_AF1_TIM9 ((uint8_t)0x01) /* TIM9 Alternate Function mapping */
+#define GPIO_AF1_SPI1 ((uint8_t)0x01) /* SPI1 Alternate Function mapping */
+#define GPIO_AF1_I2C1 ((uint8_t)0x01) /* I2C1 Alternate Function mapping */
+#define GPIO_AF1 ((uint8_t)0x01) /* test Alternate Function mapping */
+/**
+ *
+ */
+
+/*
+ * Alternate function AF2
+ */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_LPTIM ((uint8_t)0x02) /* LPTIM Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_LPUART ((uint8_t)0x02) /* LPUART Alternate Function mapping */
+/**
+ *
+ */
+
+/*
+ * Alternate function AF3
+ */
+#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /* EVENTOUT Alternate Function mapping */
+
+/**
+ *
+ */
+
+/*
+ * Alternate function AF4
+ */
+#define GPIO_AF4_USART2 ((uint8_t)0x04) /* USART2 Alternate Function mapping */
+#define GPIO_AF4_LPUART ((uint8_t)0x04) /* LPUART Alternate Function mapping */
+#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */
+#define GPIO_AF4_TIM3 ((uint8_t)0x04) /* TIM3 Alternate Function mapping*/
+#define GPIO_AF4_SPI1 ((uint8_t)0x04) /* SPI1 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_USART3 ((uint8_t)0x04) /* USART3 Alternate Function mapping */
+/**
+ *
+ */
+
+/*
+ * Alternate function AF5
+ */
+#define GPIO_AF5_TIM2 ((uint8_t)0x05) /* TIM2 Alternate Function mapping */
+#define GPIO_AF5_TIM1 ((uint8_t)0x05) /* TIM1 Alternate Function mapping */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
+#define GPIO_AF5_I2C2 ((uint8_t)0x05) /* I2C2 Alternate Function mapping */
+#define GPIO_AF5_LPTIM ((uint8_t)0x05) /* LPTIM Alternate Function mapping */
+#define GPIO_AF5_CAN ((uint8_t)0x05) /* CAN Alternate Function mapping */
+#define GPIO_AF5_USART3 ((uint8_t)0x05) /* USART3 Alternate Function mapping */
+
+/**
+ *
+ */
+
+/*
+ * Alternate function AF6
+ */
+
+#define GPIO_AF6_USART2 ((uint8_t)0x06) /* USART2 Alternate Function mapping */
+#define GPIO_AF6_LPUART ((uint8_t)0x06) /* LPUART Alternate Function mapping */
+#define GPIO_AF6_TIM5 ((uint8_t)0x06) /* TIM5 Alternate Function mapping */
+#define GPIO_AF6_TIM8 ((uint8_t)0x06) /* TIM8 Alternate Function mapping */
+#define GPIO_AF6_I2C2 ((uint8_t)0x06) /* I2C2 Alternate Function mapping */
+#define GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */
+#define GPIO_AF6_UART5 ((uint8_t)0x06) /* UART5 Alternate Function mapping */
+#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1 Alternate Function mapping */
+/**
+ *
+ */
+
+/*
+ * Alternate function AF7
+ */
+#define GPIO_AF7_COMP1 ((uint8_t)0x07) /* COMP1 Alternate Function mapping */
+#define GPIO_AF7_COMP2 ((uint8_t)0x07) /* COMP2 Alternate Function mapping */
+#define GPIO_AF7_I2C1 ((uint8_t)0x07) /* I2C1 Alternate Function mapping */
+#define GPIO_AF7_TIM8 ((uint8_t)0x07) /* TIM8 Alternate Function mapping */
+#define GPIO_AF7_TIM5 ((uint8_t)0x07) /* TIM5 Alternate Function mapping */
+#define GPIO_AF7_LPUART ((uint8_t)0x07) /* LPUART Alternate Function mapping */
+#define GPIO_AF7_UART5 ((uint8_t)0x07) /* UART5 Alternate Function mapping */
+#define GPIO_AF7_TIM1 ((uint8_t)0x07) /* TIM1 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+
+/**
+ *
+ */
+
+ /*
+ * Alternate function AF8
+ */
+#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
+#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
+#define GPIO_AF8_LPTIM ((uint8_t)0x08) /* LPTIM Alternate Function mapping */
+#define GPIO_AF8_MCO ((uint8_t)0x08) /* MCO Alternate Function mapping */
+
+/**
+ *
+ */
+
+ /*
+ * Alternate function AF9
+ */
+#define GPIO_AF9_RTC ((uint8_t)0x09) /* RTC Alternate Function mapping */
+#define GPIO_AF9_COMP1 ((uint8_t)0x09) /* COMP1 Alternate Function mapping */
+#define GPIO_AF9_TSC ((uint8_t)0x09) /* COMP1 Alternate Function mapping */
+
+/**
+ *
+ */
+
+ /*
+ * Alternate function AF15
+ */
+#define GPIO_AF15 ((uint8_t)0x0F) /* NON Alternate Function mapping */
+
+#define GPIO_NO_AF (GPIO_AF15)
+/**
+ * @}
+ */
+
+
+/**
+ * IS_GPIO_AF macro definition
+ */
+
+#define IS_GPIO_AF(__AF__) (((__AF__) == GPIO_AF0_SPI1) || ((__AF__) == GPIO_AF1_TIM5) || \
+ ((__AF__) == GPIO_AF0_LPTIM) || ((__AF__) == GPIO_AF1_USART1) || \
+ ((__AF__) == GPIO_AF0_SPI2) || ((__AF__) == GPIO_AF1_I2C2) || \
+ ((__AF__) == GPIO_AF0_TIM8) || ((__AF__) == GPIO_AF1_CAN) || \
+ ((__AF__) == GPIO_AF0_USART1) || ((__AF__) == GPIO_AF1_SPI2) || \
+ ((__AF__) == GPIO_AF0_USART3) || ((__AF__) == GPIO_AF1_TIM9) || \
+ ((__AF__) == GPIO_AF0_LPUART) || ((__AF__) == GPIO_AF1_SPI1) || \
+ ((__AF__) == GPIO_AF0_USART2) || ((__AF__) == GPIO_AF1_I2C1) || \
+ ((__AF__) == GPIO_AF3_EVENTOUT) || ((__AF__) == GPIO_AF2_TIM2) || \
+ ((__AF__) == GPIO_AF5_TIM2) || ((__AF__) == GPIO_AF2_TIM3) || \
+ ((__AF__) == GPIO_AF5_TIM1) || ((__AF__) == GPIO_AF2_TIM1) || \
+ ((__AF__) == GPIO_AF5_SPI1) || ((__AF__) == GPIO_AF2_LPTIM) || \
+ ((__AF__) == GPIO_AF5_SPI2) || ((__AF__) == GPIO_AF2_TIM4) || \
+ ((__AF__) == GPIO_AF5_I2C2) || ((__AF__) == GPIO_AF2_LPUART) || \
+ ((__AF__) == GPIO_AF5_LPTIM) || ((__AF__) == GPIO_AF4_USART2) || \
+ ((__AF__) == GPIO_AF5_CAN) || ((__AF__) == GPIO_AF4_LPUART) || \
+ ((__AF__) == GPIO_AF5_USART3) || ((__AF__) == GPIO_AF4_USART1) || \
+ ((__AF__) == GPIO_AF6_USART2) || ((__AF__) == GPIO_AF4_TIM3) || \
+ ((__AF__) == GPIO_AF6_LPUART) || ((__AF__) == GPIO_AF4_SPI1) || \
+ ((__AF__) == GPIO_AF6_TIM5) || ((__AF__) == GPIO_AF4_I2C1) || \
+ ((__AF__) == GPIO_AF6_TIM8) || ((__AF__) == GPIO_AF4_USART3) || \
+ ((__AF__) == GPIO_AF6_I2C2) || ((__AF__) == GPIO_AF7_COMP1) || \
+ ((__AF__) == GPIO_AF6_UART4) || ((__AF__) == GPIO_AF7_COMP2) || \
+ ((__AF__) == GPIO_AF6_UART5) || ((__AF__) == GPIO_AF7_I2C1) || \
+ ((__AF__) == GPIO_AF6_SPI1) || ((__AF__) == GPIO_AF7_TIM8) || \
+ ((__AF__) == GPIO_AF8_COMP1) || ((__AF__) == GPIO_AF7_TIM5) || \
+ ((__AF__) == GPIO_AF8_COMP2) || ((__AF__) == GPIO_AF7_LPUART) || \
+ ((__AF__) == GPIO_AF8_LPTIM) || ((__AF__) == GPIO_AF7_UART5) || \
+ ((__AF__) == GPIO_AF9_RTC) || ((__AF__) == GPIO_AF7_TIM1) || \
+ ((__AF__) == GPIO_AF9_COMP1) || ((__AF__) == GPIO_AF7_USART3) || \
+ ((__AF__) == GPIO_AF15) || ((__AF__) == GPIO_NO_AF))
+
+
+
+
+
+/**
+ * @}
+ */
+/** @defgroup GPIO Alternate function remaping
+ * @{
+ */
+#define AFIO_SPI1_NSS (11U)
+#define AFIO_SPI2_NSS (10U)
+
+#define IS_AFIO_SPIX(_PARAMETER_) \
+ (((_PARAMETER_) == AFIO_SPI1_NSS) ||((_PARAMETER_) == AFIO_SPI2_NSS))
+typedef enum
+{
+ AFIO_SPI_NSS_High_IMPEDANCE = 0U,
+ AFIO_SPI_NSS_High_LEVEL = 1U
+}AFIO_SPI_NSSType;
+
+#define IS_AFIO_SPI_NSS(_PARAMETER_) \
+ (((_PARAMETER_) == AFIO_SPI_NSS_High_IMPEDANCE) ||((_PARAMETER_) == AFIO_SPI_NSS_High_LEVEL))
+
+
+typedef enum
+{
+ AFIO_ADC_ETRI= 9U,
+ AFIO_ADC_ETRR = 8U
+}AFIO_ADC_ETRType;
+
+typedef enum
+{
+ AFIO_ADC_TRIG_EXTI_0 = 0x0U,
+ AFIO_ADC_TRIG_EXTI_1 = 0x01U,
+ AFIO_ADC_TRIG_EXTI_2,
+ AFIO_ADC_TRIG_EXTI_3,
+ AFIO_ADC_TRIG_EXTI_4,
+ AFIO_ADC_TRIG_EXTI_5,
+ AFIO_ADC_TRIG_EXTI_6,
+ AFIO_ADC_TRIG_EXTI_7,
+ AFIO_ADC_TRIG_EXTI_8,
+ AFIO_ADC_TRIG_EXTI_9,
+ AFIO_ADC_TRIG_EXTI_10,
+ AFIO_ADC_TRIG_EXTI_11,
+ AFIO_ADC_TRIG_EXTI_12,
+ AFIO_ADC_TRIG_EXTI_13,
+ AFIO_ADC_TRIG_EXTI_14,
+ AFIO_ADC_TRIG_EXTI_15,
+ AFIO_ADC_TRIG_TIM8_CH3,
+ AFIO_ADC_TRIG_TIM8_CH4
+}AFIO_ADC_Trig_RemapType;
+
+#define IS_AFIO_ADC_ETR(_PARAMETER_) \
+ (((_PARAMETER_) == AFIO_ADC_ETRI) ||((_PARAMETER_) == AFIO_ADC_ETRR))
+#define IS_AFIO_ADC_ETRI(_PARAMETER_) \
+ (((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_0) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_1)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_2) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_3)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_4) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_5)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_6) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_7)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_8) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_9)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_10) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_11)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_12) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_13)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_14) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_15)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_TIM8_CH4))
+
+#define IS_AFIO_ADC_ETRR(_PARAMETER_) \
+ (((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_0) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_1)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_2) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_3)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_4) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_5)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_6) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_7)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_8) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_9)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_10) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_11)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_12) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_13) ||\
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_14) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_15)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_TIM8_CH3))
+
+ /**
+ * @}
+ */
+
+/** @addtogroup GPIO_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Exported_Functions
+ * @{
+ */
+
+void GPIO_DeInit(GPIO_Module* GPIOx);
+void GPIO_AFIOInitDefault(void);
+void GPIO_InitPeripheral(GPIO_Module* GPIOx, GPIO_InitType* GPIO_InitStruct);
+void GPIO_InitStruct(GPIO_InitType* GPIO_InitStruct);
+uint8_t GPIO_ReadInputDataBit(GPIO_Module* GPIOx, uint16_t Pin);
+uint16_t GPIO_ReadInputData(GPIO_Module* GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_Module* GPIOx, uint16_t Pin);
+uint16_t GPIO_ReadOutputData(GPIO_Module* GPIOx);
+void GPIO_SetBits(GPIO_Module* GPIOx, uint16_t Pin);
+void GPIO_ResetBits(GPIO_Module* GPIOx, uint16_t Pin);
+void GPIO_WriteBit(GPIO_Module* GPIOx, uint16_t Pin, Bit_OperateType BitCmd);
+void GPIO_Write(GPIO_Module* GPIOx, uint16_t PortVal);
+void GPIO_ConfigPinLock(GPIO_Module* GPIOx, uint16_t Pin);
+void GPIO_ConfigEventOutput(uint8_t PortSource, uint8_t PinSource);
+void GPIO_CtrlEventOutput(FunctionalState Cmd);
+void GPIO_ConfigPinRemap(uint8_t PortSource, uint8_t PinSource, uint32_t AlternateFunction);
+void GPIO_ConfigEXTILine(uint8_t PortSource, uint8_t PinSource);
+
+void AFIO_ConfigSPINSSMode(uint32_t AFIO_SPIx_NSS,AFIO_SPI_NSSType SpiNssType);
+void AFIO_ConfigADCExternalTrigRemap(AFIO_ADC_ETRType ADCETRType,AFIO_ADC_Trig_RemapType ADCTrigRemap);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32G43X_GPIO_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_i2c.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_i2c.h
new file mode 100644
index 0000000000..1034014a42
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_i2c.h
@@ -0,0 +1,672 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_i2c.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_I2C_H__
+#define __N32G43X_I2C_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @{
+ */
+
+/** @addtogroup I2C_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief I2C Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t ClkSpeed; /*!< Specifies the clock frequency.
+ This parameter must be set to a value lower than 400kHz */
+
+ uint16_t BusMode; /*!< Specifies the I2C mode.
+ This parameter can be a value of @ref I2C_BusMode */
+
+ uint16_t FmDutyCycle; /*!< Specifies the I2C fast mode duty cycle.
+ This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+ uint16_t OwnAddr1; /*!< Specifies the first device own address.
+ This parameter can be a 7-bit or 10-bit address. */
+
+ uint16_t AckEnable; /*!< Enables or disables the acknowledgement.
+ This parameter can be a value of @ref I2C_acknowledgement */
+
+ uint16_t AddrMode; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
+ This parameter can be a value of @ref I2C_acknowledged_address */
+} I2C_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Exported_Constants
+ * @{
+ */
+
+#define IS_I2C_PERIPH(PERIPH) (((PERIPH) == I2C1) || ((PERIPH) == I2C2))
+/** @addtogroup I2C_BusMode
+ * @{
+ */
+
+#define I2C_BUSMODE_I2C ((uint16_t)0x0000)
+#define I2C_BUSMODE_SMBDEVICE ((uint16_t)0x0002)
+#define I2C_BUSMODE_SMBHOST ((uint16_t)0x000A)
+#define IS_I2C_BUS_MODE(MODE) \
+ (((MODE) == I2C_BUSMODE_I2C) || ((MODE) == I2C_BUSMODE_SMBDEVICE) || ((MODE) == I2C_BUSMODE_SMBHOST))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_duty_cycle_in_fast_mode
+ * @{
+ */
+
+#define I2C_FMDUTYCYCLE_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
+#define I2C_FMDUTYCYCLE_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
+#define IS_I2C_FM_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_FMDUTYCYCLE_16_9) || ((CYCLE) == I2C_FMDUTYCYCLE_2))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_acknowledgement
+ * @{
+ */
+
+#define I2C_ACKEN ((uint16_t)0x0400)
+#define I2C_ACKDIS ((uint16_t)0x0000)
+#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_ACKEN) || ((STATE) == I2C_ACKDIS))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_transfer_direction
+ * @{
+ */
+
+#define I2C_DIRECTION_SEND ((uint8_t)0x00)
+#define I2C_DIRECTION_RECV ((uint8_t)0x01)
+#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_DIRECTION_SEND) || ((DIRECTION) == I2C_DIRECTION_RECV))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_acknowledged_address
+ * @{
+ */
+
+#define I2C_ADDR_MODE_7BIT ((uint16_t)0x4000)
+#define I2C_ADDR_MODE_10BIT ((uint16_t)0xC000)
+#define IS_I2C_ADDR_MODE(ADDRESS) (((ADDRESS) == I2C_ADDR_MODE_7BIT) || ((ADDRESS) == I2C_ADDR_MODE_10BIT))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_registers
+ * @{
+ */
+
+#define I2C_REG_CTRL1 ((uint8_t)0x00)
+#define I2C_REG_CTRL2 ((uint8_t)0x04)
+#define I2C_REG_OADDR1 ((uint8_t)0x08)
+#define I2C_REG_OADDR2 ((uint8_t)0x0C)
+#define I2C_REG_DAT ((uint8_t)0x10)
+#define I2C_REG_STS1 ((uint8_t)0x14)
+#define I2C_REG_STS2 ((uint8_t)0x18)
+#define I2C_REG_CLKCTRL ((uint8_t)0x1C)
+#define I2C_REG_TMRISE ((uint8_t)0x20)
+#define IS_I2C_REG(REGISTER) \
+ (((REGISTER) == I2C_REG_CTRL1) || ((REGISTER) == I2C_REG_CTRL2) || ((REGISTER) == I2C_REG_OADDR1) \
+ || ((REGISTER) == I2C_REG_OADDR2) || ((REGISTER) == I2C_REG_DAT) || ((REGISTER) == I2C_REG_STS1) \
+ || ((REGISTER) == I2C_REG_STS2) || ((REGISTER) == I2C_REG_CLKCTRL) || ((REGISTER) == I2C_REG_TMRISE))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_SMBus_alert_pin_level
+ * @{
+ */
+
+#define I2C_SMBALERT_LOW ((uint16_t)0x2000)
+#define I2C_SMBALERT_HIGH ((uint16_t)0xDFFF)
+#define IS_I2C_SMB_ALERT(ALERT) (((ALERT) == I2C_SMBALERT_LOW) || ((ALERT) == I2C_SMBALERT_HIGH))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_PEC_position
+ * @{
+ */
+
+#define I2C_PEC_POS_NEXT ((uint16_t)0x0800)
+#define I2C_PEC_POS_CURRENT ((uint16_t)0xF7FF)
+#define IS_I2C_PEC_POS(POSITION) (((POSITION) == I2C_PEC_POS_NEXT) || ((POSITION) == I2C_PEC_POS_CURRENT))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_NCAK_position
+ * @{
+ */
+
+#define I2C_NACK_POS_NEXT ((uint16_t)0x0800)
+#define I2C_NACK_POS_CURRENT ((uint16_t)0xF7FF)
+#define IS_I2C_NACK_POS(POSITION) (((POSITION) == I2C_NACK_POS_NEXT) || ((POSITION) == I2C_NACK_POS_CURRENT))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_interrupts_definition
+ * @{
+ */
+
+#define I2C_INT_BUF ((uint16_t)0x0400)
+#define I2C_INT_EVENT ((uint16_t)0x0200)
+#define I2C_INT_ERR ((uint16_t)0x0100)
+#define IS_I2C_CFG_INT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_interrupts_definition
+ * @{
+ */
+
+#define I2C_INT_SMBALERT ((uint32_t)0x01008000)
+#define I2C_INT_TIMOUT ((uint32_t)0x01004000)
+#define I2C_INT_PECERR ((uint32_t)0x01001000)
+#define I2C_INT_OVERRUN ((uint32_t)0x01000800)
+#define I2C_INT_ACKFAIL ((uint32_t)0x01000400)
+#define I2C_INT_ARLOST ((uint32_t)0x01000200)
+#define I2C_INT_BUSERR ((uint32_t)0x01000100)
+#define I2C_INT_TXDATE ((uint32_t)0x06000080)
+#define I2C_INT_RXDATNE ((uint32_t)0x06000040)
+#define I2C_INT_STOPF ((uint32_t)0x02000010)
+#define I2C_INT_ADDR10F ((uint32_t)0x02000008)
+#define I2C_INT_BYTEF ((uint32_t)0x02000004)
+#define I2C_INT_ADDRF ((uint32_t)0x02000002)
+#define I2C_INT_STARTBF ((uint32_t)0x02000001)
+
+#define IS_I2C_CLR_INT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
+
+#define IS_I2C_GET_INT(IT) \
+ (((IT) == I2C_INT_SMBALERT) || ((IT) == I2C_INT_TIMOUT) || ((IT) == I2C_INT_PECERR) || ((IT) == I2C_INT_OVERRUN) \
+ || ((IT) == I2C_INT_ACKFAIL) || ((IT) == I2C_INT_ARLOST) || ((IT) == I2C_INT_BUSERR) || ((IT) == I2C_INT_TXDATE) \
+ || ((IT) == I2C_INT_RXDATNE) || ((IT) == I2C_INT_STOPF) || ((IT) == I2C_INT_ADDR10F) || ((IT) == I2C_INT_BYTEF) \
+ || ((IT) == I2C_INT_ADDRF) || ((IT) == I2C_INT_STARTBF))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_flags_definition
+ * @{
+ */
+
+/**
+ * @brief STS2 register flags
+ */
+
+#define I2C_FLAG_DUALFLAG ((uint32_t)0x00800000)
+#define I2C_FLAG_SMBHADDR ((uint32_t)0x00400000)
+#define I2C_FLAG_SMBDADDR ((uint32_t)0x00200000)
+#define I2C_FLAG_GCALLADDR ((uint32_t)0x00100000)
+#define I2C_FLAG_TRF ((uint32_t)0x00040000)
+#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
+#define I2C_FLAG_MSMODE ((uint32_t)0x00010000)
+
+/**
+ * @brief STS1 register flags
+ */
+
+#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
+#define I2C_FLAG_TIMOUT ((uint32_t)0x10004000)
+#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
+#define I2C_FLAG_OVERRUN ((uint32_t)0x10000800)
+#define I2C_FLAG_ACKFAIL ((uint32_t)0x10000400)
+#define I2C_FLAG_ARLOST ((uint32_t)0x10000200)
+#define I2C_FLAG_BUSERR ((uint32_t)0x10000100)
+#define I2C_FLAG_TXDATE ((uint32_t)0x10000080)
+#define I2C_FLAG_RXDATNE ((uint32_t)0x10000040)
+#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
+#define I2C_FLAG_ADDR10F ((uint32_t)0x10000008)
+#define I2C_FLAG_BYTEF ((uint32_t)0x10000004)
+#define I2C_FLAG_ADDRF ((uint32_t)0x10000002)
+#define I2C_FLAG_STARTBF ((uint32_t)0x10000001)
+
+#define IS_I2C_CLR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
+
+#define IS_I2C_GET_FLAG(FLAG) \
+ (((FLAG) == I2C_FLAG_DUALFLAG) || ((FLAG) == I2C_FLAG_SMBHADDR) || ((FLAG) == I2C_FLAG_SMBDADDR) \
+ || ((FLAG) == I2C_FLAG_GCALLADDR) || ((FLAG) == I2C_FLAG_TRF) || ((FLAG) == I2C_FLAG_BUSY) \
+ || ((FLAG) == I2C_FLAG_MSMODE) || ((FLAG) == I2C_FLAG_SMBALERT) || ((FLAG) == I2C_FLAG_TIMOUT) \
+ || ((FLAG) == I2C_FLAG_PECERR) || ((FLAG) == I2C_FLAG_OVERRUN) || ((FLAG) == I2C_FLAG_ACKFAIL) \
+ || ((FLAG) == I2C_FLAG_ARLOST) || ((FLAG) == I2C_FLAG_BUSERR) || ((FLAG) == I2C_FLAG_TXDATE) \
+ || ((FLAG) == I2C_FLAG_RXDATNE) || ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADDR10F) \
+ || ((FLAG) == I2C_FLAG_BYTEF) || ((FLAG) == I2C_FLAG_ADDRF) || ((FLAG) == I2C_FLAG_STARTBF))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Events
+ * @{
+ */
+
+/*========================================
+
+ I2C Master Events (Events grouped in order of communication)
+ ==========================================*/
+/**
+ * @brief Communication start
+ *
+ * After sending the START condition (I2C_GenerateStart() function) the master
+ * has to wait for this event. It means that the Start condition has been correctly
+ * released on the I2C bus (the bus is free, no other devices is communicating).
+ *
+ */
+/* Master mode */
+#define I2C_ROLE_MASTER ((uint32_t)0x00010000) /* MSMODE */
+/* --EV5 */
+#define I2C_EVT_MASTER_MODE_FLAG ((uint32_t)0x00030001) /* BUSY, MSMODE and SB flag */
+
+/**
+ * @brief Address Acknowledge
+ *
+ * After checking on EV5 (start condition correctly released on the bus), the
+ * master sends the address of the slave(s) with which it will communicate
+ * (I2C_SendAddr7bit() function, it also determines the direction of the communication:
+ * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
+ * his address. If an acknowledge is sent on the bus, one of the following events will
+ * be set:
+ *
+ * 1) In case of Master Receiver (7-bit addressing): the I2C_EVT_MASTER_RXMODE_FLAG
+ * event is set.
+ *
+ * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVT_MASTER_TXMODE_FLAG
+ * is set
+ *
+ * 3) In case of 10-Bit addressing mode, the master (just after generating the START
+ * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
+ * function). Then master should wait on EV9. It means that the 10-bit addressing
+ * header has been correctly sent on the bus. Then master should send the second part of
+ * the 10-bit address (LSB) using the function I2C_SendAddr7bit(). Then master
+ * should wait for event EV6.
+ *
+ */
+
+/* --EV6 */
+#define I2C_EVT_MASTER_TXMODE_FLAG ((uint32_t)0x00070082) /* BUSY, MSMODE, ADDRF, TXDATE and TRF flags */
+#define I2C_EVT_MASTER_RXMODE_FLAG ((uint32_t)0x00030002) /* BUSY, MSMODE and ADDRF flags */
+/* --EV9 */
+#define I2C_EVT_MASTER_MODE_ADDRESS10_FLAG ((uint32_t)0x00030008) /* BUSY, MSMODE and ADDR10F flags */
+
+/**
+ * @brief Communication events
+ *
+ * If a communication is established (START condition generated and slave address
+ * acknowledged) then the master has to check on one of the following events for
+ * communication procedures:
+ *
+ * 1) Master Receiver mode: The master has to wait on the event EV7 then to read
+ * the data received from the slave (I2C_RecvData() function).
+ *
+ * 2) Master Transmitter mode: The master has to send data (I2C_SendData()
+ * function) then to wait on event EV8 or EV8_2.
+ * These two events are similar:
+ * - EV8 means that the data has been written in the data register and is
+ * being shifted out.
+ * - EV8_2 means that the data has been physically shifted out and output
+ * on the bus.
+ * In most cases, using EV8 is sufficient for the application.
+ * Using EV8_2 leads to a slower communication but ensure more reliable test.
+ * EV8_2 is also more suitable than EV8 for testing on the last data transmission
+ * (before Stop condition generation).
+ *
+ * @note In case the user software does not guarantee that this event EV7 is
+ * managed before the current byte end of transfer, then user may check on EV7
+ * and BSF flag at the same time (ie. (I2C_EVT_MASTER_DATA_RECVD_FLAG | I2C_FLAG_BYTEF)).
+ * In this case the communication may be slower.
+ *
+ */
+
+/* Master RECEIVER mode -----------------------------*/
+/* --EV7 */
+#define I2C_EVT_MASTER_DATA_RECVD_FLAG ((uint32_t)0x00030040) /* BUSY, MSMODE and RXDATNE flags */
+/* EV7x shifter register full */
+#define I2C_EVT_MASTER_SFT_DATA_RECVD_FLAG ((uint32_t)0x00030044) /* BUSY, MSMODE, BSF and RXDATNE flags */
+
+/* Master TRANSMITTER mode --------------------------*/
+/* --EV8 */
+#define I2C_EVT_MASTER_DATA_SENDING ((uint32_t)0x00070080) /* TRF, BUSY, MSMODE, TXDATE flags */
+/* --EV8_2 */
+#define I2C_EVT_MASTER_DATA_SENDED ((uint32_t)0x00070084) /* TRF, BUSY, MSMODE, TXDATE and BSF flags */
+
+/*========================================
+
+ I2C Slave Events (Events grouped in order of communication)
+ ==========================================*/
+
+/**
+ * @brief Communication start events
+ *
+ * Wait on one of these events at the start of the communication. It means that
+ * the I2C peripheral detected a Start condition on the bus (generated by master
+ * device) followed by the peripheral address. The peripheral generates an ACK
+ * condition on the bus (if the acknowledge feature is enabled through function
+ * I2C_ConfigAck()) and the events listed above are set :
+ *
+ * 1) In normal case (only one address managed by the slave), when the address
+ * sent by the master matches the own address of the peripheral (configured by
+ * OwnAddr1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
+ * (where XXX could be TRANSMITTER or RECEIVER).
+ *
+ * 2) In case the address sent by the master matches the second address of the
+ * peripheral (configured by the function I2C_ConfigOwnAddr2() and enabled
+ * by the function I2C_EnableDualAddr()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
+ * (where XXX could be TRANSMITTER or RECEIVER) are set.
+ *
+ * 3) In case the address sent by the master is General Call (address 0x00) and
+ * if the General Call is enabled for the peripheral (using function I2C_EnableGeneralCall())
+ * the following event is set I2C_EVT_SLAVE_GCALLADDR_MATCHED.
+ *
+ */
+
+/* --EV1 (all the events below are variants of EV1) */
+/* 1) Case of One Single Address managed by the slave */
+#define I2C_EVT_SLAVE_RECV_ADDR_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDRF flags */
+#define I2C_EVT_SLAVE_SEND_ADDR_MATCHED ((uint32_t)0x00060082) /* TRF, BUSY, TXDATE and ADDRF flags */
+
+/* 2) Case of Dual address managed by the slave */
+#define I2C_EVT_SLAVE_RECV_ADDR2_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
+#define I2C_EVT_SLAVE_SEND_ADDR2_MATCHED ((uint32_t)0x00860080) /* DUALF, TRF, BUSY and TXDATE flags */
+
+/* 3) Case of General Call enabled for the slave */
+#define I2C_EVT_SLAVE_GCALLADDR_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
+
+/**
+ * @brief Communication events
+ *
+ * Wait on one of these events when EV1 has already been checked and:
+ *
+ * - Slave RECEIVER mode:
+ * - EV2: When the application is expecting a data byte to be received.
+ * - EV4: When the application is expecting the end of the communication: master
+ * sends a stop condition and data transmission is stopped.
+ *
+ * - Slave Transmitter mode:
+ * - EV3: When a byte has been transmitted by the slave and the application is expecting
+ * the end of the byte transmission. The two events I2C_EVT_SLAVE_DATA_SENDED and
+ * I2C_EVT_SLAVE_DATA_SENDING are similar. The second one can optionally be
+ * used when the user software doesn't guarantee the EV3 is managed before the
+ * current byte end of transfer.
+ * - EV3_2: When the master sends a NACK in order to tell slave that data transmission
+ * shall end (before sending the STOP condition). In this case slave has to stop sending
+ * data bytes and expect a Stop condition on the bus.
+ *
+ * @note In case the user software does not guarantee that the event EV2 is
+ * managed before the current byte end of transfer, then user may check on EV2
+ * and BSF flag at the same time (ie. (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_BYTEF)).
+ * In this case the communication may be slower.
+ *
+ */
+
+/* Slave RECEIVER mode --------------------------*/
+/* --EV2 */
+#define I2C_EVT_SLAVE_DATA_RECVD ((uint32_t)0x00020040) /* BUSY and RXDATNE flags */
+/* --EV2x */
+#define I2C_EVT_SLAVE_DATA_RECVD_NOBUSY ((uint32_t)0x00000040) /* no BUSY and RXDATNE flags */
+/* --EV4 */
+#define I2C_EVT_SLAVE_STOP_RECVD ((uint32_t)0x00000010) /* STOPF flag */
+
+/* Slave TRANSMITTER mode -----------------------*/
+/* --EV3 */
+#define I2C_EVT_SLAVE_DATA_SENDED ((uint32_t)0x00060084) /* TRF, BUSY, TXDATE and BSF flags */
+#define I2C_EVT_SLAVE_DATA_SENDING ((uint32_t)0x00060080) /* TRF, BUSY and TXDATE flags */
+/* --EV3_2 */
+#define I2C_EVT_SLAVE_ACK_MISS ((uint32_t)0x00000400) /* AF flag */
+
+/*=========================== End of Events Description ==========================================*/
+
+#define IS_I2C_EVT(EVENT) \
+ (((EVENT) == I2C_EVT_SLAVE_SEND_ADDR_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_RECV_ADDR_MATCHED) \
+ || ((EVENT) == I2C_EVT_SLAVE_SEND_ADDR2_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_RECV_ADDR2_MATCHED) \
+ || ((EVENT) == I2C_EVT_SLAVE_GCALLADDR_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_DATA_RECVD) \
+ || ((EVENT) == (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_DUALFLAG)) \
+ || ((EVENT) == (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_GCALLADDR)) || ((EVENT) == I2C_EVT_SLAVE_DATA_SENDED) \
+ || ((EVENT) == (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_DUALFLAG)) \
+ || ((EVENT) == (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_GCALLADDR)) || ((EVENT) == I2C_EVT_SLAVE_STOP_RECVD) \
+ || ((EVENT) == I2C_EVT_MASTER_MODE_FLAG) || ((EVENT) == I2C_EVT_MASTER_TXMODE_FLAG) \
+ || ((EVENT) == I2C_EVT_MASTER_RXMODE_FLAG) || ((EVENT) == I2C_EVT_MASTER_DATA_RECVD_FLAG) \
+ || ((EVENT) == I2C_EVT_MASTER_DATA_SENDED) || ((EVENT) == I2C_EVT_MASTER_DATA_SENDING) \
+ || ((EVENT) == I2C_EVT_MASTER_MODE_ADDRESS10_FLAG) || ((EVENT) == I2C_EVT_SLAVE_ACK_MISS) \
+ || ((EVENT) == I2C_EVT_MASTER_SFT_DATA_RECVD_FLAG) || ((EVENT) == I2C_EVT_SLAVE_DATA_RECVD_NOBUSY))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_own_address1
+ * @{
+ */
+
+#define IS_I2C_OWN_ADDR1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_clock_speed
+ * @{
+ */
+
+//#define IS_I2C_CLK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
+#define IS_I2C_CLK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 1000000))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Exported_Functions
+ * @{
+ */
+
+void I2C_DeInit(I2C_Module* I2Cx);
+void I2C_Init(I2C_Module* I2Cx, I2C_InitType* I2C_InitStruct);
+void I2C_InitStruct(I2C_InitType* I2C_InitStruct);
+void I2C_Enable(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_EnableDMA(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_EnableDmaLastSend(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_GenerateStart(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_GenerateStop(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_ConfigAck(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_ConfigOwnAddr2(I2C_Module* I2Cx, uint8_t Address);
+void I2C_EnableDualAddr(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_EnableGeneralCall(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_ConfigInt(I2C_Module* I2Cx, uint16_t I2C_IT, FunctionalState Cmd);
+void I2C_SendData(I2C_Module* I2Cx, uint8_t Data);
+uint8_t I2C_RecvData(I2C_Module* I2Cx);
+void I2C_SendAddr7bit(I2C_Module* I2Cx, uint8_t Address, uint8_t I2C_Direction);
+uint16_t I2C_GetRegister(I2C_Module* I2Cx, uint8_t I2C_Register);
+void I2C_EnableSoftwareReset(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_ConfigNackLocation(I2C_Module* I2Cx, uint16_t I2C_NACKPosition);
+void I2C_ConfigSmbusAlert(I2C_Module* I2Cx, uint16_t I2C_SMBusAlert);
+void I2C_SendPEC(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_ConfigPecLocation(I2C_Module* I2Cx, uint16_t I2C_PECPosition);
+void I2C_ComputePec(I2C_Module* I2Cx, FunctionalState Cmd);
+uint8_t I2C_GetPec(I2C_Module* I2Cx);
+void I2C_EnableArp(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_EnableExtendClk(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_ConfigFastModeDutyCycle(I2C_Module* I2Cx, uint16_t FmDutyCycle);
+
+/**
+ * @brief
+ ****************************************************************************************
+ *
+ * I2C State Monitoring Functions
+ *
+ ****************************************************************************************
+ * This I2C driver provides three different ways for I2C state monitoring
+ * depending on the application requirements and constraints:
+ *
+ *
+ * 1) Basic state monitoring:
+ * Using I2C_CheckEvent() function:
+ * It compares the status registers (STS1 and STS2) content to a given event
+ * (can be the combination of one or more flags).
+ * It returns SUCCESS if the current status includes the given flags
+ * and returns ERROR if one or more flags are missing in the current status.
+ * - When to use:
+ * - This function is suitable for most applications as well as for startup
+ * activity since the events are fully described in the product reference manual
+ * (RM0008).
+ * - It is also suitable for users who need to define their own events.
+ * - Limitations:
+ * - If an error occurs (ie. error flags are set besides to the monitored flags),
+ * the I2C_CheckEvent() function may return SUCCESS despite the communication
+ * hold or corrupted real state.
+ * In this case, it is advised to use error interrupts to monitor the error
+ * events and handle them in the interrupt IRQ handler.
+ *
+ * @note
+ * For error management, it is advised to use the following functions:
+ * - I2C_ConfigInt() to configure and enable the error interrupts (I2C_INT_ERR).
+ * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
+ * Where x is the peripheral instance (I2C1, I2C2 ...)
+ * - I2C_GetFlag() or I2C_GetIntStatus() to be called into I2Cx_ER_IRQHandler()
+ * in order to determine which error occurred.
+ * - I2C_ClrFlag() or I2C_ClrIntPendingBit() and/or I2C_EnableSoftwareReset()
+ * and/or I2C_GenerateStop() in order to clear the error flag and source,
+ * and return to correct communication status.
+ *
+ *
+ * 2) Advanced state monitoring:
+ * Using the function I2C_GetLastEvent() which returns the image of both status
+ * registers in a single word (uint32_t) (Status Register 2 value is shifted left
+ * by 16 bits and concatenated to Status Register 1).
+ * - When to use:
+ * - This function is suitable for the same applications above but it allows to
+ * overcome the limitations of I2C_GetFlag() function (see below).
+ * The returned value could be compared to events already defined in the
+ * library (n32g43x_i2c.h) or to custom values defined by user.
+ * - This function is suitable when multiple flags are monitored at the same time.
+ * - At the opposite of I2C_CheckEvent() function, this function allows user to
+ * choose when an event is accepted (when all events flags are set and no
+ * other flags are set or just when the needed flags are set like
+ * I2C_CheckEvent() function).
+ * - Limitations:
+ * - User may need to define his own events.
+ * - Same remark concerning the error management is applicable for this
+ * function if user decides to check only regular communication flags (and
+ * ignores error flags).
+ *
+ *
+ * 3) Flag-based state monitoring:
+ * Using the function I2C_GetFlag() which simply returns the status of
+ * one single flag (ie. I2C_FLAG_RXDATNE ...).
+ * - When to use:
+ * - This function could be used for specific applications or in debug phase.
+ * - It is suitable when only one flag checking is needed (most I2C events
+ * are monitored through multiple flags).
+ * - Limitations:
+ * - When calling this function, the Status register is accessed. Some flags are
+ * cleared when the status register is accessed. So checking the status
+ * of one Flag, may clear other ones.
+ * - Function may need to be called twice or more in order to monitor one
+ * single event.
+ *
+ */
+
+/**
+ *
+ * 1) Basic state monitoring
+ *******************************************************************************
+ */
+ErrorStatus I2C_CheckEvent(I2C_Module* I2Cx, uint32_t I2C_EVENT);
+/**
+ *
+ * 2) Advanced state monitoring
+ *******************************************************************************
+ */
+uint32_t I2C_GetLastEvent(I2C_Module* I2Cx);
+/**
+ *
+ * 3) Flag-based state monitoring
+ *******************************************************************************
+ */
+FlagStatus I2C_GetFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG);
+/**
+ *
+ *******************************************************************************
+ */
+
+void I2C_ClrFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG);
+INTStatus I2C_GetIntStatus(I2C_Module* I2Cx, uint32_t I2C_IT);
+void I2C_ClrIntPendingBit(I2C_Module* I2Cx, uint32_t I2C_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32G43X_I2C_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_iwdg.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_iwdg.h
new file mode 100644
index 0000000000..200c3c53ac
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_iwdg.h
@@ -0,0 +1,145 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_iwdg.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_IWDG_H__
+#define __N32G43X_IWDG_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup IWDG
+ * @{
+ */
+
+/** @addtogroup IWDG_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup IWDG_WriteAccess
+ * @{
+ */
+
+#define IWDG_WRITE_ENABLE ((uint16_t)0x5555)
+#define IWDG_WRITE_DISABLE ((uint16_t)0x0000)
+#define IS_IWDG_WRITE(ACCESS) (((ACCESS) == IWDG_WRITE_ENABLE) || ((ACCESS) == IWDG_WRITE_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_prescaler
+ * @{
+ */
+
+#define IWDG_PRESCALER_DIV4 ((uint8_t)0x00)
+#define IWDG_PRESCALER_DIV8 ((uint8_t)0x01)
+#define IWDG_PRESCALER_DIV16 ((uint8_t)0x02)
+#define IWDG_PRESCALER_DIV32 ((uint8_t)0x03)
+#define IWDG_PRESCALER_DIV64 ((uint8_t)0x04)
+#define IWDG_PRESCALER_DIV128 ((uint8_t)0x05)
+#define IWDG_PRESCALER_DIV256 ((uint8_t)0x06)
+#define IS_IWDG_PRESCALER_DIV(PRESCALER) \
+ (((PRESCALER) == IWDG_PRESCALER_DIV4) || ((PRESCALER) == IWDG_PRESCALER_DIV8) \
+ || ((PRESCALER) == IWDG_PRESCALER_DIV16) || ((PRESCALER) == IWDG_PRESCALER_DIV32) \
+ || ((PRESCALER) == IWDG_PRESCALER_DIV64) || ((PRESCALER) == IWDG_PRESCALER_DIV128) \
+ || ((PRESCALER) == IWDG_PRESCALER_DIV256))
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Flag
+ * @{
+ */
+
+#define IWDG_PVU_FLAG ((uint16_t)0x0001)
+#define IWDG_CRVU_FLAG ((uint16_t)0x0002)
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_PVU_FLAG) || ((FLAG) == IWDG_CRVU_FLAG))
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Exported_Functions
+ * @{
+ */
+
+void IWDG_WriteConfig(uint16_t IWDG_WriteAccess);
+void IWDG_SetPrescalerDiv(uint8_t IWDG_Prescaler);
+void IWDG_CntReload(uint16_t Reload);
+void IWDG_ReloadKey(void);
+void IWDG_Enable(void);
+FlagStatus IWDG_GetStatus(uint16_t IWDG_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32G43X_IWDG_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_lptim.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_lptim.h
new file mode 100644
index 0000000000..f63d7b149a
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_lptim.h
@@ -0,0 +1,427 @@
+/** ----------------------------------------------------------------------------
+ * Nationz Technology Software Support - NATIONZ -
+ * -----------------------------------------------------------------------------
+ * Copyright (c) 2022, Nationz Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaiimer below.
+ *
+ * - Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the disclaimer below in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * Nationz's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * -----------------------------------------------------------------------------
+ */
+/** ****************************************************************************
+ * @copyright Nationz Co.,Ltd
+ * Copyright (c) 2019 All Rights Reserved
+ *******************************************************************************
+ * @file n32g43x_lptim.h
+ * @author
+ * @date
+ * @version v1.2.0
+ * @brief
+ ******************************************************************************/
+#ifndef __n32g43x_LPTIM_H
+#define __n32g43x_LPTIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "n32g43x.h"
+
+/** @addtogroup n32g43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup LPTIM
+ * @{
+ */
+
+//#if defined (LPTIM)
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup LPTIM_ES_INIT LPTIM Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief LPTIM Init structure definition
+ */
+typedef struct
+{
+ uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
+ This parameter can be a value of @ref LPTIM_EC_CLK_SOURCE.
+
+ This feature can be modified afterwards using unitary function @ref LPTIM_SetClockSource().*/
+
+ uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
+ This parameter can be a value of @ref LPTIM_EC_PRESCALER.
+
+ This feature can be modified afterwards using using unitary function @ref LPTIM_SetPrescaler().*/
+
+ uint32_t Waveform; /*!< Specifies the waveform shape.
+ This parameter can be a value of @ref LPTIM_EC_OUTPUT_WAVEFORM.
+
+ This feature can be modified afterwards using unitary function @ref LPTIM_ConfigOutput().*/
+
+ uint32_t Polarity; /*!< Specifies waveform polarity.
+ This parameter can be a value of @ref LPTIM_EC_OUTPUT_POLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LPTIM_ConfigOutput().*/
+} LPTIM_InitType;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
+ * @{
+ */
+
+/** @defgroup LPTIM_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LPTIM_ReadReg function
+ * @{
+ */
+#define LPTIM_INTSTS_CMPM_FLAG LPTIM_INTSTS_CMPM /*!< Compare match */
+#define LPTIM_INTSTS_ARRM_FLAG LPTIM_INTSTS_ARRM /*!< Autoreload match */
+#define LPTIM_INTSTS_EXTRIG_FLAG LPTIM_INTSTS_EXTRIG /*!< External trigger edge event */
+#define LPTIM_INTSTS_CMPUPD_FLAG LPTIM_INTSTS_CMPUPD /*!< Compare register update OK */
+#define LPTIM_INTSTS_ARRUPD_FLAG LPTIM_INTSTS_ARRUPD /*!< Autoreload register update OK */
+#define LPTIM_INTSTS_UP_FLAG LPTIM_INTSTS_UP /*!< Counter direction change down to up */
+#define LPTIM_INTSTS_DOWN_FLAG LPTIM_INTSTS_DOWN /*!< Counter direction change up to down */
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_EC_IT IT Defines
+ * @brief IT defines which can be used with LPTIM_ReadReg and LPTIM_WriteReg functions
+ * @{
+ */
+#define LPTIM_INTEN_CMPMIE_ENABLE LPTIM_INTEN_CMPMIE /*!< Compare match Interrupt Enable */
+#define LPTIM_INTEN_ARRMIE_ENABLE LPTIM_INTEN_ARRMIE /*!< Autoreload match Interrupt Enable */
+#define LPTIM_INTEN_EXTRIGIE_ENABLE LPTIM_INTEN_EXTRIGIE /*!< External trigger valid edge Interrupt Enable */
+#define LPTIM_INTEN_CMPUPDIE_ENABLE LPTIM_INTEN_CMPUPDIE /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_INTEN_ARRUPDIE_ENABLE LPTIM_INTEN_ARRUPDIE /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_INTEN_UPIE_ENABLE LPTIM_INTEN_UPIE /*!< Direction change to UP Interrupt Enable */
+#define LPTIM_INTEN_DOWNIE_ENABLE LPTIM_INTEN_DOWNIE /*!< Direction change to down Interrupt Enable */
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_EC_OPERATING_MODE Operating Mode
+ * @{
+ */
+#define LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CTRL_TSTCM /*!(__REG__), (__VALUE__))
+
+/**
+ * @brief Read a value in LPTIM register
+ * @param __INSTANCE__ LPTIM Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->(__REG__))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
+ * @{
+ */
+
+/** @defgroup LPTIM_EF_Init Initialisation and deinitialisation functions
+ * @{
+ */
+
+void LPTIM_DeInit(LPTIM_Module *LPTIMx);
+void LPTIM_StructInit(LPTIM_InitType *LPTIM_InitStruct);
+ErrorStatus LPTIM_Init(LPTIM_Module *LPTIMx, LPTIM_InitType *LPTIM_InitStruct);
+void LPTIM_Disable(LPTIM_Module *LPTIMx);
+
+
+
+void LPTIM_Enable(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabled(LPTIM_Module *LPTIMx);
+void LPTIM_StartCounter(LPTIM_Module *LPTIMx, uint32_t OperatingMode);
+void LPTIM_SetUpdateMode(LPTIM_Module *LPTIMx, uint32_t UpdateMode);
+uint32_t LPTIM_GetUpdateMode(LPTIM_Module *LPTIMx);
+void LPTIM_SetAutoReload(LPTIM_Module *LPTIMx, uint32_t AutoReload);
+uint32_t LPTIM_GetAutoReload(LPTIM_Module *LPTIMx);
+void LPTIM_SetCompare(LPTIM_Module *LPTIMx, uint32_t CompareValue);
+uint32_t LPTIM_GetCompare(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_GetCounter(LPTIM_Module *LPTIMx);
+void LPTIM_SetCounterMode(LPTIM_Module *LPTIMx, uint32_t CounterMode);
+uint32_t LPTIM_GetCounterMode(LPTIM_Module *LPTIMx);
+void LPTIM_ConfigOutput(LPTIM_Module *LPTIMx, uint32_t Waveform, uint32_t Polarity);
+void LPTIM_SetWaveform(LPTIM_Module *LPTIMx, uint32_t Waveform);
+uint32_t LPTIM_GetWaveform(LPTIM_Module *LPTIMx);
+void LPTIM_SetPolarity(LPTIM_Module *LPTIMx, uint32_t Polarity);
+uint32_t LPTIM_GetPolarity(LPTIM_Module *LPTIMx);
+void LPTIM_SetPrescaler(LPTIM_Module *LPTIMx, uint32_t Prescaler);
+uint32_t LPTIM_GetPrescaler(LPTIM_Module *LPTIMx);
+void LPTIM_EnableTimeout(LPTIM_Module *LPTIMx);
+void LPTIM_DisableTimeout(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledTimeout(LPTIM_Module *LPTIMx);
+void LPTIM_TrigSw(LPTIM_Module *LPTIMx);
+void LPTIM_ConfigTrigger(LPTIM_Module *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity);
+uint32_t LPTIM_GetTriggerSource(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_GetTriggerFilter(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_GetTriggerPolarity(LPTIM_Module *LPTIMx);
+void LPTIM_SetClockSource(LPTIM_Module *LPTIMx, uint32_t ClockSource);
+uint32_t LPTIM_GetClockSource(LPTIM_Module *LPTIMx);
+void LPTIM_ConfigClock(LPTIM_Module *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity);
+uint32_t LPTIM_GetClockPolarity(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_GetClockFilter(LPTIM_Module *LPTIMx);
+void LPTIM_SetEncoderMode(LPTIM_Module *LPTIMx, uint32_t EncoderMode);
+uint32_t LPTIM_GetEncoderMode(LPTIM_Module *LPTIMx);
+void LPTIM_EnableEncoderMode(LPTIM_Module *LPTIMx);
+void LPTIM_DisableEncoderMode(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledEncoderMode(LPTIM_Module *LPTIMx);
+void LPTIM_ClearFLAG_CMPM(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsActiveFlag_CMPM(LPTIM_Module *LPTIMx);
+void LPTIM_ClearFLAG_ARRM(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsActiveFlag_ARRM(LPTIM_Module *LPTIMx);
+void LPTIM_ClearFlag_EXTTRIG(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsActiveFlag_EXTTRIG(LPTIM_Module *LPTIMx);
+void LPTIM_ClearFlag_CMPOK(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsActiveFlag_CMPOK(LPTIM_Module *LPTIMx);
+void LPTIM_ClearFlag_ARROK(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsActiveFlag_ARROK(LPTIM_Module *LPTIMx);
+void LPTIM_ClearFlag_UP(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsActiveFlag_UP(LPTIM_Module *LPTIMx);
+void LPTIM_ClearFlag_DOWN(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsActiveFlag_DOWN(LPTIM_Module *LPTIMx);
+void LPTIM_EnableIT_CMPM(LPTIM_Module *LPTIMx);
+void LPTIM_DisableIT_CMPM(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledIT_CMPM(LPTIM_Module *LPTIMx);
+void LPTIM_EnableIT_ARRM(LPTIM_Module *LPTIMx);
+void LPTIM_DisableIT_ARRM(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledIT_ARRM(LPTIM_Module *LPTIMx);
+void LPTIM_EnableIT_EXTTRIG(LPTIM_Module *LPTIMx);
+void LPTIM_DisableIT_EXTTRIG(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledIT_EXTTRIG(LPTIM_Module *LPTIMx);
+void LPTIM_EnableIT_CMPOK(LPTIM_Module *LPTIMx);
+void LPTIM_DisableIT_CMPOK(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledIT_CMPOK(LPTIM_Module *LPTIMx);
+void LPTIM_EnableIT_ARROK(LPTIM_Module *LPTIMx);
+void LPTIM_DisableIT_ARROK(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledIT_ARROK(LPTIM_Module *LPTIMx);
+void LPTIM_EnableIT_UP(LPTIM_Module *LPTIMx);
+void LPTIM_DisableIT_UP(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledIT_UP(LPTIM_Module *LPTIMx);
+void LPTIM_EnableIT_DOWN(LPTIM_Module *LPTIMx);
+void LPTIM_DisableIT_DOWN(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledIT_DOWN(LPTIM_Module *LPTIMx);
+void LPTIM_EnableNoEncoderMode(LPTIM_Module *LPTIMx);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+//#endif /* LPTIM */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __n32g43x_LPTIM_H */
+
+/******************* (C) COPYRIGHT 2019 NATIONZ *****END OF FILE****/
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_lpuart.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_lpuart.h
new file mode 100644
index 0000000000..be1ce1c2d6
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_lpuart.h
@@ -0,0 +1,280 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_lpuart.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43x_LPUART_H__
+#define __N32G43x_LPUART_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup LPUART
+ * @{
+ */
+
+/** @addtogroup LPUART_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief LPUART Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the LPUART communication baud rate.
+ The baud rate is computed using the following formula:
+ - IntegerDivider = ((CLK) / (LPUART_InitStruct->BaudRate)))
+ - FractionalDivider */
+
+ uint16_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (only support
+ 8 data bits). */
+
+ uint16_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref Mode */
+
+ uint16_t RtsThreshold; /* Specifies RTS Threshold.
+ This parameter can be a value of @ref RtsThreshold */
+
+ uint16_t HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
+ or disabled.
+ This parameter can be a value of @ref LPUART_Hardware_Flow_Control */
+} LPUART_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup Parity
+ * @{
+ */
+
+#define LPUART_PE_NO ((uint16_t)0x0008)
+#define LPUART_PE_EVEN ((uint16_t)0x0000)
+#define LPUART_PE_ODD ((uint16_t)0x0001)
+#define IS_LPUART_PARITY(PARITY) (((PARITY) == LPUART_PE_NO) || ((PARITY) == LPUART_PE_EVEN) || ((PARITY) == LPUART_PE_ODD))
+/**
+ * @}
+ */
+
+/** @addtogroup Mode
+ * @{
+ */
+
+#define LPUART_MODE_RX ((uint16_t)0x0000)
+#define LPUART_MODE_TX ((uint16_t)0x0002)
+#define IS_LPUART_MODE(MODE) (((MODE) == LPUART_MODE_RX) || ((MODE) == LPUART_MODE_TX))
+/**
+ * @}
+ */
+
+/** @addtogroup RtsThreshold
+ * @{
+ */
+
+#define LPUART_RTSTH_FIFOHF ((uint16_t)0x0000)
+#define LPUART_RTSTH_FIFO3QF ((uint16_t)0x0100)
+#define LPUART_RTSTH_FIFOFU ((uint16_t)0x0200)
+#define IS_LPUART_RTSTHRESHOLD(RTSTHRESHOLD) \
+ (((RTSTHRESHOLD) == LPUART_RTSTH_FIFOHF) || ((RTSTHRESHOLD) == LPUART_RTSTH_FIFO3QF) || ((RTSTHRESHOLD) == LPUART_RTSTH_FIFOFU))
+/**
+ * @}
+ */
+
+/** @addtogroup Hardware_Flow_Control
+ * @{
+ */
+#define LPUART_HFCTRL_NONE ((uint16_t)0x0000)
+#define LPUART_HFCTRL_CTS ((uint16_t)0x0400)
+#define LPUART_HFCTRL_RTS ((uint16_t)0x0800)
+#define LPUART_HFCTRL_RTS_CTS ((uint16_t)0x0C00)
+#define IS_LPUART_HARDWARE_FLOW_CONTROL(CONTROL) \
+ (((CONTROL) == LPUART_HFCTRL_NONE) || ((CONTROL) == LPUART_HFCTRL_RTS) || ((CONTROL) == LPUART_HFCTRL_CTS) \
+ || ((CONTROL) == LPUART_HFCTRL_RTS_CTS))
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Interrupt_definition
+ * @{
+ */
+
+#define LPUART_INT_PE ((uint16_t)0x0001)
+#define LPUART_INT_TXC ((uint16_t)0x0102)
+#define LPUART_INT_FIFO_OV ((uint16_t)0x0204)
+#define LPUART_INT_FIFO_FU ((uint16_t)0x0308)
+#define LPUART_INT_FIFO_HF ((uint16_t)0x0410)
+#define LPUART_INT_FIFO_NE ((uint16_t)0x0520)
+#define LPUART_INT_WUF ((uint16_t)0x0640)
+#define IS_LPUART_CFG_INT(IT) \
+ (((IT) == LPUART_INT_PE) || ((IT) == LPUART_INT_TXC) || ((IT) == LPUART_INT_FIFO_OV) || ((IT) == LPUART_INT_FIFO_FU) \
+ || ((IT) == LPUART_INT_FIFO_HF) || ((IT) == LPUART_INT_FIFO_NE) || ((IT) == LPUART_INT_WUF))
+#define IS_LPUART_GET_INT(IT) \
+ (((IT) == LPUART_INT_PE) || ((IT) == LPUART_INT_TXC) || ((IT) == LPUART_INT_FIFO_OV) || ((IT) == LPUART_INT_FIFO_FU) \
+ || ((IT) == LPUART_INT_FIFO_HF) || ((IT) == LPUART_INT_FIFO_NE) || ((IT) == LPUART_INT_WUF))
+#define IS_LPUART_CLR_INT(IT) \
+ (((IT) == LPUART_INT_PE) || ((IT) == LPUART_INT_TXC) || ((IT) == LPUART_INT_FIFO_OV) || ((IT) == LPUART_INT_FIFO_FU) \
+ || ((IT) == LPUART_INT_FIFO_HF) || ((IT) == LPUART_INT_FIFO_NE) || ((IT) == LPUART_INT_WUF))
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_DMA_Requests
+ * @{
+ */
+
+#define LPUART_DMAREQ_TX ((uint16_t)0x0020)
+#define LPUART_DMAREQ_RX ((uint16_t)0x0040)
+#define IS_LPUART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF9F) == (uint16_t)0x00) && ((DMAREQ) != (uint16_t)0x00))
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_WakeUp_methods
+ * @{
+ */
+
+#define LPUART_WUSTP_STARTBIT ((uint16_t)0x0000)
+#define LPUART_WUSTP_RXNE ((uint16_t)0x1000)
+#define LPUART_WUSTP_BYTE ((uint16_t)0x2000)
+#define LPUART_WUSTP_FRAME ((uint16_t)0x3000)
+#define IS_LPUART_WAKEUP(WAKEUP) \
+ (((WAKEUP) == LPUART_WUSTP_STARTBIT) || ((WAKEUP) == LPUART_WUSTP_RXNE) || ((WAKEUP) == LPUART_WUSTP_BYTE) || ((WAKEUP) == LPUART_WUSTP_FRAME))
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Sampling_methods
+ * @{
+ */
+
+#define LPUART_SMPCNT_3B ((uint16_t)0x0000)
+#define LPUART_SMPCNT_1B ((uint16_t)0x4000)
+#define IS_LPUART_SAMPLING(SAMPLING) (((SAMPLING) == LPUART_SMPCNT_1B) || ((SAMPLING) == LPUART_SMPCNT_3B))
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Flags
+ * @{
+ */
+
+#define LPUART_FLAG_PEF ((uint16_t)0x0001)
+#define LPUART_FLAG_TXC ((uint16_t)0x0002)
+#define LPUART_FLAG_FIFO_OV ((uint16_t)0x0004)
+#define LPUART_FLAG_FIFO_FU ((uint16_t)0x0008)
+#define LPUART_FLAG_FIFO_HF ((uint16_t)0x0010)
+#define LPUART_FLAG_FIFO_NE ((uint16_t)0x0020)
+#define LPUART_FLAG_CTS ((uint16_t)0x0040)
+#define LPUART_FLAG_WUF ((uint16_t)0x0080)
+#define LPUART_FLAG_NF ((uint16_t)0x0100)
+#define IS_LPUART_FLAG(FLAG) \
+ (((FLAG) == LPUART_FLAG_PEF) || ((FLAG) == LPUART_FLAG_TXC) || ((FLAG) == LPUART_FLAG_FIFO_OV) \
+ || ((FLAG) == LPUART_FLAG_FIFO_FU) || ((FLAG) == LPUART_FLAG_FIFO_HF) || ((FLAG) == LPUART_FLAG_FIFO_NE) \
+ || ((FLAG) == LPUART_FLAG_CTS) || ((FLAG) == LPUART_FLAG_WUF) || ((FLAG) == LPUART_FLAG_NF))
+
+#define IS_LPUART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFE40) == 0x00) && ((FLAG) != (uint16_t)0x00))
+
+#define IS_LPUART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x010000))
+
+#define IS_LPUART_DATA(DATA) ((DATA) <= 0xFF)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Exported_Functions
+ * @{
+ */
+
+void LPUART_DeInit(void);
+void LPUART_Init(LPUART_InitType* LPUART_InitStruct);
+void LPUART_StructInit(LPUART_InitType* LPUART_InitStruct);
+void LPUART_FlushRxFifo(void);
+void LPUART_ConfigInt(uint16_t LPUART_INT, FunctionalState Cmd);
+void LPUART_EnableDMA(uint16_t LPUART_DMAReq, FunctionalState Cmd);
+void LPUART_ConfigWakeUpMethod(uint16_t LPUART_WakeUpMethod);
+void LPUART_EnableWakeUpStop(FunctionalState Cmd);
+void LPUART_ConfigSamplingMethod(uint16_t LPUART_SamplingMethod);
+void LPUART_EnableLoopBack(FunctionalState Cmd);
+void LPUART_SendData(uint8_t Data);
+uint8_t LPUART_ReceiveData(void);
+void LPUART_ConfigWakeUpData(uint32_t LPUART_WakeUpData);
+FlagStatus LPUART_GetFlagStatus(uint16_t LPUART_FLAG);
+void LPUART_ClrFlag(uint16_t LPUART_FLAG);
+INTStatus LPUART_GetIntStatus(uint16_t LPUART_INT);
+void LPUART_ClrIntPendingBit(uint16_t LPART_INT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32G43x_LPUART_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_opamp.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_opamp.h
new file mode 100644
index 0000000000..18e74b0c2b
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_opamp.h
@@ -0,0 +1,209 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_opamp.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_OPAMPMP_H__
+#define __N32G43X_OPAMPMP_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+#include
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup OPAMP
+ * @{
+ */
+
+/** @addtogroup OPAMP_Exported_Constants
+ * @{
+ */
+typedef enum
+{
+ OPAMP1 = 0,
+ OPAMP2 = 4,
+} OPAMPX;
+
+// OPAMP_CS
+typedef enum
+{
+ OPAMP2_CS_TIMSRCSEL_TIM1CC6 = (0x0L << 24),
+ OPAMP2_CS_TIMSRCSEL_TIM8CC6 = (0x1L << 24),
+}OPAMP2_CS_TIMSRCSEL;
+typedef enum
+{
+ OPAMP1_CS_VPSSEL_PA1 = (0x00L << 19),
+ OPAMP1_CS_VPSSEL_PA5 = (0x01L << 19),
+ OPAMP1_CS_VPSSEL_PA4 = (0x02L << 19),
+ OPAMP1_CS_VPSSEL_PA7 = (0x03L << 19),
+ OPAMP1_CS_VPSSEL_NC = (0x04L << 19),
+
+ OPAMP2_CS_VPSSEL_PA7 = (0x00L << 19),
+ OPAMP2_CS_VPSSEL_PA4 = (0x01L << 19),
+ OPAMP2_CS_VPSSEL_PB14 = (0x02L << 19),
+ OPAMP2_CS_VPSSEL_PD13 = (0x03L << 19),
+ OPAMP2_CS_VPSSEL_NC = (0x04L << 19),
+} OPAMP_CS_VPSSEL;
+typedef enum
+{
+ OPAMP1_CS_VMSSEL_PA3 = (0x00L << 17),
+ OPAMP1_CS_VMSSEL_PC5 = (0x01L << 17),
+ OPAMP1_CS_VMSSEL_NC = (0x02L << 17),
+ OPAMP1_CS_VMSSEL_FLOAT = (0x03L << 17),
+
+ OPAMP2_CS_VMSSEL_PC5 = (0x00L << 17),
+ OPAMP2_CS_VMSSEL_PB0 = (0x01L << 17),
+ OPAMP2_CS_VMSSEL_PA5 = (0x02L << 17),
+ OPAMP2_CS_VMSSEL_FLOAT = (0x03L << 17),
+} OPAMP_CS_VMSSEL;
+
+typedef enum
+{
+ OPAMP1_CS_VPSEL_PA1 = (0x00L << 8),
+ OPAMP1_CS_VPSEL_PA5 = (0x01L << 8),
+ OPAMP1_CS_VPSEL_PA4 = (0x02L << 8),
+ OPAMP1_CS_VPSEL_PA7 = (0x03L << 8),
+ OPAMP1_CS_VPSEL_NC = (0x04L << 8),
+
+ OPAMP2_CS_VPSEL_PA7 = (0x00L << 8),
+ OPAMP2_CS_VPSEL_PA4 = (0x01L << 8),
+ OPAMP2_CS_VPSEL_PB14 = (0x02L << 8),
+ OPAMP2_CS_VPSEL_PD13 = (0x03L << 8),
+ OPAMP2_CS_VPSEL_NC = (0x04L << 8),
+} OPAMP_CS_VPSEL;
+typedef enum
+{
+ OPAMP1_CS_VMSEL_PA3 = (0x00L << 6),
+ OPAMP1_CS_VMSEL_PC5 = (0x01L << 6),
+ OPAMPx_CS_VMSEL_NC = (0x02L << 6),
+ OPAMPx_CS_VMSEL_FLOAT = (0x03L << 6),
+
+ OPAMP2_CS_VMSEL_PC5 = (0x00L << 6),
+ OPAMP2_CS_VMSEL_PB0 = (0x01L << 6),
+ OPAMP2_CS_VMSEL_PA5 = (0x02L << 6),
+ OPAMP2_CS_VMSEL_FLOAT = (0x03L << 6),
+} OPAMP_CS_VMSEL;
+typedef enum
+{
+ OPAMP_CS_PGA_GAIN_2 = (0x00 << 3),
+ OPAMP_CS_PGA_GAIN_4 = (0x01 << 3),
+ OPAMP_CS_PGA_GAIN_8 = (0x02 << 3),
+ OPAMP_CS_PGA_GAIN_16 = (0x03 << 3),
+ OPAMP_CS_PGA_GAIN_32 = (0x04 << 3),
+} OPAMP_CS_PGA_GAIN;
+typedef enum
+{
+ OPAMP_CS_EXT_OPAMP = (0x00 << 1),
+ OPAMP_CS_PGA_EN = (0x02 << 1),
+ OPAMP_CS_FOLLOW = (0x03 << 1),
+} OPAMP_CS_MOD;
+
+// bit mask
+#define OPAMP_CS_EN_MASK (0x01L << 0)
+#define OPAMP_CS_MOD_MASK (0x03L << 1)
+#define OPAMP_CS_PGA_GAIN_MASK (0x07L << 3)
+#define OPAMP_CS_VMSEL_MASK (0x03L << 6)
+#define OPAMP_CS_VPSEL_MASK (0x07L << 8)
+#define OPAMP_CS_CALON_MASK (0x01L << 11)
+#define OPAMP_CS_TSTREF_MASK (0x01L << 13)
+#define OPAMP_CS_CALOUT_MASK (0x01L << 14)
+#define OPAMP_CS_RANGE_MASK (0x01L << 15)
+#define OPAMP_CS_TCMEN_MASK (0x01L << 16)
+#define OPAMP_CS_VMSEL_SECOND_MASK (0x03L << 17)
+#define OPAMP_CS_VPSEL_SECOND_MASK (0x07L << 19)
+#define OPAMP_CS_OPAMP2_TIMSRCSEL (0x01L << 24)
+/** @addtogroup OPAMP_LOCK
+ * @{
+ */
+#define OPAMP_LOCK_1 0x01L
+#define OPAMP_LOCK_2 0x02L
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/**
+ * @brief OPAMP Init structure definition
+ */
+
+typedef struct
+{
+ OPAMP2_CS_TIMSRCSEL Opa2SrcSel; /*only for opa2 can sel,opa1 always TIM1_CC6*/
+
+ FunctionalState TimeAutoMuxEn; /*call ENABLE or DISABLE */
+
+ FunctionalState HighVolRangeEn; /*call ENABLE or DISABLE ,low range VDDA < 2.4V,high range VDDA >= 2.4V*/
+
+ OPAMP_CS_PGA_GAIN Gain; /*see @EM_PGA_GAIN */
+
+ OPAMP_CS_MOD Mod; /*see @EM_OPAMP_MOD*/
+} OPAMP_InitType;
+
+/** @addtogroup OPAMP_Exported_Functions
+ * @{
+ */
+
+void OPAMP_DeInit(void);
+void OPAMP_StructInit(OPAMP_InitType* OPAMP_InitStruct);
+void OPAMP_Init(OPAMPX OPAMPx, OPAMP_InitType* OPAMP_InitStruct);
+void OPAMP_Enable(OPAMPX OPAMPx, FunctionalState en);
+void OPAMP_SetPgaGain(OPAMPX OPAMPx, OPAMP_CS_PGA_GAIN Gain);
+void OPAMP_SetVpSecondSel(OPAMPX OPAMPx, OPAMP_CS_VPSSEL VpSSel);
+void OPAMP_SetVmSecondSel(OPAMPX OPAMPx, OPAMP_CS_VMSSEL VmSSel);
+void OPAMP_SetVpSel(OPAMPX OPAMPx, OPAMP_CS_VPSEL VpSel);
+void OPAMP_SetVmSel(OPAMPX OPAMPx, OPAMP_CS_VMSEL VmSel);
+bool OPAMP_IsCalOutHigh(OPAMPX OPAMPx);
+void OPAMP_CalibrationEnable(OPAMPX OPAMPx, FunctionalState en);
+void OPAMP_SetLock(uint32_t Lock); // see @OPAMP_LOCK
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32G43X_ADC_H */
+ /**
+ * @}
+ */
+ /**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_pwr.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_pwr.h
new file mode 100644
index 0000000000..3cfa78e65f
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_pwr.h
@@ -0,0 +1,222 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_pwr.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43x_PWR_H__
+#define __N32G43x_PWR_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup PWR
+ * @{
+ */
+
+/** @addtogroup PWR_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup PVD_detection_level
+ * @{
+ */
+
+#define PWR_PVDLEVEL_2V1 ((uint32_t)0x00000000)
+#define PWR_PVDLEVEL_2V25 ((uint32_t)0x0000002)
+#define PWR_PVDLEVEL_2V4 ((uint32_t)0x0000004)
+#define PWR_PVDLEVEL_2V55 ((uint32_t)0x0000006)
+#define PWR_PVDLEVEL_2V7 ((uint32_t)0x0000008)
+#define PWR_PVDLEVEL_2V85 ((uint32_t)0x000000A)
+#define PWR_PVDLEVEL_2V95 ((uint32_t)0x000000C)
+#define PWR_PVDLEVEL_IN ((uint32_t)0x000000E)
+
+
+#define IS_PWR_PVD_LEVEL(LEVEL) \
+ (((LEVEL) == PWR_PVDLEVEL_2V1) || ((LEVEL) == PWR_PVDLEVEL_2V25) || ((LEVEL) == PWR_PVDLEVEL_2V4) \
+ || ((LEVEL) == PWR_PVDLEVEL_2V55) || ((LEVEL) == PWR_PVDLEVEL_2V7) || ((LEVEL) == PWR_PVDLEVEL_2V85) \
+ || ((LEVEL) == PWR_PVDLEVEL_2V95) || ((LEVEL) == PWR_PVDLEVEL_IN) )
+
+/**
+ * @}
+ */
+
+/** @addtogroup Regulator_state_is_STOP_mode
+ * @{
+ */
+
+#define PWR_REGULATOR_ON ((uint32_t)0x00000000)
+#define PWR_REGULATOR_LOWPOWER ((uint32_t)0x00000001)
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_REGULATOR_ON) || ((REGULATOR) == PWR_REGULATOR_LOWPOWER))
+/**
+ * @}
+ */
+
+/** @defgroup SLEEP_mode_entry
+ * @{
+ */
+#define SLEEP_ON_EXIT (1)
+#define SLEEP_OFF_EXIT (0)
+#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
+#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
+
+
+/**
+ * @}
+ */
+
+
+/** @defgroup STOP_mode_entry
+ * @{
+ */
+
+#define PWR_STOPENTRY_WFI ((uint8_t)0x01)
+#define PWR_STOPENTRY_WFE ((uint8_t)0x02)
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Flag
+ * @{
+ */
+//STS1
+#define PWR_WKUP0_FLAG ((uint32_t)0x00000001)
+#define PWR_WKUP1_FLAG ((uint32_t)0x00000002)
+#define PWR_WKUP2_FLAG ((uint32_t)0x00000004)
+#define PWR_STBY_FLAG ((uint32_t)0x00000100)
+//STS2
+#define PWR_LPRUN_FLAG ((uint32_t)0x00000001)
+#define PWR_MR_FLAG ((uint32_t)0x00000002)
+#define PWR_PVDO_FLAG ((uint32_t)0x00000004)
+
+#define IS_PWR_GET_FLAG(FLAG) \
+ (((FLAG) == PWR_WKUP0_FLAG) || ((FLAG) == PWR_WKUP1_FLAG) || ((FLAG) == PWR_WKUP2_FLAG) || ((FLAG) == PWR_STBY_FLAG)\
+ || ((FLAG) == PWR_LPRUN_FLAG) || ((FLAG) == PWR_MR_FLAG) || ((FLAG) == PWR_PVDO_FLAG))
+
+#define IS_PWR_CLEAR_FLAG(FLAG) \
+ (((FLAG) == PWR_WKUP0_FLAG) || ((FLAG) == PWR_WKUP1_FLAG) || ((FLAG) == PWR_WKUP2_FLAG) || ((FLAG) == PWR_STBY_FLAG)\
+ || ((FLAG) == PWR_LPRUN_FLAG) || ((FLAG) == PWR_MR_FLAG) || ((FLAG) == PWR_PVDO_FLAG))
+
+
+
+/** @addtogroup SRAM1 SRAM2 retention set
+ * @{
+ */
+//#define SRAM1DIS_SRAM2DIS 0
+//#define SRAM1EN_SRAM2DIS 1
+
+//#define SRAM1DIS_SRAM2EN 2
+//#define SRAM1EN_SRAM2EN 3
+/** @addtogroup MR VOLTAGE
+ * @{
+ */
+#define MR_1V0 2
+#define MR_1V1 3
+
+
+/**
+ * @}
+ */
+typedef enum
+{
+ WAKEUP_PIN0 = 0x0001,
+ WAKEUP_PIN1 = 0x0002,
+ WAKEUP_PIN2 = 0x0004,
+} WAKEUP_PINX;
+/** @addtogroup PWR_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+#define LPRUN_SRAM_ADDR (__IO unsigned*)(0x40001800 + 0x20)
+#define CLERR_BIT25 0xfdffffff //bit25
+#define _SetLprunSramVoltage(vale) do{(*LPRUN_SRAM_ADDR) &= CLERR_BIT25;(*LPRUN_SRAM_ADDR) |= (uint32_t)(vale <<25);}while (0) //0:0.9V 1:1.1V
+#define _SetBandGapMode(vale) do{PWR->CTRL3 &= (~PWR_CTRL3_BGDTLPR);PWR->CTRL3 |= (uint32_t)(vale <<8);}while (0) //0:always on 1:duty on
+#define _SetPvdBorMode(vale) do{PWR->CTRL3 &= (~PWR_CTRL3_PBDTLPR);PWR->CTRL3 |= (uint32_t)(vale <<16);}while (0) //0:normal mode 1:standby mode
+/** @addtogroup PWR_Exported_Functions
+ * @{
+ */
+
+void PWR_DeInit(void);
+void PWR_BackupAccessEnable(FunctionalState Cmd);
+void PWR_PvdEnable(FunctionalState Cmd);
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
+void PWR_WakeUpPinEnable(WAKEUP_PINX WKUP_Pin,FunctionalState Cmd);
+void PWR_EnterStopState(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+void PWR_EnterSLEEPMode(uint8_t SLEEPONEXIT, uint8_t PWR_STOPEntry);
+void PWR_EnterSTOP2Mode(uint8_t PWR_STOPEntry,uint32_t RetentionMode);
+void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry,uint32_t Sam2Ret);
+void PWR_EnterLowPowerRunMode(void);
+void PWR_ExitLowPowerRunMode(void);
+void PWR_EnterLowPowerSleepMode(uint8_t SLEEPONEXIT, uint8_t PWR_SLEEPEntry);
+
+FlagStatus PWR_GetFlagStatus(uint8_t STS, uint32_t PWR_FLAG);
+void PWR_ClearFlag(uint32_t PWR_FLAG);
+void PWR_WakeUpPinConfig(void);
+void SetSysClock_MSI(void);
+uint8_t GetMrVoltage(void);
+void PWR_MRconfig(uint8_t voltage);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32G43x_PWR_H__ */
+ /**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_rcc.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_rcc.h
new file mode 100644
index 0000000000..329b2a7495
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_rcc.h
@@ -0,0 +1,911 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_rcc.h
+ * @author Nations
+ * @version V1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_RCC_H__
+#define __N32G43X_RCC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RCC
+ * @{
+ */
+
+/** @addtogroup RCC_Exported_Types
+ * @{
+ */
+
+typedef struct
+{
+ uint32_t SysclkFreq; /*!< returns SYSCLK clock frequency expressed in Hz */
+ uint32_t HclkFreq; /*!< returns HCLK clock frequency expressed in Hz */
+ uint32_t Pclk1Freq; /*!< returns PCLK1 clock frequency expressed in Hz */
+ uint32_t Pclk2Freq; /*!< returns PCLK2 clock frequency expressed in Hz */
+ uint32_t AdcPllClkFreq; /*!< returns ADCPLLCLK clock frequency expressed in Hz */
+ uint32_t AdcHclkFreq; /*!< returns ADCHCLK clock frequency expressed in Hz */
+} RCC_ClocksType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup HSE_configuration
+ * @{
+ */
+
+#define RCC_HSE_DISABLE ((uint32_t)0x00000000)
+#define RCC_HSE_ENABLE ((uint32_t)0x00010000)
+#define RCC_HSE_BYPASS ((uint32_t)0x00040000)
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_DISABLE) || ((HSE) == RCC_HSE_ENABLE) || ((HSE) == RCC_HSE_BYPASS))
+
+/**
+ * @}
+ */
+
+/** @addtogroup HSI_configuration
+ * @{
+ */
+
+#define RCC_HSI_DISABLE ((uint32_t)0x00000000)
+#define RCC_HSI_ENABLE ((uint32_t)0x00000001)
+#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_DISABLE) || ((HSI) == RCC_HSI_ENABLE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup MSI_configuration
+ * @{
+ */
+
+#define RCC_MSI_DISABLE ((uint32_t)0x00000000)
+#define RCC_MSI_ENABLE ((uint32_t)0x00000004)
+#define IS_RCC_MSI(MSI) (((MSI) == RCC_MSI_DISABLE) || ((MSI) == RCC_MSI_ENABLE))
+
+#define RCC_MSI_RANGE_100K ((uint32_t)0x00000000)
+#define RCC_MSI_RANGE_200K ((uint32_t)0x00000010)
+#define RCC_MSI_RANGE_400K ((uint32_t)0x00000020)
+#define RCC_MSI_RANGE_800K ((uint32_t)0x00000030)
+#define RCC_MSI_RANGE_1M ((uint32_t)0x00000040)
+#define RCC_MSI_RANGE_2M ((uint32_t)0x00000050)
+#define RCC_MSI_RANGE_4M ((uint32_t)0x00000060)
+#define IS_RCC_MSI_RANGE(MSI_RANGE) (((MSI_RANGE) == RCC_MSI_RANGE_100K) || ((MSI_RANGE) == RCC_MSI_RANGE_200K) \
+ || ((MSI_RANGE) == RCC_MSI_RANGE_400K) || ((MSI_RANGE) == RCC_MSI_RANGE_800K) \
+ || ((MSI_RANGE) == RCC_MSI_RANGE_1M) || ((MSI_RANGE) == RCC_MSI_RANGE_2M) \
+ || ((MSI_RANGE) == RCC_MSI_RANGE_4M) \
+ )
+
+/**
+ * @}
+ */
+
+/** @addtogroup PLL_entry_clock_source
+ * @{
+ */
+#define RCC_PLL_HSI_PRE_DIV1 ((uint32_t)0x00000000)
+#define RCC_PLL_HSI_PRE_DIV2 ((uint32_t)0x00000001)
+
+#define RCC_PLL_SRC_HSE_DIV1 ((uint32_t)0x00010000)
+#define RCC_PLL_SRC_HSE_DIV2 ((uint32_t)0x00030000)
+#define IS_RCC_PLL_SRC(SOURCE) \
+ (((SOURCE) == RCC_PLL_HSI_PRE_DIV1) || ((SOURCE) == RCC_PLL_HSI_PRE_DIV2) \
+ || ((SOURCE) == RCC_PLL_SRC_HSE_DIV1) || ((SOURCE) == RCC_PLL_SRC_HSE_DIV2))
+
+#define RCC_PLLDIVCLK_DISABLE ((uint32_t)0x00000000)
+#define RCC_PLLDIVCLK_ENABLE ((uint32_t)0x00000002)
+#define IS_RCC_PLL_DIVCLK(DIVCLK) \
+ (((DIVCLK) == RCC_PLLDIVCLK_DISABLE) || ((DIVCLK) == RCC_PLLDIVCLK_ENABLE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup PLL_multiplication_factor
+ * @{
+ */
+#define RCC_PLL_MUL_2 ((uint32_t)0x00000000)
+#define RCC_PLL_MUL_3 ((uint32_t)0x00040000)
+#define RCC_PLL_MUL_4 ((uint32_t)0x00080000)
+#define RCC_PLL_MUL_5 ((uint32_t)0x000C0000)
+#define RCC_PLL_MUL_6 ((uint32_t)0x00100000)
+#define RCC_PLL_MUL_7 ((uint32_t)0x00140000)
+#define RCC_PLL_MUL_8 ((uint32_t)0x00180000)
+#define RCC_PLL_MUL_9 ((uint32_t)0x001C0000)
+#define RCC_PLL_MUL_10 ((uint32_t)0x00200000)
+#define RCC_PLL_MUL_11 ((uint32_t)0x00240000)
+#define RCC_PLL_MUL_12 ((uint32_t)0x00280000)
+#define RCC_PLL_MUL_13 ((uint32_t)0x002C0000)
+#define RCC_PLL_MUL_14 ((uint32_t)0x00300000)
+#define RCC_PLL_MUL_15 ((uint32_t)0x00340000)
+#define RCC_PLL_MUL_16 ((uint32_t)0x00380000)
+#define RCC_PLL_MUL_17 ((uint32_t)0x08000000)
+#define RCC_PLL_MUL_18 ((uint32_t)0x08040000)
+#define RCC_PLL_MUL_19 ((uint32_t)0x08080000)
+#define RCC_PLL_MUL_20 ((uint32_t)0x080C0000)
+#define RCC_PLL_MUL_21 ((uint32_t)0x08100000)
+#define RCC_PLL_MUL_22 ((uint32_t)0x08140000)
+#define RCC_PLL_MUL_23 ((uint32_t)0x08180000)
+#define RCC_PLL_MUL_24 ((uint32_t)0x081C0000)
+#define RCC_PLL_MUL_25 ((uint32_t)0x08200000)
+#define RCC_PLL_MUL_26 ((uint32_t)0x08240000)
+#define RCC_PLL_MUL_27 ((uint32_t)0x08280000)
+#define RCC_PLL_MUL_28 ((uint32_t)0x082C0000)
+#define RCC_PLL_MUL_29 ((uint32_t)0x08300000)
+#define RCC_PLL_MUL_30 ((uint32_t)0x08340000)
+#define RCC_PLL_MUL_31 ((uint32_t)0x08380000)
+#define RCC_PLL_MUL_32 ((uint32_t)0x083C0000)
+#define IS_RCC_PLL_MUL(MUL) \
+ (((MUL) == RCC_PLL_MUL_2) || ((MUL) == RCC_PLL_MUL_3) || ((MUL) == RCC_PLL_MUL_4) || ((MUL) == RCC_PLL_MUL_5) \
+ || ((MUL) == RCC_PLL_MUL_6) || ((MUL) == RCC_PLL_MUL_7) || ((MUL) == RCC_PLL_MUL_8) || ((MUL) == RCC_PLL_MUL_9) \
+ || ((MUL) == RCC_PLL_MUL_10) || ((MUL) == RCC_PLL_MUL_11) || ((MUL) == RCC_PLL_MUL_12) \
+ || ((MUL) == RCC_PLL_MUL_13) || ((MUL) == RCC_PLL_MUL_14) || ((MUL) == RCC_PLL_MUL_15) \
+ || ((MUL) == RCC_PLL_MUL_16) || ((MUL) == RCC_PLL_MUL_17) || ((MUL) == RCC_PLL_MUL_18) \
+ || ((MUL) == RCC_PLL_MUL_19) || ((MUL) == RCC_PLL_MUL_20) || ((MUL) == RCC_PLL_MUL_21) \
+ || ((MUL) == RCC_PLL_MUL_22) || ((MUL) == RCC_PLL_MUL_23) || ((MUL) == RCC_PLL_MUL_24) \
+ || ((MUL) == RCC_PLL_MUL_25) || ((MUL) == RCC_PLL_MUL_26) || ((MUL) == RCC_PLL_MUL_27) \
+ || ((MUL) == RCC_PLL_MUL_28) || ((MUL) == RCC_PLL_MUL_29) || ((MUL) == RCC_PLL_MUL_30) \
+ || ((MUL) == RCC_PLL_MUL_31) || ((MUL) == RCC_PLL_MUL_32))
+
+/**
+ * @}
+ */
+
+/** @addtogroup System_clock_source
+ * @{
+ */
+
+#define RCC_SYSCLK_SRC_MSI ((uint32_t)0x00000000)
+#define RCC_SYSCLK_SRC_HSI ((uint32_t)0x00000001)
+#define RCC_SYSCLK_SRC_HSE ((uint32_t)0x00000002)
+#define RCC_SYSCLK_SRC_PLLCLK ((uint32_t)0x00000003)
+#define IS_RCC_SYSCLK_SRC(SOURCE) \
+ (((SOURCE) == RCC_SYSCLK_SRC_MSI) || ((SOURCE) == RCC_SYSCLK_SRC_HSI) \
+ || ((SOURCE) == RCC_SYSCLK_SRC_HSE) || ((SOURCE) == RCC_SYSCLK_SRC_PLLCLK))
+/**
+ * @}
+ */
+
+/** @addtogroup AHB_clock_source
+ * @{
+ */
+
+#define RCC_SYSCLK_DIV1 ((uint32_t)0x00000000)
+#define RCC_SYSCLK_DIV2 ((uint32_t)0x00000080)
+#define RCC_SYSCLK_DIV4 ((uint32_t)0x00000090)
+#define RCC_SYSCLK_DIV8 ((uint32_t)0x000000A0)
+#define RCC_SYSCLK_DIV16 ((uint32_t)0x000000B0)
+#define RCC_SYSCLK_DIV64 ((uint32_t)0x000000C0)
+#define RCC_SYSCLK_DIV128 ((uint32_t)0x000000D0)
+#define RCC_SYSCLK_DIV256 ((uint32_t)0x000000E0)
+#define RCC_SYSCLK_DIV512 ((uint32_t)0x000000F0)
+#define IS_RCC_SYSCLK_DIV(HCLK) \
+ (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || ((HCLK) == RCC_SYSCLK_DIV4) \
+ || ((HCLK) == RCC_SYSCLK_DIV8) || ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) \
+ || ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || ((HCLK) == RCC_SYSCLK_DIV512))
+/**
+ * @}
+ */
+
+/** @addtogroup APB1_APB2_clock_source
+ * @{
+ */
+
+#define RCC_HCLK_DIV1 ((uint32_t)0x00000000)
+#define RCC_HCLK_DIV2 ((uint32_t)0x00000400)
+#define RCC_HCLK_DIV4 ((uint32_t)0x00000500)
+#define RCC_HCLK_DIV8 ((uint32_t)0x00000600)
+#define RCC_HCLK_DIV16 ((uint32_t)0x00000700)
+#define IS_RCC_HCLK_DIV(PCLK) \
+ (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) \
+ || ((PCLK) == RCC_HCLK_DIV16))
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Interrupt_source
+ * @{
+ */
+
+#define RCC_INT_LSIRDIF ((uint8_t)0x01)
+#define RCC_INT_LSERDIF ((uint8_t)0x02)
+#define RCC_INT_HSIRDIF ((uint8_t)0x04)
+#define RCC_INT_HSERDIF ((uint8_t)0x08)
+#define RCC_INT_PLLRDIF ((uint8_t)0x10)
+#define RCC_INT_BORIF ((uint8_t)0x20)
+#define RCC_INT_MSIRDIF ((uint8_t)0x40)
+#define RCC_INT_CLKSSIF ((uint8_t)0x80)
+
+#define IS_RCC_INT(IT) \
+ (((IT) == RCC_INT_LSIRDIF) || ((IT) == RCC_INT_LSERDIF) || ((IT) == RCC_INT_HSIRDIF) || ((IT) == RCC_INT_HSERDIF) \
+ || ((IT) == RCC_INT_PLLRDIF) || ((IT) == RCC_INT_BORIF) || ((IT) == RCC_INT_MSIRDIF))
+
+#define IS_RCC_GET_INT(IT) \
+ (((IT) == RCC_INT_LSIRDIF) || ((IT) == RCC_INT_LSERDIF) || ((IT) == RCC_INT_HSIRDIF) || ((IT) == RCC_INT_HSERDIF) \
+ || ((IT) == RCC_INT_PLLRDIF) || ((IT) == RCC_INT_BORIF) || ((IT) == RCC_INT_MSIRDIF) || ((IT) == RCC_INT_CLKSSIF))
+
+#define RCC_CLR_MSIRDIF ((uint32_t)0x00008000)
+#define RCC_CLR_LSIRDIF ((uint32_t)0x00010000)
+#define RCC_CLR_LSERDIF ((uint32_t)0x00020000)
+#define RCC_CLR_HSIRDIF ((uint32_t)0x00040000)
+#define RCC_CLR_HSERDIF ((uint32_t)0x00080000)
+#define RCC_CLR_PLLRDIF ((uint32_t)0x00100000)
+#define RCC_CLR_BORIF ((uint32_t)0x00200000)
+#define RCC_CLR_CLKSSIF ((uint32_t)0x00800000)
+
+#define IS_RCC_CLR_INTF(IT) \
+ (((IT) == RCC_CLR_LSIRDIF) || ((IT) == RCC_CLR_LSERDIF) || ((IT) == RCC_CLR_HSIRDIF) || ((IT) == RCC_CLR_HSERDIF) \
+ || ((IT) == RCC_CLR_PLLRDIF) || ((IT) == RCC_CLR_BORIF) || ((IT) == RCC_CLR_MSIRDIF) || ((IT) == RCC_CLR_CLKSSIF))
+
+/**
+ * @}
+ */
+
+/** @addtogroup USB_Device_clock_source
+ * @{
+ */
+
+#define RCC_USBCLK_SRC_PLLCLK_DIV1_5 ((uint8_t)0x00)
+#define RCC_USBCLK_SRC_PLLCLK_DIV1 ((uint8_t)0x01)
+#define RCC_USBCLK_SRC_PLLCLK_DIV2 ((uint8_t)0x02)
+#define RCC_USBCLK_SRC_PLLCLK_DIV3 ((uint8_t)0x03)
+
+#define IS_RCC_USBCLK_SRC(SOURCE) \
+ (((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV1_5) || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV1) \
+ || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV2) || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV3))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_clock_source
+ * @{
+ */
+
+#define RCC_PCLK2_DIV2 ((uint32_t)0x00000000)
+#define RCC_PCLK2_DIV4 ((uint32_t)0x00004000)
+#define RCC_PCLK2_DIV6 ((uint32_t)0x00008000)
+#define RCC_PCLK2_DIV8 ((uint32_t)0x0000C000)
+#define IS_RCC_PCLK2_DIV(ADCCLK) \
+ (((ADCCLK) == RCC_PCLK2_DIV2) || ((ADCCLK) == RCC_PCLK2_DIV4) || ((ADCCLK) == RCC_PCLK2_DIV6) \
+ || ((ADCCLK) == RCC_PCLK2_DIV8))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_CFGR2_Config
+ * @{
+ */
+#define RCC_TIM18CLK_SRC_TIM18CLK ((uint32_t)0x00000000)
+#define RCC_TIM18CLK_SRC_SYSCLK ((uint32_t)0x20000000)
+#define IS_RCC_TIM18CLKSRC(TIM18CLK) \
+ (((TIM18CLK) == RCC_TIM18CLK_SRC_TIM18CLK) || ((TIM18CLK) == RCC_TIM18CLK_SRC_SYSCLK))
+
+#define RCC_RNGCCLK_SYSCLK_DIV1 ((uint32_t)0x00000000)
+#define RCC_RNGCCLK_SYSCLK_DIV2 ((uint32_t)0x01000000)
+#define RCC_RNGCCLK_SYSCLK_DIV3 ((uint32_t)0x02000000)
+#define RCC_RNGCCLK_SYSCLK_DIV4 ((uint32_t)0x03000000)
+#define RCC_RNGCCLK_SYSCLK_DIV5 ((uint32_t)0x04000000)
+#define RCC_RNGCCLK_SYSCLK_DIV6 ((uint32_t)0x05000000)
+#define RCC_RNGCCLK_SYSCLK_DIV7 ((uint32_t)0x06000000)
+#define RCC_RNGCCLK_SYSCLK_DIV8 ((uint32_t)0x07000000)
+#define RCC_RNGCCLK_SYSCLK_DIV9 ((uint32_t)0x08000000)
+#define RCC_RNGCCLK_SYSCLK_DIV10 ((uint32_t)0x09000000)
+#define RCC_RNGCCLK_SYSCLK_DIV11 ((uint32_t)0x0A000000)
+#define RCC_RNGCCLK_SYSCLK_DIV12 ((uint32_t)0x0B000000)
+#define RCC_RNGCCLK_SYSCLK_DIV13 ((uint32_t)0x0C000000)
+#define RCC_RNGCCLK_SYSCLK_DIV14 ((uint32_t)0x0D000000)
+#define RCC_RNGCCLK_SYSCLK_DIV15 ((uint32_t)0x0E000000)
+#define RCC_RNGCCLK_SYSCLK_DIV16 ((uint32_t)0x0F000000)
+#define RCC_RNGCCLK_SYSCLK_DIV17 ((uint32_t)0x10000000)
+#define RCC_RNGCCLK_SYSCLK_DIV18 ((uint32_t)0x11000000)
+#define RCC_RNGCCLK_SYSCLK_DIV19 ((uint32_t)0x12000000)
+#define RCC_RNGCCLK_SYSCLK_DIV20 ((uint32_t)0x13000000)
+#define RCC_RNGCCLK_SYSCLK_DIV21 ((uint32_t)0x14000000)
+#define RCC_RNGCCLK_SYSCLK_DIV22 ((uint32_t)0x15000000)
+#define RCC_RNGCCLK_SYSCLK_DIV23 ((uint32_t)0x16000000)
+#define RCC_RNGCCLK_SYSCLK_DIV24 ((uint32_t)0x17000000)
+#define RCC_RNGCCLK_SYSCLK_DIV25 ((uint32_t)0x18000000)
+#define RCC_RNGCCLK_SYSCLK_DIV26 ((uint32_t)0x19000000)
+#define RCC_RNGCCLK_SYSCLK_DIV27 ((uint32_t)0x1A000000)
+#define RCC_RNGCCLK_SYSCLK_DIV28 ((uint32_t)0x1B000000)
+#define RCC_RNGCCLK_SYSCLK_DIV29 ((uint32_t)0x1C000000)
+#define RCC_RNGCCLK_SYSCLK_DIV30 ((uint32_t)0x1D000000)
+#define RCC_RNGCCLK_SYSCLK_DIV31 ((uint32_t)0x1E000000)
+#define RCC_RNGCCLK_SYSCLK_DIV32 ((uint32_t)0x1F000000)
+#define IS_RCC_RNGCCLKPRE(DIV) \
+ (((DIV) == RCC_RNGCCLK_SYSCLK_DIV1) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV2) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV3) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV4) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV5) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV6) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV7) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV8) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV9) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV10) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV11) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV12) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV13) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV14) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV15) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV16) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV17) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV18) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV19) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV20) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV21) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV22) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV23) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV24) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV25) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV26) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV27) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV28) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV29) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV30) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV31) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV32))
+
+#define RCC_ADC1MCLK_SRC_HSI ((uint32_t)0x00000000)
+#define RCC_ADC1MCLK_SRC_HSE ((uint32_t)0x00020000)
+#define IS_RCC_ADC1MCLKSRC(ADC1MCLK) (((ADC1MCLK) == RCC_ADC1MCLK_SRC_HSI) || ((ADC1MCLK) == RCC_ADC1MCLK_SRC_HSE))
+
+#define RCC_ADC1MCLK_DIV1 ((uint32_t)0x00000000)
+#define RCC_ADC1MCLK_DIV2 ((uint32_t)0x00001000)
+#define RCC_ADC1MCLK_DIV3 ((uint32_t)0x00002000)
+#define RCC_ADC1MCLK_DIV4 ((uint32_t)0x00003000)
+#define RCC_ADC1MCLK_DIV5 ((uint32_t)0x00004000)
+#define RCC_ADC1MCLK_DIV6 ((uint32_t)0x00005000)
+#define RCC_ADC1MCLK_DIV7 ((uint32_t)0x00006000)
+#define RCC_ADC1MCLK_DIV8 ((uint32_t)0x00007000)
+#define RCC_ADC1MCLK_DIV9 ((uint32_t)0x00008000)
+#define RCC_ADC1MCLK_DIV10 ((uint32_t)0x00009000)
+#define RCC_ADC1MCLK_DIV11 ((uint32_t)0x0000A000)
+#define RCC_ADC1MCLK_DIV12 ((uint32_t)0x0000B000)
+#define RCC_ADC1MCLK_DIV13 ((uint32_t)0x0000C000)
+#define RCC_ADC1MCLK_DIV14 ((uint32_t)0x0000D000)
+#define RCC_ADC1MCLK_DIV15 ((uint32_t)0x0000E000)
+#define RCC_ADC1MCLK_DIV16 ((uint32_t)0x0000F000)
+#define RCC_ADC1MCLK_DIV17 ((uint32_t)0x00010000)
+#define RCC_ADC1MCLK_DIV18 ((uint32_t)0x00011000)
+#define RCC_ADC1MCLK_DIV19 ((uint32_t)0x00012000)
+#define RCC_ADC1MCLK_DIV20 ((uint32_t)0x00013000)
+#define RCC_ADC1MCLK_DIV21 ((uint32_t)0x00014000)
+#define RCC_ADC1MCLK_DIV22 ((uint32_t)0x00015000)
+#define RCC_ADC1MCLK_DIV23 ((uint32_t)0x00016000)
+#define RCC_ADC1MCLK_DIV24 ((uint32_t)0x00017000)
+#define RCC_ADC1MCLK_DIV25 ((uint32_t)0x00018000)
+#define RCC_ADC1MCLK_DIV26 ((uint32_t)0x00019000)
+#define RCC_ADC1MCLK_DIV27 ((uint32_t)0x0001A000)
+#define RCC_ADC1MCLK_DIV28 ((uint32_t)0x0001B000)
+#define RCC_ADC1MCLK_DIV29 ((uint32_t)0x0001C000)
+#define RCC_ADC1MCLK_DIV30 ((uint32_t)0x0001D000)
+#define RCC_ADC1MCLK_DIV31 ((uint32_t)0x0001E000)
+#define RCC_ADC1MCLK_DIV32 ((uint32_t)0x0001F000)
+#define IS_RCC_ADC1MCLKPRE(DIV) \
+ (((DIV) == RCC_ADC1MCLK_DIV1) || ((DIV) == RCC_ADC1MCLK_DIV2) || ((DIV) == RCC_ADC1MCLK_DIV3) \
+ || ((DIV) == RCC_ADC1MCLK_DIV4) || ((DIV) == RCC_ADC1MCLK_DIV5) || ((DIV) == RCC_ADC1MCLK_DIV6) \
+ || ((DIV) == RCC_ADC1MCLK_DIV7) || ((DIV) == RCC_ADC1MCLK_DIV8) || ((DIV) == RCC_ADC1MCLK_DIV9) \
+ || ((DIV) == RCC_ADC1MCLK_DIV10) || ((DIV) == RCC_ADC1MCLK_DIV11) || ((DIV) == RCC_ADC1MCLK_DIV12) \
+ || ((DIV) == RCC_ADC1MCLK_DIV13) || ((DIV) == RCC_ADC1MCLK_DIV14) || ((DIV) == RCC_ADC1MCLK_DIV15) \
+ || ((DIV) == RCC_ADC1MCLK_DIV16) || ((DIV) == RCC_ADC1MCLK_DIV17) || ((DIV) == RCC_ADC1MCLK_DIV18) \
+ || ((DIV) == RCC_ADC1MCLK_DIV19) || ((DIV) == RCC_ADC1MCLK_DIV20) || ((DIV) == RCC_ADC1MCLK_DIV21) \
+ || ((DIV) == RCC_ADC1MCLK_DIV22) || ((DIV) == RCC_ADC1MCLK_DIV23) || ((DIV) == RCC_ADC1MCLK_DIV24) \
+ || ((DIV) == RCC_ADC1MCLK_DIV25) || ((DIV) == RCC_ADC1MCLK_DIV26) || ((DIV) == RCC_ADC1MCLK_DIV27) \
+ || ((DIV) == RCC_ADC1MCLK_DIV28) || ((DIV) == RCC_ADC1MCLK_DIV29) || ((DIV) == RCC_ADC1MCLK_DIV30) \
+ || ((DIV) == RCC_ADC1MCLK_DIV31) || ((DIV) == RCC_ADC1MCLK_DIV32))
+
+#define RCC_ADCPLLCLK_DISABLE ((uint32_t)0xFFFFFEFF)
+#define RCC_ADCPLLCLK_DIV1 ((uint32_t)0x00000100)
+#define RCC_ADCPLLCLK_DIV2 ((uint32_t)0x00000110)
+#define RCC_ADCPLLCLK_DIV4 ((uint32_t)0x00000120)
+#define RCC_ADCPLLCLK_DIV6 ((uint32_t)0x00000130)
+#define RCC_ADCPLLCLK_DIV8 ((uint32_t)0x00000140)
+#define RCC_ADCPLLCLK_DIV10 ((uint32_t)0x00000150)
+#define RCC_ADCPLLCLK_DIV12 ((uint32_t)0x00000160)
+#define RCC_ADCPLLCLK_DIV16 ((uint32_t)0x00000170)
+#define RCC_ADCPLLCLK_DIV32 ((uint32_t)0x00000180)
+#define RCC_ADCPLLCLK_DIV64 ((uint32_t)0x00000190)
+#define RCC_ADCPLLCLK_DIV128 ((uint32_t)0x000001A0)
+#define RCC_ADCPLLCLK_DIV256 ((uint32_t)0x000001B0)
+#define RCC_ADCPLLCLK_DIV_OTHERS ((uint32_t)0x000001C0)
+#define IS_RCC_ADCPLLCLKPRE(DIV) \
+ (((DIV) == RCC_ADCPLLCLK_DIV1) || ((DIV) == RCC_ADCPLLCLK_DIV2) || ((DIV) == RCC_ADCPLLCLK_DIV4) \
+ || ((DIV) == RCC_ADCPLLCLK_DIV6) || ((DIV) == RCC_ADCPLLCLK_DIV8) || ((DIV) == RCC_ADCPLLCLK_DIV10) \
+ || ((DIV) == RCC_ADCPLLCLK_DIV12) || ((DIV) == RCC_ADCPLLCLK_DIV16) || ((DIV) == RCC_ADCPLLCLK_DIV32) \
+ || ((DIV) == RCC_ADCPLLCLK_DIV64) || ((DIV) == RCC_ADCPLLCLK_DIV128) || ((DIV) == RCC_ADCPLLCLK_DIV256) \
+ || (((DIV)&RCC_ADCPLLCLK_DIV_OTHERS) == 0x000001C0))
+
+#define RCC_ADCHCLK_DIV1 ((uint32_t)0x00000000)
+#define RCC_ADCHCLK_DIV2 ((uint32_t)0x00000001)
+#define RCC_ADCHCLK_DIV4 ((uint32_t)0x00000002)
+#define RCC_ADCHCLK_DIV6 ((uint32_t)0x00000003)
+#define RCC_ADCHCLK_DIV8 ((uint32_t)0x00000004)
+#define RCC_ADCHCLK_DIV10 ((uint32_t)0x00000005)
+#define RCC_ADCHCLK_DIV12 ((uint32_t)0x00000006)
+#define RCC_ADCHCLK_DIV16 ((uint32_t)0x00000007)
+#define RCC_ADCHCLK_DIV32 ((uint32_t)0x00000008)
+#define RCC_ADCHCLK_DIV_OTHERS ((uint32_t)0x00000008)
+#define IS_RCC_ADCHCLKPRE(DIV) \
+ (((DIV) == RCC_ADCHCLK_DIV1) || ((DIV) == RCC_ADCHCLK_DIV2) || ((DIV) == RCC_ADCHCLK_DIV4) \
+ || ((DIV) == RCC_ADCHCLK_DIV6) || ((DIV) == RCC_ADCHCLK_DIV8) || ((DIV) == RCC_ADCHCLK_DIV10) \
+ || ((DIV) == RCC_ADCHCLK_DIV12) || ((DIV) == RCC_ADCHCLK_DIV16) || ((DIV) == RCC_ADCHCLK_DIV32) \
+ || (((DIV)&RCC_ADCHCLK_DIV_OTHERS) != 0x00))
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_CFGR3_Config
+ * @{
+ */
+
+#define RCC_TRNG1MCLK_ENABLE ((uint32_t)0x00040000)
+#define RCC_TRNG1MCLK_DISABLE ((uint32_t)0xFFFBFFFF)
+
+#define RCC_TRNG1MCLK_SRC_HSI ((uint32_t)0x00000000)
+#define RCC_TRNG1MCLK_SRC_HSE ((uint32_t)0x00020000)
+#define IS_RCC_TRNG1MCLK_SRC(TRNG1MCLK) \
+ (((TRNG1MCLK) == RCC_TRNG1MCLK_SRC_HSI) || ((TRNG1MCLK) == RCC_TRNG1MCLK_SRC_HSE))
+
+#define RCC_TRNG1MCLK_DIV2 ((uint32_t)0x00000800)
+#define RCC_TRNG1MCLK_DIV4 ((uint32_t)0x00001000)
+#define RCC_TRNG1MCLK_DIV6 ((uint32_t)0x00001800)
+#define RCC_TRNG1MCLK_DIV8 ((uint32_t)0x00002000)
+#define RCC_TRNG1MCLK_DIV10 ((uint32_t)0x00002800)
+#define RCC_TRNG1MCLK_DIV12 ((uint32_t)0x00003000)
+#define RCC_TRNG1MCLK_DIV14 ((uint32_t)0x00003800)
+#define RCC_TRNG1MCLK_DIV16 ((uint32_t)0x00004000)
+#define RCC_TRNG1MCLK_DIV18 ((uint32_t)0x00004800)
+#define RCC_TRNG1MCLK_DIV20 ((uint32_t)0x00005000)
+#define RCC_TRNG1MCLK_DIV22 ((uint32_t)0x00005800)
+#define RCC_TRNG1MCLK_DIV24 ((uint32_t)0x00006000)
+#define RCC_TRNG1MCLK_DIV26 ((uint32_t)0x00006800)
+#define RCC_TRNG1MCLK_DIV28 ((uint32_t)0x00007000)
+#define RCC_TRNG1MCLK_DIV30 ((uint32_t)0x00007800)
+#define RCC_TRNG1MCLK_DIV32 ((uint32_t)0x00008000)
+#define RCC_TRNG1MCLK_DIV34 ((uint32_t)0x00008800)
+#define RCC_TRNG1MCLK_DIV36 ((uint32_t)0x00009000)
+#define RCC_TRNG1MCLK_DIV38 ((uint32_t)0x00009800)
+#define RCC_TRNG1MCLK_DIV40 ((uint32_t)0x0000A000)
+#define RCC_TRNG1MCLK_DIV42 ((uint32_t)0x0000A800)
+#define RCC_TRNG1MCLK_DIV44 ((uint32_t)0x0000B000)
+#define RCC_TRNG1MCLK_DIV46 ((uint32_t)0x0000B800)
+#define RCC_TRNG1MCLK_DIV48 ((uint32_t)0x0000C000)
+#define RCC_TRNG1MCLK_DIV50 ((uint32_t)0x0000C800)
+#define RCC_TRNG1MCLK_DIV52 ((uint32_t)0x0000D000)
+#define RCC_TRNG1MCLK_DIV54 ((uint32_t)0x0000D800)
+#define RCC_TRNG1MCLK_DIV56 ((uint32_t)0x0000E000)
+#define RCC_TRNG1MCLK_DIV58 ((uint32_t)0x0000E800)
+#define RCC_TRNG1MCLK_DIV60 ((uint32_t)0x0000F000)
+#define RCC_TRNG1MCLK_DIV62 ((uint32_t)0x0000F800)
+#define IS_RCC_TRNG1MCLKPRE(VAL) \
+ (((VAL) == RCC_TRNG1MCLK_DIV2) || ((VAL) == RCC_TRNG1MCLK_DIV4) || ((VAL) == RCC_TRNG1MCLK_DIV6) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV8) || ((VAL) == RCC_TRNG1MCLK_DIV10) || ((VAL) == RCC_TRNG1MCLK_DIV12) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV14) || ((VAL) == RCC_TRNG1MCLK_DIV16) || ((VAL) == RCC_TRNG1MCLK_DIV18) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV20) || ((VAL) == RCC_TRNG1MCLK_DIV22) || ((VAL) == RCC_TRNG1MCLK_DIV24) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV26) || ((VAL) == RCC_TRNG1MCLK_DIV28) || ((VAL) == RCC_TRNG1MCLK_DIV30) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV32) || ((VAL) == RCC_TRNG1MCLK_DIV34) || ((VAL) == RCC_TRNG1MCLK_DIV36) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV38) || ((VAL) == RCC_TRNG1MCLK_DIV40) || ((VAL) == RCC_TRNG1MCLK_DIV42) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV44) || ((VAL) == RCC_TRNG1MCLK_DIV46) || ((VAL) == RCC_TRNG1MCLK_DIV48) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV50) || ((VAL) == RCC_TRNG1MCLK_DIV52) || ((VAL) == RCC_TRNG1MCLK_DIV54) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV56) || ((VAL) == RCC_TRNG1MCLK_DIV58) || ((VAL) == RCC_TRNG1MCLK_DIV60) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV62))
+
+#define RCC_UCDR_ENABLE ((uint32_t)0x00000080)
+#define RCC_UCDR_DISABLE ((uint32_t)0xFFFFFF7F)
+
+#define RCC_UCDR300MSource_MASK ((uint32_t)0xFFFFFDFF)
+#define RCC_UCDR300M_SRC_OSC300M ((uint32_t)0x00000000)
+#define RCC_UCDR300M_SRC_PLLVCO ((uint32_t)0x00000200)
+#define IS_RCC_UCDR300M_SRC(UCDR300MCLK) \
+ (((UCDR300MCLK) == RCC_UCDR300M_SRC_OSC300M) || ((UCDR300MCLK) == RCC_UCDR300M_SRC_PLLVCO))
+
+#define RCC_USBXTALESSMode_MASK ((uint32_t)0xFFFFFEFF)
+#define RCC_USBXTALESS_MODE ((uint32_t)0x00000000)
+#define RCC_USBXTALESS_LESSMODE ((uint32_t)0x00000100)
+#define IS_RCC_USBXTALESS_MODE(USBXTALESS) \
+ (((USBXTALESS) == RCC_USBXTALESS_MODE) || ((USBXTALESS) == RCC_USBXTALESS_LESSMODE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup LSE_configuration
+ * @{
+ */
+
+#define RCC_LSE_DISABLE ((uint32_t)0x00000000)
+#define RCC_LSE_ENABLE ((uint32_t)0x00000001)
+#define RCC_LSE_BYPASS ((uint32_t)0x00000004)
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_DISABLE) || ((LSE) == RCC_LSE_ENABLE) || ((LSE) == RCC_LSE_BYPASS))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_clock_source
+ * @{
+ */
+
+#define RCC_RTCCLK_SRC_NONE ((uint32_t)0x00000000)
+#define RCC_RTCCLK_SRC_LSE ((uint32_t)0x00000100)
+#define RCC_RTCCLK_SRC_LSI ((uint32_t)0x00000200)
+#define RCC_RTCCLK_SRC_HSE_DIV32 ((uint32_t)0x00000300)
+#define IS_RCC_RTCCLK_SRC(SOURCE) \
+ (((SOURCE) == RCC_RTCCLK_SRC_NONE) || ((SOURCE) == RCC_RTCCLK_SRC_LSE) || ((SOURCE) == RCC_RTCCLK_SRC_LSI) \
+ || ((SOURCE) == RCC_RTCCLK_SRC_HSE_DIV32))
+/**
+ * @}
+ */
+
+/** @addtogroup LSX_clock_source
+ * @{
+ */
+
+#define RCC_LSXCLK_SRC_LSI ((uint32_t)0x00000000)
+#define RCC_LSXCLK_SRC_LSE ((uint32_t)0x00000020)
+#define IS_RCC_LSXCLK_SRC(SOURCE) \
+ (((SOURCE) == RCC_LSXCLK_SRC_LSI) || ((SOURCE) == RCC_LSXCLK_SRC_LSE))
+/**
+ * @}
+ */
+
+/** @addtogroup AHB_peripheral
+ * @{
+ */
+
+#define RCC_AHB_PERIPH_DMA ((uint32_t)0x00000001)
+#define RCC_AHB_PERIPH_SRAM ((uint32_t)0x00000004)
+#define RCC_AHB_PERIPH_FLITF ((uint32_t)0x00000010)
+#define RCC_AHB_PERIPH_CRC ((uint32_t)0x00000040)
+#define RCC_AHB_PERIPH_RNGC ((uint32_t)0x00000200)
+#define RCC_AHB_PERIPH_SAC ((uint32_t)0x00000800)
+#define RCC_AHB_PERIPH_ADC ((uint32_t)0x00001000)
+
+#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH)&0xFFFFE5AA) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @addtogroup APB2_peripheral
+ * @{
+ */
+
+#define RCC_APB2_PERIPH_AFIO ((uint32_t)0x00000001)
+#define RCC_APB2_PERIPH_GPIOA ((uint32_t)0x00000004)
+#define RCC_APB2_PERIPH_GPIOB ((uint32_t)0x00000008)
+#define RCC_APB2_PERIPH_GPIOC ((uint32_t)0x00000010)
+#define RCC_APB2_PERIPH_GPIOD ((uint32_t)0x00000020)
+#define RCC_APB2_PERIPH_TIM1 ((uint32_t)0x00000800)
+#define RCC_APB2_PERIPH_SPI1 ((uint32_t)0x00001000)
+#define RCC_APB2_PERIPH_TIM8 ((uint32_t)0x00002000)
+#define RCC_APB2_PERIPH_USART1 ((uint32_t)0x00004000)
+#define RCC_APB2_PERIPH_UART4 ((uint32_t)0x00020000)
+#define RCC_APB2_PERIPH_UART5 ((uint32_t)0x00040000)
+#define RCC_APB2_PERIPH_SPI2 ((uint32_t)0x00080000)
+
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH)&0xFFF187C2) == 0x00) && ((PERIPH) != 0x00))
+/**
+ * @}
+ */
+
+/** @addtogroup APB1_peripheral
+ * @{
+ */
+
+#define RCC_APB1_PERIPH_TIM2 ((uint32_t)0x00000001)
+#define RCC_APB1_PERIPH_TIM3 ((uint32_t)0x00000002)
+#define RCC_APB1_PERIPH_TIM4 ((uint32_t)0x00000004)
+#define RCC_APB1_PERIPH_TIM5 ((uint32_t)0x00000008)
+#define RCC_APB1_PERIPH_TIM6 ((uint32_t)0x00000010)
+#define RCC_APB1_PERIPH_TIM7 ((uint32_t)0x00000020)
+#define RCC_APB1_PERIPH_COMP ((uint32_t)0x00000040)
+#define RCC_APB1_PERIPH_COMP_FILT ((uint32_t)0x00000080)
+#define RCC_APB1_PERIPH_AFEC ((uint32_t)0x00000100)
+#define RCC_APB1_PERIPH_TIM9 ((uint32_t)0x00000200)
+#define RCC_APB1_PERIPH_TSC ((uint32_t)0x00000400)
+#define RCC_APB1_PERIPH_WWDG ((uint32_t)0x00000800)
+#define RCC_APB1_PERIPH_USART2 ((uint32_t)0x00020000)
+#define RCC_APB1_PERIPH_USART3 ((uint32_t)0x00040000)
+#define RCC_APB1_PERIPH_I2C1 ((uint32_t)0x00200000)
+#define RCC_APB1_PERIPH_I2C2 ((uint32_t)0x00400000)
+#define RCC_APB1_PERIPH_USB ((uint32_t)0x00800000)
+#define RCC_APB1_PERIPH_CAN ((uint32_t)0x02000000)
+#define RCC_APB1_PERIPH_PWR ((uint32_t)0x10000000)
+#define RCC_APB1_PERIPH_DAC ((uint32_t)0x20000000)
+#define RCC_APB1_PERIPH_OPAMP ((uint32_t)0x80000000)
+
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH)&0x4D19F000) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RET_peripheral
+ * @{
+ */
+
+#define RCC_RET_PERIPH_LPTIM ((uint32_t)0x00000040)
+#define RCC_RET_PERIPH_LPUART ((uint32_t)0x00000080)
+
+#define IS_RCC_RET_PERIPH(PERIPH) ((((PERIPH)&0xFFFFFF3F) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPTIM
+ * @{
+ */
+#define RCC_LPTIMCLK_SRC_MASK ((uint32_t)0xFFFFFFF8)
+
+#define RCC_LPTIMCLK_SRC_APB1 ((uint32_t)0x00000000)
+#define RCC_LPTIMCLK_SRC_LSI ((uint32_t)0x00000001)
+#define RCC_LPTIMCLK_SRC_HSI ((uint32_t)0x00000002)
+#define RCC_LPTIMCLK_SRC_LSE ((uint32_t)0x00000003)
+#define RCC_LPTIMCLK_SRC_COMP1 ((uint32_t)0x00000004)
+#define RCC_LPTIMCLK_SRC_COMP2 ((uint32_t)0x00000005)
+
+#define IS_RCC_LPTIM_CLK(LPTIMCLK) (((LPTIMCLK) == RCC_LPTIMCLK_SRC_APB1) \
+ || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_LSI) \
+ || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_HSI) \
+ || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_LSE) \
+ || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_COMP1) \
+ || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_COMP2))
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART
+ * @{
+ */
+#define RCC_LPUARTCLK_SRC_MASK ((uint32_t)0xFFFFFFE7)
+
+#define RCC_LPUARTCLK_SRC_APB1 ((uint32_t)0x00000000)
+#define RCC_LPUARTCLK_SRC_SYSCLK ((uint32_t)0x00000008)
+#define RCC_LPUARTCLK_SRC_HSI ((uint32_t)0x00000010)
+#define RCC_LPUARTCLK_SRC_LSE ((uint32_t)0x00000018)
+
+#define IS_RCC_LPUART_CLK(LPUARTCLK) (((LPUARTCLK)&0xFFFFFFE7) == 0x00)
+
+/**
+ * @}
+ */
+
+/** @addtogroup SRAM_CTRLSTS
+ * @{
+ */
+
+#define SRAM1_PARITYERROR_INT ((uint32_t)0x00000001)
+#define SRAM2_PARITYERROR_INT ((uint32_t)0x00000008)
+#define IS_RCC_SRAMERRORINT(PARITYERROR_INT) (((PARITYERROR_INT) == SRAM1_PARITYERROR_INT) \
+ || ((PARITYERROR_INT) == SRAM2_PARITYERROR_INT))
+
+#define SRAM1_PARITYERROR_RESET ((uint32_t)0x00000002)
+#define SRAM2_PARITYERROR_RESET ((uint32_t)0x00000010)
+#define IS_RCC_SRAMERRORRESET(PARITYERROR_RESET) (((PARITYERROR_RESET) == SRAM1_PARITYERROR_RESET) \
+ || ((PARITYERROR_RESET) == SRAM2_PARITYERROR_RESET))
+
+#define SRAM1_PARITYERROR_FLAG ((uint32_t)0x00000004)
+#define SRAM2_PARITYERROR_FLAG ((uint32_t)0x00000020)
+#define IS_RCC_SRAMERRORFLAG(PARITYERROR_FLAG) (((PARITYERROR_FLAG) == SRAM1_PARITYERROR_FLAG) \
+ || ((PARITYERROR_FLAG) == SRAM2_PARITYERROR_FLAG))
+
+/**
+ * @}
+ */
+
+#define RCC_MCO_CLK_NUM0 ((uint32_t)0x00000000)
+#define RCC_MCO_CLK_NUM1 ((uint32_t)0x10000000)
+#define RCC_MCO_CLK_NUM2 ((uint32_t)0x20000000)
+#define RCC_MCO_CLK_NUM3 ((uint32_t)0x30000000)
+#define RCC_MCO_CLK_NUM4 ((uint32_t)0x40000000)
+#define RCC_MCO_CLK_NUM5 ((uint32_t)0x50000000)
+#define RCC_MCO_CLK_NUM6 ((uint32_t)0x60000000)
+#define RCC_MCO_CLK_NUM7 ((uint32_t)0x70000000)
+#define RCC_MCO_CLK_NUM8 ((uint32_t)0x80000000)
+#define RCC_MCO_CLK_NUM9 ((uint32_t)0x90000000)
+#define RCC_MCO_CLK_NUM10 ((uint32_t)0xA0000000)
+#define RCC_MCO_CLK_NUM11 ((uint32_t)0xB0000000)
+#define RCC_MCO_CLK_NUM12 ((uint32_t)0xC0000000)
+#define RCC_MCO_CLK_NUM13 ((uint32_t)0xD0000000)
+#define RCC_MCO_CLK_NUM14 ((uint32_t)0xE0000000)
+#define RCC_MCO_CLK_NUM15 ((uint32_t)0xF0000000)
+#define IS_RCC_MCOCLKPRE(NUM) \
+ (((NUM) == RCC_MCO_CLK_NUM0) || ((NUM) == RCC_MCO_CLK_NUM1) || ((NUM) == RCC_MCO_CLK_NUM2) \
+ || ((NUM) == RCC_MCO_CLK_NUM3) || ((NUM) == RCC_MCO_CLK_NUM4) || ((NUM) == RCC_MCO_CLK_NUM5) \
+ || ((NUM) == RCC_MCO_CLK_NUM6) || ((NUM) == RCC_MCO_CLK_NUM7) || ((NUM) == RCC_MCO_CLK_NUM8) \
+ || ((NUM) == RCC_MCO_CLK_NUM9) || ((NUM) == RCC_MCO_CLK_NUM10) || ((NUM) == RCC_MCO_CLK_NUM11) \
+ || ((NUM) == RCC_MCO_CLK_NUM12) || ((NUM) == RCC_MCO_CLK_NUM13) || ((NUM) == RCC_MCO_CLK_NUM14) \
+ || ((NUM) == RCC_MCO_CLK_NUM15))
+
+/** @addtogroup Clock_source_to_output_on_MCO_pin
+ * @{
+ */
+
+#define RCC_MCO_NOCLK ((uint8_t)0x00)
+#define RCC_MCO_LSI ((uint8_t)0x01)
+#define RCC_MCO_LSE ((uint8_t)0x02)
+#define RCC_MCO_MSI ((uint8_t)0x03)
+#define RCC_MCO_SYSCLK ((uint8_t)0x04)
+#define RCC_MCO_HSI ((uint8_t)0x05)
+#define RCC_MCO_HSE ((uint8_t)0x06)
+#define RCC_MCO_PLLCLK ((uint8_t)0x07)
+
+#define IS_RCC_MCO(MCO) \
+ (((MCO) == RCC_MCO_NOCLK) || ((MCO) == RCC_MCO_LSI) || ((MCO) == RCC_MCO_LSE) || ((MCO) == RCC_MCO_MSI) \
+ || ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSI) || ((MCO) == RCC_MCO_HSE) || ((MCO) == RCC_MCO_PLLCLK))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Flag
+ * @{
+ */
+#define RCC_CTRL_FLAG_HSIRDF ((uint8_t)0x21)
+#define RCC_CTRL_FLAG_HSERDF ((uint8_t)0x31)
+#define RCC_CTRL_FLAG_PLLRDF ((uint8_t)0x39)
+#define RCC_LDCTRL_FLAG_LSERD ((uint8_t)0x41)
+#define RCC_LDCTRL_FLAG_LSECLKSSF ((uint8_t)0x44)
+#define RCC_LDCTRL_FLAG_BORRSTF ((uint8_t)0x5C)
+#define RCC_LDCTRL_FLAG_LDEMCRSTF ((uint8_t)0x5E)
+#define RCC_CTRLSTS_FLAG_LSIRD ((uint8_t)0x61)
+#define RCC_CTRLSTS_FLAG_MSIRD ((uint8_t)0x63)
+#define RCC_CTRLSTS_FLAG_RAMRSTF ((uint8_t)0x77)
+#define RCC_CTRLSTS_FLAG_MMURSTF ((uint8_t)0x79)
+#define RCC_CTRLSTS_FLAG_PINRSTF ((uint8_t)0x7A)
+#define RCC_CTRLSTS_FLAG_PORRSTF ((uint8_t)0x7B)
+#define RCC_CTRLSTS_FLAG_SFTRSTF ((uint8_t)0x7C)
+#define RCC_CTRLSTS_FLAG_IWDGRSTF ((uint8_t)0x7D)
+#define RCC_CTRLSTS_FLAG_WWDGRSTF ((uint8_t)0x7E)
+#define RCC_CTRLSTS_FLAG_LPWRRSTF ((uint8_t)0x7F)
+
+#define IS_RCC_FLAG(FLAG) \
+ (((FLAG) == RCC_CTRL_FLAG_HSIRDF) || ((FLAG) == RCC_CTRL_FLAG_HSERDF) || ((FLAG) == RCC_CTRL_FLAG_PLLRDF) \
+ || ((FLAG) == RCC_LDCTRL_FLAG_LSERD) || ((FLAG) == RCC_LDCTRL_FLAG_LSECLKSSF) || ((FLAG) == RCC_LDCTRL_FLAG_BORRSTF) \
+ || ((FLAG) == RCC_LDCTRL_FLAG_LDEMCRSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_LSIRD) || ((FLAG) == RCC_CTRLSTS_FLAG_MSIRD) \
+ || ((FLAG) == RCC_CTRLSTS_FLAG_RAMRSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_MMURSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_PINRSTF) \
+ || ((FLAG) == RCC_CTRLSTS_FLAG_PORRSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_SFTRSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_IWDGRSTF) \
+ || ((FLAG) == RCC_CTRLSTS_FLAG_WWDGRSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_LPWRRSTF))
+
+#define IS_RCC_CALIB_VALUE(VALUE) ((VALUE) <= 0x1F)
+#define IS_RCC_MSICALIB_VALUE(VALUE) ((VALUE) <= 0xFF)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Exported_Functions
+ * @{
+ */
+
+void RCC_DeInit(void);
+void RCC_ConfigHse(uint32_t RCC_HSE);
+ErrorStatus RCC_WaitHseStable(void);
+void RCC_ConfigHsi(uint32_t RCC_HSI);
+ErrorStatus RCC_WaitHsiStable(void);
+void RCC_SetHsiCalibValue(uint8_t HSICalibrationValue);
+void RCC_EnableHsi(FunctionalState Cmd);
+void RCC_ConfigMsi(uint32_t RCC_MSI, uint32_t RCC_MSI_Range);
+ErrorStatus RCC_WaitMsiStable(void);
+void RCC_SetMsiCalibValue(uint8_t MSICalibrationValue);
+void RCC_EnableMsi(FunctionalState Cmd);
+void RCC_ConfigPll(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul, uint32_t RCC_PLLDIVCLK);
+void RCC_EnablePll(FunctionalState Cmd);
+
+void RCC_ConfigSysclk(uint32_t RCC_SYSCLKSource);
+uint8_t RCC_GetSysclkSrc(void);
+void RCC_ConfigHclk(uint32_t RCC_SYSCLK);
+void RCC_ConfigPclk1(uint32_t RCC_HCLK);
+void RCC_ConfigPclk2(uint32_t RCC_HCLK);
+void RCC_ConfigInt(uint8_t RccInt, FunctionalState Cmd);
+
+void RCC_ConfigUsbClk(uint32_t RCC_USBCLKSource);
+
+void RCC_ConfigTim18Clk(uint32_t RCC_TIM18CLKSource);
+void RCC_ConfigRngcClk(uint32_t RCC_RNGCCLKPrescaler);
+
+void RCC_ConfigAdc1mClk(uint32_t RCC_ADC1MCLKSource, uint32_t RCC_ADC1MPrescaler);
+void RCC_ConfigAdcPllClk(uint32_t RCC_ADCPLLCLKPrescaler, FunctionalState Cmd);
+void RCC_ConfigAdcHclk(uint32_t RCC_ADCHCLKPrescaler);
+
+void RCC_ConfigTrng1mClk(uint32_t RCC_TRNG1MCLKSource, uint32_t RCC_TRNG1MPrescaler);
+void RCC_EnableTrng1mClk(FunctionalState Cmd);
+
+void RCC_ConfigUCDRClk(uint32_t RCC_UCDR300MSource, FunctionalState Cmd);
+
+void RCC_ConfigUSBXTALESSMode(uint32_t RCC_USBXTALESSMode);
+
+void RCC_EnableRETPeriphClk(uint32_t RCC_RETPeriph, FunctionalState Cmd);
+void RCC_EnableRETPeriphReset(uint32_t RCC_RETPeriph, FunctionalState Cmd);
+
+void RCC_ConfigLSXClk(uint32_t RCC_LSXCLKSource);
+uint32_t RCC_GetLSXClkSrc(void);
+
+void RCC_ConfigLPTIMClk(uint32_t RCC_LPTIMCLKSource);
+uint32_t RCC_GetLPTIMClkSrc(void);
+void RCC_ConfigLPUARTClk(uint32_t RCC_LPUARTCLKSource);
+uint32_t RCC_GetLPUARTClkSrc(void);
+
+void RCC_ConfigSRAMParityErrorInt(uint32_t SramInt, FunctionalState Cmd);
+void RCC_ConfigSRAMParityErrorRESET(uint32_t SramReset, FunctionalState Cmd);
+void RCC_ClrSRAMParityErrorFlag(uint32_t SramErrorflag);
+
+void RCC_ConfigLse(uint8_t RCC_LSE,uint16_t LSE_Trim);
+void RCC_EnableLsi(FunctionalState Cmd);
+void RCC_ConfigRtcClk(uint32_t RCC_RTCCLKSource);
+void RCC_EnableRtcClk(FunctionalState Cmd);
+uint32_t RCC_GetRTCClkSrc(void);
+void RCC_GetClocksFreqValue(RCC_ClocksType* RCC_Clocks);
+void RCC_EnableAHBPeriphClk(uint32_t RCC_AHBPeriph, FunctionalState Cmd);
+void RCC_EnableAPB2PeriphClk(uint32_t RCC_APB2Periph, FunctionalState Cmd);
+void RCC_EnableAPB1PeriphClk(uint32_t RCC_APB1Periph, FunctionalState Cmd);
+
+void RCC_EnableAHBPeriphReset(uint32_t RCC_AHBPeriph, FunctionalState Cmd);
+void RCC_EnableAPB2PeriphReset(uint32_t RCC_APB2Periph, FunctionalState Cmd);
+void RCC_EnableAPB1PeriphReset(uint32_t RCC_APB1Periph, FunctionalState Cmd);
+void RCC_EnableLowPowerReset(FunctionalState Cmd);
+void RCC_EnableClockSecuritySystem(FunctionalState Cmd);
+void RCC_EnableLSEClockSecuritySystem(FunctionalState Cmd);
+FlagStatus RCC_GetLSEClockSecuritySystemStatus(void);
+void RCC_ConfigMcoClkPre(uint32_t RCC_MCOCLKPrescaler);
+void RCC_ConfigMco(uint8_t RCC_MCO);
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
+void RCC_ClrFlag(void);
+INTStatus RCC_GetIntStatus(uint8_t RccInt);
+void RCC_ClrIntPendingBit(uint32_t RccClrInt);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32G43X_RCC_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_rtc.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_rtc.h
new file mode 100644
index 0000000000..bff96f5ae4
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_rtc.h
@@ -0,0 +1,789 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_rtc.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_RTC_H__
+#define __N32G43X_RTC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RTC
+ * @{
+ */
+
+/**
+ * @brief RTC Init structures definition
+ */
+typedef struct
+{
+ uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format.
+ This parameter can be a value of @ref RTC_Hour_Formats */
+
+ uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
+ This parameter must be set to a value lower than 0x7F */
+
+ uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
+ This parameter must be set to a value lower than 0x7FFF */
+} RTC_InitType;
+
+/**
+ * @brief RTC Time structure definition
+ */
+typedef struct
+{
+ uint8_t Hours; /*!< Specifies the RTC Time Hour.
+ This parameter must be set to a value in the 0-12 range
+ if the RTC_12HOUR_FORMAT is selected or 0-23 range if
+ the RTC_24HOUR_FORMAT is selected. */
+
+ uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
+ This parameter must be set to a value in the 0-59 range. */
+
+ uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
+ This parameter must be set to a value in the 0-59 range. */
+
+ uint8_t H12; /*!< Specifies the RTC AM/PM Time.
+ This parameter can be a value of @ref RTC_AM_PM_Definitions */
+} RTC_TimeType;
+
+/**
+ * @brief RTC Date structure definition
+ */
+typedef struct
+{
+ uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
+ This parameter can be a value of @ref RTC_WeekDay_Definitions */
+
+ uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
+ This parameter can be a value of @ref RTC_Month_Date_Definitions */
+
+ uint8_t Date; /*!< Specifies the RTC Date.
+ This parameter must be set to a value in the 1-31 range. */
+
+ uint8_t Year; /*!< Specifies the RTC Date Year.
+ This parameter must be set to a value in the 0-99 range. */
+} RTC_DateType;
+
+/**
+ * @brief RTC Alarm structure definition
+ */
+typedef struct
+{
+ RTC_TimeType AlarmTime; /*!< Specifies the RTC Alarm Time members. */
+
+ uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
+ This parameter can be a value of @ref RTC_AlarmMask_Definitions */
+
+ uint32_t DateWeekMode; /*!< Specifies the RTC Alarm is on Date or WeekDay.
+ This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
+
+ uint8_t DateWeekValue; /*!< Specifies the RTC Alarm Date/WeekDay.
+ If the Alarm Date is selected, this parameter
+ must be set to a value in the 1-31 range.
+ If the Alarm WeekDay is selected, this
+ parameter can be a value of @ref RTC_WeekDay_Definitions */
+} RTC_AlarmType;
+
+/** @addtogroup RTC_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup RTC_Hour_Formats
+ * @{
+ */
+#define RTC_24HOUR_FORMAT ((uint32_t)0x00000000)
+#define RTC_12HOUR_FORMAT ((uint32_t)0x00000040)
+#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_12HOUR_FORMAT) || ((FORMAT) == RTC_24HOUR_FORMAT))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Asynchronous_Predivider
+ * @{
+ */
+#define IS_RTC_PREDIV_ASYNCH(PREDIV) ((PREDIV) <= 0x7F)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Synchronous_Predivider
+ * @{
+ */
+#define IS_RTC_PREDIV_SYNCH(PREDIV) ((PREDIV) <= 0x7FFF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Time_Definitions
+ * @{
+ */
+#define IS_RTC_12HOUR(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))
+#define IS_RTC_24HOUR(HOUR) ((HOUR) <= 23)
+#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)
+#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_AM_PM_Definitions
+ * @{
+ */
+#define RTC_AM_H12 ((uint8_t)0x00)
+#define RTC_PM_H12 ((uint8_t)0x40)
+#define IS_RTC_H12(PM) (((PM) == RTC_AM_H12) || ((PM) == RTC_PM_H12))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Year_Date_Definitions
+ * @{
+ */
+#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Month_Date_Definitions
+ * @{
+ */
+
+/* Coded in BCD format */
+#define RTC_MONTH_JANUARY ((uint8_t)0x01)
+#define RTC_MONTH_FEBRURY ((uint8_t)0x02)
+#define RTC_MONTH_MARCH ((uint8_t)0x03)
+#define RTC_MONTH_APRIL ((uint8_t)0x04)
+#define RTC_MONTH_MAY ((uint8_t)0x05)
+#define RTC_MONTH_JUNE ((uint8_t)0x06)
+#define RTC_MONTH_JULY ((uint8_t)0x07)
+#define RTC_MONTH_AUGUST ((uint8_t)0x08)
+#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
+#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
+#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
+#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
+#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))
+#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_WeekDay_Definitions
+ * @{
+ */
+
+#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
+#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
+#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
+#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
+#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
+#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
+#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
+#define IS_RTC_WEEKDAY(WEEKDAY) \
+ (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) \
+ || ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) \
+ || ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Alarm_Definitions
+ * @{
+ */
+#define IS_RTC_ALARM_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
+#define IS_RTC_ALARM_WEEKDAY_WEEKDAY(WEEKDAY) \
+ (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) \
+ || ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) \
+ || ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_AlarmDateWeekDay_Definitions
+ * @{
+ */
+#define RTC_ALARM_SEL_WEEKDAY_DATE ((uint32_t)0x00000000)
+#define RTC_ALARM_SEL_WEEKDAY_WEEKDAY ((uint32_t)0x40000000)
+
+#define IS_RTC_ALARM_WEEKDAY_SEL(SEL) \
+ (((SEL) == RTC_ALARM_SEL_WEEKDAY_DATE) || ((SEL) == RTC_ALARM_SEL_WEEKDAY_WEEKDAY))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_AlarmMask_Definitions
+ * @{
+ */
+#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000)
+#define RTC_ALARMMASK_WEEKDAY ((uint32_t)0x80000000)
+#define RTC_ALARMMASK_HOURS ((uint32_t)0x00800000)
+#define RTC_ALARMMASK_MINUTES ((uint32_t)0x00008000)
+#define RTC_ALARMMASK_SECONDS ((uint32_t)0x00000080)
+#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080)
+#define IS_ALARM_MASK(INTEN) (((INTEN)&0x7F7F7F7F) == (uint32_t)RESET)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Alarms_Definitions
+ * @{
+ */
+#define RTC_A_ALARM ((uint32_t)0x00000100)
+#define RTC_B_ALARM ((uint32_t)0x00000200)
+#define IS_RTC_ALARM_SEL(ALARM) (((ALARM) == RTC_A_ALARM) || ((ALARM) == RTC_B_ALARM))
+#define IS_RTC_ALARM_ENABLE(ALARM) (((ALARM) & (RTC_A_ALARM | RTC_B_ALARM)) != (uint32_t)RESET)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Alarm_Sub_Seconds_Masks_Definitions
+ * @{
+ */
+#define RTC_SUBS_MASK_ALL \
+ ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. \
+ There is no comparison on sub seconds \
+ for Alarm */
+#define RTC_SUBS_MASK_SS14_1 \
+ ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm \
+ comparison. Only SS[0] is compared. */
+#define RTC_SUBS_MASK_SS14_2 \
+ ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm \
+ comparison. Only SS[1:0] are compared */
+#define RTC_SUBS_MASK_SS14_3 \
+ ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm \
+ comparison. Only SS[2:0] are compared */
+#define RTC_SUBS_MASK_SS14_4 \
+ ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm \
+ comparison. Only SS[3:0] are compared */
+#define RTC_SUBS_MASK_SS14_5 \
+ ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm \
+ comparison. Only SS[4:0] are compared */
+#define RTC_SUBS_MASK_SS14_6 \
+ ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm \
+ comparison. Only SS[5:0] are compared */
+#define RTC_SUBS_MASK_SS14_7 \
+ ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm \
+ comparison. Only SS[6:0] are compared */
+#define RTC_SUBS_MASK_SS14_8 \
+ ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm \
+ comparison. Only SS[7:0] are compared */
+#define RTC_SUBS_MASK_SS14_9 \
+ ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm \
+ comparison. Only SS[8:0] are compared */
+#define RTC_SUBS_MASK_SS14_10 \
+ ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm \
+ comparison. Only SS[9:0] are compared */
+#define RTC_SUBS_MASK_SS14_11 \
+ ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm \
+ comparison. Only SS[10:0] are compared */
+#define RTC_SUBS_MASK_SS14_12 \
+ ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm \
+ comparison.Only SS[11:0] are compared */
+#define RTC_SUBS_MASK_SS14_13 \
+ ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm \
+ comparison. Only SS[12:0] are compared */
+#define RTC_SUBS_MASK_SS14_14 \
+ ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm \
+ comparison.Only SS[13:0] are compared */
+#define RTC_SUBS_MASK_NONE \
+ ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match \
+ to activate alarm. */
+#define IS_RTC_ALARM_SUB_SECOND_MASK_MODE(INTEN) \
+ (((INTEN) == RTC_SUBS_MASK_ALL) || ((INTEN) == RTC_SUBS_MASK_SS14_1) || ((INTEN) == RTC_SUBS_MASK_SS14_2) \
+ || ((INTEN) == RTC_SUBS_MASK_SS14_3) || ((INTEN) == RTC_SUBS_MASK_SS14_4) || ((INTEN) == RTC_SUBS_MASK_SS14_5) \
+ || ((INTEN) == RTC_SUBS_MASK_SS14_6) || ((INTEN) == RTC_SUBS_MASK_SS14_7) || ((INTEN) == RTC_SUBS_MASK_SS14_8) \
+ || ((INTEN) == RTC_SUBS_MASK_SS14_9) || ((INTEN) == RTC_SUBS_MASK_SS14_10) || ((INTEN) == RTC_SUBS_MASK_SS14_11) \
+ || ((INTEN) == RTC_SUBS_MASK_SS14_12) || ((INTEN) == RTC_SUBS_MASK_SS14_13) || ((INTEN) == RTC_SUBS_MASK_SS14_14) \
+ || ((INTEN) == RTC_SUBS_MASK_NONE))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Alarm_Sub_Seconds_Value
+ * @{
+ */
+
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Wakeup_Timer_Definitions
+ * @{
+ */
+#define RTC_WKUPCLK_RTCCLK_DIV16 ((uint32_t)0x00000000)
+#define RTC_WKUPCLK_RTCCLK_DIV8 ((uint32_t)0x00000001)
+#define RTC_WKUPCLK_RTCCLK_DIV4 ((uint32_t)0x00000002)
+#define RTC_WKUPCLK_RTCCLK_DIV2 ((uint32_t)0x00000003)
+#define RTC_WKUPCLK_CK_SPRE_16BITS ((uint32_t)0x00000004)
+#define RTC_WKUPCLK_CK_SPRE_17BITS ((uint32_t)0x00000006)
+#define IS_RTC_WKUP_CLOCK(CLOCK) \
+ (((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV16) || ((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV8) \
+ || ((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV4) || ((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV2) \
+ || ((CLOCK) == RTC_WKUPCLK_CK_SPRE_16BITS) || ((CLOCK) == RTC_WKUPCLK_CK_SPRE_17BITS))
+#define IS_RTC_WKUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Time_Stamp_Edges_definitions
+ * @{
+ */
+#define RTC_TIMESTAMP_EDGE_RISING ((uint32_t)0x00000000)
+#define RTC_TIMESTAMP_EDGE_FALLING ((uint32_t)0x00000008)
+#define IS_RTC_TIMESTAMP_EDGE_MODE(EDGE) \
+ (((EDGE) == RTC_TIMESTAMP_EDGE_RISING) || ((EDGE) == RTC_TIMESTAMP_EDGE_FALLING))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Output_selection_Definitions
+ * @{
+ */
+#define RTC_OUTPUT_DIS ((uint32_t)0x00000000)
+#define RTC_OUTPUT_ALA ((uint32_t)0x00200000)
+#define RTC_OUTPUT_ALB ((uint32_t)0x00400000)
+#define RTC_OUTPUT_WKUP ((uint32_t)0x00600000)
+
+#define IS_RTC_OUTPUT_MODE(OUTPUT) \
+ (((OUTPUT) == RTC_OUTPUT_DIS) || ((OUTPUT) == RTC_OUTPUT_ALA) || ((OUTPUT) == RTC_OUTPUT_ALB) \
+ || ((OUTPUT) == RTC_OUTPUT_WKUP))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Output_Polarity_Definitions
+ * @{
+ */
+#define RTC_OUTPOL_HIGH ((uint32_t)0x00000000)
+#define RTC_OUTPOL_LOW ((uint32_t)0x00100000)
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPOL_HIGH) || ((POL) == RTC_OUTPOL_LOW))
+/**
+ * @}
+ */
+
+
+/** @addtogroup RTC_Calib_Output_selection_Definitions
+ * @{
+ */
+#define RTC_CALIB_OUTPUT_256HZ ((uint32_t)0x00000000)
+#define RTC_CALIB_OUTPUT_1HZ ((uint32_t)0x00080000)
+#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIB_OUTPUT_256HZ) || ((OUTPUT) == RTC_CALIB_OUTPUT_1HZ))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Smooth_calib_period_Definitions
+ * @{
+ */
+#define SMOOTH_CALIB_32SEC \
+ ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \
+ period is 32s, else 2exp20 RTCCLK seconds */
+#define SMOOTH_CALIB_16SEC \
+ ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \
+ period is 16s, else 2exp19 RTCCLK seconds */
+#define SMOOTH_CALIB_8SEC \
+ ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \
+ period is 8s, else 2exp18 RTCCLK seconds */
+#define IS_RTC_SMOOTH_CALIB_PERIOD_SEL(PERIOD) \
+ (((PERIOD) == SMOOTH_CALIB_32SEC) || ((PERIOD) == SMOOTH_CALIB_16SEC) || ((PERIOD) == SMOOTH_CALIB_8SEC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Smooth_calib_Plus_pulses_Definitions
+ * @{
+ */
+#define RTC_SMOOTH_CALIB_PLUS_PULSES_SET \
+ ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added \
+ during a X -second window = Y - CALM[8:0]. \
+ with Y = 512, 256, 128 when X = 32, 16, 8 */
+#define RTC_SMOOTH_CALIB_PLUS_PULSES__RESET \
+ ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited \
+ during a 32-second window = CALM[8:0]. */
+#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) \
+ (((PLUS) == RTC_SMOOTH_CALIB_PLUS_PULSES_SET) || ((PLUS) == RTC_SMOOTH_CALIB_PLUS_PULSES__RESET))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Smooth_calib_Minus_pulses_Definitions
+ * @{
+ */
+#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_DayLightSaving_Definitions
+ * @{
+ */
+#define RTC_DAYLIGHT_SAVING_SUB1H ((uint32_t)0x00020000)
+#define RTC_DAYLIGHT_SAVING_ADD1H ((uint32_t)0x00010000)
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHT_SAVING_SUB1H) || ((SAVE) == RTC_DAYLIGHT_SAVING_ADD1H))
+
+#define RTC_STORE_OPERATION_RESET ((uint32_t)0x00000000)
+#define RTC_STORE_OPERATION_SET ((uint32_t)0x00040000)
+#define IS_RTC_STORE_OPERATION(OPERATION) \
+ (((OPERATION) == RTC_STORE_OPERATION_RESET) || ((OPERATION) == RTC_STORE_OPERATION_SET))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Output_Type_ALARM_OUT
+ * @{
+ */
+#define RTC_OUTPUT_OPENDRAIN ((uint32_t)0x00000000)
+#define RTC_OUTPUT_PUSHPULL ((uint32_t)0x00000001)
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_OPENDRAIN) || ((TYPE) == RTC_OUTPUT_PUSHPULL))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Add_1_Second_Parameter_Definitions
+ * @{
+ */
+#define RTC_SHIFT_ADD1S_DISABLE ((uint32_t)0x00000000)
+#define RTC_SHIFT_ADD1S_ENABLE ((uint32_t)0x80000000)
+#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFT_ADD1S_DISABLE) || ((SEL) == RTC_SHIFT_ADD1S_ENABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Substract_Fraction_Of_Second_Value
+ * @{
+ */
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Input_parameter_format_definitions
+ * @{
+ */
+#define RTC_FORMAT_BIN ((uint32_t)0x000000000)
+#define RTC_FORMAT_BCD ((uint32_t)0x000000001)
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Flags_Definitions
+ * @{
+ */
+#define RTC_FLAG_RECPF ((uint32_t)0x00010000)
+#define RTC_FLAG_TAMP3F ((uint32_t)0x00008000)
+#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000)
+#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)
+#define RTC_FLAG_TISOVF ((uint32_t)0x00001000)
+#define RTC_FLAG_TISF ((uint32_t)0x00000800)
+#define RTC_FLAG_WTF ((uint32_t)0x00000400)
+#define RTC_FLAG_ALBF ((uint32_t)0x00000200)
+#define RTC_FLAG_ALAF ((uint32_t)0x00000100)
+#define RTC_FLAG_INITF ((uint32_t)0x00000040)
+#define RTC_FLAG_RSYF ((uint32_t)0x00000020)
+#define RTC_FLAG_INITSF ((uint32_t)0x00000010)
+#define RTC_FLAG_SHOPF ((uint32_t)0x00000008)
+#define RTC_FLAG_WTWF ((uint32_t)0x00000004)
+#define RTC_FLAG_ALBWF ((uint32_t)0x00000002)
+#define RTC_FLAG_ALAWF ((uint32_t)0x00000001)
+#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RECPF) || ((FLAG) == RTC_FLAG_TAMP3F) || \
+ ((FLAG) == RTC_FLAG_TAMP2F) || ((FLAG) == RTC_FLAG_TAMP1F) || \
+ ((FLAG) == RTC_FLAG_TISOVF) || ((FLAG) == RTC_FLAG_TISF) || \
+ ((FLAG) == RTC_FLAG_WTF) || ((FLAG) == RTC_FLAG_ALBF) || \
+ ((FLAG) == RTC_FLAG_ALAF) || ((FLAG) == RTC_FLAG_INITF) || \
+ ((FLAG) == RTC_FLAG_RSYF) || ((FLAG) == RTC_FLAG_INITSF) || \
+ ((FLAG) == RTC_FLAG_SHOPF) || ((FLAG) == RTC_FLAG_WTWF) || \
+ ((FLAG) == RTC_FLAG_ALBWF)|| ((FLAG) == RTC_FLAG_ALAWF))
+#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Interrupts_Definitions
+ * @{
+ */
+#define RTC_INT_TAMP3 ((uint32_t)0x00080000)
+#define RTC_INT_TAMP2 ((uint32_t)0x00040000)
+#define RTC_INT_TAMP1 ((uint32_t)0x00020000)
+#define RTC_INT_TS ((uint32_t)0x00008000)
+#define RTC_INT_WUT ((uint32_t)0x00004000)
+#define RTC_INT_ALRB ((uint32_t)0x00002000)
+#define RTC_INT_ALRA ((uint32_t)0x00001000)
+
+#define IS_RTC_CONFIG_INT(IT) (((IT) != (uint32_t)RESET) && (((IT)&0xFFFF0FFB) == (uint32_t)RESET))
+#define IS_RTC_GET_INT(IT) \
+ (((IT) == RTC_INT_TAMP3) ||((IT) == RTC_INT_TAMP2) ||((IT) == RTC_INT_TAMP1) ||((IT) == RTC_INT_TS) || ((IT) == RTC_INT_WUT) || ((IT) == RTC_INT_ALRB) || ((IT) == RTC_INT_ALRA))
+#define IS_RTC_CLEAR_INT(IT) (((IT) != (uint32_t)RESET) && (((IT)&0xFFF10FFF) == (uint32_t)RESET))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Legacy
+ * @{
+ */
+#define RTC_DigitalCalibConfig RTC_CoarseCalibConfig
+#define RTC_DigitalCalibCmd RTC_CoarseCalibCmd
+/** @defgroup RTC_Tamper_Trigger_Definitions
+ * @{
+ */
+#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000)
+#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000002)
+#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000)
+#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000002)
+#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
+ ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
+ ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
+ ((TRIGGER) == RTC_TamperTrigger_HighLevel))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Tamper_Filter_Definitions
+ * @{
+ */
+#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
+
+#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2
+ consecutive samples at the active level */
+#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4
+ consecutive samples at the active level */
+#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8
+ consecutive samples at the active leve. */
+
+#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \
+ ((FILTER) == RTC_TamperFilter_2Sample) || \
+ ((FILTER) == RTC_TamperFilter_4Sample) || \
+ ((FILTER) == RTC_TamperFilter_8Sample))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions
+ * @{
+ */
+#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 32768 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 16384 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 8192 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 4096 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 2048 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 1024 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 512 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 256 */
+#define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700) /* Clear TAMPFREQ[2:0] bits in the RTC_TAMPCR register */
+
+#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
+
+/**
+ * @}
+ */
+
+ /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions
+ * @{
+ */
+#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before
+ sampling during 1 RTCCLK cycle */
+#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before
+ sampling during 2 RTCCLK cycles */
+#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before
+ sampling during 4 RTCCLK cycles */
+#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before
+ sampling during 8 RTCCLK cycles */
+#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
+ ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
+ ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
+ ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Tamper_Pins_Definitions
+ * @{
+ */
+#define RTC_TAMPER_1 RTC_TMPCFG_TP1EN /*!< Tamper detection enable for
+ input tamper 1 */
+#define RTC_TAMPER_2 RTC_TMPCFG_TP2EN /*!< Tamper detection enable for
+ input tamper 2 */
+#define RTC_TAMPER_3 RTC_TMPCFG_TP3EN /*!< Tamper detection enable for
+ input tamper 3 */
+#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
+
+
+#define RTC_TAMPER1_INT RTC_TMPCFG_TP1INTEN /*!< Tamper detection interruput enable */
+#define RTC_TAMPER2_INT RTC_TMPCFG_TP2INTEN /*!< Tamper detection interruput enable */
+#define RTC_TAMPER3_INT RTC_TMPCFG_TP3INTEN /*!< Tamper detection interruput enable */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Function used to set the RTC configuration to the default reset state *****/
+ErrorStatus RTC_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+ErrorStatus RTC_Init(RTC_InitType* RTC_InitStruct);
+void RTC_StructInit(RTC_InitType* RTC_InitStruct);
+void RTC_EnableWriteProtection(FunctionalState Cmd);
+ErrorStatus RTC_EnterInitMode(void);
+void RTC_ExitInitMode(void);
+ErrorStatus RTC_WaitForSynchro(void);
+ErrorStatus RTC_EnableRefClock(FunctionalState Cmd);
+void RTC_EnableBypassShadow(FunctionalState Cmd);
+
+/* Time and Date configuration functions **************************************/
+ErrorStatus RTC_ConfigTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct);
+void RTC_TimeStructInit(RTC_TimeType* RTC_TimeStruct);
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct);
+uint32_t RTC_GetSubSecond(void);
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct);
+void RTC_DateStructInit(RTC_DateType* RTC_DateStruct);
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct);
+
+/* Alarms (Alarm A and Alarm B) configuration functions **********************/
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct);
+void RTC_AlarmStructInit(RTC_AlarmType* RTC_AlarmStruct);
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct);
+ErrorStatus RTC_EnableAlarm(uint32_t RTC_Alarm, FunctionalState Cmd);
+void RTC_ConfigAlarmSubSecond(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask);
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
+
+/* WakeUp Timer configuration functions ***************************************/
+void RTC_ConfigWakeUpClock(uint32_t RTC_WakeUpClock);
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);
+uint32_t RTC_GetWakeUpCounter(void);
+ErrorStatus RTC_EnableWakeUp(FunctionalState Cmd);
+
+/* Daylight Saving configuration functions ************************************/
+void RTC_ConfigDayLightSaving(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
+uint32_t RTC_GetStoreOperation(void);
+
+/* Output pin Configuration function ******************************************/
+void RTC_ConfigOutput(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
+
+/* Coarse and Smooth Calibration configuration functions **********************/
+void RTC_EnableCalibOutput(FunctionalState Cmd);
+void RTC_ConfigCalibOutput(uint32_t RTC_CalibOutput);
+ErrorStatus RTC_ConfigSmoothCalib(uint32_t RTC_SmoothCalibPeriod,
+ uint32_t RTC_SmoothCalibPlusPulses,
+ uint32_t RTC_SmouthCalibMinusPulsesValue);
+
+/* TimeStamp configuration functions ******************************************/
+void RTC_EnableTimeStamp(uint32_t RTC_TimeStampEdge, FunctionalState Cmd);
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeType* RTC_StampTimeStruct, RTC_DateType* RTC_StampDateStruct);
+uint32_t RTC_GetTimeStampSubSecond(void);
+
+/* Output Type Config configuration functions *********************************/
+void RTC_ConfigOutputType(uint32_t RTC_OutputType);
+
+/* RTC_Shift_control_synchonisation_functions *********************************/
+ErrorStatus RTC_ConfigSynchroShift(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);
+
+/* Interrupts and flags management functions **********************************/
+void RTC_ConfigInt(uint32_t RTC_INT, FunctionalState Cmd);
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
+void RTC_ClrFlag(uint32_t RTC_FLAG);
+INTStatus RTC_GetITStatus(uint32_t RTC_INT);
+void RTC_ClrIntPendingBit(uint32_t RTC_INT);
+
+/* WakeUp TSC function **********************************/
+void RTC_EnableWakeUpTsc(uint32_t count);
+
+/* Tampers configuration functions ********************************************/
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);
+void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);
+void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);
+void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);
+void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
+void RTC_TamperPullUpCmd(FunctionalState NewState);
+void RTC_TamperIECmd(uint32_t TAMPxIE, FunctionalState NewState);
+void RTC_TamperTAMPTSCmd(FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32G43X_RTC_H__ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_spi.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_spi.h
new file mode 100644
index 0000000000..4420657f72
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_spi.h
@@ -0,0 +1,470 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_spi.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43x_SPI_H__
+#define __N32G43x_SPI_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @{
+ */
+
+/** @addtogroup SPI_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief SPI Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t DataDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
+ This parameter can be a value of @ref SPI_data_direction */
+
+ uint16_t SpiMode; /*!< Specifies the SPI operating mode.
+ This parameter can be a value of @ref SPI_mode */
+
+ uint16_t DataLen; /*!< Specifies the SPI data size.
+ This parameter can be a value of @ref SPI_data_size */
+
+ uint16_t CLKPOL; /*!< Specifies the serial clock steady state.
+ This parameter can be a value of @ref SPI_Clock_Polarity */
+
+ uint16_t CLKPHA; /*!< Specifies the clock active edge for the bit capture.
+ This parameter can be a value of @ref SPI_Clock_Phase */
+
+ uint16_t NSS; /*!< Specifies whether the NSS signal is managed by
+ hardware (NSS pin) or by software using the SSI bit.
+ This parameter can be a value of @ref SPI_Slave_Select_management */
+
+ uint16_t BaudRatePres; /*!< Specifies the Baud Rate prescaler value which will be
+ used to configure the transmit and receive SCK clock.
+ This parameter can be a value of @ref SPI_BaudRate_Prescaler.
+ @note The communication clock is derived from the master
+ clock. The slave clock does not need to be set. */
+
+ uint16_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+ uint16_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. */
+} SPI_InitType;
+
+/**
+ * @brief I2S Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t I2sMode; /*!< Specifies the I2S operating mode.
+ This parameter can be a value of @ref I2sMode */
+
+ uint16_t Standard; /*!< Specifies the standard used for the I2S communication.
+ This parameter can be a value of @ref Standard */
+
+ uint16_t DataFormat; /*!< Specifies the data format for the I2S communication.
+ This parameter can be a value of @ref I2S_Data_Format */
+
+ uint16_t MCLKEnable; /*!< Specifies whether the I2S MCLK output is enabled or not.
+ This parameter can be a value of @ref I2S_MCLK_Output */
+
+ uint32_t AudioFrequency; /*!< Specifies the frequency selected for the I2S communication.
+ This parameter can be a value of @ref I2S_Audio_Frequency */
+
+ uint16_t CLKPOL; /*!< Specifies the idle state of the I2S clock.
+ This parameter can be a value of @ref I2S_Clock_Polarity */
+} I2S_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Exported_Constants
+ * @{
+ */
+
+#define IS_SPI_PERIPH(PERIPH) (((PERIPH) == SPI1) || ((PERIPH) == SPI2))
+
+
+/** @addtogroup SPI_data_direction
+ * @{
+ */
+
+#define SPI_DIR_DOUBLELINE_FULLDUPLEX ((uint16_t)0x0000)
+#define SPI_DIR_DOUBLELINE_RONLY ((uint16_t)0x0400)
+#define SPI_DIR_SINGLELINE_RX ((uint16_t)0x8000)
+#define SPI_DIR_SINGLELINE_TX ((uint16_t)0xC000)
+#define IS_SPI_DIR_MODE(MODE) \
+ (((MODE) == SPI_DIR_DOUBLELINE_FULLDUPLEX) || ((MODE) == SPI_DIR_DOUBLELINE_RONLY) \
+ || ((MODE) == SPI_DIR_SINGLELINE_RX) || ((MODE) == SPI_DIR_SINGLELINE_TX))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_mode
+ * @{
+ */
+
+#define SPI_MODE_MASTER ((uint16_t)0x0104)
+#define SPI_MODE_SLAVE ((uint16_t)0x0000)
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_MASTER) || ((MODE) == SPI_MODE_SLAVE))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_data_size
+ * @{
+ */
+
+#define SPI_DATA_SIZE_16BITS ((uint16_t)0x0800)
+#define SPI_DATA_SIZE_8BITS ((uint16_t)0x0000)
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATA_SIZE_16BITS) || ((DATASIZE) == SPI_DATA_SIZE_8BITS))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Clock_Polarity
+ * @{
+ */
+
+#define SPI_CLKPOL_LOW ((uint16_t)0x0000)
+#define SPI_CLKPOL_HIGH ((uint16_t)0x0002)
+#define IS_SPI_CLKPOL(CPOL) (((CPOL) == SPI_CLKPOL_LOW) || ((CPOL) == SPI_CLKPOL_HIGH))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Clock_Phase
+ * @{
+ */
+
+#define SPI_CLKPHA_FIRST_EDGE ((uint16_t)0x0000)
+#define SPI_CLKPHA_SECOND_EDGE ((uint16_t)0x0001)
+#define IS_SPI_CLKPHA(CPHA) (((CPHA) == SPI_CLKPHA_FIRST_EDGE) || ((CPHA) == SPI_CLKPHA_SECOND_EDGE))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Slave_Select_management
+ * @{
+ */
+
+#define SPI_NSS_SOFT ((uint16_t)0x0200)
+#define SPI_NSS_HARD ((uint16_t)0x0000)
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || ((NSS) == SPI_NSS_HARD))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_BaudRate_Prescaler
+ * @{
+ */
+
+#define SPI_BR_PRESCALER_2 ((uint16_t)0x0000)
+#define SPI_BR_PRESCALER_4 ((uint16_t)0x0008)
+#define SPI_BR_PRESCALER_8 ((uint16_t)0x0010)
+#define SPI_BR_PRESCALER_16 ((uint16_t)0x0018)
+#define SPI_BR_PRESCALER_32 ((uint16_t)0x0020)
+#define SPI_BR_PRESCALER_64 ((uint16_t)0x0028)
+#define SPI_BR_PRESCALER_128 ((uint16_t)0x0030)
+#define SPI_BR_PRESCALER_256 ((uint16_t)0x0038)
+#define IS_SPI_BR_PRESCALER(PRESCALER) \
+ (((PRESCALER) == SPI_BR_PRESCALER_2) || ((PRESCALER) == SPI_BR_PRESCALER_4) || ((PRESCALER) == SPI_BR_PRESCALER_8) \
+ || ((PRESCALER) == SPI_BR_PRESCALER_16) || ((PRESCALER) == SPI_BR_PRESCALER_32) \
+ || ((PRESCALER) == SPI_BR_PRESCALER_64) || ((PRESCALER) == SPI_BR_PRESCALER_128) \
+ || ((PRESCALER) == SPI_BR_PRESCALER_256))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_MSB_LSB_transmission
+ * @{
+ */
+
+#define SPI_FB_MSB ((uint16_t)0x0000)
+#define SPI_FB_LSB ((uint16_t)0x0080)
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FB_MSB) || ((BIT) == SPI_FB_LSB))
+/**
+ * @}
+ */
+
+/** @addtogroup I2sMode
+ * @{
+ */
+
+#define I2S_MODE_SlAVE_TX ((uint16_t)0x0000)
+#define I2S_MODE_SlAVE_RX ((uint16_t)0x0100)
+#define I2S_MODE_MASTER_TX ((uint16_t)0x0200)
+#define I2S_MODE_MASTER_RX ((uint16_t)0x0300)
+#define IS_I2S_MODE(MODE) \
+ (((MODE) == I2S_MODE_SlAVE_TX) || ((MODE) == I2S_MODE_SlAVE_RX) || ((MODE) == I2S_MODE_MASTER_TX) \
+ || ((MODE) == I2S_MODE_MASTER_RX))
+/**
+ * @}
+ */
+
+/** @addtogroup Standard
+ * @{
+ */
+
+#define I2S_STD_PHILLIPS ((uint16_t)0x0000)
+#define I2S_STD_MSB_ALIGN ((uint16_t)0x0010)
+#define I2S_STD_LSB_ALIGN ((uint16_t)0x0020)
+#define I2S_STD_PCM_SHORTFRAME ((uint16_t)0x0030)
+#define I2S_STD_PCM_LONGFRAME ((uint16_t)0x00B0)
+#define IS_I2S_STANDARD(STANDARD) \
+ (((STANDARD) == I2S_STD_PHILLIPS) || ((STANDARD) == I2S_STD_MSB_ALIGN) || ((STANDARD) == I2S_STD_LSB_ALIGN) \
+ || ((STANDARD) == I2S_STD_PCM_SHORTFRAME) || ((STANDARD) == I2S_STD_PCM_LONGFRAME))
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Data_Format
+ * @{
+ */
+
+#define I2S_DATA_FMT_16BITS ((uint16_t)0x0000)
+#define I2S_DATA_FMT_16BITS_EXTENDED ((uint16_t)0x0001)
+#define I2S_DATA_FMT_24BITS ((uint16_t)0x0003)
+#define I2S_DATA_FMT_32BITS ((uint16_t)0x0005)
+#define IS_I2S_DATA_FMT(FORMAT) \
+ (((FORMAT) == I2S_DATA_FMT_16BITS) || ((FORMAT) == I2S_DATA_FMT_16BITS_EXTENDED) \
+ || ((FORMAT) == I2S_DATA_FMT_24BITS) || ((FORMAT) == I2S_DATA_FMT_32BITS))
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_MCLK_Output
+ * @{
+ */
+
+#define I2S_MCLK_ENABLE ((uint16_t)0x0200)
+#define I2S_MCLK_DISABLE ((uint16_t)0x0000)
+#define IS_I2S_MCLK_ENABLE(OUTPUT) (((OUTPUT) == I2S_MCLK_ENABLE) || ((OUTPUT) == I2S_MCLK_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Audio_Frequency
+ * @{
+ */
+
+#define I2S_AUDIO_FREQ_192K ((uint32_t)192000)
+#define I2S_AUDIO_FREQ_96K ((uint32_t)96000)
+#define I2S_AUDIO_FREQ_48K ((uint32_t)48000)
+#define I2S_AUDIO_FREQ_44K ((uint32_t)44100)
+#define I2S_AUDIO_FREQ_32K ((uint32_t)32000)
+#define I2S_AUDIO_FREQ_22K ((uint32_t)22050)
+#define I2S_AUDIO_FREQ_16K ((uint32_t)16000)
+#define I2S_AUDIO_FREQ_11K ((uint32_t)11025)
+#define I2S_AUDIO_FREQ_8K ((uint32_t)8000)
+#define I2S_AUDIO_FREQ_DEFAULT ((uint32_t)2)
+
+#define IS_I2S_AUDIO_FREQ(FREQ) \
+ ((((FREQ) >= I2S_AUDIO_FREQ_8K) && ((FREQ) <= I2S_AUDIO_FREQ_192K)) || ((FREQ) == I2S_AUDIO_FREQ_DEFAULT))
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Clock_Polarity
+ * @{
+ */
+
+#define I2S_CLKPOL_LOW ((uint16_t)0x0000)
+#define I2S_CLKPOL_HIGH ((uint16_t)0x0008)
+#define IS_I2S_CLKPOL(CPOL) (((CPOL) == I2S_CLKPOL_LOW) || ((CPOL) == I2S_CLKPOL_HIGH))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_I2S_DMA_transfer_requests
+ * @{
+ */
+
+#define SPI_I2S_DMA_TX ((uint16_t)0x0002)
+#define SPI_I2S_DMA_RX ((uint16_t)0x0001)
+#define IS_SPI_I2S_DMA(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_NSS_internal_software_management
+ * @{
+ */
+
+#define SPI_NSS_HIGH ((uint16_t)0x0100)
+#define SPI_NSS_LOW ((uint16_t)0xFEFF)
+#define IS_SPI_NSS_LEVEL(INTERNAL) (((INTERNAL) == SPI_NSS_HIGH) || ((INTERNAL) == SPI_NSS_LOW))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_CRC_Transmit_Receive
+ * @{
+ */
+
+#define SPI_CRC_TX ((uint8_t)0x00)
+#define SPI_CRC_RX ((uint8_t)0x01)
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_TX) || ((CRC) == SPI_CRC_RX))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_direction_transmit_receive
+ * @{
+ */
+
+#define SPI_BIDIRECTION_RX ((uint16_t)0xBFFF)
+#define SPI_BIDIRECTION_TX ((uint16_t)0x4000)
+#define IS_SPI_BIDIRECTION(DIRECTION) (((DIRECTION) == SPI_BIDIRECTION_RX) || ((DIRECTION) == SPI_BIDIRECTION_TX))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_I2S_interrupts_definition
+ * @{
+ */
+
+#define SPI_I2S_INT_TE ((uint8_t)0x71)
+#define SPI_I2S_INT_RNE ((uint8_t)0x60)
+#define SPI_I2S_INT_ERR ((uint8_t)0x50)
+#define IS_SPI_I2S_CONFIG_INT(IT) (((IT) == SPI_I2S_INT_TE) || ((IT) == SPI_I2S_INT_RNE) || ((IT) == SPI_I2S_INT_ERR))
+#define SPI_I2S_INT_OVER ((uint8_t)0x56)
+#define SPI_INT_MODERR ((uint8_t)0x55)
+#define SPI_INT_CRCERR ((uint8_t)0x54)
+#define I2S_INT_UNDER ((uint8_t)0x53)
+#define IS_SPI_I2S_CLR_INT(IT) (((IT) == SPI_INT_CRCERR))
+#define IS_SPI_I2S_GET_INT(IT) \
+ (((IT) == SPI_I2S_INT_RNE) || ((IT) == SPI_I2S_INT_TE) || ((IT) == I2S_INT_UNDER) || ((IT) == SPI_INT_CRCERR) \
+ || ((IT) == SPI_INT_MODERR) || ((IT) == SPI_I2S_INT_OVER))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_I2S_flags_definition
+ * @{
+ */
+
+#define SPI_I2S_RNE_FLAG ((uint16_t)0x0001)
+#define SPI_I2S_TE_FLAG ((uint16_t)0x0002)
+#define I2S_CHSIDE_FLAG ((uint16_t)0x0004)
+#define I2S_UNDER_FLAG ((uint16_t)0x0008)
+#define SPI_CRCERR_FLAG ((uint16_t)0x0010)
+#define SPI_MODERR_FLAG ((uint16_t)0x0020)
+#define SPI_I2S_OVER_FLAG ((uint16_t)0x0040)
+#define SPI_I2S_BUSY_FLAG ((uint16_t)0x0080)
+#define IS_SPI_I2S_CLR_FLAG(FLAG) (((FLAG) == SPI_CRCERR_FLAG))
+#define IS_SPI_I2S_GET_FLAG(FLAG) \
+ (((FLAG) == SPI_I2S_BUSY_FLAG) || ((FLAG) == SPI_I2S_OVER_FLAG) || ((FLAG) == SPI_MODERR_FLAG) \
+ || ((FLAG) == SPI_CRCERR_FLAG) || ((FLAG) == I2S_UNDER_FLAG) || ((FLAG) == I2S_CHSIDE_FLAG) \
+ || ((FLAG) == SPI_I2S_TE_FLAG) || ((FLAG) == SPI_I2S_RNE_FLAG))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_CRC_polynomial
+ * @{
+ */
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Exported_Functions
+ * @{
+ */
+
+void SPI_I2S_DeInit(SPI_Module* SPIx);
+void SPI_Init(SPI_Module* SPIx, SPI_InitType* SPI_InitStruct);
+void I2S_Init(SPI_Module* SPIx, I2S_InitType* I2S_InitStruct);
+void SPI_InitStruct(SPI_InitType* SPI_InitStruct);
+void I2S_InitStruct(I2S_InitType* I2S_InitStruct);
+void SPI_Enable(SPI_Module* SPIx, FunctionalState Cmd);
+void I2S_Enable(SPI_Module* SPIx, FunctionalState Cmd);
+void SPI_I2S_EnableInt(SPI_Module* SPIx, uint8_t SPI_I2S_IT, FunctionalState Cmd);
+void SPI_I2S_EnableDma(SPI_Module* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState Cmd);
+void SPI_I2S_TransmitData(SPI_Module* SPIx, uint16_t Data);
+uint16_t SPI_I2S_ReceiveData(SPI_Module* SPIx);
+void SPI_SetNssLevel(SPI_Module* SPIx, uint16_t SPI_NSSInternalSoft);
+void SPI_SSOutputEnable(SPI_Module* SPIx, FunctionalState Cmd);
+void SPI_ConfigDataLen(SPI_Module* SPIx, uint16_t DataLen);
+void SPI_TransmitCrcNext(SPI_Module* SPIx);
+void SPI_EnableCalculateCrc(SPI_Module* SPIx, FunctionalState Cmd);
+uint16_t SPI_GetCRCDat(SPI_Module* SPIx, uint8_t SPI_CRC);
+uint16_t SPI_GetCRCPoly(SPI_Module* SPIx);
+void SPI_ConfigBidirectionalMode(SPI_Module* SPIx, uint16_t DataDirection);
+FlagStatus SPI_I2S_GetStatus(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG);
+void SPI_I2S_ClrCRCErrFlag(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG);
+INTStatus SPI_I2S_GetIntStatus(SPI_Module* SPIx, uint8_t SPI_I2S_IT);
+void SPI_I2S_ClrITPendingBit(SPI_Module* SPIx, uint8_t SPI_I2S_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32G43x_SPI_H__ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_tim.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_tim.h
new file mode 100644
index 0000000000..1432c02db2
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_tim.h
@@ -0,0 +1,1101 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_tim.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_TIM_H__
+#define __N32G43X_TIM_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+#include "stdbool.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup TIM
+ * @{
+ */
+
+/** @addtogroup TIM_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief TIM Time Base Init structure definition
+ * @note This structure is used with all TIMx except for TIM6 and TIM7.
+ */
+
+typedef struct
+{
+ uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
+ This parameter can be a number between 0x0000 and 0xFFFF */
+
+ uint16_t CntMode; /*!< Specifies the counter mode.
+ This parameter can be a value of @ref TIM_Counter_Mode */
+
+ uint16_t Period; /*!< Specifies the period value to be loaded into the active
+ Auto-Reload Register at the next update event.
+ This parameter must be a number between 0x0000 and 0xFFFF. */
+
+ uint16_t ClkDiv; /*!< Specifies the clock division.
+ This parameter can be a value of @ref TIM_Clock_Division_CKD */
+
+ uint8_t RepetCnt; /*!< Specifies the repetition counter value. Each time the REPCNT downcounter
+ reaches zero, an update event is generated and counting restarts
+ from the REPCNT value (N).
+ This means in PWM mode that (N+1) corresponds to:
+ - the number of PWM periods in edge-aligned mode
+ - the number of half PWM period in center-aligned mode
+ This parameter must be a number between 0x00 and 0xFF.
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ bool CapCh1FromCompEn; /*!< channel 1 select capture in from comp if 1, from IOM if 0
+ Tim1,Tim8,Tim2,Tim3,Tim4,Tim5 valid*/
+ bool CapCh2FromCompEn; /*!< channel 2 select capture in from comp if 1, from IOM if 0
+ Tim2,Tim3,Tim4,Tim5 valid*/
+ bool CapCh3FromCompEn; /*!< channel 3 select capture in from comp if 1, from IOM if 0
+ Tim2,Tim3,Tim4,Tim5 valid*/
+ bool CapCh4FromCompEn; /*!< channel 4 select capture in from comp if 1, from IOM if 0
+ Tim2,Tim3,Tim4 valid*/
+ bool CapEtrClrFromCompEn; /*!< etr clearref select from comp if 1, from ETR IOM if 0
+ Tim2,Tim3,Tim4 valid*/
+ bool CapEtrSelFromTscEn; /*!< etr select from TSC if 1, from IOM if 0
+ Tim2,Tim4 valid*/
+} TIM_TimeBaseInitType;
+
+/**
+ * @brief TIM Output Compare Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t OcMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+ uint16_t OutputState; /*!< Specifies the TIM Output Compare state.
+ This parameter can be a value of @ref TIM_Output_Compare_state */
+
+ uint16_t OutputNState; /*!< Specifies the TIM complementary Output Compare state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_state
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint16_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between 0x0000 and 0xFFFF */
+
+ uint16_t OcPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+ uint16_t OcNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint16_t OcIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint16_t OcNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+} OCInitType;
+
+/**
+ * @brief TIM Input Capture Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t Channel; /*!< Specifies the TIM channel.
+ This parameter can be a value of @ref Channel */
+
+ uint16_t IcPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint16_t IcSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint16_t IcPrescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint16_t IcFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between 0x0 and 0xF */
+} TIM_ICInitType;
+
+/**
+ * @brief BKDT structure definition
+ * @note This structure is used only with TIM1 and TIM8.
+ */
+
+typedef struct
+{
+ uint16_t OssrState; /*!< Specifies the Off-State selection used in Run mode.
+ This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
+
+ uint16_t OssiState; /*!< Specifies the Off-State used in Idle state.
+ This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
+
+ uint16_t LockLevel; /*!< Specifies the LOCK level parameters.
+ This parameter can be a value of @ref Lock_level */
+
+ uint16_t DeadTime; /*!< Specifies the delay time between the switching-off and the
+ switching-on of the outputs.
+ This parameter can be a number between 0x00 and 0xFF */
+
+ uint16_t Break; /*!< Specifies whether the TIM Break input is enabled or not.
+ This parameter can be a value of @ref Break_Input_enable_disable */
+
+ uint16_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
+ This parameter can be a value of @ref Break_Polarity */
+
+ uint16_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+ bool IomBreakEn; /*!< EXTENDMODE valid, open iom as break in*/
+ bool LockUpBreakEn; /*!< EXTENDMODE valid, open lockup(haldfault) as break in*/
+ bool PvdBreakEn; /*!< EXTENDMODE valid, open pvd(sys voltage too high or too low) as break in*/
+} TIM_BDTRInitType;
+
+/** @addtogroup TIM_Exported_constants
+ * @{
+ */
+
+#define IsTimAllModule(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \
+ || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8))
+
+/* LIST1: TIM 1 and 8 */
+#define IsTimList1Module(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM8))
+
+/* LIST2: TIM 1, 8 */
+#define IsTimList2Module(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM8))
+
+/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */
+#define IsTimList3Module(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \
+ || ((PERIPH) == TIM8))
+
+/* LIST4: TIM 1, 2, 3, 4, 5, 8 */
+#define IsTimList4Module(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \
+ || ((PERIPH) == TIM8))
+
+/* LIST5: TIM 1, 2, 3, 4, 5, 8 */
+#define IsTimList5Module(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \
+ || ((PERIPH) == TIM8))
+
+/* LIST6: TIM 1, 2, 3, 4, 5, 8 */
+#define IsTimList6Module(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \
+ || ((PERIPH) == TIM8))
+
+/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8 */
+#define IsTimList7Module(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \
+ || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8))
+
+/* LIST8: TIM 1, 2, 3, 4, 5, 8 */
+#define IsTimList8Module(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \
+ || ((PERIPH) == TIM8))
+
+/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8 */
+#define IsTimList9Module(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \
+ || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8))
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_and_PWM_modes
+ * @{
+ */
+
+#define TIM_OCMODE_TIMING ((uint16_t)0x0000)
+#define TIM_OCMODE_ACTIVE ((uint16_t)0x0010)
+#define TIM_OCMODE_INACTIVE ((uint16_t)0x0020)
+#define TIM_OCMODE_TOGGLE ((uint16_t)0x0030)
+#define TIM_OCMODE_PWM1 ((uint16_t)0x0060)
+#define TIM_OCMODE_PWM2 ((uint16_t)0x0070)
+#define IsTimOcMode(MODE) \
+ (((MODE) == TIM_OCMODE_TIMING) || ((MODE) == TIM_OCMODE_ACTIVE) || ((MODE) == TIM_OCMODE_INACTIVE) \
+ || ((MODE) == TIM_OCMODE_TOGGLE) || ((MODE) == TIM_OCMODE_PWM1) || ((MODE) == TIM_OCMODE_PWM2))
+#define IsTimOc(MODE) \
+ (((MODE) == TIM_OCMODE_TIMING) || ((MODE) == TIM_OCMODE_ACTIVE) || ((MODE) == TIM_OCMODE_INACTIVE) \
+ || ((MODE) == TIM_OCMODE_TOGGLE) || ((MODE) == TIM_OCMODE_PWM1) || ((MODE) == TIM_OCMODE_PWM2) \
+ || ((MODE) == TIM_FORCED_ACTION_ACTIVE) || ((MODE) == TIM_FORCED_ACTION_INACTIVE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_One_Pulse_Mode
+ * @{
+ */
+
+#define TIM_OPMODE_SINGLE ((uint16_t)0x0008)
+#define TIM_OPMODE_REPET ((uint16_t)0x0000)
+#define IsTimOpMOde(MODE) (((MODE) == TIM_OPMODE_SINGLE) || ((MODE) == TIM_OPMODE_REPET))
+/**
+ * @}
+ */
+
+/** @addtogroup Channel
+ * @{
+ */
+
+#define TIM_CH_1 ((uint16_t)0x0000)
+#define TIM_CH_2 ((uint16_t)0x0004)
+#define TIM_CH_3 ((uint16_t)0x0008)
+#define TIM_CH_4 ((uint16_t)0x000C)
+#define IsTimCh(CHANNEL) \
+ (((CHANNEL) == TIM_CH_1) || ((CHANNEL) == TIM_CH_2) || ((CHANNEL) == TIM_CH_3) || ((CHANNEL) == TIM_CH_4))
+#define IsTimPwmInCh(CHANNEL) (((CHANNEL) == TIM_CH_1) || ((CHANNEL) == TIM_CH_2))
+#define IsTimComplementaryCh(CHANNEL) (((CHANNEL) == TIM_CH_1) || ((CHANNEL) == TIM_CH_2) || ((CHANNEL) == TIM_CH_3))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Clock_Division_CKD
+ * @{
+ */
+
+#define TIM_CLK_DIV1 ((uint16_t)0x0000)
+#define TIM_CLK_DIV2 ((uint16_t)0x0100)
+#define TIM_CLK_DIV4 ((uint16_t)0x0200)
+#define IsTimClkDiv(DIV) (((DIV) == TIM_CLK_DIV1) || ((DIV) == TIM_CLK_DIV2) || ((DIV) == TIM_CLK_DIV4))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Counter_Mode
+ * @{
+ */
+
+#define TIM_CNT_MODE_UP ((uint16_t)0x0000)
+#define TIM_CNT_MODE_DOWN ((uint16_t)0x0010)
+#define TIM_CNT_MODE_CENTER_ALIGN1 ((uint16_t)0x0020)
+#define TIM_CNT_MODE_CENTER_ALIGN2 ((uint16_t)0x0040)
+#define TIM_CNT_MODE_CENTER_ALIGN3 ((uint16_t)0x0060)
+#define IsTimCntMode(MODE) \
+ (((MODE) == TIM_CNT_MODE_UP) || ((MODE) == TIM_CNT_MODE_DOWN) || ((MODE) == TIM_CNT_MODE_CENTER_ALIGN1) \
+ || ((MODE) == TIM_CNT_MODE_CENTER_ALIGN2) || ((MODE) == TIM_CNT_MODE_CENTER_ALIGN3))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_Polarity
+ * @{
+ */
+
+#define TIM_OC_POLARITY_HIGH ((uint16_t)0x0000)
+#define TIM_OC_POLARITY_LOW ((uint16_t)0x0002)
+#define IsTimOcPolarity(POLARITY) (((POLARITY) == TIM_OC_POLARITY_HIGH) || ((POLARITY) == TIM_OC_POLARITY_LOW))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_N_Polarity
+ * @{
+ */
+
+#define TIM_OCN_POLARITY_HIGH ((uint16_t)0x0000)
+#define TIM_OCN_POLARITY_LOW ((uint16_t)0x0008)
+#define IsTimOcnPolarity(POLARITY) (((POLARITY) == TIM_OCN_POLARITY_HIGH) || ((POLARITY) == TIM_OCN_POLARITY_LOW))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_state
+ * @{
+ */
+
+#define TIM_OUTPUT_STATE_DISABLE ((uint16_t)0x0000)
+#define TIM_OUTPUT_STATE_ENABLE ((uint16_t)0x0001)
+#define IsTimOutputState(STATE) (((STATE) == TIM_OUTPUT_STATE_DISABLE) || ((STATE) == TIM_OUTPUT_STATE_ENABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_N_state
+ * @{
+ */
+
+#define TIM_OUTPUT_NSTATE_DISABLE ((uint16_t)0x0000)
+#define TIM_OUTPUT_NSTATE_ENABLE ((uint16_t)0x0004)
+#define IsTimOutputNState(STATE) (((STATE) == TIM_OUTPUT_NSTATE_DISABLE) || ((STATE) == TIM_OUTPUT_NSTATE_ENABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Capture_Compare_state
+ * @{
+ */
+
+#define TIM_CAP_CMP_ENABLE ((uint16_t)0x0001)
+#define TIM_CAP_CMP_DISABLE ((uint16_t)0x0000)
+#define IsTimCapCmpState(CCX) (((CCX) == TIM_CAP_CMP_ENABLE) || ((CCX) == TIM_CAP_CMP_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Capture_Compare_N_state
+ * @{
+ */
+
+#define TIM_CAP_CMP_N_ENABLE ((uint16_t)0x0004)
+#define TIM_CAP_CMP_N_DISABLE ((uint16_t)0x0000)
+#define IsTimCapCmpNState(CCXN) (((CCXN) == TIM_CAP_CMP_N_ENABLE) || ((CCXN) == TIM_CAP_CMP_N_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup Break_Input_enable_disable
+ * @{
+ */
+
+#define TIM_BREAK_IN_ENABLE ((uint16_t)0x1000)
+#define TIM_BREAK_IN_DISABLE ((uint16_t)0x0000)
+#define IsTimBreakInState(STATE) (((STATE) == TIM_BREAK_IN_ENABLE) || ((STATE) == TIM_BREAK_IN_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup Break_Polarity
+ * @{
+ */
+
+#define TIM_BREAK_POLARITY_LOW ((uint16_t)0x0000)
+#define TIM_BREAK_POLARITY_HIGH ((uint16_t)0x2000)
+#define IsTimBreakPalarity(POLARITY) (((POLARITY) == TIM_BREAK_POLARITY_LOW) || ((POLARITY) == TIM_BREAK_POLARITY_HIGH))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_AOE_Bit_Set_Reset
+ * @{
+ */
+
+#define TIM_AUTO_OUTPUT_ENABLE ((uint16_t)0x4000)
+#define TIM_AUTO_OUTPUT_DISABLE ((uint16_t)0x0000)
+#define IsTimAutoOutputState(STATE) (((STATE) == TIM_AUTO_OUTPUT_ENABLE) || ((STATE) == TIM_AUTO_OUTPUT_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup Lock_level
+ * @{
+ */
+
+#define TIM_LOCK_LEVEL_OFF ((uint16_t)0x0000)
+#define TIM_LOCK_LEVEL_1 ((uint16_t)0x0100)
+#define TIM_LOCK_LEVEL_2 ((uint16_t)0x0200)
+#define TIM_LOCK_LEVEL_3 ((uint16_t)0x0300)
+#define IsTimLockLevel(LEVEL) \
+ (((LEVEL) == TIM_LOCK_LEVEL_OFF) || ((LEVEL) == TIM_LOCK_LEVEL_1) || ((LEVEL) == TIM_LOCK_LEVEL_2) \
+ || ((LEVEL) == TIM_LOCK_LEVEL_3))
+/**
+ * @}
+ */
+
+/** @addtogroup OSSI_Off_State_Selection_for_Idle_mode_state
+ * @{
+ */
+
+#define TIM_OSSI_STATE_ENABLE ((uint16_t)0x0400)
+#define TIM_OSSI_STATE_DISABLE ((uint16_t)0x0000)
+#define IsTimOssiState(STATE) (((STATE) == TIM_OSSI_STATE_ENABLE) || ((STATE) == TIM_OSSI_STATE_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup OSSR_Off_State_Selection_for_Run_mode_state
+ * @{
+ */
+
+#define TIM_OSSR_STATE_ENABLE ((uint16_t)0x0800)
+#define TIM_OSSR_STATE_DISABLE ((uint16_t)0x0000)
+#define IsTimOssrState(STATE) (((STATE) == TIM_OSSR_STATE_ENABLE) || ((STATE) == TIM_OSSR_STATE_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_Idle_State
+ * @{
+ */
+
+#define TIM_OC_IDLE_STATE_SET ((uint16_t)0x0100)
+#define TIM_OC_IDLE_STATE_RESET ((uint16_t)0x0000)
+#define IsTimOcIdleState(STATE) (((STATE) == TIM_OC_IDLE_STATE_SET) || ((STATE) == TIM_OC_IDLE_STATE_RESET))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_N_Idle_State
+ * @{
+ */
+
+#define TIM_OCN_IDLE_STATE_SET ((uint16_t)0x0200)
+#define TIM_OCN_IDLE_STATE_RESET ((uint16_t)0x0000)
+#define IsTimOcnIdleState(STATE) (((STATE) == TIM_OCN_IDLE_STATE_SET) || ((STATE) == TIM_OCN_IDLE_STATE_RESET))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Input_Capture_Polarity
+ * @{
+ */
+
+#define TIM_IC_POLARITY_RISING ((uint16_t)0x0000)
+#define TIM_IC_POLARITY_FALLING ((uint16_t)0x0002)
+#define TIM_IC_POLARITY_BOTHEDGE ((uint16_t)0x000A)
+#define IsTimIcPalaritySingleEdge(POLARITY) \
+ (((POLARITY) == TIM_IC_POLARITY_RISING) || ((POLARITY) == TIM_IC_POLARITY_FALLING))
+#define IsTimIcPolarityAnyEdge(POLARITY) \
+ (((POLARITY) == TIM_IC_POLARITY_RISING) || ((POLARITY) == TIM_IC_POLARITY_FALLING) \
+ || ((POLARITY) == TIM_IC_POLARITY_BOTHEDGE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Input_Capture_Selection
+ * @{
+ */
+
+#define TIM_IC_SELECTION_DIRECTTI \
+ ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be \
+ connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_IC_SELECTION_INDIRECTTI \
+ ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be \
+ connected to IC2, IC1, IC4 or IC3, respectively. */
+#define TIM_IC_SELECTION_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
+#define IsTimIcSelection(SELECTION) \
+ (((SELECTION) == TIM_IC_SELECTION_DIRECTTI) || ((SELECTION) == TIM_IC_SELECTION_INDIRECTTI) \
+ || ((SELECTION) == TIM_IC_SELECTION_TRC))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Input_Capture_Prescaler
+ * @{
+ */
+
+#define TIM_IC_PSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. \
+ */
+#define TIM_IC_PSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
+#define TIM_IC_PSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
+#define TIM_IC_PSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
+#define IsTimIcPrescaler(PRESCALER) \
+ (((PRESCALER) == TIM_IC_PSC_DIV1) || ((PRESCALER) == TIM_IC_PSC_DIV2) || ((PRESCALER) == TIM_IC_PSC_DIV4) \
+ || ((PRESCALER) == TIM_IC_PSC_DIV8))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_interrupt_sources
+ * @{
+ */
+
+#define TIM_INT_UPDATE ((uint16_t)0x0001)
+#define TIM_INT_CC1 ((uint16_t)0x0002)
+#define TIM_INT_CC2 ((uint16_t)0x0004)
+#define TIM_INT_CC3 ((uint16_t)0x0008)
+#define TIM_INT_CC4 ((uint16_t)0x0010)
+#define TIM_INT_COM ((uint16_t)0x0020)
+#define TIM_INT_TRIG ((uint16_t)0x0040)
+#define TIM_INT_BREAK ((uint16_t)0x0080)
+#define IsTimInt(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
+
+#define IsTimGetInt(IT) \
+ (((IT) == TIM_INT_UPDATE) || ((IT) == TIM_INT_CC1) || ((IT) == TIM_INT_CC2) || ((IT) == TIM_INT_CC3) \
+ || ((IT) == TIM_INT_CC4) || ((IT) == TIM_INT_COM) || ((IT) == TIM_INT_TRIG) || ((IT) == TIM_INT_BREAK))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_DMA_Base_address
+ * @{
+ */
+
+#define TIM_DMABASE_CTRL1 ((uint16_t)0x0000)
+#define TIM_DMABASE_CTRL2 ((uint16_t)0x0001)
+#define TIM_DMABASE_SMCTRL ((uint16_t)0x0002)
+#define TIM_DMABASE_DMAINTEN ((uint16_t)0x0003)
+#define TIM_DMABASE_STS ((uint16_t)0x0004)
+#define TIM_DMABASE_EVTGEN ((uint16_t)0x0005)
+#define TIM_DMABASE_CAPCMPMOD1 ((uint16_t)0x0006)
+#define TIM_DMABASE_CAPCMPMOD2 ((uint16_t)0x0007)
+#define TIM_DMABASE_CAPCMPEN ((uint16_t)0x0008)
+#define TIM_DMABASE_CNT ((uint16_t)0x0009)
+#define TIM_DMABASE_PSC ((uint16_t)0x000A)
+#define TIM_DMABASE_AR ((uint16_t)0x000B)
+#define TIM_DMABASE_REPCNT ((uint16_t)0x000C)
+#define TIM_DMABASE_CAPCMPDAT1 ((uint16_t)0x000D)
+#define TIM_DMABASE_CAPCMPDAT2 ((uint16_t)0x000E)
+#define TIM_DMABASE_CAPCMPDAT3 ((uint16_t)0x000F)
+#define TIM_DMABASE_CAPCMPDAT4 ((uint16_t)0x0010)
+#define TIM_DMABASE_BKDT ((uint16_t)0x0011)
+#define TIM_DMABASE_DMACTRL ((uint16_t)0x0012)
+
+
+#define IsTimDmaBase(BASE) \
+ (((BASE) == TIM_DMABASE_CTRL1) || ((BASE) == TIM_DMABASE_CTRL2) || ((BASE) == TIM_DMABASE_SMCTRL) \
+ || ((BASE) == TIM_DMABASE_DMAINTEN) || ((BASE) == TIM_DMABASE_STS) || ((BASE) == TIM_DMABASE_EVTGEN) \
+ || ((BASE) == TIM_DMABASE_CAPCMPMOD1) || ((BASE) == TIM_DMABASE_CAPCMPMOD2) || ((BASE) == TIM_DMABASE_CAPCMPMOD3) \
+ || ((BASE) == TIM_DMABASE_CAPCMPEN) || ((BASE) == TIM_DMABASE_CNT) || ((BASE) == TIM_DMABASE_PSC) \
+ || ((BASE) == TIM_DMABASE_AR) || ((BASE) == TIM_DMABASE_REPCNT) || ((BASE) == TIM_DMABASE_CAPCMPDAT1) \
+ || ((BASE) == TIM_DMABASE_CAPCMPDAT2) || ((BASE) == TIM_DMABASE_CAPCMPDAT3) || ((BASE) == TIM_DMABASE_CAPCMPDAT4) \
+ || ((BASE) == TIM_DMABASE_BKDT)|| ((BASE) == TIM_DMABASE_DMACTRL))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_DMA_Burst_Length
+ * @{
+ */
+
+#define TIM_DMABURST_LENGTH_1TRANSFER ((uint16_t)0x0000)
+#define TIM_DMABURST_LENGTH_2TRANSFERS ((uint16_t)0x0100)
+#define TIM_DMABURST_LENGTH_3TRANSFERS ((uint16_t)0x0200)
+#define TIM_DMABURST_LENGTH_4TRANSFERS ((uint16_t)0x0300)
+#define TIM_DMABURST_LENGTH_5TRANSFERS ((uint16_t)0x0400)
+#define TIM_DMABURST_LENGTH_6TRANSFERS ((uint16_t)0x0500)
+#define TIM_DMABURST_LENGTH_7TRANSFERS ((uint16_t)0x0600)
+#define TIM_DMABURST_LENGTH_8TRANSFERS ((uint16_t)0x0700)
+#define TIM_DMABURST_LENGTH_9TRANSFERS ((uint16_t)0x0800)
+#define TIM_DMABURST_LENGTH_10TRANSFERS ((uint16_t)0x0900)
+#define TIM_DMABURST_LENGTH_11TRANSFERS ((uint16_t)0x0A00)
+#define TIM_DMABURST_LENGTH_12TRANSFERS ((uint16_t)0x0B00)
+#define TIM_DMABURST_LENGTH_13TRANSFERS ((uint16_t)0x0C00)
+#define TIM_DMABURST_LENGTH_14TRANSFERS ((uint16_t)0x0D00)
+#define TIM_DMABURST_LENGTH_15TRANSFERS ((uint16_t)0x0E00)
+#define TIM_DMABURST_LENGTH_16TRANSFERS ((uint16_t)0x0F00)
+#define TIM_DMABURST_LENGTH_17TRANSFERS ((uint16_t)0x1000)
+#define TIM_DMABURST_LENGTH_18TRANSFERS ((uint16_t)0x1100)
+#define TIM_DMABURST_LENGTH_19TRANSFERS ((uint16_t)0x1200)
+#define TIM_DMABURST_LENGTH_20TRANSFERS ((uint16_t)0x1300)
+#define TIM_DMABURST_LENGTH_21TRANSFERS ((uint16_t)0x1400)
+#define IsTimDmaLength(LENGTH) \
+ (((LENGTH) == TIM_DMABURST_LENGTH_1TRANSFER) || ((LENGTH) == TIM_DMABURST_LENGTH_2TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_3TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_4TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_5TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_6TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_7TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_8TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_9TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_10TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_11TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_12TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_13TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_14TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_15TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_16TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_17TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_18TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_19TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_20TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_21TRANSFERS))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_DMA_sources
+ * @{
+ */
+
+#define TIM_DMA_UPDATE ((uint16_t)0x0100)
+#define TIM_DMA_CC1 ((uint16_t)0x0200)
+#define TIM_DMA_CC2 ((uint16_t)0x0400)
+#define TIM_DMA_CC3 ((uint16_t)0x0800)
+#define TIM_DMA_CC4 ((uint16_t)0x1000)
+#define TIM_DMA_COM ((uint16_t)0x2000)
+#define TIM_DMA_TRIG ((uint16_t)0x4000)
+#define IsTimDmaSrc(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_External_Trigger_Prescaler
+ * @{
+ */
+
+#define TIM_EXT_TRG_PSC_OFF ((uint16_t)0x0000)
+#define TIM_EXT_TRG_PSC_DIV2 ((uint16_t)0x1000)
+#define TIM_EXT_TRG_PSC_DIV4 ((uint16_t)0x2000)
+#define TIM_EXT_TRG_PSC_DIV8 ((uint16_t)0x3000)
+#define IsTimExtPreDiv(PRESCALER) \
+ (((PRESCALER) == TIM_EXT_TRG_PSC_OFF) || ((PRESCALER) == TIM_EXT_TRG_PSC_DIV2) \
+ || ((PRESCALER) == TIM_EXT_TRG_PSC_DIV4) || ((PRESCALER) == TIM_EXT_TRG_PSC_DIV8))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Internal_Trigger_Selection
+ * @{
+ */
+
+#define TIM_TRIG_SEL_IN_TR0 ((uint16_t)0x0000)
+#define TIM_TRIG_SEL_IN_TR1 ((uint16_t)0x0010)
+#define TIM_TRIG_SEL_IN_TR2 ((uint16_t)0x0020)
+#define TIM_TRIG_SEL_IN_TR3 ((uint16_t)0x0030)
+#define TIM_TRIG_SEL_TI1F_ED ((uint16_t)0x0040)
+#define TIM_TRIG_SEL_TI1FP1 ((uint16_t)0x0050)
+#define TIM_TRIG_SEL_TI2FP2 ((uint16_t)0x0060)
+#define TIM_TRIG_SEL_ETRF ((uint16_t)0x0070)
+#define IsTimTrigSel(SELECTION) \
+ (((SELECTION) == TIM_TRIG_SEL_IN_TR0) || ((SELECTION) == TIM_TRIG_SEL_IN_TR1) \
+ || ((SELECTION) == TIM_TRIG_SEL_IN_TR2) || ((SELECTION) == TIM_TRIG_SEL_IN_TR3) \
+ || ((SELECTION) == TIM_TRIG_SEL_TI1F_ED) || ((SELECTION) == TIM_TRIG_SEL_TI1FP1) \
+ || ((SELECTION) == TIM_TRIG_SEL_TI2FP2) || ((SELECTION) == TIM_TRIG_SEL_ETRF))
+#define IsTimInterTrigSel(SELECTION) \
+ (((SELECTION) == TIM_TRIG_SEL_IN_TR0) || ((SELECTION) == TIM_TRIG_SEL_IN_TR1) \
+ || ((SELECTION) == TIM_TRIG_SEL_IN_TR2) || ((SELECTION) == TIM_TRIG_SEL_IN_TR3))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_TIx_External_Clock_Source
+ * @{
+ */
+
+#define TIM_EXT_CLK_SRC_TI1 ((uint16_t)0x0050)
+#define TIM_EXT_CLK_SRC_TI2 ((uint16_t)0x0060)
+#define TIM_EXT_CLK_SRC_TI1ED ((uint16_t)0x0040)
+#define IsTimExtClkSrc(SOURCE) \
+ (((SOURCE) == TIM_EXT_CLK_SRC_TI1) || ((SOURCE) == TIM_EXT_CLK_SRC_TI2) || ((SOURCE) == TIM_EXT_CLK_SRC_TI1ED))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_External_Trigger_Polarity
+ * @{
+ */
+#define TIM_EXT_TRIG_POLARITY_INVERTED ((uint16_t)0x8000)
+#define TIM_EXT_TRIG_POLARITY_NONINVERTED ((uint16_t)0x0000)
+#define IsTimExtTrigPolarity(POLARITY) \
+ (((POLARITY) == TIM_EXT_TRIG_POLARITY_INVERTED) || ((POLARITY) == TIM_EXT_TRIG_POLARITY_NONINVERTED))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Prescaler_Reload_Mode
+ * @{
+ */
+
+#define TIM_PSC_RELOAD_MODE_UPDATE ((uint16_t)0x0000)
+#define TIM_PSC_RELOAD_MODE_IMMEDIATE ((uint16_t)0x0001)
+#define IsTimPscReloadMode(RELOAD) \
+ (((RELOAD) == TIM_PSC_RELOAD_MODE_UPDATE) || ((RELOAD) == TIM_PSC_RELOAD_MODE_IMMEDIATE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Forced_Action
+ * @{
+ */
+
+#define TIM_FORCED_ACTION_ACTIVE ((uint16_t)0x0050)
+#define TIM_FORCED_ACTION_INACTIVE ((uint16_t)0x0040)
+#define IsTimForceActive(OPERATE) (((OPERATE) == TIM_FORCED_ACTION_ACTIVE) || ((OPERATE) == TIM_FORCED_ACTION_INACTIVE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Encoder_Mode
+ * @{
+ */
+
+#define TIM_ENCODE_MODE_TI1 ((uint16_t)0x0001)
+#define TIM_ENCODE_MODE_TI2 ((uint16_t)0x0002)
+#define TIM_ENCODE_MODE_TI12 ((uint16_t)0x0003)
+#define IsTimEncodeMode(MODE) \
+ (((MODE) == TIM_ENCODE_MODE_TI1) || ((MODE) == TIM_ENCODE_MODE_TI2) || ((MODE) == TIM_ENCODE_MODE_TI12))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Event_Source
+ * @{
+ */
+
+#define TIM_EVT_SRC_UPDATE ((uint16_t)0x0001)
+#define TIM_EVT_SRC_CC1 ((uint16_t)0x0002)
+#define TIM_EVT_SRC_CC2 ((uint16_t)0x0004)
+#define TIM_EVT_SRC_CC3 ((uint16_t)0x0008)
+#define TIM_EVT_SRC_CC4 ((uint16_t)0x0010)
+#define TIM_EVT_SRC_COM ((uint16_t)0x0020)
+#define TIM_EVT_SRC_TRIG ((uint16_t)0x0040)
+#define TIM_EVT_SRC_BREAK ((uint16_t)0x0080)
+#define IsTimEvtSrc(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Update_Source
+ * @{
+ */
+
+#define TIM_UPDATE_SRC_GLOBAL \
+ ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow \
+ or the setting of UG bit, or an update generation \
+ through the slave mode controller. */
+#define TIM_UPDATE_SRC_REGULAr ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
+#define IsTimUpdateSrc(SOURCE) (((SOURCE) == TIM_UPDATE_SRC_GLOBAL) || ((SOURCE) == TIM_UPDATE_SRC_REGULAr))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_Preload_State
+ * @{
+ */
+
+#define TIM_OC_PRE_LOAD_ENABLE ((uint16_t)0x0008)
+#define TIM_OC_PRE_LOAD_DISABLE ((uint16_t)0x0000)
+#define IsTimOcPreLoadState(STATE) (((STATE) == TIM_OC_PRE_LOAD_ENABLE) || ((STATE) == TIM_OC_PRE_LOAD_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_Fast_State
+ * @{
+ */
+
+#define TIM_OC_FAST_ENABLE ((uint16_t)0x0004)
+#define TIM_OC_FAST_DISABLE ((uint16_t)0x0000)
+#define IsTimOcFastState(STATE) (((STATE) == TIM_OC_FAST_ENABLE) || ((STATE) == TIM_OC_FAST_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_Clear_State
+ * @{
+ */
+
+#define TIM_OC_CLR_ENABLE ((uint16_t)0x0080)
+#define TIM_OC_CLR_DISABLE ((uint16_t)0x0000)
+#define IsTimOcClrState(STATE) (((STATE) == TIM_OC_CLR_ENABLE) || ((STATE) == TIM_OC_CLR_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Trigger_Output_Source
+ * @{
+ */
+
+#define TIM_TRGO_SRC_RESET ((uint16_t)0x0000)
+#define TIM_TRGO_SRC_ENABLE ((uint16_t)0x0010)
+#define TIM_TRGO_SRC_UPDATE ((uint16_t)0x0020)
+#define TIM_TRGO_SRC_OC1 ((uint16_t)0x0030)
+#define TIM_TRGO_SRC_OC1REF ((uint16_t)0x0040)
+#define TIM_TRGO_SRC_OC2REF ((uint16_t)0x0050)
+#define TIM_TRGO_SRC_OC3REF ((uint16_t)0x0060)
+#define TIM_TRGO_SRC_OC4REF ((uint16_t)0x0070)
+#define IsTimTrgoSrc(SOURCE) \
+ (((SOURCE) == TIM_TRGO_SRC_RESET) || ((SOURCE) == TIM_TRGO_SRC_ENABLE) || ((SOURCE) == TIM_TRGO_SRC_UPDATE) \
+ || ((SOURCE) == TIM_TRGO_SRC_OC1) || ((SOURCE) == TIM_TRGO_SRC_OC1REF) || ((SOURCE) == TIM_TRGO_SRC_OC2REF) \
+ || ((SOURCE) == TIM_TRGO_SRC_OC3REF) || ((SOURCE) == TIM_TRGO_SRC_OC4REF))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Slave_Mode
+ * @{
+ */
+
+#define TIM_SLAVE_MODE_RESET ((uint16_t)0x0004)
+#define TIM_SLAVE_MODE_GATED ((uint16_t)0x0005)
+#define TIM_SLAVE_MODE_TRIG ((uint16_t)0x0006)
+#define TIM_SLAVE_MODE_EXT1 ((uint16_t)0x0007)
+#define IsTimSlaveMode(MODE) \
+ (((MODE) == TIM_SLAVE_MODE_RESET) || ((MODE) == TIM_SLAVE_MODE_GATED) || ((MODE) == TIM_SLAVE_MODE_TRIG) \
+ || ((MODE) == TIM_SLAVE_MODE_EXT1))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Master_Slave_Mode
+ * @{
+ */
+
+#define TIM_MASTER_SLAVE_MODE_ENABLE ((uint16_t)0x0080)
+#define TIM_MASTER_SLAVE_MODE_DISABLE ((uint16_t)0x0000)
+#define IsTimMasterSlaveMode(STATE) \
+ (((STATE) == TIM_MASTER_SLAVE_MODE_ENABLE) || ((STATE) == TIM_MASTER_SLAVE_MODE_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Flags
+ * @{
+ */
+
+#define TIM_FLAG_UPDATE ((uint32_t)0x0001)
+#define TIM_FLAG_CC1 ((uint32_t)0x0002)
+#define TIM_FLAG_CC2 ((uint32_t)0x0004)
+#define TIM_FLAG_CC3 ((uint32_t)0x0008)
+#define TIM_FLAG_CC4 ((uint32_t)0x0010)
+#define TIM_FLAG_COM ((uint32_t)0x0020)
+#define TIM_FLAG_TRIG ((uint32_t)0x0040)
+#define TIM_FLAG_BREAK ((uint32_t)0x0080)
+#define TIM_FLAG_CC1OF ((uint32_t)0x0200)
+#define TIM_FLAG_CC2OF ((uint32_t)0x0400)
+#define TIM_FLAG_CC3OF ((uint32_t)0x0800)
+#define TIM_FLAG_CC4OF ((uint32_t)0x1000)
+#define TIM_FLAG_CC5 ((uint32_t)0x010000)
+#define TIM_FLAG_CC6 ((uint32_t)0x020000)
+
+#define IsTimGetFlag(FLAG) \
+ (((FLAG) == TIM_FLAG_UPDATE) || ((FLAG) == TIM_FLAG_CC1) || ((FLAG) == TIM_FLAG_CC2) || ((FLAG) == TIM_FLAG_CC3) \
+ || ((FLAG) == TIM_FLAG_CC4) || ((FLAG) == TIM_FLAG_COM) || ((FLAG) == TIM_FLAG_TRIG) \
+ || ((FLAG) == TIM_FLAG_BREAK) || ((FLAG) == TIM_FLAG_CC1OF) || ((FLAG) == TIM_FLAG_CC2OF) \
+ || ((FLAG) == TIM_FLAG_CC3OF) || ((FLAG) == TIM_FLAG_CC4OF) || ((FLAG) == TIM_FLAG_CC5) \
+ || ((FLAG) == TIM_FLAG_CC6))
+
+#define IsTimClrFlag(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Input_Capture_Filer_Value
+ * @{
+ */
+
+#define IsTimInCapFilter(ICFILTER) ((ICFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_External_Trigger_Filter
+ * @{
+ */
+
+#define IsTimExtTrigFilter(EXTFILTER) ((EXTFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+#define TIM_CC1EN ((uint32_t)1<<0)
+#define TIM_CC1NEN ((uint32_t)1<<2)
+#define TIM_CC2EN ((uint32_t)1<<4)
+#define TIM_CC2NEN ((uint32_t)1<<6)
+#define TIM_CC3EN ((uint32_t)1<<8)
+#define TIM_CC3NEN ((uint32_t)1<<10)
+#define TIM_CC4EN ((uint32_t)1<<12)
+#define TIM_CC5EN ((uint32_t)1<<16)
+#define TIM_CC6EN ((uint32_t)1<<20)
+
+#define IsAdvancedTimCCENFlag(FLAG) \
+ (((FLAG) == TIM_CC1EN) || ((FLAG) == TIM_CC1NEN) || ((FLAG) == TIM_CC2EN) || ((FLAG) == TIM_CC2NEN) \
+ || ((FLAG) == TIM_CC3EN) || ((FLAG) == TIM_CC3NEN) \
+ || ((FLAG) == TIM_CC4EN) || ((FLAG) == TIM_CC5EN) || ((FLAG) == TIM_CC6EN) )
+#define IsGeneralTimCCENFlag(FLAG) \
+ (((FLAG) == TIM_CC1EN) || ((FLAG) == TIM_CC2EN) \
+ || ((FLAG) == TIM_CC3EN) \
+ || ((FLAG) == TIM_CC4EN) )
+
+/** @addtogroup TIM_Legacy
+ * @{
+ */
+
+#define TIM_DMA_BURST_LEN_1BYTE TIM_DMABURST_LENGTH_1TRANSFER
+#define TIM_DMA_BURST_LEN_2BYTES TIM_DMABURST_LENGTH_2TRANSFERS
+#define TIM_DMA_BURST_LEN_3BYTES TIM_DMABURST_LENGTH_3TRANSFERS
+#define TIM_DMA_BURST_LEN_4BYTES TIM_DMABURST_LENGTH_4TRANSFERS
+#define TIM_DMA_BURST_LEN_5BYTES TIM_DMABURST_LENGTH_5TRANSFERS
+#define TIM_DMA_BURST_LEN_6BYTES TIM_DMABURST_LENGTH_6TRANSFERS
+#define TIM_DMA_BURST_LEN_7BYTES TIM_DMABURST_LENGTH_7TRANSFERS
+#define TIM_DMA_BURST_LEN_8BYTES TIM_DMABURST_LENGTH_8TRANSFERS
+#define TIM_DMA_BURST_LEN_9BYTES TIM_DMABURST_LENGTH_9TRANSFERS
+#define TIM_DMA_BURST_LEN_10BYTES TIM_DMABURST_LENGTH_10TRANSFERS
+#define TIM_DMA_BURST_LEN_11BYTES TIM_DMABURST_LENGTH_11TRANSFERS
+#define TIM_DMA_BURST_LEN_12BYTES TIM_DMABURST_LENGTH_12TRANSFERS
+#define TIM_DMA_BURST_LEN_13BYTES TIM_DMABURST_LENGTH_13TRANSFERS
+#define TIM_DMA_BURST_LEN_14BYTES TIM_DMABURST_LENGTH_14TRANSFERS
+#define TIM_DMA_BURST_LEN_15BYTES TIM_DMABURST_LENGTH_15TRANSFERS
+#define TIM_DMA_BURST_LEN_16BYTES TIM_DMABURST_LENGTH_16TRANSFERS
+#define TIM_DMA_BURST_LEN_17BYTES TIM_DMABURST_LENGTH_17TRANSFERS
+#define TIM_DMA_BURST_LEN_18BYTES TIM_DMABURST_LENGTH_18TRANSFERS
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions
+ * @{
+ */
+
+void TIM_DeInit(TIM_Module* TIMx);
+void TIM_InitTimeBase(TIM_Module* TIMx, TIM_TimeBaseInitType* TIM_TimeBaseInitStruct);
+void TIM_InitOc1(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
+void TIM_InitOc2(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
+void TIM_InitOc3(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
+void TIM_InitOc4(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
+void TIM_InitOc5(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
+void TIM_InitOc6(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
+void TIM_ICInit(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct);
+void TIM_ConfigPwmIc(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct);
+void TIM_ConfigBkdt(TIM_Module* TIMx, TIM_BDTRInitType* TIM_BDTRInitStruct);
+void TIM_InitTimBaseStruct(TIM_TimeBaseInitType* TIM_TimeBaseInitStruct);
+void TIM_InitOcStruct(OCInitType* TIM_OCInitStruct);
+void TIM_InitIcStruct(TIM_ICInitType* TIM_ICInitStruct);
+void TIM_InitBkdtStruct(TIM_BDTRInitType* TIM_BDTRInitStruct);
+void TIM_Enable(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_EnableCtrlPwmOutputs(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_ConfigInt(TIM_Module* TIMx, uint16_t TIM_IT, FunctionalState Cmd);
+void TIM_GenerateEvent(TIM_Module* TIMx, uint16_t TIM_EventSource);
+void TIM_ConfigDma(TIM_Module* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
+void TIM_EnableDma(TIM_Module* TIMx, uint16_t TIM_DMASource, FunctionalState Cmd);
+void TIM_ConfigInternalClk(TIM_Module* TIMx);
+void TIM_ConfigInternalTrigToExt(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_ConfigExtTrigAsClk(TIM_Module* TIMx,
+ uint16_t TIM_TIxExternalCLKSource,
+ uint16_t IcPolarity,
+ uint16_t ICFilter);
+void TIM_ConfigExtClkMode1(TIM_Module* TIMx,
+ uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter);
+void TIM_ConfigExtClkMode2(TIM_Module* TIMx,
+ uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter);
+void TIM_ConfigExtTrig(TIM_Module* TIMx,
+ uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter);
+void TIM_ConfigPrescaler(TIM_Module* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
+void TIM_ConfigCntMode(TIM_Module* TIMx, uint16_t CntMode);
+void TIM_SelectInputTrig(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_ConfigEncoderInterface(TIM_Module* TIMx,
+ uint16_t TIM_EncoderMode,
+ uint16_t TIM_IC1Polarity,
+ uint16_t TIM_IC2Polarity);
+void TIM_ConfigForcedOc1(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ConfigForcedOc2(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ConfigForcedOc3(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ConfigForcedOc4(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ConfigForcedOc5(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ConfigForcedOc6(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ConfigArPreload(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_SelectComEvt(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_SelectCapCmpDmaSrc(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_EnableCapCmpPreloadControl(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_ConfigOc1Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload);
+void TIM_ConfigOc2Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload);
+void TIM_ConfigOc3Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload);
+void TIM_ConfigOc4Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload);
+void TIM_ConfigOc5Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload);
+void TIM_ConfigOc6Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload);
+void TIM_ConfigOc1Fast(TIM_Module* TIMx, uint16_t TIM_OCFast);
+void TIM_ConfigOc2Fast(TIM_Module* TIMx, uint16_t TIM_OCFast);
+void TIM_ConfigOc3Fast(TIM_Module* TIMx, uint16_t TIM_OCFast);
+void TIM_ConfigOc4Fast(TIM_Module* TIMx, uint16_t TIM_OCFast);
+void TIM_ConfigOc5Fast(TIM_Module* TIMx, uint16_t TIM_OCFast);
+void TIM_ConfigOc6Fast(TIM_Module* TIMx, uint16_t TIM_OCFast);
+void TIM_ClrOc1Ref(TIM_Module* TIMx, uint16_t TIM_OCClear);
+void TIM_ClrOc2Ref(TIM_Module* TIMx, uint16_t TIM_OCClear);
+void TIM_ClrOc3Ref(TIM_Module* TIMx, uint16_t TIM_OCClear);
+void TIM_ClrOc4Ref(TIM_Module* TIMx, uint16_t TIM_OCClear);
+void TIM_ClrOc5Ref(TIM_Module* TIMx, uint16_t TIM_OCClear);
+void TIM_ClrOc6Ref(TIM_Module* TIMx, uint16_t TIM_OCClear);
+void TIM_ConfigOc1Polarity(TIM_Module* TIMx, uint16_t OcPolarity);
+void TIM_ConfigOc1NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity);
+void TIM_ConfigOc2Polarity(TIM_Module* TIMx, uint16_t OcPolarity);
+void TIM_ConfigOc2NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity);
+void TIM_ConfigOc3Polarity(TIM_Module* TIMx, uint16_t OcPolarity);
+void TIM_ConfigOc3NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity);
+void TIM_ConfigOc4Polarity(TIM_Module* TIMx, uint16_t OcPolarity);
+void TIM_ConfigOc5Polarity(TIM_Module* TIMx, uint16_t OcPolarity);
+void TIM_ConfigOc6Polarity(TIM_Module* TIMx, uint16_t OcPolarity);
+void TIM_EnableCapCmpCh(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCx);
+void TIM_EnableCapCmpChN(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCxN);
+void TIM_SelectOcMode(TIM_Module* TIMx, uint16_t Channel, uint16_t OcMode);
+void TIM_EnableUpdateEvt(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_ConfigUpdateRequestIntSrc(TIM_Module* TIMx, uint16_t TIM_UpdateSource);
+void TIM_SelectHallSensor(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_SelectOnePulseMode(TIM_Module* TIMx, uint16_t TIM_OPMode);
+void TIM_SelectOutputTrig(TIM_Module* TIMx, uint16_t TIM_TRGOSource);
+void TIM_SelectSlaveMode(TIM_Module* TIMx, uint16_t TIM_SlaveMode);
+void TIM_SelectMasterSlaveMode(TIM_Module* TIMx, uint16_t TIM_MasterSlaveMode);
+void TIM_SetCnt(TIM_Module* TIMx, uint16_t Counter);
+void TIM_SetAutoReload(TIM_Module* TIMx, uint16_t Autoreload);
+void TIM_SetCmp1(TIM_Module* TIMx, uint16_t Compare1);
+void TIM_SetCmp2(TIM_Module* TIMx, uint16_t Compare2);
+void TIM_SetCmp3(TIM_Module* TIMx, uint16_t Compare3);
+void TIM_SetCmp4(TIM_Module* TIMx, uint16_t Compare4);
+void TIM_SetCmp5(TIM_Module* TIMx, uint16_t Compare5);
+void TIM_SetCmp6(TIM_Module* TIMx, uint16_t Compare6);
+void TIM_SetInCap1Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetInCap2Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetInCap3Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetInCap4Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetClkDiv(TIM_Module* TIMx, uint16_t TIM_CKD);
+uint16_t TIM_GetCap1(TIM_Module* TIMx);
+uint16_t TIM_GetCap2(TIM_Module* TIMx);
+uint16_t TIM_GetCap3(TIM_Module* TIMx);
+uint16_t TIM_GetCap4(TIM_Module* TIMx);
+uint16_t TIM_GetCap5(TIM_Module* TIMx);
+uint16_t TIM_GetCap6(TIM_Module* TIMx);
+uint16_t TIM_GetCnt(TIM_Module* TIMx);
+uint16_t TIM_GetPrescaler(TIM_Module* TIMx);
+uint16_t TIM_GetAutoReload(TIM_Module* TIMx);
+FlagStatus TIM_GetCCENStatus(TIM_Module* TIMx, uint32_t TIM_CCEN);
+FlagStatus TIM_GetFlagStatus(TIM_Module* TIMx, uint32_t TIM_FLAG);
+void TIM_ClearFlag(TIM_Module* TIMx, uint32_t TIM_FLAG);
+INTStatus TIM_GetIntStatus(TIM_Module* TIMx, uint32_t TIM_IT);
+void TIM_ClrIntPendingBit(TIM_Module* TIMx, uint32_t TIM_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32G43X_TIM_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_tsc.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_tsc.h
new file mode 100644
index 0000000000..0caa247c90
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_tsc.h
@@ -0,0 +1,485 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_tsc.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_TSC_H__
+#define __N32G43X_TSC_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43X_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup TSC
+ * @{
+ */
+
+/**
+ * @brief TSC error code
+ */
+ typedef enum {
+ TSC_ERROR_OK = 0x00U, /*!< No error */
+ TSC_ERROR_CLOCK = 0x01U, /*!< clock config error */
+ TSC_ERROR_PARAMETER = 0x02U, /*!< parameter error */
+ TSC_ERROR_HW_MODE = 0x03U, /*!< Exit hw mode timeout */
+
+ }TSC_ErrorTypeDef;
+ /**
+ * @
+ */
+
+/**
+ * @brief TSC clock source
+ */
+#define TSC_CLK_SRC_LSI (RCC_LSXCLK_SRC_LSI) /*!< LSI*/
+#define TSC_CLK_SRC_LSE (RCC_LSE_ENABLE|RCC_LSXCLK_SRC_LSE) /*!< LSE */
+#define TSC_CLK_SRC_LSE_BYPASS (RCC_LSE_BYPASS|RCC_LSXCLK_SRC_LSE) /*!< LSE bypass */
+/**
+ * @
+ */
+
+
+/**
+ * @defgroup Detect_Period
+ */
+#define TSC_DET_PERIOD_8 (0x00000000U) /*!< DET_PERIOD[3:0] = 8/TSC_CLOCK */
+#define TSC_DET_PERIOD_16 (0x01UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000001U DET_PERIOD[3:0] = 16/TSC_CLOCK */
+#define TSC_DET_PERIOD_24 (0x02UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000002U DET_PERIOD[3:0] = 24/TSC_CLOCK */
+#define TSC_DET_PERIOD_32 (0x03UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000003U DET_PERIOD[3:0] = 32/TSC_CLOCK(default) */
+#define TSC_DET_PERIOD_40 (0x04UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000004U DET_PERIOD[3:0] = 40/TSC_CLOCK */
+#define TSC_DET_PERIOD_48 (0x05UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000005U DET_PERIOD[3:0] = 48/TSC_CLOCK */
+#define TSC_DET_PERIOD_56 (0x06UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000006U DET_PERIOD[3:0] = 56/TSC_CLOCK */
+#define TSC_DET_PERIOD_64 (0x07UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000007U DET_PERIOD[3:0] = 64/TSC_CLOCK */
+#define TSC_DET_PERIOD_72 (0x08UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000008U DET_PERIOD[3:0] = 72/TSC_CLOCK */
+#define TSC_DET_PERIOD_80 (0x09UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000009U DET_PERIOD[3:0] = 80/TSC_CLOCK */
+#define TSC_DET_PERIOD_88 (0x0AUL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x0000000AU DET_PERIOD[3:0] = 88/TSC_CLOCK */
+#define TSC_DET_PERIOD_96 (0x0BUL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x0000000BU DET_PERIOD[3:0] = 96/TSC_CLOCK */
+#define TSC_DET_PERIOD_104 (0x0CUL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x0000000CU DET_PERIOD[3:0] = 104/TSC_CLOCK */
+/**
+ * @
+ */
+
+/**
+ * @defgroup Detect_Filter
+ */
+#define TSC_DET_FILTER_1 (0x00000000U) /*!< DET_FILTER[3:0] = 1 sample */
+#define TSC_DET_FILTER_2 (0x01UL << TSC_CTRL_DET_FILTER_Pos) /*!< 0x00000010U DET_FILTER[3:0] = 2 samples */
+#define TSC_DET_FILTER_3 (0x02UL << TSC_CTRL_DET_FILTER_Pos) /*!< 0x00000020U DET_FILTER[3:0] = 3 samples */
+#define TSC_DET_FILTER_4 (0x03UL << TSC_CTRL_DET_FILTER_Pos) /*!< 0x00000030U DET_FILTER[3:0] = 4 samples */
+/**
+ * @
+ */
+
+/**
+ * @defgroup HW_Detect_Mode
+ */
+#define TSC_HW_DET_MODE_DISABLE (0x00000000U) /*!< Hardware detect mode disable */
+#define TSC_HW_DET_MODE_ENABLE (0x01UL << TSC_CTRL_HW_DET_MODE_Pos) /*!< 0x00000040U Hardware detect mode enable */
+/**
+ * @
+ */
+
+/**
+ * @defgroup Detect_Type
+ */
+#define TSC_DET_TYPE_Msk (TSC_CTRL_LESS_DET_SEL_Msk|TSC_CTRL_GREAT_DET_SEL_Msk)
+#define TSC_DET_TYPE_Pos (TSC_CTRL_LESS_DET_SEL_Pos)
+
+#define TSC_DET_TYPE_NONE (0UL) /*!< 0x00000000U Disable detect */
+#define TSC_DET_TYPE_LESS (0x01UL << TSC_DET_TYPE_Pos) /*!< 0x00000100U Less detect enable */
+#define TSC_DET_TYPE_GREAT (0x02UL << TSC_DET_TYPE_Pos) /*!< 0x00000200U Great detect enable */
+#define TSC_DET_TYPE_PERIOD (0x03UL << TSC_DET_TYPE_Pos) /*!< 0x00000300U Both great and less detct enable */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_Interrupt
+ */
+#define TSC_IT_DET_ENABLE (TSC_CTRL_DET_INTEN) /*!< Enable TSC detect interrupt */
+#define TSC_IT_DET_DISABLE (0UL) /*!< Disable TSC detect interrupt */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_Out
+ */
+#define TSC_OUT_PIN (0x00000000U) /*!< TSC output to TSC_OUT pin */
+#define TSC_OUT_TIM4_ETR (0x1UL << TSC_CTRL_TM4_ETR_Pos) /*!< TSC output to TIM4 ETR */
+#define TSC_OUT_TIM2_ETR (0x2UL << TSC_CTRL_TM4_ETR_Pos) /*!< TSC output to TIM2 ETR and TIM2 CH1*/
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_Flag
+ */
+#define TSC_FLAG_HW (0x1UL << TSC_CTRL_HW_DET_ST_Pos) /*!< Flag of hardware detect mode */
+
+#define TSC_FLAG_GREAT_DET (0x1UL << TSC_STS_GREAT_DET_Pos) /*!< Flag of great detect type */
+#define TSC_FLAG_LESS_DET (0x1UL << TSC_STS_LESS_DET_Pos) /*!< Flag of less detect type */
+#define TSC_FLAG_PERIOD_DET (TSC_FLAG_GREAT_DET|TSC_FLAG_LESS_DET) /*!< Flag of period detect type */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_SW_Detect
+ */
+#define TSC_SW_MODE_DISABLE (0x00000000U) /*!< Disable software detect mode */
+#define TSC_SW_MODE_ENABLE (0x1UL << TSC_ANA_CTRL_SW_TSC_EN_Pos) /*!< Enable software detect mode */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_PadOption
+ */
+#define TSC_PAD_INTERNAL_RES (0x00000000U) /*!< Use internal resistor */
+#define TSC_PAD_EXTERNAL_RES (0x1UL << TSC_ANA_SEL_PAD_OPT_Pos) /*!< Use external resistor */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_PadSpeed
+ */
+#define TSC_PAD_SPEED_0 (0x00000000U) /*!< Low speed,about 100K */
+#define TSC_PAD_SPEED_1 (0x1UL << TSC_ANA_SEL_SP_OPT_Pos) /*!< Middle spped */
+#define TSC_PAD_SPEED_2 (0x2UL << TSC_ANA_SEL_SP_OPT_Pos) /*!< Middle spped */
+#define TSC_PAD_SPEED_3 (0x3UL << TSC_ANA_SEL_SP_OPT_Pos) /*!< Middle spped */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_Constant
+ */
+#define TSC_CHN_SEL_ALL (TSC_CHNEN_CHN_SELx_Msk)
+#define MAX_TSC_HW_CHN (24) /*Maximum number of tsc pin*/
+#define MAX_TSC_THRESHOLD_BASE (2047) /*Maximum detect base value of threshold*/
+#define MAX_TSC_THRESHOLD_DELTA (255) /*Maximum detect delta value of threshold*/
+#define TSC_TIMEOUT (0x01000000) /*TSC normal timeout */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_DetectMode
+ */
+#define TSC_HW_DETECT_MODE (0x00000001U) /*TSC hardware detect mode*/
+#define TSC_SW_DETECT_MODE (0x00000000U) /*TSC software detect mode*/
+/**
+ * @
+ */
+
+/* TSC Exported macros -----------------------------------------------------------*/
+/** @defgroup TSC_Exported_Macros
+ * @{
+ */
+
+/** @brief Enable the TSC HW detect mode
+ * @param None
+ * @retval None
+ */
+#define __TSC_HW_ENABLE() SET_BIT(TSC->CTRL, TSC_HW_DET_MODE_ENABLE)
+
+/** @brief Disable the TSC HW detect mode
+ * @param None
+ * @retval None
+ */
+#define __TSC_HW_DISABLE() CLEAR_BIT(TSC->CTRL, TSC_HW_DET_MODE_ENABLE)
+
+/** @brief Config TSC detect period for HW detect mode
+ * @param __PERIOD__ specifies the TSC detect period during HW detect mode
+ * @arg TSC_DET_PERIOD_8: Detect period = 8/TSC_CLK
+ * @arg TSC_DET_PERIOD_16: Detect Period = 1/TSC_CLK
+ * @arg TSC_DET_PERIOD_24: Detect Period = 2/TSC_CLK
+ * @arg TSC_DET_PERIOD_32: Detect Period = 3/TSC_CLK
+ * @arg TSC_DET_PERIOD_40: Detect Period = 4/TSC_CLK
+ * @arg TSC_DET_PERIOD_48: Detect Period = 5/TSC_CLK
+ * @arg TSC_DET_PERIOD_56: Detect Period = 6/TSC_CLK
+ * @arg TSC_DET_PERIOD_64: Detect Period = 7/TSC_CLK
+ * @arg TSC_DET_PERIOD_72: Detect Period = 7/TSC_CLK
+ * @arg TSC_DET_PERIOD_80: Detect Period = 7/TSC_CLK
+ * @arg TSC_DET_PERIOD_88: Detect Period = 7/TSC_CLK
+ * @arg TSC_DET_PERIOD_96: Detect Period = 7/TSC_CLK
+ * @arg TSC_DET_PERIOD_104:Detect Period = 7/TSC_CLK
+ * @retval None
+ */
+#define __TSC_PERIOD_CONFIG(__PERIOD__) MODIFY_REG(TSC->CTRL, TSC_CTRL_DET_PERIOD_Msk,__PERIOD__)
+
+/** @brief Config TSC detect filter for HW detect mode
+ * @param __FILTER__ specifies the least usefull continuous samples during HW detect mode
+ * @arg TSC_DET_FILTER_1: Detect filter = 1 pulse
+ * @arg TSC_DET_FILTER_2: Detect filter = 2 pulse
+ * @arg TSC_DET_FILTER_3: Detect filter = 3 pulse
+ * @arg TSC_DET_FILTER_4: Detect filter = 4 pulse
+ * @retval None
+ */
+#define __TSC_FILTER_CONFIG(__FILTER__) MODIFY_REG(TSC->CTRL, TSC_CTRL_DET_FILTER_Msk,__FILTER__)
+
+/** @brief Config TSC detect type for HW detect mode,less great or both
+ * @param __TYPE__ specifies the detect type of a sample during HW detect mode
+ * @arg TSC_DET_TYPE_NONE: Detect disable
+ * @arg TSC_DET_TYPE_LESS: Pulse number must be greater than the threshold(basee-delta) during a sample time
+ * @arg TSC_DET_TYPE_GREAT: Pulse number must be less than the threshold(basee+delta) during a sample time
+ * @arg TSC_DET_TYPE_PERIOD:Pulse number must be greater than (basee-delta)
+ and also be less than (basee+delta) during a sample time
+ * @retval None
+ */
+#define __TSC_LESS_GREAT_CONFIG(__TYPE__) MODIFY_REG(TSC->CTRL, \
+ (TSC_CTRL_LESS_DET_SEL_Msk|TSC_CTRL_GREAT_DET_SEL_Msk), \
+ __TYPE__)
+
+/** @brief Enable TSC interrupt
+ * @param None
+ * @retval None
+ */
+#define __TSC_INT_ENABLE() SET_BIT(TSC->CTRL, TSC_IT_DET_ENABLE)
+
+/** @brief Disable TSC interrupt
+ * @param None
+ * @retval None
+ */
+#define __TSC_INT_DISABLE() CLEAR_BIT(TSC->CTRL, TSC_IT_DET_ENABLE)
+
+/** @brief Config the TSC output
+ * @param __OUT__ specifies where the TSC output should go
+ * @arg TSC_OUT_PIN: TSC output to the TSC_OUT pin
+ * @arg TSC_OUT_TIM4_ETR: TSC output to TIM4 as ETR
+ * @arg TSC_OUT_TIM2_ETR: TSC output to TIM2 as ETR
+ * @retval None
+ */
+#define __TSC_OUT_CONFIG(__OUT__) MODIFY_REG( TSC->CTRL, \
+ (TSC_CTRL_TM4_ETR_Msk|TSC_CTRL_TM2_ETR_CH1_Msk),\
+ __OUT__)
+
+/** @brief Config the TSC channel
+ * @param __CHN__ specifies the pin of channels used for detect
+ * This parameter:bit[0:23] used,bit[24:31] must be 0
+ * bitx: TSC channel x
+ * @retval None
+ */
+#define __TSC_CHN_CONFIG(__CHN__) WRITE_REG(TSC->CHNEN, __CHN__)
+
+/** @brief Enable the TSC SW detect mode
+ * @param None
+ * @retval None
+ */
+#define __TSC_SW_ENABLE() SET_BIT(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_TSC_EN)
+
+/** @brief Disable the TSC SW detect mode
+ * @param None
+ * @retval None
+ */
+#define __TSC_SW_DISABLE() CLEAR_BIT(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_TSC_EN)
+
+/** @brief Config the detect channel number during SW detect mode
+ * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN
+ * @retval None
+ */
+#define __TSC_SW_CHN_NUM_CONFIG(__NUM__) MODIFY_REG(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_PAD_MUX_Msk,__NUM__)
+
+/** @brief Config the pad charge type
+ * @param __OPT__ specifies which resistor is used for charge
+ * @arg TSC_PAD_INTERNAL_RES: Internal resistor is used
+ * @arg TSC_PAD_EXTERNAL_RES: External resistor is used
+ * @retval None
+ */
+#define __TSC_PAD_OPT_CONFIG(__OPT__) MODIFY_REG(TSC->ANA_SEL, TSC_ANA_SEL_PAD_OPT_Msk,__OPT__)
+
+/** @brief Config TSC speed
+ * @param __SPEED__ specifies the TSC speed range
+ * @arg TSC_PAD_SPEED_0: Low speed
+ * @arg TSC_PAD_SPEED_1: Middle speed
+ * @arg TSC_PAD_SPEED_2: Middle speed
+ * @arg TSC_PAD_SPEED_3: High speed
+ * @retval None
+ */
+#define __TSC_PAD_SPEED_CONFIG(__SPEED__) MODIFY_REG(TSC->ANA_SEL, TSC_ANA_SEL_SP_OPT_Msk,__SPEED__)
+
+
+/** @brief Check if the HW detect mode is enable
+ * @param None
+ * @retval Current state of HW detect mode
+ */
+#define __TSC_GET_HW_MODE() (((TSC->CTRL) & TSC_FLAG_HW) == (TSC_FLAG_HW))
+
+/** @brief Check the detect type during HW detect mode
+ * @param __FLAG__ specifies the flag of detect type
+ * @arg TSC_FLAG_LESS_DET: Flag of less detect type
+ * @arg TSC_FLAG_GREAT_DET: Flag of great detect type
+ * @arg TSC_FLAG_PERIOD_DET: Flag of priod detect type
+ * @retval Current state of flag
+ */
+#define __TSC_GET_HW_DET_TYPE(__FLAG__) (((TSC->STS) & (__FLAG__))==(__FLAG__))
+
+/** @brief Get the number of channel which is detected now
+ * @param None
+ * @retval Current channel number
+ */
+#define __TSC_GET_CHN_NUMBER() (((TSC->STS) & TSC_STS_CHN_NUM_Msk) >> TSC_STS_CHN_NUM_Pos )
+
+/** @brief Get the count value of pulse
+ * @param None
+ * @retval Pulse count of current channel
+ */
+#define __TSC_GET_CHN_CNT() (((TSC->STS) & TSC_STS_CNT_VAL_Msk ) >> TSC_STS_CNT_VAL_Pos )
+
+/** @brief Get the base value of one channel
+ * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN
+ * @retval base value of the channel
+ */
+#define __TSC_GET_CHN_BASE(__NUM__) ((TSC->THRHD[(__NUM__)] & TSC_THRHDx_BASE_Msk ) >> TSC_THRHDx_BASE_Pos)
+
+/** @brief Get the delta value of one channel
+ * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN
+ * @retval delta value of the channel
+ */
+#define __TSC_GET_CHN_DELTA(__NUM__) ((TSC->THRHD[(__NUM__)] & TSC_THRHDx_DELTA_Msk ) >> TSC_THRHDx_DELTA_Pos )
+
+/** @brief Get the internal resist value of one channel
+ * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN
+ * @retval resist value of the channel
+ */
+#define __TSC_GET_CHN_RESIST(__NUM__) ((TSC->RESR[(__NUM__)>>3] >>(((__NUM__) & 0x7UL)*4)) & TSC_RESRx_CHN_RESIST_Msk)
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TSC_Private_Macros
+ * @{
+ */
+#define IS_TSC_DET_PERIOD(_PERIOD_) \
+ (((_PERIOD_)==TSC_DET_PERIOD_8) ||((_PERIOD_)==TSC_DET_PERIOD_16)||((_PERIOD_)==TSC_DET_PERIOD_24) \
+ ||((_PERIOD_)==TSC_DET_PERIOD_32)||((_PERIOD_)==TSC_DET_PERIOD_40)||((_PERIOD_)==TSC_DET_PERIOD_48) \
+ ||((_PERIOD_)==TSC_DET_PERIOD_56)||((_PERIOD_)==TSC_DET_PERIOD_64)||((_PERIOD_)==TSC_DET_PERIOD_72) \
+ ||((_PERIOD_)==TSC_DET_PERIOD_80)||((_PERIOD_)==TSC_DET_PERIOD_88)||((_PERIOD_)==TSC_DET_PERIOD_96) \
+ ||((_PERIOD_)==TSC_DET_PERIOD_104) )
+
+#define IS_TSC_FILTER(_FILTER_) \
+ ( ((_FILTER_)==TSC_DET_FILTER_1) ||((_FILTER_)==TSC_DET_FILTER_2)\
+ ||((_FILTER_)==TSC_DET_FILTER_3) ||((_FILTER_)==TSC_DET_FILTER_4) )
+
+#define IS_TSC_DET_MODE(_MODE_) \
+ ( ((_MODE_)==TSC_HW_DETECT_MODE) ||((_MODE_)==TSC_SW_DETECT_MODE) )
+
+#define IS_TSC_DET_TYPE(_TYPE_) \
+ ( ((_TYPE_)==TSC_DET_TYPE_GREAT) ||((_TYPE_)==TSC_DET_TYPE_LESS) \
+ ||((_TYPE_)==TSC_DET_TYPE_PERIOD)|| ((_TYPE_)==TSC_DET_TYPE_NONE) )
+
+#define IS_TSC_INT(_INT_) (((_INT_)==TSC_IT_DET_ENABLE)||((_INT_)==TSC_IT_DET_DISABLE))
+
+#define IS_TSC_OUT(_ETR_) (((_ETR_)==TSC_OUT_PIN)||((_ETR_)==TSC_OUT_TIM2_ETR)||((_ETR_)==TSC_OUT_TIM4_ETR))
+
+#define IS_TSC_CHN(_CHN_) (0==((_CHN_)&(~TSC_CHNEN_CHN_SELx_Msk)))
+
+#define IS_TSC_CHN_NUMBER(_NUM_) ( ((_NUM_)==1) \
+ ||(((_NUM_)>=4) && ((_NUM_)<=17)) \
+ ||(((_NUM_)>=19) && ((_NUM_)<=23)) )
+
+#define IS_TSC_PAD_OPTION(_OPT_) (((_OPT_)==TSC_PAD_INTERNAL_RES)||((_OPT_)==TSC_PAD_EXTERNAL_RES))
+
+#define IS_TSC_PAD_SPEED(_SPEED_) \
+ ( ((_SPEED_)==TSC_PAD_SPEED_0)||((_SPEED_)==TSC_PAD_SPEED_1) \
+ ||((_SPEED_)==TSC_PAD_SPEED_2)||((_SPEED_)==TSC_PAD_SPEED_3) )
+
+#define IS_TSC_RESISTOR_VALUE(_RES_) \
+ ( ((_RES_)==TSC_RESRx_CHN_RESIST_0)||((_RES_)==TSC_RESRx_CHN_RESIST_1) \
+ ||((_RES_)==TSC_RESRx_CHN_RESIST_2)||((_RES_)==TSC_RESRx_CHN_RESIST_3) \
+ ||((_RES_)==TSC_RESRx_CHN_RESIST_4)||((_RES_)==TSC_RESRx_CHN_RESIST_5) \
+ ||((_RES_)==TSC_RESRx_CHN_RESIST_6)||((_RES_)==TSC_RESRx_CHN_RESIST_7) )
+
+#define IS_TSC_THRESHOLD_BASE(_BASE_) ( (_BASE_)<=MAX_TSC_THRESHOLD_BASE)
+
+
+#define IS_TSC_THRESHOLD_DELTA(_DELTA_) ( (_DELTA_)<=MAX_TSC_THRESHOLD_DELTA)
+
+/**
+* @brief TSC Init structure definition
+*/
+
+typedef struct
+{
+ uint32_t Mode; /*!< Configures the TSC work mode.
+ This parameter can be one value of @ref TSC_DetectMode */
+ uint32_t Period; /*!< Configures the TSC check period for a sample.
+ This parameter can be one value of @ref Detect_Period */
+ uint32_t Filter; /*!< Configures the TSC filter.
+ This parameter can be one value of @ref Detect_Filter */
+ uint32_t Type; /*!< Configures the TSC check type
+ This parameter can be one value of @ref Detect_Type */
+ uint32_t Chn; /*!< Selects the TSC chnnel used
+ This parameter can be one value of @ref TSC_CHNEN_CHN_SELx_Msk */
+ uint32_t Out; /*!< Configures the TSC_OUT etr
+ This parameter can be one value of @ref TSC_Out */
+ uint32_t Int; /*!< Configures the TSC interrupt
+ This parameter can be one value of @ref TSC_Interrupt */
+ uint32_t PadOpt; /*!< Configures the TSC charge resistor
+ This parameter can be one value of @ref TSC_PadOption */
+ uint32_t Speed; /*!< Configures the TSC detect speed
+ This parameter can be one value of @ref TSC_PadSpeed */
+}TSC_InitType;
+
+typedef struct
+{
+ uint16_t TSC_Base; /*!< base value */
+ uint8_t TSC_Delta; /*!< offset value */
+ uint8_t TSC_Resistor; /*!< resistance value configuration*/
+} TSC_ChnCfg;
+
+TSC_ErrorTypeDef TSC_Init(TSC_InitType* InitParam);
+TSC_ErrorTypeDef TSC_ClockConfig(uint32_t TSC_ClkSource);
+TSC_ErrorTypeDef TSC_ConfigInternalResistor(uint32_t Channels, uint32_t res );
+TSC_ErrorTypeDef TSC_ConfigThreshold( uint32_t Channels, uint32_t base, uint32_t delta);
+TSC_ErrorTypeDef TSC_GetChannelCfg( TSC_ChnCfg* ChnCfg, uint32_t ChannelNum);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32G43X_TSC_H__ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_usart.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_usart.h
new file mode 100644
index 0000000000..5eefc26b1a
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_usart.h
@@ -0,0 +1,397 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_usart.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43x_USART_H__
+#define __N32G43x_USART_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup USART
+ * @{
+ */
+
+/** @addtogroup USART_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief USART Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the USART communication baud rate.
+ The baud rate is computed using the following formula:
+ - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->BaudRate)))
+ - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
+
+ uint16_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref USART_Word_Length */
+
+ uint16_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref USART_Stop_Bits */
+
+ uint16_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint16_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref Mode */
+
+ uint16_t HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
+ or disabled.
+ This parameter can be a value of @ref USART_Hardware_Flow_Control */
+} USART_InitType;
+
+/**
+ * @brief USART Clock Init Structure definition
+ */
+
+typedef struct
+{
+ uint16_t Clock; /*!< Specifies whether the USART clock is enabled or disabled.
+ This parameter can be a value of @ref Clock */
+
+ uint16_t Polarity; /*!< Specifies the steady state value of the serial clock.
+ This parameter can be a value of @ref USART_Clock_Polarity */
+
+ uint16_t Phase; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref USART_Clock_Phase */
+
+ uint16_t LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref USART_Last_Bit */
+} USART_ClockInitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Exported_Constants
+ * @{
+ */
+
+#define IS_USART_ALL_PERIPH(PERIPH) \
+ (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3) || ((PERIPH) == UART4) || ((PERIPH) == UART5))
+
+#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3))
+
+#define IS_USART_1234_PERIPH(PERIPH) \
+ (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3) || ((PERIPH) == UART4))
+/** @addtogroup USART_Word_Length
+ * @{
+ */
+
+#define USART_WL_8B ((uint16_t)0x0000)
+#define USART_WL_9B ((uint16_t)0x1000)
+
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WL_8B) || ((LENGTH) == USART_WL_9B))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Stop_Bits
+ * @{
+ */
+
+#define USART_STPB_1 ((uint16_t)0x0000)
+#define USART_STPB_0_5 ((uint16_t)0x1000)
+#define USART_STPB_2 ((uint16_t)0x2000)
+#define USART_STPB_1_5 ((uint16_t)0x3000)
+#define IS_USART_STOPBITS(STOPBITS) \
+ (((STOPBITS) == USART_STPB_1) || ((STOPBITS) == USART_STPB_0_5) || ((STOPBITS) == USART_STPB_2) \
+ || ((STOPBITS) == USART_STPB_1_5))
+/**
+ * @}
+ */
+
+/** @addtogroup Parity
+ * @{
+ */
+
+#define USART_PE_NO ((uint16_t)0x0000)
+#define USART_PE_EVEN ((uint16_t)0x0400)
+#define USART_PE_ODD ((uint16_t)0x0600)
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PE_NO) || ((PARITY) == USART_PE_EVEN) || ((PARITY) == USART_PE_ODD))
+/**
+ * @}
+ */
+
+/** @addtogroup Mode
+ * @{
+ */
+
+#define USART_MODE_RX ((uint16_t)0x0004)
+#define USART_MODE_TX ((uint16_t)0x0008)
+#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Hardware_Flow_Control
+ * @{
+ */
+#define USART_HFCTRL_NONE ((uint16_t)0x0000)
+#define USART_HFCTRL_RTS ((uint16_t)0x0100)
+#define USART_HFCTRL_CTS ((uint16_t)0x0200)
+#define USART_HFCTRL_RTS_CTS ((uint16_t)0x0300)
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL) \
+ (((CONTROL) == USART_HFCTRL_NONE) || ((CONTROL) == USART_HFCTRL_RTS) || ((CONTROL) == USART_HFCTRL_CTS) \
+ || ((CONTROL) == USART_HFCTRL_RTS_CTS))
+/**
+ * @}
+ */
+
+/** @addtogroup Clock
+ * @{
+ */
+#define USART_CLK_DISABLE ((uint16_t)0x0000)
+#define USART_CLK_ENABLE ((uint16_t)0x0800)
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLK_DISABLE) || ((CLOCK) == USART_CLK_ENABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Clock_Polarity
+ * @{
+ */
+
+#define USART_CLKPOL_LOW ((uint16_t)0x0000)
+#define USART_CLKPOL_HIGH ((uint16_t)0x0400)
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CLKPOL_LOW) || ((CPOL) == USART_CLKPOL_HIGH))
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Clock_Phase
+ * @{
+ */
+
+#define USART_CLKPHA_1EDGE ((uint16_t)0x0000)
+#define USART_CLKPHA_2EDGE ((uint16_t)0x0200)
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CLKPHA_1EDGE) || ((CPHA) == USART_CLKPHA_2EDGE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Last_Bit
+ * @{
+ */
+
+#define USART_CLKLB_DISABLE ((uint16_t)0x0000)
+#define USART_CLKLB_ENABLE ((uint16_t)0x0100)
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_CLKLB_DISABLE) || ((LASTBIT) == USART_CLKLB_ENABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Interrupt_definition
+ * @{
+ */
+
+#define USART_INT_PEF ((uint16_t)0x0028)
+#define USART_INT_TXDE ((uint16_t)0x0727)
+#define USART_INT_TXC ((uint16_t)0x0626)
+#define USART_INT_RXDNE ((uint16_t)0x0525)
+#define USART_INT_IDLEF ((uint16_t)0x0424)
+#define USART_INT_LINBD ((uint16_t)0x0846)
+#define USART_INT_CTSF ((uint16_t)0x096A)
+#define USART_INT_ERRF ((uint16_t)0x0060)
+#define USART_INT_OREF ((uint16_t)0x0360)
+#define USART_INT_NEF ((uint16_t)0x0260)
+#define USART_INT_FEF ((uint16_t)0x0160)
+#define IS_USART_CFG_INT(IT) \
+ (((IT) == USART_INT_PEF) || ((IT) == USART_INT_TXDE) || ((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE) \
+ || ((IT) == USART_INT_IDLEF) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF) \
+ || ((IT) == USART_INT_ERRF))
+#define IS_USART_GET_INT(IT) \
+ (((IT) == USART_INT_PEF) || ((IT) == USART_INT_TXDE) || ((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE) \
+ || ((IT) == USART_INT_IDLEF) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF) || ((IT) == USART_INT_OREF) \
+ || ((IT) == USART_INT_NEF) || ((IT) == USART_INT_FEF))
+#define IS_USART_CLR_INT(IT) \
+ (((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_DMA_Requests
+ * @{
+ */
+
+#define USART_DMAREQ_TX ((uint16_t)0x0080)
+#define USART_DMAREQ_RX ((uint16_t)0x0040)
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_WakeUp_methods
+ * @{
+ */
+
+#define USART_WUM_IDLELINE ((uint16_t)0x0000)
+#define USART_WUM_ADDRMASK ((uint16_t)0x0800)
+#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WUM_IDLELINE) || ((WAKEUP) == USART_WUM_ADDRMASK))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_LIN_Break_Detection_Length
+ * @{
+ */
+
+#define USART_LINBDL_10B ((uint16_t)0x0000)
+#define USART_LINBDL_11B ((uint16_t)0x0020)
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == USART_LINBDL_10B) || ((LENGTH) == USART_LINBDL_11B))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_IrDA_Low_Power
+ * @{
+ */
+
+#define USART_IRDAMODE_LOWPPWER ((uint16_t)0x0004)
+#define USART_IRDAMODE_NORMAL ((uint16_t)0x0000)
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IRDAMODE_LOWPPWER) || ((MODE) == USART_IRDAMODE_NORMAL))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Flags
+ * @{
+ */
+
+#define USART_FLAG_CTSF ((uint16_t)0x0200)
+#define USART_FLAG_LINBD ((uint16_t)0x0100)
+#define USART_FLAG_TXDE ((uint16_t)0x0080)
+#define USART_FLAG_TXC ((uint16_t)0x0040)
+#define USART_FLAG_RXDNE ((uint16_t)0x0020)
+#define USART_FLAG_IDLEF ((uint16_t)0x0010)
+#define USART_FLAG_OREF ((uint16_t)0x0008)
+#define USART_FLAG_NEF ((uint16_t)0x0004)
+#define USART_FLAG_FEF ((uint16_t)0x0002)
+#define USART_FLAG_PEF ((uint16_t)0x0001)
+#define IS_USART_FLAG(FLAG) \
+ (((FLAG) == USART_FLAG_PEF) || ((FLAG) == USART_FLAG_TXDE) || ((FLAG) == USART_FLAG_TXC) \
+ || ((FLAG) == USART_FLAG_RXDNE) || ((FLAG) == USART_FLAG_IDLEF) || ((FLAG) == USART_FLAG_LINBD) \
+ || ((FLAG) == USART_FLAG_CTSF) || ((FLAG) == USART_FLAG_OREF) || ((FLAG) == USART_FLAG_NEF) \
+ || ((FLAG) == USART_FLAG_FEF))
+
+#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
+#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) \
+ ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) && ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \
+ || ((USART_FLAG) != USART_FLAG_CTSF))
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x00337F99))
+#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
+#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Exported_Functions
+ * @{
+ */
+
+void USART_DeInit(USART_Module* USARTx);
+void USART_Init(USART_Module* USARTx, USART_InitType* USART_InitStruct);
+void USART_StructInit(USART_InitType* USART_InitStruct);
+void USART_ClockInit(USART_Module* USARTx, USART_ClockInitType* USART_ClockInitStruct);
+void USART_ClockStructInit(USART_ClockInitType* USART_ClockInitStruct);
+void USART_Enable(USART_Module* USARTx, FunctionalState Cmd);
+void USART_ConfigInt(USART_Module* USARTx, uint16_t USART_INT, FunctionalState Cmd);
+void USART_EnableDMA(USART_Module* USARTx, uint16_t USART_DMAReq, FunctionalState Cmd);
+void USART_SetAddr(USART_Module* USARTx, uint8_t USART_Addr);
+void USART_ConfigWakeUpMode(USART_Module* USARTx, uint16_t USART_WakeUpMode);
+void USART_EnableRcvWakeUp(USART_Module* USARTx, FunctionalState Cmd);
+void USART_ConfigLINBreakDetectLength(USART_Module* USARTx, uint16_t USART_LINBreakDetectLength);
+void USART_EnableLIN(USART_Module* USARTx, FunctionalState Cmd);
+void USART_SendData(USART_Module* USARTx, uint16_t Data);
+uint16_t USART_ReceiveData(USART_Module* USARTx);
+void USART_SendBreak(USART_Module* USARTx);
+void USART_SetGuardTime(USART_Module* USARTx, uint8_t USART_GuardTime);
+void USART_SetPrescaler(USART_Module* USARTx, uint8_t USART_Prescaler);
+void USART_EnableSmartCard(USART_Module* USARTx, FunctionalState Cmd);
+void USART_SetSmartCardNACK(USART_Module* USARTx, FunctionalState Cmd);
+void USART_EnableHalfDuplex(USART_Module* USARTx, FunctionalState Cmd);
+void USART_ConfigIrDAMode(USART_Module* USARTx, uint16_t USART_IrDAMode);
+void USART_EnableIrDA(USART_Module* USARTx, FunctionalState Cmd);
+FlagStatus USART_GetFlagStatus(USART_Module* USARTx, uint16_t USART_FLAG);
+void USART_ClrFlag(USART_Module* USARTx, uint16_t USART_FLAG);
+INTStatus USART_GetIntStatus(USART_Module* USARTx, uint16_t USART_INT);
+void USART_ClrIntPendingBit(USART_Module* USARTx, uint16_t USART_INT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32G43x_USART_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_wwdg.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_wwdg.h
new file mode 100644
index 0000000000..83a7ac00ed
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_wwdg.h
@@ -0,0 +1,122 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_wwdg.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_WWDG_H__
+#define __N32G43X_WWDG_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup WWDG
+ * @{
+ */
+
+/** @addtogroup WWDG_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup WWDG_Prescaler
+ * @{
+ */
+
+#define WWDG_PRESCALER_DIV1 ((uint32_t)0x00000000)
+#define WWDG_PRESCALER_DIV2 ((uint32_t)0x00000080)
+#define WWDG_PRESCALER_DIV4 ((uint32_t)0x00000100)
+#define WWDG_PRESCALER_DIV8 ((uint32_t)0x00000180)
+#define IS_WWDG_PRESCALER_DIV(PRESCALER) \
+ (((PRESCALER) == WWDG_PRESCALER_DIV1) || ((PRESCALER) == WWDG_PRESCALER_DIV2) \
+ || ((PRESCALER) == WWDG_PRESCALER_DIV4) || ((PRESCALER) == WWDG_PRESCALER_DIV8))
+#define IS_WWDG_WVALUE(VALUE) ((VALUE) <= 0x7F)
+#define IS_WWDG_CNT(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Exported_Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Exported_Functions
+ * @{
+ */
+
+void WWDG_DeInit(void);
+void WWDG_SetPrescalerDiv(uint32_t WWDG_Prescaler);
+void WWDG_SetWValue(uint8_t WindowValue);
+void WWDG_EnableInt(void);
+void WWDG_SetCnt(uint8_t Counter);
+void WWDG_Enable(uint8_t Counter);
+FlagStatus WWDG_GetEWINTF(void);
+void WWDG_ClrEWINTF(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32G43X__WWDG_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/misc.c b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/misc.c
new file mode 100644
index 0000000000..324035303d
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/misc.c
@@ -0,0 +1,229 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file misc.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "misc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup MISC
+ * @brief MISC driver modules
+ * @{
+ */
+
+/** @addtogroup MISC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Private_Defines
+ * @{
+ */
+
+#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Configures the priority grouping: pre-emption priority and subpriority.
+ * @param NVIC_PriorityGroup specifies the priority grouping bits length.
+ * This parameter can be one of the following values:
+ * @arg NVIC_PriorityGroup_0 0 bits for pre-emption priority
+ * 4 bits for subpriority
+ * @arg NVIC_PriorityGroup_1 1 bits for pre-emption priority
+ * 3 bits for subpriority
+ * @arg NVIC_PriorityGroup_2 2 bits for pre-emption priority
+ * 2 bits for subpriority
+ * @arg NVIC_PriorityGroup_3 3 bits for pre-emption priority
+ * 1 bits for subpriority
+ * @arg NVIC_PriorityGroup_4 4 bits for pre-emption priority
+ * 0 bits for subpriority
+ */
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
+
+ /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
+ SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
+}
+
+/**
+ * @brief Initializes the NVIC peripheral according to the specified
+ * parameters in the NVIC_InitStruct.
+ * @param NVIC_InitStruct pointer to a NVIC_InitType structure that contains
+ * the configuration information for the specified NVIC peripheral.
+ */
+void NVIC_Init(NVIC_InitType* NVIC_InitStruct)
+{
+ uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
+
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
+ assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
+
+ if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+ {
+ /* Compute the Corresponding IRQ Priority --------------------------------*/
+ tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700)) >> 0x08;
+ tmppre = (0x4 - tmppriority);
+ tmpsub = tmpsub >> tmppriority;
+
+ tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
+ tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
+ tmppriority = tmppriority << 0x04;
+
+ NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
+
+ /* Enable the Selected IRQ Channels --------------------------------------*/
+ NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = (uint32_t)0x01
+ << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+ }
+ else
+ {
+ /* Disable the Selected IRQ Channels -------------------------------------*/
+ NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = (uint32_t)0x01
+ << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+ }
+}
+
+/**
+ * @brief Sets the vector table location and Offset.
+ * @param NVIC_VectTab specifies if the vector table is in RAM or FLASH memory.
+ * This parameter can be one of the following values:
+ * @arg NVIC_VectTab_RAM
+ * @arg NVIC_VectTab_FLASH
+ * @param Offset Vector Table base offset field. This value must be a multiple
+ * of 0x200.
+ */
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
+ assert_param(IS_NVIC_OFFSET(Offset));
+
+ SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
+}
+
+/**
+ * @brief Selects the condition for the system to enter low power mode.
+ * @param LowPowerMode Specifies the new mode for the system to enter low power mode.
+ * This parameter can be one of the following values:
+ * @arg NVIC_LP_SEVONPEND
+ * @arg NVIC_LP_SLEEPDEEP
+ * @arg NVIC_LP_SLEEPONEXIT
+ * @param Cmd new state of LP condition. This parameter can be: ENABLE or DISABLE.
+ */
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_LP(LowPowerMode));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ SCB->SCR |= LowPowerMode;
+ }
+ else
+ {
+ SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
+ }
+}
+
+/**
+ * @brief Configures the SysTick clock source.
+ * @param SysTick_CLKSource specifies the SysTick clock source.
+ * This parameter can be one of the following values:
+ * @arg SysTick_CLKSource_HCLK_Div8 AHB clock divided by 8 selected as SysTick clock source.
+ * @arg SysTick_CLKSource_HCLK AHB clock selected as SysTick clock source.
+ */
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
+ if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
+ {
+ SysTick->CTRL |= SysTick_CLKSource_HCLK;
+ }
+ else
+ {
+ SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_adc.c b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_adc.c
new file mode 100644
index 0000000000..349e4ab5d2
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_adc.c
@@ -0,0 +1,1411 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_adc.c
+ * @author Nations
+ * @version V1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_adc.h"
+#include "n32g43x_rcc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @brief ADC driver modules
+ * @{
+ */
+
+/** @addtogroup ADC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Private_Defines
+ * @{
+ */
+
+/* ADC DISC_NUM mask */
+#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF)
+
+/* ADC DISC_EN mask */
+#define CTRL1_DISC_EN_SET ((uint32_t)0x00000800)
+#define CTRL1_DISC_EN_RESET ((uint32_t)0xFFFFF7FF)
+
+/* ADC INJ_AUTO mask */
+#define CR1_JAUTO_Set ((uint32_t)0x00000400)
+#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF)
+
+/* ADC INJ_DISC_EN mask */
+#define CTRL1_INJ_DISC_EN_SET ((uint32_t)0x00001000)
+#define CTRL1_INJ_DISC_EN_RESET ((uint32_t)0xFFFFEFFF)
+
+/* ADC AWDG_CH mask */
+#define CTRL1_AWDG_CH_RESET ((uint32_t)0xFFFFFFE0)
+
+/* ADC Analog watchdog enable mode mask */
+#define CTRL1_AWDG_MODE_RESET ((uint32_t)0xFF3FFDFF)
+
+/* CTRL1 register Mask */
+#define CTRL1_CLR_MASK ((uint32_t)0xFFF0FEFF)
+
+/* ADC AD_ON mask */
+#define CTRL2_AD_ON_SET ((uint32_t)0x00000001)
+#define CTRL2_AD_ON_RESET ((uint32_t)0xFFFFFFFE)
+
+/* ADC DMA mask */
+#define CTRL2_DMA_SET ((uint32_t)0x00000100)
+#define CTRL2_DMA_RESET ((uint32_t)0xFFFFFEFF)
+
+/* ADC RST_CALI mask */
+#define CTRL2_RST_CALI_SET ((uint32_t)0x00000008)
+
+/* ADC CAL mask */
+#define CTRL2_CAL_SET ((uint32_t)0x00000004)
+
+/* ADC SOFT_START mask */
+#define CTRL2_SOFT_START_SET ((uint32_t)0x00400000)
+
+/* ADC EXT_TRIG mask */
+#define CTRL2_EXT_TRIG_SET ((uint32_t)0x00100000)
+#define CTRL2_EXT_TRIG_RESET ((uint32_t)0xFFEFFFFF)
+
+/* ADC Software start mask */
+#define CTRL2_EXT_TRIG_SWSTART_SET ((uint32_t)0x00500000)
+#define CTRL2_EXT_TRIG_SWSTART_RESET ((uint32_t)0xFFAFFFFF)
+
+/* ADC INJ_EXT_SEL mask */
+#define CTRL2_INJ_EXT_SEL_RESET ((uint32_t)0xFFFF8FFF)
+
+/* ADC INJ_EXT_TRIG mask */
+#define CTRL2_INJ_EXT_TRIG_SET ((uint32_t)0x00008000)
+#define CTRL2_INJ_EXT_TRIG_RESET ((uint32_t)0xFFFF7FFF)
+
+/* ADC INJ_SWSTART mask */
+#define CTRL2_INJ_SWSTART_SET ((uint32_t)0x00200000)
+
+/* ADC injected software start mask */
+#define CTRL2_INJ_EXT_TRIG_JSWSTART_SET ((uint32_t)0x00208000)
+#define CTRL2_INJ_EXT_TRIG_JSWSTART_RESET ((uint32_t)0xFFDF7FFF)
+
+/* ADC TSPD mask */
+#define CTRL2_TSVREFE_SET ((uint32_t)0x00800000)
+#define CTRL2_TSVREFE_RESET ((uint32_t)0xFF7FFFFF)
+
+/* CTRL2 register Mask */
+#define CTRL2_CLR_MASK ((uint32_t)0xFFF1F7FD)
+
+/* ADC SQx mask */
+#define SQR4_SEQ_SET ((uint32_t)0x0000001F)
+#define SQR3_SEQ_SET ((uint32_t)0x0000001F)
+#define SQR2_SEQ_SET ((uint32_t)0x0000001F)
+#define SQR1_SEQ_SET ((uint32_t)0x0000001F)
+
+/* RSEQ1 register Mask */
+#define RSEQ1_CLR_MASK ((uint32_t)0xFF0FFFFF)
+
+/* ADC JSQx mask */
+#define JSEQ_JSQ_SET ((uint32_t)0x0000001F)
+
+/* ADC INJ_LEN mask */
+#define JSEQ_INJ_LEN_SET ((uint32_t)0x00300000)
+#define JSEQ_INJ_LEN_RESET ((uint32_t)0xFFCFFFFF)
+
+/* ADC SAMPTx mask */
+#define SAMPT1_SMP_SET ((uint32_t)0x00000007)
+#define SAMPT2_SMP_SET ((uint32_t)0x00000007)
+
+/* ADC JDATx registers offset */
+#define JDAT_OFFSET ((uint8_t)0x28)
+
+/* ADC1 DAT register base address */
+#define DAT_ADDR ((uint32_t)0x4001244C)
+
+/* ADC STS register mask */
+#define ADC_STS_RESERVE_MASK ((uint32_t)0x0000007F)
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the ADCx peripheral registers to their default reset values.
+ * @param ADCx where x can be 1, 2 ,3 or 4 to select the ADC peripheral.
+ */
+void ADC_DeInit(ADC_Module* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+
+ if (ADCx == ADC)
+ {
+ /* Enable ADC1 reset state */
+ RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_ADC, ENABLE);
+ /* Release ADC1 from reset state */
+ RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_ADC, DISABLE);
+ }
+}
+
+/**
+ * @brief Initializes the ADCx peripheral according to the specified parameters
+ * in the ADC_InitStruct.
+ * @param ADCx where x can be 1, 2 ,3 or 4 to select the ADC peripheral.
+ * @param ADC_InitStruct pointer to an ADC_InitType structure that contains
+ * the configuration information for the specified ADC peripheral.
+ */
+void ADC_Init(ADC_Module* ADCx, ADC_InitType* ADC_InitStruct)
+{
+ uint32_t tmpreg1 = 0;
+ uint8_t tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->MultiChEn));
+ assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ContinueConvEn));
+ assert_param(IsAdcExtTrig(ADC_InitStruct->ExtTrigSelect));
+ assert_param(IsAdcDatAlign(ADC_InitStruct->DatAlign));
+ assert_param(IsAdcSeqLenValid(ADC_InitStruct->ChsNumber));
+
+ /*---------------------------- ADCx CTRL1 Configuration -----------------*/
+ /* Get the ADCx CTRL1 value */
+ tmpreg1 = ADCx->CTRL1;
+ /* Clear DUALMOD and SCAN bits */
+ tmpreg1 &= CTRL1_CLR_MASK;
+ /* Configure ADCx: Dual mode and scan conversion mode */
+ /* Set DUALMOD bits according to WorkMode value */
+ /* Set SCAN bit according to MultiChEn value */
+ tmpreg1 |= (uint32_t)( ((uint32_t)ADC_InitStruct->MultiChEn << 8));
+ /* Write to ADCx CTRL1 */
+ ADCx->CTRL1 = tmpreg1;
+
+ /*---------------------------- ADCx CTRL2 Configuration -----------------*/
+ /* Get the ADCx CTRL2 value */
+ tmpreg1 = ADCx->CTRL2;
+ /* Clear CONT, ALIGN and EXTSEL bits */
+ tmpreg1 &= CTRL2_CLR_MASK;
+ /* Configure ADCx: external trigger event and continuous conversion mode */
+ /* Set ALIGN bit according to DatAlign value */
+ /* Set EXTSEL bits according to ExtTrigSelect value */
+ /* Set CONT bit according to ContinueConvEn value */
+ tmpreg1 |= (uint32_t)(ADC_InitStruct->DatAlign | ADC_InitStruct->ExtTrigSelect
+ | ((uint32_t)ADC_InitStruct->ContinueConvEn << 1));
+ /* Write to ADCx CTRL2 */
+ ADCx->CTRL2 = tmpreg1;
+
+ /*---------------------------- ADCx RSEQ1 Configuration -----------------*/
+ /* Get the ADCx RSEQ1 value */
+ tmpreg1 = ADCx->RSEQ1;
+ /* Clear L bits */
+ tmpreg1 &= RSEQ1_CLR_MASK;
+ /* Configure ADCx: regular channel sequence length */
+ /* Set L bits according to ChsNumber value */
+ tmpreg2 |= (uint8_t)(ADC_InitStruct->ChsNumber - (uint8_t)1);
+ tmpreg1 |= (uint32_t)tmpreg2 << 20;
+ /* Write to ADCx RSEQ1 */
+ ADCx->RSEQ1 = tmpreg1;
+}
+
+/**
+ * @brief Fills each ADC_InitStruct member with its default value.
+ * @param ADC_InitStruct pointer to an ADC_InitType structure which will be initialized.
+ */
+void ADC_InitStruct(ADC_InitType* ADC_InitStruct)
+{
+ /* Reset ADC init structure parameters values */
+ /* initialize the MultiChEn member */
+ ADC_InitStruct->MultiChEn = DISABLE;
+ /* Initialize the ContinueConvEn member */
+ ADC_InitStruct->ContinueConvEn = DISABLE;
+ /* Initialize the ExtTrigSelect member */
+ ADC_InitStruct->ExtTrigSelect = ADC_EXT_TRIGCONV_T1_CC1;
+ /* Initialize the DatAlign member */
+ ADC_InitStruct->DatAlign = ADC_DAT_ALIGN_R;
+ /* Initialize the ChsNumber member */
+ ADC_InitStruct->ChsNumber = 1;
+}
+
+/**
+ * @brief Enables or disables the specified ADC peripheral.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the ADCx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_Enable(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set the AD_ON bit to wake up the ADC from power down mode */
+ ADCx->CTRL2 |= CTRL2_AD_ON_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC peripheral */
+ ADCx->CTRL2 &= CTRL2_AD_ON_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified ADC DMA request.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC DMA transfer.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableDMA(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcDmaModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC DMA request */
+ ADCx->CTRL2 |= CTRL2_DMA_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC DMA request */
+ ADCx->CTRL2 &= CTRL2_DMA_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified ADC interrupts.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_IT specifies the ADC interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg ADC_INT_ENDC End of conversion interrupt mask
+ * @arg ADC_INT_AWD Analog watchdog interrupt mask
+ * @arg ADC_INT_JENDC End of injected conversion interrupt mask
+ * @param Cmd new state of the specified ADC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_ConfigInt(ADC_Module* ADCx, uint16_t ADC_IT, FunctionalState Cmd)
+{
+ uint8_t itmask = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ assert_param(IsAdcInt(ADC_IT));
+ /* Get the ADC IT index */
+ itmask = (uint8_t)ADC_IT;
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC interrupts */
+ ADCx->CTRL1 |= itmask;
+ }
+ else
+ {
+ /* Disable the selected ADC interrupts */
+ ADCx->CTRL1 &= (~(uint32_t)itmask);
+ }
+}
+
+
+/**
+ * @brief Starts the selected ADC calibration process.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ */
+void ADC_StartCalibration(ADC_Module* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ /* Enable the selected ADC calibration process */
+ if (ADCx->CALFACT==0)
+ ADCx->CTRL2 |= CTRL2_CAL_SET;
+}
+
+/**
+ * @brief Gets the selected ADC calibration status.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @return The new state of ADC calibration (SET or RESET).
+ */
+FlagStatus ADC_GetCalibrationStatus(ADC_Module* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ /* Check the status of CAL bit */
+ if ((ADCx->CTRL2 & CTRL2_CAL_SET) != (uint32_t)RESET)
+ {
+ /* CAL bit is set: calibration on going */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAL bit is reset: end of calibration */
+ bitstatus = RESET;
+ }
+ if (ADCx->CALFACT!=0)
+ bitstatus = RESET;
+ /* Return the CAL bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Enables or disables the selected ADC software start conversion .
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC software start conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableSoftwareStartConv(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC conversion on external event and start the selected
+ ADC conversion */
+ ADCx->CTRL2 |= CTRL2_EXT_TRIG_SWSTART_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC conversion on external event and stop the selected
+ ADC conversion */
+ ADCx->CTRL2 &= CTRL2_EXT_TRIG_SWSTART_RESET;
+ }
+}
+
+/**
+ * @brief Gets the selected ADC Software start conversion Status.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @return The new state of ADC software start conversion (SET or RESET).
+ */
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_Module* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ /* Check the status of SOFT_START bit */
+ if ((ADCx->CTRL2 & CTRL2_SOFT_START_SET) != (uint32_t)RESET)
+ {
+ /* SOFT_START bit is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* SOFT_START bit is reset */
+ bitstatus = RESET;
+ }
+ /* Return the SOFT_START bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Configures the discontinuous mode for the selected ADC regular
+ * group channel.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Number specifies the discontinuous mode regular channel
+ * count value. This number must be between 1 and 8.
+ */
+void ADC_ConfigDiscModeChannelCount(ADC_Module* ADCx, uint8_t Number)
+{
+ uint32_t tmpreg1 = 0;
+ uint32_t tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcSeqDiscNumberValid(Number));
+ /* Get the old register value */
+ tmpreg1 = ADCx->CTRL1;
+ /* Clear the old discontinuous mode channel count */
+ tmpreg1 &= CR1_DISCNUM_Reset;
+ /* Set the discontinuous mode channel count */
+ tmpreg2 = Number - 1;
+ tmpreg1 |= tmpreg2 << 13;
+ /* Store the new register value */
+ ADCx->CTRL1 = tmpreg1;
+}
+
+/**
+ * @brief Enables or disables the discontinuous mode on regular group
+ * channel for the specified ADC
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC discontinuous mode
+ * on regular group channel.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableDiscMode(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC regular discontinuous mode */
+ ADCx->CTRL1 |= CTRL1_DISC_EN_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC regular discontinuous mode */
+ ADCx->CTRL1 &= CTRL1_DISC_EN_RESET;
+ }
+}
+
+/**
+ * @brief Configures for the selected ADC regular channel its corresponding
+ * rank in the sequencer and its sample time.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_Channel the ADC channel to configure.
+ * This parameter can be one of the following values:
+ * @arg ADC_CH_0 ADC Channel0 selected
+ * @arg ADC_CH_1 ADC Channel1 selected
+ * @arg ADC_CH_2 ADC Channel2 selected
+ * @arg ADC_CH_3 ADC Channel3 selected
+ * @arg ADC_CH_4 ADC Channel4 selected
+ * @arg ADC_CH_5 ADC Channel5 selected
+ * @arg ADC_CH_6 ADC Channel6 selected
+ * @arg ADC_CH_7 ADC Channel7 selected
+ * @arg ADC_CH_8 ADC Channel8 selected
+ * @arg ADC_CH_9 ADC Channel9 selected
+ * @arg ADC_CH_10 ADC Channel10 selected
+ * @arg ADC_CH_11 ADC Channel11 selected
+ * @arg ADC_CH_12 ADC Channel12 selected
+ * @arg ADC_CH_13 ADC Channel13 selected
+ * @arg ADC_CH_14 ADC Channel14 selected
+ * @arg ADC_CH_15 ADC Channel15 selected
+ * @arg ADC_CH_16 ADC Channel16 selected
+ * @arg ADC_CH_17 ADC Channel17 selected
+ * @arg ADC_CH_18 ADC Channel18 selected
+ * @param Rank The rank in the regular group sequencer. This parameter must be between 1 to 16.
+ * @param ADC_SampleTime The sample time value to be set for the selected channel.
+ * This parameter can be one of the following values:
+ * @arg ADC_SAMP_TIME_1CYCLES5 Sample time equal to 1.5 cycles
+ * @arg ADC_SAMP_TIME_7CYCLES5 Sample time equal to 7.5 cycles
+ * @arg ADC_SAMP_TIME_13CYCLES5 Sample time equal to 13.5 cycles
+ * @arg ADC_SAMP_TIME_28CYCLES5 Sample time equal to 28.5 cycles
+ * @arg ADC_SAMP_TIME_41CYCLES5 Sample time equal to 41.5 cycles
+ * @arg ADC_SAMP_TIME_55CYCLES5 Sample time equal to 55.5 cycles
+ * @arg ADC_SAMP_TIME_71CYCLES5 Sample time equal to 71.5 cycles
+ * @arg ADC_SAMP_TIME_239CYCLES5 Sample time equal to 239.5 cycles
+ */
+void ADC_ConfigRegularChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcChannel(ADC_Channel));
+ assert_param(IsAdcReqRankValid(Rank));
+ assert_param(IsAdcSampleTime(ADC_SampleTime));
+
+ if (ADC_Channel == ADC_CH_18)
+ {
+ tmpreg1 = ADCx->SAMPT3;
+ tmpreg1 &= (~0x00000007);
+ tmpreg1 |= ADC_SampleTime;
+ ADCx->SAMPT3 = tmpreg1;
+ }
+ if (ADC_Channel > ADC_CH_9) /* if ADC_CH_10 ... ADC_CH_17 is selected */
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SAMPT1;
+ /* Calculate the mask to clear */
+ tmpreg2 = SAMPT1_SMP_SET << (3 * (ADC_Channel - 10));
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SAMPT1 = tmpreg1;
+ }
+ else /* ADC_Channel include in ADC_Channel_[0..9] */
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SAMPT2;
+ /* Calculate the mask to clear */
+ tmpreg2 = SAMPT2_SMP_SET << (3 * ADC_Channel);
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SAMPT2 = tmpreg1;
+ }
+ /* For Rank 1 to 6 */
+ if (Rank < 7)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->RSEQ3;
+ /* Calculate the mask to clear */
+ tmpreg2 = SQR3_SEQ_SET << (5 * (Rank - 1));
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->RSEQ3 = tmpreg1;
+ }
+ /* For Rank 7 to 12 */
+ else if (Rank < 13)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->RSEQ2;
+ /* Calculate the mask to clear */
+ tmpreg2 = SQR2_SEQ_SET << (5 * (Rank - 7));
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->RSEQ2 = tmpreg1;
+ }
+ /* For Rank 13 to 16 */
+ else
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->RSEQ1;
+ /* Calculate the mask to clear */
+ tmpreg2 = SQR1_SEQ_SET << (5 * (Rank - 13));
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->RSEQ1 = tmpreg1;
+ }
+}
+
+/**
+ * @brief Enables or disables the ADCx conversion through external trigger.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC external trigger start of conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableExternalTrigConv(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC conversion on external event */
+ ADCx->CTRL2 |= CTRL2_EXT_TRIG_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC conversion on external event */
+ ADCx->CTRL2 &= CTRL2_EXT_TRIG_RESET;
+ }
+}
+
+/**
+ * @brief Returns the last ADCx conversion result data for regular channel.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @return The Data conversion value.
+ */
+uint16_t ADC_GetDat(ADC_Module* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ /* Return the selected ADC conversion value */
+ return (uint16_t)ADCx->DAT;
+}
+
+/**
+ * @brief Enables or disables the selected ADC automatic injected group
+ * conversion after regular one.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC auto injected conversion
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableAutoInjectedConv(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC automatic injected group conversion */
+ ADCx->CTRL1 |= CR1_JAUTO_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC automatic injected group conversion */
+ ADCx->CTRL1 &= CR1_JAUTO_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the discontinuous mode for injected group
+ * channel for the specified ADC
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC discontinuous mode
+ * on injected group channel.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableInjectedDiscMode(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC injected discontinuous mode */
+ ADCx->CTRL1 |= CTRL1_INJ_DISC_EN_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC injected discontinuous mode */
+ ADCx->CTRL1 &= CTRL1_INJ_DISC_EN_RESET;
+ }
+}
+
+/**
+ * @brief Configures the ADCx external trigger for injected channels conversion.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_ExternalTrigInjecConv specifies the ADC trigger to start injected conversion.
+ * This parameter can be one of the following values:
+ * @arg ADC_EXT_TRIG_INJ_CONV_T1_TRGO Timer1 TRGO event selected (for ADC1, ADC2 and ADC3)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T1_CC4 Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T2_TRGO Timer2 TRGO event selected (for ADC1 and ADC2)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T2_CC1 Timer2 capture compare1 selected (for ADC1 and ADC2)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T3_CC4 Timer3 capture compare4 selected (for ADC1 and ADC2)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T4_TRGO Timer4 TRGO event selected (for ADC1 and ADC2)
+ * @arg ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4 External interrupt line 15 or Timer8
+ * capture compare4 event selected (for ADC1 and ADC2)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T4_CC3 Timer4 capture compare3 selected (for ADC3 only)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T8_CC2 Timer8 capture compare2 selected (for ADC3 only)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T8_CC4 Timer8 capture compare4 selected (for ADC3 only)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T5_TRGO Timer5 TRGO event selected (for ADC3 only)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T5_CC4 Timer5 capture compare4 selected (for ADC3 only)
+ * @arg ADC_EXT_TRIG_INJ_CONV_NONE Injected conversion started by software and not
+ * by external trigger (for ADC1, ADC2 and ADC3)
+ */
+void ADC_ConfigExternalTrigInjectedConv(ADC_Module* ADCx, uint32_t ADC_ExternalTrigInjecConv)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcExtInjTrig(ADC_ExternalTrigInjecConv));
+ /* Get the old register value */
+ tmpregister = ADCx->CTRL2;
+ /* Clear the old external event selection for injected group */
+ tmpregister &= CTRL2_INJ_EXT_SEL_RESET;
+ /* Set the external event selection for injected group */
+ tmpregister |= ADC_ExternalTrigInjecConv;
+ /* Store the new register value */
+ ADCx->CTRL2 = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the ADCx injected channels conversion through
+ * external trigger
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC external trigger start of
+ * injected conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableExternalTrigInjectedConv(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC external event selection for injected group */
+ ADCx->CTRL2 |= CTRL2_INJ_EXT_TRIG_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC external event selection for injected group */
+ ADCx->CTRL2 &= CTRL2_INJ_EXT_TRIG_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the selected ADC start of the injected
+ * channels conversion.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC software start injected conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableSoftwareStartInjectedConv(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC conversion for injected group on external event and start the selected
+ ADC injected conversion */
+ ADCx->CTRL2 |= CTRL2_INJ_EXT_TRIG_JSWSTART_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC conversion on external event for injected group and stop the selected
+ ADC injected conversion */
+ ADCx->CTRL2 &= CTRL2_INJ_EXT_TRIG_JSWSTART_RESET;
+ }
+}
+
+/**
+ * @brief Gets the selected ADC Software start injected conversion Status.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @return The new state of ADC software start injected conversion (SET or RESET).
+ */
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_Module* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ /* Check the status of INJ_SWSTART bit */
+ if ((ADCx->CTRL2 & CTRL2_INJ_SWSTART_SET) != (uint32_t)RESET)
+ {
+ /* INJ_SWSTART bit is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* INJ_SWSTART bit is reset */
+ bitstatus = RESET;
+ }
+ /* Return the INJ_SWSTART bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Configures for the selected ADC injected channel its corresponding
+ * rank in the sequencer and its sample time.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_Channel the ADC channel to configure.
+ * This parameter can be one of the following values:
+ * @arg ADC_CH_0 ADC Channel0 selected
+ * @arg ADC_CH_1 ADC Channel1 selected
+ * @arg ADC_CH_2 ADC Channel2 selected
+ * @arg ADC_CH_3 ADC Channel3 selected
+ * @arg ADC_CH_4 ADC Channel4 selected
+ * @arg ADC_CH_5 ADC Channel5 selected
+ * @arg ADC_CH_6 ADC Channel6 selected
+ * @arg ADC_CH_7 ADC Channel7 selected
+ * @arg ADC_CH_8 ADC Channel8 selected
+ * @arg ADC_CH_9 ADC Channel9 selected
+ * @arg ADC_CH_10 ADC Channel10 selected
+ * @arg ADC_CH_11 ADC Channel11 selected
+ * @arg ADC_CH_12 ADC Channel12 selected
+ * @arg ADC_CH_13 ADC Channel13 selected
+ * @arg ADC_CH_14 ADC Channel14 selected
+ * @arg ADC_CH_15 ADC Channel15 selected
+ * @arg ADC_CH_16 ADC Channel16 selected
+ * @arg ADC_CH_17 ADC Channel17 selected
+ * @arg ADC_CH_18 ADC Channel18 selected
+ * @param Rank The rank in the injected group sequencer. This parameter must be between 1 and 4.
+ * @param ADC_SampleTime The sample time value to be set for the selected channel.
+ * This parameter can be one of the following values:
+ * @arg ADC_SAMP_TIME_1CYCLES5 Sample time equal to 1.5 cycles
+ * @arg ADC_SAMP_TIME_7CYCLES5 Sample time equal to 7.5 cycles
+ * @arg ADC_SAMP_TIME_13CYCLES5 Sample time equal to 13.5 cycles
+ * @arg ADC_SAMP_TIME_28CYCLES5 Sample time equal to 28.5 cycles
+ * @arg ADC_SAMP_TIME_41CYCLES5 Sample time equal to 41.5 cycles
+ * @arg ADC_SAMP_TIME_55CYCLES5 Sample time equal to 55.5 cycles
+ * @arg ADC_SAMP_TIME_71CYCLES5 Sample time equal to 71.5 cycles
+ * @arg ADC_SAMP_TIME_239CYCLES5 Sample time equal to 239.5 cycles
+ */
+void ADC_ConfigInjectedChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcChannel(ADC_Channel));
+ assert_param(IsAdcInjRankValid(Rank));
+ assert_param(IsAdcSampleTime(ADC_SampleTime));
+
+ if (ADC_Channel == ADC_CH_18)
+ {
+ tmpreg1 = ADCx->SAMPT3;
+ tmpreg1 &= (~0x00000007);
+ tmpreg1 |= ADC_SampleTime;
+ ADCx->SAMPT3 = tmpreg1;
+ }
+ else if (ADC_Channel > ADC_CH_9) /* if ADC_CH_10 ... ADC_CH_17 is selected */
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SAMPT1;
+ /* Calculate the mask to clear */
+ tmpreg2 = SAMPT1_SMP_SET << (3 * (ADC_Channel - 10));
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SAMPT1 = tmpreg1;
+ }
+ else /* ADC_Channel include in ADC_Channel_[0..9] */
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SAMPT2;
+ /* Calculate the mask to clear */
+ tmpreg2 = SAMPT2_SMP_SET << (3 * ADC_Channel);
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SAMPT2 = tmpreg1;
+ }
+ /* Rank configuration */
+ /* Get the old register value */
+ tmpreg1 = ADCx->JSEQ;
+ /* Get INJ_LEN value: Number = INJ_LEN+1 */
+ tmpreg3 = (tmpreg1 & JSEQ_INJ_LEN_SET) >> 20;
+ /* Calculate the mask to clear: ((Rank-1)+(4-INJ_LEN-1)) */
+ tmpreg2 = JSEQ_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+ /* Clear the old JSQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set: ((Rank-1)+(4-INJ_LEN-1)) */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+ /* Set the JSQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->JSEQ = tmpreg1;
+}
+
+/**
+ * @brief Configures the sequencer length for injected channels
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Length The sequencer length.
+ * This parameter must be a number between 1 to 4.
+ */
+void ADC_ConfigInjectedSequencerLength(ADC_Module* ADCx, uint8_t Length)
+{
+ uint32_t tmpreg1 = 0;
+ uint32_t tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcInjLenValid(Length));
+
+ /* Get the old register value */
+ tmpreg1 = ADCx->JSEQ;
+ /* Clear the old injected sequnence lenght INJ_LEN bits */
+ tmpreg1 &= JSEQ_INJ_LEN_RESET;
+ /* Set the injected sequnence lenght INJ_LEN bits */
+ tmpreg2 = Length - 1;
+ tmpreg1 |= tmpreg2 << 20;
+ /* Store the new register value */
+ ADCx->JSEQ = tmpreg1;
+}
+
+/**
+ * @brief Set the injected channels conversion value offset
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_InjectedChannel the ADC injected channel to set its offset.
+ * This parameter can be one of the following values:
+ * @arg ADC_INJ_CH_1 Injected Channel1 selected
+ * @arg ADC_INJ_CH_2 Injected Channel2 selected
+ * @arg ADC_INJ_CH_3 Injected Channel3 selected
+ * @arg ADC_INJ_CH_4 Injected Channel4 selected
+ * @param Offset the offset value for the selected ADC injected channel
+ * This parameter must be a 12bit value.
+ */
+void ADC_SetInjectedOffsetDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcInjCh(ADC_InjectedChannel));
+ assert_param(IsAdcOffsetValid(Offset));
+
+ tmp = (uint32_t)ADCx;
+ tmp += ADC_InjectedChannel;
+
+ /* Set the selected injected channel data offset */
+ *(__IO uint32_t*)tmp = (uint32_t)Offset;
+}
+
+/**
+ * @brief Returns the ADC injected channel conversion result
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_InjectedChannel the converted ADC injected channel.
+ * This parameter can be one of the following values:
+ * @arg ADC_INJ_CH_1 Injected Channel1 selected
+ * @arg ADC_INJ_CH_2 Injected Channel2 selected
+ * @arg ADC_INJ_CH_3 Injected Channel3 selected
+ * @arg ADC_INJ_CH_4 Injected Channel4 selected
+ * @return The Data conversion value.
+ */
+uint16_t ADC_GetInjectedConversionDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcInjCh(ADC_InjectedChannel));
+
+ tmp = (uint32_t)ADCx;
+ tmp += ADC_InjectedChannel + JDAT_OFFSET;
+
+ /* Returns the selected injected channel conversion data value */
+ return (uint16_t)(*(__IO uint32_t*)tmp);
+}
+
+/**
+ * @brief Enables or disables the analog watchdog on single/all regular
+ * or injected channels
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_AnalogWatchdog the ADC analog watchdog configuration.
+ * This parameter can be one of the following values:
+ * @arg ADC_ANALOG_WTDG_SINGLEREG_ENABLE Analog watchdog on a single regular channel
+ * @arg ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE Analog watchdog on a single injected channel
+ * @arg ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE Analog watchdog on a single regular or injected channel
+ * @arg ADC_ANALOG_WTDG_ALLREG_ENABLE Analog watchdog on all regular channel
+ * @arg ADC_ANALOG_WTDG_ALLINJEC_ENABLE Analog watchdog on all injected channel
+ * @arg ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE Analog watchdog on all regular and injected channels
+ * @arg ADC_ANALOG_WTDG_NONE No channel guarded by the analog watchdog
+ */
+void ADC_ConfigAnalogWatchdogWorkChannelType(ADC_Module* ADCx, uint32_t ADC_AnalogWatchdog)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcAnalogWatchdog(ADC_AnalogWatchdog));
+ /* Get the old register value */
+ tmpregister = ADCx->CTRL1;
+ /* Clear AWDEN, AWDENJ and AWDSGL bits */
+ tmpregister &= CTRL1_AWDG_MODE_RESET;
+ /* Set the analog watchdog enable mode */
+ tmpregister |= ADC_AnalogWatchdog;
+ /* Store the new register value */
+ ADCx->CTRL1 = tmpregister;
+}
+
+/**
+ * @brief Configures the high and low thresholds of the analog watchdog.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param HighThreshold the ADC analog watchdog High threshold value.
+ * This parameter must be a 12bit value.
+ * @param LowThreshold the ADC analog watchdog Low threshold value.
+ * This parameter must be a 12bit value.
+ */
+void ADC_ConfigAnalogWatchdogThresholds(ADC_Module* ADCx, uint16_t HighThreshold, uint16_t LowThreshold)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcValid(HighThreshold));
+ assert_param(IsAdcValid(LowThreshold));
+ /* Set the ADCx high threshold */
+ ADCx->WDGHIGH = HighThreshold;
+ /* Set the ADCx low threshold */
+ ADCx->WDGLOW = LowThreshold;
+}
+
+/**
+ * @brief Configures the analog watchdog guarded single channel
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_Channel the ADC channel to configure for the analog watchdog.
+ * This parameter can be one of the following values:
+ * @arg ADC_CH_0 ADC Channel0 selected
+ * @arg ADC_CH_1 ADC Channel1 selected
+ * @arg ADC_CH_2 ADC Channel2 selected
+ * @arg ADC_CH_3 ADC Channel3 selected
+ * @arg ADC_CH_4 ADC Channel4 selected
+ * @arg ADC_CH_5 ADC Channel5 selected
+ * @arg ADC_CH_6 ADC Channel6 selected
+ * @arg ADC_CH_7 ADC Channel7 selected
+ * @arg ADC_CH_8 ADC Channel8 selected
+ * @arg ADC_CH_9 ADC Channel9 selected
+ * @arg ADC_CH_10 ADC Channel10 selected
+ * @arg ADC_CH_11 ADC Channel11 selected
+ * @arg ADC_CH_12 ADC Channel12 selected
+ * @arg ADC_CH_13 ADC Channel13 selected
+ * @arg ADC_CH_14 ADC Channel14 selected
+ * @arg ADC_CH_15 ADC Channel15 selected
+ * @arg ADC_CH_16 ADC Channel16 selected
+ * @arg ADC_CH_17 ADC Channel17 selected
+ * @arg ADC_CH_18 ADC Channel18 selected
+ */
+void ADC_ConfigAnalogWatchdogSingleChannel(ADC_Module* ADCx, uint8_t ADC_Channel)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcChannel(ADC_Channel));
+ /* Get the old register value */
+ tmpregister = ADCx->CTRL1;
+ /* Clear the Analog watchdog channel select bits */
+ tmpregister &= CTRL1_AWDG_CH_RESET;
+ /* Set the Analog watchdog channel */
+ tmpregister |= ADC_Channel;
+ /* Store the new register value */
+ ADCx->CTRL1 = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the temperature sensor and Vrefint channel.
+ * @param Cmd new state of the temperature sensor.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableTempSensorVrefint(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the temperature sensor and Vrefint channel*/
+ ADC->CTRL2 |= CTRL2_TSVREFE_SET;
+ _EnVref1p2()
+ _EnVref2p0()
+ }
+ else
+ {
+ /* Disable the temperature sensor and Vrefint channel*/
+ ADC->CTRL2 &= CTRL2_TSVREFE_RESET;
+ _DisVref1p2()
+ _DisVref2p0()
+ }
+}
+
+/**
+ * @brief Checks whether the specified ADC flag is set or not.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_FLAG specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg ADC_FLAG_AWDG Analog watchdog flag
+ * @arg ADC_FLAG_ENDC End of conversion flag
+ * @arg ADC_FLAG_JENDC End of injected group conversion flag
+ * @arg ADC_FLAG_JSTR Start of injected group conversion flag
+ * @arg ADC_FLAG_STR Start of regular group conversion flag
+ * @return The new state of ADC_FLAG (SET or RESET).
+ */
+FlagStatus ADC_GetFlagStatus(ADC_Module* ADCx, uint8_t ADC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcGetFlag(ADC_FLAG));
+ /* Check the status of the specified ADC flag */
+ if ((ADCx->STS & ADC_FLAG) != (uint8_t)RESET)
+ {
+ /* ADC_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* ADC_FLAG is reset */
+ bitstatus = RESET;
+ }
+ /* Return the ADC_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the ADCx's pending flags.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_FLAG specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg ADC_FLAG_AWDG Analog watchdog flag
+ * @arg ADC_FLAG_ENDC End of conversion flag
+ * @arg ADC_FLAG_JENDC End of injected group conversion flag
+ * @arg ADC_FLAG_JSTR Start of injected group conversion flag
+ * @arg ADC_FLAG_STR Start of regular group conversion flag
+ */
+void ADC_ClearFlag(ADC_Module* ADCx, uint8_t ADC_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcClrFlag(ADC_FLAG));
+ /* Clear the selected ADC flags */
+ ADCx->STS = (~(uint32_t)ADC_FLAG & ADC_STS_RESERVE_MASK);
+}
+
+/**
+ * @brief Checks whether the specified ADC interrupt has occurred or not.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_IT specifies the ADC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg ADC_INT_ENDC End of conversion interrupt mask
+ * @arg ADC_INT_AWD Analog watchdog interrupt mask
+ * @arg ADC_INT_JENDC End of injected conversion interrupt mask
+ * @return The new state of ADC_IT (SET or RESET).
+ */
+INTStatus ADC_GetIntStatus(ADC_Module* ADCx, uint16_t ADC_IT)
+{
+ INTStatus bitstatus = RESET;
+ uint32_t itmask = 0, enablestatus = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcGetInt(ADC_IT));
+ /* Get the ADC IT index */
+ itmask = ADC_IT >> 8;
+ /* Get the ADC_IT enable bit status */
+ enablestatus = (ADCx->CTRL1 & (uint8_t)ADC_IT);
+ /* Check the status of the specified ADC interrupt */
+ if (((ADCx->STS & itmask) != (uint32_t)RESET) && enablestatus)
+ {
+ /* ADC_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* ADC_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the ADC_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the ADCx's interrupt pending bits.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_IT specifies the ADC interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg ADC_INT_ENDC End of conversion interrupt mask
+ * @arg ADC_INT_AWD Analog watchdog interrupt mask
+ * @arg ADC_INT_JENDC End of injected conversion interrupt mask
+ */
+void ADC_ClearIntPendingBit(ADC_Module* ADCx, uint16_t ADC_IT)
+{
+ uint8_t itmask = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcInt(ADC_IT));
+ /* Get the ADC IT index */
+ itmask = (uint8_t)(ADC_IT >> 8);
+ /* Clear the selected ADC interrupt pending bits */
+ ADCx->STS = (~(uint32_t)itmask & ADC_STS_RESERVE_MASK);
+}
+
+/**
+ * @brief Initializes the ADCx peripheral according to the specified parameters
+ * in the ADC_InitStructEx.
+ * @param ADCx where x can be 1, 2 ,3 or 4 to select the ADC peripheral.
+ * @param ADC_InitStructEx pointer to an ADC_InitTypeEx structure that contains
+ * the configuration information for the specified ADC peripheral.
+ */
+void ADC_InitEx(ADC_Module* ADCx, ADC_InitTypeEx* ADC_InitStructEx)
+{
+ uint32_t tmpregister = 0;
+ /*ADC_SAMPT3 samp time sele ,as sam 103 or 303 style*/
+ if (ADC_InitStructEx->Samp303Style)
+ ADCx->SAMPT3 |= ADC_SAMPT3_SAMPSEL_MSK;
+ else
+ ADCx->SAMPT3 &= (~ADC_SAMPT3_SAMPSEL_MSK);
+
+ /*intial ADC_CTRL3 once initiall config*/
+ tmpregister = ADCx->CTRL3;
+ if (ADC_InitStructEx->DeepPowerModEn)
+ tmpregister |= ADC_CTRL3_DPWMOD_MSK;
+ else
+ tmpregister &= (~ADC_CTRL3_DPWMOD_MSK);
+
+ if (ADC_InitStructEx->JendcIntEn)
+ tmpregister |= ADC_CTRL3_JENDCAIEN_MSK;
+ else
+ tmpregister &= (~ADC_CTRL3_JENDCAIEN_MSK);
+
+ if (ADC_InitStructEx->EndcIntEn)
+ tmpregister |= ADC_CTRL3_ENDCAIEN_MSK;
+ else
+ tmpregister &= (~ADC_CTRL3_ENDCAIEN_MSK);
+
+ if (ADC_InitStructEx->CalAtuoLoadEn)
+ tmpregister |= ADC_CTRL3_CALALD_MSK;
+ else
+ tmpregister &= (~ADC_CTRL3_CALALD_MSK);
+
+ if (ADC_InitStructEx->DifModCal)
+ tmpregister |= ADC_CTRL3_CALDIF_MSK;
+ else
+ tmpregister &= (~ADC_CTRL3_CALDIF_MSK);
+
+ tmpregister &= (~ADC_CTRL3_RES_MSK);
+ tmpregister |= ADC_InitStructEx->ResBit;
+
+ tmpregister &= (~ADC_CTRL3_CKMOD_MSK);
+ if (ADC_InitStructEx->ClkMode==ADC_CTRL3_CKMOD_PLL)
+ tmpregister |= ADC_CTRL3_CKMOD_MSK;
+
+ ADCx->CTRL3 = tmpregister;
+}
+/**
+ * @brief Checks whether the specified ADC flag is set or not.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_FLAG_NEW specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg ADC_FLAG_RDY ADC ready flag
+ * @arg ADC_FLAG_PD_RDY ADC powerdown ready flag
+ * @return The new state of ADC_FLAG_NEW (SET or RESET).
+ */
+FlagStatus ADC_GetFlagStatusNew(ADC_Module* ADCx, uint8_t ADC_FLAG_NEW)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcGetFlag(ADC_FLAG_NEW));
+ /* Check the status of the specified ADC flag */
+ if ((ADCx->CTRL3 & ADC_FLAG_NEW) != (uint8_t)RESET)
+ {
+ /* ADC_FLAG_NEW is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* ADC_FLAG_NEW is reset */
+ bitstatus = RESET;
+ }
+ /* Return the ADC_FLAG_NEW status */
+ return bitstatus;
+}
+/**
+ * @brief Set Adc calibration bypass or enable.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param en enable bypass calibration.
+ * This parameter can be one of the following values:
+ * @arg true bypass calibration
+ * @arg false not bypass calibration
+ */
+void ADC_SetBypassCalibration(ADC_Module* ADCx, FunctionalState en)
+{
+ uint32_t tmpregister = 0;
+
+ tmpregister = ADCx->CTRL3;
+ if (en)
+ tmpregister |= ADC_CTRL3_BPCAL_MSK;
+ else
+ tmpregister &= (~ADC_CTRL3_BPCAL_MSK);
+ ADCx->CTRL3 = tmpregister;
+}
+/**
+ * @brief Set Adc trans bits width.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ResultBitNum specifies num with adc trans width.
+ * This parameter can be one of the following values:
+ * @arg ADC_RST_BIT_12 12 bit trans
+ * @arg ADC_RST_BIT_10 10 bit trans
+ * @arg ADC_RST_BIT_8 8 bit trans
+ * @arg ADC_RESULT_BIT_6 6 bit trans
+ */
+void ADC_SetConvResultBitNum(ADC_Module* ADCx, uint32_t ResultBitNum)
+{
+ uint32_t tmpregister = 0;
+
+ tmpregister = ADCx->CTRL3;
+ tmpregister &= 0xFFFFFFFC;
+ tmpregister |= ResultBitNum;
+ ADCx->CTRL3 = tmpregister;
+ return;
+}
+
+
+/**
+ * @brief Configures the ADCHCLK prescaler.
+ * @param RCC_ADCHCLKPrescaler specifies the ADCHCLK prescaler.
+ * This parameter can be on of the following values:
+ * @arg RCC_ADCHCLK_DIV1 ADCHCLKPRE[3:0] = 0000, HCLK Clock Divided By 1
+ * @arg RCC_ADCHCLK_DIV2 ADCHCLKPRE[3:0] = 0001, HCLK Clock Divided By 2
+ * @arg RCC_ADCHCLK_DIV4 ADCHCLKPRE[3:0] = 0010, HCLK Clock Divided By 4
+ * @arg RCC_ADCHCLK_DIV6 ADCHCLKPRE[3:0] = 0011, HCLK Clock Divided By 6
+ * @arg RCC_ADCHCLK_DIV8 ADCHCLKPRE[3:0] = 0100, HCLK Clock Divided By 8
+ * @arg RCC_ADCHCLK_DIV10 ADCHCLKPRE[3:0] = 0101, HCLK Clock Divided By 10
+ * @arg RCC_ADCHCLK_DIV12 ADCHCLKPRE[3:0] = 0110, HCLK Clock Divided By 12
+ * @arg RCC_ADCHCLK_DIV16 ADCHCLKPRE[3:0] = 0111, HCLK Clock Divided By 16
+ * @arg RCC_ADCHCLK_DIV32 ADCHCLKPRE[3:0] = 1000, HCLK Clock Divided By 32
+ * @arg RCC_ADCHCLK_DIV32 ADCHCLKPRE[3:0] = others, HCLK Clock Divided By 32
+
+ * @arg RCC_ADCPLLCLK_DISABLE ADCPLLCLKPRES[4:0] = 0xxxx, ADC Pll Clock Disable
+ * @arg RCC_ADCPLLCLK_DIV1 ADCPLLCLKPRES[4:0] = 10000, Pll Clock Divided By 1
+ * @arg RCC_ADCPLLCLK_DIV2 ADCPLLCLKPRES[4:0] = 10001, Pll Clock Divided By 2
+ * @arg RCC_ADCPLLCLK_DIV4 ADCPLLCLKPRES[4:0] = 10010, Pll Clock Divided By 4
+ * @arg RCC_ADCPLLCLK_DIV6 ADCPLLCLKPRES[4:0] = 10011, Pll Clock Divided By 6
+ * @arg RCC_ADCPLLCLK_DIV8 ADCPLLCLKPRES[4:0] = 10100, Pll Clock Divided By 8
+ * @arg RCC_ADCPLLCLK_DIV10 ADCPLLCLKPRES[4:0] = 10101, Pll Clock Divided By 10
+ * @arg RCC_ADCPLLCLK_DIV12 ADCPLLCLKPRES[4:0] = 10110, Pll Clock Divided By 12
+ * @arg RCC_ADCPLLCLK_DIV16 ADCPLLCLKPRES[4:0] = 10111, Pll Clock Divided By 16
+ * @arg RCC_ADCPLLCLK_DIV32 ADCPLLCLKPRES[4:0] = 11000, Pll Clock Divided By 32
+ * @arg RCC_ADCPLLCLK_DIV64 ADCPLLCLKPRES[4:0] = 11001, Pll Clock Divided By 64
+ * @arg RCC_ADCPLLCLK_DIV128 ADCPLLCLKPRES[4:0] = 11010, Pll Clock Divided By 128
+ * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = 11011, Pll Clock Divided By 256
+ * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = others, Pll Clock Divided By 256
+ */
+void ADC_ConfigClk(ADC_CTRL3_CKMOD ADC_ClkMode, uint32_t RCC_ADCHCLKPrescaler)
+{
+ if (ADC_ClkMode==ADC_CTRL3_CKMOD_AHB){
+ RCC_ConfigAdcPllClk(RCC_ADCPLLCLK_DIV1, DISABLE);
+ RCC_ConfigAdcHclk(RCC_ADCHCLKPrescaler);
+ }else{
+ RCC_ConfigAdcPllClk(RCC_ADCHCLKPrescaler, ENABLE);
+ RCC_ConfigAdcHclk(RCC_ADCHCLK_DIV1);
+ }
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_can.c b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_can.c
new file mode 100644
index 0000000000..3048b26523
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_can.c
@@ -0,0 +1,1372 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_can.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_can.h"
+#include "n32g43x_rcc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CAN
+ * @brief CAN driver modules
+ * @{
+ */
+
+/** @addtogroup CAN_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Private_Defines
+ * @{
+ */
+
+/* CAN Master Control Register bits */
+#define MCTRL_DBGF ((uint32_t)0x00010000) /* Debug freeze */
+#define MCTRL_MRST ((uint32_t)0x00010000) /* software master reset */
+
+/* CAN Mailbox Transmit Request */
+#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */
+
+/* CAN Filter Master Register bits */
+#define FMC_FINITM ((uint32_t)0x00000001) /* Filter init mode */
+
+/* Time out for INAK bit */
+#define INIAK_TIMEOUT ((uint32_t)0x0000FFFF)
+/* Time out for SLAK bit */
+#define SLPAK_TIMEOUT ((uint32_t)0x0000FFFF)
+
+/* Flags in TSTS register */
+#define CAN_FLAGS_TSTS ((uint32_t)0x08000000)
+/* Flags in RFF1 register */
+#define CAN_FLAGS_RFF1 ((uint32_t)0x04000000)
+/* Flags in RFF0 register */
+#define CAN_FLAGS_RFF0 ((uint32_t)0x02000000)
+/* Flags in MSTS register */
+#define CAN_FLAGS_MSTS ((uint32_t)0x01000000)
+/* Flags in ESTS register */
+#define CAN_FLAGS_ESTS ((uint32_t)0x00F00000)
+
+/* Mailboxes definition */
+#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
+#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
+#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
+
+#define CAN_MODE_MASK ((uint32_t)0x00000003)
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Private_FunctionPrototypes
+ * @{
+ */
+
+static INTStatus CheckINTStatus(uint32_t CAN_Reg, uint32_t Int_Bit);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the CAN peripheral registers to their default reset values.
+ * @param CANx.
+ */
+void CAN_DeInit(CAN_Module* CANx)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Enable CAN reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_CAN, ENABLE);
+ /* Release CAN from reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_CAN, DISABLE);
+}
+
+/**
+ * @brief Initializes the CAN peripheral according to the specified
+ * parameters in the CAN_InitParam.
+ * @param CAN to select the CAN peripheral.
+ * @param CAN_InitParam pointer to a CAN_InitType structure that
+ * contains the configuration information for the
+ * CAN peripheral.
+ * @return Constant indicates initialization succeed which will be
+ * CAN_InitSTS_Failed or CAN_InitSTS_Success.
+ */
+uint8_t CAN_Init(CAN_Module* CANx, CAN_InitType* CAN_InitParam)
+{
+ uint8_t InitStatus = CAN_InitSTS_Failed;
+ uint32_t wait_ack = 0x00000000;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->TTCM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->ABOM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->AWKUM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->NART));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->RFLM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->TXFP));
+ assert_param(IS_CAN_MODE(CAN_InitParam->OperatingMode));
+ assert_param(IS_CAN_RSJW(CAN_InitParam->RSJW));
+ assert_param(IS_CAN_TBS1(CAN_InitParam->TBS1));
+ assert_param(IS_CAN_TBS2(CAN_InitParam->TBS2));
+ assert_param(IS_CAN_BAUDRATEPRESCALER(CAN_InitParam->BaudRatePrescaler));
+
+ /* Exit from sleep mode */
+ CANx->MCTRL &= (~(uint32_t)CAN_MCTRL_SLPRQ);
+
+ /* Request initialisation */
+ CANx->MCTRL |= CAN_MCTRL_INIRQ;
+
+ /* Wait the acknowledge */
+ while (((CANx->MSTS & CAN_MSTS_INIAK) != CAN_MSTS_INIAK) && (wait_ack != INIAK_TIMEOUT))
+ {
+ wait_ack++;
+ }
+
+ /* Check acknowledge */
+ if ((CANx->MSTS & CAN_MSTS_INIAK) != CAN_MSTS_INIAK)
+ {
+ InitStatus = CAN_InitSTS_Failed;
+ }
+ else
+ {
+ /* Set the time triggered communication mode */
+ if (CAN_InitParam->TTCM == ENABLE)
+ {
+ CANx->MCTRL |= CAN_MCTRL_TTCM;
+ }
+ else
+ {
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_TTCM;
+ }
+
+ /* Set the automatic bus-off management */
+ if (CAN_InitParam->ABOM == ENABLE)
+ {
+ CANx->MCTRL |= CAN_MCTRL_ABOM;
+ }
+ else
+ {
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_ABOM;
+ }
+
+ /* Set the automatic wake-up mode */
+ if (CAN_InitParam->AWKUM == ENABLE)
+ {
+ CANx->MCTRL |= CAN_MCTRL_AWKUM;
+ }
+ else
+ {
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_AWKUM;
+ }
+
+ /* Set the no automatic retransmission */
+ if (CAN_InitParam->NART == ENABLE)
+ {
+ CANx->MCTRL |= CAN_MCTRL_NART;
+ }
+ else
+ {
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_NART;
+ }
+
+ /* Set the receive DATFIFO locked mode */
+ if (CAN_InitParam->RFLM == ENABLE)
+ {
+ CANx->MCTRL |= CAN_MCTRL_RFLM;
+ }
+ else
+ {
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_RFLM;
+ }
+
+ /* Set the transmit DATFIFO priority */
+ if (CAN_InitParam->TXFP == ENABLE)
+ {
+ CANx->MCTRL |= CAN_MCTRL_TXFP;
+ }
+ else
+ {
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_TXFP;
+ }
+
+ /* Set the bit timing register */
+ CANx->BTIM = (uint32_t)((uint32_t)CAN_InitParam->OperatingMode << 30) | ((uint32_t)CAN_InitParam->RSJW << 24)
+ | ((uint32_t)CAN_InitParam->TBS1 << 16) | ((uint32_t)CAN_InitParam->TBS2 << 20)
+ | ((uint32_t)CAN_InitParam->BaudRatePrescaler - 1);
+
+ /* Request leave initialisation */
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_INIRQ;
+
+ /* Wait the acknowledge */
+ wait_ack = 0;
+
+ while (((CANx->MSTS & CAN_MSTS_INIAK) == CAN_MSTS_INIAK) && (wait_ack != INIAK_TIMEOUT))
+ {
+ wait_ack++;
+ }
+
+ /* ...and check acknowledged */
+ if ((CANx->MSTS & CAN_MSTS_INIAK) == CAN_MSTS_INIAK)
+ {
+ InitStatus = CAN_InitSTS_Failed;
+ }
+ else
+ {
+ InitStatus = CAN_InitSTS_Success;
+ }
+ }
+
+ /* At this step, return the status of initialization */
+ return InitStatus;
+}
+
+/**
+ * @brief Initializes the CAN peripheral according to the specified
+ * parameters in the CAN_InitFilterStruct.
+ * @param CAN_InitFilterStruct pointer to a CAN_FilterInitType
+ * structure that contains the configuration
+ * information.
+ */
+void CAN_InitFilter(CAN_FilterInitType* CAN_InitFilterStruct)
+{
+ uint32_t filter_number_bit_pos = 0;
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_NUM(CAN_InitFilterStruct->Filter_Num));
+ assert_param(IS_CAN_FILTER_MODE(CAN_InitFilterStruct->Filter_Mode));
+ assert_param(IS_CAN_FILTER_SCALE(CAN_InitFilterStruct->Filter_Scale));
+ assert_param(IS_CAN_FILTER_FIFO(CAN_InitFilterStruct->Filter_FIFOAssignment));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitFilterStruct->Filter_Act));
+
+ filter_number_bit_pos = ((uint32_t)1) << CAN_InitFilterStruct->Filter_Num;
+
+ /* Initialisation mode for the filter */
+ CAN->FMC |= FMC_FINITM;
+
+ /* Filter Deactivation */
+ CAN->FA1 &= ~(uint32_t)filter_number_bit_pos;
+
+ /* Filter Scale */
+ if (CAN_InitFilterStruct->Filter_Scale == CAN_Filter_16bitScale)
+ {
+ /* 16-bit scale for the filter */
+ CAN->FS1 &= ~(uint32_t)filter_number_bit_pos;
+
+ /* First 16-bit identifier and First 16-bit mask */
+ /* Or First 16-bit identifier and Second 16-bit identifier */
+ CAN->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR1 =
+ ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_LowId) << 16)
+ | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_LowId);
+
+ /* Second 16-bit identifier and Second 16-bit mask */
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+ CAN->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR2 =
+ ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_HighId) << 16)
+ | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_HighId);
+ }
+
+ if (CAN_InitFilterStruct->Filter_Scale == CAN_Filter_32bitScale)
+ {
+ /* 32-bit scale for the filter */
+ CAN->FS1 |= filter_number_bit_pos;
+ /* 32-bit identifier or First 32-bit identifier */
+ CAN->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR1 =
+ ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_HighId) << 16)
+ | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_LowId);
+ /* 32-bit mask or Second 32-bit identifier */
+ CAN->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR2 =
+ ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_HighId) << 16)
+ | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_LowId);
+ }
+
+ /* Filter Mode */
+ if (CAN_InitFilterStruct->Filter_Mode == CAN_Filter_IdMaskMode)
+ {
+ /*Id/Mask mode for the filter*/
+ CAN->FM1 &= ~(uint32_t)filter_number_bit_pos;
+ }
+ else /* CAN_InitFilterStruct->Filter_Mode == CAN_Filter_IdListMode */
+ {
+ /*Identifier list mode for the filter*/
+ CAN->FM1 |= (uint32_t)filter_number_bit_pos;
+ }
+
+ /* Filter DATFIFO assignment */
+ if (CAN_InitFilterStruct->Filter_FIFOAssignment == CAN_Filter_FIFO0)
+ {
+ /* DATFIFO 0 assignation for the filter */
+ CAN->FFA1 &= ~(uint32_t)filter_number_bit_pos;
+ }
+
+ if (CAN_InitFilterStruct->Filter_FIFOAssignment == CAN_Filter_FIFO1)
+ {
+ /* DATFIFO 1 assignation for the filter */
+ CAN->FFA1 |= (uint32_t)filter_number_bit_pos;
+ }
+
+ /* Filter activation */
+ if (CAN_InitFilterStruct->Filter_Act == ENABLE)
+ {
+ CAN->FA1 |= filter_number_bit_pos;
+ }
+
+ /* Leave the initialisation mode for the filter */
+ CAN->FMC &= ~FMC_FINITM;
+}
+/**
+ * @brief Fills each CAN_InitParam member with its default value.
+ * @param CAN_InitParam pointer to a CAN_InitType structure which
+ * will be initialized.
+ */
+void CAN_InitStruct(CAN_InitType* CAN_InitParam)
+{
+ /* Reset CAN init structure parameters values */
+
+ /* Initialize the time triggered communication mode */
+ CAN_InitParam->TTCM = DISABLE;
+
+ /* Initialize the automatic bus-off management */
+ CAN_InitParam->ABOM = DISABLE;
+
+ /* Initialize the automatic wake-up mode */
+ CAN_InitParam->AWKUM = DISABLE;
+
+ /* Initialize the no automatic retransmission */
+ CAN_InitParam->NART = DISABLE;
+
+ /* Initialize the receive DATFIFO locked mode */
+ CAN_InitParam->RFLM = DISABLE;
+
+ /* Initialize the transmit DATFIFO priority */
+ CAN_InitParam->TXFP = DISABLE;
+
+ /* Initialize the OperatingMode member */
+ CAN_InitParam->OperatingMode = CAN_Normal_Mode;
+
+ /* Initialize the RSJW member */
+ CAN_InitParam->RSJW = CAN_RSJW_1tq;
+
+ /* Initialize the TBS1 member */
+ CAN_InitParam->TBS1 = CAN_TBS1_4tq;
+
+ /* Initialize the TBS2 member */
+ CAN_InitParam->TBS2 = CAN_TBS2_3tq;
+
+ /* Initialize the BaudRatePrescaler member */
+ CAN_InitParam->BaudRatePrescaler = 1;
+}
+
+/**
+ * @brief Enables or disables the DBG Freeze for CAN.
+ * @param CAN to select the CAN peripheral.
+ * @param Cmd new state of the CAN peripheral. This parameter can
+ * be: ENABLE or DISABLE.
+ */
+void CAN_DebugFreeze(CAN_Module* CANx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable Debug Freeze */
+ CANx->MCTRL |= MCTRL_DBGF;
+ }
+ else
+ {
+ /* Disable Debug Freeze */
+ CANx->MCTRL &= ~MCTRL_DBGF;
+ }
+}
+
+/**
+ * @brief Enables or disabes the CAN Time TriggerOperation communication mode.
+ * @param CAN to select the CAN peripheral.
+ * @param Cmd Mode new state , can be one of @ref FunctionalState.
+ * @note when enabled, Time stamp (TIME[15:0]) value is sent in the last
+ * two data bytes of the 8-byte message: TIME[7:0] in data byte 6
+ * and TIME[15:8] in data byte 7
+ * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be
+ * sent over the CAN bus.
+ */
+void CAN_EnTTComMode(CAN_Module* CANx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the TTCM mode */
+ CANx->MCTRL |= CAN_MCTRL_TTCM;
+
+ /* Set TGT bits */
+ CANx->sTxMailBox[0].TMDT |= ((uint32_t)CAN_TMDT0_TGT);
+ CANx->sTxMailBox[1].TMDT |= ((uint32_t)CAN_TMDT1_TGT);
+ CANx->sTxMailBox[2].TMDT |= ((uint32_t)CAN_TMDT2_TGT);
+ }
+ else
+ {
+ /* Disable the TTCM mode */
+ CANx->MCTRL &= (uint32_t)(~(uint32_t)CAN_MCTRL_TTCM);
+
+ /* Reset TGT bits */
+ CANx->sTxMailBox[0].TMDT &= ((uint32_t)~CAN_TMDT0_TGT);
+ CANx->sTxMailBox[1].TMDT &= ((uint32_t)~CAN_TMDT1_TGT);
+ CANx->sTxMailBox[2].TMDT &= ((uint32_t)~CAN_TMDT2_TGT);
+ }
+}
+/**
+ * @brief Initiates the transmission of a message.
+ * @param CAN to select the CAN peripheral.
+ * @param TxMessage pointer to a structure which contains CAN Id, CAN
+ * DLC and CAN data.
+ * @return The number of the mailbox that is used for transmission
+ * or CAN_TxSTS_NoMailBox if there is no empty mailbox.
+ */
+uint8_t CAN_TransmitMessage(CAN_Module* CANx, CanTxMessage* TxMessage)
+{
+ uint8_t transmit_mailbox = 0;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_ID(TxMessage->IDE));
+ assert_param(IS_CAN_RTRQ(TxMessage->RTR));
+ assert_param(IS_CAN_DLC(TxMessage->DLC));
+
+ /* Select one empty transmit mailbox */
+ if ((CANx->TSTS & CAN_TSTS_TMEM0) == CAN_TSTS_TMEM0)
+ {
+ transmit_mailbox = 0;
+ }
+ else if ((CANx->TSTS & CAN_TSTS_TMEM1) == CAN_TSTS_TMEM1)
+ {
+ transmit_mailbox = 1;
+ }
+ else if ((CANx->TSTS & CAN_TSTS_TMEM2) == CAN_TSTS_TMEM2)
+ {
+ transmit_mailbox = 2;
+ }
+ else
+ {
+ transmit_mailbox = CAN_TxSTS_NoMailBox;
+ }
+
+ if (transmit_mailbox != CAN_TxSTS_NoMailBox)
+ {
+ /* Set up the Id */
+ CANx->sTxMailBox[transmit_mailbox].TMI &= TMIDxR_TXRQ;
+ if (TxMessage->IDE == CAN_Standard_Id)
+ {
+ assert_param(IS_CAN_STDID(TxMessage->StdId));
+ CANx->sTxMailBox[transmit_mailbox].TMI |= ((TxMessage->StdId << 21) | TxMessage->RTR);
+ }
+ else
+ {
+ assert_param(IS_CAN_EXTID(TxMessage->ExtId));
+ CANx->sTxMailBox[transmit_mailbox].TMI |= ((TxMessage->ExtId << 3) | TxMessage->IDE | TxMessage->RTR);
+ }
+
+ /* Set up the DLC */
+ TxMessage->DLC &= (uint8_t)0x0000000F;
+ CANx->sTxMailBox[transmit_mailbox].TMDT &= (uint32_t)0xFFFFFFF0;
+ CANx->sTxMailBox[transmit_mailbox].TMDT |= TxMessage->DLC;
+
+ /* Set up the data field */
+ CANx->sTxMailBox[transmit_mailbox].TMDL =
+ (((uint32_t)TxMessage->Data[3] << 24) | ((uint32_t)TxMessage->Data[2] << 16)
+ | ((uint32_t)TxMessage->Data[1] << 8) | ((uint32_t)TxMessage->Data[0]));
+ CANx->sTxMailBox[transmit_mailbox].TMDH =
+ (((uint32_t)TxMessage->Data[7] << 24) | ((uint32_t)TxMessage->Data[6] << 16)
+ | ((uint32_t)TxMessage->Data[5] << 8) | ((uint32_t)TxMessage->Data[4]));
+ /* Request transmission */
+ CANx->sTxMailBox[transmit_mailbox].TMI |= TMIDxR_TXRQ;
+ }
+ return transmit_mailbox;
+}
+
+/**
+ * @brief Checks the transmission of a message.
+ * @param CANx to select the CAN peripheral.
+ * @param TransmitMailbox the number of the mailbox that is used for
+ * transmission.
+ * @return CAN_TxSTS_Ok if the CAN driver transmits the message, CAN_TxSTS_Failed
+ * in an other case.
+ */
+uint8_t CAN_TransmitSTS(CAN_Module* CANx, uint8_t TransmitMailbox)
+{
+ uint32_t state = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
+
+ switch (TransmitMailbox)
+ {
+ case (CAN_TXMAILBOX_0):
+ state = CANx->TSTS & (CAN_TSTS_RQCPM0 | CAN_TSTS_TXOKM0 | CAN_TSTS_TMEM0);
+ break;
+ case (CAN_TXMAILBOX_1):
+ state = CANx->TSTS & (CAN_TSTS_RQCPM1 | CAN_TSTS_TXOKM1 | CAN_TSTS_TMEM1);
+ break;
+ case (CAN_TXMAILBOX_2):
+ state = CANx->TSTS & (CAN_TSTS_RQCPM2 | CAN_TSTS_TXOKM2 | CAN_TSTS_TMEM2);
+ break;
+ default:
+ state = CAN_TxSTS_Failed;
+ break;
+ }
+ switch (state)
+ {
+ /* transmit pending */
+ case (0x0):
+ state = CAN_TxSTS_Pending;
+ break;
+ /* transmit failed */
+ case (CAN_TSTS_RQCPM0 | CAN_TSTS_TMEM0):
+ state = CAN_TxSTS_Failed;
+ break;
+ case (CAN_TSTS_RQCPM1 | CAN_TSTS_TMEM1):
+ state = CAN_TxSTS_Failed;
+ break;
+ case (CAN_TSTS_RQCPM2 | CAN_TSTS_TMEM2):
+ state = CAN_TxSTS_Failed;
+ break;
+ /* transmit succeeded */
+ case (CAN_TSTS_RQCPM0 | CAN_TSTS_TXOKM0 | CAN_TSTS_TMEM0):
+ state = CAN_TxSTS_Ok;
+ break;
+ case (CAN_TSTS_RQCPM1 | CAN_TSTS_TXOKM1 | CAN_TSTS_TMEM1):
+ state = CAN_TxSTS_Ok;
+ break;
+ case (CAN_TSTS_RQCPM2 | CAN_TSTS_TXOKM2 | CAN_TSTS_TMEM2):
+ state = CAN_TxSTS_Ok;
+ break;
+ default:
+ state = CAN_TxSTS_Failed;
+ break;
+ }
+ return (uint8_t)state;
+}
+
+/**
+ * @brief Cancels a transmit request.
+ * @param CAN to select the CAN peripheral.
+ * @param Mailbox Mailbox number.
+ */
+void CAN_CancelTransmitMessage(CAN_Module* CANx, uint8_t Mailbox)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));
+ /* abort transmission */
+ switch (Mailbox)
+ {
+ case (CAN_TXMAILBOX_0):
+ CANx->TSTS = CAN_TSTS_ABRQM0;
+ break;
+ case (CAN_TXMAILBOX_1):
+ CANx->TSTS = CAN_TSTS_ABRQM1;
+ break;
+ case (CAN_TXMAILBOX_2):
+ CANx->TSTS = CAN_TSTS_ABRQM2;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Receives a message.
+ * @param CAN to select the CAN peripheral.
+ * @param FIFONum Receive DATFIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @param RxMessage pointer to a structure receive message which contains
+ * CAN Id, CAN DLC, CAN datas and FMI number.
+ */
+void CAN_ReceiveMessage(CAN_Module* CANx, uint8_t FIFONum, CanRxMessage* RxMessage)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FIFO(FIFONum));
+ /* Get the Id */
+ RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONum].RMI;
+ if (RxMessage->IDE == CAN_Standard_Id)
+ {
+ RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONum].RMI >> 21);
+ }
+ else
+ {
+ RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONum].RMI >> 3);
+ }
+
+ RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONum].RMI;
+ /* Get the DLC */
+ RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONum].RMDT;
+ /* Get the FMI */
+ RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDT >> 8);
+ /* Get the data field */
+ RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONum].RMDL;
+ RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDL >> 8);
+ RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDL >> 16);
+ RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDL >> 24);
+ RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONum].RMDH;
+ RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDH >> 8);
+ RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDH >> 16);
+ RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDH >> 24);
+ /* Release the DATFIFO */
+ /* Release FIFO0 */
+ if (FIFONum == CAN_FIFO0)
+ {
+ CANx->RFF0 |= CAN_RFF0_RFFOM0;
+ }
+ /* Release FIFO1 */
+ else /* FIFONum == CAN_FIFO1 */
+ {
+ CANx->RFF1 |= CAN_RFF1_RFFOM1;
+ }
+}
+
+/**
+ * @brief Releases the specified DATFIFO.
+ * @param CAN to select the CAN peripheral.
+ * @param FIFONum DATFIFO to release, CAN_FIFO0 or CAN_FIFO1.
+ */
+void CAN_ReleaseFIFO(CAN_Module* CANx, uint8_t FIFONum)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FIFO(FIFONum));
+ /* Release FIFO0 */
+ if (FIFONum == CAN_FIFO0)
+ {
+ CANx->RFF0 |= CAN_RFF0_RFFOM0;
+ }
+ /* Release FIFO1 */
+ else /* FIFONum == CAN_FIFO1 */
+ {
+ CANx->RFF1 |= CAN_RFF1_RFFOM1;
+ }
+}
+
+/**
+ * @brief Returns the number of pending messages.
+ * @param CAN to select the CAN peripheral.
+ * @param FIFONum Receive DATFIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @return NbMessage : which is the number of pending message.
+ */
+uint8_t CAN_PendingMessage(CAN_Module* CANx, uint8_t FIFONum)
+{
+ uint8_t message_pending = 0;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FIFO(FIFONum));
+ if (FIFONum == CAN_FIFO0)
+ {
+ message_pending = (uint8_t)(CANx->RFF0 & (uint32_t)0x03);
+ }
+ else if (FIFONum == CAN_FIFO1)
+ {
+ message_pending = (uint8_t)(CANx->RFF1 & (uint32_t)0x03);
+ }
+ else
+ {
+ message_pending = 0;
+ }
+ return message_pending;
+}
+
+/**
+ * @brief Select the CAN Operation mode.
+ * @param CAN to select the CAN peripheral.
+ * @param CAN_OperatingMode CAN Operating Mode. This parameter can be one
+ * of @ref CAN_operating_mode enumeration.
+ * @return status of the requested mode which can be
+ * - CAN_ModeSTS_Failed CAN failed entering the specific mode
+ * - CAN_ModeSTS_Success CAN Succeed entering the specific mode
+
+ */
+uint8_t CAN_OperatingModeReq(CAN_Module* CANx, uint8_t CAN_OperatingMode)
+{
+ uint8_t status = CAN_ModeSTS_Failed;
+
+ /* Timeout for INAK or also for SLAK bits*/
+ uint32_t timeout = INIAK_TIMEOUT;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode));
+
+ if (CAN_OperatingMode == CAN_Operating_InitMode)
+ {
+ /* Request initialisation */
+ CANx->MCTRL = (uint32_t)((CANx->MCTRL & (uint32_t)(~(uint32_t)CAN_MCTRL_SLPRQ)) | CAN_MCTRL_INIRQ);
+
+ /* Wait the acknowledge */
+ while (((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_INIAK) && (timeout != 0))
+ {
+ timeout--;
+ }
+ if ((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_INIAK)
+ {
+ status = CAN_ModeSTS_Failed;
+ }
+ else
+ {
+ status = CAN_ModeSTS_Success;
+ }
+ }
+ else if (CAN_OperatingMode == CAN_Operating_NormalMode)
+ {
+ /* Request leave initialisation and sleep mode and enter Normal mode */
+ CANx->MCTRL &= (uint32_t)(~(CAN_MCTRL_SLPRQ | CAN_MCTRL_INIRQ));
+
+ /* Wait the acknowledge */
+ while (((CANx->MSTS & CAN_MODE_MASK) != 0) && (timeout != 0))
+ {
+ timeout--;
+ }
+ if ((CANx->MSTS & CAN_MODE_MASK) != 0)
+ {
+ status = CAN_ModeSTS_Failed;
+ }
+ else
+ {
+ status = CAN_ModeSTS_Success;
+ }
+ }
+ else if (CAN_OperatingMode == CAN_Operating_SleepMode)
+ {
+ /* Request Sleep mode */
+ CANx->MCTRL = (uint32_t)((CANx->MCTRL & (uint32_t)(~(uint32_t)CAN_MCTRL_INIRQ)) | CAN_MCTRL_SLPRQ);
+
+ /* Wait the acknowledge */
+ while (((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_SLPAK) && (timeout != 0))
+ {
+ timeout--;
+ }
+ if ((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_SLPAK)
+ {
+ status = CAN_ModeSTS_Failed;
+ }
+ else
+ {
+ status = CAN_ModeSTS_Success;
+ }
+ }
+ else
+ {
+ status = CAN_ModeSTS_Failed;
+ }
+
+ return (uint8_t)status;
+}
+
+/**
+ * @brief Enters the low power mode.
+ * @param CAN to select the CAN peripheral.
+ * @return status: CAN_SLEEP_Ok if sleep entered, CAN_SLEEP_Failed in an
+ * other case.
+ */
+uint8_t CAN_EnterSleep(CAN_Module* CANx)
+{
+ uint8_t sleepstatus = CAN_SLEEP_Failed;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Request Sleep mode */
+ CANx->MCTRL = (((CANx->MCTRL) & (uint32_t)(~(uint32_t)CAN_MCTRL_INIRQ)) | CAN_MCTRL_SLPRQ);
+
+ /* Sleep mode status */
+ if ((CANx->MSTS & (CAN_MSTS_SLPAK | CAN_MSTS_INIAK)) == CAN_MSTS_SLPAK)
+ {
+ /* Sleep mode not entered */
+ sleepstatus = CAN_SLEEP_Ok;
+ }
+ /* return sleep mode status */
+ return (uint8_t)sleepstatus;
+}
+
+/**
+ * @brief Wakes the CAN up.
+ * @param CAN to select the CAN peripheral.
+ * @return status: CAN_WKU_Ok if sleep mode left, CAN_WKU_Failed in an
+ * other case.
+ */
+uint8_t CAN_WakeUp(CAN_Module* CANx)
+{
+ uint32_t wait_slak = SLPAK_TIMEOUT;
+ uint8_t wakeupstatus = CAN_WKU_Failed;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Wake up request */
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_SLPRQ;
+
+ /* Sleep mode status */
+ while (((CANx->MSTS & CAN_MSTS_SLPAK) == CAN_MSTS_SLPAK) && (wait_slak != 0x00))
+ {
+ wait_slak--;
+ }
+ if ((CANx->MSTS & CAN_MSTS_SLPAK) != CAN_MSTS_SLPAK)
+ {
+ /* wake up done : Sleep mode exited */
+ wakeupstatus = CAN_WKU_Ok;
+ }
+ /* return wakeup status */
+ return (uint8_t)wakeupstatus;
+}
+
+/**
+ * @brief Returns the CANx's last error code (LEC).
+ * @param CAN to select the CAN peripheral.
+ * @return CAN_ErrorCode: specifies the Error code :
+ * - CAN_ERRORCODE_NoErr No Error
+ * - CAN_ERRORCODE_StuffErr Stuff Error
+ * - CAN_ERRORCODE_FormErr Form Error
+ * - CAN_ERRORCODE_ACKErr Acknowledgment Error
+ * - CAN_ERRORCODE_BitRecessiveErr Bit Recessive Error
+ * - CAN_ERRORCODE_BitDominantErr Bit Dominant Error
+ * - CAN_ERRORCODE_CRCErr CRC Error
+ * - CAN_ERRORCODE_SoftwareSetErr Software Set Error
+ */
+
+uint8_t CAN_GetLastErrCode(CAN_Module* CANx)
+{
+ uint8_t errorcode = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Get the error code*/
+ errorcode = (((uint8_t)CANx->ESTS) & (uint8_t)CAN_ESTS_LEC);
+
+ /* Return the error code*/
+ return errorcode;
+}
+/**
+ * @brief Returns the CANx Receive Error Counter (REC).
+ * @note In case of an error during reception, this counter is incremented
+ * by 1 or by 8 depending on the error condition as defined by the CAN
+ * standard. After every successful reception, the counter is
+ * decremented by 1 or reset to 120 if its value was higher than 128.
+ * When the counter value exceeds 127, the CAN controller enters the
+ * error passive state.
+ * @param CANx to to select the CAN peripheral.
+ * @return CAN Receive Error Counter.
+ */
+uint8_t CAN_GetReceiveErrCounter(CAN_Module* CANx)
+{
+ uint8_t counter = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Get the Receive Error Counter*/
+ counter = (uint8_t)((CANx->ESTS & CAN_ESTS_RXEC) >> 24);
+
+ /* Return the Receive Error Counter*/
+ return counter;
+}
+
+/**
+ * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
+ * @param CAN to to select the CAN peripheral.
+ * @return LSB of the 9-bit CAN Transmit Error Counter.
+ */
+uint8_t CAN_GetLSBTransmitErrCounter(CAN_Module* CANx)
+{
+ uint8_t counter = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
+ counter = (uint8_t)((CANx->ESTS & CAN_ESTS_TXEC) >> 16);
+
+ /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
+ return counter;
+}
+
+/**
+ * @brief Enables or disables the specified CANx interrupts.
+ * @param CAN to select the CAN peripheral.
+ * @param CAN_INT specifies the CAN interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * - CAN_INT_TME,
+ * - CAN_INT_FMP0,
+ * - CAN_INT_FF0,
+ * - CAN_INT_FOV0,
+ * - CAN_INT_FMP1,
+ * - CAN_INT_FF1,
+ * - CAN_INT_FOV1,
+ * - CAN_INT_EWG,
+ * - CAN_INT_EPV,
+ * - CAN_INT_LEC,
+ * - CAN_INT_ERR,
+ * - CAN_INT_WKU or
+ * - CAN_INT_SLK.
+ * @param Cmd new state of the CAN interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void CAN_INTConfig(CAN_Module* CANx, uint32_t CAN_INT, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_INT(CAN_INT));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected CANx interrupt */
+ CANx->INTE |= CAN_INT;
+ }
+ else
+ {
+ /* Disable the selected CANx interrupt */
+ CANx->INTE &= ~CAN_INT;
+ }
+}
+/**
+ * @brief Checks whether the specified CAN flag is set or not.
+ * @param CAN to select the CAN peripheral.
+ * @param CAN_FLAG specifies the flag to check.
+ * This parameter can be one of the following flags:
+ * - CAN_FLAG_EWGFL
+ * - CAN_FLAG_EPVFL
+ * - CAN_FLAG_BOFFL
+ * - CAN_FLAG_RQCPM0
+ * - CAN_FLAG_RQCPM1
+ * - CAN_FLAG_RQCPM2
+ * - CAN_FLAG_FFMP1
+ * - CAN_FLAG_FFULL1
+ * - CAN_FLAG_FFOVR1
+ * - CAN_FLAG_FFMP0
+ * - CAN_FLAG_FFULL0
+ * - CAN_FLAG_FFOVR0
+ * - CAN_FLAG_WKU
+ * - CAN_FLAG_SLAK
+ * - CAN_FLAG_LEC
+ * @return The new state of CAN_FLAG (SET or RESET).
+ */
+FlagStatus CAN_GetFlagSTS(CAN_Module* CANx, uint32_t CAN_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_GET_FLAG(CAN_FLAG));
+
+ if ((CAN_FLAG & CAN_FLAGS_ESTS) != (uint32_t)RESET)
+ {
+ /* Check the status of the specified CAN flag */
+ if ((CANx->ESTS & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ else if ((CAN_FLAG & CAN_FLAGS_MSTS) != (uint32_t)RESET)
+ {
+ /* Check the status of the specified CAN flag */
+ if ((CANx->MSTS & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ else if ((CAN_FLAG & CAN_FLAGS_TSTS) != (uint32_t)RESET)
+ {
+ /* Check the status of the specified CAN flag */
+ if ((CANx->TSTS & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ else if ((CAN_FLAG & CAN_FLAGS_RFF0) != (uint32_t)RESET)
+ {
+ /* Check the status of the specified CAN flag */
+ if ((CANx->RFF0 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ else /* if (CAN_FLAG & CAN_FLAGS_RFF1 != (uint32_t)RESET) */
+ {
+ /* Check the status of the specified CAN flag */
+ if ((uint32_t)(CANx->RFF1 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ /* Return the CAN_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the CAN's pending flags.
+ * @param CAN to select the CAN peripheral.
+ * @param CAN_FLAG specifies the flag to clear.
+ * This parameter can be one of the following flags:
+ * - CAN_FLAG_RQCPM0
+ * - CAN_FLAG_RQCPM1
+ * - CAN_FLAG_RQCPM2
+ * - CAN_FLAG_FFULL1
+ * - CAN_FLAG_FFOVR1
+ * - CAN_FLAG_FFULL0
+ * - CAN_FLAG_FFOVR0
+ * - CAN_FLAG_WKU
+ * - CAN_FLAG_SLAK
+ * - CAN_FLAG_LEC
+ */
+void CAN_ClearFlag(CAN_Module* CANx, uint32_t CAN_FLAG)
+{
+ uint32_t flagtmp = 0;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));
+
+ if (CAN_FLAG == CAN_FLAG_LEC) /* ESTS register */
+ {
+ /* Clear the selected CAN flags */
+ CANx->ESTS = (uint32_t)RESET;
+ }
+ else /* MSTS or TSTS or RFF0 or RFF1 */
+ {
+ flagtmp = CAN_FLAG & 0x000FFFFF;
+
+ if ((CAN_FLAG & CAN_FLAGS_RFF0) != (uint32_t)RESET)
+ {
+ /* Receive Flags */
+ CANx->RFF0 = (uint32_t)(flagtmp);
+ }
+ else if ((CAN_FLAG & CAN_FLAGS_RFF1) != (uint32_t)RESET)
+ {
+ /* Receive Flags */
+ CANx->RFF1 = (uint32_t)(flagtmp);
+ }
+ else if ((CAN_FLAG & CAN_FLAGS_TSTS) != (uint32_t)RESET)
+ {
+ /* Transmit Flags */
+ CANx->TSTS = (uint32_t)(flagtmp);
+ }
+ else /* if ((CAN_FLAG & CAN_FLAGS_MSTS)!=(uint32_t)RESET) */
+ {
+ /* Operating mode Flags */
+ CANx->MSTS = (uint32_t)(flagtmp);
+ }
+ }
+}
+
+/**
+ * @brief Checks whether the specified CANx interrupt has occurred or not.
+ * @param CAN to select the CAN peripheral.
+ * @param CAN_INT specifies the CAN interrupt source to check.
+ * This parameter can be one of the following flags:
+ * - CAN_INT_TME
+ * - CAN_INT_FMP0
+ * - CAN_INT_FF0
+ * - CAN_INT_FOV0
+ * - CAN_INT_FMP1
+ * - CAN_INT_FF1
+ * - CAN_INT_FOV1
+ * - CAN_INT_WKU
+ * - CAN_INT_SLK
+ * - CAN_INT_EWG
+ * - CAN_INT_EPV
+ * - CAN_INT_BOF
+ * - CAN_INT_LEC
+ * - CAN_INT_ERR
+ * @return The current state of CAN_INT (SET or RESET).
+ */
+INTStatus CAN_GetIntStatus(CAN_Module* CANx, uint32_t CAN_INT)
+{
+ INTStatus itstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_INT(CAN_INT));
+
+ /* check the enable interrupt bit */
+ if ((CANx->INTE & CAN_INT) != RESET)
+ {
+ /* in case the Interrupt is enabled, .... */
+ switch (CAN_INT)
+ {
+ case CAN_INT_TME:
+ /* Check CAN_TSTS_RQCPx bits */
+ itstatus = CheckINTStatus(CANx->TSTS, CAN_TSTS_RQCPM0 | CAN_TSTS_RQCPM1 | CAN_TSTS_RQCPM2);
+ break;
+ case CAN_INT_FMP0:
+ /* Check CAN_RFF0_FFMP0 bit */
+ itstatus = CheckINTStatus(CANx->RFF0, CAN_RFF0_FFMP0);
+ break;
+ case CAN_INT_FF0:
+ /* Check CAN_RFF0_FFULL0 bit */
+ itstatus = CheckINTStatus(CANx->RFF0, CAN_RFF0_FFULL0);
+ break;
+ case CAN_INT_FOV0:
+ /* Check CAN_RFF0_FFOVR0 bit */
+ itstatus = CheckINTStatus(CANx->RFF0, CAN_RFF0_FFOVR0);
+ break;
+ case CAN_INT_FMP1:
+ /* Check CAN_RFF1_FFMP1 bit */
+ itstatus = CheckINTStatus(CANx->RFF1, CAN_RFF1_FFMP1);
+ break;
+ case CAN_INT_FF1:
+ /* Check CAN_RFF1_FFULL1 bit */
+ itstatus = CheckINTStatus(CANx->RFF1, CAN_RFF1_FFULL1);
+ break;
+ case CAN_INT_FOV1:
+ /* Check CAN_RFF1_FFOVR1 bit */
+ itstatus = CheckINTStatus(CANx->RFF1, CAN_RFF1_FFOVR1);
+ break;
+ case CAN_INT_WKU:
+ /* Check CAN_MSTS_WKUINT bit */
+ itstatus = CheckINTStatus(CANx->MSTS, CAN_MSTS_WKUINT);
+ break;
+ case CAN_INT_SLK:
+ /* Check CAN_MSTS_SLAKINT bit */
+ itstatus = CheckINTStatus(CANx->MSTS, CAN_MSTS_SLAKINT);
+ break;
+ case CAN_INT_EWG:
+ /* Check CAN_ESTS_EWGFL bit */
+ itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_EWGFL);
+ break;
+ case CAN_INT_EPV:
+ /* Check CAN_ESTS_EPVFL bit */
+ itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_EPVFL);
+ break;
+ case CAN_INT_BOF:
+ /* Check CAN_ESTS_BOFFL bit */
+ itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_BOFFL);
+ break;
+ case CAN_INT_LEC:
+ /* Check CAN_ESTS_LEC bit */
+ itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_LEC);
+ break;
+ case CAN_INT_ERR:
+ /* Check CAN_MSTS_ERRINT bit */
+ itstatus = CheckINTStatus(CANx->MSTS, CAN_MSTS_ERRINT);
+ break;
+ default:
+ /* in case of error, return RESET */
+ itstatus = RESET;
+ break;
+ }
+ }
+ else
+ {
+ /* in case the Interrupt is not enabled, return RESET */
+ itstatus = RESET;
+ }
+
+ /* Return the CAN_INT status */
+ return itstatus;
+}
+
+/**
+ * @brief Clears the CANx's interrupt pending bits.
+ * @param CAN to select the CAN peripheral.
+ * @param CAN_INT specifies the interrupt pending bit to clear.
+ * - CAN_INT_TME
+ * - CAN_INT_FF0
+ * - CAN_INT_FOV0
+ * - CAN_INT_FF1
+ * - CAN_INT_FOV1
+ * - CAN_INT_WKU
+ * - CAN_INT_SLK
+ * - CAN_INT_EWG
+ * - CAN_INT_EPV
+ * - CAN_INT_BOF
+ * - CAN_INT_LEC
+ * - CAN_INT_ERR
+ */
+void CAN_ClearINTPendingBit(CAN_Module* CANx, uint32_t CAN_INT)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_CLEAR_INT(CAN_INT));
+
+ switch (CAN_INT)
+ {
+ case CAN_INT_TME:
+ /* Clear CAN_TSTS_RQCPx (rc_w1)*/
+ CANx->TSTS = CAN_TSTS_RQCPM0 | CAN_TSTS_RQCPM1 | CAN_TSTS_RQCPM2;
+ break;
+ case CAN_INT_FF0:
+ /* Clear CAN_RFF0_FFULL0 (rc_w1)*/
+ CANx->RFF0 = CAN_RFF0_FFULL0;
+ break;
+ case CAN_INT_FOV0:
+ /* Clear CAN_RFF0_FFOVR0 (rc_w1)*/
+ CANx->RFF0 = CAN_RFF0_FFOVR0;
+ break;
+ case CAN_INT_FF1:
+ /* Clear CAN_RFF1_FFULL1 (rc_w1)*/
+ CANx->RFF1 = CAN_RFF1_FFULL1;
+ break;
+ case CAN_INT_FOV1:
+ /* Clear CAN_RFF1_FFOVR1 (rc_w1)*/
+ CANx->RFF1 = CAN_RFF1_FFOVR1;
+ break;
+ case CAN_INT_WKU:
+ /* Clear CAN_MSTS_WKUINT (rc_w1)*/
+ CANx->MSTS = CAN_MSTS_WKUINT;
+ break;
+ case CAN_INT_SLK:
+ /* Clear CAN_MSTS_SLAKINT (rc_w1)*/
+ CANx->MSTS = CAN_MSTS_SLAKINT;
+ break;
+ case CAN_INT_EWG:
+ /* Clear CAN_MSTS_ERRINT (rc_w1) */
+ CANx->MSTS = CAN_MSTS_ERRINT;
+ /* Note : the corresponding Flag is cleared by hardware depending
+ of the CAN Bus status*/
+ break;
+ case CAN_INT_EPV:
+ /* Clear CAN_MSTS_ERRINT (rc_w1) */
+ CANx->MSTS = CAN_MSTS_ERRINT;
+ /* Note : the corresponding Flag is cleared by hardware depending
+ of the CAN Bus status*/
+ break;
+ case CAN_INT_BOF:
+ /* Clear CAN_MSTS_ERRINT (rc_w1) */
+ CANx->MSTS = CAN_MSTS_ERRINT;
+ /* Note : the corresponding Flag is cleared by hardware depending
+ of the CAN Bus status*/
+ break;
+ case CAN_INT_LEC:
+ /* Clear LEC bits */
+ CANx->ESTS = RESET;
+ /* Clear CAN_MSTS_ERRINT (rc_w1) */
+ CANx->MSTS = CAN_MSTS_ERRINT;
+ break;
+ case CAN_INT_ERR:
+ /*Clear LEC bits */
+ CANx->ESTS = RESET;
+ /* Clear CAN_MSTS_ERRINT (rc_w1) */
+ CANx->MSTS = CAN_MSTS_ERRINT;
+ /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending
+ of the CAN Bus status*/
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Checks whether the CAN interrupt has occurred or not.
+ * @param CAN_Reg specifies the CAN interrupt register to check.
+ * @param Int_Bit specifies the interrupt source bit to check.
+ * @return The new state of the CAN Interrupt (SET or RESET).
+ */
+static INTStatus CheckINTStatus(uint32_t CAN_Reg, uint32_t Int_Bit)
+{
+ INTStatus pendingbitstatus = RESET;
+
+ if ((CAN_Reg & Int_Bit) != (uint32_t)RESET)
+ {
+ /* CAN_INT is set */
+ pendingbitstatus = SET;
+ }
+ else
+ {
+ /* CAN_INT is reset */
+ pendingbitstatus = RESET;
+ }
+ return pendingbitstatus;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_comp.c b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_comp.c
new file mode 100644
index 0000000000..80a236a562
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_comp.c
@@ -0,0 +1,385 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_comp.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_comp.h"
+#include "n32g43x_rcc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup COMP
+ * @brief COMP driver modules
+ * @{
+ */
+
+/** @addtogroup COMP_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup COMP_Private_Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup COMP_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup COMP_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup COMP_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup COMP_Private_Functions
+ * @{
+ */
+#define SetBitMsk(reg, bit, msk) ((reg) = (((reg) & ~(msk)) | (bit)))
+#define ClrBit(reg, bit) ((reg) &= ~(bit))
+#define SetBit(reg, bit) ((reg) |= (bit))
+#define GetBit(reg, bit) ((reg) & (bit))
+/**
+ * @brief Deinitializes the COMP peripheral registers to their default reset values.
+ */
+void COMP_DeInit(void)
+{
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP, DISABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP_FILT, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP_FILT, DISABLE);
+}
+void COMP_StructInit(COMP_InitType* COMP_InitStruct)
+{
+ COMP_InitStruct->LowPoweMode =false; // only COMP1 have this bit
+ COMP_InitStruct->InpDacConnect = false; // only COMP1 have this bit
+
+ COMP_InitStruct->Blking = COMP_CTRL_BLKING_NO; /*see @ref COMP_CTRL_BLKING */
+
+ COMP_InitStruct->Hyst = COMP_CTRL_HYST_NO; // see @COMPx_CTRL_HYST_MASK
+
+ COMP_InitStruct->PolRev = false; // out polarity reverse
+
+ COMP_InitStruct->OutTrig = COMP1_CTRL_OUTSEL_NC;
+ COMP_InitStruct->InpSel = COMP1_CTRL_INPSEL_FLOAT; //Float as same with comp1 and comp2
+ COMP_InitStruct->InmSel = COMP2_CTRL_INMSEL_NC; //NC as same with comp1 and comp2s
+ COMP_InitStruct->FilterEn=false;
+ COMP_InitStruct->ClkPsc=0;
+ COMP_InitStruct->SampWindow=0;
+ COMP_InitStruct->Thresh=0;
+ COMP_InitStruct->En = false;
+}
+void COMP_Init(COMPX COMPx, COMP_InitType* COMP_InitStruct)
+{
+ COMP_SingleType* pCS;
+ __IO uint32_t tmp;
+ if (COMPx == COMP1)
+ pCS = &COMP->Cmp1;
+ else
+ pCS = &COMP->Cmp2;
+
+ // filter
+ tmp = pCS->FILC;
+ SetBitMsk(tmp, COMP_InitStruct->SampWindow << 6, COMP_FILC_SAMPW_MASK);
+ SetBitMsk(tmp, COMP_InitStruct->Thresh << 1, COMP_FILC_THRESH_MASK);
+ SetBitMsk(tmp, COMP_InitStruct->FilterEn << 0, COMP_FILC_FILEN_MASK);
+ pCS->FILC = tmp;
+ // filter psc
+ pCS->FILP = COMP_InitStruct->ClkPsc;
+
+ // ctrl
+ tmp = pCS->CTRL;
+ if (COMPx == COMP1)
+ {
+ if (COMP_InitStruct->InpDacConnect)
+ SetBit(tmp, COMP1_CTRL_INPDAC_MASK);
+ else
+ ClrBit(tmp, COMP1_CTRL_INPDAC_MASK);
+ if (COMP_InitStruct->LowPoweMode)
+ SetBit(tmp, COMP1_CTRL_PWRMODE_MASK);
+ else
+ ClrBit(tmp, COMP1_CTRL_PWRMODE_MASK);
+ }
+ SetBitMsk(tmp, COMP_InitStruct->Blking, COMP_CTRL_BLKING_MASK);
+ SetBitMsk(tmp, COMP_InitStruct->Hyst, COMPx_CTRL_HYST_MASK);
+ if (COMP_InitStruct->PolRev)
+ SetBit(tmp, COMP_POL_MASK);
+ else
+ ClrBit(tmp, COMP_POL_MASK);
+ SetBitMsk(tmp, COMP_InitStruct->OutTrig, COMP_CTRL_OUTSEL_MASK);
+ SetBitMsk(tmp, COMP_InitStruct->InpSel, COMP_CTRL_INPSEL_MASK);
+ SetBitMsk(tmp, COMP_InitStruct->InmSel, COMP_CTRL_INMSEL_MASK);
+ if (COMP_InitStruct->En)
+ SetBit(tmp, COMP_CTRL_EN_MASK);
+ else
+ ClrBit(tmp, COMP_CTRL_EN_MASK);
+ pCS->CTRL = tmp;
+}
+void COMP_Enable(COMPX COMPx, FunctionalState en)
+{
+ if (COMPx == COMP1)
+ {
+ if (en)
+ SetBit(COMP->Cmp1.CTRL, COMP_CTRL_EN_MASK);
+ else
+ ClrBit(COMP->Cmp1.CTRL, COMP_CTRL_EN_MASK);
+ }
+ else
+ {
+ if (en)
+ SetBit(COMP->Cmp2.CTRL, COMP_CTRL_EN_MASK);
+ else
+ ClrBit(COMP->Cmp2.CTRL, COMP_CTRL_EN_MASK);
+ }
+}
+
+void COMP_SetInpSel(COMPX COMPx, COMP_CTRL_INPSEL VpSel)
+{
+ __IO uint32_t tmp;
+ if (COMPx == COMP1)
+ tmp = COMP->Cmp1.CTRL;
+ else
+ tmp = COMP->Cmp2.CTRL;
+
+ SetBitMsk(tmp, VpSel, COMP_CTRL_INPSEL_MASK);
+
+ if (COMPx == COMP1)
+ COMP->Cmp1.CTRL = tmp;
+ else
+ COMP->Cmp2.CTRL = tmp;
+}
+void COMP_SetInmSel(COMPX COMPx, COMP_CTRL_INMSEL VmSel)
+{
+ __IO uint32_t tmp;
+ if (COMPx == COMP1)
+ tmp = COMP->Cmp1.CTRL;
+ else
+ tmp = COMP->Cmp2.CTRL;
+
+ SetBitMsk(tmp, VmSel, COMP_CTRL_INMSEL_MASK);
+
+ if (COMPx == COMP1)
+ COMP->Cmp1.CTRL = tmp;
+ else
+ COMP->Cmp2.CTRL = tmp;
+
+}
+void COMP_SetOutTrig(COMPX COMPx, COMP_CTRL_OUTTRIG OutTrig)
+{
+ __IO uint32_t tmp;
+ if (COMPx == COMP1)
+ tmp = COMP->Cmp1.CTRL;
+ else
+ tmp = COMP->Cmp2.CTRL;
+
+ SetBitMsk(tmp, OutTrig, COMP_CTRL_OUTSEL_MASK);
+
+ if (COMPx == COMP1)
+ COMP->Cmp1.CTRL = tmp;
+ else
+ COMP->Cmp2.CTRL = tmp;
+}
+
+// return see @COMP_INTSTS_CMPIS
+uint32_t COMP_GetIntSts(void)
+{
+ return COMP->INTSTS;
+}
+// parma range see @COMP_VREFSCL
+// Vv2Trim,Vv1Trim max 63
+void COMP_SetRefScl(uint8_t Vv2Trim, bool Vv2En, uint8_t Vv1Trim, bool Vv1En)
+{
+ __IO uint32_t tmp = 0;
+
+ SetBitMsk(tmp, Vv2Trim << 8, COMP_VREFSCL_VV2TRM_MSK);
+ SetBitMsk(tmp, Vv2En << 7, COMP_VREFSCL_VV2EN_MSK);
+ SetBitMsk(tmp, Vv1Trim << 1, COMP_VREFSCL_VV1TRM_MSK);
+ SetBitMsk(tmp, Vv1En << 0, COMP_VREFSCL_VV1EN_MSK);
+
+ COMP->VREFSCL = tmp;
+}
+// SET when comp out 1
+// RESET when comp out 0
+FlagStatus COMP_GetOutStatus(COMPX COMPx)
+{
+ if (COMPx == COMP1)
+ return (COMP->Cmp1.CTRL & COMP_CTRL_OUT_MASK) ? SET : RESET;
+ else
+ return (COMP->Cmp2.CTRL & COMP_CTRL_OUT_MASK) ? SET : RESET;
+}
+// get one comp interrupt flags
+FlagStatus COMP_GetIntStsOneComp(COMPX COMPx)
+{
+ return (COMP_GetIntSts() & (0x01 << COMPx)) ? SET : RESET;
+}
+
+// Lock see @COMP_LOCK
+void COMP_SetLock(uint32_t Lock)
+{
+ COMP->LOCK = Lock;
+}
+// IntEn see @COMP_INTEN_CMPIEN
+void COMP_SetIntEn(uint32_t IntEn)
+{
+ COMP->INTEN = IntEn;
+}
+// set comp2 xor output with comp1
+void COMP_CMP2XorOut(bool En)
+{
+ COMP->CMP2OSEL = (En==true)?0x1L:0x0L;
+}
+// set stop or lowpower mode that sel 32k clk
+void COMP_StopOrLowpower32KClkSel(bool En)
+{
+ COMP->LPCKSEL = (En==true)?0x1L:0x0L;
+}
+// set comp1 and comp2 component window compare mode
+void COMP_WindowModeEn(bool En)
+{
+ COMP->WINMODE = (En==true)?0x1L:0x0L;
+}
+
+
+/**
+ * @brief Set the COMP filter clock Prescaler value.
+ * @param COMPx where x can be 1 to 2 to select the COMP peripheral.
+ * @param FilPreVal Prescaler Value,Div clock = FilPreVal+1.
+ * @return void
+ */
+void COMP_SetFilterPrescaler(COMPX COMPx , uint16_t FilPreVal)
+{
+ if (COMPx == COMP1)
+ COMP->Cmp1.FILP=FilPreVal;
+ else
+ COMP->Cmp2.FILP=FilPreVal;
+}
+
+/**
+ * @brief Set the COMP filter control value.
+ * @param COMPx where x can be 1 to 2 to select the COMP peripheral.
+ * @param FilEn 1 for enable ,0 or disable
+ * @param TheresNum num under this value is noise
+ * @param SampPW total sample number in a window
+ * @return void
+ */
+void COMP_SetFilterControl(COMPX COMPx , uint8_t FilEn, uint8_t TheresNum , uint8_t SampPW)
+{
+ if (COMPx == COMP1)
+ COMP->Cmp1.FILC=(FilEn&COMP_FILC_FILEN_MASK)+((TheresNum<<1)&COMP_FILC_THRESH_MASK)+((SampPW<<6)&COMP_FILC_SAMPW_MASK);
+ else
+ COMP->Cmp2.FILC=(FilEn&COMP_FILC_FILEN_MASK)+((TheresNum<<1)&COMP_FILC_THRESH_MASK)+((SampPW<<6)&COMP_FILC_SAMPW_MASK);
+}
+
+/**
+ * @brief Set the COMP Hyst value.
+ * @param COMPx where x can be 1 to 2 to select the COMP peripheral.
+ * @param HYST specifies the HYST level.
+ * This parameter can be one of the following values:
+* @arg COMP_CTRL_HYST_NO Hyst disable
+* @arg COMP_CTRL_HYST_LOW Hyst level 5.1mV
+* @arg COMP_CTRL_HYST_MID Hyst level 15mV
+* @arg COMP_CTRL_HYST_HIGH Hyst level 25mV
+ * @return void
+ */
+void COMP_SetHyst(COMPX COMPx , COMP_CTRL_HYST HYST)
+{
+ uint32_t tmp;
+ if (COMPx == COMP1)
+ tmp=COMP->Cmp1.CTRL;
+ else
+ tmp=COMP->Cmp2.CTRL;
+
+ tmp&=~COMP_CTRL_HYST_HIGH;
+ tmp|=HYST;
+ if (COMPx == COMP1)
+ COMP->Cmp1.CTRL=tmp;
+ else
+ COMP->Cmp2.CTRL=tmp;
+}
+
+/**
+ * @brief Set the COMP Blanking source .
+ * @param COMPx where x can be 1 to 2 to select the COMP peripheral.
+ * @param BLK specifies the blanking source .
+ * This parameter can be one of the following values:
+* @arg COMP_CTRL_BLKING_NO Blanking disable
+* @arg COMP_CTRL_BLKING_TIM1_OC5 Blanking source TIM1_OC5
+* @arg COMP_CTRL_BLKING_TIM8_OC5 Blanking source TIM8_OC5
+ * @return void
+ */
+void COMP_SetBlanking(COMPX COMPx , COMP_CTRL_BLKING BLK)
+{
+ uint32_t tmp;
+ if (COMPx == COMP1)
+ tmp=COMP->Cmp1.CTRL;
+ else
+ tmp=COMP->Cmp2.CTRL;
+ tmp&=~(7<<16);
+ tmp|=BLK;
+ if (COMPx == COMP1)
+ COMP->Cmp1.CTRL=tmp;
+ else
+ COMP->Cmp2.CTRL=tmp;
+}
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_crc.c b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_crc.c
new file mode 100644
index 0000000000..734f16e1ed
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_crc.c
@@ -0,0 +1,227 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_crc.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_crc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CRC
+ * @brief CRC driver modules
+ * @{
+ */
+
+/** @addtogroup CRC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Private_Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Resets the CRC Data register (DAT).
+ */
+void CRC32_ResetCrc(void)
+{
+ /* Reset CRC generator */
+ CRC->CRC32CTRL = CRC32_CTRL_RESET;
+}
+
+/**
+ * @brief Computes the 32-bit CRC of a given data word(32-bit).
+ * @param Data data word(32-bit) to compute its CRC
+ * @return 32-bit CRC
+ */
+uint32_t CRC32_CalcCrc(uint32_t Data)
+{
+ CRC->CRC32DAT = Data;
+
+ return (CRC->CRC32DAT);
+}
+
+/**
+ * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
+ * @param pBuffer pointer to the buffer containing the data to be computed
+ * @param BufferLength length of the buffer to be computed
+ * @return 32-bit CRC
+ */
+uint32_t CRC32_CalcBufCrc(uint32_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t index = 0;
+
+ for (index = 0; index < BufferLength; index++)
+ {
+ CRC->CRC32DAT = pBuffer[index];
+ }
+ return (CRC->CRC32DAT);
+}
+
+/**
+ * @brief Returns the current CRC value.
+ * @return 32-bit CRC
+ */
+uint32_t CRC32_GetCrc(void)
+{
+ return (CRC->CRC32DAT);
+}
+
+/**
+ * @brief Stores a 8-bit data in the Independent Data(ID) register.
+ * @param IDValue 8-bit value to be stored in the ID register
+ */
+void CRC32_SetIDat(uint8_t IDValue)
+{
+ CRC->CRC32IDAT = IDValue;
+}
+
+/**
+ * @brief Returns the 8-bit data stored in the Independent Data(ID) register
+ * @return 8-bit value of the ID register
+ */
+uint8_t CRC32_GetIDat(void)
+{
+ return (CRC->CRC32IDAT);
+}
+
+// CRC16 add
+void __CRC16_SetLittleEndianFmt(void)
+{
+ CRC->CRC16CTRL = CRC16_CTRL_LITTLE | CRC->CRC16CTRL;
+}
+void __CRC16_SetBigEndianFmt(void)
+{
+ CRC->CRC16CTRL = CRC16_CTRL_BIG & CRC->CRC16CTRL;
+}
+void __CRC16_SetCleanEnable(void)
+{
+ CRC->CRC16CTRL = CRC16_CTRL_RESET | CRC->CRC16CTRL;
+}
+void __CRC16_SetCleanDisable(void)
+{
+ CRC->CRC16CTRL = CRC16_CTRL_NO_RESET & CRC->CRC16CTRL;
+}
+
+uint16_t __CRC16_CalcCrc(uint8_t Data)
+{
+ CRC->CRC16DAT = Data;
+ return (CRC->CRC16D);
+}
+
+void __CRC16_SetCrc(uint8_t Data)
+{
+ CRC->CRC16DAT = Data;
+}
+
+uint16_t __CRC16_GetCrc(void)
+{
+ return (CRC->CRC16D);
+}
+
+void __CRC16_SetLRC(uint8_t Data)
+{
+ CRC->LRC = Data;
+}
+
+uint8_t __CRC16_GetLRC(void)
+{
+ return (CRC->LRC);
+}
+
+uint16_t CRC16_CalcBufCrc(uint8_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t index = 0;
+
+ CRC->CRC16D = 0x00;
+ for (index = 0; index < BufferLength; index++)
+ {
+ CRC->CRC16DAT = pBuffer[index];
+ }
+ return (CRC->CRC16D);
+}
+
+uint16_t CRC16_CalcCRC(uint8_t Data)
+{
+ CRC->CRC16DAT = Data;
+
+ return (CRC->CRC16D);
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_dac.c b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_dac.c
new file mode 100644
index 0000000000..d4b9614adb
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_dac.c
@@ -0,0 +1,357 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_dac.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_dac.h"
+#include "n32g43x_rcc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DAC
+ * @brief DAC driver modules
+ * @{
+ */
+
+/** @addtogroup DAC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Private_Defines
+ * @{
+ */
+
+/* CTRL register Mask */
+#define CTRL_CLEAR_MASK ((uint32_t)0x00000FFE)
+
+/* DAC Dual Channels SWTRIG masks */
+#define DUAL_SWTRIG_SET ((uint32_t)0x00000001)
+#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFE)
+
+/* DCH registers offsets */
+#define DR12CH_OFFSET ((uint32_t)0x00000008)
+
+/* DATO register offset */
+#define DATO_OFFSET ((uint32_t)0x0000002C)
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the DAC peripheral registers to their default reset values.
+ */
+void DAC_DeInit(void)
+{
+ /* Enable DAC reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_DAC, ENABLE);
+ /* Release DAC from reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_DAC, DISABLE);
+}
+
+/**
+ * @brief Initializes the DAC peripheral according to the specified
+ * parameters in the DAC_InitStruct.
+ * @param DAC_Channel the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1 DAC Channel1 selected
+ * @arg DAC_CHANNEL_2 DAC Channel2 selected
+ * @param DAC_InitStruct pointer to a DAC_InitType structure that
+ * contains the configuration information for the specified DAC channel.
+ */
+void DAC_Init(DAC_InitType* DAC_InitStruct)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;
+ /* Check the DAC parameters */
+ assert_param(IS_DAC_TRIGGER(DAC_InitStruct->Trigger));
+ assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->WaveGen));
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->LfsrUnMaskTriAmp));
+ assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->BufferOutput));
+ /*---------------------------- DAC CTRL Configuration --------------------------*/
+ /* Get the DAC CTRL value */
+ tmpreg1 = DAC->CTRL;
+ /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
+ tmpreg1 &= ~(CTRL_CLEAR_MASK );
+ /* Configure for the selected DAC channel: buffer output, trigger, wave generation,
+ mask/amplitude for wave generation */
+ /* Set TSELx and TENx bits according to Trigger value */
+ /* Set WAVEx bits according to WaveGen value */
+ /* Set MAMPx bits according to LfsrUnMaskTriAmp value */
+ /* Set BOFFx bit according to BufferOutput value */
+ tmpreg2 = (DAC_InitStruct->Trigger | DAC_InitStruct->WaveGen | DAC_InitStruct->LfsrUnMaskTriAmp
+ | DAC_InitStruct->BufferOutput);
+ /* Calculate CTRL register value depending on DAC_Channel */
+ tmpreg1 |= tmpreg2 ;
+ /* Write to DAC CTRL */
+ DAC->CTRL = tmpreg1;
+}
+
+/**
+ * @brief Fills each DAC_InitStruct member with its default value.
+ * @param DAC_InitStruct pointer to a DAC_InitType structure which will
+ * be initialized.
+ */
+void DAC_ClearStruct(DAC_InitType* DAC_InitStruct)
+{
+ /*--------------- Reset DAC init structure parameters values -----------------*/
+ /* Initialize the Trigger member */
+ DAC_InitStruct->Trigger = DAC_TRG_NONE;
+ /* Initialize the WaveGen member */
+ DAC_InitStruct->WaveGen = DAC_WAVEGEN_NONE;
+ /* Initialize the LfsrUnMaskTriAmp member */
+ DAC_InitStruct->LfsrUnMaskTriAmp = DAC_UNMASK_LFSRBIT0;
+ /* Initialize the BufferOutput member */
+ DAC_InitStruct->BufferOutput = DAC_BUFFOUTPUT_ENABLE;
+}
+
+/**
+ * @brief Enables or disables the specified DAC channel.
+ * @param DAC_Channel the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1 DAC Channel1 selected
+ * @arg DAC_CHANNEL_2 DAC Channel2 selected
+ * @param Cmd new state of the DAC channel.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DAC_Enable(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected DAC channel */
+ DAC->CTRL |= DAC_CTRL_CHEN ;
+ }
+ else
+ {
+ /* Disable the selected DAC channel */
+ DAC->CTRL &= ~DAC_CTRL_CHEN ;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified DAC channel DMA request.
+ * @param DAC_Channel the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1 DAC Channel1 selected
+ * @arg DAC_CHANNEL_2 DAC Channel2 selected
+ * @param Cmd new state of the selected DAC channel DMA request.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DAC_DmaEnable(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected DAC channel DMA request */
+ DAC->CTRL |= DAC_CTRL_DMAEN;
+ }
+ else
+ {
+ /* Disable the selected DAC channel DMA request */
+ DAC->CTRL &= ~DAC_CTRL_DMAEN;
+ }
+}
+
+/**
+ * @brief Enables or disables the selected DAC channel software trigger.
+ * @param DAC_Channel the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1 DAC Channel1 selected
+ * @arg DAC_CHANNEL_2 DAC Channel2 selected
+ * @param Cmd new state of the selected DAC channel software trigger.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DAC_SoftTrgEnable(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable software trigger for the selected DAC channel */
+ DAC->SOTTR |= DAC_SOTTR_TREN ;
+ }
+ else
+ {
+ /* Disable software trigger for the selected DAC channel */
+ DAC->SOTTR &= ~(DAC_SOTTR_TREN);
+ }
+}
+
+/**
+ * @brief Enables or disables simultaneously the two DAC channels software
+ * triggers.
+ * @param Cmd new state of the DAC channels software triggers.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DAC_SoftwareTrgEnable(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable software trigger for both DAC channels */
+ DAC->SOTTR |= DUAL_SWTRIG_SET;
+ }
+ else
+ {
+ /* Disable software trigger for both DAC channels */
+ DAC->SOTTR &= DUAL_SWTRIG_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the selected DAC channel wave generation.
+ * @param DAC_Channel the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1 DAC Channel1 selected
+ * @arg DAC_CHANNEL_2 DAC Channel2 selected
+ * @param DAC_Wave Specifies the wave type to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg DAC_WAVE_NOISE noise wave generation
+ * @arg DAC_WAVE_TRIANGLE triangle wave generation
+ * @param Cmd new state of the selected DAC channel wave generation.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DAC_WaveGenerationEnable(uint32_t DAC_Wave, FunctionalState Cmd)
+{
+ __IO uint32_t tmp = 0;
+ /* Check the parameters */
+ assert_param(IS_DAC_WAVE(DAC_Wave));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ tmp=DAC->CTRL;
+ tmp&=~(3<<6);
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected wave generation for the selected DAC channel */
+ tmp |= DAC_Wave;
+ }
+ else
+ {
+ /* Disable the selected wave generation for the selected DAC channel */
+ tmp&=~(3<<6);
+ }
+ DAC->CTRL =tmp;
+}
+
+/**
+ * @brief Set the specified data holding register value for DAC channel1.
+ * @param DAC_Align Specifies the data alignment for DAC channel1.
+ * This parameter can be one of the following values:
+ * @arg DAC_ALIGN_R_8BIT 8bit right data alignment selected
+ * @arg DAC_ALIGN_L_12BIT 12bit left data alignment selected
+ * @arg DAC_ALIGN_R_12BIT 12bit right data alignment selected
+ * @param Data Data to be loaded in the selected data holding register.
+ */
+void DAC_SetChData(uint32_t DAC_Align, uint16_t Data)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALIGN(DAC_Align));
+ assert_param(IS_DAC_DATA(Data));
+
+ tmp = (uint32_t)DAC_BASE;
+ tmp += DR12CH_OFFSET + DAC_Align;
+
+ /* Set the DAC channel1 selected data holding register */
+ *(__IO uint32_t*)tmp = Data;
+}
+
+
+
+
+
+/**
+ * @brief Returns the last data output value of the selected DAC channel.
+ * @param DAC_Channel the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1 DAC Channel1 selected
+ * @arg DAC_CHANNEL_2 DAC Channel2 selected
+ * @return The selected DAC channel data output value.
+ */
+uint16_t DAC_GetOutputDataVal(void)
+{
+ __IO uint32_t tmp = 0;
+
+ tmp = (uint32_t)DAC_BASE;
+ tmp += DATO_OFFSET;
+
+ /* Returns the DAC channel data output register value */
+ return (uint16_t)(*(__IO uint32_t*)tmp);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_dbg.c b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_dbg.c
new file mode 100644
index 0000000000..7588a929a6
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_dbg.c
@@ -0,0 +1,246 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_dbg.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_dbg.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DBG
+ * @brief DBG driver modules
+ * @{
+ */
+
+/** @addtogroup DBGMCU_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Private_Defines
+ * @{
+ */
+
+#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Private_Functions
+ * @{
+ */
+
+
+void GetUCID(uint8_t *UCIDbuf)
+{
+ uint8_t num = 0;
+ uint32_t* ucid_addr = (void*)0;
+ uint32_t temp = 0;
+
+ ucid_addr = (uint32_t*)UCID_BASE;
+
+ for (num = 0; num < UCID_LENGTH;)
+ {
+ temp = *(__IO uint32_t*)(ucid_addr++);
+ UCIDbuf[num++] = (temp & 0xFF);
+ UCIDbuf[num++] = (temp & 0xFF00) >> 8;
+ UCIDbuf[num++] = (temp & 0xFF0000) >> 16;
+ UCIDbuf[num++] = (temp & 0xFF000000) >> 24;
+ }
+}
+
+/**
+ * @brief Returns the UID.
+ * @return UID
+ */
+
+void GetUID(uint8_t *UIDbuf)
+{
+ uint8_t num = 0;
+ uint32_t* uid_addr = (void*)0;
+ uint32_t temp = 0;
+
+ uid_addr = (uint32_t*)UID_BASE;
+
+ for (num = 0; num < UID_LENGTH;)
+ {
+ temp = *(__IO uint32_t*)(uid_addr++);
+ UIDbuf[num++] = (temp & 0xFF);
+ UIDbuf[num++] = (temp & 0xFF00) >> 8;
+ UIDbuf[num++] = (temp & 0xFF0000) >> 16;
+ UIDbuf[num++] = (temp & 0xFF000000) >> 24;
+ }
+}
+
+/**
+ * @brief Returns the DBGMCU_ID.
+ * @return DBGMCU_ID
+ */
+
+void GetDBGMCU_ID(uint8_t *DBGMCU_IDbuf)
+{
+ uint8_t num = 0;
+ uint32_t* dbgid_addr = (void*)0;
+ uint32_t temp = 0;
+
+ dbgid_addr = (uint32_t*)DBGMCU_ID_BASE;
+ for (num = 0; num < DBGMCU_ID_LENGTH;)
+ {
+ temp = *(__IO uint32_t*)(dbgid_addr++);
+ DBGMCU_IDbuf[num++] = (temp & 0xFF);
+ DBGMCU_IDbuf[num++] = (temp & 0xFF00) >> 8;
+ DBGMCU_IDbuf[num++] = (temp & 0xFF0000) >> 16;
+ DBGMCU_IDbuf[num++] = (temp & 0xFF000000) >> 24;
+ }
+}
+
+/**
+ * @brief Returns the device revision number.
+ * @return Device revision identifier
+ */
+uint32_t DBG_GetRevNum(void)
+{
+ return (DBG->ID & 0x00FF);
+}
+
+/**
+ * @brief Returns the device identifier.
+ * @return Device identifier
+ */
+uint32_t DBG_GetDevNum(void)
+{
+ uint32_t id = DBG->ID;
+ return ((id & 0x00F00000) >> 20) | ((id & 0xFF00) >> 4);
+}
+
+/**
+ * @brief Configures the specified peripheral and low power mode behavior
+ * when the MCU under Debug mode.
+ * @param DBG_Periph specifies the peripheral and low power mode.
+ * This parameter can be any combination of the following values:
+ * @arg DBG_SLEEP Keep debugger connection during SLEEP mode
+ * @arg DBG_STOP Keep debugger connection during STOP mode
+ * @arg DBG_STDBY Keep debugger connection during STANDBY mode
+ * @arg DBG_IWDG_STOP Debug IWDG stopped when Core is halted
+ * @arg DBG_WWDG_STOP Debug WWDG stopped when Core is halted
+ * @arg DBG_TIM1_STOP TIM1 counter stopped when Core is halted
+ * @arg DBG_TIM2_STOP TIM2 counter stopped when Core is halted
+ * @arg DBG_TIM3_STOP TIM3 counter stopped when Core is halted
+ * @arg DBG_TIM4_STOP TIM4 counter stopped when Core is halted
+ * @arg DBG_CAN_STOP Debug CAN stopped when Core is halted
+ * @arg DBG_I2C1SMBUS_TIMEOUT I2C1 SMBUS timeout mode stopped when Core is halted
+ * @arg DBG_I2C2SMBUS_TIMEOUT I2C2 SMBUS timeout mode stopped when Core is halted
+ * @arg DBG_TIM8_STOP TIM8 counter stopped when Core is halted
+ * @arg DBG_TIM5_STOP TIM5 counter stopped when Core is halted
+ * @arg DBG_TIM6_STOP TIM6 counter stopped when Core is halted
+ * @arg DBG_TIM7_STOP TIM7 counter stopped when Core is halted
+ * @arg DBG_TIM9_STOP TIM9 counter stopped when Core is halted
+
+ * @param Cmd new state of the specified peripheral in Debug mode.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DBG_ConfigPeriph(uint32_t DBG_Periph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_DBGMCU_PERIPH(DBG_Periph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ DBG->CTRL |= DBG_Periph;
+ }
+ else
+ {
+ DBG->CTRL &= ~DBG_Periph;
+ }
+}
+
+/**
+ * @brief Get FLASH size of this chip.
+ *
+ * @return FLASH size in bytes.
+ */
+uint32_t DBG_GetFlashSize(void)
+{
+ return (DBG->ID & 0x000F0000);
+}
+
+/**
+ * @brief Get SRAM size of this chip.
+ *
+ * @return SRAM size in bytes.
+ */
+uint32_t DBG_GetSramSize(void)
+{
+ return (((DBG->ID & 0xF0000000) >> 28) + 1) << 14;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_dma.c b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_dma.c
new file mode 100644
index 0000000000..0b7c627294
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_dma.c
@@ -0,0 +1,686 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_dma.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_dma.h"
+#include "n32g43x_rcc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @brief DMA driver modules
+ * @{
+ */
+
+/** @addtogroup DMA_Private_TypesDefinitions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Defines
+ * @{
+ */
+
+/* DMA Channelx interrupt pending bit masks */
+#define DMA_CH1_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF1 | DMA_INTSTS_TXCF1 | DMA_INTSTS_HTXF1 | DMA_INTSTS_ERRF1))
+#define DMA_CH2_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF2 | DMA_INTSTS_TXCF2 | DMA_INTSTS_HTXF2 | DMA_INTSTS_ERRF2))
+#define DMA_CH3_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF3 | DMA_INTSTS_TXCF3 | DMA_INTSTS_HTXF3 | DMA_INTSTS_ERRF3))
+#define DMA_CH4_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF4 | DMA_INTSTS_TXCF4 | DMA_INTSTS_HTXF4 | DMA_INTSTS_ERRF4))
+#define DMA_CH5_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF5 | DMA_INTSTS_TXCF5 | DMA_INTSTS_HTXF5 | DMA_INTSTS_ERRF5))
+#define DMA_CH6_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF6 | DMA_INTSTS_TXCF6 | DMA_INTSTS_HTXF6 | DMA_INTSTS_ERRF6))
+#define DMA_CH7_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF7 | DMA_INTSTS_TXCF7 | DMA_INTSTS_HTXF7 | DMA_INTSTS_ERRF7))
+#define DMA_CH8_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF8 | DMA_INTSTS_TXCF8 | DMA_INTSTS_HTXF8 | DMA_INTSTS_ERRF8))
+
+
+/* DMA CHCFGx registers Masks, MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
+#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the DMAy Channelx registers to their default reset
+ * values.
+ * @param DMAyChx where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 8 for DMA1 and 1 to 8 for DMA2 to select the DMA Channel.
+ */
+void DMA_DeInit(DMA_ChannelType* DMAChx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAChx));
+
+ /* Disable the selected DMAy Channelx */
+ DMAChx->CHCFG &= (uint16_t)(~DMA_CHCFG1_CHEN);
+
+ /* Reset DMAy Channelx control register */
+ DMAChx->CHCFG = 0;
+
+ /* Reset DMAy Channelx remaining bytes register */
+ DMAChx->TXNUM = 0;
+
+ /* Reset DMAy Channelx peripheral address register */
+ DMAChx->PADDR = 0;
+
+ /* Reset DMAy Channelx memory address register */
+ DMAChx->MADDR = 0;
+
+ if (DMAChx == DMA_CH1)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel1 */
+ DMA->INTCLR |= DMA_CH1_INT_MASK;
+ }
+ else if (DMAChx == DMA_CH2)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel2 */
+ DMA->INTCLR |= DMA_CH2_INT_MASK;
+ }
+ else if (DMAChx == DMA_CH3)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel3 */
+ DMA->INTCLR |= DMA_CH3_INT_MASK;
+ }
+ else if (DMAChx == DMA_CH4)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel4 */
+ DMA->INTCLR |= DMA_CH4_INT_MASK;
+ }
+ else if (DMAChx == DMA_CH5)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel5 */
+ DMA->INTCLR |= DMA_CH5_INT_MASK;
+ }
+ else if (DMAChx == DMA_CH6)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel6 */
+ DMA->INTCLR |= DMA_CH6_INT_MASK;
+ }
+ else if (DMAChx == DMA_CH7)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel7 */
+ DMA->INTCLR |= DMA_CH7_INT_MASK;
+ }
+ else if (DMAChx == DMA_CH8)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel8 */
+ DMA->INTCLR |= DMA_CH8_INT_MASK;
+ }
+}
+
+/**
+ * @brief Initializes the DMAy Channelx according to the specified
+ * parameters in the DMA_InitParam.
+ * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel.
+ * @param DMA_InitParam pointer to a DMA_InitType structure that
+ * contains the configuration information for the specified DMA Channel.
+ */
+void DMA_Init(DMA_ChannelType* DMAChx, DMA_InitType* DMA_InitParam)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAChx));
+ assert_param(IS_DMA_DIR(DMA_InitParam->Direction));
+ assert_param(IS_DMA_BUF_SIZE(DMA_InitParam->BufSize));
+ assert_param(IS_DMA_PERIPH_INC_STATE(DMA_InitParam->PeriphInc));
+ assert_param(IS_DMA_MEM_INC_STATE(DMA_InitParam->DMA_MemoryInc));
+ assert_param(IS_DMA_PERIPH_DATA_SIZE(DMA_InitParam->PeriphDataSize));
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitParam->MemDataSize));
+ assert_param(IS_DMA_MODE(DMA_InitParam->CircularMode));
+ assert_param(IS_DMA_PRIORITY(DMA_InitParam->Priority));
+ assert_param(IS_DMA_M2M_STATE(DMA_InitParam->Mem2Mem));
+
+ /*--------------------------- DMAy Channelx CHCFG Configuration -----------------*/
+ /* Get the DMAyChx CHCFG value */
+ tmpregister = DMAChx->CHCFG;
+ /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
+ tmpregister &= CCR_CLEAR_Mask;
+ /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
+ /* Set DIR bit according to Direction value */
+ /* Set CIRC bit according to CircularMode value */
+ /* Set PINC bit according to PeriphInc value */
+ /* Set MINC bit according to DMA_MemoryInc value */
+ /* Set PSIZE bits according to PeriphDataSize value */
+ /* Set MSIZE bits according to MemDataSize value */
+ /* Set PL bits according to Priority value */
+ /* Set the MEM2MEM bit according to Mem2Mem value */
+ tmpregister |= DMA_InitParam->Direction | DMA_InitParam->CircularMode | DMA_InitParam->PeriphInc
+ | DMA_InitParam->DMA_MemoryInc | DMA_InitParam->PeriphDataSize | DMA_InitParam->MemDataSize
+ | DMA_InitParam->Priority | DMA_InitParam->Mem2Mem;
+
+ /* Write to DMAy Channelx CHCFG */
+ DMAChx->CHCFG = tmpregister;
+
+ /*--------------------------- DMAy Channelx TXNUM Configuration ---------------*/
+ /* Write to DMAy Channelx TXNUM */
+ DMAChx->TXNUM = DMA_InitParam->BufSize;
+
+ /*--------------------------- DMAy Channelx PADDR Configuration ----------------*/
+ /* Write to DMAy Channelx PADDR */
+ DMAChx->PADDR = DMA_InitParam->PeriphAddr;
+
+ /*--------------------------- DMAy Channelx MADDR Configuration ----------------*/
+ /* Write to DMAy Channelx MADDR */
+ DMAChx->MADDR = DMA_InitParam->MemAddr;
+}
+
+/**
+ * @brief Fills each DMA_InitParam member with its default value.
+ * @param DMA_InitParam pointer to a DMA_InitType structure which will
+ * be initialized.
+ */
+void DMA_StructInit(DMA_InitType* DMA_InitParam)
+{
+ /*-------------- Reset DMA init structure parameters values ------------------*/
+ /* Initialize the PeriphAddr member */
+ DMA_InitParam->PeriphAddr = 0;
+ /* Initialize the MemAddr member */
+ DMA_InitParam->MemAddr = 0;
+ /* Initialize the Direction member */
+ DMA_InitParam->Direction = DMA_DIR_PERIPH_SRC;
+ /* Initialize the BufSize member */
+ DMA_InitParam->BufSize = 0;
+ /* Initialize the PeriphInc member */
+ DMA_InitParam->PeriphInc = DMA_PERIPH_INC_DISABLE;
+ /* Initialize the DMA_MemoryInc member */
+ DMA_InitParam->DMA_MemoryInc = DMA_MEM_INC_DISABLE;
+ /* Initialize the PeriphDataSize member */
+ DMA_InitParam->PeriphDataSize = DMA_PERIPH_DATA_SIZE_BYTE;
+ /* Initialize the MemDataSize member */
+ DMA_InitParam->MemDataSize = DMA_MemoryDataSize_Byte;
+ /* Initialize the CircularMode member */
+ DMA_InitParam->CircularMode = DMA_MODE_NORMAL;
+ /* Initialize the Priority member */
+ DMA_InitParam->Priority = DMA_PRIORITY_LOW;
+ /* Initialize the Mem2Mem member */
+ DMA_InitParam->Mem2Mem = DMA_M2M_DISABLE;
+}
+
+/**
+ * @brief Enables or disables the specified DMAy Channelx.
+ * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel.
+ * @param Cmd new state of the DMA Channelx.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DMA_EnableChannel(DMA_ChannelType* DMAChx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAChx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected DMAy Channelx */
+ DMAChx->CHCFG |= DMA_CHCFG1_CHEN;
+ }
+ else
+ {
+ /* Disable the selected DMAy Channelx */
+ DMAChx->CHCFG &= (uint16_t)(~DMA_CHCFG1_CHEN);
+ }
+}
+
+/**
+ * @brief Enables or disables the specified DMAy Channelx interrupts.
+ * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel.
+ * @param DMAInt specifies the DMA interrupts sources to be enabled
+ * or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_INT_TXC Transfer complete interrupt mask
+ * @arg DMA_INT_HTX Half transfer interrupt mask
+ * @arg DMA_INT_ERR Transfer error interrupt mask
+ * @param Cmd new state of the specified DMA interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DMA_ConfigInt(DMA_ChannelType* DMAChx, uint32_t DMAInt, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAChx));
+ assert_param(IS_DMA_CONFIG_INT(DMAInt));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected DMA interrupts */
+ DMAChx->CHCFG |= DMAInt;
+ }
+ else
+ {
+ /* Disable the selected DMA interrupts */
+ DMAChx->CHCFG &= ~DMAInt;
+ }
+}
+
+/**
+ * @brief Sets the number of data units in the current DMAy Channelx transfer.
+ * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel.
+ * @param DataNumber The number of data units in the current DMAy Channelx
+ * transfer.
+ * @note This function can only be used when the DMAyChx is disabled.
+ */
+void DMA_SetCurrDataCounter(DMA_ChannelType* DMAChx, uint16_t DataNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAChx));
+
+ /*--------------------------- DMAy Channelx TXNUM Configuration ---------------*/
+ /* Write to DMA Channelx TXNUM */
+ DMAChx->TXNUM = DataNumber;
+}
+
+/**
+ * @brief Returns the number of remaining data units in the current
+ * DMA Channelx transfer.
+ * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel.
+ * @return The number of remaining data units in the current DMA Channelx
+ * transfer.
+ */
+uint16_t DMA_GetCurrDataCounter(DMA_ChannelType* DMAChx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAChx));
+ /* Return the number of remaining data units for DMAy Channelx */
+ return ((uint16_t)(DMAChx->TXNUM));
+}
+
+/**
+ * @brief Checks whether the specified DMA Channelx flag is set or not.
+ * @param DMAFlag specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg DMA_FLAG_GL1 DMA Channel1 global flag.
+ * @arg DMA_FLAG_TC1 DMA Channel1 transfer complete flag.
+ * @arg DMA_FLAG_HT1 DMA Channel1 half transfer flag.
+ * @arg DMA_FLAG_TE1 DMA Channel1 transfer error flag.
+ * @arg DMA_FLAG_GL2 DMA Channel2 global flag.
+ * @arg DMA_FLAG_TC2 DMA Channel2 transfer complete flag.
+ * @arg DMA_FLAG_HT2 DMA Channel2 half transfer flag.
+ * @arg DMA_FLAG_TE2 DMA Channel2 transfer error flag.
+ * @arg DMA_FLAG_GL3 DMA Channel3 global flag.
+ * @arg DMA_FLAG_TC3 DMA Channel3 transfer complete flag.
+ * @arg DMA_FLAG_HT3 DMA Channel3 half transfer flag.
+ * @arg DMA_FLAG_TE3 DMA Channel3 transfer error flag.
+ * @arg DMA_FLAG_GL4 DMA Channel4 global flag.
+ * @arg DMA_FLAG_TC4 DMA Channel4 transfer complete flag.
+ * @arg DMA_FLAG_HT4 DMA Channel4 half transfer flag.
+ * @arg DMA_FLAG_TE4 DMA Channel4 transfer error flag.
+ * @arg DMA_FLAG_GL5 DMA Channel5 global flag.
+ * @arg DMA_FLAG_TC5 DMA Channel5 transfer complete flag.
+ * @arg DMA_FLAG_HT5 DMA Channel5 half transfer flag.
+ * @arg DMA_FLAG_TE5 DMA Channel5 transfer error flag.
+ * @arg DMA_FLAG_GL6 DMA Channel6 global flag.
+ * @arg DMA_FLAG_TC6 DMA Channel6 transfer complete flag.
+ * @arg DMA_FLAG_HT6 DMA Channel6 half transfer flag.
+ * @arg DMA_FLAG_TE6 DMA Channel6 transfer error flag.
+ * @arg DMA_FLAG_GL7 DMA Channel7 global flag.
+ * @arg DMA_FLAG_TC7 DMA Channel7 transfer complete flag.
+ * @arg DMA_FLAG_HT7 DMA Channel7 half transfer flag.
+ * @arg DMA_FLAG_TE7 DMA Channel7 transfer error flag.
+ * @arg DMA_FLAG_GL8 DMA Channel7 global flag.
+ * @arg DMA_FLAG_TC8 DMA Channel7 transfer complete flag.
+ * @arg DMA_FLAG_HT8 DMA Channel7 half transfer flag.
+ * @arg DMA_FLAG_TE8 DMA Channel7 transfer error flag.
+ * @param DMAy DMA
+ * This parameter can be one of the following values:
+ * @arg DMA .
+ * @return The new state of DMAFlag (SET or RESET).
+ */
+FlagStatus DMA_GetFlagStatus(uint32_t DMAFlag, DMA_Module* DMAy)
+{
+ FlagStatus bitstatus = RESET;
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_GET_FLAG(DMAFlag));
+
+ /* Calculate the used DMAy */
+ /* Get DMAy INTSTS register value */
+ tmpregister = DMAy->INTSTS;
+
+ /* Check the status of the specified DMAy flag */
+ if ((tmpregister & DMAFlag) != (uint32_t)RESET)
+ {
+ /* DMAyFlag is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DMAyFlag is reset */
+ bitstatus = RESET;
+ }
+
+ /* Return the DMAyFlag status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the DMA Channelx's pending flags.
+ * @param DMAFlag specifies the flag to clear.
+ * This parameter can be any combination (for the same DMA) of the following values:
+ * @arg DMA_FLAG_GL1 DMA Channel1 global flag.
+ * @arg DMA_FLAG_TC1 DMA Channel1 transfer complete flag.
+ * @arg DMA_FLAG_HT1 DMA Channel1 half transfer flag.
+ * @arg DMA_FLAG_TE1 DMA Channel1 transfer error flag.
+ * @arg DMA_FLAG_GL2 DMA Channel2 global flag.
+ * @arg DMA_FLAG_TC2 DMA Channel2 transfer complete flag.
+ * @arg DMA_FLAG_HT2 DMA Channel2 half transfer flag.
+ * @arg DMA_FLAG_TE2 DMA Channel2 transfer error flag.
+ * @arg DMA_FLAG_GL3 DMA Channel3 global flag.
+ * @arg DMA_FLAG_TC3 DMA Channel3 transfer complete flag.
+ * @arg DMA_FLAG_HT3 DMA Channel3 half transfer flag.
+ * @arg DMA_FLAG_TE3 DMA Channel3 transfer error flag.
+ * @arg DMA_FLAG_GL4 DMA Channel4 global flag.
+ * @arg DMA_FLAG_TC4 DMA Channel4 transfer complete flag.
+ * @arg DMA_FLAG_HT4 DMA Channel4 half transfer flag.
+ * @arg DMA_FLAG_TE4 DMA Channel4 transfer error flag.
+ * @arg DMA_FLAG_GL5 DMA Channel5 global flag.
+ * @arg DMA_FLAG_TC5 DMA Channel5 transfer complete flag.
+ * @arg DMA_FLAG_HT5 DMA Channel5 half transfer flag.
+ * @arg DMA_FLAG_TE5 DMA Channel5 transfer error flag.
+ * @arg DMA_FLAG_GL6 DMA Channel6 global flag.
+ * @arg DMA_FLAG_TC6 DMA Channel6 transfer complete flag.
+ * @arg DMA_FLAG_HT6 DMA Channel6 half transfer flag.
+ * @arg DMA_FLAG_TE6 DMA Channel6 transfer error flag.
+ * @arg DMA_FLAG_GL7 DMA Channel7 global flag.
+ * @arg DMA_FLAG_TC7 DMA Channel7 transfer complete flag.
+ * @arg DMA_FLAG_HT7 DMA Channel7 half transfer flag.
+ * @arg DMA_FLAG_TE7 DMA Channel7 transfer error flag.
+ * @arg DMA_FLAG_GL8 DMA Channel8 global flag.
+ * @arg DMA_FLAG_TC8 DMA Channel8 transfer complete flag.
+ * @arg DMA_FLAG_HT8 DMA Channel8 half transfer flag.
+ * @arg DMA_FLAG_TE8 DMA Channel8 transfer error flag.
+ * @param DMA DMA
+ * This parameter can be one of the following values:
+ * @arg DMA .
+ */
+void DMA_ClearFlag(uint32_t DMAFlag, DMA_Module* DMAy)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_CLEAR_FLAG(DMAFlag));
+
+ /* Calculate the used DMAy */
+ /* Clear the selected DMAy flags */
+ DMAy->INTCLR = DMAFlag;
+}
+
+/**
+ * @brief Checks whether the specified DMA Channelx interrupt has occurred or not.
+ * @param DMA_IT specifies the DMAy interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DMA_INT_GLB1 DMA Channel1 global interrupt.
+ * @arg DMA_INT_TXC1 DMA Channel1 transfer complete interrupt.
+ * @arg DMA_INT_HTX1 DMA Channel1 half transfer interrupt.
+ * @arg DMA_INT_ERR1 DMA Channel1 transfer error interrupt.
+ * @arg DMA_INT_GLB2 DMA Channel2 global interrupt.
+ * @arg DMA_INT_TXC2 DMA Channel2 transfer complete interrupt.
+ * @arg DMA_INT_HTX2 DMA Channel2 half transfer interrupt.
+ * @arg DMA_INT_ERR2 DMA Channel2 transfer error interrupt.
+ * @arg DMA_INT_GLB3 DMA Channel3 global interrupt.
+ * @arg DMA_INT_TXC3 DMA Channel3 transfer complete interrupt.
+ * @arg DMA_INT_HTX3 DMA Channel3 half transfer interrupt.
+ * @arg DMA_INT_ERR3 DMA Channel3 transfer error interrupt.
+ * @arg DMA_INT_GLB4 DMA Channel4 global interrupt.
+ * @arg DMA_INT_TXC4 DMA Channel4 transfer complete interrupt.
+ * @arg DMA_INT_HTX4 DMA Channel4 half transfer interrupt.
+ * @arg DMA_INT_ERR4 DMA Channel4 transfer error interrupt.
+ * @arg DMA_INT_GLB5 DMA Channel5 global interrupt.
+ * @arg DMA_INT_TXC5 DMA Channel5 transfer complete interrupt.
+ * @arg DMA_INT_HTX5 DMA Channel5 half transfer interrupt.
+ * @arg DMA_INT_ERR5 DMA Channel5 transfer error interrupt.
+ * @arg DMA_INT_GLB6 DMA Channel6 global interrupt.
+ * @arg DMA_INT_TXC6 DMA Channel6 transfer complete interrupt.
+ * @arg DMA_INT_HTX6 DMA Channel6 half transfer interrupt.
+ * @arg DMA_INT_ERR6 DMA Channel6 transfer error interrupt.
+ * @arg DMA_INT_GLB7 DMA Channel7 global interrupt.
+ * @arg DMA_INT_TXC7 DMA Channel7 transfer complete interrupt.
+ * @arg DMA_INT_HTX7 DMA Channel7 half transfer interrupt.
+ * @arg DMA_INT_ERR7 DMA Channel7 transfer error interrupt.
+ * @arg DMA_INT_GLB8 DMA Channel8 global interrupt.
+ * @arg DMA_INT_TXC8 DMA Channel8 transfer complete interrupt.
+ * @arg DMA_INT_HTX8 DMA Channel8 half transfer interrupt.
+ * @arg DMA_INT_ERR8 DMA Channel8 transfer error interrupt.
+ * @param DMA DMA
+ * This parameter can be one of the following values:
+ * @arg DMA .
+ * @return The new state of DMA_IT (SET or RESET).
+ */
+INTStatus DMA_GetIntStatus(uint32_t DMA_IT, DMA_Module* DMAy)
+{
+ INTStatus bitstatus = RESET;
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_GET_IT(DMA_IT));
+
+ /* Calculate the used DMA */
+ /* Get DMAy INTSTS register value */
+ tmpregister = DMAy->INTSTS;
+
+ /* Check the status of the specified DMAy interrupt */
+ if ((tmpregister & DMA_IT) != (uint32_t)RESET)
+ {
+ /* DMAy_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DMAy_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the DMAInt status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the DMA Channelx's interrupt pending bits.
+ * @param DMA_IT specifies the DMA interrupt pending bit to clear.
+ * This parameter can be any combination (for the same DMA) of the following values:
+ * @arg DMA_INT_GLB1 DMA Channel1 global interrupt.
+ * @arg DMA_INT_TXC1 DMA Channel1 transfer complete interrupt.
+ * @arg DMA_INT_HTX1 DMA Channel1 half transfer interrupt.
+ * @arg DMA_INT_ERR1 DMA Channel1 transfer error interrupt.
+ * @arg DMA_INT_GLB2 DMA Channel2 global interrupt.
+ * @arg DMA_INT_TXC2 DMA Channel2 transfer complete interrupt.
+ * @arg DMA_INT_HTX2 DMA Channel2 half transfer interrupt.
+ * @arg DMA_INT_ERR2 DMA Channel2 transfer error interrupt.
+ * @arg DMA_INT_GLB3 DMA Channel3 global interrupt.
+ * @arg DMA_INT_TXC3 DMA Channel3 transfer complete interrupt.
+ * @arg DMA_INT_HTX3 DMA Channel3 half transfer interrupt.
+ * @arg DMA_INT_ERR3 DMA Channel3 transfer error interrupt.
+ * @arg DMA_INT_GLB4 DMA Channel4 global interrupt.
+ * @arg DMA_INT_TXC4 DMA Channel4 transfer complete interrupt.
+ * @arg DMA_INT_HTX4 DMA Channel4 half transfer interrupt.
+ * @arg DMA_INT_ERR4 DMA Channel4 transfer error interrupt.
+ * @arg DMA_INT_GLB5 DMA Channel5 global interrupt.
+ * @arg DMA_INT_TXC5 DMA Channel5 transfer complete interrupt.
+ * @arg DMA_INT_HTX5 DMA Channel5 half transfer interrupt.
+ * @arg DMA_INT_ERR5 DMA Channel5 transfer error interrupt.
+ * @arg DMA_INT_GLB6 DMA Channel6 global interrupt.
+ * @arg DMA_INT_TXC6 DMA Channel6 transfer complete interrupt.
+ * @arg DMA_INT_HTX6 DMA Channel6 half transfer interrupt.
+ * @arg DMA_INT_ERR6 DMA Channel6 transfer error interrupt.
+ * @arg DMA_INT_GLB7 DMA Channel7 global interrupt.
+ * @arg DMA_INT_TXC7 DMA Channel7 transfer complete interrupt.
+ * @arg DMA_INT_HTX7 DMA Channel7 half transfer interrupt.
+ * @arg DMA_INT_ERR7 DMA Channel7 transfer error interrupt.
+ * @arg DMA_INT_GLB8 DMA Channel8 global interrupt.
+ * @arg DMA_INT_TXC8 DMA Channel8 transfer complete interrupt.
+ * @arg DMA_INT_HTX8 DMA Channel8 half transfer interrupt.
+ * @arg DMA_INT_ERR8 DMA Channel8 transfer error interrupt.
+ * @param DMAy DMA
+ * This parameter can be one of the following values:
+ * @arg DMA .
+ */
+void DMA_ClrIntPendingBit(uint32_t DMA_IT, DMA_Module* DMAy)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_CLR_INT(DMA_IT));
+
+ /* Calculate the used DMA */
+ /* Clear the selected DMA interrupt pending bits */
+ DMAy->INTCLR = DMA_IT;
+}
+
+/**
+ * @brief Set the DMA Channelx's remap request.
+ * @param DMA_REMAP specifies the DMA request.
+ * This parameter can be set by the following values:
+ * @arg DMA_REMAP_ADC1 DMA Request For ADC1.
+ * @arg DMA_REMAP_USART1_TX DMA Request For USART1_TX.
+ * @arg DMA_REMAP_USART1_RX DMA Request For USART1_RX.
+ * @arg DMA_REMAP_USART2_TX DMA Request For USART2_TX.
+ * @arg DMA_REMAP_USART2_RX DMA Request For USART2_RX.
+ * @arg DMA_REMAP_USART3_TX DMA Request For USART3_TX.
+ * @arg DMA_REMAP_USART3_RX DMA Request For USART3_RX.
+ * @arg DMA_REMAP_UART4_TX DMA Request For UART4_TX.
+ * @arg DMA_REMAP_UART4_RX DMA Request For UART4_RX.
+ * @arg DMA_REMAP_UART5_TX DMA Request For UART5_TX.
+ * @arg DMA_REMAP_UART5_RX DMA Request For UART5_RX.
+ * @arg DMA_REMAP_LPUART_TX DMA Request For LPUART_TX.
+ * @arg DMA_REMAP_LPUART_RX DMA Request For LPUART_RX.
+ * @arg DMA_REMAP_SPI1_TX DMA Request For SPI1_TX.
+ * @arg DMA_REMAP_SPI1_RX DMA Request For SPI1_RX.
+ * @arg DMA_REMAP_SPI2_TX DMA Request For SPI2_TX.
+ * @arg DMA_REMAP_SPI2_RX DMA Request For SPI2_RX.
+ * @arg DMA_REMAP_I2C1_TX DMA Request For I2C1_TX.
+ * @arg DMA_REMAP_I2C1_RX DMA Request For I2C1_RX.
+ * @arg DMA_REMAP_I2C2_TX DMA Request For I2C2_TX.
+ * @arg DMA_REMAP_I2C2_RX DMA Request For I2C2_RX.
+ * @arg DMA_REMAP_DAC1 DMA Request For DAC1.
+ * @arg DMA_REMAP_TIM1_CH1 DMA Request For TIM1_CH1.
+ * @arg DMA_REMAP_TIM1_CH2 DMA Request For TIM1_CH2.
+ * @arg DMA_REMAP_TIM1_CH3 DMA Request For TIM1_CH3.
+ * @arg DMA_REMAP_TIM1_CH4 DMA Request For TIM1_CH4.
+ * @arg DMA_REMAP_TIM1_COM DMA Request For TIM1_COM.
+ * @arg DMA_REMAP_TIM1_UP DMA Request For TIM1_UP.
+ * @arg DMA_REMAP_TIM1_TRIG DMA Request For TIM1_TRIG.
+ * @arg DMA_REMAP_TIM2_CH1 DMA Request For TIM2_CH1.
+ * @arg DMA_REMAP_TIM2_CH2 DMA Request For TIM2_CH2.
+ * @arg DMA_REMAP_TIM2_CH3 DMA Request For TIM2_CH3.
+ * @arg DMA_REMAP_TIM2_CH4 DMA Request For TIM3_TRIG.
+ * @arg DMA_REMAP_TIM2_UP DMA Request For TIM2_UP.
+ * @arg DMA_REMAP_TIM3_CH1 DMA Request For TIM3_CH1.
+ * @arg DMA_REMAP_TIM3_CH3 DMA Request For TIM3_CH3.
+ * @arg DMA_REMAP_TIM3_CH4 DMA Request For TIM3_CH4.
+ * @arg DMA_REMAP_TIM3_UP DMA Request For TIM3_UP.
+ * @arg DMA_REMAP_TIM3_TRIG DMA Request For TIM3_TRIG.
+ * @arg DMA_REMAP_TIM4_CH1 DMA Request For TIM4_CH1.
+ * @arg DMA_REMAP_TIM4_CH2 DMA Request For TIM4_CH2.
+ * @arg DMA_REMAP_TIM4_CH3 DMA Request For TIM4_CH3.
+ * @arg DMA_REMAP_TIM4_UP DMA Request For TIM4_UP.
+ * @arg DMA_REMAP_TIM5_CH1 DMA Request For TIM5_CH1.
+ * @arg DMA_REMAP_TIM5_CH2 DMA Request For TIM5_CH2.
+ * @arg DMA_REMAP_TIM5_CH3 DMA Request For TIM5_CH3.
+ * @arg DMA_REMAP_TIM5_CH4 DMA Request For TIM5_CH4.
+ * @arg DMA_REMAP_TIM5_UP DMA Request For TIM5_UP.
+ * @arg DMA_REMAP_TIM5_TRIG DMA Request For TIM5_TRIG.
+ * @arg DMA_REMAP_TIM6_UP DMA Request For TIM6_UP.
+ * @arg DMA_REMAP_TIM7_UP DMA Request For TIM7_UP.
+ * @arg DMA_REMAP_TIM8_CH1 DMA Request For TIM8_CH1.
+ * @arg DMA_REMAP_TIM8_CH2 DMA Request For TIM8_CH2.
+ * @arg DMA_REMAP_TIM8_CH3 DMA Request For TIM8_CH3.
+ * @arg DMA_REMAP_TIM8_CH4 DMA Request For TIM8_CH4.
+ * @arg DMA_REMAP_TIM8_COM DMA Request For TIM8_COM.
+ * @arg DMA_REMAP_TIM8_UP DMA Request For TIM8_UP.
+ * @arg DMA_REMAP_TIM8_TRIG DMA Request For TIM8_TRIG.
+ * @arg DMA_REMAP_TIM9_CH1 DMA Request For TIM9_CH1.
+ * @arg DMA_REMAP_TIM9_TRIG DMA Request For TIM9_TRIG.
+ * @arg DMA_REMAP_TIM9_CH3 DMA Request For TIM9_CH3.
+ * @arg DMA_REMAP_TIM9_CH4 DMA Request For TIM9_CH4.
+ * @arg DMA_REMAP_TIM9_UP DMA Request For TIM9_UP.
+ * @param DMAy DMA
+ * This parameter can be one of the following values:
+ * @arg DMA .
+ * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel.
+ * @param Cmd new state of the DMA Channelx.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DMA_RequestRemap(uint32_t DMA_REMAP, DMA_Module* DMAy, DMA_ChannelType* DMAChx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_REMAP(DMA_REMAP));
+
+ if (Cmd != DISABLE)
+ {
+ /* Calculate the used DMAy */
+ /* Set the selected DMAy remap request */
+ DMAChx->CHSEL = DMA_REMAP;
+ }
+ else
+ {
+ /* Clear DMAy remap */
+ DMAChx->CHSEL = 0;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_exti.c b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_exti.c
new file mode 100644
index 0000000000..4c66aada10
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_exti.c
@@ -0,0 +1,286 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_exti.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_exti.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup EXTI
+ * @brief EXTI driver modules
+ * @{
+ */
+
+/** @addtogroup EXTI_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Private_Defines
+ * @{
+ */
+
+#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the EXTI peripheral registers to their default reset values.
+ */
+void EXTI_DeInit(void)
+{
+ EXTI->IMASK = 0x00000000;
+ EXTI->EMASK = 0x00000000;
+ EXTI->RT_CFG = 0x00000000;
+ EXTI->FT_CFG = 0x00000000;
+ EXTI->PEND = 0x0FFFFFFF;
+}
+
+/**
+ * @brief Initializes the EXTI peripheral according to the specified
+ * parameters in the EXTI_InitStruct.
+ * @param EXTI_InitStruct pointer to a EXTI_InitType structure
+ * that contains the configuration information for the EXTI peripheral.
+ */
+void EXTI_InitPeripheral(EXTI_InitType* EXTI_InitStruct)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
+ assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
+ assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
+ assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
+
+ tmp = (uint32_t)EXTI_BASE;
+
+ if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
+ {
+ /* Clear EXTI line configuration */
+ EXTI->IMASK &= ~EXTI_InitStruct->EXTI_Line;
+ EXTI->EMASK &= ~EXTI_InitStruct->EXTI_Line;
+
+ tmp += EXTI_InitStruct->EXTI_Mode;
+
+ *(__IO uint32_t*)tmp |= EXTI_InitStruct->EXTI_Line;
+
+ /* Clear Rising Falling edge configuration */
+ EXTI->RT_CFG &= ~EXTI_InitStruct->EXTI_Line;
+ EXTI->FT_CFG &= ~EXTI_InitStruct->EXTI_Line;
+
+ /* Select the trigger for the selected external interrupts */
+ if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
+ {
+ /* Rising Falling edge */
+ EXTI->RT_CFG |= EXTI_InitStruct->EXTI_Line;
+ EXTI->FT_CFG |= EXTI_InitStruct->EXTI_Line;
+ }
+ else
+ {
+ tmp = (uint32_t)EXTI_BASE;
+ tmp += EXTI_InitStruct->EXTI_Trigger;
+
+ *(__IO uint32_t*)tmp |= EXTI_InitStruct->EXTI_Line;
+ }
+ }
+ else
+ {
+ tmp += EXTI_InitStruct->EXTI_Mode;
+
+ /* Disable the selected external lines */
+ *(__IO uint32_t*)tmp &= ~EXTI_InitStruct->EXTI_Line;
+ }
+}
+
+/**
+ * @brief Fills each EXTI_InitStruct member with its reset value.
+ * @param EXTI_InitStruct pointer to a EXTI_InitType structure which will
+ * be initialized.
+ */
+void EXTI_InitStruct(EXTI_InitType* EXTI_InitStruct)
+{
+ EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
+ EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
+ EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
+ EXTI_InitStruct->EXTI_LineCmd = DISABLE;
+}
+
+/**
+ * @brief Generates a Software interrupt.
+ * @param EXTI_Line specifies the EXTI lines to be enabled or disabled.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..27).
+ */
+void EXTI_TriggerSWInt(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(EXTI_Line));
+
+ EXTI->SWIE |= EXTI_Line;
+}
+
+/**
+ * @brief Checks whether the specified EXTI line flag is set or not.
+ * @param EXTI_Line specifies the EXTI line flag to check.
+ * This parameter can be:
+ * @arg EXTI_Linex External interrupt line x where x(0..27)
+ * @return The new state of EXTI_Line (SET or RESET).
+ */
+FlagStatus EXTI_GetStatusFlag(uint32_t EXTI_Line)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+ if ((EXTI->PEND & EXTI_Line) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the EXTI's line pending flags.
+ * @param EXTI_Line specifies the EXTI lines flags to clear.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..27).
+ */
+void EXTI_ClrStatusFlag(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(EXTI_Line));
+
+ EXTI->PEND = EXTI_Line;
+}
+
+/**
+ * @brief Checks whether the specified EXTI line is asserted or not.
+ * @param EXTI_Line specifies the EXTI line to check.
+ * This parameter can be:
+ * @arg EXTI_Linex External interrupt line x where x(0..27)
+ * @return The new state of EXTI_Line (SET or RESET).
+ */
+INTStatus EXTI_GetITStatus(uint32_t EXTI_Line)
+{
+ INTStatus bitstatus = RESET;
+ uint32_t enablestatus = 0;
+ /* Check the parameters */
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+ enablestatus = EXTI->IMASK & EXTI_Line;
+ if (((EXTI->PEND & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the EXTI's line pending bits.
+ * @param EXTI_Line specifies the EXTI lines to clear.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..27).
+ */
+void EXTI_ClrITPendBit(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(EXTI_Line));
+
+ EXTI->PEND = EXTI_Line;
+}
+
+/**
+ * @brief Select one of EXTI inputs to the RTC TimeStamp event.
+ * @param EXTI_TSSEL_Line specifies the EXTI lines to select.
+ * This parameter can be any combination of EXTI_TSSEL_Line where x can be (0..15).
+ */
+void EXTI_RTCTimeStampSel(uint32_t EXTI_TSSEL_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_TSSEL_LINE(EXTI_TSSEL_Line));
+
+ EXTI->TS_SEL &= EXTI_TSSEL_LINE_MASK;
+ EXTI->TS_SEL |= EXTI_TSSEL_Line;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_flash.c b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_flash.c
new file mode 100644
index 0000000000..e75f97df88
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_flash.c
@@ -0,0 +1,1565 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_flash.c
+ * @author Nations
+ * @version V1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_flash.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @brief FLASH driver modules
+ * @{
+ */
+
+/** @addtogroup FLASH_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Defines
+ * @{
+ */
+
+/* Flash Access Control Register bits */
+#define AC_LATENCY_MSK ((uint32_t)0x000000F8)
+#define AC_PRFTBE_MSK ((uint32_t)0xFFFFFFEF)
+#define AC_ICAHEN_MSK ((uint32_t)0xFFFFFF7F)
+#define AC_LVMEN_MSK ((uint32_t)0xFFFFFDFF)
+#define AC_SLMEN_MSK ((uint32_t)0xFFFFF7FF)
+
+/* Flash Access Control Register bits */
+#define AC_PRFTBS_MSK ((uint32_t)0x00000020)
+#define AC_ICAHRST_MSK ((uint32_t)0x00000040)
+#define AC_LVMF_MSK ((uint32_t)0x00000100)
+#define AC_SLMF_MSK ((uint32_t)0x00000400)
+
+/* Flash Control Register bits */
+#define CTRL_Set_PG ((uint32_t)0x00000001)
+#define CTRL_Reset_PG ((uint32_t)0x00003FFE)
+#define CTRL_Set_PER ((uint32_t)0x00000002)
+#define CTRL_Reset_PER ((uint32_t)0x00003FFD)
+#define CTRL_Set_MER ((uint32_t)0x00000004)
+#define CTRL_Reset_MER ((uint32_t)0x00003FFB)
+#define CTRL_Set_OPTPG ((uint32_t)0x00000010)
+#define CTRL_Reset_OPTPG ((uint32_t)0x00003FEF)
+#define CTRL_Set_OPTER ((uint32_t)0x00000020)
+#define CTRL_Reset_OPTER ((uint32_t)0x00003FDF)
+#define CTRL_Set_START ((uint32_t)0x00000040)
+#define CTRL_Set_LOCK ((uint32_t)0x00000080)
+#define CTRL_Reset_SMPSEL ((uint32_t)0x00003EFF)
+#define CTRL_SMPSEL_SMP1 ((uint32_t)0x00000000)
+#define CTRL_SMPSEL_SMP2 ((uint32_t)0x00000100)
+
+/* FLASH Mask */
+#define RDPRTL1_MSK ((uint32_t)0x00000002)
+#define RDPRTL2_MSK ((uint32_t)0x80000000)
+#define OBR_USER_MSK ((uint32_t)0x0000001C)
+#define WRP0_MSK ((uint32_t)0x000000FF)
+#define WRP1_MSK ((uint32_t)0x0000FF00)
+#define WRP2_MSK ((uint32_t)0x00FF0000)
+#define WRP3_MSK ((uint32_t)0xFF000000)
+
+/* FLASH Keys */
+#define L1_RDP_Key ((uint32_t)0xFFFF00A5)
+#define RDP_USER_Key ((uint32_t)0xFFF000A5)
+#define L2_RDP_Key ((uint32_t)0xFFFF33CC)
+#define FLASH_KEY1 ((uint32_t)0x45670123)
+#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
+
+/* Delay definition */
+#define EraseTimeout ((uint32_t)0x000B0000)
+#define ProgramTimeout ((uint32_t)0x00002000)
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Sets the code latency value.
+ * @note This function can be used for N32G43x devices.
+ * @param FLASH_Latency specifies the FLASH Latency value.
+ * This parameter can be one of the following values:
+ * @arg FLASH_LATENCY_0 FLASH Zero Latency cycle
+ * @arg FLASH_LATENCY_1 FLASH One Latency cycle
+ * @arg FLASH_LATENCY_2 FLASH Two Latency cycles
+ * @arg FLASH_LATENCY_3 FLASH Three Latency cycles
+ */
+void FLASH_SetLatency(uint32_t FLASH_Latency)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_LATENCY(FLASH_Latency));
+
+ /* Read the ACR register */
+ tmpregister = FLASH->AC;
+
+ /* Sets the Latency value */
+ tmpregister &= AC_LATENCY_MSK;
+ tmpregister |= FLASH_Latency;
+
+ /* Write the ACR register */
+ FLASH->AC = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the Prefetch Buffer.
+ * @note This function can be used for N32G43x devices.
+ * @param FLASH_PrefetchBuf specifies the Prefetch buffer status.
+ * This parameter can be one of the following values:
+ * @arg FLASH_PrefetchBuf_EN FLASH Prefetch Buffer Enable
+ * @arg FLASH_PrefetchBuf_DIS FLASH Prefetch Buffer Disable
+ */
+void FLASH_PrefetchBufSet(uint32_t FLASH_PrefetchBuf)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_PREFETCHBUF_STATE(FLASH_PrefetchBuf));
+
+ /* Enable or disable the Prefetch Buffer */
+ FLASH->AC &= AC_PRFTBE_MSK;
+ FLASH->AC |= FLASH_PrefetchBuf;
+}
+
+/**
+ * @brief ICache Reset.
+ * @note This function can be used for N32G43x devices.
+ */
+void FLASH_iCacheRST(void)
+{
+ /* ICache Reset */
+ FLASH->AC |= FLASH_AC_ICAHRST;
+}
+
+/**
+ * @brief Enables or disables the iCache.
+ * @note This function can be used for N32G43x devices.
+ * @param FLASH_iCache specifies the iCache status.
+ * This parameter can be one of the following values:
+ * @arg FLASH_iCache_EN FLASH iCache Enable
+ * @arg FLASH_iCache_DIS FLASH iCache Disable
+ */
+void FLASH_iCacheCmd(uint32_t FLASH_iCache)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_ICACHE_STATE(FLASH_iCache));
+
+ /* Enable or disable the iCache */
+ FLASH->AC &= AC_ICAHEN_MSK;
+ FLASH->AC |= FLASH_iCache;
+}
+
+/**
+ * @brief Enables or disables the Low Voltage Mode.
+ * @note This function can be used for N32G43x devices.
+ * @param FLASH_LVM specifies the Low Voltage Mode status.
+ * This parameter can be one of the following values:
+ * @arg FLASH_LVM_EN FLASH Low Voltage Mode Enable
+ * @arg FLASH_LVM_DIS FLASH Low Voltage Mode Disable
+ */
+void FLASH_LowVoltageModeCmd(uint32_t FLASH_LVM)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_LVM(FLASH_LVM));
+
+ /* Enable or disable LVM */
+ FLASH->AC &= AC_LVMEN_MSK;
+ FLASH->AC |= FLASH_LVM;
+}
+
+/**
+ * @brief Checks whether the Low Voltage Mode status is SET or RESET.
+ * @note This function can be used for N32G43x devices.
+ * @return Low Voltage Mode Status (SET or RESET).
+ */
+FlagStatus FLASH_GetLowVoltageModeSTS(void)
+{
+ FlagStatus bitstatus = RESET;
+
+ if ((FLASH->AC & AC_LVMF_MSK) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the new state of FLASH Low Voltage Mode Status (SET or RESET) */
+ return bitstatus;
+}
+
+/**
+ * @brief Enables or disables the FLASH Sleep Mode.
+ * @note This function can be used for N32G43x devices.
+ * @param FLASH_SLM specifies the FLASH Sleep Mode status.
+ * This parameter can be one of the following values:
+ * @arg FLASH_SLM_EN FLASH iCache Enable
+ * @arg FLASH_SLM_DIS FLASH iCache Disable
+ */
+void FLASH_FLASHSleepModeCmd(uint32_t FLASH_SLM)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_SLM(FLASH_SLM));
+
+ /* Enable or disable SLM */
+ FLASH->AC &= AC_SLMEN_MSK;
+ FLASH->AC |= FLASH_SLM;
+}
+
+/**
+ * @brief Checks whether the FLASH Sleep Mode status is SET or RESET.
+ * @note This function can be used for N32G43x devices.
+ * @return FLASH Sleep Mode Status (SET or RESET).
+ */
+FlagStatus FLASH_GetFLASHSleepModeSTS(void)
+{
+ FlagStatus bitstatus = RESET;
+
+ if ((FLASH->AC & AC_SLMF_MSK) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the new state of FLASH Sleep Mode Status (SET or RESET) */
+ return bitstatus;
+}
+
+/**
+ * @brief Checks whether the FLASH SMPSEL is SMP1 or SMP2.
+ * @note This function can be used for N32G43x devices.
+ * @param FLASH_smpsel FLASH_SMPSEL_SMP1 or FLASH_SMPSEL_SMP2
+ */
+void FLASH_SetSMPSELStatus(uint32_t FLASH_smpsel)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_SMPSEL_STATE(FLASH_smpsel));
+
+ /* SMP1 or SMP2 */
+ FLASH->CTRL &= CTRL_Reset_SMPSEL;
+ FLASH->CTRL |= FLASH_smpsel;
+}
+
+/**
+ * @brief Configures the Internal High Speed oscillator
+ * to program/erase FLASH.
+ * @note This function can be used for N32G43x devices.
+ * - For N32G43x devices this function enable HSI.
+ * @return FLASH_HSICLOCK (FLASH_HSICLOCK_ENABLE or FLASH_HSICLOCK_DISABLE).
+ */
+FLASH_HSICLOCK FLASH_ClockInit(void)
+{
+ bool HSIStatus = 0;
+ __IO uint32_t StartUpCounter = 0;
+ FLASH_HSICLOCK hsiclock_status = FLASH_HSICLOCK_ENABLE;
+
+ if ((RCC->CTRL & RCC_CTRL_HSIRDF) == RESET)
+ {
+ /* Enable HSI */
+ RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
+
+ /* Wait till HSI is ready and if Time out is reached exit */
+ do
+ {
+ HSIStatus = RCC->CTRL & RCC_CTRL_HSIRDF;
+ StartUpCounter++;
+ } while ((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));
+
+ HSIStatus = ((RCC->CTRL & RCC_CTRL_HSIRDF) != RESET);
+ if (!HSIStatus)
+ {
+ hsiclock_status = FLASH_HSICLOCK_DISABLE;
+ }
+ }
+ return hsiclock_status;
+}
+
+/**
+ * @brief Unlocks the FLASH Program Erase Controller.
+ * @note This function can be used for N32G43x devices.
+ * - For N32G43x devices this function unlocks Bank.
+ * to FLASH_Unlock function..
+ */
+void FLASH_Unlock(void)
+{
+ /* Unlocks the FLASH Program Erase Controller */
+ FLASH->KEYR = FLASH_KEY1;
+ FLASH->KEYR = FLASH_KEY2;
+}
+
+/**
+ * @brief Locks the FLASH Program Erase Controller.
+ * @note This function can be used for N32G43x devices.
+ * - For N32G43x devices this function Locks Bank.
+ * to FLASH_Lock function.
+ */
+void FLASH_Lock(void)
+{
+ /* Set the Lock Bit to lock the FLASH Program Erase Controller */
+ FLASH->CTRL |= CTRL_Set_LOCK;
+}
+
+/**
+ * @brief Erases a specified FLASH page.
+ * @note This function can be used for N32G43x devices.
+ * @param Page_Address The page address to be erased.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_EraseOnePage(uint32_t Page_Address)
+{
+ FLASH_STS status = FLASH_COMPL;
+ /* Check the parameters */
+ assert_param(IS_FLASH_ADDRESS(Page_Address));
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* if the previous operation is completed, proceed to erase the page */
+ FLASH->CTRL |= CTRL_Set_PER;
+ FLASH->ADD = Page_Address;
+ FLASH->CTRL |= CTRL_Set_START;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ /* Disable the PER Bit */
+ FLASH->CTRL &= CTRL_Reset_PER;
+ }
+
+ /* Return the Erase Status */
+ return status;
+}
+
+/**
+ * @brief Erases all FLASH pages.
+ * @note This function can be used for all N32G43x devices.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_MassErase(void)
+{
+ FLASH_STS status = FLASH_COMPL;
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+ if (status == FLASH_COMPL)
+ {
+ /* if the previous operation is completed, proceed to erase all pages */
+ FLASH->CTRL |= CTRL_Set_MER;
+ FLASH->CTRL |= CTRL_Set_START;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ /* Disable the MER Bit */
+ FLASH->CTRL &= CTRL_Reset_MER;
+ }
+
+ /* Return the Erase Status */
+ return status;
+}
+
+/**
+ * @brief Erases the FLASH option bytes.
+ * @note This functions erases all option bytes except the Read protection (RDP).
+ * @note This function can be used for N32G43x devices.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_EraseOB(void)
+{
+ uint32_t rdptmp = L1_RDP_Key;
+
+ FLASH_STS status = FLASH_COMPL;
+
+ /* Get the actual read protection L2 Option Byte value */
+ if (FLASH_GetReadOutProtectionL2STS() != RESET)
+ {
+ status = FLASH_ERR_RDP2;
+ return status;
+ }
+
+ /* Get the actual read protection Option Byte value */
+ if (FLASH_GetReadOutProtectionSTS() != RESET)
+ {
+ rdptmp = FLASH_USER_USER;
+ }
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Authorize the small information block programming */
+ FLASH->OPTKEY = FLASH_KEY1;
+ FLASH->OPTKEY = FLASH_KEY2;
+
+ /* if the previous operation is completed, proceed to erase the option bytes */
+ FLASH->CTRL |= CTRL_Set_OPTER;
+ FLASH->CTRL |= CTRL_Set_START;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* if the erase operation is completed, disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CTRL |= CTRL_Set_OPTPG;
+ /* Restore the last read protection Option Byte value */
+ OBT->USER_RDP = (uint32_t)rdptmp;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTPG;
+ }
+ }
+ else
+ {
+ if (status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+ }
+ }
+ }
+ /* Return the erase status */
+ return status;
+}
+
+
+/**
+ * @brief Programs the FLASH User Option Byte:
+ * RDP1 / IWDG_SW / RST_STOP2 / RST_STDBY / RST_PD / OB_Data0 / OB_Data1
+ * WRP_Pages / RDP2 / nBOOT0 / nBOOT1 / nSWBOOT0 / BOR_LEV[2:0].
+ * @note This function can be used for N32G43x devices.
+ * @param OB_RDP1
+ * This parameter can be one of the following values:
+ * @arg OB_RDP1_ENABLE
+ * @arg OB_RDP1_DISABLE
+ * @param OB_IWDG Selects the IWDG mode
+ * This parameter can be one of the following values:
+ * @arg OB_IWDG_SW Software IWDG selected
+ * @arg OB_IWDG_HW Hardware IWDG selected
+ * @param OB_STOP2 Reset event when entering STOP2 mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STOP2_NORST No reset generated when entering in STOP2
+ * @arg OB_STOP2_RST Reset generated when entering in STOP2
+ * @param OB_STDBY Reset event when entering Standby mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STDBY_NORST No reset generated when entering in STANDBY
+ * @arg OB_STDBY_RST Reset generated when entering in STANDBY
+ * @param OB_PD Reset event when entering PowerDown mode.
+ * This parameter can be one of the following values:
+ * @arg OB_PD_NORST No reset generated when entering in PowerDown
+ * @arg OB_PD_RST Reset generated when entering in PowerDown
+ * @param OB_Data0
+ * This parameter can be one of the following values:
+ * @arg 0x00 ~ 0xFF
+ * @param OB_Data1
+ * This parameter can be one of the following values:
+ * @arg 0x00 ~ 0xFF
+ * @param WRP_Pages specifies the address of the pages to be write protected.
+ * This parameter can be:
+ * @arg For @b N32G43x_devices: value between FLASH_WRP_Pages0to1 and
+ * FLASH_WRP_Pages62to63 or FLASH_WRP_AllPages or (~FLASH_WRP_AllPages)
+ * @param OB_RDP2
+ * This parameter can be one of the following values:
+ * @arg OB_RDP2_ENABLE
+ * @arg OB_RDP2_DISABLE
+ * @param OB2_nBOOT0
+ * This parameter can be one of the following values:
+ * @arg OB2_NBOOT0_SET Set nBOOT0
+ * @arg OB2_NBOOT0_CLR Clear nBOOT0
+ * @param OB2_nBOOT1
+ * This parameter can be one of the following values:
+ * @arg OB2_NBOOT1_SET Set nBOOT1
+ * @arg OB2_NBOOT1_CLR Clear nBOOT1
+ * @param OB2_nSWBOOT0
+ * This parameter can be one of the following values:
+ * @arg OB2_NSWBOOT0_SET Set nSWBOOT0
+ * @arg OB2_NSWBOOT0_CLR Clear nSWBOOT0
+* @param OB2_BOR_LEV[2:0]
+ * This parameter can be one of the following values:
+ * @arg OB2_BOR_LEV0
+ * @arg OB2_BOR_LEV1
+ * @arg OB2_BOR_LEV2
+ * @arg OB2_BOR_LEV3
+ * @arg OB2_BOR_LEV4
+ * @arg OB2_BOR_LEV5
+ * @arg OB2_BOR_LEV6
+ * @arg OB2_BOR_LEV7
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ConfigALLOptionByte(uint8_t OB_RDP1, uint8_t OB_IWDG, uint8_t OB_STOP2,
+ uint8_t OB_STDBY, uint8_t OB_PD, uint8_t OB_Data0,
+ uint8_t OB_Data1, uint32_t WRP_Pages, uint8_t OB_RDP2,
+ uint8_t OB2_nBOOT0, uint8_t OB2_nBOOT1, uint8_t OB2_nSWBOOT0,
+ uint8_t OB2_BOR_LEV)
+{
+ uint32_t rdpuser_tmp, data0data1_tmp, wrp0wrp1_tmp, wrp2wrp3_tmp, rdp2user2_tmp;
+
+ FLASH_STS status = FLASH_COMPL;
+
+ /* Check the parameters */
+ assert_param(IS_OB_RDP1_SOURCE(OB_RDP1));
+ assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
+ assert_param(IS_OB_STOP2_SOURCE(OB_STOP2));
+ assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
+ assert_param(IS_OB_PD_SOURCE(OB_PD));
+ assert_param(IS_FLASH_WRP_PAGE(WRP_Pages));
+ assert_param(IS_OB_RDP2_SOURCE(OB_RDP2));
+ assert_param(IS_OB2_NBOOT0_SOURCE(OB2_nBOOT0));
+ assert_param(IS_OB2_NBOOT1_SOURCE(OB2_nBOOT1));
+ assert_param(IS_OB2_NSWBOOT0_SOURCE(OB2_nSWBOOT0));
+ assert_param(IS_OB2_BOR_LEV_SOURCE(OB2_BOR_LEV));
+
+ /* Get the actual read protection L2 Option Byte value */
+ if (FLASH_GetReadOutProtectionL2STS() != RESET)
+ {
+ status = FLASH_ERR_RDP2;
+ return status;
+ }
+
+ WRP_Pages = (uint32_t)(~WRP_Pages);
+ rdpuser_tmp = (((uint32_t)OB_RDP1) | (((uint32_t)(OB_IWDG | OB_STOP2 | OB_STDBY | OB_PD)) << 16));
+ data0data1_tmp = (((uint32_t)OB_Data0) | (((uint32_t)OB_Data0) << 16));
+ wrp0wrp1_tmp = ((WRP_Pages & FLASH_WRP0_WRP0) | ((WRP_Pages << 8) & FLASH_WRP1_WRP1));
+ wrp2wrp3_tmp = (((WRP_Pages >> 16) & FLASH_WRP2_WRP2) | ((WRP_Pages >> 8) & FLASH_WRP3_WRP3));
+ rdp2user2_tmp = (((uint32_t)OB_RDP2) | (((uint32_t)(OB2_nBOOT0 | OB2_nBOOT1 | OB2_nSWBOOT0 | OB2_BOR_LEV)) << 16));
+
+ /* Authorize the small information block programming */
+ FLASH->OPTKEY = FLASH_KEY1;
+ FLASH->OPTKEY = FLASH_KEY2;
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+ if (status == FLASH_COMPL)
+ {
+ /* if the previous operation is completed, proceed to erase the option bytes */
+ FLASH->CTRL |= CTRL_Set_OPTER;
+ FLASH->CTRL |= CTRL_Set_START;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* if the erase operation is completed, disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CTRL |= CTRL_Set_OPTPG;
+
+ /* Program USER_RDP Option Byte value */
+ OBT->USER_RDP = (uint32_t)rdpuser_tmp;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* Program Data1_Data0 Option Byte value */
+ OBT->Data1_Data0 = (uint32_t)data0data1_tmp;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* Program WRP1_WRP0 Option Byte value */
+ OBT->WRP1_WRP0 = (uint32_t)wrp0wrp1_tmp;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* Program WRP3_WRP2 Option Byte value */
+ OBT->WRP3_WRP2 = (uint32_t)wrp2wrp3_tmp;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* Program USER2_RDP2 Option Byte value */
+ OBT->USER2_RDP2 = (uint32_t)rdp2user2_tmp;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+ }
+ }
+ }
+ }
+
+ if (status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTPG;
+ }
+ }
+ else
+ {
+ if (status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+ }
+ }
+ }
+
+ /* Return the Option Byte program Status */
+ return status;
+}
+
+/**
+ * @brief Programs a word at a specified address.
+ * @note This function can be used for N32G43x devices.
+ * @param Address specifies the address to be programmed.
+ * @param Data specifies the data to be programmed.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_ADD or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ProgramWord(uint32_t Address, uint32_t Data)
+{
+ FLASH_STS status = FLASH_COMPL;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_ADDRESS(Address));
+
+ if ((Address & (uint32_t)0x3) != 0)
+ {
+ /* The programming address is not a multiple of 4 */
+ status = FLASH_ERR_ADD;
+ return status;
+ }
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* if the previous operation is completed, proceed to program the new word */
+ FLASH->CTRL |= CTRL_Set_PG;
+
+ *(__IO uint32_t*)Address = (uint32_t)Data;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ /* Disable the PG Bit */
+ FLASH->CTRL &= CTRL_Reset_PG;
+ }
+
+ /* Return the Program Status */
+ return status;
+}
+
+/**
+ * @brief Programs a half word at a specified Option Byte Data address.
+ * @note This function can be used for N32G43x devices.
+ * @param Address specifies the address to be programmed.
+ * This parameter can be 0x1FFFF804.
+ * @param Data specifies the data to be programmed(Data0 and Data1).
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ProgramOBData(uint32_t Address, uint32_t Data)
+{
+ FLASH_STS status = FLASH_COMPL;
+ /* Check the parameters */
+ assert_param(IS_OB_DATA_ADDRESS(Address));
+
+ /* Get the actual read protection L2 Option Byte value */
+ if (FLASH_GetReadOutProtectionL2STS() != RESET)
+ {
+ status = FLASH_ERR_RDP2;
+ return status;
+ }
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Authorize the small information block programming */
+ FLASH->OPTKEY = FLASH_KEY1;
+ FLASH->OPTKEY = FLASH_KEY2;
+ /* Enables the Option Bytes Programming operation */
+ FLASH->CTRL |= CTRL_Set_OPTPG;
+ *(__IO uint32_t*)Address = (uint32_t)Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+ if (status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTPG;
+ }
+ }
+ /* Return the Option Byte Data Program Status */
+ return status;
+}
+
+/**
+ * @brief Write protects the desired pages
+ * @note This function can be used for N32G43x devices.
+ * @param FLASH_Pages specifies the address of the pages to be write protected.
+ * This parameter can be:
+ * @arg For @b N32G43x_devices: value between FLASH_WRP_Pages0to1 and
+ * FLASH_WRP_Pages60to61 or FLASH_WRP_Pages62to63
+ * @arg FLASH_WRP_AllPages
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_EnWriteProtection(uint32_t FLASH_Pages)
+{
+ uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
+
+ FLASH_STS status = FLASH_COMPL;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_WRP_PAGE(FLASH_Pages));
+
+ /* Get the actual read protection L2 Option Byte value */
+ if (FLASH_GetReadOutProtectionL2STS() != RESET)
+ {
+ status = FLASH_ERR_RDP2;
+ return status;
+ }
+
+ FLASH_Pages = (uint32_t)(~FLASH_Pages);
+ WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_MSK);
+ WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_MSK) >> 8);
+ WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_MSK) >> 16);
+ WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_MSK) >> 24);
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Authorizes the small information block programming */
+ FLASH->OPTKEY = FLASH_KEY1;
+ FLASH->OPTKEY = FLASH_KEY2;
+ FLASH->CTRL |= CTRL_Set_OPTPG;
+
+ if ((WRP0_Data != 0xFF) || (WRP1_Data != 0xFF))
+ {
+ OBT->WRP1_WRP0 = (((uint32_t)WRP0_Data) | (((uint32_t)WRP1_Data) << 16));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+ }
+
+ if (((WRP2_Data != 0xFF) || (WRP3_Data != 0xFF)) && (status == FLASH_COMPL))
+ {
+ OBT->WRP3_WRP2 = (((uint32_t)WRP2_Data) | (((uint32_t)WRP3_Data) << 16));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+ }
+
+ if (status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTPG;
+ }
+ }
+ /* Return the write protection operation Status */
+ return status;
+}
+
+/**
+ * @brief Enables or disables the read out protection.
+ * @note If the user has already programmed the other option bytes before calling
+ * this function, he must re-program them since this function erases all option bytes.
+ * @note This function can be used for N32G43x devices.
+ * @param Cmd new state of the ReadOut Protection.
+ * This parameter can be: ENABLE or DISABLE.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ReadOutProtectionL1(FunctionalState Cmd)
+{
+ uint32_t usertmp;
+ FLASH_STS status = FLASH_COMPL;
+
+ usertmp = ((OBR_USER_MSK & FLASH->OB) << 0x0E);
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ /* Get the actual read protection L2 Option Byte value */
+ if (FLASH_GetReadOutProtectionL2STS() != RESET)
+ {
+ status = FLASH_ERR_RDP2;
+ return status;
+ }
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Authorizes the small information block programming */
+ FLASH->OPTKEY = FLASH_KEY1;
+ FLASH->OPTKEY = FLASH_KEY2;
+ FLASH->CTRL |= CTRL_Set_OPTER;
+ FLASH->CTRL |= CTRL_Set_START;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* if the erase operation is completed, disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CTRL |= CTRL_Set_OPTPG;
+ if (Cmd != DISABLE)
+ {
+ OBT->USER_RDP = (FLASH_USER_USER & usertmp);
+ }
+ else
+ {
+ OBT->USER_RDP = ((L1_RDP_Key & FLASH_RDP_RDP1) | usertmp);
+ }
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTPG;
+ }
+ }
+ else
+ {
+ if (status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+ }
+ }
+ }
+ /* Return the protection operation Status */
+ return status;
+}
+
+/**
+ * @brief Enables or disables the read out protection L2.
+ * @note If the user has already programmed the other option bytes before calling
+ * this function, he must re-program them since this function erases all option bytes.
+ * @note This function can be used for N32G43x devices.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ReadOutProtectionL2_ENABLE(void)
+{
+ uint32_t usertmp;
+ FLASH_STS status = FLASH_COMPL;
+
+ usertmp = ((OBR_USER_MSK & FLASH->OB) << 0x0E);
+
+ /* Get the actual read protection L1 Option Byte value */
+ if (FLASH_GetReadOutProtectionSTS() == RESET)
+ {
+ usertmp |= (L1_RDP_Key & FLASH_RDP_RDP1);
+ }
+ /* Get the actual read protection L2 Option Byte value */
+ if (FLASH_GetReadOutProtectionL2STS() != RESET)
+ {
+ status = FLASH_ERR_RDP2;
+ return status;
+ }
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Authorizes the small information block programming */
+ FLASH->OPTKEY = FLASH_KEY1;
+ FLASH->OPTKEY = FLASH_KEY2;
+ FLASH->CTRL |= CTRL_Set_OPTER;
+ FLASH->CTRL |= CTRL_Set_START;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* if the erase operation is completed, disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CTRL |= CTRL_Set_OPTPG;
+
+ OBT->USER_RDP = usertmp;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* Enables the read out protection L2 */
+ OBT->USER2_RDP2 = L2_RDP_Key;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+ }
+
+ if (status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTPG;
+ }
+ }
+ else
+ {
+ if (status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+ }
+ }
+ }
+ /* Return the protection operation Status */
+ return status;
+}
+
+/**
+ * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
+ * @note This function can be used for N32G43x devices.
+ * @param OB_IWDG Selects the IWDG mode
+ * This parameter can be one of the following values:
+ * @arg OB_IWDG_SW Software IWDG selected
+ * @arg OB_IWDG_HW Hardware IWDG selected
+ * @param OB_STOP2 Reset event when entering STOP2 mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STOP2_NORST No reset generated when entering in STOP2
+ * @arg OB_STOP2_RST Reset generated when entering in STOP2
+ * @param OB_STDBY Reset event when entering Standby mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STDBY_NORST No reset generated when entering in STANDBY
+ * @arg OB_STDBY_RST Reset generated when entering in STANDBY
+ * @param OB_PD Reset event when entering PowerDown mode.
+ * This parameter can be one of the following values:
+ * @arg OB_PD_NORST No reset generated when entering in PowerDown
+ * @arg OB_PD_RST Reset generated when entering in PowerDown
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ConfigUserOB(uint8_t OB_IWDG, uint8_t OB_STOP2, uint8_t OB_STDBY, uint8_t OB_PD)
+{
+ uint32_t rdpuser_tmp = RDP_USER_Key;
+
+ FLASH_STS status = FLASH_COMPL;
+
+ /* Check the parameters */
+ assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
+ assert_param(IS_OB_STOP2_SOURCE(OB_STOP2));
+ assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
+ assert_param(IS_OB_PD_SOURCE(OB_PD));
+
+ /* Get the actual read protection L2 Option Byte value */
+ if (FLASH_GetReadOutProtectionL2STS() != RESET)
+ {
+ status = FLASH_ERR_RDP2;
+ return status;
+ }
+
+ /* Get the actual read protection Option Byte value */
+ if (FLASH_GetReadOutProtectionSTS() != RESET)
+ {
+ rdpuser_tmp = 0xFFF00000;
+ }
+
+ /* Authorize the small information block programming */
+ FLASH->OPTKEY = FLASH_KEY1;
+ FLASH->OPTKEY = FLASH_KEY2;
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* if the previous operation is completed, proceed to erase the option bytes */
+ FLASH->CTRL |= CTRL_Set_OPTER;
+ FLASH->CTRL |= CTRL_Set_START;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* if the erase operation is completed, disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CTRL |= CTRL_Set_OPTPG;
+ /* Restore the last read protection Option Byte value */
+ OBT->USER_RDP =
+ (uint32_t)rdpuser_tmp
+ | (((uint32_t)(OB_IWDG | OB_STOP2 | OB_STDBY | OB_PD)) << 16);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTPG;
+ }
+ }
+ else
+ {
+ if (status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+ }
+ }
+ }
+
+ /* Return the Option Byte program Status */
+ return status;
+}
+
+/**
+ * @brief Programs the FLASH User Option Byte: nBOOT0 / nBOOT1 / nSWBOOT0 / BOR_LEV[2:0].
+ * @note This function can be used for N32G43x devices.
+ * @param OB2_nBOOT0
+ * This parameter can be one of the following values:
+ * @arg OB2_NBOOT0_SET Set nBOOT0
+ * @arg OB2_NBOOT0_CLR Clear nBOOT0
+ * @param OB2_nBOOT1
+ * This parameter can be one of the following values:
+ * @arg OB2_NBOOT1_SET Set nBOOT1
+ * @arg OB2_NBOOT1_CLR Clear nBOOT1
+ * @param OB2_nSWBOOT0
+ * This parameter can be one of the following values:
+ * @arg OB2_NSWBOOT0_SET Set nSWBOOT0
+ * @arg OB2_NSWBOOT0_CLR Clear nSWBOOT0
+* @param OB2_BOR_LEV[2:0]
+ * This parameter can be one of the following values:
+ * @arg OB2_BOR_LEV0
+ * @arg OB2_BOR_LEV1
+ * @arg OB2_BOR_LEV2
+ * @arg OB2_BOR_LEV3
+ * @arg OB2_BOR_LEV4
+ * @arg OB2_BOR_LEV5
+ * @arg OB2_BOR_LEV6
+ * @arg OB2_BOR_LEV7
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ConfigUserOB2(uint8_t OB2_nBOOT0, uint8_t OB2_nBOOT1,
+ uint8_t OB2_nSWBOOT0, uint8_t OB2_BOR_LEV)
+{
+ uint32_t rdpuser_tmp = (RDP_USER_Key | FLASH_USER_USER);
+ uint32_t rdp2user2_tmp = 0xFF00FFFF;
+
+ FLASH_STS status = FLASH_COMPL;
+
+ /* Check the parameters */
+ assert_param(IS_OB2_NBOOT0_SOURCE(OB2_nBOOT0));
+ assert_param(IS_OB2_NBOOT1_SOURCE(OB2_nBOOT1));
+ assert_param(IS_OB2_NSWBOOT0_SOURCE(OB2_nSWBOOT0));
+ assert_param(IS_OB2_BOR_LEV_SOURCE(OB2_BOR_LEV));
+
+ /* Get the actual read protection L2 Option Byte value */
+ if (FLASH_GetReadOutProtectionL2STS() != RESET)
+ {
+ status = FLASH_ERR_RDP2;
+ return status;
+ }
+
+ /* Get the actual read protection Option Byte value */
+ if (FLASH_GetReadOutProtectionSTS() != RESET)
+ {
+ rdpuser_tmp = 0xFFFF0000;
+ }
+
+ /* Authorize the small information block programming */
+ FLASH->OPTKEY = FLASH_KEY1;
+ FLASH->OPTKEY = FLASH_KEY2;
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* if the previous operation is completed, proceed to erase the option bytes */
+ FLASH->CTRL |= CTRL_Set_OPTER;
+ FLASH->CTRL |= CTRL_Set_START;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* if the erase operation is completed, disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CTRL |= CTRL_Set_OPTPG;
+
+ /* Restore the last RDP1 Option Byte value */
+ OBT->USER_RDP = (uint32_t)rdpuser_tmp;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* Restore the last RDP2 Option Byte value */
+ OBT->USER2_RDP2 = (uint32_t)rdp2user2_tmp | (((uint32_t)(OB2_nBOOT0) | (uint32_t)(OB2_nBOOT1) \
+ | (uint32_t)(OB2_nSWBOOT0) | (uint32_t)(OB2_BOR_LEV)) << 16);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+ }
+
+ if (status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTPG;
+ }
+ }
+ else
+ {
+ if (status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+ }
+ }
+ }
+
+ /* Return the Option Byte program Status */
+ return status;
+}
+
+/**
+ * @brief Returns the FLASH User Option Bytes values.
+ * @note This function can be used for N32G43x devices.
+ * @return The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
+ * and RST_STDBY(Bit2).
+ */
+uint32_t FLASH_GetUserOB(void)
+{
+ /* Return the User Option Byte */
+ return (uint32_t)(FLASH->OB >> 2);
+}
+
+/**
+ * @brief Returns the FLASH Write Protection Option Bytes Register value.
+ * @note This function can be used for N32G43x devices.
+ * @return The FLASH Write Protection Option Bytes Register value
+ */
+uint32_t FLASH_GetWriteProtectionOB(void)
+{
+ /* Return the Flash write protection Register value */
+ return (uint32_t)(FLASH->WRP);
+}
+
+/**
+ * @brief Checks whether the FLASH Read Out Protection Status is set or not.
+ * @note This function can be used for N32G43x devices.
+ * @return FLASH ReadOut Protection Status(SET or RESET)
+ */
+FlagStatus FLASH_GetReadOutProtectionSTS(void)
+{
+ FlagStatus readoutstatus = RESET;
+ if ((FLASH->OB & RDPRTL1_MSK) != (uint32_t)RESET)
+ {
+ readoutstatus = SET;
+ }
+ else
+ {
+ readoutstatus = RESET;
+ }
+ return readoutstatus;
+}
+
+/**
+ * @brief Checks whether the FLASH Read Out Protection L2 Status is set or not.
+ * @note This function can be used for N32G43x devices.
+ * @return FLASH ReadOut Protection L2 Status(SET or RESET)
+ */
+FlagStatus FLASH_GetReadOutProtectionL2STS(void)
+{
+ FlagStatus readoutstatus = RESET;
+ if ((FLASH->OB & RDPRTL2_MSK) != (uint32_t)RESET)
+ {
+ readoutstatus = SET;
+ }
+ else
+ {
+ readoutstatus = RESET;
+ }
+ return readoutstatus;
+}
+
+/**
+ * @brief Checks whether the FLASH Prefetch Buffer status is set or not.
+ * @note This function can be used for N32G43x devices.
+ * @return FLASH Prefetch Buffer Status (SET or RESET).
+ */
+FlagStatus FLASH_GetPrefetchBufSTS(void)
+{
+ FlagStatus bitstatus = RESET;
+
+ if ((FLASH->AC & AC_PRFTBS_MSK) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */
+ return bitstatus;
+}
+
+/**
+ * @brief Checks whether the FLASH SMPSEL is SMP1 or SMP2.
+ * @note This function can be used for N32G43x devices.
+ * @return FLASH SMPSEL (FLASH_SMP1 or FLASH_SMP2).
+ */
+FLASH_SMPSEL FLASH_GetSMPSELStatus(void)
+{
+ FLASH_SMPSEL bitstatus = FLASH_SMP1;
+
+ if ((FLASH->CTRL & CTRL_Reset_SMPSEL) != (uint32_t)FLASH_SMP1)
+ {
+ bitstatus = FLASH_SMP2;
+ }
+ else
+ {
+ bitstatus = FLASH_SMP1;
+ }
+ /* Return the new state of FLASH SMPSEL (FLASH_SMP1 or FLASH_SMP2) */
+ return bitstatus;
+}
+
+/**
+ * @brief Enables or disables the specified FLASH interrupts.
+ * @note This function can be used for N32G43x devices.
+ * @param FLASH_INT specifies the FLASH interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_ERROR FLASH Error Interrupt
+ * @arg FLASH_INT_FERR EVERR PVERR Interrupt
+ * @arg FLASH_INT_EOP FLASH end of operation Interrupt
+ * @param Cmd new state of the specified Flash interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void FLASH_INTConfig(uint32_t FLASH_INT, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_INT(FLASH_INT));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the interrupt sources */
+ FLASH->CTRL |= FLASH_INT;
+ }
+ else
+ {
+ /* Disable the interrupt sources */
+ FLASH->CTRL &= ~(uint32_t)FLASH_INT;
+ }
+}
+
+/**
+ * @brief Checks whether the specified FLASH flag is set or not.
+ * @note This function can be used for N32G43x devices.
+ * @param FLASH_FLAG specifies the FLASH flag to check.
+ * This parameter can be one of the following values:
+ * @arg FLASH_FLAG_BUSY FLASH Busy flag
+ * @arg FLASH_FLAG_PGERR FLASH Program error flag
+ * @arg FLASH_FLAG_PVERR FLASH Program Verify ERROR flag
+ * @arg FLASH_FLAG_WRPERR FLASH Write protected error flag
+ * @arg FLASH_FLAG_EOP FLASH End of Operation flag
+ * @arg FLASH_FLAG_EVERR FLASH Erase Verify ERROR flag
+ * @arg FLASH_FLAG_OBERR FLASH Option Byte error flag
+ * @return The new state of FLASH_FLAG (SET or RESET).
+ */
+FlagStatus FLASH_GetFlagSTS(uint32_t FLASH_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));
+ if (FLASH_FLAG == FLASH_FLAG_OBERR)
+ {
+ if ((FLASH->OB & FLASH_FLAG_OBERR) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+ else
+ {
+ if ((FLASH->STS & FLASH_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+
+ /* Return the new state of FLASH_FLAG (SET or RESET) */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the FLASH's pending flags.
+ * @note This function can be used for N32G43x devices.
+ * @param FLASH_FLAG specifies the FLASH flags to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_FLAG_PGERR FLASH Program error flag
+ * @arg FLASH_FLAG_PVERR FLASH Program Verify ERROR flag
+ * @arg FLASH_FLAG_WRPERR FLASH Write protected error flag
+ * @arg FLASH_FLAG_EOP FLASH End of Operation flag
+ * @arg FLASH_FLAG_EVERR FLASH Erase Verify ERROR flag
+ */
+void FLASH_ClearFlag(uint32_t FLASH_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));
+
+ /* Clear the flags */
+ FLASH->STS |= FLASH_FLAG;
+}
+
+/**
+ * @brief Returns the FLASH Status.
+ * @note This function can be used for N32G43x devices, it is equivalent
+ * to FLASH_GetBank1Status function.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_GetSTS(void)
+{
+ FLASH_STS flashstatus = FLASH_COMPL;
+
+ if ((FLASH->STS & FLASH_FLAG_BUSY) == FLASH_FLAG_BUSY)
+ {
+ flashstatus = FLASH_BUSY;
+ }
+ else
+ {
+ if ((FLASH->STS & FLASH_FLAG_PGERR) != 0)
+ {
+ flashstatus = FLASH_ERR_PG;
+ }
+ else
+ {
+ if ((FLASH->STS & FLASH_FLAG_PVERR) != 0)
+ {
+ flashstatus = FLASH_ERR_PV;
+ }
+ else
+ {
+ if ((FLASH->STS & FLASH_FLAG_WRPERR) != 0)
+ {
+ flashstatus = FLASH_ERR_WRP;
+ }
+ else
+ {
+ if ((FLASH->STS & FLASH_FLAG_EVERR) != 0)
+ {
+ flashstatus = FLASH_ERR_EV;
+ }
+ else
+ {
+ flashstatus = FLASH_COMPL;
+ }
+ }
+ }
+ }
+ }
+
+ /* Return the Flash Status */
+ return flashstatus;
+}
+
+/**
+ * @brief Waits for a Flash operation to complete or a TIMEOUT to occur.
+ * @note This function can be used for N32G43x devices,
+ * it is equivalent to FLASH_WaitForLastBank1Operation..
+ * @param Timeout FLASH programming Timeout
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_WaitForLastOpt(uint32_t Timeout)
+{
+ FLASH_STS status = FLASH_COMPL;
+
+ /* Check for the Flash Status */
+ status = FLASH_GetSTS();
+ /* Wait for a Flash operation to complete or a TIMEOUT to occur */
+ while ((status == FLASH_BUSY) && (Timeout != 0x00))
+ {
+ status = FLASH_GetSTS();
+ Timeout--;
+ }
+ if (Timeout == 0x00)
+ {
+ status = FLASH_TIMEOUT;
+ }
+ /* Return the operation status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_gpio.c b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_gpio.c
new file mode 100644
index 0000000000..e9dc0bcd78
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_gpio.c
@@ -0,0 +1,768 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_gpio.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_gpio.h"
+#include "n32g43x_rcc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @brief GPIO driver modules
+ * @{
+ */
+
+/** @addtogroup GPIO_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Private_Defines
+ * @{
+ */
+
+/* ------------ RCC registers bit address in the alias region ----------------*/
+#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)
+
+/* --- Event control register -----*/
+
+/* Alias word address of EVOE bit */
+#define EVCR_OFFSET (AFIO_OFFSET + 0x00)
+#define EVOE_BitNumber ((uint8_t)0x07)
+#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
+
+
+#define GPIO_MODE ((uint32_t)0x00000003)
+#define EXTI_MODE ((uint32_t)0x10000000)
+#define GPIO_MODE_IT ((uint32_t)0x00010000)
+#define GPIO_MODE_EVT ((uint32_t)0x00020000)
+#define RISING_EDGE ((uint32_t)0x00100000)
+#define FALLING_EDGE ((uint32_t)0x00200000)
+#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
+#define GPIO_PULLUP_PULLDOWN ((uint32_t)0x00000300)
+#define GPIO_NUMBER ((uint32_t)16)
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the GPIOx peripheral registers to their default reset values.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ */
+void GPIO_DeInit(GPIO_Module* GPIOx)
+{
+
+ uint32_t position = 0x00U;
+ uint32_t iocurrent = 0x00U;
+ uint32_t tmp = 0x00U;
+ uint32_t GPIO_Pin = GPIO_PIN_ALL;
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin));
+
+ if (GPIOx == GPIOA)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOA, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOA, DISABLE);
+ }
+ else if (GPIOx == GPIOB)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOB, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOB, DISABLE);
+ }
+ else if (GPIOx == GPIOC)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOC, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOC, DISABLE);
+ }
+ else if (GPIOx == GPIOD)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOD, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOD, DISABLE);
+ }
+ else
+ {
+ return;
+ }
+
+ /* Configure the port pins */
+ while ((GPIO_Pin >> position) != 0)
+ {
+ /* Get the IO position */
+ iocurrent = (GPIO_Pin) & ((uint32_t)0x01 << position);
+
+ if (iocurrent)
+ {
+ /*------------------------- EXTI Mode Configuration --------------------*/
+ /* Clear the External Interrupt or Event for the current IO */
+ tmp = AFIO->EXTI_CFG[position>>2];
+ tmp &= (0x0FuL << (4u*(position & 0x03u)));
+ if (tmp == (GPIO_GET_INDEX(GPIOx)<<(4u * (position & 0x03u))))
+ {
+ /* Clear EXTI line configuration */
+ EXTI->IMASK &= ~(iocurrent);
+ EXTI->EMASK &= ~(iocurrent);
+
+ /* Clear Rising Falling edge configuration */
+ EXTI->RT_CFG &= ~(iocurrent);
+ EXTI->FT_CFG &= ~(iocurrent);
+ tmp = 0x0FuL << (4u * (position & 0x03u));
+ AFIO->EXTI_CFG[position >> 2u] &= ~tmp;
+ }
+
+
+ /*------------------------- GPIO Mode Configuration --------------------*/
+ /* Configure IO Direction in Input Floting Mode */
+ GPIOx->PMODE &= ~(GPIO_PMODE0_Msk << (position * 2U));
+
+ /* Configure the default Alternate Function in current IO */
+ if (position & 0x08)
+ GPIOx->AFH |= ((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4U));
+ else
+ GPIOx->AFL |= ((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4U));
+
+ /* Configure the default value IO Output Type */
+ GPIOx->POTYPE &= ~(GPIO_POTYPE_POT_0 << position) ;
+
+ /* Deactivate the Pull-up oand Pull-down resistor for the current IO */
+ GPIOx->PUPD &= ~(GPIO_PUPD0_Msk << (position * 2U));
+
+ }
+ position++;
+ }
+}
+
+
+/**
+ * @brief Deinitializes the Alternate Functions (remap, event control
+ * and EXTI configuration) registers to their default reset values.
+ */
+void GPIO_AFIOInitDefault(void)
+{
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_AFIO, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_AFIO, DISABLE);
+}
+
+/**
+ * @brief Initializes the GPIOx peripheral according to the specified
+ * parameters in the GPIO_InitStruct.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param GPIO_InitStruct pointer to a GPIO_InitType structure that
+ * contains the configuration information for the specified GPIO peripheral.
+ */
+
+void GPIO_InitPeripheral(GPIO_Module* GPIOx, GPIO_InitType * GPIO_InitStruct)
+{
+ uint32_t pinpos = 0x00U;
+ uint32_t tmp = 0x00U,tmpregister=0x00U;
+ uint32_t position = 0x00U;
+ uint32_t iocurrent = 0x00U;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
+ assert_param(IS_GPIO_PIN(GPIO_InitStruct->Pin));
+ assert_param(IS_GPIO_PULL(GPIO_InitStruct->GPIO_Pull));
+ assert_param(IS_GPIO_SLEW_RATE(GPIO_InitStruct->GPIO_Slew_Rate));
+
+ /*---------------------------- GPIO Mode Configuration -----------------------*/
+
+ /*---------------------------- GPIO PL_CFG Configuration ------------------------*/
+
+ while (((GPIO_InitStruct->Pin)>>position) != 0)
+ {
+ iocurrent = (GPIO_InitStruct->Pin)&(1U<GPIO_Mode == GPIO_Mode_AF_PP) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF_OD) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_Input) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_Analog))
+ {
+ /* Check if the Alternate function is compliant with the GPIO in use */
+ assert_param(IS_GPIO_AF(GPIO_InitStruct->GPIO_Alternate));
+ /* Configure Alternate function mapped with the current IO */
+ if (position & 0x08)
+ {
+ tmp = GPIOx->AFH;
+ tmp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4U));
+ tmp |= ((uint32_t)(GPIO_InitStruct->GPIO_Alternate) << ((uint32_t)(position & (uint32_t)0x07) * 4U)) ;
+ GPIOx->AFH = tmp;
+ }
+ else
+ {
+ tmp = GPIOx->AFL;
+ tmp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4U)) ;
+ tmp |= ((uint32_t)(GPIO_InitStruct->GPIO_Alternate) << ((uint32_t)(position & (uint32_t)0x07) * 4U)) ;
+ GPIOx->AFL = tmp;
+ }
+ }
+ /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+ tmpregister = GPIOx->PMODE;
+ tmp = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
+ tmpregister &= ~(((uint32_t)0x03) << pinpos);
+ tmpregister |=( tmp << pinpos);
+ GPIOx->PMODE = tmpregister;
+
+ /* Configure pull-down mode */
+ tmpregister = GPIOx->PUPD;
+ tmp = (GPIO_InitStruct->GPIO_Pull & (uint32_t)0x03);
+ tmpregister &=~(((uint32_t)0x03) << pinpos);
+ tmpregister |= (tmp <PUPD = tmpregister;
+
+
+ /* Configure driver current*/
+ if ((GPIO_InitStruct->GPIO_Mode & GPIO_MODE) && (GPIO_InitStruct->GPIO_Mode != GPIO_Mode_Analog))
+ {
+ assert_param(IS_GPIO_CURRENT(GPIO_InitStruct->GPIO_Current));
+ tmpregister = GPIOx->DS;
+ tmp = (GPIO_InitStruct->GPIO_Current &((uint32_t)0x03));
+ tmpregister &= ~(((uint32_t)0x03) << pinpos);
+ tmpregister |= (tmp<DS = tmpregister;
+ }
+ /* Configure slew rate*/
+ tmp = GPIOx->SR;
+ tmp &=((uint32_t)(~((uint16_t)0x01 << position)));
+ tmp |= (GPIO_InitStruct->GPIO_Slew_Rate &((uint32_t)0x01))<SR = tmp;
+ /*Configure Set/Reset register*/
+ if (GPIO_InitStruct->GPIO_Pull == GPIO_Pull_Down)
+ {
+ GPIOx->PBC |= (((uint32_t)0x01) << position);
+ }
+ else
+ {
+ /* Set the corresponding POD bit */
+ if (GPIO_InitStruct->GPIO_Pull == GPIO_Pull_Up)
+ {
+ GPIOx->PBSC |= (((uint32_t)0x01) << position);
+ }
+ }
+
+ /* In case of Output or Alternate function mode selection */
+ if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_Out_PP) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF_PP) ||
+ (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_Out_OD) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF_OD))
+ {
+ /* Configure the IO Output Type */
+
+ tmp= GPIOx->POTYPE;
+ tmp &= ~(((uint32_t)0x01U) << position) ;
+ tmp |= (((GPIO_InitStruct->GPIO_Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
+ GPIOx->POTYPE = tmp;
+ }
+ /*--------------------- EXTI Mode Configuration ------------------------*/
+ /* Configure the External Interrupt or event for the current IO */
+ if (GPIO_InitStruct->GPIO_Mode & EXTI_MODE)
+ {
+ /* Clear EXTI line configuration */
+ tmp = EXTI->IMASK;
+ tmp &= ~((uint32_t)0x01<GPIO_Mode & GPIO_MODE_IT)== GPIO_MODE_IT)
+ {
+ tmp |= ((uint32_t)0x01 << position);
+ }
+ EXTI->IMASK = tmp;
+
+ tmp = EXTI->EMASK;
+ tmp &= ~((uint32_t)0x01<GPIO_Mode & GPIO_MODE_EVT)== GPIO_MODE_EVT)
+ {
+ tmp |= ((uint32_t)0x01 << position);
+ }
+ EXTI->EMASK = tmp;
+
+ /* Clear Rising Falling edge configuration */
+
+ tmp = EXTI->RT_CFG;
+ tmp &= ~((uint32_t)0x01<GPIO_Mode & RISING_EDGE)== RISING_EDGE)
+ {
+ tmp |= ((uint32_t)0x01 << position);
+ }
+ EXTI->RT_CFG = tmp;
+
+ tmp = EXTI->FT_CFG;
+ tmp &= ~((uint32_t)0x01<GPIO_Mode & FALLING_EDGE)== FALLING_EDGE)
+ {
+ tmp |= ((uint32_t)0x01 << position);
+ }
+ EXTI->FT_CFG = tmp;
+ }
+ }
+ position++;
+ }
+}
+
+/**
+ * @brief Fills each GPIO_InitStruct member with its default value.
+ * @param GPIO_InitStruct pointer to a GPIO_InitType structure which will
+ * be initialized.
+ */
+void GPIO_InitStruct(GPIO_InitType* GPIO_InitStruct)
+{
+ /* Reset GPIO init structure parameters values */
+ GPIO_InitStruct->Pin = GPIO_PIN_ALL;
+ GPIO_InitStruct->GPIO_Slew_Rate = GPIO_Slew_Rate_High;
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_Input;
+ GPIO_InitStruct->GPIO_Alternate = GPIO_NO_AF;
+ GPIO_InitStruct->GPIO_Pull = GPIO_No_Pull;
+ GPIO_InitStruct->GPIO_Current = GPIO_DC_2mA;
+}
+
+/**
+ * @brief Reads the specified input port pin.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param Pin specifies the port bit to read.
+ * This parameter can be GPIO_Pin_x where x can be (0..15).
+ * @return The input port pin value.
+ */
+uint8_t GPIO_ReadInputDataBit(GPIO_Module* GPIOx, uint16_t Pin)
+{
+ uint8_t bitstatus = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(Pin));
+
+ if ((GPIOx->PID & Pin) != (uint32_t)Bit_RESET)
+ {
+ bitstatus = (uint8_t)Bit_SET;
+ }
+ else
+ {
+ bitstatus = (uint8_t)Bit_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Reads the specified GPIO input data port.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @return GPIO input data port value.
+ */
+uint16_t GPIO_ReadInputData(GPIO_Module* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ return ((uint16_t)GPIOx->PID);
+}
+
+/**
+ * @brief Reads the specified output data port bit.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param Pin specifies the port bit to read.
+ * This parameter can be GPIO_Pin_x where x can be (0..15).
+ * @return The output port pin value.
+ */
+uint8_t GPIO_ReadOutputDataBit(GPIO_Module* GPIOx, uint16_t Pin)
+{
+ uint8_t bitstatus = 0x00;
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(Pin));
+
+ if ((GPIOx->POD & Pin) != (uint32_t)Bit_RESET)
+ {
+ bitstatus = (uint8_t)Bit_SET;
+ }
+ else
+ {
+ bitstatus = (uint8_t)Bit_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Reads the specified GPIO output data port.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @return GPIO output data port value.
+ */
+uint16_t GPIO_ReadOutputData(GPIO_Module* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ return ((uint16_t)GPIOx->POD);
+}
+
+/**
+ * @brief Sets the selected data port bits.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param Pin specifies the port bits to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ */
+void GPIO_SetBits(GPIO_Module* GPIOx, uint16_t Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(Pin));
+
+ GPIOx->PBSC = Pin;
+}
+void GPIO_SetBitsHigh16(GPIO_Module* GPIOx, uint32_t Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ // assert_param(IS_GPIO_PIN(Pin));
+
+ GPIOx->PBSC = Pin;
+}
+
+/**
+ * @brief Clears the selected data port bits.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param Pin specifies the port bits to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ */
+void GPIO_ResetBits(GPIO_Module* GPIOx, uint16_t Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(Pin));
+
+ GPIOx->PBC = Pin;
+}
+
+/**
+ * @brief Sets or clears the selected data port bit.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param Pin specifies the port bit to be written.
+ * This parameter can be one of GPIO_Pin_x where x can be (0..15).
+ * @param BitCmd specifies the value to be written to the selected bit.
+ * This parameter can be one of the Bit_OperateType enum values:
+ * @arg Bit_RESET to clear the port pin
+ * @arg Bit_SET to set the port pin
+ */
+void GPIO_WriteBit(GPIO_Module* GPIOx, uint16_t Pin, Bit_OperateType BitCmd)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(Pin));
+ assert_param(IS_GPIO_BIT_OPERATE(BitCmd));
+
+ if (BitCmd != Bit_RESET)
+ {
+ GPIOx->PBSC = Pin;
+ }
+ else
+ {
+ GPIOx->PBC = Pin;
+ }
+}
+
+/**
+ * @brief Writes data to the specified GPIO data port.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param PortVal specifies the value to be written to the port output data register.
+ */
+void GPIO_Write(GPIO_Module* GPIOx, uint16_t PortVal)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ GPIOx->POD = PortVal;
+}
+
+/**
+ * @brief Locks GPIO Pins configuration registers.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param Pin specifies the port bit to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ */
+void GPIO_ConfigPinLock(GPIO_Module* GPIOx, uint16_t Pin)
+{
+ uint32_t tmp = 0x00010000;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(Pin));
+
+ tmp |= Pin;
+ /* Set LCKK bit */
+ GPIOx->PLOCK = tmp;
+ /* Reset LCKK bit */
+ GPIOx->PLOCK = Pin;
+ /* Set LCKK bit */
+ GPIOx->PLOCK = tmp;
+ /* Read LCKK bit*/
+ tmp = GPIOx->PLOCK;
+ /* Read LCKK bit*/
+ tmp = GPIOx->PLOCK;
+}
+
+
+
+/**
+ * @brief Changes the mapping of the specified pin.
+ * @param PortSource selects the GPIO port to be used.
+ * @param PinSource specifies the pin for the remaping.
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).
+ * @param AlternateFunction specifies the alternate function for the remaping.
+ */
+void GPIO_ConfigPinRemap(uint8_t PortSource, uint8_t PinSource, uint32_t AlternateFunction)
+{
+ uint32_t tmp = 0x00, tmpregister = 0x00;
+ GPIO_Module *GPIOx;
+ /* Check the parameters */
+ assert_param(IS_GPIO_REMAP_PORT_SOURCE(PortSource));
+ assert_param(IS_GPIO_PIN_SOURCE(PinSource));
+ assert_param(IS_GPIO_AF(AlternateFunction));
+ /*Get Peripheral point*/
+ GPIOx = GPIO_GET_PERIPH(PortSource);
+ /**/
+ if (PinSource & (uint8_t)0x08)
+ {
+ tmp = (uint32_t)(PinSource & (uint8_t)0x07);
+ /*Read GPIO_AFH register*/
+ tmpregister = GPIOx->AFH;
+ /*Reset corresponding bits*/
+ tmpregister &=~((uint32_t)0x0F <<(tmp*4U));
+ /*Set corresponding bits*/
+ tmpregister |= AlternateFunction << (tmp*4U);
+ /*Write to the GPIO_AFH register*/
+ GPIOx->AFH = tmpregister;
+ }
+ else
+ {
+ tmp = (uint32_t)(PinSource & (uint8_t)0x07);
+ /*Read GPIO_AFL register*/
+ tmpregister = GPIOx->AFL;
+ /*Reset corresponding bits*/
+ tmpregister &=~((uint32_t)0x0F <<(tmp*4U));
+ /*Set corresponding bits*/
+ tmpregister |= AlternateFunction << (tmp*4U);
+ /*Write to the GPIO_AFL register*/
+ GPIOx->AFL = tmpregister;
+ }
+}
+
+/**
+ * @brief Selects the GPIO pin used as Event output.
+ * @param PortSource selects the GPIO port to be used as source
+ * for Event output.
+ * This parameter can be GPIO_PortSourceGPIOx where x can be (A..D).
+ * @param PinSource specifies the pin for the Event output.
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).
+ */
+void GPIO_ConfigEventOutput(uint8_t PortSource, uint8_t PinSource)
+{
+ uint32_t tmpregister = 0x00,tmp = 0x00;
+ GPIO_Module *GPIOx;
+ /* Check the parameters */
+ assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(PortSource));
+ assert_param(IS_GPIO_PIN_SOURCE(PinSource));
+
+ /*Get Peripheral structure point*/
+ GPIOx = GPIO_GET_PERIPH(PortSource);
+ if (PinSource & (uint8_t)0x08)
+ {
+ tmp = (uint32_t)(PinSource & (uint8_t)0x07);
+ /*Read GPIO_AFH register*/
+ tmpregister = GPIOx->AFH;
+ /*Reset corresponding bits*/
+ tmpregister &=~((uint32_t)0x0F <<(tmp*4U));
+ /*Set corresponding bits*/
+ tmpregister |= GPIO_AF3_EVENTOUT;
+ /*Write to the GPIO_AFH register*/
+ GPIOx->AFH = tmpregister;
+ }
+ else
+ {
+ tmp = (uint32_t)(PinSource & (uint8_t)0x07);
+ /*Read GPIO_AFL register*/
+ tmpregister = GPIOx->AFL;
+ /*Reset corresponding bits*/
+ tmpregister &=~((uint32_t)0x0F <<(tmp*4U));
+ /*Set corresponding bits*/
+ tmpregister |= GPIO_AF3_EVENTOUT;
+ /*Write to the GPIO_AFL register*/
+ GPIOx->AFL = tmpregister;
+ }
+}
+
+/**
+ * @brief Enables or disables the Event Output.
+ * @param Cmd new state of the Event output.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void GPIO_CtrlEventOutput(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ *(__IO uint32_t*)EVCR_EVOE_BB = (uint32_t)Cmd;
+}
+
+
+/**
+ * @brief Selects the GPIO pin used as EXTI Line.
+ * @param PortSource selects the GPIO port to be used as source for EXTI lines.
+ * This parameter can be GPIO_PortSourceGPIOx where x can be (A..D).
+ * @param PinSource specifies the EXTI line to be configured.
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).
+ */
+void GPIO_ConfigEXTILine(uint8_t PortSource, uint8_t PinSource)
+{
+ uint32_t port = (uint32_t)PortSource;
+ /* Check the parameters */
+ assert_param(IS_GPIO_EXTI_PORT_SOURCE(PortSource));
+ assert_param(IS_GPIO_PIN_SOURCE(PinSource));
+
+ AFIO->EXTI_CFG[(PinSource >> 0x02)] &= ~(((uint32_t)0x03) << ((PinSource & (uint8_t)0x03)*4u));
+ AFIO->EXTI_CFG[(PinSource >> 0x02)] |= (port << ((PinSource & (uint8_t)0x03) *4u));
+}
+
+/**
+ * @brief Selects the alternate function SPIx NSS mode.
+ * @param AFIO_SPIx_NSS choose which SPI configuration.
+ * This parameter can be AFIO_SPI1_NSS and AFIO_SPI2_NSS.
+ * @param SpiNssType specifies the SPI_NSS mode to be configured.
+ * This parameter can be AFIO_SPI1_NSS_High_IMPEDANCE and AFIO_SPI1_NSS_High_LEVEL.
+ */
+void AFIO_ConfigSPINSSMode(uint32_t AFIO_SPIx_NSS,AFIO_SPI_NSSType SpiNssType)
+{
+ uint32_t tmp = 0x00;
+ /* Check the parameters */
+ assert_param(IS_AFIO_SPIX(AFIO_SPIx_NSS));
+ assert_param(IS_AFIO_SPI_NSS(SpiNssType));
+ tmp = AFIO->RMP_CFG;
+ tmp &=(~(0x01U << AFIO_SPIx_NSS));
+ tmp |=(SpiNssType << AFIO_SPIx_NSS);
+ AFIO->RMP_CFG = tmp;
+}
+
+/**
+ * @brief Configurate ADC external trigger.
+ * @param ADCETRType choose whether to configure rule conversion or injection conversion .
+ * This parameter can be AFIO_ADC_ETRI and AFIO_ADC_ETRR.
+ * @param ADCTrigRemap specifies the external trigger line be configured.
+ * This parameter can be AFIO_ADC_TRIG_EXTI_x where x can be (0..15) or AFIO_ADC_TRIG_TIM8_CHy where y can be(3..4).
+ */
+void AFIO_ConfigADCExternalTrigRemap(AFIO_ADC_ETRType ADCETRType,AFIO_ADC_Trig_RemapType ADCTrigRemap)
+{
+ uint32_t tmp = 0x00;
+ /* Check the parameters */
+ assert_param(IS_AFIO_ADC_ETR(ADCETRType));
+ if (ADCETRType == AFIO_ADC_ETRI)
+ {
+ /* Check the parameters */
+ assert_param(IS_AFIO_ADC_ETRI(ADCTrigRemap));
+ tmp = AFIO->RMP_CFG;
+ /* clear AFIO_RMP_CFG register ETRI bit*/
+ tmp &= (~(0x01U << AFIO_ADC_ETRI));
+ /* if ADCETRType is AFIO_ADC_ETRI then ADCTrigRemap cannot be AFIO_ADC_TRIG_TIM8_CH3*/
+ if (ADCTrigRemap == AFIO_ADC_TRIG_TIM8_CH4)
+ {
+ /* select TIM8_CH4 line to connect*/
+ tmp |= (0x01U << AFIO_ADC_ETRI);
+ }
+ else
+ {
+ /* select which external line is connected*/
+ tmp &=(~(0x0FU<<4U));
+ tmp |= (ADCTrigRemap<<4U);
+ }
+ AFIO->RMP_CFG = tmp;
+ }
+ else
+ {
+ if (ADCETRType == AFIO_ADC_ETRR)
+ {
+ /* Check the parameters */
+ assert_param(IS_AFIO_ADC_ETRR(ADCTrigRemap));
+ tmp = AFIO->RMP_CFG;
+ /* clear AFIO_RMP_CFG register ETRR bit*/
+ tmp &= (~(0x01U << AFIO_ADC_ETRR));
+ /* if ADCETRType is AFIO_ADC_ETRR then ADCTrigRemap cannot be AFIO_ADC_TRIG_TIM8_CH4*/
+ if (ADCTrigRemap == AFIO_ADC_TRIG_TIM8_CH3)
+ {
+ /* select TIM8_CH3 line to connect*/
+ tmp |= (0x01U << AFIO_ADC_ETRR);
+ }
+ else
+ {
+ /* select which external line is connected*/
+ tmp &=(~(0x0FU<<0));
+ tmp |= ADCTrigRemap;
+ }
+ AFIO->RMP_CFG = tmp;
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_i2c.c b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_i2c.c
new file mode 100644
index 0000000000..8c756c1981
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_i2c.c
@@ -0,0 +1,1301 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_i2c.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_i2c.h"
+#include "n32g43x_rcc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @brief I2C driver modules
+ * @{
+ */
+
+/** @addtogroup I2C_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_Defines
+ * @{
+ */
+
+/* I2C SPE mask */
+#define CTRL1_SPEN_SET ((uint16_t)0x0001)
+#define CTRL1_SPEN_RESET ((uint16_t)0xFFFE)
+
+/* I2C START mask */
+#define CTRL1_START_SET ((uint16_t)0x0100)
+#define CTRL1_START_RESET ((uint16_t)0xFEFF)
+
+/* I2C STOP mask */
+#define CTRL1_STOP_SET ((uint16_t)0x0200)
+#define CTRL1_STOP_RESET ((uint16_t)0xFDFF)
+
+/* I2C ACK mask */
+#define CTRL1_ACK_SET ((uint16_t)0x0400)
+#define CTRL1_ACK_RESET ((uint16_t)0xFBFF)
+
+/* I2C ENGC mask */
+#define CTRL1_GCEN_SET ((uint16_t)0x0040)
+#define CTRL1_GCEN_RESET ((uint16_t)0xFFBF)
+
+/* I2C SWRST mask */
+#define CTRL1_SWRESET_SET ((uint16_t)0x8000)
+#define CTRL1_SWRESET_RESET ((uint16_t)0x7FFF)
+
+/* I2C PEC mask */
+#define CTRL1_PEC_SET ((uint16_t)0x1000)
+#define CTRL1_PEC_RESET ((uint16_t)0xEFFF)
+
+/* I2C ENPEC mask */
+#define CTRL1_PECEN_SET ((uint16_t)0x0020)
+#define CTRL1_PECEN_RESET ((uint16_t)0xFFDF)
+
+/* I2C ENARP mask */
+#define CTRL1_ARPEN_SET ((uint16_t)0x0010)
+#define CTRL1_ARPEN_RESET ((uint16_t)0xFFEF)
+
+/* I2C NOSTRETCH mask */
+#define CTRL1_NOEXTEND_SET ((uint16_t)0x0080)
+#define CTRL1_NOEXTEND_RESET ((uint16_t)0xFF7F)
+
+/* I2C registers Masks */
+#define CTRL1_CLR_MASK ((uint16_t)0xFBF5)
+
+/* I2C DMAEN mask */
+#define CTRL2_DMAEN_SET ((uint16_t)0x0800)
+#define CTRL2_DMAEN_RESET ((uint16_t)0xF7FF)
+
+/* I2C LAST mask */
+#define CTRL2_DMALAST_SET ((uint16_t)0x1000)
+#define CTRL2_DMALAST_RESET ((uint16_t)0xEFFF)
+
+/* I2C FREQ mask */
+#define CTRL2_CLKFREQ_RESET ((uint16_t)0xFFC0)
+
+/* I2C ADD0 mask */
+#define OADDR1_ADDR0_SET ((uint16_t)0x0001)
+#define OADDR1_ADDR0_RESET ((uint16_t)0xFFFE)
+
+/* I2C ENDUAL mask */
+#define OADDR2_DUALEN_SET ((uint16_t)0x0001)
+#define OADDR2_DUALEN_RESET ((uint16_t)0xFFFE)
+
+/* I2C ADD2 mask */
+#define OADDR2_ADDR2_RESET ((uint16_t)0xFF01)
+
+/* I2C F/S mask */
+#define CLKCTRL_FSMODE_SET ((uint16_t)0x8000)
+
+/* I2C CHCFG mask */
+#define CLKCTRL_CLKCTRL_SET ((uint16_t)0x0FFF)
+
+/* I2C FLAG mask */
+#define FLAG_MASK ((uint32_t)0x00FFFFFF)
+
+/* I2C Interrupt Enable mask */
+#define INTEN_MASK ((uint32_t)0x07000000)
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the I2Cx peripheral registers to their default reset values.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ */
+void I2C_DeInit(I2C_Module* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+
+ if (I2Cx == I2C1)
+ {
+ /* Enable I2C1 reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C1, ENABLE);
+ /* Release I2C1 from reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C1, DISABLE);
+ }
+ else
+ {
+ /* Enable I2C2 reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C2, ENABLE);
+ /* Release I2C2 from reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C2, DISABLE);
+ }
+}
+
+/**
+ * @brief Initializes the I2Cx peripheral according to the specified
+ * parameters in the I2C_InitStruct.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_InitStruct pointer to a I2C_InitType structure that
+ * contains the configuration information for the specified I2C peripheral.
+ */
+void I2C_Init(I2C_Module* I2Cx, I2C_InitType* I2C_InitStruct)
+{
+ uint16_t tmpregister = 0, freqrange = 0;
+ uint16_t result = 0x04;
+ uint32_t pclk1 = 8000000;
+ RCC_ClocksType rcc_clocks;
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_CLK_SPEED(I2C_InitStruct->ClkSpeed));
+ assert_param(IS_I2C_BUS_MODE(I2C_InitStruct->BusMode));
+ assert_param(IS_I2C_FM_DUTY_CYCLE(I2C_InitStruct->FmDutyCycle));
+ assert_param(IS_I2C_OWN_ADDR1(I2C_InitStruct->OwnAddr1));
+ assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->AckEnable));
+ assert_param(IS_I2C_ADDR_MODE(I2C_InitStruct->AddrMode));
+
+ /*---------------------------- I2Cx CTRL2 Configuration ------------------------*/
+ /* Get the I2Cx CTRL2 value */
+ tmpregister = I2Cx->CTRL2;
+ /* Clear frequency FREQ[5:0] bits */
+ tmpregister &= CTRL2_CLKFREQ_RESET;
+ /* Get pclk1 frequency value */
+ RCC_GetClocksFreqValue(&rcc_clocks);
+ pclk1 = rcc_clocks.Pclk1Freq;
+ /* Set frequency bits depending on pclk1 value */
+ freqrange = (uint16_t)(pclk1 / 1000000);
+ tmpregister |= freqrange;
+ /* Write to I2Cx CTRL2 */
+ I2Cx->CTRL2 = tmpregister;
+
+ /*---------------------------- I2Cx CHCFG Configuration ------------------------*/
+ /* Disable the selected I2C peripheral to configure TMRISE */
+ I2Cx->CTRL1 &= CTRL1_SPEN_RESET;
+ /* Reset tmpregister value */
+ /* Clear F/S, DUTY and CHCFG[11:0] bits */
+ tmpregister = 0;
+
+ /* Configure speed in standard mode */
+ if (I2C_InitStruct->ClkSpeed <= 100000)
+ {
+ /* Standard mode speed calculate */
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->ClkSpeed << 1));
+ /* Test if CHCFG value is under 0x4*/
+ if (result < 0x04)
+ {
+ /* Set minimum allowed value */
+ result = 0x04;
+ }
+ /* Set speed value for standard mode */
+ tmpregister |= result;
+ /* Set Maximum Rise Time for standard mode */
+ I2Cx->TMRISE = freqrange + 1;
+ }
+ /* Configure speed in fast mode */
+ // else if ((I2C_InitStruct->ClkSpeed > 100000)&&(I2C_InitStruct->ClkSpeed <= 400000))/*(I2C_InitStruct->ClkSpeed <=
+ // 400000)*/
+ else
+ {
+ if (I2C_InitStruct->FmDutyCycle == I2C_FMDUTYCYCLE_2)
+ {
+ /* Fast mode speed calculate: Tlow/Thigh = 2 */
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->ClkSpeed * 3));
+ }
+ else /*I2C_InitStruct->FmDutyCycle == I2C_FMDUTYCYCLE_16_9*/
+ {
+ /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->ClkSpeed * 25));
+ /* Set DUTY bit */
+ result |= I2C_FMDUTYCYCLE_16_9;
+ }
+
+ /* Test if CHCFG value is under 0x1*/
+ if ((result & CLKCTRL_CLKCTRL_SET) == 0)
+ {
+ /* Set minimum allowed value */
+ result |= (uint16_t)0x0001;
+ }
+ /* Set speed value and set F/S bit for fast mode */
+ tmpregister |= (uint16_t)(result | CLKCTRL_FSMODE_SET);
+ /* Set Maximum Rise Time for fast mode */
+ // if (I2C_InitStruct->ClkSpeed <= 400000)
+ {
+ I2Cx->TMRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
+ }
+ // else//add test
+ //{
+ // I2Cx->TMRISE = (uint16_t)(((freqrange * (uint16_t)100) / (uint16_t)1000) + (uint16_t)1);
+ //}
+ }
+ /* Write to I2Cx CHCFG */
+ I2Cx->CLKCTRL = tmpregister;
+ /* Enable the selected I2C peripheral */
+ I2Cx->CTRL1 |= CTRL1_SPEN_SET;
+
+ /*---------------------------- I2Cx CTRL1 Configuration ------------------------*/
+ /* Get the I2Cx CTRL1 value */
+ tmpregister = I2Cx->CTRL1;
+ /* Clear ACK, SMBTYPE and SMBUS bits */
+ tmpregister &= CTRL1_CLR_MASK;
+ /* Configure I2Cx: mode and acknowledgement */
+ /* Set SMBTYPE and SMBUS bits according to BusMode value */
+ /* Set ACK bit according to AckEnable value */
+ tmpregister |= (uint16_t)((uint32_t)I2C_InitStruct->BusMode | I2C_InitStruct->AckEnable);
+ /* Write to I2Cx CTRL1 */
+ I2Cx->CTRL1 = tmpregister;
+
+ /*---------------------------- I2Cx OADDR1 Configuration -----------------------*/
+ /* Set I2Cx Own Address1 and acknowledged address */
+ I2Cx->OADDR1 = (I2C_InitStruct->AddrMode | I2C_InitStruct->OwnAddr1);
+}
+
+/**
+ * @brief Fills each I2C_InitStruct member with its default value.
+ * @param I2C_InitStruct pointer to an I2C_InitType structure which will be initialized.
+ */
+void I2C_InitStruct(I2C_InitType* I2C_InitStruct)
+{
+ /*---------------- Reset I2C init structure parameters values ----------------*/
+ /* initialize the ClkSpeed member */
+ I2C_InitStruct->ClkSpeed = 5000;
+ /* Initialize the BusMode member */
+ I2C_InitStruct->BusMode = I2C_BUSMODE_I2C;
+ /* Initialize the FmDutyCycle member */
+ I2C_InitStruct->FmDutyCycle = I2C_FMDUTYCYCLE_2;
+ /* Initialize the OwnAddr1 member */
+ I2C_InitStruct->OwnAddr1 = 0;
+ /* Initialize the AckEnable member */
+ I2C_InitStruct->AckEnable = I2C_ACKDIS;
+ /* Initialize the AddrMode member */
+ I2C_InitStruct->AddrMode = I2C_ADDR_MODE_7BIT;
+}
+
+/**
+ * @brief Enables or disables the specified I2C peripheral.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2Cx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_Enable(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected I2C peripheral */
+ I2Cx->CTRL1 |= CTRL1_SPEN_SET;
+ }
+ else
+ {
+ /* Disable the selected I2C peripheral */
+ I2Cx->CTRL1 &= CTRL1_SPEN_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C DMA requests.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C DMA transfer.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableDMA(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected I2C DMA requests */
+ I2Cx->CTRL2 |= CTRL2_DMAEN_SET;
+ }
+ else
+ {
+ /* Disable the selected I2C DMA requests */
+ I2Cx->CTRL2 &= CTRL2_DMAEN_RESET;
+ }
+}
+
+/**
+ * @brief Specifies if the next DMA transfer will be the last one.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C DMA last transfer.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableDmaLastSend(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Next DMA transfer is the last transfer */
+ I2Cx->CTRL2 |= CTRL2_DMALAST_SET;
+ }
+ else
+ {
+ /* Next DMA transfer is not the last transfer */
+ I2Cx->CTRL2 &= CTRL2_DMALAST_RESET;
+ }
+}
+
+/**
+ * @brief Generates I2Cx communication START condition.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C START condition generation.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_GenerateStart(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Generate a START condition */
+ I2Cx->CTRL1 |= CTRL1_START_SET;
+ }
+ else
+ {
+ /* Disable the START condition generation */
+ I2Cx->CTRL1 &= CTRL1_START_RESET;
+ }
+}
+
+/**
+ * @brief Generates I2Cx communication STOP condition.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C STOP condition generation.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_GenerateStop(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Generate a STOP condition */
+ I2Cx->CTRL1 |= CTRL1_STOP_SET;
+ }
+ else
+ {
+ /* Disable the STOP condition generation */
+ I2Cx->CTRL1 &= CTRL1_STOP_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C acknowledge feature.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C Acknowledgement.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_ConfigAck(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the acknowledgement */
+ I2Cx->CTRL1 |= CTRL1_ACK_SET;
+ }
+ else
+ {
+ /* Disable the acknowledgement */
+ I2Cx->CTRL1 &= CTRL1_ACK_RESET;
+ }
+}
+
+/**
+ * @brief Configures the specified I2C own address2.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Address specifies the 7bit I2C own address2.
+ */
+void I2C_ConfigOwnAddr2(I2C_Module* I2Cx, uint8_t Address)
+{
+ uint16_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+
+ /* Get the old register value */
+ tmpregister = I2Cx->OADDR2;
+
+ /* Reset I2Cx Own address2 bit [7:1] */
+ tmpregister &= OADDR2_ADDR2_RESET;
+
+ /* Set I2Cx Own address2 */
+ tmpregister |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
+
+ /* Store the new register value */
+ I2Cx->OADDR2 = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the specified I2C dual addressing mode.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C dual addressing mode.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableDualAddr(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable dual addressing mode */
+ I2Cx->OADDR2 |= OADDR2_DUALEN_SET;
+ }
+ else
+ {
+ /* Disable dual addressing mode */
+ I2Cx->OADDR2 &= OADDR2_DUALEN_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C general call feature.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C General call.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableGeneralCall(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable generall call */
+ I2Cx->CTRL1 |= CTRL1_GCEN_SET;
+ }
+ else
+ {
+ /* Disable generall call */
+ I2Cx->CTRL1 &= CTRL1_GCEN_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C interrupts.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT specifies the I2C interrupts sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_INT_BUF Buffer interrupt mask
+ * @arg I2C_INT_EVENT Event interrupt mask
+ * @arg I2C_INT_ERR Error interrupt mask
+ * @param Cmd new state of the specified I2C interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_ConfigInt(I2C_Module* I2Cx, uint16_t I2C_IT, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ assert_param(IS_I2C_CFG_INT(I2C_IT));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected I2C interrupts */
+ I2Cx->CTRL2 |= I2C_IT;
+ }
+ else
+ {
+ /* Disable the selected I2C interrupts */
+ I2Cx->CTRL2 &= (uint16_t)~I2C_IT;
+ }
+}
+
+/**
+ * @brief Sends a data byte through the I2Cx peripheral.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Data Byte to be transmitted..
+ */
+void I2C_SendData(I2C_Module* I2Cx, uint8_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ /* Write in the DAT register the data to be sent */
+ I2Cx->DAT = Data;
+}
+
+/**
+ * @brief Returns the most recent received data by the I2Cx peripheral.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @return The value of the received data.
+ */
+uint8_t I2C_RecvData(I2C_Module* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ /* Return the data in the DAT register */
+ return (uint8_t)I2Cx->DAT;
+}
+
+/**
+ * @brief Transmits the address byte to select the slave device.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Address specifies the slave address which will be transmitted
+ * @param I2C_Direction specifies whether the I2C device will be a
+ * Transmitter or a Receiver. This parameter can be one of the following values
+ * @arg I2C_DIRECTION_SEND Transmitter mode
+ * @arg I2C_DIRECTION_RECV Receiver mode
+ */
+void I2C_SendAddr7bit(I2C_Module* I2Cx, uint8_t Address, uint8_t I2C_Direction)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_DIRECTION(I2C_Direction));
+ /* Test on the direction to set/reset the read/write bit */
+ if (I2C_Direction != I2C_DIRECTION_SEND)
+ {
+ /* Set the address bit0 for read */
+ Address |= OADDR1_ADDR0_SET;
+ }
+ else
+ {
+ /* Reset the address bit0 for write */
+ Address &= OADDR1_ADDR0_RESET;
+ }
+ /* Send the address */
+ I2Cx->DAT = Address;
+}
+
+/**
+ * @brief Reads the specified I2C register and returns its value.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_Register specifies the register to read.
+ * This parameter can be one of the following values:
+ * @arg I2C_REG_CTRL1 CTRL1 register.
+ * @arg I2C_REG_CTRL2 CTRL2 register.
+ * @arg I2C_REG_OADDR1 OADDR1 register.
+ * @arg I2C_REG_OADDR2 OADDR2 register.
+ * @arg I2C_REG_DAT DAT register.
+ * @arg I2C_REG_STS1 STS1 register.
+ * @arg I2C_REG_STS2 STS2 register.
+ * @arg I2C_REG_CLKCTRL CHCFG register.
+ * @arg I2C_REG_TMRISE TMRISE register.
+ * @return The value of the read register.
+ */
+uint16_t I2C_GetRegister(I2C_Module* I2Cx, uint8_t I2C_Register)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_REG(I2C_Register));
+
+ tmp = (uint32_t)I2Cx;
+ tmp += I2C_Register;
+
+ /* Return the selected register value */
+ return (*(__IO uint16_t*)tmp);
+}
+
+/**
+ * @brief Enables or disables the specified I2C software reset.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C software reset.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableSoftwareReset(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Peripheral under reset */
+ I2Cx->CTRL1 |= CTRL1_SWRESET_SET;
+ }
+ else
+ {
+ /* Peripheral not under reset */
+ I2Cx->CTRL1 &= CTRL1_SWRESET_RESET;
+ }
+}
+
+/**
+ * @brief Selects the specified I2C NACK position in master receiver mode.
+ * This function is useful in I2C Master Receiver mode when the number
+ * of data to be received is equal to 2. In this case, this function
+ * should be called (with parameter I2C_NACK_POS_NEXT) before data
+ * reception starts,as described in the 2-byte reception procedure
+ * recommended in Reference Manual in Section: Master receiver.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_NACKPosition specifies the NACK position.
+ * This parameter can be one of the following values:
+ * @arg I2C_NACK_POS_NEXT indicates that the next byte will be the last
+ * received byte.
+ * @arg I2C_NACK_POS_CURRENT indicates that current byte is the last
+ * received byte.
+ *
+ * @note This function configures the same bit (POS) as I2C_ConfigPecLocation()
+ * but is intended to be used in I2C mode while I2C_ConfigPecLocation()
+ * is intended to used in SMBUS mode.
+ *
+ */
+void I2C_ConfigNackLocation(I2C_Module* I2Cx, uint16_t I2C_NACKPosition)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_NACK_POS(I2C_NACKPosition));
+
+ /* Check the input parameter */
+ if (I2C_NACKPosition == I2C_NACK_POS_NEXT)
+ {
+ /* Next byte in shift register is the last received byte */
+ I2Cx->CTRL1 |= I2C_NACK_POS_NEXT;
+ }
+ else
+ {
+ /* Current byte in shift register is the last received byte */
+ I2Cx->CTRL1 &= I2C_NACK_POS_CURRENT;
+ }
+}
+
+/**
+ * @brief Drives the SMBusAlert pin high or low for the specified I2C.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_SMBusAlert specifies SMBAlert pin level.
+ * This parameter can be one of the following values:
+ * @arg I2C_SMBALERT_LOW SMBAlert pin driven low
+ * @arg I2C_SMBALERT_HIGH SMBAlert pin driven high
+ */
+void I2C_ConfigSmbusAlert(I2C_Module* I2Cx, uint16_t I2C_SMBusAlert)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_SMB_ALERT(I2C_SMBusAlert));
+ if (I2C_SMBusAlert == I2C_SMBALERT_LOW)
+ {
+ /* Drive the SMBusAlert pin Low */
+ I2Cx->CTRL1 |= I2C_SMBALERT_LOW;
+ }
+ else
+ {
+ /* Drive the SMBusAlert pin High */
+ I2Cx->CTRL1 &= I2C_SMBALERT_HIGH;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C PEC transfer.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C PEC transmission.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_SendPEC(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected I2C PEC transmission */
+ I2Cx->CTRL1 |= CTRL1_PEC_SET;
+ }
+ else
+ {
+ /* Disable the selected I2C PEC transmission */
+ I2Cx->CTRL1 &= CTRL1_PEC_RESET;
+ }
+}
+
+/**
+ * @brief Selects the specified I2C PEC position.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_PECPosition specifies the PEC position.
+ * This parameter can be one of the following values:
+ * @arg I2C_PEC_POS_NEXT indicates that the next byte is PEC
+ * @arg I2C_PEC_POS_CURRENT indicates that current byte is PEC
+ *
+ * @note This function configures the same bit (POS) as I2C_ConfigNackLocation()
+ * but is intended to be used in SMBUS mode while I2C_ConfigNackLocation()
+ * is intended to used in I2C mode.
+ *
+ */
+void I2C_ConfigPecLocation(I2C_Module* I2Cx, uint16_t I2C_PECPosition)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_PEC_POS(I2C_PECPosition));
+ if (I2C_PECPosition == I2C_PEC_POS_NEXT)
+ {
+ /* Next byte in shift register is PEC */
+ I2Cx->CTRL1 |= I2C_PEC_POS_NEXT;
+ }
+ else
+ {
+ /* Current byte in shift register is PEC */
+ I2Cx->CTRL1 &= I2C_PEC_POS_CURRENT;
+ }
+}
+
+/**
+ * @brief Enables or disables the PEC value calculation of the transferred bytes.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2Cx PEC value calculation.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_ComputePec(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected I2C PEC calculation */
+ I2Cx->CTRL1 |= CTRL1_PECEN_SET;
+ }
+ else
+ {
+ /* Disable the selected I2C PEC calculation */
+ I2Cx->CTRL1 &= CTRL1_PECEN_RESET;
+ }
+}
+
+/**
+ * @brief Returns the PEC value for the specified I2C.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @return The PEC value.
+ */
+uint8_t I2C_GetPec(I2C_Module* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ /* Return the selected I2C PEC value */
+ return ((I2Cx->STS2) >> 8);
+}
+
+/**
+ * @brief Enables or disables the specified I2C ARP.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2Cx ARP.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableArp(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected I2C ARP */
+ I2Cx->CTRL1 |= CTRL1_ARPEN_SET;
+ }
+ else
+ {
+ /* Disable the selected I2C ARP */
+ I2Cx->CTRL1 &= CTRL1_ARPEN_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C Clock stretching.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2Cx Clock stretching.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableExtendClk(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd == DISABLE)
+ {
+ /* Enable the selected I2C Clock stretching */
+ I2Cx->CTRL1 |= CTRL1_NOEXTEND_SET;
+ }
+ else
+ {
+ /* Disable the selected I2C Clock stretching */
+ I2Cx->CTRL1 &= CTRL1_NOEXTEND_RESET;
+ }
+}
+
+/**
+ * @brief Selects the specified I2C fast mode duty cycle.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param FmDutyCycle specifies the fast mode duty cycle.
+ * This parameter can be one of the following values:
+ * @arg I2C_FMDUTYCYCLE_2 I2C fast mode Tlow/Thigh = 2
+ * @arg I2C_FMDUTYCYCLE_16_9 I2C fast mode Tlow/Thigh = 16/9
+ */
+void I2C_ConfigFastModeDutyCycle(I2C_Module* I2Cx, uint16_t FmDutyCycle)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_FM_DUTY_CYCLE(FmDutyCycle));
+ if (FmDutyCycle != I2C_FMDUTYCYCLE_16_9)
+ {
+ /* I2C fast mode Tlow/Thigh=2 */
+ I2Cx->CLKCTRL &= I2C_FMDUTYCYCLE_2;
+ }
+ else
+ {
+ /* I2C fast mode Tlow/Thigh=16/9 */
+ I2Cx->CLKCTRL |= I2C_FMDUTYCYCLE_16_9;
+ }
+}
+
+/**
+ * @brief
+ ****************************************************************************************
+ *
+ * I2C State Monitoring Functions
+ *
+ ****************************************************************************************
+ * This I2C driver provides three different ways for I2C state monitoring
+ * depending on the application requirements and constraints:
+ *
+ *
+ * 1) Basic state monitoring:
+ * Using I2C_CheckEvent() function:
+ * It compares the status registers (STS1 and STS2) content to a given event
+ * (can be the combination of one or more flags).
+ * It returns SUCCESS if the current status includes the given flags
+ * and returns ERROR if one or more flags are missing in the current status.
+ * - When to use:
+ * - This function is suitable for most applications as well as for startup
+ * activity since the events are fully described in the product reference manual
+ * (RM0008).
+ * - It is also suitable for users who need to define their own events.
+ * - Limitations:
+ * - If an error occurs (ie. error flags are set besides to the monitored flags),
+ * the I2C_CheckEvent() function may return SUCCESS despite the communication
+ * hold or corrupted real state.
+ * In this case, it is advised to use error interrupts to monitor the error
+ * events and handle them in the interrupt IRQ handler.
+ *
+ * @note
+ * For error management, it is advised to use the following functions:
+ * - I2C_ConfigInt() to configure and enable the error interrupts (I2C_INT_ERR).
+ * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
+ * Where x is the peripheral instance (I2C1, I2C2 ...)
+ * - I2C_GetFlag() or I2C_GetIntStatus() to be called into I2Cx_ER_IRQHandler()
+ * in order to determine which error occured.
+ * - I2C_ClrFlag() or I2C_ClrIntPendingBit() and/or I2C_EnableSoftwareReset()
+ * and/or I2C_GenerateStop() in order to clear the error flag and source,
+ * and return to correct communication status.
+ *
+ *
+ * 2) Advanced state monitoring:
+ * Using the function I2C_GetLastEvent() which returns the image of both status
+ * registers in a single word (uint32_t) (Status Register 2 value is shifted left
+ * by 16 bits and concatenated to Status Register 1).
+ * - When to use:
+ * - This function is suitable for the same applications above but it allows to
+ * overcome the mentioned limitation of I2C_GetFlag() function.
+ * The returned value could be compared to events already defined in the
+ * library (n32g43x_i2c.h) or to custom values defined by user.
+ * - This function is suitable when multiple flags are monitored at the same time.
+ * - At the opposite of I2C_CheckEvent() function, this function allows user to
+ * choose when an event is accepted (when all events flags are set and no
+ * other flags are set or just when the needed flags are set like
+ * I2C_CheckEvent() function).
+ * - Limitations:
+ * - User may need to define his own events.
+ * - Same remark concerning the error management is applicable for this
+ * function if user decides to check only regular communication flags (and
+ * ignores error flags).
+ *
+ *
+ * 3) Flag-based state monitoring:
+ * Using the function I2C_GetFlag() which simply returns the status of
+ * one single flag (ie. I2C_FLAG_RXDATNE ...).
+ * - When to use:
+ * - This function could be used for specific applications or in debug phase.
+ * - It is suitable when only one flag checking is needed (most I2C events
+ * are monitored through multiple flags).
+ * - Limitations:
+ * - When calling this function, the Status register is accessed. Some flags are
+ * cleared when the status register is accessed. So checking the status
+ * of one Flag, may clear other ones.
+ * - Function may need to be called twice or more in order to monitor one
+ * single event.
+ *
+ * For detailed description of Events, please refer to section I2C_Events in
+ * n32g43x_i2c.h file.
+ *
+ */
+
+/**
+ * @brief Checks whether the last I2Cx Event is equal to the one passed
+ * as parameter.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_EVENT specifies the event to be checked.
+ * This parameter can be one of the following values:
+ * @arg I2C_EVT_SLAVE_SEND_ADDR_MATCHED EV1
+ * @arg I2C_EVT_SLAVE_RECV_ADDR_MATCHED EV1
+ * @arg I2C_EVT_SLAVE_SEND_ADDR2_MATCHED EV1
+ * @arg I2C_EVT_SLAVE_RECV_ADDR2_MATCHED EV1
+ * @arg I2C_EVT_SLAVE_GCALLADDR_MATCHED EV1
+ * @arg I2C_EVT_SLAVE_DATA_RECVD EV2
+ * @arg (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_DUALFLAG) EV2
+ * @arg (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_GCALLADDR) EV2
+ * @arg I2C_EVT_SLAVE_DATA_SENDED EV3
+ * @arg (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_DUALFLAG) EV3
+ * @arg (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_GCALLADDR) EV3
+ * @arg I2C_EVT_SLAVE_ACK_MISS EV3_2
+ * @arg I2C_EVT_SLAVE_STOP_RECVD EV4
+ * @arg I2C_EVT_MASTER_MODE_FLAG EV5
+ * @arg I2C_EVT_MASTER_TXMODE_FLAG EV6
+ * @arg I2C_EVT_MASTER_RXMODE_FLAG EV6
+ * @arg I2C_EVT_MASTER_DATA_RECVD_FLAG EV7
+ * @arg I2C_EVT_MASTER_DATA_SENDING EV8
+ * @arg I2C_EVT_MASTER_DATA_SENDED EV8_2
+ * @arg I2C_EVT_MASTER_MODE_ADDRESS10_FLAG EV9
+ *
+ * @note: For detailed description of Events, please refer to section
+ * I2C_Events in n32g43x_i2c.h file.
+ *
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: Last event is equal to the I2C_EVENT
+ * - ERROR: Last event is different from the I2C_EVENT
+ */
+ErrorStatus I2C_CheckEvent(I2C_Module* I2Cx, uint32_t I2C_EVENT)
+{
+ uint32_t lastevent = 0;
+ uint32_t flag1 = 0, flag2 = 0;
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_EVT(I2C_EVENT));
+
+ /* Read the I2Cx status register */
+ flag1 = I2Cx->STS1;
+ flag2 = I2Cx->STS2;
+ flag2 = flag2 << 16;
+
+ /* Get the last event value from I2C status register */
+ lastevent = (flag1 | flag2) & FLAG_MASK;
+
+ /* Check whether the last event contains the I2C_EVENT */
+ if ((lastevent & I2C_EVENT) == I2C_EVENT)
+ {
+ /* SUCCESS: last event is equal to I2C_EVENT */
+ status = SUCCESS;
+ }
+ else
+ {
+ /* ERROR: last event is different from I2C_EVENT */
+ status = ERROR;
+ }
+ /* Return status */
+ return status;
+}
+
+/**
+ * @brief Returns the last I2Cx Event.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ *
+ * @note: For detailed description of Events, please refer to section
+ * I2C_Events in n32g43x_i2c.h file.
+ *
+ * @return The last event
+ */
+uint32_t I2C_GetLastEvent(I2C_Module* I2Cx)
+{
+ uint32_t lastevent = 0;
+ uint32_t flag1 = 0, flag2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+
+ /* Read the I2Cx status register */
+ flag1 = I2Cx->STS1;
+ flag2 = I2Cx->STS2;
+ flag2 = flag2 << 16;
+
+ /* Get the last event value from I2C status register */
+ lastevent = (flag1 | flag2) & FLAG_MASK;
+
+ /* Return status */
+ return lastevent;
+}
+
+/**
+ * @brief Checks whether the specified I2C flag is set or not.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_FLAG specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg I2C_FLAG_DUALFLAG Dual flag (Slave mode)
+ * @arg I2C_FLAG_SMBHADDR SMBus host header (Slave mode)
+ * @arg I2C_FLAG_SMBDADDR SMBus default header (Slave mode)
+ * @arg I2C_FLAG_GCALLADDR General call header flag (Slave mode)
+ * @arg I2C_FLAG_TRF Transmitter/Receiver flag
+ * @arg I2C_FLAG_BUSY Bus busy flag
+ * @arg I2C_FLAG_MSMODE Master/Slave flag
+ * @arg I2C_FLAG_SMBALERT SMBus Alert flag
+ * @arg I2C_FLAG_TIMOUT Timeout or Tlow error flag
+ * @arg I2C_FLAG_PECERR PEC error in reception flag
+ * @arg I2C_FLAG_OVERRUN Overrun/Underrun flag (Slave mode)
+ * @arg I2C_FLAG_ACKFAIL Acknowledge failure flag
+ * @arg I2C_FLAG_ARLOST Arbitration lost flag (Master mode)
+ * @arg I2C_FLAG_BUSERR Bus error flag
+ * @arg I2C_FLAG_TXDATE Data register empty flag (Transmitter)
+ * @arg I2C_FLAG_RXDATNE Data register not empty (Receiver) flag
+ * @arg I2C_FLAG_STOPF Stop detection flag (Slave mode)
+ * @arg I2C_FLAG_ADDR10F 10-bit header sent flag (Master mode)
+ * @arg I2C_FLAG_BYTEF Byte transfer finished flag
+ * @arg I2C_FLAG_ADDRF Address sent flag (Master mode) "ADSL"
+ * Address matched flag (Slave mode)"ENDA"
+ * @arg I2C_FLAG_STARTBF Start bit flag (Master mode)
+ * @return The new state of I2C_FLAG (SET or RESET).
+ */
+FlagStatus I2C_GetFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ __IO uint32_t i2creg = 0, i2cxbase = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
+
+ /* Get the I2Cx peripheral base address */
+ i2cxbase = (uint32_t)I2Cx;
+
+ /* Read flag register index */
+ i2creg = I2C_FLAG >> 28;
+
+ /* Get bit[23:0] of the flag */
+ I2C_FLAG &= FLAG_MASK;
+
+ if (i2creg != 0)
+ {
+ /* Get the I2Cx STS1 register address */
+ i2cxbase += 0x14;
+ }
+ else
+ {
+ /* Flag in I2Cx STS2 Register */
+ I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
+ /* Get the I2Cx STS2 register address */
+ i2cxbase += 0x18;
+ }
+
+ if (((*(__IO uint32_t*)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
+ {
+ /* I2C_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* I2C_FLAG is reset */
+ bitstatus = RESET;
+ }
+
+ /* Return the I2C_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the I2Cx's pending flags.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_FLAG specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_FLAG_SMBALERT SMBus Alert flag
+ * @arg I2C_FLAG_TIMOUT Timeout or Tlow error flag
+ * @arg I2C_FLAG_PECERR PEC error in reception flag
+ * @arg I2C_FLAG_OVERRUN Overrun/Underrun flag (Slave mode)
+ * @arg I2C_FLAG_ACKFAIL Acknowledge failure flag
+ * @arg I2C_FLAG_ARLOST Arbitration lost flag (Master mode)
+ * @arg I2C_FLAG_BUSERR Bus error flag
+ *
+ * @note
+ * - STOPF (STOP detection) is cleared by software sequence: a read operation
+ * to I2C_STS1 register (I2C_GetFlag()) followed by a write operation
+ * to I2C_CTRL1 register (I2C_Enable() to re-enable the I2C peripheral).
+ * - ADD10 (10-bit header sent) is cleared by software sequence: a read
+ * operation to I2C_STS1 (I2C_GetFlag()) followed by writing the
+ * second byte of the address in DAT register.
+ * - BTF (Byte Transfer Finished) is cleared by software sequence: a read
+ * operation to I2C_STS1 register (I2C_GetFlag()) followed by a
+ * read/write to I2C_DAT register (I2C_SendData()).
+ * - ADDR (Address sent) is cleared by software sequence: a read operation to
+ * I2C_STS1 register (I2C_GetFlag()) followed by a read operation to
+ * I2C_STS2 register ((void)(I2Cx->STS2)).
+ * - SB (Start Bit) is cleared software sequence: a read operation to I2C_STS1
+ * register (I2C_GetFlag()) followed by a write operation to I2C_DAT
+ * register (I2C_SendData()).
+ */
+void I2C_ClrFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG)
+{
+ uint32_t flagpos = 0;
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_CLR_FLAG(I2C_FLAG));
+ /* Get the I2C flag position */
+ flagpos = I2C_FLAG & FLAG_MASK;
+ /* Clear the selected I2C flag */
+ I2Cx->STS1 = (uint16_t)~flagpos;
+}
+
+/**
+ * @brief Checks whether the specified I2C interrupt has occurred or not.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT specifies the interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg I2C_INT_SMBALERT SMBus Alert flag
+ * @arg I2C_INT_TIMOUT Timeout or Tlow error flag
+ * @arg I2C_INT_PECERR PEC error in reception flag
+ * @arg I2C_INT_OVERRUN Overrun/Underrun flag (Slave mode)
+ * @arg I2C_INT_ACKFAIL Acknowledge failure flag
+ * @arg I2C_INT_ARLOST Arbitration lost flag (Master mode)
+ * @arg I2C_INT_BUSERR Bus error flag
+ * @arg I2C_INT_TXDATE Data register empty flag (Transmitter)
+ * @arg I2C_INT_RXDATNE Data register not empty (Receiver) flag
+ * @arg I2C_INT_STOPF Stop detection flag (Slave mode)
+ * @arg I2C_INT_ADDR10F 10-bit header sent flag (Master mode)
+ * @arg I2C_INT_BYTEF Byte transfer finished flag
+ * @arg I2C_INT_ADDRF Address sent flag (Master mode) "ADSL"
+ * Address matched flag (Slave mode)"ENDAD"
+ * @arg I2C_INT_STARTBF Start bit flag (Master mode)
+ * @return The new state of I2C_IT (SET or RESET).
+ */
+INTStatus I2C_GetIntStatus(I2C_Module* I2Cx, uint32_t I2C_IT)
+{
+ INTStatus bitstatus = RESET;
+ uint32_t enablestatus = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_GET_INT(I2C_IT));
+
+ /* Check if the interrupt source is enabled or not */
+ enablestatus = (uint32_t)(((I2C_IT & INTEN_MASK) >> 16) & (I2Cx->CTRL2));
+
+ /* Get bit[23:0] of the flag */
+ I2C_IT &= FLAG_MASK;
+
+ /* Check the status of the specified I2C flag */
+ if (((I2Cx->STS1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
+ {
+ /* I2C_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* I2C_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the I2C_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the I2Cx's interrupt pending bits.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_INT_SMBALERT SMBus Alert interrupt
+ * @arg I2C_INT_TIMOUT Timeout or Tlow error interrupt
+ * @arg I2C_INT_PECERR PEC error in reception interrupt
+ * @arg I2C_INT_OVERRUN Overrun/Underrun interrupt (Slave mode)
+ * @arg I2C_INT_ACKFAIL Acknowledge failure interrupt
+ * @arg I2C_INT_ARLOST Arbitration lost interrupt (Master mode)
+ * @arg I2C_INT_BUSERR Bus error interrupt
+ *
+ * @note
+ * - STOPF (STOP detection) is cleared by software sequence: a read operation
+ * to I2C_STS1 register (I2C_GetIntStatus()) followed by a write operation to
+ * I2C_CTRL1 register (I2C_Enable() to re-enable the I2C peripheral).
+ * - ADD10 (10-bit header sent) is cleared by software sequence: a read
+ * operation to I2C_STS1 (I2C_GetIntStatus()) followed by writing the second
+ * byte of the address in I2C_DAT register.
+ * - BTF (Byte Transfer Finished) is cleared by software sequence: a read
+ * operation to I2C_STS1 register (I2C_GetIntStatus()) followed by a
+ * read/write to I2C_DAT register (I2C_SendData()).
+ * - ADDR (Address sent) is cleared by software sequence: a read operation to
+ * I2C_STS1 register (I2C_GetIntStatus()) followed by a read operation to
+ * I2C_STS2 register ((void)(I2Cx->STS2)).
+ * - SB (Start Bit) is cleared by software sequence: a read operation to
+ * I2C_STS1 register (I2C_GetIntStatus()) followed by a write operation to
+ * I2C_DAT register (I2C_SendData()).
+ */
+void I2C_ClrIntPendingBit(I2C_Module* I2Cx, uint32_t I2C_IT)
+{
+ uint32_t flagpos = 0;
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_CLR_INT(I2C_IT));
+ /* Get the I2C flag position */
+ flagpos = I2C_IT & FLAG_MASK;
+ /* Clear the selected I2C flag */
+ I2Cx->STS1 = (uint16_t)~flagpos;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_iwdg.c b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_iwdg.c
new file mode 100644
index 0000000000..b5f3ff9180
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_iwdg.c
@@ -0,0 +1,193 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_iwdg.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_iwdg.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup IWDG
+ * @brief IWDG driver modules
+ * @{
+ */
+
+/** @addtogroup IWDG_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Private_Defines
+ * @{
+ */
+
+/* ---------------------- IWDG registers bit mask ----------------------------*/
+
+/* KEY register bit mask */
+#define KEY_ReloadKey ((uint16_t)0xAAAA)
+#define KEY_EnableKey ((uint16_t)0xCCCC)
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
+ * @param IWDG_WriteAccess new state of write access to IWDG_PR and IWDG_RLR registers.
+ * This parameter can be one of the following values:
+ * @arg IWDG_WRITE_ENABLE Enable write access to IWDG_PR and IWDG_RLR registers
+ * @arg IWDG_WRITE_DISABLE Disable write access to IWDG_PR and IWDG_RLR registers
+ */
+void IWDG_WriteConfig(uint16_t IWDG_WriteAccess)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_WRITE(IWDG_WriteAccess));
+ IWDG->KEY = IWDG_WriteAccess;
+}
+
+/**
+ * @brief Sets IWDG Prescaler value.
+ * @param IWDG_Prescaler specifies the IWDG Prescaler value.
+ * This parameter can be one of the following values:
+ * @arg IWDG_PRESCALER_DIV4 IWDG prescaler set to 4
+ * @arg IWDG_PRESCALER_DIV8 IWDG prescaler set to 8
+ * @arg IWDG_PRESCALER_DIV16 IWDG prescaler set to 16
+ * @arg IWDG_PRESCALER_DIV32 IWDG prescaler set to 32
+ * @arg IWDG_PRESCALER_DIV64 IWDG prescaler set to 64
+ * @arg IWDG_PRESCALER_DIV128 IWDG prescaler set to 128
+ * @arg IWDG_PRESCALER_DIV256 IWDG prescaler set to 256
+ */
+void IWDG_SetPrescalerDiv(uint8_t IWDG_Prescaler)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_PRESCALER_DIV(IWDG_Prescaler));
+ IWDG->PREDIV = IWDG_Prescaler;
+}
+
+/**
+ * @brief Sets IWDG Reload value.
+ * @param Reload specifies the IWDG Reload value.
+ * This parameter must be a number between 0 and 0x0FFF.
+ */
+void IWDG_CntReload(uint16_t Reload)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_RELOAD(Reload));
+ IWDG->RELV = Reload;
+}
+
+/**
+ * @brief Reloads IWDG counter with value defined in the reload register
+ * (write access to IWDG_PR and IWDG_RLR registers disabled).
+ */
+void IWDG_ReloadKey(void)
+{
+ IWDG->KEY = KEY_ReloadKey;
+}
+
+/**
+ * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
+ */
+void IWDG_Enable(void)
+{
+ IWDG->KEY = KEY_EnableKey;
+}
+
+/**
+ * @brief Checks whether the specified IWDG flag is set or not.
+ * @param IWDG_FLAG specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg IWDG_PVU_FLAG Prescaler Value Update on going
+ * @arg IWDG_CRVU_FLAG Reload Value Update on going
+ * @return The new state of IWDG_FLAG (SET or RESET).
+ */
+FlagStatus IWDG_GetStatus(uint16_t IWDG_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_IWDG_FLAG(IWDG_FLAG));
+ if ((IWDG->STS & IWDG_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_lptim.c b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_lptim.c
new file mode 100644
index 0000000000..ff0684eb9d
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_lptim.c
@@ -0,0 +1,1258 @@
+/** ----------------------------------------------------------------------------
+ * Nationz Technology Software Support - NATIONZ -
+ * -----------------------------------------------------------------------------
+ * Copyright (c) 2022, Nationz Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaiimer below.
+ *
+ * - Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the disclaimer below in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * Nationz's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+ * -----------------------------------------------------------------------------
+ */
+
+/** ****************************************************************************
+ * @copyright Nationz Co.,Ltd
+ * Copyright (c) 2019 All Rights Reserved
+ *******************************************************************************
+ * @file n32g43x_lptim.c
+ * @author
+ * @date
+ * @version v1.2.0
+ * @brief
+ ******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "n32g43x_lptim.h"
+#include "n32g43x_rcc.h"
+
+/** @addtogroup n32g43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup LPTIM
+ * @brief LPTIM driver modules
+ * @{
+ */
+
+/** @defgroup LPTIM_Private_TypesDefinitions
+ * @{
+ */
+/**
+ * @}
+ */
+//#define LPTIM
+//#if defined (LPTIM)//LPTIM
+
+/** @defgroup RCC_EC_LPTIM1 Peripheral LPTIM get clock source
+ * @{
+ */
+#define RCC_LPTIM_CLKSOURCE ((uint32_t)0x00000007)/*!< LPTIM1 clock source selection bits */
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup LPTIM_Private_Macros
+ * @{
+ */
+#define IS_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LPTIM_CLK_SOURCE_INTERNAL) \
+ || ((__VALUE__) == LPTIM_CLK_SOURCE_EXTERNAL))
+
+#define IS_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LPTIM_PRESCALER_DIV1) \
+ || ((__VALUE__) == LPTIM_PRESCALER_DIV2) \
+ || ((__VALUE__) == LPTIM_PRESCALER_DIV4) \
+ || ((__VALUE__) == LPTIM_PRESCALER_DIV8) \
+ || ((__VALUE__) == LPTIM_PRESCALER_DIV16) \
+ || ((__VALUE__) == LPTIM_PRESCALER_DIV32) \
+ || ((__VALUE__) == LPTIM_PRESCALER_DIV64) \
+ || ((__VALUE__) == LPTIM_PRESCALER_DIV128))
+
+#define IS_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LPTIM_OUTPUT_WAVEFORM_PWM) \
+ || ((__VALUE__) == LPTIM_OUTPUT_WAVEFORM_SETONCE))
+
+#define IS_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LPTIM_OUTPUT_POLARITY_REGULAR) \
+ || ((__VALUE__) == LPTIM_OUTPUT_POLARITY_INVERSE))
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
+ * @{
+ */
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup LPTIM_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup LPTIM_EF_Init
+ * @{
+ */
+
+/**
+ * @brief Set LPTIMx registers to their reset values.
+ * @param LPTIMx LP Timer instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: LPTIMx registers are de-initialized
+ * - ERROR: invalid LPTIMx instance
+ */
+void LPTIM_DeInit(LPTIM_Module* LPTIMx)
+{
+ if (LPTIMx == LPTIM)
+ {
+ RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LPTIM,ENABLE);
+ RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LPTIM,DISABLE);
+ }
+}
+
+/**
+ * @brief Set each fields of the LPTIM_InitStruct structure to its default
+ * value.
+ * @param LPTIM_InitStruct pointer to a @ref LPTIM_InitType structure
+ * @retval None
+ */
+void LPTIM_StructInit(LPTIM_InitType* LPTIM_InitStruct)
+{
+ /* Set the default configuration */
+ LPTIM_InitStruct->ClockSource = LPTIM_CLK_SOURCE_INTERNAL;
+ LPTIM_InitStruct->Prescaler = LPTIM_PRESCALER_DIV1;
+ LPTIM_InitStruct->Waveform = LPTIM_OUTPUT_WAVEFORM_PWM;
+ LPTIM_InitStruct->Polarity = LPTIM_OUTPUT_POLARITY_REGULAR;
+}
+
+/**
+ * @brief Configure the LPTIMx peripheral according to the specified parameters.
+ * @note LPTIM_Init can only be called when the LPTIM instance is disabled.
+ * @note LPTIMx can be disabled using unitary function @ref LPTIM_Disable().
+ * @param LPTIMx LP Timer Instance
+ * @param LPTIM_InitStruct pointer to a @ref LPTIM_InitType structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: LPTIMx instance has been initialized
+ * - ERROR: LPTIMx instance hasn't been initialized
+ */
+ErrorStatus LPTIM_Init(LPTIM_Module * LPTIMx, LPTIM_InitType* LPTIM_InitStruct)
+{
+ ErrorStatus result = SUCCESS;
+ /* Check the parameters */
+ assert_param(IS_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource));
+ assert_param(IS_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler));
+ assert_param(IS_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform));
+ assert_param(IS_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity));
+
+ /* The LPTIMx_CFG register must only be modified when the LPTIM is disabled
+ (ENABLE bit is reset to 0).
+ */
+ if (LPTIM_IsEnabled(LPTIMx) == 1UL)
+ {
+ result = ERROR;
+ }
+ else
+ {
+ /* Set CKSEL bitfield according to ClockSource value */
+ /* Set PRESC bitfield according to Prescaler value */
+ /* Set WAVE bitfield according to Waveform value */
+ /* Set WAVEPOL bitfield according to Polarity value */
+ MODIFY_REG(LPTIMx->CFG,
+ (LPTIM_CFG_CLKSEL | LPTIM_CFG_CLKPOL | LPTIM_CFG_WAVE| LPTIM_CFG_WAVEPOL),
+ LPTIM_InitStruct->ClockSource | \
+ LPTIM_InitStruct->Prescaler | \
+ LPTIM_InitStruct->Waveform | \
+ LPTIM_InitStruct->Polarity);
+ }
+
+ return result;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @brief Disable the LPTIM instance
+ * @rmtoll CR ENABLE LPTIM_Disable
+ * @param LPTIMx Low-Power Timer instance
+ * @note
+ * @retval None
+ */
+void LPTIM_Disable(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->CTRL, LPTIM_CTRL_LPTIMEN);
+}
+
+/** @defgroup LPTIM_EF_LPTIM_Configuration LPTIM Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable the LPTIM instance
+ * @note After setting the ENABLE bit, a delay of two counter clock is needed
+ * before the LPTIM instance is actually enabled.
+ * @rmtoll CR ENABLE LPTIM_Enable
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_Enable(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->CTRL, LPTIM_CTRL_LPTIMEN);
+}
+
+/**
+ * @brief Indicates whether the LPTIM instance is enabled.
+ * @rmtoll CR ENABLE LPTIM_IsEnabled
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsEnabled(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->CTRL, LPTIM_CTRL_LPTIMEN) == LPTIM_CTRL_LPTIMEN)? 1UL : 0UL));
+}
+
+/**
+ * @brief Starts the LPTIM counter in the desired mode.
+ * @note LPTIM instance must be enabled before starting the counter.
+ * @note It is possible to change on the fly from One Shot mode to
+ * Continuous mode.
+ * @rmtoll CR CNTSTRT LPTIM_StartCounter\n
+ * CR SNGSTRT LPTIM_StartCounter
+ * @param LPTIMx Low-Power Timer instance
+ * @param OperatingMode This parameter can be one of the following values:
+ * @arg @ref LPTIM_OPERATING_MODE_CONTINUOUS
+ * @arg @ref LPTIM_OPERATING_MODE_ONESHOT
+ * @retval None
+ */
+void LPTIM_StartCounter(LPTIM_Module *LPTIMx, uint32_t OperatingMode)
+{
+ MODIFY_REG(LPTIMx->CTRL, LPTIM_CTRL_TSTCM | LPTIM_CTRL_SNGMST, OperatingMode);
+}
+
+/**
+ * @brief Set the LPTIM registers update mode (enable/disable register preload)
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @rmtoll CFG PRELOAD LPTIM_SetUpdateMode
+ * @param LPTIMx Low-Power Timer instance
+ * @param UpdateMode This parameter can be one of the following values:
+ * @arg @ref LPTIM_UPDATE_MODE_IMMEDIATE
+ * @arg @ref LPTIM_UPDATE_MODE_ENDOFPERIOD
+ * @retval None
+ */
+void LPTIM_SetUpdateMode(LPTIM_Module *LPTIMx, uint32_t UpdateMode)
+{
+ MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_RELOAD, UpdateMode);
+}
+
+/**
+ * @brief Get the LPTIM registers update mode
+ * @rmtoll CFG PRELOAD LPTIM_GetUpdateMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_UPDATE_MODE_IMMEDIATE
+ * @arg @ref LPTIM_UPDATE_MODE_ENDOFPERIOD
+ */
+uint32_t LPTIM_GetUpdateMode(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_RELOAD));
+}
+
+/**
+ * @brief Set the auto reload value
+ * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
+ * @note After a write to the LPTIMx_ARR register a new write operation to the
+ * same register can only be performed when the previous write operation
+ * is completed. Any successive write before the ARROK flag be set, will
+ * lead to unpredictable results.
+ * @note autoreload value be strictly greater than the compare value.
+ * @rmtoll ARR ARR LPTIM_SetAutoReload
+ * @param LPTIMx Low-Power Timer instance
+ * @param AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
+ * @retval None
+ */
+void LPTIM_SetAutoReload(LPTIM_Module *LPTIMx, uint32_t AutoReload)
+{
+ MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARRVAL, AutoReload);
+}
+
+/**
+ * @brief Get actual auto reload value
+ * @rmtoll ARR ARR LPTIM_GetAutoReload
+ * @param LPTIMx Low-Power Timer instance
+ * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+uint32_t LPTIM_GetAutoReload(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARRVAL));
+}
+
+/**
+ * @brief Set the compare value
+ * @note After a write to the LPTIMx_CMP register a new write operation to the
+ * same register can only be performed when the previous write operation
+ * is completed. Any successive write before the CMPOK flag be set, will
+ * lead to unpredictable results.
+ * @rmtoll CMP CMP LPTIM_SetCompare
+ * @param LPTIMx Low-Power Timer instance
+ * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
+ * @retval None
+ */
+void LPTIM_SetCompare(LPTIM_Module *LPTIMx, uint32_t CompareValue)
+{
+ MODIFY_REG(LPTIMx->COMPx, LPTIM_COMP_CMPVAL, CompareValue);
+}
+
+/**
+ * @brief Get actual compare value
+ * @rmtoll CMP CMP LPTIM_GetCompare
+ * @param LPTIMx Low-Power Timer instance
+ * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+uint32_t LPTIM_GetCompare(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->COMPx, LPTIM_COMP_CMPVAL));
+}
+
+/**
+ * @brief Get actual counter value
+ * @note When the LPTIM instance is running with an asynchronous clock, reading
+ * the LPTIMx_CNT register may return unreliable values. So in this case
+ * it is necessary to perform two consecutive read accesses and verify
+ * that the two returned values are identical.
+ * @rmtoll CNT CNT LPTIM_GetCounter
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Counter value
+ */
+uint32_t LPTIM_GetCounter(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNTVAL));
+}
+
+/**
+ * @brief Set the counter mode (selection of the LPTIM counter clock source).
+ * @note The counter mode can be set only when the LPTIM instance is disabled.
+ * @rmtoll CFG COUNTMODE LPTIM_SetCounterMode
+ * @param LPTIMx Low-Power Timer instance
+ * @param CounterMode This parameter can be one of the following values:
+ * @arg @ref LPTIM_COUNTER_MODE_INTERNAL
+ * @arg @ref LPTIM_COUNTER_MODE_EXTERNAL
+ * @retval None
+ */
+void LPTIM_SetCounterMode(LPTIM_Module *LPTIMx, uint32_t CounterMode)
+{
+ MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CNTMEN, CounterMode);
+}
+
+/**
+ * @brief Get the counter mode
+ * @rmtoll CFG COUNTMODE LPTIM_GetCounterMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_COUNTER_MODE_INTERNAL
+ * @arg @ref LPTIM_COUNTER_MODE_EXTERNAL
+ */
+uint32_t LPTIM_GetCounterMode(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CNTMEN));
+}
+
+/**
+ * @brief Configure the LPTIM instance output (LPTIMx_OUT)
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note Regarding the LPTIM output polarity the change takes effect
+ * immediately, so the output default value will change immediately after
+ * the polarity is re-configured, even before the timer is enabled.
+ * @rmtoll CFG WAVE LPTIM_ConfigOutput\n
+ * CFG WAVPOL LPTIM_ConfigOutput
+ * @param LPTIMx Low-Power Timer instance
+ * @param Waveform This parameter can be one of the following values:
+ * @arg @ref LPTIM_OUTPUT_WAVEFORM_PWM
+ * @arg @ref LPTIM_OUTPUT_WAVEFORM_SETONCE
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LPTIM_OUTPUT_POLARITY_REGULAR
+ * @arg @ref LPTIM_OUTPUT_POLARITY_INVERSE
+ * @retval None
+ */
+void LPTIM_ConfigOutput(LPTIM_Module *LPTIMx, uint32_t Waveform, uint32_t Polarity)
+{
+ MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_WAVE | LPTIM_CFG_WAVEPOL, Waveform | Polarity);
+}
+
+/**
+ * @brief Set waveform shape
+ * @rmtoll CFG WAVE LPTIM_SetWaveform
+ * @param LPTIMx Low-Power Timer instance
+ * @param Waveform This parameter can be one of the following values:
+ * @arg @ref LPTIM_OUTPUT_WAVEFORM_PWM
+ * @arg @ref LPTIM_OUTPUT_WAVEFORM_SETONCE
+ * @retval None
+ */
+void LPTIM_SetWaveform(LPTIM_Module *LPTIMx, uint32_t Waveform)
+{
+ MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_WAVE, Waveform);
+}
+
+/**
+ * @brief Get actual waveform shape
+ * @rmtoll CFG WAVE LPTIM_GetWaveform
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_OUTPUT_WAVEFORM_PWM
+ * @arg @ref LPTIM_OUTPUT_WAVEFORM_SETONCE
+ */
+uint32_t LPTIM_GetWaveform(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_WAVE));
+}
+
+/**
+ * @brief Set output polarity
+ * @rmtoll CFG WAVPOL LPTIM_SetPolarity
+ * @param LPTIMx Low-Power Timer instance
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LPTIM_OUTPUT_POLARITY_REGULAR
+ * @arg @ref LPTIM_OUTPUT_POLARITY_INVERSE
+ * @retval None
+ */
+void LPTIM_SetPolarity(LPTIM_Module *LPTIMx, uint32_t Polarity)
+{
+ MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_WAVEPOL, Polarity);
+}
+
+/**
+ * @brief Get actual output polarity
+ * @rmtoll CFG WAVPOL LPTIM_GetPolarity
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_OUTPUT_POLARITY_REGULAR
+ * @arg @ref LPTIM_OUTPUT_POLARITY_INVERSE
+ */
+uint32_t LPTIM_GetPolarity(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_WAVEPOL));
+}
+
+/**
+ * @brief Set actual prescaler division ratio.
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note When the LPTIM is configured to be clocked by an internal clock source
+ * and the LPTIM counter is configured to be updated by active edges
+ * detected on the LPTIM external Input1, the internal clock provided to
+ * the LPTIM must be not be prescaled.
+ * @rmtoll CFG PRESC LPTIM_SetPrescaler
+ * @param LPTIMx Low-Power Timer instance
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LPTIM_PRESCALER_DIV1
+ * @arg @ref LPTIM_PRESCALER_DIV2
+ * @arg @ref LPTIM_PRESCALER_DIV4
+ * @arg @ref LPTIM_PRESCALER_DIV8
+ * @arg @ref LPTIM_PRESCALER_DIV16
+ * @arg @ref LPTIM_PRESCALER_DIV32
+ * @arg @ref LPTIM_PRESCALER_DIV64
+ * @arg @ref LPTIM_PRESCALER_DIV128
+ * @retval None
+ */
+void LPTIM_SetPrescaler(LPTIM_Module *LPTIMx, uint32_t Prescaler)
+{
+ MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKPRE, Prescaler);
+}
+
+/**
+ * @brief Get actual prescaler division ratio.
+ * @rmtoll CFG PRESC LPTIM_GetPrescaler
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_PRESCALER_DIV1
+ * @arg @ref LPTIM_PRESCALER_DIV2
+ * @arg @ref LPTIM_PRESCALER_DIV4
+ * @arg @ref LPTIM_PRESCALER_DIV8
+ * @arg @ref LPTIM_PRESCALER_DIV16
+ * @arg @ref LPTIM_PRESCALER_DIV32
+ * @arg @ref LPTIM_PRESCALER_DIV64
+ * @arg @ref LPTIM_PRESCALER_DIV128
+ */
+uint32_t LPTIM_GetPrescaler(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKPRE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_EF_Trigger_Configuration Trigger Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable the timeout function
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note The first trigger event will start the timer, any successive trigger
+ * event will reset the counter and the timer will restart.
+ * @note The timeout value corresponds to the compare value; if no trigger
+ * occurs within the expected time frame, the MCU is waked-up by the
+ * compare match event.
+ * @rmtoll CFG TIMOUT LPTIM_EnableTimeout
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_EnableTimeout(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->CFG, LPTIM_CFG_TIMOUTEN);
+}
+
+/**
+ * @brief Disable the timeout function
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note A trigger event arriving when the timer is already started will be
+ * ignored.
+ * @rmtoll CFG TIMOUT LPTIM_DisableTimeout
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_DisableTimeout(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->CFG, LPTIM_CFG_TIMOUTEN);
+}
+
+/**
+ * @brief Indicate whether the timeout function is enabled.
+ * @rmtoll CFG TIMOUT LPTIM_IsEnabledTimeout
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsEnabledTimeout(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->CFG, LPTIM_CFG_TIMOUTEN) == LPTIM_CFG_TIMOUTEN)? 1UL : 0UL));
+}
+
+/**
+ * @brief Start the LPTIM counter
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @rmtoll CFG TRIGEN LPTIM_TrigSw
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_TrigSw(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->CFG, LPTIM_CFG_TRGEN);
+}
+
+/**
+ * @brief Configure the external trigger used as a trigger event for the LPTIM.
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note An internal clock source must be present when a digital filter is
+ * required for the trigger.
+ * @rmtoll CFG TRIGSEL LPTIM_ConfigTrigger\n
+ * CFG TRGFLT LPTIM_ConfigTrigger\n
+ * CFG TRIGEN LPTIM_ConfigTrigger
+ * @param LPTIMx Low-Power Timer instance
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LPTIM_TRIG_SOURCE_GPIO
+ * @arg @ref LPTIM_TRIG_SOURCE_RTCALARMA
+ * @arg @ref LPTIM_TRIG_SOURCE_RTCALARMB
+ * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP1 (*)
+ * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP2
+ * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP3 (*)
+ * @arg @ref LPTIM_TRIG_SOURCE_COMP1
+ * @arg @ref LPTIM_TRIG_SOURCE_COMP2
+ *
+ * (*) Value not defined in all devices. \n
+ *
+ * @param Filter This parameter can be one of the following values:
+ * @arg @ref LPTIM_TRIG_FILTER_NONE
+ * @arg @ref LPTIM_TRIG_FILTER_2
+ * @arg @ref LPTIM_TRIG_FILTER_4
+ * @arg @ref LPTIM_TRIG_FILTER_8
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LPTIM_TRIG_POLARITY_RISING
+ * @arg @ref LPTIM_TRIG_POLARITY_FALLING
+ * @arg @ref LPTIM_TRIG_POLARITY_RISING_FALLING
+ * @retval None
+ */
+void LPTIM_ConfigTrigger(LPTIM_Module *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
+{
+ MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_TRGSEL | LPTIM_CFG_TRIGFLT | LPTIM_CFG_TRGEN, Source | Filter | Polarity);
+}
+
+/**
+ * @brief Get actual external trigger source.
+ * @rmtoll CFG TRIGSEL LPTIM_GetTriggerSource
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_TRIG_SOURCE_GPIO
+ * @arg @ref LPTIM_TRIG_SOURCE_RTCALARMA
+ * @arg @ref LPTIM_TRIG_SOURCE_RTCALARMB
+ * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP1 (*)
+ * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP2
+ * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP3 (*)
+ * @arg @ref LPTIM_TRIG_SOURCE_COMP1
+ * @arg @ref LPTIM_TRIG_SOURCE_COMP2
+ *
+ * (*) Value not defined in all devices. \n
+ *
+ */
+uint32_t LPTIM_GetTriggerSource(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_TRGSEL));
+}
+
+/**
+ * @brief Get actual external trigger filter.
+ * @rmtoll CFG TRGFLT LPTIM_GetTriggerFilter
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_TRIG_FILTER_NONE
+ * @arg @ref LPTIM_TRIG_FILTER_2
+ * @arg @ref LPTIM_TRIG_FILTER_4
+ * @arg @ref LPTIM_TRIG_FILTER_8
+ */
+uint32_t LPTIM_GetTriggerFilter(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_TRIGFLT));
+}
+
+/**
+ * @brief Get actual external trigger polarity.
+ * @rmtoll CFG TRIGEN LPTIM_GetTriggerPolarity
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_TRIG_POLARITY_RISING
+ * @arg @ref LPTIM_TRIG_POLARITY_FALLING
+ * @arg @ref LPTIM_TRIG_POLARITY_RISING_FALLING
+ */
+uint32_t LPTIM_GetTriggerPolarity(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_TRGEN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_EF_Clock_Configuration Clock Configuration
+ * @{
+ */
+
+/**
+ * @brief Set the source of the clock used by the LPTIM instance.
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @rmtoll CFG CKSEL LPTIM_SetClockSource
+ * @param LPTIMx Low-Power Timer instance
+ * @param ClockSource This parameter can be one of the following values:
+ * @arg @ref LPTIM_CLK_SOURCE_INTERNAL
+ * @arg @ref LPTIM_CLK_SOURCE_EXTERNAL
+ * @retval None
+ */
+void LPTIM_SetClockSource(LPTIM_Module *LPTIMx, uint32_t ClockSource)
+{
+ MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKSEL, ClockSource);
+}
+
+/**
+ * @brief Get actual LPTIM instance clock source.
+ * @rmtoll CFG CKSEL LPTIM_GetClockSource
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_CLK_SOURCE_INTERNAL
+ * @arg @ref LPTIM_CLK_SOURCE_EXTERNAL
+ */
+uint32_t LPTIM_GetClockSource(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKSEL));
+}
+
+/**
+ * @brief Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note When both external clock signal edges are considered active ones,
+ * the LPTIM must also be clocked by an internal clock source with a
+ * frequency equal to at least four times the external clock frequency.
+ * @note An internal clock source must be present when a digital filter is
+ * required for external clock.
+ * @rmtoll CFG CKFLT LPTIM_ConfigClock\n
+ * CFG CKPOL LPTIM_ConfigClock
+ * @param LPTIMx Low-Power Timer instance
+ * @param ClockFilter This parameter can be one of the following values:
+ * @arg @ref LPTIM_CLK_FILTER_NONE
+ * @arg @ref LPTIM_CLK_FILTER_2
+ * @arg @ref LPTIM_CLK_FILTER_4
+ * @arg @ref LPTIM_CLK_FILTER_8
+ * @param ClockPolarity This parameter can be one of the following values:
+ * @arg @ref LPTIM_CLK_POLARITY_RISING
+ * @arg @ref LPTIM_CLK_POLARITY_FALLING
+ * @arg @ref LPTIM_CLK_POLARITY_RISING_FALLING
+ * @retval None
+ */
+void LPTIM_ConfigClock(LPTIM_Module *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
+{
+ MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKFLT | LPTIM_CFG_CLKPOL, ClockFilter | ClockPolarity);
+}
+
+/**
+ * @brief Get actual clock polarity
+ * @rmtoll CFG CKPOL LPTIM_GetClockPolarity
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_CLK_POLARITY_RISING
+ * @arg @ref LPTIM_CLK_POLARITY_FALLING
+ * @arg @ref LPTIM_CLK_POLARITY_RISING_FALLING
+ */
+uint32_t LPTIM_GetClockPolarity(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKPOL));
+}
+
+/**
+ * @brief Get actual clock digital filter
+ * @rmtoll CFG CKFLT LPTIM_GetClockFilter
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_CLK_FILTER_NONE
+ * @arg @ref LPTIM_CLK_FILTER_2
+ * @arg @ref LPTIM_CLK_FILTER_4
+ * @arg @ref LPTIM_CLK_FILTER_8
+ */
+uint32_t LPTIM_GetClockFilter(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKFLT));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_EF_Encoder_Mode Encoder Mode
+ * @{
+ */
+
+/**
+ * @brief Configure the encoder mode.
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @rmtoll CFG CKPOL LPTIM_SetEncoderMode
+ * @param LPTIMx Low-Power Timer instance
+ * @param EncoderMode This parameter can be one of the following values:
+ * @arg @ref LPTIM_ENCODER_MODE_RISING
+ * @arg @ref LPTIM_ENCODER_MODE_FALLING
+ * @arg @ref LPTIM_ENCODER_MODE_RISING_FALLING
+ * @retval None
+ */
+void LPTIM_SetEncoderMode(LPTIM_Module *LPTIMx, uint32_t EncoderMode)
+{
+ MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKPOL, EncoderMode);
+}
+
+/**
+ * @brief Get actual encoder mode.
+ * @rmtoll CFG CKPOL LPTIM_GetEncoderMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_ENCODER_MODE_RISING
+ * @arg @ref LPTIM_ENCODER_MODE_FALLING
+ * @arg @ref LPTIM_ENCODER_MODE_RISING_FALLING
+ */
+uint32_t LPTIM_GetEncoderMode(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKPOL));
+}
+
+/**
+ * @brief Enable the encoder mode
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note In this mode the LPTIM instance must be clocked by an internal clock
+ * source. Also, the prescaler division ratio must be equal to 1.
+ * @note LPTIM instance must be configured in continuous mode prior enabling
+ * the encoder mode.
+ * @rmtoll CFG ENC LPTIM_EnableEncoderMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_EnableEncoderMode(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->CFG, LPTIM_CFG_ENC);
+}
+/**
+ * @brief Enable the encoder mode
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note In this mode the LPTIM instance must be clocked by an internal clock
+ * source. Also, the prescaler division ratio must be equal to 1.
+ * @note LPTIM instance must be configured in continuous mode prior enabling
+ * the encoder mode.
+ * @rmtoll CFG ENC LPTIM_EnableEncoderMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_EnableNoEncoderMode(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->CFG, LPTIM_CFG_NENC);
+}
+/**
+ * @brief Disable the encoder mode
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @rmtoll CFG ENC LPTIM_DisableEncoderMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_DisableEncoderMode(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->CFG, LPTIM_CFG_ENC);
+}
+
+/**
+ * @brief Indicates whether the LPTIM operates in encoder mode.
+ * @rmtoll CFG ENC LPTIM_IsEnabledEncoderMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsEnabledEncoderMode(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->CFG, LPTIM_CFG_ENC) == LPTIM_CFG_ENC)? 1UL : 0UL));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_EF_FLAG_Management FLAG Management
+ * @{
+ */
+
+/**
+ * @brief Clear the compare match flag (CMPMCF)
+ * @rmtoll ICR CMPMCF LPTIM_ClearFLAG_CMPM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_ClearFLAG_CMPM(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_CMPMCF);
+}
+
+/**
+ * @brief Inform application whether a compare match interrupt has occurred.
+ * @rmtoll ISR CMPM LPTIM_IsActiveFlag_CMPM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsActiveFlag_CMPM(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_CMPM) ==LPTIM_INTSTS_CMPM)? 1UL : 0UL));
+}
+
+/**
+ * @brief Clear the autoreload match flag (ARRMCF)
+ * @rmtoll ICR ARRMCF LPTIM_ClearFLAG_ARRM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_ClearFLAG_ARRM(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_ARRMCF);
+}
+
+/**
+ * @brief Inform application whether a autoreload match interrupt has occured.
+ * @rmtoll ISR ARRM LPTIM_IsActiveFlag_ARRM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsActiveFlag_ARRM(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_ARRM) ==LPTIM_INTSTS_ARRM)? 1UL : 0UL));
+}
+
+/**
+ * @brief Clear the external trigger valid edge flag(EXTTRIGCF).
+ * @rmtoll ICR EXTTRIGCF LPTIM_ClearFlag_EXTTRIG
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_ClearFlag_EXTTRIG(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_EXTRIGCF);
+}
+
+/**
+ * @brief Inform application whether a valid edge on the selected external trigger input has occurred.
+ * @rmtoll ISR EXTTRIG LPTIM_IsActiveFlag_EXTTRIG
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsActiveFlag_EXTTRIG(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_EXTRIG) ==LPTIM_INTSTS_EXTRIG)? 1UL : 0UL));
+}
+
+/**
+ * @brief Clear the compare register update interrupt flag (CMPOKCF).
+ * @rmtoll ICR CMPOKCF LPTIM_ClearFlag_CMPOK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_ClearFlag_CMPOK(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_CMPUPDCF);
+}
+
+/**
+ * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed. If so, a new one can be initiated.
+ * @rmtoll ISR CMPOK LPTIM_IsActiveFlag_CMPOK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsActiveFlag_CMPOK(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_CMPUPD) ==LPTIM_INTSTS_CMPUPD)? 1UL : 0UL));
+}
+
+/**
+ * @brief Clear the autoreload register update interrupt flag (ARROKCF).
+ * @rmtoll ICR ARROKCF LPTIM_ClearFlag_ARROK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_ClearFlag_ARROK(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_ARRUPDCF);
+}
+
+/**
+ * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed. If so, a new one can be initiated.
+ * @rmtoll ISR ARROK LPTIM_IsActiveFlag_ARROK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsActiveFlag_ARROK(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_ARRUPD) ==LPTIM_INTSTS_ARRUPD)? 1UL : 0UL));
+}
+
+/**
+ * @brief Clear the counter direction change to up interrupt flag (UPCF).
+ * @rmtoll ICR UPCF LPTIM_ClearFlag_UP
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_ClearFlag_UP(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_UPCF);
+}
+
+/**
+ * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).
+ * @rmtoll ISR UP LPTIM_IsActiveFlag_UP
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsActiveFlag_UP(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTSTS, LPTIM_INTSTS_UP) == LPTIM_INTSTS_UP)? 1UL : 0UL));
+}
+
+/**
+ * @brief Clear the counter direction change to down interrupt flag (DOWNCF).
+ * @rmtoll ICR DOWNCF LPTIM_ClearFlag_DOWN
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_ClearFlag_DOWN(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_DOWNCF);
+}
+
+/**
+ * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).
+ * @rmtoll ISR DOWN LPTIM_IsActiveFlag_DOWN
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsActiveFlag_DOWN(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_DOWN) ==LPTIM_INTSTS_DOWN)? 1UL : 0UL));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_EF_IT_Management Interrupt Management
+ * @{
+ */
+
+/**
+ * @brief Enable compare match interrupt (CMPMIE).
+ * @rmtoll IER CMPMIE LPTIM_EnableIT_CMPM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_EnableIT_CMPM(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPMIE);
+}
+
+/**
+ * @brief Disable compare match interrupt (CMPMIE).
+ * @rmtoll IER CMPMIE LPTIM_DisableIT_CMPM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_DisableIT_CMPM(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPMIE);
+}
+
+/**
+ * @brief Indicates whether the compare match interrupt (CMPMIE) is enabled.
+ * @rmtoll IER CMPMIE LPTIM_IsEnabledIT_CMPM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsEnabledIT_CMPM(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPMIE) == LPTIM_INTEN_CMPMIE)? 1UL : 0UL));
+}
+
+/**
+ * @brief Enable autoreload match interrupt (ARRMIE).
+ * @rmtoll IER ARRMIE LPTIM_EnableIT_ARRM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_EnableIT_ARRM(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRMIE);
+}
+
+/**
+ * @brief Disable autoreload match interrupt (ARRMIE).
+ * @rmtoll IER ARRMIE LPTIM_DisableIT_ARRM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_DisableIT_ARRM(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRMIE);
+}
+
+/**
+ * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
+ * @rmtoll IER ARRMIE LPTIM_IsEnabledIT_ARRM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsEnabledIT_ARRM(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRMIE) == LPTIM_INTEN_ARRMIE)? 1UL : 0UL));
+}
+
+/**
+ * @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
+ * @rmtoll IER EXTTRIGIE LPTIM_EnableIT_EXTTRIG
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_EnableIT_EXTTRIG(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_EXTRIGIE);
+}
+
+/**
+ * @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
+ * @rmtoll IER EXTTRIGIE LPTIM_DisableIT_EXTTRIG
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_DisableIT_EXTTRIG(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_EXTRIGIE);
+}
+
+/**
+ * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
+ * @rmtoll IER EXTTRIGIE LPTIM_IsEnabledIT_EXTTRIG
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsEnabledIT_EXTTRIG(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_EXTRIGIE) == LPTIM_INTEN_EXTRIGIE)? 1UL : 0UL));
+}
+
+/**
+ * @brief Enable compare register write completed interrupt (CMPOKIE).
+ * @rmtoll IER CMPOKIE LPTIM_EnableIT_CMPOK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_EnableIT_CMPOK(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPUPDIE);
+}
+
+/**
+ * @brief Disable compare register write completed interrupt (CMPOKIE).
+ * @rmtoll IER CMPOKIE LPTIM_DisableIT_CMPOK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_DisableIT_CMPOK(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPUPDIE);
+}
+
+/**
+ * @brief Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
+ * @rmtoll IER CMPOKIE LPTIM_IsEnabledIT_CMPOK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsEnabledIT_CMPOK(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPUPDIE) == LPTIM_INTEN_CMPUPDIE)? 1UL : 0UL));
+}
+
+/**
+ * @brief Enable autoreload register write completed interrupt (ARROKIE).
+ * @rmtoll IER ARROKIE LPTIM_EnableIT_ARROK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_EnableIT_ARROK(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRUPDIE);
+}
+
+/**
+ * @brief Disable autoreload register write completed interrupt (ARROKIE).
+ * @rmtoll IER ARROKIE LPTIM_DisableIT_ARROK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_DisableIT_ARROK(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRUPDIE);
+}
+
+/**
+ * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
+ * @rmtoll IER ARROKIE LPTIM_IsEnabledIT_ARROK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsEnabledIT_ARROK(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRUPDIE) == LPTIM_INTEN_ARRUPDIE)? 1UL : 0UL));
+}
+
+/**
+ * @brief Enable direction change to up interrupt (UPIE).
+ * @rmtoll IER UPIE LPTIM_EnableIT_UP
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_EnableIT_UP(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_UPIE);
+}
+
+/**
+ * @brief Disable direction change to up interrupt (UPIE).
+ * @rmtoll IER UPIE LPTIM_DisableIT_UP
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_DisableIT_UP(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_UPIE);
+}
+
+/**
+ * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
+ * @rmtoll IER UPIE LPTIM_IsEnabledIT_UP
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsEnabledIT_UP(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_UPIE) == LPTIM_INTEN_UPIE)? 1UL : 0UL));
+}
+
+/**
+ * @brief Enable direction change to down interrupt (DOWNIE).
+ * @rmtoll IER DOWNIE LPTIM_EnableIT_DOWN
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_EnableIT_DOWN(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_DOWNIE);
+}
+
+/**
+ * @brief Disable direction change to down interrupt (DOWNIE).
+ * @rmtoll IER DOWNIE LPTIM_DisableIT_DOWN
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_DisableIT_DOWN(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_DOWNIE);
+}
+
+/**
+ * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
+ * @rmtoll IER DOWNIE LPTIM_IsEnabledIT_DOWN
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsEnabledIT_DOWN(LPTIM_Module *LPTIMx)
+{
+ return ((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_DOWNIE) == LPTIM_INTEN_DOWNIE)? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+
+//#endif /* LPTIM */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/******************* (C) COPYRIGHT 2019 NATIONZ *****END OF FILE****/
+
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_lpuart.c b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_lpuart.c
new file mode 100644
index 0000000000..a054322487
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_lpuart.c
@@ -0,0 +1,532 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_lpuart.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_lpuart.h"
+#include "n32g43x_rcc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup LPUART
+ * @brief LPUART driver modules
+ * @{
+ */
+
+/** @addtogroup LPUART_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Private_Defines
+ * @{
+ */
+
+#define STS_CLR_MASK ((uint16_t)0x01BF) /*!< LPUART STS Mask */
+
+#define INTEN_CLR_MASK ((uint16_t)0x0000) /*!< LPUART INTEN Mask */
+#define INT_MASK ((uint16_t)0x007F) /*!< LPUART Interrupt Mask */
+
+#define CTRL_CLR_MASK ((uint16_t)0x70F4) /*!< LPUART CTRL Mask */
+#define CTRL_SMPCNT_MASK ((uint16_t)0x3FFF) /*!< LPUART Sampling Method Mask */
+#define CTRL_WUSTP_MASK ((uint16_t)0x4FFF) /*!< LPUART WakeUp Method Mask */
+#define CTRL_WUSTP_SET ((uint16_t)0x0080) /*!< LPUART stop mode Enable Mask */
+#define CTRL_WUSTP_RESET ((uint16_t)0x7F7F) /*!< LPUART stop mode Disable Mask */
+#define CTRL_LOOPBACK_SET ((uint16_t)0x0010) /*!< LPUART Loopback Test Enable Mask */
+#define CTRL_LOOPBACK_RESET ((uint16_t)0xFFEF) /*!< LPUART Loopback Test Disable Mask */
+#define CTRL_FLUSH_SET ((uint16_t)0x0004) /*!< LPUART Flush Receiver FIFO Enable Mask */
+#define CTRL_FLUSH_RESET ((uint16_t)0x7FFB) /*!< LPUART Flush Receiver FIFO Disable Mask */
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the LPUART peripheral registers to their default reset values.
+ */
+void LPUART_DeInit(void)
+{
+ RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LPUART, ENABLE);
+ RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LPUART, DISABLE);
+}
+
+/**
+ * @brief Initializes the LPUART peripheral according to the specified
+ * parameters in the LPUART_InitStruct.
+ * @param LPUART_InitStruct pointer to a LPUART_InitType structure
+ * that contains the configuration information for the specified LPUART
+ * peripheral.
+ */
+void LPUART_Init(LPUART_InitType* LPUART_InitStruct)
+{
+ uint32_t tmpregister = 0x00, clocksrc = 0x00, apbclock = 0x00;
+ uint32_t integerdivider = 0x00;
+ uint32_t fractionaldivider = 0x00;
+ uint32_t tmpdivider = 0x00, lastdivider = 0x00, i = 0x00;
+ RCC_ClocksType RCC_ClocksStatus;
+
+ /* Check the parameters */
+ // assert_param(IS_LPUART_BAUDRATE(LPUART_InitStruct->BaudRate));
+ assert_param(IS_LPUART_PARITY(LPUART_InitStruct->Parity));
+ assert_param(IS_LPUART_MODE(LPUART_InitStruct->Mode));
+ assert_param(IS_LPUART_RTSTHRESHOLD(LPUART_InitStruct->RtsThreshold));
+ assert_param(IS_LPUART_HARDWARE_FLOW_CONTROL(LPUART_InitStruct->HardwareFlowControl));
+
+ // 时钟æºåˆ¤æ–，波特率范围
+
+ /*---------------------------- LPUART CTRL Configuration -----------------------*/
+ tmpregister = LPUART->CTRL;
+ /* Clear FC_RXEN, FC_TXEN, RTS_THSEL[1:0], PCDIS, TRS and PSEL bits */
+ tmpregister &= CTRL_CLR_MASK;
+ /* Configure the LPUART Parity, Mode, RtsThrehold and HardwareFlowControl ----------------------- */
+ /* Set PCDIS and PSEL bits according to Parity value */
+ /* Set the TRS bit according to Mode */
+ /* Set RTS_THSEL[1:0] bits according to RtsThrehold */
+ /* Set FC_RXEN and FC_TXEN bits according to HardwareFlowControl */
+ tmpregister |= (uint32_t)LPUART_InitStruct->Parity | LPUART_InitStruct->Mode | LPUART_InitStruct->RtsThreshold | LPUART_InitStruct->HardwareFlowControl;
+ /* Write to LPUART CTRL */
+ LPUART->CTRL = (uint16_t)tmpregister;
+
+ /*---------------------------- LPUART BRCFG1 & 2 Configuration -----------------------*/
+ /* Configure the LPUART Baud Rate -------------------------------------------*/
+ clocksrc = RCC_GetLPUARTClkSrc();
+ if (clocksrc == RCC_LPUARTCLK_SRC_LSE)
+ {
+ apbclock = 0x8000; // 32.768kHz
+ }
+ else if (clocksrc == RCC_LPUARTCLK_SRC_HSI)
+ {
+ apbclock = 0xF42400; // 16MHz
+ }
+ else if (clocksrc == RCC_LPUARTCLK_SRC_SYSCLK)
+ {
+ RCC_GetClocksFreqValue(&RCC_ClocksStatus);
+ apbclock = RCC_ClocksStatus.SysclkFreq;
+ }
+ else //(clocksrc ==RCC_LPUARTCLK_SRC_APB1)
+ {
+ RCC_GetClocksFreqValue(&RCC_ClocksStatus);
+ apbclock = RCC_ClocksStatus.Pclk1Freq;
+ }
+
+ /* Determine the integer part */
+ integerdivider = apbclock / (LPUART_InitStruct->BaudRate);
+
+ /* Configure sampling method */
+ if (integerdivider <= 10)
+ {
+ LPUART_ConfigSamplingMethod(LPUART_SMPCNT_1B);
+ }
+ else
+ {
+ LPUART_ConfigSamplingMethod(LPUART_SMPCNT_3B);
+ }
+
+ /* Check baudrate */
+ assert_param(IS_LPUART_BAUDRATE(integerdivider));
+ /* Write to LPUART BRCFG1 */
+ LPUART->BRCFG1 = (uint16_t)integerdivider;
+
+ /* Determine the fractional part */
+ fractionaldivider = ((apbclock % (LPUART_InitStruct->BaudRate)) * 10000) / (LPUART_InitStruct->BaudRate);
+
+ tmpregister = 0x00;
+ tmpdivider = fractionaldivider;
+ /* Implement the fractional part in the register */
+ for( i = 0; i < 8; i++)
+ {
+ lastdivider = tmpdivider;
+ tmpdivider = lastdivider + fractionaldivider;
+ if ((tmpdivider / 10000) ^ (lastdivider / 10000))
+ {
+ tmpregister |= (0x01 << i);
+ }
+ }
+ /* Write to LPUART BRCFG2 */
+ LPUART->BRCFG2 = (uint8_t)tmpregister;
+}
+
+/**
+ * @brief Fills each LPUART_InitStruct member with its default value.
+ * @param LPUART_InitStruct pointer to a LPUART_InitType structure
+ * which will be initialized.
+ */
+void LPUART_StructInit(LPUART_InitType* LPUART_InitStruct)
+{
+ /* LPUART_InitStruct members default value */
+ LPUART_InitStruct->BaudRate = 9600;
+ LPUART_InitStruct->Parity = LPUART_PE_NO;
+ LPUART_InitStruct->Mode = LPUART_MODE_RX | LPUART_MODE_TX;
+ LPUART_InitStruct->RtsThreshold = LPUART_RTSTH_FIFOFU;
+ LPUART_InitStruct->HardwareFlowControl = LPUART_HFCTRL_NONE;
+}
+
+/**
+ * @brief Flushes Receiver FIFO.
+ */
+void LPUART_FlushRxFifo(void)
+{
+ /* Clear LPUART Flush Receiver FIFO */
+ LPUART->CTRL |= CTRL_FLUSH_SET;
+ while (LPUART_GetFlagStatus(LPUART_FLAG_FIFO_NE) != RESET)
+ {
+ }
+ LPUART->CTRL &= CTRL_FLUSH_RESET;
+}
+
+/**
+ * @brief Enables or disables the specified LPUART interrupts.
+ * @param LPUART_INT specifies the LPUART interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg LPUART_INT_WUF Wake-Up Interrupt
+ * @arg LPUART_INT_FIFO_NE FIFO Non-Empty Interrupt
+ * @arg LPUART_INT_FIFO_HF FIFO Half Full Interrupt
+ * @arg LPUART_INT_FIFO_FU FIFO Full Interrupt Enable
+ * @arg LPUART_INT_FIFO_OV FIFO Overflow Interrupt
+ * @arg LPUART_INT_TXC TX Complete Interrupt
+ * @arg LPUART_INT_PE Parity Check Error Interrupt
+ * @param Cmd new state of the specified LPUART interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void LPUART_ConfigInt(uint16_t LPUART_INT, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_LPUART_CFG_INT(LPUART_INT));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ LPUART->INTEN |= (uint8_t)LPUART_INT;
+ }
+ else
+ {
+ LPUART->INTEN &= (uint8_t)(~LPUART_INT);
+ }
+}
+
+/**
+ * @brief Enables or disables the LPUART's DMA interface.
+ * @param LPUART_DMAReq specifies the DMA request.
+ * This parameter can be any combination of the following values:
+ * @arg LPUART_DMAREQ_TX LPUART DMA transmit request
+ * @arg LPUART_DMAREQ_RX LPUART DMA receive request
+ * @param Cmd new state of the DMA Request sources.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void LPUART_EnableDMA(uint16_t LPUART_DMAReq, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_LPUART_DMAREQ(LPUART_DMAReq));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the DMA transfer by setting the DMA_RXEN and/or DMA_TXEN bits in the LPUART_CTRL register */
+ LPUART->CTRL |= LPUART_DMAReq;
+ }
+ else
+ {
+ /* Disable the DMA transfer by clearing the DMA_RXEN and/or DMA_TXEN bits in the LPUART_CTRL register */
+ LPUART->CTRL &= (uint16_t)(~LPUART_DMAReq);
+ }
+}
+
+/**
+ * @brief Selects the LPUART WakeUp method.
+ * @param LPUART_WakeUpMethod specifies the LPUART wakeup method.
+ * This parameter can be one of the following values:
+ * @arg LPUART_WUSTP_STARTBIT WakeUp by Start Bit Detection
+ * @arg LPUART_WUSTP_RXNE WakeUp by RXNE Detection
+ * @arg LPUART_WUSTP_BYTE WakeUp by A Configurable Received Byte
+ * @arg LPUART_WUSTP_FRAME WakeUp by A Programmed 4-Byte Frame
+ */
+void LPUART_ConfigWakeUpMethod(uint16_t LPUART_WakeUpMethod)
+{
+ /* Check the parameters */
+ assert_param(IS_LPUART_WAKEUP(LPUART_WakeUpMethod));
+
+ LPUART->CTRL &= CTRL_WUSTP_MASK;
+ LPUART->CTRL |= LPUART_WakeUpMethod;
+}
+
+/**
+ * @brief Enables or disables LPUART Wakeup in STOP2 mode.
+ * @param Cmd new state of the LPUART Wakeup in STOP2 mode.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void LPUART_EnableWakeUpStop(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable Wakeup in STOP2 mode by setting the WUSTP bit in the CTRL register */
+ LPUART->CTRL |= CTRL_WUSTP_SET;
+ }
+ else
+ {
+ /* Disable Wakeup in STOP2 mode by clearing the WUSTP bit in the CTRL register */
+ LPUART->CTRL &= CTRL_WUSTP_RESET;
+ }
+}
+
+/**
+ * @brief Selects the LPUART Sampling method.
+ * @param LPUART_SamplingMethod specifies the LPAURT sampling method.
+ * This parameter can be one of the following values:
+ * @arg LPUART_SMPCNT_3B 3 Sample bit
+ * @arg LPUART_SMPCNT_1B 1 Sample bit
+ */
+void LPUART_ConfigSamplingMethod(uint16_t LPUART_SamplingMethod)
+{
+ /* Check the parameters */
+ assert_param(IS_LPUART_SAMPLING(LPUART_SamplingMethod));
+
+ LPUART->CTRL &= CTRL_SMPCNT_MASK;
+ LPUART->CTRL |= LPUART_SamplingMethod;
+}
+
+/**
+ * @brief Enables or disables LPUART Loop Back Self-Test.
+ * @param Cmd new state of the LPUART Loop Back Self-Test.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void LPUART_EnableLoopBack(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable LPUART Loop Back Self-Test by setting the LOOKBACK bit in the CTRL register */
+ LPUART->CTRL |= CTRL_LOOPBACK_SET;
+ }
+ else
+ {
+ /* Disable LPUART Loop Back Self-Test by clearing the LOOKBACK bit in the CTRL register */
+ LPUART->CTRL &= CTRL_LOOPBACK_RESET;
+ }
+}
+
+/**
+ * @brief Transmits single data through the LPUART peripheral.
+ * @param Data the data to transmit.
+ */
+void LPUART_SendData(uint8_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_LPUART_DATA(Data));
+
+ /* Transmit Data */
+ LPUART->DAT = (Data & (uint8_t)0xFF);
+}
+
+/**
+ * @brief Returns the most recent received data by the LPUART peripheral.
+ * @return The received data.
+ */
+uint8_t LPUART_ReceiveData(void)
+{
+ /* Receive Data */
+ return (uint8_t)(LPUART->DAT & (uint8_t)0xFF);
+}
+
+/**
+ * @brief SConfigures LPUART detected byte or frame match for wakeup CPU from STOPS mode.
+ * @param LPUART_WakeUpData specifies the LPUART detected byte or frame match for wakeup CPU from STOP2 mode.
+ */
+void LPUART_ConfigWakeUpData(uint32_t LPUART_WakeUpData)
+{
+ LPUART->WUDAT = LPUART_WakeUpData;
+}
+
+/**
+ * @brief Checks whether the specified LPUART flag is set or not.
+ * @param LPUART_FLAG specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg LPUART_FLAG_PEF Parity Check Error Flag.
+ * @arg LPUART_FLAG_TXC TX Complete Flag.
+ * @arg LPUART_FLAG_FIFO_OV FIFO Overflow Flag.
+ * @arg LPUART_FLAG_FIFO_FU FIFO Full Flag.
+ * @arg LPUART_FLAG_FIFO_HF FIFO Half Full Flag.
+ * @arg LPUART_FLAG_FIFO_NE FIFO Non-Empty Flag.
+ * @arg LPUART_FLAG_CTS CTS Change(Hardware Flow Control) Flag.
+ * @arg LPUART_FLAG_WUFWakeup from STOP2 mode Flag.
+ * @arg LPUART_FLAG_NF Noise Detection Flag.
+ * @return The new state of LPUART_FLAG (SET or RESET).
+ */
+FlagStatus LPUART_GetFlagStatus(uint16_t LPUART_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_LPUART_FLAG(LPUART_FLAG));
+
+ if ((LPUART->STS & LPUART_FLAG) != (uint16_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the LPUART's pending flags.
+ * @param LPUART_FLAG specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg LPUART_FLAG_PEF Parity Check Error Flag.
+ * @arg LPUART_FLAG_TXC TX Complete Flag.
+ * @arg LPUART_FLAG_FIFO_OV FIFO Overflow Flag.
+ * @arg LPUART_FLAG_FIFO_FU FIFO Full Flag.
+ * @arg LPUART_FLAG_FIFO_HF FIFO Half Full Flag.
+ * @arg LPUART_FLAG_FIFO_NE FIFO Non-Empty Flag.
+ * @arg LPUART_FLAG_CTS CTS Change(Hardware Flow Control) Flag.
+ * @arg LPUART_FLAG_WUFWakeup from STOP2 mode Flag.
+ * @arg LPUART_FLAG_NF Noise Detection Flag.
+ */
+void LPUART_ClrFlag(uint16_t LPUART_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_LPUART_CLEAR_FLAG(LPUART_FLAG));
+
+ LPUART->STS = (uint16_t)LPUART_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified LPUART interrupt has occurred or not.
+ * @param LPUART_INT specifies the LPUART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg LPUART_INT_WUF Wake-Up Interrupt
+ * @arg LPUART_INT_FIFO_NE FIFO Non-Empty Interrupt
+ * @arg LPUART_INT_FIFO_HF FIFO Half Full Interrupt
+ * @arg LPUART_INT_FIFO_FU FIFO Full Interrupt Enable
+ * @arg LPUART_INT_FIFO_OV FIFO Overflow Interrupt
+ * @arg LPUART_INT_TXC TX Complete Interrupt
+ * @arg LPUART_INT_PE Parity Check Error Interrupt
+ * @return The new state of LPUART_INT (SET or RESET).
+ */
+INTStatus LPUART_GetIntStatus(uint16_t LPUART_INT)
+{
+ uint32_t bitpos = 0x00, itmask = 0x00;
+ INTStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_LPUART_GET_INT(LPUART_INT));
+
+ /* Get the interrupt position */
+ itmask = (uint8_t)(LPUART_INT >> 0x08) & INT_MASK;
+ itmask = (uint32_t)0x01 << itmask;
+ itmask &= LPUART->INTEN;
+
+ bitpos = ((uint8_t)LPUART_INT) & 0xFF;
+ if (LPUART_INT_WUF == LPUART_INT){
+ bitpos = (bitpos << 0x01);
+ }
+ bitpos &= LPUART->STS;
+ if ((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the LPUART's interrupt pending bits.
+ * @param LPUART_INT specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg LPUART_INT_WUF Wake-Up Interrupt
+ * @arg LPUART_INT_FIFO_NE FIFO Non-Empty Interrupt
+ * @arg LPUART_INT_FIFO_HF FIFO Half Full Interrupt
+ * @arg LPUART_INT_FIFO_FU FIFO Full Interrupt Enable
+ * @arg LPUART_INT_FIFO_OV FIFO Overflow Interrupt
+ * @arg LPUART_INT_TXC TX Complete Interrupt
+ * @arg LPUART_INT_PE Parity Check Error Interrupt
+ */
+void LPUART_ClrIntPendingBit(uint16_t LPUART_INT)
+{
+ uint16_t itmask = 0x00;
+ /* Check the parameters */
+ assert_param(IS_LPUART_CLR_INT(LPUART_INT));
+
+ itmask = ((uint8_t)LPUART_INT) & 0xFF;
+ LPUART->STS = (uint16_t)itmask;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_opamp.c b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_opamp.c
new file mode 100644
index 0000000000..f4d422f29f
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_opamp.c
@@ -0,0 +1,198 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_opamp.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_opamp.h"
+#include "n32g43x_rcc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup OPAMP
+ * @brief OPAMP driver modules
+ * @{
+ */
+
+/** @addtogroup OPAMP_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup OPAMP_Private_Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup OPAMP_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup OPAMP_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup OPAMP_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup OPAMP_Private_Functions
+ * @{
+ */
+#define SetBitMsk(reg, bit, msk) ((reg) = (((reg) & ~(msk)) | (bit)))
+#define ClrBit(reg, bit) ((reg) &= ~(bit))
+#define SetBit(reg, bit) ((reg) |= (bit))
+#define GetBit(reg, bit) ((reg) & (bit))
+/**
+ * @brief Deinitializes the OPAMP peripheral registers to their default reset values.
+ */
+void OPAMP_DeInit(void)
+{
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_OPAMP, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_OPAMP, DISABLE);
+}
+void OPAMP_StructInit(OPAMP_InitType* OPAMP_InitStruct)
+{
+ OPAMP_InitStruct->Opa2SrcSel = OPAMP2_CS_TIMSRCSEL_TIM1CC6;
+ OPAMP_InitStruct->Gain = OPAMP_CS_PGA_GAIN_2;
+ OPAMP_InitStruct->HighVolRangeEn = ENABLE;
+ OPAMP_InitStruct->TimeAutoMuxEn = DISABLE;
+ OPAMP_InitStruct->Mod = OPAMP_CS_PGA_EN;
+}
+void OPAMP_Init(OPAMPX OPAMPx, OPAMP_InitType* OPAMP_InitStruct)
+{
+ __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+ __IO uint32_t tmp = *pCs;
+ if (OPAMPx == OPAMP2)
+ SetBitMsk(tmp, OPAMP_InitStruct->Opa2SrcSel, OPAMP_CS_OPAMP2_TIMSRCSEL);
+ SetBitMsk(tmp, OPAMP_InitStruct->Gain, OPAMP_CS_PGA_GAIN_MASK);
+ if (OPAMP_InitStruct->HighVolRangeEn==ENABLE)
+ SetBitMsk(tmp, OPAMP_CS_RANGE_MASK, OPAMP_CS_RANGE_MASK);
+ else
+ ClrBit(tmp,OPAMP_CS_RANGE_MASK);
+ if (OPAMP_InitStruct->TimeAutoMuxEn==ENABLE)
+ SetBitMsk(tmp,OPAMP_CS_TCMEN_MASK, OPAMP_CS_TCMEN_MASK);
+ else
+ ClrBit(tmp,OPAMP_CS_TCMEN_MASK);
+ SetBitMsk(tmp, OPAMP_InitStruct->Mod, OPAMP_CS_MOD_MASK);
+ *pCs = tmp;
+}
+void OPAMP_Enable(OPAMPX OPAMPx, FunctionalState en)
+{
+ __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+ if (en)
+ SetBit(*pCs, OPAMP_CS_EN_MASK);
+ else
+ ClrBit(*pCs, OPAMP_CS_EN_MASK);
+}
+
+void OPAMP_SetPgaGain(OPAMPX OPAMPx, OPAMP_CS_PGA_GAIN Gain)
+{
+ __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+ __IO uint32_t tmp = *pCs;
+ SetBitMsk(tmp, Gain, OPAMP_CS_PGA_GAIN_MASK);
+ *pCs = tmp;
+}
+void OPAMP_SetVpSecondSel(OPAMPX OPAMPx, OPAMP_CS_VPSSEL VpSSel)
+{
+ __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+ __IO uint32_t tmp = *pCs;
+ SetBitMsk(tmp, VpSSel, OPAMP_CS_VPSEL_SECOND_MASK);
+ *pCs = tmp;
+}
+void OPAMP_SetVmSecondSel(OPAMPX OPAMPx, OPAMP_CS_VMSSEL VmSSel)
+{
+ __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+ __IO uint32_t tmp = *pCs;
+ SetBitMsk(tmp, VmSSel, OPAMP_CS_VMSEL_SECOND_MASK);
+ *pCs = tmp;
+}
+void OPAMP_SetVpSel(OPAMPX OPAMPx, OPAMP_CS_VPSEL VpSel)
+{
+ __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+ __IO uint32_t tmp = *pCs;
+ SetBitMsk(tmp, VpSel, OPAMP_CS_VPSEL_MASK);
+ *pCs = tmp;
+}
+void OPAMP_SetVmSel(OPAMPX OPAMPx, OPAMP_CS_VMSEL VmSel)
+{
+ __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+ __IO uint32_t tmp = *pCs;
+ SetBitMsk(tmp, VmSel, OPAMP_CS_VMSEL_MASK);
+ *pCs = tmp;
+}
+bool OPAMP_IsCalOutHigh(OPAMPX OPAMPx)
+{
+ __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+ return (GetBit(*pCs, OPAMP_CS_CALOUT_MASK)) ? true : false;
+}
+void OPAMP_CalibrationEnable(OPAMPX OPAMPx, FunctionalState en)
+{
+ __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+ if (en)
+ SetBit(*pCs, OPAMP_CS_CALON_MASK);
+ else
+ ClrBit(*pCs, OPAMP_CS_CALON_MASK);
+}
+// Lock see @OPAMP_LOCK
+void OPAMP_SetLock(uint32_t Lock)
+{
+ OPAMP->LOCK = Lock;
+}
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_pwr.c b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_pwr.c
new file mode 100644
index 0000000000..b129980b39
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_pwr.c
@@ -0,0 +1,576 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_pwr.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_pwr.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup PWR
+ * @brief PWR driver modules
+ * @{
+ */
+
+/** @addtogroup PWR_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Private_Defines
+ * @{
+ */
+
+/* --------- PWR registers bit address in the alias region ---------- */
+#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
+
+/* --- CTRL Register ---*/
+
+/* Alias word address of DBKP bit */
+#define CTRL_OFFSET (PWR_OFFSET + 0x00)
+#define DBKP_BITN 0x08
+#define CTRL_DBKP_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (DBKP_BITN * 4))
+
+/* Alias word address of PVDEN bit */
+#define PVDEN_BITN 0x04
+#define CTRL_PVDEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (PVDEN_BITN * 4))
+
+/* --- CTRLSTS Register ---*/
+
+/* Alias word address of WKUPEN bit */
+#define CTRLSTS_OFFSET (PWR_OFFSET + 0x04)
+#define WKUPEN_BITN 0x08
+#define CTRLSTS_WKUPEN_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (WKUPEN_BITN * 4))
+
+/* ------------------ PWR registers bit mask ------------------------ */
+
+
+void SetSysClock_MSI(void);
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the PWR peripheral registers to their default reset values.
+ */
+void PWR_DeInit(void)
+{
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_PWR, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_PWR, DISABLE);
+}
+
+/**
+ * @brief Enables or disables access to the RTC and backup registers.
+ * @param Cmd new state of the access to the RTC and backup registers.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void PWR_BackupAccessEnable(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)CTRL_DBKP_BB = (uint32_t)Cmd;
+}
+/**
+ * @brief MR voltage selection.
+ * @param voltage value: 1.0V and 1.1V.
+ * This parameter can be: MR_1V0 or MR_1V1.
+ */
+void PWR_MRconfig(uint8_t voltage)
+{
+ uint32_t tmpreg = 0;
+
+ tmpreg = PWR->CTRL1;
+ /* Clear MRSEL bits */
+ tmpreg &= (~PWR_CTRL1_MRSELMASK);
+ /* Set voltage*/
+ tmpreg |= (uint32_t)(voltage << 9);
+ PWR->CTRL1 = tmpreg;
+}
+/**
+ * @brief Get MR voltage value.
+ * @param voltage value: 1.0V and 1.1V.
+ * @return The value of voltage.
+ */
+uint8_t GetMrVoltage(void)
+{
+ uint8_t tmp = 0;
+
+ tmp = (uint8_t)((PWR->CTRL1 >> 9) & 0x03);//2bits
+ return tmp ;
+}
+/**
+ * @brief Enables or disables the Power Voltage Detector(PVD).
+ * @param Cmd new state of the PVD.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void PWR_PvdEnable(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ //*(__IO uint32_t*)CTRL_PVDEN_BB = (uint32_t)Cmd; //Can not enable the PVD bit
+ PWR->CTRL2 |= Cmd;
+
+}
+
+/**
+ * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+ * @param PWR_PVDLevel: specifies the PVD detection level
+ * This parameter can be one of the following values:
+ * @arg PWR_CTRL2_PLS1: PVD detection level set to 2.1V
+ * @arg PWR_CTRL2_PLS2: PVD detection level set to 2.25V
+ * @arg PWR_CTRL2_PLS3: PVD detection level set to 2.4V
+ * @arg PWR_CTRL2_PLS4: PVD detection level set to 2.55V
+ * @arg PWR_CTRL2_PLS5: PVD detection level set to 2.7V
+ * @arg PWR_CTRL2_PLS6: PVD detection level set to 2.85V
+ * @arg PWR_CTRL2_PLS7: PVD detection level set to 2.95V
+ * @arg PWR_CTRL2_PLS8: external input analog voltage PVD_IN (compared internally to VREFINT)
+ * @retval None
+ */
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
+ tmpregister = PWR->CTRL2;
+ /* Clear PLS[7:5] bits */
+ tmpregister &= (~PWR_CTRL2_PLSMASK);
+ /* Set PRS[7:5] bits according to PWR_PVDLevel value */
+ tmpregister |= PWR_PVDLevel;
+ /* Store the new value */
+ PWR->CTRL2 = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the WakeUp Pin functionality.
+ * @param Pin: which PIN select to wakeup.
+ * This parameter can be one of the following values:
+ * @arg WAKEUP_PIN0
+ * @arg WAKEUP_PIN1
+ * @arg WAKEUP_PIN2
+ * @param Cmd new state of the WakeUp Pin functionality.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void PWR_WakeUpPinEnable(WAKEUP_PINX WKUP_Pin,FunctionalState Cmd)
+{
+ uint32_t Temp = 0;
+ Temp = PWR->CTRL3;
+ if (ENABLE==Cmd)
+ {
+ Temp &= (~(PWR_CTRL3_WKUP0EN|PWR_CTRL3_WKUP1EN|PWR_CTRL3_WKUP2EN));
+ Temp |= (WKUP_Pin);
+ PWR->CTRL3 = Temp;
+ }
+ else
+ {
+ Temp &= (~(WKUP_Pin));
+ PWR->CTRL3 = Temp;
+ }
+}
+
+
+
+
+/**
+ * @brief Enters SLEEP mode.
+ * @param SLEEPONEXIT: specifies the SLEEPONEXIT state in SLEEP mode.
+ * This parameter can be one of the following values:
+ * @arg 0: SLEEP mode with SLEEPONEXIT disable
+ * @arg 1: SLEEP mode with SLEEPONEXIT enable
+ * @param PWR_STOPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.
+ * This parameter can be one of the following values:
+ * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction
+ * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction
+ * @retval None
+ */
+void PWR_EnterSLEEPMode(uint8_t SLEEPONEXIT, uint8_t PWR_SLEEPEntry)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));
+
+ /* CLEAR SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
+
+ /* Select SLEEPONEXIT mode entry --------------------------------------------------*/
+ if (SLEEPONEXIT == 1)
+ {
+ /* the MCU enters Sleep mode as soon as it exits the lowest priority ISR */
+ SCB->SCR |= SCB_SCR_SLEEPONEXIT;
+ }
+ else if (SLEEPONEXIT == 0)
+ {
+ /* Sleep-now */
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPONEXIT);
+ }
+
+ /* Select SLEEP mode entry --------------------------------------------------*/
+ if (PWR_SLEEPEntry == PWR_SLEEPENTRY_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+}
+
+
+
+/**
+ * @brief Enters STOP2 mode.
+ * @param PWR_STOPEntry specifies if STOP2 mode in entered with WFI or WFE instruction.
+ * This parameter can be one of the following values:
+ * @arg PWR_STOPENTRY_WFI enter STOP2 mode with WFI instruction
+ * @arg PWR_STOPENTRY_WFE enter STOP2 mode with WFE instruction
+ * @param RetentionMode: PWR_CTRL3_RAM1RET or PWR_CTRL3_RAM2RET
+ */
+void PWR_EnterSTOP2Mode(uint8_t PWR_STOPEntry,uint32_t RetentionMode)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
+ /* Wait MR Voltage Adjust Complete */
+ while ((PWR->STS2 &0X2) != 2);
+ tmpreg = PWR->CTRL3;
+ /* Clear SRAMRET bits */
+ tmpreg &= (~PWR_CTRL3_RAMRETMASK);
+ /* Set SRAM1/2 select */
+ tmpreg |= RetentionMode;
+ PWR->CTRL3 = tmpreg;
+ /* Select the regulator state in STOP2 mode ---------------------------------*/
+ tmpreg = PWR->CTRL1;
+ /* Clear LPMS bits */
+ tmpreg &= (~PWR_CTRL1_LPMSELMASK);
+ /* Set stop2 mode select */
+ tmpreg |= PWR_CTRL1_STOP2;
+ /* Store the new value */
+ PWR->CTRL1 = tmpreg;
+ /*Clear PWR_CTRL3_PBDTSTP2 for BOR always on*/
+ tmpreg = PWR->CTRL3;
+ tmpreg &= (~PWR_CTRL3_PBDTSTP2);
+ PWR->CTRL3 = tmpreg;
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP;
+
+ /* Select STOP mode entry --------------------------------------------------*/
+ if (PWR_STOPEntry == PWR_STOPENTRY_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
+}
+
+
+/**
+ * @brief Enters Low power run mode.
+ * @param
+ * @arg
+ * @arg
+ * @retval None
+ */
+void PWR_EnterLowPowerRunMode(void)
+{
+ uint32_t tmpreg = 0;
+
+ SetSysClock_MSI();
+ FLASH_SetLatency(FLASH_LATENCY_2); //Configure the Flash read latency to be grater than 2, so LVE/SE timing requirement is guaranteed
+ //config FLASH enter the low power voltage mode
+ FLASH->AC |= FLASH_AC_LVMEN;
+ while ((FLASH->AC & FLASH_AC_LVMF) != FLASH_AC_LVMF);
+ FLASH_SetLatency(FLASH_LATENCY_0); //Configure the latency of Flash read cycle to proper value which depends on the Flash read access time.
+
+ _SetLprunSramVoltage(0);
+ _SetBandGapMode(0);
+ _SetPvdBorMode(0);
+ /* Select the regulator state in LPRUN mode ---------------------------------*/
+ tmpreg = PWR->CTRL1;
+ /* Clear LPMS bits */
+ tmpreg &= (~PWR_CTRL1_LPMSELMASK);
+ /* Set lpr to run the main power domain*/
+ tmpreg |= PWR_CTRL1_LPREN;
+ /* Store the new value */
+ PWR->CTRL1 = tmpreg;
+ /*Clear PWR_CTRL3_PBDTLPR for BOR always on*/
+ tmpreg = PWR->CTRL3;
+ tmpreg &= (~PWR_CTRL3_PBDTLPR);
+ PWR->CTRL3 = tmpreg;
+ while ((PWR->STS2 &PWR_STS2_LPRUNF) != 0);//LPRCNT flag ready
+}
+
+/**
+ * @brief Enters Low power run mode.
+ * @param
+ * @arg
+ * @arg
+ * @retval None
+ */
+void PWR_ExitLowPowerRunMode(void)
+{
+ PWR->CTRL1 &= ~PWR_CTRL1_LPREN;
+ while ((PWR->STS2 &PWR_STS2_LPRUNF) != PWR_STS2_LPRUNF);
+ FLASH_SetLatency(FLASH_LATENCY_2); //Configure the Flash read latency to be grater than 2, so LVE/SE timing requirement is guaranteed
+ FLASH->AC &= ~FLASH_AC_LVMEN; //clear LVMREQ
+ while ((FLASH->AC &FLASH_AC_LVMF) != 0); //wait LVE is deasserted by polling the LVMVLD bit
+
+ FLASH_SetLatency(FLASH_LATENCY_0); //Configure the latency of Flash read cycle to proper value which depends on the Flash read access time.
+}
+
+/**
+ * @brief Enters LP_SLEEP mode.
+ * @param SLEEPONEXIT: specifies the SLEEPONEXIT state in SLEEP mode.
+ * This parameter can be one of the following values:
+ * @arg 0: SLEEP mode with SLEEPONEXIT disable
+ * @arg 1: SLEEP mode with SLEEPONEXIT enable
+ * @param PWR_STOPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.
+ * This parameter can be one of the following values:
+ * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction
+ * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction
+ * @retval None
+ */
+void PWR_EnterLowPowerSleepMode(uint8_t SLEEPONEXIT, uint8_t PWR_SLEEPEntry)
+{
+ PWR_EnterLowPowerRunMode();
+ PWR_EnterSLEEPMode(SLEEPONEXIT, PWR_SLEEPEntry);
+}
+
+ /**
+ * @brief Enters STANDBY mode.
+ * @param PWR_STANDBYEntry: specifies if STANDBY mode in entered with WFI or WFE instruction.
+ * This parameter can be one of the following values:
+ * @arg PWR_STANDBYEntry_WFI: enter STANDBY mode with WFI instruction
+ * @arg PWR_CTRL3_RAM2RET: SRAM2 whether to retention
+ * @retval None
+ */
+void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry,uint32_t Sam2Ret)
+{
+ uint32_t tmpreg;
+ /* Clear Wake-up flag */
+ PWR->STSCLR |= PWR_STSCLR_CLRWKUP0;
+ PWR->STSCLR |= PWR_STSCLR_CLRWKUP1;
+ PWR->STSCLR |= PWR_STSCLR_CLRWKUP2;
+ tmpreg = PWR->CTRL3;
+ /* Clear SRAMRET bits */
+ tmpreg &= (~PWR_CTRL3_RAMRETMASK);
+ /* Set SRAM1/2 select */
+ tmpreg |= Sam2Ret;
+ PWR->CTRL3 = tmpreg;
+
+ tmpreg = PWR->CTRL1;
+ /* Clear LPMS bits */
+ tmpreg &= (~PWR_CTRL1_LPMSELMASK);
+ /* Select STANDBY mode */
+ tmpreg |= PWR_CTRL1_STANDBY;
+ PWR->CTRL1 = tmpreg;
+ /*Clear PWR_CTRL3_PBDTSTBY for BOR always on*/
+ tmpreg = PWR->CTRL3;
+ tmpreg &= (~PWR_CTRL3_PBDTSTBY);
+ PWR->CTRL3 = tmpreg;
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP;
+/* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM )
+ __force_stores();
+#endif
+ /* Select STANDBY mode entry --------------------------------------------------*/
+ if (PWR_STANDBYEntry == PWR_STOPENTRY_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+}
+
+
+
+/**
+ * @brief Checks whether the specified PWR flag is set or not.
+ * @param PWR_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg PWR_WKUP0_FLAG/PWR_WKUP1_FLAG/PWR_WKUP2_FLAG: Wake Up flag
+ * @arg PWR_STBY_FLAG: StandBy flag
+ * @arg PWR_LPRUN_FLAG: low power work flag
+ * @arg PWR_MR_FLAG: MR work statue flag
+ * @arg PWR_PVDO_FLAG: PVD output flag
+ * @retval The new state of PWR_FLAG (SET or RESET).
+ */
+FlagStatus PWR_GetFlagStatus(uint8_t STS,uint32_t PWR_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
+ if (STS == 1)
+ {
+ if ((PWR->STS1 & PWR_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ }
+ else
+ {
+ if ((PWR->STS2 & PWR_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ }
+
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the PWR's pending flags.
+ * @param PWR_FLAG specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg PWR_WKUP1_FLAG/PWR_WKUP2_FLAG/PWR_WKUP3_FLAG: Wake Up flag
+ * @arg PWR_STBY_FLAG: StandBy flag
+ */
+void PWR_ClearFlag(uint32_t PWR_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
+
+ PWR->STSCLR |= PWR_FLAG ;
+}
+
+
+/**
+ * @brief set system clock with MSI.
+ * @param void.
+ */
+void SetSysClock_MSI(void)
+{
+ RCC_DeInit();
+
+ if (RESET == RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_MSIRD))
+ {
+ /* Enable MSI and Config Clock */
+ RCC_ConfigMsi(RCC_MSI_ENABLE, RCC_MSI_RANGE_4M);
+ /* Waits for MSI start-up */
+ while (SUCCESS != RCC_WaitMsiStable());
+ }
+
+ /* Enable Prefetch Buffer */
+ FLASH_PrefetchBufSet(FLASH_PrefetchBuf_EN);
+
+ /* Select MSI as system clock source */
+ RCC_ConfigSysclk(RCC_SYSCLK_SRC_MSI);
+
+ /* Wait till MSI is used as system clock source */
+ while (RCC_GetSysclkSrc() != 0x00)
+ {
+ }
+
+ /* Flash 0 wait state */
+ //FLASH_SetLatency(FLASH_LATENCY_0);
+
+ /* HCLK = SYSCLK */
+ RCC_ConfigHclk(RCC_SYSCLK_DIV1);
+
+ /* PCLK2 = HCLK */
+ RCC_ConfigPclk2(RCC_HCLK_DIV1);
+
+ /* PCLK1 = HCLK */
+ RCC_ConfigPclk1(RCC_HCLK_DIV1);
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_rcc.c b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_rcc.c
new file mode 100644
index 0000000000..1f4a4e9c79
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_rcc.c
@@ -0,0 +1,1940 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_rcc.c
+ * @author Nations
+ * @version v1.0.3
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_rcc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RCC
+ * @brief RCC driver modules
+ * @{
+ */
+
+/** @addtogroup RCC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_Defines
+ * @{
+ */
+
+/* ------------ RCC registers bit address in the alias region ----------- */
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
+
+/* --- CTRL Register ---*/
+
+/* Alias word address of HSIEN bit */
+#define CTRL_OFFSET (RCC_OFFSET + 0x00)
+#define HSIEN_BITN 0x00
+#define CTRL_HSIEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (HSIEN_BITN * 4))
+
+/* Alias word address of PLLEN bit */
+#define PLLEN_BITN 0x18
+#define CTRL_PLLEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (PLLEN_BITN * 4))
+
+/* Alias word address of CLKSSEN bit */
+#define CLKSSEN_BITN 0x13
+#define CTRL_CLKSSEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (CLKSSEN_BITN * 4))
+
+/* --- CFG Register ---*/
+
+/* Alias word address of USBPRES bit */
+#define CFG_OFFSET (RCC_OFFSET + 0x04)
+
+#define USBPRES_BITN 0x16
+#define CFG_USBPRES_BB (PERIPH_BB_BASE + (CFG_OFFSET * 32) + (USBPRES_BITN * 4))
+
+#define USBPRE_Bit1Number 0x17
+#define CFGR_USBPRE_BB_BIT1 (PERIPH_BB_BASE + (CFG_OFFSET * 32) + (USBPRE_Bit1Number * 4))
+
+/* --- CLKINT Register ---*/
+
+#define CLKINT_OFFSET (RCC_OFFSET + 0x08)
+
+/* Alias word address of LSIRDIF bit */
+#define LSIRDIF_BITN 0x00
+#define CLKINT_LSIRDIF_BB (PERIPH_BB_BASE + (CLKINT_OFFSET * 32) + (LSIRDIF_BITN * 4))
+
+/* --- LDCTRL Register ---*/
+
+/* Alias word address of LSECLKSSEN bit */
+#define LSECLKSSEN_BITN 0x03
+#define LDCTRL_LSECLKSSEN_BB (PERIPH_BB_BASE + (LDCTRL_OFFSET * 32) + (LSECLKSSEN_BITN * 4))
+
+/* Alias word address of RTCEN bit */
+#define LDCTRL_OFFSET (RCC_OFFSET + 0x20)
+#define RTCEN_BITN 0x0F
+#define LDCTRL_RTCEN_BB (PERIPH_BB_BASE + (LDCTRL_OFFSET * 32) + (RTCEN_BITN * 4))
+
+/* Alias word address of LDSFTRST bit */
+#define LDSFTRST_BITN 0x10
+#define LDCTRL_LDSFTRST_BB (PERIPH_BB_BASE + (LDCTRL_OFFSET * 32) + (LDSFTRST_BITN * 4))
+
+/* --- CTRLSTS Register ---*/
+
+/* Alias word address of LSIEN bit */
+#define CTRLSTS_OFFSET (RCC_OFFSET + 0x24)
+#define LSIEN_BITNUMBER 0x00
+#define CTRLSTS_LSIEN_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (LSIEN_BITNUMBER * 4))
+
+/* Alias word address of MSIEN bit */
+#define MSIEN_BITNUMBER 0x02
+#define CTRLSTS_MSIEN_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (MSIEN_BITNUMBER * 4))
+
+/* ---------------------- RCC registers bit mask ------------------------ */
+
+/* CTRL register bit mask */
+#define CTRL_HSEBP_RESET ((uint32_t)0xFFFBFFFF)
+#define CTRL_HSEBP_SET ((uint32_t)0x00040000)
+#define CTRL_HSEEN_RESET ((uint32_t)0xFFFEFFFF)
+#define CTRL_HSEEN_SET ((uint32_t)0x00010000)
+#define CTRL_HSITRIM_MASK ((uint32_t)0xFFFFFF83)
+#define CTRL_HSIEN_RESET ((uint32_t)0xFFFFFFFE)
+#define CTRL_HSIEN_SET ((uint32_t)0x00000001)
+
+/* CTRLSTS register bit mask */
+#define CTRLSTS_MSITRIM_MASK ((uint32_t)0xFF807FFF)
+#define CTRLSTS_MSIEN_RESET ((uint32_t)0xFFFFFFFB)
+#define CTRLSTS_MSIEN_SET ((uint32_t)0x00000004)
+
+#define CTRLSTS_MSIRANGE_MASK ((uint32_t)0xFFFFFF8F)
+#define CTRLSTS_MSIRANGE_RESET ((uint32_t)0x00000060) /* 4MHz */
+
+/* CFG register bit mask */
+#define CFG_PLL_MASK ((uint32_t)0xF7C0FFFF)
+
+#define CFG_PLLMULFCT_MASK ((uint32_t)0x083C0000)
+#define CFG_PLLSRC_MASK ((uint32_t)0x00010000)
+#define CFG_PLLHSEPRES_MASK ((uint32_t)0x00020000)
+#define CFG_SCLKSTS_MASK ((uint32_t)0x0000000C)
+#define CFG_SCLKSW_MASK ((uint32_t)0xFFFFFFFC)
+#define CFG_AHBPRES_RESET_MASK ((uint32_t)0xFFFFFF0F)
+#define CFG_AHBPRES_SET_MASK ((uint32_t)0x000000F0)
+#define CFG_APB1PRES_RESET_MASK ((uint32_t)0xFFFFF8FF)
+#define CFG_APB1PRES_SET_MASK ((uint32_t)0x00000700)
+#define CFG_APB2PRES_RESET_MASK ((uint32_t)0xFFFFC7FF)
+#define CFG_APB2PRES_SET_MASK ((uint32_t)0x00003800)
+
+/* CFG2 register bit mask */
+#define CFG2_TIM18CLKSEL_SET_MASK ((uint32_t)0x20000000)
+#define CFG2_TIM18CLKSEL_RESET_MASK ((uint32_t)0xDFFFFFFF)
+#define CFG2_RNGCPRES_SET_MASK ((uint32_t)0x1F000000)
+#define CFG2_RNGCPRES_RESET_MASK ((uint32_t)0xE0FFFFFF)
+#define CFG2_ETHCLKSEL_SET_MASK ((uint32_t)0x00100000)
+#define CFG2_ETHCLKSEL_RESET_MASK ((uint32_t)0xFFEFFFFF)
+#define CFG2_ADC1MSEL_SET_MASK ((uint32_t)0x00020000)
+#define CFG2_ADC1MSEL_RESET_MASK ((uint32_t)0xFFFDFFFF)
+#define CFG2_ADC1MPRES_SET_MASK ((uint32_t)0x0001F000)
+#define CFG2_ADC1MPRES_RESET_MASK ((uint32_t)0xFFFE0FFF)
+#define CFG2_ADCPLLPRES_SET_MASK ((uint32_t)0x000001F0)
+#define CFG2_ADCPLLPRES_RESET_MASK ((uint32_t)0xFFFFFE0F)
+#define CFG2_ADCHPRES_SET_MASK ((uint32_t)0x0000000F)
+#define CFG2_ADCHPRES_RESET_MASK ((uint32_t)0xFFFFFFF0)
+
+/* CFG3 register bit mask */
+#define CFGR3_TRNG1MSEL_SET_MASK ((uint32_t)0x00020000)
+#define CFGR3_TRNG1MSEL_RESET_MASK ((uint32_t)0xFFFDFFFF)
+#define CFGR3_TRNG1MPRES_SET_MASK ((uint32_t)0x0000F800)
+#define CFGR3_TRNG1MPRES_RESET_MASK ((uint32_t)0xFFFF07FF)
+
+/* CTRLSTS register bit mask */
+#define CSR_RMRSTF_SET ((uint32_t)0x01000000)
+#define CSR_RMVF_Reset ((uint32_t)0xfeffffff)
+
+/* RCC Flag Mask */
+#define FLAG_MASK ((uint8_t)0x1F)
+
+/* CLKINT register(Bits[31:0]) base address */
+#define CLKINT_ADDR ((uint32_t)0x40021008)
+
+/* LDCTRL register base address */
+#define LDCTRL_ADDR (PERIPH_BASE + LDCTRL_OFFSET)
+
+/* RDCTRL register bit mask */
+#define RDCTRL_LPTIMCLKSEL_MASK ((uint32_t)0x00000007)
+#define RDCTRL_LPUARTCLKSEL_MASK ((uint32_t)0x00000018)
+
+/* PLLHSIPRE register bit mask */
+#define PLLHSIPRE_PLLHSI_PRE_MASK ((uint32_t)0x00000001)
+#define PLLHSIPRE_PLLSRCDIV_MASK ((uint32_t)0x00000002)
+
+#define LSE_TRIMR_ADDR ((uint32_t)0x40001808)
+
+#define LSE_GM_MASK_VALUE (0x1FF)
+#define LSE_GM_MAX_VALUE (0x1FF)
+#define LSE_GM_DEFAULT_VALUE (0x1FF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_Variables
+ * @{
+ */
+
+static const uint8_t s_ApbAhbPresTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+static const uint8_t s_AdcHclkPresTable[16] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 32, 32, 32, 32, 32, 32, 32};
+static const uint16_t s_AdcPllClkPresTable[16] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256, 256, 256, 256, 256};
+static const uint32_t s_msiClockTable[7] = {MSI_VALUE_L0, MSI_VALUE_L1, MSI_VALUE_L2, MSI_VALUE_L3,
+ MSI_VALUE_L4, MSI_VALUE_L5, MSI_VALUE_L6};
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Resets the RCC clock configuration to the default reset state.
+ */
+void RCC_DeInit(void)
+{
+ /* Set MSIEN bit */
+ RCC->CTRLSTS |= (uint32_t)0x00000004;
+
+ /* Reset SW, HPRE, PPRE1, PPRE2 and MCO bits */
+ RCC->CFG &= (uint32_t)0xF8FFC000;
+
+ /* Reset HSIEN, HSEEN, CLKSSEN and PLLEN bits */
+ RCC->CTRL &= (uint32_t)0xFEF6FFFE;
+
+ /* Reset HSEBYP bit */
+ RCC->CTRL &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRES bits */
+ RCC->CFG &= (uint32_t)0xF700FFFF;
+
+ /* Reset CFG2 register */
+ RCC->CFG2 = 0x00007000;
+
+ /* Reset CFG3 register */
+ RCC->CFG3 = 0x00003800;
+
+ /* Reset RDCTRL register */
+ RCC->RDCTRL = 0x00000000;
+
+ /* Reset PLLHSIPRE register */
+ RCC->PLLHSIPRE = 0x00000000;
+
+ /* Disable all interrupts and clear pending bits */
+ RCC->CLKINT = 0x04BF8000;
+}
+
+/**
+ * @brief Configures the External High Speed oscillator (HSE).
+ * @note HSE can not be stopped if it is used directly or through the PLL as system clock.
+ * @param RCC_HSE specifies the new state of the HSE.
+ * This parameter can be one of the following values:
+ * @arg RCC_HSE_DISABLE HSE oscillator OFF
+ * @arg RCC_HSE_ENABLE HSE oscillator ON
+ * @arg RCC_HSE_BYPASS HSE oscillator bypassed with external clock
+ */
+void RCC_ConfigHse(uint32_t RCC_HSE)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_HSE(RCC_HSE));
+ /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
+ /* Reset HSEON bit */
+ RCC->CTRL &= CTRL_HSEEN_RESET;
+ /* Reset HSEBYP bit */
+ RCC->CTRL &= CTRL_HSEBP_RESET;
+ /* Configure HSE (RCC_HSE_DISABLE is already covered by the code section above) */
+ switch (RCC_HSE)
+ {
+ case RCC_HSE_ENABLE:
+ /* Set HSEEN bit */
+ RCC->CTRL |= CTRL_HSEEN_SET;
+ break;
+
+ case RCC_HSE_BYPASS:
+ /* Set HSEBYP and HSEEN bits */
+ RCC->CTRL |= CTRL_HSEBP_SET | CTRL_HSEEN_SET;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Waits for HSE start-up.
+ * @return An ErrorStatus enumuration value:
+ * - SUCCESS: HSE oscillator is stable and ready to use
+ * - ERROR: HSE oscillator not yet ready
+ */
+ErrorStatus RCC_WaitHseStable(void)
+{
+ __IO uint32_t StartUpCounter = 0;
+ ErrorStatus status = ERROR;
+ FlagStatus HSEStatus = RESET;
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC_GetFlagStatus(RCC_CTRL_FLAG_HSERDF);
+ StartUpCounter++;
+ } while ((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
+
+ if (RCC_GetFlagStatus(RCC_CTRL_FLAG_HSERDF) != RESET)
+ {
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+ return (status);
+}
+
+/**
+ * @brief Configures the Internal High Speed oscillator (HSI).
+ * @note HSI can not be stopped if it is used directly or through the PLL as system clock.
+ * @param RCC_HSI specifies the new state of the HSI.
+ * This parameter can be one of the following values:
+ * @arg RCC_HSI_DISABLE HSI oscillator OFF
+ * @arg RCC_HSI_ENABLE HSI oscillator ON
+ */
+void RCC_ConfigHsi(uint32_t RCC_HSI)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_HSI(RCC_HSI));
+ /* Reset HSIEN bit */
+ RCC->CTRL &= CTRL_HSIEN_RESET;
+ /* Configure HSI */
+ switch (RCC_HSI)
+ {
+ case RCC_HSI_ENABLE:
+ /* Set HSIEN bit */
+ RCC->CTRL |= CTRL_HSIEN_SET;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Waits for HSI start-up.
+ * @return An ErrorStatus enumuration value:
+ * - SUCCESS: HSI oscillator is stable and ready to use
+ * - ERROR: HSI oscillator not yet ready
+ */
+ErrorStatus RCC_WaitHsiStable(void)
+{
+ __IO uint32_t StartUpCounter = 0;
+ ErrorStatus status = ERROR;
+ FlagStatus HSIStatus = RESET;
+
+ /* Wait till HSI is ready and if Time out is reached exit */
+ do
+ {
+ HSIStatus = RCC_GetFlagStatus(RCC_CTRL_FLAG_HSIRDF);
+ StartUpCounter++;
+ } while ((StartUpCounter != HSI_STARTUP_TIMEOUT) && (HSIStatus == RESET));
+
+ if (RCC_GetFlagStatus(RCC_CTRL_FLAG_HSIRDF) != RESET)
+ {
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+ return (status);
+}
+
+/**
+ * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
+ * @param HSICalibrationValue specifies the calibration trimming value.
+ * This parameter must be a number between 0 and 0x1F.
+ */
+void RCC_SetHsiCalibValue(uint8_t HSICalibrationValue)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_CALIB_VALUE(HSICalibrationValue));
+ tmpregister = RCC->CTRL;
+ /* Clear HSITRIM[4:0] bits */
+ tmpregister &= CTRL_HSITRIM_MASK;
+ /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
+ tmpregister |= (uint32_t)HSICalibrationValue << 2;
+ /* Store the new value */
+ RCC->CTRL = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the Internal High Speed oscillator (HSI).
+ * @note HSI can not be stopped if it is used directly or through the PLL as system clock.
+ * @param Cmd new state of the HSI. This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableHsi(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)CTRL_HSIEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Configures the Multi Speed oscillator (MSI).
+ * @param RCC_MSI specifies the new state of the MSI.
+ * This parameter can be one of the following values:
+ * @arg RCC_MSI_DISABLE MSI oscillator OFF
+ * @arg RCC_MSI_ENABLE MSI oscillator ON
+ * @param RCC_MSI_Range specifies the clock of the MSI.
+ * This parameter can be one of the following values:
+ * @arg RCC_MSI_RANGE_100K 100KHz
+ * @arg RCC_MSI_RANGE_200K 200KHz
+ * @arg RCC_MSI_RANGE_400K 400KHz
+ * @arg RCC_MSI_RANGE_800K 800KHz
+ * @arg RCC_MSI_RANGE_1M 1MHz
+ * @arg RCC_MSI_RANGE_2M 2MHz
+ * @arg RCC_MSI_RANGE_4M 4MHz
+ */
+void RCC_ConfigMsi(uint32_t RCC_MSI, uint32_t RCC_MSI_Range)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_MSI(RCC_MSI));
+ assert_param(IS_RCC_MSI_RANGE(RCC_MSI_Range));
+ /* Set MSIRANGE[2:0] bit */
+ RCC->CTRLSTS &= CTRLSTS_MSIRANGE_MASK;
+ RCC->CTRLSTS |= RCC_MSI_Range;
+ /* Configure MSI */
+ switch (RCC_MSI)
+ {
+ case RCC_MSI_ENABLE:
+ /* Set MSIEN bit */
+ RCC->CTRLSTS |= CTRLSTS_MSIEN_SET;
+ break;
+ case RCC_MSI_DISABLE:
+ /* Reset MSIEN bit */
+ RCC->CTRLSTS &= CTRLSTS_MSIEN_RESET;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Waits for MSI start-up.
+ * @return An ErrorStatus enumuration value:
+ * - SUCCESS: MSI oscillator is stable and ready to use
+ * - ERROR: MSI oscillator not yet ready
+ */
+ErrorStatus RCC_WaitMsiStable(void)
+{
+ __IO uint32_t StartUpCounter = 0;
+ ErrorStatus status = ERROR;
+ FlagStatus MSIStatus = RESET;
+
+ /* Wait till MSI is ready and if Time out is reached exit */
+ do
+ {
+ MSIStatus = RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_MSIRD);
+ StartUpCounter++;
+ } while ((StartUpCounter != MSI_STARTUP_TIMEOUT) && (MSIStatus == RESET));
+
+ if (RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_MSIRD) != RESET)
+ {
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+ return (status);
+}
+
+/**
+ * @brief Adjusts the Multi Speed oscillator (MSI) calibration value.
+ * @param MSICalibrationValue specifies the calibration trimming value.
+ * This parameter must be a number between 0 and 0xFF.
+ */
+void RCC_SetMsiCalibValue(uint8_t MSICalibrationValue)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ //assert_param(IS_RCC_MSICALIB_VALUE(MSICalibrationValue));
+ tmpregister = RCC->CTRLSTS;
+ /* Clear MSITRIM[7:0] bits */
+ tmpregister &= CTRLSTS_MSITRIM_MASK;
+ /* Set the MSITRIM[7:0] bits according to MSICalibrationValue value */
+ tmpregister |= (uint32_t)MSICalibrationValue << 15;
+ /* Store the new value */
+ RCC->CTRLSTS = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the Multi Speed oscillator (MSI).
+ * @param Cmd new state of the MSI. This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableMsi(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)CTRLSTS_MSIEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Configures the PLL clock source and multiplication factor.
+ * @note This function must be used only when the PLL is disabled.
+ * @param RCC_PLLSource specifies the PLL entry clock source.
+ * this parameter can be one of the following values:
+ * @arg RCC_PLL_HSI_PRE_DIV1 HSI oscillator clock selected as PLL clock entry
+ * @arg RCC_PLL_HSI_PRE_DIV2 HSI oscillator clock divided by 2 selected as PLL clock entry
+ * @arg RCC_PLL_SRC_HSE_DIV1 HSE oscillator clock selected as PLL clock entry
+ * @arg RCC_PLL_SRC_HSE_DIV2 HSE oscillator clock divided by 2 selected as PLL clock entry
+ * @param RCC_PLLMul specifies the PLL multiplication factor.
+ * this parameter can be RCC_PLLMul_x where x:[2,32]
+ * @param RCC_PLLDIVCLK specifies the PLL divider feedback clock source.
+ * this parameter can be one of the following values:
+ * @arg RCC_PLLDIVCLK_DISABLE PLLSource clock selected as PLL clock entry
+ * @arg RCC_PLLDIVCLK_ENABLE PLLSource clock divided by 2 selected as PLL clock entry
+ */
+void RCC_ConfigPll(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul, uint32_t RCC_PLLDIVCLK)
+{
+ uint32_t tmpregister = 0;
+ uint32_t pllhsipreregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL_SRC(RCC_PLLSource));
+ assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
+ assert_param(IS_RCC_PLL_DIVCLK(RCC_PLLDIVCLK));
+
+ tmpregister = RCC->CFG;
+ pllhsipreregister = RCC->PLLHSIPRE;
+ /* Clear PLLSRC, PLLXTPRE and PLLMUL[4:0] bits */
+ tmpregister &= CFG_PLL_MASK;
+ /* Clear PLLHSIPRE, PLLSRCDIV bits */
+ pllhsipreregister &= (~(PLLHSIPRE_PLLHSI_PRE_MASK | PLLHSIPRE_PLLSRCDIV_MASK));
+ /* Set the PLL configuration bits */
+ if ((RCC_PLLSource == RCC_PLL_HSI_PRE_DIV1) || (RCC_PLLSource == RCC_PLL_HSI_PRE_DIV2))
+ {
+ tmpregister |= RCC_PLLMul;
+ pllhsipreregister |= RCC_PLLSource | RCC_PLLDIVCLK;
+ }
+ /* (RCC_PLLSource == RCC_PLL_SRC_HSE_DIV1) || (RCC_PLLSource == RCC_PLL_SRC_HSE_DIV2) */
+ else
+ {
+ tmpregister |= RCC_PLLSource | RCC_PLLMul;
+ pllhsipreregister |= RCC_PLLDIVCLK;
+ }
+ /* Store the new value */
+ RCC->CFG = tmpregister;
+ RCC->PLLHSIPRE = pllhsipreregister;
+}
+
+/**
+ * @brief Enables or disables the PLL.
+ * @note The PLL can not be disabled if it is used as system clock.
+ * @param Cmd new state of the PLL. This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnablePll(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ *(__IO uint32_t*)CTRL_PLLEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Configures the system clock (SYSCLK).
+ * @param RCC_SYSCLKSource specifies the clock source used as system clock.
+ * This parameter can be one of the following values:
+ * @arg RCC_SYSCLK_SRC_MSI HSI selected as system clock
+ * @arg RCC_SYSCLK_SRC_HSI HSI selected as system clock
+ * @arg RCC_SYSCLK_SRC_HSE HSE selected as system clock
+ * @arg RCC_SYSCLK_SRC_PLLCLK PLL selected as system clock
+ */
+void RCC_ConfigSysclk(uint32_t RCC_SYSCLKSource)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_SYSCLK_SRC(RCC_SYSCLKSource));
+ tmpregister = RCC->CFG;
+ /* Clear SW[1:0] bits */
+ tmpregister &= CFG_SCLKSW_MASK;
+ /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
+ tmpregister |= RCC_SYSCLKSource;
+ /* Store the new value */
+ RCC->CFG = tmpregister;
+}
+
+/**
+ * @brief Returns the clock source used as system clock.
+ * @return The clock source used as system clock. The returned value can
+ * be one of the following:
+ * - 0x00: MSI used as system clock
+ * - 0x04: HSI used as system clock
+ * - 0x08: HSE used as system clock
+ * - 0x0C: PLL used as system clock
+ */
+uint8_t RCC_GetSysclkSrc(void)
+{
+ return ((uint8_t)(RCC->CFG & CFG_SCLKSTS_MASK));
+}
+
+/**
+ * @brief Configures the AHB clock (HCLK).
+ * @param RCC_SYSCLK defines the AHB clock divider. This clock is derived from
+ * the system clock (SYSCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_SYSCLK_DIV1 AHB clock = SYSCLK
+ * @arg RCC_SYSCLK_DIV2 AHB clock = SYSCLK/2
+ * @arg RCC_SYSCLK_DIV4 AHB clock = SYSCLK/4
+ * @arg RCC_SYSCLK_DIV8 AHB clock = SYSCLK/8
+ * @arg RCC_SYSCLK_DIV16 AHB clock = SYSCLK/16
+ * @arg RCC_SYSCLK_DIV64 AHB clock = SYSCLK/64
+ * @arg RCC_SYSCLK_DIV128 AHB clock = SYSCLK/128
+ * @arg RCC_SYSCLK_DIV256 AHB clock = SYSCLK/256
+ * @arg RCC_SYSCLK_DIV512 AHB clock = SYSCLK/512
+ */
+void RCC_ConfigHclk(uint32_t RCC_SYSCLK)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_SYSCLK_DIV(RCC_SYSCLK));
+ tmpregister = RCC->CFG;
+ /* Clear HPRE[3:0] bits */
+ tmpregister &= CFG_AHBPRES_RESET_MASK;
+ /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
+ tmpregister |= RCC_SYSCLK;
+ /* Store the new value */
+ RCC->CFG = tmpregister;
+}
+
+/**
+ * @brief Configures the Low Speed APB clock (PCLK1).
+ * @param RCC_HCLK defines the APB1 clock divider. This clock is derived from
+ * the AHB clock (HCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_HCLK_DIV1 APB1 clock = HCLK
+ * @arg RCC_HCLK_DIV2 APB1 clock = HCLK/2
+ * @arg RCC_HCLK_DIV4 APB1 clock = HCLK/4
+ * @arg RCC_HCLK_DIV8 APB1 clock = HCLK/8
+ * @arg RCC_HCLK_DIV16 APB1 clock = HCLK/16
+ */
+void RCC_ConfigPclk1(uint32_t RCC_HCLK)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_HCLK_DIV(RCC_HCLK));
+ tmpregister = RCC->CFG;
+ /* Clear PPRE1[2:0] bits */
+ tmpregister &= CFG_APB1PRES_RESET_MASK;
+ /* Set PPRE1[2:0] bits according to RCC_HCLK value */
+ tmpregister |= RCC_HCLK;
+ /* Store the new value */
+ RCC->CFG = tmpregister;
+}
+
+/**
+ * @brief Configures the High Speed APB clock (PCLK2).
+ * @param RCC_HCLK defines the APB2 clock divider. This clock is derived from
+ * the AHB clock (HCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_HCLK_DIV1 APB2 clock = HCLK
+ * @arg RCC_HCLK_DIV2 APB2 clock = HCLK/2
+ * @arg RCC_HCLK_DIV4 APB2 clock = HCLK/4
+ * @arg RCC_HCLK_DIV8 APB2 clock = HCLK/8
+ * @arg RCC_HCLK_DIV16 APB2 clock = HCLK/16
+ */
+void RCC_ConfigPclk2(uint32_t RCC_HCLK)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_HCLK_DIV(RCC_HCLK));
+ tmpregister = RCC->CFG;
+ /* Clear PPRE2[2:0] bits */
+ tmpregister &= CFG_APB2PRES_RESET_MASK;
+ /* Set PPRE2[2:0] bits according to RCC_HCLK value */
+ tmpregister |= RCC_HCLK << 3;
+ /* Store the new value */
+ RCC->CFG = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the specified RCC interrupts.
+ * @param RccInt specifies the RCC interrupt sources to be enabled or disabled.
+ *
+ * this parameter can be any combination of the following values
+ * @arg RCC_INT_LSIRDIF LSI ready interrupt
+ * @arg RCC_INT_LSERDIF LSE ready interrupt
+ * @arg RCC_INT_HSIRDIF HSI ready interrupt
+ * @arg RCC_INT_HSERDIF HSE ready interrupt
+ * @arg RCC_INT_PLLRDIF PLL ready interrupt
+ * @arg RCC_INT_BORIF BOR interrupt
+ * @arg RCC_INT_MSIRDIF MSI ready interrupt
+ *
+ * @param Cmd new state of the specified RCC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_ConfigInt(uint8_t RccInt, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_INT(RccInt));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Perform Byte access to RCC_CLKINT bits to enable the selected interrupts */
+ *(__IO uint32_t*)CLKINT_ADDR |= (((uint32_t)RccInt) << 8);
+ }
+ else
+ {
+ /* Perform Byte access to RCC_CLKINT bits to disable the selected interrupts */
+ *(__IO uint32_t*)CLKINT_ADDR &= (~(((uint32_t)RccInt) << 8));
+ }
+}
+
+/**
+ * @brief Configures the USB clock (USBCLK).
+ * @param RCC_USBCLKSource specifies the USB clock source. This clock is
+ * derived from the PLL output.
+ * This parameter can be one of the following values:
+ * @arg RCC_USBCLK_SRC_PLLCLK_DIV1_5 PLL clock divided by 1,5 selected as USB clock source
+ * @arg RCC_USBCLK_SRC_PLLCLK_DIV1 PLL clock divided by 1 selected as USB clock source
+ * @arg RCC_USBCLK_SRC_PLLCLK_DIV2 PLL clock divided by 2 selected as USB clock source
+ * @arg RCC_USBCLK_SRC_PLLCLK_DIV3 PLL clock divided by 3 selected as USB clock source
+ */
+void RCC_ConfigUsbClk(uint32_t RCC_USBCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_USBCLK_SRC(RCC_USBCLKSource));
+
+ *(__IO uint32_t*)CFG_USBPRES_BB = RCC_USBCLKSource;
+ *(__IO uint32_t*)CFGR_USBPRE_BB_BIT1 = RCC_USBCLKSource >> 1;
+}
+
+/**
+ * @brief Configures the TIM1/8 clock (TIM1/8CLK).
+ * @param RCC_TIM18CLKSource specifies the TIM1/8 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_TIM18CLK_SRC_TIM18CLK
+ * @arg RCC_TIM18CLK_SRC_SYSCLK
+ */
+void RCC_ConfigTim18Clk(uint32_t RCC_TIM18CLKSource)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_TIM18CLKSRC(RCC_TIM18CLKSource));
+
+ tmpregister = RCC->CFG2;
+ /* Clear TIMCLK_SEL bits */
+ tmpregister &= CFG2_TIM18CLKSEL_RESET_MASK;
+ /* Set TIMCLK_SEL bits according to RCC_TIM18CLKSource value */
+ tmpregister |= RCC_TIM18CLKSource;
+
+ /* Store the new value */
+ RCC->CFG2 = tmpregister;
+}
+
+/**
+ * @brief Configures the RNGCCLK prescaler.
+ * @param RCC_RNGCCLKPrescaler specifies the RNGCCLK prescaler.
+ * This parameter can be one of the following values:
+ * @arg RCC_RNGCCLK_SYSCLK_DIV1 RNGCPRE[24:28] = 00000, SYSCLK Divided By 1
+ * @arg RCC_RNGCCLK_SYSCLK_DIV2 RNGCPRE[24:28] = 00001, SYSCLK Divided By 2
+ * @arg RCC_RNGCCLK_SYSCLK_DIV3 RNGCPRE[24:28] = 00002, SYSCLK Divided By 3
+ * ...
+ * @arg RCC_RNGCCLK_SYSCLK_DIV31 RNGCPRE[24:28] = 11110, SYSCLK Divided By 31
+ * @arg RCC_RNGCCLK_SYSCLK_DIV32 RNGCPRE[24:28] = 11111, SYSCLK Divided By 32
+ */
+void RCC_ConfigRngcClk(uint32_t RCC_RNGCCLKPrescaler)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_RNGCCLKPRE(RCC_RNGCCLKPrescaler));
+
+ tmpregister = RCC->CFG2;
+ /* Clear RNGCPRE[3:0] bits */
+ tmpregister &= CFG2_RNGCPRES_RESET_MASK;
+ /* Set RNGCPRE[3:0] bits according to RCC_RNGCCLKPrescaler value */
+ tmpregister |= RCC_RNGCCLKPrescaler;
+
+ /* Store the new value */
+ RCC->CFG2 = tmpregister;
+}
+
+/**
+ * @brief Configures the ADCx 1M clock (ADC1MCLK).
+ * @param RCC_ADC1MCLKSource specifies the ADC1M clock source.
+ * This parameter can be on of the following values:
+ * @arg RCC_ADC1MCLK_SRC_HSI
+ * @arg RCC_ADC1MCLK_SRC_HSE
+ *
+ * @param RCC_ADC1MPrescaler specifies the ADC1M clock prescaler.
+ * This parameter can be on of the following values:
+ * @arg RCC_ADC1MCLK_DIV1 ADC1M clock = RCC_ADC1MCLKSource_xxx/1
+ * @arg RCC_ADC1MCLK_DIV2 ADC1M clock = RCC_ADC1MCLKSource_xxx/2
+ * @arg RCC_ADC1MCLK_DIV3 ADC1M clock = RCC_ADC1MCLKSource_xxx/3
+ * ...
+ * @arg RCC_ADC1MCLK_DIV31 ADC1M clock = RCC_ADC1MCLKSource_xxx/31
+ * @arg RCC_ADC1MCLK_DIV32 ADC1M clock = RCC_ADC1MCLKSource_xxx/32
+ */
+void RCC_ConfigAdc1mClk(uint32_t RCC_ADC1MCLKSource, uint32_t RCC_ADC1MPrescaler)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_ADC1MCLKSRC(RCC_ADC1MCLKSource));
+ assert_param(IS_RCC_ADC1MCLKPRE(RCC_ADC1MPrescaler));
+
+ tmpregister = RCC->CFG2;
+ /* Clear ADC1MSEL and ADC1MPRE[4:0] bits */
+ tmpregister &= CFG2_ADC1MSEL_RESET_MASK;
+ tmpregister &= CFG2_ADC1MPRES_RESET_MASK;
+ /* Set ADC1MSEL bits according to RCC_ADC1MCLKSource value */
+ tmpregister |= RCC_ADC1MCLKSource;
+ /* Set ADC1MPRE[4:0] bits according to RCC_ADC1MPrescaler value */
+ tmpregister |= RCC_ADC1MPrescaler;
+
+ /* Store the new value */
+ RCC->CFG2 = tmpregister;
+}
+
+/**
+ * @brief Configures the ADCPLLCLK prescaler, and enable/disable ADCPLLCLK.
+ * @param RCC_ADCPLLCLKPrescaler specifies the ADCPLLCLK prescaler.
+ * This parameter can be on of the following values:
+ * @arg RCC_ADCPLLCLK_DIV1 ADCPLLCLKPRES[4:0] = 10000, Pll Clock Divided By 1
+ * @arg RCC_ADCPLLCLK_DIV2 ADCPLLCLKPRES[4:0] = 10001, Pll Clock Divided By 2
+ * @arg RCC_ADCPLLCLK_DIV4 ADCPLLCLKPRES[4:0] = 10010, Pll Clock Divided By 4
+ * @arg RCC_ADCPLLCLK_DIV6 ADCPLLCLKPRES[4:0] = 10011, Pll Clock Divided By 6
+ * @arg RCC_ADCPLLCLK_DIV8 ADCPLLCLKPRES[4:0] = 10100, Pll Clock Divided By 8
+ * @arg RCC_ADCPLLCLK_DIV10 ADCPLLCLKPRES[4:0] = 10101, Pll Clock Divided By 10
+ * @arg RCC_ADCPLLCLK_DIV12 ADCPLLCLKPRES[4:0] = 10110, Pll Clock Divided By 12
+ * @arg RCC_ADCPLLCLK_DIV16 ADCPLLCLKPRES[4:0] = 10111, Pll Clock Divided By 16
+ * @arg RCC_ADCPLLCLK_DIV32 ADCPLLCLKPRES[4:0] = 11000, Pll Clock Divided By 32
+ * @arg RCC_ADCPLLCLK_DIV64 ADCPLLCLKPRES[4:0] = 11001, Pll Clock Divided By 64
+ * @arg RCC_ADCPLLCLK_DIV128 ADCPLLCLKPRES[4:0] = 11010, Pll Clock Divided By 128
+ * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = 11011, Pll Clock Divided By 256
+ * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = others, Pll Clock Divided By 256
+ *
+ * @param Cmd specifies the ADCPLLCLK enable/disable selection.
+ * This parameter can be on of the following values:
+ * @arg ENABLE enable ADCPLLCLK
+ * @arg DISABLE disable ADCPLLCLK ADCPLLCLKPRES[4:0] = 0xxxx, ADC Pll Clock Disable
+ */
+void RCC_ConfigAdcPllClk(uint32_t RCC_ADCPLLCLKPrescaler, FunctionalState Cmd)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_ADCPLLCLKPRE(RCC_ADCPLLCLKPrescaler));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ tmpregister = RCC->CFG2;
+ /* Clear ADCPLLPRES[4:0] bits */
+ tmpregister &= CFG2_ADCPLLPRES_RESET_MASK;
+
+ if (Cmd != DISABLE)
+ {
+ tmpregister |= RCC_ADCPLLCLKPrescaler;
+ }
+ else
+ {
+ tmpregister |= RCC_ADCPLLCLKPrescaler;
+ tmpregister &= RCC_ADCPLLCLK_DISABLE;
+ }
+
+ /* Store the new value */
+ RCC->CFG2 = tmpregister;
+}
+
+/**
+ * @brief Configures the ADCHCLK prescaler.
+ * @param RCC_ADCHCLKPrescaler specifies the ADCHCLK prescaler.
+ * This parameter can be on of the following values:
+ * @arg RCC_ADCHCLK_DIV1 ADCHCLKPRE[3:0] = 0000, HCLK Clock Divided By 1
+ * @arg RCC_ADCHCLK_DIV2 ADCHCLKPRE[3:0] = 0001, HCLK Clock Divided By 2
+ * @arg RCC_ADCHCLK_DIV4 ADCHCLKPRE[3:0] = 0010, HCLK Clock Divided By 4
+ * @arg RCC_ADCHCLK_DIV6 ADCHCLKPRE[3:0] = 0011, HCLK Clock Divided By 6
+ * @arg RCC_ADCHCLK_DIV8 ADCHCLKPRE[3:0] = 0100, HCLK Clock Divided By 8
+ * @arg RCC_ADCHCLK_DIV10 ADCHCLKPRE[3:0] = 0101, HCLK Clock Divided By 10
+ * @arg RCC_ADCHCLK_DIV12 ADCHCLKPRE[3:0] = 0110, HCLK Clock Divided By 12
+ * @arg RCC_ADCHCLK_DIV16 ADCHCLKPRE[3:0] = 0111, HCLK Clock Divided By 16
+ * @arg RCC_ADCHCLK_DIV32 ADCHCLKPRE[3:0] = 1000, HCLK Clock Divided By 32
+ * @arg RCC_ADCHCLK_DIV_OTHERS ADCHCLKPRE[3:0] = others, HCLK Clock Divided By 32
+ */
+void RCC_ConfigAdcHclk(uint32_t RCC_ADCHCLKPrescaler)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_ADCHCLKPRE(RCC_ADCHCLKPrescaler));
+
+ tmpregister = RCC->CFG2;
+ /* Clear ADCHPRE[3:0] bits */
+ tmpregister &= CFG2_ADCHPRES_RESET_MASK;
+ /* Set ADCHPRE[3:0] bits according to RCC_ADCHCLKPrescaler value */
+ tmpregister |= RCC_ADCHCLKPrescaler;
+
+ /* Store the new value */
+ RCC->CFG2 = tmpregister;
+}
+
+/**
+ * @brief Configures the TRNG 1M clock (TRNG1MCLK).
+ * @param RCC_TRNG1MCLKSource specifies the TRNG1M clock source.
+ * This parameter can be on of the following values:
+ * @arg RCC_TRNG1MCLK_SRC_HSI
+ * @arg RCC_TRNG1MCLK_SRC_HSE
+ *
+ * @param RCC_TRNG1MPrescaler specifies the TRNG1M prescaler.
+ * This parameter can be on of the following values:
+ * @arg RCC_TRNG1MCLK_DIV2 TRNG1M clock = RCC_TRNG1MCLK_SRC_HSE/2
+ * @arg RCC_TRNG1MCLK_DIV4 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/4
+ * @arg RCC_TRNG1MCLK_DIV6 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/6
+ * ...
+ * @arg RCC_TRNG1MCLK_DIV60 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/60
+ * @arg RCC_TRNG1MCLK_DIV62 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/62
+ */
+void RCC_ConfigTrng1mClk(uint32_t RCC_TRNG1MCLKSource, uint32_t RCC_TRNG1MPrescaler)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_TRNG1MCLK_SRC(RCC_TRNG1MCLKSource));
+ assert_param(IS_RCC_TRNG1MCLKPRE(RCC_TRNG1MPrescaler));
+
+ tmpregister = RCC->CFG3;
+ /* Clear TRNG1MSEL and TRNG1MPRE[4:0] bits */
+ tmpregister &= CFGR3_TRNG1MSEL_RESET_MASK;
+ tmpregister &= CFGR3_TRNG1MPRES_RESET_MASK;
+ /* Set TRNG1MSEL bits according to RCC_TRNG1MCLKSource value */
+ tmpregister |= RCC_TRNG1MCLKSource;
+ /* Set TRNG1MPRE[4:0] bits according to RCC_TRNG1MPrescaler value */
+ tmpregister |= RCC_TRNG1MPrescaler;
+
+ /* Store the new value */
+ RCC->CFG3 = tmpregister;
+}
+
+/**
+ * @brief Enable/disable TRNG clock (TRNGCLK).
+ * @param Cmd specifies the TRNGCLK enable/disable selection.
+ * This parameter can be on of the following values:
+ * @arg ENABLE enable TRNGCLK
+ * @arg DISABLE disable TRNGCLK
+ */
+void RCC_EnableTrng1mClk(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ RCC->CFG3 |= RCC_TRNG1MCLK_ENABLE;
+ }
+ else
+ {
+ RCC->CFG3 &= RCC_TRNG1MCLK_DISABLE;
+ }
+}
+
+/**
+ * @brief Configures the UCDR clock.
+ * @param RCC_UCDR300MSource specifies the UCDR clock source.
+ * This parameter can be on of the following values:
+ * @arg RCC_UCDR300M_SRC_OSC300M
+ * @arg RCC_UCDR300M_SRC_PLLVCO
+ *
+ * @param Cmd enable/disable selection.
+ * This parameter can be on of the following values:
+ * @arg ENABLE enable UCDR
+ * @arg DISABLE disable UCDR
+ */
+void RCC_ConfigUCDRClk(uint32_t RCC_UCDR300MSource, FunctionalState Cmd)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_UCDR300M_SRC(RCC_UCDR300MSource));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ tmpregister = RCC->CFG3;
+ /* Clear UCDR300MSEL bits */
+ tmpregister &= RCC_UCDR300MSource_MASK;
+ /* Set UCDR300MSEL bits */
+ tmpregister |= RCC_UCDR300MSource;
+
+ /* Store the new value */
+ RCC->CFG3 = tmpregister;
+
+ if (Cmd != DISABLE)
+ {
+ RCC->CFG3 |= RCC_UCDR_ENABLE;
+ }
+ else
+ {
+ RCC->CFG3 &= RCC_UCDR_DISABLE;
+ }
+}
+
+/**
+ * @brief Configures the USB Crystal Mode.
+ * @param RCC_USBXTALESSMode specifies the USB Crystal Mode.
+ * This parameter can be one of the following values:
+ * @arg RCC_USBXTALESS_MODE USB work in crystal mode
+ * @arg RCC_USBXTALESS_LESSMODE USB work in crystalless mode
+ */
+void RCC_ConfigUSBXTALESSMode(uint32_t RCC_USBXTALESSMode)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_USBXTALESS_MODE(RCC_USBXTALESSMode));
+
+ /* Clear the USB Crystal Mode bit */
+ RCC->CFG3 &= RCC_USBXTALESSMode_MASK;
+
+ /* Select the USB Crystal Mode */
+ RCC->CFG3 |= RCC_USBXTALESSMode;
+}
+
+/**
+ * @brief Enables or disables the RET peripheral clock.
+ * @param RCC_RETPeriph specifies the RET peripheral to gates its clock.
+ *
+ * this parameter can be any combination of the following values:
+ * @arg RCC_RET_PERIPH_LPTIM
+ * @arg RCC_RET_PERIPH_LPUART
+ *
+ * @param Cmd new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableRETPeriphClk(uint32_t RCC_RETPeriph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_RET_PERIPH(RCC_RETPeriph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ RCC->RDCTRL |= RCC_RETPeriph;
+ }
+ else
+ {
+ RCC->RDCTRL &= ~RCC_RETPeriph;
+ }
+}
+
+/**
+ * @brief Forces or releases RET peripheral reset.
+ * @param RCC_RETPeriph specifies the RET peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_RET_PERIPH_LPTIM.
+ * RCC_RET_PERIPH_LPUART.
+ * @param Cmd new state of the specified peripheral reset. This parameter can be ENABLE or DISABLE.
+ */
+void RCC_EnableRETPeriphReset(uint32_t RCC_RETPeriph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_RET_PERIPH(RCC_RETPeriph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ RCC->RDCTRL |= (RCC_RETPeriph << 4);
+ }
+ else
+ {
+ RCC->RDCTRL &= ~(RCC_RETPeriph << 4);
+ }
+}
+
+/**
+ * @brief Configures the LPTIM clock (LPTIMCLK).
+ * @param RCC_LPTIMCLKSource specifies the LPTIM clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_LPTIMCLK_SRC_APB1 APB1 clock selected as LPTIM clock
+ * @arg RCC_LPTIMCLK_SRC_LSI LSI selected as LPTIM clock
+ * @arg RCC_LPTIMCLK_SRC_HSI HSI selected as LPTIM clock
+ * @arg RCC_LPTIMCLK_SRC_LSE LSE selected as LPTIM clock
+ * @arg RCC_LPTIMCLK_SRC_COMP1 COMP1 output selected as LPTIM clock
+ * @arg RCC_LPTIMCLK_SRC_COMP2 COMP2 output selected as LPTIM clock
+ * @note When switching from comparator1/2 to other clock sources,
+ * it is suggested to disable comparators first.
+ */
+void RCC_ConfigLPTIMClk(uint32_t RCC_LPTIMCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_LPTIM_CLK(RCC_LPTIMCLKSource));
+ //PWR DBP set 1
+ RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR, ENABLE);
+ PWR->CTRL1 |= 0x100;
+ /* Clear the LPTIM clock source */
+ RCC->RDCTRL &= RCC_LPTIMCLK_SRC_MASK;
+
+ /* Select the LPTIM clock source */
+ RCC->RDCTRL |= RCC_LPTIMCLKSource;
+}
+
+/**
+ * @brief Returns the clock source used as LPTIM clock (LPTIMCLK).
+ * @return The clock source used as system clock. The returned value can
+ * be one of the following:
+ * - RCC_LPTIMCLK_SRC_APB1 APB1 clock selected as LPTIM clock
+ * - RCC_LPTIMCLK_SRC_LSI LSI selected as LPTIM clock
+ * - RCC_LPTIMCLK_SRC_HSI HSI selected as LPTIM clock
+ * - RCC_LPTIMCLK_SRC_LSE LSE selected as LPTIM clock
+ * - RCC_LPTIMCLK_SRC_COMP1 COMP1 output selected as LPTIM clock
+ * - RCC_LPTIMCLK_SRC_COMP2 COMP2 output selected as LPTIM clock
+ */
+uint32_t RCC_GetLPTIMClkSrc(void)
+{
+ return ((uint32_t)(RCC->RDCTRL & RDCTRL_LPTIMCLKSEL_MASK));
+}
+
+/**
+ * @brief Configures the LPUART clock (LPUARTCLK).
+ * @param RCC_LPUARTCLKSource specifies the LPUART clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_LPUARTCLK_SRC_APB1 APB1 clock selected as LPTIM clock
+ * @arg RCC_LPUARTCLK_SRC_SYSCLK SYSCLK selected as LPTIM clock
+ * @arg RCC_LPUARTCLK_SRC_HSI HSI selected as LPTIM clock
+ * @arg RCC_LPUARTCLK_SRC_LSE LSE selected as LPTIM clock
+ */
+void RCC_ConfigLPUARTClk(uint32_t RCC_LPUARTCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_LPUART_CLK(RCC_LPUARTCLKSource));
+
+ /* Clear the LPUART clock source */
+ RCC->RDCTRL &= RCC_LPUARTCLK_SRC_MASK;
+
+ /* Select the LPTIM clock source */
+ RCC->RDCTRL |= RCC_LPUARTCLKSource;
+}
+
+/**
+ * @brief Returns the clock source used as LPUART clock.
+ * @return The clock source used as system clock. The returned value can
+ * be one of the following:
+ * - RCC_RDCTRL_LPUARTSEL_APB1: APB1 used as LPUART clock
+ * - RCC_RDCTRL_LPUARTSEL_SYSCLK: SYSCLK used as LPUART clock
+ * - RCC_RDCTRL_LPUARTSEL_HSI: HSI used as LPUART clock
+ * - RCC_RDCTRL_LPUARTSEL_LSE: LSE used as LPUART clock
+ */
+uint32_t RCC_GetLPUARTClkSrc(void)
+{
+ return ((uint32_t)(RCC->RDCTRL & RDCTRL_LPUARTCLKSEL_MASK));
+}
+
+/**
+ * @brief Enables or disables the specified SRAM1/2 parity error interrupts.
+ * @param SramErrorInt specifies the SRAM1/2 interrupt sources to be enabled or disabled.
+ *
+ * this parameter can be any combination of the following values
+ * @arg SRAM1_PARITYERROR_INT SRAM1 parity interrupt
+ * @arg SRAM2_PARITYERROR_INT SRAM2 parity interrupt
+ *
+ * @param Cmd new state of the specified SRAM1/2 parity error interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_ConfigSRAMParityErrorInt(uint32_t SramErrorInt, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_SRAMERRORINT(SramErrorInt));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set ERR1EN/ERR2EN bit to enable the selected parity error interrupts */
+ RCC->SRAM_CTRLSTS |= SramErrorInt;
+ }
+ else
+ {
+ /* Clear ERR1EN/ERR2EN bit to disable the selected parity error interrupts */
+ RCC->SRAM_CTRLSTS &= (~SramErrorInt);
+ }
+}
+
+/**
+ * @brief Enables or disables the specified SRAM1/2 parity error reset.
+ * @param SramErrorReset specifies the SRAM1/2 parity error reset to be enabled or disabled.
+ *
+ * this parameter can be any combination of the following values
+ * @arg SRAM1_PARITYERROR_RESET SRAM1 parity error reset
+ * @arg SRAM2_PARITYERROR_RESET SRAM2 parity error reset
+ *
+ * @param Cmd new state of the specified SRAM1/2 parity error reset.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_ConfigSRAMParityErrorRESET(uint32_t SramErrorReset, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_SRAMERRORRESET(SramErrorReset));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set ERR1EN/ERR2EN bit to enable SRAM1/2 parity error reset */
+ RCC->SRAM_CTRLSTS |= SramErrorReset;
+ }
+ else
+ {
+ /* Clear ERR1EN/ERR2EN bit to disable SRAM1/2 parity error reset */
+ RCC->SRAM_CTRLSTS &= (~SramErrorReset);
+ }
+}
+
+/**
+ * @brief Clears the specified SRAM1/2 parity error flag.
+ * @param SramErrorReset specifies the SRAM1/2 parity error flag.
+ *
+ * this parameter can be any combination of the following values
+ * @arg SRAM1_PARITYERROR_FLAG SRAM1 parity error flag
+ * @arg SRAM2_PARITYERROR_FLAG SRAM2 parity error flag
+ */
+void RCC_ClrSRAMParityErrorFlag(uint32_t SramErrorflag)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_SRAMERRORFLAG(SramErrorflag));
+ RCC->SRAM_CTRLSTS |= SramErrorflag;
+}
+
+/**
+ * @brief Configures the External Low Speed oscillator (LSE) Xtal bias.
+ * @param LSE_Trim specifies LSE Driver Trim Level.
+ * Trim value rang 0x0~0x1FF
+ */
+void LSE_XtalConfig(uint16_t LSE_Trim)
+{
+ uint32_t tmpregister = 0;
+ tmpregister = *(__IO uint32_t*)LSE_TRIMR_ADDR;
+ //clear lse trim[8:0]
+ tmpregister &= (~(LSE_GM_MASK_VALUE));
+ (LSE_Trim>LSE_GM_MAX_VALUE) ? (LSE_Trim=LSE_GM_DEFAULT_VALUE):(LSE_Trim&=LSE_GM_MASK_VALUE);
+ tmpregister |= LSE_Trim;
+ *(__IO uint32_t*)LSE_TRIMR_ADDR = tmpregister;
+}
+
+/**
+ * @brief Configures the External Low Speed oscillator (LSE).
+ * @param RCC_LSE specifies the new state of the LSE.
+ * This parameter can be one of the following values:
+ * @arg RCC_LSE_DISABLE LSE oscillator OFF
+ * @arg RCC_LSE_ENABLE LSE oscillator ON
+ * @arg RCC_LSE_BYPASS LSE oscillator bypassed with external clock
+ * @param LSE_Trim specifies LSE Driver Trim Level.
+ * Trim value rang 0x00~0x1FF
+ */
+void RCC_ConfigLse(uint8_t RCC_LSE,uint16_t LSE_Trim)
+{
+ //PWR DBP set 1
+ /* Enable PWR Clock */
+ RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR, ENABLE);
+ PWR->CTRL1 |= 0x100;
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE(RCC_LSE));
+ /* Reset LSEEN LSEBYP and LSECLKSSEN bits before configuring the LSE ------------------*/
+ *(__IO uint32_t*)LDCTRL_ADDR &= (~(RCC_LDCTRL_LSEEN | RCC_LDCTRL_LSEBP | RCC_LDCTRL_LSECLKSSEN));
+ /* Configure LSE (RCC_LSE_DISABLE is already covered by the code section above) */
+ switch (RCC_LSE)
+ {
+ case RCC_LSE_ENABLE:
+ /* Set LSEON bit */
+ *(__IO uint32_t*)LDCTRL_ADDR |= RCC_LSE_ENABLE;
+ LSE_XtalConfig(LSE_Trim);
+ break;
+ case RCC_LSE_BYPASS:
+ /* Set LSEBYP and LSEON bits */
+ *(__IO uint32_t*)LDCTRL_ADDR |= (RCC_LSE_BYPASS | RCC_LSE_ENABLE);
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Enables or disables the Internal Low Speed oscillator (LSI).
+ * @note LSI can not be disabled if the IWDG is running.
+ * @param Cmd new state of the LSI. This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableLsi(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)CTRLSTS_LSIEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Configures the RTC clock (RTCCLK).
+ * @note Once the RTC clock is selected it can't be changed unless the LowPower domain is reset.
+ * @param RCC_RTCCLKSource specifies the RTC clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_RTCCLK_SRC_NONE: No clock selected as RTC clock
+ * @arg RCC_RTCCLK_SRC_LSE: LSE selected as RTC clock
+ * @arg RCC_RTCCLK_SRC_LSI: LSI selected as RTC clock
+ * @arg RCC_RTCCLK_SRC_HSE_DIV32: HSE clock divided by 32 selected as RTC clock
+ */
+void RCC_ConfigRtcClk(uint32_t RCC_RTCCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_RTCCLK_SRC(RCC_RTCCLKSource));
+
+ /* Clear the RTC clock source */
+ RCC->LDCTRL &= (~RCC_LDCTRL_RTCSEL);
+
+ /* Select the RTC clock source */
+ RCC->LDCTRL |= RCC_RTCCLKSource;
+}
+
+/**
+ * @brief Returns the clock source used as RTC clock (RTCCLK).
+ * @return The clock source used as system clock. The returned value can
+ * be one of the following:
+ * - RCC_RTCCLK_SRC_NONE: No clock used as RTC clock (RTCCLK)
+ * - RCC_RTCCLK_SRC_LSE: LSE used as RTC clock (RTCCLK)
+ * - RCC_RTCCLK_SRC_LSI: LSI used as RTC clock (RTCCLK)
+ * - RCC_RTCCLK_SRC_HSE_DIV32: HSE clock divided by 32 used as RTC clock (RTCCLK)
+ */
+uint32_t RCC_GetRTCClkSrc(void)
+{
+ return ((uint32_t)(RCC->LDCTRL & RCC_LDCTRL_RTCSEL));
+}
+
+/**
+ * @brief Enables or disables the RTC clock.
+ * @note This function must be used only after the RTC clock was selected using the RCC_ConfigRtcClk function.
+ * @param Cmd new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableRtcClk(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)LDCTRL_RTCEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Configures the LSX clock (for TSC).
+ * @note Once the LSX clock is selected it can't be changed unless the LowPower domain is reset.
+ * @param RCC_RTCCLKSource specifies the RTC clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_LSXCLK_SRC_LSI LSI selected as RTC clock
+ * @arg RCC_LSXCLK_SRC_LSE LSE selected as RTC clock
+ */
+void RCC_ConfigLSXClk(uint32_t RCC_LSXCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_LSXCLK_SRC(RCC_LSXCLKSource));
+
+ /* Clear the LSX clock source */
+ RCC->LDCTRL &= (~RCC_LDCTRL_LSXSEL);
+
+ /* Select the LSX clock source */
+ RCC->LDCTRL |= RCC_LSXCLKSource;
+}
+
+/**
+ * @brief Returns the clock source used as LSX clock (for TSC).
+ * @return The clock source used as system clock. The returned value can
+ * be one of the following:
+ * - RCC_LSXCLK_SRC_LSI: LSI used as LSX clock (for TSC)
+ * - RCC_LSXCLK_SRC_LSE: LSE used as LSX clock (for TSC)
+ */
+uint32_t RCC_GetLSXClkSrc(void)
+{
+ return ((uint32_t)(RCC->LDCTRL & RCC_LDCTRL_LSXSEL));
+}
+
+/**
+ * @brief Returns the frequencies of different on chip clocks.
+ * @param RCC_Clocks pointer to a RCC_ClocksType structure which will hold
+ * the clocks frequencies.
+ * @note The result of this function could be not correct when using
+ * fractional value for HSE crystal.
+ */
+void RCC_GetClocksFreqValue(RCC_ClocksType* RCC_Clocks)
+{
+ uint32_t tmp = 0, pllclk = 0, pllmull = 0, pllsource = 0, presc = 0;
+ uint8_t msi_clk = 0;
+
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFG & CFG_PLLMULFCT_MASK;
+ pllsource = RCC->CFG & CFG_PLLSRC_MASK;
+ /* Get MSI clock --------------------------------------------------------*/
+ msi_clk = (uint8_t) ((RCC->CTRLSTS & RCC_CTRLSTS_MSIRANGE)>>4);
+
+ if ((pllmull & RCC_CFG_PLLMULFCT_4) == 0)
+ {
+ pllmull = (pllmull >> 18) + 2; // PLLMUL[4]=0
+ }
+ else
+ {
+ pllmull = ((pllmull >> 18) - 496) + 1; // PLLMUL[4]=1
+ }
+
+ if (pllsource == 0x00)
+ {
+ /* HSI selected as PLL clock entry */
+ if ((RCC->PLLHSIPRE & PLLHSIPRE_PLLHSI_PRE_MASK) != (uint32_t)RESET)
+ { /* HSI oscillator clock divided by 2 */
+ pllclk = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ pllclk = HSI_VALUE * pllmull;
+ }
+
+ }
+ else
+ {
+ /* HSE selected as PLL clock entry */
+ if ((RCC->CFG & CFG_PLLHSEPRES_MASK) != (uint32_t)RESET)
+ { /* HSE oscillator clock divided by 2 */
+ pllclk = (HSE_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ pllclk = HSE_VALUE * pllmull;
+ }
+ }
+
+ /* PLL Div clock */
+ if ((RCC->PLLHSIPRE & PLLHSIPRE_PLLSRCDIV_MASK) != (uint32_t)RESET)
+ { /* PLL clock divided by 2 */
+ pllclk = (pllclk >> 1);
+ }
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFG & CFG_SCLKSTS_MASK;
+
+ switch (tmp)
+ {
+ case 0x00: /* MSI used as system clock */
+ RCC_Clocks->SysclkFreq = s_msiClockTable[msi_clk];
+ break;
+ case 0x04: /* HSI used as system clock */
+ RCC_Clocks->SysclkFreq = HSI_VALUE;
+ break;
+ case 0x08: /* HSE used as system clock */
+ RCC_Clocks->SysclkFreq = HSE_VALUE;
+ break;
+ case 0x0C: /* PLL used as system clock */
+ RCC_Clocks->SysclkFreq = pllclk;
+ break;
+
+ default:
+ RCC_Clocks->SysclkFreq = s_msiClockTable[msi_clk];
+ break;
+ }
+
+ /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
+ /* Get HCLK prescaler */
+ tmp = RCC->CFG & CFG_AHBPRES_SET_MASK;
+ tmp = tmp >> 4;
+ presc = s_ApbAhbPresTable[tmp];
+ /* HCLK clock frequency */
+ RCC_Clocks->HclkFreq = RCC_Clocks->SysclkFreq >> presc;
+ /* Get PCLK1 prescaler */
+ tmp = RCC->CFG & CFG_APB1PRES_SET_MASK;
+ tmp = tmp >> 8;
+ presc = s_ApbAhbPresTable[tmp];
+ /* PCLK1 clock frequency */
+ RCC_Clocks->Pclk1Freq = RCC_Clocks->HclkFreq >> presc;
+ /* Get PCLK2 prescaler */
+ tmp = RCC->CFG & CFG_APB2PRES_SET_MASK;
+ tmp = tmp >> 11;
+ presc = s_ApbAhbPresTable[tmp];
+ /* PCLK2 clock frequency */
+ RCC_Clocks->Pclk2Freq = RCC_Clocks->HclkFreq >> presc;
+
+ /* Get ADCHCLK prescaler */
+ tmp = RCC->CFG2 & CFG2_ADCHPRES_SET_MASK;
+ presc = s_AdcHclkPresTable[tmp];
+ /* ADCHCLK clock frequency */
+ RCC_Clocks->AdcHclkFreq = RCC_Clocks->HclkFreq / presc;
+ /* Get ADCPLLCLK prescaler */
+ tmp = RCC->CFG2 & CFG2_ADCPLLPRES_SET_MASK;
+ tmp = tmp >> 4;
+ presc = s_AdcPllClkPresTable[(tmp & 0xF)]; // ignore BIT5
+ /* ADCPLLCLK clock frequency */
+ RCC_Clocks->AdcPllClkFreq = pllclk / presc;
+}
+
+/**
+ * @brief Enables or disables the AHB peripheral clock.
+ * @param RCC_AHBPeriph specifies the AHB peripheral to gates its clock.
+ *
+ * this parameter can be any combination of the following values:
+ * @arg RCC_AHB_PERIPH_DMA
+ * @arg RCC_AHB_PERIPH_SRAM
+ * @arg RCC_AHB_PERIPH_FLITF
+ * @arg RCC_AHB_PERIPH_CRC
+ * @arg RCC_AHB_PERIPH_RNGC
+ * @arg RCC_AHB_PERIPH_SAC
+ * @arg RCC_AHB_PERIPH_ADC
+ *
+ * @note SRAM and FLITF clock can be disabled only during sleep mode.
+ * @param Cmd new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableAHBPeriphClk(uint32_t RCC_AHBPeriph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ RCC->AHBPCLKEN |= RCC_AHBPeriph;
+ }
+ else
+ {
+ RCC->AHBPCLKEN &= ~RCC_AHBPeriph;
+ }
+}
+
+/**
+ * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
+ * @param RCC_APB2Periph specifies the APB2 peripheral to gates its clock.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB2_PERIPH_AFIO, RCC_APB2_PERIPH_GPIOA, RCC_APB2_PERIPH_GPIOB,
+ * RCC_APB2_PERIPH_GPIOC, RCC_APB2_PERIPH_GPIOD, RCC_APB2_PERIPH_TIM1,
+ * RCC_APB2_PERIPH_SPI1, RCC_APB2_PERIPH_TIM8, RCC_APB2_PERIPH_USART1,
+ * RCC_APB2_PERIPH_UART4, RCC_APB2_PERIPH_UART5, RCC_APB2_PERIPH_SPI2
+ * @param Cmd new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableAPB2PeriphClk(uint32_t RCC_APB2Periph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ RCC->APB2PCLKEN |= RCC_APB2Periph;
+ }
+ else
+ {
+ RCC->APB2PCLKEN &= ~RCC_APB2Periph;
+ }
+}
+
+/**
+ * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
+ * @param RCC_APB1Periph specifies the APB1 peripheral to gates its clock.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB1_PERIPH_TIM2, RCC_APB1_PERIPH_TIM3, RCC_APB1_PERIPH_TIM4,
+ * RCC_APB1_PERIPH_TIM5, RCC_APB1_PERIPH_TIM6, RCC_APB1_PERIPH_TIM7,
+ * RCC_APB1_PERIPH_COMP, RCC_APB1_PERIPH_COMP_FILT, RCC_APB1_PERIPH_AFEC,
+ * RCC_APB1_PERIPH_TIM9, RCC_APB1_PERIPH_TSC, RCC_APB1_PERIPH_WWDG,
+ * RCC_APB1_PERIPH_USART2, RCC_APB1_PERIPH_USART3, RCC_APB1_PERIPH_I2C1,
+ * RCC_APB1_PERIPH_I2C2, RCC_APB1_PERIPH_USB, RCC_APB1_PERIPH_CAN,
+ * RCC_APB1_PERIPH_PWR, RCC_APB1_PERIPH_DAC, RCC_APB1_PERIPH_OPAMP
+ *
+ * @param Cmd new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableAPB1PeriphClk(uint32_t RCC_APB1Periph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ RCC->APB1PCLKEN |= RCC_APB1Periph;
+ }
+ else
+ {
+ RCC->APB1PCLKEN &= ~RCC_APB1Periph;
+ }
+}
+
+/**
+ * @brief Forces or releases AHB peripheral reset.
+ * @param RCC_AHBPeriph specifies the AHB peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_AHB_PERIPH_ADC.
+ * RCC_AHB_PERIPH_SAC.
+ * RCC_AHB_PERIPH_RNGC.
+ * @param Cmd new state of the specified peripheral reset. This parameter can be ENABLE or DISABLE.
+ */
+void RCC_EnableAHBPeriphReset(uint32_t RCC_AHBPeriph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ RCC->AHBPRST |= RCC_AHBPeriph;
+ }
+ else
+ {
+ RCC->AHBPRST &= ~RCC_AHBPeriph;
+ }
+}
+
+/**
+ * @brief Forces or releases High Speed APB (APB2) peripheral reset.
+ * @param RCC_APB2Periph specifies the APB2 peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB2_PERIPH_AFIO, RCC_APB2_PERIPH_GPIOA, RCC_APB2_PERIPH_GPIOB,
+ * RCC_APB2_PERIPH_GPIOC, RCC_APB2_PERIPH_GPIOD, RCC_APB2_PERIPH_TIM1,
+ * RCC_APB2_PERIPH_SPI1, RCC_APB2_PERIPH_TIM8, RCC_APB2_PERIPH_USART1,
+ * RCC_APB2_PERIPH_UART4, RCC_APB2_PERIPH_UART5, RCC_APB2_PERIPH_SPI2
+ * @param Cmd new state of the specified peripheral reset.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableAPB2PeriphReset(uint32_t RCC_APB2Periph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ RCC->APB2PRST |= RCC_APB2Periph;
+ }
+ else
+ {
+ RCC->APB2PRST &= ~RCC_APB2Periph;
+ }
+}
+
+/**
+ * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
+ * @param RCC_APB1Periph specifies the APB1 peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB1_PERIPH_TIM2, RCC_APB1_PERIPH_TIM3, RCC_APB1_PERIPH_TIM4,
+ * RCC_APB1_PERIPH_TIM5, RCC_APB1_PERIPH_TIM6, RCC_APB1_PERIPH_TIM7,
+ * RCC_APB1_PERIPH_COMP, RCC_APB1_PERIPH_COMP_FILT, RCC_APB1_PERIPH_AFEC,
+ * RCC_APB1_PERIPH_TIM9, RCC_APB1_PERIPH_TSC, RCC_APB1_PERIPH_WWDG,
+ * RCC_APB1_PERIPH_USART2, RCC_APB1_PERIPH_USART3, RCC_APB1_PERIPH_I2C1,
+ * RCC_APB1_PERIPH_I2C2, RCC_APB1_PERIPH_USB, RCC_APB1_PERIPH_CAN,
+ * RCC_APB1_PERIPH_PWR, RCC_APB1_PERIPH_DAC, RCC_APB1_PERIPH_OPAMP
+ * @param Cmd new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableAPB1PeriphReset(uint32_t RCC_APB1Periph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ RCC->APB1PRST |= RCC_APB1Periph;
+ }
+ else
+ {
+ RCC->APB1PRST &= ~RCC_APB1Periph;
+ }
+}
+
+/**
+ * @brief Forces or releases the LowPower domain reset.
+ * @param Cmd new state of the Backup domain reset.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableLowPowerReset(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)LDCTRL_LDSFTRST_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Enables or disables the Clock Security System.
+ * @param Cmd new state of the Clock Security System..
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableClockSecuritySystem(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)CTRL_CLKSSEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Enables or disables the LSE Clock Security System.
+ * @param Cmd new state of the LSE Clock Security System..
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableLSEClockSecuritySystem(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)LDCTRL_LSECLKSSEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Get LSE Clock Security System failure status.
+ * @return LSE Clock Security System failure status (SET or RESET).
+ */
+FlagStatus RCC_GetLSEClockSecuritySystemStatus(void)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the status of LSE Clock Security System */
+ if ((RCC->LDCTRL & RCC_LDCTRL_LSECLKSSF) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ /* Return LSE Clock Security System status */
+ return bitstatus;
+}
+
+/**
+ * @brief Configures the MCO PLL clock prescaler.
+ * @param RCC_MCOPLLCLKPrescaler specifies the MCO PLL clock prescaler.
+ * This parameter can be on of the following values:
+ * @arg RCC_MCO_CLK_NUM0 MCOPRE[3:0] = 0000, PLL Clock Divided By 1, Duty cycle = clock source
+ * @arg RCC_MCO_CLK_NUM1 MCOPRE[3:0] = 0001, PLL Clock Divided By 2, Duty cycle = 1/((MCOPRE[3:0]+1)*2)
+ * @arg RCC_MCO_CLK_NUM2 MCOPRE[3:0] = 0010, PLL Clock Divided By 3, Duty cycle = 1/((MCOPRE[3:0]+1)*2)
+ * @arg RCC_MCO_CLK_NUM3 MCOPRE[3:0] = 0011, PLL Clock Divided By 4, Duty cycle = 1/((MCOPRE[3:0]+1)*2)
+ * @arg RCC_MCO_CLK_NUM4 MCOPRE[3:0] = 0100, PLL Clock Divided By 5, Duty cycle = 1/((MCOPRE[3:0]+1)*2)
+ * @arg RCC_MCO_CLK_NUM5 MCOPRE[3:0] = 0101, PLL Clock Divided By 6, Duty cycle = 1/((MCOPRE[3:0]+1)*2)
+ * @arg RCC_MCO_CLK_NUM6 MCOPRE[3:0] = 0110, PLL Clock Divided By 7, Duty cycle = 1/((MCOPRE[3:0]+1)*2)
+ * @arg RCC_MCO_CLK_NUM7 MCOPRE[3:0] = 0111, PLL Clock Divided By 8, Duty cycle = 1/((MCOPRE[3:0]+1)*2)
+ * @arg RCC_MCO_CLK_NUM8 MCOPRE[3:0] = 1000, PLL Clock Divided By 2, Duty cycle = 50%
+ * @arg RCC_MCO_CLK_NUM9 MCOPRE[3:0] = 1001, PLL Clock Divided By 4, Duty cycle = 50%
+ * @arg RCC_MCO_CLK_NUM10 MCOPRE[3:0] = 1010, PLL Clock Divided By 6, Duty cycle = 50%
+ * @arg RCC_MCO_CLK_NUM11 MCOPRE[3:0] = 1011, PLL Clock Divided By 8, Duty cycle = 50%
+ * @arg RCC_MCO_CLK_NUM12 MCOPRE[3:0] = 1100, PLL Clock Divided By 10, Duty cycle = 50%
+ * @arg RCC_MCO_CLK_NUM13 MCOPRE[3:0] = 1101, PLL Clock Divided By 12, Duty cycle = 50%
+ * @arg RCC_MCO_CLK_NUM14 MCOPRE[3:0] = 1110, PLL Clock Divided By 14, Duty cycle = 50%
+ * @arg RCC_MCO_CLK_NUM15 MCOPRE[3:0] = 1111, PLL Clock Divided By 16, Duty cycle = 50%
+ */
+void RCC_ConfigMcoClkPre(uint32_t RCC_MCOCLKPrescaler)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_MCOCLKPRE(RCC_MCOCLKPrescaler));
+
+ tmpregister = RCC->CFG;
+ /* Clear MCOPRE[3:0] bits */
+ tmpregister &= ((uint32_t)0x0FFFFFFF);
+ /* Set MCOPRE[3:0] bits according to RCC_ADCHCLKPrescaler value */
+ tmpregister |= RCC_MCOCLKPrescaler;
+
+ /* Store the new value */
+ RCC->CFG = tmpregister;
+}
+
+/**
+ * @brief Selects the clock source to output on MCO pin.
+ * @param RCC_MCO specifies the clock source to output.
+ *
+ * this parameter can be one of the following values:
+ * @arg RCC_MCO_NOCLK No clock selected
+ * @arg RCC_MCO_LSI LSI oscillator clock selected
+ * @arg RCC_MCO_LSE LSE oscillator clock selected
+ * @arg RCC_MCO_MSI MSI oscillator clock selected
+ * @arg RCC_MCO_SYSCLK System clock selected
+ * @arg RCC_MCO_HSI HSI oscillator clock selected
+ * @arg RCC_MCO_HSE HSE oscillator clock selected
+ * @arg RCC_MCO_PLLCLK PLL clock selected
+ *
+ */
+void RCC_ConfigMco(uint8_t RCC_MCO)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_MCO(RCC_MCO));
+
+ tmpregister = RCC->CFG;
+ /* Clear MCO[2:0] bits */
+ tmpregister &= ((uint32_t)0xF8FFFFFF);
+ /* Set MCO[2:0] bits according to RCC_MCO value */
+ tmpregister |= ((uint32_t)(RCC_MCO << 24));
+
+ /* Store the new value */
+ RCC->CFG = tmpregister;
+}
+
+/**
+ * @brief Checks whether the specified RCC flag is set or not.
+ * @param RCC_FLAG specifies the flag to check.
+ *
+ * this parameter can be one of the following values:
+ * @arg RCC_CTRL_FLAG_HSIRDF HSI oscillator clock ready
+ * @arg RCC_CTRL_FLAG_HSERDF HSE oscillator clock ready
+ * @arg RCC_CTRL_FLAG_PLLRDF PLL clock ready
+ * @arg RCC_LDCTRL_FLAG_LSERD LSE oscillator clock ready
+ * @arg RCC_LDCTRL_FLAG_LSECLKSSF LSE Clock Security System failure status
+ * @arg RCC_LDCTRL_FLAG_BORRSTF BOR reset flag
+ * @arg RCC_LDCTRL_FLAG_LDEMCRSTF LowPower EMC reset flag
+ * @arg RCC_CTRLSTS_FLAG_LSIRD LSI oscillator clock ready
+ * @arg RCC_CTRLSTS_FLAG_MSIRD MSI oscillator clock ready
+ * @arg RCC_CTRLSTS_FLAG_RAMRSTF RAM reset flag
+ * @arg RCC_CTRLSTS_FLAG_MMURSTF MMU reset flag
+ * @arg RCC_CTRLSTS_FLAG_PINRSTF Pin reset
+ * @arg RCC_CTRLSTS_FLAG_PORRSTF POR reset
+ * @arg RCC_CTRLSTS_FLAG_SFTRSTF Software reset
+ * @arg RCC_CTRLSTS_FLAG_IWDGRSTF Independent Watchdog reset
+ * @arg RCC_CTRLSTS_FLAG_WWDGRSTF Window Watchdog reset
+ * @arg RCC_CTRLSTS_FLAG_LPWRRSTF Low Power reset
+ *
+ * @return The new state of RCC_FLAG (SET or RESET).
+ */
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
+{
+ uint32_t tmp = 0;
+ uint32_t statusreg = 0;
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_RCC_FLAG(RCC_FLAG));
+
+ /* Get the RCC register index */
+ tmp = RCC_FLAG >> 5;
+ if (tmp == 1) /* The flag to check is in CTRL register */
+ {
+ statusreg = RCC->CTRL;
+ }
+ else if (tmp == 2) /* The flag to check is in BDCTRL register */
+ {
+ statusreg = RCC->LDCTRL;
+ }
+ else /* The flag to check is in CTRLSTS register */
+ {
+ statusreg = RCC->CTRLSTS;
+ }
+
+ /* Get the flag position */
+ tmp = RCC_FLAG & FLAG_MASK;
+ if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RCC reset flags.
+ * @note The reset flags are: RCC_FLAG_LPEMCRST, RCC_FLAG_BORRST, RCC_FLAG_RAMRST, RCC_FLAG_MMURST,
+ * RCC_FLAG_PINRST, RCC_FLAG_PORRST,RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST,
+ * RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
+ */
+void RCC_ClrFlag(void)
+{
+ /* Set RMVF bit to clear the reset flags */
+ RCC->CTRLSTS |= CSR_RMRSTF_SET;
+ /* RMVF bit should be reset */
+ RCC->CTRLSTS &= CSR_RMVF_Reset;
+}
+
+/**
+ * @brief Checks whether the specified RCC interrupt has occurred or not.
+ * @param RccInt specifies the RCC interrupt source to check.
+ *
+ * this parameter can be one of the following values:
+ * @arg RCC_INT_LSIRDIF LSI ready interrupt
+ * @arg RCC_INT_LSERDIF LSE ready interrupt
+ * @arg RCC_INT_HSIRDIF HSI ready interrupt
+ * @arg RCC_INT_HSERDIF HSE ready interrupt
+ * @arg RCC_INT_PLLRDIF PLL ready interrupt
+ * @arg RCC_INT_BORIF interrupt
+ * @arg RCC_INT_MSIRDIF MSI ready interrupt
+ * @arg RCC_INT_CLKSSIF Clock Security System interrupt
+ *
+ * @return The new state of RccInt (SET or RESET).
+ */
+INTStatus RCC_GetIntStatus(uint8_t RccInt)
+{
+ INTStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_RCC_GET_INT(RccInt));
+
+ /* Check the status of the specified RCC interrupt */
+ if ((RCC->CLKINT & RccInt) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ /* Return the RccInt status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RCC's interrupt pending bits.
+ * @param RccInt specifies the interrupt pending bit to clear.
+ *
+ * this parameter can be any combination of the
+ * following values:
+ * @arg RCC_CLR_MSIRDIF Clear MSI ready interrupt flag
+ * @arg RCC_CLR_LSIRDIF Clear LSI ready interrupt flag
+ * @arg RCC_CLR_LSERDIF Clear LSE ready interrupt flag
+ * @arg RCC_CLR_HSIRDIF Clear HSI ready interrupt flag
+ * @arg RCC_CLR_HSERDIF Clear HSE ready interrupt flag
+ * @arg RCC_CLR_PLLRDIF Clear PLL ready interrupt flag
+ * @arg RCC_CLR_BORIF Clear BOR interrupt flag
+ * @arg RCC_CLR_CLKSSIF Clear Clock Security System interrupt flag
+ */
+void RCC_ClrIntPendingBit(uint32_t RccClrInt)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_CLR_INTF(RccClrInt));
+ /* Software set this bit to clear INT flag. */
+ RCC->CLKINT |= RccClrInt;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_rtc.c b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_rtc.c
new file mode 100644
index 0000000000..15b4c26b71
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_rtc.c
@@ -0,0 +1,2327 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_rtc.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_rtc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RTC
+ * @brief RTC driver modules
+ * @{
+ */
+
+/* Masks Definition */
+#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
+#define RTC_DATE_RESERVED_MASK ((uint32_t)0x00FFFF3F)
+
+#define RTC_RSF_MASK ((uint32_t)0xFFFFFFDF)
+#define RTC_FLAGS_MASK \
+ ((uint32_t)(RTC_FLAG_TISOVF | RTC_FLAG_TISF | RTC_FLAG_WTF | RTC_FLAG_ALBF | RTC_FLAG_ALAF | RTC_FLAG_INITF \
+ | RTC_FLAG_RSYF | RTC_FLAG_INITSF | RTC_FLAG_WTWF | RTC_FLAG_ALBWF | RTC_FLAG_ALAWF | RTC_FLAG_RECPF \
+ | RTC_FLAG_SHOPF))
+
+#define INITMODE_TIMEOUT ((uint32_t)0x00002000)
+#define SYNCHRO_TIMEOUT ((uint32_t)0x00008000)
+#define RECALPF_TIMEOUT ((uint32_t)0x00001000)
+#define SHPF_TIMEOUT ((uint32_t)0x00002000)
+
+static uint8_t RTC_ByteToBcd2(uint8_t Value);
+static uint8_t RTC_Bcd2ToByte(uint8_t Value);
+
+/** @addtogroup RTC_Private_Functions
+ * @{
+ */
+
+/** @addtogroup RTC_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This section provide functions allowing to initialize and configure the
+ RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
+ RTC registers Write protection, enter and exit the RTC initialization mode,
+ RTC registers synchronization check and reference clock detection enable.
+ (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
+ It is split into 2 programmable prescalers to minimize power consumption.
+ (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler.
+ (++) When both prescalers are used, it is recommended to configure the
+ asynchronous prescaler to a high value to minimize consumption.
+ (#) All RTC registers are Write protected. Writing to the RTC registers
+ is enabled by writing a key into the Write Protection register, RTC_WRP.
+ (#) To Configure the RTC Calendar, user application should enter
+ initialization mode. In this mode, the calendar counter is stopped
+ and its value can be updated. When the initialization sequence is
+ complete, the calendar restarts counting after 4 RTCCLK cycles.
+ (#) To read the calendar through the shadow registers after Calendar
+ initialization, calendar update or after wakeup from low power modes
+ the software must first clear the RSYF flag. The software must then
+ wait until it is set again before reading the calendar, which means
+ that the calendar registers have been correctly copied into the
+ RTC_TSH and RTC_DATE shadow registers.The RTC_WaitForSynchro() function
+ implements the above software sequence (RSYF clear and RSYF check).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the RTC registers to their default reset values.
+ * @note This function doesn't reset the RTC Clock source and RTC Backup Data
+ * registers.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are deinitialized
+ * - ERROR: RTC registers are not deinitialized
+ */
+ErrorStatus RTC_DeInit(void)
+{
+ __IO uint32_t wutcounter = 0x00;
+ uint32_t wutwfstatus = 0x00;
+ ErrorStatus status = ERROR;
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Set Initialization mode */
+ if (RTC_EnterInitMode() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ /* Reset TSH, DAT and CTRL registers */
+ RTC->TSH = (uint32_t)0x00000000;
+ RTC->DATE = (uint32_t)0x00002101;
+
+ /* Reset All CTRL bits except CTRL[2:0] */
+ RTC->CTRL &= (uint32_t)0x00000007;
+
+ /* Wait till RTC WTWF flag is set and if Time out is reached exit */
+ do
+ {
+ wutwfstatus = RTC->INITSTS & RTC_INITSTS_WTWF;
+ wutcounter++;
+ } while ((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
+
+ if ((RTC->INITSTS & RTC_INITSTS_WTWF) == RESET)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ /* Reset all RTC CTRL register bits */
+ RTC->CTRL &= (uint32_t)0x00000000;
+ RTC->WKUPT = (uint32_t)0x0000FFFF;
+ RTC->PRE = (uint32_t)0x007F00FF;
+ RTC->ALARMA = (uint32_t)0x00000000;
+ RTC->ALARMB = (uint32_t)0x00000000;
+ RTC->SCTRL = (uint32_t)0x00000000;
+ RTC->CALIB = (uint32_t)0x00000000;
+ RTC->ALRMASS = (uint32_t)0x00000000;
+ RTC->ALRMBSS = (uint32_t)0x00000000;
+
+ /* Reset INTSTS register and exit initialization mode */
+ RTC->INITSTS = (uint32_t)0x00000000;
+
+ RTC->OPT = (uint32_t)0x00000000;
+ RTC->TSCWKUPCTRL = (uint32_t)0x00000008;
+ RTC->TSCWKUPCNT = (uint32_t)0x000002FE;
+
+ /* Wait till the RTC RSYF flag is set */
+ if (RTC_WaitForSynchro() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+
+ return status;
+}
+
+/**
+ * @brief Initializes the RTC registers according to the specified parameters
+ * in RTC_InitStruct.
+ * @param RTC_InitStruct pointer to a RTC_InitType structure that contains
+ * the configuration information for the RTC peripheral.
+ * @note The RTC Prescaler register is write protected and can be written in
+ * initialization mode only.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are initialized
+ * - ERROR: RTC registers are not initialized
+ */
+ErrorStatus RTC_Init(RTC_InitType* RTC_InitStruct)
+{
+ ErrorStatus status = ERROR;
+ uint32_t i =0;
+ /* Check the parameters */
+ assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat));
+ assert_param(IS_RTC_PREDIV_ASYNCH(RTC_InitStruct->RTC_AsynchPrediv));
+ assert_param(IS_RTC_PREDIV_SYNCH(RTC_InitStruct->RTC_SynchPrediv));
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+ /* Set Initialization mode */
+ if (RTC_EnterInitMode() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ /* Clear RTC CTRL HFMT Bit */
+ RTC->CTRL &= ((uint32_t) ~(RTC_CTRL_HFMT));
+ /* Set RTC_CTRL register */
+ RTC->CTRL |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat));
+ /* Configure the RTC PRE */
+ RTC->PRE = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv);
+ RTC->PRE |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16);
+ /* Exit Initialization mode */
+ RTC_ExitInitMode();
+ status = SUCCESS;
+ }
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+ /* Delay for the RTC prescale effect */
+ for(i=0;i<0x2FF;i++);
+ return status;
+}
+
+/**
+ * @brief Fills each RTC_InitStruct member with its default value.
+ * @param RTC_InitStruct pointer to a RTC_InitType structure which will be
+ * initialized.
+ */
+void RTC_StructInit(RTC_InitType* RTC_InitStruct)
+{
+ /* Initialize the RTC_HourFormat member */
+ RTC_InitStruct->RTC_HourFormat = RTC_24HOUR_FORMAT;
+
+ /* Initialize the RTC_AsynchPrediv member */
+ RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F;
+
+ /* Initialize the RTC_SynchPrediv member */
+ RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF;
+}
+
+/**
+ * @brief Enables or disables the RTC registers write protection.
+ * @note All the RTC registers are write protected except for RTC_INITSTS[13:8].
+ * @note Writing a wrong key reactivates the write protection.
+ * @note The protection mechanism is not affected by system reset.
+ * @param Cmd new state of the write protection.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RTC_EnableWriteProtection(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+ }
+ else
+ {
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+ }
+}
+
+/**
+ * @brief Enters the RTC Initialization mode.
+ * @note The RTC Initialization mode is write protected, use the
+ * RTC_EnableWriteProtection(DISABLE) before calling this function.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC is in Init mode
+ * - ERROR: RTC is not in Init mode
+ */
+ErrorStatus RTC_EnterInitMode(void)
+{
+ __IO uint32_t initcounter = 0x00;
+ ErrorStatus status = ERROR;
+ uint32_t initstatus = 0x00;
+
+ /* Check if the Initialization mode is set */
+ if ((RTC->INITSTS & RTC_INITSTS_INITF) == (uint32_t)RESET)
+ {
+ /* Set the Initialization mode */
+ RTC->INITSTS = (uint32_t)RTC_INITSTS_INITM;
+
+ /* Wait till RTC is in INIT state and if Time out is reached exit */
+ do
+ {
+ initstatus = RTC->INITSTS & RTC_INITSTS_INITF;
+ initcounter++;
+ } while ((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));
+
+ if ((RTC->INITSTS & RTC_INITSTS_INITF) != RESET)
+ {
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Exits the RTC Initialization mode.
+ * @note When the initialization sequence is complete, the calendar restarts
+ * counting after 4 RTCCLK cycles.
+ * @note The RTC Initialization mode is write protected, use the
+ * RTC_EnableWriteProtection(DISABLE) before calling this function.
+ */
+void RTC_ExitInitMode(void)
+{
+ /* Exit Initialization mode */
+ RTC->INITSTS &= (uint32_t)~RTC_INITSTS_INITM;
+}
+
+/**
+ * @brief Waits until the RTC Time and Date registers (RTC_TSH and RTC_DATE) are
+ * synchronized with RTC APB clock.
+ * @note The RTC Resynchronization mode is write protected, use the
+ * RTC_EnableWriteProtection(DISABLE) before calling this function.
+ * @note To read the calendar through the shadow registers after Calendar
+ * initialization, calendar update or after wakeup from low power modes
+ * the software must first clear the RSYF flag.
+ * The software must then wait until it is set again before reading
+ * the calendar, which means that the calendar registers have been
+ * correctly copied into the RTC_TSH and RTC_DATE shadow registers.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are synchronised
+ * - ERROR: RTC registers are not synchronised
+ */
+ErrorStatus RTC_WaitForSynchro(void)
+{
+ __IO uint32_t synchrocounter = 0;
+ ErrorStatus status = ERROR;
+ uint32_t synchrostatus = 0x00;
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Clear RSYF flag */
+ RTC->INITSTS &= (uint32_t)RTC_RSF_MASK;
+
+ /* Wait the registers to be synchronised */
+ do
+ {
+ synchrostatus = RTC->INITSTS & RTC_INITSTS_RSYF;
+ synchrocounter++;
+ } while ((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));
+
+ if ((RTC->INITSTS & RTC_INITSTS_RSYF) != RESET)
+ {
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+
+ return (status);
+}
+
+/**
+ * @brief Enables or disables the RTC reference clock detection.
+ * @param Cmd new state of the RTC reference clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC reference clock detection is enabled
+ * - ERROR: RTC reference clock detection is disabled
+ */
+ErrorStatus RTC_EnableRefClock(FunctionalState Cmd)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Set Initialization mode */
+ if (RTC_EnterInitMode() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ if (Cmd != DISABLE)
+ {
+ /* Enable the RTC reference clock detection */
+ RTC->CTRL |= RTC_CTRL_REFCLKEN;
+ }
+ else
+ {
+ /* Disable the RTC reference clock detection */
+ RTC->CTRL &= ~RTC_CTRL_REFCLKEN;
+ }
+ /* Exit Initialization mode */
+ RTC_ExitInitMode();
+
+ status = SUCCESS;
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+
+ return status;
+}
+
+/**
+ * @brief Enables or Disables the Bypass Shadow feature.
+ * @note When the Bypass Shadow is enabled the calendar value are taken
+ * directly from the Calendar counter.
+ * @param Cmd new state of the Bypass Shadow feature.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RTC_EnableBypassShadow(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ if (Cmd != DISABLE)
+ {
+ /* Set the BYPS bit */
+ RTC->CTRL |= (uint8_t)RTC_CTRL_BYPS;
+ }
+ else
+ {
+ /* Reset the BYPS bit */
+ RTC->CTRL &= (uint8_t)~RTC_CTRL_BYPS;
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group2 Time and Date configuration functions
+ * @brief Time and Date configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Time and Date configuration functions #####
+ ===============================================================================
+ [..] This section provide functions allowing to program and read the RTC
+ Calendar (Time and Date).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set the RTC current time.
+ * @param RTC_Format specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN Binary data format.
+ * @arg RTC_FORMAT_BCD BCD data format.
+ * @param RTC_TimeStruct pointer to a RTC_TimeType structure that contains
+ * the time configuration information for the RTC.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Time register is configured
+ * - ERROR: RTC Time register is not configured
+ */
+ErrorStatus RTC_ConfigTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct)
+{
+ uint32_t tmpregister = 0;
+ ErrorStatus status = ERROR;
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+ if (RTC_Format == RTC_FORMAT_BIN)
+ {
+ if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET)
+ {
+ assert_param(IS_RTC_12HOUR(RTC_TimeStruct->Hours));
+ assert_param(IS_RTC_H12(RTC_TimeStruct->H12));
+ }
+ else
+ {
+ RTC_TimeStruct->H12 = 0x00;
+ assert_param(IS_RTC_24HOUR(RTC_TimeStruct->Hours));
+ }
+ assert_param(IS_RTC_MINUTES(RTC_TimeStruct->Minutes));
+ assert_param(IS_RTC_SECONDS(RTC_TimeStruct->Seconds));
+ }
+ else
+ {
+ if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET)
+ {
+ tmpregister = RTC_Bcd2ToByte(RTC_TimeStruct->Hours);
+ assert_param(IS_RTC_12HOUR(tmpregister));
+ assert_param(IS_RTC_H12(RTC_TimeStruct->H12));
+ }
+ else
+ {
+ RTC_TimeStruct->H12 = 0x00;
+ assert_param(IS_RTC_24HOUR(RTC_Bcd2ToByte(RTC_TimeStruct->Hours)));
+ }
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->Seconds)));
+ }
+ /* Check the input parameters format */
+ if (RTC_Format != RTC_FORMAT_BIN)
+ {
+ tmpregister = (((uint32_t)(RTC_TimeStruct->Hours) << 16) | ((uint32_t)(RTC_TimeStruct->Minutes) << 8)
+ | ((uint32_t)RTC_TimeStruct->Seconds) | ((uint32_t)(RTC_TimeStruct->H12) << 16));
+ }
+ else
+ {
+ tmpregister =
+ (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->Hours) << 16)
+ | ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->Minutes) << 8)
+ | ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->Seconds)) | (((uint32_t)RTC_TimeStruct->H12) << 16));
+ }
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+ /* Set Initialization mode */
+ if (RTC_EnterInitMode() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ /* Set the RTC_TSH register */
+ RTC->TSH = (uint32_t)(tmpregister & RTC_TR_RESERVED_MASK);
+ /* Exit Initialization mode */
+ RTC_ExitInitMode();
+ /* If RTC_CTRL_BYPS bit = 0, wait for synchro else this check is not needed */
+ if ((RTC->CTRL & RTC_CTRL_BYPS) == RESET)
+ {
+ if (RTC_WaitForSynchro() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+ /* Waits until the RTC Time and Date registers
+ (RTC_TSH and RTC_DATE) are synchronized with RTC APB clock. */
+ status=RTC_WaitForSynchro();
+ return status;
+}
+
+/**
+ * @brief Fills each RTC_TimeStruct member with its default value
+ * (Time = 00h:00min:00sec).
+ * @param RTC_TimeStruct pointer to a RTC_TimeType structure which will be
+ * initialized.
+ */
+void RTC_TimeStructInit(RTC_TimeType* RTC_TimeStruct)
+{
+ /* Time = 00h:00min:00sec */
+ RTC_TimeStruct->H12 = RTC_AM_H12;
+ RTC_TimeStruct->Hours = 0;
+ RTC_TimeStruct->Minutes = 0;
+ RTC_TimeStruct->Seconds = 0;
+}
+
+/**
+ * @brief Get the RTC current Time.
+ * @param RTC_Format specifies the format of the returned parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN Binary data format.
+ * @arg RTC_FORMAT_BCD BCD data format.
+ * @param RTC_TimeStruct pointer to a RTC_TimeType structure that will
+ * contain the returned current time configuration.
+ */
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+
+ /* Get the RTC_TSH register */
+ tmpregister = (uint32_t)(RTC->TSH & RTC_TR_RESERVED_MASK);
+
+ /* Fill the structure fields with the read parameters */
+ RTC_TimeStruct->Hours = (uint8_t)((tmpregister & (RTC_TSH_HOT | RTC_TSH_HOU)) >> 16);
+ RTC_TimeStruct->Minutes = (uint8_t)((tmpregister & (RTC_TSH_MIT | RTC_TSH_MIU)) >> 8);
+ RTC_TimeStruct->Seconds = (uint8_t)(tmpregister & (RTC_TSH_SCT | RTC_TSH_SCU));
+ RTC_TimeStruct->H12 = (uint8_t)((tmpregister & (RTC_TSH_APM)) >> 16);
+
+ /* Check the input parameters format */
+ if (RTC_Format == RTC_FORMAT_BIN)
+ {
+ /* Convert the structure parameters to Binary format */
+ RTC_TimeStruct->Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->Hours);
+ RTC_TimeStruct->Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->Minutes);
+ RTC_TimeStruct->Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->Seconds);
+ }
+}
+
+/**
+ * @brief Gets the RTC current Calendar Subseconds value.
+ * @return RTC current Calendar Subseconds value.
+ */
+uint32_t RTC_GetSubSecond(void)
+{
+ uint32_t tmpregister = 0;
+
+ /* Get subseconds values from the correspondent registers*/
+ tmpregister = (uint32_t)(RTC->SUBS);
+
+ return (tmpregister);
+}
+
+/**
+ * @brief Set the RTC current date.
+ * @param RTC_Format specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN Binary data format.
+ * @arg RTC_FORMAT_BCD BCD data format.
+ * @param RTC_DateStruct pointer to a RTC_DateType structure that contains
+ * the date configuration information for the RTC.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Date register is configured
+ * - ERROR: RTC Date register is not configured
+ */
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct)
+{
+ uint32_t tmpregister = 0;
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+
+ if ((RTC_Format == RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10) == 0x10))
+ {
+ RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint32_t) ~(0x10)) + 0x0A;
+ }
+ if (RTC_Format == RTC_FORMAT_BIN)
+ {
+ assert_param(IS_RTC_YEAR(RTC_DateStruct->Year));
+ assert_param(IS_RTC_MONTH(RTC_DateStruct->Month));
+ assert_param(IS_RTC_DATE(RTC_DateStruct->Date));
+ }
+ else
+ {
+ assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->Year)));
+ tmpregister = RTC_Bcd2ToByte(RTC_DateStruct->Month);
+ assert_param(IS_RTC_MONTH(tmpregister));
+ tmpregister = RTC_Bcd2ToByte(RTC_DateStruct->Date);
+ assert_param(IS_RTC_DATE(tmpregister));
+ }
+ assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->WeekDay));
+
+ /* Check the input parameters format */
+ if (RTC_Format != RTC_FORMAT_BIN)
+ {
+ tmpregister = ((((uint32_t)RTC_DateStruct->Year) << 16) | (((uint32_t)RTC_DateStruct->Month) << 8)
+ | ((uint32_t)RTC_DateStruct->Date) | (((uint32_t)RTC_DateStruct->WeekDay) << 13));
+ }
+ else
+ {
+ tmpregister = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->Year) << 16)
+ | ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->Month) << 8)
+ | ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->Date)) | ((uint32_t)RTC_DateStruct->WeekDay << 13));
+ }
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Set Initialization mode */
+ if (RTC_EnterInitMode() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ /* Set the RTC_DATE register */
+ RTC->DATE = (uint32_t)(tmpregister & RTC_DATE_RESERVED_MASK);
+
+ /* Exit Initialization mode */
+ RTC_ExitInitMode();
+
+ /* If RTC_CTRL_BYPS bit = 0, wait for synchro else this check is not needed */
+ if ((RTC->CTRL & RTC_CTRL_BYPS) == RESET)
+ {
+ if (RTC_WaitForSynchro() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+ /* Waits until the RTC Time and Date registers
+ (RTC_TSH and RTC_DATE) are synchronized with RTC APB clock. */
+ status=RTC_WaitForSynchro();
+ return status;
+}
+
+/**
+ * @brief Fills each RTC_DateStruct member with its default value
+ * (Monday, January 01 xx00).
+ * @param RTC_DateStruct pointer to a RTC_DateType structure which will be
+ * initialized.
+ */
+void RTC_DateStructInit(RTC_DateType* RTC_DateStruct)
+{
+ /* Monday, January 01 xx00 */
+ RTC_DateStruct->WeekDay = RTC_WEEKDAY_MONDAY;
+ RTC_DateStruct->Date = 1;
+ RTC_DateStruct->Month = RTC_MONTH_JANUARY;
+ RTC_DateStruct->Year = 0;
+}
+
+/**
+ * @brief Get the RTC current date.
+ * @param RTC_Format specifies the format of the returned parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN Binary data format.
+ * @arg RTC_FORMAT_BCD BCD data format.
+ * @param RTC_DateStruct pointer to a RTC_DateType structure that will
+ * contain the returned current date configuration.
+ */
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+
+ /* Get the RTC_TSH register */
+ tmpregister = (uint32_t)(RTC->DATE & RTC_DATE_RESERVED_MASK);
+
+ /* Fill the structure fields with the read parameters */
+ RTC_DateStruct->Year = (uint8_t)((tmpregister & (RTC_DATE_YRT | RTC_DATE_YRU)) >> 16);
+ RTC_DateStruct->Month = (uint8_t)((tmpregister & (RTC_DATE_MOT | RTC_DATE_MOU)) >> 8);
+ RTC_DateStruct->Date = (uint8_t)(tmpregister & (RTC_DATE_DAT | RTC_DATE_DAU));
+ RTC_DateStruct->WeekDay = (uint8_t)((tmpregister & (RTC_DATE_WDU)) >> 13);
+
+ /* Check the input parameters format */
+ if (RTC_Format == RTC_FORMAT_BIN)
+ {
+ /* Convert the structure parameters to Binary format */
+ RTC_DateStruct->Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->Year);
+ RTC_DateStruct->Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->Month);
+ RTC_DateStruct->Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->Date);
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group3 Alarms configuration functions
+ * @brief Alarms (Alarm A and Alarm B) configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Alarms (Alarm A and Alarm B) configuration functions #####
+ ===============================================================================
+ [..] This section provide functions allowing to program and read the RTC
+ Alarms.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set the specified RTC Alarm.
+ * @note The Alarm register can only be written when the corresponding Alarm
+ * is disabled (Use the RTC_EnableAlarm(DISABLE)).
+ * @param RTC_Format specifies the format of the returned parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN Binary data format.
+ * @arg RTC_FORMAT_BCD BCD data format.
+ * @param RTC_Alarm specifies the alarm to be configured.
+ * This parameter can be one of the following values:
+ * @arg RTC_A_ALARM to select Alarm A.
+ * @arg RTC_B_ALARM to select Alarm B.
+ * @param RTC_AlarmStruct pointer to a RTC_AlarmType structure that
+ * contains the alarm configuration parameters.
+ */
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+ assert_param(IS_RTC_ALARM_SEL(RTC_Alarm));
+ assert_param(IS_ALARM_MASK(RTC_AlarmStruct->AlarmMask));
+ assert_param(IS_RTC_ALARM_WEEKDAY_SEL(RTC_AlarmStruct->DateWeekMode));
+
+ if (RTC_Format == RTC_FORMAT_BIN)
+ {
+ if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET)
+ {
+ assert_param(IS_RTC_12HOUR(RTC_AlarmStruct->AlarmTime.Hours));
+ assert_param(IS_RTC_H12(RTC_AlarmStruct->AlarmTime.H12));
+ }
+ else
+ {
+ RTC_AlarmStruct->AlarmTime.H12 = 0x00;
+ assert_param(IS_RTC_24HOUR(RTC_AlarmStruct->AlarmTime.Hours));
+ }
+ assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
+ assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
+
+ if (RTC_AlarmStruct->DateWeekMode == RTC_ALARM_SEL_WEEKDAY_DATE)
+ {
+ assert_param(IS_RTC_ALARM_WEEKDAY_DATE(RTC_AlarmStruct->DateWeekValue));
+ }
+ else
+ {
+ assert_param(IS_RTC_ALARM_WEEKDAY_WEEKDAY(RTC_AlarmStruct->DateWeekValue));
+ }
+ }
+ else
+ {
+ if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET)
+ {
+ tmpregister = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Hours);
+ assert_param(IS_RTC_12HOUR(tmpregister));
+ assert_param(IS_RTC_H12(RTC_AlarmStruct->AlarmTime.H12));
+ }
+ else
+ {
+ RTC_AlarmStruct->AlarmTime.H12 = 0x00;
+ assert_param(IS_RTC_24HOUR(RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Hours)));
+ }
+
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Seconds)));
+
+ if (RTC_AlarmStruct->DateWeekMode == RTC_ALARM_SEL_WEEKDAY_DATE)
+ {
+ tmpregister = RTC_Bcd2ToByte(RTC_AlarmStruct->DateWeekValue);
+ assert_param(IS_RTC_ALARM_WEEKDAY_DATE(tmpregister));
+ }
+ else
+ {
+ tmpregister = RTC_Bcd2ToByte(RTC_AlarmStruct->DateWeekValue);
+ assert_param(IS_RTC_ALARM_WEEKDAY_WEEKDAY(tmpregister));
+ }
+ }
+
+ /* Check the input parameters format */
+ if (RTC_Format != RTC_FORMAT_BIN)
+ {
+ tmpregister =
+ (((uint32_t)(RTC_AlarmStruct->AlarmTime.Hours) << 16)
+ | ((uint32_t)(RTC_AlarmStruct->AlarmTime.Minutes) << 8) | ((uint32_t)RTC_AlarmStruct->AlarmTime.Seconds)
+ | ((uint32_t)(RTC_AlarmStruct->AlarmTime.H12) << 16) | ((uint32_t)(RTC_AlarmStruct->DateWeekValue) << 24)
+ | ((uint32_t)RTC_AlarmStruct->DateWeekMode) | ((uint32_t)RTC_AlarmStruct->AlarmMask));
+ }
+ else
+ {
+ tmpregister = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->AlarmTime.Hours) << 16)
+ | ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->AlarmTime.Minutes) << 8)
+ | ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->AlarmTime.Seconds))
+ | ((uint32_t)(RTC_AlarmStruct->AlarmTime.H12) << 16)
+ | ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->DateWeekValue) << 24)
+ | ((uint32_t)RTC_AlarmStruct->DateWeekMode) | ((uint32_t)RTC_AlarmStruct->AlarmMask));
+ }
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Configure the Alarm register */
+ if (RTC_Alarm == RTC_A_ALARM)
+ {
+ RTC->ALARMA = (uint32_t)tmpregister;
+ }
+ else
+ {
+ RTC->ALARMB = (uint32_t)tmpregister;
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Fills each RTC_AlarmStruct member with its default value
+ * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask =
+ * all fields are masked).
+ * @param RTC_AlarmStruct pointer to a @ref RTC_AlarmType structure which
+ * will be initialized.
+ */
+void RTC_AlarmStructInit(RTC_AlarmType* RTC_AlarmStruct)
+{
+ /* Alarm Time Settings : Time = 00h:00mn:00sec */
+ RTC_AlarmStruct->AlarmTime.H12 = RTC_AM_H12;
+ RTC_AlarmStruct->AlarmTime.Hours = 0;
+ RTC_AlarmStruct->AlarmTime.Minutes = 0;
+ RTC_AlarmStruct->AlarmTime.Seconds = 0;
+
+ /* Alarm Date Settings : Date = 1st day of the month */
+ RTC_AlarmStruct->DateWeekMode = RTC_ALARM_SEL_WEEKDAY_DATE;
+ RTC_AlarmStruct->DateWeekValue = 1;
+
+ /* Alarm Masks Settings : Mask = all fields are not masked */
+ RTC_AlarmStruct->AlarmMask = RTC_ALARMMASK_NONE;
+}
+
+/**
+ * @brief Get the RTC Alarm value and masks.
+ * @param RTC_Format specifies the format of the output parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN Binary data format.
+ * @arg RTC_FORMAT_BCD BCD data format.
+ * @param RTC_Alarm specifies the alarm to be read.
+ * This parameter can be one of the following values:
+ * @arg RTC_A_ALARM to select Alarm A.
+ * @arg RTC_B_ALARM to select Alarm B.
+ * @param RTC_AlarmStruct pointer to a RTC_AlarmType structure that will
+ * contains the output alarm configuration values.
+ */
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+ assert_param(IS_RTC_ALARM_SEL(RTC_Alarm));
+
+ /* Get the RTC_ALARMx register */
+ if (RTC_Alarm == RTC_A_ALARM)
+ {
+ tmpregister = (uint32_t)(RTC->ALARMA);
+ }
+ else
+ {
+ tmpregister = (uint32_t)(RTC->ALARMB);
+ }
+
+ /* Fill the structure with the read parameters */
+ RTC_AlarmStruct->AlarmTime.Hours = (uint32_t)((tmpregister & (RTC_ALARMA_HOT | RTC_ALARMA_HOU)) >> 16);
+ RTC_AlarmStruct->AlarmTime.Minutes = (uint32_t)((tmpregister & (RTC_ALARMA_MIT | RTC_ALARMA_MIU)) >> 8);
+ RTC_AlarmStruct->AlarmTime.Seconds = (uint32_t)(tmpregister & (RTC_ALARMA_SET | RTC_ALARMA_SEU));
+ RTC_AlarmStruct->AlarmTime.H12 = (uint32_t)((tmpregister & RTC_ALARMA_APM) >> 16);
+ RTC_AlarmStruct->DateWeekValue = (uint32_t)((tmpregister & (RTC_ALARMA_DTT | RTC_ALARMA_DTU)) >> 24);
+ RTC_AlarmStruct->DateWeekMode = (uint32_t)(tmpregister & RTC_ALARMA_WKDSEL);
+ RTC_AlarmStruct->AlarmMask = (uint32_t)(tmpregister & RTC_ALARMMASK_ALL);
+
+ if (RTC_Format == RTC_FORMAT_BIN)
+ {
+ RTC_AlarmStruct->AlarmTime.Hours = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Hours);
+ RTC_AlarmStruct->AlarmTime.Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Minutes);
+ RTC_AlarmStruct->AlarmTime.Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Seconds);
+ RTC_AlarmStruct->DateWeekValue = RTC_Bcd2ToByte(RTC_AlarmStruct->DateWeekValue);
+ }
+}
+
+/**
+ * @brief Enables or disables the specified RTC Alarm.
+ * @param RTC_Alarm specifies the alarm to be configured.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_A_ALARM to select Alarm A.
+ * @arg RTC_B_ALARM to select Alarm B.
+ * @param Cmd new state of the specified alarm.
+ * This parameter can be: ENABLE or DISABLE.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Alarm is enabled/disabled
+ * - ERROR: RTC Alarm is not enabled/disabled
+ */
+ErrorStatus RTC_EnableAlarm(uint32_t RTC_Alarm, FunctionalState Cmd)
+{
+ __IO uint32_t alarmcounter = 0x00;
+ uint32_t alarmstatus = 0x00;
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALARM_ENABLE(RTC_Alarm));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Configure the Alarm state */
+ if (Cmd != DISABLE)
+ {
+ RTC->CTRL |= (uint32_t)RTC_Alarm;
+
+ status = SUCCESS;
+ }
+ else
+ {
+ /* Disable the Alarm in RTC_CTRL register */
+ RTC->CTRL &= (uint32_t)~RTC_Alarm;
+
+ /* Wait till RTC ALxWF flag is set and if Time out is reached exit */
+ do
+ {
+ alarmstatus = RTC->INITSTS & (RTC_Alarm >> 8);
+ alarmcounter++;
+ } while ((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00));
+
+ if ((RTC->INITSTS & (RTC_Alarm >> 8)) == RESET)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+
+ return status;
+}
+
+/**
+ * @brief Configure the RTC AlarmA/B Subseconds value and mask.*
+ * @note This function is performed only when the Alarm is disabled.
+ * @param RTC_Alarm specifies the alarm to be configured.
+ * This parameter can be one of the following values:
+ * @arg RTC_A_ALARM to select Alarm A.
+ * @arg RTC_B_ALARM to select Alarm B.
+ * @param RTC_AlarmSubSecondValue specifies the Subseconds value.
+ * This parameter can be a value from 0 to 0x00007FFF.
+ * @param RTC_AlarmSubSecondMask specifies the Subseconds Mask.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_SUBS_MASK_ALL All Alarm SS fields are masked.
+ * There is no comparison on sub seconds for Alarm.
+ * @arg RTC_SUBS_MASK_SS14_1 SS[14:1] are don't care in Alarm comparison.
+ * Only SS[0] is compared
+ * @arg RTC_SUBS_MASK_SS14_2 SS[14:2] are don't care in Alarm comparison.
+ * Only SS[1:0] are compared
+ * @arg RTC_SUBS_MASK_SS14_3 SS[14:3] are don't care in Alarm comparison.
+ * Only SS[2:0] are compared
+ * @arg RTC_SUBS_MASK_SS14_4 SS[14:4] are don't care in Alarm comparison.
+ * Only SS[3:0] are compared
+ * @arg RTC_SUBS_MASK_SS14_5 SS[14:5] are don't care in Alarm comparison.
+ * Only SS[4:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_6 SS[14:6] are don't care in Alarm comparison.
+ * Only SS[5:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_7 SS[14:7] are don't care in Alarm comparison.
+ * Only SS[6:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_8 SS[14:8] are don't care in Alarm comparison.
+ * Only SS[7:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_9 SS[14:9] are don't care in Alarm comparison.
+ * Only SS[8:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_10 SS[14:10] are don't care in Alarm comparison.
+ * Only SS[9:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_11 SS[14:11] are don't care in Alarm comparison.
+ * Only SS[10:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_12 SS[14:12] are don't care in Alarm comparison.
+ * Only SS[11:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_13 SS[14:13] are don't care in Alarm comparison.
+ * Only SS[12:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_14 SS[14] is don't care in Alarm comparison.
+ * Only SS[13:0] are compared.
+ * @arg RTC_SUBS_MASK_NONE SS[14:0] are compared and must match
+ * to activate alarm.
+ */
+void RTC_ConfigAlarmSubSecond(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALARM_SEL(RTC_Alarm));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_MASK_MODE(RTC_AlarmSubSecondMask));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Configure the Alarm A or Alarm B SubSecond registers */
+ tmpregister = (uint32_t)(uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask);
+
+ if (RTC_Alarm == RTC_A_ALARM)
+ {
+ /* Configure the AlarmA SubSecond register */
+ RTC->ALRMASS = tmpregister;
+ }
+ else
+ {
+ /* Configure the Alarm B SubSecond register */
+ RTC->ALRMBSS = tmpregister;
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Gets the RTC Alarm Subseconds value.
+ * @param RTC_Alarm specifies the alarm to be read.
+ * This parameter can be one of the following values:
+ * @arg RTC_A_ALARM to select Alarm A.
+ * @arg RTC_B_ALARM to select Alarm B.
+ * @return RTC Alarm Subseconds value.
+ */
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm)
+{
+ uint32_t tmpregister = 0;
+
+ /* Get the RTC_ALARMx register */
+ if (RTC_Alarm == RTC_A_ALARM)
+ {
+ tmpregister = (uint32_t)((RTC->ALRMASS) & RTC_ALRMASS_SSV);
+ }
+ else
+ {
+ tmpregister = (uint32_t)((RTC->ALRMBSS) & RTC_ALRMBSS_SSV);
+ }
+
+ return (tmpregister);
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group4 WakeUp Timer configuration functions
+ * @brief WakeUp Timer configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### WakeUp Timer configuration functions #####
+ ===============================================================================
+ [..] This section provide functions allowing to program and read the RTC WakeUp.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the RTC Wakeup clock source.
+ * @note The WakeUp Clock source can only be changed when the RTC WakeUp
+ * is disabled (Use the RTC_EnableWakeUp(DISABLE)).
+ * @param RTC_WakeUpClock Wakeup Clock source.
+ * This parameter can be one of the following values:
+ * @arg RTC_WKUPCLK_RTCCLK_DIV16 RTC Wakeup Counter Clock = RTCCLK/16.
+ * @arg RTC_WKUPCLK_RTCCLK_DIV8 RTC Wakeup Counter Clock = RTCCLK/8.
+ * @arg RTC_WKUPCLK_RTCCLK_DIV4 RTC Wakeup Counter Clock = RTCCLK/4.
+ * @arg RTC_WKUPCLK_RTCCLK_DIV2 RTC Wakeup Counter Clock = RTCCLK/2.
+ * @arg RTC_WKUPCLK_CK_SPRE_16BITS RTC Wakeup Counter Clock = CK_SPRE.
+ * @arg RTC_WKUPCLK_CK_SPRE_17BITS RTC Wakeup Counter Clock = CK_SPRE.
+ */
+void RTC_ConfigWakeUpClock(uint32_t RTC_WakeUpClock)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_WKUP_CLOCK(RTC_WakeUpClock));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Clear the Wakeup Timer clock source bits in CTRL register */
+ RTC->CTRL &= (uint32_t)~RTC_CTRL_WKUPSEL;
+
+ /* Configure the clock source */
+ RTC->CTRL |= (uint32_t)RTC_WakeUpClock;
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Configures the RTC Wakeup counter.
+ * @note The RTC WakeUp counter can only be written when the RTC WakeUp.
+ * is disabled (Use the RTC_EnableWakeUp(DISABLE)).
+ * @param RTC_WakeUpCounter specifies the WakeUp counter.
+ * This parameter can be a value from 0x0000 to 0xFFFF.
+ */
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_WKUP_COUNTER(RTC_WakeUpCounter));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Configure the Wakeup Timer counter */
+ RTC->WKUPT = (uint32_t)RTC_WakeUpCounter;
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Returns the RTC WakeUp timer counter value.
+ * @return The RTC WakeUp Counter value.
+ */
+uint32_t RTC_GetWakeUpCounter(void)
+{
+ /* Get the counter value */
+ return ((uint32_t)(RTC->WKUPT & RTC_WKUPT_WKUPT));
+}
+
+/**
+ * @brief Enables or Disables the RTC WakeUp timer.
+ * @param Cmd new state of the WakeUp timer.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+ErrorStatus RTC_EnableWakeUp(FunctionalState Cmd)
+{
+ __IO uint32_t wutcounter = 0x00;
+ uint32_t wutwfstatus = 0x00;
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the Wakeup Timer */
+ RTC->CTRL |= (uint32_t)RTC_CTRL_WTEN;
+ status = SUCCESS;
+ }
+ else
+ {
+ /* Disable the Wakeup Timer */
+ RTC->CTRL &= (uint32_t)~RTC_CTRL_WTEN;
+ /* Wait till RTC WTWF flag is set and if Time out is reached exit */
+ do
+ {
+ wutwfstatus = RTC->INITSTS & RTC_INITSTS_WTWF;
+ wutcounter++;
+ } while ((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
+
+ if ((RTC->INITSTS & RTC_INITSTS_WTWF) == RESET)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group5 Daylight Saving configuration functions
+ * @brief Daylight Saving configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Daylight Saving configuration functions #####
+ ===============================================================================
+ [..] This section provide functions allowing to configure the RTC DayLight Saving.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Adds or substract one hour from the current time.
+ * @param RTC_DayLightSaving the value of hour adjustment.
+ * This parameter can be one of the following values:
+ * @arg RTC_DAYLIGHT_SAVING_SUB1H Substract one hour (winter time).
+ * @arg RTC_DAYLIGHT_SAVING_ADD1H Add one hour (summer time).
+ * @param RTC_StoreOperation Specifies the value to be written in the BCK bit
+ * in CTRL register to store the operation.
+ * This parameter can be one of the following values:
+ * @arg RTC_STORE_OPERATION_RESET BCK Bit Reset.
+ * @arg RTC_STORE_OPERATION_SET BCK Bit Set.
+ */
+void RTC_ConfigDayLightSaving(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving));
+ assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Clear the bits to be configured */
+ RTC->CTRL &= (uint32_t) ~(RTC_CTRL_BAKP);
+ /* Clear the SU1H and AD1H bits to be configured */
+ RTC->CTRL &= (uint32_t) ~(RTC_CTRL_SU1H & RTC_CTRL_AD1H);
+ /* Configure the RTC_CTRL register */
+ RTC->CTRL |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation);
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Returns the RTC Day Light Saving stored operation.
+ * @return RTC Day Light Saving stored operation.
+ * - RTC_STORE_OPERATION_RESET
+ * - RTC_STORE_OPERATION_SET
+ */
+uint32_t RTC_GetStoreOperation(void)
+{
+ return (RTC->CTRL & RTC_CTRL_BAKP);
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group6 Output pin Configuration function
+ * @brief Output pin Configuration function
+ *
+@verbatim
+ ===============================================================================
+ ##### Output pin Configuration function #####
+ ===============================================================================
+ [..] This section provide functions allowing to configure the RTC Output source.
+
+@endverbatim
+ * @{
+ */
+
+
+
+/**
+ * @brief Configures the RTC output source (AFO_ALARM).
+ * @param RTC_Output Specifies which signal will be routed to the RTC output.
+ * This parameter can be one of the following values:
+ * @arg RTC_OUTPUT_DIS No output selected
+ * @arg RTC_OUTPUT_ALA signal of AlarmA mapped to output.
+ * @arg RTC_OUTPUT_ALB signal of AlarmB mapped to output.
+ * @arg RTC_OUTPUT_WKUP signal of WakeUp mapped to output.
+ * @param RTC_OutputPolarity Specifies the polarity of the output signal.
+ * This parameter can be one of the following:
+ * @arg RTC_OUTPOL_HIGH The output pin is high when the
+ * ALRAF/ALRBF/WUTF is high (depending on OSEL).
+ * @arg RTC_OUTPOL_LOW The output pin is low when the
+ * ALRAF/ALRBF/WUTF is high (depending on OSEL).
+ */
+void RTC_ConfigOutput(uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_OUTPUT_MODE(RTC_Output));
+ assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Clear the bits to be configured */
+ RTC->CTRL &= (uint32_t) ~(RTC_CTRL_OUTSEL | RTC_CTRL_OPOL);
+
+ /* Configure the output selection and polarity */
+ RTC->CTRL |= (uint32_t)(RTC_Output | RTC_OutputPolarity);
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group7 Coarse and Smooth Calibrations configuration functions
+ * @brief Coarse and Smooth Calibrations configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Coarse and Smooth Calibrations configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the RTC clock to be output through the relative
+ * pin.
+ * @param Cmd new state of the coarse calibration Output.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RTC_EnableCalibOutput(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the RTC clock output */
+ RTC->CTRL |= (uint32_t)RTC_CTRL_COEN;
+ }
+ else
+ {
+ /* Disable the RTC clock output */
+ RTC->CTRL &= (uint32_t)~RTC_CTRL_COEN;
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ * @param RTC_CalibOutput Select the Calibration output Selection .
+ * This parameter can be one of the following values:
+ * @arg RTC_CALIB_OUTPUT_256HZ A signal has a regular waveform at 256Hz.
+ * @arg RTC_CALIB_OUTPUT_1HZ A signal has a regular waveform at 1Hz.
+ */
+void RTC_ConfigCalibOutput(uint32_t RTC_CalibOutput)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /*clear flags before config*/
+ RTC->CTRL &= (uint32_t) ~(RTC_CTRL_CALOSEL);
+
+ /* Configure the RTC_CTRL register */
+ RTC->CTRL |= (uint32_t)RTC_CalibOutput;
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Configures the Smooth Calibration Settings.
+ * @param RTC_SmoothCalibPeriod Select the Smooth Calibration Period.
+ * This parameter can be can be one of the following values:
+ * @arg SMOOTH_CALIB_32SEC The smooth calibration periode is 32s.
+ * @arg SMOOTH_CALIB_16SEC The smooth calibration periode is 16s.
+ * @arg SMOOTH_CALIB_8SEC The smooth calibartion periode is 8s.
+ * @param RTC_SmoothCalibPlusPulses Select to Set or reset the CALP bit.
+ * This parameter can be one of the following values:
+ * @arg RTC_SMOOTH_CALIB_PLUS_PULSES_SET Add one RTCCLK puls every 2**11 pulses.
+ * @arg RTC_SMOOTH_CALIB_PLUS_PULSES__RESET No RTCCLK pulses are added.
+ * @param RTC_SmouthCalibMinusPulsesValue Select the value of CALM[8:0] bits.
+ * This parameter can be one any value from 0 to 0x000001FF.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Calib registers are configured
+ * - ERROR: RTC Calib registers are not configured
+ */
+ErrorStatus RTC_ConfigSmoothCalib(uint32_t RTC_SmoothCalibPeriod,
+ uint32_t RTC_SmoothCalibPlusPulses,
+ uint32_t RTC_SmouthCalibMinusPulsesValue)
+{
+ ErrorStatus status = ERROR;
+ uint32_t recalpfcount = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_SMOOTH_CALIB_PERIOD_SEL(RTC_SmoothCalibPeriod));
+ assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses));
+ assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* check if a calibration is pending*/
+ if ((RTC->INITSTS & RTC_INITSTS_RECPF) != RESET)
+ {
+ /* wait until the Calibration is completed*/
+ while (((RTC->INITSTS & RTC_INITSTS_RECPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT))
+ {
+ recalpfcount++;
+ }
+ }
+
+ /* check if the calibration pending is completed or if there is no calibration operation at all*/
+ if ((RTC->INITSTS & RTC_INITSTS_RECPF) == RESET)
+ {
+ /* Configure the Smooth calibration settings */
+ RTC->CALIB = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses
+ | (uint32_t)RTC_SmouthCalibMinusPulsesValue);
+
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+
+ return (ErrorStatus)(status);
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group8 TimeStamp configuration functions
+ * @brief TimeStamp configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### TimeStamp configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or Disables the RTC TimeStamp functionality with the
+ * specified time stamp pin stimulating edge.
+ * @param RTC_TimeStampEdge Specifies the pin edge on which the TimeStamp is
+ * activated.
+ * This parameter can be one of the following:
+ * @arg RTC_TIMESTAMP_EDGE_RISING the Time stamp event occurs on the rising
+ * edge of the related pin.
+ * @arg RTC_TIMESTAMP_EDGE_FALLING the Time stamp event occurs on the
+ * falling edge of the related pin.
+ * @param Cmd new state of the TimeStamp.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RTC_EnableTimeStamp(uint32_t RTC_TimeStampEdge, FunctionalState Cmd)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_TIMESTAMP_EDGE_MODE(RTC_TimeStampEdge));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ /* Get the RTC_CTRL register and clear the bits to be configured */
+ tmpregister = (uint32_t)(RTC->CTRL & (uint32_t) ~(RTC_CTRL_TEDGE | RTC_CTRL_TSEN));
+
+ /* Get the new configuration */
+ if (Cmd != DISABLE)
+ {
+ tmpregister |= (uint32_t)(RTC_TimeStampEdge | RTC_CTRL_TSEN);
+ }
+ else
+ {
+ tmpregister |= (uint32_t)(RTC_TimeStampEdge);
+ }
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Configure the Time Stamp TSEDGE and Enable bits */
+ RTC->CTRL = (uint32_t)tmpregister;
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Get the RTC TimeStamp value and masks.
+ * @param RTC_Format specifies the format of the output parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN Binary data format
+ * @arg RTC_FORMAT_BCD BCD data format
+ * @param RTC_StampTimeStruct pointer to a RTC_TimeType structure that will
+ * contains the TimeStamp time values.
+ * @param RTC_StampDateStruct pointer to a RTC_DateType structure that will
+ * contains the TimeStamp date values.
+ */
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeType* RTC_StampTimeStruct, RTC_DateType* RTC_StampDateStruct)
+{
+ uint32_t tmptime = 0, tmpdate = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+
+ /* Get the TimeStamp time and date registers values */
+ tmptime = (uint32_t)(RTC->TST & RTC_TR_RESERVED_MASK);
+ tmpdate = (uint32_t)(RTC->TSD & RTC_DATE_RESERVED_MASK);
+
+ /* Fill the Time structure fields with the read parameters */
+ RTC_StampTimeStruct->Hours = (uint8_t)((tmptime & (RTC_TSH_HOT | RTC_TSH_HOU)) >> 16);
+ RTC_StampTimeStruct->Minutes = (uint8_t)((tmptime & (RTC_TSH_MIT | RTC_TSH_MIU)) >> 8);
+ RTC_StampTimeStruct->Seconds = (uint8_t)(tmptime & (RTC_TSH_SCT | RTC_TSH_SCU));
+ RTC_StampTimeStruct->H12 = (uint8_t)((tmptime & (RTC_TSH_APM)) >> 16);
+
+ /* Fill the Date structure fields with the read parameters */
+ RTC_StampDateStruct->Year = (uint8_t)((tmpdate & (RTC_DATE_YRT | RTC_DATE_YRU)) >> 16);
+ RTC_StampDateStruct->Month = (uint8_t)((tmpdate & (RTC_DATE_MOT | RTC_DATE_MOU)) >> 8);
+ RTC_StampDateStruct->Date = (uint8_t)(tmpdate & (RTC_DATE_DAT | RTC_DATE_DAU));
+ RTC_StampDateStruct->WeekDay = (uint8_t)((tmpdate & (RTC_DATE_WDU)) >> 13);
+
+ /* Check the input parameters format */
+ if (RTC_Format == RTC_FORMAT_BIN)
+ {
+ /* Convert the Time structure parameters to Binary format */
+ RTC_StampTimeStruct->Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->Hours);
+ RTC_StampTimeStruct->Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->Minutes);
+ RTC_StampTimeStruct->Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->Seconds);
+
+ /* Convert the Date structure parameters to Binary format */
+ RTC_StampDateStruct->Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->Month);
+ RTC_StampDateStruct->Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->Date);
+ RTC_StampDateStruct->WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->WeekDay);
+ }
+}
+
+/**
+ * @brief Get the RTC timestamp Subseconds value.
+ * @return RTC current timestamp Subseconds value.
+ */
+uint32_t RTC_GetTimeStampSubSecond(void)
+{
+ /* Get timestamp subseconds values from the correspondent registers */
+ return (uint32_t)(RTC->TSSS);
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group11 Output Type Config configuration functions
+ * @brief Output Type Config configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Output Type Config configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the RTC Output Pin mode.
+ * @param RTC_OutputType specifies the RTC Output (PC13) pin mode.
+ * This parameter can be one of the following values:
+ * @arg RTC_OUTPUT_OPENDRAIN RTC Output (PC13) is configured in
+ * Open Drain mode.
+ * @arg RTC_OUTPUT_PUSHPULL RTC Output (PC13) is configured in
+ * Push Pull mode.
+ */
+void RTC_ConfigOutputType(uint32_t RTC_OutputType)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType));
+
+ RTC->OPT &= (uint32_t) ~(RTC_OPT_TYPE);
+ RTC->OPT |= (uint32_t)(RTC_OutputType);
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group12 Shift control synchronisation functions
+ * @brief Shift control synchronisation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Shift control synchronisation functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the Synchronization Shift Control Settings.
+ * @note When REFCKON is set, firmware must not write to Shift control register
+ * @param RTC_ShiftAdd1S Select to add or not 1 second to the time Calendar.
+ * This parameter can be one of the following values :
+ * @arg RTC_SHIFT_ADD1S_ENABLE Add one second to the clock calendar.
+ * @arg RTC_SHIFT_ADD1S_DISABLE No effect.
+ * @param RTC_ShiftSubFS Select the number of Second Fractions to Substitute.
+ * This parameter can be one any value from 0 to 0x7FFF.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Shift registers are configured
+ * - ERROR: RTC Shift registers are not configured
+ */
+ErrorStatus RTC_ConfigSynchroShift(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS)
+{
+ ErrorStatus status = ERROR;
+ uint32_t shpfcount = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S));
+ assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Check if a Shift is pending*/
+ if ((RTC->INITSTS & RTC_INITSTS_SHOPF) != RESET)
+ {
+ /* Wait until the shift is completed*/
+ while (((RTC->INITSTS & RTC_INITSTS_SHOPF) != RESET) && (shpfcount != SHPF_TIMEOUT))
+ {
+ shpfcount++;
+ }
+ }
+
+ /* Check if the Shift pending is completed or if there is no Shift operation at all*/
+ if ((RTC->INITSTS & RTC_INITSTS_SHOPF) == RESET)
+ {
+ /* check if the reference clock detection is disabled */
+ if ((RTC->CTRL & RTC_CTRL_REFCLKEN) == RESET)
+ {
+ /* Configure the Shift settings */
+ RTC->SCTRL = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S);
+
+ if (RTC_WaitForSynchro() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ else
+ {
+ status = ERROR;
+ }
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+
+ return (ErrorStatus)(status);
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group13 Interrupts and flags management functions
+ * @brief Interrupts and flags management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupts and flags management functions #####
+ ===============================================================================
+ [..] All RTC interrupts are connected to the EXTI controller.
+ (+) To enable the RTC Alarm interrupt, the following sequence is required:
+ (+) Configure and enable the EXTI Line 17 in interrupt mode and select
+ the rising edge sensitivity using the EXTI_InitPeripheral() function.
+ (+) Configure and enable the RTC_Alarm IRQ channel in the NVIC using
+ the NVIC_Init() function.
+ (+) Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B)
+ using the RTC_SetAlarm() and RTC_EnableAlarm() functions.
+
+ (+) To enable the RTC Wakeup interrupt, the following sequence is required:
+ (+) Configure and enable the EXTI Line 20 in interrupt mode and select
+ the rising edge sensitivity using the EXTI_InitPeripheral() function.
+ (+) Configure and enable the RTC_WKUP IRQ channel in the NVIC using the
+ NVIC_Init() function.
+ (+) Configure the RTC to generate the RTC wakeup timer event using the
+ RTC_ConfigWakeUpClock(), RTC_SetWakeUpCounter() and RTC_EnableWakeUp()
+ functions.
+
+ (+) To enable the RTC Tamper interrupt, the following sequence is required:
+ (+) Configure and enable the EXTI Line 19 in interrupt mode and select
+ the rising edge sensitivity using the EXTI_InitPeripheral() function.
+ (+) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using
+ the NVIC_Init() function.
+ (+) Configure the RTC to detect the RTC tamper event using the
+ RTC_TamperTriggerConfig() and RTC_TamperCmd() functions.
+
+ (+) To enable the RTC TimeStamp interrupt, the following sequence is
+ required:
+ (+) Configure and enable the EXTI Line 19 in interrupt mode and select
+ the rising edge sensitivity using the EXTI_InitPeripheral() function.
+ (+) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using
+ the NVIC_Init() function.
+ (+) Configure the RTC to detect the RTC time-stamp event using the
+ RTC_EnableTimeStamp() functions.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the specified RTC interrupts.
+ * @param RTC_INT specifies the RTC interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_INT_TS Time Stamp interrupt mask.
+ * @arg RTC_INT_WUT WakeUp Timer interrupt mask.
+ * @arg RTC_INT_ALRB Alarm B interrupt mask.
+ * @arg RTC_INT_ALRA Alarm A interrupt mask.
+ * @param Cmd new state of the specified RTC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RTC_ConfigInt(uint32_t RTC_INT, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_CONFIG_INT(RTC_INT));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ if (Cmd != DISABLE)
+ {
+ /* Configure the Interrupts in the RTC_CTRL register */
+ RTC->CTRL |= (uint32_t)(RTC_INT & ~RTC_TMPCFG_TPINTEN);
+ }
+ else
+ {
+ /* Configure the Interrupts in the RTC_CTRL register */
+ RTC->CTRL &= (uint32_t) ~(RTC_INT & (uint32_t)~RTC_TMPCFG_TPINTEN);
+ }
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Checks whether the specified RTC flag is set or not.
+ * @param RTC_FLAG specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg RTC_FLAG_RECPF RECALPF event flag.
+ * @arg RTC_FLAG_TAMP3F: Tamper 3 event flag.
+ * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag.
+ * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag.
+ * @arg RTC_FLAG_TISOVF Time Stamp OverFlow flag.
+ * @arg RTC_FLAG_TISF Time Stamp event flag.
+ * @arg RTC_FLAG_WTF WakeUp Timer flag.
+ * @arg RTC_FLAG_ALBF Alarm B flag.
+ * @arg RTC_FLAG_ALAF Alarm A flag.
+ * @arg RTC_FLAG_INITF Initialization mode flag.
+ * @arg RTC_FLAG_RSYF Registers Synchronized flag.
+ * @arg RTC_FLAG_INITSF Registers Configured flag.
+ * @arg RTC_FLAG_SHOPF Shift operation pending flag.
+ * @arg RTC_FLAG_WTWF WakeUp Timer Write flag.
+ * @arg RTC_FLAG_ALBWF Alarm B Write flag.
+ * @arg RTC_FLAG_ALAWF Alarm A write flag.
+ * @return The new state of RTC_FLAG (SET or RESET).
+ */
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
+
+ /* Get all the flags */
+ tmpregister = (uint32_t)(RTC->INITSTS & RTC_FLAGS_MASK);
+
+ /* Return the status of the flag */
+ if ((tmpregister & RTC_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RTC's pending flags.
+ * @param RTC_FLAG specifies the RTC flag to clear.
+ * This parameter can be any combination of the following values:.
+ * @arg RTC_FLAG_TAMP3F: Tamper 3 event flag.
+ * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag.
+ * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag.
+ * @arg RTC_FLAG_TISOVF Time Stamp Overflow flag.
+ * @arg RTC_FLAG_TISF Time Stamp event flag.
+ * @arg RTC_FLAG_WTF WakeUp Timer flag.
+ * @arg RTC_FLAG_ALBF Alarm B flag.
+ * @arg RTC_FLAG_ALAF Alarm A flag.
+ * @arg RTC_FLAG_RSYF Registers Synchronized flag.
+ */
+void RTC_ClrFlag(uint32_t RTC_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
+
+ /* Clear the Flags in the RTC_INITSTS register */
+ RTC->INITSTS = (uint32_t)(
+ (uint32_t)(~((RTC_FLAG | RTC_INITSTS_INITM) & 0x0001FFFF) | (uint32_t)(RTC->INITSTS & RTC_INITSTS_INITM)));
+}
+
+/**
+ * @brief Checks whether the specified RTC interrupt has occurred or not.
+ * @param RTC_INT specifies the RTC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg RTC_INT_TS Time Stamp interrupt.
+ * @arg RTC_INT_WUT WakeUp Timer interrupt.
+ * @arg RTC_INT_ALRB Alarm B interrupt.
+ * @arg RTC_INT_ALRA Alarm A interrupt.
+ * @return The new state of RTC_INT (SET or RESET).
+ */
+INTStatus RTC_GetITStatus(uint32_t RTC_INT)
+{
+ INTStatus bitstatus = RESET;
+ uint32_t tmpregister = 0, enablestatus = 0;
+ uint8_t tamperEnable = 0;
+ /* Check the parameters */
+ assert_param(IS_RTC_GET_INT(RTC_INT));
+
+ /* Get the Interrupt enable Status */
+ if ((RTC_INT == RTC_INT_TAMP1) || (RTC_INT == RTC_INT_TAMP2)|| (RTC_INT == RTC_INT_TAMP3))
+ {
+ tamperEnable = ((RTC->TMPCFG & 0x00ff0000)>>16);
+ if (tamperEnable > 0)
+ {
+ enablestatus = SET;
+ }
+
+ }
+ else
+ {
+ enablestatus = (uint32_t)((RTC->CTRL & RTC_INT));
+
+ }
+ /* Get the Interrupt pending bit */
+ tmpregister = (uint32_t)((RTC->INITSTS & (uint32_t)(RTC_INT >> 4)));
+
+ /* Get the status of the Interrupt */
+ if ((enablestatus != (uint32_t)RESET) && ((tmpregister & 0x0000FFFF) != (uint32_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RTC's interrupt pending bits.
+ * @param RTC_INT specifies the RTC interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_INT_TS Time Stamp interrupt
+ * @arg RTC_INT_WUT WakeUp Timer interrupt
+ * @arg RTC_INT_ALRB Alarm B interrupt
+ * @arg RTC_INT_ALRA Alarm A interrupt
+ */
+void RTC_ClrIntPendingBit(uint32_t RTC_INT)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_CLEAR_INT(RTC_INT));
+
+ /* Get the RTC_INITSTS Interrupt pending bits mask */
+ tmpregister = (uint32_t)(RTC_INT >> 4);
+
+ /* Clear the interrupt pending bits in the RTC_INITSTS register */
+ RTC->INITSTS = (uint32_t)(
+ (uint32_t)(~((tmpregister | RTC_INITSTS_INITM) & 0x0000FFFF) | (uint32_t)(RTC->INITSTS & RTC_INITSTS_INITM)));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief Converts a 2 digit decimal to BCD format.
+ * @param Value Byte to be converted.
+ * @return Converted byte
+ */
+static uint8_t RTC_ByteToBcd2(uint8_t Value)
+{
+ uint8_t bcdhigh = 0;
+
+ while (Value >= 10)
+ {
+ bcdhigh++;
+ Value -= 10;
+ }
+
+ return ((uint8_t)(bcdhigh << 4) | Value);
+}
+
+/**
+ * @brief Convert from 2 digit BCD to Binary.
+ * @param Value BCD value to be converted.
+ * @return Converted word
+ */
+static uint8_t RTC_Bcd2ToByte(uint8_t Value)
+{
+ uint8_t tmp = 0;
+ tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
+ return (tmp + (Value & (uint8_t)0x0F));
+}
+/**
+ * @brief Enable wakeup tsc functionand wakeup by the set time
+ * @param count wakeup time.
+ */
+void RTC_EnableWakeUpTsc(uint32_t count)
+{
+ // Wait until bit RTC_TSCWKUPCTRL_WKUPOFF is 1
+ while (!(RTC->TSCWKUPCTRL & RTC_TSCWKUPCTRL_WKUPOFF))
+ {
+ }
+ // enter config wakeup cnt mode
+ RTC->TSCWKUPCTRL = RTC_TSCWKUPCTRL_WKUPCNF;
+ // config tsc wakeup cnt ,tsc wakeup module counting cycle = WAKUPCNT * LSE/LSI
+ RTC->TSCWKUPCNT = count;
+ // exit config wakeup cnt mode
+ RTC->TSCWKUPCTRL &= ~(RTC_TSCWKUPCTRL_WKUPCNF);
+ while (!(RTC->TSCWKUPCTRL & RTC_TSCWKUPCTRL_WKUPOFF))
+ {
+ }
+ // TSC wakeup enable
+ RTC->TSCWKUPCTRL = RTC_TSCWKUPCTRL_WKUPEN;
+}
+
+/** @defgroup RTC_Group9 Tampers configuration functions
+ * @brief Tampers configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Tampers configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the select Tamper pin edge.
+ * @param RTC_Tamper: Selected tamper pin.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_Tamper_1: Select Tamper 1.
+ * @arg RTC_Tamper_2: Select Tamper 2.
+ * @arg RTC_Tamper_3: Select Tamper 3.
+ * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that
+ * stimulates tamper event.
+ * This parameter can be one of the following values:
+ * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event.
+ * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event.
+ * @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event.
+ * @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event.
+ * @retval None
+ */
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER(RTC_Tamper));
+ assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger));
+ if (RTC_Tamper == RTC_TAMPER_3)
+ {
+ RTC_TamperTrigger <<= 5;
+ }
+ else if (RTC_Tamper == RTC_TAMPER_2)
+ {
+ RTC_TamperTrigger <<= 3;
+ }
+ /* Configure the RTC_TAMPCR register */
+ RTC->TMPCFG |= (uint32_t)(RTC_Tamper | RTC_TamperTrigger);
+
+}
+
+/**
+ * @brief Enables or Disables the Tamper detection.
+ * @param RTC_Tamper: Selected tamper pin.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_TAMPER_1: Select Tamper 1.
+ * @arg RTC_TAMPER_2: Select Tamper 2.
+ * @arg RTC_TAMPER_3: Select Tamper 3.
+ * @param NewState: new state of the tamper pin.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER(RTC_Tamper));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected Tamper pin */
+ RTC->TMPCFG |= (uint32_t)RTC_Tamper;
+ }
+ else
+ {
+ /* Disable the selected Tamper pin */
+ RTC->TMPCFG &= (uint32_t)~RTC_Tamper;
+ }
+}
+
+/**
+ * @brief Configures the Tampers Filter.
+ * @param RTC_TamperFilter: Specifies the tampers filter.
+ * This parameter can be one of the following values:
+ * @arg RTC_TamperFilter_Disable: Tamper filter is disabled.
+ * @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive
+ * samples at the active level.
+ * @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive
+ * samples at the active level.
+ * @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive
+ * samples at the active level.
+ * @retval None
+ */
+void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter));
+
+ /* Clear TAMPFLT[1:0] bits in the RTC_TAMPCR register */
+ RTC->TMPCFG &= (uint32_t)~(RTC_TMPCFG_TPFLT);
+
+ /* Configure the RTC_TAMPCR register */
+ RTC->TMPCFG |= (uint32_t)RTC_TamperFilter;
+}
+
+/**
+ * @brief Configures the Tampers Sampling Frequency.
+ * @param RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency.
+ * This parameter can be one of the following values:
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 32768
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 16384
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 8192
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 4096
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 2048
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 1024
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 512
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 256
+ * @retval None
+ */
+void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq));
+
+ /* Clear TAMPFREQ[2:0] bits in the RTC_TAMPCR register */
+ RTC->TMPCFG &= (uint32_t)~(RTC_TAMPCR_TAMPFREQ);
+
+ /* Configure the RTC_TAMPCR register */
+ RTC->TMPCFG |= (uint32_t)RTC_TamperSamplingFreq;
+}
+
+/**
+ * @brief Configures the Tampers Pins input Precharge Duration.
+ * @param RTC_TamperPrechargeDuration: Specifies the Tampers Pins input
+ * Precharge Duration.
+ * This parameter can be one of the following values:
+ * @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle.
+ * @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle.
+ * @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle.
+ * @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle.
+ * @retval None
+ */
+void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration));
+
+ /* Clear TAMPPRCH[1:0] bits in the RTC_TAMPCR register */
+ RTC->TMPCFG &= (uint32_t)~(RTC_TMPCFG_TPPRCH);
+
+ /* Configure the RTC_TAMPCR register */
+ RTC->TMPCFG |= (uint32_t)RTC_TamperPrechargeDuration;
+}
+
+/**
+ * @brief Enables or Disables the TimeStamp on Tamper Detection Event.
+ * @note The timestamp is valid even the TSEN bit in tamper control register
+ * is reset.
+ * @param NewState: new state of the timestamp on tamper event.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Save timestamp on tamper detection event */
+ RTC->TMPCFG |= (uint32_t)RTC_TMPCFG_TPTS;
+ }
+ else
+ {
+ /* Tamper detection does not cause a timestamp to be saved */
+ RTC->TMPCFG &= (uint32_t)~RTC_TMPCFG_TPTS;
+ }
+}
+
+/**
+ * @brief Enables or Disables the Precharge of Tamper pin.
+ * @param NewState: new state of tamper pull up.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RTC_TamperPullUpCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable precharge of the selected Tamper pin */
+ RTC->TMPCFG &= (uint32_t)~RTC_TMPCFG_TPPUDIS;
+ }
+ else
+ {
+ /* Disable precharge of the selected Tamper pin */
+ RTC->TMPCFG |= (uint32_t)RTC_TMPCFG_TPPUDIS;
+ }
+}
+
+/**
+ * @brief Enables or Disables the TAMPTS.
+ * @param NewState: new state of TAMPTS.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RTC_TamperTAMPTSCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable precharge of the selected Tamper pin */
+ RTC->TMPCFG |= (uint32_t)RTC_TMPCFG_TPTS;
+ }
+ else
+ {
+ /* Disable precharge of the selected Tamper pin */
+ RTC->TMPCFG &= (uint32_t)~RTC_TMPCFG_TPTS;
+ }
+}
+
+/**
+ * @brief Enables or Disables the Tamper detection.
+ * @param RTC_Tamper: Selected tamper pin.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_TAMPER1_INT: Select Tamper 1.
+ * @arg RTC_TAMPER2_INT: Select Tamper 2.
+ * @arg RTC_TAMPER3_INT: Select Tamper 3.
+ * @param NewState: new state of the tamper pin.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RTC_TamperIECmd(uint32_t TAMPxIE, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER(TAMPxIE));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected Tamper pin */
+ RTC->TMPCFG |= (uint32_t)TAMPxIE;
+ }
+ else
+ {
+ /* Disable the selected Tamper pin */
+ RTC->TMPCFG &= (uint32_t)~TAMPxIE;
+ }
+}
+
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_spi.c b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_spi.c
new file mode 100644
index 0000000000..3cb8f9fd20
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_spi.c
@@ -0,0 +1,853 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_spi.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_spi.h"
+#include "n32g43x_rcc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @brief SPI driver modules
+ * @{
+ */
+
+/** @addtogroup SPI_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_Defines
+ * @{
+ */
+
+/* SPI SPIEN mask */
+#define CTRL1_SPIEN_ENABLE ((uint16_t)0x0040)
+#define CTRL1_SPIEN_DISABLE ((uint16_t)0xFFBF)
+
+/* I2S I2SEN mask */
+#define I2SCFG_I2SEN_ENABLE ((uint16_t)0x0400)
+#define I2SCFG_I2SEN_DISABLE ((uint16_t)0xFBFF)
+
+/* SPI CRCNEXT mask */
+#define CTRL1_CRCNEXT_ENABLE ((uint16_t)0x1000)
+
+/* SPI CRCEN mask */
+#define CTRL1_CRCEN_ENABLE ((uint16_t)0x2000)
+#define CTRL1_CRCEN_DISABLE ((uint16_t)0xDFFF)
+
+/* SPI SSOE mask */
+#define CTRL2_SSOEN_ENABLE ((uint16_t)0x0004)
+#define CTRL2_SSOEN_DISABLE ((uint16_t)0xFFFB)
+
+/* SPI registers Masks */
+#define CTRL1_CLR_MASK ((uint16_t)0x3040)
+#define I2SCFG_CLR_MASK ((uint16_t)0xF040)
+
+/* SPI or I2S mode selection masks */
+#define SPI_MODE_ENABLE ((uint16_t)0xF7FF)
+#define I2S_MODE_ENABLE ((uint16_t)0x0800)
+
+/* I2S clock source selection masks */
+#define I2S1_CLKSRC ((uint32_t)(0x00020000))
+#define I2S2_CLKSRC ((uint32_t)(0x00040000))
+#define I2S_MUL_MASK ((uint32_t)(0x0000F000))
+#define I2S_DIV_MASK ((uint32_t)(0x000000F0))
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the SPIx peripheral registers to their default
+ * reset values (Affects also the I2Ss).
+ * @param SPIx where x can be 1, 2 to select the SPI peripheral.
+ */
+void SPI_I2S_DeInit(SPI_Module* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+
+ if (SPIx == SPI1)
+ {
+ /* Enable SPI1 reset state */
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI1, ENABLE);
+ /* Release SPI1 from reset state */
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI1, DISABLE);
+ }
+ else if (SPIx == SPI2)
+ {
+ /* Enable SPI2 reset state */
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI2, ENABLE);
+ /* Release SPI2 from reset state */
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI2, DISABLE);
+ }
+
+}
+
+/**
+ * @brief Initializes the SPIx peripheral according to the specified
+ * parameters in the SPI_InitStruct.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param SPI_InitStruct pointer to a SPI_InitType structure that
+ * contains the configuration information for the specified SPI peripheral.
+ */
+void SPI_Init(SPI_Module* SPIx, SPI_InitType* SPI_InitStruct)
+{
+ uint16_t tmpregister = 0;
+
+ /* check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+
+ /* Check the SPI parameters */
+ assert_param(IS_SPI_DIR_MODE(SPI_InitStruct->DataDirection));
+ assert_param(IS_SPI_MODE(SPI_InitStruct->SpiMode));
+ assert_param(IS_SPI_DATASIZE(SPI_InitStruct->DataLen));
+ assert_param(IS_SPI_CLKPOL(SPI_InitStruct->CLKPOL));
+ assert_param(IS_SPI_CLKPHA(SPI_InitStruct->CLKPHA));
+ assert_param(IS_SPI_NSS(SPI_InitStruct->NSS));
+ assert_param(IS_SPI_BR_PRESCALER(SPI_InitStruct->BaudRatePres));
+ assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->FirstBit));
+ assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
+
+ /*---------------------------- SPIx CTRL1 Configuration ------------------------*/
+ /* Get the SPIx CTRL1 value */
+ tmpregister = SPIx->CTRL1;
+ /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
+ tmpregister &= CTRL1_CLR_MASK;
+ /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
+ master/salve mode, CPOL and CPHA */
+ /* Set BIDImode, BIDIOE and RxONLY bits according to DataDirection value */
+ /* Set SSM, SSI and MSTR bits according to SpiMode and NSS values */
+ /* Set LSBFirst bit according to FirstBit value */
+ /* Set BR bits according to BaudRatePres value */
+ /* Set CPOL bit according to CLKPOL value */
+ /* Set CPHA bit according to CLKPHA value */
+ tmpregister |= (uint16_t)((uint32_t)SPI_InitStruct->DataDirection | SPI_InitStruct->SpiMode
+ | SPI_InitStruct->DataLen | SPI_InitStruct->CLKPOL | SPI_InitStruct->CLKPHA
+ | SPI_InitStruct->NSS | SPI_InitStruct->BaudRatePres | SPI_InitStruct->FirstBit);
+ /* Write to SPIx CTRL1 */
+ SPIx->CTRL1 = tmpregister;
+
+ /* Activate the SPI mode (Reset I2SMOD bit in I2SCFG register) */
+ SPIx->I2SCFG &= SPI_MODE_ENABLE;
+
+ /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
+ /* Write to SPIx CRCPOLY */
+ SPIx->CRCPOLY = SPI_InitStruct->CRCPoly;
+}
+
+/**
+ * @brief Initializes the SPIx peripheral according to the specified
+ * parameters in the I2S_InitStruct.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral
+ * (configured in I2S mode).
+ * @param I2S_InitStruct pointer to an I2S_InitType structure that
+ * contains the configuration information for the specified SPI peripheral
+ * configured in I2S mode.
+ * @note
+ * The function calculates the optimal prescaler needed to obtain the most
+ * accurate audio frequency (depending on the I2S clock source, the PLL values
+ * and the product configuration). But in case the prescaler value is greater
+ * than 511, the default value (0x02) will be configured instead. *
+ */
+void I2S_Init(SPI_Module* SPIx, I2S_InitType* I2S_InitStruct)
+{
+ uint16_t tmpregister = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
+ uint32_t tmp = 0;
+ RCC_ClocksType RCC_Clocks;
+ uint32_t sourceclock = 0;
+
+ /* Check the I2S parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_I2S_MODE(I2S_InitStruct->I2sMode));
+ assert_param(IS_I2S_STANDARD(I2S_InitStruct->Standard));
+ assert_param(IS_I2S_DATA_FMT(I2S_InitStruct->DataFormat));
+ assert_param(IS_I2S_MCLK_ENABLE(I2S_InitStruct->MCLKEnable));
+ assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFrequency));
+ assert_param(IS_I2S_CLKPOL(I2S_InitStruct->CLKPOL));
+
+ /*----------------------- SPIx I2SCFG & I2SPREDIV Configuration -----------------*/
+ /* Clear I2SMOD, I2SE, MODCFG, PCMSYNC, STDSEL, CKPOL, TDATLEN and CHLEN bits */
+ SPIx->I2SCFG &= I2SCFG_CLR_MASK;
+ SPIx->I2SPREDIV = 0x0002;
+
+ /* Get the I2SCFG register value */
+ tmpregister = SPIx->I2SCFG;
+
+ /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
+ if (I2S_InitStruct->AudioFrequency == I2S_AUDIO_FREQ_DEFAULT)
+ {
+ i2sodd = (uint16_t)0;
+ i2sdiv = (uint16_t)2;
+ }
+ /* If the requested audio frequency is not the default, compute the prescaler */
+ else
+ {
+ /* Check the frame length (For the Prescaler computing) */
+ if (I2S_InitStruct->DataFormat == I2S_DATA_FMT_16BITS)
+ {
+ /* Packet length is 16 bits */
+ packetlength = 1;
+ }
+ else
+ {
+ /* Packet length is 32 bits */
+ packetlength = 2;
+ }
+
+ /* Get the I2S clock source mask depending on the peripheral number */
+ if (((uint32_t)SPIx) == SPI2_BASE)
+ {
+ /* The mask is relative to I2S1 */
+ tmp = I2S1_CLKSRC;
+ }
+ else
+ {
+ /* The mask is relative to I2S2 */
+ tmp = I2S2_CLKSRC;
+ }
+
+ /* I2S Clock source is System clock: Get System Clock frequency */
+ RCC_GetClocksFreqValue(&RCC_Clocks);
+
+ /* Get the source clock value: based on System Clock value */
+ sourceclock = RCC_Clocks.SysclkFreq;
+
+ /* Compute the Real divider depending on the MCLK output state with a floating point */
+ if (I2S_InitStruct->MCLKEnable == I2S_MCLK_ENABLE)
+ {
+ /* MCLK output is enabled */
+ tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->AudioFrequency)) + 5);
+ }
+ else
+ {
+ /* MCLK output is disabled */
+ tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) * 10) / I2S_InitStruct->AudioFrequency)) + 5);
+ }
+
+ /* Remove the floating point */
+ tmp = tmp / 10;
+
+ /* Check the parity of the divider */
+ i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
+
+ /* Compute the i2sdiv prescaler */
+ i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
+
+ /* Get the Mask for the Odd bit (SPI_I2SPREDIV[8]) register */
+ i2sodd = (uint16_t)(i2sodd << 8);
+ }
+
+ /* Test if the divider is 1 or 0 or greater than 0xFF */
+ if ((i2sdiv < 2) || (i2sdiv > 0xFF))
+ {
+ /* Set the default values */
+ i2sdiv = 2;
+ i2sodd = 0;
+ }
+
+ /* Write to SPIx I2SPREDIV register the computed value */
+ SPIx->I2SPREDIV = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->MCLKEnable));
+
+ /* Configure the I2S with the SPI_InitStruct values */
+ tmpregister |= (uint16_t)(
+ I2S_MODE_ENABLE
+ | (uint16_t)(I2S_InitStruct->I2sMode
+ | (uint16_t)(I2S_InitStruct->Standard
+ | (uint16_t)(I2S_InitStruct->DataFormat | (uint16_t)I2S_InitStruct->CLKPOL))));
+
+ /* Write to SPIx I2SCFG */
+ SPIx->I2SCFG = tmpregister;
+}
+
+/**
+ * @brief Fills each SPI_InitStruct member with its default value.
+ * @param SPI_InitStruct pointer to a SPI_InitType structure which will be initialized.
+ */
+void SPI_InitStruct(SPI_InitType* SPI_InitStruct)
+{
+ /*--------------- Reset SPI init structure parameters values -----------------*/
+ /* Initialize the DataDirection member */
+ SPI_InitStruct->DataDirection = SPI_DIR_DOUBLELINE_FULLDUPLEX;
+ /* initialize the SpiMode member */
+ SPI_InitStruct->SpiMode = SPI_MODE_SLAVE;
+ /* initialize the DataLen member */
+ SPI_InitStruct->DataLen = SPI_DATA_SIZE_8BITS;
+ /* Initialize the CLKPOL member */
+ SPI_InitStruct->CLKPOL = SPI_CLKPOL_LOW;
+ /* Initialize the CLKPHA member */
+ SPI_InitStruct->CLKPHA = SPI_CLKPHA_FIRST_EDGE;
+ /* Initialize the NSS member */
+ SPI_InitStruct->NSS = SPI_NSS_HARD;
+ /* Initialize the BaudRatePres member */
+ SPI_InitStruct->BaudRatePres = SPI_BR_PRESCALER_2;
+ /* Initialize the FirstBit member */
+ SPI_InitStruct->FirstBit = SPI_FB_MSB;
+ /* Initialize the CRCPoly member */
+ SPI_InitStruct->CRCPoly = 7;
+}
+
+/**
+ * @brief Fills each I2S_InitStruct member with its default value.
+ * @param I2S_InitStruct pointer to a I2S_InitType structure which will be initialized.
+ */
+void I2S_InitStruct(I2S_InitType* I2S_InitStruct)
+{
+ /*--------------- Reset I2S init structure parameters values -----------------*/
+ /* Initialize the I2sMode member */
+ I2S_InitStruct->I2sMode = I2S_MODE_SlAVE_TX;
+
+ /* Initialize the Standard member */
+ I2S_InitStruct->Standard = I2S_STD_PHILLIPS;
+
+ /* Initialize the DataFormat member */
+ I2S_InitStruct->DataFormat = I2S_DATA_FMT_16BITS;
+
+ /* Initialize the MCLKEnable member */
+ I2S_InitStruct->MCLKEnable = I2S_MCLK_DISABLE;
+
+ /* Initialize the AudioFrequency member */
+ I2S_InitStruct->AudioFrequency = I2S_AUDIO_FREQ_DEFAULT;
+
+ /* Initialize the CLKPOL member */
+ I2S_InitStruct->CLKPOL = I2S_CLKPOL_LOW;
+}
+
+/**
+ * @brief Enables or disables the specified SPI peripheral.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param Cmd new state of the SPIx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void SPI_Enable(SPI_Module* SPIx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected SPI peripheral */
+ SPIx->CTRL1 |= CTRL1_SPIEN_ENABLE;
+ }
+ else
+ {
+ /* Disable the selected SPI peripheral */
+ SPIx->CTRL1 &= CTRL1_SPIEN_DISABLE;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified SPI peripheral (in I2S mode).
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param Cmd new state of the SPIx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2S_Enable(SPI_Module* SPIx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected SPI peripheral (in I2S mode) */
+ SPIx->I2SCFG |= I2SCFG_I2SEN_ENABLE;
+ }
+ else
+ {
+ /* Disable the selected SPI peripheral (in I2S mode) */
+ SPIx->I2SCFG &= I2SCFG_I2SEN_DISABLE;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified SPI/I2S interrupts.
+ * @param SPIx where x can be
+ * - 1 or 2 in SPI mode
+ * - 1 or 2 in I2S mode
+ * @param SPI_I2S_IT specifies the SPI/I2S interrupt source to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg SPI_I2S_INT_TE Tx buffer empty interrupt mask
+ * @arg SPI_I2S_INT_RNE Rx buffer not empty interrupt mask
+ * @arg SPI_I2S_INT_ERR Error interrupt mask
+ * @param Cmd new state of the specified SPI/I2S interrupt.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void SPI_I2S_EnableInt(SPI_Module* SPIx, uint8_t SPI_I2S_IT, FunctionalState Cmd)
+{
+ uint16_t itpos = 0, itmask = 0;
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ assert_param(IS_SPI_I2S_CONFIG_INT(SPI_I2S_IT));
+
+ /* Get the SPI/I2S IT index */
+ itpos = SPI_I2S_IT >> 4;
+
+ /* Set the IT mask */
+ itmask = (uint16_t)1 << (uint16_t)itpos;
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected SPI/I2S interrupt */
+ SPIx->CTRL2 |= itmask;
+ }
+ else
+ {
+ /* Disable the selected SPI/I2S interrupt */
+ SPIx->CTRL2 &= (uint16_t)~itmask;
+ }
+}
+
+/**
+ * @brief Enables or disables the SPIx/I2Sx DMA interface.
+ * @param SPIx where x can be
+ * - 1 or 2 in SPI mode
+ * - 1 or 2 in I2S mode
+ * @param SPI_I2S_DMAReq specifies the SPI/I2S DMA transfer request to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg SPI_I2S_DMA_TX Tx buffer DMA transfer request
+ * @arg SPI_I2S_DMA_RX Rx buffer DMA transfer request
+ * @param Cmd new state of the selected SPI/I2S DMA transfer request.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void SPI_I2S_EnableDma(SPI_Module* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ assert_param(IS_SPI_I2S_DMA(SPI_I2S_DMAReq));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected SPI/I2S DMA requests */
+ SPIx->CTRL2 |= SPI_I2S_DMAReq;
+ }
+ else
+ {
+ /* Disable the selected SPI/I2S DMA requests */
+ SPIx->CTRL2 &= (uint16_t)~SPI_I2S_DMAReq;
+ }
+}
+
+/**
+ * @brief Transmits a Data through the SPIx/I2Sx peripheral.
+ * @param SPIx where x can be
+ * - 1 or 2 in SPI mode
+ * - 1 or 2 in I2S mode
+ * @param Data Data to be transmitted.
+ */
+void SPI_I2S_TransmitData(SPI_Module* SPIx, uint16_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+
+ /* Write in the DAT register the data to be sent */
+ SPIx->DAT = Data;
+}
+
+/**
+ * @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
+ * @param SPIx where x can be
+ * - 1 or 2 in SPI mode
+ * - 1 or 2 in I2S mode
+ * @return The value of the received data.
+ */
+uint16_t SPI_I2S_ReceiveData(SPI_Module* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+
+ /* Return the data in the DAT register */
+ return SPIx->DAT;
+}
+
+/**
+ * @brief Configures internally by software the NSS pin for the selected SPI.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param SPI_NSSInternalSoft specifies the SPI NSS internal state.
+ * This parameter can be one of the following values:
+ * @arg SPI_NSS_HIGH Set NSS pin internally
+ * @arg SPI_NSS_LOW Reset NSS pin internally
+ */
+void SPI_SetNssLevel(SPI_Module* SPIx, uint16_t SPI_NSSInternalSoft)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_NSS_LEVEL(SPI_NSSInternalSoft));
+ if (SPI_NSSInternalSoft != SPI_NSS_LOW)
+ {
+ /* Set NSS pin internally by software */
+ SPIx->CTRL1 |= SPI_NSS_HIGH;
+ }
+ else
+ {
+ /* Reset NSS pin internally by software */
+ SPIx->CTRL1 &= SPI_NSS_LOW;
+ }
+}
+
+/**
+ * @brief Enables or disables the SS output for the selected SPI.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param Cmd new state of the SPIx SS output.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void SPI_SSOutputEnable(SPI_Module* SPIx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected SPI SS output */
+ SPIx->CTRL2 |= CTRL2_SSOEN_ENABLE;
+ }
+ else
+ {
+ /* Disable the selected SPI SS output */
+ SPIx->CTRL2 &= CTRL2_SSOEN_DISABLE;
+ }
+}
+
+/**
+ * @brief Configures the data size for the selected SPI.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param DataLen specifies the SPI data size.
+ * This parameter can be one of the following values:
+ * @arg SPI_DATA_SIZE_16BITS Set data frame format to 16bit
+ * @arg SPI_DATA_SIZE_8BITS Set data frame format to 8bit
+ */
+void SPI_ConfigDataLen(SPI_Module* SPIx, uint16_t DataLen)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_DATASIZE(DataLen));
+ /* Clear DFF bit */
+ SPIx->CTRL1 &= (uint16_t)~SPI_DATA_SIZE_16BITS;
+ /* Set new DFF bit value */
+ SPIx->CTRL1 |= DataLen;
+}
+
+/**
+ * @brief Transmit the SPIx CRC value.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ */
+void SPI_TransmitCrcNext(SPI_Module* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+
+ /* Enable the selected SPI CRC transmission */
+ SPIx->CTRL1 |= CTRL1_CRCNEXT_ENABLE;
+}
+
+/**
+ * @brief Enables or disables the CRC value calculation of the transferred bytes.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param Cmd new state of the SPIx CRC value calculation.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void SPI_EnableCalculateCrc(SPI_Module* SPIx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected SPI CRC calculation */
+ SPIx->CTRL1 |= CTRL1_CRCEN_ENABLE;
+ }
+ else
+ {
+ /* Disable the selected SPI CRC calculation */
+ SPIx->CTRL1 &= CTRL1_CRCEN_DISABLE;
+ }
+}
+
+/**
+ * @brief Returns the transmit or the receive CRC register value for the specified SPI.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param SPI_CRC specifies the CRC register to be read.
+ * This parameter can be one of the following values:
+ * @arg SPI_CRC_TX Selects Tx CRC register
+ * @arg SPI_CRC_RX Selects Rx CRC register
+ * @return The selected CRC register value..
+ */
+uint16_t SPI_GetCRCDat(SPI_Module* SPIx, uint8_t SPI_CRC)
+{
+ uint16_t crcreg = 0;
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_CRC(SPI_CRC));
+ if (SPI_CRC != SPI_CRC_RX)
+ {
+ /* Get the Tx CRC register */
+ crcreg = SPIx->CRCTDAT;
+ }
+ else
+ {
+ /* Get the Rx CRC register */
+ crcreg = SPIx->CRCRDAT;
+ }
+ /* Return the selected CRC register */
+ return crcreg;
+}
+
+/**
+ * @brief Returns the CRC Polynomial register value for the specified SPI.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @return The CRC Polynomial register value.
+ */
+uint16_t SPI_GetCRCPoly(SPI_Module* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+
+ /* Return the CRC polynomial register */
+ return SPIx->CRCPOLY;
+}
+
+/**
+ * @brief Selects the data transfer direction in bi-directional mode for the specified SPI.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param DataDirection specifies the data transfer direction in bi-directional mode.
+ * This parameter can be one of the following values:
+ * @arg SPI_BIDIRECTION_TX Selects Tx transmission direction
+ * @arg SPI_BIDIRECTION_RX Selects Rx receive direction
+ */
+void SPI_ConfigBidirectionalMode(SPI_Module* SPIx, uint16_t DataDirection)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_BIDIRECTION(DataDirection));
+ if (DataDirection == SPI_BIDIRECTION_TX)
+ {
+ /* Set the Tx only mode */
+ SPIx->CTRL1 |= SPI_BIDIRECTION_TX;
+ }
+ else
+ {
+ /* Set the Rx only mode */
+ SPIx->CTRL1 &= SPI_BIDIRECTION_RX;
+ }
+}
+
+/**
+ * @brief Checks whether the specified SPI/I2S flag is set or not.
+ * @param SPIx where x can be
+ * - 1 or 2 in SPI mode
+ * - 1 or 2 in I2S mode
+ * @param SPI_I2S_FLAG specifies the SPI/I2S flag to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_I2S_TE_FLAG Transmit buffer empty flag.
+ * @arg SPI_I2S_RNE_FLAG Receive buffer not empty flag.
+ * @arg SPI_I2S_BUSY_FLAG Busy flag.
+ * @arg SPI_I2S_OVER_FLAG Overrun flag.
+ * @arg SPI_MODERR_FLAG Mode Fault flag.
+ * @arg SPI_CRCERR_FLAG CRC Error flag.
+ * @arg I2S_UNDER_FLAG Underrun Error flag.
+ * @arg I2S_CHSIDE_FLAG Channel Side flag.
+ * @return The new state of SPI_I2S_FLAG (SET or RESET).
+ */
+FlagStatus SPI_I2S_GetStatus(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
+ /* Check the status of the specified SPI/I2S flag */
+ if ((SPIx->STS & SPI_I2S_FLAG) != (uint16_t)RESET)
+ {
+ /* SPI_I2S_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* SPI_I2S_FLAG is reset */
+ bitstatus = RESET;
+ }
+ /* Return the SPI_I2S_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the SPIx CRC Error (CRCERR) flag.
+ * @param SPIx where x can be
+ * - 1 or 2 in SPI mode
+ * @param SPI_I2S_FLAG specifies the SPI flag to clear.
+ * This function clears only CRCERR flag.
+ * @note
+ * - OVR (OverRun error) flag is cleared by software sequence: a read
+ * operation to SPI_DAT register (SPI_I2S_ReceiveData()) followed by a read
+ * operation to SPI_STS register (SPI_I2S_GetStatus()).
+ * - UDR (UnderRun error) flag is cleared by a read operation to
+ * SPI_STS register (SPI_I2S_GetStatus()).
+ * - MODF (Mode Fault) flag is cleared by software sequence: a read/write
+ * operation to SPI_STS register (SPI_I2S_GetStatus()) followed by a
+ * write operation to SPI_CTRL1 register (SPI_Enable() to enable the SPI).
+ */
+void SPI_I2S_ClrCRCErrFlag(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_CLR_FLAG(SPI_I2S_FLAG));
+
+ /* Clear the selected SPI CRC Error (CRCERR) flag */
+ SPIx->STS = (uint16_t)~SPI_I2S_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified SPI/I2S interrupt has occurred or not.
+ * @param SPIx where x can be
+ * - 1 or 2 in SPI mode
+ * - 1 or 2 in I2S mode
+ * @param SPI_I2S_IT specifies the SPI/I2S interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_I2S_INT_TE Transmit buffer empty interrupt.
+ * @arg SPI_I2S_INT_RNE Receive buffer not empty interrupt.
+ * @arg SPI_I2S_INT_OVER Overrun interrupt.
+ * @arg SPI_INT_MODERR Mode Fault interrupt.
+ * @arg SPI_INT_CRCERR CRC Error interrupt.
+ * @arg I2S_INT_UNDER Underrun Error interrupt.
+ * @return The new state of SPI_I2S_IT (SET or RESET).
+ */
+INTStatus SPI_I2S_GetIntStatus(SPI_Module* SPIx, uint8_t SPI_I2S_IT)
+{
+ INTStatus bitstatus = RESET;
+ uint16_t itpos = 0, itmask = 0, enablestatus = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_GET_INT(SPI_I2S_IT));
+
+ /* Get the SPI/I2S IT index */
+ itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+
+ /* Get the SPI/I2S IT mask */
+ itmask = SPI_I2S_IT >> 4;
+
+ /* Set the IT mask */
+ itmask = 0x01 << itmask;
+
+ /* Get the SPI_I2S_IT enable bit status */
+ enablestatus = (SPIx->CTRL2 & itmask);
+
+ /* Check the status of the specified SPI/I2S interrupt */
+ if (((SPIx->STS & itpos) != (uint16_t)RESET) && enablestatus)
+ {
+ /* SPI_I2S_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* SPI_I2S_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the SPI_I2S_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
+ * @param SPIx where x can be
+ * - 1 or 2 in SPI mode
+ * @param SPI_I2S_IT specifies the SPI interrupt pending bit to clear.
+ * This function clears only CRCERR interrupt pending bit.
+ * @note
+ * - OVR (OverRun Error) interrupt pending bit is cleared by software
+ * sequence: a read operation to SPI_DAT register (SPI_I2S_ReceiveData())
+ * followed by a read operation to SPI_STS register (SPI_I2S_GetIntStatus()).
+ * - UDR (UnderRun Error) interrupt pending bit is cleared by a read
+ * operation to SPI_STS register (SPI_I2S_GetIntStatus()).
+ * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
+ * a read/write operation to SPI_STS register (SPI_I2S_GetIntStatus())
+ * followed by a write operation to SPI_CTRL1 register (SPI_Enable() to enable
+ * the SPI).
+ */
+void SPI_I2S_ClrITPendingBit(SPI_Module* SPIx, uint8_t SPI_I2S_IT)
+{
+ uint16_t itpos = 0;
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_CLR_INT(SPI_I2S_IT));
+
+ /* Get the SPI IT index */
+ itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+
+ /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
+ SPIx->STS = (uint16_t)~itpos;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_tim.c b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_tim.c
new file mode 100644
index 0000000000..17bd1b2380
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_tim.c
@@ -0,0 +1,3290 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_tim.c
+ * @author Nations
+ * @version V1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_tim.h"
+#include "n32g43x_rcc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup TIM
+ * @brief TIM driver modules
+ * @{
+ */
+
+/** @addtogroup TIM_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Defines
+ * @{
+ */
+
+/* ---------------------- TIM registers bit mask ------------------------ */
+#define SMCTRL_ETR_MASK ((uint16_t)0x00FF)
+#define CAPCMPMOD_OFFSET ((uint16_t)0x0018)
+#define CAPCMPEN_CCE_SET ((uint16_t)0x0001)
+#define CAPCMPEN_CCNE_SET ((uint16_t)0x0004)
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_FunctionPrototypes
+ * @{
+ */
+
+static void ConfigTI1(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter);
+static void ConfigTI2(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter);
+static void ConfigTI3(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter);
+static void ConfigTI4(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the TIMx peripheral registers to their default reset values.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ */
+void TIM_DeInit(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+
+ if (TIMx == TIM1)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM1, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM1, DISABLE);
+ }
+ else if (TIMx == TIM2)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM2, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM2, DISABLE);
+ }
+ else if (TIMx == TIM3)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM3, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM3, DISABLE);
+ }
+ else if (TIMx == TIM4)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM4, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM4, DISABLE);
+ }
+ else if (TIMx == TIM5)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM5, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM5, DISABLE);
+ }
+ else if (TIMx == TIM6)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM6, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM6, DISABLE);
+ }
+ else if (TIMx == TIM7)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM7, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM7, DISABLE);
+ }
+ else if (TIMx == TIM8)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM8, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM8, DISABLE);
+ }
+ else if (TIMx == TIM9)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM9, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM9, DISABLE);
+ }
+}
+
+/**
+ * @brief Initializes the TIMx Time Base Unit peripheral according to
+ * the specified parameters in the TIM_TimeBaseInitStruct.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_TimeBaseInitStruct pointer to a TIM_TimeBaseInitType
+ * structure that contains the configuration information for the
+ * specified TIM peripheral.
+ */
+void TIM_InitTimeBase(TIM_Module* TIMx, TIM_TimeBaseInitType* TIM_TimeBaseInitStruct)
+{
+ uint32_t tmpcr1 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimCntMode(TIM_TimeBaseInitStruct->CntMode));
+ assert_param(IsTimClkDiv(TIM_TimeBaseInitStruct->ClkDiv));
+
+ tmpcr1 = TIMx->CTRL1;
+
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9))
+ {
+ /* Select the Counter Mode */
+ tmpcr1 &= (uint32_t)(~((uint32_t)(TIM_CTRL1_DIR | TIM_CTRL1_CAMSEL)));
+ tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->CntMode;
+ }
+
+ if ((TIMx != TIM6) && (TIMx != TIM7))
+ {
+ /* Set the clock division */
+ tmpcr1 &= (uint32_t)(~((uint32_t)TIM_CTRL1_CLKD));
+ tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->ClkDiv;
+ }
+
+ TIMx->CTRL1 = tmpcr1;
+
+ /* Set the Autoreload value */
+ TIMx->AR = TIM_TimeBaseInitStruct->Period;
+
+ /* Set the Prescaler value */
+ TIMx->PSC = TIM_TimeBaseInitStruct->Prescaler;
+
+ if ((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ /* Set the Repetition Counter value */
+ TIMx->REPCNT = TIM_TimeBaseInitStruct->RepetCnt;
+ }
+
+ /* Generate an update event to reload the Prescaler and the Repetition counter
+ values immediately */
+ TIMx->EVTGEN = TIM_PSC_RELOAD_MODE_IMMEDIATE;
+
+ /*channel input from comp or iom*/
+ tmpcr1 = TIMx->CTRL1;
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9))
+ {
+ if (TIM_TimeBaseInitStruct->CapCh1FromCompEn)
+ tmpcr1 |= (0x01L << 11);
+ else
+ tmpcr1 &= ~(0x01L << 11);
+ }
+ if (TIMx==TIM9)
+ {
+ if (TIM_TimeBaseInitStruct->CapCh2FromCompEn)
+ tmpcr1 |= (0x01L << 12);
+ else
+ tmpcr1 &= ~(0x01L << 12);
+ if (TIM_TimeBaseInitStruct->CapCh3FromCompEn)
+ tmpcr1 |= (0x01L << 13);
+ else
+ tmpcr1 &= ~(0x01L << 13);
+ if (TIM_TimeBaseInitStruct->CapCh4FromCompEn)
+ tmpcr1 |= (0x01L << 14);
+ else
+ tmpcr1 &= ~(0x01L << 14);
+ }
+ /*etr input from comp or iom*/
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM9))
+ {
+ if (TIM_TimeBaseInitStruct->CapEtrClrFromCompEn)
+ tmpcr1 |= (0x01L << 15);
+ else
+ tmpcr1 &= ~(0x01L << 15);
+ }
+ TIMx->CTRL1 = tmpcr1;
+ /*sel etr from iom or tsc*/
+ tmpcr1 = TIMx->CTRL2;
+ if ((TIMx == TIM2) || (TIMx == TIM4))
+ {
+ if (TIM_TimeBaseInitStruct->CapEtrSelFromTscEn)
+ tmpcr1 |= (0x01L << 8);
+ else
+ tmpcr1 &= ~(0x01L << 8);
+ }
+ TIMx->CTRL2 = tmpcr1;
+}
+
+/**
+ * @brief Initializes the TIMx Channel1 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_InitOc1(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0;
+ uint32_t tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode));
+ assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState));
+ assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity));
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCEN &= (uint32_t)(~(uint32_t)TIM_CCEN_CC1EN);
+ /* Get the TIMx CCEN register value */
+ tmpccer = TIMx->CCEN;
+ /* Get the TIMx CTRL2 register value */
+ tmpcr2 = TIMx->CTRL2;
+
+ /* Get the TIMx CCMOD1 register value */
+ tmpccmrx = TIMx->CCMOD1;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_OC1M));
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_CC1SEL));
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= TIM_OCInitStruct->OcMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC1P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= TIM_OCInitStruct->OcPolarity;
+
+ /* Set the Output State */
+ tmpccer |= TIM_OCInitStruct->OutputState;
+
+ if ((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IsTimOutputNState(TIM_OCInitStruct->OutputNState));
+ assert_param(IsTimOcnPolarity(TIM_OCInitStruct->OcNPolarity));
+ assert_param(IsTimOcnIdleState(TIM_OCInitStruct->OcNIdleState));
+ assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC1NP));
+ /* Set the Output N Polarity */
+ tmpccer |= TIM_OCInitStruct->OcNPolarity;
+
+ /* Reset the Output N State */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC1NEN));
+ /* Set the Output N State */
+ tmpccer |= TIM_OCInitStruct->OutputNState;
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI1));
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI1N));
+
+ /* Set the Output Idle state */
+ tmpcr2 |= TIM_OCInitStruct->OcIdleState;
+ /* Set the Output N Idle state */
+ tmpcr2 |= TIM_OCInitStruct->OcNIdleState;
+ }
+ /* Write to TIMx CTRL2 */
+ TIMx->CTRL2 = tmpcr2;
+
+ /* Write to TIMx CCMOD1 */
+ TIMx->CCMOD1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCDAT1 = TIM_OCInitStruct->Pulse;
+
+ /* Write to TIMx CCEN */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel2 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select
+ * the TIM peripheral.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_InitOc2(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0;
+ uint32_t tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode));
+ assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState));
+ assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity));
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC2EN));
+
+ /* Get the TIMx CCEN register value */
+ tmpccer = TIMx->CCEN;
+ /* Get the TIMx CTRL2 register value */
+ tmpcr2 = TIMx->CTRL2;
+
+ /* Get the TIMx CCMOD1 register value */
+ tmpccmrx = TIMx->CCMOD1;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_OC2M));
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_CC2SEL));
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC2P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 4);
+
+ /* Set the Output State */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 4);
+
+ if ((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IsTimOutputNState(TIM_OCInitStruct->OutputNState));
+ assert_param(IsTimOcnPolarity(TIM_OCInitStruct->OcNPolarity));
+ assert_param(IsTimOcnIdleState(TIM_OCInitStruct->OcNIdleState));
+ assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC2NP));
+ /* Set the Output N Polarity */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OcNPolarity << 4);
+
+ /* Reset the Output N State */
+ tmpccer &= (uint32_t)(~((uint16_t)TIM_CCEN_CC2NEN));
+ /* Set the Output N State */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputNState << 4);
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI2));
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI2N));
+
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 2);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcNIdleState << 2);
+ }
+ /* Write to TIMx CTRL2 */
+ TIMx->CTRL2 = tmpcr2;
+
+ /* Write to TIMx CCMOD1 */
+ TIMx->CCMOD1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCDAT2 = TIM_OCInitStruct->Pulse;
+
+ /* Write to TIMx CCEN */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel3 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_InitOc3(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0;
+ uint32_t tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode));
+ assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState));
+ assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity));
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC3EN));
+
+ /* Get the TIMx CCEN register value */
+ tmpccer = TIMx->CCEN;
+ /* Get the TIMx CTRL2 register value */
+ tmpcr2 = TIMx->CTRL2;
+
+ /* Get the TIMx CCMOD2 register value */
+ tmpccmrx = TIMx->CCMOD2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_OC3MD));
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_CC3SEL));
+ /* Select the Output Compare Mode */
+ tmpccmrx |= TIM_OCInitStruct->OcMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)(~((uint16_t)TIM_CCEN_CC3P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 8);
+
+ /* Set the Output State */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 8);
+
+ if ((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IsTimOutputNState(TIM_OCInitStruct->OutputNState));
+ assert_param(IsTimOcnPolarity(TIM_OCInitStruct->OcNPolarity));
+ assert_param(IsTimOcnIdleState(TIM_OCInitStruct->OcNIdleState));
+ assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC3NP));
+ /* Set the Output N Polarity */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OcNPolarity << 8);
+ /* Reset the Output N State */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC3NEN));
+
+ /* Set the Output N State */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputNState << 8);
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI3));
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI3N));
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 4);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcNIdleState << 4);
+ }
+ /* Write to TIMx CTRL2 */
+ TIMx->CTRL2 = tmpcr2;
+
+ /* Write to TIMx CCMOD2 */
+ TIMx->CCMOD2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCDAT3 = TIM_OCInitStruct->Pulse;
+
+ /* Write to TIMx CCEN */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel4 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_InitOc4(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0;
+ uint32_t tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode));
+ assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState));
+ assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity));
+ /* Disable the Channel 2: Reset the CC4E Bit */
+ TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC4EN));
+
+ /* Get the TIMx CCEN register value */
+ tmpccer = TIMx->CCEN;
+ /* Get the TIMx CTRL2 register value */
+ tmpcr2 = TIMx->CTRL2;
+
+ /* Get the TIMx CCMOD2 register value */
+ tmpccmrx = TIMx->CCMOD2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_OC4MD));
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_CC4SEL));
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC4P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 12);
+
+ /* Set the Output State */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 12);
+
+ if ((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState));
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI4));
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 6);
+ }
+ /* Write to TIMx CTRL2 */
+ TIMx->CTRL2 = tmpcr2;
+
+ /* Write to TIMx CCMOD2 */
+ TIMx->CCMOD2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCDAT4 = TIM_OCInitStruct->Pulse;
+
+ /* Write to TIMx CCEN */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel5 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_InitOc5(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0;
+ uint32_t tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode));
+ assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState));
+ assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity));
+ /* Disable the Channel 5: Reset the CC5E Bit */
+ TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC5EN));
+
+ /* Get the TIMx CCEN register value */
+ tmpccer = TIMx->CCEN;
+ /* Get the TIMx CTRL2 register value */
+ tmpcr2 = TIMx->CTRL2;
+
+ /* Get the TIMx CCMOD3 register value */
+ tmpccmrx = TIMx->CCMOD3;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD3_OC5MD));
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC5P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 16);
+
+ /* Set the Output State */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 16);
+
+ if ((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState));
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI5));
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 8);
+ }
+ /* Write to TIMx CTRL2 */
+ TIMx->CTRL2 = tmpcr2;
+
+ /* Write to TIMx CCMOD3 */
+ TIMx->CCMOD3 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCDAT5 = TIM_OCInitStruct->Pulse;
+
+ /* Write to TIMx CCEN */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel6 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_InitOc6(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0;
+ uint32_t tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode));
+ assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState));
+ assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity));
+ /* Disable the Channel 6: Reset the CC6E Bit */
+ TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC6EN));
+
+ /* Get the TIMx CCEN register value */
+ tmpccer = TIMx->CCEN;
+ /* Get the TIMx CTRL2 register value */
+ tmpcr2 = TIMx->CTRL2;
+
+ /* Get the TIMx CCMOD3 register value */
+ tmpccmrx = TIMx->CCMOD3;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD3_OC6MD));
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC6P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 20);
+
+ /* Set the Output State */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 20);
+
+ if ((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState));
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI6));
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 10);
+ }
+ /* Write to TIMx CTRL2 */
+ TIMx->CTRL2 = tmpcr2;
+
+ /* Write to TIMx CCMOD3 */
+ TIMx->CCMOD3 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCDAT6 = TIM_OCInitStruct->Pulse;
+
+ /* Write to TIMx CCEN */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIM peripheral according to the specified
+ * parameters in the TIM_ICInitStruct.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_ICInitStruct pointer to a TIM_ICInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_ICInit(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IsTimCh(TIM_ICInitStruct->Channel));
+ assert_param(IsTimIcSelection(TIM_ICInitStruct->IcSelection));
+ assert_param(IsTimIcPrescaler(TIM_ICInitStruct->IcPrescaler));
+ assert_param(IsTimInCapFilter(TIM_ICInitStruct->IcFilter));
+
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9))
+ {
+ assert_param(IsTimIcPalaritySingleEdge(TIM_ICInitStruct->IcPolarity));
+ }
+ else
+ {
+ assert_param(IsTimIcPolarityAnyEdge(TIM_ICInitStruct->IcPolarity));
+ }
+ if (TIM_ICInitStruct->Channel == TIM_CH_1)
+ {
+ assert_param(IsTimList8Module(TIMx));
+ /* TI1 Configuration */
+ ConfigTI1(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap1Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ }
+ else if (TIM_ICInitStruct->Channel == TIM_CH_2)
+ {
+ assert_param(IsTimList6Module(TIMx));
+ /* TI2 Configuration */
+ ConfigTI2(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap2Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ }
+ else if (TIM_ICInitStruct->Channel == TIM_CH_3)
+ {
+ assert_param(IsTimList3Module(TIMx));
+ /* TI3 Configuration */
+ ConfigTI3(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap3Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ }
+ else
+ {
+ assert_param(IsTimList3Module(TIMx));
+ /* TI4 Configuration */
+ ConfigTI4(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap4Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ }
+}
+
+/**
+ * @brief Configures the TIM peripheral according to the specified
+ * parameters in the TIM_ICInitStruct to measure an external PWM signal.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param TIM_ICInitStruct pointer to a TIM_ICInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_ConfigPwmIc(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct)
+{
+ uint16_t icoppositepolarity = TIM_IC_POLARITY_RISING;
+ uint16_t icoppositeselection = TIM_IC_SELECTION_DIRECTTI;
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ /* Select the Opposite Input Polarity */
+ if (TIM_ICInitStruct->IcPolarity == TIM_IC_POLARITY_RISING)
+ {
+ icoppositepolarity = TIM_IC_POLARITY_FALLING;
+ }
+ else
+ {
+ icoppositepolarity = TIM_IC_POLARITY_RISING;
+ }
+ /* Select the Opposite Input */
+ if (TIM_ICInitStruct->IcSelection == TIM_IC_SELECTION_DIRECTTI)
+ {
+ icoppositeselection = TIM_IC_SELECTION_INDIRECTTI;
+ }
+ else
+ {
+ icoppositeselection = TIM_IC_SELECTION_DIRECTTI;
+ }
+ if (TIM_ICInitStruct->Channel == TIM_CH_1)
+ {
+ /* TI1 Configuration */
+ ConfigTI1(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap1Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ /* TI2 Configuration */
+ ConfigTI2(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap2Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ }
+ else
+ {
+ /* TI2 Configuration */
+ ConfigTI2(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap2Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ /* TI1 Configuration */
+ ConfigTI1(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap1Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ }
+}
+
+/**
+ * @brief Configures the: Break feature, dead time, Lock level, the OSSI,
+ * the OSSR State and the AOE(automatic output enable).
+ * @param TIMx where x can be 1 or 8 to select the TIM
+ * @param TIM_BDTRInitStruct pointer to a TIM_BDTRInitType structure that
+ * contains the BKDT Register configuration information for the TIM peripheral.
+ */
+void TIM_ConfigBkdt(TIM_Module* TIMx, TIM_BDTRInitType* TIM_BDTRInitStruct)
+{
+ uint32_t tmp;
+ /* Check the parameters */
+ assert_param(IsTimList2Module(TIMx));
+ assert_param(IsTimOssrState(TIM_BDTRInitStruct->OssrState));
+ assert_param(IsTimOssiState(TIM_BDTRInitStruct->OssiState));
+ assert_param(IsTimLockLevel(TIM_BDTRInitStruct->LockLevel));
+ assert_param(IsTimBreakInState(TIM_BDTRInitStruct->Break));
+ assert_param(IsTimBreakPalarity(TIM_BDTRInitStruct->BreakPolarity));
+ assert_param(IsTimAutoOutputState(TIM_BDTRInitStruct->AutomaticOutput));
+ /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */
+ TIMx->BKDT = (uint32_t)TIM_BDTRInitStruct->OssrState | TIM_BDTRInitStruct->OssiState | TIM_BDTRInitStruct->LockLevel
+ | TIM_BDTRInitStruct->DeadTime | TIM_BDTRInitStruct->Break | TIM_BDTRInitStruct->BreakPolarity
+ | TIM_BDTRInitStruct->AutomaticOutput;
+
+ /*cofigure other break in*/
+ tmp = TIMx->CTRL1;
+ /*IOMBKPEN 0 meaning iom as break enable*/
+ if (TIM_BDTRInitStruct->IomBreakEn)
+ tmp &= ~(0x01L << 10);
+ else
+ tmp |= (0x01L << 10);
+ if (TIM_BDTRInitStruct->LockUpBreakEn)
+ tmp |= (0x01L << 16);
+ else
+ tmp &= ~(0x01L << 16);
+ if (TIM_BDTRInitStruct->PvdBreakEn)
+ tmp |= (0x01L << 17);
+ else
+ tmp &= ~(0x01L << 17);
+ TIMx->CTRL1 = tmp;
+}
+
+/**
+ * @brief Fills each TIM_TimeBaseInitStruct member with its default value.
+ * @param TIM_TimeBaseInitStruct pointer to a TIM_TimeBaseInitType
+ * structure which will be initialized.
+ */
+void TIM_InitTimBaseStruct(TIM_TimeBaseInitType* TIM_TimeBaseInitStruct)
+{
+ /* Set the default configuration */
+ TIM_TimeBaseInitStruct->Period = 0xFFFF;
+ TIM_TimeBaseInitStruct->Prescaler = 0x0000;
+ TIM_TimeBaseInitStruct->ClkDiv = TIM_CLK_DIV1;
+ TIM_TimeBaseInitStruct->CntMode = TIM_CNT_MODE_UP;
+ TIM_TimeBaseInitStruct->RepetCnt = 0x0000;
+
+ TIM_TimeBaseInitStruct->CapCh1FromCompEn = false;
+ TIM_TimeBaseInitStruct->CapCh2FromCompEn = false;
+ TIM_TimeBaseInitStruct->CapCh3FromCompEn = false;
+ TIM_TimeBaseInitStruct->CapCh4FromCompEn = false;
+ TIM_TimeBaseInitStruct->CapEtrClrFromCompEn = false;
+ TIM_TimeBaseInitStruct->CapEtrSelFromTscEn = false;
+}
+
+/**
+ * @brief Fills each TIM_OCInitStruct member with its default value.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure which will
+ * be initialized.
+ */
+void TIM_InitOcStruct(OCInitType* TIM_OCInitStruct)
+{
+ /* Set the default configuration */
+ TIM_OCInitStruct->OcMode = TIM_OCMODE_TIMING;
+ TIM_OCInitStruct->OutputState = TIM_OUTPUT_STATE_DISABLE;
+ TIM_OCInitStruct->OutputNState = TIM_OUTPUT_NSTATE_DISABLE;
+ TIM_OCInitStruct->Pulse = 0x0000;
+ TIM_OCInitStruct->OcPolarity = TIM_OC_POLARITY_HIGH;
+ TIM_OCInitStruct->OcNPolarity = TIM_OC_POLARITY_HIGH;
+ TIM_OCInitStruct->OcIdleState = TIM_OC_IDLE_STATE_RESET;
+ TIM_OCInitStruct->OcNIdleState = TIM_OCN_IDLE_STATE_RESET;
+}
+
+/**
+ * @brief Fills each TIM_ICInitStruct member with its default value.
+ * @param TIM_ICInitStruct pointer to a TIM_ICInitType structure which will
+ * be initialized.
+ */
+void TIM_InitIcStruct(TIM_ICInitType* TIM_ICInitStruct)
+{
+ /* Set the default configuration */
+ TIM_ICInitStruct->Channel = TIM_CH_1;
+ TIM_ICInitStruct->IcPolarity = TIM_IC_POLARITY_RISING;
+ TIM_ICInitStruct->IcSelection = TIM_IC_SELECTION_DIRECTTI;
+ TIM_ICInitStruct->IcPrescaler = TIM_IC_PSC_DIV1;
+ TIM_ICInitStruct->IcFilter = 0x00;
+}
+
+/**
+ * @brief Fills each TIM_BDTRInitStruct member with its default value.
+ * @param TIM_BDTRInitStruct pointer to a TIM_BDTRInitType structure which
+ * will be initialized.
+ */
+void TIM_InitBkdtStruct(TIM_BDTRInitType* TIM_BDTRInitStruct)
+{
+ /* Set the default configuration */
+ TIM_BDTRInitStruct->OssrState = TIM_OSSR_STATE_DISABLE;
+ TIM_BDTRInitStruct->OssiState = TIM_OSSI_STATE_DISABLE;
+ TIM_BDTRInitStruct->LockLevel = TIM_LOCK_LEVEL_OFF;
+ TIM_BDTRInitStruct->DeadTime = 0x00;
+ TIM_BDTRInitStruct->Break = TIM_BREAK_IN_DISABLE;
+ TIM_BDTRInitStruct->BreakPolarity = TIM_BREAK_POLARITY_LOW;
+ TIM_BDTRInitStruct->AutomaticOutput = TIM_AUTO_OUTPUT_DISABLE;
+}
+
+/**
+ * @brief Enables or disables the specified TIM peripheral.
+ * @param TIMx where x can be 1 to 8 to select the TIMx peripheral.
+ * @param Cmd new state of the TIMx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_Enable(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the TIM Counter */
+ TIMx->CTRL1 |= TIM_CTRL1_CNTEN;
+ }
+ else
+ {
+ /* Disable the TIM Counter */
+ TIMx->CTRL1 &= (uint32_t)(~((uint32_t)TIM_CTRL1_CNTEN));
+ }
+}
+
+/**
+ * @brief Enables or disables the TIM peripheral Main Outputs.
+ * @param TIMx where x can be 1, 8 to select the TIMx peripheral.
+ * @param Cmd new state of the TIM peripheral Main Outputs.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_EnableCtrlPwmOutputs(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimList2Module(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the TIM Main Output */
+ TIMx->BKDT |= TIM_BKDT_MOEN;
+ }
+ else
+ {
+ /* Disable the TIM Main Output */
+ TIMx->BKDT &= (uint16_t)(~((uint16_t)TIM_BKDT_MOEN));
+ }
+}
+
+/**
+ * @brief Enables or disables the specified TIM interrupts.
+ * @param TIMx where x can be 1 to 8 to select the TIMx peripheral.
+ * @param TIM_IT specifies the TIM interrupts sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_INT_UPDATE TIM update Interrupt source
+ * @arg TIM_INT_CC1 TIM Capture Compare 1 Interrupt source
+ * @arg TIM_INT_CC2 TIM Capture Compare 2 Interrupt source
+ * @arg TIM_INT_CC3 TIM Capture Compare 3 Interrupt source
+ * @arg TIM_INT_CC4 TIM Capture Compare 4 Interrupt source
+ * @arg TIM_INT_COM TIM Commutation Interrupt source
+ * @arg TIM_INT_TRIG TIM Trigger Interrupt source
+ * @arg TIM_INT_BREAK TIM Break Interrupt source
+ * @note
+ * - TIM6 and TIM7 can only generate an update interrupt.
+ * - TIM_INT_BREAK is used only with TIM1, TIM8.
+ * - TIM_INT_COM is used only with TIM1, TIM8.
+ * @param Cmd new state of the TIM interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_ConfigInt(TIM_Module* TIMx, uint16_t TIM_IT, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimInt(TIM_IT));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the Interrupt sources */
+ TIMx->DINTEN |= TIM_IT;
+ }
+ else
+ {
+ /* Disable the Interrupt sources */
+ TIMx->DINTEN &= (uint16_t)~TIM_IT;
+ }
+}
+
+/**
+ * @brief Configures the TIMx event to be generate by software.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_EventSource specifies the event source.
+ * This parameter can be one or more of the following values:
+ * @arg TIM_EVT_SRC_UPDATE Timer update Event source
+ * @arg TIM_EVT_SRC_CC1 Timer Capture Compare 1 Event source
+ * @arg TIM_EVT_SRC_CC2 Timer Capture Compare 2 Event source
+ * @arg TIM_EVT_SRC_CC3 Timer Capture Compare 3 Event source
+ * @arg TIM_EVT_SRC_CC4 Timer Capture Compare 4 Event source
+ * @arg TIM_EVT_SRC_COM Timer COM event source
+ * @arg TIM_EVT_SRC_TRIG Timer Trigger Event source
+ * @arg TIM_EVT_SRC_BREAK Timer Break event source
+ * @note
+ * - TIM6 and TIM7 can only generate an update event.
+ * - TIM_EVT_SRC_COM and TIM_EVT_SRC_BREAK are used only with TIM1 and TIM8.
+ */
+void TIM_GenerateEvent(TIM_Module* TIMx, uint16_t TIM_EventSource)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimEvtSrc(TIM_EventSource));
+
+ /* Set the event sources */
+ TIMx->EVTGEN = TIM_EventSource;
+}
+
+/**
+ * @brief Configures the TIMx's DMA interface.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select
+ * the TIM peripheral.
+ * @param TIM_DMABase DMA Base address.
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABase_CR, TIM_DMABASE_CTRL2, TIM_DMABASE_SMCTRL,
+ * TIM_DMABASE_DMAINTEN, TIM1_DMABase_SR, TIM_DMABASE_EVTGEN,
+ * TIM_DMABASE_CAPCMPMOD1, TIM_DMABASE_CAPCMPMOD2, TIM_DMABASE_CAPCMPEN,
+ * TIM_DMABASE_CNT, TIM_DMABASE_PSC, TIM_DMABASE_AR,
+ * TIM_DMABASE_REPCNT, TIM_DMABASE_CAPCMPDAT1, TIM_DMABASE_CAPCMPDAT2,
+ * TIM_DMABASE_CAPCMPDAT3, TIM_DMABASE_CAPCMPDAT4, TIM_DMABASE_BKDT,
+ * TIM_DMABASE_DMACTRL.
+ * @param TIM_DMABurstLength DMA Burst length.
+ * This parameter can be one value between:
+ * TIM_DMABURST_LENGTH_1TRANSFER and TIM_DMABURST_LENGTH_18TRANSFERS.
+ */
+void TIM_ConfigDma(TIM_Module* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
+{
+ /* Check the parameters */
+ assert_param(IsTimList4Module(TIMx));
+ assert_param(IsTimDmaBase(TIM_DMABase));
+ assert_param(IsTimDmaLength(TIM_DMABurstLength));
+ /* Set the DMA Base and the DMA Burst Length */
+ TIMx->DCTRL = TIM_DMABase | TIM_DMABurstLength;
+}
+
+/**
+ * @brief Enables or disables the TIMx's DMA Requests.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 6, 7, 8
+ * to select the TIM peripheral.
+ * @param TIM_DMASource specifies the DMA Request sources.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_DMA_UPDATE TIM update Interrupt source
+ * @arg TIM_DMA_CC1 TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2 TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3 TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4 TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM TIM Commutation DMA source
+ * @arg TIM_DMA_TRIG TIM Trigger DMA source
+ * @param Cmd new state of the DMA Request sources.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_EnableDma(TIM_Module* TIMx, uint16_t TIM_DMASource, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimList9Module(TIMx));
+ assert_param(IsTimDmaSrc(TIM_DMASource));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the DMA sources */
+ TIMx->DINTEN |= TIM_DMASource;
+ }
+ else
+ {
+ /* Disable the DMA sources */
+ TIMx->DINTEN &= (uint16_t)~TIM_DMASource;
+ }
+}
+
+/**
+ * @brief Configures the TIMx internal Clock
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8
+ * to select the TIM peripheral.
+ */
+void TIM_ConfigInternalClk(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ /* Disable slave mode to clock the prescaler directly with the internal clock */
+ TIMx->SMCTRL &= (uint16_t)(~((uint16_t)TIM_SMCTRL_SMSEL));
+}
+
+/**
+ * @brief Configures the TIMx Internal Trigger as External Clock
+ * @param TIMx where x can be 1, 2, 3, 4, 5 to select the TIM peripheral.
+ * @param TIM_InputTriggerSource Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TRIG_SEL_IN_TR0 Internal Trigger 0
+ * @arg TIM_TRIG_SEL_IN_TR1 Internal Trigger 1
+ * @arg TIM_TRIG_SEL_IN_TR2 Internal Trigger 2
+ * @arg TIM_TRIG_SEL_IN_TR3 Internal Trigger 3
+ */
+void TIM_ConfigInternalTrigToExt(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimInterTrigSel(TIM_InputTriggerSource));
+ /* Select the Internal Trigger */
+ TIM_SelectInputTrig(TIMx, TIM_InputTriggerSource);
+ /* Select the External clock mode1 */
+ TIMx->SMCTRL |= TIM_SLAVE_MODE_EXT1;
+}
+
+/**
+ * @brief Configures the TIMx Trigger as External Clock
+ * @param TIMx where x can be 1, 2, 3, 4, 5 to select the TIM peripheral.
+ * @param TIM_TIxExternalCLKSource Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_EXT_CLK_SRC_TI1ED TI1 Edge Detector
+ * @arg TIM_EXT_CLK_SRC_TI1 Filtered Timer Input 1
+ * @arg TIM_EXT_CLK_SRC_TI2 Filtered Timer Input 2
+ * @param IcPolarity specifies the TIx Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_POLARITY_RISING
+ * @arg TIM_IC_POLARITY_FALLING
+ * @param ICFilter specifies the filter value.
+ * This parameter must be a value between 0x0 and 0xF.
+ */
+void TIM_ConfigExtTrigAsClk(TIM_Module* TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t IcPolarity, uint16_t ICFilter)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimExtClkSrc(TIM_TIxExternalCLKSource));
+ assert_param(IsTimIcPalaritySingleEdge(IcPolarity));
+ assert_param(IsTimInCapFilter(ICFilter));
+ /* Configure the Timer Input Clock Source */
+ if (TIM_TIxExternalCLKSource == TIM_EXT_CLK_SRC_TI2)
+ {
+ ConfigTI2(TIMx, IcPolarity, TIM_IC_SELECTION_DIRECTTI, ICFilter);
+ }
+ else
+ {
+ ConfigTI1(TIMx, IcPolarity, TIM_IC_SELECTION_DIRECTTI, ICFilter);
+ }
+ /* Select the Trigger source */
+ TIM_SelectInputTrig(TIMx, TIM_TIxExternalCLKSource);
+ /* Select the External clock mode1 */
+ TIMx->SMCTRL |= TIM_SLAVE_MODE_EXT1;
+}
+
+/**
+ * @brief Configures the External clock Mode1
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_EXT_TRG_PSC_OFF ETRP Prescaler OFF.
+ * @arg TIM_EXT_TRG_PSC_DIV2 ETRP frequency divided by 2.
+ * @arg TIM_EXT_TRG_PSC_DIV4 ETRP frequency divided by 4.
+ * @arg TIM_EXT_TRG_PSC_DIV8 ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_EXT_TRIG_POLARITY_INVERTED active low or falling edge active.
+ * @arg TIM_EXT_TRIG_POLARITY_NONINVERTED active high or rising edge active.
+ * @param ExtTRGFilter External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ */
+void TIM_ConfigExtClkMode1(TIM_Module* TIMx,
+ uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter)
+{
+ uint16_t tmpsmcr = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimExtPreDiv(TIM_ExtTRGPrescaler));
+ assert_param(IsTimExtTrigPolarity(TIM_ExtTRGPolarity));
+ assert_param(IsTimExtTrigFilter(ExtTRGFilter));
+ /* Configure the ETR Clock source */
+ TIM_ConfigExtTrig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+
+ /* Get the TIMx SMCTRL register value */
+ tmpsmcr = TIMx->SMCTRL;
+ /* Reset the SMS Bits */
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_SMSEL));
+ /* Select the External clock mode1 */
+ tmpsmcr |= TIM_SLAVE_MODE_EXT1;
+ /* Select the Trigger selection : ETRF */
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_TSEL));
+ tmpsmcr |= TIM_TRIG_SEL_ETRF;
+ /* Write to TIMx SMCTRL */
+ TIMx->SMCTRL = tmpsmcr;
+}
+
+/**
+ * @brief Configures the External clock Mode2
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_EXT_TRG_PSC_OFF ETRP Prescaler OFF.
+ * @arg TIM_EXT_TRG_PSC_DIV2 ETRP frequency divided by 2.
+ * @arg TIM_EXT_TRG_PSC_DIV4 ETRP frequency divided by 4.
+ * @arg TIM_EXT_TRG_PSC_DIV8 ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_EXT_TRIG_POLARITY_INVERTED active low or falling edge active.
+ * @arg TIM_EXT_TRIG_POLARITY_NONINVERTED active high or rising edge active.
+ * @param ExtTRGFilter External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ */
+void TIM_ConfigExtClkMode2(TIM_Module* TIMx,
+ uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter)
+{
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimExtPreDiv(TIM_ExtTRGPrescaler));
+ assert_param(IsTimExtTrigPolarity(TIM_ExtTRGPolarity));
+ assert_param(IsTimExtTrigFilter(ExtTRGFilter));
+ /* Configure the ETR Clock source */
+ TIM_ConfigExtTrig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+ /* Enable the External clock mode2 */
+ TIMx->SMCTRL |= TIM_SMCTRL_EXCEN;
+}
+
+/**
+ * @brief Configures the TIMx External Trigger (ETR).
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_EXT_TRG_PSC_OFF ETRP Prescaler OFF.
+ * @arg TIM_EXT_TRG_PSC_DIV2 ETRP frequency divided by 2.
+ * @arg TIM_EXT_TRG_PSC_DIV4 ETRP frequency divided by 4.
+ * @arg TIM_EXT_TRG_PSC_DIV8 ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_EXT_TRIG_POLARITY_INVERTED active low or falling edge active.
+ * @arg TIM_EXT_TRIG_POLARITY_NONINVERTED active high or rising edge active.
+ * @param ExtTRGFilter External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ */
+void TIM_ConfigExtTrig(TIM_Module* TIMx,
+ uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter)
+{
+ uint16_t tmpsmcr = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimExtPreDiv(TIM_ExtTRGPrescaler));
+ assert_param(IsTimExtTrigPolarity(TIM_ExtTRGPolarity));
+ assert_param(IsTimExtTrigFilter(ExtTRGFilter));
+ tmpsmcr = TIMx->SMCTRL;
+ /* Reset the ETR Bits */
+ tmpsmcr &= SMCTRL_ETR_MASK;
+ /* Set the Prescaler, the Filter value and the Polarity */
+ tmpsmcr |=
+ (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
+ /* Write to TIMx SMCTRL */
+ TIMx->SMCTRL = tmpsmcr;
+}
+
+/**
+ * @brief Configures the TIMx Prescaler.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param Prescaler specifies the Prescaler Register value
+ * @param TIM_PSCReloadMode specifies the TIM Prescaler Reload mode
+ * This parameter can be one of the following values:
+ * @arg TIM_PSC_RELOAD_MODE_UPDATE The Prescaler is loaded at the update event.
+ * @arg TIM_PSC_RELOAD_MODE_IMMEDIATE The Prescaler is loaded immediately.
+ */
+void TIM_ConfigPrescaler(TIM_Module* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimPscReloadMode(TIM_PSCReloadMode));
+ /* Set the Prescaler value */
+ TIMx->PSC = Prescaler;
+ /* Set or reset the UG Bit */
+ TIMx->EVTGEN = TIM_PSCReloadMode;
+}
+
+/**
+ * @brief Specifies the TIMx Counter Mode to be used.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param CntMode specifies the Counter Mode to be used
+ * This parameter can be one of the following values:
+ * @arg TIM_CNT_MODE_UP TIM Up Counting Mode
+ * @arg TIM_CNT_MODE_DOWN TIM Down Counting Mode
+ * @arg TIM_CNT_MODE_CENTER_ALIGN1 TIM Center Aligned Mode1
+ * @arg TIM_CNT_MODE_CENTER_ALIGN2 TIM Center Aligned Mode2
+ * @arg TIM_CNT_MODE_CENTER_ALIGN3 TIM Center Aligned Mode3
+ */
+void TIM_ConfigCntMode(TIM_Module* TIMx, uint16_t CntMode)
+{
+ uint32_t tmpcr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimCntMode(CntMode));
+ tmpcr1 = TIMx->CTRL1;
+ /* Reset the CMS and DIR Bits */
+ tmpcr1 &= (uint32_t)(~((uint32_t)(TIM_CTRL1_DIR | TIM_CTRL1_CAMSEL)));
+ /* Set the Counter Mode */
+ tmpcr1 |= CntMode;
+ /* Write to TIMx CTRL1 register */
+ TIMx->CTRL1 = tmpcr1;
+}
+
+/**
+ * @brief Selects the Input Trigger source
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param TIM_InputTriggerSource The Input Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TRIG_SEL_IN_TR0 Internal Trigger 0
+ * @arg TIM_TRIG_SEL_IN_TR1 Internal Trigger 1
+ * @arg TIM_TRIG_SEL_IN_TR2 Internal Trigger 2
+ * @arg TIM_TRIG_SEL_IN_TR3 Internal Trigger 3
+ * @arg TIM_TRIG_SEL_TI1F_ED TI1 Edge Detector
+ * @arg TIM_TRIG_SEL_TI1FP1 Filtered Timer Input 1
+ * @arg TIM_TRIG_SEL_TI2FP2 Filtered Timer Input 2
+ * @arg TIM_TRIG_SEL_ETRF External Trigger input
+ */
+void TIM_SelectInputTrig(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource)
+{
+ uint16_t tmpsmcr = 0;
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimTrigSel(TIM_InputTriggerSource));
+ /* Get the TIMx SMCTRL register value */
+ tmpsmcr = TIMx->SMCTRL;
+ /* Reset the TS Bits */
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_TSEL));
+ /* Set the Input Trigger source */
+ tmpsmcr |= TIM_InputTriggerSource;
+ /* Write to TIMx SMCTRL */
+ TIMx->SMCTRL = tmpsmcr;
+}
+
+/**
+ * @brief Configures the TIMx Encoder Interface.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_EncoderMode specifies the TIMx Encoder Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_ENCODE_MODE_TI1 Counter counts on TI1FP1 edge depending on TI2FP2 level.
+ * @arg TIM_ENCODE_MODE_TI2 Counter counts on TI2FP2 edge depending on TI1FP1 level.
+ * @arg TIM_ENCODE_MODE_TI12 Counter counts on both TI1FP1 and TI2FP2 edges depending
+ * on the level of the other input.
+ * @param TIM_IC1Polarity specifies the IC1 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_POLARITY_FALLING IC Falling edge.
+ * @arg TIM_IC_POLARITY_RISING IC Rising edge.
+ * @param TIM_IC2Polarity specifies the IC2 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_POLARITY_FALLING IC Falling edge.
+ * @arg TIM_IC_POLARITY_RISING IC Rising edge.
+ */
+void TIM_ConfigEncoderInterface(TIM_Module* TIMx,
+ uint16_t TIM_EncoderMode,
+ uint16_t TIM_IC1Polarity,
+ uint16_t TIM_IC2Polarity)
+{
+ uint16_t tmpsmcr = 0;
+ uint16_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList5Module(TIMx));
+ assert_param(IsTimEncodeMode(TIM_EncoderMode));
+ assert_param(IsTimIcPalaritySingleEdge(TIM_IC1Polarity));
+ assert_param(IsTimIcPalaritySingleEdge(TIM_IC2Polarity));
+
+ /* Get the TIMx SMCTRL register value */
+ tmpsmcr = TIMx->SMCTRL;
+
+ /* Get the TIMx CCMOD1 register value */
+ tmpccmr1 = TIMx->CCMOD1;
+
+ /* Get the TIMx CCEN register value */
+ tmpccer = TIMx->CCEN;
+
+ /* Set the encoder Mode */
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_SMSEL));
+ tmpsmcr |= TIM_EncoderMode;
+
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+ tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD1_CC1SEL)) & (uint16_t)(~((uint16_t)TIM_CCMOD1_CC2SEL)));
+ tmpccmr1 |= TIM_CCMOD1_CC1SEL_0 | TIM_CCMOD1_CC2SEL_0;
+
+ /* Set the TI1 and the TI2 Polarities */
+ tmpccer &= (uint32_t)(((uint32_t) ~((uint32_t)TIM_CCEN_CC1P)) & ((uint32_t) ~((uint32_t)TIM_CCEN_CC2P)));
+ tmpccer |= (uint32_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
+
+ /* Write to TIMx SMCTRL */
+ TIMx->SMCTRL = tmpsmcr;
+ /* Write to TIMx CCMOD1 */
+ TIMx->CCMOD1 = tmpccmr1;
+ /* Write to TIMx CCEN */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Forces the TIMx output 1 waveform to active or inactive level.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC1REF
+ * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC1REF.
+ */
+void TIM_ConfigForcedOc1(TIM_Module* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimForceActive(TIM_ForcedAction));
+ tmpccmr1 = TIMx->CCMOD1;
+ /* Reset the OC1M Bits */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1M);
+ /* Configure The Forced output Mode */
+ tmpccmr1 |= TIM_ForcedAction;
+ /* Write to TIMx CCMOD1 register */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Forces the TIMx output 2 waveform to active or inactive level.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC2REF
+ * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC2REF.
+ */
+void TIM_ConfigForcedOc2(TIM_Module* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimForceActive(TIM_ForcedAction));
+ tmpccmr1 = TIMx->CCMOD1;
+ /* Reset the OC2M Bits */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2M);
+ /* Configure The Forced output Mode */
+ tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
+ /* Write to TIMx CCMOD1 register */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Forces the TIMx output 3 waveform to active or inactive level.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC3REF
+ * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC3REF.
+ */
+void TIM_ConfigForcedOc3(TIM_Module* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimForceActive(TIM_ForcedAction));
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC1M Bits */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3MD);
+ /* Configure The Forced output Mode */
+ tmpccmr2 |= TIM_ForcedAction;
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Forces the TIMx output 4 waveform to active or inactive level.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC4REF
+ * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC4REF.
+ */
+void TIM_ConfigForcedOc4(TIM_Module* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimForceActive(TIM_ForcedAction));
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC2M Bits */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4MD);
+ /* Configure The Forced output Mode */
+ tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Forces the TIMx output 5 waveform to active or inactive level.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC5REF
+ * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC5REF.
+ */
+void TIM_ConfigForcedOc5(TIM_Module* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimForceActive(TIM_ForcedAction));
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC2M Bits */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5MD);
+ /* Configure The Forced output Mode */
+ tmpccmr3 |= (uint16_t)(TIM_ForcedAction);
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Forces the TIMx output 6 waveform to active or inactive level.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC6REF
+ * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC6REF.
+ */
+void TIM_ConfigForcedOc6(TIM_Module* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimForceActive(TIM_ForcedAction));
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC2M Bits */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6MD);
+ /* Configure The Forced output Mode */
+ tmpccmr3 |= (uint16_t)(TIM_ForcedAction << 8);
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Enables or disables TIMx peripheral Preload register on AR.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param Cmd new state of the TIMx peripheral Preload register
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_ConfigArPreload(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set the AR Preload Bit */
+ TIMx->CTRL1 |= TIM_CTRL1_ARPEN;
+ }
+ else
+ {
+ /* Reset the AR Preload Bit */
+ TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_ARPEN);
+ }
+}
+
+/**
+ * @brief Selects the TIM peripheral Commutation event.
+ * @param TIMx where x can be 1, 8 to select the TIMx peripheral
+ * @param Cmd new state of the Commutation event.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_SelectComEvt(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimList2Module(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set the COM Bit */
+ TIMx->CTRL2 |= TIM_CTRL2_CCUSEL;
+ }
+ else
+ {
+ /* Reset the COM Bit */
+ TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_CCUSEL);
+ }
+}
+
+/**
+ * @brief Selects the TIMx peripheral Capture Compare DMA source.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select
+ * the TIM peripheral.
+ * @param Cmd new state of the Capture Compare DMA source
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_SelectCapCmpDmaSrc(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimList4Module(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set the CCDS Bit */
+ TIMx->CTRL2 |= TIM_CTRL2_CCDSEL;
+ }
+ else
+ {
+ /* Reset the CCDS Bit */
+ TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_CCDSEL);
+ }
+}
+
+/**
+ * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8
+ * to select the TIMx peripheral
+ * @param Cmd new state of the Capture Compare Preload Control bit
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_EnableCapCmpPreloadControl(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimList5Module(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set the CCPC Bit */
+ TIMx->CTRL2 |= TIM_CTRL2_CCPCTL;
+ }
+ else
+ {
+ /* Reset the CCPC Bit */
+ TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_CCPCTL);
+ }
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCDAT1.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_OCPreload new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_PRE_LOAD_ENABLE
+ * @arg TIM_OC_PRE_LOAD_DISABLE
+ */
+void TIM_ConfigOc1Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimOcPreLoadState(TIM_OCPreload));
+ tmpccmr1 = TIMx->CCMOD1;
+ /* Reset the OC1PE Bit */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1PEN);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr1 |= TIM_OCPreload;
+ /* Write to TIMx CCMOD1 register */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCDAT2.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select
+ * the TIM peripheral.
+ * @param TIM_OCPreload new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_PRE_LOAD_ENABLE
+ * @arg TIM_OC_PRE_LOAD_DISABLE
+ */
+void TIM_ConfigOc2Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimOcPreLoadState(TIM_OCPreload));
+ tmpccmr1 = TIMx->CCMOD1;
+ /* Reset the OC2PE Bit */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2PEN);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
+ /* Write to TIMx CCMOD1 register */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCDAT3.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_PRE_LOAD_ENABLE
+ * @arg TIM_OC_PRE_LOAD_DISABLE
+ */
+void TIM_ConfigOc3Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcPreLoadState(TIM_OCPreload));
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC3PE Bit */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3PEN);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr2 |= TIM_OCPreload;
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCDAT4.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_PRE_LOAD_ENABLE
+ * @arg TIM_OC_PRE_LOAD_DISABLE
+ */
+void TIM_ConfigOc4Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcPreLoadState(TIM_OCPreload));
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC4PE Bit */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4PEN);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCDAT5.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_PRE_LOAD_ENABLE
+ * @arg TIM_OC_PRE_LOAD_DISABLE
+ */
+void TIM_ConfigOc5Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcPreLoadState(TIM_OCPreload));
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC5PE Bit */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5PEN);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr3 |= (uint16_t)(TIM_OCPreload);
+ /* Write to TIMx CCMOD3 register */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCDAT6.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_PRE_LOAD_ENABLE
+ * @arg TIM_OC_PRE_LOAD_DISABLE
+ */
+void TIM_ConfigOc6Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcPreLoadState(TIM_OCPreload));
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC6PE Bit */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6PEN);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr3 |= (uint16_t)(TIM_OCPreload << 8);
+ /* Write to TIMx CCMOD3 register */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 1 Fast feature.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_OCFast new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable
+ * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable
+ */
+void TIM_ConfigOc1Fast(TIM_Module* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimOcFastState(TIM_OCFast));
+ /* Get the TIMx CCMOD1 register value */
+ tmpccmr1 = TIMx->CCMOD1;
+ /* Reset the OC1FE Bit */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1FEN);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr1 |= TIM_OCFast;
+ /* Write to TIMx CCMOD1 */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 2 Fast feature.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select
+ * the TIM peripheral.
+ * @param TIM_OCFast new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable
+ * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable
+ */
+void TIM_ConfigOc2Fast(TIM_Module* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimOcFastState(TIM_OCFast));
+ /* Get the TIMx CCMOD1 register value */
+ tmpccmr1 = TIMx->CCMOD1;
+ /* Reset the OC2FE Bit */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2FEN);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
+ /* Write to TIMx CCMOD1 */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 3 Fast feature.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable
+ * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable
+ */
+void TIM_ConfigOc3Fast(TIM_Module* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcFastState(TIM_OCFast));
+ /* Get the TIMx CCMOD2 register value */
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC3FE Bit */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3FEN);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr2 |= TIM_OCFast;
+ /* Write to TIMx CCMOD2 */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 4 Fast feature.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable
+ * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable
+ */
+void TIM_ConfigOc4Fast(TIM_Module* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcFastState(TIM_OCFast));
+ /* Get the TIMx CCMOD2 register value */
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC4FE Bit */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4FEN);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
+ /* Write to TIMx CCMOD2 */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 5 Fast feature.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable
+ * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable
+ */
+void TIM_ConfigOc5Fast(TIM_Module* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcFastState(TIM_OCFast));
+ /* Get the TIMx CCMOD2 register value */
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC4FE Bit */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5FEN);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr3 |= (uint16_t)(TIM_OCFast);
+ /* Write to TIMx CCMOD3 */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 6 Fast feature.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable
+ * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable
+ */
+void TIM_ConfigOc6Fast(TIM_Module* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcFastState(TIM_OCFast));
+ /* Get the TIMx CCMOD2 register value */
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC4FE Bit */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6FEN);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr3 |= (uint16_t)(TIM_OCFast << 8);
+ /* Write to TIMx CCMOD3 */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF1 signal on an external event
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_CLR_ENABLE TIM Output clear enable
+ * @arg TIM_OC_CLR_DISABLE TIM Output clear disable
+ */
+void TIM_ClrOc1Ref(TIM_Module* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcClrState(TIM_OCClear));
+
+ tmpccmr1 = TIMx->CCMOD1;
+
+ /* Reset the OC1CE Bit */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1CEN);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr1 |= TIM_OCClear;
+ /* Write to TIMx CCMOD1 register */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF2 signal on an external event
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_CLR_ENABLE TIM Output clear enable
+ * @arg TIM_OC_CLR_DISABLE TIM Output clear disable
+ */
+void TIM_ClrOc2Ref(TIM_Module* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcClrState(TIM_OCClear));
+ tmpccmr1 = TIMx->CCMOD1;
+ /* Reset the OC2CE Bit */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2CEN);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
+ /* Write to TIMx CCMOD1 register */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF3 signal on an external event
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_CLR_ENABLE TIM Output clear enable
+ * @arg TIM_OC_CLR_DISABLE TIM Output clear disable
+ */
+void TIM_ClrOc3Ref(TIM_Module* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcClrState(TIM_OCClear));
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC3CE Bit */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3CEN);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr2 |= TIM_OCClear;
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF4 signal on an external event
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_CLR_ENABLE TIM Output clear enable
+ * @arg TIM_OC_CLR_DISABLE TIM Output clear disable
+ */
+void TIM_ClrOc4Ref(TIM_Module* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcClrState(TIM_OCClear));
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC4CE Bit */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4CEN);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF5 signal on an external event
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_CLR_ENABLE TIM Output clear enable
+ * @arg TIM_OC_CLR_DISABLE TIM Output clear disable
+ */
+void TIM_ClrOc5Ref(TIM_Module* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcClrState(TIM_OCClear));
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC4CE Bit */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5CEN);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr3 |= (uint16_t)(TIM_OCClear);
+ /* Write to TIMx CCMOD3 register */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF6 signal on an external event
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_CLR_ENABLE TIM Output clear enable
+ * @arg TIM_OC_CLR_DISABLE TIM Output clear disable
+ */
+void TIM_ClrOc6Ref(TIM_Module* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcClrState(TIM_OCClear));
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC4CE Bit */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6CEN);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr3 |= (uint16_t)(TIM_OCClear << 8);
+ /* Write to TIMx CCMOD3 register */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Configures the TIMx channel 1 polarity.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param OcPolarity specifies the OC1 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OC_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc1Polarity(TIM_Module* TIMx, uint16_t OcPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimOcPolarity(OcPolarity));
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC1P Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC1P);
+ tmpccer |= OcPolarity;
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx Channel 1N polarity.
+ * @param TIMx where x can be 1, 8 to select the TIM peripheral.
+ * @param OcNPolarity specifies the OC1N Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCN_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OCN_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc1NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList2Module(TIMx));
+ assert_param(IsTimOcnPolarity(OcNPolarity));
+
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC1NP Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC1NP);
+ tmpccer |= OcNPolarity;
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 2 polarity.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param OcPolarity specifies the OC2 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OC_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc2Polarity(TIM_Module* TIMx, uint16_t OcPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimOcPolarity(OcPolarity));
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC2P Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC2P);
+ tmpccer |= (uint32_t)(OcPolarity << 4);
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx Channel 2N polarity.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param OcNPolarity specifies the OC2N Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCN_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OCN_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc2NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcnPolarity(OcNPolarity));
+
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC2NP Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC2NP);
+ tmpccer |= (uint32_t)(OcNPolarity << 4);
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 3 polarity.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param OcPolarity specifies the OC3 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OC_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc3Polarity(TIM_Module* TIMx, uint16_t OcPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcPolarity(OcPolarity));
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC3P Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC3P);
+ tmpccer |= (uint32_t)(OcPolarity << 8);
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx Channel 3N polarity.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param OcNPolarity specifies the OC3N Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCN_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OCN_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc3NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity)
+{
+ uint32_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcnPolarity(OcNPolarity));
+
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC3NP Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC3NP);
+ tmpccer |= (uint32_t)(OcNPolarity << 8);
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 4 polarity.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param OcPolarity specifies the OC4 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OC_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc4Polarity(TIM_Module* TIMx, uint16_t OcPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcPolarity(OcPolarity));
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC4P Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC4P);
+ tmpccer |= (uint32_t)(OcPolarity << 12);
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 5 polarity.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param OcPolarity specifies the OC5 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OC_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc5Polarity(TIM_Module* TIMx, uint16_t OcPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcPolarity(OcPolarity));
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC5P Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC5P);
+ tmpccer |= (uint32_t)(OcPolarity << 16);
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 6 polarity.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param OcPolarity specifies the OC6 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OC_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc6Polarity(TIM_Module* TIMx, uint16_t OcPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcPolarity(OcPolarity));
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC6P Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC6P);
+ tmpccer |= (uint32_t)(OcPolarity << 20);
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel x.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CH_1 TIM Channel 1
+ * @arg TIM_CH_2 TIM Channel 2
+ * @arg TIM_CH_3 TIM Channel 3
+ * @arg TIM_CH_4 TIM Channel 4
+ * @param TIM_CCx specifies the TIM Channel CCxE bit new state.
+ * This parameter can be: TIM_CAP_CMP_ENABLE or TIM_CAP_CMP_DISABLE.
+ */
+void TIM_EnableCapCmpCh(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCx)
+{
+ uint16_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimCh(Channel));
+ assert_param(IsTimCapCmpState(TIM_CCx));
+
+ tmp = CAPCMPEN_CCE_SET << Channel;
+
+ /* Reset the CCxE Bit */
+ TIMx->CCEN &= (uint32_t)~tmp;
+
+ /* Set or reset the CCxE Bit */
+ TIMx->CCEN |= (uint32_t)(TIM_CCx << Channel);
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel xN.
+ * @param TIMx where x can be 1, 8 to select the TIM peripheral.
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CH_1 TIM Channel 1
+ * @arg TIM_CH_2 TIM Channel 2
+ * @arg TIM_CH_3 TIM Channel 3
+ * @param TIM_CCxN specifies the TIM Channel CCxNE bit new state.
+ * This parameter can be: TIM_CAP_CMP_N_ENABLE or TIM_CAP_CMP_N_DISABLE.
+ */
+void TIM_EnableCapCmpChN(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCxN)
+{
+ uint16_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList2Module(TIMx));
+ assert_param(IsTimComplementaryCh(Channel));
+ assert_param(IsTimCapCmpNState(TIM_CCxN));
+
+ tmp = CAPCMPEN_CCNE_SET << Channel;
+
+ /* Reset the CCxNE Bit */
+ TIMx->CCEN &= (uint32_t)~tmp;
+
+ /* Set or reset the CCxNE Bit */
+ TIMx->CCEN |= (uint32_t)(TIM_CCxN << Channel);
+}
+
+/**
+ * @brief Selects the TIM Output Compare Mode.
+ * @note This function disables the selected channel before changing the Output
+ * Compare Mode.
+ * User has to enable this channel using TIM_EnableCapCmpCh and TIM_EnableCapCmpChN functions.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CH_1 TIM Channel 1
+ * @arg TIM_CH_2 TIM Channel 2
+ * @arg TIM_CH_3 TIM Channel 3
+ * @arg TIM_CH_4 TIM Channel 4
+ * @param OcMode specifies the TIM Output Compare Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCMODE_TIMING
+ * @arg TIM_OCMODE_ACTIVE
+ * @arg TIM_OCMODE_TOGGLE
+ * @arg TIM_OCMODE_PWM1
+ * @arg TIM_OCMODE_PWM2
+ * @arg TIM_FORCED_ACTION_ACTIVE
+ * @arg TIM_FORCED_ACTION_INACTIVE
+ */
+void TIM_SelectOcMode(TIM_Module* TIMx, uint16_t Channel, uint16_t OcMode)
+{
+ uint32_t tmp = 0;
+ uint16_t tmp1 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimCh(Channel));
+ assert_param(IsTimOc(OcMode));
+
+ tmp = (uint32_t)TIMx;
+ tmp += CAPCMPMOD_OFFSET;
+
+ tmp1 = CAPCMPEN_CCE_SET << (uint16_t)Channel;
+
+ /* Disable the Channel: Reset the CCxE Bit */
+ TIMx->CCEN &= (uint16_t)~tmp1;
+
+ if ((Channel == TIM_CH_1) || (Channel == TIM_CH_3))
+ {
+ tmp += (Channel >> 1);
+
+ /* Reset the OCxM bits in the CCMRx register */
+ *(__IO uint32_t*)tmp &= (uint32_t) ~((uint32_t)TIM_CCMOD1_OC1M);
+
+ /* Configure the OCxM bits in the CCMRx register */
+ *(__IO uint32_t*)tmp |= OcMode;
+ }
+ else
+ {
+ tmp += (uint16_t)(Channel - (uint16_t)4) >> (uint16_t)1;
+
+ /* Reset the OCxM bits in the CCMRx register */
+ *(__IO uint32_t*)tmp &= (uint32_t) ~((uint32_t)TIM_CCMOD1_OC2M);
+
+ /* Configure the OCxM bits in the CCMRx register */
+ *(__IO uint32_t*)tmp |= (uint16_t)(OcMode << 8);
+ }
+}
+
+/**
+ * @brief Enables or Disables the TIMx Update event.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param Cmd new state of the TIMx UDIS bit
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_EnableUpdateEvt(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set the Update Disable Bit */
+ TIMx->CTRL1 |= TIM_CTRL1_UPDIS;
+ }
+ else
+ {
+ /* Reset the Update Disable Bit */
+ TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_UPDIS);
+ }
+}
+
+/**
+ * @brief Configures the TIMx Update Request Interrupt source.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_UpdateSource specifies the Update source.
+ * This parameter can be one of the following values:
+ * @arg TIM_UPDATE_SRC_REGULAr Source of update is the counter overflow/underflow
+ or the setting of UG bit, or an update generation
+ through the slave mode controller.
+ * @arg TIM_UPDATE_SRC_GLOBAL Source of update is counter overflow/underflow.
+ */
+void TIM_ConfigUpdateRequestIntSrc(TIM_Module* TIMx, uint16_t TIM_UpdateSource)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimUpdateSrc(TIM_UpdateSource));
+ if (TIM_UpdateSource != TIM_UPDATE_SRC_GLOBAL)
+ {
+ /* Set the URS Bit */
+ TIMx->CTRL1 |= TIM_CTRL1_UPRS;
+ }
+ else
+ {
+ /* Reset the URS Bit */
+ TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_UPRS);
+ }
+}
+
+/**
+ * @brief Enables or disables the TIMx's Hall sensor interface.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param Cmd new state of the TIMx Hall sensor interface.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_SelectHallSensor(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set the TI1S Bit */
+ TIMx->CTRL2 |= TIM_CTRL2_TI1SEL;
+ }
+ else
+ {
+ /* Reset the TI1S Bit */
+ TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_TI1SEL);
+ }
+}
+
+/**
+ * @brief Selects the TIMx's One Pulse Mode.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_OPMode specifies the OPM Mode to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_OPMODE_SINGLE
+ * @arg TIM_OPMODE_REPET
+ */
+void TIM_SelectOnePulseMode(TIM_Module* TIMx, uint16_t TIM_OPMode)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimOpMOde(TIM_OPMode));
+ /* Reset the OPM Bit */
+ TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_ONEPM);
+ /* Configure the OPM Mode */
+ TIMx->CTRL1 |= TIM_OPMode;
+}
+
+/**
+ * @brief Selects the TIMx Trigger Output Mode.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 6, 7, 8 to select the TIM peripheral.
+ * @param TIM_TRGOSource specifies the Trigger Output source.
+ * This paramter can be one of the following values:
+ *
+ * - For all TIMx
+ * @arg TIM_TRGO_SRC_RESET The UG bit in the TIM_EVTGEN register is used as the trigger output (TRGO).
+ * @arg TIM_TRGO_SRC_ENABLE The Counter Enable CEN is used as the trigger output (TRGO).
+ * @arg TIM_TRGO_SRC_UPDATE The update event is selected as the trigger output (TRGO).
+ *
+ * - For all TIMx except TIM6 and TIM7
+ * @arg TIM_TRGO_SRC_OC1 The trigger output sends a positive pulse when the CC1IF flag
+ * is to be set, as soon as a capture or compare match occurs (TRGO).
+ * @arg TIM_TRGO_SRC_OC1REF OC1REF signal is used as the trigger output (TRGO).
+ * @arg TIM_TRGO_SRC_OC2REF OC2REF signal is used as the trigger output (TRGO).
+ * @arg TIM_TRGO_SRC_OC3REF OC3REF signal is used as the trigger output (TRGO).
+ * @arg TIM_TRGO_SRC_OC4REF OC4REF signal is used as the trigger output (TRGO).
+ *
+ */
+void TIM_SelectOutputTrig(TIM_Module* TIMx, uint16_t TIM_TRGOSource)
+{
+ /* Check the parameters */
+ assert_param(IsTimList7Module(TIMx));
+ assert_param(IsTimTrgoSrc(TIM_TRGOSource));
+ /* Reset the MMS Bits */
+ TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_MMSEL);
+ /* Select the TRGO source */
+ TIMx->CTRL2 |= TIM_TRGOSource;
+}
+
+/**
+ * @brief Selects the TIMx Slave Mode.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param TIM_SlaveMode specifies the Timer Slave Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_SLAVE_MODE_RESET Rising edge of the selected trigger signal (TRGI) re-initializes
+ * the counter and triggers an update of the registers.
+ * @arg TIM_SLAVE_MODE_GATED The counter clock is enabled when the trigger signal (TRGI) is high.
+ * @arg TIM_SLAVE_MODE_TRIG The counter starts at a rising edge of the trigger TRGI.
+ * @arg TIM_SLAVE_MODE_EXT1 Rising edges of the selected trigger (TRGI) clock the counter.
+ */
+void TIM_SelectSlaveMode(TIM_Module* TIMx, uint16_t TIM_SlaveMode)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimSlaveMode(TIM_SlaveMode));
+ /* Reset the SMS Bits */
+ TIMx->SMCTRL &= (uint16_t) ~((uint16_t)TIM_SMCTRL_SMSEL);
+ /* Select the Slave Mode */
+ TIMx->SMCTRL |= TIM_SlaveMode;
+}
+
+/**
+ * @brief Sets or Resets the TIMx Master/Slave Mode.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param TIM_MasterSlaveMode specifies the Timer Master Slave Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_MASTER_SLAVE_MODE_ENABLE synchronization between the current timer
+ * and its slaves (through TRGO).
+ * @arg TIM_MASTER_SLAVE_MODE_DISABLE No action
+ */
+void TIM_SelectMasterSlaveMode(TIM_Module* TIMx, uint16_t TIM_MasterSlaveMode)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimMasterSlaveMode(TIM_MasterSlaveMode));
+ /* Reset the MSM Bit */
+ TIMx->SMCTRL &= (uint16_t) ~((uint16_t)TIM_SMCTRL_MSMD);
+
+ /* Set or Reset the MSM Bit */
+ TIMx->SMCTRL |= TIM_MasterSlaveMode;
+}
+
+/**
+ * @brief Sets the TIMx Counter Register value
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param Counter specifies the Counter register new value.
+ */
+void TIM_SetCnt(TIM_Module* TIMx, uint16_t Counter)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ /* Set the Counter Register value */
+ TIMx->CNT = Counter;
+}
+
+/**
+ * @brief Sets the TIMx Autoreload Register value
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param Autoreload specifies the Autoreload register new value.
+ */
+void TIM_SetAutoReload(TIM_Module* TIMx, uint16_t Autoreload)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ /* Set the Autoreload Register value */
+ TIMx->AR = Autoreload;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare1 Register value
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param Compare1 specifies the Capture Compare1 register new value.
+ */
+void TIM_SetCmp1(TIM_Module* TIMx, uint16_t Compare1)
+{
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ /* Set the Capture Compare1 Register value */
+ TIMx->CCDAT1 = Compare1;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare2 Register value
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param Compare2 specifies the Capture Compare2 register new value.
+ */
+void TIM_SetCmp2(TIM_Module* TIMx, uint16_t Compare2)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ /* Set the Capture Compare2 Register value */
+ TIMx->CCDAT2 = Compare2;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare3 Register value
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param Compare3 specifies the Capture Compare3 register new value.
+ */
+void TIM_SetCmp3(TIM_Module* TIMx, uint16_t Compare3)
+{
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ /* Set the Capture Compare3 Register value */
+ TIMx->CCDAT3 = Compare3;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare4 Register value
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param Compare4 specifies the Capture Compare4 register new value.
+ */
+void TIM_SetCmp4(TIM_Module* TIMx, uint16_t Compare4)
+{
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ /* Set the Capture Compare4 Register value */
+ TIMx->CCDAT4 = Compare4;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare5 Register value
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param Compare5 specifies the Capture Compare5 register new value.
+ */
+void TIM_SetCmp5(TIM_Module* TIMx, uint16_t Compare5)
+{
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ /* Set the Capture Compare4 Register value */
+ TIMx->CCDAT5 = Compare5;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare4 Register value
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param Compare6 specifies the Capture Compare6 register new value.
+ */
+void TIM_SetCmp6(TIM_Module* TIMx, uint16_t Compare6)
+{
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ /* Set the Capture Compare4 Register value */
+ TIMx->CCDAT6 = Compare6;
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 1 prescaler.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_ICPSC specifies the Input Capture1 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_PSC_DIV1 no prescaler
+ * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events
+ * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events
+ * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events
+ */
+void TIM_SetInCap1Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimIcPrescaler(TIM_ICPSC));
+ /* Reset the IC1PSC Bits */
+ TIMx->CCMOD1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_IC1PSC);
+ /* Set the IC1PSC value */
+ TIMx->CCMOD1 |= TIM_ICPSC;
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 2 prescaler.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param TIM_ICPSC specifies the Input Capture2 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_PSC_DIV1 no prescaler
+ * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events
+ * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events
+ * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events
+ */
+void TIM_SetInCap2Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimIcPrescaler(TIM_ICPSC));
+ /* Reset the IC2PSC Bits */
+ TIMx->CCMOD1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_IC2PSC);
+ /* Set the IC2PSC value */
+ TIMx->CCMOD1 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 3 prescaler.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPSC specifies the Input Capture3 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_PSC_DIV1 no prescaler
+ * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events
+ * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events
+ * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events
+ */
+void TIM_SetInCap3Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimIcPrescaler(TIM_ICPSC));
+ /* Reset the IC3PSC Bits */
+ TIMx->CCMOD2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_IC3PSC);
+ /* Set the IC3PSC value */
+ TIMx->CCMOD2 |= TIM_ICPSC;
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 4 prescaler.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPSC specifies the Input Capture4 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_PSC_DIV1 no prescaler
+ * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events
+ * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events
+ * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events
+ */
+void TIM_SetInCap4Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimIcPrescaler(TIM_ICPSC));
+ /* Reset the IC4PSC Bits */
+ TIMx->CCMOD2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_IC4PSC);
+ /* Set the IC4PSC value */
+ TIMx->CCMOD2 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/**
+ * @brief Sets the TIMx Clock Division value.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select
+ * the TIM peripheral.
+ * @param TIM_CKD specifies the clock division value.
+ * This parameter can be one of the following value:
+ * @arg TIM_CLK_DIV1 TDTS = Tck_tim
+ * @arg TIM_CLK_DIV2 TDTS = 2*Tck_tim
+ * @arg TIM_CLK_DIV4 TDTS = 4*Tck_tim
+ */
+void TIM_SetClkDiv(TIM_Module* TIMx, uint16_t TIM_CKD)
+{
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimClkDiv(TIM_CKD));
+ /* Reset the CKD Bits */
+ TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_CLKD);
+ /* Set the CKD value */
+ TIMx->CTRL1 |= TIM_CKD;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 1 value.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @return Capture Compare 1 Register value.
+ */
+uint16_t TIM_GetCap1(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ /* Get the Capture 1 Register value */
+ return TIMx->CCDAT1;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 2 value.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @return Capture Compare 2 Register value.
+ */
+uint16_t TIM_GetCap2(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ /* Get the Capture 2 Register value */
+ return TIMx->CCDAT2;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 3 value.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @return Capture Compare 3 Register value.
+ */
+uint16_t TIM_GetCap3(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ /* Get the Capture 3 Register value */
+ return TIMx->CCDAT3;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 4 value.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @return Capture Compare 4 Register value.
+ */
+uint16_t TIM_GetCap4(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ /* Get the Capture 4 Register value */
+ return TIMx->CCDAT4;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 5 value.
+ * @param TIMx where x can be 1 8 to select the TIM peripheral.
+ * @return Capture Compare 5 Register value.
+ */
+uint16_t TIM_GetCap5(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ /* Get the Capture 5 Register value */
+ return TIMx->CCDAT5;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 6 value.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @return Capture Compare 6 Register value.
+ */
+uint16_t TIM_GetCap6(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ /* Get the Capture 6 Register value */
+ return TIMx->CCDAT6;
+}
+
+/**
+ * @brief Gets the TIMx Counter value.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @return Counter Register value.
+ */
+uint16_t TIM_GetCnt(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ /* Get the Counter Register value */
+ return TIMx->CNT;
+}
+
+/**
+ * @brief Gets the TIMx Prescaler value.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @return Prescaler Register value.
+ */
+uint16_t TIM_GetPrescaler(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ /* Get the Prescaler Register value */
+ return TIMx->PSC;
+}
+
+/**
+ * @brief Gets the TIMx Prescaler value.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @return Prescaler Register value.
+ */
+uint16_t TIM_GetAutoReload(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ /* Get the Prescaler Register value */
+ return TIMx->AR;
+}
+
+/**
+ * @brief Checks whether the specified TIM flag is set or not.
+ * @param TIMx where x can be 1 to 5 , 8 ,9 to select the TIM peripheral.
+ * @param TIM_CCEN specifies the Bit to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_CC1EN CC1EN Bit
+ * @arg TIM_CC1NEN CC1NEN Bit
+ * @arg TIM_CC2EN CC2EN Bit
+ * @arg TIM_CC2NEN CC2NEN Bit
+ * @arg TIM_CC3EN CC3EN Bit
+ * @arg TIM_CC3NEN CC3NEN Bit
+ * @arg TIM_CC4EN CC4EN Bit
+ * @arg TIM_CC5EN CC5EN Bit
+ * @arg TIM_CC6EN CC6EN Bit
+ * @note
+ * - TIM_CC1NEN TIM_CC2NEN TIM_CC3NEN is used only with TIM1, TIM8.
+ * @return The new state of TIM_FLAG (SET or RESET).
+ */
+FlagStatus TIM_GetCCENStatus(TIM_Module* TIMx, uint32_t TIM_CCEN)
+{
+ INTStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+
+ if (TIMx==TIM1 || TIMx==TIM8){
+ assert_param(IsAdvancedTimCCENFlag(TIM_CCEN));
+ if ((TIMx->CCEN & TIM_CCEN) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }else if (TIMx==TIM2 || TIMx==TIM3 || TIMx==TIM4 || TIMx==TIM5 || TIMx==TIM9){
+ assert_param(IsGeneralTimCCENFlag(TIM_CCEN));
+ if ((TIMx->CCEN & TIM_CCEN) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+
+ return bitstatus;
+}
+
+/**
+ * @brief Checks whether the specified TIM flag is set or not.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_FLAG specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_FLAG_UPDATE TIM update Flag
+ * @arg TIM_FLAG_CC1 TIM Capture Compare 1 Flag
+ * @arg TIM_FLAG_CC2 TIM Capture Compare 2 Flag
+ * @arg TIM_FLAG_CC3 TIM Capture Compare 3 Flag
+ * @arg TIM_FLAG_CC4 TIM Capture Compare 4 Flag
+ * @arg TIM_FLAG_COM TIM Commutation Flag
+ * @arg TIM_FLAG_TRIG TIM Trigger Flag
+ * @arg TIM_FLAG_BREAK TIM Break Flag
+ * @arg TIM_FLAG_CC1OF TIM Capture Compare 1 overcapture Flag
+ * @arg TIM_FLAG_CC2OF TIM Capture Compare 2 overcapture Flag
+ * @arg TIM_FLAG_CC3OF TIM Capture Compare 3 overcapture Flag
+ * @arg TIM_FLAG_CC4OF TIM Capture Compare 4 overcapture Flag
+ * @arg TIM_FLAG_CC5 TIM Capture Compare 5 Flag
+ * @arg TIM_FLAG_CC6 TIM Capture Compare 6 Flag
+ * @note
+ * - TIM6 and TIM7 can have only one update flag.
+ * - TIM_FLAG_BREAK is used only with TIM1, TIM8.
+ * - TIM_FLAG_COM is used only with TIM1, TIM8.
+ * @return The new state of TIM_FLAG (SET or RESET).
+ */
+FlagStatus TIM_GetFlagStatus(TIM_Module* TIMx, uint32_t TIM_FLAG)
+{
+ INTStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimGetFlag(TIM_FLAG));
+
+ if ((TIMx->STS & TIM_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the TIMx's pending flags.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_FLAG specifies the flag bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_FLAG_UPDATE TIM update Flag
+ * @arg TIM_FLAG_CC1 TIM Capture Compare 1 Flag
+ * @arg TIM_FLAG_CC2 TIM Capture Compare 2 Flag
+ * @arg TIM_FLAG_CC3 TIM Capture Compare 3 Flag
+ * @arg TIM_FLAG_CC4 TIM Capture Compare 4 Flag
+ * @arg TIM_FLAG_COM TIM Commutation Flag
+ * @arg TIM_FLAG_TRIG TIM Trigger Flag
+ * @arg TIM_FLAG_BREAK TIM Break Flag
+ * @arg TIM_FLAG_CC1OF TIM Capture Compare 1 overcapture Flag
+ * @arg TIM_FLAG_CC2OF TIM Capture Compare 2 overcapture Flag
+ * @arg TIM_FLAG_CC3OF TIM Capture Compare 3 overcapture Flag
+ * @arg TIM_FLAG_CC4OF TIM Capture Compare 4 overcapture Flag
+ * @note
+ * - TIM6 and TIM7 can have only one update flag.
+ * - TIM_FLAG_BREAK is used only with TIM1, TIM8.
+ * - TIM_FLAG_COM is used only with TIM1, TIM8.
+ */
+void TIM_ClearFlag(TIM_Module* TIMx, uint32_t TIM_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimClrFlag(TIM_FLAG));
+
+ /* Clear the flags */
+ TIMx->STS = (uint32_t)~TIM_FLAG;
+}
+
+/**
+ * @brief Checks whether the TIM interrupt has occurred or not.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_IT specifies the TIM interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_INT_UPDATE TIM update Interrupt source
+ * @arg TIM_INT_CC1 TIM Capture Compare 1 Interrupt source
+ * @arg TIM_INT_CC2 TIM Capture Compare 2 Interrupt source
+ * @arg TIM_INT_CC3 TIM Capture Compare 3 Interrupt source
+ * @arg TIM_INT_CC4 TIM Capture Compare 4 Interrupt source
+ * @arg TIM_INT_COM TIM Commutation Interrupt source
+ * @arg TIM_INT_TRIG TIM Trigger Interrupt source
+ * @arg TIM_INT_BREAK TIM Break Interrupt source
+ * @note
+ * - TIM6 and TIM7 can generate only an update interrupt.
+ * - TIM_INT_BREAK is used only with TIM1, TIM8.
+ * - TIM_INT_COM is used only with TIM1, TIM8.
+ * @return The new state of the TIM_IT(SET or RESET).
+ */
+INTStatus TIM_GetIntStatus(TIM_Module* TIMx, uint32_t TIM_IT)
+{
+ INTStatus bitstatus = RESET;
+ uint32_t itstatus = 0x0, itenable = 0x0;
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimGetInt(TIM_IT));
+
+ itstatus = TIMx->STS & TIM_IT;
+
+ itenable = TIMx->DINTEN & TIM_IT;
+ if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the TIMx's interrupt pending bits.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_IT specifies the pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_INT_UPDATE TIM1 update Interrupt source
+ * @arg TIM_INT_CC1 TIM Capture Compare 1 Interrupt source
+ * @arg TIM_INT_CC2 TIM Capture Compare 2 Interrupt source
+ * @arg TIM_INT_CC3 TIM Capture Compare 3 Interrupt source
+ * @arg TIM_INT_CC4 TIM Capture Compare 4 Interrupt source
+ * @arg TIM_INT_COM TIM Commutation Interrupt source
+ * @arg TIM_INT_TRIG TIM Trigger Interrupt source
+ * @arg TIM_INT_BREAK TIM Break Interrupt source
+ * @note
+ * - TIM6 and TIM7 can generate only an update interrupt.
+ * - TIM_INT_BREAK is used only with TIM1, TIM8.
+ * - TIM_INT_COM is used only with TIM1, TIM8.
+ */
+void TIM_ClrIntPendingBit(TIM_Module* TIMx, uint32_t TIM_IT)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimInt(TIM_IT));
+ /* Clear the IT pending Bit */
+ TIMx->STS = (uint32_t)~TIM_IT;
+}
+
+/**
+ * @brief Configure the TI1 as Input.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param IcPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_POLARITY_RISING
+ * @arg TIM_IC_POLARITY_FALLING
+ * @param IcSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 1 is selected to be connected to IC1.
+ * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 1 is selected to be connected to IC2.
+ * @arg TIM_IC_SELECTION_TRC TIM Input 1 is selected to be connected to TRC.
+ * @param IcFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ */
+static void ConfigTI1(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter)
+{
+ uint16_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0;
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC1EN);
+ tmpccmr1 = TIMx->CCMOD1;
+ tmpccer = TIMx->CCEN;
+ /* Select the Input and set the filter */
+ tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD1_CC1SEL)) & ((uint16_t) ~((uint16_t)TIM_CCMOD1_IC1F)));
+ tmpccmr1 |= (uint16_t)(IcSelection | (uint16_t)(IcFilter << (uint16_t)4));
+
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9))
+ {
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC1P));
+ tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC1EN);
+ }
+ else
+ {
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC1P | TIM_CCEN_CC1NP));
+ tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC1EN);
+ }
+
+ /* Write to TIMx CCMOD1 and CCEN registers */
+ TIMx->CCMOD1 = tmpccmr1;
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configure the TI2 as Input.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param IcPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_POLARITY_RISING
+ * @arg TIM_IC_POLARITY_FALLING
+ * @param IcSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 2 is selected to be connected to IC2.
+ * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 2 is selected to be connected to IC1.
+ * @arg TIM_IC_SELECTION_TRC TIM Input 2 is selected to be connected to TRC.
+ * @param IcFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ */
+static void ConfigTI2(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter)
+{
+ uint16_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0, tmp = 0;
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC2EN);
+ tmpccmr1 = TIMx->CCMOD1;
+ tmpccer = TIMx->CCEN;
+ tmp = (uint32_t)(IcPolarity << 4);
+ /* Select the Input and set the filter */
+ tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD1_CC2SEL)) & ((uint16_t) ~((uint16_t)TIM_CCMOD1_IC2F)));
+ tmpccmr1 |= (uint16_t)(IcFilter << 12);
+ tmpccmr1 |= (uint16_t)(IcSelection << 8);
+
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9))
+ {
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC2P));
+ tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCEN_CC2EN);
+ }
+ else
+ {
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC2P | TIM_CCEN_CC2NP));
+ tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC2EN);
+ }
+
+ /* Write to TIMx CCMOD1 and CCEN registers */
+ TIMx->CCMOD1 = tmpccmr1;
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configure the TI3 as Input.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param IcPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_POLARITY_RISING
+ * @arg TIM_IC_POLARITY_FALLING
+ * @param IcSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 3 is selected to be connected to IC3.
+ * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 3 is selected to be connected to IC4.
+ * @arg TIM_IC_SELECTION_TRC TIM Input 3 is selected to be connected to TRC.
+ * @param IcFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ */
+static void ConfigTI3(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter)
+{
+ uint16_t tmpccmr2 = 0;
+ uint32_t tmpccer = 0, tmp = 0;
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC3EN);
+ tmpccmr2 = TIMx->CCMOD2;
+ tmpccer = TIMx->CCEN;
+ tmp = (uint32_t)(IcPolarity << 8);
+ /* Select the Input and set the filter */
+ tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD2_CC3SEL)) & ((uint16_t) ~((uint16_t)TIM_CCMOD2_IC3F)));
+ tmpccmr2 |= (uint16_t)(IcSelection | (uint16_t)(IcFilter << (uint16_t)4));
+
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9))
+ {
+ /* Select the Polarity and set the CC3E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC3P));
+ tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCEN_CC3EN);
+ }
+ else
+ {
+ /* Select the Polarity and set the CC3E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC3P | TIM_CCEN_CC3NP));
+ tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC3EN);
+ }
+
+ /* Write to TIMx CCMOD2 and CCEN registers */
+ TIMx->CCMOD2 = tmpccmr2;
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configure the TI4 as Input.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param IcPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_POLARITY_RISING
+ * @arg TIM_IC_POLARITY_FALLING
+ * @param IcSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 4 is selected to be connected to IC4.
+ * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 4 is selected to be connected to IC3.
+ * @arg TIM_IC_SELECTION_TRC TIM Input 4 is selected to be connected to TRC.
+ * @param IcFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ */
+static void ConfigTI4(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter)
+{
+ uint16_t tmpccmr2 = 0;
+ uint32_t tmpccer = 0, tmp = 0;
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC4EN);
+ tmpccmr2 = TIMx->CCMOD2;
+ tmpccer = TIMx->CCEN;
+ tmp = (uint32_t)(IcPolarity << 12);
+ /* Select the Input and set the filter */
+ tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMOD2_CC4SEL) & ((uint16_t) ~((uint16_t)TIM_CCMOD2_IC4F)));
+ tmpccmr2 |= (uint16_t)(IcSelection << 8);
+ tmpccmr2 |= (uint16_t)(IcFilter << 12);
+
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9))
+ {
+ /* Select the Polarity and set the CC4E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC4P));
+ tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCEN_CC4EN);
+ }
+ else
+ {
+ /* Select the Polarity and set the CC4E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC4P));
+ tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC4EN);
+ }
+ /* Write to TIMx CCMOD2 and CCEN registers */
+ TIMx->CCMOD2 = tmpccmr2;
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_tsc.c b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_tsc.c
new file mode 100644
index 0000000000..eb98157a56
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_tsc.c
@@ -0,0 +1,279 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_tsc.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x.h"
+#include "n32g43x_tsc.h"
+
+/**
+* @brief Init TSC config
+* @param InitParam: TSC initialize structure
+* @return : TSC_ErrorTypeDef
+*/
+TSC_ErrorTypeDef TSC_Init(TSC_InitType* InitParam)
+{
+ uint32_t tempreg,timeout;
+
+ assert_param(IS_TSC_DET_MODE(InitParam->Mode));
+ assert_param(IS_TSC_PAD_OPTION(InitParam->PadOpt));
+ assert_param(IS_TSC_PAD_SPEED(InitParam->Speed));
+
+ /* waiting tsc hw for idle status.*/
+ timeout = 0;
+ do
+ {
+ __TSC_HW_DISABLE();
+
+ if (++timeout > TSC_TIMEOUT)
+ return TSC_ERROR_HW_MODE;
+ }while (__TSC_GET_HW_MODE());
+
+ /*TSC_CTRL config*/
+ tempreg = 0;
+ if (InitParam->Mode == TSC_HW_DETECT_MODE)
+ {
+ assert_param(IS_TSC_DET_PERIOD(InitParam->Period));
+ assert_param(IS_TSC_FILTER(InitParam->Filter));
+ assert_param(IS_TSC_DET_TYPE(InitParam->Type));
+ assert_param(IS_TSC_INT(InitParam->Int));
+
+ tempreg |= InitParam->Period;
+ tempreg |= InitParam->Filter;
+ tempreg |= InitParam->Type;
+ tempreg |= InitParam->Int;
+ }
+ else
+ {
+ assert_param(IS_TSC_OUT(InitParam->Out));
+ tempreg |= InitParam->Out;
+ }
+
+ TSC->CTRL = tempreg;
+
+ /*TSC_ANA_SEL config*/
+ TSC->ANA_SEL = InitParam->PadOpt | InitParam->Speed;
+
+ return TSC_ERROR_OK;
+}
+
+/**
+ * @brief Config the clock source of TSC
+ * @param TSC_ClkSource specifies the clock source of TSC
+ * This parameter can be one of the following values:
+ * @arg TSC_CLK_SRC_LSI: TSC clock source is LSI(default)
+ * @arg TSC_CLK_SRC_LSE: TSC clock source is LSE,and LSE is oscillator
+ * @arg TSC_CLK_SRC_LSE_BYPASS: TSC clock source is LSE,and LSE is extennal clock
+ * @retval TSC error code
+ */
+TSC_ErrorTypeDef TSC_ClockConfig(uint32_t TSC_ClkSource)
+{
+ uint32_t timeout;
+
+ /*Enable PWR peripheral Clock*/
+ RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR,ENABLE);
+
+ if (TSC_CLK_SRC_LSI == TSC_ClkSource)
+ {
+ /*enable LSI clock*/
+ RCC_EnableLsi(ENABLE);
+
+ /*Wait LSI stable*/
+ timeout = 0;
+ while (RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_LSIRD) == RESET)
+ {
+ if (++timeout >TSC_TIMEOUT)
+ return TSC_ERROR_CLOCK;
+ }
+ }
+ else if ((TSC_CLK_SRC_LSE_BYPASS==TSC_ClkSource)||(TSC_CLK_SRC_LSE==TSC_ClkSource))
+ {
+ if (RCC_GetFlagStatus(RCC_LDCTRL_FLAG_LSERD)==RESET)
+ {
+ RCC_ConfigLse((TSC_ClkSource & (~RCC_LDCTRL_LSXSEL)),0x28);
+ timeout = 0;
+ while (RCC_GetFlagStatus(RCC_LDCTRL_FLAG_LSERD) == RESET)
+ {
+ if (++timeout >TSC_TIMEOUT)
+ return TSC_ERROR_CLOCK;
+ }
+ }
+ }
+ else
+ return TSC_ERROR_PARAMETER;
+
+ // Set bit 8 of PWR_CTRL1.Open PWR DBP.
+ PWR_BackupAccessEnable(ENABLE); //PWR->CTRL1 |= 0x100;
+
+ /*set LSI as TSC clock source*/
+ RCC_ConfigLSXClk(TSC_ClkSource & RCC_LDCTRL_LSXSEL);
+
+ /*Enable TSC clk*/
+ RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TSC,ENABLE);
+
+ return TSC_ERROR_OK;
+}
+
+/**
+* @brief Configure internal charge resistor for some channels
+* @param res: internal resistor selecte
+* This parameter can be one of the following values:
+* @arg TSC_RESR_CHN_RESIST_0: 1M OHM
+* @arg TSC_RESR_CHN_RESIST_1: 882K OHM
+* @arg TSC_RESR_CHN_RESIST_2: 756K OHM
+* @arg TSC_RESR_CHN_RESIST_3: 630K OHM
+* @arg TSC_RESR_CHN_RESIST_4: 504K OHM
+* @arg TSC_RESR_CHN_RESIST_5: 378K OHM
+* @arg TSC_RESR_CHN_RESIST_6: 252K OHM
+* @arg TSC_RESR_CHN_RESIST_7: 126K OHM
+* @param Channels: channels to be configed, as TSC_CHNEN defined
+* This parameter:bit[0:23] used,bit[24:31] must be 0
+* bitx: TSC channel x
+* @return: none
+*/
+TSC_ErrorTypeDef TSC_ConfigInternalResistor(uint32_t Channels, uint32_t res )
+{
+ uint32_t i,chn,timeout,nReg,nPos;
+
+ assert_param(IS_TSC_CHN(Channels));
+ assert_param(IS_TSC_RESISTOR_VALUE(res));
+
+ /*Check charge resistor value */
+ if (res > TSC_RESRx_CHN_RESIST_7)
+ return TSC_ERROR_PARAMETER;
+
+ /* waiting tsc hw for idle status.*/
+ timeout = 0;
+ do
+ {
+ __TSC_HW_DISABLE();
+
+ if (++timeout > TSC_TIMEOUT)
+ return TSC_ERROR_HW_MODE;
+ }while (__TSC_GET_HW_MODE());
+
+ /* Mask invalie bits*/
+ chn = Channels & TSC_CHNEN_CHN_SELx_Msk;
+
+ /* Set resistance for each channel one by one*/
+ for (i = 0; i> 3;
+ nPos = (i & 0x7UL)*4;
+ MODIFY_REG(TSC->RESR[nReg],TSC_RESRx_CHN_RESIST_Msk<>= 1;
+ }
+
+ return TSC_ERROR_OK;
+}
+
+/**
+* @brief Configure threshold value for some channels
+* @param Channels: channels to be configed, as TSC_CHNEN defined
+* This parameter:bit[0:23] used,bit[24:31] must be 0
+* bitx: TSC channel x
+* @param base: base value of threshold, 0-MAX_TSC_THRESHOLD_BASE
+* @param delta: delta value of threshold,0-MAX_TSC_THRESHOLD_DELRA
+* @return: None
+*/
+TSC_ErrorTypeDef TSC_ConfigThreshold( uint32_t Channels, uint32_t base, uint32_t delta)
+{
+ uint32_t i, chn,timeout;
+ assert_param(IS_TSC_CHN(Channels));
+ assert_param(IS_TSC_THRESHOLD_BASE(base));
+ assert_param(IS_TSC_THRESHOLD_DELTA(delta));
+
+ /*Check the base and delta value*/
+ if ( (base>MAX_TSC_THRESHOLD_BASE)||(delta>MAX_TSC_THRESHOLD_DELTA))
+ return TSC_ERROR_PARAMETER;
+
+ /* waiting tsc hw for idle status.*/
+ timeout = 0;
+ do
+ {
+ __TSC_HW_DISABLE();
+
+ if (++timeout > TSC_TIMEOUT)
+ return TSC_ERROR_HW_MODE;
+ }while (__TSC_GET_HW_MODE());
+
+ /*Mask invalie bits*/
+ chn = Channels & TSC_CHNEN_CHN_SELx_Msk;
+
+ /* Set the base and delta for each channnel one by one*/
+ for (i = 0; iTHRHD[i] = (base<>= 1;
+ }
+
+ return TSC_ERROR_OK;
+}
+
+
+/**
+* @brief Get parameters of one channel.
+* @param ChnCfg: Pointer of TSC_ChnCfg structure.
+* @param ChannelNum: The channel number of which we want to get parameters,must be less then MAX_TSC_HW_CHN
+* @return: None
+*/
+TSC_ErrorTypeDef TSC_GetChannelCfg( TSC_ChnCfg* ChnCfg, uint32_t ChannelNum)
+{
+ uint32_t nReg,nPos;
+
+ assert_param(IS_TSC_CHN_NUMBER(ChannelNum));
+
+ /*Check channel number*/
+ if (!(IS_TSC_CHN_NUMBER(ChannelNum)))
+ return TSC_ERROR_PARAMETER;
+
+ /* Get the base and delta value for a channel*/
+ ChnCfg->TSC_Base = (TSC->THRHD[ChannelNum] & TSC_THRHDx_BASE_Msk) >> TSC_THRHDx_BASE_Pos;
+ ChnCfg->TSC_Delta = (TSC->THRHD[ChannelNum] & TSC_THRHDx_DELTA_Msk)>> TSC_THRHDx_DELTA_Pos;
+
+ /* Get the charge resistor type for a channel*/
+ nReg = ChannelNum>>3;
+ nPos = (ChannelNum & 0x7UL)*4;
+ ChnCfg->TSC_Resistor = (TSC->RESR[nReg] >> nPos) & TSC_RESRx_CHN_RESIST_Msk;
+
+ return TSC_ERROR_OK;
+}
+
+
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_usart.c b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_usart.c
new file mode 100644
index 0000000000..aac0fafa7b
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_usart.c
@@ -0,0 +1,956 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_usart.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_usart.h"
+#include "n32g43x_rcc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup USART
+ * @brief USART driver modules
+ * @{
+ */
+
+/** @addtogroup USART_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Private_Defines
+ * @{
+ */
+
+#define CTRL1_UEN_SET ((uint16_t)0x2000) /*!< USART Enable Mask */
+#define CTRL1_UEN_RESET ((uint16_t)0xDFFF) /*!< USART Disable Mask */
+
+#define CTRL1_WUM_MASK ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */
+
+#define CTRL1_RCVWU_SET ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */
+#define CTRL1_RCVWU_RESET ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */
+#define CTRL1_SDBRK_SET ((uint16_t)0x0001) /*!< USART Break Character send Mask */
+#define CTRL1_CLR_MASK ((uint16_t)0xE9F3) /*!< USART CTRL1 Mask */
+#define CTRL2_ADDR_MASK ((uint16_t)0xFFF0) /*!< USART address Mask */
+
+#define CTRL2_LINMEN_SET ((uint16_t)0x4000) /*!< USART LIN Enable Mask */
+#define CTRL2_LINMEN_RESET ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */
+
+#define CTRL2_LINBDL_MASK ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */
+#define CTRL2_STPB_CLR_MASK ((uint16_t)0xCFFF) /*!< USART CTRL2 STOP Bits Mask */
+#define CTRL2_CLOCK_CLR_MASK ((uint16_t)0xF0FF) /*!< USART CTRL2 Clock Mask */
+
+#define CTRL3_SCMEN_SET ((uint16_t)0x0020) /*!< USART SC Enable Mask */
+#define CTRL3_SCMEN_RESET ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */
+
+#define CTRL3_SCNACK_SET ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */
+#define CTRL3_SCNACK_RESET ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */
+
+#define CTRL3_HDMEN_SET ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */
+#define CTRL3_HDMEN_RESET ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */
+
+#define CTRL3_IRDALP_MASK ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */
+#define CTRL3_CLR_MASK ((uint16_t)0xFCFF) /*!< USART CTRL3 Mask */
+
+#define CTRL3_IRDAMEN_SET ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */
+#define CTRL3_IRDAMEN_RESET ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */
+#define GTP_LSB_MASK ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */
+#define GTP_MSB_MASK ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */
+#define INT_MASK ((uint16_t)0x001F) /*!< USART Interrupt Mask */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the USARTx peripheral registers to their default reset values.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ */
+void USART_DeInit(USART_Module* USARTx)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ if (USARTx == USART1)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_USART1, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_USART1, DISABLE);
+ }
+ else if (USARTx == USART2)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART2, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART2, DISABLE);
+ }
+ else if (USARTx == USART3)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART3, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART3, DISABLE);
+ }
+ else if (USARTx == UART4)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART4, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART4, DISABLE);
+ }
+ else if (USARTx == UART5)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART5, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART5, DISABLE);
+ }
+}
+
+/**
+ * @brief Initializes the USARTx peripheral according to the specified
+ * parameters in the USART_InitStruct .
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_InitStruct pointer to a USART_InitType structure
+ * that contains the configuration information for the specified USART
+ * peripheral.
+ */
+void USART_Init(USART_Module* USARTx, USART_InitType* USART_InitStruct)
+{
+ uint32_t tmpregister = 0x00, apbclock = 0x00;
+ uint32_t integerdivider = 0x00;
+ uint32_t fractionaldivider = 0x00;
+ uint32_t usartxbase = 0;
+ RCC_ClocksType RCC_ClocksStatus;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_BAUDRATE(USART_InitStruct->BaudRate));
+ assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->WordLength));
+ assert_param(IS_USART_STOPBITS(USART_InitStruct->StopBits));
+ assert_param(IS_USART_PARITY(USART_InitStruct->Parity));
+ assert_param(IS_USART_MODE(USART_InitStruct->Mode));
+ assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->HardwareFlowControl));
+ /* The hardware flow control is available only for USART1, USART2 and USART3 */
+ if (USART_InitStruct->HardwareFlowControl != USART_HFCTRL_NONE)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ usartxbase = (uint32_t)USARTx;
+
+ /*---------------------------- USART CTRL2 Configuration -----------------------*/
+ tmpregister = USARTx->CTRL2;
+ /* Clear STOP[13:12] bits */
+ tmpregister &= CTRL2_STPB_CLR_MASK;
+ /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
+ /* Set STOP[13:12] bits according to StopBits value */
+ tmpregister |= (uint32_t)USART_InitStruct->StopBits;
+
+ /* Write to USART CTRL2 */
+ USARTx->CTRL2 = (uint16_t)tmpregister;
+
+ /*---------------------------- USART CTRL1 Configuration -----------------------*/
+ tmpregister = USARTx->CTRL1;
+ /* Clear M, PCE, PS, TE and RE bits */
+ tmpregister &= CTRL1_CLR_MASK;
+ /* Configure the USART Word Length, Parity and mode ----------------------- */
+ /* Set the M bits according to WordLength value */
+ /* Set PCE and PS bits according to Parity value */
+ /* Set TE and RE bits according to Mode value */
+ tmpregister |= (uint32_t)USART_InitStruct->WordLength | USART_InitStruct->Parity | USART_InitStruct->Mode;
+ /* Write to USART CTRL1 */
+ USARTx->CTRL1 = (uint16_t)tmpregister;
+
+ /*---------------------------- USART CTRL3 Configuration -----------------------*/
+ tmpregister = USARTx->CTRL3;
+ /* Clear CTSE and RTSE bits */
+ tmpregister &= CTRL3_CLR_MASK;
+ /* Configure the USART HFC -------------------------------------------------*/
+ /* Set CTSE and RTSE bits according to HardwareFlowControl value */
+ tmpregister |= USART_InitStruct->HardwareFlowControl;
+ /* Write to USART CTRL3 */
+ USARTx->CTRL3 = (uint16_t)tmpregister;
+
+ /*---------------------------- USART PBC Configuration -----------------------*/
+ /* Configure the USART Baud Rate -------------------------------------------*/
+ RCC_GetClocksFreqValue(&RCC_ClocksStatus);
+ if ((usartxbase == USART1_BASE) || (usartxbase == UART4_BASE) || (usartxbase == UART5_BASE))
+ {
+ apbclock = RCC_ClocksStatus.Pclk2Freq;
+ }
+ else
+ {
+ apbclock = RCC_ClocksStatus.Pclk1Freq;
+ }
+
+ /* Determine the integer part */
+ integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->BaudRate)));
+ tmpregister = (integerdivider / 100) << 4;
+
+ /* Determine the fractional part */
+ fractionaldivider = integerdivider - (100 * (tmpregister >> 4));
+
+ /* Implement the fractional part in the register */
+ tmpregister |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
+
+ /* Write to USART PBC */
+ USARTx->BRCF = (uint16_t)tmpregister;
+}
+
+/**
+ * @brief Fills each USART_InitStruct member with its default value.
+ * @param USART_InitStruct pointer to a USART_InitType structure
+ * which will be initialized.
+ */
+void USART_StructInit(USART_InitType* USART_InitStruct)
+{
+ /* USART_InitStruct members default value */
+ USART_InitStruct->BaudRate = 9600;
+ USART_InitStruct->WordLength = USART_WL_8B;
+ USART_InitStruct->StopBits = USART_STPB_1;
+ USART_InitStruct->Parity = USART_PE_NO;
+ USART_InitStruct->Mode = USART_MODE_RX | USART_MODE_TX;
+ USART_InitStruct->HardwareFlowControl = USART_HFCTRL_NONE;
+}
+
+/**
+ * @brief Initializes the USARTx peripheral Clock according to the
+ * specified parameters in the USART_ClockInitStruct .
+ * @param USARTx where x can be 1, 2, 3 to select the USART peripheral.
+ * @param USART_ClockInitStruct pointer to a USART_ClockInitType
+ * structure that contains the configuration information for the specified
+ * USART peripheral.
+ * @note The Smart Card and Synchronous modes are not available for UART4/UART5.
+ */
+void USART_ClockInit(USART_Module* USARTx, USART_ClockInitType* USART_ClockInitStruct)
+{
+ uint32_t tmpregister = 0x00;
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ assert_param(IS_USART_CLOCK(USART_ClockInitStruct->Clock));
+ assert_param(IS_USART_CPOL(USART_ClockInitStruct->Polarity));
+ assert_param(IS_USART_CPHA(USART_ClockInitStruct->Phase));
+ assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->LastBit));
+
+ /*---------------------------- USART CTRL2 Configuration -----------------------*/
+ tmpregister = USARTx->CTRL2;
+ /* Clear CLKEN, CPOL, CPHA and LBCL bits */
+ tmpregister &= CTRL2_CLOCK_CLR_MASK;
+ /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/
+ /* Set CLKEN bit according to Clock value */
+ /* Set CPOL bit according to Polarity value */
+ /* Set CPHA bit according to Phase value */
+ /* Set LBCL bit according to LastBit value */
+ tmpregister |= (uint32_t)USART_ClockInitStruct->Clock | USART_ClockInitStruct->Polarity
+ | USART_ClockInitStruct->Phase | USART_ClockInitStruct->LastBit;
+ /* Write to USART CTRL2 */
+ USARTx->CTRL2 = (uint16_t)tmpregister;
+}
+
+/**
+ * @brief Fills each USART_ClockInitStruct member with its default value.
+ * @param USART_ClockInitStruct pointer to a USART_ClockInitType
+ * structure which will be initialized.
+ */
+void USART_ClockStructInit(USART_ClockInitType* USART_ClockInitStruct)
+{
+ /* USART_ClockInitStruct members default value */
+ USART_ClockInitStruct->Clock = USART_CLK_DISABLE;
+ USART_ClockInitStruct->Polarity = USART_CLKPOL_LOW;
+ USART_ClockInitStruct->Phase = USART_CLKPHA_1EDGE;
+ USART_ClockInitStruct->LastBit = USART_CLKLB_DISABLE;
+}
+
+/**
+ * @brief Enables or disables the specified USART peripheral.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param Cmd new state of the USARTx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void USART_Enable(USART_Module* USARTx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected USART by setting the UE bit in the CTRL1 register */
+ USARTx->CTRL1 |= CTRL1_UEN_SET;
+ }
+ else
+ {
+ /* Disable the selected USART by clearing the UE bit in the CTRL1 register */
+ USARTx->CTRL1 &= CTRL1_UEN_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified USART interrupts.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_INT specifies the USART interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg USART_INT_CTSF CTS change interrupt (not available for UART4 and UART5)
+ * @arg USART_INT_LINBD LIN Break detection interrupt
+ * @arg USART_INT_TXDE Transmit Data Register empty interrupt
+ * @arg USART_INT_TXC Transmission complete interrupt
+ * @arg USART_INT_RXDNE Receive Data register not empty interrupt
+ * @arg USART_INT_IDLEF Idle line detection interrupt
+ * @arg USART_INT_PEF Parity Error interrupt
+ * @arg USART_INT_ERRF Error interrupt(Frame error, noise error, overrun error)
+ * @param Cmd new state of the specified USARTx interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void USART_ConfigInt(USART_Module* USARTx, uint16_t USART_INT, FunctionalState Cmd)
+{
+ uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
+ uint32_t usartxbase = 0x00;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_CFG_INT(USART_INT));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ /* The CTS interrupt is not available for UART4/UART5 */
+ if (USART_INT == USART_INT_CTSF)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ usartxbase = (uint32_t)USARTx;
+
+ /* Get the USART register index */
+ usartreg = (((uint8_t)USART_INT) >> 0x05);
+
+ /* Get the interrupt position */
+ itpos = USART_INT & INT_MASK;
+ itmask = (((uint32_t)0x01) << itpos);
+
+ if (usartreg == 0x01) /* The IT is in CTRL1 register */
+ {
+ usartxbase += 0x0C;
+ }
+ else if (usartreg == 0x02) /* The IT is in CTRL2 register */
+ {
+ usartxbase += 0x10;
+ }
+ else /* The IT is in CTRL3 register */
+ {
+ usartxbase += 0x14;
+ }
+ if (Cmd != DISABLE)
+ {
+ *(__IO uint32_t*)usartxbase |= itmask;
+ }
+ else
+ {
+ *(__IO uint32_t*)usartxbase &= ~itmask;
+ }
+}
+
+/**
+ * @brief Enables or disables the USART's DMA interface.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_DMAReq specifies the DMA request.
+ * This parameter can be any combination of the following values:
+ * @arg USART_DMAREQ_TX USART DMA transmit request
+ * @arg USART_DMAREQ_RX USART DMA receive request
+ * @param Cmd new state of the DMA Request sources.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void USART_EnableDMA(USART_Module* USARTx, uint16_t USART_DMAReq, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_DMAREQ(USART_DMAReq));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the DMA transfer for selected requests by setting the DMAT and/or
+ DADDR bits in the USART CTRL3 register */
+ USARTx->CTRL3 |= USART_DMAReq;
+ }
+ else
+ {
+ /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
+ DADDR bits in the USART CTRL3 register */
+ USARTx->CTRL3 &= (uint16_t)~USART_DMAReq;
+ }
+}
+
+/**
+ * @brief Sets the address of the USART node.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_Addr Indicates the address of the USART node.
+ */
+void USART_SetAddr(USART_Module* USARTx, uint8_t USART_Addr)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_ADDRESS(USART_Addr));
+
+ /* Clear the USART address */
+ USARTx->CTRL2 &= CTRL2_ADDR_MASK;
+ /* Set the USART address node */
+ USARTx->CTRL2 |= USART_Addr;
+}
+
+/**
+ * @brief Selects the USART WakeUp method.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_WakeUpMode specifies the USART wakeup method.
+ * This parameter can be one of the following values:
+ * @arg USART_WUM_IDLELINE WakeUp by an idle line detection
+ * @arg USART_WUM_ADDRMASK WakeUp by an address mark
+ */
+void USART_ConfigWakeUpMode(USART_Module* USARTx, uint16_t USART_WakeUpMode)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_WAKEUP(USART_WakeUpMode));
+
+ USARTx->CTRL1 &= CTRL1_WUM_MASK;
+ USARTx->CTRL1 |= USART_WakeUpMode;
+}
+
+/**
+ * @brief Determines if the USART is in mute mode or not.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param Cmd new state of the USART mute mode.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void USART_EnableRcvWakeUp(USART_Module* USARTx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the USART mute mode by setting the RWU bit in the CTRL1 register */
+ USARTx->CTRL1 |= CTRL1_RCVWU_SET;
+ }
+ else
+ {
+ /* Disable the USART mute mode by clearing the RWU bit in the CTRL1 register */
+ USARTx->CTRL1 &= CTRL1_RCVWU_RESET;
+ }
+}
+
+/**
+ * @brief Sets the USART LIN Break detection length.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_LINBreakDetectLength specifies the LIN break detection length.
+ * This parameter can be one of the following values:
+ * @arg USART_LINBDL_10B 10-bit break detection
+ * @arg USART_LINBDL_11B 11-bit break detection
+ */
+void USART_ConfigLINBreakDetectLength(USART_Module* USARTx, uint16_t USART_LINBreakDetectLength)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
+
+ USARTx->CTRL2 &= CTRL2_LINBDL_MASK;
+ USARTx->CTRL2 |= USART_LINBreakDetectLength;
+}
+
+/**
+ * @brief Enables or disables the USART's LIN mode.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param Cmd new state of the USART LIN mode.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void USART_EnableLIN(USART_Module* USARTx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the LIN mode by setting the LINEN bit in the CTRL2 register */
+ USARTx->CTRL2 |= CTRL2_LINMEN_SET;
+ }
+ else
+ {
+ /* Disable the LIN mode by clearing the LINEN bit in the CTRL2 register */
+ USARTx->CTRL2 &= CTRL2_LINMEN_RESET;
+ }
+}
+
+/**
+ * @brief Transmits single data through the USARTx peripheral.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param Data the data to transmit.
+ */
+void USART_SendData(USART_Module* USARTx, uint16_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_DATA(Data));
+
+ /* Transmit Data */
+ USARTx->DAT = (Data & (uint16_t)0x01FF);
+}
+
+/**
+ * @brief Returns the most recent received data by the USARTx peripheral.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @return The received data.
+ */
+uint16_t USART_ReceiveData(USART_Module* USARTx)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ /* Receive Data */
+ return (uint16_t)(USARTx->DAT & (uint16_t)0x01FF);
+}
+
+/**
+ * @brief Transmits break characters.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ */
+void USART_SendBreak(USART_Module* USARTx)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ /* Send break characters */
+ USARTx->CTRL1 |= CTRL1_SDBRK_SET;
+}
+
+/**
+ * @brief Sets the specified USART guard time.
+ * @param USARTx where x can be 1, 2 or 3 to select the USART peripheral.
+ * @param USART_GuardTime specifies the guard time.
+ * @note The guard time bits are not available for UART4/UART5.
+ */
+void USART_SetGuardTime(USART_Module* USARTx, uint8_t USART_GuardTime)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+
+ /* Clear the USART Guard time */
+ USARTx->GTP &= GTP_LSB_MASK;
+ /* Set the USART guard time */
+ USARTx->GTP |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
+}
+
+/**
+ * @brief Sets the system clock prescaler.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_Prescaler specifies the prescaler clock.
+ * @note The function is used for IrDA mode with UART4 and UART5.
+ */
+void USART_SetPrescaler(USART_Module* USARTx, uint8_t USART_Prescaler)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ /* Clear the USART prescaler */
+ USARTx->GTP &= GTP_MSB_MASK;
+ /* Set the USART prescaler */
+ USARTx->GTP |= USART_Prescaler;
+}
+
+/**
+ * @brief Enables or disables the USART's Smart Card mode.
+ * @param USARTx where x can be 1, 2 or 3 to select the USART peripheral.
+ * @param Cmd new state of the Smart Card mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note The Smart Card mode is not available for UART4/UART5.
+ */
+void USART_EnableSmartCard(USART_Module* USARTx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the SC mode by setting the SCEN bit in the CTRL3 register */
+ USARTx->CTRL3 |= CTRL3_SCMEN_SET;
+ }
+ else
+ {
+ /* Disable the SC mode by clearing the SCEN bit in the CTRL3 register */
+ USARTx->CTRL3 &= CTRL3_SCMEN_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables NACK transmission.
+ * @param USARTx where x can be 1, 2 or 3 to select the USART peripheral.
+ * @param Cmd new state of the NACK transmission.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note The Smart Card mode is not available for UART4/UART5.
+ */
+void USART_SetSmartCardNACK(USART_Module* USARTx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the NACK transmission by setting the NACK bit in the CTRL3 register */
+ USARTx->CTRL3 |= CTRL3_SCNACK_SET;
+ }
+ else
+ {
+ /* Disable the NACK transmission by clearing the NACK bit in the CTRL3 register */
+ USARTx->CTRL3 &= CTRL3_SCNACK_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the USART's Half Duplex communication.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param Cmd new state of the USART Communication.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void USART_EnableHalfDuplex(USART_Module* USARTx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CTRL3 register */
+ USARTx->CTRL3 |= CTRL3_HDMEN_SET;
+ }
+ else
+ {
+ /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CTRL3 register */
+ USARTx->CTRL3 &= CTRL3_HDMEN_RESET;
+ }
+}
+
+/**
+ * @brief Configures the USART's IrDA interface.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_IrDAMode specifies the IrDA mode.
+ * This parameter can be one of the following values:
+ * @arg USART_IRDAMODE_LOWPPWER
+ * @arg USART_IRDAMODE_NORMAL
+ */
+void USART_ConfigIrDAMode(USART_Module* USARTx, uint16_t USART_IrDAMode)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
+
+ USARTx->CTRL3 &= CTRL3_IRDALP_MASK;
+ USARTx->CTRL3 |= USART_IrDAMode;
+}
+
+/**
+ * @brief Enables or disables the USART's IrDA interface.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param Cmd new state of the IrDA mode.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void USART_EnableIrDA(USART_Module* USARTx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the IrDA mode by setting the IREN bit in the CTRL3 register */
+ USARTx->CTRL3 |= CTRL3_IRDAMEN_SET;
+ }
+ else
+ {
+ /* Disable the IrDA mode by clearing the IREN bit in the CTRL3 register */
+ USARTx->CTRL3 &= CTRL3_IRDAMEN_RESET;
+ }
+}
+
+/**
+ * @brief Checks whether the specified USART flag is set or not.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_FLAG specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg USART_FLAG_CTSF CTS Change flag (not available for UART4 and UART5)
+ * @arg USART_FLAG_LINBD LIN Break detection flag
+ * @arg USART_FLAG_TXDE Transmit data register empty flag
+ * @arg USART_FLAG_TXC Transmission Complete flag
+ * @arg USART_FLAG_RXDNE Receive data register not empty flag
+ * @arg USART_FLAG_IDLEF Idle Line detection flag
+ * @arg USART_FLAG_OREF OverRun Error flag
+ * @arg USART_FLAG_NEF Noise Error flag
+ * @arg USART_FLAG_FEF Framing Error flag
+ * @arg USART_FLAG_PEF Parity Error flag
+ * @return The new state of USART_FLAG (SET or RESET).
+ */
+FlagStatus USART_GetFlagStatus(USART_Module* USARTx, uint16_t USART_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_FLAG(USART_FLAG));
+ /* The CTS flag is not available for UART4/UART5 */
+ if (USART_FLAG == USART_FLAG_CTSF)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ if ((USARTx->STS & USART_FLAG) != (uint16_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the USARTx's pending flags.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_FLAG specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg USART_FLAG_CTSF CTS Change flag (not available for UART4 and UART5).
+ * @arg USART_FLAG_LINBD LIN Break detection flag.
+ * @arg USART_FLAG_TXC Transmission Complete flag.
+ * @arg USART_FLAG_RXDNE Receive data register not empty flag.
+ *
+ * @note
+ * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ * error) and IDLE (Idle line detected) flags are cleared by software
+ * sequence: a read operation to USART_SR register (USART_GetFlagStatus())
+ * followed by a read operation to USART_DR register (USART_ReceiveData()).
+ * - RXNE flag can be also cleared by a read to the USART_DR register
+ * (USART_ReceiveData()).
+ * - TC flag can be also cleared by software sequence: a read operation to
+ * USART_SR register (USART_GetFlagStatus()) followed by a write operation
+ * to USART_DR register (USART_SendData()).
+ * - TXE flag is cleared only by a write to the USART_DR register
+ * (USART_SendData()).
+ */
+void USART_ClrFlag(USART_Module* USARTx, uint16_t USART_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
+ /* The CTS flag is not available for UART4/UART5 */
+ if ((USART_FLAG & USART_FLAG_CTSF) == USART_FLAG_CTSF)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ USARTx->STS = (uint16_t)~USART_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified USART interrupt has occurred or not.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_INT specifies the USART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg USART_INT_CTSF CTS change interrupt (not available for UART4 and UART5)
+ * @arg USART_INT_LINBD LIN Break detection interrupt
+ * @arg USART_INT_TXDE Tansmit Data Register empty interrupt
+ * @arg USART_INT_TXC Transmission complete interrupt
+ * @arg USART_INT_RXDNE Receive Data register not empty interrupt
+ * @arg USART_INT_IDLEF Idle line detection interrupt
+ * @arg USART_INT_OREF OverRun Error interrupt
+ * @arg USART_INT_NEF Noise Error interrupt
+ * @arg USART_INT_FEF Framing Error interrupt
+ * @arg USART_INT_PEF Parity Error interrupt
+ * @return The new state of USART_INT (SET or RESET).
+ */
+INTStatus USART_GetIntStatus(USART_Module* USARTx, uint16_t USART_INT)
+{
+ uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
+ INTStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_GET_INT(USART_INT));
+ /* The CTS interrupt is not available for UART4/UART5 */
+ if (USART_INT == USART_INT_CTSF)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ /* Get the USART register index */
+ usartreg = (((uint8_t)USART_INT) >> 0x05);
+ /* Get the interrupt position */
+ itmask = USART_INT & INT_MASK;
+ itmask = (uint32_t)0x01 << itmask;
+
+ if (usartreg == 0x01) /* The IT is in CTRL1 register */
+ {
+ itmask &= USARTx->CTRL1;
+ }
+ else if (usartreg == 0x02) /* The IT is in CTRL2 register */
+ {
+ itmask &= USARTx->CTRL2;
+ }
+ else /* The IT is in CTRL3 register */
+ {
+ itmask &= USARTx->CTRL3;
+ }
+
+ bitpos = USART_INT >> 0x08;
+ bitpos = (uint32_t)0x01 << bitpos;
+ bitpos &= USARTx->STS;
+ if ((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the USARTx's interrupt pending bits.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_INT specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg USART_INT_CTSF CTS change interrupt (not available for UART4 and UART5)
+ * @arg USART_INT_LINBD LIN Break detection interrupt
+ * @arg USART_INT_TXC Transmission complete interrupt.
+ * @arg USART_INT_RXDNE Receive Data register not empty interrupt.
+ *
+ * @note
+ * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ * error) and IDLE (Idle line detected) pending bits are cleared by
+ * software sequence: a read operation to USART_SR register
+ * (USART_GetIntStatus()) followed by a read operation to USART_DR register
+ * (USART_ReceiveData()).
+ * - RXNE pending bit can be also cleared by a read to the USART_DR register
+ * (USART_ReceiveData()).
+ * - TC pending bit can be also cleared by software sequence: a read
+ * operation to USART_SR register (USART_GetIntStatus()) followed by a write
+ * operation to USART_DR register (USART_SendData()).
+ * - TXE pending bit is cleared only by a write to the USART_DR register
+ * (USART_SendData()).
+ */
+void USART_ClrIntPendingBit(USART_Module* USARTx, uint16_t USART_INT)
+{
+ uint16_t bitpos = 0x00, itmask = 0x00;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_CLR_INT(USART_INT));
+ /* The CTS interrupt is not available for UART4/UART5 */
+ if (USART_INT == USART_INT_CTSF)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ bitpos = USART_INT >> 0x08;
+ itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
+ USARTx->STS = (uint16_t)~itmask;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_wwdg.c b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_wwdg.c
new file mode 100644
index 0000000000..11e8495139
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_wwdg.c
@@ -0,0 +1,223 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_wwdg.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_wwdg.h"
+#include "n32g43x_rcc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup WWDG
+ * @brief WWDG driver modules
+ * @{
+ */
+
+/** @addtogroup WWDG_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Private_Defines
+ * @{
+ */
+
+/* ----------- WWDG registers bit address in the alias region ----------- */
+#define WWDG_OFFADDR (WWDG_BASE - PERIPH_BASE)
+
+/* Alias word address of EWI bit */
+#define CFG_OFFADDR (WWDG_OFFADDR + 0x04)
+#define EWINT_BIT 0x09
+#define CFG_EWINT_BB (PERIPH_BB_BASE + (CFG_OFFADDR * 32) + (EWINT_BIT * 4))
+
+/* --------------------- WWDG registers bit mask ------------------------ */
+
+/* CTRL register bit mask */
+#define CTRL_ACTB_SET ((uint32_t)0x00000080)
+
+/* CFG register bit mask */
+#define CFG_TIMERB_MASK ((uint32_t)0xFFFFFE7F)
+#define CFG_W_MASK ((uint32_t)0xFFFFFF80)
+#define BIT_MASK ((uint8_t)0x7F)
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the WWDG peripheral registers to their default reset values.
+ */
+void WWDG_DeInit(void)
+{
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_WWDG, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_WWDG, DISABLE);
+}
+
+/**
+ * @brief Sets the WWDG Prescaler.
+ * @param WWDG_Prescaler specifies the WWDG Prescaler.
+ * This parameter can be one of the following values:
+ * @arg WWDG_PRESCALER_DIV1 WWDG counter clock = (PCLK1/4096)/1
+ * @arg WWDG_PRESCALER_DIV2 WWDG counter clock = (PCLK1/4096)/2
+ * @arg WWDG_PRESCALER_DIV4 WWDG counter clock = (PCLK1/4096)/4
+ * @arg WWDG_PRESCALER_DIV8 WWDG counter clock = (PCLK1/4096)/8
+ */
+void WWDG_SetPrescalerDiv(uint32_t WWDG_Prescaler)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_WWDG_PRESCALER_DIV(WWDG_Prescaler));
+ /* Clear WDGTB[1:0] bits */
+ tmpregister = WWDG->CFG & CFG_TIMERB_MASK;
+ /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
+ tmpregister |= WWDG_Prescaler;
+ /* Store the new value */
+ WWDG->CFG = tmpregister;
+}
+
+/**
+ * @brief Sets the WWDG window value.
+ * @param WindowValue specifies the window value to be compared to the downcounter.
+ * This parameter value must be lower than 0x80.
+ */
+void WWDG_SetWValue(uint8_t WindowValue)
+{
+ __IO uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_WWDG_WVALUE(WindowValue));
+ /* Clear W[6:0] bits */
+
+ tmpregister = WWDG->CFG & CFG_W_MASK;
+
+ /* Set W[6:0] bits according to WindowValue value */
+ tmpregister |= WindowValue & (uint32_t)BIT_MASK;
+
+ /* Store the new value */
+ WWDG->CFG = tmpregister;
+}
+
+/**
+ * @brief Enables the WWDG Early Wakeup interrupt(EWI).
+ */
+void WWDG_EnableInt(void)
+{
+ *(__IO uint32_t*)CFG_EWINT_BB = (uint32_t)ENABLE;
+}
+
+/**
+ * @brief Sets the WWDG counter value.
+ * @param Counter specifies the watchdog counter value.
+ * This parameter must be a number between 0x40 and 0x7F.
+ */
+void WWDG_SetCnt(uint8_t Counter)
+{
+ /* Check the parameters */
+ assert_param(IS_WWDG_CNT(Counter));
+ /* Write to T[6:0] bits to configure the counter value, no need to do
+ a read-modify-write; writing a 0 to WDGA bit does nothing */
+ WWDG->CTRL = Counter & BIT_MASK;
+}
+
+/**
+ * @brief Enables WWDG and load the counter value.
+ * @param Counter specifies the watchdog counter value.
+ * This parameter must be a number between 0x40 and 0x7F.
+ */
+void WWDG_Enable(uint8_t Counter)
+{
+ /* Check the parameters */
+ assert_param(IS_WWDG_CNT(Counter));
+ WWDG->CTRL = CTRL_ACTB_SET | Counter;
+}
+
+/**
+ * @brief Checks whether the Early Wakeup interrupt flag is set or not.
+ * @return The new state of the Early Wakeup interrupt flag (SET or RESET)
+ */
+FlagStatus WWDG_GetEWINTF(void)
+{
+ return (FlagStatus)(WWDG->STS);
+}
+
+/**
+ * @brief Clears Early Wakeup interrupt flag.
+ */
+void WWDG_ClrEWINTF(void)
+{
+ WWDG->STS = (uint32_t)RESET;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_core.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_core.h
new file mode 100644
index 0000000000..4837d7ef40
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_core.h
@@ -0,0 +1,264 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_core.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_CORE_H__
+#define __USB_CORE_H__
+
+#include "n32g43x.h"
+
+/**
+ * @addtogroup N32G43X_USB_Driver
+ * @brief N32G43x USB low level driver
+ * @{
+ */
+
+typedef enum _CONTROL_STATE
+{
+ WaitSetup, /* 0 */
+ SettingUp, /* 1 */
+ InData, /* 2 */
+ OutData, /* 3 */
+ LastInData, /* 4 */
+ LastOutData, /* 5 */
+ WaitStatusIn, /* 6 */
+ WaitStatusOut, /* 7 */
+ Stalled, /* 8 */
+ Pause /* 9 */
+} USB_ControlState; /* The state machine states of a control pipe */
+
+typedef struct OneDescriptor
+{
+ uint8_t* Descriptor;
+ uint16_t Descriptor_Size;
+} USB_OneDescriptor, *PONE_DESCRIPTOR;
+/* All the request process routines return a value of this type
+ If the return value is not SUCCESS or NOT_READY,
+ the software will STALL the correspond endpoint */
+typedef enum _RESULT
+{
+ Success = 0, /* Process successfully */
+ Error,
+ UnSupport,
+ Not_Ready /* The process has not been finished, endpoint will be
+ NAK to further request */
+} USB_Result;
+
+/*-*-*-*-*-*-*-*-*-*-* Definitions for endpoint level -*-*-*-*-*-*-*-*-*-*-*-*/
+typedef struct _ENDPOINT_INFO
+{
+ /* When send data out of the device,
+ CopyData() is used to get data buffer 'Length' bytes data
+ if Length is 0,
+ CopyData() returns the total length of the data
+ if the request is not supported, returns 0
+ (NEW Feature )
+ if CopyData() returns -1, the calling routine should not proceed
+ further and will resume the SETUP process by the class device
+ if Length is not 0,
+ CopyData() returns a pointer to indicate the data location
+ Usb_wLength is the data remain to be sent,
+ Usb_wOffset is the Offset of original data
+ When receive data from the host,
+ CopyData() is used to get user data buffer which is capable
+ of Length bytes data to copy data from the endpoint buffer.
+ if Length is 0,
+ CopyData() returns the available data length,
+ if Length is not 0,
+ CopyData() returns user buffer address
+ Usb_rLength is the data remain to be received,
+ Usb_rPointer is the Offset of data buffer
+ */
+ uint16_t Usb_wLength;
+ uint16_t Usb_wOffset;
+ uint16_t PacketSize;
+ uint8_t* (*CopyData)(uint16_t Length);
+} USB_EndpointMess;
+
+/*-*-*-*-*-*-*-*-*-*-*-* Definitions for device level -*-*-*-*-*-*-*-*-*-*-*-*/
+
+typedef struct _DEVICE
+{
+ uint8_t TotalEndpoint; /* Number of endpoints that are used */
+ uint8_t TotalConfiguration; /* Number of configuration available */
+} USB_Device;
+
+typedef union
+{
+ uint16_t w;
+ struct BW
+ {
+ uint8_t bb1;
+ uint8_t bb0;
+ } bw;
+} uint16_t_uint8_t;
+
+typedef struct _DEVICE_INFO
+{
+ uint8_t bmRequestType; /* bmRequestType */
+ uint8_t bRequest; /* bRequest */
+ uint16_t_uint8_t wValues; /* wValue */
+ uint16_t_uint8_t wIndexs; /* wIndex */
+ uint16_t_uint8_t wLengths; /* wLength */
+
+ uint8_t CtrlState; /* of type USB_ControlState */
+ uint8_t CurrentFeature;
+ uint8_t CurrentConfiguration; /* Selected configuration */
+ uint8_t CurrentInterface; /* Selected interface of current configuration */
+ uint8_t CurrentAlternateSetting; /* Selected Alternate Setting of current
+ interface*/
+
+ USB_EndpointMess Ctrl_Info;
+} USB_DeviceMess;
+
+typedef struct _DEVICE_PROP
+{
+ void (*Init)(void); /* Initialize the device */
+ void (*Reset)(void); /* Reset routine of this device */
+
+ /* Device dependent process after the status stage */
+ void (*Process_Status_IN)(void);
+ void (*Process_Status_OUT)(void);
+
+ /* Procedure of process on setup stage of a class specified request with data stage */
+ /* All class specified requests with data stage are processed in Class_Data_Setup
+ Class_Data_Setup()
+ responses to check all special requests and fills USB_EndpointMess
+ according to the request
+ If IN tokens are expected, then wLength & wOffset will be filled
+ with the total transferring bytes and the starting position
+ If OUT tokens are expected, then rLength & rOffset will be filled
+ with the total expected bytes and the starting position in the buffer
+
+ If the request is valid, Class_Data_Setup returns SUCCESS, else UNSUPPORT
+
+ CAUTION:
+ Since GET_CONFIGURATION & GET_INTERFACE are highly related to
+ the individual classes, they will be checked and processed here.
+ */
+ USB_Result (*Class_Data_Setup)(uint8_t RequestNo);
+
+ /* Procedure of process on setup stage of a class specified request without data stage */
+ /* All class specified requests without data stage are processed in Class_NoData_Setup
+ Class_NoData_Setup
+ responses to check all special requests and perform the request
+
+ CAUTION:
+ Since SET_CONFIGURATION & SET_INTERFACE are highly related to
+ the individual classes, they will be checked and processed here.
+ */
+ USB_Result (*Class_NoData_Setup)(uint8_t RequestNo);
+
+ /*Class_Get_Interface_Setting
+ This function is used by the file usb_core.c to test if the selected Interface
+ and Alternate Setting (uint8_t Interface, uint8_t AlternateSetting) are supported by
+ the application.
+ This function is writing by user. It should return "SUCCESS" if the Interface
+ and Alternate Setting are supported by the application or "UNSUPPORT" if they
+ are not supported. */
+
+ USB_Result (*Class_Get_Interface_Setting)(uint8_t Interface, uint8_t AlternateSetting);
+
+ uint8_t* (*GetDeviceDescriptor)(uint16_t Length);
+ uint8_t* (*GetConfigDescriptor)(uint16_t Length);
+ uint8_t* (*GetStringDescriptor)(uint16_t Length);
+
+ /* This field is not used in current library version. It is kept only for
+ compatibility with previous versions */
+ void* RxEP_buffer;
+
+ uint8_t MaxPacketSize;
+
+} DEVICE_PROP;
+
+typedef struct _USER_STANDARD_REQUESTS
+{
+ void (*User_GetConfiguration)(void); /* Get Configuration */
+ void (*User_SetConfiguration)(void); /* Set Configuration */
+ void (*User_GetInterface)(void); /* Get Interface */
+ void (*User_SetInterface)(void); /* Set Interface */
+ void (*User_GetStatus)(void); /* Get Status */
+ void (*User_ClearFeature)(void); /* Clear Feature */
+ void (*User_SetEndPointFeature)(void); /* Set Endpoint Feature */
+ void (*User_SetDeviceFeature)(void); /* Set Device Feature */
+ void (*User_SetDeviceAddress)(void); /* Set Device Address */
+} USER_STANDARD_REQUESTS;
+
+#define Type_Recipient (pInformation->bmRequestType & (REQUEST_TYPE | RECIPIENT))
+
+#define Usb_rLength Usb_wLength
+#define Usb_rOffset Usb_wOffset
+
+#define USBwValue wValues.w
+#define USBwValue0 wValues.bw.bb0
+#define USBwValue1 wValues.bw.bb1
+#define USBwIndex wIndexs.w
+#define USBwIndex0 wIndexs.bw.bb0
+#define USBwIndex1 wIndexs.bw.bb1
+#define USBwLength wLengths.w
+#define USBwLength0 wLengths.bw.bb0
+#define USBwLength1 wLengths.bw.bb1
+
+uint8_t USB_ProcessSetup0(void);
+uint8_t USB_ProcessPost0(void);
+uint8_t USB_ProcessOut0(void);
+uint8_t USB_ProcessIn0(void);
+
+USB_Result Standard_SetEndPointFeature(void);
+USB_Result Standard_SetDeviceFeature(void);
+
+uint8_t* Standard_GetConfiguration(uint16_t Length);
+USB_Result Standard_SetConfiguration(void);
+uint8_t* Standard_GetInterface(uint16_t Length);
+USB_Result Standard_SetInterface(void);
+uint8_t* Standard_GetDescriptorData(uint16_t Length, PONE_DESCRIPTOR pDesc);
+
+uint8_t* Standard_GetStatus(uint16_t Length);
+USB_Result Standard_ClearFeature(void);
+void USB_SetDeviceAddress(uint8_t);
+void USB_ProcessNop(void);
+
+extern DEVICE_PROP Device_Property;
+extern USER_STANDARD_REQUESTS User_Standard_Requests;
+extern USB_Device Device_Table;
+extern USB_DeviceMess Device_Info;
+
+/* cells saving status during interrupt servicing */
+extern __IO uint16_t SaveRState;
+extern __IO uint16_t SaveTState;
+
+/**
+ * @}
+ */
+
+#endif /* __USB_CORE_H__ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_def.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_def.h
new file mode 100644
index 0000000000..56c2e3c6e6
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_def.h
@@ -0,0 +1,98 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_def.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_DEF_H__
+#define __USB_DEF_H__
+
+/**
+ * @addtogroup N32G43X_USB_Driver
+ * @{
+ */
+
+typedef enum _RECIPIENT_TYPE
+{
+ DEVICE_RECIPIENT, /* Recipient device */
+ INTERFACE_RECIPIENT, /* Recipient interface */
+ ENDPOINT_RECIPIENT, /* Recipient endpoint */
+ OTHER_RECIPIENT
+} RECIPIENT_TYPE;
+
+typedef enum _STANDARD_REQUESTS
+{
+ GET_STATUS = 0,
+ CLR_FEATURE,
+ RESERVED1,
+ SET_FEATURE,
+ RESERVED2,
+ SET_ADDRESS,
+ GET_DESCRIPTOR,
+ SET_DESCRIPTOR,
+ GET_CONFIGURATION,
+ SET_CONFIGURATION,
+ GET_INTERFACE,
+ SET_INTERFACE,
+ TOTAL_SREQUEST, /* Total number of Standard request */
+ SYNCH_FRAME = 12
+} STANDARD_REQUESTS;
+
+/* Definition of "USBwValue" */
+typedef enum _DESCRIPTOR_TYPE
+{
+ DEVICE_DESCRIPTOR = 1,
+ CONFIG_DESCRIPTOR,
+ STRING_DESCRIPTOR,
+ INTERFACE_DESCRIPTOR,
+ ENDPOINT_DESCRIPTOR
+} DESCRIPTOR_TYPE;
+
+/* Feature selector of a SET_FEATURE or CLR_FEATURE */
+typedef enum _FEATURE_SELECTOR
+{
+ ENDPOINT_STALL,
+ DEVICE_REMOTE_WAKEUP
+} FEATURE_SELECTOR;
+
+/* Definition of "bmRequestType" */
+#define REQUEST_TYPE 0x60 /* Mask to get request type */
+#define STANDARD_REQUEST 0x00 /* Standard request */
+#define CLASS_REQUEST 0x20 /* Class request */
+#define VENDOR_REQUEST 0x40 /* Vendor request */
+
+#define RECIPIENT 0x1F /* Mask to get recipient */
+
+/**
+ * @}
+ */
+
+#endif /* __USB_DEF_H__ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_init.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_init.h
new file mode 100644
index 0000000000..bb607ae383
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_init.h
@@ -0,0 +1,71 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_init.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_INIT_H__
+#define __USB_INIT_H__
+
+#include "n32g43x.h"
+#include "usb_core.h"
+
+/**
+ * @addtogroup N32G43X_USB_Driver
+ * @{
+ */
+
+void USB_Init(void);
+
+/* The number of current endpoint, it will be used to specify an endpoint */
+extern uint8_t EPindex;
+/* The number of current device, it is an index to the Device_Table */
+/*extern uint8_t Device_no; */
+/* Points to the USB_DeviceMess structure of current device */
+/* The purpose of this register is to speed up the execution */
+extern USB_DeviceMess* pInformation;
+/* Points to the DEVICE_PROP structure of current device */
+/* The purpose of this register is to speed up the execution */
+extern DEVICE_PROP* pProperty;
+/* Temporary save the state of Rx & Tx status. */
+/* Whenever the Rx or Tx state is changed, its value is saved */
+/* in this variable first and will be set to the EPRB or EPRA */
+/* at the end of interrupt process */
+extern USER_STANDARD_REQUESTS* pUser_Standard_Requests;
+
+extern uint16_t SaveState;
+extern uint16_t wInterrupt_Mask;
+
+/**
+ * @}
+ */
+
+#endif /* __USB_INIT_H__ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_int.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_int.h
new file mode 100644
index 0000000000..ddebc2396c
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_int.h
@@ -0,0 +1,50 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_int.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_INT_H__
+#define __USB_INT_H__
+
+/**
+ * @addtogroup N32G43X_USB_Driver
+ * @{
+ */
+
+void USB_CorrectTransferLp(void);
+void USB_CorrectTransferHp(void);
+
+/**
+ * @}
+ */
+
+#endif /* __USB_INT_H__ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_lib.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_lib.h
new file mode 100644
index 0000000000..0b1a044c89
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_lib.h
@@ -0,0 +1,47 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_lib.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_LIB_H__
+#define __USB_LIB_H__
+
+#include "usb_type.h"
+#include "usb_regs.h"
+#include "usb_def.h"
+#include "usb_core.h"
+#include "usb_init.h"
+#include "usb_sil.h"
+#include "usb_mem.h"
+#include "usb_int.h"
+
+#endif /* __USB_LIB_H__ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_mem.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_mem.h
new file mode 100644
index 0000000000..86a0186543
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_mem.h
@@ -0,0 +1,52 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_mem.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_MEM_H__
+#define __USB_MEM_H__
+
+#include "n32g43x.h"
+
+/**
+ * @addtogroup N32G43X_USB_Driver
+ * @{
+ */
+
+void USB_CopyUserToPMABuf(uint8_t* pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+void USB_CopyPMAToUserBuf(uint8_t* pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+
+/**
+ * @}
+ */
+
+#endif /*__USB_MEM_H__*/
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_regs.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_regs.h
new file mode 100644
index 0000000000..68562388b8
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_regs.h
@@ -0,0 +1,716 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_regs.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_REGS_H__
+#define __USB_REGS_H__
+
+#include "n32g43x.h"
+
+/**
+ * @addtogroup N32G43X_USB_Driver
+ * @{
+ */
+
+typedef enum _EP_DBUF_DIR
+{
+ /* double buffered endpoint direction */
+ EP_DBUF_ERR,
+ EP_DBUF_OUT,
+ EP_DBUF_IN
+} EP_DBUF_DIR;
+
+/* endpoint buffer number */
+enum EP_BUF_NUM
+{
+ EP_NOBUF,
+ EP_BUF0,
+ EP_BUF1
+};
+
+#define RegBase (0x40005C00L) /* USB_IP Peripheral Registers base address */
+#define PMAAddr (0x40006000L) /* USB_IP Packet Memory Area base address */
+
+/******************************************************************************/
+/* Special registers */
+/******************************************************************************/
+/* Pull up controller register */
+#define DP_CTRL ((__IO unsigned*)(0x40001824))
+
+#define _ClrDPCtrl() (*DP_CTRL = (*DP_CTRL) & (~0x8000000));
+#define _EnPortPullup() (*DP_CTRL = (*DP_CTRL) | 0x02000000);
+#define _DisPortPullup() (*DP_CTRL = (*DP_CTRL) & 0xFDFFFFFF);
+
+/******************************************************************************/
+/* General registers */
+/******************************************************************************/
+
+/* Control register */
+#define USB_CTRL ((__IO unsigned*)(RegBase + 0x40))
+/* Interrupt status register */
+#define USB_STS ((__IO unsigned*)(RegBase + 0x44))
+/* Frame number register */
+#define USB_FN ((__IO unsigned*)(RegBase + 0x48))
+/* Device address register */
+#define USB_ADDR ((__IO unsigned*)(RegBase + 0x4C))
+/* Buffer Table address register */
+#define USB_BUFTAB ((__IO unsigned*)(RegBase + 0x50))
+/******************************************************************************/
+/* Endpoint registers */
+/******************************************************************************/
+#define EP0REG ((__IO unsigned*)(RegBase)) /* endpoint 0 register address */
+
+/* Endpoint Addresses (w/direction) */
+#define EP0_OUT ((uint8_t)0x00)
+#define EP0_IN ((uint8_t)0x80)
+#define EP1_OUT ((uint8_t)0x01)
+#define EP1_IN ((uint8_t)0x81)
+#define EP2_OUT ((uint8_t)0x02)
+#define EP2_IN ((uint8_t)0x82)
+#define EP3_OUT ((uint8_t)0x03)
+#define EP3_IN ((uint8_t)0x83)
+#define EP4_OUT ((uint8_t)0x04)
+#define EP4_IN ((uint8_t)0x84)
+#define EP5_OUT ((uint8_t)0x05)
+#define EP5_IN ((uint8_t)0x85)
+#define EP6_OUT ((uint8_t)0x06)
+#define EP6_IN ((uint8_t)0x86)
+#define EP7_OUT ((uint8_t)0x07)
+#define EP7_IN ((uint8_t)0x87)
+
+/* endpoints enumeration */
+#define ENDP0 ((uint8_t)0)
+#define ENDP1 ((uint8_t)1)
+#define ENDP2 ((uint8_t)2)
+#define ENDP3 ((uint8_t)3)
+#define ENDP4 ((uint8_t)4)
+#define ENDP5 ((uint8_t)5)
+#define ENDP6 ((uint8_t)6)
+#define ENDP7 ((uint8_t)7)
+
+/******************************************************************************/
+/* USB_STS interrupt events */
+/******************************************************************************/
+#define STS_CTRS (0x8000) /* Correct TRansfer (clear-only bit) */
+#define STS_DOVR (0x4000) /* DMA OVeR/underrun (clear-only bit) */
+#define STS_ERROR (0x2000) /* ERRor (clear-only bit) */
+#define STS_WKUP (0x1000) /* WaKe UP (clear-only bit) */
+#define STS_SUSPD (0x0800) /* SUSPend (clear-only bit) */
+#define STS_RST (0x0400) /* RESET (clear-only bit) */
+#define STS_SOF (0x0200) /* Start Of Frame (clear-only bit) */
+#define STS_ESOF (0x0100) /* Expected Start Of Frame (clear-only bit) */
+
+#define STS_DIR (0x0010) /* DIRection of transaction (read-only bit) */
+#define STS_EP_ID (0x000F) /* EndPoint IDentifier (read-only bit) */
+
+#define CLR_CTRS (~STS_CTRS) /* clear Correct TRansfer bit */
+#define CLR_DOVR (~STS_DOVR) /* clear DMA OVeR/underrun bit*/
+#define CLR_ERROR (~STS_ERROR) /* clear ERRor bit */
+#define CLR_WKUP (~STS_WKUP) /* clear WaKe UP bit */
+#define CLR_SUSPD (~STS_SUSPD) /* clear SUSPend bit */
+#define CLR_RST (~STS_RST) /* clear RESET bit */
+#define CLR_SOF (~STS_SOF) /* clear Start Of Frame bit */
+#define CLR_ESOF (~STS_ESOF) /* clear Expected Start Of Frame bit */
+
+/******************************************************************************/
+/* USB_CTRL control register bits definitions */
+/******************************************************************************/
+#define CTRL_CTRSM (0x8000) /* Correct TRansfer Mask */
+#define CTRL_DOVRM (0x4000) /* DMA OVeR/underrun Mask */
+#define CTRL_ERRORM (0x2000) /* ERRor Mask */
+#define CTRL_WKUPM (0x1000) /* WaKe UP Mask */
+#define CTRL_SUSPDM (0x0800) /* SUSPend Mask */
+#define CTRL_RSTM (0x0400) /* RESET Mask */
+#define CTRL_SOFM (0x0200) /* Start Of Frame Mask */
+#define CTRL_ESOFM (0x0100) /* Expected Start Of Frame Mask */
+
+#define CTRL_RESUM (0x0010) /* RESUME request */
+#define CTRL_FSUSPD (0x0008) /* Force SUSPend */
+#define CTRL_LP_MODE (0x0004) /* Low-power MODE */
+#define CTRL_PD (0x0002) /* Power DoWN */
+#define CTRL_FRST (0x0001) /* Force USB RESet */
+
+/******************************************************************************/
+/* USB_FN Frame Number Register bit definitions */
+/******************************************************************************/
+#define FN_RXDP (0x8000) /* status of D+ data line */
+#define FN_RXDM (0x4000) /* status of D- data line */
+#define FN_LCK (0x2000) /* LoCKed */
+#define FN_LSOF (0x1800) /* Lost SOF */
+#define FN_FNUM (0x07FF) /* Frame Number */
+/******************************************************************************/
+/* USB_ADDR Device ADDRess bit definitions */
+/******************************************************************************/
+#define ADDR_EFUC (0x80)
+#define ADDR_ADDR (0x7F)
+/******************************************************************************/
+/* Endpoint register */
+/******************************************************************************/
+/* bit positions */
+#define EP_CTRS_RX (0x8000) /* EndPoint Correct TRansfer RX */
+#define EP_DATTOG_RX (0x4000) /* EndPoint Data TOGGLE RX */
+#define EPRX_STS (0x3000) /* EndPoint RX STATus bit field */
+#define EP_SETUP (0x0800) /* EndPoint SETUP */
+#define EP_T_FIELD (0x0600) /* EndPoint TYPE */
+#define EP_KIND (0x0100) /* EndPoint KIND */
+#define EP_CTRS_TX (0x0080) /* EndPoint Correct TRansfer TX */
+#define EP_DATTOG_TX (0x0040) /* EndPoint Data TOGGLE TX */
+#define EPTX_STS (0x0030) /* EndPoint TX STATus bit field */
+#define EPADDR_FIELD (0x000F) /* EndPoint ADDRess FIELD */
+
+/* EndPoint REGister INTEN (no toggle fields) */
+#define EPREG_MASK (EP_CTRS_RX | EP_SETUP | EP_T_FIELD | EP_KIND | EP_CTRS_TX | EPADDR_FIELD)
+
+/* EP_TYPE[1:0] EndPoint TYPE */
+#define EP_TYPE_MASK (0x0600) /* EndPoint TYPE Mask */
+#define EP_BULK (0x0000) /* EndPoint BULK */
+#define EP_CONTROL (0x0200) /* EndPoint CONTROL */
+#define EP_ISOCHRONOUS (0x0400) /* EndPoint ISOCHRONOUS */
+#define EP_INTERRUPT (0x0600) /* EndPoint INTERRUPT */
+#define EP_T_MASK (~EP_T_FIELD & EPREG_MASK)
+
+/* EP_KIND EndPoint KIND */
+#define EPKIND_MASK (~EP_KIND & EPREG_MASK)
+
+/* STAT_TX[1:0] STATus for TX transfer */
+#define EP_TX_DIS (0x0000) /* EndPoint TX DISabled */
+#define EP_TX_STALL (0x0010) /* EndPoint TX STALLed */
+#define EP_TX_NAK (0x0020) /* EndPoint TX NAKed */
+#define EP_TX_VALID (0x0030) /* EndPoint TX VALID */
+#define EPTX_DATTOG1 (0x0010) /* EndPoint TX Data TOGgle bit1 */
+#define EPTX_DATTOG2 (0x0020) /* EndPoint TX Data TOGgle bit2 */
+#define EPTX_DATTOGMASK (EPTX_STS | EPREG_MASK)
+
+/* STAT_RX[1:0] STATus for RX transfer */
+#define EP_RX_DIS (0x0000) /* EndPoint RX DISabled */
+#define EP_RX_STALL (0x1000) /* EndPoint RX STALLed */
+#define EP_RX_NAK (0x2000) /* EndPoint RX NAKed */
+#define EP_RX_VALID (0x3000) /* EndPoint RX VALID */
+#define EPRX_DATTOG1 (0x1000) /* EndPoint RX Data TOGgle bit1 */
+#define EPRX_DATTOG2 (0x2000) /* EndPoint RX Data TOGgle bit1 */
+#define EPRX_DATTOGMASK (EPRX_STS | EPREG_MASK)
+
+/* USB_SetCtrl */
+#define _SetCNTR(wRegValue) (*USB_CTRL = (uint16_t)wRegValue)
+
+/* USB_SetSts */
+#define _SetISTR(wRegValue) (*USB_STS = (uint16_t)wRegValue)
+
+/* USB_SetAddr */
+#define _SetDADDR(wRegValue) (*USB_ADDR = (uint16_t)wRegValue)
+
+/* USB_SetBuftab */
+#define _SetBTABLE(wRegValue) (*USB_BUFTAB = (uint16_t)(wRegValue & 0xFFF8))
+
+/* USB_GetCtrl */
+#define _GetCNTR() ((uint16_t)*USB_CTRL)
+
+/* USB_GetSts */
+#define _GetISTR() ((uint16_t)*USB_STS)
+
+/* USB_GetFn */
+#define _GetFNR() ((uint16_t)*USB_FN)
+
+/* USB_GetAddr */
+#define _GetDADDR() ((uint16_t)*USB_ADDR)
+
+/* USB_GetBTABLE */
+#define _GetBTABLE() ((uint16_t)*USB_BUFTAB)
+
+/* USB_SetEndPoint */
+#define _SetENDPOINT(bEpNum, wRegValue) (*(EP0REG + bEpNum) = (uint16_t)wRegValue)
+
+/* USB_GetEndPoint */
+#define _GetENDPOINT(bEpNum) ((uint16_t)(*(EP0REG + bEpNum)))
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpType
+ * Description : sets the type in the endpoint register(bits EP_TYPE[1:0])
+ * Input : bEpNum: Endpoint Number.
+ * wType
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPType(bEpNum, wType) (_SetENDPOINT(bEpNum, ((_GetENDPOINT(bEpNum) & EP_T_MASK) | wType)))
+
+/*******************************************************************************
+ * Macro Name : USB_GetEpType
+ * Description : gets the type in the endpoint register(bits EP_TYPE[1:0])
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : Endpoint Type
+ *******************************************************************************/
+#define _GetEPType(bEpNum) (_GetENDPOINT(bEpNum) & EP_T_FIELD)
+
+/*******************************************************************************
+ * Macro Name : SetEPTxStatus
+ * Description : sets the status for tx transfer (bits STAT_TX[1:0]).
+ * Input : bEpNum: Endpoint Number.
+ * wState: new state
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPTxStatus(bEpNum, wState) \
+ { \
+ register uint16_t _wRegVal; \
+ _wRegVal = _GetENDPOINT(bEpNum) & EPTX_DATTOGMASK; \
+ /* toggle first bit ? */ \
+ if ((EPTX_DATTOG1 & wState) != 0) \
+ _wRegVal ^= EPTX_DATTOG1; \
+ /* toggle second bit ? */ \
+ if ((EPTX_DATTOG2 & wState) != 0) \
+ _wRegVal ^= EPTX_DATTOG2; \
+ _SetENDPOINT(bEpNum, (_wRegVal | EP_CTRS_RX | EP_CTRS_TX)); \
+ } /* _SetEPTxStatus */
+
+/*******************************************************************************
+ * Macro Name : SetEPRxStatus
+ * Description : sets the status for rx transfer (bits STAT_TX[1:0])
+ * Input : bEpNum: Endpoint Number.
+ * wState: new state.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPRxStatus(bEpNum, wState) \
+ { \
+ register uint16_t _wRegVal; \
+ \
+ _wRegVal = _GetENDPOINT(bEpNum) & EPRX_DATTOGMASK; \
+ /* toggle first bit ? */ \
+ if ((EPRX_DATTOG1 & wState) != 0) \
+ _wRegVal ^= EPRX_DATTOG1; \
+ /* toggle second bit ? */ \
+ if ((EPRX_DATTOG2 & wState) != 0) \
+ _wRegVal ^= EPRX_DATTOG2; \
+ _SetENDPOINT(bEpNum, (_wRegVal | EP_CTRS_RX | EP_CTRS_TX)); \
+ } /* _SetEPRxStatus */
+
+/*******************************************************************************
+ * Macro Name : SetEPRxTxStatus
+ * Description : sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
+ * Input : bEpNum: Endpoint Number.
+ * wStaterx: new state.
+ * wStatetx: new state.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPRxTxStatus(bEpNum, wStaterx, wStatetx) \
+ { \
+ register uint32_t _wRegVal; \
+ \
+ _wRegVal = _GetENDPOINT(bEpNum) & (EPRX_DATTOGMASK | EPTX_STS); \
+ /* toggle first bit ? */ \
+ if ((EPRX_DATTOG1 & wStaterx) != 0) \
+ _wRegVal ^= EPRX_DATTOG1; \
+ /* toggle second bit ? */ \
+ if ((EPRX_DATTOG2 & wStaterx) != 0) \
+ _wRegVal ^= EPRX_DATTOG2; \
+ /* toggle first bit ? */ \
+ if ((EPTX_DATTOG1 & wStatetx) != 0) \
+ _wRegVal ^= EPTX_DATTOG1; \
+ /* toggle second bit ? */ \
+ if ((EPTX_DATTOG2 & wStatetx) != 0) \
+ _wRegVal ^= EPTX_DATTOG2; \
+ _SetENDPOINT(bEpNum, _wRegVal | EP_CTRS_RX | EP_CTRS_TX); \
+ } /* _SetEPRxTxStatus */
+/*******************************************************************************
+ * Macro Name : USB_GetEpTxSts / USB_GetEpRxSts
+ * Description : gets the status for tx/rx transfer (bits STAT_TX[1:0]
+ * /STAT_RX[1:0])
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : status .
+ *******************************************************************************/
+#define _GetEPTxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EPTX_STS)
+
+#define _GetEPRxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EPRX_STS)
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpTxValid / USB_SetEpRxValid
+ * Description : sets directly the VALID tx/rx-status into the enpoint register
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPTxValid(bEpNum) (_SetEPTxStatus(bEpNum, EP_TX_VALID))
+
+#define _SetEPRxValid(bEpNum) (_SetEPRxStatus(bEpNum, EP_RX_VALID))
+
+/*******************************************************************************
+ * Macro Name : USB_GetTxStallSts / USB_GetRxStallSts.
+ * Description : checks stall condition in an endpoint.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : TRUE = endpoint in stall condition.
+ *******************************************************************************/
+#define _GetTxStallStatus(bEpNum) (_GetEPTxStatus(bEpNum) == EP_TX_STALL)
+#define _GetRxStallStatus(bEpNum) (_GetEPRxStatus(bEpNum) == EP_RX_STALL)
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpKind / USB_ClrEpKind.
+ * Description : set & clear EP_KIND bit.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEP_KIND(bEpNum) \
+ (_SetENDPOINT(bEpNum, (EP_CTRS_RX | EP_CTRS_TX | ((_GetENDPOINT(bEpNum) | EP_KIND) & EPREG_MASK))))
+#define _ClearEP_KIND(bEpNum) (_SetENDPOINT(bEpNum, (EP_CTRS_RX | EP_CTRS_TX | (_GetENDPOINT(bEpNum) & EPKIND_MASK))))
+
+/*******************************************************************************
+ * Macro Name : USB_SetStsOut / USB_ClrStsOut.
+ * Description : Sets/clears directly STATUS_OUT bit in the endpoint register.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _Set_Status_Out(bEpNum) _SetEP_KIND(bEpNum)
+#define _Clear_Status_Out(bEpNum) _ClearEP_KIND(bEpNum)
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpDoubleBufer / USB_ClrEpDoubleBufer.
+ * Description : Sets/clears directly EP_KIND bit in the endpoint register.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPDoubleBuff(bEpNum) _SetEP_KIND(bEpNum)
+#define _ClearEPDoubleBuff(bEpNum) _ClearEP_KIND(bEpNum)
+
+/*******************************************************************************
+ * Macro Name : USB_ClrEpCtrsRx / USB_ClrEpCtrsTx.
+ * Description : Clears bit CTR_RX / CTR_TX in the endpoint register.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _ClearEP_CTR_RX(bEpNum) (_SetENDPOINT(bEpNum, _GetENDPOINT(bEpNum) & 0x7FFF & EPREG_MASK))
+#define _ClearEP_CTR_TX(bEpNum) (_SetENDPOINT(bEpNum, _GetENDPOINT(bEpNum) & 0xFF7F & EPREG_MASK))
+
+/*******************************************************************************
+ * Macro Name : USB_DattogRx / USB_DattogTx .
+ * Description : Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _ToggleDTOG_RX(bEpNum) \
+ (_SetENDPOINT(bEpNum, EP_CTRS_RX | EP_CTRS_TX | EP_DATTOG_RX | (_GetENDPOINT(bEpNum) & EPREG_MASK)))
+#define _ToggleDTOG_TX(bEpNum) \
+ (_SetENDPOINT(bEpNum, EP_CTRS_RX | EP_CTRS_TX | EP_DATTOG_TX | (_GetENDPOINT(bEpNum) & EPREG_MASK)))
+
+/*******************************************************************************
+ * Macro Name : USB_ClrDattogRx / USB_ClrDattogTx.
+ * Description : Clears DTOG_RX / DTOG_TX bit in the endpoint register.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _ClearDTOG_RX(bEpNum) \
+ if ((_GetENDPOINT(bEpNum) & EP_DATTOG_RX) != 0) \
+ _ToggleDTOG_RX(bEpNum)
+#define _ClearDTOG_TX(bEpNum) \
+ if ((_GetENDPOINT(bEpNum) & EP_DATTOG_TX) != 0) \
+ _ToggleDTOG_TX(bEpNum)
+/*******************************************************************************
+ * Macro Name : USB_SetEpAddress.
+ * Description : Sets address in an endpoint register.
+ * Input : bEpNum: Endpoint Number.
+ * bAddr: Address.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPAddress(bEpNum, bAddr) \
+ _SetENDPOINT(bEpNum, EP_CTRS_RX | EP_CTRS_TX | (_GetENDPOINT(bEpNum) & EPREG_MASK) | bAddr)
+
+/*******************************************************************************
+ * Macro Name : USB_GetEpAddress.
+ * Description : Gets address in an endpoint register.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _GetEPAddress(bEpNum) ((uint8_t)(_GetENDPOINT(bEpNum) & EPADDR_FIELD))
+
+#define _pEPTxAddr(bEpNum) ((uint32_t*)((_GetBTABLE() + bEpNum * 8) * 2 + PMAAddr))
+#define _pEPTxCount(bEpNum) ((uint32_t*)((_GetBTABLE() + bEpNum * 8 + 2) * 2 + PMAAddr))
+#define _pEPRxAddr(bEpNum) ((uint32_t*)((_GetBTABLE() + bEpNum * 8 + 4) * 2 + PMAAddr))
+#define _pEPRxCount(bEpNum) ((uint32_t*)((_GetBTABLE() + bEpNum * 8 + 6) * 2 + PMAAddr))
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpTxAddr / USB_SetEpRxAddr.
+ * Description : sets address of the tx/rx buffer.
+ * Input : bEpNum: Endpoint Number.
+ * wAddr: address to be set (must be word aligned).
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPTxAddr(bEpNum, wAddr) (*_pEPTxAddr(bEpNum) = ((wAddr >> 1) << 1))
+#define _SetEPRxAddr(bEpNum, wAddr) (*_pEPRxAddr(bEpNum) = ((wAddr >> 1) << 1))
+
+/*******************************************************************************
+ * Macro Name : USB_GetEpTxAddr / USB_GetEpRxAddr.
+ * Description : Gets address of the tx/rx buffer.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : address of the buffer.
+ *******************************************************************************/
+#define _GetEPTxAddr(bEpNum) ((uint16_t)*_pEPTxAddr(bEpNum))
+#define _GetEPRxAddr(bEpNum) ((uint16_t)*_pEPRxAddr(bEpNum))
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpCntRxReg.
+ * Description : Sets counter of rx buffer with no. of blocks.
+ * Input : pdwReg: pointer to counter.
+ * wCount: Counter.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _BlocksOf32(dwReg, wCount, wNBlocks) \
+ { \
+ wNBlocks = wCount >> 5; \
+ if ((wCount & 0x1f) == 0) \
+ wNBlocks--; \
+ *pdwReg = (uint32_t)((wNBlocks << 10) | 0x8000); \
+ } /* _BlocksOf32 */
+
+#define _BlocksOf2(dwReg, wCount, wNBlocks) \
+ { \
+ wNBlocks = wCount >> 1; \
+ if ((wCount & 0x1) != 0) \
+ wNBlocks++; \
+ *pdwReg = (uint32_t)(wNBlocks << 10); \
+ } /* _BlocksOf2 */
+
+#define _SetEPCountRxReg(dwReg, wCount) \
+ { \
+ uint16_t wNBlocks; \
+ if (wCount > 62) \
+ { \
+ _BlocksOf32(dwReg, wCount, wNBlocks); \
+ } \
+ else \
+ { \
+ _BlocksOf2(dwReg, wCount, wNBlocks); \
+ } \
+ } /* _SetEPCountRxReg */
+
+#define _SetEPRxDblBuf0Count(bEpNum, wCount) \
+ { \
+ uint32_t* pdwReg = _pEPTxCount(bEpNum); \
+ _SetEPCountRxReg(pdwReg, wCount); \
+ }
+/*******************************************************************************
+ * Macro Name : USB_SetEpTxCnt / USB_SetEpRxCnt.
+ * Description : sets counter for the tx/rx buffer.
+ * Input : bEpNum: endpoint number.
+ * wCount: Counter value.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPTxCount(bEpNum, wCount) (*_pEPTxCount(bEpNum) = wCount)
+#define _SetEPRxCount(bEpNum, wCount) \
+ { \
+ uint32_t* pdwReg = _pEPRxCount(bEpNum); \
+ _SetEPCountRxReg(pdwReg, wCount); \
+ }
+/*******************************************************************************
+ * Macro Name : USB_GetEpTxCnt / USB_GetEpRxCnt.
+ * Description : gets counter of the tx buffer.
+ * Input : bEpNum: endpoint number.
+ * Output : None.
+ * Return : Counter value.
+ *******************************************************************************/
+#define _GetEPTxCount(bEpNum) ((uint16_t)(*_pEPTxCount(bEpNum)) & 0x3ff)
+#define _GetEPRxCount(bEpNum) ((uint16_t)(*_pEPRxCount(bEpNum)) & 0x3ff)
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpDblBuf0Addr / USB_SetEpDblBuf1Addr.
+ * Description : Sets buffer 0/1 address in a double buffer endpoint.
+ * Input : bEpNum: endpoint number.
+ * : wBuf0Addr: buffer 0 address.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPDblBuf0Addr(bEpNum, wBuf0Addr) \
+ { \
+ _SetEPTxAddr(bEpNum, wBuf0Addr); \
+ }
+#define _SetEPDblBuf1Addr(bEpNum, wBuf1Addr) \
+ { \
+ _SetEPRxAddr(bEpNum, wBuf1Addr); \
+ }
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpDblBuferAddr.
+ * Description : Sets addresses in a double buffer endpoint.
+ * Input : bEpNum: endpoint number.
+ * : wBuf0Addr: buffer 0 address.
+ * : wBuf1Addr = buffer 1 address.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPDblBuffAddr(bEpNum, wBuf0Addr, wBuf1Addr) \
+ { \
+ _SetEPDblBuf0Addr(bEpNum, wBuf0Addr); \
+ _SetEPDblBuf1Addr(bEpNum, wBuf1Addr); \
+ } /* _SetEPDblBuffAddr */
+
+/*******************************************************************************
+ * Macro Name : USB_GetEpDblBuf0Addr / USB_GetEpDblBuf1Addr.
+ * Description : Gets buffer 0/1 address of a double buffer endpoint.
+ * Input : bEpNum: endpoint number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _GetEPDblBuf0Addr(bEpNum) (_GetEPTxAddr(bEpNum))
+#define _GetEPDblBuf1Addr(bEpNum) (_GetEPRxAddr(bEpNum))
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpDblBuferCnt / USB_SetEpDblBuf0Cnt / USB_SetEpDblBuf1Cnt.
+ * Description : Gets buffer 0/1 address of a double buffer endpoint.
+ * Input : bEpNum: endpoint number.
+ * : bDir: endpoint dir EP_DBUF_OUT = OUT
+ * EP_DBUF_IN = IN
+ * : wCount: Counter value
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPDblBuf0Count(bEpNum, bDir, wCount) \
+ { \
+ if (bDir == EP_DBUF_OUT) \
+ /* OUT endpoint */ \
+ { \
+ _SetEPRxDblBuf0Count(bEpNum, wCount); \
+ } \
+ else if (bDir == EP_DBUF_IN) \
+ /* IN endpoint */ \
+ *_pEPTxCount(bEpNum) = (uint32_t)wCount; \
+ } /* USB_SetEpDblBuf0Cnt*/
+
+#define _SetEPDblBuf1Count(bEpNum, bDir, wCount) \
+ { \
+ if (bDir == EP_DBUF_OUT) \
+ /* OUT endpoint */ \
+ { \
+ _SetEPRxCount(bEpNum, wCount); \
+ } \
+ else if (bDir == EP_DBUF_IN) \
+ /* IN endpoint */ \
+ *_pEPRxCount(bEpNum) = (uint32_t)wCount; \
+ } /* USB_SetEpDblBuf1Cnt */
+
+#define _SetEPDblBuffCount(bEpNum, bDir, wCount) \
+ { \
+ _SetEPDblBuf0Count(bEpNum, bDir, wCount); \
+ _SetEPDblBuf1Count(bEpNum, bDir, wCount); \
+ } /* _SetEPDblBuffCount */
+
+/*******************************************************************************
+ * Macro Name : USB_GetEpDblBuf0Cnt / USB_GetEpDblBuf1Cnt.
+ * Description : Gets buffer 0/1 rx/tx counter for double buffering.
+ * Input : bEpNum: endpoint number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _GetEPDblBuf0Count(bEpNum) (_GetEPTxCount(bEpNum))
+#define _GetEPDblBuf1Count(bEpNum) (_GetEPRxCount(bEpNum))
+
+extern __IO uint16_t wIstr; /* USB_STS register last read value */
+
+void USB_SetCtrl(uint16_t /*wRegValue*/);
+void USB_SetSts(uint16_t /*wRegValue*/);
+void USB_SetAddr(uint16_t /*wRegValue*/);
+void USB_SetBuftab(uint16_t /*wRegValue*/);
+void USB_SetBuftab(uint16_t /*wRegValue*/);
+uint16_t USB_GetCtrl(void);
+uint16_t USB_GetSts(void);
+uint16_t USB_GetFn(void);
+uint16_t USB_GetAddr(void);
+uint16_t USB_GetBTABLE(void);
+void USB_SetEndPoint(uint8_t /*bEpNum*/, uint16_t /*wRegValue*/);
+uint16_t USB_GetEndPoint(uint8_t /*bEpNum*/);
+void USB_SetEpType(uint8_t /*bEpNum*/, uint16_t /*wType*/);
+uint16_t USB_GetEpType(uint8_t /*bEpNum*/);
+void SetEPTxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/);
+void SetEPRxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/);
+void USB_SetDouBleBuferEpStall(uint8_t /*bEpNum*/, uint8_t bDir);
+uint16_t USB_GetEpTxSts(uint8_t /*bEpNum*/);
+uint16_t USB_GetEpRxSts(uint8_t /*bEpNum*/);
+void USB_SetEpTxValid(uint8_t /*bEpNum*/);
+void USB_SetEpRxValid(uint8_t /*bEpNum*/);
+uint16_t USB_GetTxStallSts(uint8_t /*bEpNum*/);
+uint16_t USB_GetRxStallSts(uint8_t /*bEpNum*/);
+void USB_SetEpKind(uint8_t /*bEpNum*/);
+void USB_ClrEpKind(uint8_t /*bEpNum*/);
+void USB_SetStsOut(uint8_t /*bEpNum*/);
+void USB_ClrStsOut(uint8_t /*bEpNum*/);
+void USB_SetEpDoubleBufer(uint8_t /*bEpNum*/);
+void USB_ClrEpDoubleBufer(uint8_t /*bEpNum*/);
+void USB_ClrEpCtrsRx(uint8_t /*bEpNum*/);
+void USB_ClrEpCtrsTx(uint8_t /*bEpNum*/);
+void USB_DattogRx(uint8_t /*bEpNum*/);
+void USB_DattogTx(uint8_t /*bEpNum*/);
+void USB_ClrDattogRx(uint8_t /*bEpNum*/);
+void USB_ClrDattogTx(uint8_t /*bEpNum*/);
+void USB_SetEpAddress(uint8_t /*bEpNum*/, uint8_t /*bAddr*/);
+uint8_t USB_GetEpAddress(uint8_t /*bEpNum*/);
+void USB_SetEpTxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/);
+void USB_SetEpRxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/);
+uint16_t USB_GetEpTxAddr(uint8_t /*bEpNum*/);
+uint16_t USB_GetEpRxAddr(uint8_t /*bEpNum*/);
+void USB_SetEpCntRxReg(uint32_t* /*pdwReg*/, uint16_t /*wCount*/);
+void USB_SetEpTxCnt(uint8_t /*bEpNum*/, uint16_t /*wCount*/);
+void USB_SetEpRxCnt(uint8_t /*bEpNum*/, uint16_t /*wCount*/);
+uint16_t USB_GetEpTxCnt(uint8_t /*bEpNum*/);
+uint16_t USB_GetEpRxCnt(uint8_t /*bEpNum*/);
+void USB_SetEpDblBuf0Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/);
+void USB_SetEpDblBuf1Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf1Addr*/);
+void USB_SetEpDblBuferAddr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/, uint16_t /*wBuf1Addr*/);
+uint16_t USB_GetEpDblBuf0Addr(uint8_t /*bEpNum*/);
+uint16_t USB_GetEpDblBuf1Addr(uint8_t /*bEpNum*/);
+void USB_SetEpDblBuferCnt(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
+void USB_SetEpDblBuf0Cnt(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
+void USB_SetEpDblBuf1Cnt(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
+uint16_t USB_GetEpDblBuf0Cnt(uint8_t /*bEpNum*/);
+uint16_t USB_GetEpDblBuf1Cnt(uint8_t /*bEpNum*/);
+EP_DBUF_DIR GetEPDblBufDir(uint8_t /*bEpNum*/);
+void USB_FreeUserBuf(uint8_t bEpNum /*bEpNum*/, uint8_t bDir);
+uint16_t USB_ToWord(uint8_t, uint8_t);
+uint16_t USB_ByteSwap(uint16_t);
+
+/**
+ * @}
+ */
+
+#endif /* __USB_REGS_H__ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_sil.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_sil.h
new file mode 100644
index 0000000000..76c5c9b0f9
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_sil.h
@@ -0,0 +1,53 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_sil.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_SIL_H__
+#define __USB_SIL_H__
+
+#include "n32g43x.h"
+
+/**
+ * @addtogroup N32G43X_USB_Driver
+ * @{
+ */
+
+uint32_t USB_SilInit(void);
+uint32_t USB_SilWrite(uint8_t bEpAddr, uint8_t* pBufferPointer, uint32_t wBufferSize);
+uint32_t USB_SilRead(uint8_t bEpAddr, uint8_t* pBufferPointer);
+
+/**
+ * @}
+ */
+
+#endif /* __USB_SIL_H__ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_type.h b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_type.h
new file mode 100644
index 0000000000..2263fc24b4
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_type.h
@@ -0,0 +1,54 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_type.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_TYPE_H__
+#define __USB_TYPE_H__
+
+#include "usb_conf.h"
+#include
+
+/**
+ * @addtogroup N32G43X_USB_Driver
+ * @{
+ */
+
+#ifndef NULL
+#define NULL ((void*)0)
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* __USB_TYPE_H__ */
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_core.c b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_core.c
new file mode 100644
index 0000000000..00a283b024
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_core.c
@@ -0,0 +1,950 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_core.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "usb_lib.h"
+
+#define ValBit(VAR, Place) (VAR & (1 << Place))
+#define SetBit(VAR, Place) (VAR |= (1 << Place))
+#define ClrBit(VAR, Place) (VAR &= ((1 << Place) ^ 255))
+
+#define Send0LengthData() \
+ { \
+ _SetEPTxCount(ENDP0, 0); \
+ vSetEPTxStatus(EP_TX_VALID); \
+ }
+
+#define vSetEPRxStatus(st) (SaveRState = st)
+#define vSetEPTxStatus(st) (SaveTState = st)
+
+#define USB_StatusIn() Send0LengthData()
+#define USB_StatusOut() vSetEPRxStatus(EP_RX_VALID)
+
+#define StatusInfo0 StatusInfo.bw.bb1 /* Reverse bb0 & bb1 */
+#define StatusInfo1 StatusInfo.bw.bb0
+
+uint16_t_uint8_t StatusInfo;
+
+bool Data_Mul_MaxPacketSize = false;
+
+static void DataStageOut(void);
+static void DataStageIn(void);
+static void NoData_Setup0(void);
+static void Data_Setup0(void);
+
+/**
+ * @brief Return the current configuration variable address.
+ * @param Length: How many bytes are needed.
+ * @return Return 1 , if the request is invalid when "Length" is 0.
+ * Return "Buffer" if the "Length" is not 0.
+ */
+uint8_t* Standard_GetConfiguration(uint16_t Length)
+{
+ if (Length == 0)
+ {
+ pInformation->Ctrl_Info.Usb_wLength = sizeof(pInformation->CurrentConfiguration);
+ return 0;
+ }
+ pUser_Standard_Requests->User_GetConfiguration();
+ return (uint8_t*)&pInformation->CurrentConfiguration;
+}
+
+/**
+ * @brief This routine is called to set the configuration value
+ * Then each class should configure device itself.
+ * @return
+ * - Success, if the request is performed.
+ * - UnSupport, if the request is invalid.
+ */
+USB_Result Standard_SetConfiguration(void)
+{
+ if ((pInformation->USBwValue0 <= Device_Table.TotalConfiguration) && (pInformation->USBwValue1 == 0)
+ && (pInformation->USBwIndex == 0)) /*call Back usb spec 2.0*/
+ {
+ pInformation->CurrentConfiguration = pInformation->USBwValue0;
+ pUser_Standard_Requests->User_SetConfiguration();
+ return Success;
+ }
+ else
+ {
+ return UnSupport;
+ }
+}
+
+/**
+ * @brief Return the Alternate Setting of the current interface.
+ * @param Length: How many bytes are needed.
+ * @return
+ * - NULL, if the request is invalid when "Length" is 0.
+ * - "Buffer" if the "Length" is not 0.
+ */
+uint8_t* Standard_GetInterface(uint16_t Length)
+{
+ if (Length == 0)
+ {
+ pInformation->Ctrl_Info.Usb_wLength = sizeof(pInformation->CurrentAlternateSetting);
+ return 0;
+ }
+ pUser_Standard_Requests->User_GetInterface();
+ return (uint8_t*)&pInformation->CurrentAlternateSetting;
+}
+
+/**
+ * @brief This routine is called to set the interface.
+ * Then each class should configure the interface them self.
+ * @return
+ * - Success, if the request is performed.
+ * - UnSupport, if the request is invalid.
+ */
+USB_Result Standard_SetInterface(void)
+{
+ USB_Result Re;
+ /*Test if the specified Interface and Alternate Setting are supported by
+ the application Firmware*/
+ Re = (*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, pInformation->USBwValue0);
+
+ if (pInformation->CurrentConfiguration != 0)
+ {
+ if ((Re != Success) || (pInformation->USBwIndex1 != 0) || (pInformation->USBwValue1 != 0))
+ {
+ return UnSupport;
+ }
+ else if (Re == Success)
+ {
+ pUser_Standard_Requests->User_SetInterface();
+ pInformation->CurrentInterface = pInformation->USBwIndex0;
+ pInformation->CurrentAlternateSetting = pInformation->USBwValue0;
+ return Success;
+ }
+ }
+
+ return UnSupport;
+}
+
+/**
+ * @brief Copy the device request data to "StatusInfo buffer".
+ * @param Length: How many bytes are needed.
+ * @return Return 0, if the request is at end of data block,
+ * or is invalid when "Length" is 0.
+ */
+uint8_t* Standard_GetStatus(uint16_t Length)
+{
+ if (Length == 0)
+ {
+ pInformation->Ctrl_Info.Usb_wLength = 2;
+ return 0;
+ }
+
+ /* Reset Status Information */
+ StatusInfo.w = 0;
+
+ if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+ {
+ /*Get Device Status */
+ uint8_t Feature = pInformation->CurrentFeature;
+
+ /* Remote Wakeup enabled */
+ if (ValBit(Feature, 5))
+ {
+ SetBit(StatusInfo0, 1);
+ }
+ else
+ {
+ ClrBit(StatusInfo0, 1);
+ }
+
+ /* Bus-powered */
+ if (ValBit(Feature, 6))
+ {
+ SetBit(StatusInfo0, 0);
+ }
+ else /* Self-powered */
+ {
+ ClrBit(StatusInfo0, 0);
+ }
+ }
+ /*Interface Status*/
+ else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
+ {
+ return (uint8_t*)&StatusInfo;
+ }
+ /*Get EndPoint Status*/
+ else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+ {
+ uint8_t Related_Endpoint;
+ uint8_t wIndex0 = pInformation->USBwIndex0;
+
+ Related_Endpoint = (wIndex0 & 0x0f);
+ if (ValBit(wIndex0, 7))
+ {
+ /* IN endpoint */
+ if (_GetTxStallStatus(Related_Endpoint))
+ {
+ SetBit(StatusInfo0, 0); /* IN Endpoint stalled */
+ }
+ }
+ else
+ {
+ /* OUT endpoint */
+ if (_GetRxStallStatus(Related_Endpoint))
+ {
+ SetBit(StatusInfo0, 0); /* OUT Endpoint stalled */
+ }
+ }
+ }
+ else
+ {
+ return NULL;
+ }
+ pUser_Standard_Requests->User_GetStatus();
+ return (uint8_t*)&StatusInfo;
+}
+
+/**
+ * @brief Clear or disable a specific feature.
+ * @return - Return Success, if the request is performed.
+ * - Return UnSupport, if the request is invalid.
+ */
+USB_Result Standard_ClearFeature(void)
+{
+ uint32_t Type_Rec = Type_Recipient;
+ uint32_t Status;
+
+ if (Type_Rec == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+ { /*Device Clear Feature*/
+ ClrBit(pInformation->CurrentFeature, 5);
+ return Success;
+ }
+ else if (Type_Rec == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+ { /*EndPoint Clear Feature*/
+ USB_Device* pDev;
+ uint32_t Related_Endpoint;
+ uint32_t wIndex0;
+ uint32_t rEP;
+
+ if ((pInformation->USBwValue != ENDPOINT_STALL) || (pInformation->USBwIndex1 != 0))
+ {
+ return UnSupport;
+ }
+
+ pDev = &Device_Table;
+ wIndex0 = pInformation->USBwIndex0;
+ rEP = wIndex0 & ~0x80;
+ Related_Endpoint = ENDP0 + rEP;
+
+ if (ValBit(pInformation->USBwIndex0, 7))
+ {
+ /*Get Status of endpoint & stall the request if the related_ENdpoint
+ is Disabled*/
+ Status = _GetEPTxStatus(Related_Endpoint);
+ }
+ else
+ {
+ Status = _GetEPRxStatus(Related_Endpoint);
+ }
+
+ if ((rEP >= pDev->TotalEndpoint) || (Status == 0) || (pInformation->CurrentConfiguration == 0))
+ {
+ return UnSupport;
+ }
+
+ if (wIndex0 & 0x80)
+ {
+ /* IN endpoint */
+ if (_GetTxStallStatus(Related_Endpoint))
+ {
+ USB_ClrDattogTx(Related_Endpoint);
+ SetEPTxStatus(Related_Endpoint, EP_TX_VALID);
+ }
+ }
+ else
+ {
+ /* OUT endpoint */
+ if (_GetRxStallStatus(Related_Endpoint))
+ {
+ if (Related_Endpoint == ENDP0)
+ {
+ /* After clear the STALL, enable the default endpoint receiver */
+ USB_SetEpRxCnt(Related_Endpoint, Device_Property.MaxPacketSize);
+ _SetEPRxStatus(Related_Endpoint, EP_RX_VALID);
+ }
+ else
+ {
+ USB_ClrDattogRx(Related_Endpoint);
+ _SetEPRxStatus(Related_Endpoint, EP_RX_VALID);
+ }
+ }
+ }
+ pUser_Standard_Requests->User_ClearFeature();
+ return Success;
+ }
+
+ return UnSupport;
+}
+
+/**
+ * @brief Set or enable a specific feature of EndPoint
+ * @return - Return Success, if the request is performed.
+ * - Return UnSupport, if the request is invalid.
+ */
+USB_Result Standard_SetEndPointFeature(void)
+{
+ uint32_t wIndex0;
+ uint32_t Related_Endpoint;
+ uint32_t rEP;
+ uint32_t Status;
+
+ wIndex0 = pInformation->USBwIndex0;
+ rEP = wIndex0 & ~0x80;
+ Related_Endpoint = ENDP0 + rEP;
+
+ if (ValBit(pInformation->USBwIndex0, 7))
+ {
+ /* get Status of endpoint & stall the request if the related_ENdpoint
+ is Disabled*/
+ Status = _GetEPTxStatus(Related_Endpoint);
+ }
+ else
+ {
+ Status = _GetEPRxStatus(Related_Endpoint);
+ }
+
+ if (Related_Endpoint >= Device_Table.TotalEndpoint || pInformation->USBwValue != 0 || Status == 0
+ || pInformation->CurrentConfiguration == 0)
+ {
+ return UnSupport;
+ }
+ else
+ {
+ if (wIndex0 & 0x80)
+ {
+ /* IN endpoint */
+ _SetEPTxStatus(Related_Endpoint, EP_TX_STALL);
+ }
+
+ else
+ {
+ /* OUT endpoint */
+ _SetEPRxStatus(Related_Endpoint, EP_RX_STALL);
+ }
+ }
+ pUser_Standard_Requests->User_SetEndPointFeature();
+ return Success;
+}
+
+/**
+ * @brief Set or enable a specific feature of Device.
+ * @return - Return Success, if the request is performed.
+ * - Return UnSupport, if the request is invalid.
+ */
+USB_Result Standard_SetDeviceFeature(void)
+{
+ SetBit(pInformation->CurrentFeature, 5);
+ pUser_Standard_Requests->User_SetDeviceFeature();
+ return Success;
+}
+
+/**
+ * @brief Standard_GetDescriptorData is used for descriptors transfer.
+ * : This routine is used for the descriptors resident in Flash
+ * or RAM
+ * pDesc can be in either Flash or RAM
+ * The purpose of this routine is to have a versatile way to
+ * response descriptors request. It allows user to generate
+ * certain descriptors with software or read descriptors from
+ * external storage part by part.
+ * @param Length: Length of the data in this transfer.
+ * @param pDesc: A pointer points to descriptor struct.
+ * The structure gives the initial address of the descriptor and
+ * its original size.
+ * @return Address of a part of the descriptor pointed by the Usb_
+ * wOffset The buffer pointed by this address contains at least
+ * Length bytes.
+ */
+uint8_t* Standard_GetDescriptorData(uint16_t Length, USB_OneDescriptor* pDesc)
+{
+ uint32_t wOffset;
+
+ wOffset = pInformation->Ctrl_Info.Usb_wOffset;
+ if (Length == 0)
+ {
+ pInformation->Ctrl_Info.Usb_wLength = pDesc->Descriptor_Size - wOffset;
+ return 0;
+ }
+
+ return pDesc->Descriptor + wOffset;
+}
+
+/**
+ * @brief Data stage of a Control Write Transfer.
+ */
+void DataStageOut(void)
+{
+ USB_EndpointMess* pEPinfo = &pInformation->Ctrl_Info;
+ uint32_t save_rLength;
+
+ save_rLength = pEPinfo->Usb_rLength;
+
+ if (pEPinfo->CopyData && save_rLength)
+ {
+ uint8_t* Buffer;
+ uint32_t Length;
+
+ Length = pEPinfo->PacketSize;
+ if (Length > save_rLength)
+ {
+ Length = save_rLength;
+ }
+
+ Buffer = (*pEPinfo->CopyData)(Length);
+ pEPinfo->Usb_rLength -= Length;
+ pEPinfo->Usb_rOffset += Length;
+
+ USB_CopyPMAToUserBuf(Buffer, USB_GetEpRxAddr(ENDP0), Length);
+ }
+
+ if (pEPinfo->Usb_rLength != 0)
+ {
+ vSetEPRxStatus(EP_RX_VALID); /* re-enable for next data reception */
+ USB_SetEpTxCnt(ENDP0, 0);
+ vSetEPTxStatus(EP_TX_VALID); /* Expect the host to abort the data OUT stage */
+ }
+ /* Set the next State*/
+ if (pEPinfo->Usb_rLength >= pEPinfo->PacketSize)
+ {
+ pInformation->CtrlState = OutData;
+ }
+ else
+ {
+ if (pEPinfo->Usb_rLength > 0)
+ {
+ pInformation->CtrlState = LastOutData;
+ }
+ else if (pEPinfo->Usb_rLength == 0)
+ {
+ pInformation->CtrlState = WaitStatusIn;
+ USB_StatusIn();
+ }
+ }
+}
+
+/**
+ * @brief Data stage of a Control Read Transfer.
+ */
+void DataStageIn(void)
+{
+ USB_EndpointMess* pEPinfo = &pInformation->Ctrl_Info;
+ uint32_t save_wLength = pEPinfo->Usb_wLength;
+ uint32_t CtrlState = pInformation->CtrlState;
+
+ uint8_t* DataBuffer;
+ uint32_t Length;
+
+ if ((save_wLength == 0) && (CtrlState == LastInData))
+ {
+ if (Data_Mul_MaxPacketSize == true)
+ {
+ /* No more data to send and empty packet */
+ Send0LengthData();
+ CtrlState = LastInData;
+ Data_Mul_MaxPacketSize = false;
+ }
+ else
+ {
+ /* No more data to send so STALL the TX Status*/
+ CtrlState = WaitStatusOut;
+ vSetEPTxStatus(EP_TX_STALL);
+ }
+
+ goto Expect_Status_Out;
+ }
+
+ Length = pEPinfo->PacketSize;
+ CtrlState = (save_wLength <= Length) ? LastInData : InData;
+
+ if (Length > save_wLength)
+ {
+ Length = save_wLength;
+ }
+
+ DataBuffer = (*pEPinfo->CopyData)(Length);
+
+ USB_CopyUserToPMABuf(DataBuffer, USB_GetEpTxAddr(ENDP0), Length);
+
+ USB_SetEpTxCnt(ENDP0, Length);
+
+ pEPinfo->Usb_wLength -= Length;
+ pEPinfo->Usb_wOffset += Length;
+ vSetEPTxStatus(EP_TX_VALID);
+
+ USB_StatusOut(); /* Expect the host to abort the data IN stage */
+
+Expect_Status_Out:
+ pInformation->CtrlState = CtrlState;
+}
+
+/**
+ * @brief Proceed the processing of setup request without data stage.
+ */
+void NoData_Setup0(void)
+{
+ USB_Result Result = UnSupport;
+ uint32_t RequestNo = pInformation->bRequest;
+ uint32_t CtrlState;
+
+ if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+ {
+ /* Device Request*/
+ /* SET_CONFIGURATION*/
+ if (RequestNo == SET_CONFIGURATION)
+ {
+ Result = Standard_SetConfiguration();
+ }
+
+ /*SET ADDRESS*/
+ else if (RequestNo == SET_ADDRESS)
+ {
+ if ((pInformation->USBwValue0 > 127) || (pInformation->USBwValue1 != 0) || (pInformation->USBwIndex != 0)
+ || (pInformation->CurrentConfiguration != 0))
+ /* Device Address should be 127 or less*/
+ {
+ CtrlState = Stalled;
+ goto exit_NoData_Setup0;
+ }
+ else
+ {
+ Result = Success;
+ }
+ }
+ /*SET FEATURE for Device*/
+ else if (RequestNo == SET_FEATURE)
+ {
+ if ((pInformation->USBwValue0 == DEVICE_REMOTE_WAKEUP) && (pInformation->USBwIndex == 0))
+ {
+ Result = Standard_SetDeviceFeature();
+ }
+ else
+ {
+ Result = UnSupport;
+ }
+ }
+ /*Clear FEATURE for Device */
+ else if (RequestNo == CLR_FEATURE)
+ {
+ if (pInformation->USBwValue0 == DEVICE_REMOTE_WAKEUP && pInformation->USBwIndex == 0
+ && ValBit(pInformation->CurrentFeature, 5))
+ {
+ Result = Standard_ClearFeature();
+ }
+ else
+ {
+ Result = UnSupport;
+ }
+ }
+ }
+
+ /* Interface Request*/
+ else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
+ {
+ /*SET INTERFACE*/
+ if (RequestNo == SET_INTERFACE)
+ {
+ Result = Standard_SetInterface();
+ }
+ }
+
+ /* EndPoint Request*/
+ else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+ {
+ /*CLEAR FEATURE for EndPoint*/
+ if (RequestNo == CLR_FEATURE)
+ {
+ Result = Standard_ClearFeature();
+ }
+ /* SET FEATURE for EndPoint*/
+ else if (RequestNo == SET_FEATURE)
+ {
+ Result = Standard_SetEndPointFeature();
+ }
+ }
+ else
+ {
+ Result = UnSupport;
+ }
+
+ if (Result != Success)
+ {
+ Result = (*pProperty->Class_NoData_Setup)(RequestNo);
+ if (Result == Not_Ready)
+ {
+ CtrlState = Pause;
+ goto exit_NoData_Setup0;
+ }
+ }
+
+ if (Result != Success)
+ {
+ CtrlState = Stalled;
+ goto exit_NoData_Setup0;
+ }
+
+ CtrlState = WaitStatusIn; /* After no data stage SETUP */
+
+ USB_StatusIn();
+
+exit_NoData_Setup0:
+ pInformation->CtrlState = CtrlState;
+ return;
+}
+
+/**
+ * @brief Proceed the processing of setup request with data stage.
+ */
+void Data_Setup0(void)
+{
+ uint8_t* (*CopyRoutine)(uint16_t);
+ USB_Result Result;
+ uint32_t Request_No = pInformation->bRequest;
+
+ uint32_t Related_Endpoint, Reserved;
+ uint32_t wOffset, Status;
+
+ CopyRoutine = NULL;
+ wOffset = 0;
+
+ /*GET DESCRIPTOR*/
+ if (Request_No == GET_DESCRIPTOR)
+ {
+ if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+ {
+ uint8_t wValue1 = pInformation->USBwValue1;
+ if (wValue1 == DEVICE_DESCRIPTOR)
+ {
+ CopyRoutine = pProperty->GetDeviceDescriptor;
+ }
+ else if (wValue1 == CONFIG_DESCRIPTOR)
+ {
+ CopyRoutine = pProperty->GetConfigDescriptor;
+ }
+ else if (wValue1 == STRING_DESCRIPTOR)
+ {
+ CopyRoutine = pProperty->GetStringDescriptor;
+ } /* End of GET_DESCRIPTOR */
+ }
+ }
+
+ /*GET STATUS*/
+ else if ((Request_No == GET_STATUS) && (pInformation->USBwValue == 0) && (pInformation->USBwLength == 0x0002)
+ && (pInformation->USBwIndex1 == 0))
+ {
+ /* GET STATUS for Device*/
+ if ((Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)) && (pInformation->USBwIndex == 0))
+ {
+ CopyRoutine = Standard_GetStatus;
+ }
+
+ /* GET STATUS for Interface*/
+ else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
+ {
+ if (((*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, 0) == Success)
+ && (pInformation->CurrentConfiguration != 0))
+ {
+ CopyRoutine = Standard_GetStatus;
+ }
+ }
+
+ /* GET STATUS for EndPoint*/
+ else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+ {
+ Related_Endpoint = (pInformation->USBwIndex0 & 0x0f);
+ Reserved = pInformation->USBwIndex0 & 0x70;
+
+ if (ValBit(pInformation->USBwIndex0, 7))
+ {
+ /*Get Status of endpoint & stall the request if the related_ENdpoint
+ is Disabled*/
+ Status = _GetEPTxStatus(Related_Endpoint);
+ }
+ else
+ {
+ Status = _GetEPRxStatus(Related_Endpoint);
+ }
+
+ if ((Related_Endpoint < Device_Table.TotalEndpoint) && (Reserved == 0) && (Status != 0))
+ {
+ CopyRoutine = Standard_GetStatus;
+ }
+ }
+ }
+
+ /*GET CONFIGURATION*/
+ else if (Request_No == GET_CONFIGURATION)
+ {
+ if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+ {
+ CopyRoutine = Standard_GetConfiguration;
+ }
+ }
+ /*GET INTERFACE*/
+ else if (Request_No == GET_INTERFACE)
+ {
+ if ((Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT)) && (pInformation->CurrentConfiguration != 0)
+ && (pInformation->USBwValue == 0) && (pInformation->USBwIndex1 == 0) && (pInformation->USBwLength == 0x0001)
+ && ((*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, 0) == Success))
+ {
+ CopyRoutine = Standard_GetInterface;
+ }
+ }
+
+ if (CopyRoutine)
+ {
+ pInformation->Ctrl_Info.Usb_wOffset = wOffset;
+ pInformation->Ctrl_Info.CopyData = CopyRoutine;
+ /* sb in the original the cast to word was directly */
+ /* now the cast is made step by step */
+ (*CopyRoutine)(0);
+ Result = Success;
+ }
+ else
+ {
+ Result = (*pProperty->Class_Data_Setup)(pInformation->bRequest);
+ if (Result == Not_Ready)
+ {
+ pInformation->CtrlState = Pause;
+ return;
+ }
+ }
+
+ if (pInformation->Ctrl_Info.Usb_wLength == 0xFFFF)
+ {
+ /* Data is not ready, wait it */
+ pInformation->CtrlState = Pause;
+ return;
+ }
+ if ((Result == UnSupport) || (pInformation->Ctrl_Info.Usb_wLength == 0))
+ {
+ /* Unsupported request */
+ pInformation->CtrlState = Stalled;
+ return;
+ }
+
+ if (ValBit(pInformation->bmRequestType, 7))
+ {
+ /* Device ==> Host */
+ __IO uint32_t wLength = pInformation->USBwLength;
+
+ /* Restrict the data length to be the one host asks for */
+ if (pInformation->Ctrl_Info.Usb_wLength > wLength)
+ {
+ pInformation->Ctrl_Info.Usb_wLength = wLength;
+ }
+
+ else if (pInformation->Ctrl_Info.Usb_wLength < pInformation->USBwLength)
+ {
+ if (pInformation->Ctrl_Info.Usb_wLength < pProperty->MaxPacketSize)
+ {
+ Data_Mul_MaxPacketSize = false;
+ }
+ else if ((pInformation->Ctrl_Info.Usb_wLength % pProperty->MaxPacketSize) == 0)
+ {
+ Data_Mul_MaxPacketSize = true;
+ }
+ }
+
+ pInformation->Ctrl_Info.PacketSize = pProperty->MaxPacketSize;
+ DataStageIn();
+ }
+ else
+ {
+ pInformation->CtrlState = OutData;
+ vSetEPRxStatus(EP_RX_VALID); /* enable for next data reception */
+ }
+
+ return;
+}
+
+/**
+ * @brief Get the device request data and dispatch to individual process.
+ * @return USB_ProcessPost0.
+ */
+uint8_t USB_ProcessSetup0(void)
+{
+ union
+ {
+ uint8_t* b;
+ uint16_t* w;
+ } pBuf;
+
+ uint16_t offset = 1;
+
+ pBuf.b = PMAAddr + (uint8_t*)(_GetEPRxAddr(ENDP0) * 2); /* *2 for 32 bits addr */
+
+ if (pInformation->CtrlState != Pause)
+ {
+ pInformation->bmRequestType = *pBuf.b++; /* bmRequestType */
+ pInformation->bRequest = *pBuf.b++; /* bRequest */
+ pBuf.w += offset; /* word not accessed because of 32 bits addressing */
+ pInformation->USBwValue = USB_ByteSwap(*pBuf.w++); /* wValue */
+ pBuf.w += offset; /* word not accessed because of 32 bits addressing */
+ pInformation->USBwIndex = USB_ByteSwap(*pBuf.w++); /* wIndex */
+ pBuf.w += offset; /* word not accessed because of 32 bits addressing */
+ pInformation->USBwLength = *pBuf.w; /* wLength */
+ }
+
+ pInformation->CtrlState = SettingUp;
+ if (pInformation->USBwLength == 0)
+ {
+ /* Setup with no data stage */
+ NoData_Setup0();
+ }
+ else
+ {
+ /* Setup with data stage */
+ Data_Setup0();
+ }
+ return USB_ProcessPost0();
+}
+
+/**
+ * @brief Process the IN token on all default endpoint.
+ * @return USB_ProcessPost0.
+ */
+uint8_t USB_ProcessIn0(void)
+{
+ uint32_t CtrlState = pInformation->CtrlState;
+
+ if ((CtrlState == InData) || (CtrlState == LastInData))
+ {
+ DataStageIn();
+ /* CtrlState may be changed outside the function */
+ CtrlState = pInformation->CtrlState;
+ }
+
+ else if (CtrlState == WaitStatusIn)
+ {
+ if ((pInformation->bRequest == SET_ADDRESS) && (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)))
+ {
+ USB_SetDeviceAddress(pInformation->USBwValue0);
+ pUser_Standard_Requests->User_SetDeviceAddress();
+ }
+ (*pProperty->Process_Status_IN)();
+ CtrlState = Stalled;
+ }
+
+ else
+ {
+ CtrlState = Stalled;
+ }
+
+ pInformation->CtrlState = CtrlState;
+
+ return USB_ProcessPost0();
+}
+
+/**
+ * @brief Process the OUT token on all default endpoint.
+ * @return USB_ProcessPost0.
+ */
+uint8_t USB_ProcessOut0(void)
+{
+ uint32_t CtrlState = pInformation->CtrlState;
+
+ if ((CtrlState == InData) || (CtrlState == LastInData))
+ {
+ /* host aborts the transfer before finish */
+ CtrlState = Stalled;
+ }
+ else if ((CtrlState == OutData) || (CtrlState == LastOutData))
+ {
+ DataStageOut();
+ CtrlState = pInformation->CtrlState; /* may be changed outside the function */
+ }
+
+ else if (CtrlState == WaitStatusOut)
+ {
+ (*pProperty->Process_Status_OUT)();
+ CtrlState = Stalled;
+ }
+
+ /* Unexpect state, STALL the endpoint */
+ else
+ {
+ CtrlState = Stalled;
+ }
+
+ pInformation->CtrlState = CtrlState;
+
+ return USB_ProcessPost0();
+}
+
+/**
+ * @brief Stall the Endpoint 0 in case of error.
+ * @return
+ * - 0 if the control State is in Pause
+ * - 1 if not.
+ */
+uint8_t USB_ProcessPost0(void)
+{
+ USB_SetEpRxCnt(ENDP0, Device_Property.MaxPacketSize);
+
+ if (pInformation->CtrlState == Stalled)
+ {
+ vSetEPRxStatus(EP_RX_STALL);
+ vSetEPTxStatus(EP_TX_STALL);
+ }
+ return (pInformation->CtrlState == Pause);
+}
+
+/**
+ * @brief Set the device and all the used Endpoints addresses.
+ * @param Val device address.
+ */
+void USB_SetDeviceAddress(uint8_t Val)
+{
+ uint32_t i;
+ uint32_t nEP = Device_Table.TotalEndpoint;
+
+ /* set address in every used endpoint */
+ for (i = 0; i < nEP; i++)
+ {
+ _SetEPAddress((uint8_t)i, (uint8_t)i);
+ } /* for */
+ _SetDADDR(Val | ADDR_EFUC); /* set device address and enable function */
+}
+
+/**
+ * @brief No operation function.
+ */
+void USB_ProcessNop(void)
+{
+}
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_init.c b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_init.c
new file mode 100644
index 0000000000..a274b60657
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_init.c
@@ -0,0 +1,71 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_init.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "usb_lib.h"
+
+/* The number of current endpoint, it will be used to specify an endpoint */
+uint8_t EPindex;
+/* The number of current device, it is an index to the Device_Table */
+/* uint8_t Device_no; */
+/* Points to the USB_DeviceMess structure of current device */
+/* The purpose of this register is to speed up the execution */
+USB_DeviceMess* pInformation;
+/* Points to the DEVICE_PROP structure of current device */
+/* The purpose of this register is to speed up the execution */
+DEVICE_PROP* pProperty;
+/* Temporary save the state of Rx & Tx status. */
+/* Whenever the Rx or Tx state is changed, its value is saved */
+/* in this variable first and will be set to the EPRB or EPRA */
+/* at the end of interrupt process */
+uint16_t SaveState;
+uint16_t wInterrupt_Mask;
+USB_DeviceMess Device_Info;
+USER_STANDARD_REQUESTS* pUser_Standard_Requests;
+
+/**
+ * @brief USB system initialization
+ */
+void USB_Init(void)
+{
+ pInformation = &Device_Info;
+ pInformation->CtrlState = 2;
+ pProperty = &Device_Property;
+ pUser_Standard_Requests = &User_Standard_Requests;
+ /* Initialize devices one by one */
+ pProperty->Init();
+ /*Pull up DP*/
+// _ClrDPCtrl();
+ _EnPortPullup();
+// printf("DP_CTRL=%x\r\n", (*DP_CTRL));
+}
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_int.c b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_int.c
new file mode 100644
index 0000000000..933ed45f29
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_int.c
@@ -0,0 +1,179 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_int.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "usb_lib.h"
+
+__IO uint16_t SaveRState;
+__IO uint16_t SaveTState;
+
+extern void (*pEpInt_IN[7])(void); /* Handles IN interrupts */
+extern void (*pEpInt_OUT[7])(void); /* Handles OUT interrupts */
+
+/**
+ * @brief Low priority Endpoint Correct Transfer interrupt's service routine.
+ */
+void USB_CorrectTransferLp(void)
+{
+ __IO uint16_t wEPVal = 0;
+ /* stay in loop while pending interrupts */
+ while (((wIstr = _GetISTR()) & STS_CTRS) != 0)
+ {
+ /* extract highest priority endpoint number */
+ EPindex = (uint8_t)(wIstr & STS_EP_ID);
+ if (EPindex == 0)
+ {
+ /* Decode and service control endpoint interrupt */
+ /* calling related service routine */
+ /* (USB_ProcessSetup0, USB_ProcessIn0, USB_ProcessOut0) */
+
+ /* save RX & TX status */
+ /* and set both to NAK */
+
+ SaveRState = _GetENDPOINT(ENDP0);
+ SaveTState = SaveRState & EPTX_STS;
+ SaveRState &= EPRX_STS;
+ _SetEPRxTxStatus(ENDP0, EP_RX_NAK, EP_TX_NAK);
+
+ /* DIR bit = origin of the interrupt */
+
+ if ((wIstr & STS_DIR) == 0)
+ {
+ /* DIR = 0 */
+
+ /* DIR = 0 => IN int */
+ /* DIR = 0 implies that (EP_CTRS_TX = 1) always */
+
+ _ClearEP_CTR_TX(ENDP0);
+ USB_ProcessIn0();
+
+ /* before terminate set Tx & Rx status */
+
+ _SetEPRxTxStatus(ENDP0, SaveRState, SaveTState);
+ return;
+ }
+ else
+ {
+ /* DIR = 1 */
+
+ /* DIR = 1 & CTR_RX => SETUP or OUT int */
+ /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
+
+ wEPVal = _GetENDPOINT(ENDP0);
+
+ if ((wEPVal & EP_SETUP) != 0)
+ {
+ _ClearEP_CTR_RX(ENDP0); /* SETUP bit kept frozen while CTR_RX = 1 */
+ USB_ProcessSetup0();
+ /* before terminate set Tx & Rx status */
+
+ _SetEPRxTxStatus(ENDP0, SaveRState, SaveTState);
+ return;
+ }
+
+ else if ((wEPVal & EP_CTRS_RX) != 0)
+ {
+ _ClearEP_CTR_RX(ENDP0);
+ USB_ProcessOut0();
+ /* before terminate set Tx & Rx status */
+
+ _SetEPRxTxStatus(ENDP0, SaveRState, SaveTState);
+ return;
+ }
+ }
+ } /* if (EPindex == 0) */
+ else
+ {
+ /* Decode and service non control endpoints interrupt */
+
+ /* process related endpoint register */
+ wEPVal = _GetENDPOINT(EPindex);
+ if ((wEPVal & EP_CTRS_RX) != 0)
+ {
+ /* clear int flag */
+ _ClearEP_CTR_RX(EPindex);
+
+ /* call OUT service function */
+ (*pEpInt_OUT[EPindex - 1])();
+
+ } /* if ((wEPVal & EP_CTRS_RX) */
+
+ if ((wEPVal & EP_CTRS_TX) != 0)
+ {
+ /* clear int flag */
+ _ClearEP_CTR_TX(EPindex);
+
+ /* call IN service function */
+ (*pEpInt_IN[EPindex - 1])();
+ } /* if ((wEPVal & EP_CTRS_TX) != 0) */
+
+ } /* if (EPindex == 0) else */
+
+ } /* while (...) */
+}
+
+/**
+ * @brief High Priority Endpoint Correct Transfer interrupt's service routine.
+ */
+void USB_CorrectTransferHp(void)
+{
+ uint32_t wEPVal = 0;
+
+ while (((wIstr = _GetISTR()) & STS_CTRS) != 0)
+ {
+ _SetISTR((uint16_t)CLR_CTRS); /* clear CTR flag */
+ /* extract highest priority endpoint number */
+ EPindex = (uint8_t)(wIstr & STS_EP_ID);
+ /* process related endpoint register */
+ wEPVal = _GetENDPOINT(EPindex);
+ if ((wEPVal & EP_CTRS_RX) != 0)
+ {
+ /* clear int flag */
+ _ClearEP_CTR_RX(EPindex);
+
+ /* call OUT service function */
+ (*pEpInt_OUT[EPindex - 1])();
+
+ } /* if ((wEPVal & EP_CTRS_RX) */
+ else if ((wEPVal & EP_CTRS_TX) != 0)
+ {
+ /* clear int flag */
+ _ClearEP_CTR_TX(EPindex);
+
+ /* call IN service function */
+ (*pEpInt_IN[EPindex - 1])();
+
+ } /* if ((wEPVal & EP_CTRS_TX) != 0) */
+
+ } /* while (...) */
+}
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_mem.c b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_mem.c
new file mode 100644
index 0000000000..02768e0307
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_mem.c
@@ -0,0 +1,81 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_mem.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "usb_lib.h"
+u8* EpOutDataPtrTmp;
+u8* EpInDataPtrTmp;
+
+/**
+ * @brief Copy a buffer from user memory area to packet memory area (PMA)
+ * @param pbUsrBuf pointer to user memory area.
+ * @param wPMABufAddr address into PMA.
+ * @param wNBytes no. of bytes to be copied.
+ */
+void USB_CopyUserToPMABuf(uint8_t* pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+ uint32_t n = (wNBytes + 1) >> 1; /* n = (wNBytes + 1) / 2 */
+ uint32_t i, temp1, temp2;
+ uint16_t* pdwVal;
+ pdwVal = (uint16_t*)(wPMABufAddr * 2 + PMAAddr);
+ for (i = n; i != 0; i--)
+ {
+ temp1 = (uint16_t)*pbUsrBuf;
+ pbUsrBuf++;
+ temp2 = temp1 | (uint16_t)*pbUsrBuf << 8;
+ *pdwVal++ = temp2;
+ pdwVal++;
+ pbUsrBuf++;
+ EpInDataPtrTmp = pbUsrBuf;
+ }
+}
+
+/**
+ * @brief Copy a buffer from user memory area to packet memory area (PMA)
+ * @param pbUsrBuf pointer to user memory area.
+ * @param wPMABufAddr address into PMA.
+ * @param wNBytes no. of bytes to be copied.
+ */
+void USB_CopyPMAToUserBuf(uint8_t* pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+ uint32_t n = (wNBytes + 1) >> 1; /* /2*/
+ uint32_t i;
+ uint32_t* pdwVal;
+ pdwVal = (uint32_t*)(wPMABufAddr * 2 + PMAAddr);
+ for (i = n; i != 0; i--)
+ {
+ *(uint16_t*)pbUsrBuf++ = *pdwVal++;
+ pbUsrBuf++;
+ EpOutDataPtrTmp = pbUsrBuf;
+ }
+}
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_regs.c b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_regs.c
new file mode 100644
index 0000000000..457eef62b1
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_regs.c
@@ -0,0 +1,598 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_regs.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "usb_lib.h"
+
+/**
+ * @brief Set the CTRL register value.
+ * @param wRegValue new register value.
+ */
+void USB_SetCtrl(uint16_t wRegValue)
+{
+ _SetCNTR(wRegValue);
+}
+
+/**
+ * @brief returns the CTRL register value.
+ * @return CTRL register Value.
+ */
+uint16_t USB_GetCtrl(void)
+{
+ return (_GetCNTR());
+}
+
+/**
+ * @brief Set the STS register value.
+ * @param wRegValue new register value.
+ */
+void USB_SetSts(uint16_t wRegValue)
+{
+ _SetISTR(wRegValue);
+}
+
+/**
+ * @brief Returns the STS register value.
+ * @return STS register Value
+ */
+uint16_t USB_GetSts(void)
+{
+ return (_GetISTR());
+}
+
+/**
+ * @brief Returns the FN register value.
+ * @return FN register Value
+ */
+uint16_t USB_GetFn(void)
+{
+ return (_GetFNR());
+}
+
+/**
+ * @brief Set the ADDR register value.
+ * @param wRegValue new register value.
+ */
+void USB_SetAddr(uint16_t wRegValue)
+{
+ _SetDADDR(wRegValue);
+}
+
+/**
+ * @brief Returns the ADDR register value.
+ * @return ADDR register Value
+ */
+uint16_t USB_GetAddr(void)
+{
+ return (_GetDADDR());
+}
+
+/**
+ * @brief Set the BUFTAB.
+ * @param wRegValue New register value.
+ */
+void USB_SetBuftab(uint16_t wRegValue)
+{
+ _SetBTABLE(wRegValue);
+}
+
+/**
+ * @brief Returns the BUFTAB register value.
+ * @return BUFTAB address.
+ */
+uint16_t USB_GetBTABLE(void)
+{
+ return (_GetBTABLE());
+}
+
+/**
+ * @brief Set the Endpoint register value.
+ * @param bEpNum Endpoint Number.
+ * @param wRegValue New register value.
+ */
+void USB_SetEndPoint(uint8_t bEpNum, uint16_t wRegValue)
+{
+ _SetENDPOINT(bEpNum, wRegValue);
+}
+
+/**
+ * @brief Return the Endpoint register value.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint register value.
+ */
+uint16_t USB_GetEndPoint(uint8_t bEpNum)
+{
+ return (_GetENDPOINT(bEpNum));
+}
+
+/**
+ * @brief sets the type in the endpoint register.
+ * @param bEpNum Endpoint Number.
+ * @param wType type definition.
+ */
+void USB_SetEpType(uint8_t bEpNum, uint16_t wType)
+{
+ _SetEPType(bEpNum, wType);
+}
+
+/**
+ * @brief Returns the endpoint type.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint Type
+ */
+uint16_t USB_GetEpType(uint8_t bEpNum)
+{
+ return (_GetEPType(bEpNum));
+}
+
+/**
+ * @brief Set the status of Tx endpoint.
+ * @param bEpNum Endpoint Number.
+ * @param wState new state.
+ */
+void SetEPTxStatus(uint8_t bEpNum, uint16_t wState)
+{
+ _SetEPTxStatus(bEpNum, wState);
+}
+
+/**
+ * @brief Set the status of Rx endpoint.
+ * @param bEpNum Endpoint Number.
+ * @param wState new state.
+ */
+void SetEPRxStatus(uint8_t bEpNum, uint16_t wState)
+{
+ _SetEPRxStatus(bEpNum, wState);
+}
+
+/**
+ * @brief sets the status for Double Buffer Endpoint to STALL
+ * @param bEpNum Endpoint Number.
+ * @param bDir Endpoint direction.
+ */
+void USB_SetDouBleBuferEpStall(uint8_t bEpNum, uint8_t bDir)
+{
+ uint16_t Endpoint_DTOG_Status;
+ Endpoint_DTOG_Status = USB_GetEndPoint(bEpNum);
+ if (bDir == EP_DBUF_OUT)
+ { /* OUT double buffered endpoint */
+ _SetENDPOINT(bEpNum, Endpoint_DTOG_Status & ~EPRX_DATTOG1);
+ }
+ else if (bDir == EP_DBUF_IN)
+ { /* IN double buffered endpoint */
+ _SetENDPOINT(bEpNum, Endpoint_DTOG_Status & ~EPTX_DATTOG1);
+ }
+}
+
+/**
+ * @brief Returns the endpoint Tx status.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint TX Status
+ */
+uint16_t USB_GetEpTxSts(uint8_t bEpNum)
+{
+ return (_GetEPTxStatus(bEpNum));
+}
+
+/**
+ * @brief Returns the endpoint Rx status.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint RX Status
+ */
+uint16_t USB_GetEpRxSts(uint8_t bEpNum)
+{
+ return (_GetEPRxStatus(bEpNum));
+}
+
+/**
+ * @brief Valid the endpoint Tx Status.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_SetEpTxValid(uint8_t bEpNum)
+{
+ _SetEPTxStatus(bEpNum, EP_TX_VALID);
+}
+
+/**
+ * @brief Valid the endpoint Rx Status.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_SetEpRxValid(uint8_t bEpNum)
+{
+ _SetEPRxStatus(bEpNum, EP_RX_VALID);
+}
+
+/**
+ * @brief Clear the EP_KIND bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_SetEpKind(uint8_t bEpNum)
+{
+ _SetEP_KIND(bEpNum);
+}
+
+/**
+ * @brief set the EP_KIND bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrEpKind(uint8_t bEpNum)
+{
+ _ClearEP_KIND(bEpNum);
+}
+/**
+ * @brief Clear the Status Out of the related Endpoint
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrStsOut(uint8_t bEpNum)
+{
+ _ClearEP_KIND(bEpNum);
+}
+/**
+ * @brief Set the Status Out of the related Endpoint
+ * @param bEpNum Endpoint Number.
+ */
+void USB_SetStsOut(uint8_t bEpNum)
+{
+ _SetEP_KIND(bEpNum);
+}
+/**
+ * @brief Enable the double buffer feature for the endpoint.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_SetEpDoubleBufer(uint8_t bEpNum)
+{
+ _SetEP_KIND(bEpNum);
+}
+/**
+ * @brief Disable the double buffer feature for the endpoint.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrEpDoubleBufer(uint8_t bEpNum)
+{
+ _ClearEP_KIND(bEpNum);
+}
+/**
+ * @brief Returns the Stall status of the Tx endpoint.
+ * @param bEpNum Endpoint Number.
+ * @return Tx Stall status.
+ */
+uint16_t USB_GetTxStallSts(uint8_t bEpNum)
+{
+ return (_GetTxStallStatus(bEpNum));
+}
+/**
+ * @brief Returns the Stall status of the Rx endpoint.
+ * @param bEpNum Endpoint Number.
+ * @return Rx Stall status.
+ */
+uint16_t USB_GetRxStallSts(uint8_t bEpNum)
+{
+ return (_GetRxStallStatus(bEpNum));
+}
+/**
+ * @brief Clear the CTR_RX bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrEpCtrsRx(uint8_t bEpNum)
+{
+ _ClearEP_CTR_RX(bEpNum);
+}
+/**
+ * @brief Clear the CTR_TX bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrEpCtrsTx(uint8_t bEpNum)
+{
+ _ClearEP_CTR_TX(bEpNum);
+}
+/**
+ * @brief Toggle the DTOG_RX bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_DattogRx(uint8_t bEpNum)
+{
+ _ToggleDTOG_RX(bEpNum);
+}
+/**
+ * @brief Toggle the DTOG_TX bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_DattogTx(uint8_t bEpNum)
+{
+ _ToggleDTOG_TX(bEpNum);
+}
+/**
+ * @brief Clear the DTOG_RX bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrDattogRx(uint8_t bEpNum)
+{
+ _ClearDTOG_RX(bEpNum);
+}
+/**
+ * @brief Clear the DTOG_TX bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrDattogTx(uint8_t bEpNum)
+{
+ _ClearDTOG_TX(bEpNum);
+}
+/**
+ * @brief Set the endpoint address.
+ * @param bEpNum Endpoint Number.
+ * @param bAddr New endpoint address.
+ */
+void USB_SetEpAddress(uint8_t bEpNum, uint8_t bAddr)
+{
+ _SetEPAddress(bEpNum, bAddr);
+}
+/**
+ * @brief Get the endpoint address.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint address.
+ */
+uint8_t USB_GetEpAddress(uint8_t bEpNum)
+{
+ return (_GetEPAddress(bEpNum));
+}
+/**
+ * @brief Set the endpoint Tx buffer address.
+ * @param bEpNum Endpoint Number.
+ * @param wAddr new address.
+ */
+void USB_SetEpTxAddr(uint8_t bEpNum, uint16_t wAddr)
+{
+ _SetEPTxAddr(bEpNum, wAddr);
+}
+/**
+ * @brief Set the endpoint Rx buffer address.
+ * @param bEpNum Endpoint Number.
+ * @param wAddr new address.
+ */
+void USB_SetEpRxAddr(uint8_t bEpNum, uint16_t wAddr)
+{
+ _SetEPRxAddr(bEpNum, wAddr);
+}
+/**
+ * @brief Returns the endpoint Tx buffer address.
+ * @param bEpNum Endpoint Number.
+ * @return Rx buffer address.
+ */
+uint16_t USB_GetEpTxAddr(uint8_t bEpNum)
+{
+ return (_GetEPTxAddr(bEpNum));
+}
+/**
+ * @brief Returns the endpoint Rx buffer address.
+ * @param bEpNum Endpoint Number.
+ * @return Rx buffer address.
+ */
+uint16_t USB_GetEpRxAddr(uint8_t bEpNum)
+{
+ return (_GetEPRxAddr(bEpNum));
+}
+/**
+ * @brief Set the Tx count.
+ * @param bEpNum Endpoint Number.
+ * @param wCount new count value.
+ */
+void USB_SetEpTxCnt(uint8_t bEpNum, uint16_t wCount)
+{
+ _SetEPTxCount(bEpNum, wCount);
+}
+/**
+ * @brief Set the Count Rx Register value.
+ * @param pdwReg point to the register.
+ * @param wCount the new register value.
+ */
+void USB_SetEpCntRxReg(uint32_t* pdwReg, uint16_t wCount)
+{
+ _SetEPCountRxReg(dwReg, wCount);
+}
+/**
+ * @brief Set the Rx count.
+ * @param bEpNum Endpoint Number.
+ * @param wCount the new count value.
+ */
+void USB_SetEpRxCnt(uint8_t bEpNum, uint16_t wCount)
+{
+ _SetEPRxCount(bEpNum, wCount);
+}
+/**
+ * @brief Get the Tx count.
+ * @param bEpNum Endpoint Number.
+ * @return Tx count value.
+ */
+uint16_t USB_GetEpTxCnt(uint8_t bEpNum)
+{
+ return (_GetEPTxCount(bEpNum));
+}
+/**
+ * @brief Get the Rx count.
+ * @param bEpNum Endpoint Number.
+ * @return Rx count value.
+ */
+uint16_t USB_GetEpRxCnt(uint8_t bEpNum)
+{
+ return (_GetEPRxCount(bEpNum));
+}
+/**
+ * @brief Set the addresses of the buffer 0 and 1.
+ * @param bEpNum Endpoint Number.
+ * @param wBuf0Addr new address of buffer 0.
+ * @param wBuf1Addr new address of buffer 1.
+ */
+void USB_SetEpDblBuferAddr(uint8_t bEpNum, uint16_t wBuf0Addr, uint16_t wBuf1Addr)
+{
+ _SetEPDblBuffAddr(bEpNum, wBuf0Addr, wBuf1Addr);
+}
+/**
+ * @brief Set the Buffer 1 address.
+ * @param bEpNum Endpoint Number
+ * @param wBuf0Addr new address.
+ */
+void USB_SetEpDblBuf0Addr(uint8_t bEpNum, uint16_t wBuf0Addr)
+{
+ _SetEPDblBuf0Addr(bEpNum, wBuf0Addr);
+}
+/**
+ * @brief Set the Buffer 1 address.
+ * @param bEpNum Endpoint Number
+ * @param wBuf1Addr new address.
+ */
+void USB_SetEpDblBuf1Addr(uint8_t bEpNum, uint16_t wBuf1Addr)
+{
+ _SetEPDblBuf1Addr(bEpNum, wBuf1Addr);
+}
+/**
+ * @brief Returns the address of the Buffer 0.
+ * @param bEpNum Endpoint Number.
+ */
+uint16_t USB_GetEpDblBuf0Addr(uint8_t bEpNum)
+{
+ return (_GetEPDblBuf0Addr(bEpNum));
+}
+/**
+ * @brief Returns the address of the Buffer 1.
+ * @param bEpNum Endpoint Number.
+ * @return Address of the Buffer 1.
+ */
+uint16_t USB_GetEpDblBuf1Addr(uint8_t bEpNum)
+{
+ return (_GetEPDblBuf1Addr(bEpNum));
+}
+/**
+ * @brief Set the number of bytes for a double Buffer endpoint.
+ * @param bEpNum
+ * @param bDir
+ * @param wCount
+ */
+void USB_SetEpDblBuferCnt(uint8_t bEpNum, uint8_t bDir, uint16_t wCount)
+{
+ _SetEPDblBuffCount(bEpNum, bDir, wCount);
+}
+/**
+ * @brief Set the number of bytes in the buffer 0 of a double Buffer endpoint.
+ * @param bEpNum
+ * @param bDir
+ * @param wCount
+ */
+void USB_SetEpDblBuf0Cnt(uint8_t bEpNum, uint8_t bDir, uint16_t wCount)
+{
+ _SetEPDblBuf0Count(bEpNum, bDir, wCount);
+}
+/**
+ * @brief Set the number of bytes in the buffer 0 of a double Buffer endpoint.
+ * @param bEpNum
+ * @param bDir
+ * @param wCount
+ */
+void USB_SetEpDblBuf1Cnt(uint8_t bEpNum, uint8_t bDir, uint16_t wCount)
+{
+ _SetEPDblBuf1Count(bEpNum, bDir, wCount);
+}
+/**
+ * @brief Returns the number of byte received in the buffer 0 of a double Buffer endpoint.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint Buffer 0 count
+ */
+uint16_t USB_GetEpDblBuf0Cnt(uint8_t bEpNum)
+{
+ return (_GetEPDblBuf0Count(bEpNum));
+}
+/**
+ * @brief Returns the number of data received in the buffer 1 of a double Buffer endpoint.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint Buffer 1 count.
+ */
+uint16_t USB_GetEpDblBuf1Cnt(uint8_t bEpNum)
+{
+ return (_GetEPDblBuf1Count(bEpNum));
+}
+/**
+ * @brief gets direction of the double buffered endpoint
+ * @param bEpNum Endpoint Number.
+ * @return EP_DBUF_OUT, EP_DBUF_IN, EP_DBUF_ERR if the endpoint counter not yet programmed.
+ */
+EP_DBUF_DIR GetEPDblBufDir(uint8_t bEpNum)
+{
+ if ((uint16_t)(*_pEPRxCount(bEpNum) & 0xFC00) != 0)
+ return (EP_DBUF_OUT);
+ else if (((uint16_t)(*_pEPTxCount(bEpNum)) & 0x03FF) != 0)
+ return (EP_DBUF_IN);
+ else
+ return (EP_DBUF_ERR);
+}
+/**
+ * @brief free buffer used from the application realizing it to the line toggles
+ * bit SW_BUF in the double buffered endpoint register
+ * @param bEpNum
+ * @param bDir
+ */
+void USB_FreeUserBuf(uint8_t bEpNum, uint8_t bDir)
+{
+ if (bDir == EP_DBUF_OUT)
+ { /* OUT double buffered endpoint */
+ _ToggleDTOG_TX(bEpNum);
+ }
+ else if (bDir == EP_DBUF_IN)
+ { /* IN double buffered endpoint */
+ _ToggleDTOG_RX(bEpNum);
+ }
+}
+
+/**
+ * @brief merge two byte in a word.
+ * @param bh byte high
+ * @param bl bytes low.
+ * @return resulted word.
+ */
+uint16_t USB_ToWord(uint8_t bh, uint8_t bl)
+{
+ uint16_t wRet;
+ wRet = (uint16_t)bl | ((uint16_t)bh << 8);
+ return (wRet);
+}
+/**
+ * @brief Swap two byte in a word.
+ * @param wSwW word to Swap.
+ * @return resulted word.
+ */
+uint16_t USB_ByteSwap(uint16_t wSwW)
+{
+ uint8_t bTemp;
+ uint16_t wRet;
+ bTemp = (uint8_t)(wSwW & 0xff);
+ wRet = (wSwW >> 8) | ((uint16_t)bTemp << 8);
+ return (wRet);
+}
diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_sil.c b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_sil.c
new file mode 100644
index 0000000000..0cea2761dd
--- /dev/null
+++ b/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_sil.c
@@ -0,0 +1,83 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_sil.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "usb_lib.h"
+
+/**
+ * @brief Initialize the USB Device IP and the Endpoint 0.
+ * @return Status.
+ */
+uint32_t USB_SilInit(void)
+{
+ /* USB interrupts initialization */
+ /* clear pending interrupts */
+ _SetISTR(0);
+ wInterrupt_Mask = IMR_MSK;
+ /* set interrupts mask */
+ _SetCNTR(wInterrupt_Mask);
+ return 0;
+}
+
+/**
+ * @brief Write a buffer of data to a selected endpoint.
+ * @param bEpAddr The address of the non control endpoint.
+ * @param pBufferPointer The pointer to the buffer of data to be written to the endpoint.
+ * @param wBufferSize Number of data to be written (in bytes).
+ * @return Status.
+ */
+uint32_t USB_SilWrite(uint8_t bEpAddr, uint8_t* pBufferPointer, uint32_t wBufferSize)
+{
+ /* Use the memory interface function to write to the selected endpoint */
+ USB_CopyUserToPMABuf(pBufferPointer, USB_GetEpTxAddr(bEpAddr & 0x7F), wBufferSize);
+ /* Update the data length in the control register */
+ USB_SetEpTxCnt((bEpAddr & 0x7F), wBufferSize);
+ return 0;
+}
+
+/**
+ * @brief Write a buffer of data to a selected endpoint.
+ * @param bEpAddr The address of the non control endpoint.
+ * @param pBufferPointer The pointer to which will be saved the received data buffer.
+ * @return Number of received data (in Bytes).
+ */
+uint32_t USB_SilRead(uint8_t bEpAddr, uint8_t* pBufferPointer)
+{
+ uint32_t DataLength = 0;
+ /* Get the number of received data on the selected Endpoint */
+ DataLength = USB_GetEpRxCnt(bEpAddr & 0x7F);
+ /* Use the memory interface function to write to the selected endpoint */
+ USB_CopyPMAToUserBuf(pBufferPointer, USB_GetEpRxAddr(bEpAddr & 0x7F), DataLength);
+ /* Return the number of received data */
+ return DataLength;
+}
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/arm_math.h b/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/arm_math.h
index ea9dd26aa8..d6b5b2b1ce 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/arm_math.h
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/arm_math.h
@@ -77,7 +77,7 @@
* ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
* For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
* Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions.
- *
+ *
*
* Examples
* --------
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_armcc.h b/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_armcc.h
index 4d9d0645d3..a4c67e0268 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_armcc.h
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_armcc.h
@@ -58,9 +58,9 @@
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
-#ifndef __STATIC_FORCEINLINE
+#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
-#endif
+#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
@@ -443,7 +443,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
__schedule_barrier();\
} while (0U)
-
+
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_armclang.h b/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_armclang.h
index 162a400ea1..a1722f87a8 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_armclang.h
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_armclang.h
@@ -43,9 +43,9 @@
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
-#ifndef __STATIC_FORCEINLINE
+#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
-#endif
+#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((__noreturn__))
#endif
@@ -570,7 +570,7 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always in non-secure
mode.
-
+
\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
\return PSPLIM Register value
*/
@@ -616,7 +616,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence the write is silently ignored in non-secure
mode.
-
+
\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
*/
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_gcc.h b/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_gcc.h
index 2d9db15a5d..cd374afaef 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_gcc.h
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_gcc.h
@@ -46,9 +46,9 @@
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
-#ifndef __STATIC_FORCEINLINE
+#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
-#endif
+#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((__noreturn__))
#endif
@@ -585,7 +585,7 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always in non-secure
mode.
-
+
\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
\return PSPLIM Register value
*/
@@ -630,7 +630,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence the write is silently ignored in non-secure
mode.
-
+
\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
*/
@@ -767,7 +767,7 @@ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
-#if __has_builtin(__builtin_arm_get_fpscr)
+#if __has_builtin(__builtin_arm_get_fpscr)
// Re-enable using built-in when GCC has been fixed
// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/mpu_armv7.h b/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/mpu_armv7.h
index 01422033d0..be73de161f 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/mpu_armv7.h
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/mpu_armv7.h
@@ -21,13 +21,13 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
-
+
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
-
+
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
@@ -79,12 +79,12 @@
/**
* MPU Memory Access Attributes
-*
+*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
-*/
+*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
@@ -93,7 +93,7 @@
/**
* MPU Region Attribute and Size Register Value
-*
+*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
@@ -104,10 +104,10 @@
((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
-
+
/**
* MPU Region Attribute and Size Register Value
-*
+*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
@@ -116,7 +116,7 @@
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
-*/
+*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
@@ -126,7 +126,7 @@
* - Shareable
* - Non-cacheable
* - Non-bufferable
-*/
+*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
@@ -137,7 +137,7 @@
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
-*/
+*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
@@ -150,7 +150,7 @@
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
-*/
+*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
/**
@@ -181,7 +181,7 @@ typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
-
+
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
@@ -219,7 +219,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
-*/
+*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
@@ -230,7 +230,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
-*/
+*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
@@ -246,7 +246,7 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t r
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
- for (i = 0U; i < len; ++i)
+ for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
@@ -256,7 +256,7 @@ __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRI
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
-__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/n32g45x.h b/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/n32g45x.h
index 43f69b5ce3..e75cdbb488 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/n32g45x.h
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/n32g45x.h
@@ -1044,8 +1044,8 @@ typedef struct
__IO uint32_t DMA_CTRL;
__IO uint32_t DMATDL_CTRL;
__IO uint32_t DMARDL_CTRL;
- __IO uint32_t IDCODE;
- __IO uint32_t RESERVED;
+ __IO uint32_t RESERVED0;
+ __IO uint32_t RESERVED1;
__IO uint32_t DAT0;
__IO uint32_t DAT1;
__IO uint32_t DAT2;
@@ -7910,58 +7910,58 @@ typedef struct
#define QSPI_CTRL0_DFS_2 ((uint32_t)0x00000004) /*!< Bit 2 */
#define QSPI_CTRL0_DFS_3 ((uint32_t)0x00000008) /*!< Bit 3 */
#define QSPI_CTRL0_DFS_4 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define QSPI_CTRL0_DFS_4_BIT ((uint32_t)0x00000003)
-#define QSPI_CTRL0_DFS_5_BIT ((uint32_t)0x00000004)
-#define QSPI_CTRL0_DFS_6_BIT ((uint32_t)0x00000005)
-#define QSPI_CTRL0_DFS_7_BIT ((uint32_t)0x00000006)
-#define QSPI_CTRL0_DFS_8_BIT ((uint32_t)0x00000007)
-#define QSPI_CTRL0_DFS_9_BIT ((uint32_t)0x00000008)
-#define QSPI_CTRL0_DFS_10_BIT ((uint32_t)0x00000009)
-#define QSPI_CTRL0_DFS_11_BIT ((uint32_t)0x0000000A)
-#define QSPI_CTRL0_DFS_12_BIT ((uint32_t)0x0000000B)
-#define QSPI_CTRL0_DFS_13_BIT ((uint32_t)0x0000000C)
-#define QSPI_CTRL0_DFS_14_BIT ((uint32_t)0x0000000D)
-#define QSPI_CTRL0_DFS_15_BIT ((uint32_t)0x0000000E)
-#define QSPI_CTRL0_DFS_16_BIT ((uint32_t)0x0000000F)
-#define QSPI_CTRL0_DFS_17_BIT ((uint32_t)0x00000010)
-#define QSPI_CTRL0_DFS_18_BIT ((uint32_t)0x00000011)
-#define QSPI_CTRL0_DFS_19_BIT ((uint32_t)0x00000012)
-#define QSPI_CTRL0_DFS_20_BIT ((uint32_t)0x00000013)
-#define QSPI_CTRL0_DFS_21_BIT ((uint32_t)0x00000014)
-#define QSPI_CTRL0_DFS_22_BIT ((uint32_t)0x00000015)
-#define QSPI_CTRL0_DFS_23_BIT ((uint32_t)0x00000016)
-#define QSPI_CTRL0_DFS_24_BIT ((uint32_t)0x00000017)
-#define QSPI_CTRL0_DFS_25_BIT ((uint32_t)0x00000018)
-#define QSPI_CTRL0_DFS_26_BIT ((uint32_t)0x00000019)
-#define QSPI_CTRL0_DFS_27_BIT ((uint32_t)0x0000001A)
-#define QSPI_CTRL0_DFS_28_BIT ((uint32_t)0x0000001B)
-#define QSPI_CTRL0_DFS_29_BIT ((uint32_t)0x0000001C)
-#define QSPI_CTRL0_DFS_30_BIT ((uint32_t)0x0000001D)
-#define QSPI_CTRL0_DFS_31_BIT ((uint32_t)0x0000001E)
-#define QSPI_CTRL0_DFS_32_BIT ((uint32_t)0x0000001F)
+#define QSPI_CTRL0_DFS_4_BIT ((uint32_t)0x00000003)
+#define QSPI_CTRL0_DFS_5_BIT ((uint32_t)0x00000004)
+#define QSPI_CTRL0_DFS_6_BIT ((uint32_t)0x00000005)
+#define QSPI_CTRL0_DFS_7_BIT ((uint32_t)0x00000006)
+#define QSPI_CTRL0_DFS_8_BIT ((uint32_t)0x00000007)
+#define QSPI_CTRL0_DFS_9_BIT ((uint32_t)0x00000008)
+#define QSPI_CTRL0_DFS_10_BIT ((uint32_t)0x00000009)
+#define QSPI_CTRL0_DFS_11_BIT ((uint32_t)0x0000000A)
+#define QSPI_CTRL0_DFS_12_BIT ((uint32_t)0x0000000B)
+#define QSPI_CTRL0_DFS_13_BIT ((uint32_t)0x0000000C)
+#define QSPI_CTRL0_DFS_14_BIT ((uint32_t)0x0000000D)
+#define QSPI_CTRL0_DFS_15_BIT ((uint32_t)0x0000000E)
+#define QSPI_CTRL0_DFS_16_BIT ((uint32_t)0x0000000F)
+#define QSPI_CTRL0_DFS_17_BIT ((uint32_t)0x00000010)
+#define QSPI_CTRL0_DFS_18_BIT ((uint32_t)0x00000011)
+#define QSPI_CTRL0_DFS_19_BIT ((uint32_t)0x00000012)
+#define QSPI_CTRL0_DFS_20_BIT ((uint32_t)0x00000013)
+#define QSPI_CTRL0_DFS_21_BIT ((uint32_t)0x00000014)
+#define QSPI_CTRL0_DFS_22_BIT ((uint32_t)0x00000015)
+#define QSPI_CTRL0_DFS_23_BIT ((uint32_t)0x00000016)
+#define QSPI_CTRL0_DFS_24_BIT ((uint32_t)0x00000017)
+#define QSPI_CTRL0_DFS_25_BIT ((uint32_t)0x00000018)
+#define QSPI_CTRL0_DFS_26_BIT ((uint32_t)0x00000019)
+#define QSPI_CTRL0_DFS_27_BIT ((uint32_t)0x0000001A)
+#define QSPI_CTRL0_DFS_28_BIT ((uint32_t)0x0000001B)
+#define QSPI_CTRL0_DFS_29_BIT ((uint32_t)0x0000001C)
+#define QSPI_CTRL0_DFS_30_BIT ((uint32_t)0x0000001D)
+#define QSPI_CTRL0_DFS_31_BIT ((uint32_t)0x0000001E)
+#define QSPI_CTRL0_DFS_32_BIT ((uint32_t)0x0000001F)
#define QSPI_CTRL0_FRF ((uint32_t)0x000000C0) /*!< FRF[1:0] bits (Frame Format) */
#define QSPI_CTRL0_FRF_0 ((uint32_t)0x00000040) /*!< Bit 0 */
#define QSPI_CTRL0_FRF_1 ((uint32_t)0x00000080) /*!< Bit 1 */
-#define QSPI_CTRL0_FRF_MOTOROLA ((uint32_t)0x00000000)
-#define QSPI_CTRL0_FRF_TI ((uint32_t)0x00000040)
-#define QSPI_CTRL0_FRF_MICROWIRE ((uint32_t)0x00000080)
+#define QSPI_CTRL0_FRF_MOTOROLA ((uint32_t)0x00000000)
+#define QSPI_CTRL0_FRF_TI ((uint32_t)0x00000040)
+#define QSPI_CTRL0_FRF_MICROWIRE ((uint32_t)0x00000080)
#define QSPI_CTRL0_SCPH ((uint32_t)0x00000100) /*!< SCPH (Serial Clock Phase) */
-#define QSPI_CTRL0_SCPH_FIRST_EDGE ((uint32_t)0x00000000)
-#define QSPI_CTRL0_SCPH_SECOND_EDGE ((uint32_t)0x00000100)
+#define QSPI_CTRL0_SCPH_FIRST_EDGE ((uint32_t)0x00000000)
+#define QSPI_CTRL0_SCPH_SECOND_EDGE ((uint32_t)0x00000100)
#define QSPI_CTRL0_SCPOL ((uint32_t)0x00000200) /*!< SCPOL(Serial Clock Polarity) */
-#define QSPI_CTRL0_SCPOL_LOW ((uint32_t)0x00000000)
-#define QSPI_CTRL0_SCPOL_HIGH ((uint32_t)0x00000200)
+#define QSPI_CTRL0_SCPOL_LOW ((uint32_t)0x00000000)
+#define QSPI_CTRL0_SCPOL_HIGH ((uint32_t)0x00000200)
#define QSPI_CTRL0_TMOD ((uint32_t)0x00000C00) /*!< TMOD[1:0] bits (Transfer Mode) */
#define QSPI_CTRL0_TMOD_0 ((uint32_t)0x00000400) /*!< Bit 0 */
#define QSPI_CTRL0_TMOD_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define QSPI_CTRL0_TMOD_TX_AND_RX ((uint32_t)0x00000000)
-#define QSPI_CTRL0_TMOD_TX_ONLY ((uint32_t)0x00000400)
-#define QSPI_CTRL0_TMOD_RX_ONLY ((uint32_t)0x00000800)
-#define QSPI_CTRL0_TMOD_EEPROM_READ ((uint32_t)0x00000C00)
+#define QSPI_CTRL0_TMOD_TX_AND_RX ((uint32_t)0x00000000)
+#define QSPI_CTRL0_TMOD_TX_ONLY ((uint32_t)0x00000400)
+#define QSPI_CTRL0_TMOD_RX_ONLY ((uint32_t)0x00000800)
+#define QSPI_CTRL0_TMOD_EEPROM_READ ((uint32_t)0x00000C00)
#define QSPI_CTRL0_SRL_EN ((uint32_t)0x00002000) /*!< SRL (Shift Register Loop) */
#define QSPI_CTRL0_SSTE_EN ((uint32_t)0x00004000) /*!< SSTE(Slave Select Toggle Enable) */
@@ -7971,29 +7971,29 @@ typedef struct
#define QSPI_CTRL0_CFS_1 ((uint32_t)0x00020000) /*!< Bit 1 */
#define QSPI_CTRL0_CFS_2 ((uint32_t)0x00040000) /*!< Bit 2 */
#define QSPI_CTRL0_CFS_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define QSPI_CTRL0_CFS_1_BIT ((uint32_t)0x00000000)
-#define QSPI_CTRL0_CFS_2_BIT ((uint32_t)0x00010000)
-#define QSPI_CTRL0_CFS_3_BIT ((uint32_t)0x00020000)
-#define QSPI_CTRL0_CFS_4_BIT ((uint32_t)0x00030000)
-#define QSPI_CTRL0_CFS_5_BIT ((uint32_t)0x00040000)
-#define QSPI_CTRL0_CFS_6_BIT ((uint32_t)0x00050000)
-#define QSPI_CTRL0_CFS_7_BIT ((uint32_t)0x00060000)
-#define QSPI_CTRL0_CFS_8_BIT ((uint32_t)0x00070000)
-#define QSPI_CTRL0_CFS_9_BIT ((uint32_t)0x00080000)
-#define QSPI_CTRL0_CFS_10_BIT ((uint32_t)0x00090000)
-#define QSPI_CTRL0_CFS_11_BIT ((uint32_t)0x000A0000)
-#define QSPI_CTRL0_CFS_12_BIT ((uint32_t)0x000B0000)
-#define QSPI_CTRL0_CFS_13_BIT ((uint32_t)0x000C0000)
-#define QSPI_CTRL0_CFS_14_BIT ((uint32_t)0x000D0000)
-#define QSPI_CTRL0_CFS_15_BIT ((uint32_t)0x000E0000)
-#define QSPI_CTRL0_CFS_16_BIT ((uint32_t)0x000F0000)
+#define QSPI_CTRL0_CFS_1_BIT ((uint32_t)0x00000000)
+#define QSPI_CTRL0_CFS_2_BIT ((uint32_t)0x00010000)
+#define QSPI_CTRL0_CFS_3_BIT ((uint32_t)0x00020000)
+#define QSPI_CTRL0_CFS_4_BIT ((uint32_t)0x00030000)
+#define QSPI_CTRL0_CFS_5_BIT ((uint32_t)0x00040000)
+#define QSPI_CTRL0_CFS_6_BIT ((uint32_t)0x00050000)
+#define QSPI_CTRL0_CFS_7_BIT ((uint32_t)0x00060000)
+#define QSPI_CTRL0_CFS_8_BIT ((uint32_t)0x00070000)
+#define QSPI_CTRL0_CFS_9_BIT ((uint32_t)0x00080000)
+#define QSPI_CTRL0_CFS_10_BIT ((uint32_t)0x00090000)
+#define QSPI_CTRL0_CFS_11_BIT ((uint32_t)0x000A0000)
+#define QSPI_CTRL0_CFS_12_BIT ((uint32_t)0x000B0000)
+#define QSPI_CTRL0_CFS_13_BIT ((uint32_t)0x000C0000)
+#define QSPI_CTRL0_CFS_14_BIT ((uint32_t)0x000D0000)
+#define QSPI_CTRL0_CFS_15_BIT ((uint32_t)0x000E0000)
+#define QSPI_CTRL0_CFS_16_BIT ((uint32_t)0x000F0000)
#define QSPI_CTRL0_SPI_FRF ((uint32_t)0x00C00000) /*!< SPI_FRF[1:0] bits (SPI Frame Format) */
#define QSPI_CTRL0_SPI_FRF_0 ((uint32_t)0x00400000) /*!< Bit 0 */
#define QSPI_CTRL0_SPI_FRF_1 ((uint32_t)0x00800000) /*!< Bit 1 */
-#define QSPI_CTRL0_SPI_FRF_STANDARD_FORMAT ((uint32_t)0x00000000)
-#define QSPI_CTRL0_SPI_FRF_DUAL_FORMAT ((uint32_t)0x00400000)
-#define QSPI_CTRL0_SPI_FRF_QUAD_FORMAT ((uint32_t)0x00800000)
+#define QSPI_CTRL0_SPI_FRF_STANDARD_FORMAT ((uint32_t)0x00000000)
+#define QSPI_CTRL0_SPI_FRF_DUAL_FORMAT ((uint32_t)0x00400000)
+#define QSPI_CTRL0_SPI_FRF_QUAD_FORMAT ((uint32_t)0x00800000)
/******************* Bit definition for QSPI_CTRL1 register *******************/
#define QSPI_CTRL1_NDF ((uint32_t)0x0000FFFF) /*!< NDF[15:0] bits (Numver of Data Frames) */
@@ -8019,12 +8019,12 @@ typedef struct
/******************* Bit definition for QSPI_MW_CTRL register *******************/
#define QSPI_MW_CTRL_MWMOD ((uint32_t)0x00000001) /*!< MWMO (Microwire Transfer Mode) */
-#define QSPI_MW_CTRL_MWMOD_UNSEQUENTIAL ((uint32_t)0x00000000)
-#define QSPI_MW_CTRL_MWMOD_SEQUENTIAL ((uint32_t)0x00000001)
+#define QSPI_MW_CTRL_MWMOD_UNSEQUENTIAL ((uint32_t)0x00000000)
+#define QSPI_MW_CTRL_MWMOD_SEQUENTIAL ((uint32_t)0x00000001)
#define QSPI_MW_CTRL_MC_DIR ((uint32_t)0x00000002) /*!< MC_DIR (Direction of Data when Microwire Control) */
-#define QSPI_MW_CTRL_MC_DIR_RX ((uint32_t)0x00000000)
-#define QSPI_MW_CTRL_MC_DIR_TX ((uint32_t)0x00000002)
+#define QSPI_MW_CTRL_MC_DIR_RX ((uint32_t)0x00000000)
+#define QSPI_MW_CTRL_MC_DIR_TX ((uint32_t)0x00000002)
#define QSPI_MW_CTRL_MHS_EN ((uint32_t)0x00000004) /*!< MHS_EN (Microwire Handshaking Enable) */
@@ -8098,8 +8098,7 @@ typedef struct
#define QSPI_STS_TXFE ((uint32_t)0x00000004) /*!< TXFE (Transmit FIFO not Empty) */
#define QSPI_STS_RXFNE ((uint32_t)0x00000008) /*!< RXFNE (Receive FIFO not Empty) */
#define QSPI_STS_RXFF ((uint32_t)0x00000010) /*!< RXFF (Receive FIFO not Full) */
-#define QSPI_STS_TX_ERR ((uint32_t)0x00000020) /*!< TX_ERR (Transmit Error) */
-#define QSPI_STS_DC_ERR ((uint32_t)0x00000040) /*!< DC_ERR (Data Conflict Error) */
+#define QSPI_STS_DC_ERR ((uint32_t)0x00000040) /*!< DC_ERR (Data Conflict Error) */
/******************* Bit definition for QSPI_IMASK register *******************/
#define QSPI_IMASK ((uint32_t)0x0000007F) /*!< IMASK[6:0] (Interrupt of Mask) */
@@ -8168,41 +8167,6 @@ typedef struct
#define QSPI_DMARDL_CTRL_DMARDL_4 ((uint32_t)0x00000010) /*!< Bit 4 */
#define QSPI_DMARDL_CTRL_DMARDL_5 ((uint32_t)0x00000020) /*!< Bit 5 */
-/******************* Bit definition for QSPI_IDCODE register *******************/
-#define QSPI_IDCODE ((uint32_t)0x0000FFFF) /*!< IDCODE[31:0] (Identification Code) */
-#define QSPI_IDCODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define QSPI_IDCODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define QSPI_IDCODE_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define QSPI_IDCODE_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define QSPI_IDCODE_4 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define QSPI_IDCODE_5 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define QSPI_IDCODE_6 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define QSPI_IDCODE_7 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define QSPI_IDCODE_8 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define QSPI_IDCODE_9 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define QSPI_IDCODE_10 ((uint32_t)0x00000400) /*!< Bit 10 */
-#define QSPI_IDCODE_11 ((uint32_t)0x00000800) /*!< Bit 11 */
-#define QSPI_IDCODE_12 ((uint32_t)0x00001000) /*!< Bit 12 */
-#define QSPI_IDCODE_13 ((uint32_t)0x00002000) /*!< Bit 13 */
-#define QSPI_IDCODE_14 ((uint32_t)0x00004000) /*!< Bit 14 */
-#define QSPI_IDCODE_15 ((uint32_t)0x00008000) /*!< Bit 15 */
-#define QSPI_IDCODE_16 ((uint32_t)0x00010000) /*!< Bit 16 */
-#define QSPI_IDCODE_17 ((uint32_t)0x00020000) /*!< Bit 17 */
-#define QSPI_IDCODE_18 ((uint32_t)0x00040000) /*!< Bit 18 */
-#define QSPI_IDCODE_19 ((uint32_t)0x00080000) /*!< Bit 19 */
-#define QSPI_IDCODE_20 ((uint32_t)0x00100000) /*!< Bit 20 */
-#define QSPI_IDCODE_21 ((uint32_t)0x00200000) /*!< Bit 21 */
-#define QSPI_IDCODE_22 ((uint32_t)0x00400000) /*!< Bit 22 */
-#define QSPI_IDCODE_23 ((uint32_t)0x00800000) /*!< Bit 23 */
-#define QSPI_IDCODE_24 ((uint32_t)0x01000000) /*!< Bit 24 */
-#define QSPI_IDCODE_25 ((uint32_t)0x02000000) /*!< Bit 25 */
-#define QSPI_IDCODE_26 ((uint32_t)0x04000000) /*!< Bit 26 */
-#define QSPI_IDCODE_27 ((uint32_t)0x08000000) /*!< Bit 27 */
-#define QSPI_IDCODE_28 ((uint32_t)0x10000000) /*!< Bit 28 */
-#define QSPI_IDCODE_29 ((uint32_t)0x20000000) /*!< Bit 29 */
-#define QSPI_IDCODE_30 ((uint32_t)0x40000000) /*!< Bit 30 */
-#define QSPI_IDCODE_31 ((uint32_t)0x80000000) /*!< Bit 31 */
-
/******************* Bit definition for QSPI_DAT0~QSPI_DAT31 register *******************/
#define QSPI_DATA_ALL ((uint32_t)0x0000FFFF) /*!< QSPI_DAT[31:0] (DATA Register) */
#define QSPI_DATA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
@@ -8248,24 +8212,24 @@ typedef struct
#define QSPI_RS_DELAY_SDCN_5 ((uint32_t)0x00000020) /*!< Bit 5 */
#define QSPI_RS_DELAY_SDCN_6 ((uint32_t)0x00000040) /*!< Bit 6 */
#define QSPI_RS_DELAY_SDCN_7 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define QSPI_RS_DELAY_SDCN_0_CYCLES ((uint32_t)0x00000000)
-#define QSPI_RS_DELAY_SDCN_1_CYCLES ((uint32_t)0x00000001)
-#define QSPI_RS_DELAY_SDCN_2_CYCLES ((uint32_t)0x00000002)
-#define QSPI_RS_DELAY_SDCN_3_CYCLES ((uint32_t)0x00000003)
-#define QSPI_RS_DELAY_SDCN_4_CYCLES ((uint32_t)0x00000004)
-#define QSPI_RS_DELAY_SDCN_5_CYCLES ((uint32_t)0x00000005)
-#define QSPI_RS_DELAY_SDCN_6_CYCLES ((uint32_t)0x00000006)
+#define QSPI_RS_DELAY_SDCN_0_CYCLES ((uint32_t)0x00000000)
+#define QSPI_RS_DELAY_SDCN_1_CYCLES ((uint32_t)0x00000001)
+#define QSPI_RS_DELAY_SDCN_2_CYCLES ((uint32_t)0x00000002)
+#define QSPI_RS_DELAY_SDCN_3_CYCLES ((uint32_t)0x00000003)
+#define QSPI_RS_DELAY_SDCN_4_CYCLES ((uint32_t)0x00000004)
+#define QSPI_RS_DELAY_SDCN_5_CYCLES ((uint32_t)0x00000005)
+#define QSPI_RS_DELAY_SDCN_6_CYCLES ((uint32_t)0x00000006)
-#define QSPI_RS_DELAY_SES ((uint32_t)0x00010000) /*!< SES (Sample Edge Select of Receive Data) */
-#define QSPI_RS_DELAY_SES_RISING_EDGE ((uint32_t)0x00000000)
-#define QSPI_RS_DELAY_SES_FALLING_EDGE ((uint32_t)0x00010000)
+#define QSPI_RS_DELAY_SES ((uint32_t)0x00010000) /*!< SES (Sample Edge Select of Receive Data) */
+#define QSPI_RS_DELAY_SES_RISING_EDGE ((uint32_t)0x00000000)
+#define QSPI_RS_DELAY_SES_FALLING_EDGE ((uint32_t)0x00010000)
/******************* Bit definition for QSPI_ENH_CTRL0 register *******************/
#define QSPI_ENH_CTRL0_TRANS_TYPE ((uint32_t)0x00000003) /*!< TRANS_TYPE[1:0] (Address and instruction transfer format) */
#define QSPI_ENH_CTRL0_TRANS_TYPE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define QSPI_ENH_CTRL0_TRANS_TYPE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define QSPI_ENH_CTRL0_TRANS_TYPE_STANDARD ((uint32_t)0x00000000)
-#define QSPI_ENH_CTRL0_TRANS_TYPE_ADDRESS_BY_FRF ((uint32_t)0x00000001)
-#define QSPI_ENH_CTRL0_TRANS_TYPE_ALL_BY_FRF ((uint32_t)0x00000002)
+#define QSPI_ENH_CTRL0_TRANS_TYPE_STANDARD ((uint32_t)0x00000000)
+#define QSPI_ENH_CTRL0_TRANS_TYPE_ADDRESS_BY_FRF ((uint32_t)0x00000001)
+#define QSPI_ENH_CTRL0_TRANS_TYPE_ALL_BY_FRF ((uint32_t)0x00000002)
#define QSPI_ENH_CTRL0_ADDR_LEN ((uint32_t)0x0000003C) /*!< ADDR_LEN[3:0] (Length of Address to transmit) */
#define QSPI_ENH_CTRL0_ADDR_LEN_0 ((uint32_t)0x00000004) /*!< Bit 0 */
@@ -8288,15 +8252,13 @@ typedef struct
#define QSPI_ENH_CTRL0_ADDR_LEN_56_BIT ((uint32_t)0x00000038)
#define QSPI_ENH_CTRL0_ADDR_LEN_60_BIT ((uint32_t)0x0000003C)
-#define QSPI_ENH_CTRL0_MD_BIT_EN ((uint32_t)0x00000080) /*!< MD_BIT_EN (Mode bits enable in XIP mode) */
-
#define QSPI_ENH_CTRL0_INST_L ((uint32_t)0x00000300) /*!< INST_L[1:0] (Dual/Quad mode instruction length in bits) */
#define QSPI_ENH_CTRL0_INST_L_0 ((uint32_t)0x00000100) /*!< Bit 0 */
#define QSPI_ENH_CTRL0_INST_L_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define QSPI_ENH_CTRL0_INST_L_0_LINE ((uint32_t)0x00000000)
-#define QSPI_ENH_CTRL0_INST_L_4_LINE ((uint32_t)0x00000100)
-#define QSPI_ENH_CTRL0_INST_L_8_LINE ((uint32_t)0x00000200)
-#define QSPI_ENH_CTRL0_INST_L_16_LINE ((uint32_t)0x00000300)
+#define QSPI_ENH_CTRL0_INST_L_0_LINE ((uint32_t)0x00000000)
+#define QSPI_ENH_CTRL0_INST_L_4_LINE ((uint32_t)0x00000100)
+#define QSPI_ENH_CTRL0_INST_L_8_LINE ((uint32_t)0x00000200)
+#define QSPI_ENH_CTRL0_INST_L_16_LINE ((uint32_t)0x00000300)
#define QSPI_ENH_CTRL0_WAIT_CYCLES ((uint32_t)0x0000F800) /*!< WAIT_CYCLES[4:0] (Wait Cycles in Dual/Quad mode between control frames transmit and data reception) */
#define QSPI_ENH_CTRL0_WAIT_CYCLES_0 ((uint32_t)0x00000800) /*!< Bit 0 */
@@ -8336,23 +8298,10 @@ typedef struct
#define QSPI_ENH_CTRL0_WAIT_30CYCLES ((uint32_t)0x0000F000)
#define QSPI_ENH_CTRL0_WAIT_31CYCLES ((uint32_t)0x0000F800)
-
#define QSPI_ENH_CTRL0_SPI_DDR_EN ((uint32_t)0x00010000) /*!< SPI_DDR_EN (SPI DDR Enable) */
#define QSPI_ENH_CTRL0_INST_DDR_EN ((uint32_t)0x00020000) /*!< INST_DDR_EN (XIP instruction enable) */
-#define QSPI_ENH_CTRL0_XIP_DFS_HC ((uint32_t)0x00080000) /*!< XIP_DFS_HC (Fix DFS for XIP transfers) */
-#define QSPI_ENH_CTRL0_XIP_INST_EN ((uint32_t)0x00100000) /*!< XIP_INST_EN (XIP instruction enable) */
-#define QSPI_ENH_CTRL0_XIP_CT_EN ((uint32_t)0x00200000) /*!< XIP_CT_EN (Enable Continuous Transfer in XIP mode) */
-#define QSPI_ENH_CTRL0_XIP_MBL ((uint32_t)0x0C000000) /*!< XIP_MBL[1:0] (XIP Mode bits length) */
-#define QSPI_ENH_CTRL0_XIP_MBL_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define QSPI_ENH_CTRL0_XIP_MBL_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define QSPI_ENH_CTRL0_XIP_MBL_2_BIT ((uint32_t)0x00000000)
-#define QSPI_ENH_CTRL0_XIP_MBL_4_BIT ((uint32_t)0x04000000)
-#define QSPI_ENH_CTRL0_XIP_MBL_8_BIT ((uint32_t)0x08000000)
-#define QSPI_ENH_CTRL0_XIP_MBL_16_BIT ((uint32_t)0x0C000000)
-
-
-#define QSPI_ENH_CTRL0_CLK_STRETCH_EN ((uint32_t)0x40000000) /*!< CLK_STRETCH_EN (Enable Continuous Transfer in XIP mode) */
+#define QSPI_ENH_CTRL0_CLK_STRETCH_EN ((uint32_t)0x40000000) /*!< CLK_STRETCH_EN (Enable clock stretch capablity in SPI tramsfers) */
/******************* Bit definition for QSPI_DDR_TXDE register *******************/
#define QSPI_DDR_TXDE ((uint32_t)0x000000FF) /*!< TXDE[7:0] (Transmit Drive Edge) */
@@ -9022,17 +8971,17 @@ typedef struct
*/
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
-
+
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
-
+
#define READ_BIT(REG, BIT) ((REG) & (BIT))
-
+
#define CLEAR_REG(REG) ((REG) = (0x0))
-
+
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
-
+
#define READ_REG(REG) ((REG))
-
+
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
/**
* @}
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/startup/startup_n32g45x_gcc.s b/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/startup/startup_n32g45x_gcc.s
index fa81b7cc64..013e739c93 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/startup/startup_n32g45x_gcc.s
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/startup/startup_n32g45x_gcc.s
@@ -57,7 +57,7 @@ defined in linker script */
* @retval : None
*/
- .section .text.Reset_Handler
+ .section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/system_n32g45x.c b/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/system_n32g45x.c
index 64a14f0016..3699bb882b 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/system_n32g45x.c
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/system_n32g45x.c
@@ -171,10 +171,10 @@ void SystemInit(void)
RCC->CFG &= (uint32_t)0xF700FFFF;
/* Reset CFG2 register */
- RCC->CFG2 = 0x00000000;
+ RCC->CFG2 = 0x00003800;
/* Reset CFG3 register */
- RCC->CFG3 = 0x00000000;
+ RCC->CFG3 = 0x00003840;
/* Disable all interrupts and clear pending bits */
RCC->CLKINT = 0x009F0000;
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_aes.h b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_aes.h
index 427a5f7941..3c6210773b 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_aes.h
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_aes.h
@@ -44,7 +44,7 @@
* @brief AES symmetrical cipher algorithm
* @{
*/
-
+
#define AES_ECB (0x11111111)
#define AES_CBC (0x22222222)
#define AES_CTR (0x33333333)
@@ -58,7 +58,7 @@ enum
AES_Init_OK = 0x0, //AES Init opreation success
AES_Crypto_ModeError = 0x5a5a5a5a, //Working mode error(Neither ECB nor CBC nor CTR)
AES_Crypto_EnOrDeError, //En&De error(Neither encryption nor decryption)
- AES_Crypto_ParaNull, // the part of input(output/iv) Null
+ AES_Crypto_ParaNull, // the part of input(output/iv) Null
AES_Crypto_LengthError, // if Working mode is ECB or CBC,the length of input message must be 4 times and cannot be zero;
//if Working mode is CTR,the length of input message cannot be zero; othets: return AES_Crypto_LengthError
@@ -81,7 +81,7 @@ typedef struct
/**
* @brief AES_Init
* @return AES_Init_OK, AES Init success; othets: AES Init fail
- * @note
+ * @note
*/
uint32_t AES_Init(AES_PARM *parm);
@@ -89,8 +89,8 @@ uint32_t AES_Init(AES_PARM *parm);
/**
* @brief AES crypto
* @param[in] parm pointer to AES context and the detail please refer to struct AES_PARM in AES.h
- * @return AES_Crypto_OK, AES crypto success; othets: AES crypto fail(reference to the definition by enum variation)
- * @note 1.Please refer to the demo in user guidance before using this function
+ * @return AES_Crypto_OK, AES crypto success; othets: AES crypto fail(reference to the definition by enum variation)
+ * @note 1.Please refer to the demo in user guidance before using this function
* 2.Input and output can be the same buffer
* 3. IV can be NULL when ECB mode
* 4. If Working mode is ECB or CBC,the length of input message must be 4 times and cannot be zero;
@@ -111,7 +111,7 @@ void AES_Close(void);
* @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
* @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
* @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
- * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
+ * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
* @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
* @return none
* @1.You can recall this function to get AES lib information
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_algo_common.h b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_algo_common.h
index ebc78a2548..2c8901426d 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_algo_common.h
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_algo_common.h
@@ -55,7 +55,7 @@ enum{
* @param[in] rand pointer to random number
* @param[in] the length of order
* @return RandomSort_OK: disturb order success; Others: disturb order fail;
- * @note
+ * @note
*/
uint32_t RandomSort(uint8_t *order, const uint8_t *rand, uint32_t len);
@@ -63,7 +63,7 @@ uint32_t RandomSort(uint8_t *order, const uint8_t *rand, uint32_t len);
* @brief Copy data by byte
* @param[in] dst pointer to destination data
* @param[in] src pointer to source data
- * @param[in] byte length
+ * @param[in] byte length
* @return Cpy_OK: success; others: fail.
* @note 1. dst and src cannot be same
*/
@@ -73,7 +73,7 @@ uint32_t Cpy_U8(uint8_t *dst, uint8_t *src, uint32_t byteLen);
* @brief Copy data by word
* @param[in] dst pointer to destination data
* @param[in] src pointer to source data
- * @param[in] word length
+ * @param[in] word length
* @return Cpy_OK: success; others: fail.
* @note 1. dst and src must be aligned by word
*/
@@ -85,7 +85,7 @@ uint32_t Cpy_U32(uint32_t *dst, const uint32_t *src, uint32_t wordLen);
* @param[in] b pointer to another data to be XORed
* @param[in] the length of order
* @return XOR_OK: operation success; Others: operation fail;
- * @note
+ * @note
*/
uint32_t XOR_U8(uint8_t *a, uint8_t *b, uint8_t *c, uint32_t byteLen);
@@ -95,33 +95,33 @@ uint32_t XOR_U8(uint8_t *a, uint8_t *b, uint8_t *c, uint32_t byteLen);
* @param[in] b pointer to another data to be XORed
* @param[in] the length of order
* @return XOR_OK: operation success; Others: operation fail;
- * @note
+ * @note
*/
uint32_t XOR_U32(uint32_t *a,uint32_t *b,uint32_t *c,uint32_t wordLen);
/**
* @brief set zero by byte
- * @param[in] dst pointer to the address to be set zero
- * @param[in] byte length
+ * @param[in] dst pointer to the address to be set zero
+ * @param[in] byte length
* @return SetZero_OK: success; others: fail.
- * @note
+ * @note
*/
uint32_t SetZero_U8(uint8_t *dst, uint32_t byteLen);
/**
* @brief set zero by word
- * @param[in] dst pointer to the address to be set zero
- * @param[in] word length
+ * @param[in] dst pointer to the address to be set zero
+ * @param[in] word length
* @return SetZero_OK: success; others: fail.
- * @note
+ * @note
*/
uint32_t SetZero_U32(uint32_t *dst, uint32_t wordLen);
/**
* @brief reverse byte order of every word, the words stay the same
* @param[in] dst pointer to the destination address
- * @param[in] src pointer to the source address
- * @param[in] word length
+ * @param[in] src pointer to the source address
+ * @param[in] word length
* @return Reverse_OK: success; others: fail.
* @note 1.dst and src can be same
*/
@@ -134,7 +134,7 @@ uint32_t ReverseBytesInWord_U32(uint32_t *dst, const uint32_t *src, uint32_t wor
* @param[in] b pointer to another big number
* @param[in] word length of b
* @return Cmp_UNEQUAL:a!=b;Cmp_EQUAL: a==b.
- *
+ *
*/
int32_t Cmp_U32(const uint32_t *a, uint32_t aWordLen, const uint32_t *b, uint32_t bWordLen);
@@ -145,7 +145,7 @@ int32_t Cmp_U32(const uint32_t *a, uint32_t aWordLen, const uint32_t *b, uint32_
* @param[in] b pointer to another big number
* @param[in] word length of b
* @return Cmp_UNEQUAL:a!=b;Cmp_EQUAL: a==b.
- *
+ *
*/
int32_t Cmp_U8(const uint8_t *a, uint32_t aByteLen, const uint8_t *b, uint32_t bByteLen);
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_des.h b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_des.h
index db80ec95c6..289d33bd44 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_des.h
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_des.h
@@ -83,15 +83,15 @@ typedef struct
/**
* @brief DES_Init
* @return DES_Init_OK, DES/TDES Init success; othets: DES/TDES Init fail
- * @note
+ * @note
*/
uint32_t DES_Init(DES_PARM* parm);
/**
* @brief DES crypto
* @param[in] parm pointer to DES/TDES context and the detail please refer to struct DES_PARM in DES.h
- * @return DES_Crypto_OK, DES/TDES crypto success; othets: DES/TDES crypto fail(reference to the definition by enum variation)
- * @note 1.Please refer to the demo in user guidance before using this function
+ * @return DES_Crypto_OK, DES/TDES crypto success; othets: DES/TDES crypto fail(reference to the definition by enum variation)
+ * @note 1.Please refer to the demo in user guidance before using this function
* 2.Input and output can be the same buffer
* 3. IV can be NULL when ECB mode
* 4. The word lengrh of message must be as times as 2.
@@ -111,7 +111,7 @@ void DES_Close(void);
* @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
* @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
* @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
- * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
+ * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
* @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
* @return none
* @1.You can recall this function to get DES/TDES lib information
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_hash.h b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_hash.h
index 50e742f80e..13faa7d52e 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_hash.h
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_hash.h
@@ -53,7 +53,7 @@
enum
{
HASH_SEQUENCE_TRUE = 0x0105A5A5,//save IV
- HASH_SEQUENCE_FALSE = 0x010A5A5A, //not save IV
+ HASH_SEQUENCE_FALSE = 0x010A5A5A, //not save IV
HASH_Init_OK = 0,//hash init success
HASH_Start_OK = 0,//hash update success
HASH_Update_OK = 0,//hash update success
@@ -67,7 +67,7 @@ enum
SHA224_Hash_OK = 0,//sha224 operation success
SHA256_Hash_OK = 0,//sha256 operation success
MD5_Hash_OK = 0,//MD5 operation success
-
+
HASH_Init_ERROR = 0x01044400,//hash init error
HASH_Start_ERROR, //hash start error
HASH_Update_ERROR, //hash update error
@@ -93,7 +93,7 @@ typedef struct _HASH_CTX_
{
const HASH_ALG *hashAlg;//pointer to HASH_ALG
uint32_t sequence; // TRUE if the IV should be saved
- uint32_t IV[16];
+ uint32_t IV[16];
uint32_t msgByteLen[4];
uint8_t msgBuf[128+4];
uint32_t msgIdx;
@@ -109,7 +109,7 @@ extern const HASH_ALG HASH_ALG_SM3[1];
* @brief Hash init
* @param[in] ctx pointer to HASH_CTX struct
* @return HASH_Init_OK, Hash init success; othets: Hash init fail
- * @note 1.Please refer to the demo in user guidance before using this function
+ * @note 1.Please refer to the demo in user guidance before using this function
*/
uint32_t HASH_Init(HASH_CTX *ctx);
@@ -117,8 +117,8 @@ uint32_t HASH_Init(HASH_CTX *ctx);
* @brief Hash start
* @param[in] ctx pointer to HASH_CTX struct
* @return HASH_Start_OK, Hash start success; othets: Hash start fail
- * @note 1.Please refer to the demo in user guidance before using this function
- * 2.HASH_Init() should be recalled before use this function
+ * @note 1.Please refer to the demo in user guidance before using this function
+ * 2.HASH_Init() should be recalled before use this function
*/
uint32_t HASH_Start(HASH_CTX *ctx);
@@ -128,8 +128,8 @@ uint32_t HASH_Start(HASH_CTX *ctx);
* @param[in] in pointer to message
* @param[out] out pointer tohash result,digest
* @return HASH_Update_OK, Hash update success; othets: Hash update fail
- * @note 1.Please refer to the demo in user guidance before using this function
- * 2.HASH_Init() and HASH_Start() should be recalled before use this function
+ * @note 1.Please refer to the demo in user guidance before using this function
+ * 2.HASH_Init() and HASH_Start() should be recalled before use this function
*/
uint32_t HASH_Update(HASH_CTX *ctx, uint8_t *in, uint32_t byteLen);
@@ -138,15 +138,15 @@ uint32_t HASH_Update(HASH_CTX *ctx, uint8_t *in, uint32_t byteLen);
* @param[in] ctx pointer to HASH_CTX struct
* @param[out] out pointer tohash result,digest
* @return HASH_Complete_OK, Hash complete success; othets: Hash complete fail
- * @note 1.Please refer to the demo in user guidance before using this function
- * 2.HASH_Init(), HASH_Start() and HASH_Update() should be recalled before use this function
+ * @note 1.Please refer to the demo in user guidance before using this function
+ * 2.HASH_Init(), HASH_Start() and HASH_Update() should be recalled before use this function
*/
uint32_t HASH_Complete(HASH_CTX *ctx, uint8_t *out);
/**
* @brief Hash close
* @return HASH_Close_OK, Hash close success; othets: Hash close fail
- * @note 1.Please refer to the demo in user guidance before using this function
+ * @note 1.Please refer to the demo in user guidance before using this function
*/
uint32_t HASH_Close(void);
@@ -156,7 +156,7 @@ uint32_t HASH_Close(void);
* @param[in] byte length of in
* @param[out] out pointer tohash result,digest
* @return SM3_Hash_OK, SM3 hash success; othets: SM3 hash fail
- * @note 1.Please refer to the demo in user guidance before using this function
+ * @note 1.Please refer to the demo in user guidance before using this function
*/
uint32_t SM3_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
@@ -167,7 +167,7 @@ uint32_t SM3_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
* @param[in] byte length of in
* @param[out] out pointer tohash result,digest
* @return SHA1_Hash_OK, SHA1 hash success; othets: SHA1 hash fail
- * @note 1.Please refer to the demo in user guidance before using this function
+ * @note 1.Please refer to the demo in user guidance before using this function
*/
uint32_t SHA1_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
@@ -177,7 +177,7 @@ uint32_t SHA1_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
* @param[in] byte length of in
* @param[out] out pointer tohash result,digest
* @return SHA224_Hash_OK, SHA224 hash success; othets: SHA224 hash fail
- * @note 1.Please refer to the demo in user guidance before using this function
+ * @note 1.Please refer to the demo in user guidance before using this function
*/
uint32_t SHA224_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
@@ -188,7 +188,7 @@ uint32_t SHA224_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
* @param[in] byte length of in
* @param[out] out pointer tohash result,digest
* @return SHA256_Hash_OK, SHA256 hash success; othets: SHA256 hash fail
- * @note 1.Please refer to the demo in user guidance before using this function
+ * @note 1.Please refer to the demo in user guidance before using this function
*/
uint32_t SHA256_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
@@ -198,7 +198,7 @@ uint32_t SHA256_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
* @param[in] byte length of in
* @param[in] out pointer tohash result,digest
* @return MD5_Hash_OK, MD5 hash success; othets: MD5 hash fail
- * @note 1.Please refer to the demo in user guidance before using this function
+ * @note 1.Please refer to the demo in user guidance before using this function
*/
uint32_t MD5_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
@@ -207,7 +207,7 @@ uint32_t MD5_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
* @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
* @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
* @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
- * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
+ * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
* @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
* @return none
* @1.You can recall this function to get RSA lib information
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_rng.h b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_rng.h
index d952485dea..0d4ee0c1df 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_rng.h
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_rng.h
@@ -50,7 +50,7 @@
enum{
RNG_OK = 0x5a5a5a5a,
- LENError = 0x311ECF50, //RNG generation of key length error
+ LENError = 0x311ECF50, //RNG generation of key length error
ADDRNULL = 0x7A9DB86C, // This address is empty
};
@@ -61,8 +61,8 @@ enum{
* @param[out] rand pointer to random number
* @param[in] the wordlen of random number
* @param[in] the seed, can be NULL
- * @return RNG_OK:get random number success; othets: get random number fail
- * @note
+ * @return RNG_OK:get random number success; othets: get random number fail
+ * @note
*/
uint32_t GetPseudoRand_U32(uint32_t *rand, uint32_t wordLen,uint32_t seed[2]);
@@ -71,8 +71,8 @@ uint32_t GetPseudoRand_U32(uint32_t *rand, uint32_t wordLen,uint32_t seed[2]);
* @brief Get true random number
* @param[out] rand pointer to random number
* @param[in] the wordlen of random number
- * @return RNG_OK:get random number success; othets: get random number fail
- * @note
+ * @return RNG_OK:get random number success; othets: get random number fail
+ * @note
*/
uint32_t GetTrueRand_U32(uint32_t *rand, uint32_t wordLen);
@@ -81,7 +81,7 @@ uint32_t GetTrueRand_U32(uint32_t *rand, uint32_t wordLen);
* @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
* @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
* @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
- * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
+ * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
* @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
* @return none
* @1.You can recall this function to get RSA lib information
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/misc.h b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/misc.h
index 543e4d1533..944a6120a3 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/misc.h
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/misc.h
@@ -180,10 +180,9 @@ priority | | | 0
* @{
*/
-#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
+//#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) \
- (((SOURCE) == SysTick_CLKSource_HCLK) || ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) ((SOURCE) == SysTick_CLKSource_HCLK)
/**
* @}
*/
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_adc.h b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_adc.h
index 35b1167070..5648df2468 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_adc.h
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_adc.h
@@ -46,8 +46,8 @@ extern "C" {
* @{
*/
#define VREF1P2_CTRL (*(uint32_t*)(0x40001800+0x20))
-#define _EnVref1p2() do{VREF1P2_CTRL|=(1<<10);}while(0);
-#define _DisVref1p2() do{VREF1P2_CTRL&=~(1<<10);}while(0);
+#define _EnVref1p2() do{VREF1P2_CTRL|=(1<<10);}while (0);
+#define _DisVref1p2() do{VREF1P2_CTRL&=~(1<<10);}while (0);
/** @addtogroup ADC
* @{
*/
@@ -528,7 +528,7 @@ typedef struct
/**
* @}
*/
-
+
#define ADC_CLOCK_PLL ((uint32_t)ADC_CTRL3_CKMOD_MSK)
#define ADC_CLOCK_AHB ((uint32_t)(~ADC_CTRL3_CKMOD_MSK))
@@ -539,7 +539,7 @@ typedef struct
/**
* @}
*/
-
+
typedef enum
{
ADC_CTRL3_CKMOD_AHB = 0,
@@ -550,7 +550,7 @@ typedef enum
ADC_CTRL3_RES_12BIT = 3,
ADC_CTRL3_RES_10BIT = 2,
ADC_CTRL3_RES_8BIT = 1,
- ADC_CTRL3_RES_6BIT = 0,
+ ADC_CTRL3_RES_6BIT = 0,
} ADC_CTRL3_RES;
typedef struct
{
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_comp.h b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_comp.h
index ae6079af33..dfbb584381 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_comp.h
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_comp.h
@@ -214,49 +214,49 @@ typedef enum {
COMP1_CTRL_INMSEL_PA0 = (0x0L << 1),
COMP1_CTRL_INMSEL_DAC1_PA4 = (0x1L << 1),
COMP1_CTRL_INMSEL_DAC2_PA5 = (0x2L << 1),
- COMP1_CTRL_INMSEL_VERF1 = (0x3L << 1),
- COMP1_CTRL_INMSEL_VERF2 = (0x4L << 1),
+ COMP1_CTRL_INMSEL_VREF1 = (0x3L << 1),
+ COMP1_CTRL_INMSEL_VREF2 = (0x4L << 1),
//comp2 inm sel
COMP2_CTRL_INMSEL_PB1 = (0x0L << 1),
COMP2_CTRL_INMSEL_PE8 = (0x1L << 1),
COMP2_CTRL_INMSEL_DAC1_PA4 = (0x2L << 1),
COMP2_CTRL_INMSEL_DAC2_PA5 = (0x3L << 1),
- COMP2_CTRL_INMSEL_VERF1 = (0x4L << 1),
- COMP2_CTRL_INMSEL_VERF2 = (0x5L << 1),
+ COMP2_CTRL_INMSEL_VREF1 = (0x4L << 1),
+ COMP2_CTRL_INMSEL_VREF2 = (0x5L << 1),
//comp3 inm sel
COMP3_CTRL_INMSEL_PB12 = (0x0L << 1),
COMP3_CTRL_INMSEL_PE7 = (0x1L << 1),
COMP3_CTRL_INMSEL_DAC1_PA4 = (0x2L << 1),
COMP3_CTRL_INMSEL_DAC2_PA5 = (0x3L << 1),
- COMP3_CTRL_INMSEL_VERF1 = (0x4L << 1),
- COMP3_CTRL_INMSEL_VERF2 = (0x5L << 1),
+ COMP3_CTRL_INMSEL_VREF1 = (0x4L << 1),
+ COMP3_CTRL_INMSEL_VREF2 = (0x5L << 1),
//comp4 inm sel
COMP4_CTRL_INMSEL_PC4 = (0x0L << 1),
COMP4_CTRL_INMSEL_PB13 = (0x1L << 1),
COMP4_CTRL_INMSEL_DAC1_PA4 = (0x2L << 1),
COMP4_CTRL_INMSEL_DAC2_PA5 = (0x3L << 1),
- COMP4_CTRL_INMSEL_VERF1 = (0x4L << 1),
- COMP4_CTRL_INMSEL_VERF2 = (0x5L << 1),
+ COMP4_CTRL_INMSEL_VREF1 = (0x4L << 1),
+ COMP4_CTRL_INMSEL_VREF2 = (0x5L << 1),
//comp5 inm sel
COMP5_CTRL_INMSEL_PB10 = (0x0L << 1),
COMP5_CTRL_INMSEL_PD10 = (0x1L << 1),
COMP5_CTRL_INMSEL_DAC1_PA4 = (0x2L << 1),
COMP5_CTRL_INMSEL_DAC2_PA5 = (0x3L << 1),
- COMP5_CTRL_INMSEL_VERF1 = (0x4L << 1),
- COMP5_CTRL_INMSEL_VERF2 = (0x5L << 1),
+ COMP5_CTRL_INMSEL_VREF1 = (0x4L << 1),
+ COMP5_CTRL_INMSEL_VREF2 = (0x5L << 1),
//comp6 inm sel
COMP6_CTRL_INMSEL_PA7 = (0x0L << 1),
COMP6_CTRL_INMSEL_PD8 = (0x1L << 1),
COMP6_CTRL_INMSEL_DAC1_PA4 = (0x2L << 1),
COMP6_CTRL_INMSEL_DAC2_PA5 = (0x3L << 1),
- COMP6_CTRL_INMSEL_VERF1 = (0x4L << 1),
- COMP6_CTRL_INMSEL_VERF2 = (0x5L << 1),
+ COMP6_CTRL_INMSEL_VREF1 = (0x4L << 1),
+ COMP6_CTRL_INMSEL_VREF2 = (0x5L << 1),
//comp7 inm sel
COMP7_CTRL_INMSEL_PC0 = (0x0L << 1),
COMP7_CTRL_INMSEL_DAC1_PA4 = (0x1L << 1),
COMP7_CTRL_INMSEL_DAC2_PA5 = (0x2L << 1),
- COMP7_CTRL_INMSEL_VERF1 = (0x3L << 1),
- COMP7_CTRL_INMSEL_VERF2 = (0x4L << 1),
+ COMP7_CTRL_INMSEL_VREF1 = (0x3L << 1),
+ COMP7_CTRL_INMSEL_VREF2 = (0x4L << 1),
}COMP_CTRL_INMSEL;
#define COMP_CTRL_EN_MASK (0x01L << 0)
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_dbg.h b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_dbg.h
index ca94b4a377..c59d8b3635 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_dbg.h
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_dbg.h
@@ -27,7 +27,7 @@
/**
* @file n32g45x_dbg.h
- * @author Nations
+ * @author Nations
* @version v1.0.1
*
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_qspi.h b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_qspi.h
index 914e426d7d..319ed15c77 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_qspi.h
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_qspi.h
@@ -89,7 +89,7 @@ typedef struct
uint32_t SSTE;
uint32_t CFS;
uint32_t SPI_FRF;
-
+
/*QSPI_CTRL1*/
uint32_t NDF;
@@ -120,17 +120,12 @@ typedef struct
/*QSPI_ENH_CTRL0*/
uint32_t ENHANCED_TRANS_TYPE;
uint32_t ENHANCED_ADDR_LEN;
- uint32_t ENHANCED_MD_BIT_EN;
uint32_t ENHANCED_INST_L;
uint32_t ENHANCED_WAIT_CYCLES;
uint32_t ENHANCED_SPI_DDR_EN;
uint32_t ENHANCED_INST_DDR_EN;
- uint32_t ENHANCED_XIP_DFS_HC;
- uint32_t ENHANCED_XIP_INST_EN;
- uint32_t ENHANCED_XIP_CT_EN;
- uint32_t ENHANCED_XIP_MBL;
uint32_t ENHANCED_CLK_STRETCH_EN;
-
+
/*QSPI_DDR_TXDE*/
uint32_t TXDE;
@@ -142,7 +137,7 @@ typedef struct
/*QSPI_XIP_WRAP_TOC*/
uint32_t WTOC;
-
+
/*QSPI_XIP_CTRL*/
uint32_t XIP_FRF;
uint32_t XIP_TRANS_TYPE;
@@ -165,14 +160,14 @@ typedef struct
#define QSPI_TIME_OUT_CNT 200
#define IS_QSPI_SPI_FRF(SPI_FRF) \
- (((SPI_FRF) == QSPI_CTRL0_SPI_FRF_STANDARD_FORMAT) || ((SPI_FRF) == QSPI_CTRL0_SPI_FRF_DUAL_FORMAT) || ((SPI_FRF) == QSPI_CTRL0_SPI_FRF_QUAD_FORMAT))
+ (((SPI_FRF) == QSPI_CTRL0_SPI_FRF_STANDARD_FORMAT) || ((SPI_FRF) == QSPI_CTRL0_SPI_FRF_DUAL_FORMAT) || ((SPI_FRF) == QSPI_CTRL0_SPI_FRF_QUAD_FORMAT))
#define IS_QSPI_CFS(CFS) ((((CFS) >= QSPI_CTRL0_CFS_2_BIT) && ((CFS) <= QSPI_CTRL0_CFS_16_BIT)) || ((CFS) == QSPI_CTRL0_CFS_1_BIT))
#define IS_QSPI_SSTE(SSTE) (((SSTE) == QSPI_CTRL0_SSTE_EN) || ((SSTE) == 0))
#define IS_QSPI_TMOD(TMOD) \
- (((TMOD) == QSPI_CTRL0_TMOD_TX_AND_RX) || ((TMOD) == QSPI_CTRL0_TMOD_TX_ONLY) || ((TMOD) == QSPI_CTRL0_TMOD_RX_ONLY) || ((TMOD) == QSPI_CTRL0_TMOD_EEPROM_READ))
+ (((TMOD) == QSPI_CTRL0_TMOD_TX_AND_RX) || ((TMOD) == QSPI_CTRL0_TMOD_TX_ONLY) || ((TMOD) == QSPI_CTRL0_TMOD_RX_ONLY) || ((TMOD) == QSPI_CTRL0_TMOD_EEPROM_READ))
#define IS_QSPI_SCPOL(SCPOL) (((SCPOL) == QSPI_CTRL0_SCPOL_LOW) || ((SCPOL) == QSPI_CTRL0_SCPOL_HIGH))
@@ -213,16 +208,6 @@ typedef struct
#define IS_QSPI_ENH_CLK_STRETCH_EN(ENH_CLK_STRETCH_EN) (((ENH_CLK_STRETCH_EN) == QSPI_ENH_CTRL0_CLK_STRETCH_EN) || ((ENH_CLK_STRETCH_EN) == 0))
-#define IS_QSPI_ENH_XIP_MBL(ENH_XIP_MBL) \
- (((ENH_XIP_MBL) == QSPI_ENH_CTRL0_XIP_MBL_2_BIT) || ((ENH_XIP_MBL) == QSPI_ENH_CTRL0_XIP_MBL_4_BIT) || \
- ((ENH_XIP_MBL) == QSPI_ENH_CTRL0_XIP_MBL_8_BIT) || ((ENH_XIP_MBL) == QSPI_ENH_CTRL0_XIP_MBL_16_BIT))
-
-#define IS_QSPI_ENH_XIP_CT_EN(ENH_XIP_CT_EN) (((ENH_XIP_CT_EN) == QSPI_ENH_CTRL0_XIP_CT_EN) || ((ENH_XIP_CT_EN) == 0))
-
-#define IS_QSPI_ENH_XIP_INST_EN(ENH_XIP_INST_EN) (((ENH_XIP_INST_EN) == QSPI_ENH_CTRL0_XIP_INST_EN) || ((ENH_XIP_INST_EN) == 0))
-
-#define IS_QSPI_ENH_XIP_DFS_HC(ENH_XIP_DFS_HC) (((ENH_XIP_DFS_HC) == QSPI_ENH_CTRL0_XIP_DFS_HC) || ((ENH_XIP_DFS_HC) == 0))
-
#define IS_QSPI_ENH_INST_DDR_EN(ENH_INST_DDR_EN) (((ENH_INST_DDR_EN) == QSPI_ENH_CTRL0_INST_DDR_EN) || ((ENH_INST_DDR_EN) == 0))
#define IS_QSPI_ENH_SPI_DDR_EN(ENH_SPI_DDR_EN) (((ENH_SPI_DDR_EN) == QSPI_ENH_CTRL0_SPI_DDR_EN) || ((ENH_SPI_DDR_EN) == 0))
@@ -234,15 +219,13 @@ typedef struct
(((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_0_LINE) || ((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_4_LINE) || \
((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_8_LINE) || ((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_16_LINE))
-#define IS_QSPI_ENH_MD_BIT_EN(ENH_MD_BIT_EN) (((ENH_MD_BIT_EN) == QSPI_ENH_CTRL0_MD_BIT_EN) || ((ENH_MD_BIT_EN) == 0))
-
#define IS_QSPI_ENH_ADDR_LEN(ENH_ADDR_LEN) ((((ENH_ADDR_LEN) >= QSPI_ENH_CTRL0_ADDR_LEN_4_BIT) && ((ENH_ADDR_LEN) <= QSPI_ENH_CTRL0_ADDR_LEN_60_BIT)) || \
((ENH_ADDR_LEN) == 0))
#define IS_QSPI_ENH_TRANS_TYPE(ENH_TRANS_TYPE) (((ENH_TRANS_TYPE) == QSPI_ENH_CTRL0_TRANS_TYPE_STANDARD) || \
((ENH_TRANS_TYPE) == QSPI_ENH_CTRL0_TRANS_TYPE_ADDRESS_BY_FRF) || \
((ENH_TRANS_TYPE) == QSPI_ENH_CTRL0_TRANS_TYPE_ALL_BY_FRF))
-
+
#define IS_QSPI_DDR_TXDE(DDR_TXDE) (((DDR_TXDE) <= 0xFF))
@@ -257,7 +240,7 @@ typedef struct
#define IS_QSPI_XIP_MBL(XIP_MBL) \
(((XIP_MBL) == QSPI_XIP_CTRL_XIP_MBL_LEN_2_BIT) || ((XIP_MBL) == QSPI_XIP_CTRL_XIP_MBL_LEN_4_BIT) || \
((XIP_MBL) == QSPI_XIP_CTRL_XIP_MBL_LEN_8_BIT) || ((XIP_MBL) == QSPI_XIP_CTRL_XIP_MBL_LEN_16_BIT))
-
+
#define IS_QSPI_XIP_CT_EN(XIP_CT_EN) (((XIP_CT_EN) == QSPI_XIP_CTRL_XIP_CT_EN) || ((XIP_CT_EN) == 0))
#define IS_QSPI_XIP_INST_EN(XIP_INST_EN) (((XIP_INST_EN) == QSPI_XIP_CTRL_XIP_INST_EN) || ((XIP_INST_EN) == 0))
@@ -285,7 +268,7 @@ typedef struct
((XIP_TRANS_TYPE) == QSPI_XIP_CTRL_TRANS_TYPE_INSTRUCT_BY_XIP_FRF))
#define IS_QSPI_XIP_FRF(XIP_FRF) (((XIP_FRF) == QSPI_XIP_CTRL_FRF_2_LINE) || ((XIP_FRF) == QSPI_XIP_CTRL_FRF_4_LINE) || ((XIP_FRF) == 0))
-
+
@@ -297,7 +280,8 @@ void QSPI_XIP_Cmd(bool cmd);
void QSPI_DeInit(void);
void QspiInitConfig(QSPI_InitType* QSPI_InitStruct);
void QSPI_GPIO(QSPI_NSS_PORT_SEL qspi_nss_port_sel, bool IO1_Input, bool IO3_Output);
-void QSPI_DMA_CTRL_Config(uint8_t TxRx,uint8_t TxDataLevel,uint8_t RxDataLevel);
+void QSPI_Tx_DMA_CTRL_Config(uint8_t Cmd,uint8_t TxDataLevel);
+void QSPI_Rx_DMA_CTRL_Config(uint8_t Cmd, uint8_t RxDataLevel);
uint16_t QSPI_GetITStatus(uint16_t FLAG);
void QSPI_ClearITFLAG(uint16_t FLAG);
void QSPI_XIP_ClearITFLAG(uint16_t FLAG);
@@ -306,7 +290,6 @@ bool GetQspiTxDataBusyStatus(void);
bool GetQspiTxDataEmptyStatus(void);
bool GetQspiRxHaveDataStatus(void);
bool GetQspiRxDataFullStatus(void);
-bool GetQspiTransmitErrorStatus(void);
bool GetQspiDataConflictErrorStatus(void);
void QspiSendWord(uint32_t SendData);
uint32_t QspiReadWord(void);
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_tim.h b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_tim.h
index 5da1c9c564..21186a781a 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_tim.h
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_tim.h
@@ -568,19 +568,17 @@ typedef struct
#define TIM_DMABASE_CAPCMPDAT4 ((uint16_t)0x0010)
#define TIM_DMABASE_BKDT ((uint16_t)0x0011)
#define TIM_DMABASE_DMACTRL ((uint16_t)0x0012)
-#define TIM_DMABASE_CAPCMPMOD3 ((uint16_t)0x0013)
-#define TIM_DMABASE_CAPCMPDAT5 ((uint16_t)0x0014)
-#define TIM_DMABASE_CAPCMPDAT6 ((uint16_t)0x0015)
+
+
#define IsTimDmaBase(BASE) \
(((BASE) == TIM_DMABASE_CTRL1) || ((BASE) == TIM_DMABASE_CTRL2) || ((BASE) == TIM_DMABASE_SMCTRL) \
|| ((BASE) == TIM_DMABASE_DMAINTEN) || ((BASE) == TIM_DMABASE_STS) || ((BASE) == TIM_DMABASE_EVTGEN) \
- || ((BASE) == TIM_DMABASE_CAPCMPMOD1) || ((BASE) == TIM_DMABASE_CAPCMPMOD2) || ((BASE) == TIM_DMABASE_CAPCMPMOD3) \
+ || ((BASE) == TIM_DMABASE_CAPCMPMOD1) || ((BASE) == TIM_DMABASE_CAPCMPMOD2) \
|| ((BASE) == TIM_DMABASE_CAPCMPEN) || ((BASE) == TIM_DMABASE_CNT) || ((BASE) == TIM_DMABASE_PSC) \
|| ((BASE) == TIM_DMABASE_AR) || ((BASE) == TIM_DMABASE_REPCNT) || ((BASE) == TIM_DMABASE_CAPCMPDAT1) \
|| ((BASE) == TIM_DMABASE_CAPCMPDAT2) || ((BASE) == TIM_DMABASE_CAPCMPDAT3) || ((BASE) == TIM_DMABASE_CAPCMPDAT4) \
- || ((BASE) == TIM_DMABASE_CAPCMPDAT5) || ((BASE) == TIM_DMABASE_CAPCMPDAT6) || ((BASE) == TIM_DMABASE_BKDT) \
- || ((BASE) == TIM_DMABASE_DMACTRL))
+ || ((BASE) == TIM_DMABASE_BKDT)|| ((BASE) == TIM_DMABASE_DMACTRL))
/**
* @}
*/
@@ -828,14 +826,14 @@ typedef struct
* @}
*/
-/** @defgroup ETR selection
+/** @defgroup ETR selection
* @{
*/
#define TIM_ETR_Seletct_ExtGpio ((uint16_t)0x0000)
#define TIM_ETR_Seletct_innerTsc ((uint16_t)0x0100)
/**
* @}
- */
+ */
/** @addtogroup TIM_Slave_Mode
* @{
@@ -926,11 +924,11 @@ typedef struct
#define IsAdvancedTimCCENFlag(FLAG) \
(((FLAG) == TIM_CC1EN) || ((FLAG) == TIM_CC1NEN) || ((FLAG) == TIM_CC2EN) || ((FLAG) == TIM_CC2NEN) \
|| ((FLAG) == TIM_CC3EN) || ((FLAG) == TIM_CC3NEN) \
- || ((FLAG) == TIM_CC4EN) || ((FLAG) == TIM_CC5EN) || ((FLAG) == TIM_CC6EN) )
+ || ((FLAG) == TIM_CC4EN) || ((FLAG) == TIM_CC5EN) || ((FLAG) == TIM_CC6EN) )
#define IsGeneralTimCCENFlag(FLAG) \
(((FLAG) == TIM_CC1EN) || ((FLAG) == TIM_CC2EN) \
|| ((FLAG) == TIM_CC3EN) \
- || ((FLAG) == TIM_CC4EN) )
+ || ((FLAG) == TIM_CC4EN) )
/** @addtogroup TIM_Legacy
* @{
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_tsc.h b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_tsc.h
index ad009b82c2..92728eaf04 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_tsc.h
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_tsc.h
@@ -149,7 +149,7 @@
/**
* @
*/
-
+
/**
* @defgroup TSC_Interrupt
*/
@@ -242,7 +242,7 @@
/**
* @
*/
-
+
/**
* @defgroup TSC_Constant
*/
@@ -307,7 +307,7 @@
* @arg TSC_DET_TYPE_NONE: Detect disable
* @arg TSC_DET_TYPE_LESS: Pulse number must be greater than the threshold(basee-delta) during a sample time
* @arg TSC_DET_TYPE_GREAT: Pulse number must be less than the threshold(basee+delta) during a sample time
- * @arg TSC_DET_TYPE_PERIOD:Pulse number must be greater than (basee-delta)
+ * @arg TSC_DET_TYPE_PERIOD:Pulse number must be greater than (basee-delta)
and also be less than (basee+delta) during a sample time
* @retval None
*/
@@ -331,7 +331,7 @@
* @param __OUT__ specifies where the TSC output should go
* @arg TSC_OUT_PIN: TSC output to the TSC_OUT pin
* @arg TSC_OUT_TIM4_ETR: TSC output to TIM4 as ETR
- * @arg TSC_OUT_TIM2_ETR: TSC output to TIM2 as ETR
+ * @arg TSC_OUT_TIM2_ETR: TSC output to TIM2 as ETR
* @retval None
*/
#define __TSC_OUT_CONFIG(__OUT__) MODIFY_REG( TSC->CTRL, \
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32xx_tsc_alg_api.h b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32xx_tsc_alg_api.h
index a0bc723d76..87e8f1fdff 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32xx_tsc_alg_api.h
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32xx_tsc_alg_api.h
@@ -26,8 +26,8 @@
* ****************************************************************************/
/**
- * @brief ´¥¿ØË㷨ͷÎļþ.
- * ´ó¸ÅÁ÷³Ì:(ÅäÖÃTIMER->¶¨Òå»Øµ÷API->³õʼ»¯->Æô¶¯)
+ * @brief 触控算法头文件.
+ * 大概æµç¨‹:(é…ç½®TIMER->定义回调API->åˆå§‹åŒ–->å¯åŠ¨)
* @file n32xx_tsc_alg_api.h
* @author Nations
* @version v1.0.1
@@ -40,16 +40,16 @@
extern "C" {
#endif // defined __cplusplus
-#define TSC_ALG_VERSION_NUMBER "Ver1.0.4" //Ëã·¨¿â°æ±¾ºÅ
+#define TSC_ALG_VERSION_NUMBER "Ver1.0.4" //算法库版本å·
-#define TSC_ALG_HANDLER_STOP2_DATA_SIZE (144) //ÓÃÓÚÔÚSTOP2ģʽϱ£´æ´¥¿Ø»½Ðѹ¦ÄÜÏà¹ØµÄTSCÊý¾Ý¡£
-#define TSC_ALG_HANDLER_PERIOD_PER_CHN (400) //´¥¿ØËã·¨µ¥Í¨µÀµÄ´¦ÀíÖÜÆÚÒò×Ó¡£
-#define TSC_ALG_WAKEUP_TIMES (1000) //ÓйØTSC»½Ðѹ¦ÄܵÄʱ¼äÅäÖ㬲»ÒªËæÒâÐÞ¸Ä
-#define TSC_ALG_DEBUG_BUF_SIZE (260) //¶¨Òåµ÷ÊÔģʽϵÄBUF´óС
-#define TSC_ALG_REF_SIZE_PER_CHN (430) //´¥¿ØÿͨµÀµÄ²Î¿¼´óС£¬Êµ¼Ê´óСÒÔtsc_alg_need_sramsize()¼ÆËãΪ׼
+#define TSC_ALG_HANDLER_STOP2_DATA_SIZE (144) //用于在STOP2模å¼ä¸‹ä¿å˜è§¦æŽ§å”¤é†’功能相关的TSCæ•°æ®ã€‚
+#define TSC_ALG_HANDLER_PERIOD_PER_CHN (400) //触控算法å•é€šé“的处ç†å‘¨æœŸå› å。
+#define TSC_ALG_WAKEUP_TIMES (1000) //有关TSC唤醒功能的时间é…置，ä¸è¦éšæ„修改
+#define TSC_ALG_DEBUG_BUF_SIZE (260) //定义调试模å¼ä¸‹çš„BUF大å°
+#define TSC_ALG_REF_SIZE_PER_CHN (430) //触控æ¯é€šé“çš„å‚考大å°ï¼Œå®žé™…大å°ä»¥tsc_alg_need_sramsize()计算为准
/**
- * @brief ¶¨Òå´¥¿ØÀàÐÍ
+ * @brief 定义触控类型
*/
typedef enum tsc_alg_type_e
{
@@ -58,76 +58,76 @@ typedef enum tsc_alg_type_e
} tsc_alg_type;
/**
- * @brief °´¼üʼþ
+ * @brief 按键事件
*/
typedef enum tsc_press_key_event_e
{
- TSC_PRESS_KEY_NORMAL = 0, //Õý³£¶Ì°´Ê¼þ
+ TSC_PRESS_KEY_NORMAL = 0, //æ£å¸¸çŸæŒ‰äº‹ä»¶
TSC_PRESS_KEY_MAX ///<
} tsc_press_key_event;
/**
- * @brief ´íÎóÀàÐͶ¨Òå
+ * @brief 错误类型定义
*/
typedef enum tsc_ret_code_e
{
- TSC_SUCCESS = 0, ///< ³É¹¦
- TSC_NOT_INIT_ERR, ///< Ä£¿éδ³õʼ»¯´íÎó
- TSC_NOT_REG_CHN_ERR, ///< Ä£¿é×¢²áÎÞЧµÄ´¥¿ØͨµÀ´íÎó
- TSC_NOT_ACCORD_LIB_ERR, ///< Ëã·¨¿â°æ±¾´íÎó
- TSC_POINTER_NULL_ERR, ///< Ö¸ÕëΪ¿Õ´íÎó
- TSC_PARAM_ZERO_ERR, ///< ²ÎÊý´íÎó
- TSC_REPEAT_REG_ERR, ///< Öظ´×¢²á´íÎó
- TSC_CHN_NUM_ERR, ///< Óë³õʼ»¯µÄͨµÀ×ÜÊý²»Ò»Ö´íÎó
- TSC_REG_CHANNEL_ENOUGH_ERR, ///< ×¢²áµÄͨµÀºÅ´íÎó»ò³¬³öϵͳ×ÜͨµÀÊý
- TSC_REG_TIMX_ERR, ///< ×¢²áµÄTimer×ÊÔ´´íÎó
- TSC_REG_DMA_ERR, ///< ×¢²áµÄDMA×ÊÔ´´íÎó
- TSC_SOURCE_NOT_ENOUGH_ERR, ///< ×ÊÔ´²»×ã´íÎó
- TSC_NOT_SUPPORT_ERR, ///< δʵÏÖ»ò²Ù×÷²»Ö§³Ö´íÎó
- TSC_LEVEL_CFG_ERR, ///< ͨµÀµÄÁéÃ÷¶ÈÅäÖôíÎó
- TSC_AUTO_CALIB_TIMER_ERR, ///< ×Ô¶¯Ð£×¼Ê±¼äСÓÚ2±¶Í¨µÀ°´¼ü±£³Öʱ¼ä.
- TSC_DISTURB_ERR, ///< ¸ÉÈÅ´íÎó.
- TSC_CHN_RAM_NOT_ENOUGH_ERR, ///< ÌṩµÄTSCͨµÀRAMΪNULL»ò¿Õ¼ä²»×ã´íÎó
- TSC_STOP2_NULL_OR_INVALID_ERR, ///< ÌṩµÄStop2DataÊý¾Ý¿Õ¼äΪNULL»ò²»ÔÚ16K retentionÇøÓòÄÚ¡£
- TSC_DEBUG_BUF_ENOUGH_ERR ///< ÌṩµÄµ÷ÊÔ»º´æ¿Õ¼ä²»×ã´íÎó
+ TSC_SUCCESS = 0, ///< æˆåŠŸ
+ TSC_NOT_INIT_ERR, ///< 模å—未åˆå§‹åŒ–错误
+ TSC_NOT_REG_CHN_ERR, ///< 模å—æ³¨å†Œæ— æ•ˆçš„è§¦æŽ§é€šé“错误
+ TSC_NOT_ACCORD_LIB_ERR, ///< 算法库版本错误
+ TSC_POINTER_NULL_ERR, ///< 指针为空错误
+ TSC_PARAM_ZERO_ERR, ///< å‚数错误
+ TSC_REPEAT_REG_ERR, ///< é‡å¤æ³¨å†Œé”™è¯¯
+ TSC_CHN_NUM_ERR, ///< 与åˆå§‹åŒ–的通é“总数ä¸ä¸€è‡´é”™è¯¯
+ TSC_REG_CHANNEL_ENOUGH_ERR, ///< 注册的通é“å·é”™è¯¯æˆ–超出系统总通é“æ•°
+ TSC_REG_TIMX_ERR, ///< 注册的Timer资æºé”™è¯¯
+ TSC_REG_DMA_ERR, ///< 注册的DMA资æºé”™è¯¯
+ TSC_SOURCE_NOT_ENOUGH_ERR, ///< 资æºä¸è¶³é”™è¯¯
+ TSC_NOT_SUPPORT_ERR, ///< 未实现或æ“作ä¸æ”¯æŒé”™è¯¯
+ TSC_LEVEL_CFG_ERR, ///< 通é“çš„çµæ˜Žåº¦é…置错误
+ TSC_AUTO_CALIB_TIMER_ERR, ///< è‡ªåŠ¨æ ¡å‡†æ—¶é—´å°äºŽ2å€é€šé“按键ä¿æŒæ—¶é—´.
+ TSC_DISTURB_ERR, ///< 干扰错误.
+ TSC_CHN_RAM_NOT_ENOUGH_ERR, ///< æ供的TSC通é“RAM为NULL或空间ä¸è¶³é”™è¯¯
+ TSC_STOP2_NULL_OR_INVALID_ERR, ///< æ供的Stop2Dataæ•°æ®ç©ºé—´ä¸ºNULL或ä¸åœ¨16K retention区域内。
+ TSC_DEBUG_BUF_ENOUGH_ERR ///< æ供的调试缓å˜ç©ºé—´ä¸è¶³é”™è¯¯
} tsc_ret_code;
/**
- * @brief ´¥¿Ø°´¼ü³ÖÐøµÈ¼¶
- * ³ÖÐøµÈ¼¶Ô½Ð¡:·´Ó¦ËÙ¶ÈÔ½¿ì£¬¿¹Ë²¼äµÄ¸ÉÈÅÒ²Ô½Èõ£»
- * ³ÖÐøµÈ¼¶Ô½´ó:·´Ó¦ËÙ¶ÈÏà¶ÔÈõ£¬¿¹Ë²¼ä¸ÉÈÅÄÜÁ¦Ô½Ç¿
+ * @brief 触控按键æŒç»ç‰çº§
+ * æŒç»ç‰çº§è¶Šå°:å应速度越快，抗瞬间的干扰也越弱；
+ * æŒç»ç‰çº§è¶Šå¤§:å应速度相对弱，抗瞬间干扰能力越强
*/
typedef enum tsc_hld_lev_e
{
- TSC_HOLD_LEV1 = 1, // HOLDµÈ¼¶1(5ms)
- TSC_HOLD_LEV2 = 2, // HOLDµÈ¼¶2(7ms)
- TSC_HOLD_LEV3 = 3, // HOLDµÈ¼¶3(11ms)
- TSC_HOLD_LEV4 = 4, // HOLDµÈ¼¶4(17ms)
- TSC_HOLD_LEV5 = 5, // HOLDµÈ¼¶5(25ms)
- TSC_HOLD_LEV6 = 6, // HOLDµÈ¼¶6(35ms)
- TSC_HOLD_LEV7 = 7, // HOLDµÈ¼¶7(47ms)
- TSC_HOLD_LEV8 = 8, // HOLDµÈ¼¶8(61ms)
- TSC_HOLD_LEV9 = 9, // HOLDµÈ¼¶9(77ms)
- TSC_HOLD_LEV10 = 10, // HOLDµÈ¼¶10(95ms)
- TSC_HOLD_LEV11 = 11, // HOLDµÈ¼¶11(115ms)
- TSC_HOLD_LEV12 = 12, // HOLDµÈ¼¶12(137ms)
- TSC_HOLD_LEV13 = 13, // HOLDµÈ¼¶13(161ms)
- TSC_HOLD_LEV14 = 14, // HOLDµÈ¼¶14(187ms)
- TSC_HOLD_LEV15 = 15, // HOLDµÈ¼¶15(215ms)
- TSC_HOLD_LEV16 = 16, // HOLDµÈ¼¶16(245ms)
- TSC_HOLD_LEV17 = 17, // HOLDµÈ¼¶17(277ms)
- TSC_HOLD_LEV18 = 18, // HOLDµÈ¼¶18(311ms)
- TSC_HOLD_LEV19 = 19, // HOLDµÈ¼¶19(347ms)
- TSC_HOLD_LEV20 = 20, // HOLDµÈ¼¶20(385ms)
- TSC_HOLD_MAX ///< ÎÞЧ
+ TSC_HOLD_LEV1 = 1, // HOLDç‰çº§1(5ms)
+ TSC_HOLD_LEV2 = 2, // HOLDç‰çº§2(7ms)
+ TSC_HOLD_LEV3 = 3, // HOLDç‰çº§3(11ms)
+ TSC_HOLD_LEV4 = 4, // HOLDç‰çº§4(17ms)
+ TSC_HOLD_LEV5 = 5, // HOLDç‰çº§5(25ms)
+ TSC_HOLD_LEV6 = 6, // HOLDç‰çº§6(35ms)
+ TSC_HOLD_LEV7 = 7, // HOLDç‰çº§7(47ms)
+ TSC_HOLD_LEV8 = 8, // HOLDç‰çº§8(61ms)
+ TSC_HOLD_LEV9 = 9, // HOLDç‰çº§9(77ms)
+ TSC_HOLD_LEV10 = 10, // HOLDç‰çº§10(95ms)
+ TSC_HOLD_LEV11 = 11, // HOLDç‰çº§11(115ms)
+ TSC_HOLD_LEV12 = 12, // HOLDç‰çº§12(137ms)
+ TSC_HOLD_LEV13 = 13, // HOLDç‰çº§13(161ms)
+ TSC_HOLD_LEV14 = 14, // HOLDç‰çº§14(187ms)
+ TSC_HOLD_LEV15 = 15, // HOLDç‰çº§15(215ms)
+ TSC_HOLD_LEV16 = 16, // HOLDç‰çº§16(245ms)
+ TSC_HOLD_LEV17 = 17, // HOLDç‰çº§17(277ms)
+ TSC_HOLD_LEV18 = 18, // HOLDç‰çº§18(311ms)
+ TSC_HOLD_LEV19 = 19, // HOLDç‰çº§19(347ms)
+ TSC_HOLD_LEV20 = 20, // HOLDç‰çº§20(385ms)
+ TSC_HOLD_MAX ///< æ— æ•ˆ
} tsc_hld_lev;
/**
- * @brief Ôڵ͹¦ºÄģʽÏ£¬Ëæ»·¾³±ä»¯¶ø¸üл½ÐÑÃÅÏÞ¡£
- * Òò´ËÉèÖÃÒ»¸ö±ä»¯Á¿Òò×Ó¡£
- * СÓڴ˱仯Á¿Òò×ÓµÄdeltaÔòÈÏΪÊÇÓÐЧ±ä»¯£¬Ôòͨ¹ý´Ë½Ó¿Ú¸üÐÂTSC»½ÐÑÃÅÏÞ£»
- * ´óÓڴ˱仯Á¿Òò×ÓµÄdeltaÔòÈÏΪÊÇÎÞЧ±ä»¯£¬Ôò´Ë½Ó¿ÚºöÂÔÖ®£¬²»¸üл½ÐÑÃÅÏÞ¡£
- * ±ä»¯Á¿Òò×ÓÔ½´ó£¬Ôò±íʾ±ä»¯Á¿Ô½´ó¡£Ò»°ãÉèÖÃΪLEV15¡£
+ * @brief 在低功耗模å¼ä¸‹ï¼ŒéšçŽ¯å¢ƒå˜åŒ–而更新唤醒门é™ã€‚
+ * å› æ¤è®¾ç½®ä¸€ä¸ªå˜åŒ–é‡å› å。
+ * å°äºŽæ¤å˜åŒ–é‡å› åçš„delta则认为是有效å˜åŒ–，则通过æ¤æŽ¥å£æ›´æ–°TSC唤醒门é™ï¼›
+ * 大于æ¤å˜åŒ–é‡å› åçš„deltaåˆ™è®¤ä¸ºæ˜¯æ— æ•ˆå˜åŒ–，则æ¤æŽ¥å£å¿½ç•¥ä¹‹ï¼Œä¸æ›´æ–°å”¤é†’é—¨é™ã€‚
+ * å˜åŒ–é‡å› å越大，则表示å˜åŒ–é‡è¶Šå¤§ã€‚一般设置为LEV15。
*/
typedef enum tsc_delta_limit_lev_e
{
@@ -151,147 +151,147 @@ typedef enum tsc_delta_limit_lev_e
TSC_DELTA_LIMIT_LEV18 = 18, //
TSC_DELTA_LIMIT_LEV19 = 19, //
TSC_DELTA_LIMIT_LEV20 = 20, //
- TSC_DELTA_LIMIT_MAX ///< ÎÞЧ
+ TSC_DELTA_LIMIT_MAX ///< æ— æ•ˆ
} tsc_delta_limit_lev;
/**
- * @brief ¿¹¸ÉÈŵȼ¶
- * ¿¹¸ÉÈŵȼ¶,µÈ¼¶Ô½¸ß¿¹¸ÉÈÅԽǿ£¬µ«Ò²¶Ô°å¼¶»·¾³ÒªÇóÔ½ÑÏ¿Á.
+ * @brief 抗干扰ç‰çº§
+ * 抗干扰ç‰çº§,ç‰çº§è¶Šé«˜æŠ—干扰越强，但也对æ¿çº§çŽ¯å¢ƒè¦æ±‚越严苛.
*/
typedef enum tsc_resist_disturb_lev_e
{
- TSC_RESIST_DIS_LEV0 = 0, //ĬÈϵȼ¶£¬¿¹Íⲿ¸ÉÈÅÒ»°ã¡£Ö§³ÖPCBA&ÑÇ¿ËÁ¦´¥Ãþ¡£
- TSC_RESIST_DIS_LEV1 = 1, //ÔöÇ¿µÈ¼¶£¬¿¹Íⲿ¸ÉÈÅÔöÇ¿¡£ÑÇ¿ËÁ¦Çé¿öÏÂÌåÑé¸üºÃ¡£
- TSC_RESIST_DIS_LEV2 = 2, //Ôݱ£Áô¡£
- TSC_RESIST_DIS_MAX ///< ÎÞЧ
+ TSC_RESIST_DIS_LEV0 = 0, //默认ç‰çº§ï¼ŒæŠ—外部干扰一般。支æŒPCBA&亚克力触摸。
+ TSC_RESIST_DIS_LEV1 = 1, //增强ç‰çº§ï¼ŒæŠ—外部干扰增强。亚克力情况下体验更好。
+ TSC_RESIST_DIS_LEV2 = 2, //æš‚ä¿ç•™ã€‚
+ TSC_RESIST_DIS_MAX ///< æ— æ•ˆ
} tsc_resist_disturb_lev;
/**
- * @brief TSC´¥¿ØͨµÀ³õʼÃÅÏÞÖµÅäÖÃ
+ * @brief TSC触控通é“åˆå§‹é—¨é™å€¼é…ç½®
*/
typedef struct TSC_AlgInitThreValue_t
{
- uint16_t hold_level; /* °´¼ü´¥·¢³ÖÐøµÈ¼¶ */
- uint16_t rate_of_change; /* ¸ÃͨµÀ°´¼ü±ä»¯ÂÊ(ÈçÎÞѹÏÂΪ70,ѹÏÂΪ77£¬Ôò±ä»¯ÂÊΪ(77-70)/70 = 0.1¼´%10(×¢Òâ:Êʵ±½µµÍΪ8%)¡£Ä¬ÈÏΪ5,Ôò±ä»¯ÂÊ%5 */
- uint32_t chn; /* ͨµÀ */
+ uint16_t hold_level; /* 按键触å‘æŒç»ç‰çº§ */
+ uint16_t rate_of_change; /* 该通é“按键å˜åŒ–率(å¦‚æ— åŽ‹ä¸‹ä¸º70,压下为77，则å˜åŒ–率为(77-70)/70 = 0.1å³%10(注æ„:适当é™ä½Žä¸º8%)。默认为5,则å˜åŒ–率%5 */
+ uint32_t chn; /* é€šé“ */
} TSC_AlgInitThreValue;
/**
- * @brief TSC³õʼ»¯ÅäÖòÎÊý
+ * @brief TSCåˆå§‹åŒ–é…ç½®å‚æ•°
*/
typedef struct TSC_AlgInitTypeDef_t
{
- TIM_Module* TIMx; /* ´¥¿ØË㷨ʹÓõÄTIMER×ÊÔ´(½öÖ§³ÖTIMER2) */
- DMA_ChannelType* DMAyChx; /* ´¥¿ØË㷨ʹÓõÄDMA×ÊÔ´(½öÖ§³ÖDMA1_CH5) */
- uint32_t DMARemapEnable; /* ÊÇ·ñʹÄÜDMA È«¾ÖREMAP¹¦ÄÜ(ÈçDMA1ÖÐÆäËûͨµÀÓÐʹÄÜREMAP¹¦ÄÜ£¬Ôò´Ë´¦ÐèÅäÖÃΪ1) */
- TSC_AlgInitThreValue* pTScChannelList; /* ÓÉ´¥¿ØͨµÀ×é³ÉÁбíµÄÊý×顣ĿǰÔÝÖ§³Ö1¸öÁÐ(¿Éͨ¹ýλ»òÔËËã,½«¶à¸öTSCͨµÀ×é³ÉÒ»¸öÁбí)¡£ */
- uint32_t AutoCalibrateTimer; /* ÅäÖÃÓи²¸ÇÎïÇé¿öϵÄ×Ô¶¯Ð£×¼Ê±¼ä(ÎÞ¸²¸ÇÎï»ò¸ÉÈÅʱ²»»áУ׼),Ò»°ãÉèÖÃ1000ms¼´¿É,×î´ó65535¡£µ¥Î»ms¡£´ËÖµ±ØÐë´óÓÚ°´¼ü±£³Öʱ¼äµÄ2±¶ÒÔÉÏ£¬·ñÔò³õʼ»¯´íÎó */
- uint32_t ResistDisturbLev; /* ¿¹¸ÉÈŵȼ¶(tsc_resist_disturb_lev),µÈ¼¶Ô½¸ß¿¹¸ÉÈÅԽǿ£¬µ«Ò²¶Ô°å¼¶×°Åä»·¾³ÒªÇóÔ½¸ß. */
- uint8_t* pTscSramAddr; /* Ó¦ÓóÌÐòÌṩ¸øTSCÇý¶¯¿âµÄ´¥¿ØͨµÀRAM¿Õ¼äµØÖ·*/
- uint32_t TscSramSize; /* Ó¦ÓóÌÐòÌṩ¸øTSCÇý¶¯¿âµÄ´¥¿ØͨµÀRAM¿Õ¼ä´óС.µ¥Î»(bytes) */
- uint16_t* LogBuf; /* ÓÃÓÚµ÷ÊÔģʽϵÄbuf»º´æ,·Çµ÷ÊÔģʽÏÂÔòΪ0 */
- uint16_t LogBufSize; /* ÿͨµÀ´óСΪu16 * 256.µ¥Î»(bytes) */
- uint8_t* Stop2Data; /* ÓÃÓÚÔÚSTOP2ģʽϱ£´æ´¥¿Ø»½Ðѹ¦ÄÜÏà¹ØµÄTSCÊý¾ÝBUF¡£ */
- uint16_t Stop2DataSize; /* ÓÃÓÚÔÚSTOP2ģʽϱ£´æ´¥¿Ø»½Ðѹ¦ÄÜÏà¹ØµÄTSCÊý¾ÝBUF´óС¡£µ¥Î»(bytes) */
+ TIM_Module* TIMx; /* 触控算法使用的TIMER资æº(仅支æŒTIMER2) */
+ DMA_ChannelType* DMAyChx; /* 触控算法使用的DMA资æº(仅支æŒDMA1_CH5) */
+ uint32_t DMARemapEnable; /* 是å¦ä½¿èƒ½DMA 全局REMAP功能(如DMA1ä¸å…¶ä»–通é“有使能REMAP功能，则æ¤å¤„需é…置为1) */
+ TSC_AlgInitThreValue* pTScChannelList; /* 由触控通é“组æˆåˆ—表的数组。目å‰æš‚支æŒ1个列(å¯é€šè¿‡ä½æˆ–è¿ç®—,将多个TSC通é“组æˆä¸€ä¸ªåˆ—表)。 */
+ uint32_t AutoCalibrateTimer; /* é…ç½®æœ‰è¦†ç›–ç‰©æƒ…å†µä¸‹çš„è‡ªåŠ¨æ ¡å‡†æ—¶é—´(æ— è¦†ç›–ç‰©æˆ–å¹²æ‰°æ—¶ä¸ä¼šæ ¡å‡†),一般设置1000mså³å¯,最大65535。å•ä½ms。æ¤å€¼å¿…须大于按键ä¿æŒæ—¶é—´çš„2å€ä»¥ä¸Šï¼Œå¦åˆ™åˆå§‹åŒ–错误 */
+ uint32_t ResistDisturbLev; /* 抗干扰ç‰çº§(tsc_resist_disturb_lev),ç‰çº§è¶Šé«˜æŠ—干扰越强，但也对æ¿çº§è£…é…环境è¦æ±‚越高. */
+ uint8_t* pTscSramAddr; /* 应用程åºæ供给TSC驱动库的触控通é“RAM空间地å€*/
+ uint32_t TscSramSize; /* 应用程åºæ供给TSC驱动库的触控通é“RAM空间大å°.å•ä½(bytes) */
+ uint16_t* LogBuf; /* 用于调试模å¼ä¸‹çš„buf缓å˜,éžè°ƒè¯•æ¨¡å¼ä¸‹åˆ™ä¸º0 */
+ uint16_t LogBufSize; /* æ¯é€šé“大å°ä¸ºu16 * 256.å•ä½(bytes) */
+ uint8_t* Stop2Data; /* 用于在STOP2模å¼ä¸‹ä¿å˜è§¦æŽ§å”¤é†’功能相关的TSCæ•°æ®BUF。 */
+ uint16_t Stop2DataSize; /* 用于在STOP2模å¼ä¸‹ä¿å˜è§¦æŽ§å”¤é†’功能相关的TSCæ•°æ®BUF大å°ã€‚å•ä½(bytes) */
} TSC_AlgInitTypeDef;
/**
- * @brief ´¥¿ØË㷨ʵʱ·ÖÎö´¦Àíº¯Êý(±ØÐë·ÅÔÚTIMERÖжϺ¯ÊýÖÐ)
- * @TIMER¶¨Ê±ÖÜÆڲο¼ÖÜÆÚÒò×Ó£¬¶¨Ê±Æ÷ÖÜÆڲο¼DEMO·¶Àý.
+ * @brief 触控算法实时分æžå¤„ç†å‡½æ•°(必须放在TIMERä¸æ–函数ä¸)
+ * @TIMER定时周期å‚è€ƒå‘¨æœŸå› å，定时器周期å‚考DEMO范例.
* @param void
* @return void
*/
void tsc_alg_analyze_handler(void);
/**
- * @brief µÍ¹¦ºÄУ׼
- * @param uint32_t delta_limit_level ±ä»¯Á¿ÏÞÖµµÈ¼¶tsc_delta_limit_lev
+ * @brief ä½ŽåŠŸè€—æ ¡å‡†
+ * @param uint32_t delta_limit_level å˜åŒ–é‡é™å€¼ç‰çº§tsc_delta_limit_lev
* @uint32_t hse_or_hsi 0:HSI, 1:HSE;
* @return
- * - `TSC_SUCCESS£º ±íʾ²Ù×÷³É¹¦
- * - ÆäËüÖµ±íʾ³ö´í
- * - ×¢Ò⣺ÓÃÓÚÔÚSTOP2µÍ¹¦ºÄģʽÏ£¬¶¨Ê±Ð£×¼¡£
+ * - `TSC_SUCCESS： 表示æ“作æˆåŠŸ
+ * - 其它值表示出错
+ * - 注æ„：用于在STOP2低功耗模å¼ä¸‹ï¼Œå®šæ—¶æ ¡å‡†ã€‚
*/
int32_t tsc_alg_set_powerdown_calibrate(tsc_delta_limit_lev delta_limit_level, uint32_t hse_or_hsi);
/**
- * @brief µÍ¹¦ºÄģʽÏÂ,¼ì²âÊÇ·ñ±»¸ÉÈÅ»½ÐÑ
+ * @brief 低功耗模å¼ä¸‹,检测是å¦è¢«å¹²æ‰°å”¤é†’
* @param void
- * @return 0:Õý³£»½ÐÑ£»1:¸ÉÈÅ»½ÐÑ
+ * @return 0:æ£å¸¸å”¤é†’ï¼›1:干扰唤醒
*/
int32_t tsc_alg_wakeup_disturb_check(uint32_t* wakeup_src);
/**
- * @brief »ñÈ¡Ëã·¨°æ±¾
+ * @brief 获å–算法版本
* @param void
* @return void
*/
char* tsc_alg_get_version(void);
/**
- * @brief ´¥¿ØË㷨ϵͳµÎ´ð,ĬÈÏ1ms
+ * @brief 触控算法系统滴ç”,默认1ms
* @param void
* @return void
*/
void tsc_alg_tick_count(void);
/**
- * @brief »ñÈ¡TSC´¥¿ØËã·¨ÐèÒªµÄSRAM´óС
- * uint32_t chn_totals; // ʹÓõÄTSC´¥¿ØͨµÀÊý
+ * @brief 获å–TSC触控算法需è¦çš„SRAM大å°
+ * uint32_t chn_totals; // 使用的TSC触控通é“æ•°
* @return
- * - 0: ±íʾʧ°Ü
- * - ·Ç0: ±íʾ³É¹¦
+ * - 0: 表示失败
+ * - éž0: 表示æˆåŠŸ
*/
uint32_t tsc_alg_need_sramsize(uint32_t chn_totals);
/**
- * @brief ´¥¿ØËã·¨³õʼ»¯
- * @param tsc_init_parameter *ptsc_init_parameter ´¥¿ØËã·¨³õʼ»¯½á¹¹ÌåµØÖ·.
+ * @brief 触控算法åˆå§‹åŒ–
+ * @param tsc_init_parameter *ptsc_init_parameter 触控算法åˆå§‹åŒ–结构体地å€.
* @param void
* @return
- * - `TSC_SUCCESS£º ±íʾ²Ù×÷³É¹¦
- * - ÆäËüÖµ±íʾ³ö´í
+ * - `TSC_SUCCESS： 表示æ“作æˆåŠŸ
+ * - 其它值表示出错
*/
int32_t tsc_alg_init(TSC_AlgInitTypeDef* TSC_AlgInitStruct);
/**
- * @brief Æô¶¯´¥¿Ø¿ªÊ¼¹¤×÷
+ * @brief å¯åŠ¨è§¦æŽ§å¼€å§‹å·¥ä½œ
* @param void
* @return
- * - `TSC_SUCCESS£º ±íʾ²Ù×÷³É¹¦
- * - ÆäËüÖµ±íʾ³ö´í
+ * - `TSC_SUCCESS： 表示æ“作æˆåŠŸ
+ * - 其它值表示出错
*/
int32_t tsc_alg_start(void);
/**
- * @brief ÉèÖÃTSC½øÈëµÍ¹¦ºÄ(ÓÃÓڵ͹¦ºÄ»½ÐÑģʽ)
- * @param uint32_t TScChannelList ±£Áô²ÎÊý¡£ÉèÖÃΪ0±íʾʹÄÜÒÑ×¢²áµÄËùÓÐͨµÀ
+ * @brief 设置TSC进入低功耗(用于低功耗唤醒模å¼)
+ * @param uint32_t TScChannelList ä¿ç•™å‚数。设置为0表示使能已注册的所有通é“
* @return
- * - `TSC_SUCCESS£º ±íʾ²Ù×÷³É¹¦
- * - ÆäËüÖµ±íʾ³ö´í
- * - ×¢Ò⣺STOP2µÍ¹¦ºÄģʽʹÓã¬Õý³£Ä£Ê½Ï²»¹Ø×¢¡£
+ * - `TSC_SUCCESS： 表示æ“作æˆåŠŸ
+ * - 其它值表示出错
+ * - 注æ„：STOP2低功耗模å¼ä½¿ç”¨ï¼Œæ£å¸¸æ¨¡å¼ä¸‹ä¸å…³æ³¨ã€‚
*/
int32_t tsc_alg_set_powerdown(uint32_t TscChannelList);
////////////////////////////////////////////////////////////
-/*****************ÉϲãÓ¦ÓÃÌṩµÄ°´¼ü»Øµ÷´¦Àíº¯Êý*********
- * @brief ×¢²á°´Å¥ÐÍ¡¢»¬ÌõÐÍ¡¢×ªÂÖÐÍ´¥¿ØµÄ»Øµ÷º¯Êý
- * @param tsc_touch_type type ²úÉúµÄ´¥¿ØÀàÐÍ(ÔÝÖ»Ö§³Ö°´¼üÐÍ)
- * @param uint32_t event 0:Õý³£´¥Ãþʼþ£»
- * @param uint32_t chn ±íʾ´¥ÃþͨµÀºÅ£»
- * @param uint32_t value ´¥Ãþ״̬£º1ѹÏ£»0ËÉ¿ª£»
+/*****************上层应用æ供的按键回调处ç†å‡½æ•°*********
+ * @brief 注册按钮型ã€æ»‘æ¡åž‹ã€è½¬è½®åž‹è§¦æŽ§çš„回调函数
+ * @param tsc_touch_type type 产生的触控类型(æš‚åªæ”¯æŒæŒ‰é”®åž‹)
+ * @param uint32_t event 0:æ£å¸¸è§¦æ‘¸äº‹ä»¶ï¼›
+ * @param uint32_t chn 表示触摸通é“å·ï¼›
+ * @param uint32_t value 触摸状æ€ï¼š1压下；0æ¾å¼€ï¼›
* @return
- * - `TSC_SUCCESS£º ±íʾ²Ù×÷³É¹¦
- * - ÆäËüÖµ±íʾ³ö´í
- * ×¢Òâ:´Ë»Øµ÷º¯Êý½«ÔÚÖжÏÖе÷Óã¬Òò´Ë¾¡Á¿¼õÉٻص÷º¯ÊýµÄ´¦Àíʱ¼ä¡£
+ * - `TSC_SUCCESS： 表示æ“作æˆåŠŸ
+ * - 其它值表示出错
+ * 注æ„:æ¤å›žè°ƒå‡½æ•°å°†åœ¨ä¸æ–ä¸è°ƒç”¨ï¼Œå› æ¤å°½é‡å‡å°‘回调函数的处ç†æ—¶é—´ã€‚
********************************************************/
int32_t tsc_alg_isr_callback(tsc_alg_type type, uint32_t event, uint32_t chn, uint32_t value);
/**
- * @brief ´¥¿ØÊý¾ÝÊä³öµ½PCµÄ½Ó¿Ú£¬ÒÔ±ãÓÚPC¶Ë¹¤¾ß¹Û²ì£¬É趨ºÏÀíµÄ´¥¿ØãÐÖµ
- * @param uint32_t chn ´¥¿ØͨµÀ
- * @return uint8_t data ¸Ã´¥¿ØͨµÀÊý¾Ý
+ * @brief 触控数æ®è¾“出到PC的接å£ï¼Œä»¥ä¾¿äºŽPC端工具观察，设定åˆç†çš„触控阈值
+ * @param uint32_t chn 触控通é“
+ * @return uint8_t data 该触控通é“æ•°æ®
*/
void tsc_alg_debug_output(uint32_t chn, uint8_t data);
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/misc.c b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/misc.c
index 274a8058cb..f00bc46507 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/misc.c
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/misc.c
@@ -199,7 +199,6 @@ void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState Cmd)
* @brief Configures the SysTick clock source.
* @param SysTick_CLKSource specifies the SysTick clock source.
* This parameter can be one of the following values:
- * @arg SysTick_CLKSource_HCLK_Div8 AHB clock divided by 8 selected as SysTick clock source.
* @arg SysTick_CLKSource_HCLK AHB clock selected as SysTick clock source.
*/
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
@@ -210,10 +209,10 @@ void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
{
SysTick->CTRL |= SysTick_CLKSource_HCLK;
}
- else
- {
- //SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
- }
+// else
+// {
+// SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
+// }
}
/**
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_adc.c b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_adc.c
index d0b34c004d..bcbe058db2 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_adc.c
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_adc.c
@@ -150,7 +150,7 @@
#define DAT_ADDR ((uint32_t)0x4001244C)
/* ADC STS register mask */
-#define ADC_STS_RESERVE_MASK ((uint32_t)0x0000007F)
+#define ADC_STS_RESERVE_MASK ((uint32_t)0x0000007F)
/**
* @}
@@ -393,7 +393,7 @@ void ADC_StartCalibration(ADC_Module* ADCx)
/* Check the parameters */
assert_param(IsAdcModule(ADCx));
/* Enable the selected ADC calibration process */
- if(ADCx->CALFACT==0)
+ if (ADCx->CALFACT==0)
ADCx->CTRL2 |= CTRL2_CAL_SET;
}
@@ -418,7 +418,7 @@ FlagStatus ADC_GetCalibrationStatus(ADC_Module* ADCx)
/* CAL bit is reset: end of calibration */
bitstatus = RESET;
}
- if(ADCx->CALFACT!=0)
+ if (ADCx->CALFACT!=0)
bitstatus = RESET;
/* Return the CAL bit status */
return bitstatus;
@@ -703,7 +703,7 @@ uint32_t ADC_GetDualModeConversionDat(ADC_Module* ADCx)
/* Check the parameters */
assert_param(IsAdcModule(ADCx));
/* Return the dual mode conversion value */
- if(ADCx==ADC1 | ADCx==ADC2)
+ if ((ADCx==ADC1) | (ADCx==ADC2))
return (uint32_t)ADC1->DAT;
else
return (uint32_t)ADC3->DAT;
@@ -1332,7 +1332,7 @@ void ADC_InitEx(ADC_Module* ADCx, ADC_InitTypeEx* ADC_InitStructEx)
tmpregister |= ADC_InitStructEx->ResBit;
tmpregister &= (~ADC_CTRL3_CKMOD_MSK);
- if(ADC_InitStructEx->ClkMode==ADC_CTRL3_CKMOD_PLL)
+ if (ADC_InitStructEx->ClkMode==ADC_CTRL3_CKMOD_PLL)
tmpregister |= ADC_CTRL3_CKMOD_MSK;
ADCx->CTRL3 = tmpregister;
@@ -1420,7 +1420,7 @@ void ADC_SetConvResultBitNum(ADC_Module* ADCx, uint32_t ResultBitNum)
*/
void ADC_AHB_Clock_Mode_Config(ADC_Module* ADCx)
{
- ADCx->CTRL3 &= ADC_CLOCK_AHB;
+ ADCx->CTRL3 &= ADC_CLOCK_AHB;
}
/**
@@ -1428,8 +1428,8 @@ void ADC_AHB_Clock_Mode_Config(ADC_Module* ADCx)
* @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
*/
void ADC_PLL_Clock_Mode_Config(ADC_Module* ADCx)
-{
- ADCx->CTRL3 |= ADC_CLOCK_PLL;
+{
+ ADCx->CTRL3 |= ADC_CLOCK_PLL;
}
/**
* @brief Configures the ADCHCLK prescaler.
@@ -1463,7 +1463,7 @@ void ADC_PLL_Clock_Mode_Config(ADC_Module* ADCx)
*/
void ADC_ConfigClk(ADC_CTRL3_CKMOD ADC_ClkMode, uint32_t RCC_ADCHCLKPrescaler)
{
- if(ADC_ClkMode==ADC_CTRL3_CKMOD_AHB)
+ if (ADC_ClkMode==ADC_CTRL3_CKMOD_AHB)
{
RCC_ConfigAdcPllClk(RCC_ADCPLLCLK_DIV1, DISABLE);
RCC_ConfigAdcHclk(RCC_ADCHCLKPrescaler);
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_can.c b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_can.c
index 6ec9f947e9..5174958d6c 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_can.c
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_can.c
@@ -1173,7 +1173,7 @@ FlagStatus CAN_GetFlagSTS(CAN_Module* CANx, uint32_t CAN_FLAG)
bitstatus = RESET;
}
}
- else /* If(CAN_FLAG & CAN_FLAGS_RFF1 != (uint32_t)RESET) */
+ else /* if (CAN_FLAG & CAN_FLAGS_RFF1 != (uint32_t)RESET) */
{
/* Check the status of the specified CAN flag */
if ((uint32_t)(CANx->RFF1 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
@@ -1238,7 +1238,7 @@ void CAN_ClearFlag(CAN_Module* CANx, uint32_t CAN_FLAG)
/* Transmit Flags */
CANx->TSTS = (uint32_t)(flagtmp);
}
- else /* If((CAN_FLAG & CAN_FLAGS_MSTS)!=(uint32_t)RESET) */
+ else /* if ((CAN_FLAG & CAN_FLAGS_MSTS)!=(uint32_t)RESET) */
{
/* Operating mode Flags */
CANx->MSTS = (uint32_t)(flagtmp);
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_comp.c b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_comp.c
index f8e0c53b12..1f43a7a747 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_comp.c
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_comp.c
@@ -87,7 +87,7 @@
/** @addtogroup COMP_Private_Functions
* @{
*/
-#define SetBitMsk(reg, bit, msk) ((reg) = ((reg) & ~(msk) | (bit)))
+#define SetBitMsk(reg, bit, msk) ((reg) = (((reg) & ~(msk)) | (bit)))
#define ClrBit(reg, bit) ((reg) &= ~(bit))
#define SetBit(reg, bit) ((reg) |= (bit))
#define GetBit(reg, bit) ((reg) & (bit))
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_dbg.c b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_dbg.c
index 743295129e..199f5e1ffb 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_dbg.c
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_dbg.c
@@ -98,7 +98,7 @@ void GetUCID(uint8_t *UCIDbuf)
uint8_t num = 0;
uint32_t* ucid_addr = (uint32_t*)0;
uint32_t temp = 0;
-
+
if (0xFFFFFFFF == *(uint32_t*)(0x1FFFF260))
{
ucid_addr = (uint32_t*)UCID_BASE;
@@ -107,10 +107,10 @@ void GetUCID(uint8_t *UCIDbuf)
{
ucid_addr = (uint32_t*)(0x1FFFF260);
}
-
+
for (num = 0; num < UCID_LENGTH;)
{
- temp = *(__IO uint32_t*)(ucid_addr++);
+ temp = *(__IO uint32_t*)(ucid_addr++);
UCIDbuf[num++] = (temp & 0xFF);
UCIDbuf[num++] = (temp & 0xFF00) >> 8;
UCIDbuf[num++] = (temp & 0xFF0000) >> 16;
@@ -128,7 +128,7 @@ void GetUID(uint8_t *UIDbuf)
uint8_t num = 0;
uint32_t* uid_addr = (uint32_t*)0;
uint32_t temp = 0;
-
+
if (0xFFFFFFFF == *(uint32_t*)(0x1FFFF270))
{
uid_addr = (uint32_t*)UID_BASE;
@@ -137,7 +137,7 @@ void GetUID(uint8_t *UIDbuf)
{
uid_addr = (uint32_t*)(0x1FFFF270);
}
-
+
for (num = 0; num < UID_LENGTH;)
{
temp = *(__IO uint32_t*)(uid_addr++);
@@ -158,11 +158,11 @@ void GetDBGMCU_ID(uint8_t *DBGMCU_IDbuf)
uint8_t num = 0;
uint32_t* dbgid_addr = (uint32_t*)0;
uint32_t temp = 0;
-
+
dbgid_addr = (uint32_t*)DBGMCU_ID_BASE;
for (num = 0; num < DBGMCU_ID_LENGTH;)
{
- temp = *(__IO uint32_t*)(dbgid_addr++);
+ temp = *(__IO uint32_t*)(dbgid_addr++);
DBGMCU_IDbuf[num++] = (temp & 0xFF);
DBGMCU_IDbuf[num++] = (temp & 0xFF00) >> 8;
DBGMCU_IDbuf[num++] = (temp & 0xFF0000) >> 16;
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_dvp.c b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_dvp.c
index 3672816dfa..5bc7227465 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_dvp.c
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_dvp.c
@@ -70,8 +70,8 @@ void DVP_Init( DVP_InitType* DVP_InitStruct)
/*---------------------------- DVP CTRL Configuration -----------------------*/
tmpregister = 0;
- tmpregister |= DVP_InitStruct->LineCapture | DVP_InitStruct->ByteCapture
- | DVP_InitStruct->DataInvert | DVP_InitStruct->PixelClkPolarity
+ tmpregister |= DVP_InitStruct->LineCapture | DVP_InitStruct->ByteCapture
+ | DVP_InitStruct->DataInvert | DVP_InitStruct->PixelClkPolarity
| DVP_InitStruct->VsyncPolarity | DVP_InitStruct->HsyncPolarity
| DVP_InitStruct->CaptureMode | DVP_InitStruct->FifoWatermark;
DVP->CTRL = tmpregister;
@@ -79,7 +79,7 @@ void DVP_Init( DVP_InitType* DVP_InitStruct)
/*---------------------------- DVP WST Configuration -----------------------*/
if (DVP_InitStruct->RowStart)
DVP_InitStruct->RowStart--;
-
+
if (DVP_InitStruct->ColumnStart)
DVP_InitStruct->ColumnStart--;
@@ -162,5 +162,5 @@ void DVP_ResetFifo(void)
DVP->CTRL |= DVP_FIFO_SOFT_RESET;
- while(DVP->CTRL & DVP_FIFO_SOFT_RESET);
+ while (DVP->CTRL & DVP_FIFO_SOFT_RESET);
}
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_flash.c b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_flash.c
index fc8b38ba38..78d2d07145 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_flash.c
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_flash.c
@@ -412,7 +412,7 @@ FLASH_STS FLASH_ProgramWord(uint32_t Address, uint32_t Data)
/* Check the parameters */
assert_param(IS_FLASH_ADDRESS(Address));
- if((Address & (uint32_t)0x3) != 0)
+ if ((Address & (uint32_t)0x3) != 0)
{
/* The programming address is not a multiple of 4 */
status = FLASH_ERR_ADD;
@@ -660,7 +660,7 @@ FLASH_STS FLASH_ReadOutProtectionL2_ENABLE(void)
FLASH_STS status = FLASH_COMPL;
usertmp = ((OBR_USER_MSK & FLASH->OBR) << 0x0E);
-
+
/* Get the actual read protection L1 Option Byte value */
if (FLASH_GetReadOutProtectionSTS() == RESET)
{
@@ -690,7 +690,7 @@ FLASH_STS FLASH_ReadOutProtectionL2_ENABLE(void)
if (status == FLASH_COMPL)
{
/* Clears the FLASH's pending flags */
- FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
/* if the erase operation is completed, disable the OPTER Bit */
FLASH->CTRL &= CTRL_Reset_OPTER;
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_i2c.c b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_i2c.c
index 0e0d335b2d..da8cb55a2f 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_i2c.c
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_i2c.c
@@ -188,24 +188,24 @@ void I2C_DeInit(I2C_Module* I2Cx)
/* Release I2C2 from reset state */
RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C2, DISABLE);
}
- else if (I2Cx == I2C3)
+ else if (I2Cx == I2C3)
{
/* Enable I2C2 reset state */
RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_I2C3, ENABLE);
/* Release I2C2 from reset state */
RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_I2C3, DISABLE);
}
- else if (I2Cx == I2C4)
+ else if (I2Cx == I2C4)
{
/* Enable I2C4 reset state */
- RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_I2C3, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_I2C4, ENABLE);
/* Release I2C4 from reset state */
- RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_I2C3, DISABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_I2C4, DISABLE);
+ }
+ else
+ {
+
}
- else
- {
-
- }
}
/**
@@ -237,7 +237,7 @@ void I2C_Init(I2C_Module* I2Cx, I2C_InitType* I2C_InitStruct)
tmpregister &= CTRL2_CLKFREQ_RESET;
/* Get APB1/2 frequency value */
RCC_GetClocksFreqValue(&rcc_clocks);
-
+
if ((I2Cx == I2C1) || (I2Cx == I2C2))
{
pclk = rcc_clocks.Pclk1Freq;
@@ -249,11 +249,11 @@ void I2C_Init(I2C_Module* I2Cx, I2C_InitType* I2C_InitStruct)
/* Set frequency bits depending on pclk1 value */
freqrange = (uint16_t)(pclk / 1000000);
- if (freqrange > 36)
+ if (freqrange > 36)
{
freqrange = 36;
}
- /* Write to I2Cx CTRL2 */
+ /* Write to I2Cx CTRL2 */
tmpregister |= freqrange;
I2Cx->CTRL2 = tmpregister;
@@ -304,7 +304,7 @@ void I2C_Init(I2C_Module* I2Cx, I2C_InitType* I2C_InitStruct)
}
/* Set speed value and set F/S bit for fast mode */
tmpregister |= (uint16_t)(result | CLKCTRL_FSMODE_SET);
-
+
/* Set Maximum Rise Time for fast mode */
I2Cx->TMRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
}
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_opamp.c b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_opamp.c
index d8dd50db71..0e51983f3b 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_opamp.c
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_opamp.c
@@ -87,7 +87,7 @@
/** @addtogroup OPAMP_Private_Functions
* @{
*/
-#define SetBitMsk(reg, bit, msk) ((reg) = ((reg) & ~(msk) | (bit)))
+#define SetBitMsk(reg, bit, msk) ((reg) = (((reg) & ~(msk)) | (bit)))
#define ClrBit(reg, bit) ((reg) &= ~(bit))
#define SetBit(reg, bit) ((reg) |= (bit))
#define GetBit(reg, bit) ((reg) & (bit))
@@ -112,19 +112,19 @@ void OPAMP_Init(OPAMPX OPAMPx, OPAMP_InitType* OPAMP_InitStruct)
{
__IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
__IO uint32_t tmp = *pCs;
-
+
SetBitMsk(tmp, OPAMP_InitStruct->Gain, OPAMP_CS_PGA_GAIN_MASK);
-
- if(OPAMP_InitStruct->HighVolRangeEn==ENABLE)
+
+ if (OPAMP_InitStruct->HighVolRangeEn==ENABLE)
SetBitMsk(tmp, OPAMP_CS_RANGE_MASK, OPAMP_CS_RANGE_MASK);
else
ClrBit(tmp,OPAMP_CS_RANGE_MASK);
- if(OPAMP_InitStruct->TimeAutoMuxEn==ENABLE)
+ if (OPAMP_InitStruct->TimeAutoMuxEn==ENABLE)
SetBitMsk(tmp,OPAMP_CS_TCMEN_MASK, OPAMP_CS_TCMEN_MASK);
else
ClrBit(tmp,OPAMP_CS_TCMEN_MASK);
-
+
SetBitMsk(tmp, OPAMP_InitStruct->Mod, OPAMP_CS_MOD_MASK);
*pCs = tmp;
}
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_qspi.c b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_qspi.c
index e51b063b71..3c05e0700f 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_qspi.c
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_qspi.c
@@ -98,15 +98,10 @@ void QspiInitConfig(QSPI_InitType* QSPI_InitStruct)
assert_param(IS_QSPI_SDCN(QSPI_InitStruct->SDCN));
assert_param(IS_QSPI_ENH_CLK_STRETCH_EN(QSPI_InitStruct->ENHANCED_CLK_STRETCH_EN));
- assert_param(IS_QSPI_ENH_XIP_MBL(QSPI_InitStruct->ENHANCED_XIP_MBL));
- assert_param(IS_QSPI_ENH_XIP_CT_EN(QSPI_InitStruct->ENHANCED_XIP_CT_EN));
- assert_param(IS_QSPI_ENH_XIP_INST_EN(QSPI_InitStruct->ENHANCED_XIP_INST_EN));
- assert_param(IS_QSPI_ENH_XIP_DFS_HC(QSPI_InitStruct->ENHANCED_XIP_DFS_HC));
assert_param(IS_QSPI_ENH_INST_DDR_EN(QSPI_InitStruct->ENHANCED_INST_DDR_EN));
assert_param(IS_QSPI_ENH_SPI_DDR_EN(QSPI_InitStruct->ENHANCED_SPI_DDR_EN));
assert_param(IS_QSPI_ENH_WAIT_CYCLES(QSPI_InitStruct->ENHANCED_WAIT_CYCLES));
assert_param(IS_QSPI_ENH_INST_L(QSPI_InitStruct->ENHANCED_INST_L));
- assert_param(IS_QSPI_ENH_MD_BIT_EN(QSPI_InitStruct->ENHANCED_MD_BIT_EN));
assert_param(IS_QSPI_ENH_ADDR_LEN(QSPI_InitStruct->ENHANCED_ADDR_LEN));
assert_param(IS_QSPI_ENH_TRANS_TYPE(QSPI_InitStruct->ENHANCED_TRANS_TYPE));
@@ -135,48 +130,47 @@ void QspiInitConfig(QSPI_InitType* QSPI_InitStruct)
assert_param(IS_QSPI_TXFN(QSPI_InitStruct->TXFN));
assert_param(IS_QSPI_RXFN(QSPI_InitStruct->RXFN));
assert_param(IS_QSPI_DDR_TXDE(QSPI_InitStruct->TXDE));
-
- if((QSPI_InitStruct->SPI_FRF) == QSPI_CTRL0_SPI_FRF_STANDARD_FORMAT)
+
+ if ((QSPI_InitStruct->SPI_FRF) == QSPI_CTRL0_SPI_FRF_STANDARD_FORMAT)
{
- tmpregister = (uint32_t)(QSPI_InitStruct->SPI_FRF | QSPI_InitStruct->CFS | QSPI_InitStruct->SSTE | QSPI_InitStruct->TMOD
+ tmpregister = (uint32_t)(QSPI_InitStruct->SPI_FRF | QSPI_InitStruct->CFS | QSPI_InitStruct->SSTE | QSPI_InitStruct->TMOD
| QSPI_InitStruct->SCPOL | QSPI_InitStruct->SCPH | QSPI_InitStruct->FRF | QSPI_InitStruct->DFS);
- QSPI->CTRL0 = tmpregister;
-
+ QSPI->CTRL0 = tmpregister;
+
tmpregister = 0;
tmpregister = (uint32_t)(QSPI_InitStruct->MWMOD | QSPI_InitStruct->MC_DIR | QSPI_InitStruct->MHS_EN);
QSPI->MW_CTRL = tmpregister;
-
+
tmpregister = 0;
tmpregister = (uint32_t)(QSPI_InitStruct->SES | QSPI_InitStruct->SDCN);
QSPI->RS_DELAY = tmpregister;
}
- else if((QSPI_InitStruct->SPI_FRF == QSPI_CTRL0_SPI_FRF_DUAL_FORMAT) || (QSPI_InitStruct->SPI_FRF == QSPI_CTRL0_SPI_FRF_QUAD_FORMAT))
+ else if ((QSPI_InitStruct->SPI_FRF == QSPI_CTRL0_SPI_FRF_DUAL_FORMAT) || (QSPI_InitStruct->SPI_FRF == QSPI_CTRL0_SPI_FRF_QUAD_FORMAT))
{
- tmpregister = (uint32_t)(QSPI_InitStruct->SPI_FRF | QSPI_InitStruct->CFS | QSPI_InitStruct->SSTE | QSPI_InitStruct->TMOD
+ tmpregister = (uint32_t)(QSPI_InitStruct->SPI_FRF | QSPI_InitStruct->CFS | QSPI_InitStruct->SSTE | QSPI_InitStruct->TMOD
| QSPI_InitStruct->SCPOL | QSPI_InitStruct->SCPH | QSPI_InitStruct->FRF | QSPI_InitStruct->DFS);
QSPI->CTRL0 = tmpregister;
-
+
tmpregister = 0;
tmpregister = (uint32_t)(QSPI_InitStruct->MWMOD | QSPI_InitStruct->MC_DIR | QSPI_InitStruct->MHS_EN);
QSPI->MW_CTRL = tmpregister;
-
+
tmpregister = 0;
tmpregister = (uint32_t)(QSPI_InitStruct->SES | QSPI_InitStruct->SDCN);
QSPI->RS_DELAY = tmpregister;
-
+
tmpregister = 0;
- tmpregister = (uint32_t)(QSPI_InitStruct->ENHANCED_CLK_STRETCH_EN | QSPI_InitStruct->ENHANCED_XIP_MBL | QSPI_InitStruct->ENHANCED_XIP_CT_EN
- | QSPI_InitStruct->ENHANCED_XIP_INST_EN | QSPI_InitStruct->ENHANCED_XIP_DFS_HC | QSPI_InitStruct->ENHANCED_INST_DDR_EN
+ tmpregister = (uint32_t)(QSPI_InitStruct->ENHANCED_CLK_STRETCH_EN | QSPI_InitStruct->ENHANCED_INST_DDR_EN
| QSPI_InitStruct->ENHANCED_SPI_DDR_EN | QSPI_InitStruct->ENHANCED_WAIT_CYCLES | QSPI_InitStruct->ENHANCED_INST_L
- | QSPI_InitStruct->ENHANCED_MD_BIT_EN | QSPI_InitStruct->ENHANCED_ADDR_LEN | QSPI_InitStruct->ENHANCED_TRANS_TYPE);
+ | QSPI_InitStruct->ENHANCED_ADDR_LEN | QSPI_InitStruct->ENHANCED_TRANS_TYPE);
QSPI->ENH_CTRL0 = tmpregister;
-
+
tmpregister = 0;
tmpregister = (uint32_t)(QSPI_InitStruct->XIP_MBL | QSPI_InitStruct->XIP_CT_EN | QSPI_InitStruct->XIP_INST_EN | QSPI_InitStruct->XIP_INST_DDR_EN
| QSPI_InitStruct->XIP_DDR_EN | QSPI_InitStruct->XIP_DFS_HC | QSPI_InitStruct->XIP_WAIT_CYCLES | QSPI_InitStruct->XIP_MD_BITS_EN
| QSPI_InitStruct->XIP_INST_L | QSPI_InitStruct->XIP_ADDR_LEN | QSPI_InitStruct->XIP_TRANS_TYPE | QSPI_InitStruct->XIP_FRF);
QSPI->XIP_CTRL = tmpregister;
-
+
QSPI->XIP_MODE = QSPI_InitStruct->XIP_MD_BITS;
QSPI->XIP_INCR_TOC = QSPI_InitStruct->ITOC;
QSPI->XIP_WRAP_TOC = QSPI_InitStruct->WTOC;
@@ -188,7 +182,7 @@ void QspiInitConfig(QSPI_InitType* QSPI_InitStruct)
QSPI->RXFT = QSPI_InitStruct->RXFT;
QSPI->TXFN = QSPI_InitStruct->TXFN;
QSPI->RXFN = QSPI_InitStruct->RXFN;
- QSPI->DDR_TXDE = QSPI_InitStruct->TXDE;
+ QSPI->DDR_TXDE = QSPI_InitStruct->TXDE;
}
/**
* @brief Configure single GPIO port as GPIO_Mode_AF_PP.
@@ -238,14 +232,14 @@ void QSPI_GPIO(QSPI_NSS_PORT_SEL qspi_nss_port_sel, bool IO1_Input, bool IO3_Out
{
QSPI_SingleGpioConfig(GPIOA, GPIO_PIN_7); // IO1
}
-
+
if (IO3_Output)
{
GPIO_InitStructure.Pin = GPIO_PIN_4 | GPIO_PIN_5; // IO2 and IO3
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitPeripheral(GPIOC, &GPIO_InitStructure);
-
+
GPIOC->PBSC |= GPIO_PIN_4 | GPIO_PIN_5;
}
else
@@ -275,14 +269,14 @@ void QSPI_GPIO(QSPI_NSS_PORT_SEL qspi_nss_port_sel, bool IO1_Input, bool IO3_Out
{
QSPI_SingleGpioConfig(GPIOD, GPIO_PIN_0); // IO1
}
-
+
if (IO3_Output)
{
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2; // IO2 and IO3
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitPeripheral(GPIOD, &GPIO_InitStructure);
-
+
GPIOD->PBSC |= GPIO_PIN_1 | GPIO_PIN_2;
}
else
@@ -310,14 +304,14 @@ void QSPI_GPIO(QSPI_NSS_PORT_SEL qspi_nss_port_sel, bool IO1_Input, bool IO3_Out
{
QSPI_SingleGpioConfig(GPIOF, GPIO_PIN_3); // IO1
}
-
+
if (IO3_Output)
{
GPIO_InitStructure.Pin = GPIO_PIN_4 | GPIO_PIN_5; // IO2 and IO3
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitPeripheral(GPIOF, &GPIO_InitStructure);
-
+
GPIOF->PBSC |= GPIO_PIN_4 | GPIO_PIN_5;
}
else
@@ -330,32 +324,48 @@ void QSPI_GPIO(QSPI_NSS_PORT_SEL qspi_nss_port_sel, bool IO1_Input, bool IO3_Out
break;
}
}
+
/**
* @brief Configuration of QSPI DMA.
- * @param TxRx transmit or receive data.
+ * @param Tx transmit or receive data.
QSPI_DMA_CTRL_TX_DMA_EN:transmit data
- QSPI_DMA_CTRL_RX_DMA_EN:receive data
* @param TxDataLevel dma transmit data level.
+ */
+void QSPI_Tx_DMA_CTRL_Config(uint8_t Cmd,uint8_t TxDataLevel)
+{
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ assert_param(IS_QSPI_DMATDL_CTRL(TxDataLevel));
+ if (Cmd)
+ {
+ QSPI->DMATDL_CTRL = TxDataLevel;
+ QSPI->DMA_CTRL |= QSPI_DMA_CTRL_TX_DMA_EN;
+ }
+ else
+ {
+ QSPI->DMA_CTRL &= ~QSPI_DMA_CTRL_TX_DMA_EN;
+ }
+}
+
+/**
+ * @brief Configuration of QSPI DMA.
+ * @param Rx transmit or receive data.
+ QSPI_DMA_CTRL_RX_DMA_EN:receive data
* @param RxDataLevel dma receive data level.
*/
-void QSPI_DMA_CTRL_Config(uint8_t TxRx,uint8_t TxDataLevel,uint8_t RxDataLevel)
+void QSPI_Rx_DMA_CTRL_Config(uint8_t Cmd, uint8_t RxDataLevel)
{
- assert_param(IS_QSPI_DMA_CTRL(TxRx));
- assert_param(IS_QSPI_DMATDL_CTRL(TxDataLevel));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
assert_param(IS_QSPI_DMARDL_CTRL(RxDataLevel));
-
- QSPI->DMA_CTRL = 0x00;
-
- if (TxRx & QSPI_DMA_CTRL_TX_DMA_EN)
- {
- QSPI->DMATDL_CTRL = TxDataLevel;
- QSPI->DMA_CTRL |= QSPI_DMA_CTRL_TX_DMA_EN;
- }
- if (TxRx & QSPI_DMA_CTRL_RX_DMA_EN)
+
+ if (Cmd)
{
QSPI->DMARDL_CTRL = RxDataLevel;
QSPI->DMA_CTRL |= QSPI_DMA_CTRL_RX_DMA_EN;
}
+ else
+ {
+ QSPI->DMA_CTRL &= ~QSPI_DMA_CTRL_RX_DMA_EN;
+ }
}
/**
* @brief Get the flag of interrupt status register.
@@ -376,18 +386,19 @@ uint16_t QSPI_GetITStatus(uint16_t FLAG)
*/
void QSPI_ClearITFLAG(uint16_t FLAG)
{
- volatile uint16_t tmp = 0;
-
if (FLAG == QSPI_ISTS_TXFOIS)
- tmp = QSPI->TXFOI_CLR;
- if (FLAG == QSPI_ISTS_RXFOIS)
- tmp = QSPI->RXFOI_CLR;
- if (FLAG == QSPI_ISTS_RXFUIS)
- tmp = QSPI->RXFUI_CLR;
- if (FLAG == QSPI_ISTS_MMCIS)
- tmp = QSPI->MMC_CLR;
- if (FLAG == QSPI_ISTS)
- tmp = QSPI->ICLR;
+ (void)QSPI->TXFOI_CLR;
+ else if (FLAG == QSPI_ISTS_RXFOIS)
+ (void)QSPI->RXFOI_CLR;
+ else if (FLAG == QSPI_ISTS_RXFUIS)
+ (void)QSPI->RXFUI_CLR;
+ else if (FLAG == QSPI_ISTS_MMCIS)
+ (void)QSPI->MMC_CLR;
+ else if (FLAG == QSPI_ISTS)
+ (void)QSPI->ICLR;
+ else
+ {
+ }
}
/**
* @brief Clear the flag of related interrupt register.
@@ -395,10 +406,11 @@ void QSPI_ClearITFLAG(uint16_t FLAG)
*/
void QSPI_XIP_ClearITFLAG(uint16_t FLAG)
{
- volatile uint16_t tmp = 0;
-
if (FLAG == QSPI_XIP_RXFOI_CLR_XRXFOIC)
- tmp = QSPI->XIP_RXFOI_CLR;
+ (void)QSPI->XIP_RXFOI_CLR;
+ else
+ {
+ }
}
/**
* @brief Get QSPI status,busy or not.
@@ -450,16 +462,7 @@ bool GetQspiRxDataFullStatus(void)
return 1;
return 0;
}
-/**
- * @brief Check transmit error or not.
- * @return 1: Transmit error;0: No transmit error.
- */
-bool GetQspiTransmitErrorStatus(void)
-{
- if ((QSPI->STS & 0x20) == 0x20)
- return 1;
- return 0;
-}
+
/**
* @brief Check data conflict error or not.
* @return 1: Data conflict error;0: No data conflict error.
@@ -512,7 +515,7 @@ void ClrFifo(void)
while (GetQspiRxHaveDataStatus())
{
QspiReadWord();
- if(++timeout >= 200)
+ if (++timeout >= 200)
{
break;
}
@@ -550,7 +553,7 @@ void QspiSendAndGetWords(uint32_t* pSrcData, uint32_t* pDstData, uint32_t cnt)
{
uint32_t num = 0;
uint32_t timeout = 0;
-
+
while (num < cnt)
{
QspiSendWord(*(pSrcData++));
@@ -558,7 +561,7 @@ void QspiSendAndGetWords(uint32_t* pSrcData, uint32_t* pDstData, uint32_t cnt)
}
while (!GetQspiRxHaveDataStatus())
{
- if(++timeout >= QSPI_TIME_OUT_CNT)
+ if (++timeout >= QSPI_TIME_OUT_CNT)
{
break;
}
@@ -566,7 +569,7 @@ void QspiSendAndGetWords(uint32_t* pSrcData, uint32_t* pDstData, uint32_t cnt)
timeout = 0;
while (QSPI->RXFN < cnt)
{
- if(++timeout >= QSPI_TIME_OUT_CNT)
+ if (++timeout >= QSPI_TIME_OUT_CNT)
{
break;
}
@@ -591,21 +594,21 @@ uint32_t QspiSendWordAndGetWords(uint32_t WrData, uint32_t* pRdData, uint8_t Las
uint32_t timeout1 = 0;
QspiSendWord(WrData); //trammit
- *pRdData = QspiReadWord();
- if(LastRd != 0)
+ *pRdData = QspiReadWord();
+ if (LastRd != 0)
{
- while(!GetQspiRxHaveDataStatus()) //wait for data
+ while (!GetQspiRxHaveDataStatus()) //wait for data
{
- if(++timeout1 >= QSPI_TIME_OUT_CNT)
+ if (++timeout1 >= QSPI_TIME_OUT_CNT)
{
return QSPI_NULL; //time out
}
}
- *pRdData = QspiReadWord(); //read data
- return QSPI_SUCCESS;
+ *pRdData = QspiReadWord(); //read data
+ return QSPI_SUCCESS;
}
-
+
return QSPI_NULL;
}
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_rtc.c b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_rtc.c
index 8a65046ab8..fa398d3d55 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_rtc.c
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_rtc.c
@@ -102,7 +102,7 @@ static uint8_t RTC_Bcd2ToByte(uint8_t Value);
/**
* @brief Deinitializes the RTC registers to their default reset values.
- * @note This function doesn't reset the RTC Clock source
+ * @note This function doesn't reset the RTC Clock source
* @return An ErrorStatus enumeration value:
* - SUCCESS: RTC registers are deinitialized
* - ERROR: RTC registers are not deinitialized
@@ -535,7 +535,7 @@ ErrorStatus RTC_ConfigTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct)
}
/* Enable the write protection for RTC registers */
RTC->WRP = 0xFF;
- /* Waits until the RTC Time and Date registers
+ /* Waits until the RTC Time and Date registers
(RTC_TSH and RTC_DATE) are synchronized with RTC APB clock. */
status=RTC_WaitForSynchro();
return status;
@@ -694,7 +694,7 @@ ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct)
}
/* Enable the write protection for RTC registers */
RTC->WRP = 0xFF;
- /* Waits until the RTC Time and Date registers
+ /* Waits until the RTC Time and Date registers
(RTC_TSH and RTC_DATE) are synchronized with RTC APB clock. */
status=RTC_WaitForSynchro();
return status;
@@ -1345,7 +1345,6 @@ uint32_t RTC_GetStoreOperation(void)
*/
void RTC_ConfigOutput(uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
{
- __IO uint32_t temp = 0;
/* Check the parameters */
assert_param(IS_RTC_OUTPUT_MODE(RTC_Output));
assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity));
@@ -1574,14 +1573,14 @@ void RTC_EnableTimeStamp(uint32_t RTC_TimeStampEdge, FunctionalState Cmd)
void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeType* RTC_StampTimeStruct, RTC_DateType* RTC_StampDateStruct)
{
uint32_t tmptime = 0, tmpdate = 0;
-
+
/* Check the parameters */
assert_param(IS_RTC_FORMAT(RTC_Format));
/* Get the TimeStamp time and date registers values */
tmptime = (uint32_t)(RTC->TST & RTC_TR_RESERVED_MASK);
tmpdate = (uint32_t)(RTC->TSD & RTC_DATE_RESERVED_MASK);
-
+
/* Fill the Time structure fields with the read parameters */
RTC_StampTimeStruct->Hours = (uint8_t)((tmptime & (RTC_TSH_HOT | RTC_TSH_HOU)) >> 16);
RTC_StampTimeStruct->Minutes = (uint8_t)((tmptime & (RTC_TSH_MIT | RTC_TSH_MIU)) >> 8);
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_sdio.c b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_sdio.c
index cff0be44fd..c8c45d7a3b 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_sdio.c
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_sdio.c
@@ -456,15 +456,15 @@ void SDIO_ConfigData(SDIO_DataInitType* SDIO_DataInitStruct)
/* Set DBCKSIZE bits according to DatBlkSize value */
tmpregister |= (uint32_t)SDIO_DataInitStruct->DatBlkSize | SDIO_DataInitStruct->TransferDirection
| SDIO_DataInitStruct->TransferMode | SDIO_DataInitStruct->DPSMConfig;
-
- if(SDIO_DataInitStruct->TransferDirection)
+
+ if (SDIO_DataInitStruct->TransferDirection)
{
tmpregister &= ~(1<<12);
}
else
{
tmpregister |= 1<<12;
- }
+ }
/* Write to SDIO DATCTRL */
SDIO->DATCTRL = tmpregister;
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_tim.c b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_tim.c
index 41e441db65..6a275dcc27 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_tim.c
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_tim.c
@@ -1056,7 +1056,6 @@ void TIM_GenerateEvent(TIM_Module* TIMx, uint16_t TIM_EventSource)
* TIM_DMABASE_CNT, TIM_DMABASE_PSC, TIM_DMABASE_AR,
* TIM_DMABASE_REPCNT, TIM_DMABASE_CAPCMPDAT1, TIM_DMABASE_CAPCMPDAT2,
* TIM_DMABASE_CAPCMPDAT3, TIM_DMABASE_CAPCMPDAT4, TIM_DMABASE_BKDT,
- * TIM_DMABASE_CAPCMPMOD3, TIM_DMABASE_CAPCMPDAT5, TIM_DMABASE_CAPCMPDAT6,
* TIM_DMABASE_DMACTRL.
* @param TIM_DMABurstLength DMA Burst length.
* This parameter can be one value between:
@@ -2938,7 +2937,7 @@ FlagStatus TIM_GetCCENStatus(TIM_Module* TIMx, uint32_t TIM_CCEN)
/* Check the parameters */
assert_param(IsTimList3Module(TIMx));
- if(TIMx==TIM1 || TIMx==TIM8)
+ if (TIMx==TIM1 || TIMx==TIM8)
{
assert_param(IsAdvancedTimCCENFlag(TIM_CCEN));
if ((TIMx->CCEN & TIM_CCEN) != (uint32_t)RESET)
@@ -2950,7 +2949,7 @@ FlagStatus TIM_GetCCENStatus(TIM_Module* TIMx, uint32_t TIM_CCEN)
bitstatus = RESET;
}
}
- else if(TIMx==TIM2 || TIMx==TIM3 || TIMx==TIM4 || TIMx==TIM5 )
+ else if (TIMx==TIM2 || TIMx==TIM3 || TIMx==TIM4 || TIMx==TIM5 )
{
assert_param(IsGeneralTimCCENFlag(TIM_CCEN));
if ((TIMx->CCEN & TIM_CCEN) != (uint32_t)RESET)
@@ -2962,7 +2961,7 @@ FlagStatus TIM_GetCCENStatus(TIM_Module* TIMx, uint32_t TIM_CCEN)
bitstatus = RESET;
}
}
-
+
return bitstatus;
}
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_tsc.c b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_tsc.c
index dcdded30d3..50ccc9b8da 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_tsc.c
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_tsc.c
@@ -47,30 +47,30 @@ TSC_ErrorTypeDef TSC_Init(TSC_Module* TSC_Def, TSC_InitType* CtrlCfg)
assert_param(IS_TSC_FILTER(CtrlCfg->TSC_FilterCount));
assert_param(IS_TSC_DET_PERIOD(CtrlCfg->TSC_DetPeriod));
- if(TSC_Def != TSC)
+ if (TSC_Def != TSC)
return TSC_ERROR_PARAMETER;
-
+
/* waiting tsc hw for idle status.*/
timeout = 0;
do
{
__TSC_HW_DISABLE();
-
- if(++timeout > TSC_TIMEOUT)
+
+ if (++timeout > TSC_TIMEOUT)
return TSC_ERROR_HW_MODE;
}while (__TSC_GET_HW_MODE());
/*TSC_CTRL config*/
tempreg = 0;
- if(CtrlCfg->TSC_DetIntEnable)
+ if (CtrlCfg->TSC_DetIntEnable)
tempreg |= TSC_IT_DET_ENABLE;
-
- if(CtrlCfg->TSC_GreatEnable)
+
+ if (CtrlCfg->TSC_GreatEnable)
tempreg |= TSC_DET_TYPE_GREAT;
-
- if(CtrlCfg->TSC_LessEnable)
+
+ if (CtrlCfg->TSC_LessEnable)
tempreg |= TSC_DET_TYPE_LESS;
-
+
tempreg |= CtrlCfg->TSC_FilterCount;
tempreg |= CtrlCfg->TSC_DetPeriod;
@@ -80,7 +80,7 @@ TSC_ErrorTypeDef TSC_Init(TSC_Module* TSC_Def, TSC_InitType* CtrlCfg)
}
/**
- * @brief Config the clock source of TSC
+ * @brief Config the clock source of TSC
* @param TSC_ClkSource specifies the clock source of TSC
* This parameter can be one of the following values:
* @arg TSC_CLK_SRC_LSI: TSC clock source is LSI(default)
@@ -91,41 +91,41 @@ TSC_ErrorTypeDef TSC_Init(TSC_Module* TSC_Def, TSC_InitType* CtrlCfg)
TSC_ErrorTypeDef TSC_ClockConfig(uint32_t TSC_ClkSource)
{
uint32_t timeout;
-
+
/*Enable PWR peripheral Clock*/
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR,ENABLE);
- if(TSC_CLK_SRC_LSI == TSC_ClkSource)
+ if (TSC_CLK_SRC_LSI == TSC_ClkSource)
{
/*enable LSI clock*/
RCC_EnableLsi(ENABLE);
/*Wait LSI stable*/
timeout = 0;
- while(RCC_GetFlagStatus(RCC_FLAG_LSIRD) == RESET)
+ while (RCC_GetFlagStatus(RCC_FLAG_LSIRD) == RESET)
{
- if(++timeout >TSC_TIMEOUT)
+ if (++timeout >TSC_TIMEOUT)
return TSC_ERROR_CLOCK;
}
}
- else if((TSC_CLK_SRC_LSE_BYPASS==TSC_ClkSource)||(TSC_CLK_SRC_LSE==TSC_ClkSource))
+ else if ((TSC_CLK_SRC_LSE_BYPASS==TSC_ClkSource)||(TSC_CLK_SRC_LSE==TSC_ClkSource))
{
- if(RCC_GetFlagStatus(RCC_FLAG_LSERD)==RESET)
+ if (RCC_GetFlagStatus(RCC_FLAG_LSERD)==RESET)
{
// Set bit 8 of PWR_CTRL1.Open PWR DBP.
PWR_BackupAccessEnable(ENABLE);
RCC_ConfigLse(TSC_ClkSource);
timeout = 0;
- while(RCC_GetFlagStatus(RCC_FLAG_LSERD) == RESET)
+ while (RCC_GetFlagStatus(RCC_FLAG_LSERD) == RESET)
{
- if(++timeout >TSC_TIMEOUT)
+ if (++timeout >TSC_TIMEOUT)
return TSC_ERROR_CLOCK;
}
}
}
else
return TSC_ERROR_PARAMETER;
-
+
/*Enable TSC clk*/
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TSC,ENABLE);
@@ -133,18 +133,18 @@ TSC_ErrorTypeDef TSC_ClockConfig(uint32_t TSC_ClkSource)
}
/**
- * @brief Configure internal charge resistor for some channels
+ * @brief Configure internal charge resistor for some channels
* @param TSC_Def Pointer of TSC register.
* @param res: internal resistor selecte
* This parameter can be one of the following values:
* @arg TSC_RESR_CHN_RESIST_0: 1M OHM
- * @arg TSC_RESR_CHN_RESIST_1: 882K OHM
- * @arg TSC_RESR_CHN_RESIST_2: 756K OHM
- * @arg TSC_RESR_CHN_RESIST_3: 630K OHM
- * @arg TSC_RESR_CHN_RESIST_4: 504K OHM
+ * @arg TSC_RESR_CHN_RESIST_1: 882K OHM
+ * @arg TSC_RESR_CHN_RESIST_2: 756K OHM
+ * @arg TSC_RESR_CHN_RESIST_3: 630K OHM
+ * @arg TSC_RESR_CHN_RESIST_4: 504K OHM
* @arg TSC_RESR_CHN_RESIST_5: 378K OHM
- * @arg TSC_RESR_CHN_RESIST_6: 252K OHM
- * @arg TSC_RESR_CHN_RESIST_7: 126K OHM
+ * @arg TSC_RESR_CHN_RESIST_6: 252K OHM
+ * @arg TSC_RESR_CHN_RESIST_7: 126K OHM
* @param Channels: channels to be configed, as TSC_CHNEN defined
* This parameter:bit[0:23] used,bit[24:31] must be 0
* bitx: TSC channel x
@@ -157,26 +157,26 @@ TSC_ErrorTypeDef TSC_ConfigInternalResistor(TSC_Module* TSC_Def,uint32_t Channel
assert_param(IS_TSC_CHN(Channels));
assert_param(IS_TSC_RESISTOR_VALUE(res));
- if(TSC_Def != TSC)
+ if (TSC_Def != TSC)
return TSC_ERROR_PARAMETER;
/*Check charge resistor value */
- if(res > TSC_RESR_CHN_RESIST_125K)
+ if (res > TSC_RESR_CHN_RESIST_125K)
return TSC_ERROR_PARAMETER;
-
+
/* waiting tsc hw for idle status.*/
timeout = 0;
do
{
__TSC_HW_DISABLE();
-
- if(++timeout > TSC_TIMEOUT)
+
+ if (++timeout > TSC_TIMEOUT)
return TSC_ERROR_HW_MODE;
}while (__TSC_GET_HW_MODE());
/* Mask invalie bits*/
chn = Channels & TSC_CHNEN_CHN_SEL_MASK;
-
+
/* Set resistance for each channel one by one*/
for (i = 0; iMAX_TSC_THRESHOLD_BASE)||(delta>MAX_TSC_THRESHOLD_DELTA))
+ if ( (base>MAX_TSC_THRESHOLD_BASE)||(delta>MAX_TSC_THRESHOLD_DELTA))
return TSC_ERROR_PARAMETER;
-
+
/* waiting tsc hw for idle status.*/
timeout = 0;
do
{
__TSC_HW_DISABLE();
-
- if(++timeout > TSC_TIMEOUT)
+
+ if (++timeout > TSC_TIMEOUT)
return TSC_ERROR_HW_MODE;
}while (__TSC_GET_HW_MODE());
pReg = (uint32_t *)(&(TSC_Def->THRHD0));
-
+
/*Mask invalie bits*/
chn = Channels & TSC_CHNEN_CHN_SEL_MASK;
-
+
/* Set the base and delta for each channnel one by one*/
for (i = 0; i TSC_TIMEOUT)
+
+ if (++timeout > TSC_TIMEOUT)
return TSC_ERROR_HW_MODE;
}while (__TSC_GET_HW_MODE());
-
+
__TSC_CHN_CONFIG(0);
}
@@ -391,23 +391,23 @@ TSC_ErrorTypeDef TSC_SW_SwtichChn(TSC_Module* TSC_Def, uint32_t Channel, TIM_Mod
{
uint32_t i, timeout;
- if(TSC_Def != TSC)
+ if (TSC_Def != TSC)
return TSC_ERROR_PARAMETER;
if ((TIMx != TIM2) && (TIMx != TIM4))
return TSC_ERROR_PARAMETER;
-
+
/* Disable the TSC HW MODE */
timeout = 0;
do
{
__TSC_HW_DISABLE();
-
- if(++timeout > TSC_TIMEOUT)
+
+ if (++timeout > TSC_TIMEOUT)
return TSC_ERROR_HW_MODE;
}while (__TSC_GET_HW_MODE());
-
+
if (Cmd == DISABLE) // Close output by software mode
{
__TSC_OUT_CONFIG(TSC_OUT_PIN);
@@ -425,7 +425,7 @@ TSC_ErrorTypeDef TSC_SW_SwtichChn(TSC_Module* TSC_Def, uint32_t Channel, TIM_Mod
Channel >>= 1;
}
-
+
// Select to output to specified TIMER.
if (TIMx == TIM4)
{
@@ -454,18 +454,18 @@ TSC_ErrorTypeDef TSC_SW_SwtichChn(TSC_Module* TSC_Def, uint32_t Channel, TIM_Mod
*/
TSC_ErrorTypeDef TSC_SetAnaoCfg(TSC_Module* TSC_Def, TSC_AnaoCfg* AnaoCfg)
{
- if(TSC_Def != TSC)
+ if (TSC_Def != TSC)
return TSC_ERROR_PARAMETER;
-
- if(AnaoCfg == 0)
+
+ if (AnaoCfg == 0)
return TSC_ERROR_PARAMETER;
assert_param(IS_TSC_PAD_OPTION(AnaoCfg->TSC_AnaoptrResisOption));
assert_param(IS_TSC_PAD_SPEED(AnaoCfg->TSC_AnaoptrSpeedOption));
-
+
__TSC_PAD_OPT_CONFIG(AnaoCfg->TSC_AnaoptrResisOption);
__TSC_PAD_SPEED_CONFIG(AnaoCfg->TSC_AnaoptrSpeedOption);
-
+
return TSC_ERROR_OK;
}
@@ -480,18 +480,18 @@ TSC_ErrorTypeDef TSC_SetAnaoCfg(TSC_Module* TSC_Def, TSC_AnaoCfg* AnaoCfg)
TSC_ErrorTypeDef TSC_SetChannelCfg(TSC_Module* TSC_Def, TSC_ChnCfg* ChnCfg, uint32_t Channels)
{
TSC_ErrorTypeDef err;
-
- if(TSC_Def != TSC)
+
+ if (TSC_Def != TSC)
return TSC_ERROR_PARAMETER;
- if(0 == ChnCfg)
+ if (0 == ChnCfg)
return TSC_ERROR_PARAMETER;
-
+
// Set resistance
err = TSC_ConfigInternalResistor(TSC_Def, Channels, ChnCfg->TSC_ResisValue);
- if(err != TSC_ERROR_OK)
+ if (err != TSC_ERROR_OK)
return err;
-
+
// Set the threshold of base and delta.
err = TSC_ConfigThreshold(TSC_Def, Channels, ChnCfg->TSC_Base, ChnCfg->TSC_Delta);
return err;
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_usart.c b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_usart.c
index a05c332d0c..8d05d3063c 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_usart.c
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_usart.c
@@ -261,10 +261,10 @@ void USART_Init(USART_Module* USARTx, USART_InitType* USART_InitStruct)
fractionaldivider = (((((integerdivider - (100 * (tmpregister >> 4))) * 16) + 50) / 100));
/*Determine whether the fractional part needs to carried*/
- if((fractionaldivider >> 4) == 1){
+ if ((fractionaldivider >> 4) == 1){
tmpregister = ((integerdivider / 100) + 1) << 4;
}
-
+
/* Implement the fractional part in the register */
tmpregister |= fractionaldivider & ((uint8_t)0x0F);
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_regs.h b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_regs.h
index 61cb75c82f..3c8a22e561 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_regs.h
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_regs.h
@@ -500,7 +500,7 @@ enum EP_BUF_NUM
wNBlocks = wCount >> 5; \
if ((wCount & 0x1f) == 0) \
wNBlocks--; \
- *pdwReg = (uint32_t)((wNBlocks << 11) | 0x8000); \
+ *pdwReg = (uint32_t)((wNBlocks << 10) | 0x8000); \
} /* _BlocksOf32 */
#define _BlocksOf2(dwReg, wCount, wNBlocks) \
diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_int.c b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_int.c
index 66f8d4fe2a..859d1f9ec8 100644
--- a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_int.c
+++ b/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_int.c
@@ -111,7 +111,7 @@ void USB_CorrectTransferLp(void)
return;
}
}
- } /* if(EPindex == 0) */
+ } /* if (EPindex == 0) */
else
{
/* Decode and service non control endpoints interrupt */
@@ -126,7 +126,7 @@ void USB_CorrectTransferLp(void)
/* call OUT service function */
(*pEpInt_OUT[EPindex - 1])();
- } /* if((wEPVal & EP_CTRS_RX) */
+ } /* if ((wEPVal & EP_CTRS_RX) */
if ((wEPVal & EP_CTRS_TX) != 0)
{
@@ -135,11 +135,11 @@ void USB_CorrectTransferLp(void)
/* call IN service function */
(*pEpInt_IN[EPindex - 1])();
- } /* if((wEPVal & EP_CTRS_TX) != 0) */
+ } /* if ((wEPVal & EP_CTRS_TX) != 0) */
- } /* if(EPindex == 0) else */
+ } /* if (EPindex == 0) else */
- } /* while(...) */
+ } /* while (...) */
}
/**
@@ -164,7 +164,7 @@ void USB_CorrectTransferHp(void)
/* call OUT service function */
(*pEpInt_OUT[EPindex - 1])();
- } /* if((wEPVal & EP_CTRS_RX) */
+ } /* if ((wEPVal & EP_CTRS_RX) */
else if ((wEPVal & EP_CTRS_TX) != 0)
{
/* clear int flag */
@@ -173,7 +173,7 @@ void USB_CorrectTransferHp(void)
/* call IN service function */
(*pEpInt_IN[EPindex - 1])();
- } /* if((wEPVal & EP_CTRS_TX) != 0) */
+ } /* if ((wEPVal & EP_CTRS_TX) != 0) */
- } /* while(...) */
+ } /* while (...) */
}
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/arm_common_tables.h b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/arm_common_tables.h
new file mode 100644
index 0000000000..dfea7460e9
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/arm_common_tables.h
@@ -0,0 +1,121 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_common_tables.h
+ * Description: Extern declaration for common tables
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
+#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
+#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
+#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
+#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
+#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
+#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
+#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /* ARM_COMMON_TABLES_H */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/arm_const_structs.h b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/arm_const_structs.h
new file mode 100644
index 0000000000..80a3e8bbe7
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/arm_const_structs.h
@@ -0,0 +1,66 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_const_structs.h
+ * Description: Constant structs that are initialized for user convenience.
+ * For example, some can be given as arguments to the arm_cfft_f32() function.
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/arm_math.h b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/arm_math.h
new file mode 100644
index 0000000000..d6b5b2b1ce
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/arm_math.h
@@ -0,0 +1,7157 @@
+/******************************************************************************
+ * @file arm_math.h
+ * @brief Public header file for CMSIS DSP LibraryU
+ * @version V1.5.3
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ \mainpage CMSIS DSP Software Library
+ *
+ * Introduction
+ * ------------
+ *
+ * This user manual describes the CMSIS DSP software library,
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.
+ *
+ * The library is divided into a number of functions each covering a specific category:
+ * - Basic math functions
+ * - Fast math functions
+ * - Complex math functions
+ * - Filters
+ * - Matrix functions
+ * - Transforms
+ * - Motor control functions
+ * - Statistical functions
+ * - Support functions
+ * - Interpolation functions
+ *
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+ * 32-bit integer and 32-bit floating-point values.
+ *
+ * Using the Library
+ * ------------
+ *
+ * The library installer contains prebuilt versions of the libraries in the Lib folder.
+ * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)
+ * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)
+ * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)
+ * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)
+ * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)
+ * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)
+ * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)
+ * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)
+ * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)
+ * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)
+ * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)
+ * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)
+ * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)
+ * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)
+ * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian)
+ * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian)
+ * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit)
+ * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions)
+ * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
+ *
+ * The library functions are declared in the public file arm_math.h which is placed in the Include folder.
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+ * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+ * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or
+ * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+ * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
+ * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions.
+ *
+ *
+ * Examples
+ * --------
+ *
+ * The library ships with a number of examples which demonstrate how to use the library functions.
+ *
+ * Toolchain Support
+ * ------------
+ *
+ * The library has been developed and tested with MDK version 5.14.0.0
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+ *
+ * Building the Library
+ * ------------
+ *
+ * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP_Lib\\Source\\ARM folder.
+ * - arm_cortexM_math.uvprojx
+ *
+ *
+ * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above.
+ *
+ * Preprocessor Macros
+ * ------------
+ *
+ * Each library project have different preprocessor macros.
+ *
+ * - UNALIGNED_SUPPORT_DISABLE:
+ *
+ * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+ *
+ * - ARM_MATH_BIG_ENDIAN:
+ *
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+ *
+ * - ARM_MATH_MATRIX_CHECK:
+ *
+ * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+ *
+ * - ARM_MATH_ROUNDING:
+ *
+ * Define macro ARM_MATH_ROUNDING for rounding on support functions
+ *
+ * - ARM_MATH_CMx:
+ *
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+ * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+ * ARM_MATH_CM7 for building the library on cortex-M7.
+ *
+ * - ARM_MATH_ARMV8MxL:
+ *
+ * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library
+ * on Armv8-M Mainline target.
+ *
+ * - __FPU_PRESENT:
+ *
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries.
+ *
+ * - __DSP_PRESENT:
+ *
+ * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions.
+ *
+ *
+ * CMSIS-DSP in ARM::CMSIS Pack
+ * -----------------------------
+ *
+ * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories:
+ * |File/Folder |Content |
+ * |------------------------------|------------------------------------------------------------------------|
+ * |\b CMSIS\\Documentation\\DSP | This documentation |
+ * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) |
+ * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions |
+ * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library |
+ *
+ *
+ * Revision History of CMSIS-DSP
+ * ------------
+ * Please refer to \ref ChangeLog_pg.
+ *
+ * Copyright Notice
+ * ------------
+ *
+ * Copyright (C) 2010-2015 Arm Limited. All rights reserved.
+ */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures. For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ *
+ * typedef struct
+ * {
+ * uint16_t numRows; // number of rows of the matrix.
+ * uint16_t numCols; // number of columns of the matrix.
+ * float32_t *pData; // points to the data of the matrix.
+ * } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data. The array is of size numRows X numCols
+ * and the values are arranged in row order. That is, the
+ * matrix element (i, j) is stored at:
+ *
+ * pData[i*numCols + j]
+ *
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function arm_mat_init_f32(), arm_mat_init_q31()
+ * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure. For example:
+ *
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns
+ * specifies the number of columns, and pData points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices. For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns. If the size check fails the functions return:
+ *
+ * ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return
+ *
+ * ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ *
+ * ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined
+ * and size checking is enabled. By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster. With size checking disabled the functions always
+ * return ARM_MATH_SUCCESS.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+/* Compiler specific diagnostic adjustment */
+#if defined ( __CC_ARM )
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+#elif defined ( __ICCARM__ )
+
+#elif defined ( __TI_ARM__ )
+
+#elif defined ( __CSMC__ )
+
+#elif defined ( __TASKING__ )
+
+#else
+ #error Unknown compiler
+#endif
+
+
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+ #include "core_cm7.h"
+ #define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM4)
+ #include "core_cm4.h"
+ #define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM3)
+ #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+ #include "core_cm0.h"
+ #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+ #include "core_cm0plus.h"
+ #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MBL)
+ #include "core_armv8mbl.h"
+ #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MML)
+ #include "core_armv8mml.h"
+ #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1))
+ #define ARM_MATH_DSP
+ #endif
+#else
+ #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML"
+#endif
+
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+ /**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31 (0x100)
+#define DELTA_Q15 0x5
+#define INDEX_MASK 0x0000003F
+#ifndef PI
+ #define PI 3.14159265358979f
+#endif
+
+ /**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define FAST_MATH_TABLE_SIZE 512
+#define FAST_MATH_Q31_SHIFT (32 - 10)
+#define FAST_MATH_Q15_SHIFT (16 - 10)
+#define CONTROLLER_Q31_SHIFT (32 - 9)
+#define TABLE_SPACING_Q31 0x400000
+#define TABLE_SPACING_Q15 0x80
+
+ /**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+ /* 1.31(q31) Fixed value of 2/360 */
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING 0xB60B61
+
+ /**
+ * @brief Macro for Unaligned Support
+ */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+ #define ALIGN4
+#else
+ #if defined (__GNUC__)
+ #define ALIGN4 __attribute__((aligned(4)))
+ #else
+ #define ALIGN4 __align(4)
+ #endif
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /**
+ * @brief Error status returned by some functions in the library.
+ */
+
+ typedef enum
+ {
+ ARM_MATH_SUCCESS = 0, /**< No error */
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
+ } arm_status;
+
+ /**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+ typedef int8_t q7_t;
+
+ /**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+ typedef int16_t q15_t;
+
+ /**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+ typedef int32_t q31_t;
+
+ /**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+ typedef int64_t q63_t;
+
+ /**
+ * @brief 32-bit floating-point type definition.
+ */
+ typedef float float32_t;
+
+ /**
+ * @brief 64-bit floating-point type definition.
+ */
+ typedef double float64_t;
+
+ /**
+ * @brief definition to read/write two 16 bit values.
+ */
+#if defined ( __CC_ARM )
+ #define __SIMD32_TYPE int32_t __packed
+ #define CMSIS_UNUSED __attribute__((unused))
+ #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED __attribute__((unused))
+ #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __GNUC__ )
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED __attribute__((unused))
+ #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ICCARM__ )
+ #define __SIMD32_TYPE int32_t __packed
+ #define CMSIS_UNUSED
+ #define CMSIS_INLINE
+
+#elif defined ( __TI_ARM__ )
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED __attribute__((unused))
+ #define CMSIS_INLINE
+
+#elif defined ( __CSMC__ )
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED
+ #define CMSIS_INLINE
+
+#elif defined ( __TASKING__ )
+ #define __SIMD32_TYPE __unaligned int32_t
+ #define CMSIS_UNUSED
+ #define CMSIS_INLINE
+
+#else
+ #error Unknown compiler
+#endif
+
+#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))
+#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))
+#define __SIMD64(addr) (*(int64_t **) & (addr))
+
+#if !defined (ARM_MATH_DSP)
+ /**
+ * @brief definition to pack two 16 bit values.
+ */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
+
+#endif /* !defined (ARM_MATH_DSP) */
+
+ /**
+ * @brief definition to pack four 8 bit values.
+ */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
+
+#endif
+
+
+ /**
+ * @brief Clips Q63 to Q31 values.
+ */
+ CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+ }
+
+ /**
+ * @brief Clips Q63 to Q15 values.
+ */
+ CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+ }
+
+ /**
+ * @brief Clips Q31 to Q7 values.
+ */
+ CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+ }
+
+ /**
+ * @brief Clips Q31 to Q15 values.
+ */
+ CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+ }
+
+ /**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+
+ CMSIS_INLINE __STATIC_INLINE q63_t mult32x64(
+ q63_t x,
+ q31_t y)
+ {
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+ (((q63_t) (x >> 32) * y)));
+ }
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+ */
+
+ CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31(
+ q31_t in,
+ q31_t * dst,
+ q31_t * pRecipTable)
+ {
+ q31_t out;
+ uint32_t tempVal;
+ uint32_t index, i;
+ uint32_t signBits;
+
+ if (in > 0)
+ {
+ signBits = ((uint32_t) (__CLZ( in) - 1));
+ }
+ else
+ {
+ signBits = ((uint32_t) (__CLZ(-in) - 1));
+ }
+
+ /* Convert input sample to 1.31 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 24);
+ index = (index & INDEX_MASK);
+
+ /* 1.31 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0U; i < 2U; i++)
+ {
+ tempVal = (uint32_t) (((q63_t) in * out) >> 31);
+ tempVal = 0x7FFFFFFFu - tempVal;
+ /* 1.31 with exp 1 */
+ /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
+ out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1U);
+ }
+
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15(
+ q15_t in,
+ q15_t * dst,
+ q15_t * pRecipTable)
+ {
+ q15_t out = 0;
+ uint32_t tempVal = 0;
+ uint32_t index = 0, i = 0;
+ uint32_t signBits = 0;
+
+ if (in > 0)
+ {
+ signBits = ((uint32_t)(__CLZ( in) - 17));
+ }
+ else
+ {
+ signBits = ((uint32_t)(__CLZ(-in) - 17));
+ }
+
+ /* Convert input sample to 1.15 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 8);
+ index = (index & INDEX_MASK);
+
+ /* 1.15 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0U; i < 2U; i++)
+ {
+ tempVal = (uint32_t) (((q31_t) in * out) >> 15);
+ tempVal = 0x7FFFu - tempVal;
+ /* 1.15 with exp 1 */
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);
+ /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1);
+ }
+
+
+/*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+#if !defined (ARM_MATH_DSP)
+
+ /*
+ * @brief C custom defined QADD8 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB8 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */
+ q31_t r = 0, s = 0;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHADD16 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB16 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSUB16 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QASX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHASX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSAX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSAX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSDX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+ /*
+ * @brief C custom defined SMUADX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined QADD for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE int32_t __QADD(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE int32_t __QSUB(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined SMLAD for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLADX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLSDX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALD for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALDX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUAD for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSD for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SXTB16 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16(
+ uint32_t x)
+ {
+ return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
+ ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) ));
+ }
+
+ /*
+ * @brief C custom defined SMMLA for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA(
+ int32_t x,
+ int32_t y,
+ int32_t sum)
+ {
+ return (sum + (int32_t) (((int64_t) x * y) >> 32));
+ }
+
+#endif /* !defined (ARM_MATH_DSP) */
+
+
+ /**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q7;
+
+ /**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] S points to an instance of the Q7 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q7(
+ const arm_fir_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 FIR filter.
+ * @param[in,out] S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ */
+ void arm_fir_init_q7(
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] S points to an instance of the Q15 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR filter.
+ * @param[in,out] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+ * numTaps is not a supported value.
+ */
+ arm_status arm_fir_init_q15(
+ arm_fir_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] S points to an instance of the Q31 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR filter.
+ * @param[in,out] S points to an instance of the Q31 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_q31(
+ arm_fir_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] S points to an instance of the floating-point FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_f32(
+ const arm_fir_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_f32(
+ arm_fir_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q15;
+
+ /**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q31;
+
+ /**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_casd_df1_inst_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float32_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f32;
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float64_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f64;
+
+ /**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q15_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q31_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q31;
+
+
+ /**
+ * @brief Floating-point matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Q31, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+
+ /**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+
+ /**
+ * @brief Q31 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix scaling.
+ * @param[in] pSrc points to the input matrix
+ * @param[in] scale scale factor
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_q31(
+ arm_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t * pData);
+
+
+ /**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_q15(
+ arm_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t * pData);
+
+
+ /**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_f32(
+ arm_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t * pData);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+ typedef struct
+ {
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+#if !defined (ARM_MATH_DSP)
+ q15_t A1;
+ q15_t A2;
+#else
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+ q15_t state[3]; /**< The state array of length 3. */
+ q15_t Kp; /**< The proportional gain. */
+ q15_t Ki; /**< The integral gain. */
+ q15_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+ typedef struct
+ {
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ q31_t A2; /**< The derived gain, A2 = Kd . */
+ q31_t state[3]; /**< The state array of length 3. */
+ q31_t Kp; /**< The proportional gain. */
+ q31_t Ki; /**< The integral gain. */
+ q31_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+ typedef struct
+ {
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ float32_t A2; /**< The derived gain, A2 = Kd . */
+ float32_t state[3]; /**< The state array of length 3. */
+ float32_t Kp; /**< The proportional gain. */
+ float32_t Ki; /**< The integral gain. */
+ float32_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_f32;
+
+
+
+ /**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ */
+ void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S);
+
+
+ /**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ */
+
+ void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S);
+
+
+ /**
+ * @brief Initialization function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the q15 PID Control structure
+ */
+ void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S);
+
+
+ /**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+ typedef struct
+ {
+ uint32_t nValues; /**< nValues */
+ float32_t x1; /**< x1 */
+ float32_t xSpacing; /**< xSpacing */
+ float32_t *pYData; /**< pointer to the table of Y values */
+ } arm_linear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ float32_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q31_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q15_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q7_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q7;
+
+
+ /**
+ * @brief Q7 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q15(
+ arm_cfft_radix2_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q31(
+ arm_cfft_radix2_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q31(
+ const arm_cfft_radix2_instance_q31 * S,
+ q31_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+ void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc);
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_f32(
+ const arm_cfft_radix2_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q15_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_q15;
+
+void arm_cfft_q15(
+ const arm_cfft_instance_q15 * S,
+ q15_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_q31;
+
+void arm_cfft_q31(
+ const arm_cfft_instance_q31 * S,
+ q31_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_f32;
+
+ void arm_cfft_f32(
+ const arm_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q15;
+
+ arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst);
+
+ /**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q31;
+
+ arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint16_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_f32;
+
+ arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_f32(
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+typedef struct
+ {
+ arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
+ uint16_t fftLenRFFT; /**< length of the real sequence */
+ float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
+ } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+ arm_rfft_fast_instance_f32 * S,
+ uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+ arm_rfft_fast_instance_f32 * S,
+ float32_t * p, float32_t * pOut,
+ uint8_t ifftFlag);
+
+ /**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ float32_t normalize; /**< normalizing factor. */
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ float32_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.
+ */
+ arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize);
+
+
+ /**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q31_t normalize; /**< normalizing factor. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ q31_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q31;
+
+
+ /**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31 * S,
+ arm_rfft_instance_q31 * S_RFFT,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q31 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q15_t normalize; /**< normalizing factor. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ q15_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15 * S,
+ arm_rfft_instance_q15 * S_RFFT,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q15 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer);
+
+
+ /**
+ * @brief Floating-point vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_f32(
+ float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q7(
+ q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q15(
+ q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q31(
+ q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result);
+
+
+ /**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result);
+
+
+ /**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q7(
+ q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q15(
+ q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q31(
+ q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_f32(
+ float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q7(
+ q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q15(
+ q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q31(
+ q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point FIR decimator.
+ * @param[in] S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR decimator.
+ * @param[in,out] S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+ arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+ arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q31(
+ arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+ arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+ } arm_fir_interpolate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+ arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+ arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+ arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
+ } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+ /**
+ * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f64;
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f32(
+ const arm_biquad_cascade_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_stereo_df2T_f32(
+ const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f64(
+ const arm_biquad_cascade_df2T_instance_f64 * S,
+ float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_stereo_df2T_init_f32(
+ arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f64(
+ arm_biquad_cascade_df2T_instance_f64 * S,
+ uint8_t numStages,
+ float64_t * pCoeffs,
+ float64_t * pState);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pkCoeffs,
+ float32_t * pvCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pkCoeffs,
+ q31_t * pvCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ */
+ void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pkCoeffs,
+ q15_t * pvCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that controls filter coefficient updates. */
+ } arm_lms_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_init_f32(
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q15(
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q15(
+ const arm_lms_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q31(
+ const arm_lms_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q31(
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that control filter coefficient updates. */
+ float32_t energy; /**< saves previous frame energy. */
+ float32_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q31_t *recipTable; /**< points to the reciprocal initial value table. */
+ q31_t energy; /**< saves previous frame energy. */
+ q31_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< Number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q15_t *recipTable; /**< Points to the reciprocal initial value table. */
+ q15_t energy; /**< saves previous frame energy. */
+ q15_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q15;
+
+
+ /**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+ void arm_correlate_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+ void arm_correlate_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+ void arm_correlate_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+ void arm_correlate_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_correlate_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q7;
+
+
+ /**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cos output.
+ */
+ void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCosVal);
+
+
+ /**
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cosine output.
+ */
+ void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal);
+
+
+ /**
+ * @brief Floating-point complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * S points to an instance of the PID control data structure. in
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ *
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ * A0 = Kp + Ki + Kd
+ * A1 = (-Kp ) - (2 * Kd )
+ * A2 = Kd
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ */
+ CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32(
+ arm_pid_instance_f32 * S,
+ float32_t in)
+ {
+ float32_t out;
+
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
+ out = (S->A0 * in) +
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @brief Process function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+ CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31(
+ arm_pid_instance_q31 * S,
+ q31_t in)
+ {
+ q63_t acc;
+ q31_t out;
+
+ /* acc = A0 * x[n] */
+ acc = (q63_t) S->A0 * in;
+
+ /* acc += A1 * x[n-1] */
+ acc += (q63_t) S->A1 * S->state[0];
+
+ /* acc += A2 * x[n-2] */
+ acc += (q63_t) S->A2 * S->state[1];
+
+ /* convert output to 1.31 format to add y[n-1] */
+ out = (q31_t) (acc >> 31U);
+
+ /* out += y[n-1] */
+ out += S->state[2];
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+
+ /**
+ * @brief Process function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+ CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15(
+ arm_pid_instance_q15 * S,
+ q15_t in)
+ {
+ q63_t acc;
+ q15_t out;
+
+#if defined (ARM_MATH_DSP)
+ __SIMD32_TYPE *vstate;
+
+ /* Implementation of PID controller */
+
+ /* acc = A0 * x[n] */
+ acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ vstate = __SIMD32_CONST(S->state);
+ acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);
+#else
+ /* acc = A0 * x[n] */
+ acc = ((q31_t) S->A0) * in;
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc += (q31_t) S->A1 * S->state[0];
+ acc += (q31_t) S->A2 * S->state[1];
+#endif
+
+ /* acc += y[n-1] */
+ acc += (q31_t) S->state[2] << 15;
+
+ /* saturate the output */
+ out = (q15_t) (__SSAT((acc >> 15), 16));
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+ /**
+ * @} end of PID group
+ */
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f32(
+ const arm_matrix_instance_f32 * src,
+ arm_matrix_instance_f32 * dst);
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f64(
+ const arm_matrix_instance_f64 * src,
+ arm_matrix_instance_f64 * dst);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents
+ * in the two-phase orthogonal stator axis Ialpha and Ibeta.
+ * When Ialpha is superposed with Ia as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta
+ * can be calculated using only Ia and Ib.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where Ia and Ib are the instantaneous stator phases and
+ * pIalpha and pIbeta are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup clarke
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point Clarke transform
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32(
+ float32_t Ia,
+ float32_t Ib,
+ float32_t * pIalpha,
+ float32_t * pIbeta)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+ }
+
+
+ /**
+ * @brief Clarke transform for Q31 version
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31(
+ q31_t Ia,
+ q31_t Ib,
+ q31_t * pIalpha,
+ q31_t * pIbeta)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+ /* pIbeta is calculated by adding the intermediate products */
+ *pIbeta = __QADD(product1, product2);
+ }
+
+ /**
+ * @} end of clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q31(
+ q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where pIa and pIb are the instantaneous stator phases and
+ * Ialpha and Ibeta are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Clarke transform
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] pIa points to output three-phase coordinate a
+ * @param[out] pIb points to output three-phase coordinate b
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pIa,
+ float32_t * pIb)
+ {
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+ *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
+ }
+
+
+ /**
+ * @brief Inverse Clarke transform for Q31 version
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] pIa points to output three-phase coordinate a
+ * @param[out] pIb points to output three-phase coordinate b
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pIa,
+ q31_t * pIb)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+ /* pIb is calculated by subtracting the products */
+ *pIb = __QSUB(product2, product1);
+ }
+
+ /**
+ * @} end of inv_clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q15(
+ q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where Ialpha and Ibeta are the stator vector components,
+ * pId and pIq are rotor vector components and cosVal and sinVal are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Park transform
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_park_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pId,
+ float32_t * pIq,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+ *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+ }
+
+
+ /**
+ * @brief Park transform for Q31 version
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_park_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pId,
+ q31_t * pIq,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Ialpha * cosVal) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * sinVal) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Ialpha * sinVal) */
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * cosVal) */
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+ /* Calculate pId by adding the two intermediate products 1 and 2 */
+ *pId = __QADD(product1, product2);
+
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+ *pIq = __QSUB(product4, product3);
+ }
+
+ /**
+ * @} end of park group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q7_to_float(
+ q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where pIalpha and pIbeta are the stator vector components,
+ * Id and Iq are rotor vector components and cosVal and sinVal are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Park transform
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32(
+ float32_t Id,
+ float32_t Iq,
+ float32_t * pIalpha,
+ float32_t * pIbeta,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+ *pIalpha = Id * cosVal - Iq * sinVal;
+
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+ *pIbeta = Id * sinVal + Iq * cosVal;
+ }
+
+
+ /**
+ * @brief Inverse Park transform for Q31 version
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31(
+ q31_t Id,
+ q31_t Iq,
+ q31_t * pIalpha,
+ q31_t * pIbeta,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Id * cosVal) */
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * sinVal) */
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Id * sinVal) */
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * cosVal) */
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+ *pIalpha = __QSUB(product1, product2);
+
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+ *pIbeta = __QADD(product4, product3);
+ }
+
+ /**
+ * @} end of Inverse park group
+ */
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_float(
+ q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ *
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ * where x0, x1 are nearest values of input x
+ * y0, y1 are nearest values to output y
+ *
+ *
+ * \par
+ * This set of functions implements Linear interpolation process
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
+ * sample of data and each call to the function returns a single processed value.
+ * S points to an instance of the Linear Interpolate function data structure.
+ * x is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+ /**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+ CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32(
+ arm_linear_interp_instance_f32 * S,
+ float32_t x)
+ {
+ float32_t y;
+ float32_t x0, x1; /* Nearest input values */
+ float32_t y0, y1; /* Nearest output values */
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */
+ int32_t i; /* Index variable */
+ float32_t *pYData = S->pYData; /* pointer to output table */
+
+ /* Calculation of index */
+ i = (int32_t) ((x - S->x1) / xSpacing);
+
+ if (i < 0)
+ {
+ /* Iniatilize output for below specified range as least output value of table */
+ y = pYData[0];
+ }
+ else if ((uint32_t)i >= S->nValues)
+ {
+ /* Iniatilize output for above specified range as last output value of table */
+ y = pYData[S->nValues - 1];
+ }
+ else
+ {
+ /* Calculation of nearest input values */
+ x0 = S->x1 + i * xSpacing;
+ x1 = S->x1 + (i + 1) * xSpacing;
+
+ /* Read of nearest output values */
+ y0 = pYData[i];
+ y1 = pYData[i + 1];
+
+ /* Calculation of output */
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+ }
+
+ /* returns output value */
+ return (y);
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q31 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q31 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31(
+ q31_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q31_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (q31_t)0xFFF00000) >> 20);
+
+ if (index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if (index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* shift left by 11 to keep fract in 1.31 format */
+ fract = (x & 0x000FFFFF) << 11;
+
+ /* Read two nearest output values from the index in 1.31(q31) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+ /* Convert y to 1.31 format */
+ return (y << 1U);
+ }
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q15 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15(
+ q15_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q63_t y; /* output */
+ q15_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (int32_t)0xFFF00000) >> 20);
+
+ if (index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if (index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+ y = ((q63_t) y0 * (0xFFFFF - fract));
+
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+ y += ((q63_t) y1 * (fract));
+
+ /* convert y to 1.15 format */
+ return (q15_t) (y >> 20);
+ }
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q7 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+ CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7(
+ q7_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q7_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ uint32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ if (x < 0)
+ {
+ return (pYData[0]);
+ }
+ index = (x >> 20) & 0xfff;
+
+ if (index >= (nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index and are in 1.7(q7) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+ y = ((y0 * (0xFFFFF - fract)));
+
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+ y += (y1 * fract);
+
+ /* convert y to 1.7(q7) format */
+ return (q7_t) (y >> 20);
+ }
+ }
+
+ /**
+ * @} end of LinearInterpolate group
+ */
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+ float32_t arm_sin_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q31_t arm_sin_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q15_t arm_sin_q15(
+ q15_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+ float32_t arm_cos_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q31_t arm_cos_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q15_t arm_cos_q15(
+ q15_t x);
+
+
+ /**
+ * @ingroup groupFastMath
+ */
+
+
+ /**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ *
+ * x1 = x0 - f(x0)/f'(x0)
+ *
+ * where x1 is the current estimate,
+ * x0 is the previous estimate, and
+ * f'(x0) is the derivative of f() evaluated at x0.
+ * For the square root function, the algorithm reduces to:
+ *
+ * x0 = in/2 [initial guess]
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]
+ *
+ */
+
+
+ /**
+ * @addtogroup SQRT
+ * @{
+ */
+
+ /**
+ * @brief Floating-point square root function.
+ * @param[in] in input value.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+ CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32(
+ float32_t in,
+ float32_t * pOut)
+ {
+ if (in >= 0.0f)
+ {
+
+#if (__FPU_USED == 1) && defined ( __CC_ARM )
+ *pOut = __sqrtf(in);
+#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+ *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined(__GNUC__)
+ *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
+ __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
+#else
+ *pOut = sqrtf(in);
+#endif
+
+ return (ARM_MATH_SUCCESS);
+ }
+ else
+ {
+ *pOut = 0.0f;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+ }
+
+
+ /**
+ * @brief Q31 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q31(
+ q31_t in,
+ q31_t * pOut);
+
+
+ /**
+ * @brief Q15 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q15(
+ q15_t in,
+ q15_t * pOut);
+
+ /**
+ * @} end of SQRT group
+ */
+
+
+ /**
+ * @brief floating-point Circular write function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const int32_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+
+ /**
+ * @brief floating-point Circular Read function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ int32_t * dst,
+ int32_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == (int32_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular write function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q15_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular Read function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q15_t * dst,
+ q15_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == (q15_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular write function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q7_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular Read function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q7_t * dst,
+ q7_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == (q7_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Floating-point complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult);
+
+
+ /**
+ * @brief Q31 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult);
+
+
+ /**
+ * @brief Floating-point complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult);
+
+
+ /**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q15(
+ q15_t * pSrcCmplx,
+ q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q31(
+ q31_t * pSrcCmplx,
+ q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_f32(
+ float32_t * pSrcCmplx,
+ float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] result is output pointer
+ * @param[in] index is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * result,
+ uint32_t * index);
+
+
+ /**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[in] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q31(
+ float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q15(
+ float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q7(
+ float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q15(
+ q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q7(
+ q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_float(
+ q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q31(
+ q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q7(
+ q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function f(x, y) is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * Algorithm
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ *
+ * typedef struct
+ * {
+ * uint16_t numRows;
+ * uint16_t numCols;
+ * float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ *
+ *
+ * \par
+ * where numRows specifies the number of rows in the table;
+ * numCols specifies the number of columns in the table;
+ * and pData points to an array of size numRows*numCols values.
+ * The data table pTable is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers.
+ *
+ * \par
+ * Let (x, y) specify the desired interpolation point. Then define:
+ *
+ * XF = floor(x)
+ * YF = floor(y)
+ *
+ * \par
+ * The interpolated output point is computed as:
+ *
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ *
+ * Note that the coordinates (x, y) contain integer and fractional components.
+ * The integer components specify which portion of the table to use while the
+ * fractional components control the interpolation processor.
+ *
+ * \par
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+ */
+
+ /**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+
+ /**
+ *
+ * @brief Floating-point bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate.
+ * @param[in] Y interpolation coordinate.
+ * @return out interpolated value.
+ */
+ CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32(
+ const arm_bilinear_interp_instance_f32 * S,
+ float32_t X,
+ float32_t Y)
+ {
+ float32_t out;
+ float32_t f00, f01, f10, f11;
+ float32_t *pData = S->pData;
+ int32_t xIndex, yIndex, index;
+ float32_t xdiff, ydiff;
+ float32_t b1, b2, b3, b4;
+
+ xIndex = (int32_t) X;
+ yIndex = (int32_t) Y;
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* Calculation of index for two nearest points in X-direction */
+ index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+ /* Read two nearest points in X-direction */
+ f00 = pData[index];
+ f01 = pData[index + 1];
+
+ /* Calculation of index for two nearest points in Y-direction */
+ index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+ /* Read two nearest points in Y-direction */
+ f10 = pData[index];
+ f11 = pData[index + 1];
+
+ /* Calculation of intermediate values */
+ b1 = f00;
+ b2 = f01 - f00;
+ b3 = f10 - f00;
+ b4 = f00 - f01 - f10 + f11;
+
+ /* Calculation of fractional part in X */
+ xdiff = X - xIndex;
+
+ /* Calculation of fractional part in Y */
+ ydiff = Y - yIndex;
+
+ /* Calculation of bi-linear interpolated output */
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+ /* return to application */
+ return (out);
+ }
+
+
+ /**
+ *
+ * @brief Q31 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31(
+ arm_bilinear_interp_instance_q31 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q31_t out; /* Temporary output */
+ q31_t acc = 0; /* output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q31_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q31_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* shift left xfract by 11 to keep 1.31 format */
+ xfract = (X & 0x000FFFFF) << 11U;
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + (int32_t)nCols * (cI) ];
+ x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* shift left yfract by 11 to keep 1.31 format */
+ yfract = (Y & 0x000FFFFF) << 11U;
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ];
+ y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* Convert acc to 1.31(q31) format */
+ return ((q31_t)(acc << 2));
+ }
+
+
+ /**
+ * @brief Q15 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15(
+ arm_bilinear_interp_instance_q15 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q15_t x1, x2, y1, y2; /* Nearest output values */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ int32_t rI, cI; /* Row and column indices */
+ q15_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U);
+ acc = ((q63_t) out * (0xFFFFF - yfract));
+
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U);
+ acc += ((q63_t) out * (xfract));
+
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U);
+ acc += ((q63_t) out * (yfract));
+
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U);
+ acc += ((q63_t) out * (yfract));
+
+ /* acc is in 13.51 format and down shift acc by 36 times */
+ /* Convert out to 1.15 format */
+ return ((q15_t)(acc >> 36));
+ }
+
+
+ /**
+ * @brief Q7 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7(
+ arm_bilinear_interp_instance_q7 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q7_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q7_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+ out = ((x1 * (0xFFFFF - xfract)));
+ acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
+ out = ((x2 * (0xFFFFF - yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y1 * (0xFFFFF - xfract)));
+ acc += (((q63_t) out * (yfract)));
+
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y2 * (yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+ return ((q7_t)(acc >> 40));
+ }
+
+ /**
+ * @} end of BilinearInterpolate group
+ */
+
+
+/* SMMLAR */
+#define multAcc_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMLSR */
+#define multSub_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMULR */
+#define mult_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+/* SMMLA */
+#define multAcc_32x32_keep32(a, x, y) \
+ a += (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMLS */
+#define multSub_32x32_keep32(a, x, y) \
+ a -= (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMUL */
+#define mult_32x32_keep32(a, x, y) \
+ a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM )
+ /* Enter low optimization region - place directly above function definition */
+ #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("push") \
+ _Pragma ("O1")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+ #define LOW_OPTIMIZATION_EXIT \
+ _Pragma ("pop")
+ #else
+ #define LOW_OPTIMIZATION_EXIT
+ #endif
+
+ /* Enter low optimization region - place directly above function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __GNUC__ )
+ #define LOW_OPTIMIZATION_ENTER \
+ __attribute__(( optimize("-O1") ))
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __ICCARM__ )
+ /* Enter low optimization region - place directly above function definition */
+ #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define LOW_OPTIMIZATION_EXIT
+
+ /* Enter low optimization region - place directly above function definition */
+ #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TI_ARM__ )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __CSMC__ )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TASKING__ )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/* Compiler specific diagnostic adjustment */
+#if defined ( __CC_ARM )
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+
+#elif defined ( __ICCARM__ )
+
+#elif defined ( __TI_ARM__ )
+
+#elif defined ( __CSMC__ )
+
+#elif defined ( __TASKING__ )
+
+#else
+ #error Unknown compiler
+#endif
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_armcc.h b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_armcc.h
new file mode 100644
index 0000000000..a4c67e0268
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_armcc.h
@@ -0,0 +1,865 @@
+/**************************************************************************//**
+ * @file cmsis_armcc.h
+ * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+ #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
+ (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
+ #define __ARM_ARCH_6M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
+ #define __ARM_ARCH_7M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+ #define __ARM_ARCH_7EM__ 1
+#endif
+
+ /* __ARM_ARCH_8M_BASE__ not applicable */
+ /* __ARM_ARCH_8M_MAIN__ not applicable */
+
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE static __forceinline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __declspec(noreturn)
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT __packed struct
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION __packed union
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); */
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() do {\
+ __schedule_barrier();\
+ __isb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+ __schedule_barrier();\
+ __dsb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+ __schedule_barrier();\
+ __dmb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+ #define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+ return result;
+}
+#endif
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+#else
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+#else
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+#else
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXB(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXH(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXW(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32U) ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_armclang.h b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_armclang.h
new file mode 100644
index 0000000000..a1722f87a8
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_armclang.h
@@ -0,0 +1,1869 @@
+/**************************************************************************//**
+ * @file cmsis_armclang.h
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR() ((uint32_t)0U)
+#endif
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __set_FPSCR __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x) ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF);
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF);
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF);
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV(value) __builtin_bswap32(value)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __builtin_arm_rbit
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_compiler.h b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_compiler.h
new file mode 100644
index 0000000000..adfd3c2504
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_compiler.h
@@ -0,0 +1,266 @@
+/**************************************************************************//**
+ * @file cmsis_compiler.h
+ * @brief CMSIS compiler generic header file
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include
+
+/*
+ * Arm Compiler 4/5
+ */
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+ #include
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+ #include
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed))
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed))
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __packed__
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __packed__
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __packed__
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __packed__ T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __align(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+ #include
+
+ #ifndef __ASM
+ #define __ASM _asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ // NO RETURN is automatically detected hence no warning here
+ #define __NO_RETURN
+ #endif
+ #ifndef __USED
+ #warning No compiler specific solution for __USED. __USED is ignored.
+ #define __USED
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __weak
+ #endif
+ #ifndef __PACKED
+ #define __PACKED @packed
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT @packed struct
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION @packed union
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ @packed struct T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+
+#else
+ #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_gcc.h b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_gcc.h
new file mode 100644
index 0000000000..cd374afaef
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_gcc.h
@@ -0,0 +1,2085 @@
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS compiler GCC header file
+ * @version V5.0.4
+ * @date 09. April 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+ #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_get_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ return __builtin_arm_get_fpscr();
+#else
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#endif
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ __builtin_arm_set_fpscr(fpscr);
+#else
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP() __ASM volatile ("nop")
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI() __ASM volatile ("wfi")
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE() __ASM volatile ("wfe")
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV() __ASM volatile ("sev")
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (int16_t)__builtin_bswap16(value);
+#else
+ int16_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return result;
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ __extension__ \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_iccarm.h b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_iccarm.h
new file mode 100644
index 0000000000..931db1d514
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_iccarm.h
@@ -0,0 +1,935 @@
+/**************************************************************************//**
+ * @file cmsis_iccarm.h
+ * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version V5.0.7
+ * @date 19. June 2018
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2018 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+ #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+ #define __ICCARM_V8 1
+#else
+ #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+ #if __ICCARM_V8
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #elif (__VER__ >= 7080000)
+ /* Needs IAR language extensions */
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #else
+ #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+ #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+ #if __ARM_ARCH == 6
+ #define __ARM_ARCH_6M__ 1
+ #elif __ARM_ARCH == 7
+ #if __ARM_FEATURE_DSP
+ #define __ARM_ARCH_7EM__ 1
+ #else
+ #define __ARM_ARCH_7M__ 1
+ #endif
+ #endif /* __ARM_ARCH */
+ #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+ !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+ #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+ #define __ARM_ARCH_6M__ 1
+ #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+ #define __ARM_ARCH_7M__ 1
+ #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+ #define __ARM_ARCH_7EM__ 1
+ #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #else
+ #error "Unknown target."
+ #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+ #define __IAR_M0_FAMILY 1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+ #define __IAR_M0_FAMILY 1
+#else
+ #define __IAR_M0_FAMILY 0
+#endif
+
+
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+
+#ifndef __NO_RETURN
+ #if __ICCARM_V8
+ #define __NO_RETURN __attribute__((__noreturn__))
+ #else
+ #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+ #endif
+#endif
+
+#ifndef __PACKED
+ #if __ICCARM_V8
+ #define __PACKED __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED __packed
+ #endif
+#endif
+
+#ifndef __PACKED_STRUCT
+ #if __ICCARM_V8
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_STRUCT __packed struct
+ #endif
+#endif
+
+#ifndef __PACKED_UNION
+ #if __ICCARM_V8
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_UNION __packed union
+ #endif
+#endif
+
+#ifndef __RESTRICT
+ #define __RESTRICT restrict
+#endif
+
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+
+#ifndef __FORCEINLINE
+ #define __FORCEINLINE _Pragma("inline=forced")
+#endif
+
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+ return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+ *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+ return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+ *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef __USED
+ #if __ICCARM_V8
+ #define __USED __attribute__((used))
+ #else
+ #define __USED _Pragma("__root")
+ #endif
+#endif
+
+#ifndef __WEAK
+ #if __ICCARM_V8
+ #define __WEAK __attribute__((weak))
+ #else
+ #define __WEAK _Pragma("__weak")
+ #endif
+#endif
+
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+ #define __ICCARM_INTRINSICS_VERSION__ 0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+ #if defined(__CLZ)
+ #undef __CLZ
+ #endif
+ #if defined(__REVSH)
+ #undef __REVSH
+ #endif
+ #if defined(__RBIT)
+ #undef __RBIT
+ #endif
+ #if defined(__SSAT)
+ #undef __SSAT
+ #endif
+ #if defined(__USAT)
+ #undef __USAT
+ #endif
+
+ #include "iccarm_builtin.h"
+
+ #define __disable_fault_irq __iar_builtin_disable_fiq
+ #define __disable_irq __iar_builtin_disable_interrupt
+ #define __enable_fault_irq __iar_builtin_enable_fiq
+ #define __enable_irq __iar_builtin_enable_interrupt
+ #define __arm_rsr __iar_builtin_rsr
+ #define __arm_wsr __iar_builtin_wsr
+
+
+ #define __get_APSR() (__arm_rsr("APSR"))
+ #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
+ #define __get_CONTROL() (__arm_rsr("CONTROL"))
+ #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
+
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ #define __get_FPSCR() (__arm_rsr("FPSCR"))
+ #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
+ #else
+ #define __get_FPSCR() ( 0 )
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #define __get_IPSR() (__arm_rsr("IPSR"))
+ #define __get_MSP() (__arm_rsr("MSP"))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __get_MSPLIM() (0U)
+ #else
+ #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
+ #endif
+ #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
+ #define __get_PSP() (__arm_rsr("PSP"))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __get_PSPLIM() (0U)
+ #else
+ #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
+ #endif
+
+ #define __get_xPSR() (__arm_rsr("xPSR"))
+
+ #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
+ #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
+ #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
+ #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
+ #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __set_MSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
+ #endif
+ #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
+ #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __set_PSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
+ #endif
+
+ #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
+ #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
+ #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
+ #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
+ #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
+ #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
+ #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
+ #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
+ #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
+ #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
+ #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
+ #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
+ #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
+ #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __TZ_get_PSPLIM_NS() (0U)
+ #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+ #else
+ #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
+ #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+ #endif
+
+ #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
+ #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+ #define __NOP __iar_builtin_no_operation
+
+ #define __CLZ __iar_builtin_CLZ
+ #define __CLREX __iar_builtin_CLREX
+
+ #define __DMB __iar_builtin_DMB
+ #define __DSB __iar_builtin_DSB
+ #define __ISB __iar_builtin_ISB
+
+ #define __LDREXB __iar_builtin_LDREXB
+ #define __LDREXH __iar_builtin_LDREXH
+ #define __LDREXW __iar_builtin_LDREX
+
+ #define __RBIT __iar_builtin_RBIT
+ #define __REV __iar_builtin_REV
+ #define __REV16 __iar_builtin_REV16
+
+ __IAR_FT int16_t __REVSH(int16_t val)
+ {
+ return (int16_t) __iar_builtin_REVSH(val);
+ }
+
+ #define __ROR __iar_builtin_ROR
+ #define __RRX __iar_builtin_RRX
+
+ #define __SEV __iar_builtin_SEV
+
+ #if !__IAR_M0_FAMILY
+ #define __SSAT __iar_builtin_SSAT
+ #endif
+
+ #define __STREXB __iar_builtin_STREXB
+ #define __STREXH __iar_builtin_STREXH
+ #define __STREXW __iar_builtin_STREX
+
+ #if !__IAR_M0_FAMILY
+ #define __USAT __iar_builtin_USAT
+ #endif
+
+ #define __WFE __iar_builtin_WFE
+ #define __WFI __iar_builtin_WFI
+
+ #if __ARM_MEDIA__
+ #define __SADD8 __iar_builtin_SADD8
+ #define __QADD8 __iar_builtin_QADD8
+ #define __SHADD8 __iar_builtin_SHADD8
+ #define __UADD8 __iar_builtin_UADD8
+ #define __UQADD8 __iar_builtin_UQADD8
+ #define __UHADD8 __iar_builtin_UHADD8
+ #define __SSUB8 __iar_builtin_SSUB8
+ #define __QSUB8 __iar_builtin_QSUB8
+ #define __SHSUB8 __iar_builtin_SHSUB8
+ #define __USUB8 __iar_builtin_USUB8
+ #define __UQSUB8 __iar_builtin_UQSUB8
+ #define __UHSUB8 __iar_builtin_UHSUB8
+ #define __SADD16 __iar_builtin_SADD16
+ #define __QADD16 __iar_builtin_QADD16
+ #define __SHADD16 __iar_builtin_SHADD16
+ #define __UADD16 __iar_builtin_UADD16
+ #define __UQADD16 __iar_builtin_UQADD16
+ #define __UHADD16 __iar_builtin_UHADD16
+ #define __SSUB16 __iar_builtin_SSUB16
+ #define __QSUB16 __iar_builtin_QSUB16
+ #define __SHSUB16 __iar_builtin_SHSUB16
+ #define __USUB16 __iar_builtin_USUB16
+ #define __UQSUB16 __iar_builtin_UQSUB16
+ #define __UHSUB16 __iar_builtin_UHSUB16
+ #define __SASX __iar_builtin_SASX
+ #define __QASX __iar_builtin_QASX
+ #define __SHASX __iar_builtin_SHASX
+ #define __UASX __iar_builtin_UASX
+ #define __UQASX __iar_builtin_UQASX
+ #define __UHASX __iar_builtin_UHASX
+ #define __SSAX __iar_builtin_SSAX
+ #define __QSAX __iar_builtin_QSAX
+ #define __SHSAX __iar_builtin_SHSAX
+ #define __USAX __iar_builtin_USAX
+ #define __UQSAX __iar_builtin_UQSAX
+ #define __UHSAX __iar_builtin_UHSAX
+ #define __USAD8 __iar_builtin_USAD8
+ #define __USADA8 __iar_builtin_USADA8
+ #define __SSAT16 __iar_builtin_SSAT16
+ #define __USAT16 __iar_builtin_USAT16
+ #define __UXTB16 __iar_builtin_UXTB16
+ #define __UXTAB16 __iar_builtin_UXTAB16
+ #define __SXTB16 __iar_builtin_SXTB16
+ #define __SXTAB16 __iar_builtin_SXTAB16
+ #define __SMUAD __iar_builtin_SMUAD
+ #define __SMUADX __iar_builtin_SMUADX
+ #define __SMMLA __iar_builtin_SMMLA
+ #define __SMLAD __iar_builtin_SMLAD
+ #define __SMLADX __iar_builtin_SMLADX
+ #define __SMLALD __iar_builtin_SMLALD
+ #define __SMLALDX __iar_builtin_SMLALDX
+ #define __SMUSD __iar_builtin_SMUSD
+ #define __SMUSDX __iar_builtin_SMUSDX
+ #define __SMLSD __iar_builtin_SMLSD
+ #define __SMLSDX __iar_builtin_SMLSDX
+ #define __SMLSLD __iar_builtin_SMLSLD
+ #define __SMLSLDX __iar_builtin_SMLSLDX
+ #define __SEL __iar_builtin_SEL
+ #define __QADD __iar_builtin_QADD
+ #define __QSUB __iar_builtin_QSUB
+ #define __PKHBT __iar_builtin_PKHBT
+ #define __PKHTB __iar_builtin_PKHTB
+ #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #define __CLZ __cmsis_iar_clz_not_active
+ #define __SSAT __cmsis_iar_ssat_not_active
+ #define __USAT __cmsis_iar_usat_not_active
+ #define __RBIT __cmsis_iar_rbit_not_active
+ #define __get_APSR __cmsis_iar_get_APSR_not_active
+ #endif
+
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+ #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+ #endif
+
+ #ifdef __INTRINSICS_INCLUDED
+ #error intrinsics.h is already included previously!
+ #endif
+
+ #include
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #undef __CLZ
+ #undef __SSAT
+ #undef __USAT
+ #undef __RBIT
+ #undef __get_APSR
+
+ __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+ {
+ if (data == 0U) { return 32U; }
+
+ uint32_t count = 0U;
+ uint32_t mask = 0x80000000U;
+
+ while ((data & mask) == 0U)
+ {
+ count += 1U;
+ mask = mask >> 1U;
+ }
+ return count;
+ }
+
+ __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+ {
+ uint8_t sc = 31U;
+ uint32_t r = v;
+ for (v >>= 1U; v; v >>= 1U)
+ {
+ r <<= 1U;
+ r |= v & 1U;
+ sc--;
+ }
+ return (r << sc);
+ }
+
+ __STATIC_INLINE uint32_t __get_APSR(void)
+ {
+ uint32_t res;
+ __asm("MRS %0,APSR" : "=r" (res));
+ return res;
+ }
+
+ #endif
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #undef __get_FPSCR
+ #undef __set_FPSCR
+ #define __get_FPSCR() (0)
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #pragma diag_suppress=Pe940
+ #pragma diag_suppress=Pe177
+
+ #define __enable_irq __enable_interrupt
+ #define __disable_irq __disable_interrupt
+ #define __NOP __no_operation
+
+ #define __get_xPSR __get_PSR
+
+ #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+ __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+ {
+ return __LDREX((unsigned long *)ptr);
+ }
+
+ __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+ {
+ return __STREX(value, (unsigned long *)ptr);
+ }
+ #endif
+
+
+ /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+ #if (__CORTEX_M >= 0x03)
+
+ __IAR_FT uint32_t __RRX(uint32_t value)
+ {
+ uint32_t result;
+ __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
+ return(result);
+ }
+
+ __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
+ }
+
+
+ #define __enable_fault_irq __enable_fiq
+ #define __disable_fault_irq __disable_fiq
+
+
+ #endif /* (__CORTEX_M >= 0x03) */
+
+ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+ {
+ return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+ }
+
+ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+ __IAR_FT uint32_t __get_MSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,MSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_MSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR MSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __get_PSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_PSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
+ {
+ __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR PSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_SP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,SP_NS" : "=r" (res));
+ return res;
+ }
+ __IAR_FT void __TZ_set_SP_NS(uint32_t value)
+ {
+ __asm volatile("MSR SP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
+ }
+
+ #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+ __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+ {
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+ }
+
+ __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+ {
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+ }
+#endif
+
+#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+ __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+ {
+ __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+ {
+ __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+ {
+ __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+ }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+
+ __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+ {
+ __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+ {
+ __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+ {
+ __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_version.h b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_version.h
new file mode 100644
index 0000000000..660f612aa3
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_version.h
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file cmsis_version.h
+ * @brief CMSIS Core(M) Version definitions
+ * @version V5.0.2
+ * @date 19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/* CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
+#endif
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/core_cm4.h b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/core_cm4.h
new file mode 100644
index 0000000000..7d56873532
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/core_cm4.h
@@ -0,0 +1,2129 @@
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V5.0.8
+ * @date 04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M4
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (4U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000U
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/mpu_armv7.h b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/mpu_armv7.h
new file mode 100644
index 0000000000..be73de161f
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/mpu_armv7.h
@@ -0,0 +1,270 @@
+/******************************************************************************
+ * @file mpu_armv7.h
+ * @brief CMSIS MPU API for Armv7-M MPU
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+ (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
+ ((Region) & MPU_RBAR_REGION_Msk) | \
+ (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+*
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
+ ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
+ (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
+ (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
+ (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
+ ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
+ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
+ (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+ ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+* - TEX: 000b
+* - Shareable
+* - Non-cacheable
+* - Non-bufferable
+*/
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+* - TEX: 000b (if non-shareable) or 010b (if shareable)
+* - Shareable or non-shareable
+* - Non-cacheable
+* - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+* - TEX: 1BBb (reflecting outer cacheability rules)
+* - Shareable or non-shareable
+* - Cacheable or non-cacheable (reflecting inner cacheability rules)
+* - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+ uint32_t RBAR; //!< The region base address register value (RBAR)
+ uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+ __DSB();
+ __ISB();
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+ __DSB();
+ __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+ MPU->RNR = rnr;
+ MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+ MPU->RNR = rnr;
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+ uint32_t i;
+ for (i = 0U; i < len; ++i)
+ {
+ dst[i] = src[i];
+ }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+ while (cnt > MPU_TYPE_RALIASES) {
+ orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+ table += MPU_TYPE_RALIASES;
+ cnt -= MPU_TYPE_RALIASES;
+ }
+ orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/n32l40x.h b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/n32l40x.h
new file mode 100644
index 0000000000..27ce0237e4
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/n32l40x.h
@@ -0,0 +1,7921 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L40X_H__
+#define __N32L40X_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup n32l40x_Library_Basic
+ * @{
+ */
+
+#if !defined USE_STDPERIPH_DRIVER
+/*
+ * Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+#define USE_STDPERIPH_DRIVER
+#endif
+
+/*
+ * In the following line adjust the value of External High Speed oscillator (HSE)
+ used in your application
+
+ Tip: To avoid modifying this file each time you need to use different HSE, you
+ can define the HSE value in your toolchain compiler preprocessor.
+ */
+#if !defined HSE_VALUE
+#define HSE_VALUE (8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+/*
+ * In the following line adjust the External High Speed oscillator (HSE) Startup
+ Timeout value
+ */
+#define HSE_STARTUP_TIMEOUT ((uint16_t)0x2000) /*!< Time out for HSE start up */
+#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */
+#define MSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for MSI start up */
+
+#define MSI_VALUE_L0 (100000) /*!< L0 Value of the Multi oscillator in Hz*/
+#define MSI_VALUE_L1 (200000) /*!< L1 Value of the Multi oscillator in Hz*/
+#define MSI_VALUE_L2 (400000) /*!< L2 Value of the Multi oscillator in Hz*/
+#define MSI_VALUE_L3 (800000) /*!< L3 Value of the Multi oscillator in Hz*/
+#define MSI_VALUE_L4 (1000000) /*!< L4 Value of the Multi oscillator in Hz*/
+#define MSI_VALUE_L5 (2000000) /*!< L5 Value of the Multi oscillator in Hz*/
+#define MSI_VALUE_L6 (4000000) /*!< L6 Value of the Multi oscillator in Hz*/
+
+#define HSI_VALUE (16000000) /*!< Value of the Internal oscillator in Hz*/
+
+#define __N32L40X_STDPERIPH_VERSION_MAIN (0x00) /*!< [31:24] main version */
+#define __N32L40X_STDPERIPH_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */
+#define __N32L40X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __N32L40X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
+
+/**
+ * @brief n32l40x Standard Peripheral Library version number
+ */
+#define __N32L40X_STDPERIPH_VERSION \
+ ((__N32L40X_STDPERIPH_VERSION_MAIN << 24) | (__N32L40X_STDPERIPH_VERSION_SUB1 << 16) \
+ | (__N32L40X_STDPERIPH_VERSION_SUB2 << 8) | (__N32L40X_STDPERIPH_VERSION_RC))
+
+/*
+ * Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#ifdef N32L40X
+#define __MPU_PRESENT 1 /*!< n32l40x devices does not provide an MPU */
+#define __FPU_PRESENT 1 /*!< FPU present */
+#endif /* n32l40x */
+#define __NVIC_PRIO_BITS 4 /*!< n32l40x uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @brief n32l40x Interrupt Number Definition
+ */
+typedef enum IRQn
+{
+ /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+
+ /****** n32l40x specific Interrupt Numbers ********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_IRQn = 2, /*!< RTC Tamper interrupt or Timestamp through EXTI line 19 */
+ RTC_IRQn = 3, /*!< RTC wakeup timer through EXTI line 20 */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA_Channel1_IRQn = 11, /*!< DMA Channel 1 global Interrupt */
+ DMA_Channel2_IRQn = 12, /*!< DMA Channel 2 global Interrupt */
+ DMA_Channel3_IRQn = 13, /*!< DMA Channel 3 global Interrupt */
+ DMA_Channel4_IRQn = 14, /*!< DMA Channel 4 global Interrupt */
+ DMA_Channel5_IRQn = 15, /*!< DMA Channel 5 global Interrupt */
+ DMA_Channel6_IRQn = 16, /*!< DMA Channel 6 global Interrupt */
+ DMA_Channel7_IRQn = 17, /*!< DMA Channel 7 global Interrupt */
+ DMA_Channel8_IRQn = 18, /*!< DMA Channel 8 global Interrupt */
+ ADC_IRQn = 19, /*!< ADC global Interrupt */
+ USB_HP_IRQn = 20, /*!< USB Device High Priority Interrupts */
+ USB_LP_IRQn = 21, /*!< USB Device Low Priority Interrupts */
+ COMP_1_2_IRQn = 22, /*!< COMP1 & COMP2 global Interrupt through EXTI line 21/22 */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+ TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
+ TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
+ TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ UART4_IRQn = 47, /*!< UART4 global Interrupt */
+ UART5_IRQn = 48, /*!< UART5 global Interrupt */
+ LPUART_IRQn = 49, /*!< LPUART global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ TIM6_IRQn = 51, /*!< TIM6 global Interrupt */
+ TIM7_IRQn = 52, /*!< TIM7 global Interrupt */
+ CAN_TX_IRQn = 53, /*!< CAN TX Interrupt */
+ CAN_RX0_IRQn = 54, /*!< CAN RX0 Interrupt */
+ CAN_RX1_IRQn = 55, /*!< CAN RX1 Interrupt */
+ CAN_SCE_IRQn = 56, /*!< CAN SCE Interrupt */
+ LPUART_WKUP_IRQn = 57, /*!< LPUART wakeup interrupt through EXTI line 23 */
+ LPTIM_WKUP_IRQn = 58, /*!< LPTIMER wakeup interrupt through EXTI line 24 */
+ LCD_IRQn = 59, /*!< LCD global interrupt through EXTI line 26 */
+ SAC_IRQn = 60, /*!< SAC global Interrupt */
+ MMU_IRQn = 61, /*!< MMU global Interrupt */
+ TSC_IRQn = 62, /*!< TSC global Interrupt */
+ RAMC_PERR_IRQn = 63, /*!< RAM parity error interrupt */
+ TIM9_IRQn = 64, /*!< TIM9 global interrupt */
+ UCDR_IRQn = 65, /*!< UCDR error interrupt */
+
+} IRQn_Type;
+
+#include "core_cm4.h"
+#include "system_n32l40x.h"
+#include
+#include
+
+typedef int32_t s32;
+typedef int16_t s16;
+typedef int8_t s8;
+
+typedef const int32_t sc32; /*!< Read Only */
+typedef const int16_t sc16; /*!< Read Only */
+typedef const int8_t sc8; /*!< Read Only */
+
+typedef __IO int32_t vs32;
+typedef __IO int16_t vs16;
+typedef __IO int8_t vs8;
+
+typedef __I int32_t vsc32; /*!< Read Only */
+typedef __I int16_t vsc16; /*!< Read Only */
+typedef __I int8_t vsc8; /*!< Read Only */
+
+typedef uint32_t u32;
+typedef uint16_t u16;
+typedef uint8_t u8;
+
+typedef const uint32_t uc32; /*!< Read Only */
+typedef const uint16_t uc16; /*!< Read Only */
+typedef const uint8_t uc8; /*!< Read Only */
+
+typedef __IO uint32_t vu32;
+typedef __IO uint16_t vu16;
+typedef __IO uint8_t vu8;
+
+typedef __I uint32_t vuc32; /*!< Read Only */
+typedef __I uint16_t vuc16; /*!< Read Only */
+typedef __I uint8_t vuc8; /*!< Read Only */
+typedef enum
+{
+ RESET = 0,
+ SET = !RESET
+} FlagStatus,
+ INTStatus;
+
+typedef enum
+{
+ DISABLE = 0,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/* n32l40x Standard Peripheral Library old definitions (maintained for legacy purpose) */
+#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT
+#define HSE_Value HSE_VALUE
+#define HSI_Value HSI_VALUE
+
+/**
+ * @brief Analog to Digital Converter
+ */
+typedef struct
+{
+ __IO uint32_t STS;
+ __IO uint32_t CTRL1;
+ __IO uint32_t CTRL2;
+ __IO uint32_t SAMPT1;
+ __IO uint32_t SAMPT2;
+ __IO uint32_t JOFFSET1;
+ __IO uint32_t JOFFSET2;
+ __IO uint32_t JOFFSET3;
+ __IO uint32_t JOFFSET4;
+ __IO uint32_t WDGHIGH;
+ __IO uint32_t WDGLOW;
+ __IO uint32_t RSEQ1;
+ __IO uint32_t RSEQ2;
+ __IO uint32_t RSEQ3;
+ __IO uint32_t JSEQ;
+ __IO uint32_t JDAT1;
+ __IO uint32_t JDAT2;
+ __IO uint32_t JDAT3;
+ __IO uint32_t JDAT4;
+ __IO uint32_t DAT;
+ __IO uint32_t DIFSEL;
+ __IO uint32_t CALFACT;
+ __IO uint32_t CTRL3;
+ __IO uint32_t SAMPT3;
+} ADC_Module;
+
+/**
+ * @brief OPAMP
+ */
+typedef struct
+{
+ __IO uint32_t CS1;
+ __IO uint32_t RES1[3];
+ __IO uint32_t CS2;
+ __IO uint32_t RES2[3];
+ __IO uint32_t LOCK;
+} OPAMP_Module;
+
+/**
+ * @brief COMP_Single
+ */
+typedef struct
+{
+ __IO uint32_t CTRL;
+ __IO uint32_t FILC;
+ __IO uint32_t FILP;
+} COMP_SingleType;
+
+/**
+ * @brief COMP
+ */
+typedef struct
+{
+ __IO uint32_t INTEN;
+ __IO uint32_t LPCKSEL;
+ __IO uint32_t WINMODE;
+ __IO uint32_t LOCK;
+ COMP_SingleType Cmp1;
+ __IO uint32_t RES;
+ COMP_SingleType Cmp2;
+ __IO uint32_t CMP2OSEL;
+ __IO uint32_t VREFSCL;
+ __IO uint32_t TEST;
+ __IO uint32_t INTSTS;
+} COMP_Module;
+
+/**
+ * @brief AFEC
+ */
+
+typedef struct
+{
+ __IO uint32_t TRIMR0;
+ __IO uint32_t TRIMR1;
+ __IO uint32_t TRIMR2;
+ __IO uint32_t TRIMR3;
+ __IO uint32_t TRIMR4;
+ __IO uint32_t TRIMR5;
+ __IO uint32_t TRIMR6;
+ __IO uint32_t TRIMR7;
+ __IO uint32_t TRIMR8;
+ //uint32_t RESERVED0;
+ __IO uint32_t TESTR0;
+ __IO uint32_t TESTR1;
+} AFEC_Module;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TMI;
+ __IO uint32_t TMDT;
+ __IO uint32_t TMDL;
+ __IO uint32_t TMDH;
+} CAN_TxMailBox_Param;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RMI;
+ __IO uint32_t RMDT;
+ __IO uint32_t RMDL;
+ __IO uint32_t RMDH;
+} CAN_FIFOMailBox_Param;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1;
+ __IO uint32_t FR2;
+} CAN_FilterRegister_Param;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCTRL;
+ __IO uint32_t MSTS;
+ __IO uint32_t TSTS;
+ __IO uint32_t RFF0;
+ __IO uint32_t RFF1;
+ __IO uint32_t INTE;
+ __IO uint32_t ESTS;
+ __IO uint32_t BTIM;
+ uint32_t RESERVED0[88];
+ CAN_TxMailBox_Param sTxMailBox[3];
+ CAN_FIFOMailBox_Param sFIFOMailBox[2];
+ uint32_t RESERVED1[12];
+ __IO uint32_t FMC;
+ __IO uint32_t FM1;
+ uint32_t RESERVED2;
+ __IO uint32_t FS1;
+ uint32_t RESERVED3;
+ __IO uint32_t FFA1;
+ uint32_t RESERVED4;
+ __IO uint32_t FA1;
+ uint32_t RESERVED5[8];
+ CAN_FilterRegister_Param sFilterRegister[14];
+} CAN_Module;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t CRC32DAT; /*!< CRC data register */
+ __IO uint8_t CRC32IDAT; /*!< CRC independent data register*/
+ uint8_t RESERVED0;
+ uint16_t RESERVED1;
+ __IO uint32_t CRC32CTRL; /*!< CRC control register */
+ __IO uint32_t CRC16CTRL;
+ __IO uint8_t CRC16DAT;
+ uint8_t RESERVED2;
+ uint16_t RESERVED3;
+ __IO uint16_t CRC16D;
+ uint16_t RESERVED4;
+ __IO uint8_t LRC;
+ uint8_t RESERVED5;
+ uint16_t RESERVED6;
+} CRC_Module;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CTRL;
+ __IO uint32_t SOTTR;
+ __IO uint32_t DR12CH;
+ __IO uint32_t DL12CH;
+ __IO uint32_t DR8CH;
+ __IO uint32_t DATO;
+
+} DAC_Module;
+/**
+ * @brief USB
+ */
+
+typedef struct
+{
+ __IO uint32_t EP0;
+ __IO uint32_t EP1;
+ __IO uint32_t EP2;
+ __IO uint32_t EP3;
+ __IO uint32_t EP4;
+ __IO uint32_t EP5;
+ __IO uint32_t EP6;
+ __IO uint32_t EP7;
+ __IO uint32_t Reserve20h;
+ __IO uint32_t Reserve24h;
+ __IO uint32_t Reserve28h;
+ __IO uint32_t Reserve2Ch;
+ __IO uint32_t Reserve30h;
+ __IO uint32_t Reserve34h;
+ __IO uint32_t Reserve38h;
+ __IO uint32_t Reserve3Ch;
+ __IO uint32_t CTRL;
+ __IO uint32_t STS;
+ __IO uint32_t FN;
+ __IO uint32_t ADDR;
+ __IO uint32_t BUFTAB;
+} USB_Module;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t ID;
+ __IO uint32_t CTRL;
+} DBG_Module;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CHCFG;
+ __IO uint32_t TXNUM;
+ __IO uint32_t PADDR;
+ __IO uint32_t MADDR;
+ __IO uint32_t CHSEL;
+
+} DMA_ChannelType;
+
+typedef struct
+{
+ __IO uint32_t INTSTS;
+ __IO uint32_t INTCLR;
+ __IO DMA_ChannelType DMA_Channel[8];
+} DMA_Module;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMASK; /*offset 0x00*/
+ __IO uint32_t EMASK; /*offset 0x04*/
+ __IO uint32_t RT_CFG; /*offset 0x08*/
+ __IO uint32_t FT_CFG; /*offset 0x0C*/
+ __IO uint32_t SWIE; /*offset 0x10*/
+ __IO uint32_t PEND; /*offset 0x14*/
+ __IO uint32_t TS_SEL; /*offset 0x18*/
+} EXTI_Module;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t AC;
+ __IO uint32_t KEYR;
+ __IO uint32_t OPTKEY;
+ __IO uint32_t STS;
+ __IO uint32_t CTRL;
+ __IO uint32_t ADD;
+ __IO uint32_t OB2;
+ __IO uint32_t OB;
+ __IO uint32_t WRP;
+ __IO uint32_t RESERVED0;
+ __IO uint32_t RESERVED1;
+ __IO uint32_t RESERVED2;
+ __IO uint32_t CAHR;
+} FLASH_Module;
+
+/**
+ * @brief Option Bytes Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t USER_RDP;
+ __IO uint32_t Data1_Data0;
+ __IO uint32_t WRP1_WRP0;
+ __IO uint32_t WRP3_WRP2;
+ __IO uint32_t USER2_RDP2;
+} OB_Module;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t PMODE; /*offset 0x00*/
+ __IO uint32_t POTYPE; /*offset 0x04*/
+ __IO uint32_t SR; /*offset 0x08*/
+ __IO uint32_t PUPD; /*offset 0x0C*/
+ __IO uint32_t PID; /*offset 0x10*/
+ __IO uint32_t POD; /*offset 0x14*/
+ __IO uint32_t PBSC; /*offset 0x18*/
+ __IO uint32_t PLOCK; /*offset 0x1C*/
+ __IO uint32_t AFL; /*offset 0x20*/
+ __IO uint32_t AFH; /*offset 0x24*/
+ __IO uint32_t PBC; /*offset 0x28*/
+ __IO uint32_t DS; /*offset 0x2C*/
+
+} GPIO_Module;
+
+/**
+ * @brief Alternate Function I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t RMP_CFG;
+ __IO uint32_t EXTI_CFG[4];
+} AFIO_Module;
+/**
+ * @brief Inter Integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint16_t CTRL1;
+ uint16_t RESERVED0;
+ __IO uint16_t CTRL2;
+ uint16_t RESERVED1;
+ __IO uint16_t OADDR1;
+ uint16_t RESERVED2;
+ __IO uint16_t OADDR2;
+ uint16_t RESERVED3;
+ __IO uint16_t DAT;
+ uint16_t RESERVED4;
+ __IO uint16_t STS1;
+ uint16_t RESERVED5;
+ __IO uint16_t STS2;
+ uint16_t RESERVED6;
+ __IO uint16_t CLKCTRL;
+ uint16_t RESERVED7;
+ __IO uint16_t TMRISE;
+ uint16_t RESERVED8;
+} I2C_Module;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KEY;
+ __IO uint32_t PREDIV; /*!< IWDG PREDIV */
+ __IO uint32_t RELV;
+ __IO uint32_t STS;
+} IWDG_Module;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CTRL1;
+ __IO uint32_t CTRL2;
+ __IO uint32_t CTRL3;
+ __IO uint32_t STS1;
+ __IO uint32_t STS2;
+ __IO uint32_t STSCLR;
+} PWR_Module;
+/**
+ * @brief Low-Power Timer
+ */
+typedef struct
+{
+ __IO uint32_t INTSTS;
+ __IO uint32_t INTCLR;
+ __IO uint32_t INTEN;
+ __IO uint32_t CFG;
+ __IO uint32_t CTRL;
+ __IO uint32_t COMPx;
+ __IO uint32_t ARR;
+ __IO uint32_t CNT;
+
+} LPTIM_Module;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CTRL;
+ __IO uint32_t CFG;
+ __IO uint32_t CLKINT;
+ __IO uint32_t APB2PRST;
+ __IO uint32_t APB1PRST;
+ __IO uint32_t AHBPCLKEN;
+ __IO uint32_t APB2PCLKEN;
+ __IO uint32_t APB1PCLKEN;
+ __IO uint32_t LDCTRL;
+ __IO uint32_t CTRLSTS;
+ __IO uint32_t AHBPRST;
+ __IO uint32_t CFG2;
+ __IO uint32_t CFG3;
+ __IO uint32_t RDCTRL;
+ __IO uint32_t Reserve0;
+ __IO uint32_t Reserve1;
+ __IO uint32_t PLLHSIPRE;
+ __IO uint32_t SRAM_CTRLSTS;
+} RCC_Module;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TSH; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DATE; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CTRL; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t INITSTS; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRE; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WKUPT; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t reserved0; /*!< Reserved */
+ __IO uint32_t ALARMA; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALARMB; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WRP; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SUBS; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SCTRL; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TST; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSD; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSS; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALIB; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TMPCFG; /*!< RTC tamper configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASS; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSS; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ __IO uint32_t OPT; /*!< RTC option register, Address offset: 0x4C */
+ __IO uint32_t BKP1R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP4R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP5R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP8R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP9R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP12R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP13R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP16R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP17R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP20R; /*!< RTC backup register 19, Address offset: 0x9C */
+ __IO uint32_t TSCWKUPCTRL; /*!< TSC register 1, Address offset: 0xA0 */
+ __IO uint32_t TSCWKUPCNT; /*!< TSC register 2, Address offset: 0xA4 */
+} RTC_Module;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint16_t CTRL1;
+ uint16_t RESERVED0;
+ __IO uint16_t CTRL2;
+ uint16_t RESERVED1;
+ __IO uint16_t STS;
+ uint16_t RESERVED2;
+ __IO uint16_t DAT;
+ uint16_t RESERVED3;
+ __IO uint16_t CRCPOLY;
+ uint16_t RESERVED4;
+ __IO uint16_t CRCRDAT;
+ uint16_t RESERVED5;
+ __IO uint16_t CRCTDAT;
+ uint16_t RESERVED6;
+ __IO uint16_t I2SCFG;
+ uint16_t RESERVED7;
+ __IO uint16_t I2SPREDIV;
+ uint16_t RESERVED8;
+} SPI_Module;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CTRL1;
+ __IO uint32_t CTRL2;
+ __IO uint16_t SMCTRL;
+ uint16_t RESERVED1;
+ __IO uint16_t DINTEN;
+ uint16_t RESERVED2;
+ __IO uint32_t STS;
+ __IO uint16_t EVTGEN;
+ uint16_t RESERVED3;
+ __IO uint16_t CCMOD1;
+ uint16_t RESERVED4;
+ __IO uint16_t CCMOD2;
+ uint16_t RESERVED5;
+ __IO uint32_t CCEN;
+ __IO uint16_t CNT;
+ uint16_t RESERVED6;
+ __IO uint16_t PSC;
+ uint16_t RESERVED7;
+ __IO uint16_t AR;
+ uint16_t RESERVED8;
+ __IO uint16_t REPCNT;
+ uint16_t RESERVED9;
+ __IO uint16_t CCDAT1;
+ uint16_t RESERVED10;
+ __IO uint16_t CCDAT2;
+ uint16_t RESERVED11;
+ __IO uint16_t CCDAT3;
+ uint16_t RESERVED12;
+ __IO uint16_t CCDAT4;
+ uint16_t RESERVED13;
+ __IO uint16_t BKDT;
+ uint16_t RESERVED14;
+ __IO uint16_t DCTRL;
+ uint16_t RESERVED15;
+ __IO uint16_t DADDR;
+ uint16_t RESERVED16;
+ uint32_t RESERVED17;
+ __IO uint16_t CCMOD3;
+ uint16_t RESERVED18;
+ __IO uint16_t CCDAT5;
+ uint16_t RESERVED19;
+ __IO uint16_t CCDAT6;
+ uint16_t RESERVED20;
+} TIM_Module;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint16_t STS;
+ uint16_t RESERVED0;
+ __IO uint16_t DAT;
+ uint16_t RESERVED1;
+ __IO uint16_t BRCF;
+ uint16_t RESERVED2;
+ __IO uint16_t CTRL1;
+ uint16_t RESERVED3;
+ __IO uint16_t CTRL2;
+ uint16_t RESERVED4;
+ __IO uint16_t CTRL3;
+ uint16_t RESERVED5;
+ __IO uint16_t GTP;
+ uint16_t RESERVED6;
+} USART_Module;
+
+/**
+ * @brief Low-power Universal Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint16_t STS;
+ uint16_t RESERVED0;
+ __IO uint8_t INTEN;
+ uint8_t RESERVED1;
+ uint16_t RESERVED2;
+ __IO uint16_t CTRL;
+ uint16_t RESERVED3;
+ __IO uint16_t BRCFG1;
+ uint16_t RESERVED4;
+ __IO uint8_t DAT;
+ uint8_t RESERVED5;
+ uint16_t RESERVED6;
+ __IO uint8_t BRCFG2;
+ uint8_t RESERVED7;
+ uint16_t RESERVED8;
+ __IO uint32_t WUDAT;
+} LPUART_Module;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CTRL;
+ __IO uint32_t CFG;
+ __IO uint32_t STS;
+} WWDG_Module;
+
+/**
+ * @brief LCD Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CTRL;
+ __IO uint32_t FCTRL;
+ __IO uint32_t STS;
+ __IO uint32_t CLR;
+ uint32_t RESERVED;
+ __IO uint32_t RAM_COM[16];
+} LCD_Module;
+
+/**
+ * @brief Touch Sensor Controller
+ */
+typedef struct
+{
+ __IO uint32_t CTRL;
+ __IO uint32_t CHNEN;
+ __IO uint32_t STS;
+ __IO uint32_t RESERVED;
+ __IO uint32_t ANA_CTRL;
+ __IO uint32_t ANA_SEL;
+ __IO uint32_t RESR[3];
+// __IO uint32_t RESR0;
+// __IO uint32_t RESR1;
+// __IO uint32_t RESR2;
+ __IO uint32_t THRHD[24];
+// __IO uint32_t THRHD0;
+// __IO uint32_t THRHD1;
+// __IO uint32_t THRHD2;
+// __IO uint32_t THRHD3;
+// __IO uint32_t THRHD4;
+// __IO uint32_t THRHD5;
+// __IO uint32_t THRHD6;
+// __IO uint32_t THRHD7;
+// __IO uint32_t THRHD8;
+// __IO uint32_t THRHD9;
+// __IO uint32_t THRHD10;
+// __IO uint32_t THRHD11;
+// __IO uint32_t THRHD12;
+// __IO uint32_t THRHD13;
+// __IO uint32_t THRHD14;
+// __IO uint32_t THRHD15;
+// __IO uint32_t THRHD16;
+// __IO uint32_t THRHD17;
+// __IO uint32_t THRHD18;
+// __IO uint32_t THRHD19;
+// __IO uint32_t THRHD20;
+// __IO uint32_t THRHD21;
+// __IO uint32_t THRHD22;
+// __IO uint32_t THRHD23;
+
+} TSC_Module;
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+#define UCID_BASE ((uint32_t)0x1FFFF7C0) /*!< UCID Address : 0x1FFF_F7C0 */
+#define UCID_LENGTH ((uint32_t)0x10) /*!< UCID Length : 16Bytes */
+#define UID_BASE ((uint32_t)0x1FFFF7F0) /*!< UID Address : 0x1FFF_F7F0 */
+#define UID_LENGTH ((uint32_t)0x0C) /*!< UID Length : 12Bytes */
+#define DBGMCU_ID_BASE ((uint32_t)0x1FFFF7FC) /*!< DBGMCU_ID Address */
+#define DBGMCU_ID_LENGTH ((uint8_t)0x04) /*!< DBGMCU_ID Length : 4 Bytes */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE (PERIPH_BASE)
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x18000)
+
+/* APB1 */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
+#define AFEC_BASE (APB1PERIPH_BASE + 0x1800)
+#define OPAMP_BASE (APB1PERIPH_BASE + 0x2000)
+#define COMP_BASE (APB1PERIPH_BASE + 0x2400)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define TSC_BASE (APB1PERIPH_BASE + 0x3400)
+
+#define TIM9_BASE (APB1PERIPH_BASE + 0x3C00)
+#define LCD_BASE (APB1PERIPH_BASE + 0x4000)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define LPTIM_BASE (APB1PERIPH_BASE + 0x4C00)
+#define LPUART_BASE (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define USB_BASE (APB1PERIPH_BASE + 0x5C00)
+#define USB_SRAM_BASE (APB1PERIPH_BASE + 0x6000)
+#define CAN_BASE (APB1PERIPH_BASE + 0x6400)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+
+/* APB2 */
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+#define SPI2_BASE (APB2PERIPH_BASE + 0x3C00)
+#define UART4_BASE (APB2PERIPH_BASE + 0x5000)
+#define UART5_BASE (APB2PERIPH_BASE + 0x5400)
+
+/* AHB */
+#define DMA_BASE (AHBPERIPH_BASE + 0x8000)
+#define DMA_CH1_BASE (AHBPERIPH_BASE + 0x8008)
+#define DMA_CH2_BASE (AHBPERIPH_BASE + 0x801C)
+#define DMA_CH3_BASE (AHBPERIPH_BASE + 0x8030)
+#define DMA_CH4_BASE (AHBPERIPH_BASE + 0x8044)
+#define DMA_CH5_BASE (AHBPERIPH_BASE + 0x8058)
+#define DMA_CH6_BASE (AHBPERIPH_BASE + 0x806C)
+#define DMA_CH7_BASE (AHBPERIPH_BASE + 0x8080)
+#define DMA_CH8_BASE (AHBPERIPH_BASE + 0x8094)
+#define ADC_BASE (AHBPERIPH_BASE + 0x8800)
+#define RCC_BASE (AHBPERIPH_BASE + 0x9000)
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0xA000) /*!< Flash registers base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+#define CRC_BASE (AHBPERIPH_BASE + 0xB000)
+#define SAC_BASE (AHBPERIPH_BASE + 0xC000)
+#define SAC_SRAM_BASE (AHBPERIPH_BASE + 0xC400)
+#define MMU_BASE (AHBPERIPH_BASE + 0xCC00)
+
+#define DBG_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+#define TIM2 ((TIM_Module*)TIM2_BASE)
+#define TIM3 ((TIM_Module*)TIM3_BASE)
+#define TIM4 ((TIM_Module*)TIM4_BASE)
+#define TIM5 ((TIM_Module*)TIM5_BASE)
+#define TIM6 ((TIM_Module*)TIM6_BASE)
+#define TIM7 ((TIM_Module*)TIM7_BASE)
+#define AFEC ((AFEC_Module*)AFEC_BASE)
+#define OPAMP ((OPAMP_Module*)OPAMP_BASE)
+#define COMP ((COMP_Module*)COMP_BASE)
+#define RTC ((RTC_Module*)RTC_BASE)
+#define WWDG ((WWDG_Module*)WWDG_BASE)
+#define IWDG ((IWDG_Module*)IWDG_BASE)
+#define TSC ((TSC_Module*)TSC_BASE)
+
+#define TIM9 ((TIM_Module*)TIM9_BASE)
+#define LCD ((LCD_Module*)LCD_BASE)
+#define USART2 ((USART_Module*)USART2_BASE)
+#define USART3 ((USART_Module*)USART3_BASE)
+#define LPTIM ((LPTIM_Module*)LPTIM_BASE)
+#define LPUART ((LPUART_Module*)LPUART_BASE)
+#define I2C1 ((I2C_Module*)I2C1_BASE)
+#define I2C2 ((I2C_Module*)I2C2_BASE)
+#define USB ((USB_Module*)USB_BASE)
+#define CAN ((CAN_Module*)CAN_BASE)
+#define PWR ((PWR_Module*)PWR_BASE)
+#define DAC ((DAC_Module*)DAC_BASE)
+#define AFIO ((AFIO_Module*)AFIO_BASE)
+#define EXTI ((EXTI_Module*)EXTI_BASE)
+#define GPIOA ((GPIO_Module*)GPIOA_BASE)
+#define GPIOB ((GPIO_Module*)GPIOB_BASE)
+#define GPIOC ((GPIO_Module*)GPIOC_BASE)
+#define GPIOD ((GPIO_Module*)GPIOD_BASE)
+#define TIM1 ((TIM_Module*)TIM1_BASE)
+#define SPI1 ((SPI_Module*)SPI1_BASE)
+#define TIM8 ((TIM_Module*)TIM8_BASE)
+#define USART1 ((USART_Module*)USART1_BASE)
+#define SPI2 ((SPI_Module*)SPI2_BASE)
+#define UART4 ((USART_Module*)UART4_BASE)
+#define UART5 ((USART_Module*)UART5_BASE)
+#define DMA ((DMA_Module*)DMA_BASE)
+#define DMA_CH1 ((DMA_ChannelType*)DMA_CH1_BASE)
+#define DMA_CH2 ((DMA_ChannelType*)DMA_CH2_BASE)
+#define DMA_CH3 ((DMA_ChannelType*)DMA_CH3_BASE)
+#define DMA_CH4 ((DMA_ChannelType*)DMA_CH4_BASE)
+#define DMA_CH5 ((DMA_ChannelType*)DMA_CH5_BASE)
+#define DMA_CH6 ((DMA_ChannelType*)DMA_CH6_BASE)
+#define DMA_CH7 ((DMA_ChannelType*)DMA_CH7_BASE)
+#define DMA_CH8 ((DMA_ChannelType*)DMA_CH8_BASE)
+#define ADC ((ADC_Module*)ADC_BASE)
+#define RCC ((RCC_Module*)RCC_BASE)
+#define FLASH ((FLASH_Module*)FLASH_R_BASE)
+#define OBT ((OB_Module*)OB_BASE)
+#define CRC ((CRC_Module*)CRC_BASE)
+
+#define DBG ((DBG_Module*)DBG_BASE)
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRC_CRC32DAT register *********************/
+#define CRC32_DAT_DAT ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/******************* Bit definition for CRC_CRC32IDAT register ********************/
+#define CRC32_IDAT_IDAT ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CRC32CTRL register ********************/
+#define CRC32_CTRL_RESET ((uint8_t)0x01) /*!< RESET bit */
+
+/******************** Bit definition for CRC16_CR register ********************/
+#define CRC16_CTRL_LITTLE ((uint8_t)0x02)
+#define CRC16_CTRL_BIG ((uint8_t)0xFD)
+
+#define CRC16_CTRL_RESET ((uint8_t)0x04)
+#define CRC16_CTRL_NO_RESET ((uint8_t)0xFB)
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CTRL1 register ********************/
+#define PWR_CTRL1_LPMSEL ((uint16_t)0x0007) /*!< no low power mode entered */
+#define PWR_CTRL1_STOP2 ((uint16_t)0x0002) /*!< stop2 mode */
+#define PWR_CTRL1_STANDBY ((uint16_t)0x0003) /*!< standby mode */
+
+
+#define PWR_CTRL1_DRBP ((uint16_t)0x0100) /*!< Access to RTC and Backup registers enabled */
+
+#define PWR_CTRL1_MRSEL ((uint16_t)0x0600) /*!< vddd Range Mask */
+#define PWR_CTRL1_MRSEL_bit0 ((uint16_t)0x0200) /*!< vddd Range MRSEL bit0 */
+#define PWR_CTRL1_MRSEL_bit1 ((uint16_t)0x0400) /*!< vddd Range MRSEL bit1 */
+#define PWR_CTRL1_MRSEL2 ((uint16_t)0x0400) /*!< vddd Range2=1.0 V */
+
+#define PWR_CTRL1_LPREN ((uint16_t)0x4000) /*!< When this bit is set, MR is turned off and LPR is used to run the main power domain. */
+#define PWR_CTRL1_MRSELMASK ((uint16_t)0x0600) /*!< MR voltage mask */
+/******************** Bit definition for PWR_CTRL2 register ********************/
+#define PWR_CTRL2_PVDEN ((uint16_t)0x0001) /*!< Power voltage detector enable */
+#define PWR_CTRL2_PLS1 ((uint16_t)0x0000) /*!< voltage threshold around 2.1 V */
+#define PWR_CTRL2_PLS2 ((uint16_t)0x0002) /*!< voltage threshold around 2.25 V */
+#define PWR_CTRL2_PLS3 ((uint16_t)0x0004) /*!< voltage threshold around 2.4 V */
+#define PWR_CTRL2_PLS4 ((uint16_t)0x0006) /*!< voltage threshold around 2.55 V */
+#define PWR_CTRL2_PLS5 ((uint16_t)0x0008) /*!< voltage threshold around 2.7 V */
+#define PWR_CTRL2_PLS6 ((uint16_t)0x000A) /*!< voltage threshold around 2.85 V */
+#define PWR_CTRL2_PLS7 ((uint16_t)0x000C) /*!< voltage threshold around 2.95 V */
+#define PWR_CTRL2_PLS8 ((uint16_t)0x000E) /*!< external input analog voltage PVD_IN (compared internally to VREFINT) */
+
+#define PWR_CTRL2_PVDFLTEN ((uint16_t)0x0010) /*!< Power voltage detector filter enable */
+
+
+/******************** Bit definition for PWR_CTRL3 register ********************/
+#define PWR_CTRL3_WKUP0EN ((uint16_t)0x0001) /*!< When this bit is set, WKUP0 pin is enable and triggers a wakeup from standby . */
+#define PWR_CTRL3_WKUP1EN ((uint16_t)0x0002) /*!< When this bit is set, WKUP1 pin is enable and triggers a wakeup from standby . */
+#define PWR_CTRL3_WKUP2EN ((uint16_t)0x0004) /*!< When this bit is set, WKUP2 pin is enable and triggers a wakeup from standby. */
+#define PWR_CTRL3_WKUP0PS ((uint16_t)0x0010) /*!< falling edge wake up */
+#define PWR_CTRL3_WKUP1PS ((uint16_t)0x0020) /*!< falling edge wake up */
+#define PWR_CTRL3_WKUP2PS ((uint16_t)0x0040) /*!< falling edge wake up */
+#define PWR_CTRL3_BGDTLPR ((uint16_t)0x0100) /*!< BANDGAP/BG_Buffer/IBIAS duty on in LPRUN */
+#define PWR_CTRL3_BGDTSTP2 ((uint16_t)0x0200) /*!< BANDGAP/BG_Buffer/IBIAS duty on in stop2 */
+#define PWR_CTRL3_BGDTSTBY ((uint16_t)0x0400) /*!< BANDGAP/BG_Buffer/IBIAS duty on in standby */
+#define PWR_CTRL3_RAM1RET ((uint16_t)0x1000) /*!< SRAM1 is powered by the LPR in stop2 mode */
+#define PWR_CTRL3_RAM2RET ((uint16_t)0x2000) /*!< SRAM2 is powered by the LPR in standby mode */
+#define PWR_CTRL3_IWKUPLEN ((uint16_t)0x4000) /*!< internal wakeup line enable */
+
+#define PWR_CTRL3_PBDTLPR ((uint32_t)0x10000) /*!< PVDBOR duty on in LP RUN */
+#define PWR_CTRL3_PBDTSTP2 ((uint32_t)0x20000) /*!< PVDBOR duty on in STOP2 */
+#define PWR_CTRL3_PBDTSTBY ((uint32_t)0x40000) /*!< PVDBOR is iduty on standby */
+#define PWR_CTRL3_PSTSTBY ((uint32_t)0x100000) /*!< PAD in HI-Z state */
+#define PWR_CTRL3_PSTSTP2 ((uint32_t)0x200000) /*!< PAD in HI-Z state */
+
+#define PWR_CTRL3_RAMRETMASK ((uint16_t)0x3000) /*!< SRAM1 and SRAM2 ENABLE */
+#define PWR_CTRL1_LPMSELMASK ((uint16_t)0x0007) /*!< Low power mode selection */
+#define PWR_CTRL2_PLSMASK ((uint16_t)0x000E) /*!< Low power mode selection */
+/******************** Bit definition for PWR_STS1 register ********************/
+#define PWR_STS1_WKUPF0 ((uint16_t)0x0001) /*!< This bit is set when a wakeup event is detected on wakeup pin, WKUP0. */
+#define PWR_STS1_WKUPF1 ((uint16_t)0x0002) /*!< This bit is set when a wakeup event is detected on wakeup pin, WKUP1. */
+#define PWR_STS1_WKUPF2 ((uint16_t)0x0004) /*!< This bit is set when a wakeup event is detected on wakeup pin, WKUP2. */
+#define PWR_STS1_STBYF ((uint16_t)0x0100) /*!< the device entered the standby mode */
+#define PWR_STS1_IWKUPF ((uint16_t)0x8000) /*!< This bit is set when a wakeup is detected on the internal wakeup line. */
+
+/******************** Bit definition for PWR_STS2 register ********************/
+#define PWR_STS2_LPRUNF ((uint16_t)0x0001) /*!< MCU is in low power run mode */
+#define PWR_STS2_MRF ((uint16_t)0x0002) /*!< voltage scaling ready */
+#define PWR_STS2_PVDO ((uint16_t)0x0004) /*!< Power voltage detector output */
+
+/******************** Bit definition for PWR_STSCLR register ********************/
+#define PWR_STSCLR_CLRWKUP0 ((uint16_t)0x0001) /*!< Setting this bit clears the WKPF1 flag in the PWR_STS1 register */
+#define PWR_STSCLR_CLRWKUP1 ((uint16_t)0x0002) /*!< Setting this bit clears the WKPF2 flag in the PWR_STS1 register */
+#define PWR_STSCLR_CLRWKUP2 ((uint16_t)0x0004) /*!< Setting this bit clears the WKPF3 flag in the PWR_STS1 register */
+#define PWR_STSCLR_CLRSTBY ((uint16_t)0x0100) /*!< Setting this bit clears the SBF flag in the PWR_STS1 register */
+
+
+
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for RCC_CTRL register ********************/
+#define RCC_CTRL_HSIEN ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
+#define RCC_CTRL_HSIRDF ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
+#define RCC_CTRL_HSITRIM ((uint32_t)0x0000007C) /*!< Internal High Speed clock trimming */
+#define RCC_CTRL_HSICAL ((uint32_t)0x0000FF80) /*!< Internal High Speed clock Calibration */
+#define RCC_CTRL_HSEEN ((uint32_t)0x00010000) /*!< External High Speed clock enable */
+#define RCC_CTRL_HSERDF ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
+#define RCC_CTRL_HSEBP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
+#define RCC_CTRL_CLKSSEN ((uint32_t)0x00080000) /*!< Clock Security System enable */
+#define RCC_CTRL_PLLEN ((uint32_t)0x01000000) /*!< PLL enable */
+#define RCC_CTRL_PLLRDF ((uint32_t)0x02000000) /*!< PLL clock ready flag */
+
+/******************* Bit definition for RCC_CFG register *******************/
+/*!< SW configuration */
+#define RCC_CFG_SCLKSW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFG_SCLKSW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFG_SCLKSW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFG_SCLKSW_MSI ((uint32_t)0x00000000) /*!< MSI selected as system clock */
+#define RCC_CFG_SCLKSW_HSI ((uint32_t)0x00000001) /*!< HSI selected as system clock */
+#define RCC_CFG_SCLKSW_HSE ((uint32_t)0x00000002) /*!< HSE selected as system clock */
+#define RCC_CFG_SCLKSW_PLL ((uint32_t)0x00000003) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFG_SCLKSTS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFG_SCLKSTS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFG_SCLKSTS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFG_SCLKSTS_MSI ((uint32_t)0x00000000) /*!< MSI oscillator used as system clock */
+#define RCC_CFG_SCLKSTS_HSI ((uint32_t)0x00000004) /*!< HSI oscillator used as system clock */
+#define RCC_CFG_SCLKSTS_HSE ((uint32_t)0x00000008) /*!< HSE oscillator used as system clock */
+#define RCC_CFG_SCLKSTS_PLL ((uint32_t)0x0000000C) /*!< PLL used as system clock */
+
+/*!< AHBPRES configuration */
+#define RCC_CFG_AHBPRES ((uint32_t)0x000000F0) /*!< AHBPRES[3:0] bits (AHB prescaler) */
+#define RCC_CFG_AHBPRES_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFG_AHBPRES_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFG_AHBPRES_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFG_AHBPRES_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFG_AHBPRES_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFG_AHBPRES_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFG_AHBPRES_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFG_AHBPRES_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFG_AHBPRES_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFG_AHBPRES_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFG_AHBPRES_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFG_AHBPRES_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFG_AHBPRES_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< APB1PRES configuration */
+#define RCC_CFG_APB1PRES ((uint32_t)0x00000700) /*!< APB1PRES[2:0] bits (APB1 prescaler) */
+#define RCC_CFG_APB1PRES_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_CFG_APB1PRES_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define RCC_CFG_APB1PRES_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+#define RCC_CFG_APB1PRES_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFG_APB1PRES_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFG_APB1PRES_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFG_APB1PRES_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFG_APB1PRES_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< APB2PRES configuration */
+#define RCC_CFG_APB2PRES ((uint32_t)0x00003800) /*!< APB2PRES[2:0] bits (APB2 prescaler) */
+#define RCC_CFG_APB2PRES_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define RCC_CFG_APB2PRES_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+#define RCC_CFG_APB2PRES_2 ((uint32_t)0x00002000) /*!< Bit 2 */
+
+#define RCC_CFG_APB2PRES_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFG_APB2PRES_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFG_APB2PRES_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFG_APB2PRES_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFG_APB2PRES_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+/*!< PLLSRC configuration */
+#define RCC_CFG_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
+
+#define RCC_CFG_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI clock selected as PLL entry clock source */
+#define RCC_CFG_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */
+
+/*!< PLLXTPRE configuration */
+#define RCC_CFG_PLLHSEPRES ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
+
+#define RCC_CFG_PLLHSEPRES_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
+#define RCC_CFG_PLLHSEPRES_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFG_PLLMULFCT ((uint32_t)0x083C0000) /*!< PLLMUL[4:0] bits (PLL multiplication factor) */
+#define RCC_CFG_PLLMULFCT_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFG_PLLMULFCT_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define RCC_CFG_PLLMULFCT_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+#define RCC_CFG_PLLMULFCT_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+#define RCC_CFG_PLLMULFCT_4 ((uint32_t)0x08000000) /*!< Bit 4 */
+
+#define RCC_CFG_PLLMULFCT2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFG_PLLMULFCT3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
+#define RCC_CFG_PLLMULFCT4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
+#define RCC_CFG_PLLMULFCT5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
+#define RCC_CFG_PLLMULFCT6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
+#define RCC_CFG_PLLMULFCT7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
+#define RCC_CFG_PLLMULFCT8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
+#define RCC_CFG_PLLMULFCT9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
+#define RCC_CFG_PLLMULFCT10 ((uint32_t)0x00200000) /*!< PLL input clock*10 */
+#define RCC_CFG_PLLMULFCT11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
+#define RCC_CFG_PLLMULFCT12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
+#define RCC_CFG_PLLMULFCT13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
+#define RCC_CFG_PLLMULFCT14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
+#define RCC_CFG_PLLMULFCT15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
+#define RCC_CFG_PLLMULFCT16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
+#define RCC_CFG_PLLMULFCT16N ((uint32_t)0x003C0000) /*!< PLL input clock*16 */
+#define RCC_CFG_PLLMULFCT17 ((uint32_t)0x08000000) /*!< PLL input clock*17 */
+#define RCC_CFG_PLLMULFCT18 ((uint32_t)0x08040000) /*!< PLL input clock*18 */
+#define RCC_CFG_PLLMULFCT19 ((uint32_t)0x08080000) /*!< PLL input clock*19 */
+#define RCC_CFG_PLLMULFCT20 ((uint32_t)0x080C0000) /*!< PLL input clock*20 */
+#define RCC_CFG_PLLMULFCT21 ((uint32_t)0x08100000) /*!< PLL input clock*21 */
+#define RCC_CFG_PLLMULFCT22 ((uint32_t)0x08140000) /*!< PLL input clock*22 */
+#define RCC_CFG_PLLMULFCT23 ((uint32_t)0x08180000) /*!< PLL input clock*23 */
+#define RCC_CFG_PLLMULFCT24 ((uint32_t)0x081C0000) /*!< PLL input clock*24 */
+#define RCC_CFG_PLLMULFCT25 ((uint32_t)0x08200000) /*!< PLL input clock*25 */
+#define RCC_CFG_PLLMULFCT26 ((uint32_t)0x08240000) /*!< PLL input clock*26 */
+#define RCC_CFG_PLLMULFCT27 ((uint32_t)0x08280000) /*!< PLL input clock*27 */
+#define RCC_CFG_PLLMULFCT28 ((uint32_t)0x082C0000) /*!< PLL input clock*28 */
+#define RCC_CFG_PLLMULFCT29 ((uint32_t)0x08300000) /*!< PLL input clock*29 */
+#define RCC_CFG_PLLMULFCT30 ((uint32_t)0x08340000) /*!< PLL input clock*30 */
+#define RCC_CFG_PLLMULFCT31 ((uint32_t)0x08380000) /*!< PLL input clock*31 */
+#define RCC_CFG_PLLMULFCT32 ((uint32_t)0x083C0000) /*!< PLL input clock*32 */
+
+/*!< USBPRES configuration */
+#define RCC_CFG_USBPRES ((uint32_t)0x00C00000) /*!< USB Device prescaler */
+#define RCC_CFG_USBPRES_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define RCC_CFG_USBPRES_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define RCC_CFG_USBPRES_PLLDIV1_5 ((uint32_t)0x00000000) /*!< PLL clock is divided by 1.5 */
+#define RCC_CFG_USBPRES_PLLDIV1 ((uint32_t)0x00400000) /*!< PLL clock is not divided */
+#define RCC_CFG_USBPRES_PLLDIV2 ((uint32_t)0x00800000) /*!< PLL clock is divided by 2 */
+#define RCC_CFG_USBPRES_PLLDIV3 ((uint32_t)0x00C00000) /*!< PLL clock is divided by 3 */
+
+/*!< MCO configuration */
+#define RCC_CFG_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define RCC_CFG_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define RCC_CFG_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define RCC_CFG_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define RCC_CFG_MCO_NOCLK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFG_MCO_LSI ((uint32_t)0x01000000) /*!< LSI clock selected as MCO source */
+#define RCC_CFG_MCO_LSE ((uint32_t)0x02000000) /*!< LSE clock selected as MCO source */
+#define RCC_CFG_MCO_MSI ((uint32_t)0x03000000) /*!< MSI clock selected as MCO source */
+#define RCC_CFG_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFG_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFG_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFG_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock selected as MCO source */
+
+/*!< MCOPRE configuration */
+#define RCC_CFG_MCOPRES ((uint32_t)0xF0000000) /*!< MCOPRE[3:0] bits ( PLL prescaler set and cleared by
+ software to generate MCOPRE clock.) */
+#define RCC_CFG_MCOPRES_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define RCC_CFG_MCOPRES_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+#define RCC_CFG_MCOPRES_2 ((uint32_t)0x40000000) /*!< Bit 2 */
+#define RCC_CFG_MCOPRES_3 ((uint32_t)0x80000000) /*!< Bit 3 */
+
+#define RCC_CFG_MCOPRES_PLLDIV1 ((uint32_t)0x00000000) /*!< PLL clock is not divided */
+#define RCC_CFG_MCOPRES_PLLDIV2 ((uint32_t)0x10000000) /*!< PLL clock is divided by 2 */
+#define RCC_CFG_MCOPRES_PLLDIV3 ((uint32_t)0x20000000) /*!< PLL clock is divided by 3 */
+#define RCC_CFG_MCOPRES_PLLDIV4 ((uint32_t)0x30000000) /*!< PLL clock is divided by 4 */
+#define RCC_CFG_MCOPRES_PLLDIV5 ((uint32_t)0x40000000) /*!< PLL clock is divided by 5 */
+#define RCC_CFG_MCOPRES_PLLDIV6 ((uint32_t)0x50000000) /*!< PLL clock is divided by 6 */
+#define RCC_CFG_MCOPRES_PLLDIV7 ((uint32_t)0x60000000) /*!< PLL clock is divided by 7 */
+#define RCC_CFG_MCOPRES_PLLDIV8 ((uint32_t)0x70000000) /*!< PLL clock is divided by 8 */
+#define RCC_CFG_MCOPRES_PLLDIV9 ((uint32_t)0x80000000) /*!< PLL clock is divided by 9 */
+#define RCC_CFG_MCOPRES_PLLDIV10 ((uint32_t)0x90000000) /*!< PLL clock is divided by 10 */
+#define RCC_CFG_MCOPRES_PLLDIV11 ((uint32_t)0xA0000000) /*!< PLL clock is divided by 11 */
+#define RCC_CFG_MCOPRES_PLLDIV12 ((uint32_t)0xB0000000) /*!< PLL clock is divided by 12 */
+#define RCC_CFG_MCOPRES_PLLDIV13 ((uint32_t)0xC0000000) /*!< PLL clock is divided by 13 */
+#define RCC_CFG_MCOPRES_PLLDIV14 ((uint32_t)0xD0000000) /*!< PLL clock is divided by 14 */
+#define RCC_CFG_MCOPRES_PLLDIV15 ((uint32_t)0xE0000000) /*!< PLL clock is divided by 15 */
+#define RCC_CFG_MCOPRES_PLLDIV16 ((uint32_t)0xF0000000) /*!< PLL clock is divided by 16 */
+
+/*!<****************** Bit definition for RCC_CLKINT register ********************/
+#define RCC_CLKINT_LSIRDIF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
+#define RCC_CLKINT_LSERDIF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
+#define RCC_CLKINT_HSIRDIF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
+#define RCC_CLKINT_HSERDIF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
+#define RCC_CLKINT_PLLRDIF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
+#define RCC_CLKINT_BORIF ((uint32_t)0x00000020) /*!< BOR Interrupt flag */
+#define RCC_CLKINT_MSIRDIF ((uint32_t)0x00000040) /*!< MSI Ready Interrupt flag */
+#define RCC_CLKINT_CLKSSIF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
+#define RCC_CLKINT_LSIRDIEN ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
+#define RCC_CLKINT_LSERDIEN ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
+#define RCC_CLKINT_HSIRDIEN ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
+#define RCC_CLKINT_HSERDIEN ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
+#define RCC_CLKINT_PLLRDIEN ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
+#define RCC_CLKINT_BORIEN ((uint32_t)0x00002000) /*!< BOR Interrupt Enable */
+#define RCC_CLKINT_MSIRDIEN ((uint32_t)0x00004000) /*!< MSI Ready Interrupt Enable */
+#define RCC_CLKINT_MSIRDICLR ((uint32_t)0x00008000) /*!< MSI Ready Interrupt Clear */
+#define RCC_CLKINT_LSIRDICLR ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
+#define RCC_CLKINT_LSERDICLR ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
+#define RCC_CLKINT_HSIRDICLR ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
+#define RCC_CLKINT_HSERDICLR ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
+#define RCC_CLKINT_PLLRDICLR ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
+#define RCC_CLKINT_BORICLR ((uint32_t)0x00200000) /*!< BOR Interrupt Clear */
+#define RCC_CLKINT_CLKSSICLR ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
+#define RCC_CLKINT_LSESSIF ((uint32_t)0x01000000) /*!< LSE Security System Interrupt flag */
+#define RCC_CLKINT_LSESSIEN ((uint32_t)0x02000000) /*!< LSE ecurity System Interrupt Enable */
+#define RCC_CLKINT_LSESSICLR ((uint32_t)0x04000000) /*!< LSE ecurity System Interrupt Clear */
+
+/***************** Bit definition for RCC_APB2PRST register *****************/
+#define RCC_APB2PRST_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */
+#define RCC_APB2PRST_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */
+#define RCC_APB2PRST_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */
+#define RCC_APB2PRST_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */
+#define RCC_APB2PRST_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */
+#define RCC_APB2PRST_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */
+#define RCC_APB2PRST_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */
+#define RCC_APB2PRST_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */
+#define RCC_APB2PRST_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
+#define RCC_APB2PRST_UART4RST ((uint32_t)0x00020000) /*!< UART4 reset */
+#define RCC_APB2PRST_UART5RST ((uint32_t)0x00040000) /*!< UART5 reset */
+#define RCC_APB2PRST_SPI2RST ((uint32_t)0x00080000) /*!< SPI2 reset */
+
+/***************** Bit definition for RCC_APB1PRST register *****************/
+#define RCC_APB1PRST_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
+#define RCC_APB1PRST_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
+#define RCC_APB1PRST_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
+#define RCC_APB1PRST_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
+#define RCC_APB1PRST_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
+#define RCC_APB1PRST_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
+#define RCC_APB1PRST_COMPRST ((uint32_t)0x00000040) /*!< COMP reset */
+#define RCC_APB1PRST_TIM9RST ((uint32_t)0x00000200) /*!< Timer 9 reset */
+#define RCC_APB1PRST_TSCRST ((uint32_t)0x00000400) /*!< TSC reset */
+#define RCC_APB1PRST_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
+#define RCC_APB1PRST_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
+#define RCC_APB1PRST_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
+#define RCC_APB1PRST_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
+#define RCC_APB1PRST_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
+#define RCC_APB1PRST_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */
+#define RCC_APB1PRST_UCDRRST ((uint32_t)0x01000000) /*!< UCDR reset */
+#define RCC_APB1PRST_CANRST ((uint32_t)0x02000000) /*!< CAN reset */
+#define RCC_APB1PRST_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
+#define RCC_APB1PRST_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
+#define RCC_APB1PRST_OPARST ((uint32_t)0x80000000) /*!< OPA interface reset */
+
+/****************** Bit definition for RCC_AHBPCLKEN register ******************/
+#define RCC_AHBPCLKEN_DMAEN ((uint32_t)0x00000001) /*!< DMA clock enable */
+#define RCC_AHBPCLKEN_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
+#define RCC_AHBPCLKEN_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
+#define RCC_AHBPCLKEN_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
+#define RCC_AHBPCLKEN_RNGCEN ((uint32_t)0x00000200) /*!< RNGC clock enable */
+#define RCC_AHBPCLKEN_SACEN ((uint32_t)0x00000800) /*!< SAC clock enable */
+#define RCC_AHBPCLKEN_ADCEN ((uint32_t)0x00001000) /*!< ADC clock enable */
+
+/****************** Bit definition for RCC_APB2PCLKEN register *****************/
+#define RCC_APB2PCLKEN_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */
+#define RCC_APB2PCLKEN_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */
+#define RCC_APB2PCLKEN_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */
+#define RCC_APB2PCLKEN_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */
+#define RCC_APB2PCLKEN_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */
+#define RCC_APB2PCLKEN_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */
+#define RCC_APB2PCLKEN_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
+#define RCC_APB2PCLKEN_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */
+#define RCC_APB2PCLKEN_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
+#define RCC_APB2PCLKEN_UART4EN ((uint32_t)0x00020000) /*!< UART4 clock enable */
+#define RCC_APB2PCLKEN_UART5EN ((uint32_t)0x00040000) /*!< UART5 clock enable */
+#define RCC_APB2PCLKEN_SPI2EN ((uint32_t)0x00080000) /*!< SPI2 clock enable */
+
+/***************** Bit definition for RCC_APB1PCLKEN register ******************/
+#define RCC_APB1PCLKEN_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
+#define RCC_APB1PCLKEN_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
+#define RCC_APB1PCLKEN_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
+#define RCC_APB1PCLKEN_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */
+#define RCC_APB1PCLKEN_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
+#define RCC_APB1PCLKEN_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
+#define RCC_APB1PCLKEN_COMPEN ((uint32_t)0x00000040) /*!< COMP clock enable */
+#define RCC_APB1PCLKEN_COMPFILTEN ((uint32_t)0x00000080) /*!< COMPFILT clock enable */
+#define RCC_APB1PCLKEN_AFECEN ((uint32_t)0x00000100) /*!< AFEC clock enable */
+#define RCC_APB1PCLKEN_TIM9EN ((uint32_t)0x00000200) /*!< Timer 9 clock enable */
+#define RCC_APB1PCLKEN_TSCEN ((uint32_t)0x00000400) /*!< TSC clock enable */
+#define RCC_APB1PCLKEN_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
+#define RCC_APB1PCLKEN_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
+#define RCC_APB1PCLKEN_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
+#define RCC_APB1PCLKEN_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
+#define RCC_APB1PCLKEN_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
+#define RCC_APB1PCLKEN_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */
+#define RCC_APB1PCLKEN_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
+#define RCC_APB1PCLKEN_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
+#define RCC_APB1PCLKEN_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
+#define RCC_APB1PCLKEN_OPAMPEN ((uint32_t)0x80000000) /*!< OPAMP interface clock enable */
+
+/******************* Bit definition for RCC_LDCTRL register *******************/
+#define RCC_LDCTRL_LSEEN ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
+#define RCC_LDCTRL_LSERD ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
+#define RCC_LDCTRL_LSEBP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
+
+#define RCC_LDCTRL_LSECLKSSEN ((uint32_t)0x00000008) /*!< LSE Security System enable */
+#define RCC_LDCTRL_LSECLKSSF ((uint32_t)0x00000010) /*!< LSE Security System failure detection */
+#define RCC_LDCTRL_LSXSEL ((uint32_t)0x00000020) /*!< LSXSEL bits (TSC clock source selection) */
+
+#define RCC_LDCTRL_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_LDCTRL_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_LDCTRL_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< RTC congiguration */
+#define RCC_LDCTRL_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_LDCTRL_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_LDCTRL_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_LDCTRL_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 32 used as RTC clock */
+
+#define RCC_LDCTRL_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
+#define RCC_LDCTRL_LDSFTRST ((uint32_t)0x00010000) /*!< Low power domain software reset */
+#define RCC_LDCTRL_BORRSTF ((uint32_t)0x10000000) /*!< BOR reset flag */
+#define RCC_LDCTRL_LDEMCRSTF ((uint32_t)0x40000000) /*!< Low power EMC reset flag */
+
+/******************* Bit definition for RCC_CTRLSTS register ********************/
+#define RCC_CTRLSTS_LSIEN ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
+#define RCC_CTRLSTS_LSIRD ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
+#define RCC_CTRLSTS_MSIEN ((uint32_t)0x00000004) /*!< Internal Multi Speed oscillator enable */
+#define RCC_CTRLSTS_MSIRD ((uint32_t)0x00000008) /*!< Internal Multi Speed oscillator Ready */
+
+#define RCC_CTRLSTS_MSIRANGE ((uint32_t)0x00000070) /*!< Internal Multi Speed oscillator Clock Range */
+#define RCC_CTRLSTS_MSIRANGE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CTRLSTS_MSIRANGE_1 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define RCC_CTRLSTS_MSIRANGE_2 ((uint32_t)0x00000040) /*!< Bit 0 */
+
+#define RCC_CTRLSTS_MSIRANGE_100KHz ((uint32_t)0x00000000) /*!< Internal Multi Speed oscillator output 100KHz */
+#define RCC_CTRLSTS_MSIRANGE_200KHz ((uint32_t)0x00000010) /*!< Internal Multi Speed oscillator output 200KHz */
+#define RCC_CTRLSTS_MSIRANGE_400KHz ((uint32_t)0x00000020) /*!< Internal Multi Speed oscillator output 400KHz */
+#define RCC_CTRLSTS_MSIRANGE_800KHz ((uint32_t)0x00000030) /*!< Internal Multi Speed oscillator output 800KHz */
+#define RCC_CTRLSTS_MSIRANGE_1MHz ((uint32_t)0x00000040) /*!< Internal Multi Speed oscillator output 1MHz */
+#define RCC_CTRLSTS_MSIRANGE_2MHz ((uint32_t)0x00000050) /*!< Internal Multi Speed oscillator output 2MHz */
+#define RCC_CTRLSTS_MSIRANGE_4MHz ((uint32_t)0x00000060) /*!< Internal Multi Speed oscillator output 4MHz */
+
+#define RCC_CTRLSTS_MSICAL ((uint32_t)0x00007F80) /*!< Internal Multi Speed clock Calibration */
+#define RCC_CTRLSTS_MSITRIM ((uint32_t)0x007F8000) /*!< Internal Multi Speed clock trimming */
+#define RCC_CTRLSTS_RAMRSTF ((uint32_t)0x00800000) /*!< RAM reset flag */
+#define RCC_CTRLSTS_RMRSTF ((uint32_t)0x01000000) /*!< Remove reset flag */
+#define RCC_CTRLSTS_MMURSTF ((uint32_t)0x02000000) /*!< MMU reset flag */
+#define RCC_CTRLSTS_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
+#define RCC_CTRLSTS_PORRSTF ((uint32_t)0x08000000) /*!< POR reset flag */
+#define RCC_CTRLSTS_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
+#define RCC_CTRLSTS_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
+#define RCC_CTRLSTS_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
+#define RCC_CTRLSTS_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
+
+/******************* Bit definition for RCC_AHBPRST register ****************/
+#define RCC_AHBRST_RNGCRST ((uint32_t)0x00000200) /*!< RNGC reset */
+#define RCC_AHBRST_SACRST ((uint32_t)0x00000800) /*!< SAC reset */
+#define RCC_AHBRST_ADCRST ((uint32_t)0x00001000) /*!< ADC reset */
+
+/******************* Bit definition for RCC_CFG2 register ******************/
+/*!< ADCHPRE configuration */
+#define RCC_CFG2_ADCHPRES ((uint32_t)0x0000000F) /*!< ADCHPRE[3:0] bits */
+#define RCC_CFG2_ADCHPRES_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFG2_ADCHPRES_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RCC_CFG2_ADCHPRES_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RCC_CFG2_ADCHPRES_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define RCC_CFG2_ADCHPRES_DIV1 ((uint32_t)0x00000000) /*!< HCLK clock divided by 1 */
+#define RCC_CFG2_ADCHPRES_DIV2 ((uint32_t)0x00000001) /*!< HCLK clock divided by 2 */
+#define RCC_CFG2_ADCHPRES_DIV4 ((uint32_t)0x00000002) /*!< HCLK clock divided by 4 */
+#define RCC_CFG2_ADCHPRES_DIV6 ((uint32_t)0x00000003) /*!< HCLK clock divided by 6 */
+#define RCC_CFG2_ADCHPRES_DIV8 ((uint32_t)0x00000004) /*!< HCLK clock divided by 8 */
+#define RCC_CFG2_ADCHPRES_DIV10 ((uint32_t)0x00000005) /*!< HCLK clock divided by 10 */
+#define RCC_CFG2_ADCHPRES_DIV12 ((uint32_t)0x00000006) /*!< HCLK clock divided by 12 */
+#define RCC_CFG2_ADCHPRES_DIV16 ((uint32_t)0x00000007) /*!< HCLK clock divided by 16 */
+#define RCC_CFG2_ADCHPRES_DIV32 ((uint32_t)0x00000008) /*!< HCLK clock divided by 32 */
+#define RCC_CFG2_ADCHPRES_OTHERS ((uint32_t)0x00000008) /*!< HCLK clock divided by 32 */
+
+/*!< ADCPLLPRES configuration */
+#define RCC_CFG2_ADCPLLPRES ((uint32_t)0x000001F0) /*!< ADCPLLPRES[4:0] bits */
+#define RCC_CFG2_ADCPLLPRES_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFG2_ADCPLLPRES_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFG2_ADCPLLPRES_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFG2_ADCPLLPRES_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+#define RCC_CFG2_ADCPLLPRES_4 ((uint32_t)0x00000100) /*!< Bit 4 */
+
+#define RCC_CFG2_ADCPLLCLK_DISABLE ((uint32_t)0xFFFFFEFF) /*!< ADC PLL clock Disable */
+#define RCC_CFG2_ADCPLLPRES_DIV1 ((uint32_t)0x00000100) /*!< PLL clock divided by 1 */
+#define RCC_CFG2_ADCPLLPRES_DIV2 ((uint32_t)0x00000110) /*!< PLL clock divided by 2 */
+#define RCC_CFG2_ADCPLLPRES_DIV4 ((uint32_t)0x00000120) /*!< PLL clock divided by 4 */
+#define RCC_CFG2_ADCPLLPRES_DIV6 ((uint32_t)0x00000130) /*!< PLL clock divided by 6 */
+#define RCC_CFG2_ADCPLLPRES_DIV8 ((uint32_t)0x00000140) /*!< PLL clock divided by 8 */
+#define RCC_CFG2_ADCPLLPRES_DIV10 ((uint32_t)0x00000150) /*!< PLL clock divided by 10 */
+#define RCC_CFG2_ADCPLLPRES_DIV12 ((uint32_t)0x00000160) /*!< PLL clock divided by 12 */
+#define RCC_CFG2_ADCPLLPRES_DIV16 ((uint32_t)0x00000170) /*!< PLL clock divided by 16 */
+#define RCC_CFG2_ADCPLLPRES_DIV32 ((uint32_t)0x00000180) /*!< PLL clock divided by 32 */
+#define RCC_CFG2_ADCPLLPRES_DIV64 ((uint32_t)0x00000190) /*!< PLL clock divided by 64 */
+#define RCC_CFG2_ADCPLLPRES_DIV128 ((uint32_t)0x000001A0) /*!< PLL clock divided by 128 */
+#define RCC_CFG2_ADCPLLPRES_DIV256 ((uint32_t)0x000001B0) /*!< PLL clock divided by 256 */
+#define RCC_CFG2_ADCPLLPRES_DIV256N ((uint32_t)0x000001C0) /*!< PLL clock divided by 256 */
+
+/*!< ADC1MPRE configuration */
+#define RCC_CFG2_ADC1MPRES ((uint32_t)0x0001F000) /*!< ADC1MPRE[4:0] bits */
+#define RCC_CFG2_ADC1MPRES_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define RCC_CFG2_ADC1MPRES_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define RCC_CFG2_ADC1MPRES_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+#define RCC_CFG2_ADC1MPRES_3 ((uint32_t)0x00008000) /*!< Bit 3 */
+#define RCC_CFG2_ADC1MPRES_4 ((uint32_t)0x00010000) /*!< Bit 4 */
+
+#define RCC_CFG2_ADC1MPRES_DIV1 ((uint32_t)0x00000000) /*!< ADC1M source clock is divided by 1 */
+#define RCC_CFG2_ADC1MPRES_DIV2 ((uint32_t)0x00001000) /*!< ADC1M source clock is divided by 2 */
+#define RCC_CFG2_ADC1MPRES_DIV3 ((uint32_t)0x00002000) /*!< ADC1M source clock is divided by 3 */
+#define RCC_CFG2_ADC1MPRES_DIV4 ((uint32_t)0x00003000) /*!< ADC1M source clock is divided by 4 */
+#define RCC_CFG2_ADC1MPRES_DIV5 ((uint32_t)0x00004000) /*!< ADC1M source clock is divided by 5 */
+#define RCC_CFG2_ADC1MPRES_DIV6 ((uint32_t)0x00005000) /*!< ADC1M source clock is divided by 6 */
+#define RCC_CFG2_ADC1MPRES_DIV7 ((uint32_t)0x00006000) /*!< ADC1M source clock is divided by 7 */
+#define RCC_CFG2_ADC1MPRES_DIV8 ((uint32_t)0x00007000) /*!< ADC1M source clock is divided by 8 */
+#define RCC_CFG2_ADC1MPRES_DIV9 ((uint32_t)0x00008000) /*!< ADC1M source clock is divided by 9 */
+#define RCC_CFG2_ADC1MPRES_DIV10 ((uint32_t)0x00009000) /*!< ADC1M source clock is divided by 10 */
+#define RCC_CFG2_ADC1MPRES_DIV11 ((uint32_t)0x0000A000) /*!< ADC1M source clock is divided by 11 */
+#define RCC_CFG2_ADC1MPRES_DIV12 ((uint32_t)0x0000B000) /*!< ADC1M source clock is divided by 12 */
+#define RCC_CFG2_ADC1MPRES_DIV13 ((uint32_t)0x0000C000) /*!< ADC1M source clock is divided by 13 */
+#define RCC_CFG2_ADC1MPRES_DIV14 ((uint32_t)0x0000D000) /*!< ADC1M source clock is divided by 14 */
+#define RCC_CFG2_ADC1MPRES_DIV15 ((uint32_t)0x0000E000) /*!< ADC1M source clock is divided by 15 */
+#define RCC_CFG2_ADC1MPRES_DIV16 ((uint32_t)0x0000F000) /*!< ADC1M source clock is divided by 16 */
+#define RCC_CFG2_ADC1MPRES_DIV17 ((uint32_t)0x00010000) /*!< ADC1M source clock is divided by 17 */
+#define RCC_CFG2_ADC1MPRES_DIV18 ((uint32_t)0x00011000) /*!< ADC1M source clock is divided by 18 */
+#define RCC_CFG2_ADC1MPRES_DIV19 ((uint32_t)0x00012000) /*!< ADC1M source clock is divided by 19 */
+#define RCC_CFG2_ADC1MPRES_DIV20 ((uint32_t)0x00013000) /*!< ADC1M source clock is divided by 20 */
+#define RCC_CFG2_ADC1MPRES_DIV21 ((uint32_t)0x00014000) /*!< ADC1M source clock is divided by 21 */
+#define RCC_CFG2_ADC1MPRES_DIV22 ((uint32_t)0x00015000) /*!< ADC1M source clock is divided by 22 */
+#define RCC_CFG2_ADC1MPRES_DIV23 ((uint32_t)0x00016000) /*!< ADC1M source clock is divided by 23 */
+#define RCC_CFG2_ADC1MPRES_DIV24 ((uint32_t)0x00017000) /*!< ADC1M source clock is divided by 24 */
+#define RCC_CFG2_ADC1MPRES_DIV25 ((uint32_t)0x00018000) /*!< ADC1M source clock is divided by 25 */
+#define RCC_CFG2_ADC1MPRES_DIV26 ((uint32_t)0x00019000) /*!< ADC1M source clock is divided by 26 */
+#define RCC_CFG2_ADC1MPRES_DIV27 ((uint32_t)0x0001A000) /*!< ADC1M source clock is divided by 27 */
+#define RCC_CFG2_ADC1MPRES_DIV28 ((uint32_t)0x0001B000) /*!< ADC1M source clock is divided by 28 */
+#define RCC_CFG2_ADC1MPRES_DIV29 ((uint32_t)0x0001C000) /*!< ADC1M source clock is divided by 29 */
+#define RCC_CFG2_ADC1MPRES_DIV30 ((uint32_t)0x0001D000) /*!< ADC1M source clock is divided by 30 */
+#define RCC_CFG2_ADC1MPRES_DIV31 ((uint32_t)0x0001E000) /*!< ADC1M source clock is divided by 31 */
+#define RCC_CFG2_ADC1MPRES_DIV32 ((uint32_t)0x0001F000) /*!< ADC1M source clock is divided by 32 */
+
+/*!< ADC1MSEL configuration */
+#define RCC_CFG2_ADC1MSEL ((uint32_t)0x00020000) /*!< ADC1M clock source select */
+
+#define RCC_CFG2_ADC1MSEL_HSI ((uint32_t)0x00000000) /*!< HSI clock selected as ADC1M input clock */
+#define RCC_CFG2_ADC1MSEL_HSE ((uint32_t)0x00020000) /*!< HSE clock selected as ADC1M input clock */
+
+/*!< RNGCPRE configuration */
+#define RCC_CFG2_RNGCPRES ((uint32_t)0x1F000000) /*!< RNGCPRE[4:0] bits */
+#define RCC_CFG2_RNGCPRES_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define RCC_CFG2_RNGCPRES_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define RCC_CFG2_RNGCPRES_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define RCC_CFG2_RNGCPRES_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define RCC_CFG2_RNGCPRES_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+
+#define RCC_CFG2_RNGCPRES_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK source clock is divided by 1 */
+#define RCC_CFG2_RNGCPRES_DIV2 ((uint32_t)0x01000000) /*!< SYSCLK source clock is divided by 2 */
+#define RCC_CFG2_RNGCPRES_DIV3 ((uint32_t)0x02000000) /*!< SYSCLK source clock is divided by 3 */
+#define RCC_CFG2_RNGCPRES_DIV4 ((uint32_t)0x03000000) /*!< SYSCLK source clock is divided by 4 */
+#define RCC_CFG2_RNGCPRES_DIV5 ((uint32_t)0x04000000) /*!< SYSCLK source clock is divided by 5 */
+#define RCC_CFG2_RNGCPRES_DIV6 ((uint32_t)0x05000000) /*!< SYSCLK source clock is divided by 6 */
+#define RCC_CFG2_RNGCPRES_DIV7 ((uint32_t)0x06000000) /*!< SYSCLK source clock is divided by 7 */
+#define RCC_CFG2_RNGCPRES_DIV8 ((uint32_t)0x07000000) /*!< SYSCLK source clock is divided by 8 */
+#define RCC_CFG2_RNGCPRES_DIV9 ((uint32_t)0x08000000) /*!< SYSCLK source clock is divided by 9 */
+#define RCC_CFG2_RNGCPRES_DIV10 ((uint32_t)0x09000000) /*!< SYSCLK source clock is divided by 10 */
+#define RCC_CFG2_RNGCPRES_DIV11 ((uint32_t)0x0A000000) /*!< SYSCLK source clock is divided by 11 */
+#define RCC_CFG2_RNGCPRES_DIV12 ((uint32_t)0x0B000000) /*!< SYSCLK source clock is divided by 12 */
+#define RCC_CFG2_RNGCPRES_DIV13 ((uint32_t)0x0C000000) /*!< SYSCLK source clock is divided by 13 */
+#define RCC_CFG2_RNGCPRES_DIV14 ((uint32_t)0x0D000000) /*!< SYSCLK source clock is divided by 14 */
+#define RCC_CFG2_RNGCPRES_DIV15 ((uint32_t)0x0E000000) /*!< SYSCLK source clock is divided by 15 */
+#define RCC_CFG2_RNGCPRES_DIV16 ((uint32_t)0x0F000000) /*!< SYSCLK source clock is divided by 16 */
+#define RCC_CFG2_RNGCPRES_DIV17 ((uint32_t)0x10000000) /*!< SYSCLK source clock is divided by 17 */
+#define RCC_CFG2_RNGCPRES_DIV18 ((uint32_t)0x11000000) /*!< SYSCLK source clock is divided by 18 */
+#define RCC_CFG2_RNGCPRES_DIV19 ((uint32_t)0x12000000) /*!< SYSCLK source clock is divided by 19 */
+#define RCC_CFG2_RNGCPRES_DIV20 ((uint32_t)0x13000000) /*!< SYSCLK source clock is divided by 20 */
+#define RCC_CFG2_RNGCPRES_DIV21 ((uint32_t)0x14000000) /*!< SYSCLK source clock is divided by 21 */
+#define RCC_CFG2_RNGCPRES_DIV22 ((uint32_t)0x15000000) /*!< SYSCLK source clock is divided by 22 */
+#define RCC_CFG2_RNGCPRES_DIV23 ((uint32_t)0x16000000) /*!< SYSCLK source clock is divided by 23 */
+#define RCC_CFG2_RNGCPRES_DIV24 ((uint32_t)0x17000000) /*!< SYSCLK source clock is divided by 24 */
+#define RCC_CFG2_RNGCPRES_DIV25 ((uint32_t)0x18000000) /*!< SYSCLK source clock is divided by 25 */
+#define RCC_CFG2_RNGCPRES_DIV26 ((uint32_t)0x19000000) /*!< SYSCLK source clock is divided by 26 */
+#define RCC_CFG2_RNGCPRES_DIV27 ((uint32_t)0x1A000000) /*!< SYSCLK source clock is divided by 27 */
+#define RCC_CFG2_RNGCPRES_DIV28 ((uint32_t)0x1B000000) /*!< SYSCLK source clock is divided by 28 */
+#define RCC_CFG2_RNGCPRES_DIV29 ((uint32_t)0x1C000000) /*!< SYSCLK source clock is divided by 29 */
+#define RCC_CFG2_RNGCPRES_DIV30 ((uint32_t)0x1D000000) /*!< SYSCLK source clock is divided by 30 */
+#define RCC_CFG2_RNGCPRES_DIV31 ((uint32_t)0x1E000000) /*!< SYSCLK source clock is divided by 31 */
+#define RCC_CFG2_RNGCPRES_DIV32 ((uint32_t)0x1F000000) /*!< SYSCLK source clock is divided by 32 */
+
+/*!< TIMCLK_SEL configuration */
+#define RCC_CFG2_TIMCLKSEL ((uint32_t)0x20000000) /*!< Timer1/8 clock source select */
+
+#define RCC_CFG2_TIMCLKSEL_TIM18CLK ((uint32_t)0x00000000) /*!< Timer1/8 clock selected as tim1/8_clk input clock */
+#define RCC_CFG2_TIMCLKSEL_SYSCLK ((uint32_t)0x20000000) /*!< Timer1/8 clock selected as sysclk input clock */
+
+/******************* Bit definition for RCC_CFG3 register ******************/
+/*!< UCDREN configuration */
+#define RCC_CFG3_UCDREN ((uint32_t)0x00000080) /*!< UCDR enable */
+
+#define RCC_CFG3_UCDREN_ENABLE ((uint32_t)0x00000080) /*!< UCDREN enable */
+#define RCC_CFG3_UCDREN_DISABLE ((uint32_t)0x00000000) /*!< UCDREN disable */
+
+/*!< USBXTALESS configuration */
+#define RCC_CFG3_USBXTALESS ((uint32_t)0x00000100) /*!< UCDR enable */
+
+#define RCC_CFG3_USBXTALESS_LESSMODE ((uint32_t)0x00000100) /*!< USB Crystalless mode */
+#define RCC_CFG3_USBXTALESS_MODE ((uint32_t)0x00000000) /*!< USB Crystal mode */
+
+/*!< UCDR300MSEL configuration */
+#define RCC_CFG3_UCDR300MSEL ((uint32_t)0x00000200) /*!< UCDR 300M Clock source */
+
+#define RCC_CFG3_UCDR300MSEL_PLLVCO ((uint32_t)0x00000200) /*!< PLL VCO selected as UCDR 300M Clock source */
+#define RCC_CFG3_UCDR300MSEL_OSC300M ((uint32_t)0x00000000) /*!< OSC300M selected as UCDR 300M Clock source */
+
+/*!< TRNG1MPRE configuration */
+#define RCC_CFG3_TRNG1MPRES ((uint32_t)0x0000F800) /*!< TRNG1MPRE[4:0] bits */
+#define RCC_CFG3_TRNG1MPRES_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define RCC_CFG3_TRNG1MPRES_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+#define RCC_CFG3_TRNG1MPRES_2 ((uint32_t)0x00002000) /*!< Bit 2 */
+#define RCC_CFG3_TRNG1MPRES_3 ((uint32_t)0x00004000) /*!< Bit 3 */
+#define RCC_CFG3_TRNG1MPRES_4 ((uint32_t)0x00008000) /*!< Bit 4 */
+
+#define RCC_CFG3_TRNG1MPRES_VAL2 ((uint32_t)0x00000800) /*!< TRNG 1M source clock is divided by 2 */
+#define RCC_CFG3_TRNG1MPRES_VAL3 ((uint32_t)0x00001000) /*!< TRNG 1M source clock is divided by 4 */
+#define RCC_CFG3_TRNG1MPRES_VAL4 ((uint32_t)0x00001800) /*!< TRNG 1M source clock is divided by 6 */
+#define RCC_CFG3_TRNG1MPRES_VAL5 ((uint32_t)0x00002000) /*!< TRNG 1M source clock is divided by 8 */
+#define RCC_CFG3_TRNG1MPRES_VAL6 ((uint32_t)0x00002800) /*!< TRNG 1M source clock is divided by 10 */
+#define RCC_CFG3_TRNG1MPRES_VAL7 ((uint32_t)0x00003000) /*!< TRNG 1M source clock is divided by 12 */
+#define RCC_CFG3_TRNG1MPRES_VAL8 ((uint32_t)0x00003800) /*!< TRNG 1M source clock is divided by 14 */
+#define RCC_CFG3_TRNG1MPRES_VAL9 ((uint32_t)0x00004000) /*!< TRNG 1M source clock is divided by 16 */
+#define RCC_CFG3_TRNG1MPRES_VAL10 ((uint32_t)0x00004800) /*!< TRNG 1M source clock is divided by 18 */
+#define RCC_CFG3_TRNG1MPRES_VAL11 ((uint32_t)0x00005000) /*!< TRNG 1M source clock is divided by 20 */
+#define RCC_CFG3_TRNG1MPRES_VAL12 ((uint32_t)0x00005800) /*!< TRNG 1M source clock is divided by 22 */
+#define RCC_CFG3_TRNG1MPRES_VAL13 ((uint32_t)0x00006000) /*!< TRNG 1M source clock is divided by 24 */
+#define RCC_CFG3_TRNG1MPRES_VAL14 ((uint32_t)0x00006800) /*!< TRNG 1M source clock is divided by 26 */
+#define RCC_CFG3_TRNG1MPRES_VAL15 ((uint32_t)0x00007000) /*!< TRNG 1M source clock is divided by 28 */
+#define RCC_CFG3_TRNG1MPRES_VAL16 ((uint32_t)0x00007800) /*!< TRNG 1M source clock is divided by 30 */
+#define RCC_CFG3_TRNG1MPRES_VAL17 ((uint32_t)0x00008000) /*!< TRNG 1M source clock is divided by 32 */
+#define RCC_CFG3_TRNG1MPRES_VAL18 ((uint32_t)0x00008800) /*!< TRNG 1M source clock is divided by 34 */
+#define RCC_CFG3_TRNG1MPRES_VAL19 ((uint32_t)0x00009000) /*!< TRNG 1M source clock is divided by 36 */
+#define RCC_CFG3_TRNG1MPRES_VAL20 ((uint32_t)0x00009800) /*!< TRNG 1M source clock is divided by 38 */
+#define RCC_CFG3_TRNG1MPRES_VAL21 ((uint32_t)0x0000A000) /*!< TRNG 1M source clock is divided by 40 */
+#define RCC_CFG3_TRNG1MPRES_VAL22 ((uint32_t)0x0000A800) /*!< TRNG 1M source clock is divided by 42 */
+#define RCC_CFG3_TRNG1MPRES_VAL23 ((uint32_t)0x0000B000) /*!< TRNG 1M source clock is divided by 44 */
+#define RCC_CFG3_TRNG1MPRES_VAL24 ((uint32_t)0x0000B800) /*!< TRNG 1M source clock is divided by 46 */
+#define RCC_CFG3_TRNG1MPRES_VAL25 ((uint32_t)0x0000C000) /*!< TRNG 1M source clock is divided by 48 */
+#define RCC_CFG3_TRNG1MPRES_VAL26 ((uint32_t)0x0000C800) /*!< TRNG 1M source clock is divided by 50 */
+#define RCC_CFG3_TRNG1MPRES_VAL27 ((uint32_t)0x0000D000) /*!< TRNG 1M source clock is divided by 52 */
+#define RCC_CFG3_TRNG1MPRES_VAL28 ((uint32_t)0x0000D800) /*!< TRNG 1M source clock is divided by 54 */
+#define RCC_CFG3_TRNG1MPRES_VAL29 ((uint32_t)0x0000E000) /*!< TRNG 1M source clock is divided by 56 */
+#define RCC_CFG3_TRNG1MPRES_VAL30 ((uint32_t)0x0000E800) /*!< TRNG 1M source clock is divided by 58 */
+#define RCC_CFG3_TRNG1MPRES_VAL31 ((uint32_t)0x0000F000) /*!< TRNG 1M source clock is divided by 60 */
+#define RCC_CFG3_TRNG1MPRES_VAL32 ((uint32_t)0x0000F800) /*!< TRNG 1M source clock is divided by 62 */
+
+/*!< TRNG1MSEL configuration */
+#define RCC_CFG3_TRNG1MSEL ((uint32_t)0x00020000) /*!< TRNG_1M clock source select */
+
+#define RCC_CFG3_TRNG1MSEL_HSI ((uint32_t)0x00000000) /*!< HSI clock selected as TRNG_1M input clock */
+#define RCC_CFG3_TRNG1MSEL_HSE ((uint32_t)0x00020000) /*!< HSE clock selected as TRNG_1M input clock */
+
+/*!< TRNG1MEN configuration */
+#define RCC_CFG3_TRNG1MEN ((uint32_t)0x00040000) /*!< TRNG_1M clock enable */
+
+#define RCC_CFG3_TRNG1MEN_DISABLE ((uint32_t)0x00000000) /*!< TRNG_1M clock disable */
+#define RCC_CFG3_TRNG1MEN_ENABLE ((uint32_t)0x00040000) /*!< TRNG_1M clock enable */
+
+/******************* Bit definition for RCC_RDCTRL register ******************/
+/*!< LPTIMSEL congiguration */
+#define RCC_RDCTRL_LPTIMSEL ((uint32_t)0x00000007) /*!< LPTIMSEL[2:0] bits (LPTIM clock source selection) */
+#define RCC_RDCTRL_LPTIMSEL_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_RDCTRL_LPTIMSEL_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RCC_RDCTRL_LPTIMSEL_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define RCC_RDCTRL_LPTIMSEL_APB1 ((uint32_t)0x00000000) /*!< APB1 clock used as LPTIM clock */
+#define RCC_RDCTRL_LPTIMSEL_LSI ((uint32_t)0x00000001) /*!< LSI oscillator clock used as LPTIM clock */
+#define RCC_RDCTRL_LPTIMSEL_HSI ((uint32_t)0x00000002) /*!< HSI oscillator clock used as LPTIM clock */
+#define RCC_RDCTRL_LPTIMSEL_LSE ((uint32_t)0x00000003) /*!< LSE oscillator clock used as LPTIM clock */
+#define RCC_RDCTRL_LPTIMSEL_COMP1 ((uint32_t)0x00000004) /*!< COMP1 output used as LPTIM clock */
+#define RCC_RDCTRL_LPTIMSEL_COMP2 ((uint32_t)0x00000005) /*!< COMP1 output used as LPTIM clock */
+
+/*!< LPUARTSEL congiguration */
+#define RCC_RDCTRL_LPUARTSEL ((uint32_t)0x00000018) /*!< LPUARTSEL[1:0] bits (LPUART clock source selection) */
+#define RCC_RDCTRL_LPUARTSEL_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define RCC_RDCTRL_LPUARTSEL_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+
+#define RCC_RDCTRL_LPUARTSEL_APB1 ((uint32_t)0x00000000) /*!< APB1 clock used as LPUART clock */
+#define RCC_RDCTRL_LPUARTSEL_SYSCLK ((uint32_t)0x00000008) /*!< SYSCLK used as LPUART clock */
+#define RCC_RDCTRL_LPUARTSEL_HSI ((uint32_t)0x00000010) /*!< HSI oscillator clock used as LPUART clock */
+#define RCC_RDCTRL_LPUARTSEL_LSE ((uint32_t)0x00000018) /*!< LSE oscillator clock used as LPUART clock */
+
+#define RCC_RDCTRL_LPTIMEN ((uint32_t)0x00000040) /*!< LPTIM clock enable */
+#define RCC_RDCTRL_LPUARTEN ((uint32_t)0x00000080) /*!< LPUART clock enable */
+#define RCC_RDCTRL_LCDEN ((uint32_t)0x00000100) /*!< LCD clock enable */
+
+#define RCC_RDCTRL_LPTIMRST ((uint32_t)0x00000400) /*!< LPTIM reset */
+#define RCC_RDCTRL_LPUARTRST ((uint32_t)0x00000800) /*!< LPUART reset */
+#define RCC_RDCTRL_LCDRST ((uint32_t)0x00001000) /*!< LCD reset */
+
+
+/******************* Bit definition for RCC_PLLHSIPRE register ******************/
+/*!< PLLHSIPRE configuration */
+#define RCC_PLLHSIPRE_PLLHSIPRE ((uint32_t)0x00000001) /*!< HSI divider for PLL entry */
+
+#define RCC_PLLHSIPRE_PLLHSIPRE_HSI ((uint32_t)0x00000000) /*!< HSI clock not divided for PLL entry */
+#define RCC_PLLHSIPRE_PLLHSIPRE_HSI_DIV2 ((uint32_t)0x00000001) /*!< HSI clock divided by 2 for PLL entry */
+
+/*!< PLLSRCDIV configuration */
+#define RCC_PLLHSIPRE_PLLSRCDIV ((uint32_t)0x00000002) /*!< PLL source clock for PLL entry */
+
+#define RCC_PLLHSIPRE_PLLSRCDIV_DISABLE ((uint32_t)0x00000000) /*!< PLL source clock not divided for PLL entry */
+#define RCC_PLLHSIPRE_PLLSRCDIV_ENABLE ((uint32_t)0x00000002) /*!< PLL source clock divided by 2 for PLL entry */
+
+/******************* Bit definition for RCC_SRAM_CTRLSTS register ******************/
+#define RCC_SRAM_CTRLSTS_ERR1EN ((uint32_t)0x00000001) /*!< SRAM1 Parity Error Interrupt Enable */
+#define RCC_SRAM_CTRLSTS_ERR1RSTEN ((uint32_t)0x00000002) /*!< SRAM1 Parity Error Reset Enable */
+#define RCC_SRAM_CTRLSTS_ERR1STS ((uint32_t)0x00000004) /*!< SRAM1 Parity Error Status */
+#define RCC_SRAM_CTRLSTS_ERR2EN ((uint32_t)0x00000008) /*!< SRAM2 Parity Error Interrupt Enable */
+#define RCC_SRAM_CTRLSTS_ERR2RSTEN ((uint32_t)0x00000010) /*!< SRAM2 Parity Error Reset Enable */
+#define RCC_SRAM_CTRLSTS_ERR2STS ((uint32_t)0x00000020) /*!< SRAM2 Parity Error Status */
+
+/******************************************************************************/
+/* */
+/* SystemTick */
+/* */
+/******************************************************************************/
+
+/***************** Bit definition for SysTick_CTRL register *****************/
+#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
+#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
+#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
+#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
+
+/***************** Bit definition for SysTick_LOAD register *****************/
+#define SysTick_LOAD_RELOAD \
+ ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/***************** Bit definition for SysTick_VAL register ******************/
+#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
+
+/***************** Bit definition for SysTick_CALIB register ****************/
+#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
+#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
+#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/* */
+/* Nested Vectored Interrupt Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for NVIC_ISER register *******************/
+#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */
+#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ICER register *******************/
+#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */
+#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ISPR register *******************/
+#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */
+#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ICPR register *******************/
+#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */
+#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_IABR register *******************/
+#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */
+#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_PRI0 register *******************/
+#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
+#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
+#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
+#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
+
+/****************** Bit definition for NVIC_PRI1 register *******************/
+#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
+#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
+#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
+#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
+
+/****************** Bit definition for NVIC_PRI2 register *******************/
+#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
+#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
+#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
+#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
+
+/****************** Bit definition for NVIC_PRI3 register *******************/
+#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
+#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
+#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
+#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
+
+/****************** Bit definition for NVIC_PRI4 register *******************/
+#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
+#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
+#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
+#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
+
+/****************** Bit definition for NVIC_PRI5 register *******************/
+#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
+#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
+#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
+#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
+
+/****************** Bit definition for NVIC_PRI6 register *******************/
+#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
+#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
+#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
+#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
+
+/****************** Bit definition for NVIC_PRI7 register *******************/
+#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
+#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
+#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
+#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
+
+/****************** Bit definition for SCB_CPUID register *******************/
+#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
+#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
+#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
+#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
+#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
+
+/******************* Bit definition for SCB_ICSR register *******************/
+#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active INTSTS number field */
+#define SCB_ICSR_RETTOBASE \
+ ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending INTSTS number field */
+#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
+#define SCB_ICSR_ISRPREEMPT \
+ ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
+#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
+#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
+#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
+#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
+
+/******************* Bit definition for SCB_VTOR register *******************/
+#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
+#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
+
+/*!<***************** Bit definition for SCB_AIRCR register *******************/
+#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
+#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
+#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
+
+#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
+#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+/* prority group configuration */
+#define SCB_AIRCR_PRIGROUP0 \
+ ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define SCB_AIRCR_PRIGROUP1 \
+ ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP2 \
+ ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP3 \
+ ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP4 \
+ ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP5 \
+ ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP6 \
+ ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP7 \
+ ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
+#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/******************* Bit definition for SCB_SCR register ********************/
+#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */
+#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */
+#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */
+
+/******************** Bit definition for SCB_CCR register *******************/
+#define SCB_CCR_NONBASETHRDENA \
+ ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define SCB_CCR_USERSETMPEND \
+ ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a \
+ Main exception */
+#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */
+#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */
+#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */
+#define SCB_CCR_STKALIGN \
+ ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/******************* Bit definition for SCB_SHPR register ********************/
+#define SCB_SHPR_PRI_N \
+ ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define SCB_SHPR_PRI_N1 \
+ ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define SCB_SHPR_PRI_N2 \
+ ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define SCB_SHPR_PRI_N3 \
+ ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/****************** Bit definition for SCB_SHCSR register *******************/
+#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
+#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
+#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
+#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
+#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
+#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
+#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
+#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
+#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
+#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
+#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
+#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
+#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
+#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
+
+/******************* Bit definition for SCB_CFSR register *******************/
+/*!< MFSR */
+#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */
+#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */
+#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */
+#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */
+#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED \
+ ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO \
+ ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/******************* Bit definition for SCB_HFSR register *******************/
+#define SCB_HFSR_VECTTBL \
+ ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
+#define SCB_HFSR_FORCED \
+ ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
+
+/******************* Bit definition for SCB_DFSR register *******************/
+#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */
+#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */
+#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */
+#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */
+#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */
+
+/******************* Bit definition for SCB_MMFAR register ******************/
+#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */
+
+/******************* Bit definition for SCB_BFAR register *******************/
+#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */
+
+/******************* Bit definition for SCB_afsr register *******************/
+#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */
+
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_INTSTS register ********************/
+#define DMA_INTSTS_GLBF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
+#define DMA_INTSTS_TXCF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
+#define DMA_INTSTS_HTXF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
+#define DMA_INTSTS_ERRF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
+#define DMA_INTSTS_GLBF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
+#define DMA_INTSTS_TXCF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
+#define DMA_INTSTS_HTXF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
+#define DMA_INTSTS_ERRF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
+#define DMA_INTSTS_GLBF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
+#define DMA_INTSTS_TXCF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
+#define DMA_INTSTS_HTXF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
+#define DMA_INTSTS_ERRF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
+#define DMA_INTSTS_GLBF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
+#define DMA_INTSTS_TXCF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
+#define DMA_INTSTS_HTXF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
+#define DMA_INTSTS_ERRF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
+#define DMA_INTSTS_GLBF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
+#define DMA_INTSTS_TXCF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
+#define DMA_INTSTS_HTXF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
+#define DMA_INTSTS_ERRF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
+#define DMA_INTSTS_GLBF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
+#define DMA_INTSTS_TXCF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
+#define DMA_INTSTS_HTXF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
+#define DMA_INTSTS_ERRF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
+#define DMA_INTSTS_GLBF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
+#define DMA_INTSTS_TXCF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
+#define DMA_INTSTS_HTXF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
+#define DMA_INTSTS_ERRF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
+#define DMA_INTSTS_GLBF8 ((uint32_t)0x10000000) /*!< Channel 7 Global interrupt flag */
+#define DMA_INTSTS_TXCF8 ((uint32_t)0x20000000) /*!< Channel 7 Transfer Complete flag */
+#define DMA_INTSTS_HTXF8 ((uint32_t)0x40000000) /*!< Channel 7 Half Transfer flag */
+#define DMA_INTSTS_ERRF8 ((uint32_t)0x80000000) /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_INTCLR register *******************/
+#define DMA_INTCLR_CGLBF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
+#define DMA_INTCLR_CTXCF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
+#define DMA_INTCLR_CERRF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
+#define DMA_INTCLR_CGLBF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
+#define DMA_INTCLR_CTXCF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
+#define DMA_INTCLR_CERRF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
+#define DMA_INTCLR_CGLBF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
+#define DMA_INTCLR_CTXCF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
+#define DMA_INTCLR_CERRF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
+#define DMA_INTCLR_CGLBF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
+#define DMA_INTCLR_CTXCF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
+#define DMA_INTCLR_CERRF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
+#define DMA_INTCLR_CGLBF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
+#define DMA_INTCLR_CTXCF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
+#define DMA_INTCLR_CERRF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
+#define DMA_INTCLR_CGLBF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
+#define DMA_INTCLR_CTXCF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
+#define DMA_INTCLR_CERRF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
+#define DMA_INTCLR_CGLBF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
+#define DMA_INTCLR_CTXCF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
+#define DMA_INTCLR_CERRF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
+#define DMA_INTCLR_CGLBF8 ((uint32_t)0x10000000) /*!< Channel 7 Global interrupt clear */
+#define DMA_INTCLR_CTXCF8 ((uint32_t)0x20000000) /*!< Channel 7 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF8 ((uint32_t)0x40000000) /*!< Channel 7 Half Transfer clear */
+#define DMA_INTCLR_CERRF8 ((uint32_t)0x80000000) /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CHCFG1 register *******************/
+#define DMA_CHCFG1_CHEN ((uint16_t)0x0001) /*!< Channel enable*/
+#define DMA_CHCFG1_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG1_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG1_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG1_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CHCFG1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CHCFG1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG1_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */
+#define DMA_CHCFG1_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG1_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/******************* Bit definition for DMA_CHCFG2 register *******************/
+#define DMA_CHCFG2_CHEN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CHCFG2_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG2_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG2_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG2_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CHCFG2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CHCFG2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG2_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CHCFG2_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG2_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/******************* Bit definition for DMA_CHCFG3 register *******************/
+#define DMA_CHCFG3_CHEN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CHCFG3_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG3_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG3_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG3_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CHCFG3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CHCFG3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG3_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CHCFG3_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG3_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/*!<****************** Bit definition for DMA_CHCFG4 register *******************/
+#define DMA_CHCFG4_CHEN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CHCFG4_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG4_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG4_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG4_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CHCFG4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CHCFG4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG4_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CHCFG4_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG4_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CHCFG5 register *******************/
+#define DMA_CHCFG5_CHEN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CHCFG5_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG5_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG5_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG5_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CHCFG5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CHCFG5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG5_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CHCFG5_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG5_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
+
+/******************* Bit definition for DMA_CHCFG6 register *******************/
+#define DMA_CHCFG6_CHEN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CHCFG6_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG6_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG6_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG6_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CHCFG6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CHCFG6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG6_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CHCFG6_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG6_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/******************* Bit definition for DMA_CHCFG7 register *******************/
+#define DMA_CHCFG7_CHEN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CHCFG7_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG7_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG7_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG7_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG7_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CHCFG7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CHCFG7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG7_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CHCFG7_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG7_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
+
+/******************* Bit definition for DMA_CHCFG8 register *******************/
+#define DMA_CHCFG8_CHEN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CHCFG8_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG8_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG8_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG8_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG8_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG8_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG8_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG8_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG8_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CHCFG8_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CHCFG8_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG8_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG8_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG8_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CHCFG8_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG8_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG8_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
+
+/****************** Bit definition for DMA_TXNUM1 register ******************/
+#define DMA_TXNUM1_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_TXNUM2 register ******************/
+#define DMA_TXNUM2_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_TXNUM3 register ******************/
+#define DMA_TXNUM3_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_TXNUM4 register ******************/
+#define DMA_TXNUM4_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_TXNUM5 register ******************/
+#define DMA_TXNUM5_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_TXNUM6 register ******************/
+#define DMA_TXNUM6_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_TXNUM7 register ******************/
+#define DMA_TXNUM7_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_TXNUM8 register ******************/
+#define DMA_TXNUM8_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_PADDR1 register *******************/
+#define DMA_PADDR1_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_PADDR2 register *******************/
+#define DMA_PADDR2_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_PADDR3 register *******************/
+#define DMA_PADDR3_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_PADDR4 register *******************/
+#define DMA_PADDR4_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_PADDR5 register *******************/
+#define DMA_PADDR5_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_PADDR6 register *******************/
+#define DMA_PADDR6_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_PADDR7 register *******************/
+#define DMA_PADDR7_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_PADDR8 register *******************/
+#define DMA_PADDR8_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_MADDR1 register *******************/
+#define DMA_MADDR1_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_MADDR2 register *******************/
+#define DMA_MADDR2_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_MADDR3 register *******************/
+#define DMA_MADDR3_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_MADDR4 register *******************/
+#define DMA_MADDR4_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_MADDR5 register *******************/
+#define DMA_MADDR5_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_MADDR6 register *******************/
+#define DMA_MADDR6_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_MADDR7 register *******************/
+#define DMA_MADDR7_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_MADDR8 register *******************/
+#define DMA_MADDR8_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for ADC_STS register ********************/
+#define ADC_STS_AWDG ((uint8_t)0x01) /*!< Analog watchdog flag */
+#define ADC_STS_ENDC ((uint8_t)0x02) /*!< End of conversion */
+#define ADC_STS_JENDC ((uint8_t)0x04) /*!< Injected channel end of conversion */
+#define ADC_STS_JSTR ((uint8_t)0x08) /*!< Injected channel Start flag */
+#define ADC_STS_STR ((uint8_t)0x10) /*!< Regular channel Start flag */
+#define ADC_STS_ENDCA ((uint8_t)0x20) /*!< Regular channel any end flag */
+#define ADC_STS_JENDCA ((uint8_t)0x40) /*!< Injected channel any end flag */
+
+
+/******************* Bit definition for ADC_CTRL1 register ********************/
+#define ADC_CTRL1_AWDGCH ((uint32_t)0x0000001F) /*!< AWDG_CH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CTRL1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_CTRL1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_CTRL1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_CTRL1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_CTRL1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_CTRL1_ENDCIEN ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */
+#define ADC_CTRL1_AWDGIEN ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */
+#define ADC_CTRL1_JENDCIEN ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */
+#define ADC_CTRL1_SCANMD ((uint32_t)0x00000100) /*!< Scan mode */
+#define ADC_CTRL1_AWDGSGLEN ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */
+#define ADC_CTRL1_AUTOJC ((uint32_t)0x00000400) /*!< Automatic injected group conversion */
+#define ADC_CTRL1_DREGCH ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */
+#define ADC_CTRL1_DJCH ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */
+
+#define ADC_CTRL1_DCTU ((uint32_t)0x0000E000) /*!< DISC_NUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CTRL1_DCTU_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define ADC_CTRL1_DCTU_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define ADC_CTRL1_DCTU_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+
+#define ADC_CTRL1_AWDGEJCH ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */
+#define ADC_CTRL1_AWDGERCH ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
+
+/******************* Bit definition for ADC_CTRL2 register ********************/
+#define ADC_CTRL2_ON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */
+#define ADC_CTRL2_CTU ((uint32_t)0x00000002) /*!< Continuous Conversion */
+#define ADC_CTRL2_ENCAL ((uint32_t)0x00000004) /*!< A/D Calibration */
+#define ADC_CTRL2_ENDMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */
+#define ADC_CTRL2_ALIG ((uint32_t)0x00000800) /*!< Data Alignment */
+
+#define ADC_CTRL2_EXTJSEL \
+ ((uint32_t)0x00007000) /*!< INJ_EXT_SEL[2:0] bits (External event select for injected group) */
+#define ADC_CTRL2_EXTJSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_CTRL2_EXTJSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_CTRL2_EXTJSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_CTRL2_EXTJTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */
+
+#define ADC_CTRL2_EXTRSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CTRL2_EXTRSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define ADC_CTRL2_EXTRSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define ADC_CTRL2_EXTRSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+
+#define ADC_CTRL2_EXTRTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */
+#define ADC_CTRL2_SWSTRJCH ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */
+#define ADC_CTRL2_SWSTRRCH ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */
+#define ADC_CTRL2_TEMPEN ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */
+
+/****************** Bit definition for ADC_SAMPT1 register *******************/
+#define ADC_SAMPT1_SAMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SAMPT1_SAMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define ADC_SAMPT1_SAMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SAMPT1_SAMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define ADC_SAMPT1_SAMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SAMPT1_SAMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+
+#define ADC_SAMPT1_SAMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SAMPT1_SAMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+
+#define ADC_SAMPT1_SAMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SAMPT1_SAMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_SAMPT1_SAMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SAMPT1_SAMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+
+#define ADC_SAMPT1_SAMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SAMPT1_SAMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+
+#define ADC_SAMPT1_SAMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SAMPT1_SAMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+
+/****************** Bit definition for ADC_SAMPT2 register *******************/
+#define ADC_SAMPT2_SAMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SAMPT2_SAMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SAMPT2_SAMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SAMPT2_SAMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SAMPT2_SAMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SAMPT2_SAMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SAMPT2_SAMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SAMPT2_SAMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SAMPT2_SAMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SAMPT2_SAMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SAMPT2_SAMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */
+
+/****************** Bit definition for ADC_JOFFSET1 register *******************/
+#define ADC_JOFFSET1_OFFSETJCH1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFFSET2 register *******************/
+#define ADC_JOFFSET2_OFFSETJCH2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFFSET3 register *******************/
+#define ADC_JOFFSET3_OFFSETJCH3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFFSET4 register *******************/
+#define ADC_JOFFSET4_OFFSETJCH4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_WDGHIGH register ********************/
+#define ADC_WDGHIGH_HTH ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_WDGLOW register ********************/
+#define ADC_WDGLOW_LTH ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_RSEQ1 register *******************/
+#define ADC_RSEQ1_SEQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_RSEQ1_SEQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_RSEQ1_SEQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_RSEQ1_SEQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_RSEQ1_SEQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_RSEQ1_SEQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_RSEQ1_SEQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_RSEQ1_SEQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_RSEQ1_SEQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_RSEQ1_SEQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_RSEQ1_SEQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_RSEQ1_SEQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_RSEQ1_SEQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_RSEQ1_SEQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_RSEQ1_SEQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_RSEQ1_SEQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_RSEQ1_SEQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_RSEQ1_SEQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_RSEQ1_SEQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_RSEQ1_SEQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_RSEQ1_SEQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_RSEQ1_SEQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_RSEQ1_SEQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_RSEQ1_SEQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_RSEQ1_LEN ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */
+#define ADC_RSEQ1_LEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_RSEQ1_LEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_RSEQ1_LEN_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_RSEQ1_LEN_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+/******************* Bit definition for ADC_RSEQ2 register *******************/
+#define ADC_RSEQ2_SEQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_RSEQ2_SEQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_RSEQ2_SEQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_RSEQ2_SEQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_RSEQ2_SEQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_RSEQ2_SEQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_RSEQ2_SEQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_RSEQ2_SEQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_RSEQ2_SEQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_RSEQ2_SEQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_RSEQ2_SEQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_RSEQ2_SEQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_RSEQ2_SEQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_RSEQ2_SEQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_RSEQ2_SEQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_RSEQ2_SEQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_RSEQ2_SEQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_RSEQ2_SEQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_RSEQ2_SEQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_RSEQ2_SEQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_RSEQ2_SEQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_RSEQ2_SEQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_RSEQ2_SEQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_RSEQ2_SEQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_RSEQ2_SEQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_RSEQ2_SEQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_RSEQ2_SEQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_RSEQ2_SEQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_RSEQ2_SEQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+#define ADC_RSEQ2_SEQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */
+
+#define ADC_RSEQ2_SEQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_RSEQ2_SEQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */
+#define ADC_RSEQ2_SEQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define ADC_RSEQ2_SEQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */
+#define ADC_RSEQ2_SEQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */
+#define ADC_RSEQ2_SEQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */
+
+/******************* Bit definition for ADC_RSEQ3 register *******************/
+#define ADC_RSEQ3_SEQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_RSEQ3_SEQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_RSEQ3_SEQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_RSEQ3_SEQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_RSEQ3_SEQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_RSEQ3_SEQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_RSEQ3_SEQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_RSEQ3_SEQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_RSEQ3_SEQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_RSEQ3_SEQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_RSEQ3_SEQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_RSEQ3_SEQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_RSEQ3_SEQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_RSEQ3_SEQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_RSEQ3_SEQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_RSEQ3_SEQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_RSEQ3_SEQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_RSEQ3_SEQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_RSEQ3_SEQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_RSEQ3_SEQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_RSEQ3_SEQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_RSEQ3_SEQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_RSEQ3_SEQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_RSEQ3_SEQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_RSEQ3_SEQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_RSEQ3_SEQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_RSEQ3_SEQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_RSEQ3_SEQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_RSEQ3_SEQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+#define ADC_RSEQ3_SEQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */
+
+#define ADC_RSEQ3_SEQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_RSEQ3_SEQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */
+#define ADC_RSEQ3_SEQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define ADC_RSEQ3_SEQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */
+#define ADC_RSEQ3_SEQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */
+#define ADC_RSEQ3_SEQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */
+
+/******************* Bit definition for ADC_JSEQ register *******************/
+#define ADC_JSEQ_JSEQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSEQ_JSEQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_JSEQ_JSEQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_JSEQ_JSEQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_JSEQ_JSEQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_JSEQ_JSEQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_JSEQ_JSEQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSEQ_JSEQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_JSEQ_JSEQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_JSEQ_JSEQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_JSEQ_JSEQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_JSEQ_JSEQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_JSEQ_JSEQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSEQ_JSEQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_JSEQ_JSEQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_JSEQ_JSEQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_JSEQ_JSEQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_JSEQ_JSEQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_JSEQ_JSEQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSEQ_JSEQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_JSEQ_JSEQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_JSEQ_JSEQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_JSEQ_JSEQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_JSEQ_JSEQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_JSEQ_JLEN ((uint32_t)0x00300000) /*!< INJ_LEN[1:0] bits (Injected Sequence length) */
+#define ADC_JSEQ_JLEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_JSEQ_JLEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+/******************* Bit definition for ADC_JDAT1 register *******************/
+#define ADC_JDAT1_JDAT ((uint16_t)0xFFFF) /*!< Injected data */
+
+/******************* Bit definition for ADC_JDAT2 register *******************/
+#define ADC_JDAT2_JDAT ((uint16_t)0xFFFF) /*!< Injected data */
+
+/******************* Bit definition for ADC_JDAT3 register *******************/
+#define ADC_JDAT3_JDAT ((uint16_t)0xFFFF) /*!< Injected data */
+
+/******************* Bit definition for ADC_JDAT4 register *******************/
+#define ADC_JDAT4_JDAT ((uint16_t)0xFFFF) /*!< Injected data */
+
+/******************** Bit definition for ADC_DAT register ********************/
+#define ADC_DAT_DAT ((uint32_t)0x0000FFFF) /*!< Regular data */
+
+///******************** Bit definition for ADC_DIFSEL register ********************/
+//#define ADC_DIFSEL_DIFSEL ((uint32_t)0x000FFFFE) /*!< Differential data */
+//#define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000002) /*!< Differential_1 data */
+//#define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000004) /*!< Differential_2 data */
+//#define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000008) /*!< Differential_3 data */
+//#define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000010) /*!< Differential_4 data */
+//#define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000020) /*!< Differential_5 data */
+//#define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000040) /*!< Differential_6 data */
+//#define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000080) /*!< Differential_7 data */
+//#define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000100) /*!< Differential_8 data */
+//#define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000200) /*!< Differential_9 data */
+//#define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000400) /*!< Differential_10 data */
+//#define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000800) /*!< Differential_11 data */
+//#define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00001000) /*!< Differential_12 data */
+//#define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00002000) /*!< Differential_13 data */
+//#define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00004000) /*!< Differential_14 data */
+//#define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00008000) /*!< Differential_15 data */
+//#define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00010000) /*!< Differential_16 data */
+//#define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00020000) /*!< Differential_17 data */
+//#define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00040000) /*!< Differential_18 data */
+//#define ADC_DIFSEL_DIFSEL_18 ((uint32_t)0x00080000) /*!< Differential_19 data */
+
+///******************** Bit definition for ADC_CALFACT register ********************/
+//#define ADC_CALFACT_CALFACTS ((uint32_t)0x0000007F) /*!< Calibration factors in single data */
+//#define ADC_CALFACT_CALFACTS_0 ((uint32_t)0x00000001) /*!< Calibration factors_0 in single data */
+//#define ADC_CALFACT_CALFACTS_1 ((uint32_t)0x00000002) /*!< Calibration factors_1 in single data */
+//#define ADC_CALFACT_CALFACTS_2 ((uint32_t)0x00000004) /*!< Calibration factors_2 in single data */
+//#define ADC_CALFACT_CALFACTS_3 ((uint32_t)0x00000008) /*!< Calibration factors_3 in single data */
+//#define ADC_CALFACT_CALFACTS_4 ((uint32_t)0x00000010) /*!< Calibration factors_4 in single data */
+//#define ADC_CALFACT_CALFACTS_5 ((uint32_t)0x00000020) /*!< Calibration factors_5 in single data */
+//#define ADC_CALFACT_CALFACTS_6 ((uint32_t)0x00000040) /*!< Calibration factors_6 in single data */
+
+//#define ADC_CALFACT_CALFACTD ((uint32_t)0x007F0000) /*!< Calibration factors in differential data */
+//#define ADC_CALFACT_CALFACTD_0 ((uint32_t)0x00010000) /*!< Calibration factors_0 in differential data */
+//#define ADC_CALFACT_CALFACTD_1 ((uint32_t)0x00020000) /*!< Calibration factors_1 in differential data */
+//#define ADC_CALFACT_CALFACTD_2 ((uint32_t)0x00040000) /*!< Calibration factors_2 in differential data */
+//#define ADC_CALFACT_CALFACTD_3 ((uint32_t)0x00080000) /*!< Calibration factors_3 in differential data */
+//#define ADC_CALFACT_CALFACTD_4 ((uint32_t)0x00100000) /*!< Calibration factors_4 in differential data */
+//#define ADC_CALFACT_CALFACTD_5 ((uint32_t)0x00200000) /*!< Calibration factors_5 in differential data */
+//#define ADC_CALFACT_CALFACTD_6 ((uint32_t)0x00400000) /*!< Calibration factors_6 in differential data */
+
+///******************** Bit definition for ADC_CTRL3 register ********************/
+//#define ADC_CTRL3_RES ((uint32_t)0x00000003) /*!< Resolution data */
+//#define ADC_CTRL3_RES_0 ((uint32_t)0x00000001) /*!< Resolution_0 data */
+//#define ADC_CTRL3_RES_1 ((uint32_t)0x00000002) /*!< Resolution_1 data */
+
+//#define ADC_CTRL3_CALDIF ((uint32_t)0x00000004) /*!< Differential mode for calibration enable */
+//#define ADC_CTRL3_CALALD ((uint32_t)0x00000008) /*!< Differential mode for calibration auto reload enable */
+//#define ADC_CTRL3_CKMOD ((uint32_t)0x00000010) /*!< Clock mode selection */
+//#define ADC_CTRL3_RDY ((uint32_t)0x00000020) /*!< Ready flag */
+//#define ADC_CTRL3_PDRDY ((uint32_t)0x00000040) /*!< Powerdown ready flag */
+//#define ADC_CTRL3_BPCAL ((uint32_t)0x00000080) /*!< Bypass calibration */
+//#define ADC_CTRL3_ENDCAIEN ((uint32_t)0x00000100) /*!< Interrupt enable for any regular channels */
+//#define ADC_CTRL3_JENDCAIEN ((uint32_t)0x00000200) /*!< Interrupt enable for any injected channels */
+//#define ADC_CTRL3_DPWMOD ((uint32_t)0x00000400) /*!< Deep Power Mode */
+//#define ADC_CTRL3_VBATMEN ((uint32_t)0x00000800) /*!< Vbat monitor enable */
+
+///******************** Bit definition for ADC_SAMPT3 register ********************/
+//#define ADC_SAMPT3_SAMP18 ((uint32_t)0x00000007) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
+//#define ADC_SAMPT3_SAMP18_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+//#define ADC_SAMPT3_SAMP18_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+//#define ADC_SAMPT3_SAMP18_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+//#define ADC_SAMPT3_SAMPSEL ((uint32_t)0x00000008) /*!< Sample time selection */
+
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DAC_CTRL register ********************/
+#define DAC_CTRL_CHEN ((uint32_t)0x00000001) /*!< DAC channel enable */
+#define DAC_CTRL_BEN ((uint32_t)0x00000002) /*!< DAC channel output buffer enable */
+#define DAC_CTRL_TEN ((uint32_t)0x00000004) /*!< DAC channel Trigger enable */
+
+#define DAC_CTRL_TSEL ((uint32_t)0x00000038) /*!< TSEL[2:0] (DAC channel Trigger selection) */
+#define DAC_CTRL_TSEL_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define DAC_CTRL_TSEL_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define DAC_CTRL_TSEL_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define DAC_CTRL_WEN ((uint32_t)0x000000C0) /*!< WEN[1:0] (DAC channel noise/triangle wave generation enable) */
+#define DAC_CTRL_WEN_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define DAC_CTRL_WEN_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define DAC_CTRL_MASEL ((uint32_t)0x00000F00) /*!< MASEL [3:0] (DAC channel Mask/Amplitude selector) */
+#define DAC_CTRL_MASEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DAC_CTRL_MASEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define DAC_CTRL_MASEL_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define DAC_CTRL_MASEL_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define DAC_CTRL_DMAEN ((uint32_t)0x00001000) /*!< DAC channel DMA enable */
+
+
+
+/***************** Bit definition for DAC_SOTTR register ******************/
+#define DAC_SOTTR_TREN ((uint8_t)0x01) /*!< DAC channel software trigger */
+
+
+/***************** Bit definition for DAC_DR12CH register ******************/
+#define DAC_DR12CH_DACCHD ((uint16_t)0x0FFF) /*!< DAC channel 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DL12CH register ******************/
+#define DAC_DL12CH_DACCHD ((uint16_t)0xFFF0) /*!< DAC channel 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DR8CH register ******************/
+#define DAC_DR8CH_DACCHD ((uint8_t)0xFF) /*!< DAC channel 8-bit Right aligned data */
+
+
+
+
+/******************* Bit definition for DAC_DATO register *******************/
+#define DAC_DATO_DACCHDO ((uint16_t)0x0FFF) /*!< DAC channel data output */
+
+
+
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for TIM_CTRL1 register ********************/
+#define TIM_CTRL1_CNTEN ((uint32_t)0x00000001) /*!< Counter enable */
+#define TIM_CTRL1_UPDIS ((uint32_t)0x00000002) /*!< Update disable */
+#define TIM_CTRL1_UPRS ((uint32_t)0x00000004) /*!< Update request source */
+#define TIM_CTRL1_ONEPM ((uint32_t)0x00000008) /*!< One pulse mode */
+#define TIM_CTRL1_DIR ((uint32_t)0x00000010) /*!< Direction */
+
+#define TIM_CTRL1_CAMSEL ((uint32_t)0x00000060) /*!< CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CTRL1_CAMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define TIM_CTRL1_CAMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+
+#define TIM_CTRL1_ARPEN ((uint32_t)0x00000080) /*!< Auto-reload preload enable */
+
+#define TIM_CTRL1_CLKD ((uint32_t)0x00000300) /*!< CKD[1:0] bits (clock division) */
+#define TIM_CTRL1_CLKD_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define TIM_CTRL1_CLKD_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define TIM_CTRL1_IOMBKPEN ((uint32_t)0x00000400) /*!< Break_in selection from IOM/COMP */
+#define TIM_CTRL1_C1SEL ((uint32_t)0x00000800) /*!< Channel 1 selection from IOM/COMP */
+#define TIM_CTRL1_C2SEL ((uint32_t)0x00001000) /*!< Channel 2 selection from IOM/COMP */
+#define TIM_CTRL1_C3SEL ((uint32_t)0x00002000) /*!< Channel 3 selection from IOM/COMP */
+#define TIM_CTRL1_C4SEL ((uint32_t)0x00004000) /*!< Channel 4 selection from IOM/COMP */
+#define TIM_CTRL1_CLRSEL ((uint32_t)0x00008000) /*!< OCxRef selection from ETR/COMP */
+
+#define TIM_CTRL1_LBKPEN ((uint32_t)0x00010000) /*!< LOCKUP as bkp Enable*/
+#define TIM_CTRL1_PBKPEN ((uint32_t)0x00020000) /*!< PVD as bkp Enable */
+
+/******************* Bit definition for TIM_CTRL2 register ********************/
+#define TIM_CTRL2_CCPCTL ((uint32_t)0x00000001) /*!< Capture/Compare Preloaded Control */
+#define TIM_CTRL2_CCUSEL ((uint32_t)0x00000004) /*!< Capture/Compare Control Update Selection */
+#define TIM_CTRL2_CCDSEL ((uint32_t)0x00000008) /*!< Capture/Compare DMA Selection */
+
+#define TIM_CTRL2_MMSEL ((uint32_t)0x00000070) /*!< MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CTRL2_MMSEL_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define TIM_CTRL2_MMSEL_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define TIM_CTRL2_MMSEL_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+
+#define TIM_CTRL2_TI1SEL ((uint32_t)0x00000080) /*!< TI1 Selection */
+#define TIM_CTRL2_OI1 ((uint32_t)0x00000100) /*!< Output Idle state 1 (OC1 output) */
+#define TIM_CTRL2_OI1N ((uint32_t)0x00000200) /*!< Output Idle state 1 (OC1N output) */
+#define TIM_CTRL2_OI2 ((uint32_t)0x00000400) /*!< Output Idle state 2 (OC2 output) */
+#define TIM_CTRL2_OI2N ((uint32_t)0x00000800) /*!< Output Idle state 2 (OC2N output) */
+#define TIM_CTRL2_OI3 ((uint32_t)0x00001000) /*!< Output Idle state 3 (OC3 output) */
+#define TIM_CTRL2_OI3N ((uint32_t)0x00002000) /*!< Output Idle state 3 (OC3N output) */
+#define TIM_CTRL2_OI4 ((uint32_t)0x00004000) /*!< Output Idle state 4 (OC4 output) */
+
+#define TIM_CTRL2_OI5 ((uint32_t)0x00010000) /*!< Output Idle state 5 (OC5 output) */
+#define TIM_CTRL2_OI6 ((uint32_t)0x00040000) /*!< Output Idle state 6 (OC6 output) */
+
+/******************* Bit definition for TIM_SMCTRL register *******************/
+#define TIM_SMCTRL_SMSEL ((uint16_t)0x0007) /*!< SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCTRL_SMSEL_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_SMCTRL_SMSEL_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define TIM_SMCTRL_SMSEL_2 ((uint16_t)0x0004) /*!< Bit 2 */
+
+#define TIM_SMCTRL_TSEL ((uint16_t)0x0070) /*!< TS[2:0] bits (Trigger selection) */
+#define TIM_SMCTRL_TSEL_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_SMCTRL_TSEL_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_SMCTRL_TSEL_2 ((uint16_t)0x0040) /*!< Bit 2 */
+
+#define TIM_SMCTRL_MSMD ((uint16_t)0x0080) /*!< Master/slave mode */
+
+#define TIM_SMCTRL_EXTF ((uint16_t)0x0F00) /*!< ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCTRL_EXTF_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_SMCTRL_EXTF_1 ((uint16_t)0x0200) /*!< Bit 1 */
+#define TIM_SMCTRL_EXTF_2 ((uint16_t)0x0400) /*!< Bit 2 */
+#define TIM_SMCTRL_EXTF_3 ((uint16_t)0x0800) /*!< Bit 3 */
+
+#define TIM_SMCTRL_EXTPS ((uint16_t)0x3000) /*!< ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCTRL_EXTPS_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_SMCTRL_EXTPS_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define TIM_SMCTRL_EXCEN ((uint16_t)0x4000) /*!< External clock enable */
+#define TIM_SMCTRL_EXTP ((uint16_t)0x8000) /*!< External trigger polarity */
+
+/******************* Bit definition for TIM_DINTEN register *******************/
+#define TIM_DINTEN_UIEN ((uint16_t)0x0001) /*!< Update interrupt enable */
+#define TIM_DINTEN_CC1IEN ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt enable */
+#define TIM_DINTEN_CC2IEN ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt enable */
+#define TIM_DINTEN_CC3IEN ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt enable */
+#define TIM_DINTEN_CC4IEN ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt enable */
+#define TIM_DINTEN_COMIEN ((uint16_t)0x0020) /*!< COM interrupt enable */
+#define TIM_DINTEN_TIEN ((uint16_t)0x0040) /*!< Trigger interrupt enable */
+#define TIM_DINTEN_BIEN ((uint16_t)0x0080) /*!< Break interrupt enable */
+#define TIM_DINTEN_UDEN ((uint16_t)0x0100) /*!< Update DMA request enable */
+#define TIM_DINTEN_CC1DEN ((uint16_t)0x0200) /*!< Capture/Compare 1 DMA request enable */
+#define TIM_DINTEN_CC2DEN ((uint16_t)0x0400) /*!< Capture/Compare 2 DMA request enable */
+#define TIM_DINTEN_CC3DEN ((uint16_t)0x0800) /*!< Capture/Compare 3 DMA request enable */
+#define TIM_DINTEN_CC4DEN ((uint16_t)0x1000) /*!< Capture/Compare 4 DMA request enable */
+#define TIM_DINTEN_COMDEN ((uint16_t)0x2000) /*!< COM DMA request enable */
+#define TIM_DINTEN_TDEN ((uint16_t)0x4000) /*!< Trigger DMA request enable */
+
+/******************** Bit definition for TIM_STS register ********************/
+#define TIM_STS_UDITF ((uint32_t)0x00000001) /*!< Update interrupt Flag */
+#define TIM_STS_CC1ITF ((uint32_t)0x00000002) /*!< Capture/Compare 1 interrupt Flag */
+#define TIM_STS_CC2ITF ((uint32_t)0x00000004) /*!< Capture/Compare 2 interrupt Flag */
+#define TIM_STS_CC3ITF ((uint32_t)0x00000008) /*!< Capture/Compare 3 interrupt Flag */
+#define TIM_STS_CC4ITF ((uint32_t)0x00000010) /*!< Capture/Compare 4 interrupt Flag */
+#define TIM_STS_COMITF ((uint32_t)0x00000020) /*!< COM interrupt Flag */
+#define TIM_STS_TITF ((uint32_t)0x00000040) /*!< Trigger interrupt Flag */
+#define TIM_STS_BITF ((uint32_t)0x00000080) /*!< Break interrupt Flag */
+#define TIM_STS_CC1OCF ((uint32_t)0x00000200) /*!< Capture/Compare 1 Overcapture Flag */
+#define TIM_STS_CC2OCF ((uint32_t)0x00000400) /*!< Capture/Compare 2 Overcapture Flag */
+#define TIM_STS_CC3OCF ((uint32_t)0x00000800) /*!< Capture/Compare 3 Overcapture Flag */
+#define TIM_STS_CC4OCF ((uint32_t)0x00001000) /*!< Capture/Compare 4 Overcapture Flag */
+
+#define TIM_STS_CC5ITF ((uint32_t)0x00010000) /*!< Capture/Compare 5 interrupt Flag */
+#define TIM_STS_CC6ITF ((uint32_t)0x00020000) /*!< Capture/Compare 6 interrupt Flag */
+
+/******************* Bit definition for TIM_EVTGEN register ********************/
+#define TIM_EVTGEN_UDGN ((uint8_t)0x01) /*!< Update Generation */
+#define TIM_EVTGEN_CC1GN ((uint8_t)0x02) /*!< Capture/Compare 1 Generation */
+#define TIM_EVTGEN_CC2GN ((uint8_t)0x04) /*!< Capture/Compare 2 Generation */
+#define TIM_EVTGEN_CC3GN ((uint8_t)0x08) /*!< Capture/Compare 3 Generation */
+#define TIM_EVTGEN_CC4GN ((uint8_t)0x10) /*!< Capture/Compare 4 Generation */
+#define TIM_EVTGEN_CCUDGN ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation */
+#define TIM_EVTGEN_TGN ((uint8_t)0x40) /*!< Trigger Generation */
+#define TIM_EVTGEN_BGN ((uint8_t)0x80) /*!< Break Generation */
+
+/****************** Bit definition for TIM_CCMOD1 register *******************/
+#define TIM_CCMOD1_CC1SEL ((uint16_t)0x0003) /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMOD1_CC1SEL_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_CCMOD1_CC1SEL_1 ((uint16_t)0x0002) /*!< Bit 1 */
+
+#define TIM_CCMOD1_OC1FEN ((uint16_t)0x0004) /*!< Output Compare 1 Fast enable */
+#define TIM_CCMOD1_OC1PEN ((uint16_t)0x0008) /*!< Output Compare 1 Preload enable */
+
+#define TIM_CCMOD1_OC1M ((uint16_t)0x0070) /*!< OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMOD1_OC1M_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMOD1_OC1M_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMOD1_OC1M_2 ((uint16_t)0x0040) /*!< Bit 2 */
+
+#define TIM_CCMOD1_OC1CEN ((uint16_t)0x0080) /*!< Output Compare 1Clear Enable */
+
+#define TIM_CCMOD1_CC2SEL ((uint16_t)0x0300) /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMOD1_CC2SEL_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_CCMOD1_CC2SEL_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define TIM_CCMOD1_OC2FEN ((uint16_t)0x0400) /*!< Output Compare 2 Fast enable */
+#define TIM_CCMOD1_OC2PEN ((uint16_t)0x0800) /*!< Output Compare 2 Preload enable */
+
+#define TIM_CCMOD1_OC2M ((uint16_t)0x7000) /*!< OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMOD1_OC2M_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMOD1_OC2M_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMOD1_OC2M_2 ((uint16_t)0x4000) /*!< Bit 2 */
+
+#define TIM_CCMOD1_OC2CEN ((uint16_t)0x8000) /*!< Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMOD1_IC1PSC ((uint16_t)0x000C) /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMOD1_IC1PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */
+#define TIM_CCMOD1_IC1PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */
+
+#define TIM_CCMOD1_IC1F ((uint16_t)0x00F0) /*!< IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMOD1_IC1F_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMOD1_IC1F_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMOD1_IC1F_2 ((uint16_t)0x0040) /*!< Bit 2 */
+#define TIM_CCMOD1_IC1F_3 ((uint16_t)0x0080) /*!< Bit 3 */
+
+#define TIM_CCMOD1_IC2PSC ((uint16_t)0x0C00) /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMOD1_IC2PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define TIM_CCMOD1_IC2PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define TIM_CCMOD1_IC2F ((uint16_t)0xF000) /*!< IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMOD1_IC2F_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMOD1_IC2F_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMOD1_IC2F_2 ((uint16_t)0x4000) /*!< Bit 2 */
+#define TIM_CCMOD1_IC2F_3 ((uint16_t)0x8000) /*!< Bit 3 */
+
+/****************** Bit definition for TIM_CCMOD2 register *******************/
+#define TIM_CCMOD2_CC3SEL ((uint16_t)0x0003) /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMOD2_CC3SEL_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_CCMOD2_CC3SEL_1 ((uint16_t)0x0002) /*!< Bit 1 */
+
+#define TIM_CCMOD2_OC3FEN ((uint16_t)0x0004) /*!< Output Compare 3 Fast enable */
+#define TIM_CCMOD2_OC3PEN ((uint16_t)0x0008) /*!< Output Compare 3 Preload enable */
+
+#define TIM_CCMOD2_OC3MD ((uint16_t)0x0070) /*!< OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMOD2_OC3MD_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMOD2_OC3MD_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMOD2_OC3MD_2 ((uint16_t)0x0040) /*!< Bit 2 */
+
+#define TIM_CCMOD2_OC3CEN ((uint16_t)0x0080) /*!< Output Compare 3 Clear Enable */
+
+#define TIM_CCMOD2_CC4SEL ((uint16_t)0x0300) /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMOD2_CC4SEL_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_CCMOD2_CC4SEL_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define TIM_CCMOD2_OC4FEN ((uint16_t)0x0400) /*!< Output Compare 4 Fast enable */
+#define TIM_CCMOD2_OC4PEN ((uint16_t)0x0800) /*!< Output Compare 4 Preload enable */
+
+#define TIM_CCMOD2_OC4MD ((uint16_t)0x7000) /*!< OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMOD2_OC4MD_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMOD2_OC4MD_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMOD2_OC4MD_2 ((uint16_t)0x4000) /*!< Bit 2 */
+
+#define TIM_CCMOD2_OC4CEN ((uint16_t)0x8000) /*!< Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMOD2_IC3PSC ((uint16_t)0x000C) /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMOD2_IC3PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */
+#define TIM_CCMOD2_IC3PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */
+
+#define TIM_CCMOD2_IC3F ((uint16_t)0x00F0) /*!< IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMOD2_IC3F_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMOD2_IC3F_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMOD2_IC3F_2 ((uint16_t)0x0040) /*!< Bit 2 */
+#define TIM_CCMOD2_IC3F_3 ((uint16_t)0x0080) /*!< Bit 3 */
+
+#define TIM_CCMOD2_IC4PSC ((uint16_t)0x0C00) /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMOD2_IC4PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define TIM_CCMOD2_IC4PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define TIM_CCMOD2_IC4F ((uint16_t)0xF000) /*!< IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMOD2_IC4F_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMOD2_IC4F_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMOD2_IC4F_2 ((uint16_t)0x4000) /*!< Bit 2 */
+#define TIM_CCMOD2_IC4F_3 ((uint16_t)0x8000) /*!< Bit 3 */
+
+/****************** Bit definition for TIM_CCMOD3 register *******************/
+#define TIM_CCMOD3_OC5FEN ((uint16_t)0x0004) /*!< Output Compare 5 Fast enable */
+#define TIM_CCMOD3_OC5PEN ((uint16_t)0x0008) /*!< Output Compare 5 Preload enable */
+
+#define TIM_CCMOD3_OC5MD ((uint16_t)0x0070) /*!< OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMOD3_OC5MD_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMOD3_OC5MD_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMOD3_OC5MD_2 ((uint16_t)0x0040) /*!< Bit 2 */
+
+#define TIM_CCMOD3_OC5CEN ((uint16_t)0x0080) /*!< Output Compare 5Clear Enable */
+
+#define TIM_CCMOD3_OC6FEN ((uint16_t)0x0400) /*!< Output Compare 6 Fast enable */
+#define TIM_CCMOD3_OC6PEN ((uint16_t)0x0800) /*!< Output Compare 6 Preload enable */
+
+#define TIM_CCMOD3_OC6MD ((uint16_t)0x7000) /*!< OC6M[2:0] bits (Output Compare 6 Mode) */
+#define TIM_CCMOD3_OC6MD_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMOD3_OC6MD_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMOD3_OC6MD_2 ((uint16_t)0x4000) /*!< Bit 2 */
+
+#define TIM_CCMOD3_OC6CEN ((uint16_t)0x8000) /*!< Output Compare 6 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+/******************* Bit definition for TIM_CCEN register *******************/
+#define TIM_CCEN_CC1EN ((uint32_t)0x00000001) /*!< Capture/Compare 1 output enable */
+#define TIM_CCEN_CC1P ((uint32_t)0x00000002) /*!< Capture/Compare 1 output Polarity */
+#define TIM_CCEN_CC1NEN ((uint32_t)0x00000004) /*!< Capture/Compare 1 Complementary output enable */
+#define TIM_CCEN_CC1NP ((uint32_t)0x00000008) /*!< Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCEN_CC2EN ((uint32_t)0x00000010) /*!< Capture/Compare 2 output enable */
+#define TIM_CCEN_CC2P ((uint32_t)0x00000020) /*!< Capture/Compare 2 output Polarity */
+#define TIM_CCEN_CC2NEN ((uint32_t)0x00000040) /*!< Capture/Compare 2 Complementary output enable */
+#define TIM_CCEN_CC2NP ((uint32_t)0x00000080) /*!< Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCEN_CC3EN ((uint32_t)0x00000100) /*!< Capture/Compare 3 output enable */
+#define TIM_CCEN_CC3P ((uint32_t)0x00000200) /*!< Capture/Compare 3 output Polarity */
+#define TIM_CCEN_CC3NEN ((uint32_t)0x00000400) /*!< Capture/Compare 3 Complementary output enable */
+#define TIM_CCEN_CC3NP ((uint32_t)0x00000800) /*!< Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCEN_CC4EN ((uint32_t)0x00001000) /*!< Capture/Compare 4 output enable */
+#define TIM_CCEN_CC4P ((uint32_t)0x00002000) /*!< Capture/Compare 4 output Polarity */
+
+#define TIM_CCEN_CC5EN ((uint32_t)0x00010000) /*!< Capture/Compare 5 output enable */
+#define TIM_CCEN_CC5P ((uint32_t)0x00020000) /*!< Capture/Compare 5 output Polarity */
+#define TIM_CCEN_CC6EN ((uint32_t)0x00100000) /*!< Capture/Compare 6 output enable */
+#define TIM_CCEN_CC6P ((uint32_t)0x00200000) /*!< Capture/Compare 6 output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!< Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!< Prescaler Value */
+
+/******************* Bit definition for TIM_AR register ********************/
+#define TIM_AR_AR ((uint16_t)0xFFFF) /*!< actual auto-reload Value */
+
+/******************* Bit definition for TIM_REPCNT register ********************/
+#define TIM_REPCNT_REPCNT ((uint8_t)0xFF) /*!< Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCDAT1 register *******************/
+#define TIM_CCDAT1_CCDAT1 ((uint16_t)0xFFFF) /*!< Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCDAT2 register *******************/
+#define TIM_CCDAT2_CCDAT2 ((uint16_t)0xFFFF) /*!< Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCDAT3 register *******************/
+#define TIM_CCDAT3_CCDAT3 ((uint16_t)0xFFFF) /*!< Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCDAT4 register *******************/
+#define TIM_CCDAT4_CCDAT4 ((uint16_t)0xFFFF) /*!< Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_CCDAT5 register *******************/
+#define TIM_CCDAT5_CCDAT5 ((uint16_t)0xFFFF) /*!< Capture/Compare 5 Value */
+
+/******************* Bit definition for TIM_CCDAT6 register *******************/
+#define TIM_CCDAT6_CCDAT6 ((uint16_t)0xFFFF) /*!< Capture/Compare 6 Value */
+
+/******************* Bit definition for TIM_BKDT register *******************/
+#define TIM_BKDT_DTGN ((uint16_t)0x00FF) /*!< DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BKDT_DTGN_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_BKDT_DTGN_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define TIM_BKDT_DTGN_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define TIM_BKDT_DTGN_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define TIM_BKDT_DTGN_4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define TIM_BKDT_DTGN_5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define TIM_BKDT_DTGN_6 ((uint16_t)0x0040) /*!< Bit 6 */
+#define TIM_BKDT_DTGN_7 ((uint16_t)0x0080) /*!< Bit 7 */
+
+#define TIM_BKDT_LCKCFG ((uint16_t)0x0300) /*!< LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BKDT_LCKCFG_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_BKDT_LCKCFG_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define TIM_BKDT_OSSI ((uint16_t)0x0400) /*!< Off-State Selection for Idle mode */
+#define TIM_BKDT_OSSR ((uint16_t)0x0800) /*!< Off-State Selection for Run mode */
+#define TIM_BKDT_BKEN ((uint16_t)0x1000) /*!< Break enable */
+#define TIM_BKDT_BKP ((uint16_t)0x2000) /*!< Break Polarity */
+#define TIM_BKDT_AOEN ((uint16_t)0x4000) /*!< Automatic Output enable */
+#define TIM_BKDT_MOEN ((uint16_t)0x8000) /*!< Main Output enable */
+
+/******************* Bit definition for TIM_DCTRL register ********************/
+#define TIM_DCTRL_DBADDR ((uint16_t)0x001F) /*!< DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCTRL_DBADDR_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_DCTRL_DBADDR_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define TIM_DCTRL_DBADDR_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define TIM_DCTRL_DBADDR_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define TIM_DCTRL_DBADDR_4 ((uint16_t)0x0010) /*!< Bit 4 */
+
+#define TIM_DCTRL_DBLEN ((uint16_t)0x1F00) /*!< DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCTRL_DBLEN_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_DCTRL_DBLEN_1 ((uint16_t)0x0200) /*!< Bit 1 */
+#define TIM_DCTRL_DBLEN_2 ((uint16_t)0x0400) /*!< Bit 2 */
+#define TIM_DCTRL_DBLEN_3 ((uint16_t)0x0800) /*!< Bit 3 */
+#define TIM_DCTRL_DBLEN_4 ((uint16_t)0x1000) /*!< Bit 4 */
+
+/******************* Bit definition for TIM_DADDR register *******************/
+#define TIM_DADDR_BURST ((uint16_t)0xFFFF) /*!< DMA register for burst accesses */
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_INTSTS register *******************/
+#define LPTIM_INTSTS_CMPM ((uint32_t)0x00000001) /*!< Compare match */
+#define LPTIM_INTSTS_ARRM ((uint32_t)0x00000002) /*!< Autoreload match */
+#define LPTIM_INTSTS_EXTRIG ((uint32_t)0x00000004) /*!< External trigger edge event */
+#define LPTIM_INTSTS_CMPUPD ((uint32_t)0x00000008) /*!< Compare register update OK */
+#define LPTIM_INTSTS_ARRUPD ((uint32_t)0x00000010) /*!< Autoreload register update OK */
+#define LPTIM_INTSTS_UP ((uint32_t)0x00000020) /*!< Counter direction change down to up */
+#define LPTIM_INTSTS_DOWN ((uint32_t)0x00000040) /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_INTCLR register *******************/
+#define LPTIM_INTCLR_CMPMCF ((uint32_t)0x00000001) /*!< Compare match Clear Flag */
+#define LPTIM_INTCLR_ARRMCF ((uint32_t)0x00000002) /*!< Autoreload match Clear Flag */
+#define LPTIM_INTCLR_EXTRIGCF ((uint32_t)0x00000004) /*!< External trigger edge event Clear Flag */
+#define LPTIM_INTCLR_CMPUPDCF ((uint32_t)0x00000008) /*!< Compare register update OK Clear Flag */
+#define LPTIM_INTCLR_ARRUPDCF ((uint32_t)0x00000010) /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_INTCLR_UPCF ((uint32_t)0x00000020) /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_INTCLR_DOWNCF ((uint32_t)0x00000040) /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_INTEN register ********************/
+#define LPTIM_INTEN_CMPMIE ((uint32_t)0x00000001) /*!< Compare match Interrupt Enable */
+#define LPTIM_INTEN_ARRMIE ((uint32_t)0x00000002) /*!< Autoreload match Interrupt Enable */
+#define LPTIM_INTEN_EXTRIGIE ((uint32_t)0x00000004) /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_INTEN_CMPUPDIE ((uint32_t)0x00000008) /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_INTEN_ARRUPDIE ((uint32_t)0x00000010) /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_INTEN_UPIE ((uint32_t)0x00000020) /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_INTEN_DOWNIE ((uint32_t)0x00000040) /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFG register *******************/
+#define LPTIM_CFG_CLKSEL ((uint32_t)0x00000001) /*!< Clock selector */
+
+#define LPTIM_CFG_CLKPOL ((uint32_t)0x00000006) /*!< CLKP[1:0] bits (Clock polarity) */
+#define LPTIM_CFG_CLKPOL_0 ((uint32_t)0x00000002) /*!< 0x00000002 */
+#define LPTIM_CFG_CLKPOL_1 ((uint32_t)0x00000004) /*!< 0x00000004 */
+
+#define LPTIM_CFG_CLKFLT ((uint32_t)0x00000018) /*!< CFGDFFEXT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFG_CLKFLT_0 ((uint32_t)0x00000008) /*!< 0x00000008 */
+#define LPTIM_CFG_CLKFLT_1 ((uint32_t)0x00000010) /*!< 0x00000010 */
+
+#define LPTIM_CFG_TRIGFLT ((uint32_t)0x000000C0) /*!< CFGDFFTRG[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFG_TRIGFLT_0 ((uint32_t)0x00000040) /*!< 0x00000040 */
+#define LPTIM_CFG_TRIGFLT_1 ((uint32_t)0x00000080) /*!< 0x00000080 */
+
+#define LPTIM_CFG_CLKPRE ((uint32_t)0x00000E00) /*!< CLKPRE[2:0] bits (Clock prescaler) */
+#define LPTIM_CFG_CLKPRE_0 ((uint32_t)0x00000200) /*!< 0x00000200 */
+#define LPTIM_CFG_CLKPRE_1 ((uint32_t)0x00000400) /*!< 0x00000400 */
+#define LPTIM_CFG_CLKPRE_2 ((uint32_t)0x00000800) /*!< 0x00000800 */
+
+#define LPTIM_CFG_TRGSEL ((uint32_t)0x0000E000) /*!< TRGS[2:0]] bits (Trigger selector) */
+#define LPTIM_CFG_TRGSEL_0 ((uint32_t)0x00002000) /*!< 0x00002000 */
+#define LPTIM_CFG_TRGSEL_1 ((uint32_t)0x00004000) /*!< 0x00004000 */
+#define LPTIM_CFG_TRGSEL_2 ((uint32_t)0x00008000) /*!< 0x00008000 */
+
+#define LPTIM_CFG_TRGEN ((uint32_t)0x00060000) /*!< TRGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFG_TRGEN_0 ((uint32_t)0x00020000) /*!< 0x00020000 */
+#define LPTIM_CFG_TRGEN_1 ((uint32_t)0x00040000) /*!< 0x00040000 */
+
+#define LPTIM_CFG_TIMOUTEN ((uint32_t)0x00080000) /*!< Timout enable */
+#define LPTIM_CFG_WAVE ((uint32_t)0x00100000) /*!< Waveform shape */
+#define LPTIM_CFG_WAVEPOL ((uint32_t)0x00200000) /*!< Waveform shape polarity */
+#define LPTIM_CFG_RELOAD ((uint32_t)0x00400000) /*!< Reg update mode */
+#define LPTIM_CFG_CNTMEN ((uint32_t)0x00800000) /*!< Counter mode enable */
+#define LPTIM_CFG_ENC ((uint32_t)0x01000000) /*!< Encoder mode enable */
+#define LPTIM_CFG_NENC ((uint32_t)0x02000000) /*!< NONEncoder mode enable */
+/****************** Bit definition for LPTIM_CTRL register ********************/
+#define LPTIM_CTRL_LPTIMEN ((uint32_t)0x000000001) /*!< LPTIMer enable */
+#define LPTIM_CTRL_SNGMST ((uint32_t)0x000000002) /*!< Timer start in single mode */
+#define LPTIM_CTRL_TSTCM ((uint32_t)0x000000004) /*!< Timer start in continuous mode */
+
+/****************** Bit definition for LPTIM_CMPT register *******************/
+#define LPTIM_COMP_CMPVAL ((uint16_t)0xFFFF) /*!< Compare register */
+
+/****************** Bit definition for LPTIM_AUTRLD register *******************/
+#define LPTIM_ARR_ARRVAL ((uint16_t)0xFFFF) /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNTVAL ((uint16_t)0xFFFF) /*!< Counter register */
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TSH register *******************/
+#define RTC_TSH_APM ((uint32_t)0x00400000)
+#define RTC_TSH_HOT ((uint32_t)0x00300000)
+#define RTC_TSH_HOT_0 ((uint32_t)0x00100000)
+#define RTC_TSH_HOT_1 ((uint32_t)0x00200000)
+#define RTC_TSH_HOU ((uint32_t)0x000F0000)
+#define RTC_TSH_HOU_0 ((uint32_t)0x00010000)
+#define RTC_TSH_HOU_1 ((uint32_t)0x00020000)
+#define RTC_TSH_HOU_2 ((uint32_t)0x00040000)
+#define RTC_TSH_HOU_3 ((uint32_t)0x00080000)
+#define RTC_TSH_MIT ((uint32_t)0x00007000)
+#define RTC_TSH_MIT_0 ((uint32_t)0x00001000)
+#define RTC_TSH_MIT_1 ((uint32_t)0x00002000)
+#define RTC_TSH_MIT_2 ((uint32_t)0x00004000)
+#define RTC_TSH_MIU ((uint32_t)0x00000F00)
+#define RTC_TSH_MIU_0 ((uint32_t)0x00000100)
+#define RTC_TSH_MIU_1 ((uint32_t)0x00000200)
+#define RTC_TSH_MIU_2 ((uint32_t)0x00000400)
+#define RTC_TSH_MIU_3 ((uint32_t)0x00000800)
+#define RTC_TSH_SCT ((uint32_t)0x00000070)
+#define RTC_TSH_SCT_0 ((uint32_t)0x00000010)
+#define RTC_TSH_SCT_1 ((uint32_t)0x00000020)
+#define RTC_TSH_SCT_2 ((uint32_t)0x00000040)
+#define RTC_TSH_SCU ((uint32_t)0x0000000F)
+#define RTC_TSH_SCU_0 ((uint32_t)0x00000001)
+#define RTC_TSH_SCU_1 ((uint32_t)0x00000002)
+#define RTC_TSH_SCU_2 ((uint32_t)0x00000004)
+#define RTC_TSH_SCU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_DATE register *******************/
+#define RTC_DATE_YRT ((uint32_t)0x00F00000)
+#define RTC_DATE_YRT_0 ((uint32_t)0x00100000)
+#define RTC_DATE_YRT_1 ((uint32_t)0x00200000)
+#define RTC_DATE_YRT_2 ((uint32_t)0x00400000)
+#define RTC_DATE_YRT_3 ((uint32_t)0x00800000)
+#define RTC_DATE_YRU ((uint32_t)0x000F0000)
+#define RTC_DATE_YRU_0 ((uint32_t)0x00010000)
+#define RTC_DATE_YRU_1 ((uint32_t)0x00020000)
+#define RTC_DATE_YRU_2 ((uint32_t)0x00040000)
+#define RTC_DATE_YRU_3 ((uint32_t)0x00080000)
+#define RTC_DATE_WDU ((uint32_t)0x0000E000)
+#define RTC_DATE_WDU_0 ((uint32_t)0x00002000)
+#define RTC_DATE_WDU_1 ((uint32_t)0x00004000)
+#define RTC_DATE_WDU_2 ((uint32_t)0x00008000)
+#define RTC_DATE_MOT ((uint32_t)0x00001000)
+#define RTC_DATE_MOU ((uint32_t)0x00000F00)
+#define RTC_DATE_MOU_0 ((uint32_t)0x00000100)
+#define RTC_DATE_MOU_1 ((uint32_t)0x00000200)
+#define RTC_DATE_MOU_2 ((uint32_t)0x00000400)
+#define RTC_DATE_MOU_3 ((uint32_t)0x00000800)
+#define RTC_DATE_DAT ((uint32_t)0x00000030)
+#define RTC_DATE_DAT_0 ((uint32_t)0x00000010)
+#define RTC_DATE_DAT_1 ((uint32_t)0x00000020)
+#define RTC_DATE_DAU ((uint32_t)0x0000000F)
+#define RTC_DATE_DAU_0 ((uint32_t)0x00000001)
+#define RTC_DATE_DAU_1 ((uint32_t)0x00000002)
+#define RTC_DATE_DAU_2 ((uint32_t)0x00000004)
+#define RTC_DATE_DAU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_CTRL register *******************/
+#define RTC_CTRL_COEN ((uint32_t)0x00800000)
+#define RTC_CTRL_OUTSEL ((uint32_t)0x00600000)
+#define RTC_CTRL_OUTSEL_0 ((uint32_t)0x00200000)
+#define RTC_CTRL_OUTSEL_1 ((uint32_t)0x00400000)
+#define RTC_CTRL_OPOL ((uint32_t)0x00100000)
+#define RTC_CTRL_CALOSEL ((uint32_t)0x00080000)
+#define RTC_CTRL_BAKP ((uint32_t)0x00040000)
+#define RTC_CTRL_SU1H ((uint32_t)0x00020000)
+#define RTC_CTRL_AD1H ((uint32_t)0x00010000)
+#define RTC_CTRL_TSIEN ((uint32_t)0x00008000)
+#define RTC_CTRL_WTIEN ((uint32_t)0x00004000)
+#define RTC_CTRL_ALBIEN ((uint32_t)0x00002000)
+#define RTC_CTRL_ALAIEN ((uint32_t)0x00001000)
+#define RTC_CTRL_TSEN ((uint32_t)0x00000800)
+#define RTC_CTRL_WTEN ((uint32_t)0x00000400)
+#define RTC_CTRL_ALBEN ((uint32_t)0x00000200)
+#define RTC_CTRL_ALAEN ((uint32_t)0x00000100)
+
+#define RTC_CTRL_HFMT ((uint32_t)0x00000040)
+#define RTC_CTRL_BYPS ((uint32_t)0x00000020)
+#define RTC_CTRL_REFCLKEN ((uint32_t)0x00000010)
+#define RTC_CTRL_TEDGE ((uint32_t)0x00000008)
+#define RTC_CTRL_WKUPSEL ((uint32_t)0x00000007)
+#define RTC_CTRL_WKUPSEL_0 ((uint32_t)0x00000001)
+#define RTC_CTRL_WKUPSEL_1 ((uint32_t)0x00000002)
+#define RTC_CTRL_WKUPSEL_2 ((uint32_t)0x00000004)
+
+/******************** Bits definition for RTC_INITSTS register ******************/
+#define RTC_INITSTS_RECPF ((uint32_t)0x00010000)
+#define RTC_INITSTS_TAM3F ((uint32_t)0x00008000)
+#define RTC_INITSTS_TAM2F ((uint32_t)0x00004000)
+#define RTC_INITSTS_TAM1F ((uint32_t)0x00002000)
+#define RTC_INITSTS_TISOVF ((uint32_t)0x00001000)
+#define RTC_INITSTS_TISF ((uint32_t)0x00000800)
+#define RTC_INITSTS_WTF ((uint32_t)0x00000400)
+#define RTC_INITSTS_ALBF ((uint32_t)0x00000200)
+#define RTC_INITSTS_ALAF ((uint32_t)0x00000100)
+#define RTC_INITSTS_INITM ((uint32_t)0x00000080)
+#define RTC_INITSTS_INITF ((uint32_t)0x00000040)
+#define RTC_INITSTS_RSYF ((uint32_t)0x00000020)
+#define RTC_INITSTS_INITSF ((uint32_t)0x00000010)
+#define RTC_INITSTS_SHOPF ((uint32_t)0x00000008)
+#define RTC_INITSTS_WTWF ((uint32_t)0x00000004)
+#define RTC_INITSTS_ALBWF ((uint32_t)0x00000002)
+#define RTC_INITSTS_ALAWF ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_PRE register *****************/
+#define RTC_PRE_DIVA ((uint32_t)0x007F0000)
+#define RTC_PRE_DIVS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_WKUPT register *****************/
+#define RTC_WKUPT_WKUPT ((uint32_t)0x0000FFFF)
+
+
+/******************** Bits definition for RTC_ALARMA register ***************/
+#define RTC_ALARMA_MASK4 ((uint32_t)0x80000000)
+#define RTC_ALARMA_WKDSEL ((uint32_t)0x40000000)
+#define RTC_ALARMA_DTT ((uint32_t)0x30000000)
+#define RTC_ALARMA_DTT_0 ((uint32_t)0x10000000)
+#define RTC_ALARMA_DTT_1 ((uint32_t)0x20000000)
+#define RTC_ALARMA_DTU ((uint32_t)0x0F000000)
+#define RTC_ALARMA_DTU_0 ((uint32_t)0x01000000)
+#define RTC_ALARMA_DTU_1 ((uint32_t)0x02000000)
+#define RTC_ALARMA_DTU_2 ((uint32_t)0x04000000)
+#define RTC_ALARMA_DTU_3 ((uint32_t)0x08000000)
+#define RTC_ALARMA_MASK3 ((uint32_t)0x00800000)
+#define RTC_ALARMA_APM ((uint32_t)0x00400000)
+#define RTC_ALARMA_HOT ((uint32_t)0x00300000)
+#define RTC_ALARMA_HOT_0 ((uint32_t)0x00100000)
+#define RTC_ALARMA_HOT_1 ((uint32_t)0x00200000)
+#define RTC_ALARMA_HOU ((uint32_t)0x000F0000)
+#define RTC_ALARMA_HOU_0 ((uint32_t)0x00010000)
+#define RTC_ALARMA_HOU_1 ((uint32_t)0x00020000)
+#define RTC_ALARMA_HOU_2 ((uint32_t)0x00040000)
+#define RTC_ALARMA_HOU_3 ((uint32_t)0x00080000)
+#define RTC_ALARMA_MASK2 ((uint32_t)0x00008000)
+#define RTC_ALARMA_MIT ((uint32_t)0x00007000)
+#define RTC_ALARMA_MIT_0 ((uint32_t)0x00001000)
+#define RTC_ALARMA_MIT_1 ((uint32_t)0x00002000)
+#define RTC_ALARMA_MIT_2 ((uint32_t)0x00004000)
+#define RTC_ALARMA_MIU ((uint32_t)0x00000F00)
+#define RTC_ALARMA_MIU_0 ((uint32_t)0x00000100)
+#define RTC_ALARMA_MIU_1 ((uint32_t)0x00000200)
+#define RTC_ALARMA_MIU_2 ((uint32_t)0x00000400)
+#define RTC_ALARMA_MIU_3 ((uint32_t)0x00000800)
+#define RTC_ALARMA_MASK1 ((uint32_t)0x00000080)
+#define RTC_ALARMA_SET ((uint32_t)0x00000070)
+#define RTC_ALARMA_SET_0 ((uint32_t)0x00000010)
+#define RTC_ALARMA_SET_1 ((uint32_t)0x00000020)
+#define RTC_ALARMA_SET_2 ((uint32_t)0x00000040)
+#define RTC_ALARMA_SEU ((uint32_t)0x0000000F)
+#define RTC_ALARMA_SEU_0 ((uint32_t)0x00000001)
+#define RTC_ALARMA_SEU_1 ((uint32_t)0x00000002)
+#define RTC_ALARMA_SEU_2 ((uint32_t)0x00000004)
+#define RTC_ALARMA_SEU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_ALARMB register ***************/
+#define RTC_ALARMB_MASK4 ((uint32_t)0x80000000)
+#define RTC_ALARMB_WKDSEL ((uint32_t)0x40000000)
+#define RTC_ALARMB_DTT ((uint32_t)0x30000000)
+#define RTC_ALARMB_DTT_0 ((uint32_t)0x10000000)
+#define RTC_ALARMB_DTT_1 ((uint32_t)0x20000000)
+#define RTC_ALARMB_DTU ((uint32_t)0x0F000000)
+#define RTC_ALARMB_DTU_0 ((uint32_t)0x01000000)
+#define RTC_ALARMB_DTU_1 ((uint32_t)0x02000000)
+#define RTC_ALARMB_DTU_2 ((uint32_t)0x04000000)
+#define RTC_ALARMB_DTU_3 ((uint32_t)0x08000000)
+#define RTC_ALARMB_MASK3 ((uint32_t)0x00800000)
+#define RTC_ALARMB_APM ((uint32_t)0x00400000)
+#define RTC_ALARMB_HOT ((uint32_t)0x00300000)
+#define RTC_ALARMB_HOT_0 ((uint32_t)0x00100000)
+#define RTC_ALARMB_HOT_1 ((uint32_t)0x00200000)
+#define RTC_ALARMB_HOU ((uint32_t)0x000F0000)
+#define RTC_ALARMB_HOU_0 ((uint32_t)0x00010000)
+#define RTC_ALARMB_HOU_1 ((uint32_t)0x00020000)
+#define RTC_ALARMB_HOU_2 ((uint32_t)0x00040000)
+#define RTC_ALARMB_HOU_3 ((uint32_t)0x00080000)
+#define RTC_ALARMB_MASK2 ((uint32_t)0x00008000)
+#define RTC_ALARMB_MIT ((uint32_t)0x00007000)
+#define RTC_ALARMB_MIT_0 ((uint32_t)0x00001000)
+#define RTC_ALARMB_MIT_1 ((uint32_t)0x00002000)
+#define RTC_ALARMB_MIT_2 ((uint32_t)0x00004000)
+#define RTC_ALARMB_MIU ((uint32_t)0x00000F00)
+#define RTC_ALARMB_MIU_0 ((uint32_t)0x00000100)
+#define RTC_ALARMB_MIU_1 ((uint32_t)0x00000200)
+#define RTC_ALARMB_MIU_2 ((uint32_t)0x00000400)
+#define RTC_ALARMB_MIU_3 ((uint32_t)0x00000800)
+#define RTC_ALARMB_MASK1 ((uint32_t)0x00000080)
+#define RTC_ALARMB_SET ((uint32_t)0x00000070)
+#define RTC_ALARMB_SET_0 ((uint32_t)0x00000010)
+#define RTC_ALARMB_SET_1 ((uint32_t)0x00000020)
+#define RTC_ALARMB_SET_2 ((uint32_t)0x00000040)
+#define RTC_ALARMB_SEU ((uint32_t)0x0000000F)
+#define RTC_ALARMB_SEU_0 ((uint32_t)0x00000001)
+#define RTC_ALARMB_SEU_1 ((uint32_t)0x00000002)
+#define RTC_ALARMB_SEU_2 ((uint32_t)0x00000004)
+#define RTC_ALARMB_SEU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_WRP register ******************/
+#define RTC_WRP_PKEY ((uint32_t)0x000000FF)
+
+/******************** Bits definition for RTC_SUBS register ******************/
+#define RTC_SUBS_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_SCTRL register ***************/
+#define RTC_SCTRL_SUBF ((uint32_t)0x00007FFF)
+#define RTC_SCTRL_AD1S ((uint32_t)0x80000000)
+
+/******************** Bits definition for RTC_TST register *****************/
+#define RTC_TST_APM ((uint32_t)0x00400000)
+#define RTC_TST_HOT ((uint32_t)0x00300000)
+#define RTC_TST_HOT_0 ((uint32_t)0x00100000)
+#define RTC_TST_HOT_1 ((uint32_t)0x00200000)
+#define RTC_TST_HOU ((uint32_t)0x000F0000)
+#define RTC_TST_HOU_0 ((uint32_t)0x00010000)
+#define RTC_TST_HOU_1 ((uint32_t)0x00020000)
+#define RTC_TST_HOU_2 ((uint32_t)0x00040000)
+#define RTC_TST_HOU_3 ((uint32_t)0x00080000)
+#define RTC_TST_MIT ((uint32_t)0x00007000)
+#define RTC_TST_MIT_0 ((uint32_t)0x00001000)
+#define RTC_TST_MIT_1 ((uint32_t)0x00002000)
+#define RTC_TST_MIT_2 ((uint32_t)0x00004000)
+#define RTC_TST_MIU ((uint32_t)0x00000F00)
+#define RTC_TST_MIU_0 ((uint32_t)0x00000100)
+#define RTC_TST_MIU_1 ((uint32_t)0x00000200)
+#define RTC_TST_MIU_2 ((uint32_t)0x00000400)
+#define RTC_TST_MIU_3 ((uint32_t)0x00000800)
+#define RTC_TST_SET ((uint32_t)0x00000070)
+#define RTC_TST_SET_0 ((uint32_t)0x00000010)
+#define RTC_TST_SET_1 ((uint32_t)0x00000020)
+#define RTC_TST_SET_2 ((uint32_t)0x00000040)
+#define RTC_TST_SEU ((uint32_t)0x0000000F)
+#define RTC_TST_SEU_0 ((uint32_t)0x00000001)
+#define RTC_TST_SEU_1 ((uint32_t)0x00000002)
+#define RTC_TST_SEU_2 ((uint32_t)0x00000004)
+#define RTC_TST_SEU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSD register *****************/
+#define RTC_TSD_YRT ((uint32_t)0x00F00000)
+#define RTC_TSD_YRT_0 ((uint32_t)0x00100000)
+#define RTC_TSD_YRT_1 ((uint32_t)0x00200000)
+#define RTC_TSD_YRT_2 ((uint32_t)0x00400000)
+#define RTC_TSD_YRT_3 ((uint32_t)0x00800000)
+#define RTC_TSD_YRU ((uint32_t)0x000F0000)
+#define RTC_TSD_YRU_0 ((uint32_t)0x00010000)
+#define RTC_TSD_YRU_1 ((uint32_t)0x00020000)
+#define RTC_TSD_YRU_2 ((uint32_t)0x00040000)
+#define RTC_TSD_YRU_3 ((uint32_t)0x00080000)
+
+#define RTC_TSD_WDU ((uint32_t)0x0000E000)
+#define RTC_TSD_WDU_0 ((uint32_t)0x00002000)
+#define RTC_TSD_WDU_1 ((uint32_t)0x00004000)
+#define RTC_TSD_WDU_2 ((uint32_t)0x00008000)
+#define RTC_TSD_MOT ((uint32_t)0x00001000)
+#define RTC_TSD_MOU ((uint32_t)0x00000F00)
+#define RTC_TSD_MOU_0 ((uint32_t)0x00000100)
+#define RTC_TSD_MOU_1 ((uint32_t)0x00000200)
+#define RTC_TSD_MOU_2 ((uint32_t)0x00000400)
+#define RTC_TSD_MOU_3 ((uint32_t)0x00000800)
+#define RTC_TSD_DAT ((uint32_t)0x00000030)
+#define RTC_TSD_DAT_0 ((uint32_t)0x00000010)
+#define RTC_TSD_DAT_1 ((uint32_t)0x00000020)
+#define RTC_TSD_DAU ((uint32_t)0x0000000F)
+#define RTC_TSD_DAU_0 ((uint32_t)0x00000001)
+#define RTC_TSD_DAU_1 ((uint32_t)0x00000002)
+#define RTC_TSD_DAU_2 ((uint32_t)0x00000004)
+#define RTC_TSD_DAU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSSS register ****************/
+#define RTC_TSSS_SSE ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CALIB register *****************/
+#define RTC_CALIB_CP ((uint32_t)0x00008000)
+#define RTC_CALIB_CW8 ((uint32_t)0x00004000)
+#define RTC_CALIB_CW16 ((uint32_t)0x00002000)
+#define RTC_CALIB_CM ((uint32_t)0x000001FF)
+#define RTC_CALIB_CM_0 ((uint32_t)0x00000001)
+#define RTC_CALIB_CM_1 ((uint32_t)0x00000002)
+#define RTC_CALIB_CM_2 ((uint32_t)0x00000004)
+#define RTC_CALIB_CM_3 ((uint32_t)0x00000008)
+#define RTC_CALIB_CM_4 ((uint32_t)0x00000010)
+#define RTC_CALIB_CM_5 ((uint32_t)0x00000020)
+#define RTC_CALIB_CM_6 ((uint32_t)0x00000040)
+#define RTC_CALIB_CM_7 ((uint32_t)0x00000080)
+#define RTC_CALIB_CM_8 ((uint32_t)0x00000100)
+
+/******************** Bits definition for RTC_TMPCFG register ****************/
+
+#define RTC_TMPCFG_TP3MF ((uint32_t)0x01000000)
+#define RTC_TMPCFG_TP3NOE ((uint32_t)0x00800000)
+#define RTC_TMPCFG_TP3INTEN ((uint32_t)0x00400000)
+#define RTC_TMPCFG_TP2MF ((uint32_t)0x00200000)
+#define RTC_TMPCFG_TP2NOE ((uint32_t)0x00100000)
+#define RTC_TMPCFG_TP2INTEN ((uint32_t)0x00080000)
+#define RTC_TMPCFG_TP1MF ((uint32_t)0x00040000)
+#define RTC_TMPCFG_TP1NOE ((uint32_t)0x00020000)
+#define RTC_TMPCFG_TP1INTEN ((uint32_t)0x00010000)
+#define RTC_TMPCFG_TPPUDIS ((uint32_t)0x00008000)
+#define RTC_TMPCFG_TPPRCH ((uint32_t)0x00006000)
+#define RTC_TMPCFG_TPPRCH_0 ((uint32_t)0x00002000)
+#define RTC_TMPCFG_TPPRCH_1 ((uint32_t)0x00004000)
+#define RTC_TMPCFG_TPFLT ((uint32_t)0x00001800)
+#define RTC_TMPCFG_TPFLT_0 ((uint32_t)0x00000800)
+#define RTC_TMPCFG_TPFLT_1 ((uint32_t)0x00001000)
+#define RTC_TMPCFG_TPFREQ ((uint32_t)0x00000700)
+#define RTC_TMPCFG_TPFREQ_0 ((uint32_t)0x00000100)
+#define RTC_TMPCFG_TPFREQ_1 ((uint32_t)0x00000200)
+#define RTC_TMPCFG_TPFREQ_2 ((uint32_t)0x00000400)
+#define RTC_TMPCFG_TPTS ((uint32_t)0x00000080)
+#define RTC_TMPCFG_TP3TRG ((uint32_t)0x00000040)
+#define RTC_TMPCFG_TP3EN ((uint32_t)0x00000020)
+#define RTC_TMPCFG_TP2TRG ((uint32_t)0x00000010)
+#define RTC_TMPCFG_TP2EN ((uint32_t)0x00000008)
+#define RTC_TMPCFG_TPINTEN ((uint32_t)0x00000004)
+#define RTC_TMPCFG_TP1TRG ((uint32_t)0x00000002)
+#define RTC_TMPCFG_TP1EN ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_ALRMASS register *************/
+#define RTC_ALRMASS_MASKSSB ((uint32_t)0x0F000000)
+#define RTC_ALRMASS_MASKSSB_0 ((uint32_t)0x01000000)
+#define RTC_ALRMASS_MASKSSB_1 ((uint32_t)0x02000000)
+#define RTC_ALRMASS_MASKSSB_2 ((uint32_t)0x04000000)
+#define RTC_ALRMASS_MASKSSB_3 ((uint32_t)0x08000000)
+#define RTC_ALRMASS_SSV ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_ALRMBSS register *************/
+#define RTC_ALRMBSS_MASKSSB ((uint32_t)0x0F000000)
+#define RTC_ALRMBSS_MASKSSB_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBSS_MASKSSB_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBSS_MASKSSB_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBSS_MASKSSB_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBSS_SSV ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_OPT register *******************/
+#define RTC_OPT_TYPE ((uint32_t)0x00000001)
+/******************** Bits definition for RTC_TSCWKUPCTRL register *******************/
+#define RTC_TSCWKUPCTRL_WKUPOFF ((uint32_t)0x00000008)
+#define RTC_TSCWKUPCTRL_WKUPCNF ((uint32_t)0x00000004)
+#define RTC_TSCWKUPCTRL_WKUPEN ((uint32_t)0x00000001)
+/******************** Bits definition for RTC_TSCWKUPCNT register *******************/
+#define RTC_TSCWKUPCNT_CNT ((uint32_t)0x00003FFF)
+/******************** Bits definition for RTC_BKP1 register ****************/
+#define RTC_BKP1 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP2 register ****************/
+#define RTC_BKP2 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP3 register ****************/
+#define RTC_BKP3 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP4 register ****************/
+#define RTC_BKP4 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP5 register ****************/
+#define RTC_BKP5 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP6 register ****************/
+#define RTC_BKP6 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP7 register ****************/
+#define RTC_BKP7 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP8 register ****************/
+#define RTC_BKP8 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP9 register ****************/
+#define RTC_BKP9 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP10 register ****************/
+#define RTC_BKP10 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP11 register ***************/
+#define RTC_BKP11 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP12register ***************/
+#define RTC_BKP12 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP13 register ***************/
+#define RTC_BKP13 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP14 register ***************/
+#define RTC_BKP14 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP15 register ***************/
+#define RTC_BKP15 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP16 register ***************/
+#define RTC_BKP16 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP17register ***************/
+#define RTC_BKP17 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP18 register ***************/
+#define RTC_BKP18 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP19 register ***************/
+#define RTC_BKP19 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP20 register ***************/
+#define RTC_BKP20 ((uint32_t)0xFFFFFFFF)
+
+
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for IWDG_KEY register ********************/
+#define IWDG_KEY_KEYV ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PREDIV register ********************/
+#define IWDG_PREDIV_PD ((uint8_t)0x07) /*!< PD[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */
+#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */
+#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */
+
+/******************* Bit definition for IWDG_RELV register *******************/
+#define IWDG_RELV_REL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_STS register ********************/
+#define IWDG_STS_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */
+#define IWDG_STS_CRVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CTRL register ********************/
+#define WWDG_CTRL_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CTRL_T0 ((uint8_t)0x01) /*!< Bit 0 */
+#define WWDG_CTRL_T1 ((uint8_t)0x02) /*!< Bit 1 */
+#define WWDG_CTRL_T2 ((uint8_t)0x04) /*!< Bit 2 */
+#define WWDG_CTRL_T3 ((uint8_t)0x08) /*!< Bit 3 */
+#define WWDG_CTRL_T4 ((uint8_t)0x10) /*!< Bit 4 */
+#define WWDG_CTRL_T5 ((uint8_t)0x20) /*!< Bit 5 */
+#define WWDG_CTRL_T6 ((uint8_t)0x40) /*!< Bit 6 */
+
+#define WWDG_CTRL_ACTB ((uint8_t)0x80) /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFG register *******************/
+#define WWDG_CFG_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFG_W0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define WWDG_CFG_W1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define WWDG_CFG_W2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define WWDG_CFG_W3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define WWDG_CFG_W4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define WWDG_CFG_W5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define WWDG_CFG_W6 ((uint16_t)0x0040) /*!< Bit 6 */
+
+#define WWDG_CFG_TIMERB ((uint16_t)0x0180) /*!< TIMERB[1:0] bits (Timer Base) */
+#define WWDG_CFG_TIMERB0 ((uint16_t)0x0080) /*!< Bit 0 */
+#define WWDG_CFG_TIMERB1 ((uint16_t)0x0100) /*!< Bit 1 */
+
+#define WWDG_CFG_EWINT ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_STS register ********************/
+#define WWDG_STS_EWINTF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Flexible Static Memory Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for XFMC_BCR1 register *******************/
+#define XFMC_BK1CSCTRL1_MBEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
+#define XFMC_BK1CSCTRL1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
+
+#define XFMC_BK1CSCTRL1_MTYPE ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
+#define XFMC_BK1CSCTRL1_MTYPE_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define XFMC_BK1CSCTRL1_MTYPE_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define XFMC_BK1CSCTRL1_MDBW ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
+#define XFMC_BK1CSCTRL1_MDBW_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK1CSCTRL1_MDBW_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define XFMC_BK1CSCTRL1_ACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
+#define XFMC_BK1CSCTRL1_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
+#define XFMC_BK1CSCTRL1_WAITDIR ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
+#define XFMC_BK1CSCTRL1_WRAPEN ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
+#define XFMC_BK1CSCTRL1_WCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
+#define XFMC_BK1CSCTRL1_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
+#define XFMC_BK1CSCTRL1_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
+#define XFMC_BK1CSCTRL1_EXTEN ((uint32_t)0x00004000) /*!< Extended mode enable */
+#define XFMC_BK1CSCTRL1_WAITASYNC ((uint32_t)0x00008000) /*!< Asynchronous wait */
+#define XFMC_BK1CSCTRL1_BURSTWREN ((uint32_t)0x00080000) /*!< Write burst enable */
+
+/****************** Bit definition for XFMC_BCR2 register *******************/
+#define XFMC_BK1CSCTRL2_MBEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
+#define XFMC_BK1CSCTRL2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
+
+#define XFMC_BK1CSCTRL2_MTYPE ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
+#define XFMC_BK1CSCTRL2_MTYPE_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define XFMC_BK1CSCTRL2_MTYPE_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define XFMC_BK1CSCTRL2_MDBW ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
+#define XFMC_BK1CSCTRL2_MDBW_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK1CSCTRL2_MDBW_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define XFMC_BK1CSCTRL2_ACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
+#define XFMC_BK1CSCTRL2_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
+#define XFMC_BK1CSCTRL2_WAITDIR ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
+#define XFMC_BK1CSCTRL2_WRAPEN ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
+#define XFMC_BK1CSCTRL2_WCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
+#define XFMC_BK1CSCTRL2_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
+#define XFMC_BK1CSCTRL2_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
+#define XFMC_BK1CSCTRL2_EXTEN ((uint32_t)0x00004000) /*!< Extended mode enable */
+#define XFMC_BK1CSCTRL2_WAITASYNC ((uint32_t)0x00008000) /*!< Asynchronous wait */
+#define XFMC_BK1CSCTRL2_BURSTWREN ((uint32_t)0x00080000) /*!< Write burst enable */
+
+/****************** Bit definition for XFMC_BTR1 register ******************/
+#define XFMC_BK1TM1_ADDBLD ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define XFMC_BK1TM1_ADDBLD_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_BK1TM1_ADDBLD_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_BK1TM1_ADDBLD_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_BK1TM1_ADDBLD_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define XFMC_BK1TM1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define XFMC_BK1TM1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK1TM1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define XFMC_BK1TM1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define XFMC_BK1TM1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define XFMC_BK1TM1_DATABLD ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define XFMC_BK1TM1_DATABLD_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_BK1TM1_DATABLD_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_BK1TM1_DATABLD_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_BK1TM1_DATABLD_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define XFMC_BK1TM1_BUSRECOVERY ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define XFMC_BK1TM1_BUSRECOVERY_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define XFMC_BK1TM1_BUSRECOVERY_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define XFMC_BK1TM1_BUSRECOVERY_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define XFMC_BK1TM1_BUSRECOVERY_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+
+#define XFMC_BK1TM1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define XFMC_BK1TM1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define XFMC_BK1TM1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define XFMC_BK1TM1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define XFMC_BK1TM1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define XFMC_BK1TM1_DATAHLD ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define XFMC_BK1TM1_DATAHLD_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_BK1TM1_DATAHLD_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_BK1TM1_DATAHLD_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_BK1TM1_DATAHLD_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define XFMC_BK1TM1_ACCMODE ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define XFMC_BK1TM1_ACCMODE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define XFMC_BK1TM1_ACCMODE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for XFMC_BTR2 register *******************/
+#define XFMC_BK1TM2_ADDBLD ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define XFMC_BK1TM2_ADDBLD_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_BK1TM2_ADDBLD_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_BK1TM2_ADDBLD_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_BK1TM2_ADDBLD_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define XFMC_BK1TM2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define XFMC_BK1TM2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK1TM2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define XFMC_BK1TM2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define XFMC_BK1TM2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define XFMC_BK1TM2_DATABLD ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define XFMC_BK1TM2_DATABLD_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_BK1TM2_DATABLD_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_BK1TM2_DATABLD_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_BK1TM2_DATABLD_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define XFMC_BK1TM2_BUSRECOVERY ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define XFMC_BK1TM2_BUSRECOVERY_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define XFMC_BK1TM2_BUSRECOVERY_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define XFMC_BK1TM2_BUSRECOVERY_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define XFMC_BK1TM2_BUSRECOVERY_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+
+#define XFMC_BK1TM2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define XFMC_BK1TM2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define XFMC_BK1TM2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define XFMC_BK1TM2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define XFMC_BK1TM2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define XFMC_BK1TM2_DATAHLD ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define XFMC_BK1TM2_DATAHLD_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_BK1TM2_DATAHLD_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_BK1TM2_DATAHLD_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_BK1TM2_DATAHLD_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define XFMC_BK1TM2_ACCMODE ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define XFMC_BK1TM2_ACCMODE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define XFMC_BK1TM2_ACCMODE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for XFMC_BWTR1 register ******************/
+#define XFMC_BK1WTM1_ADDBLD ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define XFMC_BK1WTM1_ADDBLD_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_BK1WTM1_ADDBLD_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_BK1WTM1_ADDBLD_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_BK1WTM1_ADDBLD_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define XFMC_BK1WTM1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define XFMC_BK1WTM1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK1WTM1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define XFMC_BK1WTM1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define XFMC_BK1WTM1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define XFMC_BK1WTM1_DATABLD ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define XFMC_BK1WTM1_DATABLD_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_BK1WTM1_DATABLD_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_BK1WTM1_DATABLD_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_BK1WTM1_DATABLD_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define XFMC_BK1WTM1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define XFMC_BK1WTM1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define XFMC_BK1WTM1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define XFMC_BK1WTM1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define XFMC_BK1WTM1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define XFMC_BK1WTM1_DATAHLD ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define XFMC_BK1WTM1_DATAHLD_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_BK1WTM1_DATAHLD_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_BK1WTM1_DATAHLD_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_BK1WTM1_DATAHLD_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define XFMC_BK1WTM1_ACCMODE ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define XFMC_BK1WTM1_ACCMODE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define XFMC_BK1WTM1_ACCMODE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for XFMC_BWTR2 register ******************/
+#define XFMC_BK1WTM2_ADDBLD ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define XFMC_BK1WTM2_ADDBLD_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_BK1WTM2_ADDBLD_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_BK1WTM2_ADDBLD_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_BK1WTM2_ADDBLD_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define XFMC_BK1WTM2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define XFMC_BK1WTM2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK1WTM2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define XFMC_BK1WTM2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define XFMC_BK1WTM2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define XFMC_BK1WTM2_DATABLD ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define XFMC_BK1WTM2_DATABLD_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_BK1WTM2_DATABLD_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_BK1WTM2_DATABLD_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_BK1WTM2_DATABLD_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define XFMC_BK1WTM2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define XFMC_BK1WTM2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define XFMC_BK1WTM2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1*/
+#define XFMC_BK1WTM2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define XFMC_BK1WTM2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define XFMC_BK1WTM2_DATAHLD ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define XFMC_BK1WTM2_DATAHLD_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_BK1WTM2_DATAHLD_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_BK1WTM2_DATAHLD_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_BK1WTM2_DATAHLD_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define XFMC_BK1WTM2_ACCMODE ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define XFMC_BK1WTM2_ACCMODE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define XFMC_BK1WTM2_ACCMODE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for XFMC_PCR2 register *******************/
+#define XFMC_BK2CTRL_WAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */
+#define XFMC_BK2CTRL_BANKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */
+#define XFMC_BK2CTRL_MEMTYPE ((uint32_t)0x00000008) /*!< Memory type */
+
+#define XFMC_BK2CTRL_BUSWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define XFMC_BK2CTRL_BUSWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK2CTRL_BUSWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define XFMC_BK2CTRL_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */
+
+#define XFMC_BK2CTRL_CRDLY ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define XFMC_BK2CTRL_CRDLY_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define XFMC_BK2CTRL_CRDLY_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define XFMC_BK2CTRL_CRDLY_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+#define XFMC_BK2CTRL_CRDLY_3 ((uint32_t)0x00001000) /*!< Bit 3 */
+
+#define XFMC_BK2CTRL_ARDLY ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */
+#define XFMC_BK2CTRL_ARDLY_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define XFMC_BK2CTRL_ARDLY_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define XFMC_BK2CTRL_ARDLY_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+#define XFMC_BK2CTRL_ARDLY_3 ((uint32_t)0x00010000) /*!< Bit 3 */
+
+#define XFMC_BK2CTRL_ECCPGS ((uint32_t)0x000E0000) /*!< ECCPS[1:0] bits (ECC page size) */
+#define XFMC_BK2CTRL_ECCPGS_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define XFMC_BK2CTRL_ECCPGS_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define XFMC_BK2CTRL_ECCPGS_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+
+/****************** Bit definition for XFMC_PCR3 register *******************/
+#define XFMC_BK3CTRL_WAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */
+#define XFMC_BK3CTRL_BANKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */
+#define XFMC_BK3CTRL_MEMTYPE ((uint32_t)0x00000008) /*!< Memory type */
+
+#define XFMC_BK3CTRL_BUSWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define XFMC_BK3CTRL_BUSWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK3CTRL_BUSWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define XFMC_BK3CTRL_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */
+
+#define XFMC_BK3CTRL_CRDLY ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define XFMC_BK3CTRL_CRDLY_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define XFMC_BK3CTRL_CRDLY_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define XFMC_BK3CTRL_CRDLY_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+#define XFMC_BK3CTRL_CRDLY_3 ((uint32_t)0x00001000) /*!< Bit 3 */
+
+#define XFMC_BK3CTRL_ARDLY ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */
+#define XFMC_BK3CTRL_ARDLY_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define XFMC_BK3CTRL_ARDLY_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define XFMC_BK3CTRL_ARDLY_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+#define XFMC_BK3CTRL_ARDLY_3 ((uint32_t)0x00010000) /*!< Bit 3 */
+
+#define XFMC_BK3CTRL_ECCPGS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */
+#define XFMC_BK3CTRL_ECCPGS_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define XFMC_BK3CTRL_ECCPGS_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define XFMC_BK3CTRL_ECCPGS_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+
+/******************* Bit definition for XFMC_SR2 register *******************/
+//#define XFMC_SR2_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */
+//#define XFMC_SR2_ILS ((uint8_t)0x02) /*!< Interrupt Level status */
+//#define XFMC_SR2_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */
+//#define XFMC_SR2_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable
+// bit */ #define XFMC_SR2_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection
+// Enable bit */ #define XFMC_SR2_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge
+// detection Enable bit */
+#define XFMC_STS2_FIFOEMPT ((uint8_t)0x40) /*!< DATFIFO empty */
+
+/******************* Bit definition for XFMC_SR3 register *******************/
+//#define XFMC_SR3_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */
+//#define XFMC_SR3_ILS ((uint8_t)0x02) /*!< Interrupt Level status */
+//#define XFMC_SR3_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */
+//#define XFMC_SR3_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable
+// bit */ #define XFMC_SR3_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection
+// Enable bit */ #define XFMC_SR3_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge
+// detection Enable bit */
+#define XFMC_STS3_FIFOEMPT ((uint8_t)0x40) /*!< DATFIFO empty */
+
+/****************** Bit definition for XFMC_PMEM2 register ******************/
+#define XFMC_CMEMTM2_SET ((uint32_t)0x000000FF) /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define XFMC_CMEMTM2_SET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_CMEMTM2_SET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_CMEMTM2_SET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_CMEMTM2_SET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define XFMC_CMEMTM2_SET_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define XFMC_CMEMTM2_SET_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define XFMC_CMEMTM2_SET_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define XFMC_CMEMTM2_SET_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define XFMC_CMEMTM2_WAIT ((uint32_t)0x0000FF00) /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define XFMC_CMEMTM2_WAIT_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_CMEMTM2_WAIT_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_CMEMTM2_WAIT_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_CMEMTM2_WAIT_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define XFMC_CMEMTM2_WAIT_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define XFMC_CMEMTM2_WAIT_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define XFMC_CMEMTM2_WAIT_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define XFMC_CMEMTM2_WAIT_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define XFMC_CMEMTM2_HLD ((uint32_t)0x00FF0000) /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define XFMC_CMEMTM2_HLD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define XFMC_CMEMTM2_HLD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define XFMC_CMEMTM2_HLD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define XFMC_CMEMTM2_HLD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define XFMC_CMEMTM2_HLD_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define XFMC_CMEMTM2_HLD_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define XFMC_CMEMTM2_HLD_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define XFMC_CMEMTM2_HLD_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+
+#define XFMC_CMEMTM2_HIZ ((uint32_t)0xFF000000) /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define XFMC_CMEMTM2_HIZ_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_CMEMTM2_HIZ_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_CMEMTM2_HIZ_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_CMEMTM2_HIZ_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define XFMC_CMEMTM2_HIZ_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define XFMC_CMEMTM2_HIZ_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define XFMC_CMEMTM2_HIZ_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define XFMC_CMEMTM2_HIZ_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/****************** Bit definition for XFMC_PMEM3 register ******************/
+#define XFMC_CMEMTM3_SET ((uint32_t)0x000000FF) /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define XFMC_CMEMTM3_SET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_CMEMTM3_SET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_CMEMTM3_SET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_CMEMTM3_SET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define XFMC_CMEMTM3_SET_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define XFMC_CMEMTM3_SET_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define XFMC_CMEMTM3_SET_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define XFMC_CMEMTM3_SET_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define XFMC_CMEMTM3_WAIT ((uint32_t)0x0000FF00) /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define XFMC_CMEMTM3_WAIT_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_CMEMTM3_WAIT_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_CMEMTM3_WAIT_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_CMEMTM3_WAIT_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define XFMC_CMEMTM3_WAIT_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define XFMC_CMEMTM3_WAIT_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define XFMC_CMEMTM3_WAIT_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define XFMC_CMEMTM3_WAIT_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define XFMC_CMEMTM3_HLD ((uint32_t)0x00FF0000) /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define XFMC_CMEMTM3_HLD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define XFMC_CMEMTM3_HLD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define XFMC_CMEMTM3_HLD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define XFMC_CMEMTM3_HLD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define XFMC_CMEMTM3_HLD_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define XFMC_CMEMTM3_HLD_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define XFMC_CMEMTM3_HLD_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define XFMC_CMEMTM3_HLD_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+
+#define XFMC_CMEMTM3_HIZ ((uint32_t)0xFF000000) /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define XFMC_CMEMTM3_HIZ_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_CMEMTM3_HIZ_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_CMEMTM3_HIZ_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_CMEMTM3_HIZ_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define XFMC_CMEMTM3_HIZ_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define XFMC_CMEMTM3_HIZ_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define XFMC_CMEMTM3_HIZ_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define XFMC_CMEMTM3_HIZ_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/****************** Bit definition for XFMC_PATT2 register ******************/
+#define XFMC_ATTMEMTM2_SET ((uint32_t)0x000000FF) /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define XFMC_ATTMEMTM2_SET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_ATTMEMTM2_SET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_ATTMEMTM2_SET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_ATTMEMTM2_SET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define XFMC_ATTMEMTM2_SET_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define XFMC_ATTMEMTM2_SET_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define XFMC_ATTMEMTM2_SET_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define XFMC_ATTMEMTM2_SET_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define XFMC_ATTMEMTM2_WAIT ((uint32_t)0x0000FF00) /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define XFMC_ATTMEMTM2_WAIT_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_ATTMEMTM2_WAIT_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_ATTMEMTM2_WAIT_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_ATTMEMTM2_WAIT_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define XFMC_ATTMEMTM2_WAIT_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define XFMC_ATTMEMTM2_WAIT_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define XFMC_ATTMEMTM2_WAIT_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define XFMC_ATTMEMTM2_WAIT_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define XFMC_ATTMEMTM2_HLD ((uint32_t)0x00FF0000) /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define XFMC_ATTMEMTM2_HLD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define XFMC_ATTMEMTM2_HLD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define XFMC_ATTMEMTM2_HLD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define XFMC_ATTMEMTM2_HLD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define XFMC_ATTMEMTM2_HLD_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define XFMC_ATTMEMTM2_HLD_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define XFMC_ATTMEMTM2_HLD_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define XFMC_ATTMEMTM2_HLD_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+
+#define XFMC_ATTMEMTM2_HIZ ((uint32_t)0xFF000000) /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define XFMC_ATTMEMTM2_HIZ_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_ATTMEMTM2_HIZ_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_ATTMEMTM2_HIZ_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_ATTMEMTM2_HIZ_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define XFMC_ATTMEMTM2_HIZ_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define XFMC_ATTMEMTM2_HIZ_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define XFMC_ATTMEMTM2_HIZ_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define XFMC_ATTMEMTM2_HIZ_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/****************** Bit definition for XFMC_PATT3 register ******************/
+#define XFMC_ATTMEMTM3_SET ((uint32_t)0x000000FF) /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define XFMC_ATTMEMTM3_SET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_ATTMEMTM3_SET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_ATTMEMTM3_SET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_ATTMEMTM3_SET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define XFMC_ATTMEMTM3_SET_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define XFMC_ATTMEMTM3_SET_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define XFMC_ATTMEMTM3_SET_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define XFMC_ATTMEMTM3_SET_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define XFMC_ATTMEMTM3_WAIT ((uint32_t)0x0000FF00) /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define XFMC_ATTMEMTM3_WAIT_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_ATTMEMTM3_WAIT_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_ATTMEMTM3_WAIT_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_ATTMEMTM3_WAIT_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define XFMC_ATTMEMTM3_WAIT_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define XFMC_ATTMEMTM3_WAIT_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define XFMC_ATTMEMTM3_WAIT_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define XFMC_ATTMEMTM3_WAIT_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define XFMC_ATTMEMTM3_HLD ((uint32_t)0x00FF0000) /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define XFMC_ATTMEMTM3_HLD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define XFMC_ATTMEMTM3_HLD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define XFMC_ATTMEMTM3_HLD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define XFMC_ATTMEMTM3_HLD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define XFMC_ATTMEMTM3_HLD_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define XFMC_ATTMEMTM3_HLD_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define XFMC_ATTMEMTM3_HLD_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define XFMC_ATTMEMTM3_HLD_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+
+#define XFMC_ATTMEMTM3_HIZ ((uint32_t)0xFF000000) /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define XFMC_ATTMEMTM3_HIZ_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_ATTMEMTM3_HIZ_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_ATTMEMTM3_HIZ_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_ATTMEMTM3_HIZ_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define XFMC_ATTMEMTM3_HIZ_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define XFMC_ATTMEMTM3_HIZ_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define XFMC_ATTMEMTM3_HIZ_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define XFMC_ATTMEMTM3_HIZ_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/****************** Bit definition for XFMC_ECCR2 register ******************/
+#define XFMC_ECCR2 ((uint32_t)0xFFFFFFFF) /*!< ECC result */
+
+/****************** Bit definition for XFMC_ECCR3 register ******************/
+#define XFMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!< ECC result */
+
+/******************************************************************************/
+/* */
+/* USB Device FS */
+/* */
+/******************************************************************************/
+
+/*!< Endpoint-specific registers */
+/******************* Bit definition for USB_EP0R register *******************/
+#define USB_EP0_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP0_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP0_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP0_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP0_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP0_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP0_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP0_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP0_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP0_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP0_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP0_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP0_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP0_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP0_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP0_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP1R register *******************/
+#define USB_EP1_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP1_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP1_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP1_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP1_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP1_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP1_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP1_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP1_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP1_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP1_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP1_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP1_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP1_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP1_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP1_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP2R register *******************/
+#define USB_EP2_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP2_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP2_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP2_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP2_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP2_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP2_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP2_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP2_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP2_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP2_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP2_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP2_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP2_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP2_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP2_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP3R register *******************/
+#define USB_EP3_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP3_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP3_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP3_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP3_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP3_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP3_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP3_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP3_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP3_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP3_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP3_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP3_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP3_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP3_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP3_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP4R register *******************/
+#define USB_EP4_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP4_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP4_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP4_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP4_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP4_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP4_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP4_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP4_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP4_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP4_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP4_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP4_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP4_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP4_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP4_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP5R register *******************/
+#define USB_EP5_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP5_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP5_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP5_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP5_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP5_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP5_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP5_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP5_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP5_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP5_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP5_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP5_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP5_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP5_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP5_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP6R register *******************/
+#define USB_EP6_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP6_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP6_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP6_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP6_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP6_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP6_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP6_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP6_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP6_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP6_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP6_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP6_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP6_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP6_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP6_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP7R register *******************/
+#define USB_EP7_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP7_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP7_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP7_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP7_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP7_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP7_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP7_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP7_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP7_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP7_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP7_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP7_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP7_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP7_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP7_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/*!< Common registers */
+/******************* Bit definition for USB_CNTR register *******************/
+#define USB_CTRL_FRST ((uint16_t)0x0001) /*!< Force USB Reset */
+#define USB_CTRL_PD ((uint16_t)0x0002) /*!< Power down */
+#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power mode */
+#define USB_CTRL_FSUSPD ((uint16_t)0x0008) /*!< Force suspend */
+#define USB_CTRL_RESUM ((uint16_t)0x0010) /*!< Resume request */
+#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Interrupt Mask */
+#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Interrupt Mask */
+#define USB_CTRL_RSTM ((uint16_t)0x0400) /*!< RESET Interrupt Mask */
+#define USB_CTRL_SUSPDM ((uint16_t)0x0800) /*!< Suspend mode Interrupt Mask */
+#define USB_CTRL_WKUPM ((uint16_t)0x1000) /*!< Wakeup Interrupt Mask */
+#define USB_CTRL_ERRORM ((uint16_t)0x2000) /*!< Error Interrupt Mask */
+#define USB_CTRL_PMAOM ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun Interrupt Mask */
+#define USB_CTRL_CTRSM ((uint16_t)0x8000) /*!< Correct Transfer Interrupt Mask */
+
+/******************* Bit definition for USB_ISTR register *******************/
+#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< Endpoint Identifier */
+#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< Direction of transaction */
+#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame */
+#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame */
+#define USB_STS_RST ((uint16_t)0x0400) /*!< USB RESET request */
+#define USB_STS_SUSPD ((uint16_t)0x0800) /*!< Suspend mode request */
+#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< Wake up */
+#define USB_STS_ERROR ((uint16_t)0x2000) /*!< Error */
+#define USB_STS_PMAO ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun */
+#define USB_STS_CTRS ((uint16_t)0x8000) /*!< Correct Transfer */
+
+/******************* Bit definition for USB_FNR register ********************/
+#define USB_FN_FNUM ((uint16_t)0x07FF) /*!< Frame Number */
+#define USB_FN_LSTSOF ((uint16_t)0x1800) /*!< Lost SOF */
+#define USB_FNR_LCK ((uint16_t)0x2000) /*!< Locked */
+#define USB_FN_RXDM_STS ((uint16_t)0x4000) /*!< Receive Data - Line Status */
+#define USB_FN_RXDP_STS ((uint16_t)0x8000) /*!< Receive Data + Line Status */
+
+/****************** Bit definition for USB_DADDR register *******************/
+#define USB_ADDR_ADDR ((uint8_t)0x7F) /*!< ADD[6:0] bits (Device Address) */
+#define USB_ADDR_ADDR0 ((uint8_t)0x01) /*!< Bit 0 */
+#define USB_ADDR_ADDR1 ((uint8_t)0x02) /*!< Bit 1 */
+#define USB_ADDR_ADDR2 ((uint8_t)0x04) /*!< Bit 2 */
+#define USB_ADDR_ADDR3 ((uint8_t)0x08) /*!< Bit 3 */
+#define USB_ADDR_ADDR4 ((uint8_t)0x10) /*!< Bit 4 */
+#define USB_ADDR_ADDR5 ((uint8_t)0x20) /*!< Bit 5 */
+#define USB_ADDR_ADDR6 ((uint8_t)0x40) /*!< Bit 6 */
+
+#define USB_ADDR_EFUC ((uint8_t)0x80) /*!< Enable Function */
+
+/****************** Bit definition for USB_BTABLE register ******************/
+#define USB_BUFTAB_BUFTAB ((uint16_t)0xFFF8) /*!< Buffer Table */
+
+/*!< Buffer descriptor table */
+/***************** Bit definition for USB_ADDR0_TX register *****************/
+#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_TX register *****************/
+#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_TX register *****************/
+#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_TX register *****************/
+#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_TX register *****************/
+#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_TX register *****************/
+#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_TX register *****************/
+#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_TX register *****************/
+#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_TX register ****************/
+#define USB_CNT0_TX_CNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */
+
+/***************** Bit definition for USB_COUNT1_TX register ****************/
+#define USB_CNT1_TX_CNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */
+
+/***************** Bit definition for USB_COUNT2_TX register ****************/
+#define USB_CNT2_TX_CNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */
+
+/***************** Bit definition for USB_COUNT3_TX register ****************/
+#define USB_CNT3_TX_CNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */
+
+/***************** Bit definition for USB_COUNT4_TX register ****************/
+#define USB_CNT4_TX_CNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */
+
+/***************** Bit definition for USB_COUNT5_TX register ****************/
+#define USB_CNT5_TX_CNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */
+
+/***************** Bit definition for USB_COUNT6_TX register ****************/
+#define USB_CNT6_TX_CNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */
+
+/***************** Bit definition for USB_COUNT7_TX register ****************/
+#define USB_CNT7_TX_CNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
+#define USB_CNT0_TX_0_CNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
+
+/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
+#define USB_CNT0_TX_1_CNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
+
+/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
+#define USB_CNT1_TX_0_CNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
+
+/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
+#define USB_CNT1_TX_1_CNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
+
+/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
+#define USB_CNT2_TX_0_CNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
+
+/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
+#define USB_CNT2_TX_1_CNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
+
+/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
+#define USB_CNT3_TX_0_CNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */
+
+/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
+#define USB_CNT3_TX_1_CNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */
+
+/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
+#define USB_CNT4_TX_0_CNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
+
+/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
+#define USB_CNT4_TX_1_CNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
+
+/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
+#define USB_CNT5_TX_0_CNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
+
+/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
+#define USB_CNT5_TX_1_CNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
+
+/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
+#define USB_CNT6_TX_0_CNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
+
+/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
+#define USB_CNT6_TX_1_CNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
+
+/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
+#define USB_CNT7_TX_0_CNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
+
+/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
+#define USB_CNT7_TX_1_CNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_ADDR0_RX register *****************/
+#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_RX register *****************/
+#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_RX register *****************/
+#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_RX register *****************/
+#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_RX register *****************/
+#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_RX register *****************/
+#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_RX register *****************/
+#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_RX register *****************/
+#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_RX register ****************/
+#define USB_CNT0_RX_CNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT0_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT0_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT0_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT0_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT0_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT0_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT1_RX register ****************/
+#define USB_CNT1_RX_CNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT1_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT1_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT1_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT1_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT1_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT1_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT2_RX register ****************/
+#define USB_CNT2_RX_CNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT2_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT2_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT2_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT2_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT2_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT2_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT3_RX register ****************/
+#define USB_CNT3_RX_CNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT3_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT3_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT3_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT3_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT3_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT3_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT4_RX register ****************/
+#define USB_CNT4_RX_CNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT4_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT4_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT4_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT4_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT4_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT4_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT5_RX register ****************/
+#define USB_CNT5_RX_CNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT5_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT5_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT5_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT5_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT5_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT5_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT6_RX register ****************/
+#define USB_CNT6_RX_CNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT6_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT6_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT6_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT6_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT6_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT6_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT7_RX register ****************/
+#define USB_CNT7_RX_CNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT7_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT7_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT7_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT7_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT7_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT7_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
+#define USB_CNT0_RX_0_CNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT0_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT0_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT0_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT0_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT0_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT0_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
+#define USB_CNT0_RX_1_CNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT0_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT0_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define USB_CNT0_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT0_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT0_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT0_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
+#define USB_CNT1_RX_0_CNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT1_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT1_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT1_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT1_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT1_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT1_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
+#define USB_CNT1_RX_1_CNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT1_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT1_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_CNT1_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT1_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT1_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT1_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
+#define USB_CNT2_RX_0_CNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT2_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT2_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT2_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT2_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT2_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT2_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
+#define USB_CNT2_RX_1_CNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT2_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT2_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_CNT2_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT2_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT2_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT2_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
+#define USB_CNT3_RX_0_CNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT3_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT3_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT3_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT3_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT3_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT3_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
+#define USB_CNT3_RX_1_CNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT3_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT3_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_CNT3_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT3_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT3_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT3_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
+#define USB_CNT4_RX_0_CNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT4_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT4_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT4_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT4_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT4_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT4_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
+#define USB_CNT4_RX_1_CNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT4_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT4_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_CNT4_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT4_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT4_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT4_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
+#define USB_CNT5_RX_0_CNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT5_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT5_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT5_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT5_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT5_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT5_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
+#define USB_CNT5_RX_1_CNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT5_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT5_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_CNT5_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT5_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT5_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT5_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
+#define USB_CNT6_RX_0_CNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT6_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT6_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT6_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT6_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT6_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT6_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
+#define USB_CNT6_RX_1_CNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT6_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT6_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_CNT6_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT6_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT6_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT6_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
+#define USB_CNT7_RX_0_CNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT7_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT7_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT7_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT7_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT7_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT7_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
+#define USB_CNT7_RX_1_CNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT7_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT7_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_CNT7_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT7_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT7_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT7_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+
+/*!< CAN control and status registers */
+/******************* Bit definition for CAN_MCTRL register ********************/
+#define CAN_MCTRL_INIRQ ((uint16_t)0x0001) /*!< Initialization Request */
+#define CAN_MCTRL_SLPRQ ((uint16_t)0x0002) /*!< Sleep Mode Request */
+#define CAN_MCTRL_TXFP ((uint16_t)0x0004) /*!< Transmit DATFIFO Priority */
+#define CAN_MCTRL_RFLM ((uint16_t)0x0008) /*!< Receive DATFIFO Locked Mode */
+#define CAN_MCTRL_NART ((uint16_t)0x0010) /*!< No Automatic Retransmission */
+#define CAN_MCTRL_AWKUM ((uint16_t)0x0020) /*!< Automatic Wakeup Mode */
+#define CAN_MCTRL_ABOM ((uint16_t)0x0040) /*!< Automatic Bus-Off Management */
+#define CAN_MCTRL_TTCM ((uint16_t)0x0080) /*!< Time Triggered Communication Mode */
+#define CAN_MCTRL_MRST ((uint16_t)0x8000) /*!< CAN software master reset */
+#define CAN_MCTRL_DBGF ((uint32_t)0x00010000) /*!< CAN Debug freeze */
+
+/******************* Bit definition for CAN_MSTS register ********************/
+#define CAN_MSTS_INIAK ((uint16_t)0x0001) /*!< Initialization Acknowledge */
+#define CAN_MSTS_SLPAK ((uint16_t)0x0002) /*!< Sleep Acknowledge */
+#define CAN_MSTS_ERRINT ((uint16_t)0x0004) /*!< Error Interrupt */
+#define CAN_MSTS_WKUINT ((uint16_t)0x0008) /*!< Wakeup Interrupt */
+#define CAN_MSTS_SLAKINT ((uint16_t)0x0010) /*!< Sleep Acknowledge Interrupt */
+#define CAN_MSTS_TXMD ((uint16_t)0x0100) /*!< Transmit Mode */
+#define CAN_MSTS_RXMD ((uint16_t)0x0200) /*!< Receive Mode */
+#define CAN_MSTS_LSMP ((uint16_t)0x0400) /*!< Last Sample Point */
+#define CAN_MSTS_RXS ((uint16_t)0x0800) /*!< CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSTS register ********************/
+#define CAN_TSTS_RQCPM0 ((uint32_t)0x00000001) /*!< Request Completed Mailbox0 */
+#define CAN_TSTS_TXOKM0 ((uint32_t)0x00000002) /*!< Transmission OK of Mailbox0 */
+#define CAN_TSTS_ALSTM0 ((uint32_t)0x00000004) /*!< Arbitration Lost for Mailbox0 */
+#define CAN_TSTS_TERRM0 ((uint32_t)0x00000008) /*!< Transmission Error of Mailbox0 */
+#define CAN_TSTS_ABRQM0 ((uint32_t)0x00000080) /*!< Abort Request for Mailbox0 */
+#define CAN_TSTS_RQCPM1 ((uint32_t)0x00000100) /*!< Request Completed Mailbox1 */
+#define CAN_TSTS_TXOKM1 ((uint32_t)0x00000200) /*!< Transmission OK of Mailbox1 */
+#define CAN_TSTS_ALSTM1 ((uint32_t)0x00000400) /*!< Arbitration Lost for Mailbox1 */
+#define CAN_TSTS_TERRM1 ((uint32_t)0x00000800) /*!< Transmission Error of Mailbox1 */
+#define CAN_TSTS_ABRQM1 ((uint32_t)0x00008000) /*!< Abort Request for Mailbox 1 */
+#define CAN_TSTS_RQCPM2 ((uint32_t)0x00010000) /*!< Request Completed Mailbox2 */
+#define CAN_TSTS_TXOKM2 ((uint32_t)0x00020000) /*!< Transmission OK of Mailbox 2 */
+#define CAN_TSTS_ALSTM2 ((uint32_t)0x00040000) /*!< Arbitration Lost for mailbox 2 */
+#define CAN_TSTS_TERRM2 ((uint32_t)0x00080000) /*!< Transmission Error of Mailbox 2 */
+#define CAN_TSTS_ABRQM2 ((uint32_t)0x00800000) /*!< Abort Request for Mailbox 2 */
+#define CAN_TSTS_CODE ((uint32_t)0x03000000) /*!< Mailbox Code */
+
+#define CAN_TSTS_TMEM ((uint32_t)0x1C000000) /*!< TME[2:0] bits */
+#define CAN_TSTS_TMEM0 ((uint32_t)0x04000000) /*!< Transmit Mailbox 0 Empty */
+#define CAN_TSTS_TMEM1 ((uint32_t)0x08000000) /*!< Transmit Mailbox 1 Empty */
+#define CAN_TSTS_TMEM2 ((uint32_t)0x10000000) /*!< Transmit Mailbox 2 Empty */
+
+#define CAN_TSTS_LOWM ((uint32_t)0xE0000000) /*!< LOW[2:0] bits */
+#define CAN_TSTS_LOWM0 ((uint32_t)0x20000000) /*!< Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSTS_LOWM1 ((uint32_t)0x40000000) /*!< Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSTS_LOWM2 ((uint32_t)0x80000000) /*!< Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RFF0 register *******************/
+#define CAN_RFF0_FFMP0 ((uint8_t)0x03) /*!< DATFIFO 0 Message Pending */
+#define CAN_RFF0_FFULL0 ((uint8_t)0x08) /*!< DATFIFO 0 Full */
+#define CAN_RFF0_FFOVR0 ((uint8_t)0x10) /*!< DATFIFO 0 Overrun */
+#define CAN_RFF0_RFFOM0 ((uint8_t)0x20) /*!< Release DATFIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RFF1 register *******************/
+#define CAN_RFF1_FFMP1 ((uint8_t)0x03) /*!< DATFIFO 1 Message Pending */
+#define CAN_RFF1_FFULL1 ((uint8_t)0x08) /*!< DATFIFO 1 Full */
+#define CAN_RFF1_FFOVR1 ((uint8_t)0x10) /*!< DATFIFO 1 Overrun */
+#define CAN_RFF1_RFFOM1 ((uint8_t)0x20) /*!< Release DATFIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_INTE register *******************/
+#define CAN_INTE_TMEITE ((uint32_t)0x00000001) /*!< Transmit Mailbox Empty Interrupt Enable */
+#define CAN_INTE_FMPITE0 ((uint32_t)0x00000002) /*!< DATFIFO Message Pending Interrupt Enable */
+#define CAN_INTE_FFITE0 ((uint32_t)0x00000004) /*!< DATFIFO Full Interrupt Enable */
+#define CAN_INTE_FOVITE0 ((uint32_t)0x00000008) /*!< DATFIFO Overrun Interrupt Enable */
+#define CAN_INTE_FMPITE1 ((uint32_t)0x00000010) /*!< DATFIFO Message Pending Interrupt Enable */
+#define CAN_INTE_FFITE1 ((uint32_t)0x00000020) /*!< DATFIFO Full Interrupt Enable */
+#define CAN_INTE_FOVITE1 ((uint32_t)0x00000040) /*!< DATFIFO Overrun Interrupt Enable */
+#define CAN_INTE_EWGITE ((uint32_t)0x00000100) /*!< Error Warning Interrupt Enable */
+#define CAN_INTE_EPVITE ((uint32_t)0x00000200) /*!< Error Passive Interrupt Enable */
+#define CAN_INTE_BOFITE ((uint32_t)0x00000400) /*!< Bus-Off Interrupt Enable */
+#define CAN_INTE_LECITE ((uint32_t)0x00000800) /*!< Last Error Code Interrupt Enable */
+#define CAN_INTE_ERRITE ((uint32_t)0x00008000) /*!< Error Interrupt Enable */
+#define CAN_INTE_WKUITE ((uint32_t)0x00010000) /*!< Wakeup Interrupt Enable */
+#define CAN_INTE_SLKITE ((uint32_t)0x00020000) /*!< Sleep Interrupt Enable */
+
+/******************** Bit definition for CAN_ESTS register *******************/
+#define CAN_ESTS_EWGFL ((uint32_t)0x00000001) /*!< Error Warning Flag */
+#define CAN_ESTS_EPVFL ((uint32_t)0x00000002) /*!< Error Passive Flag */
+#define CAN_ESTS_BOFFL ((uint32_t)0x00000004) /*!< Bus-Off Flag */
+
+#define CAN_ESTS_LEC ((uint32_t)0x00000070) /*!< LEC[2:0] bits (Last Error Code) */
+#define CAN_ESTS_LEC_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define CAN_ESTS_LEC_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define CAN_ESTS_LEC_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+
+#define CAN_ESTS_TXEC ((uint32_t)0x00FF0000) /*!< Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESTS_RXEC ((uint32_t)0xFF000000) /*!< Receive Error Counter */
+
+/******************* Bit definition for CAN_BTIM register ********************/
+#define CAN_BTIM_BRTP ((uint32_t)0x000003FF) /*!< Baud Rate Prescaler */
+#define CAN_BTIM_TBS1 ((uint32_t)0x000F0000) /*!< Time Segment 1 */
+#define CAN_BTIM_TBS2 ((uint32_t)0x00700000) /*!< Time Segment 2 */
+#define CAN_BTIM_RSJW ((uint32_t)0x03000000) /*!< Resynchronization Jump Width */
+#define CAN_BTIM_LBM ((uint32_t)0x40000000) /*!< Loop Back Mode (Debug) */
+#define CAN_BTIM_SLM ((uint32_t)0x80000000) /*!< Silent Mode */
+
+/*!< Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TMI0_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
+#define CAN_TMI0_RTRQ ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_TMI0_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_TMI0_EXTID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
+#define CAN_TMI0_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TMDT0_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_TMDT0_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */
+#define CAN_TMDT0_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TMDL0_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_TMDL0_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_TMDL0_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_TMDL0_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TMDH0_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_TMDH0_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_TMDH0_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_TMDH0_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TMI1_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
+#define CAN_TMI1_RTRQ ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_TMI1_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_TMI1_EXTID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
+#define CAN_TMI1_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TMDT1_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_TMDT1_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */
+#define CAN_TMDT1_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TMDL1_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_TMDL1_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_TMDL1_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_TMDL1_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TMDH1_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_TMDH1_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_TMDH1_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_TMDH1_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TMI2_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
+#define CAN_TMI2_RTRQ ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_TMI2_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_TMI2_EXTID ((uint32_t)0x001FFFF8) /*!< Extended identifier */
+#define CAN_TMI2_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TMDT2_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_TMDT2_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */
+#define CAN_TMDT2_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TMDL2_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_TMDL2_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_TMDL2_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_TMDL2_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TMDH2_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_TMDH2_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_TMDH2_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_TMDH2_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RMI0_RTRQ ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_RMI0_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_RMI0_EXTID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
+#define CAN_RMI0_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RMDT0_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_RMDT0_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */
+#define CAN_RMDT0_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RMDL0_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_RMDL0_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_RMDL0_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_RMDL0_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RMDH0_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_RMDH0_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_RMDH0_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_RMDH0_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RMI1_RTRQ ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_RMI1_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_RMI1_EXTID ((uint32_t)0x001FFFF8) /*!< Extended identifier */
+#define CAN_RMI1_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RMDT1_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_RMDT1_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */
+#define CAN_RMDT1_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RMDL1_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_RMDL1_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_RMDL1_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_RMDL1_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RMDH1_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_RMDH1_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_RMDH1_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_RMDH1_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/*!< CAN filter registers */
+/******************* Bit definition for CAN_FMC register ********************/
+#define CAN_FMC_FINITM ((uint8_t)0x01) /*!< Filter Init Mode */
+
+/******************* Bit definition for CAN_FM1 register *******************/
+#define CAN_FM1_FB ((uint16_t)0x3FFF) /*!< Filter Mode */
+#define CAN_FM1_FB0 ((uint16_t)0x0001) /*!< Filter Init Mode bit 0 */
+#define CAN_FM1_FB1 ((uint16_t)0x0002) /*!< Filter Init Mode bit 1 */
+#define CAN_FM1_FB2 ((uint16_t)0x0004) /*!< Filter Init Mode bit 2 */
+#define CAN_FM1_FB3 ((uint16_t)0x0008) /*!< Filter Init Mode bit 3 */
+#define CAN_FM1_FB4 ((uint16_t)0x0010) /*!< Filter Init Mode bit 4 */
+#define CAN_FM1_FB5 ((uint16_t)0x0020) /*!< Filter Init Mode bit 5 */
+#define CAN_FM1_FB6 ((uint16_t)0x0040) /*!< Filter Init Mode bit 6 */
+#define CAN_FM1_FB7 ((uint16_t)0x0080) /*!< Filter Init Mode bit 7 */
+#define CAN_FM1_FB8 ((uint16_t)0x0100) /*!< Filter Init Mode bit 8 */
+#define CAN_FM1_FB9 ((uint16_t)0x0200) /*!< Filter Init Mode bit 9 */
+#define CAN_FM1_FB10 ((uint16_t)0x0400) /*!< Filter Init Mode bit 10 */
+#define CAN_FM1_FB11 ((uint16_t)0x0800) /*!< Filter Init Mode bit 11 */
+#define CAN_FM1_FB12 ((uint16_t)0x1000) /*!< Filter Init Mode bit 12 */
+#define CAN_FM1_FB13 ((uint16_t)0x2000) /*!< Filter Init Mode bit 13 */
+
+/******************* Bit definition for CAN_FS1 register *******************/
+#define CAN_FS1_FSC ((uint16_t)0x3FFF) /*!< Filter Scale Configuration */
+#define CAN_FS1_FSC0 ((uint16_t)0x0001) /*!< Filter Scale Configuration bit 0 */
+#define CAN_FS1_FSC1 ((uint16_t)0x0002) /*!< Filter Scale Configuration bit 1 */
+#define CAN_FS1_FSC2 ((uint16_t)0x0004) /*!< Filter Scale Configuration bit 2 */
+#define CAN_FS1_FSC3 ((uint16_t)0x0008) /*!< Filter Scale Configuration bit 3 */
+#define CAN_FS1_FSC4 ((uint16_t)0x0010) /*!< Filter Scale Configuration bit 4 */
+#define CAN_FS1_FSC5 ((uint16_t)0x0020) /*!< Filter Scale Configuration bit 5 */
+#define CAN_FS1_FSC6 ((uint16_t)0x0040) /*!< Filter Scale Configuration bit 6 */
+#define CAN_FS1_FSC7 ((uint16_t)0x0080) /*!< Filter Scale Configuration bit 7 */
+#define CAN_FS1_FSC8 ((uint16_t)0x0100) /*!< Filter Scale Configuration bit 8 */
+#define CAN_FS1_FSC9 ((uint16_t)0x0200) /*!< Filter Scale Configuration bit 9 */
+#define CAN_FS1_FSC10 ((uint16_t)0x0400) /*!< Filter Scale Configuration bit 10 */
+#define CAN_FS1_FSC11 ((uint16_t)0x0800) /*!< Filter Scale Configuration bit 11 */
+#define CAN_FS1_FSC12 ((uint16_t)0x1000) /*!< Filter Scale Configuration bit 12 */
+#define CAN_FS1_FSC13 ((uint16_t)0x2000) /*!< Filter Scale Configuration bit 13 */
+
+/****************** Bit definition for CAN_FFA1 register *******************/
+#define CAN_FFA1_FAF ((uint16_t)0x3FFF) /*!< Filter DATFIFO Assignment */
+#define CAN_FFA1_FAF0 ((uint16_t)0x0001) /*!< Filter DATFIFO Assignment for Filter 0 */
+#define CAN_FFA1_FAF1 ((uint16_t)0x0002) /*!< Filter DATFIFO Assignment for Filter 1 */
+#define CAN_FFA1_FAF2 ((uint16_t)0x0004) /*!< Filter DATFIFO Assignment for Filter 2 */
+#define CAN_FFA1_FAF3 ((uint16_t)0x0008) /*!< Filter DATFIFO Assignment for Filter 3 */
+#define CAN_FFA1_FAF4 ((uint16_t)0x0010) /*!< Filter DATFIFO Assignment for Filter 4 */
+#define CAN_FFA1_FAF5 ((uint16_t)0x0020) /*!< Filter DATFIFO Assignment for Filter 5 */
+#define CAN_FFA1_FAF6 ((uint16_t)0x0040) /*!< Filter DATFIFO Assignment for Filter 6 */
+#define CAN_FFA1_FAF7 ((uint16_t)0x0080) /*!< Filter DATFIFO Assignment for Filter 7 */
+#define CAN_FFA1_FAF8 ((uint16_t)0x0100) /*!< Filter DATFIFO Assignment for Filter 8 */
+#define CAN_FFA1_FAF9 ((uint16_t)0x0200) /*!< Filter DATFIFO Assignment for Filter 9 */
+#define CAN_FFA1_FAF10 ((uint16_t)0x0400) /*!< Filter DATFIFO Assignment for Filter 10 */
+#define CAN_FFA1_FAF11 ((uint16_t)0x0800) /*!< Filter DATFIFO Assignment for Filter 11 */
+#define CAN_FFA1_FAF12 ((uint16_t)0x1000) /*!< Filter DATFIFO Assignment for Filter 12 */
+#define CAN_FFA1_FAF13 ((uint16_t)0x2000) /*!< Filter DATFIFO Assignment for Filter 13 */
+
+/******************* Bit definition for CAN_FA1 register *******************/
+#define CAN_FA1_FAC ((uint16_t)0x3FFF) /*!< Filter Active */
+#define CAN_FA1_FAC0 ((uint16_t)0x0001) /*!< Filter 0 Active */
+#define CAN_FA1_FAC1 ((uint16_t)0x0002) /*!< Filter 1 Active */
+#define CAN_FA1_FAC2 ((uint16_t)0x0004) /*!< Filter 2 Active */
+#define CAN_FA1_FAC3 ((uint16_t)0x0008) /*!< Filter 3 Active */
+#define CAN_FA1_FAC4 ((uint16_t)0x0010) /*!< Filter 4 Active */
+#define CAN_FA1_FAC5 ((uint16_t)0x0020) /*!< Filter 5 Active */
+#define CAN_FA1_FAC6 ((uint16_t)0x0040) /*!< Filter 6 Active */
+#define CAN_FA1_FAC7 ((uint16_t)0x0080) /*!< Filter 7 Active */
+#define CAN_FA1_FAC8 ((uint16_t)0x0100) /*!< Filter 8 Active */
+#define CAN_FA1_FAC9 ((uint16_t)0x0200) /*!< Filter 9 Active */
+#define CAN_FA1_FAC10 ((uint16_t)0x0400) /*!< Filter 10 Active */
+#define CAN_FA1_FAC11 ((uint16_t)0x0800) /*!< Filter 11 Active */
+#define CAN_FA1_FAC12 ((uint16_t)0x1000) /*!< Filter 12 Active */
+#define CAN_FA1_FAC13 ((uint16_t)0x2000) /*!< Filter 13 Active */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F0B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F0B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F0B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F0B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F0B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F0B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F0B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F0B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F0B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F0B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F0B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F0B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F0B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F0B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F0B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F0B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F0B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F0B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F0B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F0B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F0B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F0B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F0B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F0B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F0B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F0B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F0B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F0B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F0B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F0B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F0B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F1B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F1B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F1B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F1B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F1B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F1B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F1B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F1B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F1B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F1B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F1B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F1B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F1B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F1B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F1B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F1B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F1B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F1B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F1B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F1B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F1B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F1B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F1B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F1B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F1B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F1B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F1B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F1B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F1B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F1B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F1B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F2B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F2B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F2B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F2B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F2B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F2B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F2B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F2B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F2B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F2B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F2B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F2B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F2B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F2B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F2B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F2B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F2B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F2B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F2B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F2B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F2B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F2B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F2B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F2B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F2B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F2B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F2B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F2B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F2B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F2B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F2B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F3B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F3B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F3B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F3B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F3B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F3B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F3B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F3B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F3B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F3B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F3B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F3B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F3B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F3B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F3B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F3B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F3B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F3B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F3B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F3B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F3B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F3B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F3B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F3B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F3B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F3B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F3B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F3B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F3B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F3B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F3B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F4B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F4B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F4B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F4B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F4B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F4B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F4B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F4B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F4B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F4B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F4B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F4B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F4B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F4B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F4B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F4B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F4B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F4B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F4B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F4B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F4B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F4B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F4B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F4B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F4B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F4B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F4B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F4B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F4B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F4B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F4B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F5B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F5B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F5B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F5B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F5B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F5B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F5B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F5B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F5B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F5B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F5B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F5B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F5B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F5B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F5B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F5B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F5B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F5B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F5B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F5B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F5B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F5B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F5B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F5B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F5B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F5B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F5B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F5B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F5B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F5B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F5B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F6B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F6B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F6B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F6B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F6B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F6B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F6B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F6B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F6B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F6B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F6B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F6B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F6B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F6B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F6B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F6B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F6B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F6B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F6B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F6B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F6B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F6B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F6B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F6B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F6B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F6B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F6B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F6B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F6B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F6B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F6B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F7B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F7B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F7B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F7B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F7B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F7B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F7B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F7B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F7B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F7B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F7B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F7B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F7B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F7B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F7B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F7B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F7B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F7B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F7B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F7B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F7B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F7B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F7B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F7B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F7B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F7B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F7B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F7B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F7B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F7B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F7B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F8B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F8B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F8B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F8B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F8B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F8B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F8B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F8B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F8B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F8B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F8B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F8B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F8B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F8B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F8B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F8B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F8B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F8B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F8B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F8B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F8B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F8B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F8B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F8B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F8B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F8B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F8B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F8B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F8B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F8B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F8B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F9B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F9B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F9B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F9B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F9B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F9B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F9B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F9B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F9B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F9B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F9B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F9B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F9B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F9B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F9B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F9B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F9B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F9B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F9B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F9B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F9B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F9B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F9B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F9B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F9B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F9B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F9B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F9B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F9B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F9B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F9B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F10B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F10B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F10B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F10B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F10B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F10B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F10B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F10B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F10B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F10B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F10B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F10B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F10B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F10B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F10B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F10B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F10B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F10B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F10B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F10B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F10B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F10B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F10B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F10B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F10B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F10B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F10B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F10B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F10B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F10B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F10B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F11B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F11B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F11B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F11B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F11B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F11B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F11B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F11B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F11B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F11B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F11B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F11B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F11B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F11B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F11B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F11B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F11B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F11B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F11B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F11B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F11B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F11B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F11B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F11B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F11B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F11B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F11B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F11B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F11B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F11B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F11B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F12B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F12B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F12B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F12B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F12B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F12B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F12B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F12B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F12B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F12B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F12B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F12B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F12B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F12B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F12B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F12B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F12B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F12B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F12B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F12B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F12B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F12B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F12B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F12B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F12B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F12B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F12B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F12B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F12B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F12B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F12B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F13B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F13B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F13B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F13B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F13B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F13B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F13B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F13B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F13B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F13B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F13B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F13B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F13B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F13B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F13B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F13B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F13B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F13B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F13B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F13B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F13B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F13B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F13B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F13B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F13B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F13B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F13B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F13B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F13B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F13B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F13B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F0B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F0B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F0B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F0B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F0B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F0B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F0B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F0B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F0B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F0B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F0B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F0B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F0B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F0B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F0B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F0B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F0B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F0B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F0B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F0B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F0B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F0B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F0B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F0B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F0B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F0B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F0B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F0B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F0B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F0B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F0B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F1B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F1B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F1B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F1B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F1B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F1B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F1B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F1B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F1B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F1B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F1B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F1B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F1B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F1B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F1B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F1B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F1B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F1B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F1B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F1B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F1B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F1B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F1B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F1B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F1B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F1B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F1B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F1B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F1B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F1B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F1B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F2B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F2B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F2B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F2B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F2B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F2B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F2B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F2B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F2B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F2B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F2B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F2B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F2B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F2B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F2B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F2B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F2B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F2B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F2B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F2B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F2B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F2B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F2B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F2B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F2B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F2B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F2B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F2B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F2B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F2B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F2B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F3B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F3B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F3B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F3B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F3B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F3B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F3B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F3B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F3B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F3B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F3B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F3B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F3B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F3B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F3B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F3B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F3B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F3B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F3B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F3B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F3B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F3B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F3B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F3B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F3B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F3B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F3B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F3B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F3B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F3B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F3B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F4B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F4B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F4B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F4B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F4B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F4B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F4B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F4B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F4B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F4B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F4B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F4B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F4B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F4B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F4B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F4B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F4B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F4B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F4B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F4B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F4B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F4B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F4B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F4B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F4B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F4B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F4B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F4B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F4B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F4B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F4B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F5B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F5B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F5B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F5B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F5B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F5B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F5B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F5B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F5B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F5B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F5B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F5B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F5B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F5B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F5B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F5B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F5B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F5B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F5B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F5B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F5B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F5B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F5B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F5B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F5B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F5B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F5B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F5B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F5B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F5B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F5B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F6B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F6B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F6B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F6B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F6B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F6B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F6B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F6B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F6B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F6B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F6B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F6B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F6B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F6B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F6B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F6B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F6B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F6B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F6B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F6B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F6B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F6B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F6B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F6B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F6B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F6B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F6B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F6B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F6B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F6B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F6B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F7B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F7B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F7B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F7B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F7B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F7B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F7B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F7B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F7B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F7B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F7B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F7B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F7B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F7B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F7B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F7B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F7B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F7B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F7B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F7B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F7B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F7B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F7B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F7B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F7B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F7B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F7B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F7B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F7B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F7B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F7B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F8B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F8B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F8B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F8B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F8B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F8B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F8B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F8B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F8B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F8B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F8B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F8B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F8B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F8B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F8B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F8B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F8B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F8B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F8B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F8B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F8B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F8B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F8B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F8B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F8B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F8B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F8B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F8B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F8B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F8B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F8B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F9B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F9B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F9B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F9B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F9B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F9B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F9B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F9B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F9B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F9B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F9B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F9B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F9B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F9B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F9B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F9B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F9B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F9B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F9B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F9B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F9B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F9B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F9B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F9B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F9B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F9B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F9B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F9B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F9B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F9B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F9B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F10B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F10B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F10B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F10B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F10B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F10B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F10B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F10B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F10B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F10B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F10B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F10B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F10B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F10B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F10B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F10B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F10B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F10B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F10B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F10B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F10B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F10B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F10B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F10B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F10B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F10B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F10B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F10B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F10B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F10B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F10B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F11B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F11B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F11B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F11B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F11B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F11B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F11B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F11B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F11B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F11B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F11B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F11B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F11B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F11B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F11B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F11B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F11B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F11B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F11B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F11B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F11B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F11B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F11B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F11B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F11B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F11B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F11B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F11B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F11B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F11B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F11B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F12B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F12B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F12B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F12B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F12B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F12B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F12B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F12B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F12B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F12B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F12B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F12B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F12B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F12B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F12B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F12B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F12B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F12B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F12B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F12B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F12B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F12B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F12B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F12B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F12B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F12B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F12B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F12B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F12B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F12B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F12B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F13B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F13B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F13B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F13B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F13B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F13B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F13B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F13B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F13B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F13B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F13B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F13B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F13B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F13B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F13B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F13B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F13B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F13B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F13B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F13B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F13B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F13B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F13B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F13B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F13B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F13B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F13B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F13B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F13B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F13B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F13B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for SPI_CTRL1 register ********************/
+#define SPI_CTRL1_CLKPHA ((uint16_t)0x0001) /*!< Clock Phase */
+#define SPI_CTRL1_CLKPOL ((uint16_t)0x0002) /*!< Clock Polarity */
+#define SPI_CTRL1_MSEL ((uint16_t)0x0004) /*!< Master Selection */
+
+#define SPI_CTRL1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CTRL1_BR0 ((uint16_t)0x0008) /*!< Bit 0 */
+#define SPI_CTRL1_BR1 ((uint16_t)0x0010) /*!< Bit 1 */
+#define SPI_CTRL1_BR2 ((uint16_t)0x0020) /*!< Bit 2 */
+
+#define SPI_CTRL1_SPIEN ((uint16_t)0x0040) /*!< SPI Enable */
+#define SPI_CTRL1_LSBFF ((uint16_t)0x0080) /*!< Frame Format */
+#define SPI_CTRL1_SSEL ((uint16_t)0x0100) /*!< Internal slave select */
+#define SPI_CTRL1_SSMEN ((uint16_t)0x0200) /*!< Software slave management */
+#define SPI_CTRL1_RONLY ((uint16_t)0x0400) /*!< Receive only */
+#define SPI_CTRL1_DATFF ((uint16_t)0x0800) /*!< Data Frame Format */
+#define SPI_CTRL1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */
+#define SPI_CTRL1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */
+#define SPI_CTRL1_BIDIROEN ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */
+#define SPI_CTRL1_BIDIRMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CTRL2 register ********************/
+#define SPI_CTRL2_RDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */
+#define SPI_CTRL2_TDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */
+#define SPI_CTRL2_SSOEN ((uint8_t)0x04) /*!< SS Output Enable */
+#define SPI_CTRL2_ERRINTEN ((uint8_t)0x20) /*!< Error Interrupt Enable */
+#define SPI_CTRL2_RNEINTEN ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CTRL2_TEINTEN ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_STS register ********************/
+#define SPI_STS_RNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */
+#define SPI_STS_TE ((uint8_t)0x02) /*!< Transmit buffer Empty */
+#define SPI_STS_CHSIDE ((uint8_t)0x04) /*!< Channel side */
+#define SPI_STS_UNDER ((uint8_t)0x08) /*!< Underrun flag */
+#define SPI_STS_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */
+#define SPI_STS_MODERR ((uint8_t)0x20) /*!< Mode fault */
+#define SPI_STS_OVER ((uint8_t)0x40) /*!< Overrun flag */
+#define SPI_STS_BUSY ((uint8_t)0x80) /*!< Busy flag */
+
+/******************** Bit definition for SPI_DAT register ********************/
+#define SPI_DAT_DAT ((uint16_t)0xFFFF) /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPOLY register ******************/
+#define SPI_CRCPOLY_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_CRCRDAT register ******************/
+#define SPI_CRCRDAT_CRCRDAT ((uint16_t)0xFFFF) /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_CRCTDAT register ******************/
+#define SPI_CRCTDAT_CRCTDAT ((uint16_t)0xFFFF) /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFG register *****************/
+#define SPI_I2SCFG_CHBITS ((uint16_t)0x0001) /*!< Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFG_TDATLEN ((uint16_t)0x0006) /*!< TDATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFG_TDATLEN0 ((uint16_t)0x0002) /*!< Bit 0 */
+#define SPI_I2SCFG_TDATLEN1 ((uint16_t)0x0004) /*!< Bit 1 */
+
+#define SPI_I2SCFG_CLKPOL ((uint16_t)0x0008) /*!< steady state clock polarity */
+
+#define SPI_I2SCFG_STDSEL ((uint16_t)0x0030) /*!< STDSEL[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFG_STDSEL0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define SPI_I2SCFG_STDSEL1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define SPI_I2SCFG_PCMFSYNC ((uint16_t)0x0080) /*!< PCM frame synchronization */
+
+#define SPI_I2SCFG_MODCFG ((uint16_t)0x0300) /*!< MODCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFG_MODCFG0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define SPI_I2SCFG_MODCFG1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define SPI_I2SCFG_I2SEN ((uint16_t)0x0400) /*!< I2S Enable */
+#define SPI_I2SCFG_MODSEL ((uint16_t)0x0800) /*!< I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPREDIV register *******************/
+#define SPI_I2SPREDIV_LDIV ((uint16_t)0x00FF) /*!< I2S Linear prescaler */
+#define SPI_I2SPREDIV_ODD_EVEN ((uint16_t)0x0100) /*!< Odd factor for the prescaler */
+#define SPI_I2SPREDIV_MCLKOEN ((uint16_t)0x0200) /*!< Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CTRL1 register ********************/
+#define I2C_CTRL1_EN ((uint16_t)0x0001) /*!< Peripheral Enable */
+#define I2C_CTRL1_SMBMODE ((uint16_t)0x0002) /*!< SMBus Mode */
+#define I2C_CTRL1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */
+#define I2C_CTRL1_ARPEN ((uint16_t)0x0010) /*!< ARP Enable */
+#define I2C_CTRL1_PECEN ((uint16_t)0x0020) /*!< PEC Enable */
+#define I2C_CTRL1_GCEN ((uint16_t)0x0040) /*!< General Call Enable */
+#define I2C_CTRL1_NOEXTEND ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */
+#define I2C_CTRL1_STARTGEN ((uint16_t)0x0100) /*!< Start Generation */
+#define I2C_CTRL1_STOPGEN ((uint16_t)0x0200) /*!< Stop Generation */
+#define I2C_CTRL1_ACKEN ((uint16_t)0x0400) /*!< Acknowledge Enable */
+#define I2C_CTRL1_ACKPOS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */
+#define I2C_CTRL1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */
+#define I2C_CTRL1_SMBALERT ((uint16_t)0x2000) /*!< SMBus Alert */
+#define I2C_CTRL1_SWRESET ((uint16_t)0x8000) /*!< Software Reset */
+
+/******************* Bit definition for I2C_CTRL2 register ********************/
+#define I2C_CTRL2_CLKFREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CTRL2_CLKFREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define I2C_CTRL2_CLKFREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define I2C_CTRL2_CLKFREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define I2C_CTRL2_CLKFREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define I2C_CTRL2_CLKFREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define I2C_CTRL2_CLKFREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */
+
+#define I2C_CTRL2_ERRINTEN ((uint16_t)0x0100) /*!< Error Interrupt Enable */
+#define I2C_CTRL2_EVTINTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */
+#define I2C_CTRL2_BUFINTEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */
+#define I2C_CTRL2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */
+#define I2C_CTRL2_DMALAST ((uint16_t)0x1000) /*!< DMA Last Transfer */
+
+/******************* Bit definition for I2C_OADDR1 register *******************/
+#define I2C_OADDR1_ADDR1_7 ((uint16_t)0x00FE) /*!< Interface Address */
+#define I2C_OADDR1_ADDR8_9 ((uint16_t)0x0300) /*!< Interface Address */
+
+#define I2C_OADDR1_ADDR0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define I2C_OADDR1_ADDR1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define I2C_OADDR1_ADDR2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define I2C_OADDR1_ADDR3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define I2C_OADDR1_ADDR4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define I2C_OADDR1_ADDR5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define I2C_OADDR1_ADDR6 ((uint16_t)0x0040) /*!< Bit 6 */
+#define I2C_OADDR1_ADDR7 ((uint16_t)0x0080) /*!< Bit 7 */
+#define I2C_OADDR1_ADDR8 ((uint16_t)0x0100) /*!< Bit 8 */
+#define I2C_OADDR1_ADDR9 ((uint16_t)0x0200) /*!< Bit 9 */
+
+#define I2C_OADDR1_ADDRMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OADDR2 register *******************/
+#define I2C_OADDR2_DUALEN ((uint8_t)0x01) /*!< Dual addressing mode enable */
+#define I2C_OADDR2_ADDR2 ((uint8_t)0xFE) /*!< Interface address */
+
+/******************** Bit definition for I2C_DAT register ********************/
+#define I2C_DAT_DATA ((uint8_t)0xFF) /*!< 8-bit Data Register */
+
+/******************* Bit definition for I2C_STS1 register ********************/
+#define I2C_STS1_STARTBF ((uint16_t)0x0001) /*!< Start Bit (Master mode) */
+#define I2C_STS1_ADDRF ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */
+#define I2C_STS1_BSF ((uint16_t)0x0004) /*!< Byte Transfer Finished */
+#define I2C_STS1_ADDR10F ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */
+#define I2C_STS1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */
+#define I2C_STS1_RXDATNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */
+#define I2C_STS1_TXDATE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */
+#define I2C_STS1_BUSERR ((uint16_t)0x0100) /*!< Bus Error */
+#define I2C_STS1_ARLOST ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */
+#define I2C_STS1_ACKFAIL ((uint16_t)0x0400) /*!< Acknowledge Failure */
+#define I2C_STS1_OVERRUN ((uint16_t)0x0800) /*!< Overrun/Underrun */
+#define I2C_STS1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */
+#define I2C_STS1_TIMOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */
+#define I2C_STS1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */
+
+/******************* Bit definition for I2C_STS2 register ********************/
+#define I2C_STS2_MSMODE ((uint16_t)0x0001) /*!< Master/Slave */
+#define I2C_STS2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */
+#define I2C_STS2_TRF ((uint16_t)0x0004) /*!< Transmitter/Receiver */
+#define I2C_STS2_GCALLADDR ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */
+#define I2C_STS2_SMBDADDR ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */
+#define I2C_STS2_SMBHADDR ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */
+#define I2C_STS2_DUALFLAG ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */
+#define I2C_STS2_PECVAL ((uint16_t)0xFF00) /*!< Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CLKCTRL register ********************/
+#define I2C_CLKCTRL_CLKCTRL ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CLKCTRL_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */
+#define I2C_CLKCTRL_FSMODE ((uint16_t)0x8000) /*!< I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TMRISE_TMRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for USART_STS register *******************/
+#define USART_STS_PEF ((uint16_t)0x0001) /*!< Parity Error */
+#define USART_STS_FEF ((uint16_t)0x0002) /*!< Framing Error */
+#define USART_STS_NEF ((uint16_t)0x0004) /*!< Noise Error Flag */
+#define USART_STS_OREF ((uint16_t)0x0008) /*!< OverRun Error */
+#define USART_STS_IDLEF ((uint16_t)0x0010) /*!< IDLE line detected */
+#define USART_STS_RXDNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */
+#define USART_STS_TXC ((uint16_t)0x0040) /*!< Transmission Complete */
+#define USART_STS_TXDE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */
+#define USART_STS_LINBDF ((uint16_t)0x0100) /*!< LIN Break Detection Flag */
+#define USART_STS_CTSF ((uint16_t)0x0200) /*!< CTS Flag */
+
+/******************* Bit definition for USART_DAT register *******************/
+#define USART_DAT_DATV ((uint16_t)0x01FF) /*!< Data value */
+
+/****************** Bit definition for USART_BRCF register *******************/
+#define USART_BRCF_DIV_Decimal ((uint16_t)0x000F) /*!< Fraction of USARTDIV */
+#define USART_BRCF_DIV_Integer ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CTRL1 register *******************/
+#define USART_CTRL1_SDBRK ((uint16_t)0x0001) /*!< Send Break */
+#define USART_CTRL1_RCVWU ((uint16_t)0x0002) /*!< Receiver wakeup */
+#define USART_CTRL1_RXEN ((uint16_t)0x0004) /*!< Receiver Enable */
+#define USART_CTRL1_TXEN ((uint16_t)0x0008) /*!< Transmitter Enable */
+#define USART_CTRL1_IDLEIEN ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */
+#define USART_CTRL1_RXDNEIEN ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */
+#define USART_CTRL1_TXCIEN ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */
+#define USART_CTRL1_TXDEIEN ((uint16_t)0x0080) /*!< PE Interrupt Enable */
+#define USART_CTRL1_PEIEN ((uint16_t)0x0100) /*!< PE Interrupt Enable */
+#define USART_CTRL1_PSEL ((uint16_t)0x0200) /*!< Parity Selection */
+#define USART_CTRL1_PCEN ((uint16_t)0x0400) /*!< Parity Control Enable */
+#define USART_CTRL1_WUM ((uint16_t)0x0800) /*!< Wakeup method */
+#define USART_CTRL1_WL ((uint16_t)0x1000) /*!< Word length */
+#define USART_CTRL1_UEN ((uint16_t)0x2000) /*!< USART Enable */
+
+/****************** Bit definition for USART_CTRL2 register *******************/
+#define USART_CTRL2_ADDR ((uint16_t)0x000F) /*!< Address of the USART node */
+#define USART_CTRL2_LINBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */
+#define USART_CTRL2_LINBDIEN ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */
+#define USART_CTRL2_LBCLK ((uint16_t)0x0100) /*!< Last Bit Clock pulse */
+#define USART_CTRL2_CLKPHA ((uint16_t)0x0200) /*!< Clock Phase */
+#define USART_CTRL2_CLKPOL ((uint16_t)0x0400) /*!< Clock Polarity */
+#define USART_CTRL2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */
+
+#define USART_CTRL2_STPB ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CTRL2_STPB_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USART_CTRL2_STPB_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USART_CTRL2_LINMEN ((uint16_t)0x4000) /*!< LIN mode enable */
+
+/****************** Bit definition for USART_CTRL3 register *******************/
+#define USART_CTRL3_ERRIEN ((uint16_t)0x0001) /*!< Error Interrupt Enable */
+#define USART_CTRL3_IRDAMEN ((uint16_t)0x0002) /*!< IrDA mode Enable */
+#define USART_CTRL3_IRDALP ((uint16_t)0x0004) /*!< IrDA Low-Power */
+#define USART_CTRL3_HDMEN ((uint16_t)0x0008) /*!< Half-Duplex Selection */
+#define USART_CTRL3_SCNACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */
+#define USART_CTRL3_SCMEN ((uint16_t)0x0020) /*!< Smartcard mode enable */
+#define USART_CTRL3_DMARXEN ((uint16_t)0x0040) /*!< DMA Enable Receiver */
+#define USART_CTRL3_DMATXEN ((uint16_t)0x0080) /*!< DMA Enable Transmitter */
+#define USART_CTRL3_RTSEN ((uint16_t)0x0100) /*!< RTS Enable */
+#define USART_CTRL3_CTSEN ((uint16_t)0x0200) /*!< CTS Enable */
+#define USART_CTRL3_CTSIEN ((uint16_t)0x0400) /*!< CTS Interrupt Enable */
+
+/****************** Bit definition for USART_GTP register ******************/
+#define USART_GTP_PSCV ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTP_PSCV_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define USART_GTP_PSCV_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define USART_GTP_PSCV_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define USART_GTP_PSCV_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define USART_GTP_PSCV_4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define USART_GTP_PSCV_5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define USART_GTP_PSCV_6 ((uint16_t)0x0040) /*!< Bit 6 */
+#define USART_GTP_PSCV_7 ((uint16_t)0x0080) /*!< Bit 7 */
+
+#define USART_GTP_GTV ((uint16_t)0xFF00) /*!< Guard time value */
+
+/******************************************************************************/
+/* */
+/* Low-power Universal Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for LPUART_STS register ******************/
+#define LPUART_STS_PEF ((uint16_t)0x0001) /*!< Parity Check Error Flag */
+#define LPUART_STS_TXC ((uint16_t)0x0002) /*!< TX Complete Flag */
+#define LPUART_STS_FIFO_OV ((uint16_t)0x0004) /*!< FIFO Overflow Flag */
+#define LPUART_STS_FIFO_FU ((uint16_t)0x0008) /*!< FIFO Full Flag */
+#define LPUART_STS_FIFO_HF ((uint16_t)0x0010) /*!< FIFO Half Full Flag */
+#define LPUART_STS_FIFO_NE ((uint16_t)0x0020) /*!< FIFO Non-Empty Flag */
+#define LPUART_STS_CTS ((uint16_t)0x0040) /*!< Clear to Send (Hardware Flow Control) Flag */
+#define LPUART_STS_WUF ((uint16_t)0x0080) /*!< Wakeup from Stop mode Flag */
+#define LPUART_STS_NF ((uint16_t)0x0100) /*!< Noise Detected Flag */
+
+/****************** Bit definition for LPUART_INTEN register ******************/
+#define LPUART_INTEN_PEIE ((uint8_t)0x01) /*!< Parity Check Error Interrupt Enable */
+#define LPUART_INTEN_TXCIE ((uint8_t)0x02) /*!< TX Complete Interrupt Enable */
+#define LPUART_INTEN_FIFO_OVIE ((uint8_t)0x04) /*!< FIFO Overflow Interrupt Enable */
+#define LPUART_INTEN_FIFO_FUIE ((uint8_t)0x08) /*!< FIFO Full Interrupt Enable*/
+#define LPUART_INTEN_FIFO_HFIE ((uint8_t)0x10) /*!< FIFO Half Full Interrupt Enable */
+#define LPUART_INTEN_FIFO_NEIE ((uint8_t)0x20) /*!< FIFO Non-Empty Interrupt Enable */
+#define LPUART_INTEN_WUFIE ((uint8_t)0x40) /*!< Wakeup Interrupt Enable */
+
+/****************** Bit definition for LPUART_CTRL register ******************/
+#define LPUART_CTRL_PSEL ((uint16_t)0x0001) /*!< Odd Parity Bit Enable */
+#define LPUART_CTRL_TXEN ((uint16_t)0x0002) /*!< TX Enable */
+#define LPUART_CTRL_FLUSH ((uint16_t)0x0004) /*!< Flush Receiver FIFO Enable */
+#define LPUART_CTRL_PCDIS ((uint16_t)0x0008) /*!< Parity Control Disable */
+#define LPUART_CTRL_LOOPBACK ((uint16_t)0x0010) /*!< Loop Back Self-Test */
+#define LPUART_CTRL_DMA_TXEN ((uint16_t)0x0020) /*!< DMA TX Request Enable */
+#define LPUART_CTRL_DMA_RXEN ((uint16_t)0x0040) /*!< DMA RX Request Enable */
+#define LPUART_CTRL_WUSTP ((uint16_t)0x0080) /*!< LPUART Wakeup Enable in Stop mode */
+#define LPUART_CTRL_RTS_THSEL ((uint16_t)0x0300) /*!< RTS Threshold Selection */
+#define LPUART_CTRL_CTSEN ((uint16_t)0x0400) /*!< Hardware Flow Control TX Enable */
+#define LPUART_CTRL_RTSEN ((uint16_t)0x0800) /*!< Hardware Flow Control RX Enable */
+#define LPUART_CTRL_WUSEL ((uint16_t)0x3000) /*!< Wakeup Event Selection */
+#define LPUART_CTRL_SMPCNT ((uint16_t)0x4000) /*!< Specify the Sampling Method */
+
+/****************** Bit definition for LPUART_BRCFG1 register ******************/
+#define LPUART_BRCFG1_INTEGER ((uint16_t)0xFFFF) /*!< Baud Rate Parameter Configeration Register1: Fraction */
+
+/****************** Bit definition for LPUART_DAT register ******************/
+#define LPUART_DAT_DAT ((uint8_t)0xFF) /*!< Data Register */
+
+/****************** Bit definition for LPUART_BRCFG2 register ******************/
+#define LPUART_BRCFG2_DECIMAL ((uint8_t)0xFF) /*!< Baud Rate Parameter Configeration Register2: Mantissa */
+
+/****************** Bit definition for LPUART_WUDAT register ******************/
+#define LPUART_WUDAT_WUDAT ((uint32_t)0xFFFFFFFF) /*!< Data Register */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBG_ID register *****************/
+#define DBG_ID_DEV ((uint32_t)0x00000FFF) /*!< Device Identifier */
+
+#define DBG_ID_REV ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBG_ID_REV_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define DBG_ID_REV_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define DBG_ID_REV_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define DBG_ID_REV_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define DBG_ID_REV_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define DBG_ID_REV_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define DBG_ID_REV_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define DBG_ID_REV_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+#define DBG_ID_REV_8 ((uint32_t)0x01000000) /*!< Bit 8 */
+#define DBG_ID_REV_9 ((uint32_t)0x02000000) /*!< Bit 9 */
+#define DBG_ID_REV_10 ((uint32_t)0x04000000) /*!< Bit 10 */
+#define DBG_ID_REV_11 ((uint32_t)0x08000000) /*!< Bit 11 */
+#define DBG_ID_REV_12 ((uint32_t)0x10000000) /*!< Bit 12 */
+#define DBG_ID_REV_13 ((uint32_t)0x20000000) /*!< Bit 13 */
+#define DBG_ID_REV_14 ((uint32_t)0x40000000) /*!< Bit 14 */
+#define DBG_ID_REV_15 ((uint32_t)0x80000000) /*!< Bit 15 */
+
+/****************** Bit definition for DBG_CTRL register *******************/
+#define DBG_CTRL_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
+#define DBG_CTRL_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
+#define DBG_CTRL_STDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
+
+#define DBG_CTRL_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBG_CTRL_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBG_CTRL_TIM1_STOP ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */
+#define DBG_CTRL_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */
+#define DBG_CTRL_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */
+#define DBG_CTRL_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */
+#define DBG_CTRL_CAN_STOP ((uint32_t)0x00004000) /*!< Debug CAN stopped when Core is halted */
+#define DBG_CTRL_I2C1SMBUS_TO ((uint32_t)0x00008000) /*!< SMBUS I2C1 timeout mode stopped when Core is halted */
+#define DBG_CTRL_I2C2SMBUS_TO ((uint32_t)0x00010000) /*!< SMBUS I2C2 timeout mode stopped when Core is halted */
+#define DBG_CTRL_TIM8_STOP ((uint32_t)0x00020000) /*!< TIM8 counter stopped when core is halted */
+#define DBG_CTRL_TIM5_STOP ((uint32_t)0x00040000) /*!< TIM5 counter stopped when core is halted */
+#define DBG_CTRL_TIM6_STOP ((uint32_t)0x00080000) /*!< TIM6 counter stopped when core is halted */
+#define DBG_CTRL_TIM7_STOP ((uint32_t)0x00100000) /*!< TIM7 counter stopped when core is halted */
+#define DBG_CTRL_TIM9_STOP ((uint32_t)0x00200000) /*!< TIM9 counter stopped when core is halted*/
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_AC register ******************/
+#define FLASH_AC_LATENCY ((uint32_t)0x00000003) /*!< LATENCY[2:0] bits (Latency) */
+#define FLASH_AC_LATENCY_0 ((uint32_t)0x00000000) /*!< Bit 0 = 0 */
+#define FLASH_AC_LATENCY_1 ((uint32_t)0x00000001) /*!< Bit 0 = 1 */
+#define FLASH_AC_LATENCY_2 ((uint32_t)0x00000002) /*!< Bit 0 = 0; Bit 1 = 1 */
+#define FLASH_AC_LATENCY_3 ((uint32_t)0x00000003) /*!< Bit 0 = 1; Bit 1 = 1 */
+
+#define FLASH_AC_PRFTBFEN ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
+#define FLASH_AC_PRFTBFSTS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
+#define FLASH_AC_ICAHRST ((uint32_t)0x00000040) /*!< Icache Reset */
+#define FLASH_AC_ICAHEN ((uint32_t)0x00000080) /*!< Icache Enable */
+#define FLASH_AC_LVMF ((uint32_t)0x00000100) /*!< Flash low power work mode status */
+#define FLASH_AC_LVMEN ((uint32_t)0x00000200) /*!< Flash low power work mode Enable */
+#define FLASH_AC_SLMF ((uint32_t)0x00000400) /*!< Flash sleep mode status */
+#define FLASH_AC_SLMEN ((uint32_t)0x00000800) /*!< Flash sleep mode Enable */
+
+/****************** Bit definition for FLASH_KEY register ******************/
+#define FLASH_KEY_FKEY ((uint32_t)0xFFFFFFFF) /*!< FLASH Key */
+
+/***************** Bit definition for FLASH_OPTKEY register ****************/
+#define FLASH_OPTKEY_OPTKEY ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
+
+/****************** Bit definition for FLASH_STS register *******************/
+#define FLASH_STS_BUSY ((uint8_t)0x01) /*!< Busy */
+#define FLASH_STS_PGERR ((uint8_t)0x04) /*!< Programming Error */
+#define FLASH_STS_PVERR ((uint8_t)0x08) /*!< Programming Verify ERROR after program */
+#define FLASH_STS_WRPERR ((uint8_t)0x10) /*!< Write Protection Error */
+#define FLASH_STS_EOP ((uint8_t)0x20) /*!< End of operation */
+#define FLASH_STS_EVERR ((uint8_t)0x40) /*!< Erase Verify ERROR after page erase */
+
+/******************* Bit definition for FLASH_CTRL register *******************/
+#define FLASH_CTRL_PG ((uint16_t)0x0001) /*!< Programming */
+#define FLASH_CTRL_PER ((uint16_t)0x0002) /*!< Page Erase */
+#define FLASH_CTRL_MER ((uint16_t)0x0004) /*!< Mass Erase */
+#define FLASH_CTRL_OPTPG ((uint16_t)0x0010) /*!< Option Byte Programming */
+#define FLASH_CTRL_OPTER ((uint16_t)0x0020) /*!< Option Byte Erase */
+#define FLASH_CTRL_START ((uint16_t)0x0040) /*!< Start */
+#define FLASH_CTRL_LOCK ((uint16_t)0x0080) /*!< Lock */
+#define FLASH_CTRL_SMPSEL ((uint16_t)0x0100) /*!< Flash Program Option Select */
+#define FLASH_CTRL_OPTWE ((uint16_t)0x0200) /*!< Option Bytes Write Enable */
+#define FLASH_CTRL_ERRITE ((uint16_t)0x0400) /*!< Error Interrupt Enable */
+#define FLASH_CTRL_FERRITE ((uint16_t)0x0800) /*!< EVERR PVERR Error Interrupt Enable */
+#define FLASH_CTRL_EOPITE ((uint16_t)0x1000) /*!< End of operation Interrupt Enable */
+
+/******************* Bit definition for FLASH_ADD register *******************/
+#define FLASH_ADD_FADD ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OB2 register *******************/
+#define FLASH_OB2_BOR_LEV ((uint32_t)0x00000700) /*!< BOR_LEV[2:0] */
+#define FLASH_OB2_nBOOT1 ((uint32_t)0x00800000) /*!< nBOOT1 */
+#define FLASH_OB2_nSWBOOT0 ((uint32_t)0x04000000) /*!< nSWBOOT0 */
+#define FLASH_OB2_nBOOT0 ((uint32_t)0x08000000) /*!< nBOOT1 */
+
+/****************** Bit definition for FLASH_OB register *******************/
+#define FLASH_OB_OBERR ((uint16_t)0x0001) /*!< Option Byte Error */
+#define FLASH_OB_RDPRT1 ((uint16_t)0x0002) /*!< Read Protection */
+
+#define FLASH_OB_USER ((uint16_t)0x03FC) /*!< User Option Bytes */
+#define FLASH_OB_WDG_SW ((uint16_t)0x0004) /*!< WDG_SW */
+#define FLASH_OB_NRST_STOP2 ((uint16_t)0x0008) /*!< nRST_STOP2 */
+#define FLASH_OB_NRST_STDBY ((uint16_t)0x0010) /*!< nRST_STDBY */
+#define FLASH_OB_NRST_PD ((uint16_t)0x0020) /*!< nRST_PD */
+
+#define FLASH_OB_DATA0_MSK ((uint32_t)0x0003FC00) /*!< Data0 Mask */
+#define FLASH_OB_DATA1_MSK ((uint32_t)0x03FC0000) /*!< Data1 Mask */
+#define FLASH_OB_RDPRT2 ((uint32_t)0x80000000) /*!< Read Protection Level 2 */
+
+/****************** Bit definition for FLASH_WRP register ******************/
+#define FLASH_WRP_WRPT ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
+
+/****************** Bit definition for FLASH_CAHR register ******************/
+#define FLASH_CAHR_LOCKSTRT_MSK ((uint32_t)0x000F) /*!< LOCKSTRT Mask */
+#define FLASH_CAHR_LOCKSTOP_MSK ((uint32_t)0x00F0) /*!< LOCKSTOP Mask */
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for OptionByte USER ******************/
+#define FLASH_RDP_RDP1 ((uint32_t)0x000000FF) /*!< Read protection option byte */
+#define FLASH_RDP_NRDP1 ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
+
+/****************** Bit definition for OptionByte USER ******************/
+#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
+#define FLASH_USER_NUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
+
+/****************** Bit definition for OptionByte Data0 *****************/
+#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!< User data storage option byte */
+#define FLASH_Data0_NData0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */
+
+/****************** Bit definition for OptionByte Data1 *****************/
+#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */
+#define FLASH_Data1_NData1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */
+
+/****************** Bit definition for OptionByte WRP0 ******************/
+#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP0_NWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for OptionByte WRP1 ******************/
+#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP1_NWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for OptionByte WRP2 ******************/
+#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP2_NWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for OptionByte WRP3 ******************/
+#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP3_NWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for OptionByte RDP2 *******************/
+#define FLASH_RDP_RDP2 ((uint32_t)0x000000FF) /*!< Read protection level 2 option byte */
+#define FLASH_RDP_NRDP2 ((uint32_t)0x0000FF00) /*!< Read protection level 2 complemented option byte */
+
+/****************** Bit definition for OptionByte USER2 ******************/
+#define FLASH_USER_USER2 ((uint32_t)0x00FF0000) /*!< User option byte */
+#define FLASH_USER_NUSER2 ((uint32_t)0xFF000000) /*!< User complemented option byte */
+
+/******************************************************************************/
+/* */
+/* General Purpose and Alternate Function I/O */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for GPIO_PMODE register *******************/
+
+
+#define GPIO_PMODE0_Pos (0)
+#define GPIO_PMODE0_Msk (0x3 << GPIO_PMODE0_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE0 GPIO_PMODE0_Msk
+#define GPIO_PMODE0_0 (0x0 << GPIO_PMODE0_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE0_1 (0x1 << GPIO_PMODE0_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE0_2 (0x2 << GPIO_PMODE0_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE0_3 (0x3 << GPIO_PMODE0_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE1_Pos (2)
+#define GPIO_PMODE1_Msk (0x3 << GPIO_PMODE1_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE1 GPIO_PMODE1_Msk
+#define GPIO_PMODE1_0 (0x0 << GPIO_PMODE1_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE1_1 (0x1 << GPIO_PMODE1_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE1_2 (0x2 << GPIO_PMODE1_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE1_3 (0x3 << GPIO_PMODE1_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE2_Pos (4)
+#define GPIO_PMODE2_Msk (0x3 << GPIO_PMODE2_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE2 GPIO_PMODE2_Msk
+#define GPIO_PMODE2_0 (0x0 << GPIO_PMODE2_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE2_1 (0x1 << GPIO_PMODE2_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE2_2 (0x2 << GPIO_PMODE2_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE2_3 (0x3 << GPIO_PMODE2_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE3_Pos (6)
+#define GPIO_PMODE3_Msk (0x3 << GPIO_PMODE3_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE3 GPIO_PMODE3_Msk
+#define GPIO_PMODE3_0 (0x0 << GPIO_PMODE3_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE3_1 (0x1 << GPIO_PMODE3_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE3_2 (0x2 << GPIO_PMODE3_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE3_3 (0x3 << GPIO_PMODE3_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE4_Pos (8)
+#define GPIO_PMODE4_Msk (0x3 << GPIO_PMODE4_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE4 GPIO_PMODE4_Msk
+#define GPIO_PMODE4_0 (0x0 << GPIO_PMODE4_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE4_1 (0x1 << GPIO_PMODE4_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE4_2 (0x2 << GPIO_PMODE4_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE4_3 (0x3 << GPIO_PMODE4_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE5_Pos (10)
+#define GPIO_PMODE5_Msk (0x3 << GPIO_PMODE5_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE5 GPIO_PMODE5_Msk
+#define GPIO_PMODE5_0 (0x0 << GPIO_PMODE5_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE5_1 (0x1 << GPIO_PMODE5_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE5_2 (0x2 << GPIO_PMODE5_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE5_3 (0x3 << GPIO_PMODE5_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE6_Pos (12)
+#define GPIO_PMODE6_Msk (0x3 << GPIO_PMODE6_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE6 GPIO_PMODE6_Msk
+#define GPIO_PMODE6_0 (0x0 << GPIO_PMODE6_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE6_1 (0x1 << GPIO_PMODE6_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE6_2 (0x2 << GPIO_PMODE6_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE6_3 (0x3 << GPIO_PMODE6_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE7_Pos (14)
+#define GPIO_PMODE7_Msk (0x3 << GPIO_PMODE7_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE7 GPIO_PMODE7_Msk
+#define GPIO_PMODE7_0 (0x0 << GPIO_PMODE7_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE7_1 (0x1 << GPIO_PMODE7_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE7_2 (0x2 << GPIO_PMODE7_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE7_3 (0x3 << GPIO_PMODE7_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE8_Pos (16)
+#define GPIO_PMODE8_Msk (0x3 << GPIO_PMODE8_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE8 GPIO_PMODE8_Msk
+#define GPIO_PMODE8_0 (0x0 << GPIO_PMODE8_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE8_1 (0x1 << GPIO_PMODE8_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE8_2 (0x2 << GPIO_PMODE8_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE8_3 (0x3 << GPIO_PMODE8_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE9_Pos (18)
+#define GPIO_PMODE9_Msk (0x3 << GPIO_PMODE9_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE9 GPIO_PMODE9_Msk
+#define GPIO_PMODE9_0 (0x0 << GPIO_PMODE9_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE9_1 (0x1 << GPIO_PMODE9_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE9_2 (0x2 << GPIO_PMODE9_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE9_3 (0x3 << GPIO_PMODE9_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE10_Pos (20)
+#define GPIO_PMODE10_Msk (0x3 << GPIO_PMODE10_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE10 GPIO_PMODE10_Msk
+#define GPIO_PMODE10_0 (0x0 << GPIO_PMODE10_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE10_1 (0x1 << GPIO_PMODE10_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE10_2 (0x2 << GPIO_PMODE10_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE10_3 (0x3 << GPIO_PMODE10_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE11_Pos (22)
+#define GPIO_PMODE11_Msk (0x3 << GPIO_PMODE11_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE11 GPIO_PMODE11_Msk
+#define GPIO_PMODE11_0 (0x0 << GPIO_PMODE11_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE11_1 (0x1 << GPIO_PMODE11_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE11_2 (0x2 << GPIO_PMODE11_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE11_3 (0x3 << GPIO_PMODE11_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE12_Pos (24)
+#define GPIO_PMODE12_Msk (0x3 << GPIO_PMODE12_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE12 GPIO_PMODE12_Msk
+#define GPIO_PMODE12_0 (0x0 << GPIO_PMODE12_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE12_1 (0x1 << GPIO_PMODE12_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE12_2 (0x2 << GPIO_PMODE12_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE12_3 (0x3 << GPIO_PMODE12_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE13_Pos (26)
+#define GPIO_PMODE13_Msk (0x3 << GPIO_PMODE13_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE13 GPIO_PMODE13_Msk
+#define GPIO_PMODE13_0 (0x0 << GPIO_PMODE13_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE13_1 (0x1 << GPIO_PMODE13_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE13_2 (0x2 << GPIO_PMODE13_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE13_3 (0x3 << GPIO_PMODE13_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE14_Pos (28)
+#define GPIO_PMODE14_Msk (0x3 << GPIO_PMODE14_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE14 GPIO_PMODE14_Msk
+#define GPIO_PMODE14_0 (0x0 << GPIO_PMODE14_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE14_1 (0x1 << GPIO_PMODE14_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE14_2 (0x2 << GPIO_PMODE14_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE14_3 (0x3 << GPIO_PMODE14_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE15_Pos (30)
+#define GPIO_PMODE15_Msk (0x3 << GPIO_PMODE15_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE15 GPIO_PMODE15_Msk
+#define GPIO_PMODE15_0 (0x0 << GPIO_PMODE15_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE15_1 (0x1 << GPIO_PMODE15_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE15_2 (0x2 << GPIO_PMODE15_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE15_3 (0x3 << GPIO_PMODE15_Pos) /*!< 0x00000003 */
+
+
+
+
+/****************** Bit definition for GPIO_POTYPER register *****************/
+#define GPIO_POTYPE_POT_0 (0x00000001)
+#define GPIO_POTYPE_POT_1 (0x00000002)
+#define GPIO_POTYPE_POT_2 (0x00000004)
+#define GPIO_POTYPE_POT_3 (0x00000008)
+#define GPIO_POTYPE_POT_4 (0x00000010)
+#define GPIO_POTYPE_POT_5 (0x00000020)
+#define GPIO_POTYPE_POT_6 (0x00000040)
+#define GPIO_POTYPE_POT_7 (0x00000080)
+#define GPIO_POTYPE_POT_8 (0x00000100)
+#define GPIO_POTYPE_POT_9 (0x00000200)
+#define GPIO_POTYPE_POT_10 (0x00000400)
+#define GPIO_POTYPE_POT_11 (0x00000800)
+#define GPIO_POTYPE_POT_12 (0x00001000)
+#define GPIO_POTYPE_POT_13 (0x00002000)
+#define GPIO_POTYPE_POT_14 (0x00004000)
+#define GPIO_POTYPE_POT_15 (0x00008000)
+
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPD0_Pos (0)
+#define GPIO_PUPD0_Msk (0x3 << GPIO_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD0 GPIO_PUPD0_Msk
+#define GPIO_PUPD0_0 (0x0 << GPIO_PUPD0_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD0_1 (0x1 << GPIO_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD0_2 (0x2 << GPIO_PUPD0_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD1_Pos (2)
+#define GPIO_PUPD1_Msk (0x3 << GPIO_PUPD1_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD1 GPIO_PUPD1_Msk
+#define GPIO_PUPD1_0 (0x0 << GPIO_PUPD1_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD1_1 (0x1 << GPIO_PUPD1_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD1_2 (0x2 << GPIO_PUPD1_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD2_Pos (4)
+#define GPIO_PUPD2_Msk (0x3 << GPIO_PUPD2_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD2 GPIO_PUPD2_Msk
+#define GPIO_PUPD2_0 (0x0 << GPIO_PUPD2_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD2_1 (0x1 << GPIO_PUPD2_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD2_2 (0x2 << GPIO_PUPD2_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD3_Pos (6)
+#define GPIO_PUPD3_Msk (0x3 << GPIO_PUPD3_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD3 GPIO_PUPD3_Msk
+#define GPIO_PUPD3_0 (0x0 << GPIO_PUPD3_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD3_1 (0x1 << GPIO_PUPD3_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD3_2 (0x2 << GPIO_PUPD3_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD4_Pos (8)
+#define GPIO_PUPD4_Msk (0x3 << GPIO_PUPD4_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD4 GPIO_PUPD4_Msk
+#define GPIO_PUPD4_0 (0x0 << GPIO_PUPD4_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD4_1 (0x1 << GPIO_PUPD4_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD4_2 (0x2 << GPIO_PUPD4_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD5_Pos (10)
+#define GPIO_PUPD5_Msk (0x3 << GPIO_PUPD5_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD5 GPIO_PUPD5_Msk
+#define GPIO_PUPD5_0 (0x0 << GPIO_PUPD5_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD5_1 (0x1 << GPIO_PUPD5_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD5_2 (0x2 << GPIO_PUPD5_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD6_Pos (12)
+#define GPIO_PUPD6_Msk (0x3 << GPIO_PUPD6_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD6 GPIO_PUPD6_Msk
+#define GPIO_PUPD6_0 (0x0 << GPIO_PUPD6_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD6_1 (0x1 << GPIO_PUPD6_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD6_2 (0x2 << GPIO_PUPD6_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD7_Pos (14)
+#define GPIO_PUPD7_Msk (0x3 << GPIO_PUPD7_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD7 GPIO_PUPD7_Msk
+#define GPIO_PUPD7_0 (0x0 << GPIO_PUPD7_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD7_1 (0x1 << GPIO_PUPD7_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD7_2 (0x2 << GPIO_PUPD7_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD8_Pos (16)
+#define GPIO_PUPD8_Msk (0x3 << GPIO_PUPD8_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD8 GPIO_PUPD8_Msk
+#define GPIO_PUPD8_0 (0x0 << GPIO_PUPD8_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD8_1 (0x1 << GPIO_PUPD8_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD8_2 (0x2 << GPIO_PUPD8_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD9_Pos (18)
+#define GPIO_PUPD9_Msk (0x3 << GPIO_PUPD9_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD9 GPIO_PUPD9_Msk
+#define GPIO_PUPD9_0 (0x0 << GPIO_PUPD9_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD9_1 (0x1 << GPIO_PUPD9_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD9_2 (0x2 << GPIO_PUPD9_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD10_Pos (20)
+#define GPIO_PUPD10_Msk (0x3 << GPIO_PUPD10_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD10 GPIO_PUPD10_Msk
+#define GPIO_PUPD10_0 (0x0 << GPIO_PUPD10_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD10_1 (0x1 << GPIO_PUPD10_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD10_2 (0x2 << GPIO_PUPD10_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD11_Pos (22)
+#define GPIO_PUPD11_Msk (0x3 << GPIO_PUPD11_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD11 GPIO_PUPD11_Msk
+#define GPIO_PUPD11_0 (0x0 << GPIO_PUPD11_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD11_1 (0x1 << GPIO_PUPD11_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD11_2 (0x2 << GPIO_PUPD11_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD12_Pos (24)
+#define GPIO_PUPD12_Msk (0x3 << GPIO_PUPD12_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD12 GPIO_PUPD12_Msk
+#define GPIO_PUPD12_0 (0x0 << GPIO_PUPD12_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD12_1 (0x1 << GPIO_PUPD12_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD12_2 (0x2 << GPIO_PUPD12_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD13_Pos (26)
+#define GPIO_PUPD13_Msk (0x3 << GPIO_PUPD13_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD13 GPIO_PUPD13_Msk
+#define GPIO_PUPD13_0 (0x0 << GPIO_PUPD13_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD13_1 (0x1 << GPIO_PUPD13_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD13_2 (0x2 << GPIO_PUPD13_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD14_Pos (28)
+#define GPIO_PUPD14_Msk (0x3 << GPIO_PUPD14_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD14 GPIO_PUPD14_Msk
+#define GPIO_PUPD14_0 (0x0 << GPIO_PUPD14_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD14_1 (0x1 << GPIO_PUPD14_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD14_2 (0x2 << GPIO_PUPD14_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD15_Pos (30)
+#define GPIO_PUPD15_Msk (0x3 << GPIO_PUPD15_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD15 GPIO_PUPD15_Msk
+#define GPIO_PUPD15_0 (0x0 << GPIO_PUPD15_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD15_1 (0x1 << GPIO_PUPD15_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD15_2 (0x2 << GPIO_PUPD15_Pos) /*!< 0x00000002 */
+
+
+/*!<****************** Bit definition for GPIO_IDR register *******************/
+#define GPIO_PID_PID0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */
+#define GPIO_PID_PID1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */
+#define GPIO_PID_PID2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */
+#define GPIO_PID_PID3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */
+#define GPIO_PID_PID4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */
+#define GPIO_PID_PID5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */
+#define GPIO_PID_PID6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */
+#define GPIO_PID_PID7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */
+#define GPIO_PID_PID8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */
+#define GPIO_PID_PID9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */
+#define GPIO_PID_PID10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */
+#define GPIO_PID_PID11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */
+#define GPIO_PID_PID12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */
+#define GPIO_PID_PID13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */
+#define GPIO_PID_PID14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */
+#define GPIO_PID_PID15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */
+
+/******************* Bit definition for GPIO_POD register *******************/
+#define GPIO_POD_POD0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */
+#define GPIO_POD_POD1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */
+#define GPIO_POD_POD2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */
+#define GPIO_POD_POD3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */
+#define GPIO_POD_POD4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */
+#define GPIO_POD_POD5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */
+#define GPIO_POD_POD6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */
+#define GPIO_POD_POD7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */
+#define GPIO_POD_POD8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */
+#define GPIO_POD_POD9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */
+#define GPIO_POD_POD10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */
+#define GPIO_POD_POD11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */
+#define GPIO_POD_POD12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */
+#define GPIO_POD_POD13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */
+#define GPIO_POD_POD14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */
+#define GPIO_POD_POD15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */
+
+/****************** Bit definition for GPIO_BSRR register *******************/
+#define GPIO_PBSC_PBS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */
+#define GPIO_PBSC_PBS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */
+#define GPIO_PBSC_PBS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */
+#define GPIO_PBSC_PBS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */
+#define GPIO_PBSC_PBS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */
+#define GPIO_PBSC_PBS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */
+#define GPIO_PBSC_PBS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */
+#define GPIO_PBSC_PBS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */
+#define GPIO_PBSC_PBS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */
+#define GPIO_PBSC_PBS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */
+#define GPIO_PBSC_PBS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */
+#define GPIO_PBSC_PBS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */
+#define GPIO_PBSC_PBS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */
+#define GPIO_PBSC_PBS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */
+#define GPIO_PBSC_PBS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */
+#define GPIO_PBSC_PBS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */
+
+#define GPIO_PBSC_PBC0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */
+#define GPIO_PBSC_PBC1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */
+#define GPIO_PBSC_PBC2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */
+#define GPIO_PBSC_PBC3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */
+#define GPIO_PBSC_PBC4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */
+#define GPIO_PBSC_PBC5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */
+#define GPIO_PBSC_PBC6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */
+#define GPIO_PBSC_PBC7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */
+#define GPIO_PBSC_PBC8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */
+#define GPIO_PBSC_PBC9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */
+#define GPIO_PBSC_PBC10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */
+#define GPIO_PBSC_PBC11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */
+#define GPIO_PBSC_PBC12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */
+#define GPIO_PBSC_PBC13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */
+#define GPIO_PBSC_PBC14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */
+#define GPIO_PBSC_PBC15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */
+
+/******************* Bit definition for GPIO_BRR register *******************/
+#define GPIO_PBC_PBC0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */
+#define GPIO_PBC_PBC1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */
+#define GPIO_PBC_PBC2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */
+#define GPIO_PBC_PBC3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */
+#define GPIO_PBC_PBC4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */
+#define GPIO_PBC_PBC5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */
+#define GPIO_PBC_PBC6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */
+#define GPIO_PBC_PBC7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */
+#define GPIO_PBC_PBC8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */
+#define GPIO_PBC_PBC9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */
+#define GPIO_PBC_PBC10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */
+#define GPIO_PBC_PBC11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */
+#define GPIO_PBC_PBC12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */
+#define GPIO_PBC_PBC13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */
+#define GPIO_PBC_PBC14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */
+#define GPIO_PBC_PBC15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */
+
+/****************** Bit definition for GPIO_LCKR register *******************/
+#define GPIO_PLOCK_PLOCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */
+#define GPIO_PLOCK_PLOCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */
+#define GPIO_PLOCK_PLOCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */
+#define GPIO_PLOCK_PLOCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */
+#define GPIO_PLOCK_PLOCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */
+#define GPIO_PLOCK_PLOCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */
+#define GPIO_PLOCK_PLOCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */
+#define GPIO_PLOCK_PLOCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */
+#define GPIO_PLOCK_PLOCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */
+#define GPIO_PLOCK_PLOCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */
+#define GPIO_PLOCK_PLOCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */
+#define GPIO_PLOCK_PLOCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */
+#define GPIO_PLOCK_PLOCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */
+#define GPIO_PLOCK_PLOCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */
+#define GPIO_PLOCK_PLOCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */
+#define GPIO_PLOCK_PLOCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */
+#define GPIO_PLOCK_PLOCKK ((uint32_t)0x00010000) /*!< Lock key */
+
+/****************** Bit definition for GPIO_AFL register *******************/
+#define GPIO_AFL_AFSEL0 ((uint32_t)0x0000000F) /*!< Port x AFL bit (0..3) */
+#define GPIO_AFL_AFSEL1 ((uint32_t)0x000000F0) /*!< Port x AFL bit (4..7) */
+#define GPIO_AFL_AFSEL2 ((uint32_t)0x00000F00) /*!< Port x AFL bit (8..11) */
+#define GPIO_AFL_AFSEL3 ((uint32_t)0x0000F000) /*!< Port x AFL bit (12..15) */
+#define GPIO_AFL_AFSEL4 ((uint32_t)0x000F0000) /*!< Port x AFL bit (16..19) */
+#define GPIO_AFL_AFSEL5 ((uint32_t)0x00F00000) /*!< Port x AFL bit (20..23) */
+#define GPIO_AFL_AFSEL6 ((uint32_t)0x0F000000) /*!< Port x AFL bit (24..27) */
+#define GPIO_AFL_AFSEL7 ((uint32_t)0xF0000000) /*!< Port x AFL bit (27..31) */
+
+/****************** Bit definition for GPIO_AFH register *******************/
+#define GPIO_AFH_AFSEL8 ((uint32_t)0x0000000F) /*!< Port x AFH bit (0..3) */
+#define GPIO_AFH_AFSEL9 ((uint32_t)0x000000F0) /*!< Port x AFH bit (4..7) */
+#define GPIO_AFH_AFSEL10 ((uint32_t)0x00000F00) /*!< Port x AFH bit (8..11) */
+#define GPIO_AFH_AFSEL11 ((uint32_t)0x0000F000) /*!< Port x AFH bit (12..15) */
+#define GPIO_AFH_AFSEL12 ((uint32_t)0x000F0000) /*!< Port x AFH bit (16..19) */
+#define GPIO_AFH_AFSEL13 ((uint32_t)0x00F00000) /*!< Port x AFH bit (20..23) */
+#define GPIO_AFH_AFSEL14 ((uint32_t)0x0F000000) /*!< Port x AFH bit (24..27) */
+#define GPIO_AFH_AFSEL15 ((uint32_t)0xF0000000) /*!< Port x AFH bit (27..31) */
+
+
+/******************* Bit definition for GPIO_DS register ******************/
+#define GPIO_DS0_Pos (0)
+#define GPIO_DS0_Msk (0x3 << GPIO_DS0_Pos) /*!< 0x00000003 */
+#define GPIO_DS0 GPIO_DS0_Msk
+#define GPIO_DS0_0 (0x0 << GPIO_DS0_Pos) /*!< 0x00000000 */
+#define GPIO_DS0_1 (0x1 << GPIO_DS0_Pos) /*!< 0x00000001 */
+#define GPIO_DS0_2 (0x2 << GPIO_DS0_Pos) /*!< 0x00000002 */
+#define GPIO_DS0_3 (0x3 << GPIO_DS0_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS1_Pos (2)
+#define GPIO_DS1_Msk (0x3 << GPIO_DS1_Pos) /*!< 0x00000003 */
+#define GPIO_DS1 GPIO_DS1_Msk
+#define GPIO_DS1_0 (0x0 << GPIO_DS1_Pos) /*!< 0x00000000 */
+#define GPIO_DS1_1 (0x1 << GPIO_DS1_Pos) /*!< 0x00000001 */
+#define GPIO_DS1_2 (0x2 << GPIO_DS1_Pos) /*!< 0x00000002 */
+#define GPIO_DS1_3 (0x3 << GPIO_DS1_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS2_Pos (4)
+#define GPIO_DS2_Msk (0x3 << GPIO_DS2_Pos) /*!< 0x00000003 */
+#define GPIO_DS2 GPIO_DS2_Msk
+#define GPIO_DS2_0 (0x0 << GPIO_DS2_Pos) /*!< 0x00000000 */
+#define GPIO_DS2_1 (0x1 << GPIO_DS2_Pos) /*!< 0x00000001 */
+#define GPIO_DS2_2 (0x2 << GPIO_DS2_Pos) /*!< 0x00000002 */
+#define GPIO_DS2_3 (0x3 << GPIO_DS2_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS3_Pos (6)
+#define GPIO_DS3_Msk (0x3 << GPIO_DS3_Pos) /*!< 0x00000003 */
+#define GPIO_DS3 GPIO_DS3_Msk
+#define GPIO_DS3_0 (0x0 << GPIO_DS3_Pos) /*!< 0x00000000 */
+#define GPIO_DS3_1 (0x1 << GPIO_DS3_Pos) /*!< 0x00000001 */
+#define GPIO_DS3_2 (0x2 << GPIO_DS3_Pos) /*!< 0x00000002 */
+#define GPIO_DS3_3 (0x3 << GPIO_DS3_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS4_Pos (8)
+#define GPIO_DS4_Msk (0x3 << GPIO_DS4_Pos) /*!< 0x00000003 */
+#define GPIO_DS4 GPIO_DS4_Msk
+#define GPIO_DS4_0 (0x0 << GPIO_DS4_Pos) /*!< 0x00000000 */
+#define GPIO_DS4_1 (0x1 << GPIO_DS4_Pos) /*!< 0x00000001 */
+#define GPIO_DS4_2 (0x2 << GPIO_DS4_Pos) /*!< 0x00000002 */
+#define GPIO_DS4_3 (0x3 << GPIO_DS4_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS5_Pos (10)
+#define GPIO_DS5_Msk (0x3 << GPIO_DS5_Pos) /*!< 0x00000003 */
+#define GPIO_DS5 GPIO_DS5_Msk
+#define GPIO_DS5_0 (0x0 << GPIO_DS5_Pos) /*!< 0x00000000 */
+#define GPIO_DS5_1 (0x1 << GPIO_DS5_Pos) /*!< 0x00000001 */
+#define GPIO_DS5_2 (0x2 << GPIO_DS5_Pos) /*!< 0x00000002 */
+#define GPIO_DS5_3 (0x3 << GPIO_DS5_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS6_Pos (12)
+#define GPIO_DS6_Msk (0x3 << GPIO_DS6_Pos) /*!< 0x00000003 */
+#define GPIO_DS6 GPIO_DS6_Msk
+#define GPIO_DS6_0 (0x0 << GPIO_DS6_Pos) /*!< 0x00000000 */
+#define GPIO_DS6_1 (0x1 << GPIO_DS6_Pos) /*!< 0x00000001 */
+#define GPIO_DS6_2 (0x2 << GPIO_DS6_Pos) /*!< 0x00000002 */
+#define GPIO_DS6_3 (0x3 << GPIO_DS6_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS7_Pos (14)
+#define GPIO_DS7_Msk (0x3 << GPIO_DS7_Pos) /*!< 0x00000003 */
+#define GPIO_DS7 GPIO_DS7_Msk
+#define GPIO_DS7_0 (0x0 << GPIO_DS7_Pos) /*!< 0x00000000 */
+#define GPIO_DS7_1 (0x1 << GPIO_DS7_Pos) /*!< 0x00000001 */
+#define GPIO_DS7_2 (0x2 << GPIO_DS7_Pos) /*!< 0x00000002 */
+#define GPIO_DS7_3 (0x3 << GPIO_DS7_Pos) /*!< 0x00000003 */
+
+
+#define GPIO_DS8_Pos (16)
+#define GPIO_DS8_Msk (0x3 << GPIO_DS8_Pos) /*!< 0x00000003 */
+#define GPIO_DS8 GPIO_DS8_Msk
+#define GPIO_DS8_0 (0x0 << GPIO_DS8_Pos) /*!< 0x00000000 */
+#define GPIO_DS8_1 (0x1 << GPIO_DS8_Pos) /*!< 0x00000001 */
+#define GPIO_DS8_2 (0x2 << GPIO_DS8_Pos) /*!< 0x00000002 */
+#define GPIO_DS8_3 (0x3 << GPIO_DS8_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS9_Pos (18)
+#define GPIO_DS9_Msk (0x3 << GPIO_DS9_Pos) /*!< 0x00000003 */
+#define GPIO_DS9 GPIO_DS9_Msk
+#define GPIO_DS9_0 (0x0 << GPIO_DS9_Pos) /*!< 0x00000000 */
+#define GPIO_DS9_1 (0x1 << GPIO_DS9_Pos) /*!< 0x00000001 */
+#define GPIO_DS9_2 (0x2 << GPIO_DS9_Pos) /*!< 0x00000002 */
+#define GPIO_DS9_3 (0x3 << GPIO_DS9_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS10_Pos (20)
+#define GPIO_DS10_Msk (0x3 << GPIO_DS10_Pos) /*!< 0x00000003 */
+#define GPIO_DS10 GPIO_DS10_Msk
+#define GPIO_DS10_0 (0x0 << GPIO_DS10_Pos) /*!< 0x00000000 */
+#define GPIO_DS10_1 (0x1 << GPIO_DS10_Pos) /*!< 0x00000001 */
+#define GPIO_DS10_2 (0x2 << GPIO_DS10_Pos) /*!< 0x00000002 */
+#define GPIO_DS10_3 (0x3 << GPIO_DS10_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS11_Pos (22)
+#define GPIO_DS11_Msk (0x3 << GPIO_DS11_Pos) /*!< 0x00000003 */
+#define GPIO_DS11 GPIO_DS11_Msk
+#define GPIO_DS11_0 (0x0 << GPIO_DS11_Pos) /*!< 0x00000000 */
+#define GPIO_DS11_1 (0x1 << GPIO_DS11_Pos) /*!< 0x00000001 */
+#define GPIO_DS11_2 (0x2 << GPIO_DS11_Pos) /*!< 0x00000002 */
+#define GPIO_DS11_3 (0x3 << GPIO_DS11_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS12_Pos (24)
+#define GPIO_DS12_Msk (0x3 << GPIO_DS12_Pos) /*!< 0x00000003 */
+#define GPIO_DS12 GPIO_DS12_Msk
+#define GPIO_DS12_0 (0x0 << GPIO_DS12_Pos) /*!< 0x00000000 */
+#define GPIO_DS12_1 (0x1 << GPIO_DS12_Pos) /*!< 0x00000001 */
+#define GPIO_DS12_2 (0x2 << GPIO_DS12_Pos) /*!< 0x00000002 */
+#define GPIO_DS12_3 (0x3 << GPIO_DS12_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS13_Pos (26)
+#define GPIO_DS13_Msk (0x3 << GPIO_DS13_Pos) /*!< 0x00000003 */
+#define GPIO_DS13 GPIO_DS13_Msk
+#define GPIO_DS13_0 (0x0 << GPIO_DS13_Pos) /*!< 0x00000000 */
+#define GPIO_DS13_1 (0x1 << GPIO_DS13_Pos) /*!< 0x00000001 */
+#define GPIO_DS13_2 (0x2 << GPIO_DS13_Pos) /*!< 0x00000002 */
+#define GPIO_DS13_3 (0x3 << GPIO_DS13_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS14_Pos (28)
+#define GPIO_DS14_Msk (0x3 << GPIO_DS14_Pos) /*!< 0x00000003 */
+#define GPIO_DS14 GPIO_DS14_Msk
+#define GPIO_DS14_0 (0x0 << GPIO_DS14_Pos) /*!< 0x00000000 */
+#define GPIO_DS14_1 (0x1 << GPIO_DS14_Pos) /*!< 0x00000001 */
+#define GPIO_DS14_2 (0x2 << GPIO_DS14_Pos) /*!< 0x00000002 */
+#define GPIO_DS14_3 (0x3 << GPIO_DS14_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS15_Pos (30)
+#define GPIO_DS15_Msk (0x3 << GPIO_DS15_Pos) /*!< 0x00000003 */
+#define GPIO_DS15 GPIO_DS15_Msk
+#define GPIO_DS15_0 (0x0 << GPIO_DS15_Pos) /*!< 0x00000000 */
+#define GPIO_DS15_1 (0x1 << GPIO_DS15_Pos) /*!< 0x00000001 */
+#define GPIO_DS15_2 (0x2 << GPIO_DS15_Pos) /*!< 0x00000002 */
+#define GPIO_DS15_3 (0x3 << GPIO_DS15_Pos) /*!< 0x00000003 */
+
+/******************* Bit definition for GPIO_SR register *******************/
+#define GPIO_SR_SR0 ((uint16_t)0x0001) /*!< Slew rate bit 0 */
+#define GPIO_SR_SR1 ((uint16_t)0x0002) /*!< Slew rate bit 1 */
+#define GPIO_SR_SR2 ((uint16_t)0x0004) /*!< Slew rate bit 2 */
+#define GPIO_SR_SR3 ((uint16_t)0x0008) /*!< Slew rate bit 3 */
+#define GPIO_SR_SR4 ((uint16_t)0x0010) /*!< Slew rate bit 4 */
+#define GPIO_SR_SR5 ((uint16_t)0x0020) /*!< Slew rate bit 5 */
+#define GPIO_SR_SR6 ((uint16_t)0x0040) /*!< Slew rate bit 6 */
+#define GPIO_SR_SR7 ((uint16_t)0x0080) /*!< Slew rate bit 7 */
+#define GPIO_SR_SR8 ((uint16_t)0x0100) /*!< Slew rate bit 8 */
+#define GPIO_SR_SR9 ((uint16_t)0x0200) /*!< Slew rate bit 9 */
+#define GPIO_SR_SR10 ((uint16_t)0x0400) /*!< Slew rate bit 10 */
+#define GPIO_SR_SR11 ((uint16_t)0x0800) /*!< Slew rate bit 11 */
+#define GPIO_SR_SR12 ((uint16_t)0x1000) /*!< Slew rate bit 12 */
+#define GPIO_SR_SR13 ((uint16_t)0x2000) /*!< Slew rate bit 13 */
+#define GPIO_SR_SR14 ((uint16_t)0x4000) /*!< Slew rate bit 14 */
+#define GPIO_SR_SR15 ((uint16_t)0x8000) /*!< Slew rate bit 15 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for AFIO_RMP_CFG register *****************/
+#define AFIO_RMP_CFG_SPI1_NSS ((uint16_t)0x0800) /*!< AFIO_RMP_CFG bit 11 */
+#define AFIO_RMP_CFG_SPI2_NSS ((uint16_t)0x0400) /*!< AFIO_RMP_CFG bit 10 */
+#define AFIO_RMP_CFG_ADC_ETRI ((uint16_t)0x0200) /*!< AFIO_RMP_CFG bit 9 */
+#define AFIO_RMP_CFG_ADC_ETRR ((uint16_t)0x0100) /*!< AFIO_RMP_CFG bit 8 */
+#define AFIO_RMP_CFG_EXTI_ETRI ((uint16_t)0x00F0) /*!< AFIO_RMP_CFG bit (4..7) */
+#define AFIO_RMP_CFG_EXTI_ETRR ((uint16_t)0x000F) /*!< AFIO_RMP_CFG bit (0..3) */
+
+/***************** Bit definition for AFIO_EXTICR1 register *****************/
+#define AFIO_EXTI_CFG1_EXTI0 ((uint16_t)0x0003) /*!< EXTI 0 configuration */
+#define AFIO_EXTI_CFG1_EXTI1 ((uint16_t)0x0030) /*!< EXTI 1 configuration */
+#define AFIO_EXTI_CFG1_EXTI2 ((uint16_t)0x0300) /*!< EXTI 2 configuration */
+#define AFIO_EXTI_CFG1_EXTI3 ((uint16_t)0x3000) /*!< EXTI 3 configuration */
+
+/*!< EXTI0 configuration */
+#define AFIO_EXTI_CFG1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
+#define AFIO_EXTI_CFG1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
+#define AFIO_EXTI_CFG1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
+#define AFIO_EXTI_CFG1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
+
+/*!< EXTI1 configuration */
+#define AFIO_EXTI_CFG1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
+#define AFIO_EXTI_CFG1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
+#define AFIO_EXTI_CFG1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
+#define AFIO_EXTI_CFG1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
+
+/*!< EXTI2 configuration */
+#define AFIO_EXTI_CFG1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
+#define AFIO_EXTI_CFG1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
+#define AFIO_EXTI_CFG1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
+#define AFIO_EXTI_CFG1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
+
+/*!< EXTI3 configuration */
+#define AFIO_EXTI_CFG1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
+#define AFIO_EXTI_CFG1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
+#define AFIO_EXTI_CFG1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
+#define AFIO_EXTI_CFG1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
+
+/***************** Bit definition for AFIO_EXTICR2 register *****************/
+#define AFIO_EXTI_CFG2_EXTI4 ((uint16_t)0x0003) /*!< EXTI 4 configuration */
+#define AFIO_EXTI_CFG2_EXTI5 ((uint16_t)0x0030) /*!< EXTI 5 configuration */
+#define AFIO_EXTI_CFG2_EXTI6 ((uint16_t)0x0300) /*!< EXTI 6 configuration */
+#define AFIO_EXTI_CFG2_EXTI7 ((uint16_t)0x3000) /*!< EXTI 7 configuration */
+
+/*!< EXTI4 configuration */
+#define AFIO_EXTI_CFG2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
+#define AFIO_EXTI_CFG2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
+#define AFIO_EXTI_CFG2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
+#define AFIO_EXTI_CFG2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
+
+/*!< EXTI5 configuration */
+#define AFIO_EXTI_CFG2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
+#define AFIO_EXTI_CFG2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
+#define AFIO_EXTI_CFG2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
+#define AFIO_EXTI_CFG2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
+
+/*!< EXTI6 configuration */
+#define AFIO_EXTI_CFG2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
+#define AFIO_EXTI_CFG2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
+#define AFIO_EXTI_CFG2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
+#define AFIO_EXTI_CFG2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
+
+/*!< EXTI7 configuration */
+#define AFIO_EXTI_CFG2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
+#define AFIO_EXTI_CFG2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
+#define AFIO_EXTI_CFG2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
+#define AFIO_EXTI_CFG2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
+
+/***************** Bit definition for AFIO_EXTICR3 register *****************/
+#define AFIO_EXTI_CFG3_EXTI8 ((uint16_t)0x0003) /*!< EXTI 8 configuration */
+#define AFIO_EXTI_CFG3_EXTI9 ((uint16_t)0x0030) /*!< EXTI 9 configuration */
+#define AFIO_EXTI_CFG3_EXTI10 ((uint16_t)0x0300) /*!< EXTI 10 configuration */
+#define AFIO_EXTI_CFG3_EXTI11 ((uint16_t)0x3000) /*!< EXTI 11 configuration */
+
+/*!< EXTI8 configuration */
+#define AFIO_EXTI_CFG3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
+#define AFIO_EXTI_CFG3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
+#define AFIO_EXTI_CFG3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
+#define AFIO_EXTI_CFG3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
+
+/*!< EXTI9 configuration */
+#define AFIO_EXTI_CFG3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
+#define AFIO_EXTI_CFG3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
+#define AFIO_EXTI_CFG3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
+#define AFIO_EXTI_CFG3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
+
+/*!< EXTI10 configuration */
+#define AFIO_EXTI_CFG3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
+#define AFIO_EXTI_CFG3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
+#define AFIO_EXTI_CFG3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
+#define AFIO_EXTI_CFG3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
+
+/*!< EXTI11 configuration */
+#define AFIO_EXTI_CFG3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
+#define AFIO_EXTI_CFG3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
+#define AFIO_EXTI_CFG3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
+#define AFIO_EXTI_CFG3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
+
+/***************** Bit definition for AFIO_EXTICR4 register *****************/
+#define AFIO_EXTI_CFG4_EXTI12 ((uint16_t)0x0003) /*!< EXTI 12 configuration */
+#define AFIO_EXTI_CFG4_EXTI13 ((uint16_t)0x0030) /*!< EXTI 13 configuration */
+#define AFIO_EXTI_CFG4_EXTI14 ((uint16_t)0x0300) /*!< EXTI 14 configuration */
+#define AFIO_EXTI_CFG4_EXTI15 ((uint16_t)0x3000) /*!< EXTI 15 configuration */
+
+/*!< EXTI12 configuration */
+#define AFIO_EXTI_CFG4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
+#define AFIO_EXTI_CFG4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
+#define AFIO_EXTI_CFG4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
+#define AFIO_EXTI_CFG4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
+
+/*!< EXTI13 configuration */
+#define AFIO_EXTI_CFG4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
+#define AFIO_EXTI_CFG4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
+#define AFIO_EXTI_CFG4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
+#define AFIO_EXTI_CFG4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
+
+/*!< EXTI14 configuration */
+#define AFIO_EXTI_CFG4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
+#define AFIO_EXTI_CFG4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
+#define AFIO_EXTI_CFG4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
+#define AFIO_EXTI_CFG4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
+
+/*!< EXTI15 configuration */
+#define AFIO_EXTI_CFG4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
+#define AFIO_EXTI_CFG4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
+#define AFIO_EXTI_CFG4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
+#define AFIO_EXTI_CFG4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMASK_IMASK0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMASK_IMASK1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMASK_IMASK2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMASK_IMASK3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMASK_IMASK4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMASK_IMASK5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMASK_IMASK6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMASK_IMASK7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMASK_IMASK8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMASK_IMASK9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMASK_IMASK10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMASK_IMASK11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMASK_IMASK12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMASK_IMASK13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMASK_IMASK14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMASK_IMASK15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMASK_IMASK16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMASK_IMASK17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMASK_IMASK18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMASK_IMASK19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMASK_IMASK20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMASK_IMASK21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMASK_IMASK22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
+#define EXTI_IMASK_IMASK23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
+#define EXTI_IMASK_IMASK24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */
+#define EXTI_IMASK_IMASK25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
+#define EXTI_IMASK_IMASK26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
+#define EXTI_IMASK_IMASK27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMASK_EMASK0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMASK_EMASK1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMASK_EMASK2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMASK_EMASK3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMASK_EMASK4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMASK_EMASK5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMASK_EMASK6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMASK_EMASK7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMASK_EMASK8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMASK_EMASK9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMASK_EMASK10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMASK_EMASK11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMASK_EMASK12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMASK_EMASK13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMASK_EMASK14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMASK_EMASK15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMASK_EMASK16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMASK_EMASK17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMASK_EMASK18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+#define EXTI_EMASK_EMASK19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMASK_EMASK20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMASK_EMASK21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMASK_EMASK22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
+#define EXTI_EMASK_EMASK23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
+#define EXTI_EMASK_EMASK24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */
+#define EXTI_EMASK_EMASK25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
+#define EXTI_EMASK_EMASK26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
+#define EXTI_EMASK_EMASK27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
+
+
+/****************** Bit definition for EXTI_RT_CFG register *******************/
+#define EXTI_EMASK_RT_CFG_RT_CFG0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_EMASK_RT_CFG_RT_CFG1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_EMASK_RT_CFG_RT_CFG2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_EMASK_RT_CFG_RT_CFG3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_EMASK_RT_CFG_RT_CFG4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_EMASK_RT_CFG_RT_CFG5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_EMASK_RT_CFG_RT_CFG6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_EMASK_RT_CFG_RT_CFG7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_EMASK_RT_CFG_RT_CFG8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_EMASK_RT_CFG_RT_CFG9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_EMASK_RT_CFG_RT_CFG10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_EMASK_RT_CFG_RT_CFG11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_EMASK_RT_CFG_RT_CFG12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_EMASK_RT_CFG_RT_CFG13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_EMASK_RT_CFG_RT_CFG14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_EMASK_RT_CFG_RT_CFG15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_EMASK_RT_CFG_RT_CFG16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_EMASK_RT_CFG_RT_CFG17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_EMASK_RT_CFG_RT_CFG18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_EMASK_RT_CFG_RT_CFG19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_EMASK_RT_CFG_RT_CFG20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_EMASK_RT_CFG_RT_CFG21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_EMASK_RT_CFG_RT_CFG22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
+#define EXTI_EMASK_RT_CFG_RT_CFG23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
+#define EXTI_EMASK_RT_CFG_RT_CFG24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
+#define EXTI_EMASK_RT_CFG_RT_CFG25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
+#define EXTI_EMASK_RT_CFG_RT_CFG26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
+#define EXTI_EMASK_RT_CFG_RT_CFG27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
+
+
+
+/****************** Bit definition for EXTI_FT_CFG register *******************/
+#define EXTI_EMASK_FT_CFG_FT_CFG0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_EMASK_FT_CFG_FT_CFG1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_EMASK_FT_CFG_FT_CFG2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_EMASK_FT_CFG_FT_CFG3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_EMASK_FT_CFG_FT_CFG4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_EMASK_FT_CFG_FT_CFG5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_EMASK_FT_CFG_FT_CFG6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_EMASK_FT_CFG_FT_CFG7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_EMASK_FT_CFG_FT_CFG8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_EMASK_FT_CFG_FT_CFG9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_EMASK_FT_CFG_FT_CFG10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_EMASK_FT_CFG_FT_CFG11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_EMASK_FT_CFG_FT_CFG12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_EMASK_FT_CFG_FT_CFG13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_EMASK_FT_CFG_FT_CFG14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_EMASK_FT_CFG_FT_CFG15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_EMASK_FT_CFG_FT_CFG16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_EMASK_FT_CFG_FT_CFG17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_EMASK_FT_CFG_FT_CFG18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_EMASK_FT_CFG_FT_CFG19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_EMASK_FT_CFG_FT_CFG20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_EMASK_FT_CFG_FT_CFG21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_EMASK_FT_CFG_FT_CFG22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
+#define EXTI_EMASK_FT_CFG_FT_CFG23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
+#define EXTI_EMASK_FT_CFG_FT_CFG24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
+#define EXTI_EMASK_FT_CFG_FT_CFG25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
+#define EXTI_EMASK_FT_CFG_FT_CFG26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
+#define EXTI_EMASK_FT_CFG_FT_CFG27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
+
+/****************** Bit definition for EXTI_SWIE register ******************/
+#define EXTI_SWIE_SWIE0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIE_SWIE1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIE_SWIE2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIE_SWIE3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIE_SWIE4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIE_SWIE5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIE_SWIE6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIE_SWIE7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIE_SWIE8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIE_SWIE9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIE_SWIE10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIE_SWIE11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIE_SWIE12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIE_SWIE13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIE_SWIE14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIE_SWIE15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIE_SWIE16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIE_SWIE17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIE_SWIE18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
+#define EXTI_SWIE_SWIE19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIE_SWIE20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIE_SWIE21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIE_SWIE22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
+#define EXTI_SWIE_SWIE23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
+#define EXTI_SWIE_SWIE24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
+#define EXTI_SWIE_SWIE25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
+#define EXTI_SWIE_SWIE26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
+#define EXTI_SWIE_SWIE27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
+
+/******************* Bit definition for EXTI_PEND register ********************/
+#define EXTI_PEND_PEND0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
+#define EXTI_PEND_PEND1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
+#define EXTI_PEND_PEND2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
+#define EXTI_PEND_PEND3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
+#define EXTI_PEND_PEND4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
+#define EXTI_PEND_PEND5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
+#define EXTI_PEND_PEND6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
+#define EXTI_PEND_PEND7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
+#define EXTI_PEND_PEND8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
+#define EXTI_PEND_PEND9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
+#define EXTI_PEND_PEND10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
+#define EXTI_PEND_PEND11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
+#define EXTI_PEND_PEND12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
+#define EXTI_PEND_PEND13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
+#define EXTI_PEND_PEND14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
+#define EXTI_PEND_PEND15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
+#define EXTI_PEND_PEND16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
+#define EXTI_PEND_PEND17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
+#define EXTI_PEND_PEND18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
+#define EXTI_PEND_PEND19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PEND_PEND20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PEND_PEND21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PEND_PEND22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
+#define EXTI_PEND_PEND23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
+#define EXTI_PEND_PEND24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
+#define EXTI_PEND_PEND25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
+#define EXTI_PEND_PEND26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
+#define EXTI_PEND_PEND27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
+
+
+/******************************************************************************/
+/* */
+/* LCD Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for LCD_CTRL register *******************/
+#define LCD_CTRL_BUFEN_Msk ((uint32_t)0x00000100)
+#define LCD_CTRL_BUFEN_Pos (8U)
+#define LCD_CTRL_BUFEN (LCD_CTRL_BUFEN_Msk) /*!< High driving capacity buffer enable bit*/
+
+#define LCD_CTRL_MUXSEG_Msk ((uint32_t)0x00000080)
+#define LCD_CTRL_MUXSEG_Pos (7U)
+#define LCD_CTRL_MUXSEG (LCD_CTRL_MUXSEG_Msk) /*!< Mux segment enable bit*/
+
+#define LCD_CTRL_BIAS_Msk ((uint32_t)0x00000060)
+#define LCD_CTRL_BIAS_Pos (5U)
+#define LCD_CTRL_BIAS (LCD_CTRL_BIAS_Msk)
+#define LCD_CTRL_BIAS_0 (0x1UL << LCD_CTRL_BIAS_Pos) /*!< Bias selector bit*/
+#define LCD_CTRL_BIAS_1 (0x2UL << LCD_CTRL_BIAS_Pos)
+
+#define LCD_CTRL_DUTY_Msk ((uint32_t)0x0000001C)
+#define LCD_CTRL_DUTY_Pos (2U)
+#define LCD_CTRL_DUTY (LCD_CTRL_DUTY_Msk) /*!< Duty selection bit*/
+#define LCD_CTRL_DUTY_0 (0x1UL << LCD_CTRL_DUTY_Pos)
+#define LCD_CTRL_DUTY_1 (0x2UL << LCD_CTRL_DUTY_Pos)
+#define LCD_CTRL_DUTY_2 (0x4UL << LCD_CTRL_DUTY_Pos)
+
+#define LCD_CTRL_VSEL_Msk ((uint32_t)0x00000002)
+#define LCD_CTRL_VSEL_Pos (1U)
+#define LCD_CTRL_VSEL (LCD_CTRL_VSEL_Msk) /*!< Voltage source selection bit*/
+
+#define LCD_CTRL_LCDEN_Msk ((uint32_t)0x00000001)
+#define LCD_CTRL_LCDEN_Pos (0U)
+#define LCD_CTRL_LCDEN (LCD_CTRL_LCDEN_Msk) /*!< LCD controller enable bit*/
+
+/******************* Bit definition for LCD_FCTRL register *******************/
+#define LCD_FCTRL_PRES_Msk ((uint32_t)0x03C00000)
+#define LCD_FCTRL_PRES_Pos (22U)
+#define LCD_FCTRL_PRES (LCD_FCTRL_PRES_Msk) /*!< 16-bit prescaler bit*/
+#define LCD_FCTRL_PRES_0 (0x1UL << LCD_FCTRL_PRES_Pos)
+#define LCD_FCTRL_PRES_1 (0x2UL << LCD_FCTRL_PRES_Pos)
+#define LCD_FCTRL_PRES_2 (0x4UL << LCD_FCTRL_PRES_Pos)
+#define LCD_FCTRL_PRES_3 (0x8UL << LCD_FCTRL_PRES_Pos)
+
+#define LCD_FCTRL_DIV_Msk ((uint32_t)0x003C0000)
+#define LCD_FCTRL_DIV_Pos (18U)
+#define LCD_FCTRL_DIV (LCD_FCTRL_DIV_Msk) /*!< DIV clock divider bit*/
+#define LCD_FCTRL_DIV_0 (0x1UL << LCD_FCTRL_DIV_Pos)
+#define LCD_FCTRL_DIV_1 (0x2UL << LCD_FCTRL_DIV_Pos)
+#define LCD_FCTRL_DIV_2 (0x4UL << LCD_FCTRL_DIV_Pos)
+#define LCD_FCTRL_DIV_3 (0x8UL << LCD_FCTRL_DIV_Pos)
+
+#define LCD_FCTRL_BLINK_Msk ((uint32_t)0x00030000)
+#define LCD_FCTRL_BLINK_Pos (16U)
+#define LCD_FCTRL_BLINK (LCD_FCTRL_BLINK_Msk) /*!< Blink mode selection bit*/
+#define LCD_FCTRL_BLINK_0 (0x1UL << LCD_FCTRL_BLINK_Pos)
+#define LCD_FCTRL_BLINK_1 (0x2UL << LCD_FCTRL_BLINK_Pos)
+
+#define LCD_FCTRL_BLINKF_Msk ((uint32_t)0x0000E000)
+#define LCD_FCTRL_BLINKF_Pos (13U)
+#define LCD_FCTRL_BLINKF (LCD_FCTRL_BLINKF_Msk) /*!< Blink frequency selection bit*/
+#define LCD_FCTRL_BLINKF_0 (0x1UL << LCD_FCTRL_BLINKF_Pos)
+#define LCD_FCTRL_BLINKF_1 (0x2UL << LCD_FCTRL_BLINKF_Pos)
+#define LCD_FCTRL_BLINKF_2 (0x4UL << LCD_FCTRL_BLINKF_Pos)
+
+#define LCD_FCTRL_CONTRAST_Msk ((uint32_t)0x00001C00)
+#define LCD_FCTRL_CONTRAST_Pos (10U)
+#define LCD_FCTRL_CONTRAST (LCD_FCTRL_CONTRAST_Msk) /*!< Contrast Control bit*/
+#define LCD_FCTRL_CONTRAST_0 (0x1UL << LCD_FCTRL_CONTRAST_Pos)
+#define LCD_FCTRL_CONTRAST_1 (0x2UL << LCD_FCTRL_CONTRAST_Pos)
+#define LCD_FCTRL_CONTRAST_2 (0x4UL << LCD_FCTRL_CONTRAST_Pos)
+
+#define LCD_FCTRL_DEAD_Msk ((uint32_t)0x00000380)
+#define LCD_FCTRL_DEAD_Pos (7U)
+#define LCD_FCTRL_DEAD (LCD_FCTRL_DEAD_Msk) /*!< Dead time duration bit*/
+#define LCD_FCTRL_DEAD_0 (0x1UL << LCD_FCTRL_DEAD_Pos)
+#define LCD_FCTRL_DEAD_1 (0x2UL << LCD_FCTRL_DEAD_Pos)
+#define LCD_FCTRL_DEAD_2 (0x4UL << LCD_FCTRL_DEAD_Pos)
+
+#define LCD_FCTRL_PULSEON_Msk ((uint32_t)0x00000070)
+#define LCD_FCTRL_PULSEON_Pos (4U)
+#define LCD_FCTRL_PULSEON (LCD_FCTRL_PULSEON_Msk) /*!< Pulse on duration bit*/
+#define LCD_FCTRL_PULSEON_0 (0x1UL << LCD_FCTRL_PULSEON_Pos)
+#define LCD_FCTRL_PULSEON_1 (0x2UL << LCD_FCTRL_PULSEON_Pos)
+#define LCD_FCTRL_PULSEON_2 (0x4UL << LCD_FCTRL_PULSEON_Pos)
+
+#define LCD_FCTRL_UDDIE_Msk ((uint32_t)0x00000008)
+#define LCD_FCTRL_UDDIE_Pos (3U)
+#define LCD_FCTRL_UDDIE (LCD_FCTRL_UDDIE_Msk) /*!< Update display done interrupt enable bit*/
+
+#define LCD_FCTRL_SOFIE_Msk ((uint32_t)0x00000002)
+#define LCD_FCTRL_SOFIE_Pos (1U)
+#define LCD_FCTRL_SOFIE (LCD_FCTRL_SOFIE_Msk) /*!< Start of frame interrupt enable bit*/
+
+#define LCD_FCTRL_HDEN_Msk ((uint32_t)0x00000001)
+#define LCD_FCTRL_HDEN_Pos (0U)
+#define LCD_FCTRL_HDEN (LCD_FCTRL_HDEN_Msk) /*!< High drive enable bit*/
+
+/******************* Bit definition for LCD_STS register *******************/
+#define LCD_STS_FCRSF_Msk ((uint32_t)0x00000020)
+#define LCD_STS_FCRSF_Pos (5U)
+#define LCD_STS_FCRSF (LCD_STS_FCRSF_Msk) /*!< LCD Frame Control Register Synchronization flag bit*/
+
+#define LCD_STS_RDY_Msk ((uint32_t)0x00000010)
+#define LCD_STS_RDY_Pos (4U)
+#define LCD_STS_RDY (LCD_STS_RDY_Msk) /*!< VLCD Ready Flag bit*/
+
+#define LCD_STS_UDD_Msk ((uint32_t)0x00000008)
+#define LCD_STS_UDD_Pos (3U)
+#define LCD_STS_UDD (LCD_STS_UDD_Msk) /*!< Update Display Done bit*/
+
+#define LCD_STS_UDR_Msk ((uint32_t)0x00000004)
+#define LCD_STS_UDR_Pos (2U)
+#define LCD_STS_UDR (LCD_STS_UDR_Msk) /*!< Update Display Request bit*/
+
+#define LCD_STS_SOF_Msk ((uint32_t)0x00000002)
+#define LCD_STS_SOF_Pos (1U)
+#define LCD_STS_SOF (LCD_STS_SOF_Msk) /*!< Start of Frame flag*/
+
+#define LCD_STS_ENSTS_Msk ((uint32_t)0x00000001)
+#define LCD_STS_ENSTS_Pos (0U)
+#define LCD_STS_ENSTS (LCD_STS_ENSTS_Msk) /*!< LCD state bit*/
+
+/******************* Bit definition for LCD_CLR register *******************/
+#define LCD_CLR_UDDCLR_Msk ((uint32_t)0x00000008) /*!< Update display done clear bit*/
+#define LCD_CLR_UDDCLR_Pos (3U)
+#define LCD_CLR_UDDCLR (LCD_CLR_UDDCLR_Msk)
+
+#define LCD_CLR_SOFCLR_Msk ((uint32_t)0x00000002) /*!FLASH
+
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ /* section information for finsh shell */
+ . = ALIGN(4);
+ __fsymtab_start = .;
+ KEEP(*(FSymTab))
+ __fsymtab_end = .;
+
+ . = ALIGN(4);
+ __vsymtab_start = .;
+ KEEP(*(VSymTab))
+ __vsymtab_end = .;
+
+ /* section information for initial. */
+ . = ALIGN(4);
+ __rt_init_start = .;
+ KEEP(*(SORT(.rti_fn*)))
+ __rt_init_end = .;
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data goes into FLASH */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >FLASH
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH
+
+ /* used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(4);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(4);
+ } >RAM
+
+
+
+ /* Remove information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/startup/startup_n32l40x.s b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/startup/startup_n32l40x.s
new file mode 100644
index 0000000000..cee6fb09b2
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/startup/startup_n32l40x.s
@@ -0,0 +1,373 @@
+; ****************************************************************************
+; Copyright (c) 2019, Nations Technologies Inc.
+;
+; All rights reserved.
+; ****************************************************************************
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; - Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the disclaimer below.
+;
+; Nations' name may not be used to endorse or promote products derived from
+; this software without specific prior written permission.
+;
+; DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+; DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+; OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; ****************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00001500
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000300
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; RTC Tamper interrupt or Timestamp through EXTI line 19 interrupt
+ DCD RTC_WKUP_IRQHandler ; RTC_WKUP
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA_Channel1_IRQHandler ; DMA Channel 1
+ DCD DMA_Channel2_IRQHandler ; DMA Channel 2
+ DCD DMA_Channel3_IRQHandler ; DMA Channel 3
+ DCD DMA_Channel4_IRQHandler ; DMA Channel 4
+ DCD DMA_Channel5_IRQHandler ; DMA Channel 5
+ DCD DMA_Channel6_IRQHandler ; DMA Channel 6
+ DCD DMA_Channel7_IRQHandler ; DMA Channel 7
+ DCD DMA_Channel8_IRQHandler ; DMA Channel 8
+ DCD ADC_IRQHandler ; ADC
+ DCD USB_HP_IRQHandler ; USB High Priority
+ DCD USB_LP_IRQHandler ; USB Low Priority
+ DCD COMP_1_2_IRQHandler ; COMP1 & COMP2 through EXTI line 21/22
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
+ DCD TIM8_BRK_IRQHandler ; TIM8 Break
+ DCD TIM8_UP_IRQHandler ; TIM8 Update
+ DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD LPUART_IRQHandler ; LPUART
+ DCD TIM5_IRQHandler ; TIM5
+ DCD TIM6_IRQHandler ; TIM6
+ DCD TIM7_IRQHandler ; TIM7
+ DCD CAN_TX_IRQHandler ; CAN TX
+ DCD CAN_RX0_IRQHandler ; CAN RX0
+ DCD CAN_RX1_IRQHandler ; CAN RX1
+ DCD CAN_SCE_IRQHandler ; CAN SCE
+ DCD LPUART_WKUP_IRQHandler ; LPUART_WKUP
+ DCD LPTIM_WKUP_IRQHandler ; LPTIM_WKUP
+ DCD LCD_IRQHandler ; LCD
+ DCD SAC_IRQHandler ; SAC
+ DCD MMU_IRQHandler ; MMU
+ DCD TSC_IRQHandler ; TSC
+ DCD RAMC_PERR_IRQHandler ; RAMC ERR
+ DCD TIM9_IRQHandler ; TIM9
+ DCD UCDR_IRQHandler ; UCDR ERR
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ IMPORT SystemInit
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_IRQHandler [WEAK]
+ EXPORT TAMPER_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA_Channel1_IRQHandler [WEAK]
+ EXPORT DMA_Channel2_IRQHandler [WEAK]
+ EXPORT DMA_Channel3_IRQHandler [WEAK]
+ EXPORT DMA_Channel4_IRQHandler [WEAK]
+ EXPORT DMA_Channel5_IRQHandler [WEAK]
+ EXPORT DMA_Channel6_IRQHandler [WEAK]
+ EXPORT DMA_Channel7_IRQHandler [WEAK]
+ EXPORT DMA_Channel8_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT USB_HP_IRQHandler [WEAK]
+ EXPORT USB_LP_IRQHandler [WEAK]
+ EXPORT COMP_1_2_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTCAlarm_IRQHandler [WEAK]
+ EXPORT USBWakeUp_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_IRQHandler [WEAK]
+ EXPORT TIM8_UP_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT LPUART_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT TIM6_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT CAN_TX_IRQHandler [WEAK]
+ EXPORT CAN_RX0_IRQHandler [WEAK]
+ EXPORT CAN_RX1_IRQHandler [WEAK]
+ EXPORT CAN_SCE_IRQHandler [WEAK]
+ EXPORT LPUART_WKUP_IRQHandler [WEAK]
+ EXPORT LPTIM_WKUP_IRQHandler [WEAK]
+ EXPORT LCD_IRQHandler [WEAK]
+ EXPORT SAC_IRQHandler [WEAK]
+ EXPORT MMU_IRQHandler [WEAK]
+ EXPORT TSC_IRQHandler [WEAK]
+ EXPORT RAMC_PERR_IRQHandler [WEAK]
+ EXPORT TIM9_IRQHandler [WEAK]
+ EXPORT UCDR_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA_Channel1_IRQHandler
+DMA_Channel2_IRQHandler
+DMA_Channel3_IRQHandler
+DMA_Channel4_IRQHandler
+DMA_Channel5_IRQHandler
+DMA_Channel6_IRQHandler
+DMA_Channel7_IRQHandler
+DMA_Channel8_IRQHandler
+ADC_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+COMP_1_2_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+USBWakeUp_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+LPUART_IRQHandler
+TIM5_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+CAN_TX_IRQHandler
+CAN_RX0_IRQHandler
+CAN_RX1_IRQHandler
+CAN_SCE_IRQHandler
+LPUART_WKUP_IRQHandler
+LPTIM_WKUP_IRQHandler
+LCD_IRQHandler
+SAC_IRQHandler
+MMU_IRQHandler
+TSC_IRQHandler
+RAMC_PERR_IRQHandler
+TIM9_IRQHandler
+UCDR_IRQHandler
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/startup/startup_n32l40x_EWARM.s b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/startup/startup_n32l40x_EWARM.s
new file mode 100644
index 0000000000..e9a39bed20
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/startup/startup_n32l40x_EWARM.s
@@ -0,0 +1,523 @@
+; ****************************************************************************
+; Copyright (c) 2019, Nations Technologies Inc.
+;
+; All rights reserved.
+; ****************************************************************************
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; - Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the disclaimer below.
+;
+; Nations name may not be used to endorse or promote products derived from
+; this software without specific prior written permission.
+;
+; DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+; DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+; OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; ****************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; RTC Tamper interrupt or Timestamp through EXTI line 19 interrupt
+ DCD RTC_WKUP_IRQHandler ; RTC_WKUP
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD DMA_Channel8_IRQHandler ; DMA Channel 8
+ DCD ADC_IRQHandler ; ADC
+ DCD USB_HP_IRQHandler ; USB High Priority
+ DCD USB_LP_IRQHandler ; USB Low Priority
+ DCD COMP_1_2_IRQHandler ; COMP1 & COMP2 through EXTI line 21/22
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
+ DCD TIM8_BRK_IRQHandler ; TIM8 Break
+ DCD TIM8_UP_IRQHandler ; TIM8 Update
+ DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD LPUART_IRQHandler ; LPUART
+ DCD TIM5_IRQHandler ; TIM5
+ DCD TIM6_IRQHandler ; TIM6
+ DCD TIM7_IRQHandler ; TIM7
+ DCD CAN_TX_IRQHandler ; CAN TX
+ DCD CAN_RX0_IRQHandler ; CAN RX0
+ DCD CAN_RX1_IRQHandler ; CAN RX1
+ DCD CAN_SCE_IRQHandler ; CAN SCE
+ DCD LPUART_WKUP_IRQHandler ; LPUART_WKUP
+ DCD LPTIM_WKUP_IRQHandler ; LPTIM_WKUP
+ DCD LCD_IRQHandler ; LCD
+ DCD SAC_IRQHandler ; SAC
+ DCD MMU_IRQHandler ; MMU
+ DCD TSC_IRQHandler ; TSC
+ DCD RAMC_PERR_IRQHandler ; RAMC ERR
+ DCD TIM9_IRQHandler ; TIM9
+ DCD UCDR_IRQHandler ; UCDR ERR
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+ PUBWEAK TAMPER_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TAMPER_IRQHandler
+ B TAMPER_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel1_IRQHandler
+ B DMA_Channel1_IRQHandler
+
+ PUBWEAK DMA_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel2_IRQHandler
+ B DMA_Channel2_IRQHandler
+
+ PUBWEAK DMA_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel3_IRQHandler
+ B DMA_Channel3_IRQHandler
+
+ PUBWEAK DMA_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel4_IRQHandler
+ B DMA_Channel4_IRQHandler
+
+ PUBWEAK DMA_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel5_IRQHandler
+ B DMA_Channel5_IRQHandler
+
+ PUBWEAK DMA_Channel6_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel6_IRQHandler
+ B DMA_Channel6_IRQHandler
+
+ PUBWEAK DMA_Channel7_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel7_IRQHandler
+ B DMA_Channel7_IRQHandler
+
+ PUBWEAK DMA_Channel8_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel8_IRQHandler
+ B DMA_Channel8_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK USB_HP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USB_HP_IRQHandler
+ B USB_HP_IRQHandler
+
+ PUBWEAK USB_LP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USB_LP_IRQHandler
+ B USB_LP_IRQHandler
+
+ PUBWEAK COMP_1_2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+COMP_1_2_IRQHandler
+ B COMP_1_2_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTCAlarm_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTCAlarm_IRQHandler
+ B RTCAlarm_IRQHandler
+
+ PUBWEAK USBWakeUp_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USBWakeUp_IRQHandler
+ B USBWakeUp_IRQHandler
+
+ PUBWEAK TIM8_BRK_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_BRK_IRQHandler
+ B TIM8_BRK_IRQHandler
+
+ PUBWEAK TIM8_UP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_UP_IRQHandler
+ B TIM8_UP_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_TRG_COM_IRQHandler
+ B TIM8_TRG_COM_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK LPUART_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+LPUART_IRQHandler
+ B LPUART_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK TIM6_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM6_IRQHandler
+ B TIM6_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK CAN_TX_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN_TX_IRQHandler
+ B CAN_TX_IRQHandler
+
+ PUBWEAK CAN_RX0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN_RX0_IRQHandler
+ B CAN_RX0_IRQHandler
+
+ PUBWEAK CAN_RX1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN_RX1_IRQHandler
+ B CAN_RX1_IRQHandler
+
+ PUBWEAK CAN_SCE_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN_SCE_IRQHandler
+ B CAN_SCE_IRQHandler
+
+ PUBWEAK LPUART_WKUP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+LPUART_WKUP_IRQHandler
+ B LPUART_WKUP_IRQHandler
+
+ PUBWEAK LPTIM_WKUP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+LPTIM_WKUP_IRQHandler
+ B LPTIM_WKUP_IRQHandler
+
+ PUBWEAK LCD_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+LCD_IRQHandler
+ B LCD_IRQHandler
+
+ PUBWEAK SAC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SAC_IRQHandler
+ B SAC_IRQHandler
+
+ PUBWEAK MMU_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MMU_IRQHandler
+ B MMU_IRQHandler
+
+ PUBWEAK TSC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TSC_IRQHandler
+ B TSC_IRQHandler
+
+ PUBWEAK RAMC_PERR_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RAMC_PERR_IRQHandler
+ B RAMC_PERR_IRQHandler
+
+ PUBWEAK TIM9_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM9_IRQHandler
+ B TIM9_IRQHandler
+
+ PUBWEAK UCDR_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UCDR_IRQHandler
+ B UCDR_IRQHandler
+
+
+ END
+
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/startup/startup_n32l40x_gcc.s b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/startup/startup_n32l40x_gcc.s
new file mode 100644
index 0000000000..b495ed49b0
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/startup/startup_n32l40x_gcc.s
@@ -0,0 +1,450 @@
+/**
+ ****************************************************************************
+ Copyright (c) 2019, Nations Technologies Inc.
+
+ All rights reserved.
+ ****************************************************************************
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ - Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the disclaimer below.
+
+ Nations' name may not be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+ DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************
+ **/
+
+/**
+******************************************************************************
+* @file startup_n32l40x_gcc.s
+******************************************************************************
+*/
+
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+ Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl entry
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_IRQHandler /* PVD through EXTI Line detection */
+ .word TAMPER_IRQHandler /* Tamper */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA_Channel1_IRQHandler /* DMA1 Channel 1 */
+ .word DMA_Channel2_IRQHandler /* DMA1 Channel 2 */
+ .word DMA_Channel3_IRQHandler /* DMA1 Channel 3 */
+ .word DMA_Channel4_IRQHandler /* DMA1 Channel 4 */
+ .word DMA_Channel5_IRQHandler /* DMA1 Channel 5 */
+ .word DMA_Channel6_IRQHandler /* DMA1 Channel 6 */
+ .word DMA_Channel7_IRQHandler /* DMA1 Channel 7 */
+ .word DMA_Channel8_IRQHandler /* DMA1 Channel 8 */
+ .word ADC_IRQHandler /* ADC */
+ .word USB_HP_IRQHandler /* USB High Priority */
+ .word USB_LP_IRQHandler /* USB Low Priority */
+ .word COMP_1_2_IRQHandler /* COMP1 & COMP2 through EXTI line 21/22 */
+ .word EXTI9_5_IRQHandler /* EXTI Line 9..5 */
+ .word TIM1_BRK_IRQHandler /* TIM1 Break */
+ .word TIM1_UP_IRQHandler /* TIM1 Update */
+ .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */
+ .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
+ .word USBWakeUp_IRQHandler /* USB Wakeup from suspend */
+ .word TIM8_BRK_IRQHandler /* TIM8 Break */
+ .word TIM8_UP_IRQHandler /* TIM8 Update */
+ .word TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word LPUART_IRQHandler /* LPUART */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word TIM6_IRQHandler /* TIM6 */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word CAN_TX_IRQHandler /* CAN TX */
+ .word CAN_RX0_IRQHandler /* CAN RX0 */
+ .word CAN_RX1_IRQHandler /* CAN RX1 */
+ .word CAN_SCE_IRQHandler /* CAN SCE */
+ .word LPUART_WKUP_IRQHandler /* LPUART_WKUP */
+ .word LPTIM_WKUP_IRQHandler /* LPTIM_WKUP */
+ .word LCD_IRQHandler /* LCD */
+ .word SAC_IRQHandler /* SAC */
+ .word MMU_IRQHandler /* MMU */
+ .word TSC_IRQHandler /* TSC */
+ .word RAMC_PERR_IRQHandler /* RAMC ERR */
+ .word TIM9_IRQHandler /* TIM9 */
+ .word UCDR_IRQHandler /* UCDR ERR */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA_Channel1_IRQHandler
+ .thumb_set DMA_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA_Channel2_IRQHandler
+ .thumb_set DMA_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA_Channel3_IRQHandler
+ .thumb_set DMA_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA_Channel4_IRQHandler
+ .thumb_set DMA_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA_Channel5_IRQHandler
+ .thumb_set DMA_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA_Channel6_IRQHandler
+ .thumb_set DMA_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA_Channel7_IRQHandler
+ .thumb_set DMA_Channel7_IRQHandler,Default_Handler
+
+ .weak DMA_Channel8_IRQHandler
+ .thumb_set DMA_Channel8_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak USB_HP_IRQHandler
+ .thumb_set USB_HP_IRQHandler,Default_Handler
+
+ .weak USB_LP_IRQHandler
+ .thumb_set USB_LP_IRQHandler,Default_Handler
+
+ .weak COMP_1_2_IRQHandler
+ .thumb_set COMP_1_2_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTCAlarm_IRQHandler
+ .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_IRQHandler
+ .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_IRQHandler
+ .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_IRQHandler
+ .thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_IRQHandler
+ .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak LPUART_IRQHandler
+ .thumb_set LPUART_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak TIM6_IRQHandler
+ .thumb_set TIM6_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak CAN_TX_IRQHandler
+ .thumb_set CAN_TX_IRQHandler,Default_Handler
+
+ .weak CAN_RX0_IRQHandler
+ .thumb_set CAN_RX0_IRQHandler,Default_Handler
+
+ .weak CAN_RX1_IRQHandler
+ .thumb_set CAN_RX1_IRQHandler,Default_Handler
+
+ .weak CAN_SCE_IRQHandler
+ .thumb_set CAN_SCE_IRQHandler,Default_Handler
+
+ .weak LPUART_WKUP_IRQHandler
+ .thumb_set LPUART_WKUP_IRQHandler,Default_Handler
+
+ .weak LPTIM_WKUP_IRQHandler
+ .thumb_set LPTIM_WKUP_IRQHandler,Default_Handler
+
+ .weak LCD_IRQHandler
+ .thumb_set LCD_IRQHandler,Default_Handler
+
+ .weak SAC_IRQHandler
+ .thumb_set SAC_IRQHandler,Default_Handler
+
+ .weak MMU_IRQHandler
+ .thumb_set MMU_IRQHandler,Default_Handler
+
+ .weak TSC_IRQHandler
+ .thumb_set TSC_IRQHandler,Default_Handler
+
+ .weak RAMC_PERR_IRQHandler
+ .thumb_set RAMC_PERR_IRQHandler,Default_Handler
+
+ .weak TIM9_IRQHandler
+ .thumb_set TIM9_IRQHandler,Default_Handler
+
+ .weak UCDR_IRQHandler
+ .thumb_set UCDR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/system_n32l40x.c b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/system_n32l40x.c
new file mode 100644
index 0000000000..1c68ad1104
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/system_n32l40x.c
@@ -0,0 +1,619 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file system_n32l40x.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l40x.h"
+
+/* Uncomment the line corresponding to the desired System clock (SYSCLK)
+ frequency (after reset the HSI is used as SYSCLK source)
+
+ IMPORTANT NOTE:
+ ==============
+ 1. After each device reset the HSI is used as System clock source.
+
+ 2. Please make sure that the selected System clock doesn't exceed your
+ device's maximum frequency.
+
+ 3. If none of the define below is enabled, the HSI is used as System clock
+ source.
+
+ 4. The System clock configuration functions provided within this file assume
+ that:
+ - For Low, Medium and High density Value line devices an external 8MHz
+ crystal is used to drive the System clock.
+ - For Low, Medium and High density devices an external 8MHz crystal is
+ used to drive the System clock.
+ - For Connectivity line devices an external 25MHz crystal is used to
+ drive the System clock. If you are using different crystal you have to adapt
+ those functions accordingly.
+ */
+
+#define SYSCLK_USE_MSI 0
+#define SYSCLK_USE_HSI 1
+#define SYSCLK_USE_HSE 2
+#define SYSCLK_USE_HSI_PLL 3
+#define SYSCLK_USE_HSE_PLL 4
+
+#ifndef SYSCLK_FREQ
+#define SYSCLK_FREQ 64000000
+#endif
+
+/*
+* SYSCLK_SRC *
+** SYSCLK_USE_MSI **
+** SYSCLK_USE_HSI **
+** SYSCLK_USE_HSE **
+** SYSCLK_USE_HSI_PLL **
+** SYSCLK_USE_HSE_PLL **
+*/
+#ifndef SYSCLK_SRC
+#define SYSCLK_SRC SYSCLK_USE_HSE_PLL
+#endif
+
+#define PLL_DIV2_DISABLE 0x00000000
+#define PLL_DIV2_ENABLE 0x00000002
+#define SRAM_VOL (__IO unsigned*)(0x40001800 + 0x20)
+#define ConfigSRAMVoltage(vale) do{(*SRAM_VOL ) &= (~(uint32_t)(1 <<25));(*SRAM_VOL ) |= (uint32_t)(vale <<25);}while (0) //vale only equal to 0,1
+#if SYSCLK_SRC == SYSCLK_USE_MSI
+
+ #if (SYSCLK_FREQ == MSI_VALUE_L0)
+ #define MSI_CLK 0
+ #elif (SYSCLK_FREQ == MSI_VALUE_L1)
+ #define MSI_CLK 1
+ #elif (SYSCLK_FREQ == MSI_VALUE_L2)
+ #define MSI_CLK 2
+ #elif (SYSCLK_FREQ == MSI_VALUE_L3)
+ #define MSI_CLK 3
+ #elif (SYSCLK_FREQ == MSI_VALUE_L4)
+ #define MSI_CLK 4
+ #elif (SYSCLK_FREQ == MSI_VALUE_L5)
+ #define MSI_CLK 5
+ #elif (SYSCLK_FREQ == MSI_VALUE_L6)
+ #define MSI_CLK 6
+ #else
+ #error SYSCL_FREQ must be set to MSI_VALUE_Lx(x=0~6)
+ #endif
+
+#elif SYSCLK_SRC == SYSCLK_USE_HSI
+
+ #if SYSCLK_FREQ != HSI_VALUE
+ #error SYSCL_FREQ must be set to HSI_VALUE
+ #endif
+
+#elif SYSCLK_SRC == SYSCLK_USE_HSE
+
+ #ifndef HSE_VALUE
+ #error HSE_VALUE must be defined!
+ #endif
+
+ #if SYSCLK_FREQ != HSE_VALUE
+ #error SYSCL_FREQ must be set to HSE_VALUE
+ #endif
+
+#elif SYSCLK_SRC == SYSCLK_USE_HSI_PLL
+
+ #ifndef HSI_VALUE
+ #error HSI_VALUE must be defined!
+ #endif
+
+ #if ((SYSCLK_FREQ % (HSI_VALUE / 2)) == 0) && (SYSCLK_FREQ / (HSI_VALUE / 2) >= 2) \
+ && (SYSCLK_FREQ / (HSI_VALUE / 2) <= 32)
+
+ #define PLLSRC_DIV 2
+ #define PLL_DIV PLL_DIV2_DISABLE
+ #define PLL_MUL (SYSCLK_FREQ / (HSI_VALUE / 2))
+
+ #elif (SYSCLK_FREQ % HSI_VALUE == 0) && (SYSCLK_FREQ / HSI_VALUE >= 2) && (SYSCLK_FREQ / HSI_VALUE <= 32)
+
+ #define PLLSRC_DIV 1
+ #define PLL_DIV PLL_DIV2_DISABLE
+ #define PLL_MUL (SYSCLK_FREQ / HSI_VALUE)
+
+ #elif ((SYSCLK_FREQ % (HSI_VALUE / 4)) == 0) && (SYSCLK_FREQ / (HSI_VALUE / 4) >= 2) \
+ && (SYSCLK_FREQ / (HSI_VALUE / 4) <= 32)
+
+ #define PLLSRC_DIV 2
+ #define PLL_DIV PLL_DIV2_ENABLE
+ #define PLL_MUL (SYSCLK_FREQ / (HSI_VALUE / 4))
+
+ #else
+ #error Cannot make a PLL multiply factor to SYSCLK_FREQ.
+ #endif
+
+#elif SYSCLK_SRC == SYSCLK_USE_HSE_PLL
+
+ #ifndef HSE_VALUE
+ #error HSE_VALUE must be defined!
+ #endif
+
+ #if ((SYSCLK_FREQ % (HSE_VALUE / 2)) == 0) && (SYSCLK_FREQ / (HSE_VALUE / 2) >= 2) \
+ && (SYSCLK_FREQ / (HSE_VALUE / 2) <= 32)
+
+ #define PLLSRC_DIV 2
+ #define PLL_DIV PLL_DIV2_DISABLE
+ #define PLL_MUL (SYSCLK_FREQ / (HSE_VALUE / 2))
+
+ #elif (SYSCLK_FREQ % HSE_VALUE == 0) && (SYSCLK_FREQ / HSE_VALUE >= 2) && (SYSCLK_FREQ / HSE_VALUE <= 32)
+
+ #define PLLSRC_DIV 1
+ #define PLL_DIV PLL_DIV2_DISABLE
+ #define PLL_MUL (SYSCLK_FREQ / HSE_VALUE)
+
+ #elif ((SYSCLK_FREQ % (HSE_VALUE / 4)) == 0) && (SYSCLK_FREQ / (HSE_VALUE / 4) >= 2) \
+ && (SYSCLK_FREQ / (HSE_VALUE / 4) <= 32)
+
+ #define PLLSRC_DIV 2
+ #define PLL_DIV PLL_DIV2_ENABLE
+ #define PLL_MUL (SYSCLK_FREQ / (HSE_VALUE / 4))
+
+ #else
+ #error Cannot make a PLL multiply factor to SYSCLK_FREQ.
+ #endif
+
+#else
+#error wrong value for SYSCLK_SRC
+#endif
+
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */
+
+/*******************************************************************************
+ * Clock Definitions
+ *******************************************************************************/
+uint32_t SystemCoreClock = SYSCLK_FREQ; /*!< System Clock Frequency (Core Clock) */
+
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint32_t MSIClockTable[7] = {MSI_VALUE_L0, MSI_VALUE_L1, MSI_VALUE_L2, MSI_VALUE_L3,
+ MSI_VALUE_L4, MSI_VALUE_L5, MSI_VALUE_L6};
+
+static void SetSysClock(void);
+
+#ifdef DATA_IN_ExtSRAM
+static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the Embedded Flash Interface, the PLL and update the
+ * SystemCoreClock variable.
+ * @note This function should be used only after reset.
+ */
+void SystemInit(void)
+{
+ /* FPU settings
+ * ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
+
+ /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+ /* Set MSIEN bit */
+ RCC->CTRLSTS |= (uint32_t)0x00000004;
+
+ /* Reset SW, HPRE, PPRE1, PPRE2 and MCO bits */
+ RCC->CFG &= (uint32_t)0xF8FFC000;
+
+ /* Reset HSEON, CLKSSEN and PLLEN bits */
+ RCC->CTRL &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CTRL &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL, MCOPRES and USBPRES bits */
+ RCC->CFG &= (uint32_t)0x0700FFFF;
+
+ /* Reset CFG2 register */
+ RCC->CFG2 = 0x00007000;
+
+ /* Reset CFG3 register */
+ RCC->CFG3 = 0x00003800;
+
+ /* Reset RDCTRL register */
+ RCC->RDCTRL = 0x00000000;
+
+ /* Reset PLLHSIPRE register */
+ RCC->PLLHSIPRE = 0x00000000;
+
+ /* Disable all interrupts and clear pending bits */
+ RCC->CLKINT = 0x04BF8000;
+
+ /* Enable ex mode */
+ RCC->APB1PCLKEN |= RCC_APB1PCLKEN_PWREN;
+
+ if ((PWR->CTRL1 & PWR_CTRL1_MRSEL2) == PWR_CTRL1_MRSEL2)
+ {
+ ConfigSRAMVoltage(1);
+ }
+ /* Enable ICACHE and Prefetch Buffer */
+ FLASH->AC |= (uint32_t)(FLASH_AC_ICAHEN | FLASH_AC_PRFTBFEN);
+
+ /* Checks whether the Low Voltage Mode status is SET or RESET */
+ if ((FLASH->AC & FLASH_AC_LVMF) != RESET)
+ {
+ /* FLASH Low Voltage Mode Disable */
+ FLASH->AC &= (uint32_t)(~FLASH_AC_LVMEN);
+ }
+
+#ifdef DATA_IN_ExtSRAM
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM */
+
+ /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+ /* Configure the Flash Latency cycles and enable prefetch buffer */
+ SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or
+ * configure other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any
+ * configuration based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is MSI, SystemCoreClock will contain the
+ * MSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the
+ * HSI_VALUE(**)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the
+ * HSE_VALUE(***)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the
+ * HSE_VALUE(***) or HSI_VALUE(**) multiplied by the PLL factors.
+ *
+ * (*) MSI_VALUE is a constant defined in n32l40x.h file (default value
+ * 4 MHz, 100KHz/200KHz/400KHz/800KHz/1MHz/2MHz/4MHz ) but the real
+ * value may vary depending on the variations in voltage and temperature.
+ *
+ * (**) HSI_VALUE is a constant defined in n32l40x.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (***) HSE_VALUE is a constant defined in n32l40x.h file (default value
+ * 8 MHz or 25 MHz, depedning on the product used), user has to
+ * ensure that HSE_VALUE is same as the real frequency of the crystal used.
+ * Otherwise, this function may have wrong result.
+ *
+ * - The result of this function could be not correct when using
+ * fractional value for HSE crystal.
+ */
+void SystemCoreClockUpdate(void)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0, plldiv2 = 0;
+ uint8_t msi_clk = 0;
+
+ /* Get SYSCLK source
+ * -------------------------------------------------------*/
+ tmp = RCC->CFG & RCC_CFG_SCLKSTS;
+
+ /* Get MSI clock
+ * -------------------------------------------------------*/
+ msi_clk = (uint8_t) ((RCC->CTRLSTS & RCC_CTRLSTS_MSIRANGE)>>4);
+
+ switch (tmp)
+ {
+ case 0x00: /* MSI used as system clock */
+ SystemCoreClock = MSIClockTable[msi_clk];
+ break;
+ case 0x04: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x08: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x0C: /* PLL used as system clock */
+
+ /* Get PLL clock source and multiplication factor
+ * ----------------------*/
+ pllmull = RCC->CFG & RCC_CFG_PLLMULFCT;
+ pllsource = RCC->CFG & RCC_CFG_PLLSRC;
+ plldiv2 = RCC->PLLHSIPRE & RCC_PLLHSIPRE_PLLSRCDIV;
+
+ if ((pllmull & RCC_CFG_PLLMULFCT_4) == 0)
+ {
+ pllmull = (pllmull >> 18) + 2; // PLLMUL[4]=0
+ }
+ else
+ {
+ pllmull = ((pllmull >> 18) - 496) + 1; // PLLMUL[4]=1
+ }
+
+ if (pllsource == 0x00)
+ {
+ /* HSI selected as PLL clock entry */
+ if ((RCC->PLLHSIPRE & RCC_PLLHSIPRE_PLLSRCDIV) != (uint32_t)RESET)
+ { /* HSI oscillator clock divided by 2 */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ SystemCoreClock = HSI_VALUE * pllmull;
+ }
+ }
+ else
+ {
+ /* HSE selected as PLL clock entry */
+ if ((RCC->CFG & RCC_CFG_PLLHSEPRES) != (uint32_t)RESET)
+ { /* HSE oscillator clock divided by 2 */
+ SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ SystemCoreClock = HSE_VALUE * pllmull;
+ }
+ }
+
+ if (plldiv2 == 0x02)
+ {
+ /* PLL source clock divided by 2 selected as PLL clock entry */
+ SystemCoreClock >>= 1;
+ }
+
+ break;
+
+ default:
+ SystemCoreClock = MSIClockTable[msi_clk];
+ break;
+ }
+
+ /* Compute HCLK clock frequency ----------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFG & RCC_CFG_AHBPRES) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/**
+ * @brief Configures the System PWR level to 1.0V
+ * .
+ */
+void ConfigMRVoltage1V(void)
+{
+ uint32_t i=0;
+ ConfigSRAMVoltage(1); //SRAM read margin setting switch in 0.9/lprun mode: use low voltage mode settings and 1.0v use normal mode
+ PWR->CTRL1 &= (uint32_t)(~PWR_CTRL1_MRSEL);
+ PWR->CTRL1 |= PWR_CTRL1_MRSEL2; //MR=1.0V
+ while ((PWR->STS2 &PWR_STS2_MRF) != 0); // wait VOSF to be 0 first
+ for(i=0;i<0x2A;i++);
+ while ((PWR->STS2 & PWR_STS2_MRF) != PWR_STS2_MRF); // wait VOSF to be 1 then
+}
+/**
+ * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1
+ * prescalers.
+ */
+static void SetSysClock(void)
+{
+ uint32_t rcc_cfg = 0;
+ uint32_t rcc_pllhsipre = 0;
+ uint32_t StartUpCounter = 0;
+
+#if (SYSCLK_SRC == SYSCLK_USE_MSI)
+ uint8_t i=0;
+ bool MSIStatus = 0;
+ /* Config MSI */
+ RCC->CTRLSTS &= 0xFFFFFF8F;
+ /*Delay for while*/
+ for(i=0;i<0x30;i++);
+ RCC->CTRLSTS |= (((uint32_t)MSI_CLK) << 4);
+ /*Delay for while*/
+ for(i=0;i<0x30;i++);
+ /* Enable MSI */
+ RCC->CTRLSTS |= ((uint32_t)RCC_CTRLSTS_MSIEN);
+
+ /* Wait till MSI is ready and if Time out is reached exit */
+ do
+ {
+ MSIStatus = RCC->CTRLSTS & RCC_CTRLSTS_MSIRD;
+ StartUpCounter++;
+ } while ((MSIStatus == 0) && (StartUpCounter != MSI_STARTUP_TIMEOUT));
+
+ MSIStatus = ((RCC->CTRLSTS & RCC_CTRLSTS_MSIRD) != RESET);
+ if (!MSIStatus)
+ {
+ /* If MSI fails to start-up, the application will have wrong clock
+ * configuration. User can add here some code to deal with this error */
+ SystemCoreClock = MSI_VALUE_L6;
+ return;
+ }
+
+#elif ((SYSCLK_SRC == SYSCLK_USE_HSI) || (SYSCLK_SRC == SYSCLK_USE_HSI_PLL))
+
+ bool HSIStatus = 0;
+ /* Enable HSI */
+ RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
+
+ /* Wait till HSI is ready and if Time out is reached exit */
+ do
+ {
+ HSIStatus = RCC->CTRL & RCC_CTRL_HSIRDF;
+ StartUpCounter++;
+ } while ((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));
+
+ HSIStatus = ((RCC->CTRL & RCC_CTRL_HSIRDF) != RESET);
+ if (!HSIStatus)
+ {
+ /* If HSI fails to start-up, the application will have wrong clock
+ * configuration. User can add here some code to deal with this error */
+ SystemCoreClock = MSI_VALUE_L6;
+ return;
+ }
+
+#elif ((SYSCLK_SRC == SYSCLK_USE_HSE) || (SYSCLK_SRC == SYSCLK_USE_HSE_PLL))
+
+ bool HSEStatus = 0;
+ /* Enable HSE */
+ RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CTRL & RCC_CTRL_HSERDF;
+ StartUpCounter++;
+ } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ HSEStatus = ((RCC->CTRL & RCC_CTRL_HSERDF) != RESET);
+ if (!HSEStatus)
+ {
+ /* If HSE fails to start-up, the application will have wrong clock
+ * configuration. User can add here some code to deal with this error */
+ SystemCoreClock = MSI_VALUE_L6;
+ return;
+ }
+#endif
+
+ ConfigMRVoltage1V();
+
+ /* Flash wait state
+ 0: HCLK <= 32M
+ 1: HCLK <= 64M
+ */
+ FLASH->AC &= (uint32_t)((uint32_t)~FLASH_AC_LATENCY);
+ FLASH->AC |= (uint32_t)((SYSCLK_FREQ - 1) / 32000000);
+
+ /* HCLK = SYSCLK */
+ RCC->CFG |= (uint32_t)RCC_CFG_AHBPRES_DIV1;
+
+ /* PCLK2 max 32M */
+ if (SYSCLK_FREQ > 54000000)
+ {
+ RCC->CFG |= (uint32_t)RCC_CFG_APB2PRES_DIV2;
+ }
+ else
+ {
+ RCC->CFG |= (uint32_t)RCC_CFG_APB2PRES_DIV1;
+ }
+
+ /* PCLK1 max 16M */
+ if (SYSCLK_FREQ > 54000000)
+ {
+ RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV4;
+ }
+ else if (SYSCLK_FREQ > 27000000)
+ {
+ RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV2;
+ }
+ else
+ {
+ RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV1;
+ }
+
+#if SYSCLK_SRC == SYSCLK_USE_MSI
+ /* Select MSI as system clock source */
+ RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW));
+ RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_MSI;
+
+ /* Wait till MSI is used as system clock source */
+ while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x00)
+ {
+ }
+#elif SYSCLK_SRC == SYSCLK_USE_HSI
+ /* Select HSI as system clock source */
+ RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW));
+ RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_HSI;
+
+ /* Wait till HSI is used as system clock source */
+ while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x04)
+ {
+ }
+#elif SYSCLK_SRC == SYSCLK_USE_HSE
+ /* Select HSE as system clock source */
+ RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW));
+ RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_HSE;
+
+ /* Wait till HSE is used as system clock source */
+ while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x08)
+ {
+ }
+#elif SYSCLK_SRC == SYSCLK_USE_HSI_PLL || SYSCLK_SRC == SYSCLK_USE_HSE_PLL
+
+ /* clear bits */
+ RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_PLLSRC | RCC_CFG_PLLHSEPRES | RCC_CFG_PLLMULFCT));
+ RCC->PLLHSIPRE &= (uint32_t)((uint32_t) ~(RCC_PLLHSIPRE_PLLHSIPRE | RCC_PLLHSIPRE_PLLSRCDIV));
+
+ /* set PLL source */
+ rcc_cfg = RCC->CFG;
+ rcc_cfg |= (SYSCLK_SRC == SYSCLK_USE_HSI_PLL ? RCC_CFG_PLLSRC_HSI : RCC_CFG_PLLSRC_HSE);
+ /* PLL DIV */
+ rcc_pllhsipre = RCC->PLLHSIPRE;
+
+ #if SYSCLK_SRC == SYSCLK_USE_HSI_PLL
+ rcc_pllhsipre |= (PLLSRC_DIV == 1 ? RCC_PLLHSIPRE_PLLHSIPRE_HSI : RCC_PLLHSIPRE_PLLHSIPRE_HSI_DIV2);
+ #elif SYSCLK_SRC == SYSCLK_USE_HSE_PLL
+ rcc_cfg |= (PLLSRC_DIV == 1 ? RCC_CFG_PLLHSEPRES_HSE : RCC_CFG_PLLHSEPRES_HSE_DIV2);
+ #endif
+
+ /* set PLL DIV */
+ rcc_pllhsipre |= (PLL_DIV == PLL_DIV2_DISABLE ? RCC_PLLHSIPRE_PLLSRCDIV_DISABLE : RCC_PLLHSIPRE_PLLSRCDIV_ENABLE);
+
+ /* set PLL multiply factor */
+ #if PLL_MUL <= 16
+ rcc_cfg |= (PLL_MUL - 2) << 18;
+ #else
+ rcc_cfg |= ((PLL_MUL - 17) << 18) | (1 << 27);
+ #endif
+
+ RCC->CFG = rcc_cfg;
+ RCC->PLLHSIPRE = rcc_pllhsipre;
+
+ /* Enable PLL */
+ RCC->CTRL |= RCC_CTRL_PLLEN;
+
+ /* Wait till PLL is ready */
+ while ((RCC->CTRL & RCC_CTRL_PLLRDF) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW));
+ RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x0C)
+ {
+ }
+#endif
+}
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/system_n32l40x.h b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/system_n32l40x.h
new file mode 100644
index 0000000000..8fb27240f8
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/system_n32l40x.h
@@ -0,0 +1,59 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file system_n32l40x.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __SYSTEM_n32l40x_H__
+#define __SYSTEM_n32l40x_H__
+
+#include
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup n32l40x_System
+ * @{
+ */
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_n32l40x_H__ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/SConscript b/bsp/n32/libraries/N32L40x_Firmware_Library/SConscript
new file mode 100644
index 0000000000..55291a12fa
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/SConscript
@@ -0,0 +1,63 @@
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+
+src = Split('''
+CMSIS/device/system_n32l40x.c
+n32l40x_std_periph_driver/src/n32l40x_gpio.c
+n32l40x_std_periph_driver/src/n32l40x_rcc.c
+n32l40x_std_periph_driver/src/n32l40x_exti.c
+n32l40x_std_periph_driver/src/misc.c
+''')
+
+if GetDepend(['RT_USING_SERIAL']):
+ src += ['n32l40x_std_periph_driver/src/n32l40x_usart.c']
+
+if GetDepend(['RT_USING_I2C']):
+ src += ['n32l40x_std_periph_driver/src/n32l40x_i2c.c']
+
+if GetDepend(['RT_USING_SPI']):
+ src += ['n32l40x_std_periph_driver/src/n32l40x_spi.c']
+
+if GetDepend(['RT_USING_CAN']):
+ src += ['n32l40x_std_periph_driver/src/n32l40x_can.c']
+
+if GetDepend(['RT_USING_ADC']):
+ src += ['n32l40x_std_periph_driver/src/n32l40x_adc.c']
+
+if GetDepend(['RT_USING_DAC']):
+ src += ['n32l40x_std_periph_driver/src/n32l40x_dac.c']
+
+if GetDepend(['RT_USING_HWTIMER']):
+ src += ['n32l40x_std_periph_driver/src/n32l40x_tim.c']
+
+if GetDepend(['RT_USING_RTC']):
+ src += ['n32l40x_std_periph_driver/src/n32l40x_rtc.c']
+ src += ['n32l40x_std_periph_driver/src/n32l40x_pwr.c']
+ src += ['n32l40x_std_periph_driver/src/n32l40x_flash.c']
+
+if GetDepend(['RT_USING_WDT']):
+ src += ['n32l40x_std_periph_driver/src/n32l40x_iwdg.c']
+ src += ['n32l40x_std_periph_driver/src/n32l40x_wwdg.c']
+
+if GetDepend(['RT_USING_BSP_USB']):
+ path += [cwd + '/n32l40x_usbfs_driver/inc']
+ src += [cwd + '/n32l40x_usbfs_driver/src']
+
+path = [
+ cwd + '/CMSIS/device',
+ cwd + '/CMSIS/core',
+ cwd + '/n32l40x_std_periph_driver/inc',]
+
+CPPDEFINES = ['USE_STDPERIPH_DRIVER']
+
+
+
+group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_aes.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_aes.h
new file mode 100644
index 0000000000..4909c677e0
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_aes.h
@@ -0,0 +1,119 @@
+/*****************************************************************************
+* NationS Microcontroller Software Support
+* ----------------------------------------------------------------------------
+* Copyright (c) 2020, NationS Corporation
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* - Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the disclaimer below.
+*
+* NationS's name may not be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ****************************************************************************/
+/*****************************************************************************
+* File Name: n32l40x_aes.h
+* Function: Declaring AES algorithm library API
+* version: V1.2.0
+* Author: zhang.zhenshan
+* date: 2020-4-8
+* ****************************************************************************/
+
+#ifndef __N32L40X_AES_H__
+#define __N32L40X_AES_H__
+
+#include
+
+#define AES_ECB (0x11111111)
+#define AES_CBC (0x22222222)
+#define AES_CTR (0x33333333)
+
+#define AES_ENC (0x44444444)
+#define AES_DEC (0x55555555)
+
+enum
+{
+ AES_Crypto_OK = 0x0, //AES opreation success
+ AES_Init_OK = 0x0, //AES Init opreation success
+ AES_Crypto_ModeError = 0x5a5a5a5a, //Working mode error(Neither ECB nor CBC nor CTR)
+ AES_Crypto_EnOrDeError, //En&De error(Neither encryption nor decryption)
+ AES_Crypto_ParaNull, // the part of input(output/iv) Null
+ AES_Crypto_LengthError, // if Working mode is ECB or CBC,the length of input message must be 4 times and cannot be zero;
+ //if Working mode is CTR,the length of input message cannot be zero; othets: return AES_Crypto_LengthError
+
+ AES_Crypto_KeyLengthError, //the keyWordLen must be 4 or 6 or 8; othets:return AES_Crypto_KeyLengthError
+ AES_Crypto_UnInitError, //AES uninitialized
+};
+
+typedef struct
+{
+ uint32_t *in; // the part of input to be encrypted or decrypted
+ uint32_t *iv; // the part of initial vector
+ uint32_t *out; // the part of out
+ uint32_t *key; // the part of key
+ uint32_t keyWordLen; // the length(by word) of key
+ uint32_t inWordLen; // the length(by word) of plaintext or cipher
+ uint32_t En_De; // 0x44444444- encrypt, 0x55555555 - decrypt
+ uint32_t Mode; // 0x11111111 - ECB, 0x22222222 - CBC, 0x33333333 - CTR
+}AES_PARM;
+
+ /**
+ * @brief AES_Init
+ * @return AES_Init_OK, AES Init success; othets: AES Init fail
+ * @note
+ */
+
+uint32_t AES_Init(AES_PARM *parm);
+
+/**
+ * @brief AES crypto
+ * @param[in] parm pointer to AES context and the detail please refer to struct AES_PARM in AES.h
+ * @return AES_Crypto_OK, AES crypto success; othets: AES crypto fail(reference to the definition by enum variation)
+ * @note 1.Please refer to the demo in user guidance before using this function
+ * 2.Input and output can be the same buffer
+ * 3. IV can be NULL when ECB mode
+ * 4. If Working mode is ECB or CBC,the length of input message must be 4 times and cannot be zero;
+ * if Working mode is CTR,the length of input message cannot be zero;
+ * 5. If the input is in byte, make sure align by word.
+ */
+uint32_t AES_Crypto(AES_PARM *parm);
+
+/**
+ * @brief AES close
+ * @return none
+ * @note if you want to close AES algorithm, this function can be recalled.
+ */
+void AES_Close(void);
+
+/**
+ * @brief Get AES lib version
+ * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
+ * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
+ * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
+ * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
+ * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
+ * @return none
+ * @1.You can recall this function to get AES lib information
+ */
+void AES_Version(uint8_t *type, uint8_t *customer, uint8_t date[3], uint8_t *version);
+
+
+
+
+#endif
+
+
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_algo_common.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_algo_common.h
new file mode 100644
index 0000000000..2b61983d1f
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_algo_common.h
@@ -0,0 +1,154 @@
+/*****************************************************************************
+* NationS Microcontroller Software Support
+* ----------------------------------------------------------------------------
+* Copyright (c) 2020, NationS Corporation
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* - Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the disclaimer below.
+*
+* NationS's name may not be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+* DISCLAIMED. IN NO EVENT SHALL NATIONZ BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ****************************************************************************/
+/*****************************************************************************
+* File Name: Common.h
+* Function: Defining the public functions used by other algorithm lib
+* version: V1.2.0
+* Author: huang.jinshang
+* date: 2020-01-06
+* ****************************************************************************/
+
+#ifndef _N32L40X_ALGO_COMMON_H_
+#define _N32L40X_ALGO_COMMON_H_
+
+#include
+
+
+enum{
+ Cpy_OK=0,//copy success
+ SetZero_OK = 0,//set zero success
+ XOR_OK = 0, //XOR success
+ Reverse_OK = 0, //Reverse success
+ Cmp_EQUAL = 0, //Two big number are equal
+ Cmp_UNEQUAL = 1, //Two big number are not equal
+
+};
+
+/**
+ * @brief disturb the sequence order
+ * @param[in] order pointer to the sequence to be disturbed
+ * @param[in] rand pointer to random number
+ * @param[in] the length of order
+ * @return RandomSort_OK: disturb order success; Others: disturb order fail;
+ * @note
+ */
+uint32_t RandomSort(uint8_t *order, const uint8_t *rand, uint32_t len);
+
+/**
+ * @brief Copy data by byte
+ * @param[in] dst pointer to destination data
+ * @param[in] src pointer to source data
+ * @param[in] byte length
+ * @return Cpy_OK: success; others: fail.
+ * @note 1. dst and src cannot be same
+ */
+uint32_t Cpy_U8( uint8_t *dst, uint8_t *src, uint32_t byteLen);
+
+/**
+ * @brief Copy data by word
+ * @param[in] dst pointer to destination data
+ * @param[in] src pointer to source data
+ * @param[in] word length
+ * @return Cpy_OK: success; others: fail.
+ * @note 1. dst and src must be aligned by word
+ */
+uint32_t Cpy_U32( uint32_t *dst, const uint32_t *src, uint32_t wordLen);
+
+ /**
+ * @brief XOR
+ * @param[in] a pointer to one data to be XORed
+ * @param[in] b pointer to another data to be XORed
+ * @param[in] the length of order
+ * @return XOR_OK: operation success; Others: operation fail;
+ * @note
+ */
+uint32_t XOR_U8(uint8_t *a, uint8_t *b, uint8_t *c, uint32_t byteLen);
+
+ /**
+ * @brief XORed two u32 arrays
+ * @param[in] a pointer to one data to be XORed
+ * @param[in] b pointer to another data to be XORed
+ * @param[in] the length of order
+ * @return XOR_OK: operation success; Others: operation fail;
+ * @note
+ */
+uint32_t XOR_U32(uint32_t *a,uint32_t *b,uint32_t *c,uint32_t wordLen);
+
+/**
+ * @brief set zero by byte
+ * @param[in] dst pointer to the address to be set zero
+ * @param[in] byte length
+ * @return SetZero_OK: success; others: fail.
+ * @note
+ */
+uint32_t SetZero_U8(uint8_t *dst, uint32_t byteLen);
+
+/**
+ * @brief set zero by word
+ * @param[in] dst pointer to the address to be set zero
+ * @param[in] word length
+ * @return SetZero_OK: success; others: fail.
+ * @note
+ */
+uint32_t SetZero_U32(uint32_t *dst, uint32_t wordLen);
+
+/**
+ * @brief reverse byte order of every word, the words stay the same
+ * @param[in] dst pointer to the destination address
+ * @param[in] src pointer to the source address
+ * @param[in] word length
+ * @return Reverse_OK: success; others: fail.
+ * @note 1.dst and src can be same
+ */
+uint32_t ReverseBytesInWord_U32(uint32_t *dst, const uint32_t *src, uint32_t wordLen);
+
+/**
+ * @brief compare two big number
+ * @param[in] a pointer to one big number
+ * @param[in] word length of a
+ * @param[in] b pointer to another big number
+ * @param[in] word length of b
+ * @return Cmp_UNEQUAL:a!=b;Cmp_EQUAL: a==b.
+ *
+ */
+int32_t Cmp_U32(const uint32_t *a, uint32_t aWordLen, const uint32_t *b, uint32_t bWordLen);
+
+/**
+ * @brief compare two big number
+ * @param[in] a pointer to one big number
+ * @param[in] word length of a
+ * @param[in] b pointer to another big number
+ * @param[in] word length of b
+ * @return Cmp_UNEQUAL:a!=b;Cmp_EQUAL: a==b.
+ *
+ */
+int32_t Cmp_U8(const uint8_t *a, uint32_t aByteLen, const uint8_t *b, uint32_t bByteLen);
+
+
+#endif
+
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_des.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_des.h
new file mode 100644
index 0000000000..14fee1cd6a
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_des.h
@@ -0,0 +1,115 @@
+/*****************************************************************************
+* Nations Microcontroller Software Support
+* ----------------------------------------------------------------------------
+* Copyright (c) 2020, Nations Corporation
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* - Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the disclaimer below.
+*
+* Nations's name may not be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY Nations "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+* DISCLAIMED. IN NO EVENT SHALL Nations BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ****************************************************************************/
+/*****************************************************************************
+* File Name: n32l40x_des.h
+* Function: Declaring DES algorithm library API
+* version: V1.2.0
+* Author: zhang.zhenshan
+* date: 2020-4-8
+* ****************************************************************************/
+
+
+#ifndef _N32L40X_DES_H_
+#define _N32L40X_DES_H_
+
+#include
+
+#define DES_ECB (0x11111111)
+#define DES_CBC (0x22222222)
+
+
+#define DES_ENC (0x33333333)
+#define DES_DEC (0x44444444)
+
+#define DES_KEY (0x55555555)
+#define TDES_2KEY (0x66666666)
+#define TDES_3KEY (0x77777777)
+
+enum DES
+{
+ DES_Crypto_OK = 0x0, //DES/TDES opreation success
+ DES_Init_OK = 0x0, //DES/TDES Init opreation success
+ DES_Crypto_ModeError = 0x5a5a5a5a, //Working mode error(Neither ECB nor CBC)
+ DES_Crypto_EnOrDeError, //En&De error(Neither encryption nor decryption)
+ DES_Crypto_ParaNull, // the part of input(output/iv) Null
+ DES_Crypto_LengthError, //the length of input message must be 2 times and cannot be zero
+ DES_Crypto_KeyError, //keyMode error(Neither DES_KEY nor TDES_2KEY nor TDES_3KEY)
+ DES_Crypto_UnInitError, //DES/TDES uninitialized
+};
+
+typedef struct
+{
+ uint32_t *in; // the part of input to be encrypted or decrypted
+ uint32_t *iv; // the part of initial vector
+ uint32_t *out; // the part of out
+ uint32_t *key; // the part of key
+ uint32_t inWordLen; // the length(by word) of plaintext or cipher
+ uint32_t En_De; // 0x33333333- encrypt, 0x44444444 - decrypt
+ uint32_t Mode; // 0x11111111 - ECB, 0x22222222 - CBC
+ uint32_t keyMode; //TDES key mode: 0x55555555-key,0x66666666-2key, 0x77777777-3key
+}DES_PARM;
+
+ /**
+ * @brief DES_Init
+ * @return DES_Init_OK, DES/TDES Init success; othets: DES/TDES Init fail
+ * @note
+ */
+uint32_t DES_Init(DES_PARM *parm);
+
+/**
+ * @brief DES crypto
+ * @param[in] parm pointer to DES/TDES context and the detail please refer to struct DES_PARM in DES.h
+ * @return DES_Crypto_OK, DES/TDES crypto success; othets: DES/TDES crypto fail(reference to the definition by enum variation)
+ * @note 1.Please refer to the demo in user guidance before using this function
+ * 2.Input and output can be the same buffer
+ * 3. IV can be NULL when ECB mode
+ * 4. The word lengrh of message must be as times as 2.
+ * 5. If the input is in byte, make sure align by word.
+ */
+uint32_t DES_Crypto(DES_PARM *parm);
+
+/**
+ * @brief DES close
+ * @return none
+ * @note if you want to close DES algorithm, this function can be recalled.
+ */
+void DES_Close(void);
+
+/**
+ * @brief Get DES/TDES lib version
+ * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
+ * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
+ * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
+ * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
+ * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
+ * @return none
+ * @1.You can recall this function to get DES/TDES lib information
+ */
+void DES_Version(uint8_t *type, uint8_t *customer, uint8_t date[3], uint8_t *version);
+
+#endif
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_hash.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_hash.h
new file mode 100644
index 0000000000..97f6e73779
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_hash.h
@@ -0,0 +1,212 @@
+/*****************************************************************************
+* Nationz Microcontroller Software Support
+* ----------------------------------------------------------------------------
+* Copyright (c) 2020, Nationz Corporation
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* - Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the disclaimer below.
+*
+* Nationz's name may not be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+* DISCLAIMED. IN NO EVENT SHALL NATIONZ BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ****************************************************************************/
+/*****************************************************************************
+* File Name: HASH.h
+* Function: Declaring HASH algorithm library API
+* version: V1.2.0
+* Author: zhang.zhenshan
+* date: 2020-4-8
+* ****************************************************************************/
+
+#ifndef _N32L40X_HASH_H_
+#define _N32L40X_HASH_H_
+
+#include
+
+#define ALG_SHA1 (uint16_t)(0x0004)
+#define ALG_SHA224 (uint16_t)(0x000A)
+#define ALG_SHA256 (uint16_t)(0x000B)
+//#define ALG_MD5 (u16)(0x000C)
+#define ALG_SM3 (uint16_t)(0x0012)
+
+enum
+{
+ HASH_SEQUENCE_TRUE = 0x0105A5A5,//save IV
+ HASH_SEQUENCE_FALSE = 0x010A5A5A, //not save IV
+ HASH_Init_OK = 0,//hash init success
+ HASH_Start_OK = 0,//hash update success
+ HASH_Update_OK = 0,//hash update success
+ HASH_Complete_OK = 0,//hash complete success
+ HASH_Close_OK = 0,//hash close success
+ HASH_ByteLenPlus_OK = 0,//byte length plus success
+ HASH_PadMsg_OK = 0,//message padding success
+ HASH_ProcMsgBuf_OK = 0, //message processing success
+ SHA1_Hash_OK = 0,//sha1 operation success
+ SM3_Hash_OK = 0,//sm3 operation success
+ SHA224_Hash_OK = 0,//sha224 operation success
+ SHA256_Hash_OK = 0,//sha256 operation success
+ //MD5_Hash_OK = 0,//MD5 operation success
+
+ HASH_Init_ERROR = 0x01044400,//hash init error
+ HASH_Start_ERROR, //hash start error
+ HASH_Update_ERROR, //hash update error
+ HASH_ByteLenPlus_ERROR,//hash byte plus error
+};
+
+struct _HASH_CTX_;
+
+typedef struct
+{
+ const uint16_t HashAlgID;//choice hash algorithm
+ const uint32_t * const K, KLen;//K and word length of K
+ const uint32_t * const IV, IVLen;//IV and word length of IV
+ const uint32_t HASH_SACCR, HASH_HASHCTRL;//relate registers
+ const uint32_t BlockByteLen, BlockWordLen; //byte length of block, word length of block
+ const uint32_t DigestByteLen, DigestWordLen; //byte length of digest,word length of digest
+ const uint32_t Cycle; //interation times
+ uint32_t (* const ByteLenPlus)(uint32_t *, uint32_t); //function pointer
+ uint32_t (* const PadMsg)(struct _HASH_CTX_ *); //function pointer
+}HASH_ALG;
+
+typedef struct _HASH_CTX_
+{
+ const HASH_ALG *hashAlg;//pointer to HASH_ALG
+ uint32_t sequence; // TRUE if the IV should be saved
+ uint32_t IV[16];
+ uint32_t msgByteLen[4];
+ uint8_t msgBuf[128+4];
+ uint32_t msgIdx;
+}HASH_CTX;
+
+extern const HASH_ALG HASH_ALG_SHA1[1];
+extern const HASH_ALG HASH_ALG_SHA224[1];
+extern const HASH_ALG HASH_ALG_SHA256[1];
+//extern const HASH_ALG HASH_ALG_MD5[1];
+extern const HASH_ALG HASH_ALG_SM3[1];
+
+/**
+ * @brief Hash init
+ * @param[in] ctx pointer to HASH_CTX struct
+ * @return HASH_Init_OK, Hash init success; othets: Hash init fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ */
+uint32_t HASH_Init(HASH_CTX *ctx);
+
+/**
+ * @brief Hash start
+ * @param[in] ctx pointer to HASH_CTX struct
+ * @return HASH_Start_OK, Hash start success; othets: Hash start fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ * 2.HASH_Init() should be recalled before use this function
+ */
+uint32_t HASH_Start(HASH_CTX *ctx);
+
+/**
+ * @brief Hash update
+ * @param[in] ctx pointer to HASH_CTX struct
+ * @param[in] in pointer to message
+ * @param[out] out pointer tohash result,digest
+ * @return HASH_Update_OK, Hash update success; othets: Hash update fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ * 2.HASH_Init() and HASH_Start() should be recalled before use this function
+ */
+uint32_t HASH_Update(HASH_CTX *ctx, uint8_t *in, uint32_t byteLen);
+
+/**
+ * @brief Hash complete
+ * @param[in] ctx pointer to HASH_CTX struct
+ * @param[out] out pointer tohash result,digest
+ * @return HASH_Complete_OK, Hash complete success; othets: Hash complete fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ * 2.HASH_Init(), HASH_Start() and HASH_Update() should be recalled before use this function
+ */
+uint32_t HASH_Complete(HASH_CTX *ctx, uint8_t *out);
+
+/**
+ * @brief Hash close
+ * @return HASH_Close_OK, Hash close success; othets: Hash close fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ */
+uint32_t HASH_Close(void);
+
+/**
+ * @brief SM3 Hash for 256bits digest
+ * @param[in] in pointer to message
+ * @param[in] byte length of in
+ * @param[out] out pointer tohash result,digest
+ * @return SM3_Hash_OK, SM3 hash success; othets: SM3 hash fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ */
+uint32_t SM3_Hash(uint8_t *in,uint32_t byteLen, uint8_t* out);
+
+
+/**
+ * @brief SHA1 Hash
+ * @param[in] in pointer to message
+ * @param[in] byte length of in
+ * @param[out] out pointer tohash result,digest
+ * @return SHA1_Hash_OK, SHA1 hash success; othets: SHA1 hash fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ */
+uint32_t SHA1_Hash(uint8_t*in, uint32_t byteLen, uint8_t*out);
+
+/**
+ * @brief SHA224 Hash
+ * @param[in] in pointer to message
+ * @param[in] byte length of in
+ * @param[out] out pointer tohash result,digest
+ * @return SHA224_Hash_OK, SHA224 hash success; othets: SHA224 hash fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ */
+uint32_t SHA224_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
+
+
+/**
+ * @brief SHA256 Hash
+ * @param[in] in pointer to message
+ * @param[in] byte length of in
+ * @param[out] out pointer tohash result,digest
+ * @return SHA256_Hash_OK, SHA256 hash success; othets: SHA256 hash fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ */
+uint32_t SHA256_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
+
+/**
+ * @brief MD5 Hash
+ * @param[in] in pointer to message
+ * @param[in] byte length of in
+ * @param[in] out pointer tohash result,digest
+ * @return MD5_Hash_OK, MD5 hash success; othets: MD5 hash fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ */
+//u32 MD5_Hash(u8* in,u32 byteLen, u8* out);
+
+/**
+ * @brief Get HASH lib version
+ * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
+ * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
+ * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
+ * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
+ * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
+ * @return none
+ * @1.You can recall this function to get RSA lib information
+ */
+void HASH_Version(uint8_t*type, uint8_t*customer, uint8_t date[3], uint8_t *version);
+
+
+#endif
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_rng.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_rng.h
new file mode 100644
index 0000000000..2016559d61
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_rng.h
@@ -0,0 +1,83 @@
+/*****************************************************************************
+* NationS Microcontroller Software Support
+* ----------------------------------------------------------------------------
+* Copyright (c) 2020, NationS Corporation
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* - Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the disclaimer below.
+*
+* NationS's name may not be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+* DISCLAIMED. IN NO EVENT SHALL NATIONZ BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ****************************************************************************/
+/*****************************************************************************
+* File Name: n32l40x_rng.h
+* Function: Declaring RNG algorithm library API
+* version: V1.2.0
+* Author: zhang.zhenshan
+* date: 2020-4-8
+* ****************************************************************************/
+
+#ifndef _N32L40X_RNG_H_
+#define _N32L40X_RNG_H_
+
+#include
+
+enum{
+ RNG_OK = 0x5a5a5a5a,
+ LENError = 0x311ECF50, //RNG generation of key length error
+ ADDRNULL = 0x7A9DB86C, // This address is empty
+};
+
+
+//u32 RNG_init(void);
+/**
+ * @brief Get pseudo random number
+ * @param[out] rand pointer to random number
+ * @param[in] the wordlen of random number
+ * @param[in] the seed, can be NULL
+ * @return RNG_OK:get random number success; othets: get random number fail
+ * @note
+ */
+uint32_t GetPseudoRand_U32(uint32_t *rand, uint32_t wordLen,uint32_t seed[2]);
+
+
+/**
+ * @brief Get true random number
+ * @param[out] rand pointer to random number
+ * @param[in] the wordlen of random number
+ * @return RNG_OK:get random number success; othets: get random number fail
+ * @note
+ */
+uint32_t GetTrueRand_U32(uint32_t *rand, uint32_t wordLen);
+
+/**
+ * @brief Get RNG lib version
+ * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
+ * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
+ * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
+ * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
+ * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
+ * @return none
+ * @1.You can recall this function to get RSA lib information
+ */
+void RNG_Version(uint8_t *type, uint8_t *customer, uint8_t date[3], uint8_t *version);
+
+#endif
+
+
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/misc.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/misc.h
new file mode 100644
index 0000000000..41ad9772a2
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/misc.h
@@ -0,0 +1,229 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file misc.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __MISC_H__
+#define __MISC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l40x.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup MISC
+ * @{
+ */
+
+/** @addtogroup MISC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief NVIC Init Structure definition
+ */
+
+typedef struct
+{
+ uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
+ This parameter can be a value of @ref IRQn_Type
+ (For the complete n32l40x Devices IRQ Channels list, please
+ refer to n32l40x.h file) */
+
+ uint8_t
+ NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
+ specified in NVIC_IRQChannel. This parameter can be a value
+ between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+ uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
+ in NVIC_IRQChannel. This parameter can be a value
+ between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+ FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
+ will be enabled or disabled.
+ This parameter can be set either to ENABLE or DISABLE */
+} NVIC_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup NVIC_Priority_Table
+ * @{
+ */
+
+/**
+@code
+ The table below gives the allowed values of the pre-emption priority and subpriority according
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
+ ============================================================================================================================
+ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
+ ============================================================================================================================
+ NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption
+priority | | | 4 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption
+priority | | | 3 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption
+priority | | | 2 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption
+priority | | | 1 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption
+priority | | | 0 bits for subpriority
+ ============================================================================================================================
+@endcode
+*/
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup Vector_Table_Base
+ * @{
+ */
+
+#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
+#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || ((VECTTAB) == NVIC_VectTab_FLASH))
+/**
+ * @}
+ */
+
+/** @addtogroup System_Low_Power
+ * @{
+ */
+
+#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || ((LP) == NVIC_LP_SLEEPDEEP) || ((LP) == NVIC_LP_SLEEPONEXIT))
+/**
+ * @}
+ */
+
+/** @addtogroup Preemption_Priority_Group
+ * @{
+ */
+
+#define NVIC_PriorityGroup_0 \
+ ((uint32_t)0x700) /*!< 0 bits for pre-emption priority \
+ 4 bits for subpriority */
+#define NVIC_PriorityGroup_1 \
+ ((uint32_t)0x600) /*!< 1 bits for pre-emption priority \
+ 3 bits for subpriority */
+#define NVIC_PriorityGroup_2 \
+ ((uint32_t)0x500) /*!< 2 bits for pre-emption priority \
+ 2 bits for subpriority */
+#define NVIC_PriorityGroup_3 \
+ ((uint32_t)0x400) /*!< 3 bits for pre-emption priority \
+ 1 bits for subpriority */
+#define NVIC_PriorityGroup_4 \
+ ((uint32_t)0x300) /*!< 4 bits for pre-emption priority \
+ 0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP) \
+ (((GROUP) == NVIC_PriorityGroup_0) || ((GROUP) == NVIC_PriorityGroup_1) || ((GROUP) == NVIC_PriorityGroup_2) \
+ || ((GROUP) == NVIC_PriorityGroup_3) || ((GROUP) == NVIC_PriorityGroup_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup SysTick_clock_source
+ * @{
+ */
+
+#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) \
+ (((SOURCE) == SysTick_CLKSource_HCLK) || ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Exported_Functions
+ * @{
+ */
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitType* NVIC_InitStruct);
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState Cmd);
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MISC_H__ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_adc.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_adc.h
new file mode 100644
index 0000000000..8bb6506027
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_adc.h
@@ -0,0 +1,545 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_adc.h
+ * @author Nations Solution Team
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L40X_ADC_H__
+#define __N32L40X_ADC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l40x.h"
+#include
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+#define VREF1P2_CTRL (*(uint32_t*)(0x40001800+0x24))
+#define _EnVref1p2() do{VREF1P2_CTRL|=(0x1<<13);}while (0);
+#define _DisVref1p2() do{VREF1P2_CTRL&=~(0x1<<13);}while (0);
+
+#define VREF2P0_CTRL (*(uint32_t*)(0x40001800+0x24))
+#define _EnVref2p0() do{VREF2P0_CTRL|=(0x1<<20);}while (0);
+#define _DisVref2p0() do{VREF2P0_CTRL&=~(0x1<<20);}while (0);
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/** @addtogroup ADC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief ADC Init structure definition
+ */
+typedef struct
+{
+
+ FunctionalState MultiChEn; /*!< Specifies whether the conversion is performed in
+ Scan (multichannels) or Single (one channel) mode.
+ This parameter can be set to ENABLE or DISABLE */
+
+ FunctionalState ContinueConvEn; /*!< Specifies whether the conversion is performed in
+ Continuous or Single mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t ExtTrigSelect; /*!< Defines the external trigger used to start the analog
+ to digital conversion of regular channels. This parameter
+ can be a value of @ref
+ ADC_external_trigger_sources_for_regular_channels_conversion */
+
+ uint32_t DatAlign; /*!< Specifies whether the ADC data alignment is left or right.
+ This parameter can be a value of @ref ADC_data_align */
+
+ uint8_t ChsNumber; /*!< Specifies the number of ADC channels that will be converted
+ using the sequencer for regular channel group.
+ This parameter must range from 1 to 16. */
+} ADC_InitType;
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Exported_Constants
+ * @{
+ */
+
+#define IsAdcModule(PERIPH) (((PERIPH) == ADC))
+
+#define IsAdcDmaModule(PERIPH) (((PERIPH) == ADC))
+
+
+
+/** @addtogroup ADC_external_trigger_sources_for_regular_channels_conversion
+ * @{
+ */
+
+#define ADC_EXT_TRIGCONV_T1_CC1 ((uint32_t)0x00000000)
+#define ADC_EXT_TRIGCONV_T1_CC2 ((uint32_t)0x00020000)
+#define ADC_EXT_TRIGCONV_T1_CC3 ((uint32_t)0x00040000)
+#define ADC_EXT_TRIGCONV_T2_CC2 ((uint32_t)0x00060000)
+#define ADC_EXT_TRIGCONV_T3_TRGO ((uint32_t)0x00080000)
+#define ADC_EXT_TRIGCONV_T4_CC4 ((uint32_t)0x000A0000)
+#define ADC_EXT_TRIGCONV_EXT_INT11_TIM8_TRGO ((uint32_t)0x000C0000)
+#define ADC_EXT_TRIGCONV_NONE ((uint32_t)0x000E0000)
+
+
+#define IsAdcExtTrig(REGTRIG) \
+ (((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC2) \
+ || ((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC3) || ((REGTRIG) == ADC_EXT_TRIGCONV_T2_CC2) \
+ || ((REGTRIG) == ADC_EXT_TRIGCONV_T3_TRGO) || ((REGTRIG) == ADC_EXT_TRIGCONV_T4_CC4) \
+ || ((REGTRIG) == ADC_EXT_TRIGCONV_EXT_INT11_TIM8_TRGO) || ((REGTRIG) == ADC_EXT_TRIGCONV_NONE))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_data_align
+ * @{
+ */
+
+#define ADC_DAT_ALIGN_R ((uint32_t)0x00000000)
+#define ADC_DAT_ALIGN_L ((uint32_t)0x00000800)
+#define IsAdcDatAlign(ALIGN) (((ALIGN) == ADC_DAT_ALIGN_R) || ((ALIGN) == ADC_DAT_ALIGN_L))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_channels
+ * @{
+ */
+
+#define ADC_CH_0 ((uint8_t)0x00)
+#define ADC_CH_1 ((uint8_t)0x01)
+#define ADC_CH_2 ((uint8_t)0x02)
+#define ADC_CH_3 ((uint8_t)0x03)
+#define ADC_CH_4 ((uint8_t)0x04)
+#define ADC_CH_5 ((uint8_t)0x05)
+#define ADC_CH_6 ((uint8_t)0x06)
+#define ADC_CH_7 ((uint8_t)0x07)
+#define ADC_CH_8 ((uint8_t)0x08)
+#define ADC_CH_9 ((uint8_t)0x09)
+#define ADC_CH_10 ((uint8_t)0x0A)
+#define ADC_CH_11 ((uint8_t)0x0B)
+#define ADC_CH_12 ((uint8_t)0x0C)
+#define ADC_CH_13 ((uint8_t)0x0D)
+#define ADC_CH_14 ((uint8_t)0x0E)
+#define ADC_CH_15 ((uint8_t)0x0F)
+#define ADC_CH_16 ((uint8_t)0x10)
+#define ADC_CH_17 ((uint8_t)0x11)
+#define ADC_CH_18 ((uint8_t)0x12)
+
+#define ADC_CH_VREFINT ((uint8_t)ADC_CH_0)
+#define ADC_CH_TEMP_SENSOR ((uint8_t)ADC_CH_17)
+#define ADC_CH_VREFBUF ((uint8_t)ADC_CH_18)
+
+#define IsAdcChannel(CHANNEL) \
+ (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) \
+ || ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) \
+ || ((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9) || ((CHANNEL) == ADC_CH_10) || ((CHANNEL) == ADC_CH_11) \
+ || ((CHANNEL) == ADC_CH_12) || ((CHANNEL) == ADC_CH_13) || ((CHANNEL) == ADC_CH_14) || ((CHANNEL) == ADC_CH_15) \
+ || ((CHANNEL) == ADC_CH_16) || ((CHANNEL) == ADC_CH_17) || ((CHANNEL) == ADC_CH_18))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_sampling_time
+ * @{
+ */
+
+#define ADC_SAMP_TIME_1CYCLES5 ((uint8_t)0x00)
+#define ADC_SAMP_TIME_7CYCLES5 ((uint8_t)0x01)
+#define ADC_SAMP_TIME_13CYCLES5 ((uint8_t)0x02)
+#define ADC_SAMP_TIME_28CYCLES5 ((uint8_t)0x03)
+#define ADC_SAMP_TIME_41CYCLES5 ((uint8_t)0x04)
+#define ADC_SAMP_TIME_55CYCLES5 ((uint8_t)0x05)
+#define ADC_SAMP_TIME_71CYCLES5 ((uint8_t)0x06)
+#define ADC_SAMP_TIME_239CYCLES5 ((uint8_t)0x07)
+#define IsAdcSampleTime(TIME) \
+ (((TIME) == ADC_SAMP_TIME_1CYCLES5) || ((TIME) == ADC_SAMP_TIME_7CYCLES5) || ((TIME) == ADC_SAMP_TIME_13CYCLES5) \
+ || ((TIME) == ADC_SAMP_TIME_28CYCLES5) || ((TIME) == ADC_SAMP_TIME_41CYCLES5) \
+ || ((TIME) == ADC_SAMP_TIME_55CYCLES5) || ((TIME) == ADC_SAMP_TIME_71CYCLES5) \
+ || ((TIME) == ADC_SAMP_TIME_239CYCLES5))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_external_trigger_sources_for_injected_channels_conversion
+ * @{
+ */
+
+#define ADC_EXT_TRIG_INJ_CONV_T1_TRGO ((uint32_t)0x00000000)
+#define ADC_EXT_TRIG_INJ_CONV_T1_CC4 ((uint32_t)0x00001000)
+#define ADC_EXT_TRIG_INJ_CONV_T2_TRGO ((uint32_t)0x00002000)
+#define ADC_EXT_TRIG_INJ_CONV_T2_CC1 ((uint32_t)0x00003000)
+#define ADC_EXT_TRIG_INJ_CONV_T3_CC4 ((uint32_t)0x00004000)
+#define ADC_EXT_TRIG_INJ_CONV_T4_TRGO ((uint32_t)0x00005000)
+#define ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4 ((uint32_t)0x00006000)
+#define ADC_EXT_TRIG_INJ_CONV_NONE ((uint32_t)0x00007000)
+
+
+#define IsAdcExtInjTrig(INJTRIG) \
+ (((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T1_TRGO) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T1_CC4) \
+ || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T2_TRGO) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T2_CC1) \
+ || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T3_CC4) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T4_TRGO) \
+ || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_NONE))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_injected_channel_selection
+ * @{
+ */
+
+#define ADC_INJ_CH_1 ((uint8_t)0x14)
+#define ADC_INJ_CH_2 ((uint8_t)0x18)
+#define ADC_INJ_CH_3 ((uint8_t)0x1C)
+#define ADC_INJ_CH_4 ((uint8_t)0x20)
+#define IsAdcInjCh(CHANNEL) \
+ (((CHANNEL) == ADC_INJ_CH_1) || ((CHANNEL) == ADC_INJ_CH_2) || ((CHANNEL) == ADC_INJ_CH_3) \
+ || ((CHANNEL) == ADC_INJ_CH_4))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_analog_watchdog_selection
+ * @{
+ */
+
+#define ADC_ANALOG_WTDG_SINGLEREG_ENABLE ((uint32_t)0x00800200)
+#define ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE ((uint32_t)0x00400200)
+#define ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE ((uint32_t)0x00C00200)
+#define ADC_ANALOG_WTDG_ALLREG_ENABLE ((uint32_t)0x00800000)
+#define ADC_ANALOG_WTDG_ALLINJEC_ENABLE ((uint32_t)0x00400000)
+#define ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE ((uint32_t)0x00C00000)
+#define ADC_ANALOG_WTDG_NONE ((uint32_t)0x00000000)
+
+#define IsAdcAnalogWatchdog(WATCHDOG) \
+ (((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEREG_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE) \
+ || ((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLREG_ENABLE) \
+ || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLINJEC_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE) \
+ || ((WATCHDOG) == ADC_ANALOG_WTDG_NONE))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_interrupts_definition
+ * @{
+ */
+
+#define ADC_INT_ENDC ((uint16_t)0x0220)
+#define ADC_INT_AWD ((uint16_t)0x0140)
+#define ADC_INT_JENDC ((uint16_t)0x0480)
+
+#define IsAdcInt(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))
+
+#define IsAdcGetInt(IT) (((IT) == ADC_INT_ENDC) || ((IT) == ADC_INT_AWD) || ((IT) == ADC_INT_JENDC))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_flags_definition
+ * @{
+ */
+
+#define ADC_FLAG_AWDG ((uint8_t)0x01)
+#define ADC_FLAG_ENDC ((uint8_t)0x02)
+#define ADC_FLAG_JENDC ((uint8_t)0x04)
+#define ADC_FLAG_JSTR ((uint8_t)0x08)
+#define ADC_FLAG_STR ((uint8_t)0x10)
+#define ADC_FLAG_EOC_ANY ((uint8_t)0x20)
+#define ADC_FLAG_JEOC_ANY ((uint8_t)0x40)
+#define IsAdcClrFlag(FLAG) ((((FLAG) & (uint8_t)0x80) == 0x00) && ((FLAG) != 0x00))
+#define IsAdcGetFlag(FLAG) \
+ (((FLAG) == ADC_FLAG_AWDG) || ((FLAG) == ADC_FLAG_ENDC) || ((FLAG) == ADC_FLAG_JENDC) || ((FLAG) == ADC_FLAG_JSTR) \
+ || ((FLAG) == ADC_FLAG_STR) || ((FLAG) == ADC_FLAG_EOC_ANY) || ((FLAG) == ADC_FLAG_JEOC_ANY))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_thresholds
+ * @{
+ */
+#define IsAdcValid(THRESHOLD) ((THRESHOLD) <= 0xFFF)
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_injected_offset
+ * @{
+ */
+
+#define IsAdcOffsetValid(OFFSET) ((OFFSET) <= 0xFFF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_injected_length
+ * @{
+ */
+
+#define IsAdcInjLenValid(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_injected_rank
+ * @{
+ */
+
+#define IsAdcInjRankValid(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_regular_length
+ * @{
+ */
+
+#define IsAdcSeqLenValid(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_regular_rank
+ * @{
+ */
+
+#define IsAdcReqRankValid(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_regular_discontinuous_mode_number
+ * @{
+ */
+
+#define IsAdcSeqDiscNumberValid(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
+
+/**
+ * @}
+ */
+
+/************************** fllowing bit seg in ex register **********************/
+/**@addtogroup ADC_channels_ex_style
+ * @{
+ */
+
+
+#define ADC_CH_0 ((uint8_t)0x00)
+#define ADC_CH_1_PA0 ((uint8_t)0x01)
+#define ADC_CH_2_PA1 ((uint8_t)0x02)
+#define ADC_CH_3_PA2 ((uint8_t)0x03)
+#define ADC_CH_4_PA3 ((uint8_t)0x04)
+#define ADC_CH_5_PA4 ((uint8_t)0x05)
+#define ADC_CH_6_PA5 ((uint8_t)0x06)
+#define ADC_CH_7_PA6 ((uint8_t)0x07)
+#define ADC_CH_8_PA7 ((uint8_t)0x08)
+#define ADC_CH_9_PB0 ((uint8_t)0x09)
+#define ADC_CH_10_PB1 ((uint8_t)0x0A)
+#define ADC_CH_11_PC0 ((uint8_t)0x0B)
+#define ADC_CH_12_PC1 ((uint8_t)0x0C)
+#define ADC_CH_13_PC2 ((uint8_t)0x0D)
+#define ADC_CH_14_PC3 ((uint8_t)0x0E)
+#define ADC_CH_15_PC4 ((uint8_t)0x0F)
+#define ADC_CH_16_PC5 ((uint8_t)0x10)
+#define ADC_CH_17 ((uint8_t)0x11)
+#define ADC_CH_18 ((uint8_t)0x12)
+/**
+ * @}
+ */
+
+/**@addtogroup ADC_dif_sel_ch_definition
+ * @{
+ */
+#define aDC_DIFSEL_CHS_MASK ((uint32_t)0x0007FFFF)
+#define ADC_DIFSEL_CHS_0 ((uint32_t)0x00000001)
+#define ADC_DIFSEL_CHS_1 ((uint32_t)0x00000002)
+#define ADC_DIFSEL_CHS_2 ((uint32_t)0x00000004)
+#define ADC_DIFSEL_CHS_3 ((uint32_t)0x00000008)
+#define ADC_DIFSEL_CHS_4 ((uint32_t)0x00000010)
+#define ADC_DIFSEL_CHS_5 ((uint32_t)0x00000020)
+#define ADC_DIFSEL_CHS_6 ((uint32_t)0x00000040)
+#define ADC_DIFSEL_CHS_7 ((uint32_t)0x00000080)
+#define ADC_DIFSEL_CHS_8 ((uint32_t)0x00000100)
+#define ADC_DIFSEL_CHS_9 ((uint32_t)0x00000200)
+#define ADC_DIFSEL_CHS_10 ((uint32_t)0x00000400)
+#define ADC_DIFSEL_CHS_11 ((uint32_t)0x00000800)
+#define ADC_DIFSEL_CHS_12 ((uint32_t)0x00001000)
+#define ADC_DIFSEL_CHS_13 ((uint32_t)0x00002000)
+#define ADC_DIFSEL_CHS_14 ((uint32_t)0x00004000)
+#define ADC_DIFSEL_CHS_15 ((uint32_t)0x00008000)
+#define ADC_DIFSEL_CHS_16 ((uint32_t)0x00010000)
+#define ADC_DIFSEL_CHS_17 ((uint32_t)0x00020000)
+#define ADC_DIFSEL_CHS_18 ((uint32_t)0x00040000)
+/**
+ * @}
+ */
+
+/**@addtogroup ADC_calfact_definition
+ * @{
+ */
+#define ADC_CALFACT_CALFACTD_MSK ((uint32_t)0x3FL << 16)
+#define ADC_CALFACT_CALFACTS_MSK ((uint32_t)0x3FL << 0)
+/**
+ * @}
+ */
+
+/**@addtogroup ADC_ctrl3_definition
+ * @{
+ */
+#define ADC_CTRL3_DPWMOD_MSK ((uint32_t)0x01L << 10)
+#define ADC_CTRL3_JENDCAIEN_MSK ((uint32_t)0x01L << 9)
+#define ADC_CTRL3_ENDCAIEN_MSK ((uint32_t)0x01L << 8)
+#define ADC_CTRL3_BPCAL_MSK ((uint32_t)0x01L << 7)
+#define ADC_CTRL3_CKMOD_MSK ((uint32_t)0x01L << 4)
+#define ADC_CTRL3_CALALD_MSK ((uint32_t)0x01L << 3)
+#define ADC_CTRL3_CALDIF_MSK ((uint32_t)0x01L << 2)
+#define ADC_CTRL3_RES_MSK ((uint32_t)0x03L << 0)
+#define ADC_SAMPT3_SAMPSEL_MSK ((uint32_t)0x01L << 3)
+typedef enum
+{
+ ADC_CTRL3_CKMOD_AHB = 0,
+ ADC_CTRL3_CKMOD_PLL = 1,
+} ADC_CTRL3_CKMOD;
+typedef enum
+{
+ ADC_CTRL3_RES_12BIT = 3,
+ ADC_CTRL3_RES_10BIT = 2,
+ ADC_CTRL3_RES_8BIT = 1,
+ ADC_CTRL3_RES_6BIT = 0,
+} ADC_CTRL3_RES;
+typedef struct
+{
+ FunctionalState DeepPowerModEn;
+ FunctionalState JendcIntEn;
+ FunctionalState EndcIntEn;
+ ADC_CTRL3_CKMOD ClkMode;
+ FunctionalState CalAtuoLoadEn;
+ bool DifModCal;
+ ADC_CTRL3_RES ResBit;
+ bool Samp303Style;
+} ADC_InitTypeEx;
+/**
+ * @}
+ */
+
+/**@addtogroup ADC_bit_num_definition
+ * @{
+ */
+#define ADC_RST_BIT_12 ((uint32_t)0x03)
+#define ADC_RST_BIT_10 ((uint32_t)0x02)
+#define ADC_RST_BIT_8 ((uint32_t)0x01)
+#define ADC_RESULT_BIT_6 ((uint32_t)0x00)
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_flags_ex_definition
+ * @{
+ */
+#define ADC_FLAG_RDY ((uint8_t)0x20)
+#define ADC_FLAG_PD_RDY ((uint8_t)0x40)
+#define IS_ADC_GET_READY(FLAG) (((FLAG) == ADC_FLAG_RDY) || ((FLAG) == ADC_FLAG_PD_RDY))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Exported_Functions
+ * @{
+ */
+
+void ADC_DeInit(ADC_Module* ADCx);
+void ADC_Init(ADC_Module* ADCx, ADC_InitType* ADC_InitStruct);
+void ADC_InitStruct(ADC_InitType* ADC_InitStruct);
+void ADC_Enable(ADC_Module* ADCx, FunctionalState Cmd);
+void ADC_EnableDMA(ADC_Module* ADCx, FunctionalState Cmd);
+void ADC_ConfigInt(ADC_Module* ADCx, uint16_t ADC_IT, FunctionalState Cmd);
+void ADC_StartCalibration(ADC_Module* ADCx);
+FlagStatus ADC_GetCalibrationStatus(ADC_Module* ADCx);
+void ADC_EnableSoftwareStartConv(ADC_Module* ADCx, FunctionalState Cmd);
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_Module* ADCx);
+void ADC_ConfigDiscModeChannelCount(ADC_Module* ADCx, uint8_t Number);
+void ADC_EnableDiscMode(ADC_Module* ADCx, FunctionalState Cmd);
+void ADC_ConfigRegularChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_EnableExternalTrigConv(ADC_Module* ADCx, FunctionalState Cmd);
+uint16_t ADC_GetDat(ADC_Module* ADCx);
+void ADC_EnableAutoInjectedConv(ADC_Module* ADCx, FunctionalState Cmd);
+void ADC_EnableInjectedDiscMode(ADC_Module* ADCx, FunctionalState Cmd);
+void ADC_ConfigExternalTrigInjectedConv(ADC_Module* ADCx, uint32_t ADC_ExternalTrigInjecConv);
+void ADC_EnableExternalTrigInjectedConv(ADC_Module* ADCx, FunctionalState Cmd);
+void ADC_EnableSoftwareStartInjectedConv(ADC_Module* ADCx, FunctionalState Cmd);
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_Module* ADCx);
+void ADC_ConfigInjectedChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_ConfigInjectedSequencerLength(ADC_Module* ADCx, uint8_t Length);
+void ADC_SetInjectedOffsetDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
+uint16_t ADC_GetInjectedConversionDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel);
+void ADC_ConfigAnalogWatchdogWorkChannelType(ADC_Module* ADCx, uint32_t ADC_AnalogWatchdog);
+void ADC_ConfigAnalogWatchdogThresholds(ADC_Module* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
+void ADC_ConfigAnalogWatchdogSingleChannel(ADC_Module* ADCx, uint8_t ADC_Channel);
+void ADC_EnableTempSensorVrefint(FunctionalState Cmd);
+FlagStatus ADC_GetFlagStatus(ADC_Module* ADCx, uint8_t ADC_FLAG);
+void ADC_ClearFlag(ADC_Module* ADCx, uint8_t ADC_FLAG);
+INTStatus ADC_GetIntStatus(ADC_Module* ADCx, uint16_t ADC_IT);
+void ADC_ClearIntPendingBit(ADC_Module* ADCx, uint16_t ADC_IT);
+
+void ADC_InitEx(ADC_Module* ADCx, ADC_InitTypeEx* ADC_InitStructEx);
+FlagStatus ADC_GetFlagStatusNew(ADC_Module* ADCx, uint8_t ADC_FLAG_NEW);
+void ADC_SetBypassCalibration(ADC_Module* ADCx, FunctionalState en);
+void ADC_SetConvResultBitNum(ADC_Module* ADCx, uint32_t ResultBitNum);
+
+void ADC_ConfigClk(ADC_CTRL3_CKMOD ADC_ClkMode, uint32_t RCC_ADCHCLKPrescaler);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32L40X_ADC_H__ */
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_can.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_can.h
new file mode 100644
index 0000000000..63cb7f3dc5
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_can.h
@@ -0,0 +1,670 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_can.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L40X_CAN_H__
+#define __N32L40X_CAN_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l40x.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CAN
+ * @{
+ */
+
+/** @addtogroup CAN_Exported_Types
+ * @{
+ */
+
+#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN))
+
+/**
+ * @brief CAN init structure definition
+ */
+
+typedef struct
+{
+ uint16_t BaudRatePrescaler; /*!< Specifies the length of a time quantum.
+ It ranges from 1 to 1024. */
+
+ uint8_t OperatingMode; /*!< Specifies the CAN operating mode.
+ This parameter can be a value of
+ @ref CAN_operating_mode */
+
+ uint8_t RSJW; /*!< Specifies the maximum number of time quanta
+ the CAN hardware is allowed to lengthen or
+ shorten a bit to perform resynchronization.
+ This parameter can be a value of
+ @ref CAN_synchronisation_jump_width */
+
+ uint8_t TBS1; /*!< Specifies the number of time quanta in Bit
+ Segment 1. This parameter can be a value of
+ @ref CAN_time_quantum_in_bit_segment_1 */
+
+ uint8_t TBS2; /*!< Specifies the number of time quanta in Bit
+ Segment 2.
+ This parameter can be a value of
+ @ref CAN_time_quantum_in_bit_segment_2 */
+
+ FunctionalState TTCM; /*!< Enable or disable the time triggered
+ communication mode. This parameter can be set
+ either to ENABLE or DISABLE. */
+
+ FunctionalState ABOM; /*!< Enable or disable the automatic bus-off
+ management. This parameter can be set either
+ to ENABLE or DISABLE. */
+
+ FunctionalState AWKUM; /*!< Enable or disable the automatic wake-up mode.
+ This parameter can be set either to ENABLE or
+ DISABLE. */
+
+ FunctionalState NART; /*!< Enable or disable the no-automatic
+ retransmission mode. This parameter can be
+ set either to ENABLE or DISABLE. */
+
+ FunctionalState RFLM; /*!< Enable or disable the Receive DATFIFO Locked mode.
+ This parameter can be set either to ENABLE
+ or DISABLE. */
+
+ FunctionalState TXFP; /*!< Enable or disable the transmit DATFIFO priority.
+ This parameter can be set either to ENABLE
+ or DISABLE. */
+} CAN_InitType;
+
+/**
+ * @brief CAN filter init structure definition
+ */
+
+typedef struct
+{
+ uint16_t Filter_HighId; /*!< Specifies the filter identification number (MSBs for a 32-bit
+ configuration, first one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t Filter_LowId; /*!< Specifies the filter identification number (LSBs for a 32-bit
+ configuration, second one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t FilterMask_HighId; /*!< Specifies the filter mask number or identification number,
+ according to the mode (MSBs for a 32-bit configuration,
+ first one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t FilterMask_LowId; /*!< Specifies the filter mask number or identification number,
+ according to the mode (LSBs for a 32-bit configuration,
+ second one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t Filter_FIFOAssignment; /*!< Specifies the DATFIFO (0 or 1) which will be assigned to the filter.
+ This parameter can be a value of @ref CAN_filter_FIFO */
+
+ uint8_t Filter_Num; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
+
+ uint8_t Filter_Mode; /*!< Specifies the filter mode to be initialized.
+ This parameter can be a value of @ref CAN_filter_mode */
+
+ uint8_t Filter_Scale; /*!< Specifies the filter scale.
+ This parameter can be a value of @ref CAN_filter_scale */
+
+ FunctionalState Filter_Act; /*!< Enable or disable the filter.
+ This parameter can be set either to ENABLE or DISABLE. */
+} CAN_FilterInitType;
+
+/**
+ * @brief CAN Tx message structure definition
+ */
+
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter can be a value between 0 to 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+ uint8_t IDE; /*!< Specifies the type of identifier for the message that
+ will be transmitted. This parameter can be a value
+ of @ref CAN_identifier_type */
+
+ uint8_t RTR; /*!< Specifies the type of frame for the message that will
+ be transmitted. This parameter can be a value of
+ @ref CAN_remote_transmission_request */
+
+ uint8_t DLC; /*!< Specifies the length of the frame that will be
+ transmitted. This parameter can be a value between
+ 0 to 8 */
+
+ uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
+ to 0xFF. */
+} CanTxMessage;
+
+/**
+ * @brief CAN Rx message structure definition
+ */
+
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter can be a value between 0 to 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+ uint8_t IDE; /*!< Specifies the type of identifier for the message that
+ will be received. This parameter can be a value of
+ @ref CAN_identifier_type */
+
+ uint8_t RTR; /*!< Specifies the type of frame for the received message.
+ This parameter can be a value of
+ @ref CAN_remote_transmission_request */
+
+ uint8_t DLC; /*!< Specifies the length of the frame that will be received.
+ This parameter can be a value between 0 to 8 */
+
+ uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
+ 0xFF. */
+
+ uint8_t FMI; /*!< Specifies the index of the filter the message stored in
+ the mailbox passes through. This parameter can be a
+ value between 0 to 0xFF */
+} CanRxMessage;
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup CAN_sleep_constants
+ * @{
+ */
+
+#define CAN_InitSTS_Failed ((uint8_t)0x00) /*!< CAN initialization failed */
+#define CAN_InitSTS_Success ((uint8_t)0x01) /*!< CAN initialization OK */
+
+/**
+ * @}
+ */
+
+/** @addtogroup OperatingMode
+ * @{
+ */
+
+#define CAN_Normal_Mode ((uint8_t)0x00) /*!< normal mode */
+#define CAN_LoopBack_Mode ((uint8_t)0x01) /*!< loopback mode */
+#define CAN_Silent_Mode ((uint8_t)0x02) /*!< silent mode */
+#define CAN_Silent_LoopBack_Mode ((uint8_t)0x03) /*!< loopback combined with silent mode */
+
+#define IS_CAN_MODE(MODE) \
+ (((MODE) == CAN_Normal_Mode) || ((MODE) == CAN_LoopBack_Mode) || ((MODE) == CAN_Silent_Mode) \
+ || ((MODE) == CAN_Silent_LoopBack_Mode))
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup CAN_operating_mode
+ * @{
+ */
+#define CAN_Operating_InitMode ((uint8_t)0x00) /*!< Initialization mode */
+#define CAN_Operating_NormalMode ((uint8_t)0x01) /*!< Normal mode */
+#define CAN_Operating_SleepMode ((uint8_t)0x02) /*!< sleep mode */
+
+#define IS_CAN_OPERATING_MODE(MODE) \
+ (((MODE) == CAN_Operating_InitMode) || ((MODE) == CAN_Operating_NormalMode) || ((MODE) == CAN_Operating_SleepMode))
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup CAN_Mode_Status
+ * @{
+ */
+
+#define CAN_ModeSTS_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */
+#define CAN_ModeSTS_Success ((uint8_t)!CAN_ModeSTS_Failed) /*!< CAN entering the specific mode Succeed */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_synchronisation_jump_width
+ * @{
+ */
+
+#define CAN_RSJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_RSJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_RSJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_RSJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+
+#define IS_CAN_RSJW(SJW) \
+ (((SJW) == CAN_RSJW_1tq) || ((SJW) == CAN_RSJW_2tq) || ((SJW) == CAN_RSJW_3tq) || ((SJW) == CAN_RSJW_4tq))
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_time_quantum_in_bit_segment_1
+ * @{
+ */
+
+#define CAN_TBS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_TBS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_TBS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_TBS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+#define CAN_TBS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */
+#define CAN_TBS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */
+#define CAN_TBS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */
+#define CAN_TBS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */
+#define CAN_TBS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */
+#define CAN_TBS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */
+#define CAN_TBS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */
+#define CAN_TBS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */
+#define CAN_TBS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */
+#define CAN_TBS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */
+#define CAN_TBS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */
+#define CAN_TBS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */
+
+#define IS_CAN_TBS1(BS1) ((BS1) <= CAN_TBS1_16tq)
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_time_quantum_in_bit_segment_2
+ * @{
+ */
+
+#define CAN_TBS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_TBS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_TBS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_TBS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+#define CAN_TBS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */
+#define CAN_TBS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */
+#define CAN_TBS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */
+#define CAN_TBS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */
+
+#define IS_CAN_TBS2(BS2) ((BS2) <= CAN_TBS2_8tq)
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_clock_prescaler
+ * @{
+ */
+
+#define IS_CAN_BAUDRATEPRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_filter_number
+ * @{
+ */
+#define IS_CAN_FILTER_NUM(NUMBER) ((NUMBER) <= 13)
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_filter_mode
+ * @{
+ */
+
+#define CAN_Filter_IdMaskMode ((uint8_t)0x00) /*!< identifier/mask mode */
+#define CAN_Filter_IdListMode ((uint8_t)0x01) /*!< identifier list mode */
+
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_Filter_IdMaskMode) || ((MODE) == CAN_Filter_IdListMode))
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_filter_scale
+ * @{
+ */
+
+#define CAN_Filter_16bitScale ((uint8_t)0x00) /*!< Two 16-bit filters */
+#define CAN_Filter_32bitScale ((uint8_t)0x01) /*!< One 32-bit filter */
+
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_Filter_16bitScale) || ((SCALE) == CAN_Filter_32bitScale))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_filter_FIFO
+ * @{
+ */
+
+#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter DATFIFO 0 assignment for filter x */
+#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter DATFIFO 1 assignment for filter x */
+#define IS_CAN_FILTER_FIFO(DATFIFO) (((DATFIFO) == CAN_FilterFIFO0) || ((DATFIFO) == CAN_FilterFIFO1))
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Tx
+ * @{
+ */
+
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_identifier_type
+ * @{
+ */
+
+#define CAN_Standard_Id ((uint32_t)0x00000000) /*!< Standard Id */
+#define CAN_Extended_Id ((uint32_t)0x00000004) /*!< Extended Id */
+#define IS_CAN_ID(IDTYPE) (((IDTYPE) == CAN_Standard_Id) || ((IDTYPE) == CAN_Extended_Id))
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_remote_transmission_request
+ * @{
+ */
+
+#define CAN_RTRQ_Data ((uint32_t)0x00000000) /*!< Data frame */
+#define CAN_RTRQ_Remote ((uint32_t)0x00000002) /*!< Remote frame */
+#define IS_CAN_RTRQ(RTR) (((RTR) == CAN_RTRQ_Data) || ((RTR) == CAN_RTRQ_Remote))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_transmit_constants
+ * @{
+ */
+
+#define CAN_TxSTS_Failed ((uint8_t)0x00) /*!< CAN transmission failed */
+#define CAN_TxSTS_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */
+#define CAN_TxSTS_Pending ((uint8_t)0x02) /*!< CAN transmission pending */
+#define CAN_TxSTS_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_receive_FIFO_number_constants
+ * @{
+ */
+
+#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN DATFIFO 0 used to receive */
+#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN DATFIFO 1 used to receive */
+
+#define IS_CAN_FIFO(DATFIFO) (((DATFIFO) == CAN_FIFO0) || ((DATFIFO) == CAN_FIFO1))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_sleep_constants
+ * @{
+ */
+
+#define CAN_SLEEP_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
+#define CAN_SLEEP_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_wake_up_constants
+ * @{
+ */
+
+#define CAN_WKU_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
+#define CAN_WKU_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
+
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup CAN_Error_Code_constants
+ * @{
+ */
+
+#define CAN_ERRCode_NoErr ((uint8_t)0x00) /*!< No Error */
+#define CAN_ERRCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */
+#define CAN_ERRCode_FormErr ((uint8_t)0x20) /*!< Form Error */
+#define CAN_ERRCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */
+#define CAN_ERRCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */
+#define CAN_ERRCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */
+#define CAN_ERRCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */
+#define CAN_ERRCode_SWSetErr ((uint8_t)0x70) /*!< Software Set Error */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_flags
+ * @{
+ */
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagSTS()
+ and CAN_ClearFlag() functions. */
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagSTS() function. */
+
+/* Transmit Flags */
+#define CAN_FLAG_RQCPM0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
+#define CAN_FLAG_RQCPM1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
+#define CAN_FLAG_RQCPM2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
+
+/* Receive Flags */
+#define CAN_FLAG_FFMP0 ((uint32_t)0x12000003) /*!< DATFIFO 0 Message Pending Flag */
+#define CAN_FLAG_FFULL0 ((uint32_t)0x32000008) /*!< DATFIFO 0 Full Flag */
+#define CAN_FLAG_FFOVR0 ((uint32_t)0x32000010) /*!< DATFIFO 0 Overrun Flag */
+#define CAN_FLAG_FFMP1 ((uint32_t)0x14000003) /*!< DATFIFO 1 Message Pending Flag */
+#define CAN_FLAG_FFULL1 ((uint32_t)0x34000008) /*!< DATFIFO 1 Full Flag */
+#define CAN_FLAG_FFOVR1 ((uint32_t)0x34000010) /*!< DATFIFO 1 Overrun Flag */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */
+#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
+/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible.
+ In this case the SLAK bit can be polled.*/
+
+/* Error Flags */
+#define CAN_FLAG_EWGFL ((uint32_t)0x10F00001) /*!< Error Warning Flag */
+#define CAN_FLAG_EPVFL ((uint32_t)0x10F00002) /*!< Error Passive Flag */
+#define CAN_FLAG_BOFFL ((uint32_t)0x10F00004) /*!< Bus-Off Flag */
+#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */
+
+#define IS_CAN_GET_FLAG(FLAG) \
+ (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOFFL) || ((FLAG) == CAN_FLAG_EPVFL) \
+ || ((FLAG) == CAN_FLAG_EWGFL) || ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FFOVR0) \
+ || ((FLAG) == CAN_FLAG_FFULL0) || ((FLAG) == CAN_FLAG_FFMP0) || ((FLAG) == CAN_FLAG_FFOVR1) \
+ || ((FLAG) == CAN_FLAG_FFULL1) || ((FLAG) == CAN_FLAG_FFMP1) || ((FLAG) == CAN_FLAG_RQCPM2) \
+ || ((FLAG) == CAN_FLAG_RQCPM1) || ((FLAG) == CAN_FLAG_RQCPM0) || ((FLAG) == CAN_FLAG_SLAK))
+
+#define IS_CAN_CLEAR_FLAG(FLAG) \
+ (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCPM2) || ((FLAG) == CAN_FLAG_RQCPM1) \
+ || ((FLAG) == CAN_FLAG_RQCPM0) || ((FLAG) == CAN_FLAG_FFULL0) || ((FLAG) == CAN_FLAG_FFOVR0) \
+ || ((FLAG) == CAN_FLAG_FFULL1) || ((FLAG) == CAN_FLAG_FFOVR1) || ((FLAG) == CAN_FLAG_WKU) \
+ || ((FLAG) == CAN_FLAG_SLAK))
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_interrupts
+ * @{
+ */
+
+#define CAN_INT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
+
+/* Receive Interrupts */
+#define CAN_INT_FMP0 ((uint32_t)0x00000002) /*!< DATFIFO 0 message pending Interrupt*/
+#define CAN_INT_FF0 ((uint32_t)0x00000004) /*!< DATFIFO 0 full Interrupt*/
+#define CAN_INT_FOV0 ((uint32_t)0x00000008) /*!< DATFIFO 0 overrun Interrupt*/
+#define CAN_INT_FMP1 ((uint32_t)0x00000010) /*!< DATFIFO 1 message pending Interrupt*/
+#define CAN_INT_FF1 ((uint32_t)0x00000020) /*!< DATFIFO 1 full Interrupt*/
+#define CAN_INT_FOV1 ((uint32_t)0x00000040) /*!< DATFIFO 1 overrun Interrupt*/
+
+/* Operating Mode Interrupts */
+#define CAN_INT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
+#define CAN_INT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
+
+/* Error Interrupts */
+#define CAN_INT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
+#define CAN_INT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
+#define CAN_INT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
+#define CAN_INT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
+#define CAN_INT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/
+
+/* Flags named as Interrupts : kept only for FW compatibility */
+#define CAN_INT_RQCPM0 CAN_INT_TME
+#define CAN_INT_RQCPM1 CAN_INT_TME
+#define CAN_INT_RQCPM2 CAN_INT_TME
+
+#define IS_CAN_INT(IT) \
+ (((IT) == CAN_INT_TME) || ((IT) == CAN_INT_FMP0) || ((IT) == CAN_INT_FF0) || ((IT) == CAN_INT_FOV0) \
+ || ((IT) == CAN_INT_FMP1) || ((IT) == CAN_INT_FF1) || ((IT) == CAN_INT_FOV1) || ((IT) == CAN_INT_EWG) \
+ || ((IT) == CAN_INT_EPV) || ((IT) == CAN_INT_BOF) || ((IT) == CAN_INT_LEC) || ((IT) == CAN_INT_ERR) \
+ || ((IT) == CAN_INT_WKU) || ((IT) == CAN_INT_SLK))
+
+#define IS_CAN_CLEAR_INT(IT) \
+ (((IT) == CAN_INT_TME) || ((IT) == CAN_INT_FF0) || ((IT) == CAN_INT_FOV0) || ((IT) == CAN_INT_FF1) \
+ || ((IT) == CAN_INT_FOV1) || ((IT) == CAN_INT_EWG) || ((IT) == CAN_INT_EPV) || ((IT) == CAN_INT_BOF) \
+ || ((IT) == CAN_INT_LEC) || ((IT) == CAN_INT_ERR) || ((IT) == CAN_INT_WKU) || ((IT) == CAN_INT_SLK))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Legacy
+ * @{
+ */
+#define CANINITSTSFAILED CAN_InitSTS_Failed
+#define CANINITSTSOK CAN_InitSTS_Success
+#define CAN_FilterFIFO0 CAN_Filter_FIFO0
+#define CAN_FilterFIFO1 CAN_Filter_FIFO1
+#define CAN_ID_STD CAN_Standard_Id
+#define CAN_ID_EXT CAN_Extended_Id
+#define CAN_RTRQ_DATA CAN_RTRQ_Data
+#define CAN_RTRQ_REMOTE CAN_RTRQ_Remote
+#define CANTXSTSFAILE CAN_TxSTS_Failed
+#define CANTXSTSOK CAN_TxSTS_Ok
+#define CANTXSTSPENDING CAN_TxSTS_Pending
+#define CAN_STS_NO_MB CAN_TxSTS_NoMailBox
+#define CANSLEEPFAILED CAN_SLEEP_Failed
+#define CANSLEEPOK CAN_SLEEP_Ok
+#define CANWKUFAILED CAN_WKU_Failed
+#define CANWKUOK CAN_WKU_Ok
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions
+ * @{
+ */
+/* Function used to set the CAN configuration to the default reset state *****/
+void CAN_DeInit(CAN_Module* CANx);
+
+/* Initialization and Configuration functions *********************************/
+uint8_t CAN_Init(CAN_Module* CANx, CAN_InitType* CAN_InitParam);
+void CAN_InitFilter(CAN_FilterInitType* CAN_InitFilterStruct);
+void CAN_InitStruct(CAN_InitType* CAN_InitParam);
+void CAN_DebugFreeze(CAN_Module* CANx, FunctionalState Cmd);
+void CAN_EnTTComMode(CAN_Module* CANx, FunctionalState Cmd);
+
+/* Transmit functions *********************************************************/
+uint8_t CAN_TransmitMessage(CAN_Module* CANx, CanTxMessage* TxMessage);
+uint8_t CAN_TransmitSTS(CAN_Module* CANx, uint8_t TransmitMailbox);
+void CAN_CancelTransmitMessage(CAN_Module* CANx, uint8_t Mailbox);
+
+/* Receive functions **********************************************************/
+void CAN_ReceiveMessage(CAN_Module* CANx, uint8_t FIFONum, CanRxMessage* RxMessage);
+void CAN_ReleaseFIFO(CAN_Module* CANx, uint8_t FIFONum);
+uint8_t CAN_PendingMessage(CAN_Module* CANx, uint8_t FIFONum);
+
+/* Operation modes functions **************************************************/
+uint8_t CAN_OperatingModeReq(CAN_Module* CANx, uint8_t CAN_OperatingMode);
+uint8_t CAN_EnterSleep(CAN_Module* CANx);
+uint8_t CAN_WakeUp(CAN_Module* CANx);
+
+/* Error management functions *************************************************/
+uint8_t CAN_GetLastErrCode(CAN_Module* CANx);
+uint8_t CAN_GetReceiveErrCounter(CAN_Module* CANx);
+uint8_t CAN_GetLSBTransmitErrCounter(CAN_Module* CANx);
+
+/* Interrupts and flags management functions **********************************/
+void CAN_INTConfig(CAN_Module* CANx, uint32_t CAN_INT, FunctionalState Cmd);
+FlagStatus CAN_GetFlagSTS(CAN_Module* CANx, uint32_t CAN_FLAG);
+void CAN_ClearFlag(CAN_Module* CANx, uint32_t CAN_FLAG);
+INTStatus CAN_GetIntStatus(CAN_Module* CANx, uint32_t CAN_INT);
+void CAN_ClearINTPendingBit(CAN_Module* CANx, uint32_t CAN_INT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32L40X_CAN_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_comp.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_comp.h
new file mode 100644
index 0000000000..9afb06e2b0
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_comp.h
@@ -0,0 +1,282 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_comp.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L40X_COMP_H__
+#define __N32L40X_COMP_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l40x.h"
+#include
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup COMP
+ * @{
+ */
+
+/** @addtogroup COMP_Exported_Constants
+ * @{
+ */
+typedef enum
+{
+ COMP1 = 0,
+ COMP2 = 1,
+} COMPX;
+
+// COMPx_CTRL
+#define COMP1_CTRL_PWRMODE_MASK (0x01L << 21)
+#define COMP1_CTRL_INPDAC_MASK (0x01L << 20)
+#define COMP_CTRL_OUT_MASK (0x01L << 19)
+#define COMP_CTRL_BLKING_MASK (0x03L << 16)
+typedef enum
+{
+ COMP_CTRL_BLKING_NO = (0x0L << 16),
+ COMP_CTRL_BLKING_TIM1_OC5 = (0x1L << 16),
+ COMP_CTRL_BLKING_TIM8_OC5 = (0x2L << 16),
+} COMP_CTRL_BLKING;
+#define COMPx_CTRL_HYST_MASK (0x03L << 14)
+typedef enum
+{
+ COMP_CTRL_HYST_NO = (0x0L << 14),
+ COMP_CTRL_HYST_LOW = (0x1L << 14),
+ COMP_CTRL_HYST_MID = (0x2L << 14),
+ COMP_CTRL_HYST_HIGH = (0x3L << 14),
+} COMP_CTRL_HYST;
+
+#define COMP_POL_MASK (0x01L << 13)
+#define COMP_CTRL_OUTSEL_MASK (0x0FL << 9)
+typedef enum
+{
+ // comp1 out trig
+ COMP1_CTRL_OUTSEL_NC = (0x0L << 9),
+ COMP1_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 9),
+ COMP1_CTRL_OUTSEL_TIM1_OCrefclear = (0x2L << 9),
+ COMP1_CTRL_OUTSEL_TIM1_IC1 = (0x3L << 9),
+ COMP1_CTRL_OUTSEL_TIM2_IC1 = (0x4L << 9),
+ COMP1_CTRL_OUTSEL_TIM2_OCrefclear = (0x5L << 9),
+ COMP1_CTRL_OUTSEL_TIM3_IC1 = (0x6L << 9),
+ COMP1_CTRL_OUTSEL_TIM3_OCrefclear = (0x7L << 9),
+ COMP1_CTRL_OUTSEL_TIM4_OCrefclear = (0x8L << 9),
+ COMP1_CTRL_OUTSEL_TIM5_IC1 = (0x9L << 9),
+ COMP1_CTRL_OUTSEL_TIM8_IC1 = (0xAL << 9),
+ COMP1_CTRL_OUTSEL_TIM8_OCrefclear = (0xBL << 9),
+ COMP1_CTRL_OUTSEL_TIM9_OCrefclear = (0xCL << 9),
+ COMP1_CTRL_OUTSEL_TIM8_BKIN = (0xDL << 9),
+ COMP1_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xEL << 9),
+ COMP1_CTRL_OUTSEL_LPTIM_ETR = (0xFL << 9),
+ // comp2 out trig
+ COMP2_CTRL_OUTSEL_NC = (0x0L << 9),
+ COMP2_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 9),
+ COMP2_CTRL_OUTSEL_TIM1_OCrefclear = (0x2L << 9),
+ COMP2_CTRL_OUTSEL_TIM1_IC1 = (0x3L << 9),
+ COMP2_CTRL_OUTSEL_TIM2_OCrefclear = (0x4L << 9),
+ COMP2_CTRL_OUTSEL_TIM3_OCrefclear = (0x5L << 9),
+ COMP2_CTRL_OUTSEL_TIM4_IC1 = (0x6L << 9),
+ COMP2_CTRL_OUTSEL_TIM4_OCrefclear = (0x7L << 9),
+ COMP2_CTRL_OUTSEL_TIM5_IC1 = (0x8L << 9),
+ COMP2_CTRL_OUTSEL_TIM8_IC1 = (0x9L << 9),
+ COMP2_CTRL_OUTSEL_TIM8_OCrefclear = (0xAL << 9),
+ COMP2_CTRL_OUTSEL_TIM9_IC1 = (0xBL << 9),
+ COMP2_CTRL_OUTSEL_TIM9_OCrefclear = (0xCL << 9),
+ COMP2_CTRL_OUTSEL_TIM8_BKIN = (0xDL << 9),
+ COMP2_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xEL << 9),
+ COMP2_CTRL_OUTSEL_LPTIM_ETR = (0xFL << 9),
+} COMP_CTRL_OUTTRIG;
+
+#define COMP_CTRL_INPSEL_MASK (0x0FL<<5)
+typedef enum {
+ //comp1 inp sel
+ COMP1_CTRL_INPSEL_FLOAT = ((uint32_t)0x00000000),
+ COMP1_CTRL_INPSEL_PA0 = ((uint32_t)0x00000100),
+ COMP1_CTRL_INPSEL_PA2 = ((uint32_t)0x00000140),
+ COMP1_CTRL_INPSEL_PA12 = ((uint32_t)0x00000160),
+ COMP1_CTRL_INPSEL_PB3 = ((uint32_t)0x00000180),
+ COMP1_CTRL_INPSEL_PB4 = ((uint32_t)0x000001A0),
+ COMP1_CTRL_INPSEL_PB10 = ((uint32_t)0x000001C0),
+ COMP1_CTRL_INPSEL_PD5 = ((uint32_t)0x000001E0),
+ COMP1_CTRL_INPSEL_PA1_DAC1 = ((uint32_t)0x00000120),
+ //comp2 inp sel
+ COMP2_CTRL_INPSEL_FLOAT = ((uint32_t)0x00000000),
+ COMP2_CTRL_INPSEL_PA1_DAC1_PA4= ((uint32_t)0x00000100),
+ COMP2_CTRL_INPSEL_PA3 = ((uint32_t)0x00000120),
+ COMP2_CTRL_INPSEL_PA6 = ((uint32_t)0x00000140),
+ COMP2_CTRL_INPSEL_PA7 = ((uint32_t)0x00000160),
+ COMP2_CTRL_INPSEL_PA11 = ((uint32_t)0x00000180),
+ COMP2_CTRL_INPSEL_PA15 = ((uint32_t)0x000001A0),
+ COMP2_CTRL_INPSEL_PB7 = ((uint32_t)0x000001C0),
+ COMP2_CTRL_INPSEL_PD7 = ((uint32_t)0x000001E0),
+}COMP_CTRL_INPSEL;
+
+
+#define COMP_CTRL_INMSEL_MASK (0x07L<<1)
+typedef enum {
+ //comp1 inm sel
+ COMP1_CTRL_INMSEL_DAC1_PA4 = ((uint32_t)0x00000002),
+ COMP1_CTRL_INMSEL_PA0 = ((uint32_t)0x00000004),
+ COMP1_CTRL_INMSEL_PA5 = ((uint32_t)0x00000006),
+ COMP1_CTRL_INMSEL_PB5 = ((uint32_t)0x00000008),
+ COMP1_CTRL_INMSEL_PD4 = ((uint32_t)0x0000000A),
+ COMP1_CTRL_INMSEL_VREF_VC1 = ((uint32_t)0x0000000C),
+ COMP1_CTRL_INMSEL_VREF_VC2 = ((uint32_t)0x0000000E),
+ COMP1_CTRL_INMSEL_NC = ((uint32_t)0x00000000),
+ //comp2 inm sel
+ COMP2_CTRL_INMSEL_PA2 = ((uint32_t)0x00000002),
+ COMP2_CTRL_INMSEL_PA5 = ((uint32_t)0x00000004),
+ COMP2_CTRL_INMSEL_PA6 = ((uint32_t)0x00000006),
+ COMP2_CTRL_INMSEL_PB3 = ((uint32_t)0x00000008),
+ COMP2_CTRL_INMSEL_PD6 = ((uint32_t)0x0000000A),
+ COMP2_CTRL_INMSEL_DAC1_PA4 = ((uint32_t)0x0000000C),
+ COMP2_CTRL_INMSEL_VREF_VC2 = ((uint32_t)0x0000000E),
+ COMP2_CTRL_INMSEL_NC = ((uint32_t)0x00000000),
+}COMP_CTRL_INMSEL;
+
+#define COMP_CTRL_EN_MASK (0x01L << 0)
+
+//COMPx_FILC
+#define COMP_FILC_SAMPW_MASK (0x1FL<<6)//Low filter sample window size. Number of samples to monitor is SAMPWIN+1.
+#define COMP_FILC_THRESH_MASK (0x1FL<<1)//For proper operation, the value of THRESH must be greater than SAMPWIN / 2.
+#define COMP_FILC_FILEN_MASK (0x01L<<0)//Filter enable.
+
+//COMPx_FILP
+#define COMP_FILP_CLKPSC_MASK (0xFFFFL)//Prescale number .
+
+//COMP_WINMODE @addtogroup COMP_WINMODE_CMPMD
+#define COMP_WINMODE_CMP12MD (0x01L <<0)//1: Comparators 1 and 2 can be used in window mode.
+
+//COMP_INTEN @addtogroup COMP_INTEN_CMPIEN
+#define COMP_INTEN_CMPIEN_MSK (0x3L << 0) // This bit control Interrput enable of COMP.
+#define COMP_INTEN_CMP2IEN (0x01L << 1)
+#define COMP_INTEN_CMP1IEN (0x01L << 0)
+
+//COMP_INTSTS @addtogroup COMP_INTSTS_CMPIS
+#define COMP_INTSTS_INTSTS_MSK (0x3L << 0) // This bit control Interrput enable of COMP.
+#define COMP_INTSTS_CMP2IS (0x01L << 1)
+#define COMP_INTSTS_CMP1IS (0x01L << 0)
+
+//COMP_VREFSCL @addtogroup COMP_VREFSCL
+#define COMP_VREFSCL_VV2TRM_MSK (0x3FL << 8) // Vref2 Voltage scaler triming value.
+#define COMP_VREFSCL_VV2EN_MSK (0x01L << 7)
+#define COMP_VREFSCL_VV1TRM_MSK (0x3FL << 1) // Vref1 Voltage scaler triming value.
+#define COMP_VREFSCL_VV1EN_MSK (0x01L << 0)
+
+//COMP_LOCK @addtogroup COMP_LOCK
+#define COMP_LOCK_CMP2LK (0x1L << 1) // Vref1 Voltage scaler triming value.
+#define COMP_LOCK_CMP1LK (0x1L << 0)
+
+//COMP_LPCKSEL @addtogroup COMP_LPCKSEL
+#define COMP_LKCKSEL_LPCLKSEL (0x1L << 0)
+
+//COMP_OSEL @addtogroup COMP_OSEL
+#define COMP_OSEL_CMP2XO (0x1L << 0)
+
+/**
+ * @}
+ */
+
+/**
+ * @brief COMP Init structure definition
+ */
+
+typedef struct
+{
+ // ctrl
+ bool LowPoweMode; // only COMP1 have this bit
+ bool InpDacConnect; // only COMP1 have this bit
+
+ COMP_CTRL_BLKING Blking; /*see @ref COMP_CTRL_BLKING */
+
+ COMP_CTRL_HYST Hyst;
+
+ bool PolRev; // out polarity reverse
+
+ COMP_CTRL_OUTTRIG OutTrig;
+ COMP_CTRL_INPSEL InpSel;
+ COMP_CTRL_INMSEL InmSel;
+
+ bool En;
+
+ // filter
+ uint8_t SampWindow; // 5bit
+ uint8_t Thresh; // 5bit ,need > SampWindow/2
+ bool FilterEn;
+
+ // filter psc
+ uint16_t ClkPsc;
+} COMP_InitType;
+
+/** @addtogroup COMP_Exported_Functions
+ * @{
+ */
+
+void COMP_DeInit(void);
+void COMP_StructInit(COMP_InitType* COMP_InitStruct);
+void COMP_Init(COMPX COMPx, COMP_InitType* COMP_InitStruct);
+void COMP_Enable(COMPX COMPx, FunctionalState en);
+void COMP_SetInpSel(COMPX COMPx, COMP_CTRL_INPSEL VpSel);
+void COMP_SetInmSel(COMPX COMPx, COMP_CTRL_INMSEL VmSel);
+void COMP_SetOutTrig(COMPX COMPx, COMP_CTRL_OUTTRIG OutTrig);
+uint32_t COMP_GetIntSts(void); // return see @COMP_INTSTS_CMPIS
+void COMP_SetRefScl(uint8_t Vv2Trim, bool Vv2En, uint8_t Vv1Trim, bool Vv1En); // parma range see @COMP_VREFSCL
+FlagStatus COMP_GetOutStatus(COMPX COMPx);
+FlagStatus COMP_GetIntStsOneComp(COMPX COMPx);
+void COMP_SetLock(uint32_t Lock); // see @COMP_LOCK_CMPLK
+void COMP_SetIntEn(uint32_t IntEn); // see @COMP_INTEN_CMPIEN
+void COMP_CMP2XorOut(bool En);
+void COMP_StopOrLowpower32KClkSel(bool En);
+void COMP_WindowModeEn(bool En);
+void COMP_SetFilterPrescaler(COMPX COMPx , uint16_t FilPreVal);
+void COMP_SetFilterControl(COMPX COMPx , uint8_t FilEn, uint8_t TheresNum , uint8_t SampPW);
+void COMP_SetHyst(COMPX COMPx , COMP_CTRL_HYST HYST);
+void COMP_SetBlanking(COMPX COMPx , COMP_CTRL_BLKING BLK);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32L40X_ADC_H */
+/**
+ * @}
+ */
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_crc.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_crc.h
new file mode 100644
index 0000000000..d15a8ba0af
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_crc.h
@@ -0,0 +1,105 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_crc.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L40X_CRC_H__
+#define __N32L40X_CRC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l40x.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CRC
+ * @{
+ */
+
+/** @addtogroup CRC_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Exported_Functions
+ * @{
+ */
+
+void CRC32_ResetCrc(void);
+uint32_t CRC32_CalcCrc(uint32_t Data);
+uint32_t CRC32_CalcBufCrc(uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t CRC32_GetCrc(void);
+void CRC32_SetIDat(uint8_t IDValue);
+uint8_t CRC32_GetIDat(void);
+
+uint16_t CRC16_CalcBufCrc(uint8_t pBuffer[], uint32_t BufferLength);
+uint16_t CRC16_CalcCRC(uint8_t Data);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32L40X_CRC_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_dac.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_dac.h
new file mode 100644
index 0000000000..8954e6e347
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_dac.h
@@ -0,0 +1,293 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_dac.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L40X_DAC_H__
+#define __N32L40X_DAC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l40x.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DAC
+ * @{
+ */
+
+/** @addtogroup DAC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief DAC Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t Trigger; /*!< Specifies the external trigger for the selected DAC channel.
+ This parameter can be a value of @ref DAC_trigger_selection */
+
+ uint32_t WaveGen; /*!< Specifies whether DAC channel noise waves or triangle waves
+ are generated, or whether no wave is generated.
+ This parameter can be a value of @ref DAC_wave_generation */
+
+ uint32_t
+ LfsrUnMaskTriAmp; /*!< Specifies the LFSR mask for noise wave generation or
+ the maximum amplitude triangle generation for the DAC channel.
+ This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
+
+ uint32_t BufferOutput; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+ This parameter can be a value of @ref DAC_output_buffer */
+} DAC_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup DAC_trigger_selection
+ * @{
+ */
+
+#define DAC_TRG_NONE \
+ ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register \
+ has been loaded, and not by external trigger */
+#define DAC_TRG_T6_TRGO \
+ ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel \
+ */
+#define DAC_TRG_T8_TRGO \
+ ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel \
+ only in High-density devices*/
+#define DAC_TRG_T7_TRGO \
+ ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel \
+ */
+#define DAC_TRG_T5_TRGO \
+ ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel \
+ */
+#define DAC_TRG_T2_TRGO \
+ ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel \
+ */
+#define DAC_TRG_T4_TRGO \
+ ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel \
+ */
+#define DAC_TRG_EXT_IT9 \
+ ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRG_SOFTWARE ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER) \
+ (((TRIGGER) == DAC_TRG_NONE) || ((TRIGGER) == DAC_TRG_T6_TRGO) || ((TRIGGER) == DAC_TRG_T8_TRGO) \
+ || ((TRIGGER) == DAC_TRG_T7_TRGO) || ((TRIGGER) == DAC_TRG_T5_TRGO) || ((TRIGGER) == DAC_TRG_T2_TRGO) \
+ || ((TRIGGER) == DAC_TRG_T4_TRGO) || ((TRIGGER) == DAC_TRG_EXT_IT9) || ((TRIGGER) == DAC_TRG_SOFTWARE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_wave_generation
+ * @{
+ */
+
+#define DAC_WAVEGEN_NONE ((uint32_t)0x00000000)
+#define DAC_WAVEGEN_NOISE ((uint32_t)0x00000040)
+#define DAC_WAVEGEN_TRIANGLE ((uint32_t)0x00000080)
+#define IS_DAC_GENERATE_WAVE(WAVE) \
+ (((WAVE) == DAC_WAVEGEN_NONE) || ((WAVE) == DAC_WAVEGEN_NOISE) || ((WAVE) == DAC_WAVEGEN_TRIANGLE))
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_lfsrunmask_triangleamplitude
+ * @{
+ */
+
+#define DAC_UNMASK_LFSRBIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_UNMASK_LFSRBITS1_0 \
+ ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS2_0 \
+ ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS3_0 \
+ ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS4_0 \
+ ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS5_0 \
+ ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS6_0 \
+ ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS7_0 \
+ ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS8_0 \
+ ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS9_0 \
+ ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS10_0 \
+ ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_UNMASK_LFSRBITS11_0 \
+ ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TRIAMP_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TRIAMP_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
+#define DAC_TRIAMP_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
+#define DAC_TRIAMP_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
+#define DAC_TRIAMP_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
+#define DAC_TRIAMP_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
+#define DAC_TRIAMP_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
+#define DAC_TRIAMP_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
+#define DAC_TRIAMP_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
+#define DAC_TRIAMP_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TRIAMP_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TRIAMP_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) \
+ (((VALUE) == DAC_UNMASK_LFSRBIT0) || ((VALUE) == DAC_UNMASK_LFSRBITS1_0) || ((VALUE) == DAC_UNMASK_LFSRBITS2_0) \
+ || ((VALUE) == DAC_UNMASK_LFSRBITS3_0) || ((VALUE) == DAC_UNMASK_LFSRBITS4_0) \
+ || ((VALUE) == DAC_UNMASK_LFSRBITS5_0) || ((VALUE) == DAC_UNMASK_LFSRBITS6_0) \
+ || ((VALUE) == DAC_UNMASK_LFSRBITS7_0) || ((VALUE) == DAC_UNMASK_LFSRBITS8_0) \
+ || ((VALUE) == DAC_UNMASK_LFSRBITS9_0) || ((VALUE) == DAC_UNMASK_LFSRBITS10_0) \
+ || ((VALUE) == DAC_UNMASK_LFSRBITS11_0) || ((VALUE) == DAC_TRIAMP_1) || ((VALUE) == DAC_TRIAMP_3) \
+ || ((VALUE) == DAC_TRIAMP_7) || ((VALUE) == DAC_TRIAMP_15) || ((VALUE) == DAC_TRIAMP_31) \
+ || ((VALUE) == DAC_TRIAMP_63) || ((VALUE) == DAC_TRIAMP_127) || ((VALUE) == DAC_TRIAMP_255) \
+ || ((VALUE) == DAC_TRIAMP_511) || ((VALUE) == DAC_TRIAMP_1023) || ((VALUE) == DAC_TRIAMP_2047) \
+ || ((VALUE) == DAC_TRIAMP_4095))
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_output_buffer
+ * @{
+ */
+
+#define DAC_BUFFOUTPUT_ENABLE ((uint32_t)0x00000002)
+#define DAC_BUFFOUTPUT_DISABLE ((uint32_t)0x00000000)
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_BUFFOUTPUT_ENABLE) || ((STATE) == DAC_BUFFOUTPUT_DISABLE))
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_data_alignment
+ * @{
+ */
+
+#define DAC_ALIGN_R_12BIT ((uint32_t)0x00000000)
+#define DAC_ALIGN_L_12BIT ((uint32_t)0x00000004)
+#define DAC_ALIGN_R_8BIT ((uint32_t)0x00000008)
+#define IS_DAC_ALIGN(ALIGN) \
+ (((ALIGN) == DAC_ALIGN_R_12BIT) || ((ALIGN) == DAC_ALIGN_L_12BIT) || ((ALIGN) == DAC_ALIGN_R_8BIT))
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_wave_generation
+ * @{
+ */
+
+#define DAC_WAVE_NOISE ((uint32_t)0x00000040)
+#define DAC_WAVE_TRIANGLE ((uint32_t)0x00000080)
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NOISE) || ((WAVE) == DAC_WAVE_TRIANGLE))
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_data
+ * @{
+ */
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Functions
+ * @{
+ */
+
+void DAC_DeInit(void);
+void DAC_Init(DAC_InitType* DAC_InitStruct);
+void DAC_ClearStruct(DAC_InitType* DAC_InitStruct);
+void DAC_Enable(FunctionalState Cmd);
+
+void DAC_DmaEnable(FunctionalState Cmd);
+void DAC_SoftTrgEnable(FunctionalState Cmd);
+void DAC_SoftwareTrgEnable(FunctionalState Cmd);
+void DAC_WaveGenerationEnable(uint32_t DAC_Wave, FunctionalState Cmd);
+void DAC_SetChData(uint32_t DAC_Align, uint16_t Data);
+uint16_t DAC_GetOutputDataVal(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32L40X_DAC_H__ */
+ /**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_dbg.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_dbg.h
new file mode 100644
index 0000000000..2310504317
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_dbg.h
@@ -0,0 +1,124 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_dbg.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L40X_DBG_H__
+#define __N32L40X_DBG_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l40x.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DBG
+ * @{
+ */
+
+/** @addtogroup DBGMCU_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Exported_Constants
+ * @{
+ */
+
+#define DBG_SLEEP ((uint32_t)0x00000001)
+#define DBG_STOP ((uint32_t)0x00000002)
+#define DBG_STDBY ((uint32_t)0x00000004)
+#define DBG_IWDG_STOP ((uint32_t)0x00000100)
+#define DBG_WWDG_STOP ((uint32_t)0x00000200)
+#define DBG_TIM1_STOP ((uint32_t)0x00000400)
+#define DBG_TIM2_STOP ((uint32_t)0x00000800)
+#define DBG_TIM3_STOP ((uint32_t)0x00001000)
+#define DBG_TIM4_STOP ((uint32_t)0x00002000)
+#define DBG_CAN_STOP ((uint32_t)0x00004000)
+#define DBG_I2C1SMBUS_TIMEOUT ((uint32_t)0x00008000)
+#define DBG_I2C2SMBUS_TIMEOUT ((uint32_t)0x00010000)
+#define DBG_TIM8_STOP ((uint32_t)0x00020000)
+#define DBG_TIM5_STOP ((uint32_t)0x00040000)
+#define DBG_TIM6_STOP ((uint32_t)0x00080000)
+#define DBG_TIM7_STOP ((uint32_t)0x00100000)
+#define DBG_TIM9_STOP ((uint32_t)0x00200000)
+
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH)&0xFFC000F8) == 0x00) && ((PERIPH) != 0x00))
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Exported_Functions
+ * @{
+ */
+
+void GetUCID(uint8_t *UCIDbuf);
+void GetUID(uint8_t *UIDbuf);
+void GetDBGMCU_ID(uint8_t *DBGMCU_IDbuf);
+uint32_t DBG_GetRevNum(void);
+uint32_t DBG_GetDevNum(void);
+void DBG_ConfigPeriph(uint32_t DBG_Periph, FunctionalState Cmd);
+
+uint32_t DBG_GetFlashSize(void);
+uint32_t DBG_GetSramSize(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32L40X_DBG_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_dma.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_dma.h
new file mode 100644
index 0000000000..9f82edb254
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_dma.h
@@ -0,0 +1,469 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_dma.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L40X_DMA_H__
+#define __N32L40X_DMA_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l40x.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @{
+ */
+
+/** @addtogroup DMA_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief DMA Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t PeriphAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
+
+ uint32_t MemAddr; /*!< Specifies the memory base address for DMAy Channelx. */
+
+ uint32_t Direction; /*!< Specifies if the peripheral is the source or destination.
+ This parameter can be a value of @ref DMA_data_transfer_direction */
+
+ uint32_t BufSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
+ The data unit is equal to the configuration set in PeriphDataSize
+ or MemDataSize members depending in the transfer direction. */
+
+ uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register is incremented or not.
+ This parameter can be a value of @ref DMA_peripheral_incremented_mode */
+
+ uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
+ This parameter can be a value of @ref DMA_memory_incremented_mode */
+
+ uint32_t PeriphDataSize; /*!< Specifies the Peripheral data width.
+ This parameter can be a value of @ref DMA_peripheral_data_size */
+
+ uint32_t MemDataSize; /*!< Specifies the Memory data width.
+ This parameter can be a value of @ref DMA_memory_data_size */
+
+ uint32_t CircularMode; /*!< Specifies the operation mode of the DMAy Channelx.
+ This parameter can be a value of @ref DMA_circular_normal_mode.
+ @note: The circular buffer mode cannot be used if the memory-to-memory
+ data transfer is configured on the selected Channel */
+
+ uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
+ This parameter can be a value of @ref DMA_priority_level */
+
+ uint32_t Mem2Mem; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
+ This parameter can be a value of @ref DMA_memory_to_memory */
+} DMA_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Constants
+ * @{
+ */
+
+#define IS_DMA_ALL_PERIPH(PERIPH) \
+ (((PERIPH) == DMA_CH1) || ((PERIPH) == DMA_CH2) || ((PERIPH) == DMA_CH3) || ((PERIPH) == DMA_CH4) \
+ || ((PERIPH) == DMA_CH5) || ((PERIPH) == DMA_CH6) || ((PERIPH) == DMA_CH7) || ((PERIPH) == DMA_CH8))
+
+/** @addtogroup DMA_data_transfer_direction
+ * @{
+ */
+
+#define DMA_DIR_PERIPH_DST ((uint32_t)0x00000010)
+#define DMA_DIR_PERIPH_SRC ((uint32_t)0x00000000)
+#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PERIPH_DST) || ((DIR) == DMA_DIR_PERIPH_SRC))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_peripheral_incremented_mode
+ * @{
+ */
+
+#define DMA_PERIPH_INC_ENABLE ((uint32_t)0x00000040)
+#define DMA_PERIPH_INC_DISABLE ((uint32_t)0x00000000)
+#define IS_DMA_PERIPH_INC_STATE(STATE) (((STATE) == DMA_PERIPH_INC_ENABLE) || ((STATE) == DMA_PERIPH_INC_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_memory_incremented_mode
+ * @{
+ */
+
+#define DMA_MEM_INC_ENABLE ((uint32_t)0x00000080)
+#define DMA_MEM_INC_DISABLE ((uint32_t)0x00000000)
+#define IS_DMA_MEM_INC_STATE(STATE) (((STATE) == DMA_MEM_INC_ENABLE) || ((STATE) == DMA_MEM_INC_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_peripheral_data_size
+ * @{
+ */
+
+#define DMA_PERIPH_DATA_SIZE_BYTE ((uint32_t)0x00000000)
+#define DMA_PERIPH_DATA_SIZE_HALFWORD ((uint32_t)0x00000100)
+#define DMA_PERIPH_DATA_SIZE_WORD ((uint32_t)0x00000200)
+#define IS_DMA_PERIPH_DATA_SIZE(SIZE) \
+ (((SIZE) == DMA_PERIPH_DATA_SIZE_BYTE) || ((SIZE) == DMA_PERIPH_DATA_SIZE_HALFWORD) \
+ || ((SIZE) == DMA_PERIPH_DATA_SIZE_WORD))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_memory_data_size
+ * @{
+ */
+
+#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
+#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
+#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) \
+ (((SIZE) == DMA_MemoryDataSize_Byte) || ((SIZE) == DMA_MemoryDataSize_HalfWord) \
+ || ((SIZE) == DMA_MemoryDataSize_Word))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_circular_normal_mode
+ * @{
+ */
+
+#define DMA_MODE_CIRCULAR ((uint32_t)0x00000020)
+#define DMA_MODE_NORMAL ((uint32_t)0x00000000)
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_MODE_CIRCULAR) || ((MODE) == DMA_MODE_NORMAL))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_priority_level
+ * @{
+ */
+
+#define DMA_PRIORITY_VERY_HIGH ((uint32_t)0x00003000)
+#define DMA_PRIORITY_HIGH ((uint32_t)0x00002000)
+#define DMA_PRIORITY_MEDIUM ((uint32_t)0x00001000)
+#define DMA_PRIORITY_LOW ((uint32_t)0x00000000)
+#define IS_DMA_PRIORITY(PRIORITY) \
+ (((PRIORITY) == DMA_PRIORITY_VERY_HIGH) || ((PRIORITY) == DMA_PRIORITY_HIGH) \
+ || ((PRIORITY) == DMA_PRIORITY_MEDIUM) || ((PRIORITY) == DMA_PRIORITY_LOW))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_memory_to_memory
+ * @{
+ */
+
+#define DMA_M2M_ENABLE ((uint32_t)0x00004000)
+#define DMA_M2M_DISABLE ((uint32_t)0x00000000)
+#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_ENABLE) || ((STATE) == DMA_M2M_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_interrupts_definition
+ * @{
+ */
+
+#define DMA_INT_TXC ((uint32_t)0x00000002)
+#define DMA_INT_HTX ((uint32_t)0x00000004)
+#define DMA_INT_ERR ((uint32_t)0x00000008)
+#define IS_DMA_CONFIG_INT(IT) ((((IT)&0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
+
+#define DMA_INT_GLB1 ((uint32_t)0x00000001)
+#define DMA_INT_TXC1 ((uint32_t)0x00000002)
+#define DMA_INT_HTX1 ((uint32_t)0x00000004)
+#define DMA_INT_ERR1 ((uint32_t)0x00000008)
+#define DMA_INT_GLB2 ((uint32_t)0x00000010)
+#define DMA_INT_TXC2 ((uint32_t)0x00000020)
+#define DMA_INT_HTX2 ((uint32_t)0x00000040)
+#define DMA_INT_ERR2 ((uint32_t)0x00000080)
+#define DMA_INT_GLB3 ((uint32_t)0x00000100)
+#define DMA_INT_TXC3 ((uint32_t)0x00000200)
+#define DMA_INT_HTX3 ((uint32_t)0x00000400)
+#define DMA_INT_ERR3 ((uint32_t)0x00000800)
+#define DMA_INT_GLB4 ((uint32_t)0x00001000)
+#define DMA_INT_TXC4 ((uint32_t)0x00002000)
+#define DMA_INT_HTX4 ((uint32_t)0x00004000)
+#define DMA_INT_ERR4 ((uint32_t)0x00008000)
+#define DMA_INT_GLB5 ((uint32_t)0x00010000)
+#define DMA_INT_TXC5 ((uint32_t)0x00020000)
+#define DMA_INT_HTX5 ((uint32_t)0x00040000)
+#define DMA_INT_ERR5 ((uint32_t)0x00080000)
+#define DMA_INT_GLB6 ((uint32_t)0x00100000)
+#define DMA_INT_TXC6 ((uint32_t)0x00200000)
+#define DMA_INT_HTX6 ((uint32_t)0x00400000)
+#define DMA_INT_ERR6 ((uint32_t)0x00800000)
+#define DMA_INT_GLB7 ((uint32_t)0x01000000)
+#define DMA_INT_TXC7 ((uint32_t)0x02000000)
+#define DMA_INT_HTX7 ((uint32_t)0x04000000)
+#define DMA_INT_ERR7 ((uint32_t)0x08000000)
+#define DMA_INT_GLB8 ((uint32_t)0x10000000)
+#define DMA_INT_TXC8 ((uint32_t)0x20000000)
+#define DMA_INT_HTX8 ((uint32_t)0x40000000)
+#define DMA_INT_ERR8 ((uint32_t)0x80000000)
+
+
+#define IS_DMA_CLR_INT(IT) ((IT) != 0x00)
+
+#define IS_DMA_GET_IT(IT) \
+ (((IT) == DMA_INT_GLB1) || ((IT) == DMA_INT_TXC1) || ((IT) == DMA_INT_HTX1) || ((IT) == DMA_INT_ERR1) \
+ || ((IT) == DMA_INT_GLB2) || ((IT) == DMA_INT_TXC2) || ((IT) == DMA_INT_HTX2) || ((IT) == DMA_INT_ERR2) \
+ || ((IT) == DMA_INT_GLB3) || ((IT) == DMA_INT_TXC3) || ((IT) == DMA_INT_HTX3) || ((IT) == DMA_INT_ERR3) \
+ || ((IT) == DMA_INT_GLB4) || ((IT) == DMA_INT_TXC4) || ((IT) == DMA_INT_HTX4) || ((IT) == DMA_INT_ERR4) \
+ || ((IT) == DMA_INT_GLB5) || ((IT) == DMA_INT_TXC5) || ((IT) == DMA_INT_HTX5) || ((IT) == DMA_INT_ERR5) \
+ || ((IT) == DMA_INT_GLB6) || ((IT) == DMA_INT_TXC6) || ((IT) == DMA_INT_HTX6) || ((IT) == DMA_INT_ERR6) \
+ || ((IT) == DMA_INT_GLB7) || ((IT) == DMA_INT_TXC7) || ((IT) == DMA_INT_HTX7) || ((IT) == DMA_INT_ERR7) \
+ || ((IT) == DMA_INT_GLB8) || ((IT) == DMA_INT_TXC8) || ((IT) == DMA_INT_HTX8) || ((IT) == DMA_INT_ERR8))
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_flags_definition
+ * @{
+ */
+#define DMA_FLAG_GL1 ((uint32_t)0x00000001)
+#define DMA_FLAG_TC1 ((uint32_t)0x00000002)
+#define DMA_FLAG_HT1 ((uint32_t)0x00000004)
+#define DMA_FLAG_TE1 ((uint32_t)0x00000008)
+#define DMA_FLAG_GL2 ((uint32_t)0x00000010)
+#define DMA_FLAG_TC2 ((uint32_t)0x00000020)
+#define DMA_FLAG_HT2 ((uint32_t)0x00000040)
+#define DMA_FLAG_TE2 ((uint32_t)0x00000080)
+#define DMA_FLAG_GL3 ((uint32_t)0x00000100)
+#define DMA_FLAG_TC3 ((uint32_t)0x00000200)
+#define DMA_FLAG_HT3 ((uint32_t)0x00000400)
+#define DMA_FLAG_TE3 ((uint32_t)0x00000800)
+#define DMA_FLAG_GL4 ((uint32_t)0x00001000)
+#define DMA_FLAG_TC4 ((uint32_t)0x00002000)
+#define DMA_FLAG_HT4 ((uint32_t)0x00004000)
+#define DMA_FLAG_TE4 ((uint32_t)0x00008000)
+#define DMA_FLAG_GL5 ((uint32_t)0x00010000)
+#define DMA_FLAG_TC5 ((uint32_t)0x00020000)
+#define DMA_FLAG_HT5 ((uint32_t)0x00040000)
+#define DMA_FLAG_TE5 ((uint32_t)0x00080000)
+#define DMA_FLAG_GL6 ((uint32_t)0x00100000)
+#define DMA_FLAG_TC6 ((uint32_t)0x00200000)
+#define DMA_FLAG_HT6 ((uint32_t)0x00400000)
+#define DMA_FLAG_TE6 ((uint32_t)0x00800000)
+#define DMA_FLAG_GL7 ((uint32_t)0x01000000)
+#define DMA_FLAG_TC7 ((uint32_t)0x02000000)
+#define DMA_FLAG_HT7 ((uint32_t)0x04000000)
+#define DMA_FLAG_TE7 ((uint32_t)0x08000000)
+#define DMA_FLAG_GL8 ((uint32_t)0x10000000)
+#define DMA_FLAG_TC8 ((uint32_t)0x20000000)
+#define DMA_FLAG_HT8 ((uint32_t)0x40000000)
+#define DMA_FLAG_TE8 ((uint32_t)0x80000000)
+
+#define IS_DMA_CLEAR_FLAG(FLAG) ((FLAG) != 0x00)
+
+#define IS_DMA_GET_FLAG(FLAG) \
+ (((FLAG) == DMA_FLAG_GL1) || ((FLAG) == DMA_FLAG_TC1) || ((FLAG) == DMA_FLAG_HT1) || ((FLAG) == DMA_FLAG_TE1) \
+ || ((FLAG) == DMA_FLAG_GL2) || ((FLAG) == DMA_FLAG_TC2) || ((FLAG) == DMA_FLAG_HT2) \
+ || ((FLAG) == DMA_FLAG_TE2) || ((FLAG) == DMA_FLAG_GL3) || ((FLAG) == DMA_FLAG_TC3) \
+ || ((FLAG) == DMA_FLAG_HT3) || ((FLAG) == DMA_FLAG_TE3) || ((FLAG) == DMA_FLAG_GL4) \
+ || ((FLAG) == DMA_FLAG_TC4) || ((FLAG) == DMA_FLAG_HT4) || ((FLAG) == DMA_FLAG_TE4) \
+ || ((FLAG) == DMA_FLAG_GL5) || ((FLAG) == DMA_FLAG_TC5) || ((FLAG) == DMA_FLAG_HT5) \
+ || ((FLAG) == DMA_FLAG_TE5) || ((FLAG) == DMA_FLAG_GL6) || ((FLAG) == DMA_FLAG_TC6) \
+ || ((FLAG) == DMA_FLAG_HT6) || ((FLAG) == DMA_FLAG_TE6) || ((FLAG) == DMA_FLAG_GL7) \
+ || ((FLAG) == DMA_FLAG_TC7) || ((FLAG) == DMA_FLAG_HT7) || ((FLAG) == DMA_FLAG_TE7) \
+ || ((FLAG) == DMA_FLAG_GL8) || ((FLAG) == DMA_FLAG_TC8) || ((FLAG) == DMA_FLAG_HT8) \
+ || ((FLAG) == DMA_FLAG_TE8))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Buffer_Size
+ * @{
+ */
+
+#define IS_DMA_BUF_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_remap_request_definition
+ * @{
+ */
+#define DMA_REMAP_ADC1 ((uint32_t)0x00000000)
+#define DMA_REMAP_USART1_TX ((uint32_t)0x00000001)
+#define DMA_REMAP_USART1_RX ((uint32_t)0x00000002)
+#define DMA_REMAP_USART2_TX ((uint32_t)0x00000003)
+#define DMA_REMAP_USART2_RX ((uint32_t)0x00000004)
+#define DMA_REMAP_USART3_TX ((uint32_t)0x00000005)
+#define DMA_REMAP_USART3_RX ((uint32_t)0x00000006)
+#define DMA_REMAP_UART4_TX ((uint32_t)0x00000007)
+#define DMA_REMAP_UART4_RX ((uint32_t)0x00000008)
+#define DMA_REMAP_UART5_TX ((uint32_t)0x00000009)
+#define DMA_REMAP_UART5_RX ((uint32_t)0x0000000A)
+#define DMA_REMAP_LPUART_TX ((uint32_t)0x0000000B)
+#define DMA_REMAP_LPUART_RX ((uint32_t)0x0000000C)
+#define DMA_REMAP_SPI1_TX ((uint32_t)0x0000000D)
+#define DMA_REMAP_SPI1_RX ((uint32_t)0x0000000E)
+#define DMA_REMAP_SPI2_TX ((uint32_t)0x0000000F)
+#define DMA_REMAP_SPI2_RX ((uint32_t)0x00000010)
+#define DMA_REMAP_I2C1_TX ((uint32_t)0x00000011)
+#define DMA_REMAP_I2C1_RX ((uint32_t)0x00000012)
+#define DMA_REMAP_I2C2_TX ((uint32_t)0x00000013)
+#define DMA_REMAP_I2C2_RX ((uint32_t)0x00000014)
+#define DMA_REMAP_DAC1 ((uint32_t)0x00000015)
+#define DMA_REMAP_TIM1_CH1 ((uint32_t)0x00000016)
+#define DMA_REMAP_TIM1_CH2 ((uint32_t)0x00000017)
+#define DMA_REMAP_TIM1_CH3 ((uint32_t)0x00000018)
+#define DMA_REMAP_TIM1_CH4 ((uint32_t)0x00000019)
+#define DMA_REMAP_TIM1_COM ((uint32_t)0x0000001A)
+#define DMA_REMAP_TIM1_UP ((uint32_t)0x0000001B)
+#define DMA_REMAP_TIM1_TRIG ((uint32_t)0x0000001C)
+#define DMA_REMAP_TIM2_CH1 ((uint32_t)0x0000001D)
+#define DMA_REMAP_TIM2_CH2 ((uint32_t)0x0000001E)
+#define DMA_REMAP_TIM2_CH3 ((uint32_t)0x0000001F)
+#define DMA_REMAP_TIM2_CH4 ((uint32_t)0x00000020)
+#define DMA_REMAP_TIM2_UP ((uint32_t)0x00000021)
+#define DMA_REMAP_TIM3_CH1 ((uint32_t)0x00000022)
+#define DMA_REMAP_TIM3_CH3 ((uint32_t)0x00000023)
+#define DMA_REMAP_TIM3_CH4 ((uint32_t)0x00000024)
+#define DMA_REMAP_TIM3_UP ((uint32_t)0x00000025)
+#define DMA_REMAP_TIM3_TRIG ((uint32_t)0x00000026)
+#define DMA_REMAP_TIM4_CH1 ((uint32_t)0x00000027)
+#define DMA_REMAP_TIM4_CH2 ((uint32_t)0x00000028)
+#define DMA_REMAP_TIM4_CH3 ((uint32_t)0x00000029)
+#define DMA_REMAP_TIM4_UP ((uint32_t)0x0000002A)
+#define DMA_REMAP_TIM5_CH1 ((uint32_t)0x0000002B)
+#define DMA_REMAP_TIM5_CH2 ((uint32_t)0x0000002C)
+#define DMA_REMAP_TIM5_CH3 ((uint32_t)0x0000002D)
+#define DMA_REMAP_TIM5_CH4 ((uint32_t)0x0000002E)
+#define DMA_REMAP_TIM5_UP ((uint32_t)0x0000002F)
+#define DMA_REMAP_TIM5_TRIG ((uint32_t)0x00000030)
+#define DMA_REMAP_TIM6_UP ((uint32_t)0x00000031)
+#define DMA_REMAP_TIM7_UP ((uint32_t)0x00000032)
+#define DMA_REMAP_TIM8_CH1 ((uint32_t)0x00000033)
+#define DMA_REMAP_TIM8_CH2 ((uint32_t)0x00000034)
+#define DMA_REMAP_TIM8_CH3 ((uint32_t)0x00000035)
+#define DMA_REMAP_TIM8_CH4 ((uint32_t)0x00000036)
+#define DMA_REMAP_TIM8_COM ((uint32_t)0x00000037)
+#define DMA_REMAP_TIM8_UP ((uint32_t)0x00000038)
+#define DMA_REMAP_TIM8_TRIG ((uint32_t)0x00000039)
+#define DMA_REMAP_TIM9_CH1 ((uint32_t)0x0000003A)
+#define DMA_REMAP_TIM9_TRIG ((uint32_t)0x0000003B)
+#define DMA_REMAP_TIM9_CH3 ((uint32_t)0x0000003C)
+#define DMA_REMAP_TIM9_CH4 ((uint32_t)0x0000003D)
+#define DMA_REMAP_TIM9_UP ((uint32_t)0x0000003E)
+
+
+#define IS_DMA_REMAP(FLAG) \
+ (((FLAG) == DMA_REMAP_ADC1) || ((FLAG) == DMA_REMAP_USART1_TX) || ((FLAG) == DMA_REMAP_USART1_RX) \
+ || ((FLAG) == DMA_REMAP_USART2_TX) || ((FLAG) == DMA_REMAP_USART2_RX) || ((FLAG) == DMA_REMAP_USART3_TX) \
+ || ((FLAG) == DMA_REMAP_USART3_RX) || ((FLAG) == DMA_REMAP_UART4_TX) || ((FLAG) == DMA_REMAP_UART4_RX) \
+ || ((FLAG) == DMA_REMAP_UART5_TX) || ((FLAG) == DMA_REMAP_UART5_RX) || ((FLAG) == DMA_REMAP_LPUART_TX) \
+ || ((FLAG) == DMA_REMAP_LPUART_RX) || ((FLAG) == DMA_REMAP_SPI1_TX) || ((FLAG) == DMA_REMAP_SPI1_RX) \
+ || ((FLAG) == DMA_REMAP_SPI2_TX) || ((FLAG) == DMA_REMAP_SPI2_RX) || ((FLAG) == DMA_REMAP_I2C1_TX) \
+ || ((FLAG) == DMA_REMAP_I2C1_RX) || ((FLAG) == DMA_REMAP_I2C2_TX) || ((FLAG) == DMA_REMAP_I2C2_RX) \
+ || ((FLAG) == DMA_REMAP_DAC1) || ((FLAG) == DMA_REMAP_TIM1_CH1) || ((FLAG) == DMA_REMAP_TIM1_CH2) \
+ || ((FLAG) == DMA_REMAP_TIM1_CH3) || ((FLAG) == DMA_REMAP_TIM1_CH4) || ((FLAG) == DMA_REMAP_TIM1_COM) \
+ || ((FLAG) == DMA_REMAP_TIM1_UP) || ((FLAG) == DMA_REMAP_TIM1_TRIG)|| ((FLAG) == DMA_REMAP_TIM2_CH1) \
+ || ((FLAG) == DMA_REMAP_TIM2_CH2) || ((FLAG) == DMA_REMAP_TIM2_CH3) || ((FLAG) == DMA_REMAP_TIM2_CH4) \
+ || ((FLAG) == DMA_REMAP_TIM2_UP) || ((FLAG) == DMA_REMAP_TIM3_CH1) || ((FLAG) == DMA_REMAP_TIM3_CH3) \
+ || ((FLAG) == DMA_REMAP_TIM3_CH4) || ((FLAG) == DMA_REMAP_TIM3_UP) || ((FLAG) == DMA_REMAP_TIM3_TRIG) \
+ || ((FLAG) == DMA_REMAP_TIM4_CH1) || ((FLAG) == DMA_REMAP_TIM4_CH2) || ((FLAG) == DMA_REMAP_TIM4_CH3) \
+ || ((FLAG) == DMA_REMAP_TIM4_UP) || ((FLAG) == DMA_REMAP_TIM5_CH1) || ((FLAG) == DMA_REMAP_TIM5_CH2) \
+ || ((FLAG) == DMA_REMAP_TIM5_CH3) || ((FLAG) == DMA_REMAP_TIM5_CH4) || ((FLAG) == DMA_REMAP_TIM5_UP) \
+ || ((FLAG) == DMA_REMAP_TIM5_TRIG)|| ((FLAG) == DMA_REMAP_TIM6_UP) || ((FLAG) == DMA_REMAP_TIM7_UP) \
+ || ((FLAG) == DMA_REMAP_TIM8_CH1) || ((FLAG) == DMA_REMAP_TIM8_CH2) || ((FLAG) == DMA_REMAP_TIM8_CH3) \
+ || ((FLAG) == DMA_REMAP_TIM8_CH4) || ((FLAG) == DMA_REMAP_TIM8_COM) || ((FLAG) == DMA_REMAP_TIM8_UP) \
+ || ((FLAG) == DMA_REMAP_TIM8_TRIG)|| ((FLAG) == DMA_REMAP_TIM9_CH1) || ((FLAG) == DMA_REMAP_TIM9_TRIG) \
+ || ((FLAG) == DMA_REMAP_TIM9_CH3) || ((FLAG) == DMA_REMAP_TIM9_CH4) || ((FLAG) == DMA_REMAP_TIM9_UP))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Functions
+ * @{
+ */
+
+void DMA_DeInit(DMA_ChannelType* DMAChx);
+void DMA_Init(DMA_ChannelType* DMAChx, DMA_InitType* DMA_InitParam);
+void DMA_StructInit(DMA_InitType* DMA_InitParam);
+void DMA_EnableChannel(DMA_ChannelType* DMAChx, FunctionalState Cmd);
+void DMA_ConfigInt(DMA_ChannelType* DMAChx, uint32_t DMAInt, FunctionalState Cmd);
+void DMA_SetCurrDataCounter(DMA_ChannelType* DMAChx, uint16_t DataNumber);
+uint16_t DMA_GetCurrDataCounter(DMA_ChannelType* DMAChx);
+FlagStatus DMA_GetFlagStatus(uint32_t DMAFlag, DMA_Module* DMAy);
+void DMA_ClearFlag(uint32_t DMAFlag, DMA_Module* DMAy);
+INTStatus DMA_GetIntStatus(uint32_t DMA_IT, DMA_Module* DMAy);
+void DMA_ClrIntPendingBit(uint32_t DMA_IT, DMA_Module* DMAy);
+void DMA_RequestRemap(uint32_t DMA_REMAP, DMA_Module* DMAy, DMA_ChannelType* DMAChx, FunctionalState Cmd);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32L40X_DMA_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_exti.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_exti.h
new file mode 100644
index 0000000000..aff5681cba
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_exti.h
@@ -0,0 +1,234 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_exti.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L40X_EXTI_H__
+#define __N32L40X_EXTI_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l40x.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup EXTI
+ * @{
+ */
+
+/** @addtogroup EXTI_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief EXTI mode enumeration
+ */
+
+typedef enum
+{
+ EXTI_Mode_Interrupt = 0x00,
+ EXTI_Mode_Event = 0x04
+} EXTI_ModeType;
+
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
+
+/**
+ * @brief EXTI Trigger enumeration
+ */
+
+typedef enum
+{
+ EXTI_Trigger_Rising = 0x08,
+ EXTI_Trigger_Falling = 0x0C,
+ EXTI_Trigger_Rising_Falling = 0x10
+} EXTI_TriggerType;
+
+#define IS_EXTI_TRIGGER(TRIGGER) \
+ (((TRIGGER) == EXTI_Trigger_Rising) || ((TRIGGER) == EXTI_Trigger_Falling) \
+ || ((TRIGGER) == EXTI_Trigger_Rising_Falling))
+/**
+ * @brief EXTI Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
+ This parameter can be any combination of @ref EXTI_Lines */
+
+ EXTI_ModeType EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
+ This parameter can be a value of @ref EXTI_ModeType */
+
+ EXTI_TriggerType EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+ This parameter can be a value of @ref EXTI_ModeType */
+
+ FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
+ This parameter can be set either to ENABLE or DISABLE */
+} EXTI_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup EXTI_Lines
+ * @{
+ */
+
+#define EXTI_LINE0 ((uint32_t)0x00001) /*!< External interrupt line 0 */
+#define EXTI_LINE1 ((uint32_t)0x00002) /*!< External interrupt line 1 */
+#define EXTI_LINE2 ((uint32_t)0x00004) /*!< External interrupt line 2 */
+#define EXTI_LINE3 ((uint32_t)0x00008) /*!< External interrupt line 3 */
+#define EXTI_LINE4 ((uint32_t)0x00010) /*!< External interrupt line 4 */
+#define EXTI_LINE5 ((uint32_t)0x00020) /*!< External interrupt line 5 */
+#define EXTI_LINE6 ((uint32_t)0x00040) /*!< External interrupt line 6 */
+#define EXTI_LINE7 ((uint32_t)0x00080) /*!< External interrupt line 7 */
+#define EXTI_LINE8 ((uint32_t)0x00100) /*!< External interrupt line 8 */
+#define EXTI_LINE9 ((uint32_t)0x00200) /*!< External interrupt line 9 */
+#define EXTI_LINE10 ((uint32_t)0x00400) /*!< External interrupt line 10 */
+#define EXTI_LINE11 ((uint32_t)0x00800) /*!< External interrupt line 11 */
+#define EXTI_LINE12 ((uint32_t)0x01000) /*!< External interrupt line 12 */
+#define EXTI_LINE13 ((uint32_t)0x02000) /*!< External interrupt line 13 */
+#define EXTI_LINE14 ((uint32_t)0x04000) /*!< External interrupt line 14 */
+#define EXTI_LINE15 ((uint32_t)0x08000) /*!< External interrupt line 15 */
+#define EXTI_LINE16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */
+#define EXTI_LINE17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the USB Device/USB OTG FS Wakeup from suspend event */
+#define EXTI_LINE18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the RTC Alarm event */
+#define EXTI_LINE19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the RTC Time stamp event */
+#define EXTI_LINE20 ((uint32_t)0x100000) /*!< External interrupt line 20 Connected to the RTC Wakeup event */
+#define EXTI_LINE21 ((uint32_t)0x200000) /*!< External interrupt line 21 Connected to the COMP1 Global interrupt */
+#define EXTI_LINE22 ((uint32_t)0x400000) /*!< External interrupt line 22 Connected to the COMP2 Global interrupt */
+#define EXTI_LINE23 ((uint32_t)0x800000) /*!< External interrupt line 23 Connected to the LPUART Global interrupt */
+#define EXTI_LINE24 ((uint32_t)0x1000000) /*!< External interrupt line 24 Connected to the LPTIM Global interrupt */
+#define EXTI_LINE25 ((uint32_t)0x2000000) /*!< External interrupt line 25 Connected to the TSC Global interrupt */
+#define EXTI_LINE26 ((uint32_t)0x4000000) /*!< External interrupt line 26 Connected to the LCD Global interrupt */
+
+
+
+
+
+
+
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xF0000000) == 0x00) && ((LINE) != (uint16_t)0x00))
+#define IS_GET_EXTI_LINE(LINE) \
+ (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) \
+ || ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) \
+ || ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) \
+ || ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) \
+ || ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) \
+ || ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) \
+ || ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || ((LINE) == EXTI_LINE26))
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_TSSEL_Line
+ * @{
+ */
+#define EXTI_TSSEL_LINE_MASK ((uint32_t)0x00000)
+#define EXTI_TSSEL_LINE0 ((uint32_t)0x00000) /*!< External interrupt line 0 */
+#define EXTI_TSSEL_LINE1 ((uint32_t)0x00001) /*!< External interrupt line 1 */
+#define EXTI_TSSEL_LINE2 ((uint32_t)0x00002) /*!< External interrupt line 2 */
+#define EXTI_TSSEL_LINE3 ((uint32_t)0x00003) /*!< External interrupt line 3 */
+#define EXTI_TSSEL_LINE4 ((uint32_t)0x00004) /*!< External interrupt line 4 */
+#define EXTI_TSSEL_LINE5 ((uint32_t)0x00005) /*!< External interrupt line 5 */
+#define EXTI_TSSEL_LINE6 ((uint32_t)0x00006) /*!< External interrupt line 6 */
+#define EXTI_TSSEL_LINE7 ((uint32_t)0x00007) /*!< External interrupt line 7 */
+#define EXTI_TSSEL_LINE8 ((uint32_t)0x00008) /*!< External interrupt line 8 */
+#define EXTI_TSSEL_LINE9 ((uint32_t)0x00009) /*!< External interrupt line 9 */
+#define EXTI_TSSEL_LINE10 ((uint32_t)0x0000A) /*!< External interrupt line 10 */
+#define EXTI_TSSEL_LINE11 ((uint32_t)0x0000B) /*!< External interrupt line 11 */
+#define EXTI_TSSEL_LINE12 ((uint32_t)0x0000C) /*!< External interrupt line 12 */
+#define EXTI_TSSEL_LINE13 ((uint32_t)0x0000D) /*!< External interrupt line 13 */
+#define EXTI_TSSEL_LINE14 ((uint32_t)0x0000E) /*!< External interrupt line 14 */
+#define EXTI_TSSEL_LINE15 ((uint32_t)0x0000F) /*!< External interrupt line 15 */
+
+#define IS_EXTI_TSSEL_LINE(LINE) \
+ (((LINE) == EXTI_TSSEL_LINE0) || ((LINE) == EXTI_TSSEL_LINE1) || ((LINE) == EXTI_TSSEL_LINE2) \
+ || ((LINE) == EXTI_TSSEL_LINE3) || ((LINE) == EXTI_TSSEL_LINE4) || ((LINE) == EXTI_TSSEL_LINE5) \
+ || ((LINE) == EXTI_TSSEL_LINE6) || ((LINE) == EXTI_TSSEL_LINE7) || ((LINE) == EXTI_TSSEL_LINE8) \
+ || ((LINE) == EXTI_TSSEL_LINE9) || ((LINE) == EXTI_TSSEL_LINE10) || ((LINE) == EXTI_TSSEL_LINE11) \
+ || ((LINE) == EXTI_TSSEL_LINE12) || ((LINE) == EXTI_TSSEL_LINE13) || ((LINE) == EXTI_TSSEL_LINE14) \
+ || ((LINE) == EXTI_TSSEL_LINE15))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Exported_Functions
+ * @{
+ */
+
+void EXTI_DeInit(void);
+void EXTI_InitPeripheral(EXTI_InitType* EXTI_InitStruct);
+void EXTI_InitStruct(EXTI_InitType* EXTI_InitStruct);
+void EXTI_TriggerSWInt(uint32_t EXTI_Line);
+FlagStatus EXTI_GetStatusFlag(uint32_t EXTI_Line);
+void EXTI_ClrStatusFlag(uint32_t EXTI_Line);
+INTStatus EXTI_GetITStatus(uint32_t EXTI_Line);
+void EXTI_ClrITPendBit(uint32_t EXTI_Line);
+void EXTI_RTCTimeStampSel(uint32_t EXTI_TSSEL_Line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32L40X_EXTI_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_flash.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_flash.h
new file mode 100644
index 0000000000..7bec5f3c46
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_flash.h
@@ -0,0 +1,513 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_flash.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L40X_FLASH_H__
+#define __N32L40X_FLASH_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l40x.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @{
+ */
+
+/** @addtogroup FLASH_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief FLASH Status
+ */
+
+typedef enum
+{
+ FLASH_BUSY = 1,
+ FLASH_RESERVED,
+ FLASH_ERR_PG,
+ FLASH_ERR_PV,
+ FLASH_ERR_WRP,
+ FLASH_COMPL,
+ FLASH_ERR_EV,
+ FLASH_ERR_RDP2,
+ FLASH_ERR_ADD,
+ FLASH_TIMEOUT
+} FLASH_STS;
+
+/**
+ * @brief FLASH_SMPSEL
+ */
+
+typedef enum
+{
+ FLASH_SMP1 = 0,
+ FLASH_SMP2
+} FLASH_SMPSEL;
+
+/**
+ * @brief FLASH_HSICLOCK
+ */
+
+typedef enum
+{
+ FLASH_HSICLOCK_ENABLE = 0,
+ FLASH_HSICLOCK_DISABLE
+} FLASH_HSICLOCK;
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup Flash_Latency
+ * @{
+ */
+
+#define FLASH_LATENCY_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
+#define FLASH_LATENCY_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */
+#define FLASH_LATENCY_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */
+#define FLASH_LATENCY_3 ((uint32_t)0x00000003) /*!< FLASH Three Latency cycles */
+#define IS_FLASH_LATENCY(LATENCY) \
+ (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || ((LATENCY) == FLASH_LATENCY_2) \
+ || ((LATENCY) == FLASH_LATENCY_3))
+/**
+ * @}
+ */
+
+/** @addtogroup Prefetch_Buffer_Enable_Disable
+ * @{
+ */
+
+#define FLASH_PrefetchBuf_EN ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */
+#define FLASH_PrefetchBuf_DIS ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */
+#define IS_FLASH_PREFETCHBUF_STATE(STATE) (((STATE) == FLASH_PrefetchBuf_EN) || ((STATE) == FLASH_PrefetchBuf_DIS))
+/**
+ * @}
+ */
+
+/** @addtogroup iCache_Enable_Disable
+ * @{
+ */
+
+#define FLASH_iCache_EN ((uint32_t)0x00000080) /*!< FLASH iCache Enable */
+#define FLASH_iCache_DIS ((uint32_t)0x00000000) /*!< FLASH iCache Disable */
+#define IS_FLASH_ICACHE_STATE(STATE) (((STATE) == FLASH_iCache_EN) || ((STATE) == FLASH_iCache_DIS))
+/**
+ * @}
+ */
+
+/** @addtogroup Low Voltage Mode
+ * @{
+ */
+
+#define FLASH_LVM_EN ((uint32_t)0x00000200) /*!< FLASH Low Voltage Mode Enable */
+#define FLASH_LVM_DIS ((uint32_t)0x00000000) /*!< FLASH Low Voltage Mode Disable */
+#define IS_FLASH_LVM(STATE) (((STATE) == FLASH_LVM_EN) || ((STATE) == FLASH_LVM_DIS))
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH Sleep Mode
+ * @{
+ */
+
+#define FLASH_SLM_EN ((uint32_t)0x00000800) /*!< FLASH Sleep Mode Enable */
+#define FLASH_SLM_DIS ((uint32_t)0x00000000) /*!< FLASH Sleep Mode Disable */
+#define IS_FLASH_SLM(STATE) (((STATE) == FLASH_SLM_EN) || ((STATE) == FLASH_SLM_DIS))
+/**
+ * @}
+ */
+
+/** @addtogroup SMPSEL_SMP1_SMP2
+ * @{
+ */
+
+#define FLASH_SMPSEL_SMP1 ((uint32_t)0x00000000) /*!< FLASH SMPSEL SMP1 */
+#define FLASH_SMPSEL_SMP2 ((uint32_t)0x00000100) /*!< FLASH SMPSEL SMP2 */
+#define IS_FLASH_SMPSEL_STATE(STATE) (((STATE) == FLASH_SMPSEL_SMP1) || ((STATE) == FLASH_SMPSEL_SMP2))
+/**
+ * @}
+ */
+
+/* Values to be used with n32l40x devices */
+#define FLASH_WRP_Pages0to1 \
+ ((uint32_t)0x00000001) /*!< n32l40x devices: \
+ Write protection of page 0 to 1 */
+#define FLASH_WRP_Pages2to3 \
+ ((uint32_t)0x00000002) /*!< n32l40x devices: \
+ Write protection of page 2 to 3 */
+#define FLASH_WRP_Pages4to5 \
+ ((uint32_t)0x00000004) /*!< n32l40x devices: \
+ Write protection of page 4 to 5 */
+#define FLASH_WRP_Pages6to7 \
+ ((uint32_t)0x00000008) /*!< n32l40x devices: \
+ Write protection of page 6 to 7 */
+#define FLASH_WRP_Pages8to9 \
+ ((uint32_t)0x00000010) /*!< n32l40x devices: \
+ Write protection of page 8 to 9 */
+#define FLASH_WRP_Pages10to11 \
+ ((uint32_t)0x00000020) /*!< n32l40x devices: \
+ Write protection of page 10 to 11 */
+#define FLASH_WRP_Pages12to13 \
+ ((uint32_t)0x00000040) /*!< n32l40x devices: \
+ Write protection of page 12 to 13 */
+#define FLASH_WRP_Pages14to15 \
+ ((uint32_t)0x00000080) /*!< n32l40x devices: \
+ Write protection of page 14 to 15 */
+#define FLASH_WRP_Pages16to17 \
+ ((uint32_t)0x00000100) /*!< n32l40x devices: \
+ Write protection of page 16 to 17 */
+#define FLASH_WRP_Pages18to19 \
+ ((uint32_t)0x00000200) /*!< n32l40x devices: \
+ Write protection of page 18 to 19 */
+#define FLASH_WRP_Pages20to21 \
+ ((uint32_t)0x00000400) /*!< n32l40x devices: \
+ Write protection of page 20 to 21 */
+#define FLASH_WRP_Pages22to23 \
+ ((uint32_t)0x00000800) /*!< n32l40x devices: \
+ Write protection of page 22 to 23 */
+#define FLASH_WRP_Pages24to25 \
+ ((uint32_t)0x00001000) /*!< n32l40x devices: \
+ Write protection of page 24 to 25 */
+#define FLASH_WRP_Pages26to27 \
+ ((uint32_t)0x00002000) /*!< n32l40x devices: \
+ Write protection of page 26 to 27 */
+#define FLASH_WRP_Pages28to29 \
+ ((uint32_t)0x00004000) /*!< n32l40x devices: \
+ Write protection of page 28 to 29 */
+#define FLASH_WRP_Pages30to31 \
+ ((uint32_t)0x00008000) /*!< n32l40x devices: \
+ Write protection of page 30 to 31 */
+#define FLASH_WRP_Pages32to33 \
+ ((uint32_t)0x00010000) /*!< n32l40x devices: \
+ Write protection of page 32 to 33 */
+#define FLASH_WRP_Pages34to35 \
+ ((uint32_t)0x00020000) /*!< n32l40x devices: \
+ Write protection of page 34 to 35 */
+#define FLASH_WRP_Pages36to37 \
+ ((uint32_t)0x00040000) /*!< n32l40x devices: \
+ Write protection of page 36 to 37 */
+#define FLASH_WRP_Pages38to39 \
+ ((uint32_t)0x00080000) /*!< n32l40x devices: \
+ Write protection of page 38 to 39 */
+#define FLASH_WRP_Pages40to41 \
+ ((uint32_t)0x00100000) /*!< n32l40x devices: \
+ Write protection of page 40 to 41 */
+#define FLASH_WRP_Pages42to43 \
+ ((uint32_t)0x00200000) /*!< n32l40x devices: \
+ Write protection of page 42 to 43 */
+#define FLASH_WRP_Pages44to45 \
+ ((uint32_t)0x00400000) /*!< n32l40x devices: \
+ Write protection of page 44 to 45 */
+#define FLASH_WRP_Pages46to47 \
+ ((uint32_t)0x00800000) /*!< n32l40x devices: \
+ Write protection of page 46 to 47 */
+#define FLASH_WRP_Pages48to49 \
+ ((uint32_t)0x01000000) /*!< n32l40x devices: \
+ Write protection of page 48 to 49 */
+#define FLASH_WRP_Pages50to51 \
+ ((uint32_t)0x02000000) /*!< n32l40x devices: \
+ Write protection of page 50 to 51 */
+#define FLASH_WRP_Pages52to53 \
+ ((uint32_t)0x04000000) /*!< n32l40x devices: \
+ Write protection of page 52 to 53 */
+#define FLASH_WRP_Pages54to55 \
+ ((uint32_t)0x08000000) /*!< n32l40x devices: \
+ Write protection of page 54 to 55 */
+#define FLASH_WRP_Pages56to57 \
+ ((uint32_t)0x10000000) /*!< n32l40x devices: \
+ Write protection of page 56 to 57 */
+#define FLASH_WRP_Pages58to59 \
+ ((uint32_t)0x20000000) /*!< n32l40x devices: \
+ Write protection of page 58 to 59 */
+#define FLASH_WRP_Pages60to61 \
+ ((uint32_t)0x40000000) /*!< n32l40x devices: \
+ Write protection of page 60 to 61 */
+#define FLASH_WRP_Pages62to63 \
+ ((uint32_t)0x80000000) /*!< n32l40x devices:
+ Write protection of page 62 to 63 */
+
+#define FLASH_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
+
+#define IS_FLASH_WRP_PAGE(PAGE) (1)//(((PAGE) <= FLASH_WRP_AllPages))
+
+#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0801FFFF))
+
+#define IS_OB_DATA_ADDRESS(ADDRESS) ((ADDRESS) == 0x1FFFF804)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_RDP1
+ * @{
+ */
+
+#define OB_RDP1_ENABLE ((uint8_t)0x00) /*!< Enable RDP1 */
+#define OB_RDP1_DISABLE ((uint8_t)0xA5) /*!< DISABLE RDP1 */
+#define IS_OB_RDP1_SOURCE(SOURCE) (((SOURCE) == OB_RDP1_ENABLE) || ((SOURCE) == OB_RDP1_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_IWatchdog
+ * @{
+ */
+
+#define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */
+#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_nRST_STOP
+ * @{
+ */
+
+#define OB_STOP2_NORST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */
+#define OB_STOP2_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
+#define IS_OB_STOP2_SOURCE(SOURCE) (((SOURCE) == OB_STOP2_NORST) || ((SOURCE) == OB_STOP2_RST))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_nRST_STDBY
+ * @{
+ */
+
+#define OB_STDBY_NORST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NORST) || ((SOURCE) == OB_STDBY_RST))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_nRST_PD
+ * @{
+ */
+
+#define OB_PD_NORST ((uint8_t)0x08) /*!< No reset generated when entering in PowerDown */
+#define OB_PD_RST ((uint8_t)0x00) /*!< Reset generated when entering in PowerDown */
+#define IS_OB_PD_SOURCE(SOURCE) (((SOURCE) == OB_PD_NORST) || ((SOURCE) == OB_PD_RST))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_RDP2
+ * @{
+ */
+
+#define OB_RDP2_ENABLE ((uint8_t)0x33) /*!< Enable RDP2 */
+#define OB_RDP2_DISABLE ((uint8_t)0x00) /*!< Disable RDP2 */
+#define IS_OB_RDP2_SOURCE(SOURCE) (((SOURCE) == OB_RDP2_ENABLE) || ((SOURCE) == OB_RDP2_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_nBOOT0
+ * @{
+ */
+
+#define OB2_NBOOT0_SET ((uint8_t)0x01) /*!< Set nBOOT0 */
+#define OB2_NBOOT0_CLR ((uint8_t)0x00) /*!< Clear nBOOT0 */
+#define IS_OB2_NBOOT0_SOURCE(SOURCE) (((SOURCE) == OB2_NBOOT0_SET) || ((SOURCE) == OB2_NBOOT0_CLR))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_nBOOT1
+ * @{
+ */
+
+#define OB2_NBOOT1_SET ((uint8_t)0x02) /*!< Set nBOOT1 */
+#define OB2_NBOOT1_CLR ((uint8_t)0x00) /*!< Clear nBOOT1 */
+#define IS_OB2_NBOOT1_SOURCE(SOURCE) (((SOURCE) == OB2_NBOOT1_SET) || ((SOURCE) == OB2_NBOOT1_CLR))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_nSWBOOT0
+ * @{
+ */
+
+#define OB2_NSWBOOT0_SET ((uint8_t)0x04) /*!< Set nSWBOOT0 */
+#define OB2_NSWBOOT0_CLR ((uint8_t)0x00) /*!< Clear nSWBOOT0 */
+#define IS_OB2_NSWBOOT0_SOURCE(SOURCE) (((SOURCE) == OB2_NSWBOOT0_SET) || ((SOURCE) == OB2_NSWBOOT0_CLR))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_BOR_LEV
+ * @{
+ */
+
+#define OB2_BOR_LEV0 ((uint8_t)0x00) /*!< BOR_LEV[2:0] L0 */
+#define OB2_BOR_LEV1 ((uint8_t)0x10) /*!< BOR_LEV[2:0] L1 */
+#define OB2_BOR_LEV2 ((uint8_t)0x20) /*!< BOR_LEV[2:0] L2 */
+#define OB2_BOR_LEV3 ((uint8_t)0x30) /*!< BOR_LEV[2:0] L3 */
+#define OB2_BOR_LEV4 ((uint8_t)0x40) /*!< BOR_LEV[2:0] L4 */
+#define OB2_BOR_LEV5 ((uint8_t)0x50) /*!< BOR_LEV[2:0] L5 */
+#define OB2_BOR_LEV6 ((uint8_t)0x60) /*!< BOR_LEV[2:0] L6 */
+#define OB2_BOR_LEV7 ((uint8_t)0x70) /*!< BOR_LEV[2:0] L7 */
+#define IS_OB2_BOR_LEV_SOURCE(SOURCE) (((SOURCE) == OB2_BOR_LEV0) || ((SOURCE) == OB2_BOR_LEV1) \
+ || ((SOURCE) == OB2_BOR_LEV2) || ((SOURCE) == OB2_BOR_LEV3) \
+ || ((SOURCE) == OB2_BOR_LEV4) || ((SOURCE) == OB2_BOR_LEV5) \
+ || ((SOURCE) == OB2_BOR_LEV6) || ((SOURCE) == OB2_BOR_LEV7))
+
+
+/**
+ * @}
+ */
+/** @addtogroup FLASH_Interrupts
+ * @{
+ */
+#define FLASH_INT_ERRIE ((uint32_t)0x00000400) /*!< PGERR WRPERR ERROR error interrupt source */
+#define FLASH_INT_FERR ((uint32_t)0x00000800) /*!< EVERR PVERR interrupt source */
+#define FLASH_INT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */
+
+#define IS_FLASH_INT(IT) ((((IT) & (uint32_t)0xFFFFE3FF) == 0x00000000) && (((IT) != 0x00000000)))
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Flags
+ * @{
+ */
+#define FLASH_FLAG_BUSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */
+#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */
+#define FLASH_FLAG_PVERR ((uint32_t)0x00000008) /*!< FLASH Program Verify ERROR flag after program */
+#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */
+#define FLASH_FLAG_EVERR ((uint32_t)0x00000040) /*!< FLASH Erase Verify ERROR flag after page erase */
+#define FLASH_FLAG_OBERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */
+
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF83) == 0x00000000) && ((FLAG) != 0x00000000))
+#define IS_FLASH_GET_FLAG(FLAG) \
+ (((FLAG) == FLASH_FLAG_BUSY) || ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_PVERR) \
+ || ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_EVERR) \
+ || ((FLAG) == FLASH_FLAG_OBERR))
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_STS_CLRFLAG
+ * @{
+ */
+#define FLASH_STS_CLRFLAG (FLASH_FLAG_PGERR | FLASH_FLAG_PVERR | FLASH_FLAG_WRPERR | FLASH_FLAG_EOP |FLASH_FLAG_EVERR)
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Exported_Functions
+ * @{
+ */
+
+/*------------ Functions used for n32l40x devices -----*/
+void FLASH_SetLatency(uint32_t FLASH_Latency);
+void FLASH_PrefetchBufSet(uint32_t FLASH_PrefetchBuf);
+void FLASH_iCacheRST(void);
+void FLASH_iCacheCmd(uint32_t FLASH_iCache);
+void FLASH_LowVoltageModeCmd(uint32_t FLASH_LVM);
+FlagStatus FLASH_GetLowVoltageModeSTS(void);
+void FLASH_FLASHSleepModeCmd(uint32_t FLASH_SLM);
+FlagStatus FLASH_GetFLASHSleepModeSTS(void);
+FLASH_HSICLOCK FLASH_ClockInit(void);
+void FLASH_Unlock(void);
+void FLASH_Lock(void);
+FLASH_STS FLASH_EraseOnePage(uint32_t Page_Address);
+FLASH_STS FLASH_MassErase(void);
+FLASH_STS FLASH_EraseOB(void);
+FLASH_STS FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+FLASH_STS FLASH_ProgramOBData(uint32_t Address, uint32_t Data);
+FLASH_STS FLASH_EnWriteProtection(uint32_t FLASH_Pages);
+FLASH_STS FLASH_ReadOutProtectionL1(FunctionalState Cmd);
+FLASH_STS FLASH_ReadOutProtectionL2_ENABLE(void);
+FLASH_STS FLASH_ConfigALLOptionByte(uint8_t OB_RDP1, uint8_t OB_IWDG, uint8_t OB_STOP2,
+ uint8_t OB_STDBY, uint8_t OB_PD, uint8_t OB_Data0,
+ uint8_t OB_Data1, uint32_t WRP_Pages, uint8_t OB_RDP2,
+ uint8_t OB2_nBOOT0, uint8_t OB2_nBOOT1, uint8_t OB2_nSWBOOT0,
+ uint8_t OB2_BOR_LEV);
+FLASH_STS FLASH_ConfigUserOB(uint8_t OB_IWDG, uint8_t OB_STOP2, uint8_t OB_STDBY, uint8_t OB_PD);
+FLASH_STS FLASH_ConfigUserOB2(uint8_t OB2_nBOOT0, uint8_t OB2_nBOOT1, uint8_t OB2_nSWBOOT0, uint8_t OB2_BOR_LEV);
+uint32_t FLASH_GetUserOB(void);
+uint32_t FLASH_GetWriteProtectionOB(void);
+FlagStatus FLASH_GetReadOutProtectionSTS(void);
+FlagStatus FLASH_GetReadOutProtectionL2STS(void);
+FlagStatus FLASH_GetPrefetchBufSTS(void);
+void FLASH_SetSMPSELStatus(uint32_t FLASH_smpsel);
+FLASH_SMPSEL FLASH_GetSMPSELStatus(void);
+void FLASH_INTConfig(uint32_t FLASH_INT, FunctionalState Cmd);
+FlagStatus FLASH_GetFlagSTS(uint32_t FLASH_FLAG);
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);
+FLASH_STS FLASH_GetSTS(void);
+FLASH_STS FLASH_WaitForLastOpt(uint32_t Timeout);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32L40X_FLASH_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_gpio.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_gpio.h
new file mode 100644
index 0000000000..c40cef92aa
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_gpio.h
@@ -0,0 +1,676 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_gpio.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L40X_GPIO_H__
+#define __N32L40X_GPIO_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l40x.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/** @addtogroup GPIO_Exported_Types
+ * @{
+ */
+
+#define IS_GPIO_ALL_PERIPH(PERIPH) \
+ (((PERIPH) == GPIOA) || ((PERIPH) == GPIOB) || ((PERIPH) == GPIOC) || ((PERIPH) == GPIOD))
+
+
+#define GPIO_GET_INDEX(PERIPH) (((PERIPH) == (GPIOA))? 0 :\
+ ((PERIPH) == (GPIOB))? 1 :\
+ ((PERIPH) == (GPIOC))? 2 :3)
+#define GPIO_GET_PERIPH(INDEX) (((INDEX)==((uint8_t)0x00))? GPIOA :\
+ ((INDEX)==((uint8_t)0x01))? GPIOB :\
+ ((INDEX)==((uint8_t)0x02))? GPIOC : GPIOD )
+
+
+/**
+ * @brief Output Maximum frequency selection
+ */
+
+typedef enum
+{
+ GPIO_Slew_Rate_High = 0,
+ GPIO_Slew_Rate_Low
+} GPIO_SpeedType;
+#define IS_GPIO_SLEW_RATE(_RATE_) \
+ (((_RATE_) == GPIO_Slew_Rate_High) || ((_RATE_) == GPIO_Slew_Rate_Low))
+
+/**
+ * @brief driver strength config
+ */
+
+typedef enum
+{
+ GPIO_DC_2mA = 0x00,
+ GPIO_DC_4mA = 0x10,
+ GPIO_DC_8mA = 0x01,
+ GPIO_DC_12mA= 0x11
+}GPIO_CurrentType;
+
+#define IS_GPIO_CURRENT(CURRENT) \
+ (((CURRENT) == GPIO_DC_2mA) ||((CURRENT) == GPIO_DC_4mA) \
+ || ((CURRENT) == GPIO_DC_8mA)||((CURRENT) == GPIO_DC_12mA))
+/**
+ * @brief Configuration Mode enumeration
+ */
+
+
+/** @brief GPIO_mode_define Mode definition
+ * @brief GPIO Configuration Mode
+ * Values convention: 0xW0yz00YZ
+ * - W : GPIO mode or EXTI Mode
+ * - y : External IT or Event trigger detection
+ * - z : IO configuration on External IT or Event
+ * - Y : Output type (Push Pull or Open Drain)
+ * - Z : IO Direction mode (Input, Output, Alternate or Analog)
+ * @{
+ */
+
+typedef enum
+{
+ GPIO_Mode_Input = 0x00000000, /*!< Input Floating Mode */
+ GPIO_Mode_Out_PP = 0x00000001, /*!< Output Push Pull Mode */
+ GPIO_Mode_Out_OD = 0x00000011, /*!< Output Open Drain Mode */
+ GPIO_Mode_AF_PP = 0x00000002, /*!< Alternate Function Push Pull Mode */
+ GPIO_Mode_AF_OD = 0x00000012, /*!< Alternate Function Open Drain Mode */
+
+ GPIO_Mode_Analog = 0x00000003, /*!< Analog Mode */
+
+ GPIO_Mode_IT_Rising = 0x10110000, /*!< External Interrupt Mode with Rising edge trigger detection */
+ GPIO_Mode_IT_Falling = 0x10210000, /*!< External Interrupt Mode with Falling edge trigger detection */
+ GPIO_Mode_IT_Rising_Falling = 0x10310000, /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+
+ GPIO_Mode_EVT_Rising = 0x10120000, /*!< External Event Mode with Rising edge trigger detection */
+ GPIO_Mode_EVT_Falling = 0x10220000, /*!< External Event Mode with Falling edge trigger detection */
+ GPIO_Mode_EVT_Rising_Falling = 0x10320000
+}GPIO_ModeType;
+
+
+
+/**
+ * @}
+ */
+#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_Mode_Input) ||\
+ ((__MODE__) == GPIO_Mode_Out_PP) ||\
+ ((__MODE__) == GPIO_Mode_Out_OD) ||\
+ ((__MODE__) == GPIO_Mode_AF_PP) ||\
+ ((__MODE__) == GPIO_Mode_AF_OD) ||\
+ ((__MODE__) == GPIO_Mode_IT_Rising) ||\
+ ((__MODE__) == GPIO_Mode_IT_Falling) ||\
+ ((__MODE__) == GPIO_Mode_IT_Rising_Falling) ||\
+ ((__MODE__) == GPIO_Mode_EVT_Rising) ||\
+ ((__MODE__) == GPIO_Mode_EVT_Falling) ||\
+ ((__MODE__) == GPIO_Mode_EVT_Rising_Falling) ||\
+ ((__MODE__) == GPIO_Mode_Analog))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @brief GPIO_pull_define Pull definition
+ * @brief GPIO Pull-Up or Pull-Down Activation
+ * @{
+ */
+
+typedef enum
+{
+ GPIO_No_Pull = 0x00000000, /*!< No Pull-up or Pull-down activation */
+ GPIO_Pull_Up = 0x00000001, /*!< Pull-up activation */
+ GPIO_Pull_Down = 0x00000002 /*!< Pull-down activation */
+}GPIO_PuPdType;
+/**
+ * @}
+ */
+
+#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_No_Pull) || ((__PULL__) == GPIO_Pull_Up) || \
+ ((__PULL__) == GPIO_Pull_Down))
+/**
+ * @}
+ */
+
+/**
+ * @brief GPIO Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_pins_define */
+
+ GPIO_CurrentType GPIO_Current; /*!.
+ This paramter can be a value of @ref GPIO_CurrentType*/
+
+ GPIO_SpeedType GPIO_Slew_Rate; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIO_SpeedType */
+
+ GPIO_PuPdType GPIO_Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+ This parameter can be a value of @ref GPIO_pull_define */
+
+ GPIO_ModeType GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIO_ModeType */
+
+ uint32_t GPIO_Alternate; /*!< Peripheral to be connected to the selected pins
+ This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
+} GPIO_InitType;
+
+/**
+ * @brief Bit_SET and Bit_RESET enumeration
+ */
+
+typedef enum
+{
+ Bit_RESET = 0,
+ Bit_SET
+} Bit_OperateType;
+
+#define IS_GPIO_BIT_OPERATE(OPERATE) (((OPERATE) == Bit_RESET) || ((OPERATE) == Bit_SET))
+
+/**
+ * @}
+ */
+
+
+
+
+/** @addtogroup GPIO_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup GPIO_pins_define
+ * @{
+ */
+
+#define GPIO_PIN_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
+#define GPIO_PIN_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
+#define GPIO_PIN_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
+#define GPIO_PIN_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
+#define GPIO_PIN_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
+#define GPIO_PIN_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
+#define GPIO_PIN_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
+#define GPIO_PIN_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
+#define GPIO_PIN_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
+#define GPIO_PIN_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
+#define GPIO_PIN_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
+#define GPIO_PIN_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
+#define GPIO_PIN_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
+#define GPIO_PIN_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
+#define GPIO_PIN_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
+#define GPIO_PIN_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
+#define GPIO_PIN_ALL ((uint16_t)0xFFFF) /*!< All pins selected */
+
+#define GPIOA_PIN_AVAILABLE ((uint16_t)0xFFFF)
+#define GPIOB_PIN_AVAILABLE ((uint16_t)0xFFFF)
+#define GPIOC_PIN_AVAILABLE ((uint16_t)0xFFFF)
+#define GPIOD_PIN_AVAILABLE ((uint16_t)0xFFFF)
+
+#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
+
+#define IS_GET_GPIO_PIN(PIN) \
+ (((PIN) == GPIO_PIN_0) || ((PIN) == GPIO_PIN_1) || ((PIN) == GPIO_PIN_2) || ((PIN) == GPIO_PIN_3) \
+ || ((PIN) == GPIO_PIN_4) || ((PIN) == GPIO_PIN_5) || ((PIN) == GPIO_PIN_6) || ((PIN) == GPIO_PIN_7) \
+ || ((PIN) == GPIO_PIN_8) || ((PIN) == GPIO_PIN_9) || ((PIN) == GPIO_PIN_10) || ((PIN) == GPIO_PIN_11) \
+ || ((PIN) == GPIO_PIN_12) || ((PIN) == GPIO_PIN_13) || ((PIN) == GPIO_PIN_14) || ((PIN) == GPIO_PIN_15))
+
+
+#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) \
+ ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \
+ (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \
+ (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \
+ (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))))
+
+
+
+
+
+/**
+ * @}
+ */
+
+
+
+
+/** @addtogroup GPIO_Port_Sources
+ * @{
+ */
+
+#define GPIOA_PORT_SOURCE ((uint8_t)0x00)
+#define GPIOB_PORT_SOURCE ((uint8_t)0x01)
+#define GPIOC_PORT_SOURCE ((uint8_t)0x02)
+#define GPIOD_PORT_SOURCE ((uint8_t)0x03)
+
+#define IS_GPIO_REMAP_PORT_SOURCE(PORTSOURCE) \
+ (((PORTSOURCE) == GPIOA_PORT_SOURCE) || ((PORTSOURCE) == GPIOB_PORT_SOURCE) || ((PORTSOURCE) == GPIOC_PORT_SOURCE) \
+ || ((PORTSOURCE) == GPIOD_PORT_SOURCE))
+
+
+#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) \
+ (((PORTSOURCE) == GPIOA_PORT_SOURCE) || ((PORTSOURCE) == GPIOB_PORT_SOURCE) || ((PORTSOURCE) == GPIOC_PORT_SOURCE) \
+ || ((PORTSOURCE) == GPIOD_PORT_SOURCE))
+
+#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) \
+ (((PORTSOURCE) == GPIOA_PORT_SOURCE) || ((PORTSOURCE) == GPIOB_PORT_SOURCE) || ((PORTSOURCE) == GPIOC_PORT_SOURCE) \
+ || ((PORTSOURCE) == GPIOD_PORT_SOURCE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Pin_sources
+ * @{
+ */
+
+#define GPIO_PIN_SOURCE0 ((uint8_t)0x00)
+#define GPIO_PIN_SOURCE1 ((uint8_t)0x01)
+#define GPIO_PIN_SOURCE2 ((uint8_t)0x02)
+#define GPIO_PIN_SOURCE3 ((uint8_t)0x03)
+#define GPIO_PIN_SOURCE4 ((uint8_t)0x04)
+#define GPIO_PIN_SOURCE5 ((uint8_t)0x05)
+#define GPIO_PIN_SOURCE6 ((uint8_t)0x06)
+#define GPIO_PIN_SOURCE7 ((uint8_t)0x07)
+#define GPIO_PIN_SOURCE8 ((uint8_t)0x08)
+#define GPIO_PIN_SOURCE9 ((uint8_t)0x09)
+#define GPIO_PIN_SOURCE10 ((uint8_t)0x0A)
+#define GPIO_PIN_SOURCE11 ((uint8_t)0x0B)
+#define GPIO_PIN_SOURCE12 ((uint8_t)0x0C)
+#define GPIO_PIN_SOURCE13 ((uint8_t)0x0D)
+#define GPIO_PIN_SOURCE14 ((uint8_t)0x0E)
+#define GPIO_PIN_SOURCE15 ((uint8_t)0x0F)
+
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) \
+ (((PINSOURCE) == GPIO_PIN_SOURCE0) || ((PINSOURCE) == GPIO_PIN_SOURCE1) || ((PINSOURCE) == GPIO_PIN_SOURCE2) \
+ || ((PINSOURCE) == GPIO_PIN_SOURCE3) || ((PINSOURCE) == GPIO_PIN_SOURCE4) || ((PINSOURCE) == GPIO_PIN_SOURCE5) \
+ || ((PINSOURCE) == GPIO_PIN_SOURCE6) || ((PINSOURCE) == GPIO_PIN_SOURCE7) || ((PINSOURCE) == GPIO_PIN_SOURCE8) \
+ || ((PINSOURCE) == GPIO_PIN_SOURCE9) || ((PINSOURCE) == GPIO_PIN_SOURCE10) || ((PINSOURCE) == GPIO_PIN_SOURCE11) \
+ || ((PINSOURCE) == GPIO_PIN_SOURCE12) || ((PINSOURCE) == GPIO_PIN_SOURCE13) || ((PINSOURCE) == GPIO_PIN_SOURCE14) \
+ || ((PINSOURCE) == GPIO_PIN_SOURCE15))
+
+/**
+ * @}
+ */
+
+
+
+/** @defgroup GPIOx_Alternate_function_selection Alternate function selection
+ * @{
+ */
+
+/*
+ * Alternate function AF0
+ */
+#define GPIO_AF0_SW_JTAG ((uint8_t)0x00) /* SPI1 Alternate Function mapping */
+#define GPIO_AF0_SPI1 ((uint8_t)0x00) /* SPI1 Alternate Function mapping */
+#define GPIO_AF0_LPTIM ((uint8_t)0x00) /* LPTIM Alternate Function mapping */
+#define GPIO_AF0_SPI2 ((uint8_t)0x00) /* SPI2 Alternate Function mapping */
+#define GPIO_AF0_TIM8 ((uint8_t)0x00) /* TIM8 Alternate Function mapping */
+#define GPIO_AF0_USART1 ((uint8_t)0x00) /* USART1 Alternate Function mapping */
+#define GPIO_AF0_USART3 ((uint8_t)0x00) /* USART3 Alternate Function mapping */
+#define GPIO_AF0_LPUART ((uint8_t)0x00) /* LPUART Alternate Function mapping */
+#define GPIO_AF0_USART2 ((uint8_t)0x00) /* USART2 Alternate Function mapping */
+
+/**
+ *
+ */
+
+/*
+ * Alternate function AF1
+ */
+#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */
+#define GPIO_AF1_USART1 ((uint8_t)0x01) /* USART1 Alternate Function mapping */
+#define GPIO_AF1_I2C2 ((uint8_t)0x01) /* I2C2 Alternate Function mapping */
+#define GPIO_AF1_CAN ((uint8_t)0x01) /* CAN Alternate Function mapping */
+#define GPIO_AF1_SPI2 ((uint8_t)0x01) /* SPI2 Alternate Function mapping */
+#define GPIO_AF1_TIM9 ((uint8_t)0x01) /* TIM9 Alternate Function mapping */
+#define GPIO_AF1_SPI1 ((uint8_t)0x01) /* SPI1 Alternate Function mapping */
+#define GPIO_AF1_I2C1 ((uint8_t)0x01) /* I2C1 Alternate Function mapping */
+#define GPIO_AF1 ((uint8_t)0x01) /* test Alternate Function mapping */
+/**
+ *
+ */
+
+/*
+ * Alternate function AF2
+ */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_LPTIM ((uint8_t)0x02) /* LPTIM Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_LPUART ((uint8_t)0x02) /* LPUART Alternate Function mapping */
+/**
+ *
+ */
+
+/*
+ * Alternate function AF3
+ */
+#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /* EVENTOUT Alternate Function mapping */
+
+/**
+ *
+ */
+
+/*
+ * Alternate function AF4
+ */
+#define GPIO_AF4_USART2 ((uint8_t)0x04) /* USART2 Alternate Function mapping */
+#define GPIO_AF4_LPUART ((uint8_t)0x04) /* LPUART Alternate Function mapping */
+#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */
+#define GPIO_AF4_TIM3 ((uint8_t)0x04) /* TIM3 Alternate Function mapping*/
+#define GPIO_AF4_SPI1 ((uint8_t)0x04) /* SPI1 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_USART3 ((uint8_t)0x04) /* USART3 Alternate Function mapping */
+/**
+ *
+ */
+
+/*
+ * Alternate function AF5
+ */
+#define GPIO_AF5_TIM2 ((uint8_t)0x05) /* TIM2 Alternate Function mapping */
+#define GPIO_AF5_TIM1 ((uint8_t)0x05) /* TIM1 Alternate Function mapping */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
+#define GPIO_AF5_I2C2 ((uint8_t)0x05) /* I2C2 Alternate Function mapping */
+#define GPIO_AF5_LPTIM ((uint8_t)0x05) /* LPTIM Alternate Function mapping */
+#define GPIO_AF5_CAN ((uint8_t)0x05) /* CAN Alternate Function mapping */
+#define GPIO_AF5_USART3 ((uint8_t)0x05) /* USART3 Alternate Function mapping */
+
+/**
+ *
+ */
+
+/*
+ * Alternate function AF6
+ */
+
+#define GPIO_AF6_USART2 ((uint8_t)0x06) /* USART2 Alternate Function mapping */
+#define GPIO_AF6_LPUART ((uint8_t)0x06) /* LPUART Alternate Function mapping */
+#define GPIO_AF6_TIM5 ((uint8_t)0x06) /* TIM5 Alternate Function mapping */
+#define GPIO_AF6_TIM8 ((uint8_t)0x06) /* TIM8 Alternate Function mapping */
+#define GPIO_AF6_I2C2 ((uint8_t)0x06) /* I2C2 Alternate Function mapping */
+#define GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */
+#define GPIO_AF6_UART5 ((uint8_t)0x06) /* UART5 Alternate Function mapping */
+#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1 Alternate Function mapping */
+/**
+ *
+ */
+
+/*
+ * Alternate function AF7
+ */
+#define GPIO_AF7_COMP1 ((uint8_t)0x07) /* COMP1 Alternate Function mapping */
+#define GPIO_AF7_COMP2 ((uint8_t)0x07) /* COMP2 Alternate Function mapping */
+#define GPIO_AF7_I2C1 ((uint8_t)0x07) /* I2C1 Alternate Function mapping */
+#define GPIO_AF7_TIM8 ((uint8_t)0x07) /* TIM8 Alternate Function mapping */
+#define GPIO_AF7_TIM5 ((uint8_t)0x07) /* TIM5 Alternate Function mapping */
+#define GPIO_AF7_LPUART ((uint8_t)0x07) /* LPUART Alternate Function mapping */
+#define GPIO_AF7_UART5 ((uint8_t)0x07) /* UART5 Alternate Function mapping */
+#define GPIO_AF7_TIM1 ((uint8_t)0x07) /* TIM1 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+
+/**
+ *
+ */
+
+ /*
+ * Alternate function AF8
+ */
+#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
+#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
+#define GPIO_AF8_LPTIM ((uint8_t)0x08) /* LPTIM Alternate Function mapping */
+#define GPIO_AF8_MCO ((uint8_t)0x08) /* MCO Alternate Function mapping */
+
+/**
+ *
+ */
+
+ /*
+ * Alternate function AF9
+ */
+#define GPIO_AF9_RTC ((uint8_t)0x09) /* RTC Alternate Function mapping */
+#define GPIO_AF9_COMP1 ((uint8_t)0x09) /* COMP1 Alternate Function mapping */
+#define GPIO_AF9_TSC ((uint8_t)0x09) /* COMP1 Alternate Function mapping */
+
+/**
+ *
+ */
+
+ /*
+ * Alternate function AF10
+ */
+#define GPIO_AF10_LCD ((uint8_t)0x0A) /* LCD Alternate Function mapping */
+
+/**
+ *
+ */
+
+ /*
+ * Alternate function AF11
+ */
+#define GPIO_AF11_LCD ((uint8_t)0x0B) /* LCD Alternate Function mapping */
+
+
+ /*
+ * Alternate function AF15
+ */
+#define GPIO_AF15 ((uint8_t)0x0F) /* NON Alternate Function mapping */
+
+#define GPIO_NO_AF (GPIO_AF15)
+/**
+ * @}
+ */
+
+
+/**
+ * IS_GPIO_AF macro definition
+ */
+
+#define IS_GPIO_AF(__AF__) (((__AF__) == GPIO_AF0_SPI1) || ((__AF__) == GPIO_AF1_TIM5) || \
+ ((__AF__) == GPIO_AF0_LPTIM) || ((__AF__) == GPIO_AF1_USART1) || \
+ ((__AF__) == GPIO_AF0_SPI2) || ((__AF__) == GPIO_AF1_I2C2) || \
+ ((__AF__) == GPIO_AF0_TIM8) || ((__AF__) == GPIO_AF1_CAN) || \
+ ((__AF__) == GPIO_AF0_USART1) || ((__AF__) == GPIO_AF1_SPI2) || \
+ ((__AF__) == GPIO_AF0_USART3) || ((__AF__) == GPIO_AF1_TIM9) || \
+ ((__AF__) == GPIO_AF0_LPUART) || ((__AF__) == GPIO_AF1_SPI1) || \
+ ((__AF__) == GPIO_AF0_USART2) || ((__AF__) == GPIO_AF1_I2C1) || \
+ ((__AF__) == GPIO_AF3_EVENTOUT) || ((__AF__) == GPIO_AF2_TIM2) || \
+ ((__AF__) == GPIO_AF5_TIM2) || ((__AF__) == GPIO_AF2_TIM3) || \
+ ((__AF__) == GPIO_AF5_TIM1) || ((__AF__) == GPIO_AF2_TIM1) || \
+ ((__AF__) == GPIO_AF5_SPI1) || ((__AF__) == GPIO_AF2_LPTIM) || \
+ ((__AF__) == GPIO_AF5_SPI2) || ((__AF__) == GPIO_AF2_TIM4) || \
+ ((__AF__) == GPIO_AF5_I2C2) || ((__AF__) == GPIO_AF2_LPUART) || \
+ ((__AF__) == GPIO_AF5_LPTIM) || ((__AF__) == GPIO_AF4_USART2) || \
+ ((__AF__) == GPIO_AF5_CAN) || ((__AF__) == GPIO_AF4_LPUART) || \
+ ((__AF__) == GPIO_AF5_USART3) || ((__AF__) == GPIO_AF4_USART1) || \
+ ((__AF__) == GPIO_AF6_USART2) || ((__AF__) == GPIO_AF4_TIM3) || \
+ ((__AF__) == GPIO_AF6_LPUART) || ((__AF__) == GPIO_AF4_SPI1) || \
+ ((__AF__) == GPIO_AF6_TIM5) || ((__AF__) == GPIO_AF4_I2C1) || \
+ ((__AF__) == GPIO_AF6_TIM8) || ((__AF__) == GPIO_AF4_USART3) || \
+ ((__AF__) == GPIO_AF6_I2C2) || ((__AF__) == GPIO_AF7_COMP1) || \
+ ((__AF__) == GPIO_AF6_UART4) || ((__AF__) == GPIO_AF7_COMP2) || \
+ ((__AF__) == GPIO_AF6_UART5) || ((__AF__) == GPIO_AF7_I2C1) || \
+ ((__AF__) == GPIO_AF6_SPI1) || ((__AF__) == GPIO_AF7_TIM8) || \
+ ((__AF__) == GPIO_AF8_COMP1) || ((__AF__) == GPIO_AF7_TIM5) || \
+ ((__AF__) == GPIO_AF8_COMP2) || ((__AF__) == GPIO_AF7_LPUART) || \
+ ((__AF__) == GPIO_AF8_LPTIM) || ((__AF__) == GPIO_AF7_UART5) || \
+ ((__AF__) == GPIO_AF9_RTC) || ((__AF__) == GPIO_AF7_TIM1) || \
+ ((__AF__) == GPIO_AF9_COMP1) || ((__AF__) == GPIO_AF7_USART3) || \
+ ((__AF__) == GPIO_AF10_LCD) || ((__AF__) == GPIO_AF11_LCD) || \
+ ((__AF__) == GPIO_AF15) || ((__AF__) == GPIO_NO_AF))
+
+
+
+
+
+/**
+ * @}
+ */
+/** @defgroup GPIO Alternate function remaping
+ * @{
+ */
+#define AFIO_SPI1_NSS (11U)
+#define AFIO_SPI2_NSS (10U)
+
+#define IS_AFIO_SPIX(_PARAMETER_) \
+ (((_PARAMETER_) == AFIO_SPI1_NSS) ||((_PARAMETER_) == AFIO_SPI2_NSS))
+typedef enum
+{
+ AFIO_SPI_NSS_High_IMPEDANCE = 0U,
+ AFIO_SPI_NSS_High_LEVEL = 1U
+}AFIO_SPI_NSSType;
+
+#define IS_AFIO_SPI_NSS(_PARAMETER_) \
+ (((_PARAMETER_) == AFIO_SPI_NSS_High_IMPEDANCE) ||((_PARAMETER_) == AFIO_SPI_NSS_High_LEVEL))
+
+
+typedef enum
+{
+ AFIO_ADC_ETRI= 9U,
+ AFIO_ADC_ETRR = 8U
+}AFIO_ADC_ETRType;
+
+typedef enum
+{
+ AFIO_ADC_TRIG_EXTI_0 = 0x0U,
+ AFIO_ADC_TRIG_EXTI_1 = 0x01U,
+ AFIO_ADC_TRIG_EXTI_2,
+ AFIO_ADC_TRIG_EXTI_3,
+ AFIO_ADC_TRIG_EXTI_4,
+ AFIO_ADC_TRIG_EXTI_5,
+ AFIO_ADC_TRIG_EXTI_6,
+ AFIO_ADC_TRIG_EXTI_7,
+ AFIO_ADC_TRIG_EXTI_8,
+ AFIO_ADC_TRIG_EXTI_9,
+ AFIO_ADC_TRIG_EXTI_10,
+ AFIO_ADC_TRIG_EXTI_11,
+ AFIO_ADC_TRIG_EXTI_12,
+ AFIO_ADC_TRIG_EXTI_13,
+ AFIO_ADC_TRIG_EXTI_14,
+ AFIO_ADC_TRIG_EXTI_15,
+ AFIO_ADC_TRIG_TIM8_CH3,
+ AFIO_ADC_TRIG_TIM8_CH4
+}AFIO_ADC_Trig_RemapType;
+
+#define IS_AFIO_ADC_ETR(_PARAMETER_) \
+ (((_PARAMETER_) == AFIO_ADC_ETRI) ||((_PARAMETER_) == AFIO_ADC_ETRR))
+#define IS_AFIO_ADC_ETRI(_PARAMETER_) \
+ (((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_0) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_1)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_2) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_3)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_4) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_5)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_6) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_7)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_8) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_9)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_10) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_11)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_12) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_13)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_14) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_15)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_TIM8_CH4))
+
+#define IS_AFIO_ADC_ETRR(_PARAMETER_) \
+ (((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_0) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_1)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_2) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_3)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_4) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_5)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_6) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_7)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_8) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_9)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_10) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_11)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_12) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_13) ||\
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_14) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_15)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_TIM8_CH3))
+
+ /**
+ * @}
+ */
+
+/** @addtogroup GPIO_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Exported_Functions
+ * @{
+ */
+
+void GPIO_DeInit(GPIO_Module* GPIOx);
+void GPIO_AFIOInitDefault(void);
+void GPIO_InitPeripheral(GPIO_Module* GPIOx, GPIO_InitType* GPIO_InitStruct);
+void GPIO_InitStruct(GPIO_InitType* GPIO_InitStruct);
+uint8_t GPIO_ReadInputDataBit(GPIO_Module* GPIOx, uint16_t Pin);
+uint16_t GPIO_ReadInputData(GPIO_Module* GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_Module* GPIOx, uint16_t Pin);
+uint16_t GPIO_ReadOutputData(GPIO_Module* GPIOx);
+void GPIO_SetBits(GPIO_Module* GPIOx, uint16_t Pin);
+void GPIO_ResetBits(GPIO_Module* GPIOx, uint16_t Pin);
+void GPIO_WriteBit(GPIO_Module* GPIOx, uint16_t Pin, Bit_OperateType BitCmd);
+void GPIO_Write(GPIO_Module* GPIOx, uint16_t PortVal);
+void GPIO_ConfigPinLock(GPIO_Module* GPIOx, uint16_t Pin);
+void GPIO_ConfigEventOutput(uint8_t PortSource, uint8_t PinSource);
+void GPIO_CtrlEventOutput(FunctionalState Cmd);
+void GPIO_ConfigPinRemap(uint8_t PortSource, uint8_t PinSource, uint32_t AlternateFunction);
+void GPIO_ConfigEXTILine(uint8_t PortSource, uint8_t PinSource);
+
+void AFIO_ConfigSPINSSMode(uint32_t AFIO_SPIx_NSS,AFIO_SPI_NSSType SpiNssType);
+void AFIO_ConfigADCExternalTrigRemap(AFIO_ADC_ETRType ADCETRType,AFIO_ADC_Trig_RemapType ADCTrigRemap);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32L40X_GPIO_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_i2c.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_i2c.h
new file mode 100644
index 0000000000..64ce034ade
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_i2c.h
@@ -0,0 +1,671 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_i2c.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L40X_I2C_H__
+#define __N32L40X_I2C_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l40x.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @{
+ */
+
+/** @addtogroup I2C_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief I2C Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t ClkSpeed; /*!< Specifies the clock frequency.
+ This parameter must be set to a value lower than 400kHz */
+
+ uint16_t BusMode; /*!< Specifies the I2C mode.
+ This parameter can be a value of @ref I2C_BusMode */
+
+ uint16_t FmDutyCycle; /*!< Specifies the I2C fast mode duty cycle.
+ This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+ uint16_t OwnAddr1; /*!< Specifies the first device own address.
+ This parameter can be a 7-bit or 10-bit address. */
+
+ uint16_t AckEnable; /*!< Enables or disables the acknowledgement.
+ This parameter can be a value of @ref I2C_acknowledgement */
+
+ uint16_t AddrMode; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
+ This parameter can be a value of @ref I2C_acknowledged_address */
+} I2C_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Exported_Constants
+ * @{
+ */
+
+#define IS_I2C_PERIPH(PERIPH) (((PERIPH) == I2C1) || ((PERIPH) == I2C2))
+/** @addtogroup I2C_BusMode
+ * @{
+ */
+
+#define I2C_BUSMODE_I2C ((uint16_t)0x0000)
+#define I2C_BUSMODE_SMBDEVICE ((uint16_t)0x0002)
+#define I2C_BUSMODE_SMBHOST ((uint16_t)0x000A)
+#define IS_I2C_BUS_MODE(MODE) \
+ (((MODE) == I2C_BUSMODE_I2C) || ((MODE) == I2C_BUSMODE_SMBDEVICE) || ((MODE) == I2C_BUSMODE_SMBHOST))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_duty_cycle_in_fast_mode
+ * @{
+ */
+
+#define I2C_FMDUTYCYCLE_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
+#define I2C_FMDUTYCYCLE_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
+#define IS_I2C_FM_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_FMDUTYCYCLE_16_9) || ((CYCLE) == I2C_FMDUTYCYCLE_2))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_acknowledgement
+ * @{
+ */
+
+#define I2C_ACKEN ((uint16_t)0x0400)
+#define I2C_ACKDIS ((uint16_t)0x0000)
+#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_ACKEN) || ((STATE) == I2C_ACKDIS))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_transfer_direction
+ * @{
+ */
+
+#define I2C_DIRECTION_SEND ((uint8_t)0x00)
+#define I2C_DIRECTION_RECV ((uint8_t)0x01)
+#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_DIRECTION_SEND) || ((DIRECTION) == I2C_DIRECTION_RECV))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_acknowledged_address
+ * @{
+ */
+
+#define I2C_ADDR_MODE_7BIT ((uint16_t)0x4000)
+#define I2C_ADDR_MODE_10BIT ((uint16_t)0xC000)
+#define IS_I2C_ADDR_MODE(ADDRESS) (((ADDRESS) == I2C_ADDR_MODE_7BIT) || ((ADDRESS) == I2C_ADDR_MODE_10BIT))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_registers
+ * @{
+ */
+
+#define I2C_REG_CTRL1 ((uint8_t)0x00)
+#define I2C_REG_CTRL2 ((uint8_t)0x04)
+#define I2C_REG_OADDR1 ((uint8_t)0x08)
+#define I2C_REG_OADDR2 ((uint8_t)0x0C)
+#define I2C_REG_DAT ((uint8_t)0x10)
+#define I2C_REG_STS1 ((uint8_t)0x14)
+#define I2C_REG_STS2 ((uint8_t)0x18)
+#define I2C_REG_CLKCTRL ((uint8_t)0x1C)
+#define I2C_REG_TMRISE ((uint8_t)0x20)
+#define IS_I2C_REG(REGISTER) \
+ (((REGISTER) == I2C_REG_CTRL1) || ((REGISTER) == I2C_REG_CTRL2) || ((REGISTER) == I2C_REG_OADDR1) \
+ || ((REGISTER) == I2C_REG_OADDR2) || ((REGISTER) == I2C_REG_DAT) || ((REGISTER) == I2C_REG_STS1) \
+ || ((REGISTER) == I2C_REG_STS2) || ((REGISTER) == I2C_REG_CLKCTRL) || ((REGISTER) == I2C_REG_TMRISE))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_SMBus_alert_pin_level
+ * @{
+ */
+
+#define I2C_SMBALERT_LOW ((uint16_t)0x2000)
+#define I2C_SMBALERT_HIGH ((uint16_t)0xDFFF)
+#define IS_I2C_SMB_ALERT(ALERT) (((ALERT) == I2C_SMBALERT_LOW) || ((ALERT) == I2C_SMBALERT_HIGH))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_PEC_position
+ * @{
+ */
+
+#define I2C_PEC_POS_NEXT ((uint16_t)0x0800)
+#define I2C_PEC_POS_CURRENT ((uint16_t)0xF7FF)
+#define IS_I2C_PEC_POS(POSITION) (((POSITION) == I2C_PEC_POS_NEXT) || ((POSITION) == I2C_PEC_POS_CURRENT))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_NCAK_position
+ * @{
+ */
+
+#define I2C_NACK_POS_NEXT ((uint16_t)0x0800)
+#define I2C_NACK_POS_CURRENT ((uint16_t)0xF7FF)
+#define IS_I2C_NACK_POS(POSITION) (((POSITION) == I2C_NACK_POS_NEXT) || ((POSITION) == I2C_NACK_POS_CURRENT))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_interrupts_definition
+ * @{
+ */
+
+#define I2C_INT_BUF ((uint16_t)0x0400)
+#define I2C_INT_EVENT ((uint16_t)0x0200)
+#define I2C_INT_ERR ((uint16_t)0x0100)
+#define IS_I2C_CFG_INT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_interrupts_definition
+ * @{
+ */
+
+#define I2C_INT_SMBALERT ((uint32_t)0x01008000)
+#define I2C_INT_TIMOUT ((uint32_t)0x01004000)
+#define I2C_INT_PECERR ((uint32_t)0x01001000)
+#define I2C_INT_OVERRUN ((uint32_t)0x01000800)
+#define I2C_INT_ACKFAIL ((uint32_t)0x01000400)
+#define I2C_INT_ARLOST ((uint32_t)0x01000200)
+#define I2C_INT_BUSERR ((uint32_t)0x01000100)
+#define I2C_INT_TXDATE ((uint32_t)0x06000080)
+#define I2C_INT_RXDATNE ((uint32_t)0x06000040)
+#define I2C_INT_STOPF ((uint32_t)0x02000010)
+#define I2C_INT_ADDR10F ((uint32_t)0x02000008)
+#define I2C_INT_BYTEF ((uint32_t)0x02000004)
+#define I2C_INT_ADDRF ((uint32_t)0x02000002)
+#define I2C_INT_STARTBF ((uint32_t)0x02000001)
+
+#define IS_I2C_CLR_INT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
+
+#define IS_I2C_GET_INT(IT) \
+ (((IT) == I2C_INT_SMBALERT) || ((IT) == I2C_INT_TIMOUT) || ((IT) == I2C_INT_PECERR) || ((IT) == I2C_INT_OVERRUN) \
+ || ((IT) == I2C_INT_ACKFAIL) || ((IT) == I2C_INT_ARLOST) || ((IT) == I2C_INT_BUSERR) || ((IT) == I2C_INT_TXDATE) \
+ || ((IT) == I2C_INT_RXDATNE) || ((IT) == I2C_INT_STOPF) || ((IT) == I2C_INT_ADDR10F) || ((IT) == I2C_INT_BYTEF) \
+ || ((IT) == I2C_INT_ADDRF) || ((IT) == I2C_INT_STARTBF))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_flags_definition
+ * @{
+ */
+
+/**
+ * @brief STS2 register flags
+ */
+
+#define I2C_FLAG_DUALFLAG ((uint32_t)0x00800000)
+#define I2C_FLAG_SMBHADDR ((uint32_t)0x00400000)
+#define I2C_FLAG_SMBDADDR ((uint32_t)0x00200000)
+#define I2C_FLAG_GCALLADDR ((uint32_t)0x00100000)
+#define I2C_FLAG_TRF ((uint32_t)0x00040000)
+#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
+#define I2C_FLAG_MSMODE ((uint32_t)0x00010000)
+
+/**
+ * @brief STS1 register flags
+ */
+
+#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
+#define I2C_FLAG_TIMOUT ((uint32_t)0x10004000)
+#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
+#define I2C_FLAG_OVERRUN ((uint32_t)0x10000800)
+#define I2C_FLAG_ACKFAIL ((uint32_t)0x10000400)
+#define I2C_FLAG_ARLOST ((uint32_t)0x10000200)
+#define I2C_FLAG_BUSERR ((uint32_t)0x10000100)
+#define I2C_FLAG_TXDATE ((uint32_t)0x10000080)
+#define I2C_FLAG_RXDATNE ((uint32_t)0x10000040)
+#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
+#define I2C_FLAG_ADDR10F ((uint32_t)0x10000008)
+#define I2C_FLAG_BYTEF ((uint32_t)0x10000004)
+#define I2C_FLAG_ADDRF ((uint32_t)0x10000002)
+#define I2C_FLAG_STARTBF ((uint32_t)0x10000001)
+
+#define IS_I2C_CLR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
+
+#define IS_I2C_GET_FLAG(FLAG) \
+ (((FLAG) == I2C_FLAG_DUALFLAG) || ((FLAG) == I2C_FLAG_SMBHADDR) || ((FLAG) == I2C_FLAG_SMBDADDR) \
+ || ((FLAG) == I2C_FLAG_GCALLADDR) || ((FLAG) == I2C_FLAG_TRF) || ((FLAG) == I2C_FLAG_BUSY) \
+ || ((FLAG) == I2C_FLAG_MSMODE) || ((FLAG) == I2C_FLAG_SMBALERT) || ((FLAG) == I2C_FLAG_TIMOUT) \
+ || ((FLAG) == I2C_FLAG_PECERR) || ((FLAG) == I2C_FLAG_OVERRUN) || ((FLAG) == I2C_FLAG_ACKFAIL) \
+ || ((FLAG) == I2C_FLAG_ARLOST) || ((FLAG) == I2C_FLAG_BUSERR) || ((FLAG) == I2C_FLAG_TXDATE) \
+ || ((FLAG) == I2C_FLAG_RXDATNE) || ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADDR10F) \
+ || ((FLAG) == I2C_FLAG_BYTEF) || ((FLAG) == I2C_FLAG_ADDRF) || ((FLAG) == I2C_FLAG_STARTBF))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Events
+ * @{
+ */
+
+/*========================================
+
+ I2C Master Events (Events grouped in order of communication)
+ ==========================================*/
+/**
+ * @brief Communication start
+ *
+ * After sending the START condition (I2C_GenerateStart() function) the master
+ * has to wait for this event. It means that the Start condition has been correctly
+ * released on the I2C bus (the bus is free, no other devices is communicating).
+ *
+ */
+/* Master mode */
+#define I2C_ROLE_MASTER ((uint32_t)0x00010000) /* MSMODE */
+/* --EV5 */
+#define I2C_EVT_MASTER_MODE_FLAG ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
+
+/**
+ * @brief Address Acknowledge
+ *
+ * After checking on EV5 (start condition correctly released on the bus), the
+ * master sends the address of the slave(s) with which it will communicate
+ * (I2C_SendAddr7bit() function, it also determines the direction of the communication:
+ * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
+ * his address. If an acknowledge is sent on the bus, one of the following events will
+ * be set:
+ *
+ * 1) In case of Master Receiver (7-bit addressing): the I2C_EVT_MASTER_RXMODE_FLAG
+ * event is set.
+ *
+ * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVT_MASTER_TXMODE_FLAG
+ * is set
+ *
+ * 3) In case of 10-Bit addressing mode, the master (just after generating the START
+ * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
+ * function). Then master should wait on EV9. It means that the 10-bit addressing
+ * header has been correctly sent on the bus. Then master should send the second part of
+ * the 10-bit address (LSB) using the function I2C_SendAddr7bit(). Then master
+ * should wait for event EV6.
+ *
+ */
+
+/* --EV6 */
+#define I2C_EVT_MASTER_TXMODE_FLAG ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
+#define I2C_EVT_MASTER_RXMODE_FLAG ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
+/* --EV9 */
+#define I2C_EVT_MASTER_MODE_ADDRESS10_FLAG ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
+
+/**
+ * @brief Communication events
+ *
+ * If a communication is established (START condition generated and slave address
+ * acknowledged) then the master has to check on one of the following events for
+ * communication procedures:
+ *
+ * 1) Master Receiver mode: The master has to wait on the event EV7 then to read
+ * the data received from the slave (I2C_RecvData() function).
+ *
+ * 2) Master Transmitter mode: The master has to send data (I2C_SendData()
+ * function) then to wait on event EV8 or EV8_2.
+ * These two events are similar:
+ * - EV8 means that the data has been written in the data register and is
+ * being shifted out.
+ * - EV8_2 means that the data has been physically shifted out and output
+ * on the bus.
+ * In most cases, using EV8 is sufficient for the application.
+ * Using EV8_2 leads to a slower communication but ensure more reliable test.
+ * EV8_2 is also more suitable than EV8 for testing on the last data transmission
+ * (before Stop condition generation).
+ *
+ * @note In case the user software does not guarantee that this event EV7 is
+ * managed before the current byte end of transfer, then user may check on EV7
+ * and BTF flag at the same time (ie. (I2C_EVT_MASTER_DATA_RECVD_FLAG | I2C_FLAG_BYTEF)).
+ * In this case the communication may be slower.
+ *
+ */
+
+/* Master RECEIVER mode -----------------------------*/
+/* --EV7 */
+#define I2C_EVT_MASTER_DATA_RECVD_FLAG ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
+/* EV7x shifter register full */
+#define I2C_EVT_MASTER_SFT_DATA_RECVD_FLAG ((uint32_t)0x00030044) /* BUSY, MSMODE, BSF and RXDATNE flags */
+
+/* Master TRANSMITTER mode --------------------------*/
+/* --EV8 */
+#define I2C_EVT_MASTER_DATA_SENDING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
+/* --EV8_2 */
+#define I2C_EVT_MASTER_DATA_SENDED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
+
+/*========================================
+
+ I2C Slave Events (Events grouped in order of communication)
+ ==========================================*/
+
+/**
+ * @brief Communication start events
+ *
+ * Wait on one of these events at the start of the communication. It means that
+ * the I2C peripheral detected a Start condition on the bus (generated by master
+ * device) followed by the peripheral address. The peripheral generates an ACK
+ * condition on the bus (if the acknowledge feature is enabled through function
+ * I2C_ConfigAck()) and the events listed above are set :
+ *
+ * 1) In normal case (only one address managed by the slave), when the address
+ * sent by the master matches the own address of the peripheral (configured by
+ * OwnAddr1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
+ * (where XXX could be TRANSMITTER or RECEIVER).
+ *
+ * 2) In case the address sent by the master matches the second address of the
+ * peripheral (configured by the function I2C_ConfigOwnAddr2() and enabled
+ * by the function I2C_EnableDualAddr()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
+ * (where XXX could be TRANSMITTER or RECEIVER) are set.
+ *
+ * 3) In case the address sent by the master is General Call (address 0x00) and
+ * if the General Call is enabled for the peripheral (using function I2C_EnableGeneralCall())
+ * the following event is set I2C_EVT_SLAVE_GCALLADDR_MATCHED.
+ *
+ */
+
+/* --EV1 (all the events below are variants of EV1) */
+/* 1) Case of One Single Address managed by the slave */
+#define I2C_EVT_SLAVE_RECV_ADDR_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
+#define I2C_EVT_SLAVE_SEND_ADDR_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
+
+/* 2) Case of Dual address managed by the slave */
+#define I2C_EVT_SLAVE_RECV_ADDR2_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
+#define I2C_EVT_SLAVE_SEND_ADDR2_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
+
+/* 3) Case of General Call enabled for the slave */
+#define I2C_EVT_SLAVE_GCALLADDR_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
+
+/**
+ * @brief Communication events
+ *
+ * Wait on one of these events when EV1 has already been checked and:
+ *
+ * - Slave RECEIVER mode:
+ * - EV2: When the application is expecting a data byte to be received.
+ * - EV4: When the application is expecting the end of the communication: master
+ * sends a stop condition and data transmission is stopped.
+ *
+ * - Slave Transmitter mode:
+ * - EV3: When a byte has been transmitted by the slave and the application is expecting
+ * the end of the byte transmission. The two events I2C_EVT_SLAVE_DATA_SENDED and
+ * I2C_EVT_SLAVE_DATA_SENDING are similar. The second one can optionally be
+ * used when the user software doesn't guarantee the EV3 is managed before the
+ * current byte end of transfer.
+ * - EV3_2: When the master sends a NACK in order to tell slave that data transmission
+ * shall end (before sending the STOP condition). In this case slave has to stop sending
+ * data bytes and expect a Stop condition on the bus.
+ *
+ * @note In case the user software does not guarantee that the event EV2 is
+ * managed before the current byte end of transfer, then user may check on EV2
+ * and BTF flag at the same time (ie. (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_BYTEF)).
+ * In this case the communication may be slower.
+ *
+ */
+
+/* Slave RECEIVER mode --------------------------*/
+/* --EV2 */
+#define I2C_EVT_SLAVE_DATA_RECVD ((uint32_t)0x00020040) /* BUSY and RXNE flags */
+/* --EV2x */
+#define I2C_EVT_SLAVE_DATA_RECVD_NOBUSY ((uint32_t)0x00000040) /* no BUSY and RXDATNE flags */
+/* --EV4 */
+#define I2C_EVT_SLAVE_STOP_RECVD ((uint32_t)0x00000010) /* STOPF flag */
+
+/* Slave TRANSMITTER mode -----------------------*/
+/* --EV3 */
+#define I2C_EVT_SLAVE_DATA_SENDED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
+#define I2C_EVT_SLAVE_DATA_SENDING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
+/* --EV3_2 */
+#define I2C_EVT_SLAVE_ACK_MISS ((uint32_t)0x00000400) /* AF flag */
+
+/*=========================== End of Events Description ==========================================*/
+
+#define IS_I2C_EVT(EVENT) \
+ (((EVENT) == I2C_EVT_SLAVE_SEND_ADDR_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_RECV_ADDR_MATCHED) \
+ || ((EVENT) == I2C_EVT_SLAVE_SEND_ADDR2_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_RECV_ADDR2_MATCHED) \
+ || ((EVENT) == I2C_EVT_SLAVE_GCALLADDR_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_DATA_RECVD) \
+ || ((EVENT) == (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_DUALFLAG)) \
+ || ((EVENT) == (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_GCALLADDR)) || ((EVENT) == I2C_EVT_SLAVE_DATA_SENDED) \
+ || ((EVENT) == (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_DUALFLAG)) \
+ || ((EVENT) == (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_GCALLADDR)) || ((EVENT) == I2C_EVT_SLAVE_STOP_RECVD) \
+ || ((EVENT) == I2C_EVT_MASTER_MODE_FLAG) || ((EVENT) == I2C_EVT_MASTER_TXMODE_FLAG) \
+ || ((EVENT) == I2C_EVT_MASTER_RXMODE_FLAG) || ((EVENT) == I2C_EVT_MASTER_DATA_RECVD_FLAG) \
+ || ((EVENT) == I2C_EVT_MASTER_DATA_SENDED) || ((EVENT) == I2C_EVT_MASTER_DATA_SENDING) \
+ || ((EVENT) == I2C_EVT_MASTER_MODE_ADDRESS10_FLAG) || ((EVENT) == I2C_EVT_SLAVE_ACK_MISS))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_own_address1
+ * @{
+ */
+
+#define IS_I2C_OWN_ADDR1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_clock_speed
+ * @{
+ */
+
+//#define IS_I2C_CLK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
+#define IS_I2C_CLK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 1000000))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Exported_Functions
+ * @{
+ */
+
+void I2C_DeInit(I2C_Module* I2Cx);
+void I2C_Init(I2C_Module* I2Cx, I2C_InitType* I2C_InitStruct);
+void I2C_InitStruct(I2C_InitType* I2C_InitStruct);
+void I2C_Enable(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_EnableDMA(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_EnableDmaLastSend(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_GenerateStart(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_GenerateStop(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_ConfigAck(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_ConfigOwnAddr2(I2C_Module* I2Cx, uint8_t Address);
+void I2C_EnableDualAddr(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_EnableGeneralCall(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_ConfigInt(I2C_Module* I2Cx, uint16_t I2C_IT, FunctionalState Cmd);
+void I2C_SendData(I2C_Module* I2Cx, uint8_t Data);
+uint8_t I2C_RecvData(I2C_Module* I2Cx);
+void I2C_SendAddr7bit(I2C_Module* I2Cx, uint8_t Address, uint8_t I2C_Direction);
+uint16_t I2C_GetRegister(I2C_Module* I2Cx, uint8_t I2C_Register);
+void I2C_EnableSoftwareReset(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_ConfigNackLocation(I2C_Module* I2Cx, uint16_t I2C_NACKPosition);
+void I2C_ConfigSmbusAlert(I2C_Module* I2Cx, uint16_t I2C_SMBusAlert);
+void I2C_SendPEC(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_ConfigPecLocation(I2C_Module* I2Cx, uint16_t I2C_PECPosition);
+void I2C_ComputePec(I2C_Module* I2Cx, FunctionalState Cmd);
+uint8_t I2C_GetPec(I2C_Module* I2Cx);
+void I2C_EnableArp(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_EnableExtendClk(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_ConfigFastModeDutyCycle(I2C_Module* I2Cx, uint16_t FmDutyCycle);
+
+/**
+ * @brief
+ ****************************************************************************************
+ *
+ * I2C State Monitoring Functions
+ *
+ ****************************************************************************************
+ * This I2C driver provides three different ways for I2C state monitoring
+ * depending on the application requirements and constraints:
+ *
+ *
+ * 1) Basic state monitoring:
+ * Using I2C_CheckEvent() function:
+ * It compares the status registers (STS1 and STS2) content to a given event
+ * (can be the combination of one or more flags).
+ * It returns SUCCESS if the current status includes the given flags
+ * and returns ERROR if one or more flags are missing in the current status.
+ * - When to use:
+ * - This function is suitable for most applications as well as for startup
+ * activity since the events are fully described in the product reference manual
+ * (RM0008).
+ * - It is also suitable for users who need to define their own events.
+ * - Limitations:
+ * - If an error occurs (ie. error flags are set besides to the monitored flags),
+ * the I2C_CheckEvent() function may return SUCCESS despite the communication
+ * hold or corrupted real state.
+ * In this case, it is advised to use error interrupts to monitor the error
+ * events and handle them in the interrupt IRQ handler.
+ *
+ * @note
+ * For error management, it is advised to use the following functions:
+ * - I2C_ConfigInt() to configure and enable the error interrupts (I2C_INT_ERR).
+ * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
+ * Where x is the peripheral instance (I2C1, I2C2 ...)
+ * - I2C_GetFlag() or I2C_GetIntStatus() to be called into I2Cx_ER_IRQHandler()
+ * in order to determine which error occurred.
+ * - I2C_ClrFlag() or I2C_ClrIntPendingBit() and/or I2C_EnableSoftwareReset()
+ * and/or I2C_GenerateStop() in order to clear the error flag and source,
+ * and return to correct communication status.
+ *
+ *
+ * 2) Advanced state monitoring:
+ * Using the function I2C_GetLastEvent() which returns the image of both status
+ * registers in a single word (uint32_t) (Status Register 2 value is shifted left
+ * by 16 bits and concatenated to Status Register 1).
+ * - When to use:
+ * - This function is suitable for the same applications above but it allows to
+ * overcome the limitations of I2C_GetFlag() function (see below).
+ * The returned value could be compared to events already defined in the
+ * library (n32l40x_i2c.h) or to custom values defined by user.
+ * - This function is suitable when multiple flags are monitored at the same time.
+ * - At the opposite of I2C_CheckEvent() function, this function allows user to
+ * choose when an event is accepted (when all events flags are set and no
+ * other flags are set or just when the needed flags are set like
+ * I2C_CheckEvent() function).
+ * - Limitations:
+ * - User may need to define his own events.
+ * - Same remark concerning the error management is applicable for this
+ * function if user decides to check only regular communication flags (and
+ * ignores error flags).
+ *
+ *
+ * 3) Flag-based state monitoring:
+ * Using the function I2C_GetFlag() which simply returns the status of
+ * one single flag (ie. I2C_FLAG_RXDATNE ...).
+ * - When to use:
+ * - This function could be used for specific applications or in debug phase.
+ * - It is suitable when only one flag checking is needed (most I2C events
+ * are monitored through multiple flags).
+ * - Limitations:
+ * - When calling this function, the Status register is accessed. Some flags are
+ * cleared when the status register is accessed. So checking the status
+ * of one Flag, may clear other ones.
+ * - Function may need to be called twice or more in order to monitor one
+ * single event.
+ *
+ */
+
+/**
+ *
+ * 1) Basic state monitoring
+ *******************************************************************************
+ */
+ErrorStatus I2C_CheckEvent(I2C_Module* I2Cx, uint32_t I2C_EVENT);
+/**
+ *
+ * 2) Advanced state monitoring
+ *******************************************************************************
+ */
+uint32_t I2C_GetLastEvent(I2C_Module* I2Cx);
+/**
+ *
+ * 3) Flag-based state monitoring
+ *******************************************************************************
+ */
+FlagStatus I2C_GetFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG);
+/**
+ *
+ *******************************************************************************
+ */
+
+void I2C_ClrFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG);
+INTStatus I2C_GetIntStatus(I2C_Module* I2Cx, uint32_t I2C_IT);
+void I2C_ClrIntPendingBit(I2C_Module* I2Cx, uint32_t I2C_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32L40X_I2C_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_iwdg.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_iwdg.h
new file mode 100644
index 0000000000..ce37ebf7cd
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_iwdg.h
@@ -0,0 +1,145 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_iwdg.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L40X_IWDG_H__
+#define __N32L40X_IWDG_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l40x.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup IWDG
+ * @{
+ */
+
+/** @addtogroup IWDG_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup IWDG_WriteAccess
+ * @{
+ */
+
+#define IWDG_WRITE_ENABLE ((uint16_t)0x5555)
+#define IWDG_WRITE_DISABLE ((uint16_t)0x0000)
+#define IS_IWDG_WRITE(ACCESS) (((ACCESS) == IWDG_WRITE_ENABLE) || ((ACCESS) == IWDG_WRITE_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_prescaler
+ * @{
+ */
+
+#define IWDG_PRESCALER_DIV4 ((uint8_t)0x00)
+#define IWDG_PRESCALER_DIV8 ((uint8_t)0x01)
+#define IWDG_PRESCALER_DIV16 ((uint8_t)0x02)
+#define IWDG_PRESCALER_DIV32 ((uint8_t)0x03)
+#define IWDG_PRESCALER_DIV64 ((uint8_t)0x04)
+#define IWDG_PRESCALER_DIV128 ((uint8_t)0x05)
+#define IWDG_PRESCALER_DIV256 ((uint8_t)0x06)
+#define IS_IWDG_PRESCALER_DIV(PRESCALER) \
+ (((PRESCALER) == IWDG_PRESCALER_DIV4) || ((PRESCALER) == IWDG_PRESCALER_DIV8) \
+ || ((PRESCALER) == IWDG_PRESCALER_DIV16) || ((PRESCALER) == IWDG_PRESCALER_DIV32) \
+ || ((PRESCALER) == IWDG_PRESCALER_DIV64) || ((PRESCALER) == IWDG_PRESCALER_DIV128) \
+ || ((PRESCALER) == IWDG_PRESCALER_DIV256))
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Flag
+ * @{
+ */
+
+#define IWDG_PVU_FLAG ((uint16_t)0x0001)
+#define IWDG_CRVU_FLAG ((uint16_t)0x0002)
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_PVU_FLAG) || ((FLAG) == IWDG_CRVU_FLAG))
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Exported_Functions
+ * @{
+ */
+
+void IWDG_WriteConfig(uint16_t IWDG_WriteAccess);
+void IWDG_SetPrescalerDiv(uint8_t IWDG_Prescaler);
+void IWDG_CntReload(uint16_t Reload);
+void IWDG_ReloadKey(void);
+void IWDG_Enable(void);
+FlagStatus IWDG_GetStatus(uint16_t IWDG_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32L40X_IWDG_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_lcd.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_lcd.h
new file mode 100644
index 0000000000..e0e6feb29e
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_lcd.h
@@ -0,0 +1,735 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_lcd.hd
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+
+#ifndef __N32L40X_LCD_H__
+#define __N32L40X_LCD_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "n32l40x.h"
+/** @addtogroup N32L40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup LCD
+ * @{
+ */
+
+/* LCD Exported constants --------------------------------------------------------*/
+/** @addtogroup LCD_Exported_Constants LCD Exported Constants
+ * @{
+ */
+
+/**
+ * @brief LCD error code
+ */
+typedef enum {
+ LCD_ERROR_OK = 0x00, /*!< No error */
+ LCD_ERROR_FCRSF = 0x01, /*!< Synchro flag error */
+ LCD_ERROR_UDR = 0x02, /*!< Update display request flag error */
+ LCD_ERROR_UDD = 0x03, /*!< Update display done flag error */
+ LCD_ERROR_ENSTS = 0x04, /*!< LCD enabled status flag error */
+ LCD_ERROR_RDY = 0x05, /*!< LCD VLCD ready flag error */
+ LCD_ERROR_PARAM = 0x06, /*!< LCD function parameter error */
+ LCD_ERROR_CLK = 0x07, /*!< LCD clock source fail error */
+}LCD_ErrorTypeDef;
+
+/**
+* @brief LCD normal timeout
+*/
+#define LCD_TIME_OUT (0x01000000)
+
+/**
+ * @defgroup LCD_Clock_Source
+ */
+#define LCD_CLK_SRC_LSI (RCC_RTCCLK_SRC_LSI) /*!< LSI*/
+#define LCD_CLK_SRC_LSE (RCC_LSE_ENABLE|RCC_RTCCLK_SRC_LSE) /*!< LSE */
+#define LCD_CLK_SRC_LSE_BYPASS (RCC_LSE_BYPASS|RCC_RTCCLK_SRC_LSE) /*!< LSE bypass */
+#define LCD_CLK_SRC_HSE_DIV32 (RCC_HSE_ENABLE|RCC_RTCCLK_SRC_HSE_DIV32) /*!< HSE */
+#define LCD_CLK_SRC_HSE_BYPASS_DIV32 (RCC_HSE_BYPASS|RCC_RTCCLK_SRC_HSE_DIV32) /*!< HSE bypass */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_RAMRegister
+ */
+#define LCD_RAM1_COM0 (0x00000000U)
+#define LCD_RAM2_COM0 (0x00000001U)
+#define LCD_RAM1_COM1 (0x00000002U)
+#define LCD_RAM2_COM1 (0x00000003U)
+#define LCD_RAM1_COM2 (0x00000004U)
+#define LCD_RAM2_COM2 (0x00000005U)
+#define LCD_RAM1_COM3 (0x00000006U)
+#define LCD_RAM2_COM3 (0x00000007U)
+#define LCD_RAM1_COM4 (0x00000008U)
+#define LCD_RAM2_COM4 (0x00000009U)
+#define LCD_RAM1_COM5 (0x0000000AU)
+#define LCD_RAM2_COM5 (0x0000000BU)
+#define LCD_RAM1_COM6 (0x0000000CU)
+#define LCD_RAM2_COM6 (0x0000000DU)
+#define LCD_RAM1_COM7 (0x0000000EU)
+#define LCD_RAM2_COM7 (0x0000000FU)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_Prescaler
+ */
+#define LCD_PRESCALER_1 (0x00000000U) /*!< CLKPS = LCDCLK */
+#define LCD_PRESCALER_2 (0x1UL << LCD_FCTRL_PRES_Pos) /*!< 0x00400000U CLKPS = LCDCLK/2 */
+#define LCD_PRESCALER_4 (0x2UL << LCD_FCTRL_PRES_Pos) /*!< 0x00800000U CLKPS = LCDCLK/4 */
+#define LCD_PRESCALER_8 (0x3UL << LCD_FCTRL_PRES_Pos) /*!< 0x00C00000U CLKPS = LCDCLK/8 */
+#define LCD_PRESCALER_16 (0x4UL << LCD_FCTRL_PRES_Pos) /*!< 0x01000000U CLKPS = LCDCLK/16 */
+#define LCD_PRESCALER_32 (0x5UL << LCD_FCTRL_PRES_Pos) /*!< 0x01400000U CLKPS = LCDCLK/32 */
+#define LCD_PRESCALER_64 (0x6UL << LCD_FCTRL_PRES_Pos) /*!< 0x01800000U CLKPS = LCDCLK/64 */
+#define LCD_PRESCALER_128 (0x7UL << LCD_FCTRL_PRES_Pos) /*!< 0x01C00000U CLKPS = LCDCLK/128 */
+#define LCD_PRESCALER_256 (0x8UL << LCD_FCTRL_PRES_Pos) /*!< 0x02000000U CLKPS = LCDCLK/256 */
+#define LCD_PRESCALER_512 (0x9UL << LCD_FCTRL_PRES_Pos) /*!< 0x02400000U CLKPS = LCDCLK/512 */
+#define LCD_PRESCALER_1024 (0xAUL << LCD_FCTRL_PRES_Pos) /*!< 0x02800000U CLKPS = LCDCLK/1024 */
+#define LCD_PRESCALER_2048 (0xBUL << LCD_FCTRL_PRES_Pos) /*!< 0x02C00000U CLKPS = LCDCLK/2048 */
+#define LCD_PRESCALER_4096 (0xCUL << LCD_FCTRL_PRES_Pos) /*!< 0x03000000U CLKPS = LCDCLK/4096 */
+#define LCD_PRESCALER_8192 (0xDUL << LCD_FCTRL_PRES_Pos) /*!< 0x03400000U CLKPS = LCDCLK/8192 */
+#define LCD_PRESCALER_16384 (0xEUL << LCD_FCTRL_PRES_Pos) /*!< 0x03800000U CLKPS = LCDCLK/16384 */
+#define LCD_PRESCALER_32768 (0xFUL << LCD_FCTRL_PRES_Pos) /*!< 0x03C00000U CLKPS = LCDCLK/32768 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_Divider
+ */
+#define LCD_DIV_16 (0x00000000U) /*!< CLKDIV = CLKPS/(16) */
+#define LCD_DIV_17 (0x1UL << LCD_FCTRL_DIV_Pos) /*!< 0x00040000U CLKDIV = CLKPS/(17) */
+#define LCD_DIV_18 (0x2UL << LCD_FCTRL_DIV_Pos) /*!< 0x00080000U CLKDIV = CLKPS/(18) */
+#define LCD_DIV_19 (0x3UL << LCD_FCTRL_DIV_Pos) /*!< 0x000C0000U CLKDIV = CLKPS/(19) */
+#define LCD_DIV_20 (0x4UL << LCD_FCTRL_DIV_Pos) /*!< 0x00100000U CLKDIV = CLKPS/(20) */
+#define LCD_DIV_21 (0x5UL << LCD_FCTRL_DIV_Pos) /*!< 0x00140000U CLKDIV = CLKPS/(21) */
+#define LCD_DIV_22 (0x6UL << LCD_FCTRL_DIV_Pos) /*!< 0x00180000U CLKDIV = CLKPS/(22) */
+#define LCD_DIV_23 (0x7UL << LCD_FCTRL_DIV_Pos) /*!< 0x001C0000U CLKDIV = CLKPS/(23) */
+#define LCD_DIV_24 (0x8UL << LCD_FCTRL_DIV_Pos) /*!< 0x00200000U CLKDIV = CLKPS/(24) */
+#define LCD_DIV_25 (0x9UL << LCD_FCTRL_DIV_Pos) /*!< 0x00240000U CLKDIV = CLKPS/(25) */
+#define LCD_DIV_26 (0xAUL << LCD_FCTRL_DIV_Pos) /*!< 0x00280000U CLKDIV = CLKPS/(26) */
+#define LCD_DIV_27 (0xBUL << LCD_FCTRL_DIV_Pos) /*!< 0x002C0000U CLKDIV = CLKPS/(27) */
+#define LCD_DIV_28 (0xCUL << LCD_FCTRL_DIV_Pos) /*!< 0x00300000U CLKDIV = CLKPS/(28) */
+#define LCD_DIV_29 (0xDUL << LCD_FCTRL_DIV_Pos) /*!< 0x00340000U CLKDIV = CLKPS/(29) */
+#define LCD_DIV_30 (0xEUL << LCD_FCTRL_DIV_Pos) /*!< 0x00380000U CLKDIV = CLKPS/(30) */
+#define LCD_DIV_31 (0xFUL << LCD_FCTRL_DIV_Pos) /*!< 0x003C0000U CLKDIV = CLKPS/(31) */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_Duty
+ */
+#define LCD_DUTY_STATIC (0x00000000U) /*!< Static duty */
+#define LCD_DUTY_1_2 (0x1UL << LCD_CTRL_DUTY_Pos) /*!< 0x00000004U 1/2 duty */
+#define LCD_DUTY_1_3 (0x2UL << LCD_CTRL_DUTY_Pos) /*!< 0x00000004U 1/3 duty */
+#define LCD_DUTY_1_4 (0x3UL << LCD_CTRL_DUTY_Pos) /*!< 0x00000004U 1/4 duty */
+#define LCD_DUTY_1_8 (0x4UL << LCD_CTRL_DUTY_Pos) /*!< 0x00000004U 1/8 duty */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_Bias
+ */
+#define LCD_BIAS_1_2 (0x00000000U) /*!< 1/2 Bias */
+#define LCD_BIAS_1_3 (0x1UL << LCD_CTRL_BIAS_Pos) /*!< 0x00000020U 1/3 Bias */
+#define LCD_BIAS_1_4 (0x2UL << LCD_CTRL_BIAS_Pos) /*!< 0x00000040U 1/4 Bias */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_Voltage_source
+ */
+#define LCD_VOLTAGESOURCE_INTERNAL (0x00000000U) /*!< Internal voltage source for the LCD */
+#define LCD_VOLTAGESOURCE_EXTERNAL (LCD_CTRL_VSEL) /*!< External voltage source for the LCD */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_Contrast
+ */
+#define LCD_CONTRASTLEVEL_0 (0x00000000U) /*!< Maximum Voltage = 2.60V */
+#define LCD_CONTRASTLEVEL_1 (0x1UL << LCD_FCTRL_CONTRAST_Pos) /*!< 0x00000400U Maximum Voltage = 2.73V */
+#define LCD_CONTRASTLEVEL_2 (0x2UL << LCD_FCTRL_CONTRAST_Pos) /*!< 0x00000800U Maximum Voltage = 2.86V */
+#define LCD_CONTRASTLEVEL_3 (0x3UL << LCD_FCTRL_CONTRAST_Pos) /*!< 0x00000C00U Maximum Voltage = 2.99V */
+#define LCD_CONTRASTLEVEL_4 (0x4UL << LCD_FCTRL_CONTRAST_Pos) /*!< 0x00001000U Maximum Voltage = 3.12V */
+#define LCD_CONTRASTLEVEL_5 (0x5UL << LCD_FCTRL_CONTRAST_Pos) /*!< 0x00001400U Maximum Voltage = 3.26V */
+#define LCD_CONTRASTLEVEL_6 (0x6UL << LCD_FCTRL_CONTRAST_Pos) /*!< 0x00001800U Maximum Voltage = 3.40V */
+#define LCD_CONTRASTLEVEL_7 (0x7UL << LCD_FCTRL_CONTRAST_Pos) /*!< 0x00001C00U Maximum Voltage = 3.55V */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_DeadTime
+ */
+#define LCD_DEADTIME_0 (0x00000000U) /*!< No dead Time */
+#define LCD_DEADTIME_1 (0x1UL << LCD_FCTRL_DEAD_Pos) /*!< 0x00000080U One Phase between different couple of Frame */
+#define LCD_DEADTIME_2 (0x2UL << LCD_FCTRL_DEAD_Pos) /*!< 0x00000100U Two Phase between different couple of Frame */
+#define LCD_DEADTIME_3 (0x3UL << LCD_FCTRL_DEAD_Pos) /*!< 0x00000180UThree Phase between different couple of Frame */
+#define LCD_DEADTIME_4 (0x4UL << LCD_FCTRL_DEAD_Pos) /*!< 0x00000200UFour Phase between different couple of Frame */
+#define LCD_DEADTIME_5 (0x5UL << LCD_FCTRL_DEAD_Pos) /*!< 0x00000280UFive Phase between different couple of Frame */
+#define LCD_DEADTIME_6 (0x6UL << LCD_FCTRL_DEAD_Pos) /*!< 0x00000300USix Phase between different couple of Frame */
+#define LCD_DEADTIME_7 (0x7UL << LCD_FCTRL_DEAD_Pos) /*!< 0x00000380USeven Phase between different couple of Frame */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_PulseOnDuration
+ */
+#define LCD_PULSEONDURATION_0 (0x00000000U) /*!< Pulse ON duration = 0 pulse */
+#define LCD_PULSEONDURATION_1 (0x1U << LCD_FCTRL_PULSEON_Pos) /*!< 0x00000010U Pulse ON duration = 1/CK_PS */
+#define LCD_PULSEONDURATION_2 (0x2U << LCD_FCTRL_PULSEON_Pos) /*!< 0x00000020U Pulse ON duration = 2/CK_PS */
+#define LCD_PULSEONDURATION_3 (0x3U << LCD_FCTRL_PULSEON_Pos) /*!< 0x00000030U Pulse ON duration = 3/CK_PS */
+#define LCD_PULSEONDURATION_4 (0x4U << LCD_FCTRL_PULSEON_Pos) /*!< 0x00000040U Pulse ON duration = 4/CK_PS */
+#define LCD_PULSEONDURATION_5 (0x5U << LCD_FCTRL_PULSEON_Pos) /*!< 0x00000050U Pulse ON duration = 5/CK_PS */
+#define LCD_PULSEONDURATION_6 (0x6U << LCD_FCTRL_PULSEON_Pos) /*!< 0x00000060U Pulse ON duration = 6/CK_PS */
+#define LCD_PULSEONDURATION_7 (0x7U << LCD_FCTRL_PULSEON_Pos) /*!< 0x00000070U Pulse ON duration = 7/CK_PS */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_HighDrive
+ */
+#define LCD_HIGHDRIVE_DISABLE (0x00000000U) /*!< High drive disabled */
+#define LCD_HIGHDRIVE_ENABLE (LCD_FCTRL_HDEN) /*!< High drive enabled */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_HighDrive_Buffer
+ */
+#define LCD_HIGHDRIVEBUFFER_DISABLE (0x00000000U) /*!< High drive buffer disabled */
+#define LCD_HIGHDRIVEBUFFER_ENABLE (LCD_CTRL_BUFEN) /*!< High drive buffer enabled */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_Blink_Mode
+ */
+#define LCD_BLINKMODE_OFF (0x00000000U) /*!< Blink disable */
+#define LCD_BLINKMODE_SEG0_COM0 (0x1UL << LCD_FCTRL_BLINK_Pos) /*!< 0x00010000U Blink enabled on SEG[0], COM[0] (1 pixel) */
+#define LCD_BLINKMODE_SEG0_ALLCOM (0x2UL << LCD_FCTRL_BLINK_Pos) /*!< 0x00020000U Blink enabled on SEG[0], all COM (up to 8 pixels according to the programmed duty) */
+#define LCD_BLINKMODE_ALLSEG_ALLCOM (0x3UL << LCD_FCTRL_BLINK_Pos) /*!< 0x00030000U Blink enabled on all SEG and all COM (all pixels) */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_Blink_Frequency
+ */
+#define LCD_BLINKFREQ_DIV_8 (0x00000000U) /*!< The Blink frequency = fck_div/8 */
+#define LCD_BLINKFREQ_DIV_16 (0x1UL << LCD_FCTRL_BLINKF_Pos) /*!< 0x00002000U The Blink frequency = fck_div/16 */
+#define LCD_BLINKFREQ_DIV_32 (0x2UL << LCD_FCTRL_BLINKF_Pos) /*!< 0x00004000U The Blink frequency = fck_div/32 */
+#define LCD_BLINKFREQ_DIV_64 (0x3UL << LCD_FCTRL_BLINKF_Pos) /*!< 0x00006000U The Blink frequency = fck_div/64 */
+#define LCD_BLINKFREQ_DIV_128 (0x4UL << LCD_FCTRL_BLINKF_Pos) /*!< 0x00008000U The Blink frequency = fck_div/128 */
+#define LCD_BLINKFREQ_DIV_256 (0x5UL << LCD_FCTRL_BLINKF_Pos) /*!< 0x0000A000U The Blink frequency = fck_div/256 */
+#define LCD_BLINKFREQ_DIV_512 (0x6UL << LCD_FCTRL_BLINKF_Pos) /*!< 0x0000C000U The Blink frequency = fck_div/512 */
+#define LCD_BLINKFREQ_DIV_1024 (0x7UL << LCD_FCTRL_BLINKF_Pos) /*!< 0x0000E000U The Blink frequency = fck_div/1024 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_MuxSegment
+ */
+#define LCD_MUXSEGMENT_DISABLE (0x00000000U) /*!< Mux segment disabled */
+#define LCD_MUXSEGMENT_ENABLE (LCD_CTRL_MUXSEG) /*!< Mux segment enabled */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_Interrupt
+ */
+#define LCD_IT_UDD (LCD_FCTRL_UDDIE) /*!< Update display done interrupt */
+#define LCD_IT_SOF (LCD_FCTRL_SOFIE) /*!< Start of frame interrupt */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_Flag
+ */
+#define LCD_FLAG_ENSTS (LCD_STS_ENSTS) /*!< LCD enable flag*/
+#define LCD_FLAG_SOF (LCD_STS_SOF) /*!< LCD start of frame event flag*/
+#define LCD_FLAG_UDR (LCD_STS_UDR) /*!< Update display request Flag*/
+#define LCD_FLAG_UDD (LCD_STS_UDD) /*!< Update display done event flag */
+#define LCD_FLAG_RDY (LCD_STS_RDY) /*!< Ready flag */
+#define LCD_FLAG_FCRSF (LCD_STS_FCRSF) /*!< LCD frame control register synchronization flag */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_Flag_Clear
+ */
+#define LCD_FLAG_SOF_CLEAR (LCD_CLR_SOFCLR) /*!< Clear LCD start of frame event flag*/
+#define LCD_FLAG_UDD_CLEAR (LCD_CLR_UDDCLR) /*!< Clear Update display done event flag */
+/**
+ * @}
+ */
+
+
+/* LCD Exported macros -----------------------------------------------------------*/
+/** @defgroup LCD_Exported_Macros LCD Exported Macros
+ * @{
+ */
+
+/** @brief Enable the LCD peripheral.
+ * @param None
+ * @retval None
+ */
+#define __LCD_ENABLE() SET_BIT(LCD->CTRL, LCD_CTRL_LCDEN)
+
+/** @brief Disable the LCD peripheral.
+ * @param None
+ * @retval None
+ */
+#define __LCD_DISABLE() CLEAR_BIT(LCD->CTRL, LCD_CTRL_LCDEN)
+
+/** @brief Enable the LCD voltage output buffer.
+ * @param None
+ * @retval None
+ */
+#define __LCD_HIGHDRIVE_BUF_ENABLE() SET_BIT(LCD->CTRL, LCD_CTRL_BUFEN)
+
+/** @brief Disable the LCD voltage output buffer.
+ * @param None
+ * @retval None
+ */
+#define __LCD_HIGHDRIVE_BUF_DISABLE() CLEAR_BIT(LCD->CTRL, LCD_CTRL_BUFEN)
+
+/** @brief Enable the LCD mux segment.
+ * @param None
+ * @retval None
+ */
+#define __LCD_MUXSEG_ENABLE() SET_BIT(LCD->CTRL, LCD_CTRL_MUXSEG)
+
+/** @brief Disable the LCD mux segment.
+ * @param None
+ * @retval None
+ */
+#define __LCD_MUXSEG_DISABLE() CLEAR_BIT(LCD->CTRL, LCD_CTRL_MUXSEG)
+
+/** @brief Select internal VLCD as LCD voltage source
+ * @param None
+ * @retval None
+ */
+#define __LCD_SELECT_INTERNAL_VLCD() CLEAR_BIT(LCD->CTRL, LCD_CTRL_VSEL)
+
+/** @brief Select external VLCD as LCD voltage source
+ * @param None
+ * @retval None
+ */
+#define __LCD_SELECT_EXTERNAL_VLCD() SET_BIT(LCD->CTRL, LCD_CTRL_VSEL)
+
+/** @brief Enable the LCD high driver mode.
+ * @param None
+ * @retval None
+ */
+#define __LCD_HIGHDRIVE_ENABLE() SET_BIT(LCD->FCTRL, LCD_FCTRL_HDEN)
+
+/** @brief Disable the LCD high driver mode.
+ * @param None
+ * @retval None
+ */
+#define __LCD_HIGHDRIVE_DISABLE() CLEAR_BIT(LCD->FCTRL, LCD_FCTRL_HDEN)
+
+/** @brief Config the prescaler factor
+ * @param __PRES__ specifies the LCD prescaler
+ * This parameter can be one of the following values:
+ * @arg LCD_PRESCALER_1: CLKPS = LCDCLK
+ * @arg LCD_PRESCALER_2: CLKPS = LCDCLK/2
+ * @arg LCD_PRESCALER_4: CLKPS = LCDCLK/4
+ * @arg LCD_PRESCALER_8: CLKPS = LCDCLK/8
+ * @arg LCD_PRESCALER_16: CLKPS = LCDCLK/16
+ * @arg LCD_PRESCALER_32: CLKPS = LCDCLK/32
+ * @arg LCD_PRESCALER_64: CLKPS = LCDCLK/64
+ * @arg LCD_PRESCALER_128: CLKPS = LCDCLK/128
+ * @arg LCD_PRESCALER_256: CLKPS = LCDCLK/256
+ * @arg LCD_PRESCALER_512: CLKPS = LCDCLK/512
+ * @arg LCD_PRESCALER_1024: CLKPS = LCDCLK/1024
+ * @arg LCD_PRESCALER_2048: CLKPS = LCDCLK/2048
+ * @arg LCD_PRESCALER_4096: CLKPS = LCDCLK/4096
+ * @arg LCD_PRESCALER_8192: CLKPS = LCDCLK/8192
+ * @arg LCD_PRESCALER_16384: CLKPS = LCDCLK/16384
+ * @arg LCD_PRESCALER_32768: CLKPS = LCDCLK/32768
+ * @retval None
+ */
+#define __LCD_PRESCALER_CONFIG(__PRES__) MODIFY_REG(LCD->FCTRL, LCD_FCTRL_PRES,__PRES__)
+
+/** @brief Config the divider factor
+ * @param __DIV__ specifies the LCD divider
+ * This parameter can be one of the following values:
+ * @arg LCD_DIV_16: CLKDIV = CLKPS/(16)
+ * @arg LCD_DIV_17: CLKDIV = CLKPS/(17)
+ * @arg LCD_DIV_18: CLKDIV = CLKPS/(18)
+ * @arg LCD_DIV_19: CLKDIV = CLKPS/(19)
+ * @arg LCD_DIV_20: CLKDIV = CLKPS/(20)
+ * @arg LCD_DIV_21: CLKDIV = CLKPS/(21)
+ * @arg LCD_DIV_22: CLKDIV = CLKPS/(22)
+ * @arg LCD_DIV_23: CLKDIV = CLKPS/(23)
+ * @arg LCD_DIV_24: CLKDIV = CLKPS/(24)
+ * @arg LCD_DIV_25: CLKDIV = CLKPS/(25)
+ * @arg LCD_DIV_26: CLKDIV = CLKPS/(26)
+ * @arg LCD_DIV_27: CLKDIV = CLKPS/(27)
+ * @arg LCD_DIV_28: CLKDIV = CLKPS/(28)
+ * @arg LCD_DIV_29: CLKDIV = CLKPS/(29)
+ * @arg LCD_DIV_30: CLKDIV = CLKPS/(30)
+ * @arg LCD_DIV_31: CLKDIV = CLKPS/(31)
+ * @retval None
+ */
+#define __LCD_DIVIDER_CONFIG(__DIV__) MODIFY_REG(LCD->FCTRL, LCD_FCTRL_DIV,__DIV__)
+
+/** @brief Config the blink mode and frequency
+ * @param __BLINKMODE__ specifies the LCD blink mode
+ * This parameter can be one of the following values:
+ * @arg LCD_DIV_16: CLKDIV = CLKPS/(16)
+ * @arg LCD_BLINKMODE_OFF: Blink disable
+ * @arg LCD_BLINKMODE_SEG0_COM0: Blink enabled on SEG[0], COM[0] (1 pixel)
+ * @arg LCD_BLINKMODE_SEG0_ALLCOM: Blink enabled on SEG[0], all COM (up to 8 pixels according to the programmed duty)
+ * @arg LCD_BLINKMODE_ALLSEG_ALLCOM: Blink enabled on all SEG and all COM (all pixels)
+ * @param __BLINKFREQUENCY__ specifies the LCD blink frequency
+ * This parameter can be one of the following values:
+ * @arg LCD_BLINKFREQ_DIV_8: The Blink frequency = fck_div/8
+ * @arg LCD_BLINKFREQ_DIV_16: The Blink frequency = fck_div/16
+ * @arg LCD_BLINKFREQ_DIV_32: The Blink frequency = fck_div/32
+ * @arg LCD_BLINKFREQ_DIV_64: The Blink frequency = fck_div/64
+ * @arg LCD_BLINKFREQ_DIV_128: The Blink frequency = fck_div/128
+ * @arg LCD_BLINKFREQ_DIV_256: The Blink frequency = fck_div/256
+ * @arg LCD_BLINKFREQ_DIV_512: The Blink frequency = fck_div/512
+ * @arg LCD_BLINKFREQ_DIV_1024: The Blink frequency = fck_div/1024
+ * @retval None
+ */
+#define __LCD_BLINK_CONFIG(__BLINKMODE__,__BLINKFREQUENCY__) MODIFY_REG(LCD->FCTRL, (LCD_FCTRL_BLINK|LCD_FCTRL_BLINKF),(__BLINKMODE__|__BLINKFREQUENCY__))
+
+
+/** @brief Config the contrast
+ * @param __CONTRAST__ specifies the LCD contrast
+ * This parameter can be one of the following values:
+ * @arg LCD_CONTRASTLEVEL_0: Maximum Voltage = 2.60V
+ * @arg LCD_CONTRASTLEVEL_1: Maximum Voltage = 2.73V
+ * @arg LCD_CONTRASTLEVEL_2: Maximum Voltage = 2.86V
+ * @arg LCD_CONTRASTLEVEL_3: Maximum Voltage = 2.99V
+ * @arg LCD_CONTRASTLEVEL_4: Maximum Voltage = 3.12V
+ * @arg LCD_CONTRASTLEVEL_5: Maximum Voltage = 3.26V
+ * @arg LCD_CONTRASTLEVEL_6: Maximum Voltage = 3.40V
+ * @arg LCD_CONTRASTLEVEL_7: Maximum Voltage = 3.55V
+ * @retval None
+ */
+#define __LCD_CONTRAST_CONFIG(__CONTRAST__) MODIFY_REG(LCD->FCTRL, LCD_FCTRL_CONTRAST,__CONTRAST__)
+
+/** @brief Config the dead time
+ * @param __CONTRAST__ specifies the LCD dead time
+ * This parameter can be one of the following values:
+ * @arg LCD_DEADTIME_0: No dead Time
+ * @arg LCD_DEADTIME_1: One Phase between different couple of Frame
+ * @arg LCD_DEADTIME_2: Two Phase between different couple of Frame
+ * @arg LCD_DEADTIME_3: Three Phase between different couple of Frame
+ * @arg LCD_DEADTIME_4: Four Phase between different couple of Frame
+ * @arg LCD_DEADTIME_5: Five Phase between different couple of Frame
+ * @arg LCD_DEADTIME_6: Six Phase between different couple of Frame
+ * @arg LCD_DEADTIME_7: Seven Phase between different couple of Frame
+ * @retval None
+ */
+#define __LCD_DEADTIME_CONFIG(__DEADTIME__) MODIFY_REG(LCD->FCTRL, LCD_FCTRL_DEAD,__DEADTIME__)
+
+/** @brief Config the pulse on duration
+ * @param __PULSEON__ specifies the LCD pulse on duration in terms of
+ * CK_PS (prescaled LCD clock period) pulses.
+ * This parameter can be one of the following values:
+ * @arg LCD_PULSEONDURATION_0: 0 pulse
+ * @arg LCD_PULSEONDURATION_1: Pulse ON duration = 1/CK_PS
+ * @arg LCD_PULSEONDURATION_2: Pulse ON duration = 2/CK_PS
+ * @arg LCD_PULSEONDURATION_3: Pulse ON duration = 3/CK_PS
+ * @arg LCD_PULSEONDURATION_4: Pulse ON duration = 4/CK_PS
+ * @arg LCD_PULSEONDURATION_5: Pulse ON duration = 5/CK_PS
+ * @arg LCD_PULSEONDURATION_6: Pulse ON duration = 6/CK_PS
+ * @arg LCD_PULSEONDURATION_7: Pulse ON duration = 7/CK_PS
+ * @retval None
+ */
+#define __LCD_PULSEONDURATION_CONFIG(__PULSEON__) MODIFY_REG(LCD->FCTRL, LCD_FCTRL_PULSEON,__PULSEON__)
+
+/** @brief Enable the specified LCD interrupt.
+ * @param __INTERRUPT__ specifies the LCD interrupt source to be enabled.
+ * This parameter can be one of the following values:
+ * @arg LCD_IT_SOF: Start of Frame Interrupt
+ * @arg LCD_IT_UDD: Update Display Done Interrupt
+ * @retval None
+ */
+#define __LCD_ENABLE_IT(__INTERRUPT__) SET_BIT(LCD->FCTRL, __INTERRUPT__)
+
+/** @brief Disable the specified LCD interrupt.
+ * @param __INTERRUPT__ specifies the LCD interrupt source to be disabled.
+ * This parameter can be one of the following values:
+ * @arg LCD_IT_SOF: Start of Frame Interrupt
+ * @arg LCD_IT_UDD: Update Display Done Interrupt
+ * @retval None
+ */
+#define __LCD_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(LCD->FCTRL, __INTERRUPT__)
+
+/** @brief Check whether the specified LCD interrupt source is enabled or not.
+ * @param __INTERRUPT__ specifies the LCD interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg LCD_IT_SOF: Start of Frame Interrupt
+ * @arg LCD_IT_UDD: Update Display Done Interrupt.
+ * @retval The state of __INTERRUPT__
+ */
+#define __LCD_GET_IT_SOURCE(__INTERRUPT__) ((LCD->FCTRL) & (__INTERRUPT__))
+
+/** @brief Set LCD UDR flag for update dispaly request
+ * @param None
+ * @retval None
+ */
+#define __LCD_UPDATE_REQUEST() SET_BIT(LCD->STS, LCD_FLAG_UDR)
+
+/** @brief Check whether the specified LCD flag is set or not.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status.
+ * @note The ENS bit is set immediately when the LCDEN bit in the LCD_CR
+ * goes from 0 to 1. On deactivation it reflects the real status of
+ * LCD so it becomes 0 at the end of the last displayed frame.
+ * @arg LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at
+ * the beginning of a new frame, at the same time as the display data is
+ * updated.
+ * @arg LCD_FLAG_UDR: Update Display Request flag.
+ * @arg LCD_FLAG_UDD: Update Display Done flag.
+ * @arg LCD_FLAG_RDY: Step_up converter Ready flag. It indicates the status
+ * of the step-up converter.
+ * @arg LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag.
+ * This flag is set by hardware each time the LCD_FCR register is updated
+ * in the LCDCLK domain.
+ * @retval The new state of __FLAG__
+ */
+#define __LCD_GET_FLAG(__FLAG__) (((LCD->STS) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the specified LCD pending flag.
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg LCD_FLAG_SOF_CLEAR: Start of Frame Interrupt
+ * @arg LCD_FLAG_UDD_CLEAR: Update Display Done Interrupt
+ * @retval None
+ */
+#define __LCD_CLEAR_FLAG(__FLAG__) \
+ do { \
+ SET_BIT((LCD->CLR), (__FLAG__)); \
+ CLEAR_BIT((LCD->CLR), (__FLAG__)); \
+ }while (0)
+
+/** @brief Config LCD to keep display in STOP2 mode.
+ * @param None
+ * @retval None
+ */
+#define __LCD_DISPLAY_IN_STOP2() \
+ do { \
+ SET_BIT(*(__IO uint32_t *)(PWR_BASE+0x08), (0x1UL << 21)); \
+ CLEAR_BIT(*(__IO uint32_t *)(PWR_BASE+0x1c), (0x1UL << 7)); \
+ }while (0)
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup LCD_Private_Macros LCD Private Macros
+ * @{
+ */
+#define IS_LCD_RAM_REGISTER_INDEX(__RAMRegIndex__) ((__RAMRegIndex__)<=LCD_RAM2_COM7)
+
+#define IS_LCD_PRESCALER(_PRESCALER_) \
+ (((_PRESCALER_)==LCD_PRESCALER_1) ||((_PRESCALER_)==LCD_PRESCALER_2) \
+ ||((_PRESCALER_)==LCD_PRESCALER_4) ||((_PRESCALER_)==LCD_PRESCALER_8) \
+ ||((_PRESCALER_)==LCD_PRESCALER_16) ||((_PRESCALER_)==LCD_PRESCALER_32) \
+ ||((_PRESCALER_)==LCD_PRESCALER_64) ||((_PRESCALER_)==LCD_PRESCALER_128) \
+ ||((_PRESCALER_)==LCD_PRESCALER_256) ||((_PRESCALER_)==LCD_PRESCALER_512) \
+ ||((_PRESCALER_)==LCD_PRESCALER_1024)||((_PRESCALER_)==LCD_PRESCALER_2048) \
+ ||((_PRESCALER_)==LCD_PRESCALER_4096)||((_PRESCALER_)==LCD_PRESCALER_8192) \
+ ||((_PRESCALER_)==LCD_PRESCALER_16384)||((_PRESCALER_)==LCD_PRESCALER_32768))
+
+#define IS_LCD_DIVIDER(__DIVIDER__) \
+ (((__DIVIDER__)==LCD_DIV_16)||((__DIVIDER__)==LCD_DIV_17)||((__DIVIDER__)==LCD_DIV_18) \
+ ||((__DIVIDER__)==LCD_DIV_19)||((__DIVIDER__)==LCD_DIV_20)||((__DIVIDER__)==LCD_DIV_21) \
+ ||((__DIVIDER__)==LCD_DIV_22)||((__DIVIDER__)==LCD_DIV_23)||((__DIVIDER__)==LCD_DIV_24) \
+ ||((__DIVIDER__)==LCD_DIV_25)||((__DIVIDER__)==LCD_DIV_26)||((__DIVIDER__)==LCD_DIV_27) \
+ ||((__DIVIDER__)==LCD_DIV_28)||((__DIVIDER__)==LCD_DIV_29)||((__DIVIDER__)==LCD_DIV_30) \
+ ||((__DIVIDER__)==LCD_DIV_31))
+
+#define IS_LCD_DUTY(__DUTY__) \
+ (((__DUTY__)==LCD_DUTY_STATIC)||((__DUTY__)==LCD_DUTY_1_2) \
+ ||((__DUTY__)==LCD_DUTY_1_3) ||((__DUTY__)==LCD_DUTY_1_4) \
+ ||((__DUTY__)==LCD_DUTY_1_8) )
+
+#define IS_LCD_BIAS(__BIAS__) \
+ (((__BIAS__)==LCD_BIAS_1_2)||((__BIAS__)==LCD_BIAS_1_3)||((__BIAS__)==LCD_BIAS_1_4))
+
+#define IS_LCD_VOLTAGESOURCE(__SOURCE__) \
+ (((__SOURCE__)==LCD_VOLTAGESOURCE_INTERNAL)||((__SOURCE__)==LCD_VOLTAGESOURCE_EXTERNAL))
+
+#define IS_LCD_CONTRASTLEVEL(__CONTRAST__) \
+ (((__CONTRAST__)==LCD_CONTRASTLEVEL_0) ||((__CONTRAST__)==LCD_CONTRASTLEVEL_1) \
+ ||((__CONTRAST__)==LCD_CONTRASTLEVEL_2) ||((__CONTRAST__)==LCD_CONTRASTLEVEL_3) \
+ ||((__CONTRAST__)==LCD_CONTRASTLEVEL_4) ||((__CONTRAST__)==LCD_CONTRASTLEVEL_5) \
+ ||((__CONTRAST__)==LCD_CONTRASTLEVEL_6) ||((__CONTRAST__)==LCD_CONTRASTLEVEL_7))
+
+#define IS_LCD_DEADTIME(__DEADTIME__) \
+ (((__DEADTIME__)==LCD_DEADTIME_0) ||((__DEADTIME__)==LCD_DEADTIME_1) \
+ ||((__DEADTIME__)==LCD_DEADTIME_2) ||((__DEADTIME__)==LCD_DEADTIME_3) \
+ ||((__DEADTIME__)==LCD_DEADTIME_4) ||((__DEADTIME__)==LCD_DEADTIME_5) \
+ ||((__DEADTIME__)==LCD_DEADTIME_6) ||((__DEADTIME__)==LCD_DEADTIME_7))
+
+#define IS_LCD_PULSEONDURATION(__PULSE__) \
+ (((__PULSE__)==LCD_PULSEONDURATION_0) ||((__PULSE__)==LCD_PULSEONDURATION_1) \
+ ||((__PULSE__)==LCD_PULSEONDURATION_2) ||((__PULSE__)==LCD_PULSEONDURATION_3) \
+ ||((__PULSE__)==LCD_PULSEONDURATION_4) ||((__PULSE__)==LCD_PULSEONDURATION_5) \
+ ||((__PULSE__)==LCD_PULSEONDURATION_6) ||((__PULSE__)==LCD_PULSEONDURATION_7))
+
+#define IS_LCD_HIGHDRIVE(__HIGHDRIVE__) \
+ ((((__HIGHDRIVE__))==LCD_HIGHDRIVE_DISABLE)||(((__HIGHDRIVE__))==LCD_HIGHDRIVE_ENABLE))
+
+#define IS_LCD_HIGHDRIVEBUFFER(__HIGHDRIVEBUF__) \
+ (((__HIGHDRIVEBUF__)==LCD_HIGHDRIVEBUFFER_DISABLE)||((__HIGHDRIVEBUF__)==LCD_HIGHDRIVEBUFFER_ENABLE))
+
+#define IS_LCD_BLINKMODE(__BLINKMODE__) \
+ (((__BLINKMODE__)==LCD_BLINKMODE_OFF) ||((__BLINKMODE__)==LCD_BLINKMODE_SEG0_COM0) \
+ ||((__BLINKMODE__)==LCD_BLINKMODE_SEG0_ALLCOM) ||((__BLINKMODE__)==LCD_BLINKMODE_ALLSEG_ALLCOM))
+
+#define IS_LCD_BLINKFREQ(__BLINKFREQ__) \
+ (((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_8) ||((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_16) \
+ ||((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_32) ||((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_64) \
+ ||((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_128) ||((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_256) \
+ ||((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_512) ||((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_1024))
+
+#define IS_LCD_MUXSEGMENT(__MUXSEG__) \
+ (((__MUXSEG__)==LCD_MUXSEGMENT_DISABLE)||((__MUXSEG__)==LCD_MUXSEGMENT_ENABLE))
+
+#define IS_LCD_FLAG(__FLAG__) \
+ (((__FLAG__)==LCD_FLAG_ENSTS)||((__FLAG__)==LCD_FLAG_SOF) \
+ ||((__FLAG__)==LCD_FLAG_UDR)||((__FLAG__)==LCD_FLAG_UDD) \
+ ||((__FLAG__)==LCD_FLAG_RDY)||((__FLAG__)==LCD_FLAG_FCRSF))
+
+#define IS_LCD_CLR_FLAG(__CLEARFLAG__) (((__CLEARFLAG__)==LCD_FLAG_SOF_CLEAR)||((__CLEARFLAG__)==LCD_FLAG_UDD_CLEAR)
+
+
+/**
+ * @brief LCD Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t Prescaler; /*!< Configures the LCD Prescaler.
+ This parameter can be one value of @ref LCD_Prescaler */
+ uint32_t Divider; /*!< Configures the LCD Divider.
+ This parameter can be one value of @ref LCD_Divider */
+ uint32_t Duty; /*!< Configures the LCD Duty.
+ This parameter can be one value of @ref LCD_Duty */
+ uint32_t Bias; /*!< Configures the LCD Bias.
+ This parameter can be one value of @ref LCD_Bias */
+ uint32_t VoltageSource; /*!< Selects the LCD Voltage source.
+ This parameter can be one value of @ref LCD_Voltage_source */
+ uint32_t Contrast; /*!< Configures the LCD Contrast.
+ This parameter can be one value of @ref LCD_Contrast */
+ uint32_t DeadTime; /*!< Configures the LCD Dead Time.
+ This parameter can be one value of @ref LCD_DeadTime */
+ uint32_t PulseOnDuration; /*!< Configures the LCD Pulse On Duration.
+ This parameter can be one value of @ref LCD_PulseOnDuration */
+ uint32_t HighDrive; /*!< Enable or disable the permanent high driver.
+ This parameter can be one value of @ref LCD_HighDrive */
+ uint32_t HighDriveBuffer; /*!< Enable or disable the high driver buffer.
+ This parameter can be one value of @ref LCD_HighDrive_Buffer */
+ uint32_t BlinkMode; /*!< Configures the LCD Blink Mode.
+ This parameter can be one value of @ref LCD_Blink_Mode */
+ uint32_t BlinkFreq; /*!< Configures the LCD Blink frequency.
+ This parameter can be one value of @ref LCD_Blink_Frequency */
+ uint32_t MuxSegment; /*!< Enable or disable mux segment.
+ This parameter can be one value of @ref LCD_MuxSegment */
+}LCD_InitType;
+
+
+/** @addtogroup LCD_Exported_Functions
+ * @{
+ */
+LCD_ErrorTypeDef LCD_Init(LCD_InitType *LCD_InitStructure );
+void LCD_DeInit(void);
+
+LCD_ErrorTypeDef LCD_ClockConfig(uint32_t LCD_ClkSource);
+
+void LCD_RamClear(void);
+
+LCD_ErrorTypeDef LCD_UpdateDisplayRequest(void);
+
+LCD_ErrorTypeDef LCD_Write(uint32_t RAMRegisterIndex,uint32_t RAMRegisterMask,uint32_t RAMData);
+
+
+LCD_ErrorTypeDef LCD_SetBit(uint32_t RAMRegisterIndex,uint32_t RAMData);
+
+LCD_ErrorTypeDef LCD_ClearBit(uint32_t RAMRegisterIndex,uint32_t RAMData);
+
+LCD_ErrorTypeDef LCD_WaitForSynchro(void);
+
+/**
+ * @}
+ */
+
+
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* __N32L40X_LCD_H__ */
+ /**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_lptim.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_lptim.h
new file mode 100644
index 0000000000..e008d93a5b
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_lptim.h
@@ -0,0 +1,427 @@
+/** ----------------------------------------------------------------------------
+ * Nationz Technology Software Support - NATIONZ -
+ * -----------------------------------------------------------------------------
+ * Copyright (c) 2022, Nationz Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaiimer below.
+ *
+ * - Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the disclaimer below in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * Nationz's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * -----------------------------------------------------------------------------
+ */
+/** ****************************************************************************
+ * @copyright Nationz Co.,Ltd
+ * Copyright (c) 2019 All Rights Reserved
+ *******************************************************************************
+ * @file n32l40x_lptim.h
+ * @author
+ * @date
+ * @version v1.2.0
+ * @brief
+ ******************************************************************************/
+#ifndef __N32L40X_LPTIM_H
+#define __N32L40X_LPTIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "n32l40x.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup LPTIM
+ * @{
+ */
+
+//#if defined (LPTIM)
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup LPTIM_ES_INIT LPTIM Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief LPTIM Init structure definition
+ */
+typedef struct
+{
+ uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
+ This parameter can be a value of @ref LPTIM_EC_CLK_SOURCE.
+
+ This feature can be modified afterwards using unitary function @ref LPTIM_SetClockSource().*/
+
+ uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
+ This parameter can be a value of @ref LPTIM_EC_PRESCALER.
+
+ This feature can be modified afterwards using using unitary function @ref LPTIM_SetPrescaler().*/
+
+ uint32_t Waveform; /*!< Specifies the waveform shape.
+ This parameter can be a value of @ref LPTIM_EC_OUTPUT_WAVEFORM.
+
+ This feature can be modified afterwards using unitary function @ref LPTIM_ConfigOutput().*/
+
+ uint32_t Polarity; /*!< Specifies waveform polarity.
+ This parameter can be a value of @ref LPTIM_EC_OUTPUT_POLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LPTIM_ConfigOutput().*/
+} LPTIM_InitType;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
+ * @{
+ */
+
+/** @defgroup LPTIM_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LPTIM_ReadReg function
+ * @{
+ */
+#define LPTIM_INTSTS_CMPM_FLAG LPTIM_INTSTS_CMPM /*!< Compare match */
+#define LPTIM_INTSTS_ARRM_FLAG LPTIM_INTSTS_ARRM /*!< Autoreload match */
+#define LPTIM_INTSTS_EXTRIG_FLAG LPTIM_INTSTS_EXTRIG /*!< External trigger edge event */
+#define LPTIM_INTSTS_CMPUPD_FLAG LPTIM_INTSTS_CMPUPD /*!< Compare register update OK */
+#define LPTIM_INTSTS_ARRUPD_FLAG LPTIM_INTSTS_ARRUPD /*!< Autoreload register update OK */
+#define LPTIM_INTSTS_UP_FLAG LPTIM_INTSTS_UP /*!< Counter direction change down to up */
+#define LPTIM_INTSTS_DOWN_FLAG LPTIM_INTSTS_DOWN /*!< Counter direction change up to down */
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_EC_IT IT Defines
+ * @brief IT defines which can be used with LPTIM_ReadReg and LPTIM_WriteReg functions
+ * @{
+ */
+#define LPTIM_INTEN_CMPMIE_ENABLE LPTIM_INTEN_CMPMIE /*!< Compare match Interrupt Enable */
+#define LPTIM_INTEN_ARRMIE_ENABLE LPTIM_INTEN_ARRMIE /*!< Autoreload match Interrupt Enable */
+#define LPTIM_INTEN_EXTRIGIE_ENABLE LPTIM_INTEN_EXTRIGIE /*!< External trigger valid edge Interrupt Enable */
+#define LPTIM_INTEN_CMPUPDIE_ENABLE LPTIM_INTEN_CMPUPDIE /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_INTEN_ARRUPDIE_ENABLE LPTIM_INTEN_ARRUPDIE /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_INTEN_UPIE_ENABLE LPTIM_INTEN_UPIE /*!< Direction change to UP Interrupt Enable */
+#define LPTIM_INTEN_DOWNIE_ENABLE LPTIM_INTEN_DOWNIE /*!< Direction change to down Interrupt Enable */
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_EC_OPERATING_MODE Operating Mode
+ * @{
+ */
+#define LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CTRL_TSTCM /*!(__REG__), (__VALUE__))
+
+/**
+ * @brief Read a value in LPTIM register
+ * @param __INSTANCE__ LPTIM Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->(__REG__))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
+ * @{
+ */
+
+/** @defgroup LPTIM_EF_Init Initialisation and deinitialisation functions
+ * @{
+ */
+
+void LPTIM_DeInit(LPTIM_Module *LPTIMx);
+void LPTIM_StructInit(LPTIM_InitType *LPTIM_InitStruct);
+ErrorStatus LPTIM_Init(LPTIM_Module *LPTIMx, LPTIM_InitType *LPTIM_InitStruct);
+void LPTIM_Disable(LPTIM_Module *LPTIMx);
+
+
+
+void LPTIM_Enable(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabled(LPTIM_Module *LPTIMx);
+void LPTIM_StartCounter(LPTIM_Module *LPTIMx, uint32_t OperatingMode);
+void LPTIM_SetUpdateMode(LPTIM_Module *LPTIMx, uint32_t UpdateMode);
+uint32_t LPTIM_GetUpdateMode(LPTIM_Module *LPTIMx);
+void LPTIM_SetAutoReload(LPTIM_Module *LPTIMx, uint32_t AutoReload);
+uint32_t LPTIM_GetAutoReload(LPTIM_Module *LPTIMx);
+void LPTIM_SetCompare(LPTIM_Module *LPTIMx, uint32_t CompareValue);
+uint32_t LPTIM_GetCompare(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_GetCounter(LPTIM_Module *LPTIMx);
+void LPTIM_SetCounterMode(LPTIM_Module *LPTIMx, uint32_t CounterMode);
+uint32_t LPTIM_GetCounterMode(LPTIM_Module *LPTIMx);
+void LPTIM_ConfigOutput(LPTIM_Module *LPTIMx, uint32_t Waveform, uint32_t Polarity);
+void LPTIM_SetWaveform(LPTIM_Module *LPTIMx, uint32_t Waveform);
+uint32_t LPTIM_GetWaveform(LPTIM_Module *LPTIMx);
+void LPTIM_SetPolarity(LPTIM_Module *LPTIMx, uint32_t Polarity);
+uint32_t LPTIM_GetPolarity(LPTIM_Module *LPTIMx);
+void LPTIM_SetPrescaler(LPTIM_Module *LPTIMx, uint32_t Prescaler);
+uint32_t LPTIM_GetPrescaler(LPTIM_Module *LPTIMx);
+void LPTIM_EnableTimeout(LPTIM_Module *LPTIMx);
+void LPTIM_DisableTimeout(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledTimeout(LPTIM_Module *LPTIMx);
+void LPTIM_TrigSw(LPTIM_Module *LPTIMx);
+void LPTIM_ConfigTrigger(LPTIM_Module *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity);
+uint32_t LPTIM_GetTriggerSource(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_GetTriggerFilter(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_GetTriggerPolarity(LPTIM_Module *LPTIMx);
+void LPTIM_SetClockSource(LPTIM_Module *LPTIMx, uint32_t ClockSource);
+uint32_t LPTIM_GetClockSource(LPTIM_Module *LPTIMx);
+void LPTIM_ConfigClock(LPTIM_Module *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity);
+uint32_t LPTIM_GetClockPolarity(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_GetClockFilter(LPTIM_Module *LPTIMx);
+void LPTIM_SetEncoderMode(LPTIM_Module *LPTIMx, uint32_t EncoderMode);
+uint32_t LPTIM_GetEncoderMode(LPTIM_Module *LPTIMx);
+void LPTIM_EnableEncoderMode(LPTIM_Module *LPTIMx);
+void LPTIM_DisableEncoderMode(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledEncoderMode(LPTIM_Module *LPTIMx);
+void LPTIM_ClearFLAG_CMPM(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsActiveFlag_CMPM(LPTIM_Module *LPTIMx);
+void LPTIM_ClearFLAG_ARRM(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsActiveFlag_ARRM(LPTIM_Module *LPTIMx);
+void LPTIM_ClearFlag_EXTTRIG(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsActiveFlag_EXTTRIG(LPTIM_Module *LPTIMx);
+void LPTIM_ClearFlag_CMPOK(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsActiveFlag_CMPOK(LPTIM_Module *LPTIMx);
+void LPTIM_ClearFlag_ARROK(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsActiveFlag_ARROK(LPTIM_Module *LPTIMx);
+void LPTIM_ClearFlag_UP(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsActiveFlag_UP(LPTIM_Module *LPTIMx);
+void LPTIM_ClearFlag_DOWN(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsActiveFlag_DOWN(LPTIM_Module *LPTIMx);
+void LPTIM_EnableIT_CMPM(LPTIM_Module *LPTIMx);
+void LPTIM_DisableIT_CMPM(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledIT_CMPM(LPTIM_Module *LPTIMx);
+void LPTIM_EnableIT_ARRM(LPTIM_Module *LPTIMx);
+void LPTIM_DisableIT_ARRM(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledIT_ARRM(LPTIM_Module *LPTIMx);
+void LPTIM_EnableIT_EXTTRIG(LPTIM_Module *LPTIMx);
+void LPTIM_DisableIT_EXTTRIG(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledIT_EXTTRIG(LPTIM_Module *LPTIMx);
+void LPTIM_EnableIT_CMPOK(LPTIM_Module *LPTIMx);
+void LPTIM_DisableIT_CMPOK(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledIT_CMPOK(LPTIM_Module *LPTIMx);
+void LPTIM_EnableIT_ARROK(LPTIM_Module *LPTIMx);
+void LPTIM_DisableIT_ARROK(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledIT_ARROK(LPTIM_Module *LPTIMx);
+void LPTIM_EnableIT_UP(LPTIM_Module *LPTIMx);
+void LPTIM_DisableIT_UP(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledIT_UP(LPTIM_Module *LPTIMx);
+void LPTIM_EnableIT_DOWN(LPTIM_Module *LPTIMx);
+void LPTIM_DisableIT_DOWN(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledIT_DOWN(LPTIM_Module *LPTIMx);
+void LPTIM_EnableNoEncoderMode(LPTIM_Module *LPTIMx);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+//#endif /* LPTIM */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32L40X_LPTIM_H */
+
+/******************* (C) COPYRIGHT 2019 NATIONZ *****END OF FILE****/
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_lpuart.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_lpuart.h
new file mode 100644
index 0000000000..3b8ac42464
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_lpuart.h
@@ -0,0 +1,280 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_lpuart.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L40X_LPUART_H__
+#define __N32L40X_LPUART_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l40x.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup LPUART
+ * @{
+ */
+
+/** @addtogroup LPUART_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief LPUART Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the LPUART communication baud rate.
+ The baud rate is computed using the following formula:
+ - IntegerDivider = ((CLK) / (LPUART_InitStruct->BaudRate)))
+ - FractionalDivider */
+
+ uint16_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (only support
+ 8 data bits). */
+
+ uint16_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref Mode */
+
+ uint16_t RtsThreshold; /* Specifies RTS Threshold.
+ This parameter can be a value of @ref RtsThreshold */
+
+ uint16_t HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
+ or disabled.
+ This parameter can be a value of @ref LPUART_Hardware_Flow_Control */
+} LPUART_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup Parity
+ * @{
+ */
+
+#define LPUART_PE_NO ((uint16_t)0x0008)
+#define LPUART_PE_EVEN ((uint16_t)0x0000)
+#define LPUART_PE_ODD ((uint16_t)0x0001)
+#define IS_LPUART_PARITY(PARITY) (((PARITY) == LPUART_PE_NO) || ((PARITY) == LPUART_PE_EVEN) || ((PARITY) == LPUART_PE_ODD))
+/**
+ * @}
+ */
+
+/** @addtogroup Mode
+ * @{
+ */
+
+#define LPUART_MODE_RX ((uint16_t)0x0000)
+#define LPUART_MODE_TX ((uint16_t)0x0002)
+#define IS_LPUART_MODE(MODE) (((MODE) == LPUART_MODE_RX) || ((MODE) == LPUART_MODE_TX))
+/**
+ * @}
+ */
+
+/** @addtogroup RtsThreshold
+ * @{
+ */
+
+#define LPUART_RTSTH_FIFOHF ((uint16_t)0x0000)
+#define LPUART_RTSTH_FIFO3QF ((uint16_t)0x0100)
+#define LPUART_RTSTH_FIFOFU ((uint16_t)0x0200)
+#define IS_LPUART_RTSTHRESHOLD(RTSTHRESHOLD) \
+ (((RTSTHRESHOLD) == LPUART_RTSTH_FIFOHF) || ((RTSTHRESHOLD) == LPUART_RTSTH_FIFO3QF) || ((RTSTHRESHOLD) == LPUART_RTSTH_FIFOFU))
+/**
+ * @}
+ */
+
+/** @addtogroup Hardware_Flow_Control
+ * @{
+ */
+#define LPUART_HFCTRL_NONE ((uint16_t)0x0000)
+#define LPUART_HFCTRL_CTS ((uint16_t)0x0400)
+#define LPUART_HFCTRL_RTS ((uint16_t)0x0800)
+#define LPUART_HFCTRL_RTS_CTS ((uint16_t)0x0C00)
+#define IS_LPUART_HARDWARE_FLOW_CONTROL(CONTROL) \
+ (((CONTROL) == LPUART_HFCTRL_NONE) || ((CONTROL) == LPUART_HFCTRL_RTS) || ((CONTROL) == LPUART_HFCTRL_CTS) \
+ || ((CONTROL) == LPUART_HFCTRL_RTS_CTS))
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Interrupt_definition
+ * @{
+ */
+
+#define LPUART_INT_PE ((uint16_t)0x0001)
+#define LPUART_INT_TXC ((uint16_t)0x0102)
+#define LPUART_INT_FIFO_OV ((uint16_t)0x0204)
+#define LPUART_INT_FIFO_FU ((uint16_t)0x0308)
+#define LPUART_INT_FIFO_HF ((uint16_t)0x0410)
+#define LPUART_INT_FIFO_NE ((uint16_t)0x0520)
+#define LPUART_INT_WUF ((uint16_t)0x0640)
+#define IS_LPUART_CFG_INT(IT) \
+ (((IT) == LPUART_INT_PE) || ((IT) == LPUART_INT_TXC) || ((IT) == LPUART_INT_FIFO_OV) || ((IT) == LPUART_INT_FIFO_FU) \
+ || ((IT) == LPUART_INT_FIFO_HF) || ((IT) == LPUART_INT_FIFO_NE) || ((IT) == LPUART_INT_WUF))
+#define IS_LPUART_GET_INT(IT) \
+ (((IT) == LPUART_INT_PE) || ((IT) == LPUART_INT_TXC) || ((IT) == LPUART_INT_FIFO_OV) || ((IT) == LPUART_INT_FIFO_FU) \
+ || ((IT) == LPUART_INT_FIFO_HF) || ((IT) == LPUART_INT_FIFO_NE) || ((IT) == LPUART_INT_WUF))
+#define IS_LPUART_CLR_INT(IT) \
+ (((IT) == LPUART_INT_PE) || ((IT) == LPUART_INT_TXC) || ((IT) == LPUART_INT_FIFO_OV) || ((IT) == LPUART_INT_FIFO_FU) \
+ || ((IT) == LPUART_INT_FIFO_HF) || ((IT) == LPUART_INT_FIFO_NE) || ((IT) == LPUART_INT_WUF))
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_DMA_Requests
+ * @{
+ */
+
+#define LPUART_DMAREQ_TX ((uint16_t)0x0020)
+#define LPUART_DMAREQ_RX ((uint16_t)0x0040)
+#define IS_LPUART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF9F) == (uint16_t)0x00) && ((DMAREQ) != (uint16_t)0x00))
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_WakeUp_methods
+ * @{
+ */
+
+#define LPUART_WUSTP_STARTBIT ((uint16_t)0x0000)
+#define LPUART_WUSTP_RXNE ((uint16_t)0x1000)
+#define LPUART_WUSTP_BYTE ((uint16_t)0x2000)
+#define LPUART_WUSTP_FRAME ((uint16_t)0x3000)
+#define IS_LPUART_WAKEUP(WAKEUP) \
+ (((WAKEUP) == LPUART_WUSTP_STARTBIT) || ((WAKEUP) == LPUART_WUSTP_RXNE) || ((WAKEUP) == LPUART_WUSTP_BYTE) || ((WAKEUP) == LPUART_WUSTP_FRAME))
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Sampling_methods
+ * @{
+ */
+
+#define LPUART_SMPCNT_3B ((uint16_t)0x0000)
+#define LPUART_SMPCNT_1B ((uint16_t)0x4000)
+#define IS_LPUART_SAMPLING(SAMPLING) (((SAMPLING) == LPUART_SMPCNT_1B) || ((SAMPLING) == LPUART_SMPCNT_3B))
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Flags
+ * @{
+ */
+
+#define LPUART_FLAG_PEF ((uint16_t)0x0001)
+#define LPUART_FLAG_TXC ((uint16_t)0x0002)
+#define LPUART_FLAG_FIFO_OV ((uint16_t)0x0004)
+#define LPUART_FLAG_FIFO_FU ((uint16_t)0x0008)
+#define LPUART_FLAG_FIFO_HF ((uint16_t)0x0010)
+#define LPUART_FLAG_FIFO_NE ((uint16_t)0x0020)
+#define LPUART_FLAG_CTS ((uint16_t)0x0040)
+#define LPUART_FLAG_WUF ((uint16_t)0x0080)
+#define LPUART_FLAG_NF ((uint16_t)0x0100)
+#define IS_LPUART_FLAG(FLAG) \
+ (((FLAG) == LPUART_FLAG_PEF) || ((FLAG) == LPUART_FLAG_TXC) || ((FLAG) == LPUART_FLAG_FIFO_OV) \
+ || ((FLAG) == LPUART_FLAG_FIFO_FU) || ((FLAG) == LPUART_FLAG_FIFO_HF) || ((FLAG) == LPUART_FLAG_FIFO_NE) \
+ || ((FLAG) == LPUART_FLAG_CTS) || ((FLAG) == LPUART_FLAG_WUF) || ((FLAG) == LPUART_FLAG_NF))
+
+#define IS_LPUART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFE40) == 0x00) && ((FLAG) != (uint16_t)0x00))
+
+#define IS_LPUART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x010000))
+
+#define IS_LPUART_DATA(DATA) ((DATA) <= 0xFF)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Exported_Functions
+ * @{
+ */
+
+void LPUART_DeInit(void);
+void LPUART_Init(LPUART_InitType* LPUART_InitStruct);
+void LPUART_StructInit(LPUART_InitType* LPUART_InitStruct);
+void LPUART_FlushRxFifo(void);
+void LPUART_ConfigInt(uint16_t LPUART_INT, FunctionalState Cmd);
+void LPUART_EnableDMA(uint16_t LPUART_DMAReq, FunctionalState Cmd);
+void LPUART_ConfigWakeUpMethod(uint16_t LPUART_WakeUpMethod);
+void LPUART_EnableWakeUpStop(FunctionalState Cmd);
+void LPUART_ConfigSamplingMethod(uint16_t LPUART_SamplingMethod);
+void LPUART_EnableLoopBack(FunctionalState Cmd);
+void LPUART_SendData(uint8_t Data);
+uint8_t LPUART_ReceiveData(void);
+void LPUART_ConfigWakeUpData(uint32_t LPUART_WakeUpData);
+FlagStatus LPUART_GetFlagStatus(uint16_t LPUART_FLAG);
+void LPUART_ClrFlag(uint16_t LPUART_FLAG);
+INTStatus LPUART_GetIntStatus(uint16_t LPUART_INT);
+void LPUART_ClrIntPendingBit(uint16_t LPART_INT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32L40X_LPUART_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_opamp.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_opamp.h
new file mode 100644
index 0000000000..ddc075138e
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_opamp.h
@@ -0,0 +1,209 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_opamp.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L40X_OPAMPMP_H__
+#define __N32L40X_OPAMPMP_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l40x.h"
+#include
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup OPAMP
+ * @{
+ */
+
+/** @addtogroup OPAMP_Exported_Constants
+ * @{
+ */
+typedef enum
+{
+ OPAMP1 = 0,
+ OPAMP2 = 4,
+} OPAMPX;
+
+// OPAMP_CS
+typedef enum
+{
+ OPAMP2_CS_TIMSRCSEL_TIM1CC6 = (0x0L << 24),
+ OPAMP2_CS_TIMSRCSEL_TIM8CC6 = (0x1L << 24),
+}OPAMP2_CS_TIMSRCSEL;
+typedef enum
+{
+ OPAMP1_CS_VPSSEL_PA1 = (0x00L << 19),
+ OPAMP1_CS_VPSSEL_PA5 = (0x01L << 19),
+ OPAMP1_CS_VPSSEL_PA4 = (0x02L << 19),
+ OPAMP1_CS_VPSSEL_PA7 = (0x03L << 19),
+ OPAMP1_CS_VPSSEL_NC = (0x04L << 19),
+
+ OPAMP2_CS_VPSSEL_PA7 = (0x00L << 19),
+ OPAMP2_CS_VPSSEL_PA4 = (0x01L << 19),
+ OPAMP2_CS_VPSSEL_PB14 = (0x02L << 19),
+ OPAMP2_CS_VPSSEL_PD13 = (0x03L << 19),
+ OPAMP2_CS_VPSSEL_NC = (0x04L << 19),
+} OPAMP_CS_VPSSEL;
+typedef enum
+{
+ OPAMP1_CS_VMSSEL_PA3 = (0x00L << 17),
+ OPAMP1_CS_VMSSEL_PC5 = (0x01L << 17),
+ OPAMP1_CS_VMSSEL_NC = (0x02L << 17),
+ OPAMP1_CS_VMSSEL_FLOAT = (0x03L << 17),
+
+ OPAMP2_CS_VMSSEL_PC5 = (0x00L << 17),
+ OPAMP2_CS_VMSSEL_PB0 = (0x01L << 17),
+ OPAMP2_CS_VMSSEL_PA5 = (0x02L << 17),
+ OPAMP2_CS_VMSSEL_FLOAT = (0x03L << 17),
+} OPAMP_CS_VMSSEL;
+
+typedef enum
+{
+ OPAMP1_CS_VPSEL_PA1 = (0x00L << 8),
+ OPAMP1_CS_VPSEL_PA5 = (0x01L << 8),
+ OPAMP1_CS_VPSEL_PA4 = (0x02L << 8),
+ OPAMP1_CS_VPSEL_PA7 = (0x03L << 8),
+ OPAMP1_CS_VPSEL_NC = (0x04L << 8),
+
+ OPAMP2_CS_VPSEL_PA7 = (0x00L << 8),
+ OPAMP2_CS_VPSEL_PA4 = (0x01L << 8),
+ OPAMP2_CS_VPSEL_PB14 = (0x02L << 8),
+ OPAMP2_CS_VPSEL_PD13 = (0x03L << 8),
+ OPAMP2_CS_VPSEL_NC = (0x04L << 8),
+} OPAMP_CS_VPSEL;
+typedef enum
+{
+ OPAMP1_CS_VMSEL_PA3 = (0x00L << 6),
+ OPAMP1_CS_VMSEL_PC5 = (0x01L << 6),
+ OPAMPx_CS_VMSEL_NC = (0x02L << 6),
+ OPAMPx_CS_VMSEL_FLOAT = (0x03L << 6),
+
+ OPAMP2_CS_VMSEL_PC5 = (0x00L << 6),
+ OPAMP2_CS_VMSEL_PB0 = (0x01L << 6),
+ OPAMP2_CS_VMSEL_PA5 = (0x02L << 6),
+ OPAMP2_CS_VMSEL_FLOAT = (0x03L << 6),
+} OPAMP_CS_VMSEL;
+typedef enum
+{
+ OPAMP_CS_PGA_GAIN_2 = (0x00 << 3),
+ OPAMP_CS_PGA_GAIN_4 = (0x01 << 3),
+ OPAMP_CS_PGA_GAIN_8 = (0x02 << 3),
+ OPAMP_CS_PGA_GAIN_16 = (0x03 << 3),
+ OPAMP_CS_PGA_GAIN_32 = (0x04 << 3),
+} OPAMP_CS_PGA_GAIN;
+typedef enum
+{
+ OPAMP_CS_EXT_OPAMP = (0x00 << 1),
+ OPAMP_CS_PGA_EN = (0x02 << 1),
+ OPAMP_CS_FOLLOW = (0x03 << 1),
+} OPAMP_CS_MOD;
+
+// bit mask
+#define OPAMP_CS_EN_MASK (0x01L << 0)
+#define OPAMP_CS_MOD_MASK (0x03L << 1)
+#define OPAMP_CS_PGA_GAIN_MASK (0x07L << 3)
+#define OPAMP_CS_VMSEL_MASK (0x03L << 6)
+#define OPAMP_CS_VPSEL_MASK (0x07L << 8)
+#define OPAMP_CS_CALON_MASK (0x01L << 11)
+#define OPAMP_CS_TSTREF_MASK (0x01L << 13)
+#define OPAMP_CS_CALOUT_MASK (0x01L << 14)
+#define OPAMP_CS_RANGE_MASK (0x01L << 15)
+#define OPAMP_CS_TCMEN_MASK (0x01L << 16)
+#define OPAMP_CS_VMSEL_SECOND_MASK (0x03L << 17)
+#define OPAMP_CS_VPSEL_SECOND_MASK (0x07L << 19)
+#define OPAMP_CS_OPAMP2_TIMSRCSEL (0x01L << 24)
+/** @addtogroup OPAMP_LOCK
+ * @{
+ */
+#define OPAMP_LOCK_1 0x01L
+#define OPAMP_LOCK_2 0x02L
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/**
+ * @brief OPAMP Init structure definition
+ */
+
+typedef struct
+{
+ OPAMP2_CS_TIMSRCSEL Opa2SrcSel; /*only for opa2 can sel,opa1 always TIM1_CC6*/
+
+ FunctionalState TimeAutoMuxEn; /*call ENABLE or DISABLE */
+
+ FunctionalState HighVolRangeEn; /*call ENABLE or DISABLE ,low range VDDA < 2.4V,high range VDDA >= 2.4V*/
+
+ OPAMP_CS_PGA_GAIN Gain; /*see @EM_PGA_GAIN */
+
+ OPAMP_CS_MOD Mod; /*see @EM_OPAMP_MOD*/
+} OPAMP_InitType;
+
+/** @addtogroup OPAMP_Exported_Functions
+ * @{
+ */
+
+void OPAMP_DeInit(void);
+void OPAMP_StructInit(OPAMP_InitType* OPAMP_InitStruct);
+void OPAMP_Init(OPAMPX OPAMPx, OPAMP_InitType* OPAMP_InitStruct);
+void OPAMP_Enable(OPAMPX OPAMPx, FunctionalState en);
+void OPAMP_SetPgaGain(OPAMPX OPAMPx, OPAMP_CS_PGA_GAIN Gain);
+void OPAMP_SetVpSecondSel(OPAMPX OPAMPx, OPAMP_CS_VPSSEL VpSSel);
+void OPAMP_SetVmSecondSel(OPAMPX OPAMPx, OPAMP_CS_VMSSEL VmSSel);
+void OPAMP_SetVpSel(OPAMPX OPAMPx, OPAMP_CS_VPSEL VpSel);
+void OPAMP_SetVmSel(OPAMPX OPAMPx, OPAMP_CS_VMSEL VmSel);
+bool OPAMP_IsCalOutHigh(OPAMPX OPAMPx);
+void OPAMP_CalibrationEnable(OPAMPX OPAMPx, FunctionalState en);
+void OPAMP_SetLock(uint32_t Lock); // see @OPAMP_LOCK
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32L40X_ADC_H */
+ /**
+ * @}
+ */
+ /**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_pwr.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_pwr.h
new file mode 100644
index 0000000000..509a0edbc9
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_pwr.h
@@ -0,0 +1,224 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_pwr.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L40X_PWR_H__
+#define __N32L40X_PWR_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l40x.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup PWR
+ * @{
+ */
+
+/** @addtogroup PWR_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup PVD_detection_level
+ * @{
+ */
+
+#define PWR_PVDLEVEL_2V1 ((uint32_t)0x00000000)
+#define PWR_PVDLEVEL_2V25 ((uint32_t)0x0000002)
+#define PWR_PVDLEVEL_2V4 ((uint32_t)0x0000004)
+#define PWR_PVDLEVEL_2V55 ((uint32_t)0x0000006)
+#define PWR_PVDLEVEL_2V7 ((uint32_t)0x0000008)
+#define PWR_PVDLEVEL_2V85 ((uint32_t)0x000000A)
+#define PWR_PVDLEVEL_2V95 ((uint32_t)0x000000C)
+#define PWR_PVDLEVEL_IN ((uint32_t)0x000000E)
+
+
+#define IS_PWR_PVD_LEVEL(LEVEL) \
+ (((LEVEL) == PWR_PVDLEVEL_2V1) || ((LEVEL) == PWR_PVDLEVEL_2V25) || ((LEVEL) == PWR_PVDLEVEL_2V4) \
+ || ((LEVEL) == PWR_PVDLEVEL_2V55) || ((LEVEL) == PWR_PVDLEVEL_2V7) || ((LEVEL) == PWR_PVDLEVEL_2V85) \
+ || ((LEVEL) == PWR_PVDLEVEL_2V95) || ((LEVEL) == PWR_PVDLEVEL_IN) )
+
+/**
+ * @}
+ */
+
+/** @addtogroup Regulator_state_is_STOP_mode
+ * @{
+ */
+
+#define PWR_REGULATOR_ON ((uint32_t)0x00000000)
+#define PWR_REGULATOR_LOWPOWER ((uint32_t)0x00000001)
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_REGULATOR_ON) || ((REGULATOR) == PWR_REGULATOR_LOWPOWER))
+/**
+ * @}
+ */
+
+/** @defgroup SLEEP_mode_entry
+ * @{
+ */
+#define SLEEP_ON_EXIT (1)
+#define SLEEP_OFF_EXIT (0)
+#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
+#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
+
+
+/**
+ * @}
+ */
+
+
+/** @defgroup STOP_mode_entry
+ * @{
+ */
+
+#define PWR_STOPENTRY_WFI ((uint8_t)0x01)
+#define PWR_STOPENTRY_WFE ((uint8_t)0x02)
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Flag
+ * @{
+ */
+//STS1
+#define PWR_WKUP0_FLAG ((uint32_t)0x00000001)
+#define PWR_WKUP1_FLAG ((uint32_t)0x00000002)
+#define PWR_WKUP2_FLAG ((uint32_t)0x00000004)
+#define PWR_STBY_FLAG ((uint32_t)0x00000100)
+//STS2
+#define PWR_LPRUN_FLAG ((uint32_t)0x00000001)
+#define PWR_MR_FLAG ((uint32_t)0x00000002)
+#define PWR_PVDO_FLAG ((uint32_t)0x00000004)
+
+#define IS_PWR_GET_FLAG(FLAG) \
+ (((FLAG) == PWR_WKUP0_FLAG) || ((FLAG) == PWR_WKUP1_FLAG) || ((FLAG) == PWR_WKUP2_FLAG) || ((FLAG) == PWR_STBY_FLAG)\
+ || ((FLAG) == PWR_LPRUN_FLAG) || ((FLAG) == PWR_MR_FLAG) || ((FLAG) == PWR_PVDO_FLAG))
+
+#define IS_PWR_CLEAR_FLAG(FLAG) \
+ (((FLAG) == PWR_WKUP0_FLAG) || ((FLAG) == PWR_WKUP1_FLAG) || ((FLAG) == PWR_WKUP2_FLAG) || ((FLAG) == PWR_STBY_FLAG)\
+ || ((FLAG) == PWR_LPRUN_FLAG) || ((FLAG) == PWR_MR_FLAG) || ((FLAG) == PWR_PVDO_FLAG))
+
+
+
+/** @addtogroup SRAM1 SRAM2 retention set
+ * @{
+ */
+//#define SRAM1DIS_SRAM2DIS 0
+//#define SRAM1EN_SRAM2DIS 1
+
+//#define SRAM1DIS_SRAM2EN 2
+//#define SRAM1EN_SRAM2EN 3
+/** @addtogroup MR VOLTAGE
+ * @{
+ */
+#define MR_1V0 2
+#define MR_1V1 3
+
+
+/**
+ * @}
+ */
+typedef enum
+{
+ WAKEUP_PIN0 = 0x0001,
+ WAKEUP_PIN1 = 0x0002,
+ WAKEUP_PIN2 = 0x0004,
+} WAKEUP_PINX;
+/** @addtogroup PWR_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+#define LPRUN_SWITCH_ADDR (__IO unsigned*)(0x40007000)
+#define LPRUN_SRAM_ADDR (__IO unsigned*)(0x40001800 + 0x20)
+#define CLERR_BIT25 0xfdffffff //bit25
+#define _SetLprunSramVoltage(vale) do{(*LPRUN_SRAM_ADDR) &= CLERR_BIT25;(*LPRUN_SRAM_ADDR) |= (uint32_t)(vale <<25);}while (0) //0:0.9V 1:1.1V
+#define _SetBandGapMode(vale) do{PWR->CTRL3 &= (~PWR_CTRL3_BGDTLPR);PWR->CTRL3 |= (uint32_t)(vale <<8);}while (0) //0:always on 1:duty on
+#define _SetPvdBorMode(vale) do{PWR->CTRL3 &= (~PWR_CTRL3_PBDTLPR);PWR->CTRL3 |= (uint32_t)(vale <<16);}while (0) //0:normal mode 1:standby mode
+#define _SetLprunswitch(vale) do{(*LPRUN_SWITCH_ADDR) &= (~0x0600);(*LPRUN_SWITCH_ADDR) |= (uint32_t)(vale <<9);}while (0)
+/** @addtogroup PWR_Exported_Functions
+ * @{
+ */
+
+void PWR_DeInit(void);
+void PWR_BackupAccessEnable(FunctionalState Cmd);
+void PWR_PvdEnable(FunctionalState Cmd);
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
+void PWR_WakeUpPinEnable(WAKEUP_PINX WKUP_Pin,FunctionalState Cmd);
+void PWR_EnterStopState(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+void PWR_EnterSLEEPMode(uint8_t SLEEPONEXIT, uint8_t PWR_STOPEntry);
+void PWR_EnterSTOP2Mode(uint8_t PWR_STOPEntry,uint32_t RetentionMode);
+void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry,uint32_t Sam2Ret);
+void PWR_EnterLowPowerRunMode(void);
+void PWR_ExitLowPowerRunMode(void);
+void PWR_EnterLowPowerSleepMode(uint8_t SLEEPONEXIT, uint8_t PWR_SLEEPEntry);
+
+FlagStatus PWR_GetFlagStatus(uint8_t STS, uint32_t PWR_FLAG);
+void PWR_ClearFlag(uint32_t PWR_FLAG);
+void PWR_WakeUpPinConfig(void);
+void SetSysClock_MSI(void);
+uint8_t GetMrVoltage(void);
+void PWR_MRconfig(uint8_t voltage);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32L40X_PWR_H__ */
+ /**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_rcc.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_rcc.h
new file mode 100644
index 0000000000..fa3491a545
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_rcc.h
@@ -0,0 +1,913 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_rcc.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L40X_RCC_H__
+#define __N32L40X_RCC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l40x.h"
+
+/** @addtogroup N32L40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RCC
+ * @{
+ */
+
+/** @addtogroup RCC_Exported_Types
+ * @{
+ */
+
+typedef struct
+{
+ uint32_t SysclkFreq; /*!< returns SYSCLK clock frequency expressed in Hz */
+ uint32_t HclkFreq; /*!< returns HCLK clock frequency expressed in Hz */
+ uint32_t Pclk1Freq; /*!< returns PCLK1 clock frequency expressed in Hz */
+ uint32_t Pclk2Freq; /*!< returns PCLK2 clock frequency expressed in Hz */
+ uint32_t AdcPllClkFreq; /*!< returns ADCPLLCLK clock frequency expressed in Hz */
+ uint32_t AdcHclkFreq; /*!< returns ADCHCLK clock frequency expressed in Hz */
+} RCC_ClocksType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup HSE_configuration
+ * @{
+ */
+
+#define RCC_HSE_DISABLE ((uint32_t)0x00000000)
+#define RCC_HSE_ENABLE ((uint32_t)0x00010000)
+#define RCC_HSE_BYPASS ((uint32_t)0x00040000)
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_DISABLE) || ((HSE) == RCC_HSE_ENABLE) || ((HSE) == RCC_HSE_BYPASS))
+
+/**
+ * @}
+ */
+
+/** @addtogroup HSI_configuration
+ * @{
+ */
+
+#define RCC_HSI_DISABLE ((uint32_t)0x00000000)
+#define RCC_HSI_ENABLE ((uint32_t)0x00000001)
+#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_DISABLE) || ((HSI) == RCC_HSI_ENABLE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup MSI_configuration
+ * @{
+ */
+
+#define RCC_MSI_DISABLE ((uint32_t)0x00000000)
+#define RCC_MSI_ENABLE ((uint32_t)0x00000004)
+#define IS_RCC_MSI(MSI) (((MSI) == RCC_MSI_DISABLE) || ((MSI) == RCC_MSI_ENABLE))
+
+#define RCC_MSI_RANGE_100K ((uint32_t)0x00000000)
+#define RCC_MSI_RANGE_200K ((uint32_t)0x00000010)
+#define RCC_MSI_RANGE_400K ((uint32_t)0x00000020)
+#define RCC_MSI_RANGE_800K ((uint32_t)0x00000030)
+#define RCC_MSI_RANGE_1M ((uint32_t)0x00000040)
+#define RCC_MSI_RANGE_2M ((uint32_t)0x00000050)
+#define RCC_MSI_RANGE_4M ((uint32_t)0x00000060)
+#define IS_RCC_MSI_RANGE(MSI_RANGE) (((MSI_RANGE) == RCC_MSI_RANGE_100K) || ((MSI_RANGE) == RCC_MSI_RANGE_200K) \
+ || ((MSI_RANGE) == RCC_MSI_RANGE_400K) || ((MSI_RANGE) == RCC_MSI_RANGE_800K) \
+ || ((MSI_RANGE) == RCC_MSI_RANGE_1M) || ((MSI_RANGE) == RCC_MSI_RANGE_2M) \
+ || ((MSI_RANGE) == RCC_MSI_RANGE_4M) \
+ )
+
+/**
+ * @}
+ */
+
+/** @addtogroup PLL_entry_clock_source
+ * @{
+ */
+#define RCC_PLL_HSI_PRE_DIV1 ((uint32_t)0x00000000)
+#define RCC_PLL_HSI_PRE_DIV2 ((uint32_t)0x00000001)
+
+#define RCC_PLL_SRC_HSE_DIV1 ((uint32_t)0x00010000)
+#define RCC_PLL_SRC_HSE_DIV2 ((uint32_t)0x00030000)
+#define IS_RCC_PLL_SRC(SOURCE) \
+ (((SOURCE) == RCC_PLL_HSI_PRE_DIV1) || ((SOURCE) == RCC_PLL_HSI_PRE_DIV2) \
+ || ((SOURCE) == RCC_PLL_SRC_HSE_DIV1) || ((SOURCE) == RCC_PLL_SRC_HSE_DIV2))
+
+#define RCC_PLLDIVCLK_DISABLE ((uint32_t)0x00000000)
+#define RCC_PLLDIVCLK_ENABLE ((uint32_t)0x00000002)
+#define IS_RCC_PLL_DIVCLK(DIVCLK) \
+ (((DIVCLK) == RCC_PLLDIVCLK_DISABLE) || ((DIVCLK) == RCC_PLLDIVCLK_ENABLE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup PLL_multiplication_factor
+ * @{
+ */
+#define RCC_PLL_MUL_2 ((uint32_t)0x00000000)
+#define RCC_PLL_MUL_3 ((uint32_t)0x00040000)
+#define RCC_PLL_MUL_4 ((uint32_t)0x00080000)
+#define RCC_PLL_MUL_5 ((uint32_t)0x000C0000)
+#define RCC_PLL_MUL_6 ((uint32_t)0x00100000)
+#define RCC_PLL_MUL_7 ((uint32_t)0x00140000)
+#define RCC_PLL_MUL_8 ((uint32_t)0x00180000)
+#define RCC_PLL_MUL_9 ((uint32_t)0x001C0000)
+#define RCC_PLL_MUL_10 ((uint32_t)0x00200000)
+#define RCC_PLL_MUL_11 ((uint32_t)0x00240000)
+#define RCC_PLL_MUL_12 ((uint32_t)0x00280000)
+#define RCC_PLL_MUL_13 ((uint32_t)0x002C0000)
+#define RCC_PLL_MUL_14 ((uint32_t)0x00300000)
+#define RCC_PLL_MUL_15 ((uint32_t)0x00340000)
+#define RCC_PLL_MUL_16 ((uint32_t)0x00380000)
+#define RCC_PLL_MUL_17 ((uint32_t)0x08000000)
+#define RCC_PLL_MUL_18 ((uint32_t)0x08040000)
+#define RCC_PLL_MUL_19 ((uint32_t)0x08080000)
+#define RCC_PLL_MUL_20 ((uint32_t)0x080C0000)
+#define RCC_PLL_MUL_21 ((uint32_t)0x08100000)
+#define RCC_PLL_MUL_22 ((uint32_t)0x08140000)
+#define RCC_PLL_MUL_23 ((uint32_t)0x08180000)
+#define RCC_PLL_MUL_24 ((uint32_t)0x081C0000)
+#define RCC_PLL_MUL_25 ((uint32_t)0x08200000)
+#define RCC_PLL_MUL_26 ((uint32_t)0x08240000)
+#define RCC_PLL_MUL_27 ((uint32_t)0x08280000)
+#define RCC_PLL_MUL_28 ((uint32_t)0x082C0000)
+#define RCC_PLL_MUL_29 ((uint32_t)0x08300000)
+#define RCC_PLL_MUL_30 ((uint32_t)0x08340000)
+#define RCC_PLL_MUL_31 ((uint32_t)0x08380000)
+#define RCC_PLL_MUL_32 ((uint32_t)0x083C0000)
+#define IS_RCC_PLL_MUL(MUL) \
+ (((MUL) == RCC_PLL_MUL_2) || ((MUL) == RCC_PLL_MUL_3) || ((MUL) == RCC_PLL_MUL_4) || ((MUL) == RCC_PLL_MUL_5) \
+ || ((MUL) == RCC_PLL_MUL_6) || ((MUL) == RCC_PLL_MUL_7) || ((MUL) == RCC_PLL_MUL_8) || ((MUL) == RCC_PLL_MUL_9) \
+ || ((MUL) == RCC_PLL_MUL_10) || ((MUL) == RCC_PLL_MUL_11) || ((MUL) == RCC_PLL_MUL_12) \
+ || ((MUL) == RCC_PLL_MUL_13) || ((MUL) == RCC_PLL_MUL_14) || ((MUL) == RCC_PLL_MUL_15) \
+ || ((MUL) == RCC_PLL_MUL_16) || ((MUL) == RCC_PLL_MUL_17) || ((MUL) == RCC_PLL_MUL_18) \
+ || ((MUL) == RCC_PLL_MUL_19) || ((MUL) == RCC_PLL_MUL_20) || ((MUL) == RCC_PLL_MUL_21) \
+ || ((MUL) == RCC_PLL_MUL_22) || ((MUL) == RCC_PLL_MUL_23) || ((MUL) == RCC_PLL_MUL_24) \
+ || ((MUL) == RCC_PLL_MUL_25) || ((MUL) == RCC_PLL_MUL_26) || ((MUL) == RCC_PLL_MUL_27) \
+ || ((MUL) == RCC_PLL_MUL_28) || ((MUL) == RCC_PLL_MUL_29) || ((MUL) == RCC_PLL_MUL_30) \
+ || ((MUL) == RCC_PLL_MUL_31) || ((MUL) == RCC_PLL_MUL_32))
+
+/**
+ * @}
+ */
+
+/** @addtogroup System_clock_source
+ * @{
+ */
+
+#define RCC_SYSCLK_SRC_MSI ((uint32_t)0x00000000)
+#define RCC_SYSCLK_SRC_HSI ((uint32_t)0x00000001)
+#define RCC_SYSCLK_SRC_HSE ((uint32_t)0x00000002)
+#define RCC_SYSCLK_SRC_PLLCLK ((uint32_t)0x00000003)
+#define IS_RCC_SYSCLK_SRC(SOURCE) \
+ (((SOURCE) == RCC_SYSCLK_SRC_MSI) || ((SOURCE) == RCC_SYSCLK_SRC_HSI) \
+ || ((SOURCE) == RCC_SYSCLK_SRC_HSE) || ((SOURCE) == RCC_SYSCLK_SRC_PLLCLK))
+/**
+ * @}
+ */
+
+/** @addtogroup AHB_clock_source
+ * @{
+ */
+
+#define RCC_SYSCLK_DIV1 ((uint32_t)0x00000000)
+#define RCC_SYSCLK_DIV2 ((uint32_t)0x00000080)
+#define RCC_SYSCLK_DIV4 ((uint32_t)0x00000090)
+#define RCC_SYSCLK_DIV8 ((uint32_t)0x000000A0)
+#define RCC_SYSCLK_DIV16 ((uint32_t)0x000000B0)
+#define RCC_SYSCLK_DIV64 ((uint32_t)0x000000C0)
+#define RCC_SYSCLK_DIV128 ((uint32_t)0x000000D0)
+#define RCC_SYSCLK_DIV256 ((uint32_t)0x000000E0)
+#define RCC_SYSCLK_DIV512 ((uint32_t)0x000000F0)
+#define IS_RCC_SYSCLK_DIV(HCLK) \
+ (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || ((HCLK) == RCC_SYSCLK_DIV4) \
+ || ((HCLK) == RCC_SYSCLK_DIV8) || ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) \
+ || ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || ((HCLK) == RCC_SYSCLK_DIV512))
+/**
+ * @}
+ */
+
+/** @addtogroup APB1_APB2_clock_source
+ * @{
+ */
+
+#define RCC_HCLK_DIV1 ((uint32_t)0x00000000)
+#define RCC_HCLK_DIV2 ((uint32_t)0x00000400)
+#define RCC_HCLK_DIV4 ((uint32_t)0x00000500)
+#define RCC_HCLK_DIV8 ((uint32_t)0x00000600)
+#define RCC_HCLK_DIV16 ((uint32_t)0x00000700)
+#define IS_RCC_HCLK_DIV(PCLK) \
+ (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) \
+ || ((PCLK) == RCC_HCLK_DIV16))
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Interrupt_source
+ * @{
+ */
+
+#define RCC_INT_LSIRDIF ((uint8_t)0x01)
+#define RCC_INT_LSERDIF ((uint8_t)0x02)
+#define RCC_INT_HSIRDIF ((uint8_t)0x04)
+#define RCC_INT_HSERDIF ((uint8_t)0x08)
+#define RCC_INT_PLLRDIF ((uint8_t)0x10)
+#define RCC_INT_BORIF ((uint8_t)0x20)
+#define RCC_INT_MSIRDIF ((uint8_t)0x40)
+#define RCC_INT_CLKSSIF ((uint8_t)0x80)
+
+#define IS_RCC_INT(IT) \
+ (((IT) == RCC_INT_LSIRDIF) || ((IT) == RCC_INT_LSERDIF) || ((IT) == RCC_INT_HSIRDIF) || ((IT) == RCC_INT_HSERDIF) \
+ || ((IT) == RCC_INT_PLLRDIF) || ((IT) == RCC_INT_BORIF) || ((IT) == RCC_INT_MSIRDIF))
+
+#define IS_RCC_GET_INT(IT) \
+ (((IT) == RCC_INT_LSIRDIF) || ((IT) == RCC_INT_LSERDIF) || ((IT) == RCC_INT_HSIRDIF) || ((IT) == RCC_INT_HSERDIF) \
+ || ((IT) == RCC_INT_PLLRDIF) || ((IT) == RCC_INT_BORIF) || ((IT) == RCC_INT_MSIRDIF) || ((IT) == RCC_INT_CLKSSIF))
+
+#define RCC_CLR_MSIRDIF ((uint32_t)0x00008000)
+#define RCC_CLR_LSIRDIF ((uint32_t)0x00010000)
+#define RCC_CLR_LSERDIF ((uint32_t)0x00020000)
+#define RCC_CLR_HSIRDIF ((uint32_t)0x00040000)
+#define RCC_CLR_HSERDIF ((uint32_t)0x00080000)
+#define RCC_CLR_PLLRDIF ((uint32_t)0x00100000)
+#define RCC_CLR_BORIF ((uint32_t)0x00200000)
+#define RCC_CLR_CLKSSIF ((uint32_t)0x00800000)
+
+#define IS_RCC_CLR_INTF(IT) \
+ (((IT) == RCC_CLR_LSIRDIF) || ((IT) == RCC_CLR_LSERDIF) || ((IT) == RCC_CLR_HSIRDIF) || ((IT) == RCC_CLR_HSERDIF) \
+ || ((IT) == RCC_CLR_PLLRDIF) || ((IT) == RCC_CLR_BORIF) || ((IT) == RCC_CLR_MSIRDIF) || ((IT) == RCC_CLR_CLKSSIF))
+
+/**
+ * @}
+ */
+
+/** @addtogroup USB_Device_clock_source
+ * @{
+ */
+
+#define RCC_USBCLK_SRC_PLLCLK_DIV1_5 ((uint8_t)0x00)
+#define RCC_USBCLK_SRC_PLLCLK_DIV1 ((uint8_t)0x01)
+#define RCC_USBCLK_SRC_PLLCLK_DIV2 ((uint8_t)0x02)
+#define RCC_USBCLK_SRC_PLLCLK_DIV3 ((uint8_t)0x03)
+
+#define IS_RCC_USBCLK_SRC(SOURCE) \
+ (((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV1_5) || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV1) \
+ || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV2) || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV3))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_clock_source
+ * @{
+ */
+
+#define RCC_PCLK2_DIV2 ((uint32_t)0x00000000)
+#define RCC_PCLK2_DIV4 ((uint32_t)0x00004000)
+#define RCC_PCLK2_DIV6 ((uint32_t)0x00008000)
+#define RCC_PCLK2_DIV8 ((uint32_t)0x0000C000)
+#define IS_RCC_PCLK2_DIV(ADCCLK) \
+ (((ADCCLK) == RCC_PCLK2_DIV2) || ((ADCCLK) == RCC_PCLK2_DIV4) || ((ADCCLK) == RCC_PCLK2_DIV6) \
+ || ((ADCCLK) == RCC_PCLK2_DIV8))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_CFGR2_Config
+ * @{
+ */
+#define RCC_TIM18CLK_SRC_TIM18CLK ((uint32_t)0x00000000)
+#define RCC_TIM18CLK_SRC_SYSCLK ((uint32_t)0x20000000)
+#define IS_RCC_TIM18CLKSRC(TIM18CLK) \
+ (((TIM18CLK) == RCC_TIM18CLK_SRC_TIM18CLK) || ((TIM18CLK) == RCC_TIM18CLK_SRC_SYSCLK))
+
+#define RCC_RNGCCLK_SYSCLK_DIV1 ((uint32_t)0x00000000)
+#define RCC_RNGCCLK_SYSCLK_DIV2 ((uint32_t)0x01000000)
+#define RCC_RNGCCLK_SYSCLK_DIV3 ((uint32_t)0x02000000)
+#define RCC_RNGCCLK_SYSCLK_DIV4 ((uint32_t)0x03000000)
+#define RCC_RNGCCLK_SYSCLK_DIV5 ((uint32_t)0x04000000)
+#define RCC_RNGCCLK_SYSCLK_DIV6 ((uint32_t)0x05000000)
+#define RCC_RNGCCLK_SYSCLK_DIV7 ((uint32_t)0x06000000)
+#define RCC_RNGCCLK_SYSCLK_DIV8 ((uint32_t)0x07000000)
+#define RCC_RNGCCLK_SYSCLK_DIV9 ((uint32_t)0x08000000)
+#define RCC_RNGCCLK_SYSCLK_DIV10 ((uint32_t)0x09000000)
+#define RCC_RNGCCLK_SYSCLK_DIV11 ((uint32_t)0x0A000000)
+#define RCC_RNGCCLK_SYSCLK_DIV12 ((uint32_t)0x0B000000)
+#define RCC_RNGCCLK_SYSCLK_DIV13 ((uint32_t)0x0C000000)
+#define RCC_RNGCCLK_SYSCLK_DIV14 ((uint32_t)0x0D000000)
+#define RCC_RNGCCLK_SYSCLK_DIV15 ((uint32_t)0x0E000000)
+#define RCC_RNGCCLK_SYSCLK_DIV16 ((uint32_t)0x0F000000)
+#define RCC_RNGCCLK_SYSCLK_DIV17 ((uint32_t)0x10000000)
+#define RCC_RNGCCLK_SYSCLK_DIV18 ((uint32_t)0x11000000)
+#define RCC_RNGCCLK_SYSCLK_DIV19 ((uint32_t)0x12000000)
+#define RCC_RNGCCLK_SYSCLK_DIV20 ((uint32_t)0x13000000)
+#define RCC_RNGCCLK_SYSCLK_DIV21 ((uint32_t)0x14000000)
+#define RCC_RNGCCLK_SYSCLK_DIV22 ((uint32_t)0x15000000)
+#define RCC_RNGCCLK_SYSCLK_DIV23 ((uint32_t)0x16000000)
+#define RCC_RNGCCLK_SYSCLK_DIV24 ((uint32_t)0x17000000)
+#define RCC_RNGCCLK_SYSCLK_DIV25 ((uint32_t)0x18000000)
+#define RCC_RNGCCLK_SYSCLK_DIV26 ((uint32_t)0x19000000)
+#define RCC_RNGCCLK_SYSCLK_DIV27 ((uint32_t)0x1A000000)
+#define RCC_RNGCCLK_SYSCLK_DIV28 ((uint32_t)0x1B000000)
+#define RCC_RNGCCLK_SYSCLK_DIV29 ((uint32_t)0x1C000000)
+#define RCC_RNGCCLK_SYSCLK_DIV30 ((uint32_t)0x1D000000)
+#define RCC_RNGCCLK_SYSCLK_DIV31 ((uint32_t)0x1E000000)
+#define RCC_RNGCCLK_SYSCLK_DIV32 ((uint32_t)0x1F000000)
+#define IS_RCC_RNGCCLKPRE(DIV) \
+ (((DIV) == RCC_RNGCCLK_SYSCLK_DIV1) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV2) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV3) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV4) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV5) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV6) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV7) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV8) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV9) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV10) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV11) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV12) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV13) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV14) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV15) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV16) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV17) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV18) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV19) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV20) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV21) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV22) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV23) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV24) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV25) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV26) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV27) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV28) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV29) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV30) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV31) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV32))
+
+#define RCC_ADC1MCLK_SRC_HSI ((uint32_t)0x00000000)
+#define RCC_ADC1MCLK_SRC_HSE ((uint32_t)0x00020000)
+#define IS_RCC_ADC1MCLKSRC(ADC1MCLK) (((ADC1MCLK) == RCC_ADC1MCLK_SRC_HSI) || ((ADC1MCLK) == RCC_ADC1MCLK_SRC_HSE))
+
+#define RCC_ADC1MCLK_DIV1 ((uint32_t)0x00000000)
+#define RCC_ADC1MCLK_DIV2 ((uint32_t)0x00001000)
+#define RCC_ADC1MCLK_DIV3 ((uint32_t)0x00002000)
+#define RCC_ADC1MCLK_DIV4 ((uint32_t)0x00003000)
+#define RCC_ADC1MCLK_DIV5 ((uint32_t)0x00004000)
+#define RCC_ADC1MCLK_DIV6 ((uint32_t)0x00005000)
+#define RCC_ADC1MCLK_DIV7 ((uint32_t)0x00006000)
+#define RCC_ADC1MCLK_DIV8 ((uint32_t)0x00007000)
+#define RCC_ADC1MCLK_DIV9 ((uint32_t)0x00008000)
+#define RCC_ADC1MCLK_DIV10 ((uint32_t)0x00009000)
+#define RCC_ADC1MCLK_DIV11 ((uint32_t)0x0000A000)
+#define RCC_ADC1MCLK_DIV12 ((uint32_t)0x0000B000)
+#define RCC_ADC1MCLK_DIV13 ((uint32_t)0x0000C000)
+#define RCC_ADC1MCLK_DIV14 ((uint32_t)0x0000D000)
+#define RCC_ADC1MCLK_DIV15 ((uint32_t)0x0000E000)
+#define RCC_ADC1MCLK_DIV16 ((uint32_t)0x0000F000)
+#define RCC_ADC1MCLK_DIV17 ((uint32_t)0x00010000)
+#define RCC_ADC1MCLK_DIV18 ((uint32_t)0x00011000)
+#define RCC_ADC1MCLK_DIV19 ((uint32_t)0x00012000)
+#define RCC_ADC1MCLK_DIV20 ((uint32_t)0x00013000)
+#define RCC_ADC1MCLK_DIV21 ((uint32_t)0x00014000)
+#define RCC_ADC1MCLK_DIV22 ((uint32_t)0x00015000)
+#define RCC_ADC1MCLK_DIV23 ((uint32_t)0x00016000)
+#define RCC_ADC1MCLK_DIV24 ((uint32_t)0x00017000)
+#define RCC_ADC1MCLK_DIV25 ((uint32_t)0x00018000)
+#define RCC_ADC1MCLK_DIV26 ((uint32_t)0x00019000)
+#define RCC_ADC1MCLK_DIV27 ((uint32_t)0x0001A000)
+#define RCC_ADC1MCLK_DIV28 ((uint32_t)0x0001B000)
+#define RCC_ADC1MCLK_DIV29 ((uint32_t)0x0001C000)
+#define RCC_ADC1MCLK_DIV30 ((uint32_t)0x0001D000)
+#define RCC_ADC1MCLK_DIV31 ((uint32_t)0x0001E000)
+#define RCC_ADC1MCLK_DIV32 ((uint32_t)0x0001F000)
+#define IS_RCC_ADC1MCLKPRE(DIV) \
+ (((DIV) == RCC_ADC1MCLK_DIV1) || ((DIV) == RCC_ADC1MCLK_DIV2) || ((DIV) == RCC_ADC1MCLK_DIV3) \
+ || ((DIV) == RCC_ADC1MCLK_DIV4) || ((DIV) == RCC_ADC1MCLK_DIV5) || ((DIV) == RCC_ADC1MCLK_DIV6) \
+ || ((DIV) == RCC_ADC1MCLK_DIV7) || ((DIV) == RCC_ADC1MCLK_DIV8) || ((DIV) == RCC_ADC1MCLK_DIV9) \
+ || ((DIV) == RCC_ADC1MCLK_DIV10) || ((DIV) == RCC_ADC1MCLK_DIV11) || ((DIV) == RCC_ADC1MCLK_DIV12) \
+ || ((DIV) == RCC_ADC1MCLK_DIV13) || ((DIV) == RCC_ADC1MCLK_DIV14) || ((DIV) == RCC_ADC1MCLK_DIV15) \
+ || ((DIV) == RCC_ADC1MCLK_DIV16) || ((DIV) == RCC_ADC1MCLK_DIV17) || ((DIV) == RCC_ADC1MCLK_DIV18) \
+ || ((DIV) == RCC_ADC1MCLK_DIV19) || ((DIV) == RCC_ADC1MCLK_DIV20) || ((DIV) == RCC_ADC1MCLK_DIV21) \
+ || ((DIV) == RCC_ADC1MCLK_DIV22) || ((DIV) == RCC_ADC1MCLK_DIV23) || ((DIV) == RCC_ADC1MCLK_DIV24) \
+ || ((DIV) == RCC_ADC1MCLK_DIV25) || ((DIV) == RCC_ADC1MCLK_DIV26) || ((DIV) == RCC_ADC1MCLK_DIV27) \
+ || ((DIV) == RCC_ADC1MCLK_DIV28) || ((DIV) == RCC_ADC1MCLK_DIV29) || ((DIV) == RCC_ADC1MCLK_DIV30) \
+ || ((DIV) == RCC_ADC1MCLK_DIV31) || ((DIV) == RCC_ADC1MCLK_DIV32))
+
+#define RCC_ADCPLLCLK_DISABLE ((uint32_t)0xFFFFFEFF)
+#define RCC_ADCPLLCLK_DIV1 ((uint32_t)0x00000100)
+#define RCC_ADCPLLCLK_DIV2 ((uint32_t)0x00000110)
+#define RCC_ADCPLLCLK_DIV4 ((uint32_t)0x00000120)
+#define RCC_ADCPLLCLK_DIV6 ((uint32_t)0x00000130)
+#define RCC_ADCPLLCLK_DIV8 ((uint32_t)0x00000140)
+#define RCC_ADCPLLCLK_DIV10 ((uint32_t)0x00000150)
+#define RCC_ADCPLLCLK_DIV12 ((uint32_t)0x00000160)
+#define RCC_ADCPLLCLK_DIV16 ((uint32_t)0x00000170)
+#define RCC_ADCPLLCLK_DIV32 ((uint32_t)0x00000180)
+#define RCC_ADCPLLCLK_DIV64 ((uint32_t)0x00000190)
+#define RCC_ADCPLLCLK_DIV128 ((uint32_t)0x000001A0)
+#define RCC_ADCPLLCLK_DIV256 ((uint32_t)0x000001B0)
+#define RCC_ADCPLLCLK_DIV_OTHERS ((uint32_t)0x000001C0)
+#define IS_RCC_ADCPLLCLKPRE(DIV) \
+ (((DIV) == RCC_ADCPLLCLK_DIV1) || ((DIV) == RCC_ADCPLLCLK_DIV2) || ((DIV) == RCC_ADCPLLCLK_DIV4) \
+ || ((DIV) == RCC_ADCPLLCLK_DIV6) || ((DIV) == RCC_ADCPLLCLK_DIV8) || ((DIV) == RCC_ADCPLLCLK_DIV10) \
+ || ((DIV) == RCC_ADCPLLCLK_DIV12) || ((DIV) == RCC_ADCPLLCLK_DIV16) || ((DIV) == RCC_ADCPLLCLK_DIV32) \
+ || ((DIV) == RCC_ADCPLLCLK_DIV64) || ((DIV) == RCC_ADCPLLCLK_DIV128) || ((DIV) == RCC_ADCPLLCLK_DIV256) \
+ || (((DIV)&RCC_ADCPLLCLK_DIV_OTHERS) == 0x000001C0))
+
+#define RCC_ADCHCLK_DIV1 ((uint32_t)0x00000000)
+#define RCC_ADCHCLK_DIV2 ((uint32_t)0x00000001)
+#define RCC_ADCHCLK_DIV4 ((uint32_t)0x00000002)
+#define RCC_ADCHCLK_DIV6 ((uint32_t)0x00000003)
+#define RCC_ADCHCLK_DIV8 ((uint32_t)0x00000004)
+#define RCC_ADCHCLK_DIV10 ((uint32_t)0x00000005)
+#define RCC_ADCHCLK_DIV12 ((uint32_t)0x00000006)
+#define RCC_ADCHCLK_DIV16 ((uint32_t)0x00000007)
+#define RCC_ADCHCLK_DIV32 ((uint32_t)0x00000008)
+#define RCC_ADCHCLK_DIV_OTHERS ((uint32_t)0x00000008)
+#define IS_RCC_ADCHCLKPRE(DIV) \
+ (((DIV) == RCC_ADCHCLK_DIV1) || ((DIV) == RCC_ADCHCLK_DIV2) || ((DIV) == RCC_ADCHCLK_DIV4) \
+ || ((DIV) == RCC_ADCHCLK_DIV6) || ((DIV) == RCC_ADCHCLK_DIV8) || ((DIV) == RCC_ADCHCLK_DIV10) \
+ || ((DIV) == RCC_ADCHCLK_DIV12) || ((DIV) == RCC_ADCHCLK_DIV16) || ((DIV) == RCC_ADCHCLK_DIV32) \
+ || (((DIV)&RCC_ADCHCLK_DIV_OTHERS) != 0x00))
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_CFGR3_Config
+ * @{
+ */
+
+#define RCC_TRNG1MCLK_ENABLE ((uint32_t)0x00040000)
+#define RCC_TRNG1MCLK_DISABLE ((uint32_t)0xFFFBFFFF)
+
+#define RCC_TRNG1MCLK_SRC_HSI ((uint32_t)0x00000000)
+#define RCC_TRNG1MCLK_SRC_HSE ((uint32_t)0x00020000)
+#define IS_RCC_TRNG1MCLK_SRC(TRNG1MCLK) \
+ (((TRNG1MCLK) == RCC_TRNG1MCLK_SRC_HSI) || ((TRNG1MCLK) == RCC_TRNG1MCLK_SRC_HSE))
+
+#define RCC_TRNG1MCLK_DIV2 ((uint32_t)0x00000800)
+#define RCC_TRNG1MCLK_DIV4 ((uint32_t)0x00001000)
+#define RCC_TRNG1MCLK_DIV6 ((uint32_t)0x00001800)
+#define RCC_TRNG1MCLK_DIV8 ((uint32_t)0x00002000)
+#define RCC_TRNG1MCLK_DIV10 ((uint32_t)0x00002800)
+#define RCC_TRNG1MCLK_DIV12 ((uint32_t)0x00003000)
+#define RCC_TRNG1MCLK_DIV14 ((uint32_t)0x00003800)
+#define RCC_TRNG1MCLK_DIV16 ((uint32_t)0x00004000)
+#define RCC_TRNG1MCLK_DIV18 ((uint32_t)0x00004800)
+#define RCC_TRNG1MCLK_DIV20 ((uint32_t)0x00005000)
+#define RCC_TRNG1MCLK_DIV22 ((uint32_t)0x00005800)
+#define RCC_TRNG1MCLK_DIV24 ((uint32_t)0x00006000)
+#define RCC_TRNG1MCLK_DIV26 ((uint32_t)0x00006800)
+#define RCC_TRNG1MCLK_DIV28 ((uint32_t)0x00007000)
+#define RCC_TRNG1MCLK_DIV30 ((uint32_t)0x00007800)
+#define RCC_TRNG1MCLK_DIV32 ((uint32_t)0x00008000)
+#define RCC_TRNG1MCLK_DIV34 ((uint32_t)0x00008800)
+#define RCC_TRNG1MCLK_DIV36 ((uint32_t)0x00009000)
+#define RCC_TRNG1MCLK_DIV38 ((uint32_t)0x00009800)
+#define RCC_TRNG1MCLK_DIV40 ((uint32_t)0x0000A000)
+#define RCC_TRNG1MCLK_DIV42 ((uint32_t)0x0000A800)
+#define RCC_TRNG1MCLK_DIV44 ((uint32_t)0x0000B000)
+#define RCC_TRNG1MCLK_DIV46 ((uint32_t)0x0000B800)
+#define RCC_TRNG1MCLK_DIV48 ((uint32_t)0x0000C000)
+#define RCC_TRNG1MCLK_DIV50 ((uint32_t)0x0000C800)
+#define RCC_TRNG1MCLK_DIV52 ((uint32_t)0x0000D000)
+#define RCC_TRNG1MCLK_DIV54 ((uint32_t)0x0000D800)
+#define RCC_TRNG1MCLK_DIV56 ((uint32_t)0x0000E000)
+#define RCC_TRNG1MCLK_DIV58 ((uint32_t)0x0000E800)
+#define RCC_TRNG1MCLK_DIV60 ((uint32_t)0x0000F000)
+#define RCC_TRNG1MCLK_DIV62 ((uint32_t)0x0000F800)
+#define IS_RCC_TRNG1MCLKPRE(VAL) \
+ (((VAL) == RCC_TRNG1MCLK_DIV2) || ((VAL) == RCC_TRNG1MCLK_DIV4) || ((VAL) == RCC_TRNG1MCLK_DIV6) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV8) || ((VAL) == RCC_TRNG1MCLK_DIV10) || ((VAL) == RCC_TRNG1MCLK_DIV12) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV14) || ((VAL) == RCC_TRNG1MCLK_DIV16) || ((VAL) == RCC_TRNG1MCLK_DIV18) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV20) || ((VAL) == RCC_TRNG1MCLK_DIV22) || ((VAL) == RCC_TRNG1MCLK_DIV24) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV26) || ((VAL) == RCC_TRNG1MCLK_DIV28) || ((VAL) == RCC_TRNG1MCLK_DIV30) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV32) || ((VAL) == RCC_TRNG1MCLK_DIV34) || ((VAL) == RCC_TRNG1MCLK_DIV36) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV38) || ((VAL) == RCC_TRNG1MCLK_DIV40) || ((VAL) == RCC_TRNG1MCLK_DIV42) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV44) || ((VAL) == RCC_TRNG1MCLK_DIV46) || ((VAL) == RCC_TRNG1MCLK_DIV48) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV50) || ((VAL) == RCC_TRNG1MCLK_DIV52) || ((VAL) == RCC_TRNG1MCLK_DIV54) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV56) || ((VAL) == RCC_TRNG1MCLK_DIV58) || ((VAL) == RCC_TRNG1MCLK_DIV60) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV62))
+
+#define RCC_UCDR_ENABLE ((uint32_t)0x00000080)
+#define RCC_UCDR_DISABLE ((uint32_t)0xFFFFFF7F)
+
+#define RCC_UCDR300MSource_MASK ((uint32_t)0xFFFFFDFF)
+#define RCC_UCDR300M_SRC_OSC300M ((uint32_t)0x00000000)
+#define RCC_UCDR300M_SRC_PLLVCO ((uint32_t)0x00000200)
+#define IS_RCC_UCDR300M_SRC(UCDR300MCLK) \
+ (((UCDR300MCLK) == RCC_UCDR300M_SRC_OSC300M) || ((UCDR300MCLK) == RCC_UCDR300M_SRC_PLLVCO))
+
+#define RCC_USBXTALESSMode_MASK ((uint32_t)0xFFFFFEFF)
+#define RCC_USBXTALESS_MODE ((uint32_t)0x00000000)
+#define RCC_USBXTALESS_LESSMODE ((uint32_t)0x00000100)
+#define IS_RCC_USBXTALESS_MODE(USBXTALESS) \
+ (((USBXTALESS) == RCC_USBXTALESS_MODE) || ((USBXTALESS) == RCC_USBXTALESS_LESSMODE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup LSE_configuration
+ * @{
+ */
+
+#define RCC_LSE_DISABLE ((uint32_t)0x00000000)
+#define RCC_LSE_ENABLE ((uint32_t)0x00000001)
+#define RCC_LSE_BYPASS ((uint32_t)0x00000004)
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_DISABLE) || ((LSE) == RCC_LSE_ENABLE) || ((LSE) == RCC_LSE_BYPASS))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_clock_source
+ * @{
+ */
+
+#define RCC_RTCCLK_SRC_NONE ((uint32_t)0x00000000)
+#define RCC_RTCCLK_SRC_LSE ((uint32_t)0x00000100)
+#define RCC_RTCCLK_SRC_LSI ((uint32_t)0x00000200)
+#define RCC_RTCCLK_SRC_HSE_DIV32 ((uint32_t)0x00000300)
+#define IS_RCC_RTCCLK_SRC(SOURCE) \
+ (((SOURCE) == RCC_RTCCLK_SRC_NONE) || ((SOURCE) == RCC_RTCCLK_SRC_LSE) || ((SOURCE) == RCC_RTCCLK_SRC_LSI) \
+ || ((SOURCE) == RCC_RTCCLK_SRC_HSE_DIV32))
+/**
+ * @}
+ */
+
+/** @addtogroup LSX_clock_source
+ * @{
+ */
+
+#define RCC_LSXCLK_SRC_LSI ((uint32_t)0x00000000)
+#define RCC_LSXCLK_SRC_LSE ((uint32_t)0x00000020)
+#define IS_RCC_LSXCLK_SRC(SOURCE) \
+ (((SOURCE) == RCC_LSXCLK_SRC_LSI) || ((SOURCE) == RCC_LSXCLK_SRC_LSE))
+/**
+ * @}
+ */
+
+/** @addtogroup AHB_peripheral
+ * @{
+ */
+
+#define RCC_AHB_PERIPH_DMA ((uint32_t)0x00000001)
+#define RCC_AHB_PERIPH_SRAM ((uint32_t)0x00000004)
+#define RCC_AHB_PERIPH_FLITF ((uint32_t)0x00000010)
+#define RCC_AHB_PERIPH_CRC ((uint32_t)0x00000040)
+#define RCC_AHB_PERIPH_RNGC ((uint32_t)0x00000200)
+#define RCC_AHB_PERIPH_SAC ((uint32_t)0x00000800)
+#define RCC_AHB_PERIPH_ADC ((uint32_t)0x00001000)
+
+#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH)&0xFFFFE5AA) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @addtogroup APB2_peripheral
+ * @{
+ */
+
+#define RCC_APB2_PERIPH_AFIO ((uint32_t)0x00000001)
+#define RCC_APB2_PERIPH_GPIOA ((uint32_t)0x00000004)
+#define RCC_APB2_PERIPH_GPIOB ((uint32_t)0x00000008)
+#define RCC_APB2_PERIPH_GPIOC ((uint32_t)0x00000010)
+#define RCC_APB2_PERIPH_GPIOD ((uint32_t)0x00000020)
+#define RCC_APB2_PERIPH_TIM1 ((uint32_t)0x00000800)
+#define RCC_APB2_PERIPH_SPI1 ((uint32_t)0x00001000)
+#define RCC_APB2_PERIPH_TIM8 ((uint32_t)0x00002000)
+#define RCC_APB2_PERIPH_USART1 ((uint32_t)0x00004000)
+#define RCC_APB2_PERIPH_UART4 ((uint32_t)0x00020000)
+#define RCC_APB2_PERIPH_UART5 ((uint32_t)0x00040000)
+#define RCC_APB2_PERIPH_SPI2 ((uint32_t)0x00080000)
+
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH)&0xFFF187C2) == 0x00) && ((PERIPH) != 0x00))
+/**
+ * @}
+ */
+
+/** @addtogroup APB1_peripheral
+ * @{
+ */
+
+#define RCC_APB1_PERIPH_TIM2 ((uint32_t)0x00000001)
+#define RCC_APB1_PERIPH_TIM3 ((uint32_t)0x00000002)
+#define RCC_APB1_PERIPH_TIM4 ((uint32_t)0x00000004)
+#define RCC_APB1_PERIPH_TIM5 ((uint32_t)0x00000008)
+#define RCC_APB1_PERIPH_TIM6 ((uint32_t)0x00000010)
+#define RCC_APB1_PERIPH_TIM7 ((uint32_t)0x00000020)
+#define RCC_APB1_PERIPH_COMP ((uint32_t)0x00000040)
+#define RCC_APB1_PERIPH_COMP_FILT ((uint32_t)0x00000080)
+#define RCC_APB1_PERIPH_AFEC ((uint32_t)0x00000100)
+#define RCC_APB1_PERIPH_TIM9 ((uint32_t)0x00000200)
+#define RCC_APB1_PERIPH_TSC ((uint32_t)0x00000400)
+#define RCC_APB1_PERIPH_WWDG ((uint32_t)0x00000800)
+#define RCC_APB1_PERIPH_USART2 ((uint32_t)0x00020000)
+#define RCC_APB1_PERIPH_USART3 ((uint32_t)0x00040000)
+#define RCC_APB1_PERIPH_I2C1 ((uint32_t)0x00200000)
+#define RCC_APB1_PERIPH_I2C2 ((uint32_t)0x00400000)
+#define RCC_APB1_PERIPH_USB ((uint32_t)0x00800000)
+#define RCC_APB1_PERIPH_CAN ((uint32_t)0x02000000)
+#define RCC_APB1_PERIPH_PWR ((uint32_t)0x10000000)
+#define RCC_APB1_PERIPH_DAC ((uint32_t)0x20000000)
+#define RCC_APB1_PERIPH_OPAMP ((uint32_t)0x80000000)
+
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH)&0x4D19F000) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RET_peripheral
+ * @{
+ */
+
+#define RCC_RET_PERIPH_LPTIM ((uint32_t)0x00000040)
+#define RCC_RET_PERIPH_LPUART ((uint32_t)0x00000080)
+#define RCC_RET_PERIPH_LCD ((uint32_t)0x00000100)
+
+
+#define IS_RCC_RET_PERIPH(PERIPH) ((((PERIPH)&0xFFFFFC3F) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPTIM
+ * @{
+ */
+#define RCC_LPTIMCLK_SRC_MASK ((uint32_t)0xFFFFFFF8)
+
+#define RCC_LPTIMCLK_SRC_APB1 ((uint32_t)0x00000000)
+#define RCC_LPTIMCLK_SRC_LSI ((uint32_t)0x00000001)
+#define RCC_LPTIMCLK_SRC_HSI ((uint32_t)0x00000002)
+#define RCC_LPTIMCLK_SRC_LSE ((uint32_t)0x00000003)
+#define RCC_LPTIMCLK_SRC_COMP1 ((uint32_t)0x00000004)
+#define RCC_LPTIMCLK_SRC_COMP2 ((uint32_t)0x00000005)
+
+#define IS_RCC_LPTIM_CLK(LPTIMCLK) (((LPTIMCLK) == RCC_LPTIMCLK_SRC_APB1) \
+ || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_LSI) \
+ || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_HSI) \
+ || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_LSE) \
+ || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_COMP1) \
+ || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_COMP2))
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART
+ * @{
+ */
+#define RCC_LPUARTCLK_SRC_MASK ((uint32_t)0xFFFFFFE7)
+
+#define RCC_LPUARTCLK_SRC_APB1 ((uint32_t)0x00000000)
+#define RCC_LPUARTCLK_SRC_SYSCLK ((uint32_t)0x00000008)
+#define RCC_LPUARTCLK_SRC_HSI ((uint32_t)0x00000010)
+#define RCC_LPUARTCLK_SRC_LSE ((uint32_t)0x00000018)
+
+#define IS_RCC_LPUART_CLK(LPUARTCLK) (((LPUARTCLK)&0xFFFFFFE7) == 0x00)
+
+/**
+ * @}
+ */
+
+/** @addtogroup SRAM_CTRLSTS
+ * @{
+ */
+
+#define SRAM1_PARITYERROR_INT ((uint32_t)0x00000001)
+#define SRAM2_PARITYERROR_INT ((uint32_t)0x00000008)
+#define IS_RCC_SRAMERRORINT(PARITYERROR_INT) (((PARITYERROR_INT) == SRAM1_PARITYERROR_INT) \
+ || ((PARITYERROR_INT) == SRAM2_PARITYERROR_INT))
+
+#define SRAM1_PARITYERROR_RESET ((uint32_t)0x00000002)
+#define SRAM2_PARITYERROR_RESET ((uint32_t)0x00000010)
+#define IS_RCC_SRAMERRORRESET(PARITYERROR_RESET) (((PARITYERROR_RESET) == SRAM1_PARITYERROR_RESET) \
+ || ((PARITYERROR_RESET) == SRAM2_PARITYERROR_RESET))
+
+#define SRAM1_PARITYERROR_FLAG ((uint32_t)0x00000004)
+#define SRAM2_PARITYERROR_FLAG ((uint32_t)0x00000020)
+#define IS_RCC_SRAMERRORFLAG(PARITYERROR_FLAG) (((PARITYERROR_FLAG) == SRAM1_PARITYERROR_FLAG) \
+ || ((PARITYERROR_FLAG) == SRAM2_PARITYERROR_FLAG))
+
+/**
+ * @}
+ */
+
+#define RCC_MCO_CLK_NUM0 ((uint32_t)0x00000000)
+#define RCC_MCO_CLK_NUM1 ((uint32_t)0x10000000)
+#define RCC_MCO_CLK_NUM2 ((uint32_t)0x20000000)
+#define RCC_MCO_CLK_NUM3 ((uint32_t)0x30000000)
+#define RCC_MCO_CLK_NUM4 ((uint32_t)0x40000000)
+#define RCC_MCO_CLK_NUM5 ((uint32_t)0x50000000)
+#define RCC_MCO_CLK_NUM6 ((uint32_t)0x60000000)
+#define RCC_MCO_CLK_NUM7 ((uint32_t)0x70000000)
+#define RCC_MCO_CLK_NUM8 ((uint32_t)0x80000000)
+#define RCC_MCO_CLK_NUM9 ((uint32_t)0x90000000)
+#define RCC_MCO_CLK_NUM10 ((uint32_t)0xA0000000)
+#define RCC_MCO_CLK_NUM11 ((uint32_t)0xB0000000)
+#define RCC_MCO_CLK_NUM12 ((uint32_t)0xC0000000)
+#define RCC_MCO_CLK_NUM13 ((uint32_t)0xD0000000)
+#define RCC_MCO_CLK_NUM14 ((uint32_t)0xE0000000)
+#define RCC_MCO_CLK_NUM15 ((uint32_t)0xF0000000)
+#define IS_RCC_MCOCLKPRE(NUM) \
+ (((NUM) == RCC_MCO_CLK_NUM0) || ((NUM) == RCC_MCO_CLK_NUM1) || ((NUM) == RCC_MCO_CLK_NUM2) \
+ || ((NUM) == RCC_MCO_CLK_NUM3) || ((NUM) == RCC_MCO_CLK_NUM4) || ((NUM) == RCC_MCO_CLK_NUM5) \
+ || ((NUM) == RCC_MCO_CLK_NUM6) || ((NUM) == RCC_MCO_CLK_NUM7) || ((NUM) == RCC_MCO_CLK_NUM8) \
+ || ((NUM) == RCC_MCO_CLK_NUM9) || ((NUM) == RCC_MCO_CLK_NUM10) || ((NUM) == RCC_MCO_CLK_NUM11) \
+ || ((NUM) == RCC_MCO_CLK_NUM12) || ((NUM) == RCC_MCO_CLK_NUM13) || ((NUM) == RCC_MCO_CLK_NUM14) \
+ || ((NUM) == RCC_MCO_CLK_NUM15))
+
+/** @addtogroup Clock_source_to_output_on_MCO_pin
+ * @{
+ */
+
+#define RCC_MCO_NOCLK ((uint8_t)0x00)
+#define RCC_MCO_LSI ((uint8_t)0x01)
+#define RCC_MCO_LSE ((uint8_t)0x02)
+#define RCC_MCO_MSI ((uint8_t)0x03)
+#define RCC_MCO_SYSCLK ((uint8_t)0x04)
+#define RCC_MCO_HSI ((uint8_t)0x05)
+#define RCC_MCO_HSE ((uint8_t)0x06)
+#define RCC_MCO_PLLCLK ((uint8_t)0x07)
+
+#define IS_RCC_MCO(MCO) \
+ (((MCO) == RCC_MCO_NOCLK) || ((MCO) == RCC_MCO_LSI) || ((MCO) == RCC_MCO_LSE) || ((MCO) == RCC_MCO_MSI) \
+ || ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSI) || ((MCO) == RCC_MCO_HSE) || ((MCO) == RCC_MCO_PLLCLK))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Flag
+ * @{
+ */
+#define RCC_CTRL_FLAG_HSIRDF ((uint8_t)0x21)
+#define RCC_CTRL_FLAG_HSERDF ((uint8_t)0x31)
+#define RCC_CTRL_FLAG_PLLRDF ((uint8_t)0x39)
+#define RCC_LDCTRL_FLAG_LSERD ((uint8_t)0x41)
+#define RCC_LDCTRL_FLAG_LSECLKSSF ((uint8_t)0x44)
+#define RCC_LDCTRL_FLAG_BORRSTF ((uint8_t)0x5C)
+#define RCC_LDCTRL_FLAG_LDEMCRSTF ((uint8_t)0x5E)
+#define RCC_CTRLSTS_FLAG_LSIRD ((uint8_t)0x61)
+#define RCC_CTRLSTS_FLAG_MSIRD ((uint8_t)0x63)
+#define RCC_CTRLSTS_FLAG_RAMRSTF ((uint8_t)0x77)
+#define RCC_CTRLSTS_FLAG_MMURSTF ((uint8_t)0x79)
+#define RCC_CTRLSTS_FLAG_PINRSTF ((uint8_t)0x7A)
+#define RCC_CTRLSTS_FLAG_PORRSTF ((uint8_t)0x7B)
+#define RCC_CTRLSTS_FLAG_SFTRSTF ((uint8_t)0x7C)
+#define RCC_CTRLSTS_FLAG_IWDGRSTF ((uint8_t)0x7D)
+#define RCC_CTRLSTS_FLAG_WWDGRSTF ((uint8_t)0x7E)
+#define RCC_CTRLSTS_FLAG_LPWRRSTF ((uint8_t)0x7F)
+
+#define IS_RCC_FLAG(FLAG) \
+ (((FLAG) == RCC_CTRL_FLAG_HSIRDF) || ((FLAG) == RCC_CTRL_FLAG_HSERDF) || ((FLAG) == RCC_CTRL_FLAG_PLLRDF) \
+ || ((FLAG) == RCC_LDCTRL_FLAG_LSERD) || ((FLAG) == RCC_LDCTRL_FLAG_LSECLKSSF) || ((FLAG) == RCC_LDCTRL_FLAG_BORRSTF) \
+ || ((FLAG) == RCC_LDCTRL_FLAG_LDEMCRSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_LSIRD) || ((FLAG) == RCC_CTRLSTS_FLAG_MSIRD) \
+ || ((FLAG) == RCC_CTRLSTS_FLAG_RAMRSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_MMURSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_PINRSTF) \
+ || ((FLAG) == RCC_CTRLSTS_FLAG_PORRSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_SFTRSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_IWDGRSTF) \
+ || ((FLAG) == RCC_CTRLSTS_FLAG_WWDGRSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_LPWRRSTF))
+
+#define IS_RCC_CALIB_VALUE(VALUE) ((VALUE) <= 0x1F)
+#define IS_RCC_MSICALIB_VALUE(VALUE) ((VALUE) <= 0xFF)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Exported_Functions
+ * @{
+ */
+
+void RCC_DeInit(void);
+void RCC_ConfigHse(uint32_t RCC_HSE);
+ErrorStatus RCC_WaitHseStable(void);
+void RCC_ConfigHsi(uint32_t RCC_HSI);
+ErrorStatus RCC_WaitHsiStable(void);
+void RCC_SetHsiCalibValue(uint8_t HSICalibrationValue);
+void RCC_EnableHsi(FunctionalState Cmd);
+void RCC_ConfigMsi(uint32_t RCC_MSI, uint32_t RCC_MSI_Range);
+ErrorStatus RCC_WaitMsiStable(void);
+void RCC_SetMsiCalibValue(uint8_t MSICalibrationValue);
+void RCC_EnableMsi(FunctionalState Cmd);
+void RCC_ConfigPll(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul, uint32_t RCC_PLLDIVCLK);
+void RCC_EnablePll(FunctionalState Cmd);
+
+void RCC_ConfigSysclk(uint32_t RCC_SYSCLKSource);
+uint8_t RCC_GetSysclkSrc(void);
+void RCC_ConfigHclk(uint32_t RCC_SYSCLK);
+void RCC_ConfigPclk1(uint32_t RCC_HCLK);
+void RCC_ConfigPclk2(uint32_t RCC_HCLK);
+void RCC_ConfigInt(uint8_t RccInt, FunctionalState Cmd);
+
+void RCC_ConfigUsbClk(uint32_t RCC_USBCLKSource);
+
+void RCC_ConfigTim18Clk(uint32_t RCC_TIM18CLKSource);
+void RCC_ConfigRngcClk(uint32_t RCC_RNGCCLKPrescaler);
+
+void RCC_ConfigAdc1mClk(uint32_t RCC_ADC1MCLKSource, uint32_t RCC_ADC1MPrescaler);
+void RCC_ConfigAdcPllClk(uint32_t RCC_ADCPLLCLKPrescaler, FunctionalState Cmd);
+void RCC_ConfigAdcHclk(uint32_t RCC_ADCHCLKPrescaler);
+
+void RCC_ConfigTrng1mClk(uint32_t RCC_TRNG1MCLKSource, uint32_t RCC_TRNG1MPrescaler);
+void RCC_EnableTrng1mClk(FunctionalState Cmd);
+
+void RCC_ConfigUCDRClk(uint32_t RCC_UCDR300MSource, FunctionalState Cmd);
+
+void RCC_ConfigUSBXTALESSMode(uint32_t RCC_USBXTALESSMode);
+
+void RCC_EnableRETPeriphClk(uint32_t RCC_RETPeriph, FunctionalState Cmd);
+void RCC_EnableRETPeriphReset(uint32_t RCC_RETPeriph, FunctionalState Cmd);
+
+void RCC_ConfigLSXClk(uint32_t RCC_LSXCLKSource);
+uint32_t RCC_GetLSXClkSrc(void);
+
+void RCC_ConfigLPTIMClk(uint32_t RCC_LPTIMCLKSource);
+uint32_t RCC_GetLPTIMClkSrc(void);
+void RCC_ConfigLPUARTClk(uint32_t RCC_LPUARTCLKSource);
+uint32_t RCC_GetLPUARTClkSrc(void);
+
+void RCC_ConfigSRAMParityErrorInt(uint32_t SramInt, FunctionalState Cmd);
+void RCC_ConfigSRAMParityErrorRESET(uint32_t SramReset, FunctionalState Cmd);
+void RCC_ClrSRAMParityErrorFlag(uint32_t SramErrorflag);
+
+void RCC_ConfigLse(uint8_t RCC_LSE,uint16_t LSE_Trim);
+void RCC_EnableLsi(FunctionalState Cmd);
+void RCC_ConfigRtcClk(uint32_t RCC_RTCCLKSource);
+void RCC_EnableRtcClk(FunctionalState Cmd);
+uint32_t RCC_GetRTCClkSrc(void);
+void RCC_GetClocksFreqValue(RCC_ClocksType* RCC_Clocks);
+void RCC_EnableAHBPeriphClk(uint32_t RCC_AHBPeriph, FunctionalState Cmd);
+void RCC_EnableAPB2PeriphClk(uint32_t RCC_APB2Periph, FunctionalState Cmd);
+void RCC_EnableAPB1PeriphClk(uint32_t RCC_APB1Periph, FunctionalState Cmd);
+
+void RCC_EnableAHBPeriphReset(uint32_t RCC_AHBPeriph, FunctionalState Cmd);
+void RCC_EnableAPB2PeriphReset(uint32_t RCC_APB2Periph, FunctionalState Cmd);
+void RCC_EnableAPB1PeriphReset(uint32_t RCC_APB1Periph, FunctionalState Cmd);
+void RCC_EnableLowPowerReset(FunctionalState Cmd);
+void RCC_EnableClockSecuritySystem(FunctionalState Cmd);
+void RCC_EnableLSEClockSecuritySystem(FunctionalState Cmd);
+FlagStatus RCC_GetLSEClockSecuritySystemStatus(void);
+void RCC_ConfigMcoClkPre(uint32_t RCC_MCOCLKPrescaler);
+void RCC_ConfigMco(uint8_t RCC_MCO);
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
+void RCC_ClrFlag(void);
+INTStatus RCC_GetIntStatus(uint8_t RccInt);
+void RCC_ClrIntPendingBit(uint32_t RccClrInt);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32L40X_RCC_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_rtc.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_rtc.h
new file mode 100644
index 0000000000..269611ca30
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_rtc.h
@@ -0,0 +1,789 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_rtc.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L40X_RTC_H__
+#define __N32L40X_RTC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l40x.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RTC
+ * @{
+ */
+
+/**
+ * @brief RTC Init structures definition
+ */
+typedef struct
+{
+ uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format.
+ This parameter can be a value of @ref RTC_Hour_Formats */
+
+ uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
+ This parameter must be set to a value lower than 0x7F */
+
+ uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
+ This parameter must be set to a value lower than 0x7FFF */
+} RTC_InitType;
+
+/**
+ * @brief RTC Time structure definition
+ */
+typedef struct
+{
+ uint8_t Hours; /*!< Specifies the RTC Time Hour.
+ This parameter must be set to a value in the 0-12 range
+ if the RTC_12HOUR_FORMAT is selected or 0-23 range if
+ the RTC_24HOUR_FORMAT is selected. */
+
+ uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
+ This parameter must be set to a value in the 0-59 range. */
+
+ uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
+ This parameter must be set to a value in the 0-59 range. */
+
+ uint8_t H12; /*!< Specifies the RTC AM/PM Time.
+ This parameter can be a value of @ref RTC_AM_PM_Definitions */
+} RTC_TimeType;
+
+/**
+ * @brief RTC Date structure definition
+ */
+typedef struct
+{
+ uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
+ This parameter can be a value of @ref RTC_WeekDay_Definitions */
+
+ uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
+ This parameter can be a value of @ref RTC_Month_Date_Definitions */
+
+ uint8_t Date; /*!< Specifies the RTC Date.
+ This parameter must be set to a value in the 1-31 range. */
+
+ uint8_t Year; /*!< Specifies the RTC Date Year.
+ This parameter must be set to a value in the 0-99 range. */
+} RTC_DateType;
+
+/**
+ * @brief RTC Alarm structure definition
+ */
+typedef struct
+{
+ RTC_TimeType AlarmTime; /*!< Specifies the RTC Alarm Time members. */
+
+ uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
+ This parameter can be a value of @ref RTC_AlarmMask_Definitions */
+
+ uint32_t DateWeekMode; /*!< Specifies the RTC Alarm is on Date or WeekDay.
+ This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
+
+ uint8_t DateWeekValue; /*!< Specifies the RTC Alarm Date/WeekDay.
+ If the Alarm Date is selected, this parameter
+ must be set to a value in the 1-31 range.
+ If the Alarm WeekDay is selected, this
+ parameter can be a value of @ref RTC_WeekDay_Definitions */
+} RTC_AlarmType;
+
+/** @addtogroup RTC_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup RTC_Hour_Formats
+ * @{
+ */
+#define RTC_24HOUR_FORMAT ((uint32_t)0x00000000)
+#define RTC_12HOUR_FORMAT ((uint32_t)0x00000040)
+#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_12HOUR_FORMAT) || ((FORMAT) == RTC_24HOUR_FORMAT))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Asynchronous_Predivider
+ * @{
+ */
+#define IS_RTC_PREDIV_ASYNCH(PREDIV) ((PREDIV) <= 0x7F)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Synchronous_Predivider
+ * @{
+ */
+#define IS_RTC_PREDIV_SYNCH(PREDIV) ((PREDIV) <= 0x7FFF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Time_Definitions
+ * @{
+ */
+#define IS_RTC_12HOUR(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))
+#define IS_RTC_24HOUR(HOUR) ((HOUR) <= 23)
+#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)
+#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_AM_PM_Definitions
+ * @{
+ */
+#define RTC_AM_H12 ((uint8_t)0x00)
+#define RTC_PM_H12 ((uint8_t)0x40)
+#define IS_RTC_H12(PM) (((PM) == RTC_AM_H12) || ((PM) == RTC_PM_H12))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Year_Date_Definitions
+ * @{
+ */
+#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Month_Date_Definitions
+ * @{
+ */
+
+/* Coded in BCD format */
+#define RTC_MONTH_JANUARY ((uint8_t)0x01)
+#define RTC_MONTH_FEBRURY ((uint8_t)0x02)
+#define RTC_MONTH_MARCH ((uint8_t)0x03)
+#define RTC_MONTH_APRIL ((uint8_t)0x04)
+#define RTC_MONTH_MAY ((uint8_t)0x05)
+#define RTC_MONTH_JUNE ((uint8_t)0x06)
+#define RTC_MONTH_JULY ((uint8_t)0x07)
+#define RTC_MONTH_AUGUST ((uint8_t)0x08)
+#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
+#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
+#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
+#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
+#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))
+#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_WeekDay_Definitions
+ * @{
+ */
+
+#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
+#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
+#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
+#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
+#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
+#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
+#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
+#define IS_RTC_WEEKDAY(WEEKDAY) \
+ (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) \
+ || ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) \
+ || ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Alarm_Definitions
+ * @{
+ */
+#define IS_RTC_ALARM_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
+#define IS_RTC_ALARM_WEEKDAY_WEEKDAY(WEEKDAY) \
+ (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) \
+ || ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) \
+ || ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_AlarmDateWeekDay_Definitions
+ * @{
+ */
+#define RTC_ALARM_SEL_WEEKDAY_DATE ((uint32_t)0x00000000)
+#define RTC_ALARM_SEL_WEEKDAY_WEEKDAY ((uint32_t)0x40000000)
+
+#define IS_RTC_ALARM_WEEKDAY_SEL(SEL) \
+ (((SEL) == RTC_ALARM_SEL_WEEKDAY_DATE) || ((SEL) == RTC_ALARM_SEL_WEEKDAY_WEEKDAY))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_AlarmMask_Definitions
+ * @{
+ */
+#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000)
+#define RTC_ALARMMASK_WEEKDAY ((uint32_t)0x80000000)
+#define RTC_ALARMMASK_HOURS ((uint32_t)0x00800000)
+#define RTC_ALARMMASK_MINUTES ((uint32_t)0x00008000)
+#define RTC_ALARMMASK_SECONDS ((uint32_t)0x00000080)
+#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080)
+#define IS_ALARM_MASK(INTEN) (((INTEN)&0x7F7F7F7F) == (uint32_t)RESET)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Alarms_Definitions
+ * @{
+ */
+#define RTC_A_ALARM ((uint32_t)0x00000100)
+#define RTC_B_ALARM ((uint32_t)0x00000200)
+#define IS_RTC_ALARM_SEL(ALARM) (((ALARM) == RTC_A_ALARM) || ((ALARM) == RTC_B_ALARM))
+#define IS_RTC_ALARM_ENABLE(ALARM) (((ALARM) & (RTC_A_ALARM | RTC_B_ALARM)) != (uint32_t)RESET)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Alarm_Sub_Seconds_Masks_Definitions
+ * @{
+ */
+#define RTC_SUBS_MASK_ALL \
+ ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. \
+ There is no comparison on sub seconds \
+ for Alarm */
+#define RTC_SUBS_MASK_SS14_1 \
+ ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm \
+ comparison. Only SS[0] is compared. */
+#define RTC_SUBS_MASK_SS14_2 \
+ ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm \
+ comparison. Only SS[1:0] are compared */
+#define RTC_SUBS_MASK_SS14_3 \
+ ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm \
+ comparison. Only SS[2:0] are compared */
+#define RTC_SUBS_MASK_SS14_4 \
+ ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm \
+ comparison. Only SS[3:0] are compared */
+#define RTC_SUBS_MASK_SS14_5 \
+ ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm \
+ comparison. Only SS[4:0] are compared */
+#define RTC_SUBS_MASK_SS14_6 \
+ ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm \
+ comparison. Only SS[5:0] are compared */
+#define RTC_SUBS_MASK_SS14_7 \
+ ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm \
+ comparison. Only SS[6:0] are compared */
+#define RTC_SUBS_MASK_SS14_8 \
+ ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm \
+ comparison. Only SS[7:0] are compared */
+#define RTC_SUBS_MASK_SS14_9 \
+ ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm \
+ comparison. Only SS[8:0] are compared */
+#define RTC_SUBS_MASK_SS14_10 \
+ ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm \
+ comparison. Only SS[9:0] are compared */
+#define RTC_SUBS_MASK_SS14_11 \
+ ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm \
+ comparison. Only SS[10:0] are compared */
+#define RTC_SUBS_MASK_SS14_12 \
+ ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm \
+ comparison.Only SS[11:0] are compared */
+#define RTC_SUBS_MASK_SS14_13 \
+ ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm \
+ comparison. Only SS[12:0] are compared */
+#define RTC_SUBS_MASK_SS14_14 \
+ ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm \
+ comparison.Only SS[13:0] are compared */
+#define RTC_SUBS_MASK_NONE \
+ ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match \
+ to activate alarm. */
+#define IS_RTC_ALARM_SUB_SECOND_MASK_MODE(INTEN) \
+ (((INTEN) == RTC_SUBS_MASK_ALL) || ((INTEN) == RTC_SUBS_MASK_SS14_1) || ((INTEN) == RTC_SUBS_MASK_SS14_2) \
+ || ((INTEN) == RTC_SUBS_MASK_SS14_3) || ((INTEN) == RTC_SUBS_MASK_SS14_4) || ((INTEN) == RTC_SUBS_MASK_SS14_5) \
+ || ((INTEN) == RTC_SUBS_MASK_SS14_6) || ((INTEN) == RTC_SUBS_MASK_SS14_7) || ((INTEN) == RTC_SUBS_MASK_SS14_8) \
+ || ((INTEN) == RTC_SUBS_MASK_SS14_9) || ((INTEN) == RTC_SUBS_MASK_SS14_10) || ((INTEN) == RTC_SUBS_MASK_SS14_11) \
+ || ((INTEN) == RTC_SUBS_MASK_SS14_12) || ((INTEN) == RTC_SUBS_MASK_SS14_13) || ((INTEN) == RTC_SUBS_MASK_SS14_14) \
+ || ((INTEN) == RTC_SUBS_MASK_NONE))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Alarm_Sub_Seconds_Value
+ * @{
+ */
+
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Wakeup_Timer_Definitions
+ * @{
+ */
+#define RTC_WKUPCLK_RTCCLK_DIV16 ((uint32_t)0x00000000)
+#define RTC_WKUPCLK_RTCCLK_DIV8 ((uint32_t)0x00000001)
+#define RTC_WKUPCLK_RTCCLK_DIV4 ((uint32_t)0x00000002)
+#define RTC_WKUPCLK_RTCCLK_DIV2 ((uint32_t)0x00000003)
+#define RTC_WKUPCLK_CK_SPRE_16BITS ((uint32_t)0x00000004)
+#define RTC_WKUPCLK_CK_SPRE_17BITS ((uint32_t)0x00000006)
+#define IS_RTC_WKUP_CLOCK(CLOCK) \
+ (((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV16) || ((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV8) \
+ || ((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV4) || ((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV2) \
+ || ((CLOCK) == RTC_WKUPCLK_CK_SPRE_16BITS) || ((CLOCK) == RTC_WKUPCLK_CK_SPRE_17BITS))
+#define IS_RTC_WKUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Time_Stamp_Edges_definitions
+ * @{
+ */
+#define RTC_TIMESTAMP_EDGE_RISING ((uint32_t)0x00000000)
+#define RTC_TIMESTAMP_EDGE_FALLING ((uint32_t)0x00000008)
+#define IS_RTC_TIMESTAMP_EDGE_MODE(EDGE) \
+ (((EDGE) == RTC_TIMESTAMP_EDGE_RISING) || ((EDGE) == RTC_TIMESTAMP_EDGE_FALLING))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Output_selection_Definitions
+ * @{
+ */
+#define RTC_OUTPUT_DIS ((uint32_t)0x00000000)
+#define RTC_OUTPUT_ALA ((uint32_t)0x00200000)
+#define RTC_OUTPUT_ALB ((uint32_t)0x00400000)
+#define RTC_OUTPUT_WKUP ((uint32_t)0x00600000)
+
+#define IS_RTC_OUTPUT_MODE(OUTPUT) \
+ (((OUTPUT) == RTC_OUTPUT_DIS) || ((OUTPUT) == RTC_OUTPUT_ALA) || ((OUTPUT) == RTC_OUTPUT_ALB) \
+ || ((OUTPUT) == RTC_OUTPUT_WKUP))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Output_Polarity_Definitions
+ * @{
+ */
+#define RTC_OUTPOL_HIGH ((uint32_t)0x00000000)
+#define RTC_OUTPOL_LOW ((uint32_t)0x00100000)
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPOL_HIGH) || ((POL) == RTC_OUTPOL_LOW))
+/**
+ * @}
+ */
+
+
+/** @addtogroup RTC_Calib_Output_selection_Definitions
+ * @{
+ */
+#define RTC_CALIB_OUTPUT_256HZ ((uint32_t)0x00000000)
+#define RTC_CALIB_OUTPUT_1HZ ((uint32_t)0x00080000)
+#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIB_OUTPUT_256HZ) || ((OUTPUT) == RTC_CALIB_OUTPUT_1HZ))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Smooth_calib_period_Definitions
+ * @{
+ */
+#define SMOOTH_CALIB_32SEC \
+ ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \
+ period is 32s, else 2exp20 RTCCLK seconds */
+#define SMOOTH_CALIB_16SEC \
+ ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \
+ period is 16s, else 2exp19 RTCCLK seconds */
+#define SMOOTH_CALIB_8SEC \
+ ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \
+ period is 8s, else 2exp18 RTCCLK seconds */
+#define IS_RTC_SMOOTH_CALIB_PERIOD_SEL(PERIOD) \
+ (((PERIOD) == SMOOTH_CALIB_32SEC) || ((PERIOD) == SMOOTH_CALIB_16SEC) || ((PERIOD) == SMOOTH_CALIB_8SEC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Smooth_calib_Plus_pulses_Definitions
+ * @{
+ */
+#define RTC_SMOOTH_CALIB_PLUS_PULSES_SET \
+ ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added \
+ during a X -second window = Y - CALM[8:0]. \
+ with Y = 512, 256, 128 when X = 32, 16, 8 */
+#define RTC_SMOOTH_CALIB_PLUS_PULSES__RESET \
+ ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited \
+ during a 32-second window = CALM[8:0]. */
+#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) \
+ (((PLUS) == RTC_SMOOTH_CALIB_PLUS_PULSES_SET) || ((PLUS) == RTC_SMOOTH_CALIB_PLUS_PULSES__RESET))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Smooth_calib_Minus_pulses_Definitions
+ * @{
+ */
+#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_DayLightSaving_Definitions
+ * @{
+ */
+#define RTC_DAYLIGHT_SAVING_SUB1H ((uint32_t)0x00020000)
+#define RTC_DAYLIGHT_SAVING_ADD1H ((uint32_t)0x00010000)
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHT_SAVING_SUB1H) || ((SAVE) == RTC_DAYLIGHT_SAVING_ADD1H))
+
+#define RTC_STORE_OPERATION_RESET ((uint32_t)0x00000000)
+#define RTC_STORE_OPERATION_SET ((uint32_t)0x00040000)
+#define IS_RTC_STORE_OPERATION(OPERATION) \
+ (((OPERATION) == RTC_STORE_OPERATION_RESET) || ((OPERATION) == RTC_STORE_OPERATION_SET))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Output_Type_ALARM_OUT
+ * @{
+ */
+#define RTC_OUTPUT_OPENDRAIN ((uint32_t)0x00000000)
+#define RTC_OUTPUT_PUSHPULL ((uint32_t)0x00000001)
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_OPENDRAIN) || ((TYPE) == RTC_OUTPUT_PUSHPULL))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Add_1_Second_Parameter_Definitions
+ * @{
+ */
+#define RTC_SHIFT_ADD1S_DISABLE ((uint32_t)0x00000000)
+#define RTC_SHIFT_ADD1S_ENABLE ((uint32_t)0x80000000)
+#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFT_ADD1S_DISABLE) || ((SEL) == RTC_SHIFT_ADD1S_ENABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Substract_Fraction_Of_Second_Value
+ * @{
+ */
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Input_parameter_format_definitions
+ * @{
+ */
+#define RTC_FORMAT_BIN ((uint32_t)0x000000000)
+#define RTC_FORMAT_BCD ((uint32_t)0x000000001)
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Flags_Definitions
+ * @{
+ */
+#define RTC_FLAG_RECPF ((uint32_t)0x00010000)
+#define RTC_FLAG_TAMP3F ((uint32_t)0x00008000)
+#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000)
+#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)
+#define RTC_FLAG_TISOVF ((uint32_t)0x00001000)
+#define RTC_FLAG_TISF ((uint32_t)0x00000800)
+#define RTC_FLAG_WTF ((uint32_t)0x00000400)
+#define RTC_FLAG_ALBF ((uint32_t)0x00000200)
+#define RTC_FLAG_ALAF ((uint32_t)0x00000100)
+#define RTC_FLAG_INITF ((uint32_t)0x00000040)
+#define RTC_FLAG_RSYF ((uint32_t)0x00000020)
+#define RTC_FLAG_INITSF ((uint32_t)0x00000010)
+#define RTC_FLAG_SHOPF ((uint32_t)0x00000008)
+#define RTC_FLAG_WTWF ((uint32_t)0x00000004)
+#define RTC_FLAG_ALBWF ((uint32_t)0x00000002)
+#define RTC_FLAG_ALAWF ((uint32_t)0x00000001)
+#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RECPF) || ((FLAG) == RTC_FLAG_TAMP3F) || \
+ ((FLAG) == RTC_FLAG_TAMP2F) || ((FLAG) == RTC_FLAG_TAMP1F) || \
+ ((FLAG) == RTC_FLAG_TISOVF) || ((FLAG) == RTC_FLAG_TISF) || \
+ ((FLAG) == RTC_FLAG_WTF) || ((FLAG) == RTC_FLAG_ALBF) || \
+ ((FLAG) == RTC_FLAG_ALAF) || ((FLAG) == RTC_FLAG_INITF) || \
+ ((FLAG) == RTC_FLAG_RSYF) || ((FLAG) == RTC_FLAG_INITSF) || \
+ ((FLAG) == RTC_FLAG_SHOPF) || ((FLAG) == RTC_FLAG_WTWF) || \
+ ((FLAG) == RTC_FLAG_ALBWF)|| ((FLAG) == RTC_FLAG_ALAWF))
+#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Interrupts_Definitions
+ * @{
+ */
+#define RTC_INT_TAMP3 ((uint32_t)0x00080000)
+#define RTC_INT_TAMP2 ((uint32_t)0x00040000)
+#define RTC_INT_TAMP1 ((uint32_t)0x00020000)
+#define RTC_INT_TS ((uint32_t)0x00008000)
+#define RTC_INT_WUT ((uint32_t)0x00004000)
+#define RTC_INT_ALRB ((uint32_t)0x00002000)
+#define RTC_INT_ALRA ((uint32_t)0x00001000)
+
+#define IS_RTC_CONFIG_INT(IT) (((IT) != (uint32_t)RESET) && (((IT)&0xFFFF0FFB) == (uint32_t)RESET))
+#define IS_RTC_GET_INT(IT) \
+ (((IT) == RTC_INT_TAMP3) ||((IT) == RTC_INT_TAMP2) ||((IT) == RTC_INT_TAMP1) ||((IT) == RTC_INT_TS) || ((IT) == RTC_INT_WUT) || ((IT) == RTC_INT_ALRB) || ((IT) == RTC_INT_ALRA))
+#define IS_RTC_CLEAR_INT(IT) (((IT) != (uint32_t)RESET) && (((IT)&0xFFF10FFF) == (uint32_t)RESET))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Legacy
+ * @{
+ */
+#define RTC_DigitalCalibConfig RTC_CoarseCalibConfig
+#define RTC_DigitalCalibCmd RTC_CoarseCalibCmd
+/** @defgroup RTC_Tamper_Trigger_Definitions
+ * @{
+ */
+#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000)
+#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000002)
+#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000)
+#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000002)
+#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
+ ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
+ ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
+ ((TRIGGER) == RTC_TamperTrigger_HighLevel))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Tamper_Filter_Definitions
+ * @{
+ */
+#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
+
+#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2
+ consecutive samples at the active level */
+#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4
+ consecutive samples at the active level */
+#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8
+ consecutive samples at the active leve. */
+
+#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \
+ ((FILTER) == RTC_TamperFilter_2Sample) || \
+ ((FILTER) == RTC_TamperFilter_4Sample) || \
+ ((FILTER) == RTC_TamperFilter_8Sample))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions
+ * @{
+ */
+#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 32768 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 16384 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 8192 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 4096 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 2048 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 1024 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 512 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 256 */
+#define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700) /* Clear TAMPFREQ[2:0] bits in the RTC_TAMPCR register */
+
+#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
+
+/**
+ * @}
+ */
+
+ /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions
+ * @{
+ */
+#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before
+ sampling during 1 RTCCLK cycle */
+#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before
+ sampling during 2 RTCCLK cycles */
+#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before
+ sampling during 4 RTCCLK cycles */
+#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before
+ sampling during 8 RTCCLK cycles */
+#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
+ ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
+ ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
+ ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Tamper_Pins_Definitions
+ * @{
+ */
+#define RTC_TAMPER_1 RTC_TMPCFG_TP1EN /*!< Tamper detection enable for
+ input tamper 1 */
+#define RTC_TAMPER_2 RTC_TMPCFG_TP2EN /*!< Tamper detection enable for
+ input tamper 2 */
+#define RTC_TAMPER_3 RTC_TMPCFG_TP3EN /*!< Tamper detection enable for
+ input tamper 3 */
+#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
+
+
+#define RTC_TAMPER1_INT RTC_TMPCFG_TP1INTEN /*!< Tamper detection interruput enable */
+#define RTC_TAMPER2_INT RTC_TMPCFG_TP2INTEN /*!< Tamper detection interruput enable */
+#define RTC_TAMPER3_INT RTC_TMPCFG_TP3INTEN /*!< Tamper detection interruput enable */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Function used to set the RTC configuration to the default reset state *****/
+ErrorStatus RTC_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+ErrorStatus RTC_Init(RTC_InitType* RTC_InitStruct);
+void RTC_StructInit(RTC_InitType* RTC_InitStruct);
+void RTC_EnableWriteProtection(FunctionalState Cmd);
+ErrorStatus RTC_EnterInitMode(void);
+void RTC_ExitInitMode(void);
+ErrorStatus RTC_WaitForSynchro(void);
+ErrorStatus RTC_EnableRefClock(FunctionalState Cmd);
+void RTC_EnableBypassShadow(FunctionalState Cmd);
+
+/* Time and Date configuration functions **************************************/
+ErrorStatus RTC_ConfigTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct);
+void RTC_TimeStructInit(RTC_TimeType* RTC_TimeStruct);
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct);
+uint32_t RTC_GetSubSecond(void);
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct);
+void RTC_DateStructInit(RTC_DateType* RTC_DateStruct);
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct);
+
+/* Alarms (Alarm A and Alarm B) configuration functions **********************/
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct);
+void RTC_AlarmStructInit(RTC_AlarmType* RTC_AlarmStruct);
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct);
+ErrorStatus RTC_EnableAlarm(uint32_t RTC_Alarm, FunctionalState Cmd);
+void RTC_ConfigAlarmSubSecond(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask);
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
+
+/* WakeUp Timer configuration functions ***************************************/
+void RTC_ConfigWakeUpClock(uint32_t RTC_WakeUpClock);
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);
+uint32_t RTC_GetWakeUpCounter(void);
+ErrorStatus RTC_EnableWakeUp(FunctionalState Cmd);
+
+/* Daylight Saving configuration functions ************************************/
+void RTC_ConfigDayLightSaving(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
+uint32_t RTC_GetStoreOperation(void);
+
+/* Output pin Configuration function ******************************************/
+void RTC_ConfigOutput(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
+
+/* Coarse and Smooth Calibration configuration functions **********************/
+void RTC_EnableCalibOutput(FunctionalState Cmd);
+void RTC_ConfigCalibOutput(uint32_t RTC_CalibOutput);
+ErrorStatus RTC_ConfigSmoothCalib(uint32_t RTC_SmoothCalibPeriod,
+ uint32_t RTC_SmoothCalibPlusPulses,
+ uint32_t RTC_SmouthCalibMinusPulsesValue);
+
+/* TimeStamp configuration functions ******************************************/
+void RTC_EnableTimeStamp(uint32_t RTC_TimeStampEdge, FunctionalState Cmd);
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeType* RTC_StampTimeStruct, RTC_DateType* RTC_StampDateStruct);
+uint32_t RTC_GetTimeStampSubSecond(void);
+
+/* Output Type Config configuration functions *********************************/
+void RTC_ConfigOutputType(uint32_t RTC_OutputType);
+
+/* RTC_Shift_control_synchonisation_functions *********************************/
+ErrorStatus RTC_ConfigSynchroShift(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);
+
+/* Interrupts and flags management functions **********************************/
+void RTC_ConfigInt(uint32_t RTC_INT, FunctionalState Cmd);
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
+void RTC_ClrFlag(uint32_t RTC_FLAG);
+INTStatus RTC_GetITStatus(uint32_t RTC_INT);
+void RTC_ClrIntPendingBit(uint32_t RTC_INT);
+
+/* WakeUp TSC function **********************************/
+void RTC_EnableWakeUpTsc(uint32_t count);
+
+/* Tampers configuration functions ********************************************/
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);
+void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);
+void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);
+void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);
+void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
+void RTC_TamperPullUpCmd(FunctionalState NewState);
+void RTC_TamperIECmd(uint32_t TAMPxIE, FunctionalState NewState);
+void RTC_TamperTAMPTSCmd(FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32L40X_RTC_H__ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_spi.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_spi.h
new file mode 100644
index 0000000000..3e373d5c2c
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_spi.h
@@ -0,0 +1,470 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_spi.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L40X_SPI_H__
+#define __N32L40X_SPI_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l40x.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @{
+ */
+
+/** @addtogroup SPI_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief SPI Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t DataDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
+ This parameter can be a value of @ref SPI_data_direction */
+
+ uint16_t SpiMode; /*!< Specifies the SPI operating mode.
+ This parameter can be a value of @ref SPI_mode */
+
+ uint16_t DataLen; /*!< Specifies the SPI data size.
+ This parameter can be a value of @ref SPI_data_size */
+
+ uint16_t CLKPOL; /*!< Specifies the serial clock steady state.
+ This parameter can be a value of @ref SPI_Clock_Polarity */
+
+ uint16_t CLKPHA; /*!< Specifies the clock active edge for the bit capture.
+ This parameter can be a value of @ref SPI_Clock_Phase */
+
+ uint16_t NSS; /*!< Specifies whether the NSS signal is managed by
+ hardware (NSS pin) or by software using the SSI bit.
+ This parameter can be a value of @ref SPI_Slave_Select_management */
+
+ uint16_t BaudRatePres; /*!< Specifies the Baud Rate prescaler value which will be
+ used to configure the transmit and receive SCK clock.
+ This parameter can be a value of @ref SPI_BaudRate_Prescaler.
+ @note The communication clock is derived from the master
+ clock. The slave clock does not need to be set. */
+
+ uint16_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+ uint16_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. */
+} SPI_InitType;
+
+/**
+ * @brief I2S Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t I2sMode; /*!< Specifies the I2S operating mode.
+ This parameter can be a value of @ref I2sMode */
+
+ uint16_t Standard; /*!< Specifies the standard used for the I2S communication.
+ This parameter can be a value of @ref Standard */
+
+ uint16_t DataFormat; /*!< Specifies the data format for the I2S communication.
+ This parameter can be a value of @ref I2S_Data_Format */
+
+ uint16_t MCLKEnable; /*!< Specifies whether the I2S MCLK output is enabled or not.
+ This parameter can be a value of @ref I2S_MCLK_Output */
+
+ uint32_t AudioFrequency; /*!< Specifies the frequency selected for the I2S communication.
+ This parameter can be a value of @ref I2S_Audio_Frequency */
+
+ uint16_t CLKPOL; /*!< Specifies the idle state of the I2S clock.
+ This parameter can be a value of @ref I2S_Clock_Polarity */
+} I2S_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Exported_Constants
+ * @{
+ */
+
+#define IS_SPI_PERIPH(PERIPH) (((PERIPH) == SPI1) || ((PERIPH) == SPI2))
+
+
+/** @addtogroup SPI_data_direction
+ * @{
+ */
+
+#define SPI_DIR_DOUBLELINE_FULLDUPLEX ((uint16_t)0x0000)
+#define SPI_DIR_DOUBLELINE_RONLY ((uint16_t)0x0400)
+#define SPI_DIR_SINGLELINE_RX ((uint16_t)0x8000)
+#define SPI_DIR_SINGLELINE_TX ((uint16_t)0xC000)
+#define IS_SPI_DIR_MODE(MODE) \
+ (((MODE) == SPI_DIR_DOUBLELINE_FULLDUPLEX) || ((MODE) == SPI_DIR_DOUBLELINE_RONLY) \
+ || ((MODE) == SPI_DIR_SINGLELINE_RX) || ((MODE) == SPI_DIR_SINGLELINE_TX))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_mode
+ * @{
+ */
+
+#define SPI_MODE_MASTER ((uint16_t)0x0104)
+#define SPI_MODE_SLAVE ((uint16_t)0x0000)
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_MASTER) || ((MODE) == SPI_MODE_SLAVE))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_data_size
+ * @{
+ */
+
+#define SPI_DATA_SIZE_16BITS ((uint16_t)0x0800)
+#define SPI_DATA_SIZE_8BITS ((uint16_t)0x0000)
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATA_SIZE_16BITS) || ((DATASIZE) == SPI_DATA_SIZE_8BITS))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Clock_Polarity
+ * @{
+ */
+
+#define SPI_CLKPOL_LOW ((uint16_t)0x0000)
+#define SPI_CLKPOL_HIGH ((uint16_t)0x0002)
+#define IS_SPI_CLKPOL(CPOL) (((CPOL) == SPI_CLKPOL_LOW) || ((CPOL) == SPI_CLKPOL_HIGH))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Clock_Phase
+ * @{
+ */
+
+#define SPI_CLKPHA_FIRST_EDGE ((uint16_t)0x0000)
+#define SPI_CLKPHA_SECOND_EDGE ((uint16_t)0x0001)
+#define IS_SPI_CLKPHA(CPHA) (((CPHA) == SPI_CLKPHA_FIRST_EDGE) || ((CPHA) == SPI_CLKPHA_SECOND_EDGE))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Slave_Select_management
+ * @{
+ */
+
+#define SPI_NSS_SOFT ((uint16_t)0x0200)
+#define SPI_NSS_HARD ((uint16_t)0x0000)
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || ((NSS) == SPI_NSS_HARD))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_BaudRate_Prescaler
+ * @{
+ */
+
+#define SPI_BR_PRESCALER_2 ((uint16_t)0x0000)
+#define SPI_BR_PRESCALER_4 ((uint16_t)0x0008)
+#define SPI_BR_PRESCALER_8 ((uint16_t)0x0010)
+#define SPI_BR_PRESCALER_16 ((uint16_t)0x0018)
+#define SPI_BR_PRESCALER_32 ((uint16_t)0x0020)
+#define SPI_BR_PRESCALER_64 ((uint16_t)0x0028)
+#define SPI_BR_PRESCALER_128 ((uint16_t)0x0030)
+#define SPI_BR_PRESCALER_256 ((uint16_t)0x0038)
+#define IS_SPI_BR_PRESCALER(PRESCALER) \
+ (((PRESCALER) == SPI_BR_PRESCALER_2) || ((PRESCALER) == SPI_BR_PRESCALER_4) || ((PRESCALER) == SPI_BR_PRESCALER_8) \
+ || ((PRESCALER) == SPI_BR_PRESCALER_16) || ((PRESCALER) == SPI_BR_PRESCALER_32) \
+ || ((PRESCALER) == SPI_BR_PRESCALER_64) || ((PRESCALER) == SPI_BR_PRESCALER_128) \
+ || ((PRESCALER) == SPI_BR_PRESCALER_256))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_MSB_LSB_transmission
+ * @{
+ */
+
+#define SPI_FB_MSB ((uint16_t)0x0000)
+#define SPI_FB_LSB ((uint16_t)0x0080)
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FB_MSB) || ((BIT) == SPI_FB_LSB))
+/**
+ * @}
+ */
+
+/** @addtogroup I2sMode
+ * @{
+ */
+
+#define I2S_MODE_SlAVE_TX ((uint16_t)0x0000)
+#define I2S_MODE_SlAVE_RX ((uint16_t)0x0100)
+#define I2S_MODE_MASTER_TX ((uint16_t)0x0200)
+#define I2S_MODE_MASTER_RX ((uint16_t)0x0300)
+#define IS_I2S_MODE(MODE) \
+ (((MODE) == I2S_MODE_SlAVE_TX) || ((MODE) == I2S_MODE_SlAVE_RX) || ((MODE) == I2S_MODE_MASTER_TX) \
+ || ((MODE) == I2S_MODE_MASTER_RX))
+/**
+ * @}
+ */
+
+/** @addtogroup Standard
+ * @{
+ */
+
+#define I2S_STD_PHILLIPS ((uint16_t)0x0000)
+#define I2S_STD_MSB_ALIGN ((uint16_t)0x0010)
+#define I2S_STD_LSB_ALIGN ((uint16_t)0x0020)
+#define I2S_STD_PCM_SHORTFRAME ((uint16_t)0x0030)
+#define I2S_STD_PCM_LONGFRAME ((uint16_t)0x00B0)
+#define IS_I2S_STANDARD(STANDARD) \
+ (((STANDARD) == I2S_STD_PHILLIPS) || ((STANDARD) == I2S_STD_MSB_ALIGN) || ((STANDARD) == I2S_STD_LSB_ALIGN) \
+ || ((STANDARD) == I2S_STD_PCM_SHORTFRAME) || ((STANDARD) == I2S_STD_PCM_LONGFRAME))
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Data_Format
+ * @{
+ */
+
+#define I2S_DATA_FMT_16BITS ((uint16_t)0x0000)
+#define I2S_DATA_FMT_16BITS_EXTENDED ((uint16_t)0x0001)
+#define I2S_DATA_FMT_24BITS ((uint16_t)0x0003)
+#define I2S_DATA_FMT_32BITS ((uint16_t)0x0005)
+#define IS_I2S_DATA_FMT(FORMAT) \
+ (((FORMAT) == I2S_DATA_FMT_16BITS) || ((FORMAT) == I2S_DATA_FMT_16BITS_EXTENDED) \
+ || ((FORMAT) == I2S_DATA_FMT_24BITS) || ((FORMAT) == I2S_DATA_FMT_32BITS))
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_MCLK_Output
+ * @{
+ */
+
+#define I2S_MCLK_ENABLE ((uint16_t)0x0200)
+#define I2S_MCLK_DISABLE ((uint16_t)0x0000)
+#define IS_I2S_MCLK_ENABLE(OUTPUT) (((OUTPUT) == I2S_MCLK_ENABLE) || ((OUTPUT) == I2S_MCLK_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Audio_Frequency
+ * @{
+ */
+
+#define I2S_AUDIO_FREQ_192K ((uint32_t)192000)
+#define I2S_AUDIO_FREQ_96K ((uint32_t)96000)
+#define I2S_AUDIO_FREQ_48K ((uint32_t)48000)
+#define I2S_AUDIO_FREQ_44K ((uint32_t)44100)
+#define I2S_AUDIO_FREQ_32K ((uint32_t)32000)
+#define I2S_AUDIO_FREQ_22K ((uint32_t)22050)
+#define I2S_AUDIO_FREQ_16K ((uint32_t)16000)
+#define I2S_AUDIO_FREQ_11K ((uint32_t)11025)
+#define I2S_AUDIO_FREQ_8K ((uint32_t)8000)
+#define I2S_AUDIO_FREQ_DEFAULT ((uint32_t)2)
+
+#define IS_I2S_AUDIO_FREQ(FREQ) \
+ ((((FREQ) >= I2S_AUDIO_FREQ_8K) && ((FREQ) <= I2S_AUDIO_FREQ_192K)) || ((FREQ) == I2S_AUDIO_FREQ_DEFAULT))
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Clock_Polarity
+ * @{
+ */
+
+#define I2S_CLKPOL_LOW ((uint16_t)0x0000)
+#define I2S_CLKPOL_HIGH ((uint16_t)0x0008)
+#define IS_I2S_CLKPOL(CPOL) (((CPOL) == I2S_CLKPOL_LOW) || ((CPOL) == I2S_CLKPOL_HIGH))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_I2S_DMA_transfer_requests
+ * @{
+ */
+
+#define SPI_I2S_DMA_TX ((uint16_t)0x0002)
+#define SPI_I2S_DMA_RX ((uint16_t)0x0001)
+#define IS_SPI_I2S_DMA(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_NSS_internal_software_management
+ * @{
+ */
+
+#define SPI_NSS_HIGH ((uint16_t)0x0100)
+#define SPI_NSS_LOW ((uint16_t)0xFEFF)
+#define IS_SPI_NSS_LEVEL(INTERNAL) (((INTERNAL) == SPI_NSS_HIGH) || ((INTERNAL) == SPI_NSS_LOW))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_CRC_Transmit_Receive
+ * @{
+ */
+
+#define SPI_CRC_TX ((uint8_t)0x00)
+#define SPI_CRC_RX ((uint8_t)0x01)
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_TX) || ((CRC) == SPI_CRC_RX))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_direction_transmit_receive
+ * @{
+ */
+
+#define SPI_BIDIRECTION_RX ((uint16_t)0xBFFF)
+#define SPI_BIDIRECTION_TX ((uint16_t)0x4000)
+#define IS_SPI_BIDIRECTION(DIRECTION) (((DIRECTION) == SPI_BIDIRECTION_RX) || ((DIRECTION) == SPI_BIDIRECTION_TX))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_I2S_interrupts_definition
+ * @{
+ */
+
+#define SPI_I2S_INT_TE ((uint8_t)0x71)
+#define SPI_I2S_INT_RNE ((uint8_t)0x60)
+#define SPI_I2S_INT_ERR ((uint8_t)0x50)
+#define IS_SPI_I2S_CONFIG_INT(IT) (((IT) == SPI_I2S_INT_TE) || ((IT) == SPI_I2S_INT_RNE) || ((IT) == SPI_I2S_INT_ERR))
+#define SPI_I2S_INT_OVER ((uint8_t)0x56)
+#define SPI_INT_MODERR ((uint8_t)0x55)
+#define SPI_INT_CRCERR ((uint8_t)0x54)
+#define I2S_INT_UNDER ((uint8_t)0x53)
+#define IS_SPI_I2S_CLR_INT(IT) (((IT) == SPI_INT_CRCERR))
+#define IS_SPI_I2S_GET_INT(IT) \
+ (((IT) == SPI_I2S_INT_RNE) || ((IT) == SPI_I2S_INT_TE) || ((IT) == I2S_INT_UNDER) || ((IT) == SPI_INT_CRCERR) \
+ || ((IT) == SPI_INT_MODERR) || ((IT) == SPI_I2S_INT_OVER))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_I2S_flags_definition
+ * @{
+ */
+
+#define SPI_I2S_RNE_FLAG ((uint16_t)0x0001)
+#define SPI_I2S_TE_FLAG ((uint16_t)0x0002)
+#define I2S_CHSIDE_FLAG ((uint16_t)0x0004)
+#define I2S_UNDER_FLAG ((uint16_t)0x0008)
+#define SPI_CRCERR_FLAG ((uint16_t)0x0010)
+#define SPI_MODERR_FLAG ((uint16_t)0x0020)
+#define SPI_I2S_OVER_FLAG ((uint16_t)0x0040)
+#define SPI_I2S_BUSY_FLAG ((uint16_t)0x0080)
+#define IS_SPI_I2S_CLR_FLAG(FLAG) (((FLAG) == SPI_CRCERR_FLAG))
+#define IS_SPI_I2S_GET_FLAG(FLAG) \
+ (((FLAG) == SPI_I2S_BUSY_FLAG) || ((FLAG) == SPI_I2S_OVER_FLAG) || ((FLAG) == SPI_MODERR_FLAG) \
+ || ((FLAG) == SPI_CRCERR_FLAG) || ((FLAG) == I2S_UNDER_FLAG) || ((FLAG) == I2S_CHSIDE_FLAG) \
+ || ((FLAG) == SPI_I2S_TE_FLAG) || ((FLAG) == SPI_I2S_RNE_FLAG))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_CRC_polynomial
+ * @{
+ */
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Exported_Functions
+ * @{
+ */
+
+void SPI_I2S_DeInit(SPI_Module* SPIx);
+void SPI_Init(SPI_Module* SPIx, SPI_InitType* SPI_InitStruct);
+void I2S_Init(SPI_Module* SPIx, I2S_InitType* I2S_InitStruct);
+void SPI_InitStruct(SPI_InitType* SPI_InitStruct);
+void I2S_InitStruct(I2S_InitType* I2S_InitStruct);
+void SPI_Enable(SPI_Module* SPIx, FunctionalState Cmd);
+void I2S_Enable(SPI_Module* SPIx, FunctionalState Cmd);
+void SPI_I2S_EnableInt(SPI_Module* SPIx, uint8_t SPI_I2S_IT, FunctionalState Cmd);
+void SPI_I2S_EnableDma(SPI_Module* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState Cmd);
+void SPI_I2S_TransmitData(SPI_Module* SPIx, uint16_t Data);
+uint16_t SPI_I2S_ReceiveData(SPI_Module* SPIx);
+void SPI_SetNssLevel(SPI_Module* SPIx, uint16_t SPI_NSSInternalSoft);
+void SPI_SSOutputEnable(SPI_Module* SPIx, FunctionalState Cmd);
+void SPI_ConfigDataLen(SPI_Module* SPIx, uint16_t DataLen);
+void SPI_TransmitCrcNext(SPI_Module* SPIx);
+void SPI_EnableCalculateCrc(SPI_Module* SPIx, FunctionalState Cmd);
+uint16_t SPI_GetCRCDat(SPI_Module* SPIx, uint8_t SPI_CRC);
+uint16_t SPI_GetCRCPoly(SPI_Module* SPIx);
+void SPI_ConfigBidirectionalMode(SPI_Module* SPIx, uint16_t DataDirection);
+FlagStatus SPI_I2S_GetStatus(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG);
+void SPI_I2S_ClrCRCErrFlag(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG);
+INTStatus SPI_I2S_GetIntStatus(SPI_Module* SPIx, uint8_t SPI_I2S_IT);
+void SPI_I2S_ClrITPendingBit(SPI_Module* SPIx, uint8_t SPI_I2S_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32L40X_SPI_H__ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_tim.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_tim.h
new file mode 100644
index 0000000000..d612ca7061
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_tim.h
@@ -0,0 +1,1101 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_tim.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L40X_TIM_H__
+#define __N32L40X_TIM_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l40x.h"
+#include "stdbool.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup TIM
+ * @{
+ */
+
+/** @addtogroup TIM_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief TIM Time Base Init structure definition
+ * @note This structure is used with all TIMx except for TIM6 and TIM7.
+ */
+
+typedef struct
+{
+ uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
+ This parameter can be a number between 0x0000 and 0xFFFF */
+
+ uint16_t CntMode; /*!< Specifies the counter mode.
+ This parameter can be a value of @ref TIM_Counter_Mode */
+
+ uint16_t Period; /*!< Specifies the period value to be loaded into the active
+ Auto-Reload Register at the next update event.
+ This parameter must be a number between 0x0000 and 0xFFFF. */
+
+ uint16_t ClkDiv; /*!< Specifies the clock division.
+ This parameter can be a value of @ref TIM_Clock_Division_CKD */
+
+ uint8_t RepetCnt; /*!< Specifies the repetition counter value. Each time the REPCNT downcounter
+ reaches zero, an update event is generated and counting restarts
+ from the REPCNT value (N).
+ This means in PWM mode that (N+1) corresponds to:
+ - the number of PWM periods in edge-aligned mode
+ - the number of half PWM period in center-aligned mode
+ This parameter must be a number between 0x00 and 0xFF.
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ bool CapCh1FromCompEn; /*!< channel 1 select capture in from comp if 1, from IOM if 0
+ Tim1,Tim8,Tim2,Tim3,Tim4,Tim5 valid*/
+ bool CapCh2FromCompEn; /*!< channel 2 select capture in from comp if 1, from IOM if 0
+ Tim2,Tim3,Tim4,Tim5 valid*/
+ bool CapCh3FromCompEn; /*!< channel 3 select capture in from comp if 1, from IOM if 0
+ Tim2,Tim3,Tim4,Tim5 valid*/
+ bool CapCh4FromCompEn; /*!< channel 4 select capture in from comp if 1, from IOM if 0
+ Tim2,Tim3,Tim4 valid*/
+ bool CapEtrClrFromCompEn; /*!< etr clearref select from comp if 1, from ETR IOM if 0
+ Tim2,Tim3,Tim4 valid*/
+ bool CapEtrSelFromTscEn; /*!< etr select from TSC if 1, from IOM if 0
+ Tim2,Tim4 valid*/
+} TIM_TimeBaseInitType;
+
+/**
+ * @brief TIM Output Compare Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t OcMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+ uint16_t OutputState; /*!< Specifies the TIM Output Compare state.
+ This parameter can be a value of @ref TIM_Output_Compare_state */
+
+ uint16_t OutputNState; /*!< Specifies the TIM complementary Output Compare state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_state
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint16_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between 0x0000 and 0xFFFF */
+
+ uint16_t OcPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+ uint16_t OcNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint16_t OcIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint16_t OcNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+} OCInitType;
+
+/**
+ * @brief TIM Input Capture Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t Channel; /*!< Specifies the TIM channel.
+ This parameter can be a value of @ref Channel */
+
+ uint16_t IcPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint16_t IcSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint16_t IcPrescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint16_t IcFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between 0x0 and 0xF */
+} TIM_ICInitType;
+
+/**
+ * @brief BKDT structure definition
+ * @note This structure is used only with TIM1 and TIM8.
+ */
+
+typedef struct
+{
+ uint16_t OssrState; /*!< Specifies the Off-State selection used in Run mode.
+ This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
+
+ uint16_t OssiState; /*!< Specifies the Off-State used in Idle state.
+ This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
+
+ uint16_t LockLevel; /*!< Specifies the LOCK level parameters.
+ This parameter can be a value of @ref Lock_level */
+
+ uint16_t DeadTime; /*!< Specifies the delay time between the switching-off and the
+ switching-on of the outputs.
+ This parameter can be a number between 0x00 and 0xFF */
+
+ uint16_t Break; /*!< Specifies whether the TIM Break input is enabled or not.
+ This parameter can be a value of @ref Break_Input_enable_disable */
+
+ uint16_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
+ This parameter can be a value of @ref Break_Polarity */
+
+ uint16_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+ bool IomBreakEn; /*!< EXTENDMODE valid, open iom as break in*/
+ bool LockUpBreakEn; /*!< EXTENDMODE valid, open lockup(haldfault) as break in*/
+ bool PvdBreakEn; /*!< EXTENDMODE valid, open pvd(sys voltage too high or too low) as break in*/
+} TIM_BDTRInitType;
+
+/** @addtogroup TIM_Exported_constants
+ * @{
+ */
+
+#define IsTimAllModule(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \
+ || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8))
+
+/* LIST1: TIM 1 and 8 */
+#define IsTimList1Module(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM8))
+
+/* LIST2: TIM 1, 8 */
+#define IsTimList2Module(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM8))
+
+/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */
+#define IsTimList3Module(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \
+ || ((PERIPH) == TIM8))
+
+/* LIST4: TIM 1, 2, 3, 4, 5, 8 */
+#define IsTimList4Module(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \
+ || ((PERIPH) == TIM8))
+
+/* LIST5: TIM 1, 2, 3, 4, 5, 8 */
+#define IsTimList5Module(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \
+ || ((PERIPH) == TIM8))
+
+/* LIST6: TIM 1, 2, 3, 4, 5, 8 */
+#define IsTimList6Module(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \
+ || ((PERIPH) == TIM8))
+
+/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8 */
+#define IsTimList7Module(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \
+ || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8))
+
+/* LIST8: TIM 1, 2, 3, 4, 5, 8 */
+#define IsTimList8Module(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \
+ || ((PERIPH) == TIM8))
+
+/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8 */
+#define IsTimList9Module(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \
+ || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8))
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_and_PWM_modes
+ * @{
+ */
+
+#define TIM_OCMODE_TIMING ((uint16_t)0x0000)
+#define TIM_OCMODE_ACTIVE ((uint16_t)0x0010)
+#define TIM_OCMODE_INACTIVE ((uint16_t)0x0020)
+#define TIM_OCMODE_TOGGLE ((uint16_t)0x0030)
+#define TIM_OCMODE_PWM1 ((uint16_t)0x0060)
+#define TIM_OCMODE_PWM2 ((uint16_t)0x0070)
+#define IsTimOcMode(MODE) \
+ (((MODE) == TIM_OCMODE_TIMING) || ((MODE) == TIM_OCMODE_ACTIVE) || ((MODE) == TIM_OCMODE_INACTIVE) \
+ || ((MODE) == TIM_OCMODE_TOGGLE) || ((MODE) == TIM_OCMODE_PWM1) || ((MODE) == TIM_OCMODE_PWM2))
+#define IsTimOc(MODE) \
+ (((MODE) == TIM_OCMODE_TIMING) || ((MODE) == TIM_OCMODE_ACTIVE) || ((MODE) == TIM_OCMODE_INACTIVE) \
+ || ((MODE) == TIM_OCMODE_TOGGLE) || ((MODE) == TIM_OCMODE_PWM1) || ((MODE) == TIM_OCMODE_PWM2) \
+ || ((MODE) == TIM_FORCED_ACTION_ACTIVE) || ((MODE) == TIM_FORCED_ACTION_INACTIVE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_One_Pulse_Mode
+ * @{
+ */
+
+#define TIM_OPMODE_SINGLE ((uint16_t)0x0008)
+#define TIM_OPMODE_REPET ((uint16_t)0x0000)
+#define IsTimOpMOde(MODE) (((MODE) == TIM_OPMODE_SINGLE) || ((MODE) == TIM_OPMODE_REPET))
+/**
+ * @}
+ */
+
+/** @addtogroup Channel
+ * @{
+ */
+
+#define TIM_CH_1 ((uint16_t)0x0000)
+#define TIM_CH_2 ((uint16_t)0x0004)
+#define TIM_CH_3 ((uint16_t)0x0008)
+#define TIM_CH_4 ((uint16_t)0x000C)
+#define IsTimCh(CHANNEL) \
+ (((CHANNEL) == TIM_CH_1) || ((CHANNEL) == TIM_CH_2) || ((CHANNEL) == TIM_CH_3) || ((CHANNEL) == TIM_CH_4))
+#define IsTimPwmInCh(CHANNEL) (((CHANNEL) == TIM_CH_1) || ((CHANNEL) == TIM_CH_2))
+#define IsTimComplementaryCh(CHANNEL) (((CHANNEL) == TIM_CH_1) || ((CHANNEL) == TIM_CH_2) || ((CHANNEL) == TIM_CH_3))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Clock_Division_CKD
+ * @{
+ */
+
+#define TIM_CLK_DIV1 ((uint16_t)0x0000)
+#define TIM_CLK_DIV2 ((uint16_t)0x0100)
+#define TIM_CLK_DIV4 ((uint16_t)0x0200)
+#define IsTimClkDiv(DIV) (((DIV) == TIM_CLK_DIV1) || ((DIV) == TIM_CLK_DIV2) || ((DIV) == TIM_CLK_DIV4))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Counter_Mode
+ * @{
+ */
+
+#define TIM_CNT_MODE_UP ((uint16_t)0x0000)
+#define TIM_CNT_MODE_DOWN ((uint16_t)0x0010)
+#define TIM_CNT_MODE_CENTER_ALIGN1 ((uint16_t)0x0020)
+#define TIM_CNT_MODE_CENTER_ALIGN2 ((uint16_t)0x0040)
+#define TIM_CNT_MODE_CENTER_ALIGN3 ((uint16_t)0x0060)
+#define IsTimCntMode(MODE) \
+ (((MODE) == TIM_CNT_MODE_UP) || ((MODE) == TIM_CNT_MODE_DOWN) || ((MODE) == TIM_CNT_MODE_CENTER_ALIGN1) \
+ || ((MODE) == TIM_CNT_MODE_CENTER_ALIGN2) || ((MODE) == TIM_CNT_MODE_CENTER_ALIGN3))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_Polarity
+ * @{
+ */
+
+#define TIM_OC_POLARITY_HIGH ((uint16_t)0x0000)
+#define TIM_OC_POLARITY_LOW ((uint16_t)0x0002)
+#define IsTimOcPolarity(POLARITY) (((POLARITY) == TIM_OC_POLARITY_HIGH) || ((POLARITY) == TIM_OC_POLARITY_LOW))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_N_Polarity
+ * @{
+ */
+
+#define TIM_OCN_POLARITY_HIGH ((uint16_t)0x0000)
+#define TIM_OCN_POLARITY_LOW ((uint16_t)0x0008)
+#define IsTimOcnPolarity(POLARITY) (((POLARITY) == TIM_OCN_POLARITY_HIGH) || ((POLARITY) == TIM_OCN_POLARITY_LOW))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_state
+ * @{
+ */
+
+#define TIM_OUTPUT_STATE_DISABLE ((uint16_t)0x0000)
+#define TIM_OUTPUT_STATE_ENABLE ((uint16_t)0x0001)
+#define IsTimOutputState(STATE) (((STATE) == TIM_OUTPUT_STATE_DISABLE) || ((STATE) == TIM_OUTPUT_STATE_ENABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_N_state
+ * @{
+ */
+
+#define TIM_OUTPUT_NSTATE_DISABLE ((uint16_t)0x0000)
+#define TIM_OUTPUT_NSTATE_ENABLE ((uint16_t)0x0004)
+#define IsTimOutputNState(STATE) (((STATE) == TIM_OUTPUT_NSTATE_DISABLE) || ((STATE) == TIM_OUTPUT_NSTATE_ENABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Capture_Compare_state
+ * @{
+ */
+
+#define TIM_CAP_CMP_ENABLE ((uint16_t)0x0001)
+#define TIM_CAP_CMP_DISABLE ((uint16_t)0x0000)
+#define IsTimCapCmpState(CCX) (((CCX) == TIM_CAP_CMP_ENABLE) || ((CCX) == TIM_CAP_CMP_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Capture_Compare_N_state
+ * @{
+ */
+
+#define TIM_CAP_CMP_N_ENABLE ((uint16_t)0x0004)
+#define TIM_CAP_CMP_N_DISABLE ((uint16_t)0x0000)
+#define IsTimCapCmpNState(CCXN) (((CCXN) == TIM_CAP_CMP_N_ENABLE) || ((CCXN) == TIM_CAP_CMP_N_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup Break_Input_enable_disable
+ * @{
+ */
+
+#define TIM_BREAK_IN_ENABLE ((uint16_t)0x1000)
+#define TIM_BREAK_IN_DISABLE ((uint16_t)0x0000)
+#define IsTimBreakInState(STATE) (((STATE) == TIM_BREAK_IN_ENABLE) || ((STATE) == TIM_BREAK_IN_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup Break_Polarity
+ * @{
+ */
+
+#define TIM_BREAK_POLARITY_LOW ((uint16_t)0x0000)
+#define TIM_BREAK_POLARITY_HIGH ((uint16_t)0x2000)
+#define IsTimBreakPalarity(POLARITY) (((POLARITY) == TIM_BREAK_POLARITY_LOW) || ((POLARITY) == TIM_BREAK_POLARITY_HIGH))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_AOE_Bit_Set_Reset
+ * @{
+ */
+
+#define TIM_AUTO_OUTPUT_ENABLE ((uint16_t)0x4000)
+#define TIM_AUTO_OUTPUT_DISABLE ((uint16_t)0x0000)
+#define IsTimAutoOutputState(STATE) (((STATE) == TIM_AUTO_OUTPUT_ENABLE) || ((STATE) == TIM_AUTO_OUTPUT_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup Lock_level
+ * @{
+ */
+
+#define TIM_LOCK_LEVEL_OFF ((uint16_t)0x0000)
+#define TIM_LOCK_LEVEL_1 ((uint16_t)0x0100)
+#define TIM_LOCK_LEVEL_2 ((uint16_t)0x0200)
+#define TIM_LOCK_LEVEL_3 ((uint16_t)0x0300)
+#define IsTimLockLevel(LEVEL) \
+ (((LEVEL) == TIM_LOCK_LEVEL_OFF) || ((LEVEL) == TIM_LOCK_LEVEL_1) || ((LEVEL) == TIM_LOCK_LEVEL_2) \
+ || ((LEVEL) == TIM_LOCK_LEVEL_3))
+/**
+ * @}
+ */
+
+/** @addtogroup OSSI_Off_State_Selection_for_Idle_mode_state
+ * @{
+ */
+
+#define TIM_OSSI_STATE_ENABLE ((uint16_t)0x0400)
+#define TIM_OSSI_STATE_DISABLE ((uint16_t)0x0000)
+#define IsTimOssiState(STATE) (((STATE) == TIM_OSSI_STATE_ENABLE) || ((STATE) == TIM_OSSI_STATE_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup OSSR_Off_State_Selection_for_Run_mode_state
+ * @{
+ */
+
+#define TIM_OSSR_STATE_ENABLE ((uint16_t)0x0800)
+#define TIM_OSSR_STATE_DISABLE ((uint16_t)0x0000)
+#define IsTimOssrState(STATE) (((STATE) == TIM_OSSR_STATE_ENABLE) || ((STATE) == TIM_OSSR_STATE_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_Idle_State
+ * @{
+ */
+
+#define TIM_OC_IDLE_STATE_SET ((uint16_t)0x0100)
+#define TIM_OC_IDLE_STATE_RESET ((uint16_t)0x0000)
+#define IsTimOcIdleState(STATE) (((STATE) == TIM_OC_IDLE_STATE_SET) || ((STATE) == TIM_OC_IDLE_STATE_RESET))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_N_Idle_State
+ * @{
+ */
+
+#define TIM_OCN_IDLE_STATE_SET ((uint16_t)0x0200)
+#define TIM_OCN_IDLE_STATE_RESET ((uint16_t)0x0000)
+#define IsTimOcnIdleState(STATE) (((STATE) == TIM_OCN_IDLE_STATE_SET) || ((STATE) == TIM_OCN_IDLE_STATE_RESET))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Input_Capture_Polarity
+ * @{
+ */
+
+#define TIM_IC_POLARITY_RISING ((uint16_t)0x0000)
+#define TIM_IC_POLARITY_FALLING ((uint16_t)0x0002)
+#define TIM_IC_POLARITY_BOTHEDGE ((uint16_t)0x000A)
+#define IsTimIcPalaritySingleEdge(POLARITY) \
+ (((POLARITY) == TIM_IC_POLARITY_RISING) || ((POLARITY) == TIM_IC_POLARITY_FALLING))
+#define IsTimIcPolarityAnyEdge(POLARITY) \
+ (((POLARITY) == TIM_IC_POLARITY_RISING) || ((POLARITY) == TIM_IC_POLARITY_FALLING) \
+ || ((POLARITY) == TIM_IC_POLARITY_BOTHEDGE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Input_Capture_Selection
+ * @{
+ */
+
+#define TIM_IC_SELECTION_DIRECTTI \
+ ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be \
+ connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_IC_SELECTION_INDIRECTTI \
+ ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be \
+ connected to IC2, IC1, IC4 or IC3, respectively. */
+#define TIM_IC_SELECTION_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
+#define IsTimIcSelection(SELECTION) \
+ (((SELECTION) == TIM_IC_SELECTION_DIRECTTI) || ((SELECTION) == TIM_IC_SELECTION_INDIRECTTI) \
+ || ((SELECTION) == TIM_IC_SELECTION_TRC))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Input_Capture_Prescaler
+ * @{
+ */
+
+#define TIM_IC_PSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. \
+ */
+#define TIM_IC_PSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
+#define TIM_IC_PSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
+#define TIM_IC_PSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
+#define IsTimIcPrescaler(PRESCALER) \
+ (((PRESCALER) == TIM_IC_PSC_DIV1) || ((PRESCALER) == TIM_IC_PSC_DIV2) || ((PRESCALER) == TIM_IC_PSC_DIV4) \
+ || ((PRESCALER) == TIM_IC_PSC_DIV8))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_interrupt_sources
+ * @{
+ */
+
+#define TIM_INT_UPDATE ((uint16_t)0x0001)
+#define TIM_INT_CC1 ((uint16_t)0x0002)
+#define TIM_INT_CC2 ((uint16_t)0x0004)
+#define TIM_INT_CC3 ((uint16_t)0x0008)
+#define TIM_INT_CC4 ((uint16_t)0x0010)
+#define TIM_INT_COM ((uint16_t)0x0020)
+#define TIM_INT_TRIG ((uint16_t)0x0040)
+#define TIM_INT_BREAK ((uint16_t)0x0080)
+#define IsTimInt(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
+
+#define IsTimGetInt(IT) \
+ (((IT) == TIM_INT_UPDATE) || ((IT) == TIM_INT_CC1) || ((IT) == TIM_INT_CC2) || ((IT) == TIM_INT_CC3) \
+ || ((IT) == TIM_INT_CC4) || ((IT) == TIM_INT_COM) || ((IT) == TIM_INT_TRIG) || ((IT) == TIM_INT_BREAK))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_DMA_Base_address
+ * @{
+ */
+
+#define TIM_DMABASE_CTRL1 ((uint16_t)0x0000)
+#define TIM_DMABASE_CTRL2 ((uint16_t)0x0001)
+#define TIM_DMABASE_SMCTRL ((uint16_t)0x0002)
+#define TIM_DMABASE_DMAINTEN ((uint16_t)0x0003)
+#define TIM_DMABASE_STS ((uint16_t)0x0004)
+#define TIM_DMABASE_EVTGEN ((uint16_t)0x0005)
+#define TIM_DMABASE_CAPCMPMOD1 ((uint16_t)0x0006)
+#define TIM_DMABASE_CAPCMPMOD2 ((uint16_t)0x0007)
+#define TIM_DMABASE_CAPCMPEN ((uint16_t)0x0008)
+#define TIM_DMABASE_CNT ((uint16_t)0x0009)
+#define TIM_DMABASE_PSC ((uint16_t)0x000A)
+#define TIM_DMABASE_AR ((uint16_t)0x000B)
+#define TIM_DMABASE_REPCNT ((uint16_t)0x000C)
+#define TIM_DMABASE_CAPCMPDAT1 ((uint16_t)0x000D)
+#define TIM_DMABASE_CAPCMPDAT2 ((uint16_t)0x000E)
+#define TIM_DMABASE_CAPCMPDAT3 ((uint16_t)0x000F)
+#define TIM_DMABASE_CAPCMPDAT4 ((uint16_t)0x0010)
+#define TIM_DMABASE_BKDT ((uint16_t)0x0011)
+#define TIM_DMABASE_DMACTRL ((uint16_t)0x0012)
+
+
+#define IsTimDmaBase(BASE) \
+ (((BASE) == TIM_DMABASE_CTRL1) || ((BASE) == TIM_DMABASE_CTRL2) || ((BASE) == TIM_DMABASE_SMCTRL) \
+ || ((BASE) == TIM_DMABASE_DMAINTEN) || ((BASE) == TIM_DMABASE_STS) || ((BASE) == TIM_DMABASE_EVTGEN) \
+ || ((BASE) == TIM_DMABASE_CAPCMPMOD1) || ((BASE) == TIM_DMABASE_CAPCMPMOD2) \
+ || ((BASE) == TIM_DMABASE_CAPCMPEN) || ((BASE) == TIM_DMABASE_CNT) || ((BASE) == TIM_DMABASE_PSC) \
+ || ((BASE) == TIM_DMABASE_AR) || ((BASE) == TIM_DMABASE_REPCNT) || ((BASE) == TIM_DMABASE_CAPCMPDAT1) \
+ || ((BASE) == TIM_DMABASE_CAPCMPDAT2) || ((BASE) == TIM_DMABASE_CAPCMPDAT3) || ((BASE) == TIM_DMABASE_CAPCMPDAT4) \
+ || ((BASE) == TIM_DMABASE_BKDT)|| ((BASE) == TIM_DMABASE_DMACTRL))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_DMA_Burst_Length
+ * @{
+ */
+
+#define TIM_DMABURST_LENGTH_1TRANSFER ((uint16_t)0x0000)
+#define TIM_DMABURST_LENGTH_2TRANSFERS ((uint16_t)0x0100)
+#define TIM_DMABURST_LENGTH_3TRANSFERS ((uint16_t)0x0200)
+#define TIM_DMABURST_LENGTH_4TRANSFERS ((uint16_t)0x0300)
+#define TIM_DMABURST_LENGTH_5TRANSFERS ((uint16_t)0x0400)
+#define TIM_DMABURST_LENGTH_6TRANSFERS ((uint16_t)0x0500)
+#define TIM_DMABURST_LENGTH_7TRANSFERS ((uint16_t)0x0600)
+#define TIM_DMABURST_LENGTH_8TRANSFERS ((uint16_t)0x0700)
+#define TIM_DMABURST_LENGTH_9TRANSFERS ((uint16_t)0x0800)
+#define TIM_DMABURST_LENGTH_10TRANSFERS ((uint16_t)0x0900)
+#define TIM_DMABURST_LENGTH_11TRANSFERS ((uint16_t)0x0A00)
+#define TIM_DMABURST_LENGTH_12TRANSFERS ((uint16_t)0x0B00)
+#define TIM_DMABURST_LENGTH_13TRANSFERS ((uint16_t)0x0C00)
+#define TIM_DMABURST_LENGTH_14TRANSFERS ((uint16_t)0x0D00)
+#define TIM_DMABURST_LENGTH_15TRANSFERS ((uint16_t)0x0E00)
+#define TIM_DMABURST_LENGTH_16TRANSFERS ((uint16_t)0x0F00)
+#define TIM_DMABURST_LENGTH_17TRANSFERS ((uint16_t)0x1000)
+#define TIM_DMABURST_LENGTH_18TRANSFERS ((uint16_t)0x1100)
+#define TIM_DMABURST_LENGTH_19TRANSFERS ((uint16_t)0x1200)
+#define TIM_DMABURST_LENGTH_20TRANSFERS ((uint16_t)0x1300)
+#define TIM_DMABURST_LENGTH_21TRANSFERS ((uint16_t)0x1400)
+#define IsTimDmaLength(LENGTH) \
+ (((LENGTH) == TIM_DMABURST_LENGTH_1TRANSFER) || ((LENGTH) == TIM_DMABURST_LENGTH_2TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_3TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_4TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_5TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_6TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_7TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_8TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_9TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_10TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_11TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_12TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_13TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_14TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_15TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_16TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_17TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_18TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_19TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_20TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_21TRANSFERS))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_DMA_sources
+ * @{
+ */
+
+#define TIM_DMA_UPDATE ((uint16_t)0x0100)
+#define TIM_DMA_CC1 ((uint16_t)0x0200)
+#define TIM_DMA_CC2 ((uint16_t)0x0400)
+#define TIM_DMA_CC3 ((uint16_t)0x0800)
+#define TIM_DMA_CC4 ((uint16_t)0x1000)
+#define TIM_DMA_COM ((uint16_t)0x2000)
+#define TIM_DMA_TRIG ((uint16_t)0x4000)
+#define IsTimDmaSrc(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_External_Trigger_Prescaler
+ * @{
+ */
+
+#define TIM_EXT_TRG_PSC_OFF ((uint16_t)0x0000)
+#define TIM_EXT_TRG_PSC_DIV2 ((uint16_t)0x1000)
+#define TIM_EXT_TRG_PSC_DIV4 ((uint16_t)0x2000)
+#define TIM_EXT_TRG_PSC_DIV8 ((uint16_t)0x3000)
+#define IsTimExtPreDiv(PRESCALER) \
+ (((PRESCALER) == TIM_EXT_TRG_PSC_OFF) || ((PRESCALER) == TIM_EXT_TRG_PSC_DIV2) \
+ || ((PRESCALER) == TIM_EXT_TRG_PSC_DIV4) || ((PRESCALER) == TIM_EXT_TRG_PSC_DIV8))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Internal_Trigger_Selection
+ * @{
+ */
+
+#define TIM_TRIG_SEL_IN_TR0 ((uint16_t)0x0000)
+#define TIM_TRIG_SEL_IN_TR1 ((uint16_t)0x0010)
+#define TIM_TRIG_SEL_IN_TR2 ((uint16_t)0x0020)
+#define TIM_TRIG_SEL_IN_TR3 ((uint16_t)0x0030)
+#define TIM_TRIG_SEL_TI1F_ED ((uint16_t)0x0040)
+#define TIM_TRIG_SEL_TI1FP1 ((uint16_t)0x0050)
+#define TIM_TRIG_SEL_TI2FP2 ((uint16_t)0x0060)
+#define TIM_TRIG_SEL_ETRF ((uint16_t)0x0070)
+#define IsTimTrigSel(SELECTION) \
+ (((SELECTION) == TIM_TRIG_SEL_IN_TR0) || ((SELECTION) == TIM_TRIG_SEL_IN_TR1) \
+ || ((SELECTION) == TIM_TRIG_SEL_IN_TR2) || ((SELECTION) == TIM_TRIG_SEL_IN_TR3) \
+ || ((SELECTION) == TIM_TRIG_SEL_TI1F_ED) || ((SELECTION) == TIM_TRIG_SEL_TI1FP1) \
+ || ((SELECTION) == TIM_TRIG_SEL_TI2FP2) || ((SELECTION) == TIM_TRIG_SEL_ETRF))
+#define IsTimInterTrigSel(SELECTION) \
+ (((SELECTION) == TIM_TRIG_SEL_IN_TR0) || ((SELECTION) == TIM_TRIG_SEL_IN_TR1) \
+ || ((SELECTION) == TIM_TRIG_SEL_IN_TR2) || ((SELECTION) == TIM_TRIG_SEL_IN_TR3))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_TIx_External_Clock_Source
+ * @{
+ */
+
+#define TIM_EXT_CLK_SRC_TI1 ((uint16_t)0x0050)
+#define TIM_EXT_CLK_SRC_TI2 ((uint16_t)0x0060)
+#define TIM_EXT_CLK_SRC_TI1ED ((uint16_t)0x0040)
+#define IsTimExtClkSrc(SOURCE) \
+ (((SOURCE) == TIM_EXT_CLK_SRC_TI1) || ((SOURCE) == TIM_EXT_CLK_SRC_TI2) || ((SOURCE) == TIM_EXT_CLK_SRC_TI1ED))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_External_Trigger_Polarity
+ * @{
+ */
+#define TIM_EXT_TRIG_POLARITY_INVERTED ((uint16_t)0x8000)
+#define TIM_EXT_TRIG_POLARITY_NONINVERTED ((uint16_t)0x0000)
+#define IsTimExtTrigPolarity(POLARITY) \
+ (((POLARITY) == TIM_EXT_TRIG_POLARITY_INVERTED) || ((POLARITY) == TIM_EXT_TRIG_POLARITY_NONINVERTED))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Prescaler_Reload_Mode
+ * @{
+ */
+
+#define TIM_PSC_RELOAD_MODE_UPDATE ((uint16_t)0x0000)
+#define TIM_PSC_RELOAD_MODE_IMMEDIATE ((uint16_t)0x0001)
+#define IsTimPscReloadMode(RELOAD) \
+ (((RELOAD) == TIM_PSC_RELOAD_MODE_UPDATE) || ((RELOAD) == TIM_PSC_RELOAD_MODE_IMMEDIATE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Forced_Action
+ * @{
+ */
+
+#define TIM_FORCED_ACTION_ACTIVE ((uint16_t)0x0050)
+#define TIM_FORCED_ACTION_INACTIVE ((uint16_t)0x0040)
+#define IsTimForceActive(OPERATE) (((OPERATE) == TIM_FORCED_ACTION_ACTIVE) || ((OPERATE) == TIM_FORCED_ACTION_INACTIVE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Encoder_Mode
+ * @{
+ */
+
+#define TIM_ENCODE_MODE_TI1 ((uint16_t)0x0001)
+#define TIM_ENCODE_MODE_TI2 ((uint16_t)0x0002)
+#define TIM_ENCODE_MODE_TI12 ((uint16_t)0x0003)
+#define IsTimEncodeMode(MODE) \
+ (((MODE) == TIM_ENCODE_MODE_TI1) || ((MODE) == TIM_ENCODE_MODE_TI2) || ((MODE) == TIM_ENCODE_MODE_TI12))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Event_Source
+ * @{
+ */
+
+#define TIM_EVT_SRC_UPDATE ((uint16_t)0x0001)
+#define TIM_EVT_SRC_CC1 ((uint16_t)0x0002)
+#define TIM_EVT_SRC_CC2 ((uint16_t)0x0004)
+#define TIM_EVT_SRC_CC3 ((uint16_t)0x0008)
+#define TIM_EVT_SRC_CC4 ((uint16_t)0x0010)
+#define TIM_EVT_SRC_COM ((uint16_t)0x0020)
+#define TIM_EVT_SRC_TRIG ((uint16_t)0x0040)
+#define TIM_EVT_SRC_BREAK ((uint16_t)0x0080)
+#define IsTimEvtSrc(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Update_Source
+ * @{
+ */
+
+#define TIM_UPDATE_SRC_GLOBAL \
+ ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow \
+ or the setting of UG bit, or an update generation \
+ through the slave mode controller. */
+#define TIM_UPDATE_SRC_REGULAr ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
+#define IsTimUpdateSrc(SOURCE) (((SOURCE) == TIM_UPDATE_SRC_GLOBAL) || ((SOURCE) == TIM_UPDATE_SRC_REGULAr))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_Preload_State
+ * @{
+ */
+
+#define TIM_OC_PRE_LOAD_ENABLE ((uint16_t)0x0008)
+#define TIM_OC_PRE_LOAD_DISABLE ((uint16_t)0x0000)
+#define IsTimOcPreLoadState(STATE) (((STATE) == TIM_OC_PRE_LOAD_ENABLE) || ((STATE) == TIM_OC_PRE_LOAD_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_Fast_State
+ * @{
+ */
+
+#define TIM_OC_FAST_ENABLE ((uint16_t)0x0004)
+#define TIM_OC_FAST_DISABLE ((uint16_t)0x0000)
+#define IsTimOcFastState(STATE) (((STATE) == TIM_OC_FAST_ENABLE) || ((STATE) == TIM_OC_FAST_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_Clear_State
+ * @{
+ */
+
+#define TIM_OC_CLR_ENABLE ((uint16_t)0x0080)
+#define TIM_OC_CLR_DISABLE ((uint16_t)0x0000)
+#define IsTimOcClrState(STATE) (((STATE) == TIM_OC_CLR_ENABLE) || ((STATE) == TIM_OC_CLR_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Trigger_Output_Source
+ * @{
+ */
+
+#define TIM_TRGO_SRC_RESET ((uint16_t)0x0000)
+#define TIM_TRGO_SRC_ENABLE ((uint16_t)0x0010)
+#define TIM_TRGO_SRC_UPDATE ((uint16_t)0x0020)
+#define TIM_TRGO_SRC_OC1 ((uint16_t)0x0030)
+#define TIM_TRGO_SRC_OC1REF ((uint16_t)0x0040)
+#define TIM_TRGO_SRC_OC2REF ((uint16_t)0x0050)
+#define TIM_TRGO_SRC_OC3REF ((uint16_t)0x0060)
+#define TIM_TRGO_SRC_OC4REF ((uint16_t)0x0070)
+#define IsTimTrgoSrc(SOURCE) \
+ (((SOURCE) == TIM_TRGO_SRC_RESET) || ((SOURCE) == TIM_TRGO_SRC_ENABLE) || ((SOURCE) == TIM_TRGO_SRC_UPDATE) \
+ || ((SOURCE) == TIM_TRGO_SRC_OC1) || ((SOURCE) == TIM_TRGO_SRC_OC1REF) || ((SOURCE) == TIM_TRGO_SRC_OC2REF) \
+ || ((SOURCE) == TIM_TRGO_SRC_OC3REF) || ((SOURCE) == TIM_TRGO_SRC_OC4REF))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Slave_Mode
+ * @{
+ */
+
+#define TIM_SLAVE_MODE_RESET ((uint16_t)0x0004)
+#define TIM_SLAVE_MODE_GATED ((uint16_t)0x0005)
+#define TIM_SLAVE_MODE_TRIG ((uint16_t)0x0006)
+#define TIM_SLAVE_MODE_EXT1 ((uint16_t)0x0007)
+#define IsTimSlaveMode(MODE) \
+ (((MODE) == TIM_SLAVE_MODE_RESET) || ((MODE) == TIM_SLAVE_MODE_GATED) || ((MODE) == TIM_SLAVE_MODE_TRIG) \
+ || ((MODE) == TIM_SLAVE_MODE_EXT1))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Master_Slave_Mode
+ * @{
+ */
+
+#define TIM_MASTER_SLAVE_MODE_ENABLE ((uint16_t)0x0080)
+#define TIM_MASTER_SLAVE_MODE_DISABLE ((uint16_t)0x0000)
+#define IsTimMasterSlaveMode(STATE) \
+ (((STATE) == TIM_MASTER_SLAVE_MODE_ENABLE) || ((STATE) == TIM_MASTER_SLAVE_MODE_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Flags
+ * @{
+ */
+
+#define TIM_FLAG_UPDATE ((uint32_t)0x0001)
+#define TIM_FLAG_CC1 ((uint32_t)0x0002)
+#define TIM_FLAG_CC2 ((uint32_t)0x0004)
+#define TIM_FLAG_CC3 ((uint32_t)0x0008)
+#define TIM_FLAG_CC4 ((uint32_t)0x0010)
+#define TIM_FLAG_COM ((uint32_t)0x0020)
+#define TIM_FLAG_TRIG ((uint32_t)0x0040)
+#define TIM_FLAG_BREAK ((uint32_t)0x0080)
+#define TIM_FLAG_CC1OF ((uint32_t)0x0200)
+#define TIM_FLAG_CC2OF ((uint32_t)0x0400)
+#define TIM_FLAG_CC3OF ((uint32_t)0x0800)
+#define TIM_FLAG_CC4OF ((uint32_t)0x1000)
+#define TIM_FLAG_CC5 ((uint32_t)0x010000)
+#define TIM_FLAG_CC6 ((uint32_t)0x020000)
+
+#define IsTimGetFlag(FLAG) \
+ (((FLAG) == TIM_FLAG_UPDATE) || ((FLAG) == TIM_FLAG_CC1) || ((FLAG) == TIM_FLAG_CC2) || ((FLAG) == TIM_FLAG_CC3) \
+ || ((FLAG) == TIM_FLAG_CC4) || ((FLAG) == TIM_FLAG_COM) || ((FLAG) == TIM_FLAG_TRIG) \
+ || ((FLAG) == TIM_FLAG_BREAK) || ((FLAG) == TIM_FLAG_CC1OF) || ((FLAG) == TIM_FLAG_CC2OF) \
+ || ((FLAG) == TIM_FLAG_CC3OF) || ((FLAG) == TIM_FLAG_CC4OF) || ((FLAG) == TIM_FLAG_CC5) \
+ || ((FLAG) == TIM_FLAG_CC6))
+
+#define IsTimClrFlag(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Input_Capture_Filer_Value
+ * @{
+ */
+
+#define IsTimInCapFilter(ICFILTER) ((ICFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_External_Trigger_Filter
+ * @{
+ */
+
+#define IsTimExtTrigFilter(EXTFILTER) ((EXTFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+#define TIM_CC1EN ((uint32_t)1<<0)
+#define TIM_CC1NEN ((uint32_t)1<<2)
+#define TIM_CC2EN ((uint32_t)1<<4)
+#define TIM_CC2NEN ((uint32_t)1<<6)
+#define TIM_CC3EN ((uint32_t)1<<8)
+#define TIM_CC3NEN ((uint32_t)1<<10)
+#define TIM_CC4EN ((uint32_t)1<<12)
+#define TIM_CC5EN ((uint32_t)1<<16)
+#define TIM_CC6EN ((uint32_t)1<<20)
+
+#define IsAdvancedTimCCENFlag(FLAG) \
+ (((FLAG) == TIM_CC1EN) || ((FLAG) == TIM_CC1NEN) || ((FLAG) == TIM_CC2EN) || ((FLAG) == TIM_CC2NEN) \
+ || ((FLAG) == TIM_CC3EN) || ((FLAG) == TIM_CC3NEN) \
+ || ((FLAG) == TIM_CC4EN) || ((FLAG) == TIM_CC5EN) || ((FLAG) == TIM_CC6EN) )
+#define IsGeneralTimCCENFlag(FLAG) \
+ (((FLAG) == TIM_CC1EN) || ((FLAG) == TIM_CC2EN) \
+ || ((FLAG) == TIM_CC3EN) \
+ || ((FLAG) == TIM_CC4EN) )
+
+/** @addtogroup TIM_Legacy
+ * @{
+ */
+
+#define TIM_DMA_BURST_LEN_1BYTE TIM_DMABURST_LENGTH_1TRANSFER
+#define TIM_DMA_BURST_LEN_2BYTES TIM_DMABURST_LENGTH_2TRANSFERS
+#define TIM_DMA_BURST_LEN_3BYTES TIM_DMABURST_LENGTH_3TRANSFERS
+#define TIM_DMA_BURST_LEN_4BYTES TIM_DMABURST_LENGTH_4TRANSFERS
+#define TIM_DMA_BURST_LEN_5BYTES TIM_DMABURST_LENGTH_5TRANSFERS
+#define TIM_DMA_BURST_LEN_6BYTES TIM_DMABURST_LENGTH_6TRANSFERS
+#define TIM_DMA_BURST_LEN_7BYTES TIM_DMABURST_LENGTH_7TRANSFERS
+#define TIM_DMA_BURST_LEN_8BYTES TIM_DMABURST_LENGTH_8TRANSFERS
+#define TIM_DMA_BURST_LEN_9BYTES TIM_DMABURST_LENGTH_9TRANSFERS
+#define TIM_DMA_BURST_LEN_10BYTES TIM_DMABURST_LENGTH_10TRANSFERS
+#define TIM_DMA_BURST_LEN_11BYTES TIM_DMABURST_LENGTH_11TRANSFERS
+#define TIM_DMA_BURST_LEN_12BYTES TIM_DMABURST_LENGTH_12TRANSFERS
+#define TIM_DMA_BURST_LEN_13BYTES TIM_DMABURST_LENGTH_13TRANSFERS
+#define TIM_DMA_BURST_LEN_14BYTES TIM_DMABURST_LENGTH_14TRANSFERS
+#define TIM_DMA_BURST_LEN_15BYTES TIM_DMABURST_LENGTH_15TRANSFERS
+#define TIM_DMA_BURST_LEN_16BYTES TIM_DMABURST_LENGTH_16TRANSFERS
+#define TIM_DMA_BURST_LEN_17BYTES TIM_DMABURST_LENGTH_17TRANSFERS
+#define TIM_DMA_BURST_LEN_18BYTES TIM_DMABURST_LENGTH_18TRANSFERS
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions
+ * @{
+ */
+
+void TIM_DeInit(TIM_Module* TIMx);
+void TIM_InitTimeBase(TIM_Module* TIMx, TIM_TimeBaseInitType* TIM_TimeBaseInitStruct);
+void TIM_InitOc1(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
+void TIM_InitOc2(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
+void TIM_InitOc3(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
+void TIM_InitOc4(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
+void TIM_InitOc5(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
+void TIM_InitOc6(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
+void TIM_ICInit(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct);
+void TIM_ConfigPwmIc(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct);
+void TIM_ConfigBkdt(TIM_Module* TIMx, TIM_BDTRInitType* TIM_BDTRInitStruct);
+void TIM_InitTimBaseStruct(TIM_TimeBaseInitType* TIM_TimeBaseInitStruct);
+void TIM_InitOcStruct(OCInitType* TIM_OCInitStruct);
+void TIM_InitIcStruct(TIM_ICInitType* TIM_ICInitStruct);
+void TIM_InitBkdtStruct(TIM_BDTRInitType* TIM_BDTRInitStruct);
+void TIM_Enable(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_EnableCtrlPwmOutputs(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_ConfigInt(TIM_Module* TIMx, uint16_t TIM_IT, FunctionalState Cmd);
+void TIM_GenerateEvent(TIM_Module* TIMx, uint16_t TIM_EventSource);
+void TIM_ConfigDma(TIM_Module* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
+void TIM_EnableDma(TIM_Module* TIMx, uint16_t TIM_DMASource, FunctionalState Cmd);
+void TIM_ConfigInternalClk(TIM_Module* TIMx);
+void TIM_ConfigInternalTrigToExt(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_ConfigExtTrigAsClk(TIM_Module* TIMx,
+ uint16_t TIM_TIxExternalCLKSource,
+ uint16_t IcPolarity,
+ uint16_t ICFilter);
+void TIM_ConfigExtClkMode1(TIM_Module* TIMx,
+ uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter);
+void TIM_ConfigExtClkMode2(TIM_Module* TIMx,
+ uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter);
+void TIM_ConfigExtTrig(TIM_Module* TIMx,
+ uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter);
+void TIM_ConfigPrescaler(TIM_Module* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
+void TIM_ConfigCntMode(TIM_Module* TIMx, uint16_t CntMode);
+void TIM_SelectInputTrig(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_ConfigEncoderInterface(TIM_Module* TIMx,
+ uint16_t TIM_EncoderMode,
+ uint16_t TIM_IC1Polarity,
+ uint16_t TIM_IC2Polarity);
+void TIM_ConfigForcedOc1(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ConfigForcedOc2(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ConfigForcedOc3(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ConfigForcedOc4(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ConfigForcedOc5(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ConfigForcedOc6(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ConfigArPreload(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_SelectComEvt(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_SelectCapCmpDmaSrc(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_EnableCapCmpPreloadControl(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_ConfigOc1Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload);
+void TIM_ConfigOc2Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload);
+void TIM_ConfigOc3Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload);
+void TIM_ConfigOc4Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload);
+void TIM_ConfigOc5Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload);
+void TIM_ConfigOc6Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload);
+void TIM_ConfigOc1Fast(TIM_Module* TIMx, uint16_t TIM_OCFast);
+void TIM_ConfigOc2Fast(TIM_Module* TIMx, uint16_t TIM_OCFast);
+void TIM_ConfigOc3Fast(TIM_Module* TIMx, uint16_t TIM_OCFast);
+void TIM_ConfigOc4Fast(TIM_Module* TIMx, uint16_t TIM_OCFast);
+void TIM_ConfigOc5Fast(TIM_Module* TIMx, uint16_t TIM_OCFast);
+void TIM_ConfigOc6Fast(TIM_Module* TIMx, uint16_t TIM_OCFast);
+void TIM_ClrOc1Ref(TIM_Module* TIMx, uint16_t TIM_OCClear);
+void TIM_ClrOc2Ref(TIM_Module* TIMx, uint16_t TIM_OCClear);
+void TIM_ClrOc3Ref(TIM_Module* TIMx, uint16_t TIM_OCClear);
+void TIM_ClrOc4Ref(TIM_Module* TIMx, uint16_t TIM_OCClear);
+void TIM_ClrOc5Ref(TIM_Module* TIMx, uint16_t TIM_OCClear);
+void TIM_ClrOc6Ref(TIM_Module* TIMx, uint16_t TIM_OCClear);
+void TIM_ConfigOc1Polarity(TIM_Module* TIMx, uint16_t OcPolarity);
+void TIM_ConfigOc1NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity);
+void TIM_ConfigOc2Polarity(TIM_Module* TIMx, uint16_t OcPolarity);
+void TIM_ConfigOc2NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity);
+void TIM_ConfigOc3Polarity(TIM_Module* TIMx, uint16_t OcPolarity);
+void TIM_ConfigOc3NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity);
+void TIM_ConfigOc4Polarity(TIM_Module* TIMx, uint16_t OcPolarity);
+void TIM_ConfigOc5Polarity(TIM_Module* TIMx, uint16_t OcPolarity);
+void TIM_ConfigOc6Polarity(TIM_Module* TIMx, uint16_t OcPolarity);
+void TIM_EnableCapCmpCh(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCx);
+void TIM_EnableCapCmpChN(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCxN);
+void TIM_SelectOcMode(TIM_Module* TIMx, uint16_t Channel, uint16_t OcMode);
+void TIM_EnableUpdateEvt(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_ConfigUpdateRequestIntSrc(TIM_Module* TIMx, uint16_t TIM_UpdateSource);
+void TIM_SelectHallSensor(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_SelectOnePulseMode(TIM_Module* TIMx, uint16_t TIM_OPMode);
+void TIM_SelectOutputTrig(TIM_Module* TIMx, uint16_t TIM_TRGOSource);
+void TIM_SelectSlaveMode(TIM_Module* TIMx, uint16_t TIM_SlaveMode);
+void TIM_SelectMasterSlaveMode(TIM_Module* TIMx, uint16_t TIM_MasterSlaveMode);
+void TIM_SetCnt(TIM_Module* TIMx, uint16_t Counter);
+void TIM_SetAutoReload(TIM_Module* TIMx, uint16_t Autoreload);
+void TIM_SetCmp1(TIM_Module* TIMx, uint16_t Compare1);
+void TIM_SetCmp2(TIM_Module* TIMx, uint16_t Compare2);
+void TIM_SetCmp3(TIM_Module* TIMx, uint16_t Compare3);
+void TIM_SetCmp4(TIM_Module* TIMx, uint16_t Compare4);
+void TIM_SetCmp5(TIM_Module* TIMx, uint16_t Compare5);
+void TIM_SetCmp6(TIM_Module* TIMx, uint16_t Compare6);
+void TIM_SetInCap1Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetInCap2Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetInCap3Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetInCap4Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetClkDiv(TIM_Module* TIMx, uint16_t TIM_CKD);
+uint16_t TIM_GetCap1(TIM_Module* TIMx);
+uint16_t TIM_GetCap2(TIM_Module* TIMx);
+uint16_t TIM_GetCap3(TIM_Module* TIMx);
+uint16_t TIM_GetCap4(TIM_Module* TIMx);
+uint16_t TIM_GetCap5(TIM_Module* TIMx);
+uint16_t TIM_GetCap6(TIM_Module* TIMx);
+uint16_t TIM_GetCnt(TIM_Module* TIMx);
+uint16_t TIM_GetPrescaler(TIM_Module* TIMx);
+uint16_t TIM_GetAutoReload(TIM_Module* TIMx);
+FlagStatus TIM_GetCCENStatus(TIM_Module* TIMx, uint32_t TIM_CCEN);
+FlagStatus TIM_GetFlagStatus(TIM_Module* TIMx, uint32_t TIM_FLAG);
+void TIM_ClearFlag(TIM_Module* TIMx, uint32_t TIM_FLAG);
+INTStatus TIM_GetIntStatus(TIM_Module* TIMx, uint32_t TIM_IT);
+void TIM_ClrIntPendingBit(TIM_Module* TIMx, uint32_t TIM_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32L40X_TIM_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_tsc.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_tsc.h
new file mode 100644
index 0000000000..59ef6b403f
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_tsc.h
@@ -0,0 +1,483 @@
+/*****************************************************************************
+* Copyright (c) 2022, Nations Technologies Inc.
+*
+* All rights reserved.
+* ****************************************************************************
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* - Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the disclaimer below.
+*
+* Nations' name may not be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ****************************************************************************/
+
+/**
+ * @file n32l40x_tsc.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L40X_TSC_H__
+#define __N32L40X_TSC_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "n32l40x.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup TSC
+ * @{
+ */
+
+/**
+ * @brief TSC error code
+ */
+ typedef enum {
+ TSC_ERROR_OK = 0x00U, /*!< No error */
+ TSC_ERROR_CLOCK = 0x01U, /*!< clock config error */
+ TSC_ERROR_PARAMETER = 0x02U, /*!< parameter error */
+ TSC_ERROR_HW_MODE = 0x03U, /*!< Exit hw mode timeout */
+
+ }TSC_ErrorTypeDef;
+ /**
+ * @
+ */
+
+/**
+ * @brief TSC clock source
+ */
+#define TSC_CLK_SRC_LSI (RCC_LSXCLK_SRC_LSI) /*!< LSI*/
+#define TSC_CLK_SRC_LSE (RCC_LSE_ENABLE|RCC_LSXCLK_SRC_LSE) /*!< LSE */
+#define TSC_CLK_SRC_LSE_BYPASS (RCC_LSE_BYPASS|RCC_LSXCLK_SRC_LSE) /*!< LSE bypass */
+/**
+ * @
+ */
+
+
+/**
+ * @defgroup Detect_Period
+ */
+#define TSC_DET_PERIOD_8 (0x00000000U) /*!< DET_PERIOD[3:0] = 8/TSC_CLOCK */
+#define TSC_DET_PERIOD_16 (0x01UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000001U DET_PERIOD[3:0] = 16/TSC_CLOCK */
+#define TSC_DET_PERIOD_24 (0x02UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000002U DET_PERIOD[3:0] = 24/TSC_CLOCK */
+#define TSC_DET_PERIOD_32 (0x03UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000003U DET_PERIOD[3:0] = 32/TSC_CLOCK(default) */
+#define TSC_DET_PERIOD_40 (0x04UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000004U DET_PERIOD[3:0] = 40/TSC_CLOCK */
+#define TSC_DET_PERIOD_48 (0x05UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000005U DET_PERIOD[3:0] = 48/TSC_CLOCK */
+#define TSC_DET_PERIOD_56 (0x06UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000006U DET_PERIOD[3:0] = 56/TSC_CLOCK */
+#define TSC_DET_PERIOD_64 (0x07UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000007U DET_PERIOD[3:0] = 64/TSC_CLOCK */
+#define TSC_DET_PERIOD_72 (0x08UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000008U DET_PERIOD[3:0] = 72/TSC_CLOCK */
+#define TSC_DET_PERIOD_80 (0x09UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000009U DET_PERIOD[3:0] = 80/TSC_CLOCK */
+#define TSC_DET_PERIOD_88 (0x0AUL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x0000000AU DET_PERIOD[3:0] = 88/TSC_CLOCK */
+#define TSC_DET_PERIOD_96 (0x0BUL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x0000000BU DET_PERIOD[3:0] = 96/TSC_CLOCK */
+#define TSC_DET_PERIOD_104 (0x0CUL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x0000000CU DET_PERIOD[3:0] = 104/TSC_CLOCK */
+/**
+ * @
+ */
+
+/**
+ * @defgroup Detect_Filter
+ */
+#define TSC_DET_FILTER_1 (0x00000000U) /*!< DET_FILTER[3:0] = 1 sample */
+#define TSC_DET_FILTER_2 (0x01UL << TSC_CTRL_DET_FILTER_Pos) /*!< 0x00000010U DET_FILTER[3:0] = 2 samples */
+#define TSC_DET_FILTER_3 (0x02UL << TSC_CTRL_DET_FILTER_Pos) /*!< 0x00000020U DET_FILTER[3:0] = 3 samples */
+#define TSC_DET_FILTER_4 (0x03UL << TSC_CTRL_DET_FILTER_Pos) /*!< 0x00000030U DET_FILTER[3:0] = 4 samples */
+/**
+ * @
+ */
+
+/**
+ * @defgroup HW_Detect_Mode
+ */
+#define TSC_HW_DET_MODE_DISABLE (0x00000000U) /*!< Hardware detect mode disable */
+#define TSC_HW_DET_MODE_ENABLE (0x01UL << TSC_CTRL_HW_DET_MODE_Pos) /*!< 0x00000040U Hardware detect mode enable */
+/**
+ * @
+ */
+
+/**
+ * @defgroup Detect_Type
+ */
+#define TSC_DET_TYPE_Msk (TSC_CTRL_LESS_DET_SEL_Msk|TSC_CTRL_GREAT_DET_SEL_Msk)
+#define TSC_DET_TYPE_Pos (TSC_CTRL_LESS_DET_SEL_Pos)
+
+#define TSC_DET_TYPE_NONE (0UL) /*!< 0x00000000U Disable detect */
+#define TSC_DET_TYPE_LESS (0x01UL << TSC_DET_TYPE_Pos) /*!< 0x00000100U Less detect enable */
+#define TSC_DET_TYPE_GREAT (0x02UL << TSC_DET_TYPE_Pos) /*!< 0x00000200U Great detect enable */
+#define TSC_DET_TYPE_PERIOD (0x03UL << TSC_DET_TYPE_Pos) /*!< 0x00000300U Both great and less detct enable */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_Interrupt
+ */
+#define TSC_IT_DET_ENABLE (TSC_CTRL_DET_INTEN) /*!< Enable TSC detect interrupt */
+#define TSC_IT_DET_DISABLE (0UL) /*!< Disable TSC detect interrupt */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_Out
+ */
+#define TSC_OUT_PIN (0x00000000U) /*!< TSC output to TSC_OUT pin */
+#define TSC_OUT_TIM4_ETR (0x1UL << TSC_CTRL_TM4_ETR_Pos) /*!< TSC output to TIM4 ETR */
+#define TSC_OUT_TIM2_ETR (0x2UL << TSC_CTRL_TM4_ETR_Pos) /*!< TSC output to TIM2 ETR and TIM2 CH1*/
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_Flag
+ */
+#define TSC_FLAG_HW (0x1UL << TSC_CTRL_HW_DET_ST_Pos) /*!< Flag of hardware detect mode */
+
+#define TSC_FLAG_GREAT_DET (0x1UL << TSC_STS_GREAT_DET_Pos) /*!< Flag of great detect type */
+#define TSC_FLAG_LESS_DET (0x1UL << TSC_STS_LESS_DET_Pos) /*!< Flag of less detect type */
+#define TSC_FLAG_PERIOD_DET (TSC_FLAG_GREAT_DET|TSC_FLAG_LESS_DET) /*!< Flag of period detect type */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_SW_Detect
+ */
+#define TSC_SW_MODE_DISABLE (0x00000000U) /*!< Disable software detect mode */
+#define TSC_SW_MODE_ENABLE (0x1UL << TSC_ANA_CTRL_SW_TSC_EN_Pos) /*!< Enable software detect mode */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_PadOption
+ */
+#define TSC_PAD_INTERNAL_RES (0x00000000U) /*!< Use internal resistor */
+#define TSC_PAD_EXTERNAL_RES (0x1UL << TSC_ANA_SEL_PAD_OPT_Pos) /*!< Use external resistor */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_PadSpeed
+ */
+#define TSC_PAD_SPEED_0 (0x00000000U) /*!< Low speed,about 100K */
+#define TSC_PAD_SPEED_1 (0x1UL << TSC_ANA_SEL_SP_OPT_Pos) /*!< Middle spped */
+#define TSC_PAD_SPEED_2 (0x2UL << TSC_ANA_SEL_SP_OPT_Pos) /*!< Middle spped */
+#define TSC_PAD_SPEED_3 (0x3UL << TSC_ANA_SEL_SP_OPT_Pos) /*!< Middle spped */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_Constant
+ */
+#define TSC_CHN_SEL_ALL (TSC_CHNEN_CHN_SELx_Msk)
+#define MAX_TSC_HW_CHN (24) /*Maximum number of tsc pin*/
+#define MAX_TSC_THRESHOLD_BASE (2047) /*Maximum detect base value of threshold*/
+#define MAX_TSC_THRESHOLD_DELTA (255) /*Maximum detect delta value of threshold*/
+#define TSC_TIMEOUT (0x01000000) /*TSC normal timeout */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_DetectMode
+ */
+#define TSC_HW_DETECT_MODE (0x00000001U) /*TSC hardware detect mode*/
+#define TSC_SW_DETECT_MODE (0x00000000U) /*TSC software detect mode*/
+/**
+ * @
+ */
+
+/* TSC Exported macros -----------------------------------------------------------*/
+/** @defgroup TSC_Exported_Macros
+ * @{
+ */
+
+/** @brief Enable the TSC HW detect mode
+ * @param None
+ * @retval None
+ */
+#define __TSC_HW_ENABLE() SET_BIT(TSC->CTRL, TSC_HW_DET_MODE_ENABLE)
+
+/** @brief Disable the TSC HW detect mode
+ * @param None
+ * @retval None
+ */
+#define __TSC_HW_DISABLE() CLEAR_BIT(TSC->CTRL, TSC_HW_DET_MODE_ENABLE)
+
+/** @brief Config TSC detect period for HW detect mode
+ * @param __PERIOD__ specifies the TSC detect period during HW detect mode
+ * @arg TSC_DET_PERIOD_8: Detect period = 8/TSC_CLK
+ * @arg TSC_DET_PERIOD_16: Detect Period = 1/TSC_CLK
+ * @arg TSC_DET_PERIOD_24: Detect Period = 2/TSC_CLK
+ * @arg TSC_DET_PERIOD_32: Detect Period = 3/TSC_CLK
+ * @arg TSC_DET_PERIOD_40: Detect Period = 4/TSC_CLK
+ * @arg TSC_DET_PERIOD_48: Detect Period = 5/TSC_CLK
+ * @arg TSC_DET_PERIOD_56: Detect Period = 6/TSC_CLK
+ * @arg TSC_DET_PERIOD_64: Detect Period = 7/TSC_CLK
+ * @arg TSC_DET_PERIOD_72: Detect Period = 7/TSC_CLK
+ * @arg TSC_DET_PERIOD_80: Detect Period = 7/TSC_CLK
+ * @arg TSC_DET_PERIOD_88: Detect Period = 7/TSC_CLK
+ * @arg TSC_DET_PERIOD_96: Detect Period = 7/TSC_CLK
+ * @arg TSC_DET_PERIOD_104:Detect Period = 7/TSC_CLK
+ * @retval None
+ */
+#define __TSC_PERIOD_CONFIG(__PERIOD__) MODIFY_REG(TSC->CTRL, TSC_CTRL_DET_PERIOD_Msk,__PERIOD__)
+
+/** @brief Config TSC detect filter for HW detect mode
+ * @param __FILTER__ specifies the least usefull continuous samples during HW detect mode
+ * @arg TSC_DET_FILTER_1: Detect filter = 1 pulse
+ * @arg TSC_DET_FILTER_2: Detect filter = 2 pulse
+ * @arg TSC_DET_FILTER_3: Detect filter = 3 pulse
+ * @arg TSC_DET_FILTER_4: Detect filter = 4 pulse
+ * @retval None
+ */
+#define __TSC_FILTER_CONFIG(__FILTER__) MODIFY_REG(TSC->CTRL, TSC_CTRL_DET_FILTER_Msk,__FILTER__)
+
+/** @brief Config TSC detect type for HW detect mode,less great or both
+ * @param __TYPE__ specifies the detect type of a sample during HW detect mode
+ * @arg TSC_DET_TYPE_NONE: Detect disable
+ * @arg TSC_DET_TYPE_LESS: Pulse number must be greater than the threshold(basee-delta) during a sample time
+ * @arg TSC_DET_TYPE_GREAT: Pulse number must be less than the threshold(basee+delta) during a sample time
+ * @arg TSC_DET_TYPE_PERIOD:Pulse number must be greater than (basee-delta)
+ and also be less than (basee+delta) during a sample time
+ * @retval None
+ */
+#define __TSC_LESS_GREAT_CONFIG(__TYPE__) MODIFY_REG(TSC->CTRL, \
+ (TSC_CTRL_LESS_DET_SEL_Msk|TSC_CTRL_GREAT_DET_SEL_Msk), \
+ __TYPE__)
+
+/** @brief Enable TSC interrupt
+ * @param None
+ * @retval None
+ */
+#define __TSC_INT_ENABLE() SET_BIT(TSC->CTRL, TSC_IT_DET_ENABLE)
+
+/** @brief Disable TSC interrupt
+ * @param None
+ * @retval None
+ */
+#define __TSC_INT_DISABLE() CLEAR_BIT(TSC->CTRL, TSC_IT_DET_ENABLE)
+
+/** @brief Config the TSC output
+ * @param __OUT__ specifies where the TSC output should go
+ * @arg TSC_OUT_PIN: TSC output to the TSC_OUT pin
+ * @arg TSC_OUT_TIM4_ETR: TSC output to TIM4 as ETR
+ * @arg TSC_OUT_TIM2_ETR: TSC output to TIM2 as ETR
+ * @retval None
+ */
+#define __TSC_OUT_CONFIG(__OUT__) MODIFY_REG( TSC->CTRL, \
+ (TSC_CTRL_TM4_ETR_Msk|TSC_CTRL_TM2_ETR_CH1_Msk),\
+ __OUT__)
+
+/** @brief Config the TSC channel
+ * @param __CHN__ specifies the pin of channels used for detect
+ * This parameter:bit[0:23] used,bit[24:31] must be 0
+ * bitx: TSC channel x
+ * @retval None
+ */
+#define __TSC_CHN_CONFIG(__CHN__) WRITE_REG(TSC->CHNEN, __CHN__)
+
+/** @brief Enable the TSC SW detect mode
+ * @param None
+ * @retval None
+ */
+#define __TSC_SW_ENABLE() SET_BIT(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_TSC_EN)
+
+/** @brief Disable the TSC SW detect mode
+ * @param None
+ * @retval None
+ */
+#define __TSC_SW_DISABLE() CLEAR_BIT(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_TSC_EN)
+
+/** @brief Config the detect channel number during SW detect mode
+ * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN
+ * @retval None
+ */
+#define __TSC_SW_CHN_NUM_CONFIG(__NUM__) MODIFY_REG(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_PAD_MUX_Msk,__NUM__)
+
+/** @brief Config the pad charge type
+ * @param __OPT__ specifies which resistor is used for charge
+ * @arg TSC_PAD_INTERNAL_RES: Internal resistor is used
+ * @arg TSC_PAD_EXTERNAL_RES: External resistor is used
+ * @retval None
+ */
+#define __TSC_PAD_OPT_CONFIG(__OPT__) MODIFY_REG(TSC->ANA_SEL, TSC_ANA_SEL_PAD_OPT_Msk,__OPT__)
+
+/** @brief Config TSC speed
+ * @param __SPEED__ specifies the TSC speed range
+ * @arg TSC_PAD_SPEED_0: Low speed
+ * @arg TSC_PAD_SPEED_1: Middle speed
+ * @arg TSC_PAD_SPEED_2: Middle speed
+ * @arg TSC_PAD_SPEED_3: High speed
+ * @retval None
+ */
+#define __TSC_PAD_SPEED_CONFIG(__SPEED__) MODIFY_REG(TSC->ANA_SEL, TSC_ANA_SEL_SP_OPT_Msk,__SPEED__)
+
+
+/** @brief Check if the HW detect mode is enable
+ * @param None
+ * @retval Current state of HW detect mode
+ */
+#define __TSC_GET_HW_MODE() (((TSC->CTRL) & TSC_FLAG_HW) == (TSC_FLAG_HW))
+
+/** @brief Check the detect type during HW detect mode
+ * @param __FLAG__ specifies the flag of detect type
+ * @arg TSC_FLAG_LESS_DET: Flag of less detect type
+ * @arg TSC_FLAG_GREAT_DET: Flag of great detect type
+ * @arg TSC_FLAG_PERIOD_DET: Flag of priod detect type
+ * @retval Current state of flag
+ */
+#define __TSC_GET_HW_DET_TYPE(__FLAG__) (((TSC->STS) & (__FLAG__))==(__FLAG__))
+
+/** @brief Get the number of channel which is detected now
+ * @param None
+ * @retval Current channel number
+ */
+#define __TSC_GET_CHN_NUMBER() (((TSC->STS) & TSC_STS_CHN_NUM_Msk) >> TSC_STS_CHN_NUM_Pos )
+
+/** @brief Get the count value of pulse
+ * @param None
+ * @retval Pulse count of current channel
+ */
+#define __TSC_GET_CHN_CNT() (((TSC->STS) & TSC_STS_CNT_VAL_Msk ) >> TSC_STS_CNT_VAL_Pos )
+
+/** @brief Get the base value of one channel
+ * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN
+ * @retval base value of the channel
+ */
+#define __TSC_GET_CHN_BASE(__NUM__) ((TSC->THRHD[(__NUM__)] & TSC_THRHDx_BASE_Msk ) >> TSC_THRHDx_BASE_Pos)
+
+/** @brief Get the delta value of one channel
+ * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN
+ * @retval delta value of the channel
+ */
+#define __TSC_GET_CHN_DELTA(__NUM__) ((TSC->THRHD[(__NUM__)] & TSC_THRHDx_DELTA_Msk ) >> TSC_THRHDx_DELTA_Pos )
+
+/** @brief Get the internal resist value of one channel
+ * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN
+ * @retval resist value of the channel
+ */
+#define __TSC_GET_CHN_RESIST(__NUM__) ((TSC->RESR[(__NUM__)>>3] >>(((__NUM__) & 0x7UL)*4)) & TSC_RESRx_CHN_RESIST_Msk)
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TSC_Private_Macros
+ * @{
+ */
+#define IS_TSC_DET_PERIOD(_PERIOD_) \
+ (((_PERIOD_)==TSC_DET_PERIOD_8) ||((_PERIOD_)==TSC_DET_PERIOD_16)||((_PERIOD_)==TSC_DET_PERIOD_24) \
+ ||((_PERIOD_)==TSC_DET_PERIOD_32)||((_PERIOD_)==TSC_DET_PERIOD_40)||((_PERIOD_)==TSC_DET_PERIOD_48) \
+ ||((_PERIOD_)==TSC_DET_PERIOD_56)||((_PERIOD_)==TSC_DET_PERIOD_64)||((_PERIOD_)==TSC_DET_PERIOD_72) \
+ ||((_PERIOD_)==TSC_DET_PERIOD_80)||((_PERIOD_)==TSC_DET_PERIOD_88)||((_PERIOD_)==TSC_DET_PERIOD_96) \
+ ||((_PERIOD_)==TSC_DET_PERIOD_104) )
+
+#define IS_TSC_FILTER(_FILTER_) \
+ ( ((_FILTER_)==TSC_DET_FILTER_1) ||((_FILTER_)==TSC_DET_FILTER_2)\
+ ||((_FILTER_)==TSC_DET_FILTER_3) ||((_FILTER_)==TSC_DET_FILTER_4) )
+
+#define IS_TSC_DET_MODE(_MODE_) \
+ ( ((_MODE_)==TSC_HW_DETECT_MODE) ||((_MODE_)==TSC_SW_DETECT_MODE) )
+
+#define IS_TSC_DET_TYPE(_TYPE_) \
+ ( ((_TYPE_)==TSC_DET_TYPE_GREAT) ||((_TYPE_)==TSC_DET_TYPE_LESS) \
+ ||((_TYPE_)==TSC_DET_TYPE_PERIOD)|| ((_TYPE_)==TSC_DET_TYPE_NONE) )
+
+#define IS_TSC_INT(_INT_) (((_INT_)==TSC_IT_DET_ENABLE)||((_INT_)==TSC_IT_DET_DISABLE))
+
+#define IS_TSC_OUT(_ETR_) (((_ETR_)==TSC_OUT_PIN)||((_ETR_)==TSC_OUT_TIM2_ETR)||((_ETR_)==TSC_OUT_TIM4_ETR))
+
+#define IS_TSC_CHN(_CHN_) (0==((_CHN_)&(~TSC_CHNEN_CHN_SELx_Msk)))
+
+#define IS_TSC_CHN_NUMBER(_NUM_) ((uint32_t)(_NUM_)BaudRate)))
+ - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
+
+ uint16_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref USART_Word_Length */
+
+ uint16_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref USART_Stop_Bits */
+
+ uint16_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint16_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref Mode */
+
+ uint16_t HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
+ or disabled.
+ This parameter can be a value of @ref USART_Hardware_Flow_Control */
+} USART_InitType;
+
+/**
+ * @brief USART Clock Init Structure definition
+ */
+
+typedef struct
+{
+ uint16_t Clock; /*!< Specifies whether the USART clock is enabled or disabled.
+ This parameter can be a value of @ref Clock */
+
+ uint16_t Polarity; /*!< Specifies the steady state value of the serial clock.
+ This parameter can be a value of @ref USART_Clock_Polarity */
+
+ uint16_t Phase; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref USART_Clock_Phase */
+
+ uint16_t LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref USART_Last_Bit */
+} USART_ClockInitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Exported_Constants
+ * @{
+ */
+
+#define IS_USART_ALL_PERIPH(PERIPH) \
+ (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3) || ((PERIPH) == UART4) || ((PERIPH) == UART5))
+
+#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3))
+
+#define IS_USART_1234_PERIPH(PERIPH) \
+ (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3) || ((PERIPH) == UART4))
+/** @addtogroup USART_Word_Length
+ * @{
+ */
+
+#define USART_WL_8B ((uint16_t)0x0000)
+#define USART_WL_9B ((uint16_t)0x1000)
+
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WL_8B) || ((LENGTH) == USART_WL_9B))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Stop_Bits
+ * @{
+ */
+
+#define USART_STPB_1 ((uint16_t)0x0000)
+#define USART_STPB_0_5 ((uint16_t)0x1000)
+#define USART_STPB_2 ((uint16_t)0x2000)
+#define USART_STPB_1_5 ((uint16_t)0x3000)
+#define IS_USART_STOPBITS(STOPBITS) \
+ (((STOPBITS) == USART_STPB_1) || ((STOPBITS) == USART_STPB_0_5) || ((STOPBITS) == USART_STPB_2) \
+ || ((STOPBITS) == USART_STPB_1_5))
+/**
+ * @}
+ */
+
+/** @addtogroup Parity
+ * @{
+ */
+
+#define USART_PE_NO ((uint16_t)0x0000)
+#define USART_PE_EVEN ((uint16_t)0x0400)
+#define USART_PE_ODD ((uint16_t)0x0600)
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PE_NO) || ((PARITY) == USART_PE_EVEN) || ((PARITY) == USART_PE_ODD))
+/**
+ * @}
+ */
+
+/** @addtogroup Mode
+ * @{
+ */
+
+#define USART_MODE_RX ((uint16_t)0x0004)
+#define USART_MODE_TX ((uint16_t)0x0008)
+#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Hardware_Flow_Control
+ * @{
+ */
+#define USART_HFCTRL_NONE ((uint16_t)0x0000)
+#define USART_HFCTRL_RTS ((uint16_t)0x0100)
+#define USART_HFCTRL_CTS ((uint16_t)0x0200)
+#define USART_HFCTRL_RTS_CTS ((uint16_t)0x0300)
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL) \
+ (((CONTROL) == USART_HFCTRL_NONE) || ((CONTROL) == USART_HFCTRL_RTS) || ((CONTROL) == USART_HFCTRL_CTS) \
+ || ((CONTROL) == USART_HFCTRL_RTS_CTS))
+/**
+ * @}
+ */
+
+/** @addtogroup Clock
+ * @{
+ */
+#define USART_CLK_DISABLE ((uint16_t)0x0000)
+#define USART_CLK_ENABLE ((uint16_t)0x0800)
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLK_DISABLE) || ((CLOCK) == USART_CLK_ENABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Clock_Polarity
+ * @{
+ */
+
+#define USART_CLKPOL_LOW ((uint16_t)0x0000)
+#define USART_CLKPOL_HIGH ((uint16_t)0x0400)
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CLKPOL_LOW) || ((CPOL) == USART_CLKPOL_HIGH))
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Clock_Phase
+ * @{
+ */
+
+#define USART_CLKPHA_1EDGE ((uint16_t)0x0000)
+#define USART_CLKPHA_2EDGE ((uint16_t)0x0200)
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CLKPHA_1EDGE) || ((CPHA) == USART_CLKPHA_2EDGE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Last_Bit
+ * @{
+ */
+
+#define USART_CLKLB_DISABLE ((uint16_t)0x0000)
+#define USART_CLKLB_ENABLE ((uint16_t)0x0100)
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_CLKLB_DISABLE) || ((LASTBIT) == USART_CLKLB_ENABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Interrupt_definition
+ * @{
+ */
+
+#define USART_INT_PEF ((uint16_t)0x0028)
+#define USART_INT_TXDE ((uint16_t)0x0727)
+#define USART_INT_TXC ((uint16_t)0x0626)
+#define USART_INT_RXDNE ((uint16_t)0x0525)
+#define USART_INT_IDLEF ((uint16_t)0x0424)
+#define USART_INT_LINBD ((uint16_t)0x0846)
+#define USART_INT_CTSF ((uint16_t)0x096A)
+#define USART_INT_ERRF ((uint16_t)0x0060)
+#define USART_INT_OREF ((uint16_t)0x0360)
+#define USART_INT_NEF ((uint16_t)0x0260)
+#define USART_INT_FEF ((uint16_t)0x0160)
+#define IS_USART_CFG_INT(IT) \
+ (((IT) == USART_INT_PEF) || ((IT) == USART_INT_TXDE) || ((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE) \
+ || ((IT) == USART_INT_IDLEF) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF) \
+ || ((IT) == USART_INT_ERRF))
+#define IS_USART_GET_INT(IT) \
+ (((IT) == USART_INT_PEF) || ((IT) == USART_INT_TXDE) || ((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE) \
+ || ((IT) == USART_INT_IDLEF) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF) || ((IT) == USART_INT_OREF) \
+ || ((IT) == USART_INT_NEF) || ((IT) == USART_INT_FEF))
+#define IS_USART_CLR_INT(IT) \
+ (((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_DMA_Requests
+ * @{
+ */
+
+#define USART_DMAREQ_TX ((uint16_t)0x0080)
+#define USART_DMAREQ_RX ((uint16_t)0x0040)
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_WakeUp_methods
+ * @{
+ */
+
+#define USART_WUM_IDLELINE ((uint16_t)0x0000)
+#define USART_WUM_ADDRMASK ((uint16_t)0x0800)
+#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WUM_IDLELINE) || ((WAKEUP) == USART_WUM_ADDRMASK))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_LIN_Break_Detection_Length
+ * @{
+ */
+
+#define USART_LINBDL_10B ((uint16_t)0x0000)
+#define USART_LINBDL_11B ((uint16_t)0x0020)
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == USART_LINBDL_10B) || ((LENGTH) == USART_LINBDL_11B))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_IrDA_Low_Power
+ * @{
+ */
+
+#define USART_IRDAMODE_LOWPPWER ((uint16_t)0x0004)
+#define USART_IRDAMODE_NORMAL ((uint16_t)0x0000)
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IRDAMODE_LOWPPWER) || ((MODE) == USART_IRDAMODE_NORMAL))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Flags
+ * @{
+ */
+
+#define USART_FLAG_CTSF ((uint16_t)0x0200)
+#define USART_FLAG_LINBD ((uint16_t)0x0100)
+#define USART_FLAG_TXDE ((uint16_t)0x0080)
+#define USART_FLAG_TXC ((uint16_t)0x0040)
+#define USART_FLAG_RXDNE ((uint16_t)0x0020)
+#define USART_FLAG_IDLEF ((uint16_t)0x0010)
+#define USART_FLAG_OREF ((uint16_t)0x0008)
+#define USART_FLAG_NEF ((uint16_t)0x0004)
+#define USART_FLAG_FEF ((uint16_t)0x0002)
+#define USART_FLAG_PEF ((uint16_t)0x0001)
+#define IS_USART_FLAG(FLAG) \
+ (((FLAG) == USART_FLAG_PEF) || ((FLAG) == USART_FLAG_TXDE) || ((FLAG) == USART_FLAG_TXC) \
+ || ((FLAG) == USART_FLAG_RXDNE) || ((FLAG) == USART_FLAG_IDLEF) || ((FLAG) == USART_FLAG_LINBD) \
+ || ((FLAG) == USART_FLAG_CTSF) || ((FLAG) == USART_FLAG_OREF) || ((FLAG) == USART_FLAG_NEF) \
+ || ((FLAG) == USART_FLAG_FEF))
+
+#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
+#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) \
+ ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) && ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \
+ || ((USART_FLAG) != USART_FLAG_CTSF))
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x00337F99))
+#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
+#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Exported_Functions
+ * @{
+ */
+
+void USART_DeInit(USART_Module* USARTx);
+void USART_Init(USART_Module* USARTx, USART_InitType* USART_InitStruct);
+void USART_StructInit(USART_InitType* USART_InitStruct);
+void USART_ClockInit(USART_Module* USARTx, USART_ClockInitType* USART_ClockInitStruct);
+void USART_ClockStructInit(USART_ClockInitType* USART_ClockInitStruct);
+void USART_Enable(USART_Module* USARTx, FunctionalState Cmd);
+void USART_ConfigInt(USART_Module* USARTx, uint16_t USART_INT, FunctionalState Cmd);
+void USART_EnableDMA(USART_Module* USARTx, uint16_t USART_DMAReq, FunctionalState Cmd);
+void USART_SetAddr(USART_Module* USARTx, uint8_t USART_Addr);
+void USART_ConfigWakeUpMode(USART_Module* USARTx, uint16_t USART_WakeUpMode);
+void USART_EnableRcvWakeUp(USART_Module* USARTx, FunctionalState Cmd);
+void USART_ConfigLINBreakDetectLength(USART_Module* USARTx, uint16_t USART_LINBreakDetectLength);
+void USART_EnableLIN(USART_Module* USARTx, FunctionalState Cmd);
+void USART_SendData(USART_Module* USARTx, uint16_t Data);
+uint16_t USART_ReceiveData(USART_Module* USARTx);
+void USART_SendBreak(USART_Module* USARTx);
+void USART_SetGuardTime(USART_Module* USARTx, uint8_t USART_GuardTime);
+void USART_SetPrescaler(USART_Module* USARTx, uint8_t USART_Prescaler);
+void USART_EnableSmartCard(USART_Module* USARTx, FunctionalState Cmd);
+void USART_SetSmartCardNACK(USART_Module* USARTx, FunctionalState Cmd);
+void USART_EnableHalfDuplex(USART_Module* USARTx, FunctionalState Cmd);
+void USART_ConfigIrDAMode(USART_Module* USARTx, uint16_t USART_IrDAMode);
+void USART_EnableIrDA(USART_Module* USARTx, FunctionalState Cmd);
+FlagStatus USART_GetFlagStatus(USART_Module* USARTx, uint16_t USART_FLAG);
+void USART_ClrFlag(USART_Module* USARTx, uint16_t USART_FLAG);
+INTStatus USART_GetIntStatus(USART_Module* USARTx, uint16_t USART_INT);
+void USART_ClrIntPendingBit(USART_Module* USARTx, uint16_t USART_INT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32L40X_USART_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_wwdg.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_wwdg.h
new file mode 100644
index 0000000000..ca107fa1f5
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_wwdg.h
@@ -0,0 +1,122 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_wwdg.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L40X_WWDG_H__
+#define __N32L40X_WWDG_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l40x.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup WWDG
+ * @{
+ */
+
+/** @addtogroup WWDG_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup WWDG_Prescaler
+ * @{
+ */
+
+#define WWDG_PRESCALER_DIV1 ((uint32_t)0x00000000)
+#define WWDG_PRESCALER_DIV2 ((uint32_t)0x00000080)
+#define WWDG_PRESCALER_DIV4 ((uint32_t)0x00000100)
+#define WWDG_PRESCALER_DIV8 ((uint32_t)0x00000180)
+#define IS_WWDG_PRESCALER_DIV(PRESCALER) \
+ (((PRESCALER) == WWDG_PRESCALER_DIV1) || ((PRESCALER) == WWDG_PRESCALER_DIV2) \
+ || ((PRESCALER) == WWDG_PRESCALER_DIV4) || ((PRESCALER) == WWDG_PRESCALER_DIV8))
+#define IS_WWDG_WVALUE(VALUE) ((VALUE) <= 0x7F)
+#define IS_WWDG_CNT(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Exported_Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Exported_Functions
+ * @{
+ */
+
+void WWDG_DeInit(void);
+void WWDG_SetPrescalerDiv(uint32_t WWDG_Prescaler);
+void WWDG_SetWValue(uint8_t WindowValue);
+void WWDG_EnableInt(void);
+void WWDG_SetCnt(uint8_t Counter);
+void WWDG_Enable(uint8_t Counter);
+FlagStatus WWDG_GetEWINTF(void);
+void WWDG_ClrEWINTF(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32L40X__WWDG_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/misc.c b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/misc.c
new file mode 100644
index 0000000000..9eb36283ee
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/misc.c
@@ -0,0 +1,229 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file misc.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "misc.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup MISC
+ * @brief MISC driver modules
+ * @{
+ */
+
+/** @addtogroup MISC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Private_Defines
+ * @{
+ */
+
+#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Configures the priority grouping: pre-emption priority and subpriority.
+ * @param NVIC_PriorityGroup specifies the priority grouping bits length.
+ * This parameter can be one of the following values:
+ * @arg NVIC_PriorityGroup_0 0 bits for pre-emption priority
+ * 4 bits for subpriority
+ * @arg NVIC_PriorityGroup_1 1 bits for pre-emption priority
+ * 3 bits for subpriority
+ * @arg NVIC_PriorityGroup_2 2 bits for pre-emption priority
+ * 2 bits for subpriority
+ * @arg NVIC_PriorityGroup_3 3 bits for pre-emption priority
+ * 1 bits for subpriority
+ * @arg NVIC_PriorityGroup_4 4 bits for pre-emption priority
+ * 0 bits for subpriority
+ */
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
+
+ /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
+ SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
+}
+
+/**
+ * @brief Initializes the NVIC peripheral according to the specified
+ * parameters in the NVIC_InitStruct.
+ * @param NVIC_InitStruct pointer to a NVIC_InitType structure that contains
+ * the configuration information for the specified NVIC peripheral.
+ */
+void NVIC_Init(NVIC_InitType* NVIC_InitStruct)
+{
+ uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
+
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
+ assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
+
+ if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+ {
+ /* Compute the Corresponding IRQ Priority --------------------------------*/
+ tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700)) >> 0x08;
+ tmppre = (0x4 - tmppriority);
+ tmpsub = tmpsub >> tmppriority;
+
+ tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
+ tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
+ tmppriority = tmppriority << 0x04;
+
+ NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
+
+ /* Enable the Selected IRQ Channels --------------------------------------*/
+ NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = (uint32_t)0x01
+ << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+ }
+ else
+ {
+ /* Disable the Selected IRQ Channels -------------------------------------*/
+ NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = (uint32_t)0x01
+ << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+ }
+}
+
+/**
+ * @brief Sets the vector table location and Offset.
+ * @param NVIC_VectTab specifies if the vector table is in RAM or FLASH memory.
+ * This parameter can be one of the following values:
+ * @arg NVIC_VectTab_RAM
+ * @arg NVIC_VectTab_FLASH
+ * @param Offset Vector Table base offset field. This value must be a multiple
+ * of 0x200.
+ */
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
+ assert_param(IS_NVIC_OFFSET(Offset));
+
+ SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
+}
+
+/**
+ * @brief Selects the condition for the system to enter low power mode.
+ * @param LowPowerMode Specifies the new mode for the system to enter low power mode.
+ * This parameter can be one of the following values:
+ * @arg NVIC_LP_SEVONPEND
+ * @arg NVIC_LP_SLEEPDEEP
+ * @arg NVIC_LP_SLEEPONEXIT
+ * @param Cmd new state of LP condition. This parameter can be: ENABLE or DISABLE.
+ */
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_LP(LowPowerMode));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ SCB->SCR |= LowPowerMode;
+ }
+ else
+ {
+ SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
+ }
+}
+
+/**
+ * @brief Configures the SysTick clock source.
+ * @param SysTick_CLKSource specifies the SysTick clock source.
+ * This parameter can be one of the following values:
+ * @arg SysTick_CLKSource_HCLK_Div8 AHB clock divided by 8 selected as SysTick clock source.
+ * @arg SysTick_CLKSource_HCLK AHB clock selected as SysTick clock source.
+ */
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
+ if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
+ {
+ SysTick->CTRL |= SysTick_CLKSource_HCLK;
+ }
+ else
+ {
+ SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_adc.c b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_adc.c
new file mode 100644
index 0000000000..4e7efa2f36
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_adc.c
@@ -0,0 +1,1411 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_adc.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l40x_adc.h"
+#include "n32l40x_rcc.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @brief ADC driver modules
+ * @{
+ */
+
+/** @addtogroup ADC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Private_Defines
+ * @{
+ */
+
+/* ADC DISC_NUM mask */
+#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF)
+
+/* ADC DISC_EN mask */
+#define CTRL1_DISC_EN_SET ((uint32_t)0x00000800)
+#define CTRL1_DISC_EN_RESET ((uint32_t)0xFFFFF7FF)
+
+/* ADC INJ_AUTO mask */
+#define CR1_JAUTO_Set ((uint32_t)0x00000400)
+#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF)
+
+/* ADC INJ_DISC_EN mask */
+#define CTRL1_INJ_DISC_EN_SET ((uint32_t)0x00001000)
+#define CTRL1_INJ_DISC_EN_RESET ((uint32_t)0xFFFFEFFF)
+
+/* ADC AWDG_CH mask */
+#define CTRL1_AWDG_CH_RESET ((uint32_t)0xFFFFFFE0)
+
+/* ADC Analog watchdog enable mode mask */
+#define CTRL1_AWDG_MODE_RESET ((uint32_t)0xFF3FFDFF)
+
+/* CTRL1 register Mask */
+#define CTRL1_CLR_MASK ((uint32_t)0xFFF0FEFF)
+
+/* ADC AD_ON mask */
+#define CTRL2_AD_ON_SET ((uint32_t)0x00000001)
+#define CTRL2_AD_ON_RESET ((uint32_t)0xFFFFFFFE)
+
+/* ADC DMA mask */
+#define CTRL2_DMA_SET ((uint32_t)0x00000100)
+#define CTRL2_DMA_RESET ((uint32_t)0xFFFFFEFF)
+
+/* ADC RST_CALI mask */
+#define CTRL2_RST_CALI_SET ((uint32_t)0x00000008)
+
+/* ADC CAL mask */
+#define CTRL2_CAL_SET ((uint32_t)0x00000004)
+
+/* ADC SOFT_START mask */
+#define CTRL2_SOFT_START_SET ((uint32_t)0x00400000)
+
+/* ADC EXT_TRIG mask */
+#define CTRL2_EXT_TRIG_SET ((uint32_t)0x00100000)
+#define CTRL2_EXT_TRIG_RESET ((uint32_t)0xFFEFFFFF)
+
+/* ADC Software start mask */
+#define CTRL2_EXT_TRIG_SWSTART_SET ((uint32_t)0x00500000)
+#define CTRL2_EXT_TRIG_SWSTART_RESET ((uint32_t)0xFFAFFFFF)
+
+/* ADC INJ_EXT_SEL mask */
+#define CTRL2_INJ_EXT_SEL_RESET ((uint32_t)0xFFFF8FFF)
+
+/* ADC INJ_EXT_TRIG mask */
+#define CTRL2_INJ_EXT_TRIG_SET ((uint32_t)0x00008000)
+#define CTRL2_INJ_EXT_TRIG_RESET ((uint32_t)0xFFFF7FFF)
+
+/* ADC INJ_SWSTART mask */
+#define CTRL2_INJ_SWSTART_SET ((uint32_t)0x00200000)
+
+/* ADC injected software start mask */
+#define CTRL2_INJ_EXT_TRIG_JSWSTART_SET ((uint32_t)0x00208000)
+#define CTRL2_INJ_EXT_TRIG_JSWSTART_RESET ((uint32_t)0xFFDF7FFF)
+
+/* ADC TSPD mask */
+#define CTRL2_TSVREFE_SET ((uint32_t)0x00800000)
+#define CTRL2_TSVREFE_RESET ((uint32_t)0xFF7FFFFF)
+
+/* CTRL2 register Mask */
+#define CTRL2_CLR_MASK ((uint32_t)0xFFF1F7FD)
+
+/* ADC SQx mask */
+#define SQR4_SEQ_SET ((uint32_t)0x0000001F)
+#define SQR3_SEQ_SET ((uint32_t)0x0000001F)
+#define SQR2_SEQ_SET ((uint32_t)0x0000001F)
+#define SQR1_SEQ_SET ((uint32_t)0x0000001F)
+
+/* RSEQ1 register Mask */
+#define RSEQ1_CLR_MASK ((uint32_t)0xFF0FFFFF)
+
+/* ADC JSQx mask */
+#define JSEQ_JSQ_SET ((uint32_t)0x0000001F)
+
+/* ADC INJ_LEN mask */
+#define JSEQ_INJ_LEN_SET ((uint32_t)0x00300000)
+#define JSEQ_INJ_LEN_RESET ((uint32_t)0xFFCFFFFF)
+
+/* ADC SAMPTx mask */
+#define SAMPT1_SMP_SET ((uint32_t)0x00000007)
+#define SAMPT2_SMP_SET ((uint32_t)0x00000007)
+
+/* ADC JDATx registers offset */
+#define JDAT_OFFSET ((uint8_t)0x28)
+
+/* ADC1 DAT register base address */
+#define DAT_ADDR ((uint32_t)0x4001244C)
+
+/* ADC STS register mask */
+#define ADC_STS_RESERVE_MASK ((uint32_t)0x0000007F)
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the ADCx peripheral registers to their default reset values.
+ * @param ADCx where x can be 1, 2 ,3 or 4 to select the ADC peripheral.
+ */
+void ADC_DeInit(ADC_Module* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+
+ if (ADCx == ADC)
+ {
+ /* Enable ADC1 reset state */
+ RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_ADC, ENABLE);
+ /* Release ADC1 from reset state */
+ RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_ADC, DISABLE);
+ }
+}
+
+/**
+ * @brief Initializes the ADCx peripheral according to the specified parameters
+ * in the ADC_InitStruct.
+ * @param ADCx where x can be 1, 2 ,3 or 4 to select the ADC peripheral.
+ * @param ADC_InitStruct pointer to an ADC_InitType structure that contains
+ * the configuration information for the specified ADC peripheral.
+ */
+void ADC_Init(ADC_Module* ADCx, ADC_InitType* ADC_InitStruct)
+{
+ uint32_t tmpreg1 = 0;
+ uint8_t tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->MultiChEn));
+ assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ContinueConvEn));
+ assert_param(IsAdcExtTrig(ADC_InitStruct->ExtTrigSelect));
+ assert_param(IsAdcDatAlign(ADC_InitStruct->DatAlign));
+ assert_param(IsAdcSeqLenValid(ADC_InitStruct->ChsNumber));
+
+ /*---------------------------- ADCx CTRL1 Configuration -----------------*/
+ /* Get the ADCx CTRL1 value */
+ tmpreg1 = ADCx->CTRL1;
+ /* Clear DUALMOD and SCAN bits */
+ tmpreg1 &= CTRL1_CLR_MASK;
+ /* Configure ADCx: Dual mode and scan conversion mode */
+ /* Set DUALMOD bits according to WorkMode value */
+ /* Set SCAN bit according to MultiChEn value */
+ tmpreg1 |= (uint32_t)( ((uint32_t)ADC_InitStruct->MultiChEn << 8));
+ /* Write to ADCx CTRL1 */
+ ADCx->CTRL1 = tmpreg1;
+
+ /*---------------------------- ADCx CTRL2 Configuration -----------------*/
+ /* Get the ADCx CTRL2 value */
+ tmpreg1 = ADCx->CTRL2;
+ /* Clear CONT, ALIGN and EXTSEL bits */
+ tmpreg1 &= CTRL2_CLR_MASK;
+ /* Configure ADCx: external trigger event and continuous conversion mode */
+ /* Set ALIGN bit according to DatAlign value */
+ /* Set EXTSEL bits according to ExtTrigSelect value */
+ /* Set CONT bit according to ContinueConvEn value */
+ tmpreg1 |= (uint32_t)(ADC_InitStruct->DatAlign | ADC_InitStruct->ExtTrigSelect
+ | ((uint32_t)ADC_InitStruct->ContinueConvEn << 1));
+ /* Write to ADCx CTRL2 */
+ ADCx->CTRL2 = tmpreg1;
+
+ /*---------------------------- ADCx RSEQ1 Configuration -----------------*/
+ /* Get the ADCx RSEQ1 value */
+ tmpreg1 = ADCx->RSEQ1;
+ /* Clear L bits */
+ tmpreg1 &= RSEQ1_CLR_MASK;
+ /* Configure ADCx: regular channel sequence length */
+ /* Set L bits according to ChsNumber value */
+ tmpreg2 |= (uint8_t)(ADC_InitStruct->ChsNumber - (uint8_t)1);
+ tmpreg1 |= (uint32_t)tmpreg2 << 20;
+ /* Write to ADCx RSEQ1 */
+ ADCx->RSEQ1 = tmpreg1;
+}
+
+/**
+ * @brief Fills each ADC_InitStruct member with its default value.
+ * @param ADC_InitStruct pointer to an ADC_InitType structure which will be initialized.
+ */
+void ADC_InitStruct(ADC_InitType* ADC_InitStruct)
+{
+ /* Reset ADC init structure parameters values */
+ /* initialize the MultiChEn member */
+ ADC_InitStruct->MultiChEn = DISABLE;
+ /* Initialize the ContinueConvEn member */
+ ADC_InitStruct->ContinueConvEn = DISABLE;
+ /* Initialize the ExtTrigSelect member */
+ ADC_InitStruct->ExtTrigSelect = ADC_EXT_TRIGCONV_T1_CC1;
+ /* Initialize the DatAlign member */
+ ADC_InitStruct->DatAlign = ADC_DAT_ALIGN_R;
+ /* Initialize the ChsNumber member */
+ ADC_InitStruct->ChsNumber = 1;
+}
+
+/**
+ * @brief Enables or disables the specified ADC peripheral.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the ADCx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_Enable(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set the AD_ON bit to wake up the ADC from power down mode */
+ ADCx->CTRL2 |= CTRL2_AD_ON_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC peripheral */
+ ADCx->CTRL2 &= CTRL2_AD_ON_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified ADC DMA request.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC DMA transfer.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableDMA(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcDmaModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC DMA request */
+ ADCx->CTRL2 |= CTRL2_DMA_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC DMA request */
+ ADCx->CTRL2 &= CTRL2_DMA_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified ADC interrupts.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_IT specifies the ADC interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg ADC_INT_ENDC End of conversion interrupt mask
+ * @arg ADC_INT_AWD Analog watchdog interrupt mask
+ * @arg ADC_INT_JENDC End of injected conversion interrupt mask
+ * @param Cmd new state of the specified ADC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_ConfigInt(ADC_Module* ADCx, uint16_t ADC_IT, FunctionalState Cmd)
+{
+ uint8_t itmask = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ assert_param(IsAdcInt(ADC_IT));
+ /* Get the ADC IT index */
+ itmask = (uint8_t)ADC_IT;
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC interrupts */
+ ADCx->CTRL1 |= itmask;
+ }
+ else
+ {
+ /* Disable the selected ADC interrupts */
+ ADCx->CTRL1 &= (~(uint32_t)itmask);
+ }
+}
+
+
+/**
+ * @brief Starts the selected ADC calibration process.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ */
+void ADC_StartCalibration(ADC_Module* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ /* Enable the selected ADC calibration process */
+ if (ADCx->CALFACT==0)
+ ADCx->CTRL2 |= CTRL2_CAL_SET;
+}
+
+/**
+ * @brief Gets the selected ADC calibration status.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @return The new state of ADC calibration (SET or RESET).
+ */
+FlagStatus ADC_GetCalibrationStatus(ADC_Module* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ /* Check the status of CAL bit */
+ if ((ADCx->CTRL2 & CTRL2_CAL_SET) != (uint32_t)RESET)
+ {
+ /* CAL bit is set: calibration on going */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAL bit is reset: end of calibration */
+ bitstatus = RESET;
+ }
+ if (ADCx->CALFACT!=0)
+ bitstatus = RESET;
+ /* Return the CAL bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Enables or disables the selected ADC software start conversion .
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC software start conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableSoftwareStartConv(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC conversion on external event and start the selected
+ ADC conversion */
+ ADCx->CTRL2 |= CTRL2_EXT_TRIG_SWSTART_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC conversion on external event and stop the selected
+ ADC conversion */
+ ADCx->CTRL2 &= CTRL2_EXT_TRIG_SWSTART_RESET;
+ }
+}
+
+/**
+ * @brief Gets the selected ADC Software start conversion Status.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @return The new state of ADC software start conversion (SET or RESET).
+ */
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_Module* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ /* Check the status of SOFT_START bit */
+ if ((ADCx->CTRL2 & CTRL2_SOFT_START_SET) != (uint32_t)RESET)
+ {
+ /* SOFT_START bit is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* SOFT_START bit is reset */
+ bitstatus = RESET;
+ }
+ /* Return the SOFT_START bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Configures the discontinuous mode for the selected ADC regular
+ * group channel.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Number specifies the discontinuous mode regular channel
+ * count value. This number must be between 1 and 8.
+ */
+void ADC_ConfigDiscModeChannelCount(ADC_Module* ADCx, uint8_t Number)
+{
+ uint32_t tmpreg1 = 0;
+ uint32_t tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcSeqDiscNumberValid(Number));
+ /* Get the old register value */
+ tmpreg1 = ADCx->CTRL1;
+ /* Clear the old discontinuous mode channel count */
+ tmpreg1 &= CR1_DISCNUM_Reset;
+ /* Set the discontinuous mode channel count */
+ tmpreg2 = Number - 1;
+ tmpreg1 |= tmpreg2 << 13;
+ /* Store the new register value */
+ ADCx->CTRL1 = tmpreg1;
+}
+
+/**
+ * @brief Enables or disables the discontinuous mode on regular group
+ * channel for the specified ADC
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC discontinuous mode
+ * on regular group channel.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableDiscMode(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC regular discontinuous mode */
+ ADCx->CTRL1 |= CTRL1_DISC_EN_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC regular discontinuous mode */
+ ADCx->CTRL1 &= CTRL1_DISC_EN_RESET;
+ }
+}
+
+/**
+ * @brief Configures for the selected ADC regular channel its corresponding
+ * rank in the sequencer and its sample time.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_Channel the ADC channel to configure.
+ * This parameter can be one of the following values:
+ * @arg ADC_CH_0 ADC Channel0 selected
+ * @arg ADC_CH_1 ADC Channel1 selected
+ * @arg ADC_CH_2 ADC Channel2 selected
+ * @arg ADC_CH_3 ADC Channel3 selected
+ * @arg ADC_CH_4 ADC Channel4 selected
+ * @arg ADC_CH_5 ADC Channel5 selected
+ * @arg ADC_CH_6 ADC Channel6 selected
+ * @arg ADC_CH_7 ADC Channel7 selected
+ * @arg ADC_CH_8 ADC Channel8 selected
+ * @arg ADC_CH_9 ADC Channel9 selected
+ * @arg ADC_CH_10 ADC Channel10 selected
+ * @arg ADC_CH_11 ADC Channel11 selected
+ * @arg ADC_CH_12 ADC Channel12 selected
+ * @arg ADC_CH_13 ADC Channel13 selected
+ * @arg ADC_CH_14 ADC Channel14 selected
+ * @arg ADC_CH_15 ADC Channel15 selected
+ * @arg ADC_CH_16 ADC Channel16 selected
+ * @arg ADC_CH_17 ADC Channel17 selected
+ * @arg ADC_CH_18 ADC Channel18 selected
+ * @param Rank The rank in the regular group sequencer. This parameter must be between 1 to 16.
+ * @param ADC_SampleTime The sample time value to be set for the selected channel.
+ * This parameter can be one of the following values:
+ * @arg ADC_SAMP_TIME_1CYCLES5 Sample time equal to 1.5 cycles
+ * @arg ADC_SAMP_TIME_7CYCLES5 Sample time equal to 7.5 cycles
+ * @arg ADC_SAMP_TIME_13CYCLES5 Sample time equal to 13.5 cycles
+ * @arg ADC_SAMP_TIME_28CYCLES5 Sample time equal to 28.5 cycles
+ * @arg ADC_SAMP_TIME_41CYCLES5 Sample time equal to 41.5 cycles
+ * @arg ADC_SAMP_TIME_55CYCLES5 Sample time equal to 55.5 cycles
+ * @arg ADC_SAMP_TIME_71CYCLES5 Sample time equal to 71.5 cycles
+ * @arg ADC_SAMP_TIME_239CYCLES5 Sample time equal to 239.5 cycles
+ */
+void ADC_ConfigRegularChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcChannel(ADC_Channel));
+ assert_param(IsAdcReqRankValid(Rank));
+ assert_param(IsAdcSampleTime(ADC_SampleTime));
+
+ if (ADC_Channel == ADC_CH_18)
+ {
+ tmpreg1 = ADCx->SAMPT3;
+ tmpreg1 &= (~0x00000007);
+ tmpreg1 |= ADC_SampleTime;
+ ADCx->SAMPT3 = tmpreg1;
+ }
+ if (ADC_Channel > ADC_CH_9) /* if ADC_CH_10 ... ADC_CH_17 is selected */
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SAMPT1;
+ /* Calculate the mask to clear */
+ tmpreg2 = SAMPT1_SMP_SET << (3 * (ADC_Channel - 10));
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SAMPT1 = tmpreg1;
+ }
+ else /* ADC_Channel include in ADC_Channel_[0..9] */
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SAMPT2;
+ /* Calculate the mask to clear */
+ tmpreg2 = SAMPT2_SMP_SET << (3 * ADC_Channel);
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SAMPT2 = tmpreg1;
+ }
+ /* For Rank 1 to 6 */
+ if (Rank < 7)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->RSEQ3;
+ /* Calculate the mask to clear */
+ tmpreg2 = SQR3_SEQ_SET << (5 * (Rank - 1));
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->RSEQ3 = tmpreg1;
+ }
+ /* For Rank 7 to 12 */
+ else if (Rank < 13)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->RSEQ2;
+ /* Calculate the mask to clear */
+ tmpreg2 = SQR2_SEQ_SET << (5 * (Rank - 7));
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->RSEQ2 = tmpreg1;
+ }
+ /* For Rank 13 to 16 */
+ else
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->RSEQ1;
+ /* Calculate the mask to clear */
+ tmpreg2 = SQR1_SEQ_SET << (5 * (Rank - 13));
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->RSEQ1 = tmpreg1;
+ }
+}
+
+/**
+ * @brief Enables or disables the ADCx conversion through external trigger.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC external trigger start of conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableExternalTrigConv(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC conversion on external event */
+ ADCx->CTRL2 |= CTRL2_EXT_TRIG_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC conversion on external event */
+ ADCx->CTRL2 &= CTRL2_EXT_TRIG_RESET;
+ }
+}
+
+/**
+ * @brief Returns the last ADCx conversion result data for regular channel.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @return The Data conversion value.
+ */
+uint16_t ADC_GetDat(ADC_Module* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ /* Return the selected ADC conversion value */
+ return (uint16_t)ADCx->DAT;
+}
+
+/**
+ * @brief Enables or disables the selected ADC automatic injected group
+ * conversion after regular one.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC auto injected conversion
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableAutoInjectedConv(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC automatic injected group conversion */
+ ADCx->CTRL1 |= CR1_JAUTO_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC automatic injected group conversion */
+ ADCx->CTRL1 &= CR1_JAUTO_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the discontinuous mode for injected group
+ * channel for the specified ADC
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC discontinuous mode
+ * on injected group channel.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableInjectedDiscMode(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC injected discontinuous mode */
+ ADCx->CTRL1 |= CTRL1_INJ_DISC_EN_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC injected discontinuous mode */
+ ADCx->CTRL1 &= CTRL1_INJ_DISC_EN_RESET;
+ }
+}
+
+/**
+ * @brief Configures the ADCx external trigger for injected channels conversion.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_ExternalTrigInjecConv specifies the ADC trigger to start injected conversion.
+ * This parameter can be one of the following values:
+ * @arg ADC_EXT_TRIG_INJ_CONV_T1_TRGO Timer1 TRGO event selected (for ADC1, ADC2 and ADC3)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T1_CC4 Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T2_TRGO Timer2 TRGO event selected (for ADC1 and ADC2)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T2_CC1 Timer2 capture compare1 selected (for ADC1 and ADC2)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T3_CC4 Timer3 capture compare4 selected (for ADC1 and ADC2)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T4_TRGO Timer4 TRGO event selected (for ADC1 and ADC2)
+ * @arg ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4 External interrupt line 15 or Timer8
+ * capture compare4 event selected (for ADC1 and ADC2)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T4_CC3 Timer4 capture compare3 selected (for ADC3 only)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T8_CC2 Timer8 capture compare2 selected (for ADC3 only)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T8_CC4 Timer8 capture compare4 selected (for ADC3 only)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T5_TRGO Timer5 TRGO event selected (for ADC3 only)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T5_CC4 Timer5 capture compare4 selected (for ADC3 only)
+ * @arg ADC_EXT_TRIG_INJ_CONV_NONE Injected conversion started by software and not
+ * by external trigger (for ADC1, ADC2 and ADC3)
+ */
+void ADC_ConfigExternalTrigInjectedConv(ADC_Module* ADCx, uint32_t ADC_ExternalTrigInjecConv)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcExtInjTrig(ADC_ExternalTrigInjecConv));
+ /* Get the old register value */
+ tmpregister = ADCx->CTRL2;
+ /* Clear the old external event selection for injected group */
+ tmpregister &= CTRL2_INJ_EXT_SEL_RESET;
+ /* Set the external event selection for injected group */
+ tmpregister |= ADC_ExternalTrigInjecConv;
+ /* Store the new register value */
+ ADCx->CTRL2 = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the ADCx injected channels conversion through
+ * external trigger
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC external trigger start of
+ * injected conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableExternalTrigInjectedConv(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC external event selection for injected group */
+ ADCx->CTRL2 |= CTRL2_INJ_EXT_TRIG_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC external event selection for injected group */
+ ADCx->CTRL2 &= CTRL2_INJ_EXT_TRIG_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the selected ADC start of the injected
+ * channels conversion.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC software start injected conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableSoftwareStartInjectedConv(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC conversion for injected group on external event and start the selected
+ ADC injected conversion */
+ ADCx->CTRL2 |= CTRL2_INJ_EXT_TRIG_JSWSTART_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC conversion on external event for injected group and stop the selected
+ ADC injected conversion */
+ ADCx->CTRL2 &= CTRL2_INJ_EXT_TRIG_JSWSTART_RESET;
+ }
+}
+
+/**
+ * @brief Gets the selected ADC Software start injected conversion Status.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @return The new state of ADC software start injected conversion (SET or RESET).
+ */
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_Module* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ /* Check the status of INJ_SWSTART bit */
+ if ((ADCx->CTRL2 & CTRL2_INJ_SWSTART_SET) != (uint32_t)RESET)
+ {
+ /* INJ_SWSTART bit is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* INJ_SWSTART bit is reset */
+ bitstatus = RESET;
+ }
+ /* Return the INJ_SWSTART bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Configures for the selected ADC injected channel its corresponding
+ * rank in the sequencer and its sample time.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_Channel the ADC channel to configure.
+ * This parameter can be one of the following values:
+ * @arg ADC_CH_0 ADC Channel0 selected
+ * @arg ADC_CH_1 ADC Channel1 selected
+ * @arg ADC_CH_2 ADC Channel2 selected
+ * @arg ADC_CH_3 ADC Channel3 selected
+ * @arg ADC_CH_4 ADC Channel4 selected
+ * @arg ADC_CH_5 ADC Channel5 selected
+ * @arg ADC_CH_6 ADC Channel6 selected
+ * @arg ADC_CH_7 ADC Channel7 selected
+ * @arg ADC_CH_8 ADC Channel8 selected
+ * @arg ADC_CH_9 ADC Channel9 selected
+ * @arg ADC_CH_10 ADC Channel10 selected
+ * @arg ADC_CH_11 ADC Channel11 selected
+ * @arg ADC_CH_12 ADC Channel12 selected
+ * @arg ADC_CH_13 ADC Channel13 selected
+ * @arg ADC_CH_14 ADC Channel14 selected
+ * @arg ADC_CH_15 ADC Channel15 selected
+ * @arg ADC_CH_16 ADC Channel16 selected
+ * @arg ADC_CH_17 ADC Channel17 selected
+ * @arg ADC_CH_18 ADC Channel18 selected
+ * @param Rank The rank in the injected group sequencer. This parameter must be between 1 and 4.
+ * @param ADC_SampleTime The sample time value to be set for the selected channel.
+ * This parameter can be one of the following values:
+ * @arg ADC_SAMP_TIME_1CYCLES5 Sample time equal to 1.5 cycles
+ * @arg ADC_SAMP_TIME_7CYCLES5 Sample time equal to 7.5 cycles
+ * @arg ADC_SAMP_TIME_13CYCLES5 Sample time equal to 13.5 cycles
+ * @arg ADC_SAMP_TIME_28CYCLES5 Sample time equal to 28.5 cycles
+ * @arg ADC_SAMP_TIME_41CYCLES5 Sample time equal to 41.5 cycles
+ * @arg ADC_SAMP_TIME_55CYCLES5 Sample time equal to 55.5 cycles
+ * @arg ADC_SAMP_TIME_71CYCLES5 Sample time equal to 71.5 cycles
+ * @arg ADC_SAMP_TIME_239CYCLES5 Sample time equal to 239.5 cycles
+ */
+void ADC_ConfigInjectedChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcChannel(ADC_Channel));
+ assert_param(IsAdcInjRankValid(Rank));
+ assert_param(IsAdcSampleTime(ADC_SampleTime));
+
+ if (ADC_Channel == ADC_CH_18)
+ {
+ tmpreg1 = ADCx->SAMPT3;
+ tmpreg1 &= (~0x00000007);
+ tmpreg1 |= ADC_SampleTime;
+ ADCx->SAMPT3 = tmpreg1;
+ }
+ else if (ADC_Channel > ADC_CH_9) /* if ADC_CH_10 ... ADC_CH_17 is selected */
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SAMPT1;
+ /* Calculate the mask to clear */
+ tmpreg2 = SAMPT1_SMP_SET << (3 * (ADC_Channel - 10));
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SAMPT1 = tmpreg1;
+ }
+ else /* ADC_Channel include in ADC_Channel_[0..9] */
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SAMPT2;
+ /* Calculate the mask to clear */
+ tmpreg2 = SAMPT2_SMP_SET << (3 * ADC_Channel);
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SAMPT2 = tmpreg1;
+ }
+ /* Rank configuration */
+ /* Get the old register value */
+ tmpreg1 = ADCx->JSEQ;
+ /* Get INJ_LEN value: Number = INJ_LEN+1 */
+ tmpreg3 = (tmpreg1 & JSEQ_INJ_LEN_SET) >> 20;
+ /* Calculate the mask to clear: ((Rank-1)+(4-INJ_LEN-1)) */
+ tmpreg2 = JSEQ_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+ /* Clear the old JSQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set: ((Rank-1)+(4-INJ_LEN-1)) */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+ /* Set the JSQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->JSEQ = tmpreg1;
+}
+
+/**
+ * @brief Configures the sequencer length for injected channels
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Length The sequencer length.
+ * This parameter must be a number between 1 to 4.
+ */
+void ADC_ConfigInjectedSequencerLength(ADC_Module* ADCx, uint8_t Length)
+{
+ uint32_t tmpreg1 = 0;
+ uint32_t tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcInjLenValid(Length));
+
+ /* Get the old register value */
+ tmpreg1 = ADCx->JSEQ;
+ /* Clear the old injected sequnence lenght INJ_LEN bits */
+ tmpreg1 &= JSEQ_INJ_LEN_RESET;
+ /* Set the injected sequnence lenght INJ_LEN bits */
+ tmpreg2 = Length - 1;
+ tmpreg1 |= tmpreg2 << 20;
+ /* Store the new register value */
+ ADCx->JSEQ = tmpreg1;
+}
+
+/**
+ * @brief Set the injected channels conversion value offset
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_InjectedChannel the ADC injected channel to set its offset.
+ * This parameter can be one of the following values:
+ * @arg ADC_INJ_CH_1 Injected Channel1 selected
+ * @arg ADC_INJ_CH_2 Injected Channel2 selected
+ * @arg ADC_INJ_CH_3 Injected Channel3 selected
+ * @arg ADC_INJ_CH_4 Injected Channel4 selected
+ * @param Offset the offset value for the selected ADC injected channel
+ * This parameter must be a 12bit value.
+ */
+void ADC_SetInjectedOffsetDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcInjCh(ADC_InjectedChannel));
+ assert_param(IsAdcOffsetValid(Offset));
+
+ tmp = (uint32_t)ADCx;
+ tmp += ADC_InjectedChannel;
+
+ /* Set the selected injected channel data offset */
+ *(__IO uint32_t*)tmp = (uint32_t)Offset;
+}
+
+/**
+ * @brief Returns the ADC injected channel conversion result
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_InjectedChannel the converted ADC injected channel.
+ * This parameter can be one of the following values:
+ * @arg ADC_INJ_CH_1 Injected Channel1 selected
+ * @arg ADC_INJ_CH_2 Injected Channel2 selected
+ * @arg ADC_INJ_CH_3 Injected Channel3 selected
+ * @arg ADC_INJ_CH_4 Injected Channel4 selected
+ * @return The Data conversion value.
+ */
+uint16_t ADC_GetInjectedConversionDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcInjCh(ADC_InjectedChannel));
+
+ tmp = (uint32_t)ADCx;
+ tmp += ADC_InjectedChannel + JDAT_OFFSET;
+
+ /* Returns the selected injected channel conversion data value */
+ return (uint16_t)(*(__IO uint32_t*)tmp);
+}
+
+/**
+ * @brief Enables or disables the analog watchdog on single/all regular
+ * or injected channels
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_AnalogWatchdog the ADC analog watchdog configuration.
+ * This parameter can be one of the following values:
+ * @arg ADC_ANALOG_WTDG_SINGLEREG_ENABLE Analog watchdog on a single regular channel
+ * @arg ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE Analog watchdog on a single injected channel
+ * @arg ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE Analog watchdog on a single regular or injected channel
+ * @arg ADC_ANALOG_WTDG_ALLREG_ENABLE Analog watchdog on all regular channel
+ * @arg ADC_ANALOG_WTDG_ALLINJEC_ENABLE Analog watchdog on all injected channel
+ * @arg ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE Analog watchdog on all regular and injected channels
+ * @arg ADC_ANALOG_WTDG_NONE No channel guarded by the analog watchdog
+ */
+void ADC_ConfigAnalogWatchdogWorkChannelType(ADC_Module* ADCx, uint32_t ADC_AnalogWatchdog)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcAnalogWatchdog(ADC_AnalogWatchdog));
+ /* Get the old register value */
+ tmpregister = ADCx->CTRL1;
+ /* Clear AWDEN, AWDENJ and AWDSGL bits */
+ tmpregister &= CTRL1_AWDG_MODE_RESET;
+ /* Set the analog watchdog enable mode */
+ tmpregister |= ADC_AnalogWatchdog;
+ /* Store the new register value */
+ ADCx->CTRL1 = tmpregister;
+}
+
+/**
+ * @brief Configures the high and low thresholds of the analog watchdog.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param HighThreshold the ADC analog watchdog High threshold value.
+ * This parameter must be a 12bit value.
+ * @param LowThreshold the ADC analog watchdog Low threshold value.
+ * This parameter must be a 12bit value.
+ */
+void ADC_ConfigAnalogWatchdogThresholds(ADC_Module* ADCx, uint16_t HighThreshold, uint16_t LowThreshold)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcValid(HighThreshold));
+ assert_param(IsAdcValid(LowThreshold));
+ /* Set the ADCx high threshold */
+ ADCx->WDGHIGH = HighThreshold;
+ /* Set the ADCx low threshold */
+ ADCx->WDGLOW = LowThreshold;
+}
+
+/**
+ * @brief Configures the analog watchdog guarded single channel
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_Channel the ADC channel to configure for the analog watchdog.
+ * This parameter can be one of the following values:
+ * @arg ADC_CH_0 ADC Channel0 selected
+ * @arg ADC_CH_1 ADC Channel1 selected
+ * @arg ADC_CH_2 ADC Channel2 selected
+ * @arg ADC_CH_3 ADC Channel3 selected
+ * @arg ADC_CH_4 ADC Channel4 selected
+ * @arg ADC_CH_5 ADC Channel5 selected
+ * @arg ADC_CH_6 ADC Channel6 selected
+ * @arg ADC_CH_7 ADC Channel7 selected
+ * @arg ADC_CH_8 ADC Channel8 selected
+ * @arg ADC_CH_9 ADC Channel9 selected
+ * @arg ADC_CH_10 ADC Channel10 selected
+ * @arg ADC_CH_11 ADC Channel11 selected
+ * @arg ADC_CH_12 ADC Channel12 selected
+ * @arg ADC_CH_13 ADC Channel13 selected
+ * @arg ADC_CH_14 ADC Channel14 selected
+ * @arg ADC_CH_15 ADC Channel15 selected
+ * @arg ADC_CH_16 ADC Channel16 selected
+ * @arg ADC_CH_17 ADC Channel17 selected
+ * @arg ADC_CH_18 ADC Channel18 selected
+ */
+void ADC_ConfigAnalogWatchdogSingleChannel(ADC_Module* ADCx, uint8_t ADC_Channel)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcChannel(ADC_Channel));
+ /* Get the old register value */
+ tmpregister = ADCx->CTRL1;
+ /* Clear the Analog watchdog channel select bits */
+ tmpregister &= CTRL1_AWDG_CH_RESET;
+ /* Set the Analog watchdog channel */
+ tmpregister |= ADC_Channel;
+ /* Store the new register value */
+ ADCx->CTRL1 = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the temperature sensor and Vrefint channel.
+ * @param Cmd new state of the temperature sensor.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableTempSensorVrefint(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the temperature sensor and Vrefint channel*/
+ ADC->CTRL2 |= CTRL2_TSVREFE_SET;
+ _EnVref1p2()
+ _EnVref2p0()
+ }
+ else
+ {
+ /* Disable the temperature sensor and Vrefint channel*/
+ ADC->CTRL2 &= CTRL2_TSVREFE_RESET;
+ _DisVref1p2()
+ _DisVref2p0()
+ }
+}
+
+/**
+ * @brief Checks whether the specified ADC flag is set or not.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_FLAG specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg ADC_FLAG_AWDG Analog watchdog flag
+ * @arg ADC_FLAG_ENDC End of conversion flag
+ * @arg ADC_FLAG_JENDC End of injected group conversion flag
+ * @arg ADC_FLAG_JSTR Start of injected group conversion flag
+ * @arg ADC_FLAG_STR Start of regular group conversion flag
+ * @return The new state of ADC_FLAG (SET or RESET).
+ */
+FlagStatus ADC_GetFlagStatus(ADC_Module* ADCx, uint8_t ADC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcGetFlag(ADC_FLAG));
+ /* Check the status of the specified ADC flag */
+ if ((ADCx->STS & ADC_FLAG) != (uint8_t)RESET)
+ {
+ /* ADC_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* ADC_FLAG is reset */
+ bitstatus = RESET;
+ }
+ /* Return the ADC_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the ADCx's pending flags.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_FLAG specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg ADC_FLAG_AWDG Analog watchdog flag
+ * @arg ADC_FLAG_ENDC End of conversion flag
+ * @arg ADC_FLAG_JENDC End of injected group conversion flag
+ * @arg ADC_FLAG_JSTR Start of injected group conversion flag
+ * @arg ADC_FLAG_STR Start of regular group conversion flag
+ */
+void ADC_ClearFlag(ADC_Module* ADCx, uint8_t ADC_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcClrFlag(ADC_FLAG));
+ /* Clear the selected ADC flags */
+ ADCx->STS = (~(uint32_t)ADC_FLAG & ADC_STS_RESERVE_MASK);
+}
+
+/**
+ * @brief Checks whether the specified ADC interrupt has occurred or not.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_IT specifies the ADC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg ADC_INT_ENDC End of conversion interrupt mask
+ * @arg ADC_INT_AWD Analog watchdog interrupt mask
+ * @arg ADC_INT_JENDC End of injected conversion interrupt mask
+ * @return The new state of ADC_IT (SET or RESET).
+ */
+INTStatus ADC_GetIntStatus(ADC_Module* ADCx, uint16_t ADC_IT)
+{
+ INTStatus bitstatus = RESET;
+ uint32_t itmask = 0, enablestatus = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcGetInt(ADC_IT));
+ /* Get the ADC IT index */
+ itmask = ADC_IT >> 8;
+ /* Get the ADC_IT enable bit status */
+ enablestatus = (ADCx->CTRL1 & (uint8_t)ADC_IT);
+ /* Check the status of the specified ADC interrupt */
+ if (((ADCx->STS & itmask) != (uint32_t)RESET) && enablestatus)
+ {
+ /* ADC_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* ADC_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the ADC_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the ADCx's interrupt pending bits.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_IT specifies the ADC interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg ADC_INT_ENDC End of conversion interrupt mask
+ * @arg ADC_INT_AWD Analog watchdog interrupt mask
+ * @arg ADC_INT_JENDC End of injected conversion interrupt mask
+ */
+void ADC_ClearIntPendingBit(ADC_Module* ADCx, uint16_t ADC_IT)
+{
+ uint8_t itmask = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcInt(ADC_IT));
+ /* Get the ADC IT index */
+ itmask = (uint8_t)(ADC_IT >> 8);
+ /* Clear the selected ADC interrupt pending bits */
+ ADCx->STS = (~(uint32_t)itmask & ADC_STS_RESERVE_MASK);
+}
+
+/**
+ * @brief Initializes the ADCx peripheral according to the specified parameters
+ * in the ADC_InitStructEx.
+ * @param ADCx where x can be 1, 2 ,3 or 4 to select the ADC peripheral.
+ * @param ADC_InitStructEx pointer to an ADC_InitTypeEx structure that contains
+ * the configuration information for the specified ADC peripheral.
+ */
+void ADC_InitEx(ADC_Module* ADCx, ADC_InitTypeEx* ADC_InitStructEx)
+{
+ uint32_t tmpregister = 0;
+ /*ADC_SAMPT3 samp time sele ,as sam 103 or 303 style*/
+ if (ADC_InitStructEx->Samp303Style)
+ ADCx->SAMPT3 |= ADC_SAMPT3_SAMPSEL_MSK;
+ else
+ ADCx->SAMPT3 &= (~ADC_SAMPT3_SAMPSEL_MSK);
+
+ /*intial ADC_CTRL3 once initiall config*/
+ tmpregister = ADCx->CTRL3;
+ if (ADC_InitStructEx->DeepPowerModEn)
+ tmpregister |= ADC_CTRL3_DPWMOD_MSK;
+ else
+ tmpregister &= (~ADC_CTRL3_DPWMOD_MSK);
+
+ if (ADC_InitStructEx->JendcIntEn)
+ tmpregister |= ADC_CTRL3_JENDCAIEN_MSK;
+ else
+ tmpregister &= (~ADC_CTRL3_JENDCAIEN_MSK);
+
+ if (ADC_InitStructEx->EndcIntEn)
+ tmpregister |= ADC_CTRL3_ENDCAIEN_MSK;
+ else
+ tmpregister &= (~ADC_CTRL3_ENDCAIEN_MSK);
+
+ if (ADC_InitStructEx->CalAtuoLoadEn)
+ tmpregister |= ADC_CTRL3_CALALD_MSK;
+ else
+ tmpregister &= (~ADC_CTRL3_CALALD_MSK);
+
+ if (ADC_InitStructEx->DifModCal)
+ tmpregister |= ADC_CTRL3_CALDIF_MSK;
+ else
+ tmpregister &= (~ADC_CTRL3_CALDIF_MSK);
+
+ tmpregister &= (~ADC_CTRL3_RES_MSK);
+ tmpregister |= ADC_InitStructEx->ResBit;
+
+ tmpregister &= (~ADC_CTRL3_CKMOD_MSK);
+ if (ADC_InitStructEx->ClkMode==ADC_CTRL3_CKMOD_PLL)
+ tmpregister |= ADC_CTRL3_CKMOD_MSK;
+
+ ADCx->CTRL3 = tmpregister;
+}
+/**
+ * @brief Checks whether the specified ADC flag is set or not.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_FLAG_NEW specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg ADC_FLAG_RDY ADC ready flag
+ * @arg ADC_FLAG_PD_RDY ADC powerdown ready flag
+ * @return The new state of ADC_FLAG_NEW (SET or RESET).
+ */
+FlagStatus ADC_GetFlagStatusNew(ADC_Module* ADCx, uint8_t ADC_FLAG_NEW)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcGetFlag(ADC_FLAG_NEW));
+ /* Check the status of the specified ADC flag */
+ if ((ADCx->CTRL3 & ADC_FLAG_NEW) != (uint8_t)RESET)
+ {
+ /* ADC_FLAG_NEW is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* ADC_FLAG_NEW is reset */
+ bitstatus = RESET;
+ }
+ /* Return the ADC_FLAG_NEW status */
+ return bitstatus;
+}
+/**
+ * @brief Set Adc calibration bypass or enable.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param en enable bypass calibration.
+ * This parameter can be one of the following values:
+ * @arg true bypass calibration
+ * @arg false not bypass calibration
+ */
+void ADC_SetBypassCalibration(ADC_Module* ADCx, FunctionalState en)
+{
+ uint32_t tmpregister = 0;
+
+ tmpregister = ADCx->CTRL3;
+ if (en)
+ tmpregister |= ADC_CTRL3_BPCAL_MSK;
+ else
+ tmpregister &= (~ADC_CTRL3_BPCAL_MSK);
+ ADCx->CTRL3 = tmpregister;
+}
+/**
+ * @brief Set Adc trans bits width.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ResultBitNum specifies num with adc trans width.
+ * This parameter can be one of the following values:
+ * @arg ADC_RST_BIT_12 12 bit trans
+ * @arg ADC_RST_BIT_10 10 bit trans
+ * @arg ADC_RST_BIT_8 8 bit trans
+ * @arg ADC_RESULT_BIT_6 6 bit trans
+ */
+void ADC_SetConvResultBitNum(ADC_Module* ADCx, uint32_t ResultBitNum)
+{
+ uint32_t tmpregister = 0;
+
+ tmpregister = ADCx->CTRL3;
+ tmpregister &= 0xFFFFFFFC;
+ tmpregister |= ResultBitNum;
+ ADCx->CTRL3 = tmpregister;
+ return;
+}
+
+
+/**
+ * @brief Configures the ADCHCLK prescaler.
+ * @param RCC_ADCHCLKPrescaler specifies the ADCHCLK prescaler.
+ * This parameter can be on of the following values:
+ * @arg RCC_ADCHCLK_DIV1 ADCHCLKPRE[3:0] = 0000, HCLK Clock Divided By 1
+ * @arg RCC_ADCHCLK_DIV2 ADCHCLKPRE[3:0] = 0001, HCLK Clock Divided By 2
+ * @arg RCC_ADCHCLK_DIV4 ADCHCLKPRE[3:0] = 0010, HCLK Clock Divided By 4
+ * @arg RCC_ADCHCLK_DIV6 ADCHCLKPRE[3:0] = 0011, HCLK Clock Divided By 6
+ * @arg RCC_ADCHCLK_DIV8 ADCHCLKPRE[3:0] = 0100, HCLK Clock Divided By 8
+ * @arg RCC_ADCHCLK_DIV10 ADCHCLKPRE[3:0] = 0101, HCLK Clock Divided By 10
+ * @arg RCC_ADCHCLK_DIV12 ADCHCLKPRE[3:0] = 0110, HCLK Clock Divided By 12
+ * @arg RCC_ADCHCLK_DIV16 ADCHCLKPRE[3:0] = 0111, HCLK Clock Divided By 16
+ * @arg RCC_ADCHCLK_DIV32 ADCHCLKPRE[3:0] = 1000, HCLK Clock Divided By 32
+ * @arg RCC_ADCHCLK_DIV32 ADCHCLKPRE[3:0] = others, HCLK Clock Divided By 32
+
+ * @arg RCC_ADCPLLCLK_DISABLE ADCPLLCLKPRES[4:0] = 0xxxx, ADC Pll Clock Disable
+ * @arg RCC_ADCPLLCLK_DIV1 ADCPLLCLKPRES[4:0] = 10000, Pll Clock Divided By 1
+ * @arg RCC_ADCPLLCLK_DIV2 ADCPLLCLKPRES[4:0] = 10001, Pll Clock Divided By 2
+ * @arg RCC_ADCPLLCLK_DIV4 ADCPLLCLKPRES[4:0] = 10010, Pll Clock Divided By 4
+ * @arg RCC_ADCPLLCLK_DIV6 ADCPLLCLKPRES[4:0] = 10011, Pll Clock Divided By 6
+ * @arg RCC_ADCPLLCLK_DIV8 ADCPLLCLKPRES[4:0] = 10100, Pll Clock Divided By 8
+ * @arg RCC_ADCPLLCLK_DIV10 ADCPLLCLKPRES[4:0] = 10101, Pll Clock Divided By 10
+ * @arg RCC_ADCPLLCLK_DIV12 ADCPLLCLKPRES[4:0] = 10110, Pll Clock Divided By 12
+ * @arg RCC_ADCPLLCLK_DIV16 ADCPLLCLKPRES[4:0] = 10111, Pll Clock Divided By 16
+ * @arg RCC_ADCPLLCLK_DIV32 ADCPLLCLKPRES[4:0] = 11000, Pll Clock Divided By 32
+ * @arg RCC_ADCPLLCLK_DIV64 ADCPLLCLKPRES[4:0] = 11001, Pll Clock Divided By 64
+ * @arg RCC_ADCPLLCLK_DIV128 ADCPLLCLKPRES[4:0] = 11010, Pll Clock Divided By 128
+ * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = 11011, Pll Clock Divided By 256
+ * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = others, Pll Clock Divided By 256
+ */
+void ADC_ConfigClk(ADC_CTRL3_CKMOD ADC_ClkMode, uint32_t RCC_ADCHCLKPrescaler)
+{
+ if (ADC_ClkMode==ADC_CTRL3_CKMOD_AHB){
+ RCC_ConfigAdcPllClk(RCC_ADCPLLCLK_DIV1, DISABLE);
+ RCC_ConfigAdcHclk(RCC_ADCHCLKPrescaler);
+ }else{
+ RCC_ConfigAdcPllClk(RCC_ADCHCLKPrescaler, ENABLE);
+ RCC_ConfigAdcHclk(RCC_ADCHCLK_DIV1);
+ }
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_can.c b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_can.c
new file mode 100644
index 0000000000..9037b4d49f
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_can.c
@@ -0,0 +1,1372 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_can.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l40x_can.h"
+#include "n32l40x_rcc.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CAN
+ * @brief CAN driver modules
+ * @{
+ */
+
+/** @addtogroup CAN_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Private_Defines
+ * @{
+ */
+
+/* CAN Master Control Register bits */
+#define MCTRL_DBGF ((uint32_t)0x00010000) /* Debug freeze */
+#define MCTRL_MRST ((uint32_t)0x00010000) /* software master reset */
+
+/* CAN Mailbox Transmit Request */
+#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */
+
+/* CAN Filter Master Register bits */
+#define FMC_FINITM ((uint32_t)0x00000001) /* Filter init mode */
+
+/* Time out for INAK bit */
+#define INIAK_TIMEOUT ((uint32_t)0x0000FFFF)
+/* Time out for SLAK bit */
+#define SLPAK_TIMEOUT ((uint32_t)0x0000FFFF)
+
+/* Flags in TSTS register */
+#define CAN_FLAGS_TSTS ((uint32_t)0x08000000)
+/* Flags in RFF1 register */
+#define CAN_FLAGS_RFF1 ((uint32_t)0x04000000)
+/* Flags in RFF0 register */
+#define CAN_FLAGS_RFF0 ((uint32_t)0x02000000)
+/* Flags in MSTS register */
+#define CAN_FLAGS_MSTS ((uint32_t)0x01000000)
+/* Flags in ESTS register */
+#define CAN_FLAGS_ESTS ((uint32_t)0x00F00000)
+
+/* Mailboxes definition */
+#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
+#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
+#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
+
+#define CAN_MODE_MASK ((uint32_t)0x00000003)
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Private_FunctionPrototypes
+ * @{
+ */
+
+static INTStatus CheckINTStatus(uint32_t CAN_Reg, uint32_t Int_Bit);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the CAN peripheral registers to their default reset values.
+ * @param CANx.
+ */
+void CAN_DeInit(CAN_Module* CANx)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Enable CAN reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_CAN, ENABLE);
+ /* Release CAN from reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_CAN, DISABLE);
+}
+
+/**
+ * @brief Initializes the CAN peripheral according to the specified
+ * parameters in the CAN_InitParam.
+ * @param CAN to select the CAN peripheral.
+ * @param CAN_InitParam pointer to a CAN_InitType structure that
+ * contains the configuration information for the
+ * CAN peripheral.
+ * @return Constant indicates initialization succeed which will be
+ * CAN_InitSTS_Failed or CAN_InitSTS_Success.
+ */
+uint8_t CAN_Init(CAN_Module* CANx, CAN_InitType* CAN_InitParam)
+{
+ uint8_t InitStatus = CAN_InitSTS_Failed;
+ uint32_t wait_ack = 0x00000000;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->TTCM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->ABOM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->AWKUM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->NART));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->RFLM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->TXFP));
+ assert_param(IS_CAN_MODE(CAN_InitParam->OperatingMode));
+ assert_param(IS_CAN_RSJW(CAN_InitParam->RSJW));
+ assert_param(IS_CAN_TBS1(CAN_InitParam->TBS1));
+ assert_param(IS_CAN_TBS2(CAN_InitParam->TBS2));
+ assert_param(IS_CAN_BAUDRATEPRESCALER(CAN_InitParam->BaudRatePrescaler));
+
+ /* Exit from sleep mode */
+ CANx->MCTRL &= (~(uint32_t)CAN_MCTRL_SLPRQ);
+
+ /* Request initialisation */
+ CANx->MCTRL |= CAN_MCTRL_INIRQ;
+
+ /* Wait the acknowledge */
+ while (((CANx->MSTS & CAN_MSTS_INIAK) != CAN_MSTS_INIAK) && (wait_ack != INIAK_TIMEOUT))
+ {
+ wait_ack++;
+ }
+
+ /* Check acknowledge */
+ if ((CANx->MSTS & CAN_MSTS_INIAK) != CAN_MSTS_INIAK)
+ {
+ InitStatus = CAN_InitSTS_Failed;
+ }
+ else
+ {
+ /* Set the time triggered communication mode */
+ if (CAN_InitParam->TTCM == ENABLE)
+ {
+ CANx->MCTRL |= CAN_MCTRL_TTCM;
+ }
+ else
+ {
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_TTCM;
+ }
+
+ /* Set the automatic bus-off management */
+ if (CAN_InitParam->ABOM == ENABLE)
+ {
+ CANx->MCTRL |= CAN_MCTRL_ABOM;
+ }
+ else
+ {
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_ABOM;
+ }
+
+ /* Set the automatic wake-up mode */
+ if (CAN_InitParam->AWKUM == ENABLE)
+ {
+ CANx->MCTRL |= CAN_MCTRL_AWKUM;
+ }
+ else
+ {
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_AWKUM;
+ }
+
+ /* Set the no automatic retransmission */
+ if (CAN_InitParam->NART == ENABLE)
+ {
+ CANx->MCTRL |= CAN_MCTRL_NART;
+ }
+ else
+ {
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_NART;
+ }
+
+ /* Set the receive DATFIFO locked mode */
+ if (CAN_InitParam->RFLM == ENABLE)
+ {
+ CANx->MCTRL |= CAN_MCTRL_RFLM;
+ }
+ else
+ {
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_RFLM;
+ }
+
+ /* Set the transmit DATFIFO priority */
+ if (CAN_InitParam->TXFP == ENABLE)
+ {
+ CANx->MCTRL |= CAN_MCTRL_TXFP;
+ }
+ else
+ {
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_TXFP;
+ }
+
+ /* Set the bit timing register */
+ CANx->BTIM = (uint32_t)((uint32_t)CAN_InitParam->OperatingMode << 30) | ((uint32_t)CAN_InitParam->RSJW << 24)
+ | ((uint32_t)CAN_InitParam->TBS1 << 16) | ((uint32_t)CAN_InitParam->TBS2 << 20)
+ | ((uint32_t)CAN_InitParam->BaudRatePrescaler - 1);
+
+ /* Request leave initialisation */
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_INIRQ;
+
+ /* Wait the acknowledge */
+ wait_ack = 0;
+
+ while (((CANx->MSTS & CAN_MSTS_INIAK) == CAN_MSTS_INIAK) && (wait_ack != INIAK_TIMEOUT))
+ {
+ wait_ack++;
+ }
+
+ /* ...and check acknowledged */
+ if ((CANx->MSTS & CAN_MSTS_INIAK) == CAN_MSTS_INIAK)
+ {
+ InitStatus = CAN_InitSTS_Failed;
+ }
+ else
+ {
+ InitStatus = CAN_InitSTS_Success;
+ }
+ }
+
+ /* At this step, return the status of initialization */
+ return InitStatus;
+}
+
+/**
+ * @brief Initializes the CAN peripheral according to the specified
+ * parameters in the CAN_InitFilterStruct.
+ * @param CAN_InitFilterStruct pointer to a CAN_FilterInitType
+ * structure that contains the configuration
+ * information.
+ */
+void CAN_InitFilter(CAN_FilterInitType* CAN_InitFilterStruct)
+{
+ uint32_t filter_number_bit_pos = 0;
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_NUM(CAN_InitFilterStruct->Filter_Num));
+ assert_param(IS_CAN_FILTER_MODE(CAN_InitFilterStruct->Filter_Mode));
+ assert_param(IS_CAN_FILTER_SCALE(CAN_InitFilterStruct->Filter_Scale));
+ assert_param(IS_CAN_FILTER_FIFO(CAN_InitFilterStruct->Filter_FIFOAssignment));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitFilterStruct->Filter_Act));
+
+ filter_number_bit_pos = ((uint32_t)1) << CAN_InitFilterStruct->Filter_Num;
+
+ /* Initialisation mode for the filter */
+ CAN->FMC |= FMC_FINITM;
+
+ /* Filter Deactivation */
+ CAN->FA1 &= ~(uint32_t)filter_number_bit_pos;
+
+ /* Filter Scale */
+ if (CAN_InitFilterStruct->Filter_Scale == CAN_Filter_16bitScale)
+ {
+ /* 16-bit scale for the filter */
+ CAN->FS1 &= ~(uint32_t)filter_number_bit_pos;
+
+ /* First 16-bit identifier and First 16-bit mask */
+ /* Or First 16-bit identifier and Second 16-bit identifier */
+ CAN->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR1 =
+ ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_LowId) << 16)
+ | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_LowId);
+
+ /* Second 16-bit identifier and Second 16-bit mask */
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+ CAN->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR2 =
+ ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_HighId) << 16)
+ | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_HighId);
+ }
+
+ if (CAN_InitFilterStruct->Filter_Scale == CAN_Filter_32bitScale)
+ {
+ /* 32-bit scale for the filter */
+ CAN->FS1 |= filter_number_bit_pos;
+ /* 32-bit identifier or First 32-bit identifier */
+ CAN->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR1 =
+ ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_HighId) << 16)
+ | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_LowId);
+ /* 32-bit mask or Second 32-bit identifier */
+ CAN->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR2 =
+ ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_HighId) << 16)
+ | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_LowId);
+ }
+
+ /* Filter Mode */
+ if (CAN_InitFilterStruct->Filter_Mode == CAN_Filter_IdMaskMode)
+ {
+ /*Id/Mask mode for the filter*/
+ CAN->FM1 &= ~(uint32_t)filter_number_bit_pos;
+ }
+ else /* CAN_InitFilterStruct->Filter_Mode == CAN_Filter_IdListMode */
+ {
+ /*Identifier list mode for the filter*/
+ CAN->FM1 |= (uint32_t)filter_number_bit_pos;
+ }
+
+ /* Filter DATFIFO assignment */
+ if (CAN_InitFilterStruct->Filter_FIFOAssignment == CAN_Filter_FIFO0)
+ {
+ /* DATFIFO 0 assignation for the filter */
+ CAN->FFA1 &= ~(uint32_t)filter_number_bit_pos;
+ }
+
+ if (CAN_InitFilterStruct->Filter_FIFOAssignment == CAN_Filter_FIFO1)
+ {
+ /* DATFIFO 1 assignation for the filter */
+ CAN->FFA1 |= (uint32_t)filter_number_bit_pos;
+ }
+
+ /* Filter activation */
+ if (CAN_InitFilterStruct->Filter_Act == ENABLE)
+ {
+ CAN->FA1 |= filter_number_bit_pos;
+ }
+
+ /* Leave the initialisation mode for the filter */
+ CAN->FMC &= ~FMC_FINITM;
+}
+/**
+ * @brief Fills each CAN_InitParam member with its default value.
+ * @param CAN_InitParam pointer to a CAN_InitType structure which
+ * will be initialized.
+ */
+void CAN_InitStruct(CAN_InitType* CAN_InitParam)
+{
+ /* Reset CAN init structure parameters values */
+
+ /* Initialize the time triggered communication mode */
+ CAN_InitParam->TTCM = DISABLE;
+
+ /* Initialize the automatic bus-off management */
+ CAN_InitParam->ABOM = DISABLE;
+
+ /* Initialize the automatic wake-up mode */
+ CAN_InitParam->AWKUM = DISABLE;
+
+ /* Initialize the no automatic retransmission */
+ CAN_InitParam->NART = DISABLE;
+
+ /* Initialize the receive DATFIFO locked mode */
+ CAN_InitParam->RFLM = DISABLE;
+
+ /* Initialize the transmit DATFIFO priority */
+ CAN_InitParam->TXFP = DISABLE;
+
+ /* Initialize the OperatingMode member */
+ CAN_InitParam->OperatingMode = CAN_Normal_Mode;
+
+ /* Initialize the RSJW member */
+ CAN_InitParam->RSJW = CAN_RSJW_1tq;
+
+ /* Initialize the TBS1 member */
+ CAN_InitParam->TBS1 = CAN_TBS1_4tq;
+
+ /* Initialize the TBS2 member */
+ CAN_InitParam->TBS2 = CAN_TBS2_3tq;
+
+ /* Initialize the BaudRatePrescaler member */
+ CAN_InitParam->BaudRatePrescaler = 1;
+}
+
+/**
+ * @brief Enables or disables the DBG Freeze for CAN.
+ * @param CAN to select the CAN peripheral.
+ * @param Cmd new state of the CAN peripheral. This parameter can
+ * be: ENABLE or DISABLE.
+ */
+void CAN_DebugFreeze(CAN_Module* CANx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable Debug Freeze */
+ CANx->MCTRL |= MCTRL_DBGF;
+ }
+ else
+ {
+ /* Disable Debug Freeze */
+ CANx->MCTRL &= ~MCTRL_DBGF;
+ }
+}
+
+/**
+ * @brief Enables or disabes the CAN Time TriggerOperation communication mode.
+ * @param CAN to select the CAN peripheral.
+ * @param Cmd Mode new state , can be one of @ref FunctionalState.
+ * @note when enabled, Time stamp (TIME[15:0]) value is sent in the last
+ * two data bytes of the 8-byte message: TIME[7:0] in data byte 6
+ * and TIME[15:8] in data byte 7
+ * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be
+ * sent over the CAN bus.
+ */
+void CAN_EnTTComMode(CAN_Module* CANx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the TTCM mode */
+ CANx->MCTRL |= CAN_MCTRL_TTCM;
+
+ /* Set TGT bits */
+ CANx->sTxMailBox[0].TMDT |= ((uint32_t)CAN_TMDT0_TGT);
+ CANx->sTxMailBox[1].TMDT |= ((uint32_t)CAN_TMDT1_TGT);
+ CANx->sTxMailBox[2].TMDT |= ((uint32_t)CAN_TMDT2_TGT);
+ }
+ else
+ {
+ /* Disable the TTCM mode */
+ CANx->MCTRL &= (uint32_t)(~(uint32_t)CAN_MCTRL_TTCM);
+
+ /* Reset TGT bits */
+ CANx->sTxMailBox[0].TMDT &= ((uint32_t)~CAN_TMDT0_TGT);
+ CANx->sTxMailBox[1].TMDT &= ((uint32_t)~CAN_TMDT1_TGT);
+ CANx->sTxMailBox[2].TMDT &= ((uint32_t)~CAN_TMDT2_TGT);
+ }
+}
+/**
+ * @brief Initiates the transmission of a message.
+ * @param CAN to select the CAN peripheral.
+ * @param TxMessage pointer to a structure which contains CAN Id, CAN
+ * DLC and CAN data.
+ * @return The number of the mailbox that is used for transmission
+ * or CAN_TxSTS_NoMailBox if there is no empty mailbox.
+ */
+uint8_t CAN_TransmitMessage(CAN_Module* CANx, CanTxMessage* TxMessage)
+{
+ uint8_t transmit_mailbox = 0;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_ID(TxMessage->IDE));
+ assert_param(IS_CAN_RTRQ(TxMessage->RTR));
+ assert_param(IS_CAN_DLC(TxMessage->DLC));
+
+ /* Select one empty transmit mailbox */
+ if ((CANx->TSTS & CAN_TSTS_TMEM0) == CAN_TSTS_TMEM0)
+ {
+ transmit_mailbox = 0;
+ }
+ else if ((CANx->TSTS & CAN_TSTS_TMEM1) == CAN_TSTS_TMEM1)
+ {
+ transmit_mailbox = 1;
+ }
+ else if ((CANx->TSTS & CAN_TSTS_TMEM2) == CAN_TSTS_TMEM2)
+ {
+ transmit_mailbox = 2;
+ }
+ else
+ {
+ transmit_mailbox = CAN_TxSTS_NoMailBox;
+ }
+
+ if (transmit_mailbox != CAN_TxSTS_NoMailBox)
+ {
+ /* Set up the Id */
+ CANx->sTxMailBox[transmit_mailbox].TMI &= TMIDxR_TXRQ;
+ if (TxMessage->IDE == CAN_Standard_Id)
+ {
+ assert_param(IS_CAN_STDID(TxMessage->StdId));
+ CANx->sTxMailBox[transmit_mailbox].TMI |= ((TxMessage->StdId << 21) | TxMessage->RTR);
+ }
+ else
+ {
+ assert_param(IS_CAN_EXTID(TxMessage->ExtId));
+ CANx->sTxMailBox[transmit_mailbox].TMI |= ((TxMessage->ExtId << 3) | TxMessage->IDE | TxMessage->RTR);
+ }
+
+ /* Set up the DLC */
+ TxMessage->DLC &= (uint8_t)0x0000000F;
+ CANx->sTxMailBox[transmit_mailbox].TMDT &= (uint32_t)0xFFFFFFF0;
+ CANx->sTxMailBox[transmit_mailbox].TMDT |= TxMessage->DLC;
+
+ /* Set up the data field */
+ CANx->sTxMailBox[transmit_mailbox].TMDL =
+ (((uint32_t)TxMessage->Data[3] << 24) | ((uint32_t)TxMessage->Data[2] << 16)
+ | ((uint32_t)TxMessage->Data[1] << 8) | ((uint32_t)TxMessage->Data[0]));
+ CANx->sTxMailBox[transmit_mailbox].TMDH =
+ (((uint32_t)TxMessage->Data[7] << 24) | ((uint32_t)TxMessage->Data[6] << 16)
+ | ((uint32_t)TxMessage->Data[5] << 8) | ((uint32_t)TxMessage->Data[4]));
+ /* Request transmission */
+ CANx->sTxMailBox[transmit_mailbox].TMI |= TMIDxR_TXRQ;
+ }
+ return transmit_mailbox;
+}
+
+/**
+ * @brief Checks the transmission of a message.
+ * @param CANx to select the CAN peripheral.
+ * @param TransmitMailbox the number of the mailbox that is used for
+ * transmission.
+ * @return CAN_TxSTS_Ok if the CAN driver transmits the message, CAN_TxSTS_Failed
+ * in an other case.
+ */
+uint8_t CAN_TransmitSTS(CAN_Module* CANx, uint8_t TransmitMailbox)
+{
+ uint32_t state = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
+
+ switch (TransmitMailbox)
+ {
+ case (CAN_TXMAILBOX_0):
+ state = CANx->TSTS & (CAN_TSTS_RQCPM0 | CAN_TSTS_TXOKM0 | CAN_TSTS_TMEM0);
+ break;
+ case (CAN_TXMAILBOX_1):
+ state = CANx->TSTS & (CAN_TSTS_RQCPM1 | CAN_TSTS_TXOKM1 | CAN_TSTS_TMEM1);
+ break;
+ case (CAN_TXMAILBOX_2):
+ state = CANx->TSTS & (CAN_TSTS_RQCPM2 | CAN_TSTS_TXOKM2 | CAN_TSTS_TMEM2);
+ break;
+ default:
+ state = CAN_TxSTS_Failed;
+ break;
+ }
+ switch (state)
+ {
+ /* transmit pending */
+ case (0x0):
+ state = CAN_TxSTS_Pending;
+ break;
+ /* transmit failed */
+ case (CAN_TSTS_RQCPM0 | CAN_TSTS_TMEM0):
+ state = CAN_TxSTS_Failed;
+ break;
+ case (CAN_TSTS_RQCPM1 | CAN_TSTS_TMEM1):
+ state = CAN_TxSTS_Failed;
+ break;
+ case (CAN_TSTS_RQCPM2 | CAN_TSTS_TMEM2):
+ state = CAN_TxSTS_Failed;
+ break;
+ /* transmit succeeded */
+ case (CAN_TSTS_RQCPM0 | CAN_TSTS_TXOKM0 | CAN_TSTS_TMEM0):
+ state = CAN_TxSTS_Ok;
+ break;
+ case (CAN_TSTS_RQCPM1 | CAN_TSTS_TXOKM1 | CAN_TSTS_TMEM1):
+ state = CAN_TxSTS_Ok;
+ break;
+ case (CAN_TSTS_RQCPM2 | CAN_TSTS_TXOKM2 | CAN_TSTS_TMEM2):
+ state = CAN_TxSTS_Ok;
+ break;
+ default:
+ state = CAN_TxSTS_Failed;
+ break;
+ }
+ return (uint8_t)state;
+}
+
+/**
+ * @brief Cancels a transmit request.
+ * @param CAN to select the CAN peripheral.
+ * @param Mailbox Mailbox number.
+ */
+void CAN_CancelTransmitMessage(CAN_Module* CANx, uint8_t Mailbox)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));
+ /* abort transmission */
+ switch (Mailbox)
+ {
+ case (CAN_TXMAILBOX_0):
+ CANx->TSTS = CAN_TSTS_ABRQM0;
+ break;
+ case (CAN_TXMAILBOX_1):
+ CANx->TSTS = CAN_TSTS_ABRQM1;
+ break;
+ case (CAN_TXMAILBOX_2):
+ CANx->TSTS = CAN_TSTS_ABRQM2;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Receives a message.
+ * @param CAN to select the CAN peripheral.
+ * @param FIFONum Receive DATFIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @param RxMessage pointer to a structure receive message which contains
+ * CAN Id, CAN DLC, CAN datas and FMI number.
+ */
+void CAN_ReceiveMessage(CAN_Module* CANx, uint8_t FIFONum, CanRxMessage* RxMessage)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FIFO(FIFONum));
+ /* Get the Id */
+ RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONum].RMI;
+ if (RxMessage->IDE == CAN_Standard_Id)
+ {
+ RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONum].RMI >> 21);
+ }
+ else
+ {
+ RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONum].RMI >> 3);
+ }
+
+ RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONum].RMI;
+ /* Get the DLC */
+ RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONum].RMDT;
+ /* Get the FMI */
+ RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDT >> 8);
+ /* Get the data field */
+ RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONum].RMDL;
+ RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDL >> 8);
+ RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDL >> 16);
+ RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDL >> 24);
+ RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONum].RMDH;
+ RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDH >> 8);
+ RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDH >> 16);
+ RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDH >> 24);
+ /* Release the DATFIFO */
+ /* Release FIFO0 */
+ if (FIFONum == CAN_FIFO0)
+ {
+ CANx->RFF0 |= CAN_RFF0_RFFOM0;
+ }
+ /* Release FIFO1 */
+ else /* FIFONum == CAN_FIFO1 */
+ {
+ CANx->RFF1 |= CAN_RFF1_RFFOM1;
+ }
+}
+
+/**
+ * @brief Releases the specified DATFIFO.
+ * @param CAN to select the CAN peripheral.
+ * @param FIFONum DATFIFO to release, CAN_FIFO0 or CAN_FIFO1.
+ */
+void CAN_ReleaseFIFO(CAN_Module* CANx, uint8_t FIFONum)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FIFO(FIFONum));
+ /* Release FIFO0 */
+ if (FIFONum == CAN_FIFO0)
+ {
+ CANx->RFF0 |= CAN_RFF0_RFFOM0;
+ }
+ /* Release FIFO1 */
+ else /* FIFONum == CAN_FIFO1 */
+ {
+ CANx->RFF1 |= CAN_RFF1_RFFOM1;
+ }
+}
+
+/**
+ * @brief Returns the number of pending messages.
+ * @param CAN to select the CAN peripheral.
+ * @param FIFONum Receive DATFIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @return NbMessage : which is the number of pending message.
+ */
+uint8_t CAN_PendingMessage(CAN_Module* CANx, uint8_t FIFONum)
+{
+ uint8_t message_pending = 0;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FIFO(FIFONum));
+ if (FIFONum == CAN_FIFO0)
+ {
+ message_pending = (uint8_t)(CANx->RFF0 & (uint32_t)0x03);
+ }
+ else if (FIFONum == CAN_FIFO1)
+ {
+ message_pending = (uint8_t)(CANx->RFF1 & (uint32_t)0x03);
+ }
+ else
+ {
+ message_pending = 0;
+ }
+ return message_pending;
+}
+
+/**
+ * @brief Select the CAN Operation mode.
+ * @param CAN to select the CAN peripheral.
+ * @param CAN_OperatingMode CAN Operating Mode. This parameter can be one
+ * of @ref CAN_operating_mode enumeration.
+ * @return status of the requested mode which can be
+ * - CAN_ModeSTS_Failed CAN failed entering the specific mode
+ * - CAN_ModeSTS_Success CAN Succeed entering the specific mode
+
+ */
+uint8_t CAN_OperatingModeReq(CAN_Module* CANx, uint8_t CAN_OperatingMode)
+{
+ uint8_t status = CAN_ModeSTS_Failed;
+
+ /* Timeout for INAK or also for SLAK bits*/
+ uint32_t timeout = INIAK_TIMEOUT;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode));
+
+ if (CAN_OperatingMode == CAN_Operating_InitMode)
+ {
+ /* Request initialisation */
+ CANx->MCTRL = (uint32_t)((CANx->MCTRL & (uint32_t)(~(uint32_t)CAN_MCTRL_SLPRQ)) | CAN_MCTRL_INIRQ);
+
+ /* Wait the acknowledge */
+ while (((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_INIAK) && (timeout != 0))
+ {
+ timeout--;
+ }
+ if ((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_INIAK)
+ {
+ status = CAN_ModeSTS_Failed;
+ }
+ else
+ {
+ status = CAN_ModeSTS_Success;
+ }
+ }
+ else if (CAN_OperatingMode == CAN_Operating_NormalMode)
+ {
+ /* Request leave initialisation and sleep mode and enter Normal mode */
+ CANx->MCTRL &= (uint32_t)(~(CAN_MCTRL_SLPRQ | CAN_MCTRL_INIRQ));
+
+ /* Wait the acknowledge */
+ while (((CANx->MSTS & CAN_MODE_MASK) != 0) && (timeout != 0))
+ {
+ timeout--;
+ }
+ if ((CANx->MSTS & CAN_MODE_MASK) != 0)
+ {
+ status = CAN_ModeSTS_Failed;
+ }
+ else
+ {
+ status = CAN_ModeSTS_Success;
+ }
+ }
+ else if (CAN_OperatingMode == CAN_Operating_SleepMode)
+ {
+ /* Request Sleep mode */
+ CANx->MCTRL = (uint32_t)((CANx->MCTRL & (uint32_t)(~(uint32_t)CAN_MCTRL_INIRQ)) | CAN_MCTRL_SLPRQ);
+
+ /* Wait the acknowledge */
+ while (((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_SLPAK) && (timeout != 0))
+ {
+ timeout--;
+ }
+ if ((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_SLPAK)
+ {
+ status = CAN_ModeSTS_Failed;
+ }
+ else
+ {
+ status = CAN_ModeSTS_Success;
+ }
+ }
+ else
+ {
+ status = CAN_ModeSTS_Failed;
+ }
+
+ return (uint8_t)status;
+}
+
+/**
+ * @brief Enters the low power mode.
+ * @param CAN to select the CAN peripheral.
+ * @return status: CAN_SLEEP_Ok if sleep entered, CAN_SLEEP_Failed in an
+ * other case.
+ */
+uint8_t CAN_EnterSleep(CAN_Module* CANx)
+{
+ uint8_t sleepstatus = CAN_SLEEP_Failed;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Request Sleep mode */
+ CANx->MCTRL = (((CANx->MCTRL) & (uint32_t)(~(uint32_t)CAN_MCTRL_INIRQ)) | CAN_MCTRL_SLPRQ);
+
+ /* Sleep mode status */
+ if ((CANx->MSTS & (CAN_MSTS_SLPAK | CAN_MSTS_INIAK)) == CAN_MSTS_SLPAK)
+ {
+ /* Sleep mode not entered */
+ sleepstatus = CAN_SLEEP_Ok;
+ }
+ /* return sleep mode status */
+ return (uint8_t)sleepstatus;
+}
+
+/**
+ * @brief Wakes the CAN up.
+ * @param CAN to select the CAN peripheral.
+ * @return status: CAN_WKU_Ok if sleep mode left, CAN_WKU_Failed in an
+ * other case.
+ */
+uint8_t CAN_WakeUp(CAN_Module* CANx)
+{
+ uint32_t wait_slak = SLPAK_TIMEOUT;
+ uint8_t wakeupstatus = CAN_WKU_Failed;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Wake up request */
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_SLPRQ;
+
+ /* Sleep mode status */
+ while (((CANx->MSTS & CAN_MSTS_SLPAK) == CAN_MSTS_SLPAK) && (wait_slak != 0x00))
+ {
+ wait_slak--;
+ }
+ if ((CANx->MSTS & CAN_MSTS_SLPAK) != CAN_MSTS_SLPAK)
+ {
+ /* wake up done : Sleep mode exited */
+ wakeupstatus = CAN_WKU_Ok;
+ }
+ /* return wakeup status */
+ return (uint8_t)wakeupstatus;
+}
+
+/**
+ * @brief Returns the CANx's last error code (LEC).
+ * @param CAN to select the CAN peripheral.
+ * @return CAN_ErrorCode: specifies the Error code :
+ * - CAN_ERRORCODE_NoErr No Error
+ * - CAN_ERRORCODE_StuffErr Stuff Error
+ * - CAN_ERRORCODE_FormErr Form Error
+ * - CAN_ERRORCODE_ACKErr Acknowledgment Error
+ * - CAN_ERRORCODE_BitRecessiveErr Bit Recessive Error
+ * - CAN_ERRORCODE_BitDominantErr Bit Dominant Error
+ * - CAN_ERRORCODE_CRCErr CRC Error
+ * - CAN_ERRORCODE_SoftwareSetErr Software Set Error
+ */
+
+uint8_t CAN_GetLastErrCode(CAN_Module* CANx)
+{
+ uint8_t errorcode = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Get the error code*/
+ errorcode = (((uint8_t)CANx->ESTS) & (uint8_t)CAN_ESTS_LEC);
+
+ /* Return the error code*/
+ return errorcode;
+}
+/**
+ * @brief Returns the CANx Receive Error Counter (REC).
+ * @note In case of an error during reception, this counter is incremented
+ * by 1 or by 8 depending on the error condition as defined by the CAN
+ * standard. After every successful reception, the counter is
+ * decremented by 1 or reset to 120 if its value was higher than 128.
+ * When the counter value exceeds 127, the CAN controller enters the
+ * error passive state.
+ * @param CANx to to select the CAN peripheral.
+ * @return CAN Receive Error Counter.
+ */
+uint8_t CAN_GetReceiveErrCounter(CAN_Module* CANx)
+{
+ uint8_t counter = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Get the Receive Error Counter*/
+ counter = (uint8_t)((CANx->ESTS & CAN_ESTS_RXEC) >> 24);
+
+ /* Return the Receive Error Counter*/
+ return counter;
+}
+
+/**
+ * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
+ * @param CAN to to select the CAN peripheral.
+ * @return LSB of the 9-bit CAN Transmit Error Counter.
+ */
+uint8_t CAN_GetLSBTransmitErrCounter(CAN_Module* CANx)
+{
+ uint8_t counter = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
+ counter = (uint8_t)((CANx->ESTS & CAN_ESTS_TXEC) >> 16);
+
+ /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
+ return counter;
+}
+
+/**
+ * @brief Enables or disables the specified CANx interrupts.
+ * @param CAN to select the CAN peripheral.
+ * @param CAN_INT specifies the CAN interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * - CAN_INT_TME,
+ * - CAN_INT_FMP0,
+ * - CAN_INT_FF0,
+ * - CAN_INT_FOV0,
+ * - CAN_INT_FMP1,
+ * - CAN_INT_FF1,
+ * - CAN_INT_FOV1,
+ * - CAN_INT_EWG,
+ * - CAN_INT_EPV,
+ * - CAN_INT_LEC,
+ * - CAN_INT_ERR,
+ * - CAN_INT_WKU or
+ * - CAN_INT_SLK.
+ * @param Cmd new state of the CAN interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void CAN_INTConfig(CAN_Module* CANx, uint32_t CAN_INT, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_INT(CAN_INT));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected CANx interrupt */
+ CANx->INTE |= CAN_INT;
+ }
+ else
+ {
+ /* Disable the selected CANx interrupt */
+ CANx->INTE &= ~CAN_INT;
+ }
+}
+/**
+ * @brief Checks whether the specified CAN flag is set or not.
+ * @param CAN to select the CAN peripheral.
+ * @param CAN_FLAG specifies the flag to check.
+ * This parameter can be one of the following flags:
+ * - CAN_FLAG_EWGFL
+ * - CAN_FLAG_EPVFL
+ * - CAN_FLAG_BOFFL
+ * - CAN_FLAG_RQCPM0
+ * - CAN_FLAG_RQCPM1
+ * - CAN_FLAG_RQCPM2
+ * - CAN_FLAG_FFMP1
+ * - CAN_FLAG_FFULL1
+ * - CAN_FLAG_FFOVR1
+ * - CAN_FLAG_FFMP0
+ * - CAN_FLAG_FFULL0
+ * - CAN_FLAG_FFOVR0
+ * - CAN_FLAG_WKU
+ * - CAN_FLAG_SLAK
+ * - CAN_FLAG_LEC
+ * @return The new state of CAN_FLAG (SET or RESET).
+ */
+FlagStatus CAN_GetFlagSTS(CAN_Module* CANx, uint32_t CAN_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_GET_FLAG(CAN_FLAG));
+
+ if ((CAN_FLAG & CAN_FLAGS_ESTS) != (uint32_t)RESET)
+ {
+ /* Check the status of the specified CAN flag */
+ if ((CANx->ESTS & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ else if ((CAN_FLAG & CAN_FLAGS_MSTS) != (uint32_t)RESET)
+ {
+ /* Check the status of the specified CAN flag */
+ if ((CANx->MSTS & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ else if ((CAN_FLAG & CAN_FLAGS_TSTS) != (uint32_t)RESET)
+ {
+ /* Check the status of the specified CAN flag */
+ if ((CANx->TSTS & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ else if ((CAN_FLAG & CAN_FLAGS_RFF0) != (uint32_t)RESET)
+ {
+ /* Check the status of the specified CAN flag */
+ if ((CANx->RFF0 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ else /* if (CAN_FLAG & CAN_FLAGS_RFF1 != (uint32_t)RESET) */
+ {
+ /* Check the status of the specified CAN flag */
+ if ((uint32_t)(CANx->RFF1 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ /* Return the CAN_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the CAN's pending flags.
+ * @param CAN to select the CAN peripheral.
+ * @param CAN_FLAG specifies the flag to clear.
+ * This parameter can be one of the following flags:
+ * - CAN_FLAG_RQCPM0
+ * - CAN_FLAG_RQCPM1
+ * - CAN_FLAG_RQCPM2
+ * - CAN_FLAG_FFULL1
+ * - CAN_FLAG_FFOVR1
+ * - CAN_FLAG_FFULL0
+ * - CAN_FLAG_FFOVR0
+ * - CAN_FLAG_WKU
+ * - CAN_FLAG_SLAK
+ * - CAN_FLAG_LEC
+ */
+void CAN_ClearFlag(CAN_Module* CANx, uint32_t CAN_FLAG)
+{
+ uint32_t flagtmp = 0;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));
+
+ if (CAN_FLAG == CAN_FLAG_LEC) /* ESTS register */
+ {
+ /* Clear the selected CAN flags */
+ CANx->ESTS = (uint32_t)RESET;
+ }
+ else /* MSTS or TSTS or RFF0 or RFF1 */
+ {
+ flagtmp = CAN_FLAG & 0x000FFFFF;
+
+ if ((CAN_FLAG & CAN_FLAGS_RFF0) != (uint32_t)RESET)
+ {
+ /* Receive Flags */
+ CANx->RFF0 = (uint32_t)(flagtmp);
+ }
+ else if ((CAN_FLAG & CAN_FLAGS_RFF1) != (uint32_t)RESET)
+ {
+ /* Receive Flags */
+ CANx->RFF1 = (uint32_t)(flagtmp);
+ }
+ else if ((CAN_FLAG & CAN_FLAGS_TSTS) != (uint32_t)RESET)
+ {
+ /* Transmit Flags */
+ CANx->TSTS = (uint32_t)(flagtmp);
+ }
+ else /* if ((CAN_FLAG & CAN_FLAGS_MSTS)!=(uint32_t)RESET) */
+ {
+ /* Operating mode Flags */
+ CANx->MSTS = (uint32_t)(flagtmp);
+ }
+ }
+}
+
+/**
+ * @brief Checks whether the specified CANx interrupt has occurred or not.
+ * @param CAN to select the CAN peripheral.
+ * @param CAN_INT specifies the CAN interrupt source to check.
+ * This parameter can be one of the following flags:
+ * - CAN_INT_TME
+ * - CAN_INT_FMP0
+ * - CAN_INT_FF0
+ * - CAN_INT_FOV0
+ * - CAN_INT_FMP1
+ * - CAN_INT_FF1
+ * - CAN_INT_FOV1
+ * - CAN_INT_WKU
+ * - CAN_INT_SLK
+ * - CAN_INT_EWG
+ * - CAN_INT_EPV
+ * - CAN_INT_BOF
+ * - CAN_INT_LEC
+ * - CAN_INT_ERR
+ * @return The current state of CAN_INT (SET or RESET).
+ */
+INTStatus CAN_GetIntStatus(CAN_Module* CANx, uint32_t CAN_INT)
+{
+ INTStatus itstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_INT(CAN_INT));
+
+ /* check the enable interrupt bit */
+ if ((CANx->INTE & CAN_INT) != RESET)
+ {
+ /* in case the Interrupt is enabled, .... */
+ switch (CAN_INT)
+ {
+ case CAN_INT_TME:
+ /* Check CAN_TSTS_RQCPx bits */
+ itstatus = CheckINTStatus(CANx->TSTS, CAN_TSTS_RQCPM0 | CAN_TSTS_RQCPM1 | CAN_TSTS_RQCPM2);
+ break;
+ case CAN_INT_FMP0:
+ /* Check CAN_RFF0_FFMP0 bit */
+ itstatus = CheckINTStatus(CANx->RFF0, CAN_RFF0_FFMP0);
+ break;
+ case CAN_INT_FF0:
+ /* Check CAN_RFF0_FFULL0 bit */
+ itstatus = CheckINTStatus(CANx->RFF0, CAN_RFF0_FFULL0);
+ break;
+ case CAN_INT_FOV0:
+ /* Check CAN_RFF0_FFOVR0 bit */
+ itstatus = CheckINTStatus(CANx->RFF0, CAN_RFF0_FFOVR0);
+ break;
+ case CAN_INT_FMP1:
+ /* Check CAN_RFF1_FFMP1 bit */
+ itstatus = CheckINTStatus(CANx->RFF1, CAN_RFF1_FFMP1);
+ break;
+ case CAN_INT_FF1:
+ /* Check CAN_RFF1_FFULL1 bit */
+ itstatus = CheckINTStatus(CANx->RFF1, CAN_RFF1_FFULL1);
+ break;
+ case CAN_INT_FOV1:
+ /* Check CAN_RFF1_FFOVR1 bit */
+ itstatus = CheckINTStatus(CANx->RFF1, CAN_RFF1_FFOVR1);
+ break;
+ case CAN_INT_WKU:
+ /* Check CAN_MSTS_WKUINT bit */
+ itstatus = CheckINTStatus(CANx->MSTS, CAN_MSTS_WKUINT);
+ break;
+ case CAN_INT_SLK:
+ /* Check CAN_MSTS_SLAKINT bit */
+ itstatus = CheckINTStatus(CANx->MSTS, CAN_MSTS_SLAKINT);
+ break;
+ case CAN_INT_EWG:
+ /* Check CAN_ESTS_EWGFL bit */
+ itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_EWGFL);
+ break;
+ case CAN_INT_EPV:
+ /* Check CAN_ESTS_EPVFL bit */
+ itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_EPVFL);
+ break;
+ case CAN_INT_BOF:
+ /* Check CAN_ESTS_BOFFL bit */
+ itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_BOFFL);
+ break;
+ case CAN_INT_LEC:
+ /* Check CAN_ESTS_LEC bit */
+ itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_LEC);
+ break;
+ case CAN_INT_ERR:
+ /* Check CAN_MSTS_ERRINT bit */
+ itstatus = CheckINTStatus(CANx->MSTS, CAN_MSTS_ERRINT);
+ break;
+ default:
+ /* in case of error, return RESET */
+ itstatus = RESET;
+ break;
+ }
+ }
+ else
+ {
+ /* in case the Interrupt is not enabled, return RESET */
+ itstatus = RESET;
+ }
+
+ /* Return the CAN_INT status */
+ return itstatus;
+}
+
+/**
+ * @brief Clears the CANx's interrupt pending bits.
+ * @param CAN to select the CAN peripheral.
+ * @param CAN_INT specifies the interrupt pending bit to clear.
+ * - CAN_INT_TME
+ * - CAN_INT_FF0
+ * - CAN_INT_FOV0
+ * - CAN_INT_FF1
+ * - CAN_INT_FOV1
+ * - CAN_INT_WKU
+ * - CAN_INT_SLK
+ * - CAN_INT_EWG
+ * - CAN_INT_EPV
+ * - CAN_INT_BOF
+ * - CAN_INT_LEC
+ * - CAN_INT_ERR
+ */
+void CAN_ClearINTPendingBit(CAN_Module* CANx, uint32_t CAN_INT)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_CLEAR_INT(CAN_INT));
+
+ switch (CAN_INT)
+ {
+ case CAN_INT_TME:
+ /* Clear CAN_TSTS_RQCPx (rc_w1)*/
+ CANx->TSTS = CAN_TSTS_RQCPM0 | CAN_TSTS_RQCPM1 | CAN_TSTS_RQCPM2;
+ break;
+ case CAN_INT_FF0:
+ /* Clear CAN_RFF0_FFULL0 (rc_w1)*/
+ CANx->RFF0 = CAN_RFF0_FFULL0;
+ break;
+ case CAN_INT_FOV0:
+ /* Clear CAN_RFF0_FFOVR0 (rc_w1)*/
+ CANx->RFF0 = CAN_RFF0_FFOVR0;
+ break;
+ case CAN_INT_FF1:
+ /* Clear CAN_RFF1_FFULL1 (rc_w1)*/
+ CANx->RFF1 = CAN_RFF1_FFULL1;
+ break;
+ case CAN_INT_FOV1:
+ /* Clear CAN_RFF1_FFOVR1 (rc_w1)*/
+ CANx->RFF1 = CAN_RFF1_FFOVR1;
+ break;
+ case CAN_INT_WKU:
+ /* Clear CAN_MSTS_WKUINT (rc_w1)*/
+ CANx->MSTS = CAN_MSTS_WKUINT;
+ break;
+ case CAN_INT_SLK:
+ /* Clear CAN_MSTS_SLAKINT (rc_w1)*/
+ CANx->MSTS = CAN_MSTS_SLAKINT;
+ break;
+ case CAN_INT_EWG:
+ /* Clear CAN_MSTS_ERRINT (rc_w1) */
+ CANx->MSTS = CAN_MSTS_ERRINT;
+ /* Note : the corresponding Flag is cleared by hardware depending
+ of the CAN Bus status*/
+ break;
+ case CAN_INT_EPV:
+ /* Clear CAN_MSTS_ERRINT (rc_w1) */
+ CANx->MSTS = CAN_MSTS_ERRINT;
+ /* Note : the corresponding Flag is cleared by hardware depending
+ of the CAN Bus status*/
+ break;
+ case CAN_INT_BOF:
+ /* Clear CAN_MSTS_ERRINT (rc_w1) */
+ CANx->MSTS = CAN_MSTS_ERRINT;
+ /* Note : the corresponding Flag is cleared by hardware depending
+ of the CAN Bus status*/
+ break;
+ case CAN_INT_LEC:
+ /* Clear LEC bits */
+ CANx->ESTS = RESET;
+ /* Clear CAN_MSTS_ERRINT (rc_w1) */
+ CANx->MSTS = CAN_MSTS_ERRINT;
+ break;
+ case CAN_INT_ERR:
+ /*Clear LEC bits */
+ CANx->ESTS = RESET;
+ /* Clear CAN_MSTS_ERRINT (rc_w1) */
+ CANx->MSTS = CAN_MSTS_ERRINT;
+ /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending
+ of the CAN Bus status*/
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Checks whether the CAN interrupt has occurred or not.
+ * @param CAN_Reg specifies the CAN interrupt register to check.
+ * @param Int_Bit specifies the interrupt source bit to check.
+ * @return The new state of the CAN Interrupt (SET or RESET).
+ */
+static INTStatus CheckINTStatus(uint32_t CAN_Reg, uint32_t Int_Bit)
+{
+ INTStatus pendingbitstatus = RESET;
+
+ if ((CAN_Reg & Int_Bit) != (uint32_t)RESET)
+ {
+ /* CAN_INT is set */
+ pendingbitstatus = SET;
+ }
+ else
+ {
+ /* CAN_INT is reset */
+ pendingbitstatus = RESET;
+ }
+ return pendingbitstatus;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_comp.c b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_comp.c
new file mode 100644
index 0000000000..59855d075f
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_comp.c
@@ -0,0 +1,385 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_comp.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l40x_comp.h"
+#include "n32l40x_rcc.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup COMP
+ * @brief COMP driver modules
+ * @{
+ */
+
+/** @addtogroup COMP_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup COMP_Private_Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup COMP_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup COMP_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup COMP_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup COMP_Private_Functions
+ * @{
+ */
+#define SetBitMsk(reg, bit, msk) ((reg) = (((reg) & ~(msk)) | (bit)))
+#define ClrBit(reg, bit) ((reg) &= ~(bit))
+#define SetBit(reg, bit) ((reg) |= (bit))
+#define GetBit(reg, bit) ((reg) & (bit))
+/**
+ * @brief Deinitializes the COMP peripheral registers to their default reset values.
+ */
+void COMP_DeInit(void)
+{
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP, DISABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP_FILT, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP_FILT, DISABLE);
+}
+void COMP_StructInit(COMP_InitType* COMP_InitStruct)
+{
+ COMP_InitStruct->LowPoweMode =false; // only COMP1 have this bit
+ COMP_InitStruct->InpDacConnect = false; // only COMP1 have this bit
+
+ COMP_InitStruct->Blking = COMP_CTRL_BLKING_NO; /*see @ref COMP_CTRL_BLKING */
+
+ COMP_InitStruct->Hyst = COMP_CTRL_HYST_NO; // see @COMPx_CTRL_HYST_MASK
+
+ COMP_InitStruct->PolRev = false; // out polarity reverse
+
+ COMP_InitStruct->OutTrig = COMP1_CTRL_OUTSEL_NC;
+ COMP_InitStruct->InpSel = COMP1_CTRL_INPSEL_FLOAT; //Float as same with comp1 and comp2
+ COMP_InitStruct->InmSel = COMP2_CTRL_INMSEL_NC; //NC as same with comp1 and comp2s
+ COMP_InitStruct->FilterEn=false;
+ COMP_InitStruct->ClkPsc=0;
+ COMP_InitStruct->SampWindow=0;
+ COMP_InitStruct->Thresh=0;
+ COMP_InitStruct->En = false;
+}
+void COMP_Init(COMPX COMPx, COMP_InitType* COMP_InitStruct)
+{
+ COMP_SingleType* pCS;
+ __IO uint32_t tmp;
+ if (COMPx == COMP1)
+ pCS = &COMP->Cmp1;
+ else
+ pCS = &COMP->Cmp2;
+
+ // filter
+ tmp = pCS->FILC;
+ SetBitMsk(tmp, COMP_InitStruct->SampWindow << 6, COMP_FILC_SAMPW_MASK);
+ SetBitMsk(tmp, COMP_InitStruct->Thresh << 1, COMP_FILC_THRESH_MASK);
+ SetBitMsk(tmp, COMP_InitStruct->FilterEn << 0, COMP_FILC_FILEN_MASK);
+ pCS->FILC = tmp;
+ // filter psc
+ pCS->FILP = COMP_InitStruct->ClkPsc;
+
+ // ctrl
+ tmp = pCS->CTRL;
+ if (COMPx == COMP1)
+ {
+ if (COMP_InitStruct->InpDacConnect)
+ SetBit(tmp, COMP1_CTRL_INPDAC_MASK);
+ else
+ ClrBit(tmp, COMP1_CTRL_INPDAC_MASK);
+ if (COMP_InitStruct->LowPoweMode)
+ SetBit(tmp, COMP1_CTRL_PWRMODE_MASK);
+ else
+ ClrBit(tmp, COMP1_CTRL_PWRMODE_MASK);
+ }
+ SetBitMsk(tmp, COMP_InitStruct->Blking, COMP_CTRL_BLKING_MASK);
+ SetBitMsk(tmp, COMP_InitStruct->Hyst, COMPx_CTRL_HYST_MASK);
+ if (COMP_InitStruct->PolRev)
+ SetBit(tmp, COMP_POL_MASK);
+ else
+ ClrBit(tmp, COMP_POL_MASK);
+ SetBitMsk(tmp, COMP_InitStruct->OutTrig, COMP_CTRL_OUTSEL_MASK);
+ SetBitMsk(tmp, COMP_InitStruct->InpSel, COMP_CTRL_INPSEL_MASK);
+ SetBitMsk(tmp, COMP_InitStruct->InmSel, COMP_CTRL_INMSEL_MASK);
+ if (COMP_InitStruct->En)
+ SetBit(tmp, COMP_CTRL_EN_MASK);
+ else
+ ClrBit(tmp, COMP_CTRL_EN_MASK);
+ pCS->CTRL = tmp;
+}
+void COMP_Enable(COMPX COMPx, FunctionalState en)
+{
+ if (COMPx == COMP1)
+ {
+ if (en)
+ SetBit(COMP->Cmp1.CTRL, COMP_CTRL_EN_MASK);
+ else
+ ClrBit(COMP->Cmp1.CTRL, COMP_CTRL_EN_MASK);
+ }
+ else
+ {
+ if (en)
+ SetBit(COMP->Cmp2.CTRL, COMP_CTRL_EN_MASK);
+ else
+ ClrBit(COMP->Cmp2.CTRL, COMP_CTRL_EN_MASK);
+ }
+}
+
+void COMP_SetInpSel(COMPX COMPx, COMP_CTRL_INPSEL VpSel)
+{
+ __IO uint32_t tmp;
+ if (COMPx == COMP1)
+ tmp = COMP->Cmp1.CTRL;
+ else
+ tmp = COMP->Cmp2.CTRL;
+
+ SetBitMsk(tmp, VpSel, COMP_CTRL_INPSEL_MASK);
+
+ if (COMPx == COMP1)
+ COMP->Cmp1.CTRL = tmp;
+ else
+ COMP->Cmp2.CTRL = tmp;
+}
+void COMP_SetInmSel(COMPX COMPx, COMP_CTRL_INMSEL VmSel)
+{
+ __IO uint32_t tmp;
+ if (COMPx == COMP1)
+ tmp = COMP->Cmp1.CTRL;
+ else
+ tmp = COMP->Cmp2.CTRL;
+
+ SetBitMsk(tmp, VmSel, COMP_CTRL_INMSEL_MASK);
+
+ if (COMPx == COMP1)
+ COMP->Cmp1.CTRL = tmp;
+ else
+ COMP->Cmp2.CTRL = tmp;
+
+}
+void COMP_SetOutTrig(COMPX COMPx, COMP_CTRL_OUTTRIG OutTrig)
+{
+ __IO uint32_t tmp;
+ if (COMPx == COMP1)
+ tmp = COMP->Cmp1.CTRL;
+ else
+ tmp = COMP->Cmp2.CTRL;
+
+ SetBitMsk(tmp, OutTrig, COMP_CTRL_OUTSEL_MASK);
+
+ if (COMPx == COMP1)
+ COMP->Cmp1.CTRL = tmp;
+ else
+ COMP->Cmp2.CTRL = tmp;
+}
+
+// return see @COMP_INTSTS_CMPIS
+uint32_t COMP_GetIntSts(void)
+{
+ return COMP->INTSTS;
+}
+// parma range see @COMP_VREFSCL
+// Vv2Trim,Vv1Trim max 63
+void COMP_SetRefScl(uint8_t Vv2Trim, bool Vv2En, uint8_t Vv1Trim, bool Vv1En)
+{
+ __IO uint32_t tmp = 0;
+
+ SetBitMsk(tmp, Vv2Trim << 8, COMP_VREFSCL_VV2TRM_MSK);
+ SetBitMsk(tmp, Vv2En << 7, COMP_VREFSCL_VV2EN_MSK);
+ SetBitMsk(tmp, Vv1Trim << 1, COMP_VREFSCL_VV1TRM_MSK);
+ SetBitMsk(tmp, Vv1En << 0, COMP_VREFSCL_VV1EN_MSK);
+
+ COMP->VREFSCL = tmp;
+}
+// SET when comp out 1
+// RESET when comp out 0
+FlagStatus COMP_GetOutStatus(COMPX COMPx)
+{
+ if (COMPx == COMP1)
+ return (COMP->Cmp1.CTRL & COMP_CTRL_OUT_MASK) ? SET : RESET;
+ else
+ return (COMP->Cmp2.CTRL & COMP_CTRL_OUT_MASK) ? SET : RESET;
+}
+// get one comp interrupt flags
+FlagStatus COMP_GetIntStsOneComp(COMPX COMPx)
+{
+ return (COMP_GetIntSts() & (0x01 << COMPx)) ? SET : RESET;
+}
+
+// Lock see @COMP_LOCK
+void COMP_SetLock(uint32_t Lock)
+{
+ COMP->LOCK = Lock;
+}
+// IntEn see @COMP_INTEN_CMPIEN
+void COMP_SetIntEn(uint32_t IntEn)
+{
+ COMP->INTEN = IntEn;
+}
+// set comp2 xor output with comp1
+void COMP_CMP2XorOut(bool En)
+{
+ COMP->CMP2OSEL = (En==true)?0x1L:0x0L;
+}
+// set stop or lowpower mode that sel 32k clk
+void COMP_StopOrLowpower32KClkSel(bool En)
+{
+ COMP->LPCKSEL = (En==true)?0x1L:0x0L;
+}
+// set comp1 and comp2 component window compare mode
+void COMP_WindowModeEn(bool En)
+{
+ COMP->WINMODE = (En==true)?0x1L:0x0L;
+}
+
+
+/**
+ * @brief Set the COMP filter clock Prescaler value.
+ * @param COMPx where x can be 1 to 2 to select the COMP peripheral.
+ * @param FilPreVal Prescaler Value,Div clock = FilPreVal+1.
+ * @return void
+ */
+void COMP_SetFilterPrescaler(COMPX COMPx , uint16_t FilPreVal)
+{
+ if (COMPx == COMP1)
+ COMP->Cmp1.FILP=FilPreVal;
+ else
+ COMP->Cmp2.FILP=FilPreVal;
+}
+
+/**
+ * @brief Set the COMP filter control value.
+ * @param COMPx where x can be 1 to 2 to select the COMP peripheral.
+ * @param FilEn 1 for enable ,0 or disable
+ * @param TheresNum num under this value is noise
+ * @param SampPW total sample number in a window
+ * @return void
+ */
+void COMP_SetFilterControl(COMPX COMPx , uint8_t FilEn, uint8_t TheresNum , uint8_t SampPW)
+{
+ if (COMPx == COMP1)
+ COMP->Cmp1.FILC=(FilEn&COMP_FILC_FILEN_MASK)+((TheresNum<<1)&COMP_FILC_THRESH_MASK)+((SampPW<<6)&COMP_FILC_SAMPW_MASK);
+ else
+ COMP->Cmp2.FILC=(FilEn&COMP_FILC_FILEN_MASK)+((TheresNum<<1)&COMP_FILC_THRESH_MASK)+((SampPW<<6)&COMP_FILC_SAMPW_MASK);
+}
+
+/**
+ * @brief Set the COMP Hyst value.
+ * @param COMPx where x can be 1 to 2 to select the COMP peripheral.
+ * @param HYST specifies the HYST level.
+ * This parameter can be one of the following values:
+* @arg COMP_CTRL_HYST_NO Hyst disable
+* @arg COMP_CTRL_HYST_LOW Hyst level 5.1mV
+* @arg COMP_CTRL_HYST_MID Hyst level 15mV
+* @arg COMP_CTRL_HYST_HIGH Hyst level 25mV
+ * @return void
+ */
+void COMP_SetHyst(COMPX COMPx , COMP_CTRL_HYST HYST)
+{
+ uint32_t tmp;
+ if (COMPx == COMP1)
+ tmp=COMP->Cmp1.CTRL;
+ else
+ tmp=COMP->Cmp2.CTRL;
+
+ tmp&=~COMP_CTRL_HYST_HIGH;
+ tmp|=HYST;
+ if (COMPx == COMP1)
+ COMP->Cmp1.CTRL=tmp;
+ else
+ COMP->Cmp2.CTRL=tmp;
+}
+
+/**
+ * @brief Set the COMP Blanking source .
+ * @param COMPx where x can be 1 to 2 to select the COMP peripheral.
+ * @param BLK specifies the blanking source .
+ * This parameter can be one of the following values:
+* @arg COMP_CTRL_BLKING_NO Blanking disable
+* @arg COMP_CTRL_BLKING_TIM1_OC5 Blanking source TIM1_OC5
+* @arg COMP_CTRL_BLKING_TIM8_OC5 Blanking source TIM8_OC5
+ * @return void
+ */
+void COMP_SetBlanking(COMPX COMPx , COMP_CTRL_BLKING BLK)
+{
+ uint32_t tmp;
+ if (COMPx == COMP1)
+ tmp=COMP->Cmp1.CTRL;
+ else
+ tmp=COMP->Cmp2.CTRL;
+ tmp&=~(7<<16);
+ tmp|=BLK;
+ if (COMPx == COMP1)
+ COMP->Cmp1.CTRL=tmp;
+ else
+ COMP->Cmp2.CTRL=tmp;
+}
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_crc.c b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_crc.c
new file mode 100644
index 0000000000..b4bb9c69f1
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_crc.c
@@ -0,0 +1,227 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_crc.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l40x_crc.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CRC
+ * @brief CRC driver modules
+ * @{
+ */
+
+/** @addtogroup CRC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Private_Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Resets the CRC Data register (DAT).
+ */
+void CRC32_ResetCrc(void)
+{
+ /* Reset CRC generator */
+ CRC->CRC32CTRL = CRC32_CTRL_RESET;
+}
+
+/**
+ * @brief Computes the 32-bit CRC of a given data word(32-bit).
+ * @param Data data word(32-bit) to compute its CRC
+ * @return 32-bit CRC
+ */
+uint32_t CRC32_CalcCrc(uint32_t Data)
+{
+ CRC->CRC32DAT = Data;
+
+ return (CRC->CRC32DAT);
+}
+
+/**
+ * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
+ * @param pBuffer pointer to the buffer containing the data to be computed
+ * @param BufferLength length of the buffer to be computed
+ * @return 32-bit CRC
+ */
+uint32_t CRC32_CalcBufCrc(uint32_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t index = 0;
+
+ for (index = 0; index < BufferLength; index++)
+ {
+ CRC->CRC32DAT = pBuffer[index];
+ }
+ return (CRC->CRC32DAT);
+}
+
+/**
+ * @brief Returns the current CRC value.
+ * @return 32-bit CRC
+ */
+uint32_t CRC32_GetCrc(void)
+{
+ return (CRC->CRC32DAT);
+}
+
+/**
+ * @brief Stores a 8-bit data in the Independent Data(ID) register.
+ * @param IDValue 8-bit value to be stored in the ID register
+ */
+void CRC32_SetIDat(uint8_t IDValue)
+{
+ CRC->CRC32IDAT = IDValue;
+}
+
+/**
+ * @brief Returns the 8-bit data stored in the Independent Data(ID) register
+ * @return 8-bit value of the ID register
+ */
+uint8_t CRC32_GetIDat(void)
+{
+ return (CRC->CRC32IDAT);
+}
+
+// CRC16 add
+void __CRC16_SetLittleEndianFmt(void)
+{
+ CRC->CRC16CTRL = CRC16_CTRL_LITTLE | CRC->CRC16CTRL;
+}
+void __CRC16_SetBigEndianFmt(void)
+{
+ CRC->CRC16CTRL = CRC16_CTRL_BIG & CRC->CRC16CTRL;
+}
+void __CRC16_SetCleanEnable(void)
+{
+ CRC->CRC16CTRL = CRC16_CTRL_RESET | CRC->CRC16CTRL;
+}
+void __CRC16_SetCleanDisable(void)
+{
+ CRC->CRC16CTRL = CRC16_CTRL_NO_RESET & CRC->CRC16CTRL;
+}
+
+uint16_t __CRC16_CalcCrc(uint8_t Data)
+{
+ CRC->CRC16DAT = Data;
+ return (CRC->CRC16D);
+}
+
+void __CRC16_SetCrc(uint8_t Data)
+{
+ CRC->CRC16DAT = Data;
+}
+
+uint16_t __CRC16_GetCrc(void)
+{
+ return (CRC->CRC16D);
+}
+
+void __CRC16_SetLRC(uint8_t Data)
+{
+ CRC->LRC = Data;
+}
+
+uint8_t __CRC16_GetLRC(void)
+{
+ return (CRC->LRC);
+}
+
+uint16_t CRC16_CalcBufCrc(uint8_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t index = 0;
+
+ CRC->CRC16D = 0x00;
+ for (index = 0; index < BufferLength; index++)
+ {
+ CRC->CRC16DAT = pBuffer[index];
+ }
+ return (CRC->CRC16D);
+}
+
+uint16_t CRC16_CalcCRC(uint8_t Data)
+{
+ CRC->CRC16DAT = Data;
+
+ return (CRC->CRC16D);
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_dac.c b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_dac.c
new file mode 100644
index 0000000000..e389604b2f
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_dac.c
@@ -0,0 +1,357 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_dac.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l40x_dac.h"
+#include "n32l40x_rcc.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DAC
+ * @brief DAC driver modules
+ * @{
+ */
+
+/** @addtogroup DAC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Private_Defines
+ * @{
+ */
+
+/* CTRL register Mask */
+#define CTRL_CLEAR_MASK ((uint32_t)0x00000FFE)
+
+/* DAC Dual Channels SWTRIG masks */
+#define DUAL_SWTRIG_SET ((uint32_t)0x00000001)
+#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFE)
+
+/* DCH registers offsets */
+#define DR12CH_OFFSET ((uint32_t)0x00000008)
+
+/* DATO register offset */
+#define DATO_OFFSET ((uint32_t)0x0000002C)
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the DAC peripheral registers to their default reset values.
+ */
+void DAC_DeInit(void)
+{
+ /* Enable DAC reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_DAC, ENABLE);
+ /* Release DAC from reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_DAC, DISABLE);
+}
+
+/**
+ * @brief Initializes the DAC peripheral according to the specified
+ * parameters in the DAC_InitStruct.
+ * @param DAC_Channel the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1 DAC Channel1 selected
+ * @arg DAC_CHANNEL_2 DAC Channel2 selected
+ * @param DAC_InitStruct pointer to a DAC_InitType structure that
+ * contains the configuration information for the specified DAC channel.
+ */
+void DAC_Init(DAC_InitType* DAC_InitStruct)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;
+ /* Check the DAC parameters */
+ assert_param(IS_DAC_TRIGGER(DAC_InitStruct->Trigger));
+ assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->WaveGen));
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->LfsrUnMaskTriAmp));
+ assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->BufferOutput));
+ /*---------------------------- DAC CTRL Configuration --------------------------*/
+ /* Get the DAC CTRL value */
+ tmpreg1 = DAC->CTRL;
+ /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
+ tmpreg1 &= ~(CTRL_CLEAR_MASK );
+ /* Configure for the selected DAC channel: buffer output, trigger, wave generation,
+ mask/amplitude for wave generation */
+ /* Set TSELx and TENx bits according to Trigger value */
+ /* Set WAVEx bits according to WaveGen value */
+ /* Set MAMPx bits according to LfsrUnMaskTriAmp value */
+ /* Set BOFFx bit according to BufferOutput value */
+ tmpreg2 = (DAC_InitStruct->Trigger | DAC_InitStruct->WaveGen | DAC_InitStruct->LfsrUnMaskTriAmp
+ | DAC_InitStruct->BufferOutput);
+ /* Calculate CTRL register value depending on DAC_Channel */
+ tmpreg1 |= tmpreg2 ;
+ /* Write to DAC CTRL */
+ DAC->CTRL = tmpreg1;
+}
+
+/**
+ * @brief Fills each DAC_InitStruct member with its default value.
+ * @param DAC_InitStruct pointer to a DAC_InitType structure which will
+ * be initialized.
+ */
+void DAC_ClearStruct(DAC_InitType* DAC_InitStruct)
+{
+ /*--------------- Reset DAC init structure parameters values -----------------*/
+ /* Initialize the Trigger member */
+ DAC_InitStruct->Trigger = DAC_TRG_NONE;
+ /* Initialize the WaveGen member */
+ DAC_InitStruct->WaveGen = DAC_WAVEGEN_NONE;
+ /* Initialize the LfsrUnMaskTriAmp member */
+ DAC_InitStruct->LfsrUnMaskTriAmp = DAC_UNMASK_LFSRBIT0;
+ /* Initialize the BufferOutput member */
+ DAC_InitStruct->BufferOutput = DAC_BUFFOUTPUT_ENABLE;
+}
+
+/**
+ * @brief Enables or disables the specified DAC channel.
+ * @param DAC_Channel the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1 DAC Channel1 selected
+ * @arg DAC_CHANNEL_2 DAC Channel2 selected
+ * @param Cmd new state of the DAC channel.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DAC_Enable(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected DAC channel */
+ DAC->CTRL |= DAC_CTRL_CHEN ;
+ }
+ else
+ {
+ /* Disable the selected DAC channel */
+ DAC->CTRL &= ~DAC_CTRL_CHEN ;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified DAC channel DMA request.
+ * @param DAC_Channel the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1 DAC Channel1 selected
+ * @arg DAC_CHANNEL_2 DAC Channel2 selected
+ * @param Cmd new state of the selected DAC channel DMA request.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DAC_DmaEnable(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected DAC channel DMA request */
+ DAC->CTRL |= DAC_CTRL_DMAEN;
+ }
+ else
+ {
+ /* Disable the selected DAC channel DMA request */
+ DAC->CTRL &= ~DAC_CTRL_DMAEN;
+ }
+}
+
+/**
+ * @brief Enables or disables the selected DAC channel software trigger.
+ * @param DAC_Channel the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1 DAC Channel1 selected
+ * @arg DAC_CHANNEL_2 DAC Channel2 selected
+ * @param Cmd new state of the selected DAC channel software trigger.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DAC_SoftTrgEnable(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable software trigger for the selected DAC channel */
+ DAC->SOTTR |= DAC_SOTTR_TREN ;
+ }
+ else
+ {
+ /* Disable software trigger for the selected DAC channel */
+ DAC->SOTTR &= ~(DAC_SOTTR_TREN);
+ }
+}
+
+/**
+ * @brief Enables or disables simultaneously the two DAC channels software
+ * triggers.
+ * @param Cmd new state of the DAC channels software triggers.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DAC_SoftwareTrgEnable(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable software trigger for both DAC channels */
+ DAC->SOTTR |= DUAL_SWTRIG_SET;
+ }
+ else
+ {
+ /* Disable software trigger for both DAC channels */
+ DAC->SOTTR &= DUAL_SWTRIG_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the selected DAC channel wave generation.
+ * @param DAC_Channel the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1 DAC Channel1 selected
+ * @arg DAC_CHANNEL_2 DAC Channel2 selected
+ * @param DAC_Wave Specifies the wave type to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg DAC_WAVE_NOISE noise wave generation
+ * @arg DAC_WAVE_TRIANGLE triangle wave generation
+ * @param Cmd new state of the selected DAC channel wave generation.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DAC_WaveGenerationEnable(uint32_t DAC_Wave, FunctionalState Cmd)
+{
+ __IO uint32_t tmp = 0;
+ /* Check the parameters */
+ assert_param(IS_DAC_WAVE(DAC_Wave));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ tmp=DAC->CTRL;
+ tmp&=~(3<<6);
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected wave generation for the selected DAC channel */
+ tmp |= DAC_Wave;
+ }
+ else
+ {
+ /* Disable the selected wave generation for the selected DAC channel */
+ tmp&=~(3<<6);
+ }
+ DAC->CTRL =tmp;
+}
+
+/**
+ * @brief Set the specified data holding register value for DAC channel1.
+ * @param DAC_Align Specifies the data alignment for DAC channel1.
+ * This parameter can be one of the following values:
+ * @arg DAC_ALIGN_R_8BIT 8bit right data alignment selected
+ * @arg DAC_ALIGN_L_12BIT 12bit left data alignment selected
+ * @arg DAC_ALIGN_R_12BIT 12bit right data alignment selected
+ * @param Data Data to be loaded in the selected data holding register.
+ */
+void DAC_SetChData(uint32_t DAC_Align, uint16_t Data)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALIGN(DAC_Align));
+ assert_param(IS_DAC_DATA(Data));
+
+ tmp = (uint32_t)DAC_BASE;
+ tmp += DR12CH_OFFSET + DAC_Align;
+
+ /* Set the DAC channel1 selected data holding register */
+ *(__IO uint32_t*)tmp = Data;
+}
+
+
+
+
+
+/**
+ * @brief Returns the last data output value of the selected DAC channel.
+ * @param DAC_Channel the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1 DAC Channel1 selected
+ * @arg DAC_CHANNEL_2 DAC Channel2 selected
+ * @return The selected DAC channel data output value.
+ */
+uint16_t DAC_GetOutputDataVal(void)
+{
+ __IO uint32_t tmp = 0;
+
+ tmp = (uint32_t)DAC_BASE;
+ tmp += DATO_OFFSET;
+
+ /* Returns the DAC channel data output register value */
+ return (uint16_t)(*(__IO uint32_t*)tmp);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_dbg.c b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_dbg.c
new file mode 100644
index 0000000000..105800c779
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_dbg.c
@@ -0,0 +1,246 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_dbg.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l40x_dbg.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DBG
+ * @brief DBG driver modules
+ * @{
+ */
+
+/** @addtogroup DBGMCU_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Private_Defines
+ * @{
+ */
+
+#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Private_Functions
+ * @{
+ */
+
+
+void GetUCID(uint8_t *UCIDbuf)
+{
+ uint8_t num = 0;
+ uint32_t* ucid_addr = (void*)0;
+ uint32_t temp = 0;
+
+ ucid_addr = (uint32_t*)UCID_BASE;
+
+ for (num = 0; num < UCID_LENGTH;)
+ {
+ temp = *(__IO uint32_t*)(ucid_addr++);
+ UCIDbuf[num++] = (temp & 0xFF);
+ UCIDbuf[num++] = (temp & 0xFF00) >> 8;
+ UCIDbuf[num++] = (temp & 0xFF0000) >> 16;
+ UCIDbuf[num++] = (temp & 0xFF000000) >> 24;
+ }
+}
+
+/**
+ * @brief Returns the UID.
+ * @return UID
+ */
+
+void GetUID(uint8_t *UIDbuf)
+{
+ uint8_t num = 0;
+ uint32_t* uid_addr = (void*)0;
+ uint32_t temp = 0;
+
+ uid_addr = (uint32_t*)UID_BASE;
+
+ for (num = 0; num < UID_LENGTH;)
+ {
+ temp = *(__IO uint32_t*)(uid_addr++);
+ UIDbuf[num++] = (temp & 0xFF);
+ UIDbuf[num++] = (temp & 0xFF00) >> 8;
+ UIDbuf[num++] = (temp & 0xFF0000) >> 16;
+ UIDbuf[num++] = (temp & 0xFF000000) >> 24;
+ }
+}
+
+/**
+ * @brief Returns the DBGMCU_ID.
+ * @return DBGMCU_ID
+ */
+
+void GetDBGMCU_ID(uint8_t *DBGMCU_IDbuf)
+{
+ uint8_t num = 0;
+ uint32_t* dbgid_addr = (void*)0;
+ uint32_t temp = 0;
+
+ dbgid_addr = (uint32_t*)DBGMCU_ID_BASE;
+ for (num = 0; num < DBGMCU_ID_LENGTH;)
+ {
+ temp = *(__IO uint32_t*)(dbgid_addr++);
+ DBGMCU_IDbuf[num++] = (temp & 0xFF);
+ DBGMCU_IDbuf[num++] = (temp & 0xFF00) >> 8;
+ DBGMCU_IDbuf[num++] = (temp & 0xFF0000) >> 16;
+ DBGMCU_IDbuf[num++] = (temp & 0xFF000000) >> 24;
+ }
+}
+
+/**
+ * @brief Returns the device revision number.
+ * @return Device revision identifier
+ */
+uint32_t DBG_GetRevNum(void)
+{
+ return (DBG->ID & 0x00FF);
+}
+
+/**
+ * @brief Returns the device identifier.
+ * @return Device identifier
+ */
+uint32_t DBG_GetDevNum(void)
+{
+ uint32_t id = DBG->ID;
+ return ((id & 0x00F00000) >> 20) | ((id & 0xFF00) >> 4);
+}
+
+/**
+ * @brief Configures the specified peripheral and low power mode behavior
+ * when the MCU under Debug mode.
+ * @param DBG_Periph specifies the peripheral and low power mode.
+ * This parameter can be any combination of the following values:
+ * @arg DBG_SLEEP Keep debugger connection during SLEEP mode
+ * @arg DBG_STOP Keep debugger connection during STOP mode
+ * @arg DBG_STDBY Keep debugger connection during STANDBY mode
+ * @arg DBG_IWDG_STOP Debug IWDG stopped when Core is halted
+ * @arg DBG_WWDG_STOP Debug WWDG stopped when Core is halted
+ * @arg DBG_TIM1_STOP TIM1 counter stopped when Core is halted
+ * @arg DBG_TIM2_STOP TIM2 counter stopped when Core is halted
+ * @arg DBG_TIM3_STOP TIM3 counter stopped when Core is halted
+ * @arg DBG_TIM4_STOP TIM4 counter stopped when Core is halted
+ * @arg DBG_CAN_STOP Debug CAN stopped when Core is halted
+ * @arg DBG_I2C1SMBUS_TIMEOUT I2C1 SMBUS timeout mode stopped when Core is halted
+ * @arg DBG_I2C2SMBUS_TIMEOUT I2C2 SMBUS timeout mode stopped when Core is halted
+ * @arg DBG_TIM8_STOP TIM8 counter stopped when Core is halted
+ * @arg DBG_TIM5_STOP TIM5 counter stopped when Core is halted
+ * @arg DBG_TIM6_STOP TIM6 counter stopped when Core is halted
+ * @arg DBG_TIM7_STOP TIM7 counter stopped when Core is halted
+ * @arg DBG_TIM9_STOP TIM9 counter stopped when Core is halted
+
+ * @param Cmd new state of the specified peripheral in Debug mode.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DBG_ConfigPeriph(uint32_t DBG_Periph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_DBGMCU_PERIPH(DBG_Periph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ DBG->CTRL |= DBG_Periph;
+ }
+ else
+ {
+ DBG->CTRL &= ~DBG_Periph;
+ }
+}
+
+/**
+ * @brief Get FLASH size of this chip.
+ *
+ * @return FLASH size in bytes.
+ */
+uint32_t DBG_GetFlashSize(void)
+{
+ return (DBG->ID & 0x000F0000);
+}
+
+/**
+ * @brief Get SRAM size of this chip.
+ *
+ * @return SRAM size in bytes.
+ */
+uint32_t DBG_GetSramSize(void)
+{
+ return (((DBG->ID & 0xF0000000) >> 28) + 1) << 14;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_dma.c b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_dma.c
new file mode 100644
index 0000000000..f510b3f527
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_dma.c
@@ -0,0 +1,686 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_dma.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l40x_dma.h"
+#include "n32l40x_rcc.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @brief DMA driver modules
+ * @{
+ */
+
+/** @addtogroup DMA_Private_TypesDefinitions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Defines
+ * @{
+ */
+
+/* DMA Channelx interrupt pending bit masks */
+#define DMA_CH1_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF1 | DMA_INTSTS_TXCF1 | DMA_INTSTS_HTXF1 | DMA_INTSTS_ERRF1))
+#define DMA_CH2_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF2 | DMA_INTSTS_TXCF2 | DMA_INTSTS_HTXF2 | DMA_INTSTS_ERRF2))
+#define DMA_CH3_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF3 | DMA_INTSTS_TXCF3 | DMA_INTSTS_HTXF3 | DMA_INTSTS_ERRF3))
+#define DMA_CH4_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF4 | DMA_INTSTS_TXCF4 | DMA_INTSTS_HTXF4 | DMA_INTSTS_ERRF4))
+#define DMA_CH5_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF5 | DMA_INTSTS_TXCF5 | DMA_INTSTS_HTXF5 | DMA_INTSTS_ERRF5))
+#define DMA_CH6_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF6 | DMA_INTSTS_TXCF6 | DMA_INTSTS_HTXF6 | DMA_INTSTS_ERRF6))
+#define DMA_CH7_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF7 | DMA_INTSTS_TXCF7 | DMA_INTSTS_HTXF7 | DMA_INTSTS_ERRF7))
+#define DMA_CH8_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF8 | DMA_INTSTS_TXCF8 | DMA_INTSTS_HTXF8 | DMA_INTSTS_ERRF8))
+
+
+/* DMA CHCFGx registers Masks, MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
+#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the DMAy Channelx registers to their default reset
+ * values.
+ * @param DMAyChx where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 8 for DMA1 and 1 to 8 for DMA2 to select the DMA Channel.
+ */
+void DMA_DeInit(DMA_ChannelType* DMAChx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAChx));
+
+ /* Disable the selected DMAy Channelx */
+ DMAChx->CHCFG &= (uint16_t)(~DMA_CHCFG1_CHEN);
+
+ /* Reset DMAy Channelx control register */
+ DMAChx->CHCFG = 0;
+
+ /* Reset DMAy Channelx remaining bytes register */
+ DMAChx->TXNUM = 0;
+
+ /* Reset DMAy Channelx peripheral address register */
+ DMAChx->PADDR = 0;
+
+ /* Reset DMAy Channelx memory address register */
+ DMAChx->MADDR = 0;
+
+ if (DMAChx == DMA_CH1)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel1 */
+ DMA->INTCLR |= DMA_CH1_INT_MASK;
+ }
+ else if (DMAChx == DMA_CH2)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel2 */
+ DMA->INTCLR |= DMA_CH2_INT_MASK;
+ }
+ else if (DMAChx == DMA_CH3)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel3 */
+ DMA->INTCLR |= DMA_CH3_INT_MASK;
+ }
+ else if (DMAChx == DMA_CH4)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel4 */
+ DMA->INTCLR |= DMA_CH4_INT_MASK;
+ }
+ else if (DMAChx == DMA_CH5)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel5 */
+ DMA->INTCLR |= DMA_CH5_INT_MASK;
+ }
+ else if (DMAChx == DMA_CH6)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel6 */
+ DMA->INTCLR |= DMA_CH6_INT_MASK;
+ }
+ else if (DMAChx == DMA_CH7)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel7 */
+ DMA->INTCLR |= DMA_CH7_INT_MASK;
+ }
+ else if (DMAChx == DMA_CH8)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel8 */
+ DMA->INTCLR |= DMA_CH8_INT_MASK;
+ }
+}
+
+/**
+ * @brief Initializes the DMAy Channelx according to the specified
+ * parameters in the DMA_InitParam.
+ * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel.
+ * @param DMA_InitParam pointer to a DMA_InitType structure that
+ * contains the configuration information for the specified DMA Channel.
+ */
+void DMA_Init(DMA_ChannelType* DMAChx, DMA_InitType* DMA_InitParam)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAChx));
+ assert_param(IS_DMA_DIR(DMA_InitParam->Direction));
+ assert_param(IS_DMA_BUF_SIZE(DMA_InitParam->BufSize));
+ assert_param(IS_DMA_PERIPH_INC_STATE(DMA_InitParam->PeriphInc));
+ assert_param(IS_DMA_MEM_INC_STATE(DMA_InitParam->DMA_MemoryInc));
+ assert_param(IS_DMA_PERIPH_DATA_SIZE(DMA_InitParam->PeriphDataSize));
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitParam->MemDataSize));
+ assert_param(IS_DMA_MODE(DMA_InitParam->CircularMode));
+ assert_param(IS_DMA_PRIORITY(DMA_InitParam->Priority));
+ assert_param(IS_DMA_M2M_STATE(DMA_InitParam->Mem2Mem));
+
+ /*--------------------------- DMAy Channelx CHCFG Configuration -----------------*/
+ /* Get the DMAyChx CHCFG value */
+ tmpregister = DMAChx->CHCFG;
+ /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
+ tmpregister &= CCR_CLEAR_Mask;
+ /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
+ /* Set DIR bit according to Direction value */
+ /* Set CIRC bit according to CircularMode value */
+ /* Set PINC bit according to PeriphInc value */
+ /* Set MINC bit according to DMA_MemoryInc value */
+ /* Set PSIZE bits according to PeriphDataSize value */
+ /* Set MSIZE bits according to MemDataSize value */
+ /* Set PL bits according to Priority value */
+ /* Set the MEM2MEM bit according to Mem2Mem value */
+ tmpregister |= DMA_InitParam->Direction | DMA_InitParam->CircularMode | DMA_InitParam->PeriphInc
+ | DMA_InitParam->DMA_MemoryInc | DMA_InitParam->PeriphDataSize | DMA_InitParam->MemDataSize
+ | DMA_InitParam->Priority | DMA_InitParam->Mem2Mem;
+
+ /* Write to DMAy Channelx CHCFG */
+ DMAChx->CHCFG = tmpregister;
+
+ /*--------------------------- DMAy Channelx TXNUM Configuration ---------------*/
+ /* Write to DMAy Channelx TXNUM */
+ DMAChx->TXNUM = DMA_InitParam->BufSize;
+
+ /*--------------------------- DMAy Channelx PADDR Configuration ----------------*/
+ /* Write to DMAy Channelx PADDR */
+ DMAChx->PADDR = DMA_InitParam->PeriphAddr;
+
+ /*--------------------------- DMAy Channelx MADDR Configuration ----------------*/
+ /* Write to DMAy Channelx MADDR */
+ DMAChx->MADDR = DMA_InitParam->MemAddr;
+}
+
+/**
+ * @brief Fills each DMA_InitParam member with its default value.
+ * @param DMA_InitParam pointer to a DMA_InitType structure which will
+ * be initialized.
+ */
+void DMA_StructInit(DMA_InitType* DMA_InitParam)
+{
+ /*-------------- Reset DMA init structure parameters values ------------------*/
+ /* Initialize the PeriphAddr member */
+ DMA_InitParam->PeriphAddr = 0;
+ /* Initialize the MemAddr member */
+ DMA_InitParam->MemAddr = 0;
+ /* Initialize the Direction member */
+ DMA_InitParam->Direction = DMA_DIR_PERIPH_SRC;
+ /* Initialize the BufSize member */
+ DMA_InitParam->BufSize = 0;
+ /* Initialize the PeriphInc member */
+ DMA_InitParam->PeriphInc = DMA_PERIPH_INC_DISABLE;
+ /* Initialize the DMA_MemoryInc member */
+ DMA_InitParam->DMA_MemoryInc = DMA_MEM_INC_DISABLE;
+ /* Initialize the PeriphDataSize member */
+ DMA_InitParam->PeriphDataSize = DMA_PERIPH_DATA_SIZE_BYTE;
+ /* Initialize the MemDataSize member */
+ DMA_InitParam->MemDataSize = DMA_MemoryDataSize_Byte;
+ /* Initialize the CircularMode member */
+ DMA_InitParam->CircularMode = DMA_MODE_NORMAL;
+ /* Initialize the Priority member */
+ DMA_InitParam->Priority = DMA_PRIORITY_LOW;
+ /* Initialize the Mem2Mem member */
+ DMA_InitParam->Mem2Mem = DMA_M2M_DISABLE;
+}
+
+/**
+ * @brief Enables or disables the specified DMAy Channelx.
+ * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel.
+ * @param Cmd new state of the DMA Channelx.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DMA_EnableChannel(DMA_ChannelType* DMAChx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAChx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected DMAy Channelx */
+ DMAChx->CHCFG |= DMA_CHCFG1_CHEN;
+ }
+ else
+ {
+ /* Disable the selected DMAy Channelx */
+ DMAChx->CHCFG &= (uint16_t)(~DMA_CHCFG1_CHEN);
+ }
+}
+
+/**
+ * @brief Enables or disables the specified DMAy Channelx interrupts.
+ * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel.
+ * @param DMAInt specifies the DMA interrupts sources to be enabled
+ * or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_INT_TXC Transfer complete interrupt mask
+ * @arg DMA_INT_HTX Half transfer interrupt mask
+ * @arg DMA_INT_ERR Transfer error interrupt mask
+ * @param Cmd new state of the specified DMA interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DMA_ConfigInt(DMA_ChannelType* DMAChx, uint32_t DMAInt, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAChx));
+ assert_param(IS_DMA_CONFIG_INT(DMAInt));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected DMA interrupts */
+ DMAChx->CHCFG |= DMAInt;
+ }
+ else
+ {
+ /* Disable the selected DMA interrupts */
+ DMAChx->CHCFG &= ~DMAInt;
+ }
+}
+
+/**
+ * @brief Sets the number of data units in the current DMAy Channelx transfer.
+ * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel.
+ * @param DataNumber The number of data units in the current DMAy Channelx
+ * transfer.
+ * @note This function can only be used when the DMAyChx is disabled.
+ */
+void DMA_SetCurrDataCounter(DMA_ChannelType* DMAChx, uint16_t DataNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAChx));
+
+ /*--------------------------- DMAy Channelx TXNUM Configuration ---------------*/
+ /* Write to DMA Channelx TXNUM */
+ DMAChx->TXNUM = DataNumber;
+}
+
+/**
+ * @brief Returns the number of remaining data units in the current
+ * DMA Channelx transfer.
+ * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel.
+ * @return The number of remaining data units in the current DMA Channelx
+ * transfer.
+ */
+uint16_t DMA_GetCurrDataCounter(DMA_ChannelType* DMAChx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAChx));
+ /* Return the number of remaining data units for DMAy Channelx */
+ return ((uint16_t)(DMAChx->TXNUM));
+}
+
+/**
+ * @brief Checks whether the specified DMA Channelx flag is set or not.
+ * @param DMAFlag specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg DMA_FLAG_GL1 DMA Channel1 global flag.
+ * @arg DMA_FLAG_TC1 DMA Channel1 transfer complete flag.
+ * @arg DMA_FLAG_HT1 DMA Channel1 half transfer flag.
+ * @arg DMA_FLAG_TE1 DMA Channel1 transfer error flag.
+ * @arg DMA_FLAG_GL2 DMA Channel2 global flag.
+ * @arg DMA_FLAG_TC2 DMA Channel2 transfer complete flag.
+ * @arg DMA_FLAG_HT2 DMA Channel2 half transfer flag.
+ * @arg DMA_FLAG_TE2 DMA Channel2 transfer error flag.
+ * @arg DMA_FLAG_GL3 DMA Channel3 global flag.
+ * @arg DMA_FLAG_TC3 DMA Channel3 transfer complete flag.
+ * @arg DMA_FLAG_HT3 DMA Channel3 half transfer flag.
+ * @arg DMA_FLAG_TE3 DMA Channel3 transfer error flag.
+ * @arg DMA_FLAG_GL4 DMA Channel4 global flag.
+ * @arg DMA_FLAG_TC4 DMA Channel4 transfer complete flag.
+ * @arg DMA_FLAG_HT4 DMA Channel4 half transfer flag.
+ * @arg DMA_FLAG_TE4 DMA Channel4 transfer error flag.
+ * @arg DMA_FLAG_GL5 DMA Channel5 global flag.
+ * @arg DMA_FLAG_TC5 DMA Channel5 transfer complete flag.
+ * @arg DMA_FLAG_HT5 DMA Channel5 half transfer flag.
+ * @arg DMA_FLAG_TE5 DMA Channel5 transfer error flag.
+ * @arg DMA_FLAG_GL6 DMA Channel6 global flag.
+ * @arg DMA_FLAG_TC6 DMA Channel6 transfer complete flag.
+ * @arg DMA_FLAG_HT6 DMA Channel6 half transfer flag.
+ * @arg DMA_FLAG_TE6 DMA Channel6 transfer error flag.
+ * @arg DMA_FLAG_GL7 DMA Channel7 global flag.
+ * @arg DMA_FLAG_TC7 DMA Channel7 transfer complete flag.
+ * @arg DMA_FLAG_HT7 DMA Channel7 half transfer flag.
+ * @arg DMA_FLAG_TE7 DMA Channel7 transfer error flag.
+ * @arg DMA_FLAG_GL8 DMA Channel7 global flag.
+ * @arg DMA_FLAG_TC8 DMA Channel7 transfer complete flag.
+ * @arg DMA_FLAG_HT8 DMA Channel7 half transfer flag.
+ * @arg DMA_FLAG_TE8 DMA Channel7 transfer error flag.
+ * @param DMAy DMA
+ * This parameter can be one of the following values:
+ * @arg DMA .
+ * @return The new state of DMAFlag (SET or RESET).
+ */
+FlagStatus DMA_GetFlagStatus(uint32_t DMAFlag, DMA_Module* DMAy)
+{
+ FlagStatus bitstatus = RESET;
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_GET_FLAG(DMAFlag));
+
+ /* Calculate the used DMAy */
+ /* Get DMAy INTSTS register value */
+ tmpregister = DMAy->INTSTS;
+
+ /* Check the status of the specified DMAy flag */
+ if ((tmpregister & DMAFlag) != (uint32_t)RESET)
+ {
+ /* DMAyFlag is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DMAyFlag is reset */
+ bitstatus = RESET;
+ }
+
+ /* Return the DMAyFlag status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the DMA Channelx's pending flags.
+ * @param DMAFlag specifies the flag to clear.
+ * This parameter can be any combination (for the same DMA) of the following values:
+ * @arg DMA_FLAG_GL1 DMA Channel1 global flag.
+ * @arg DMA_FLAG_TC1 DMA Channel1 transfer complete flag.
+ * @arg DMA_FLAG_HT1 DMA Channel1 half transfer flag.
+ * @arg DMA_FLAG_TE1 DMA Channel1 transfer error flag.
+ * @arg DMA_FLAG_GL2 DMA Channel2 global flag.
+ * @arg DMA_FLAG_TC2 DMA Channel2 transfer complete flag.
+ * @arg DMA_FLAG_HT2 DMA Channel2 half transfer flag.
+ * @arg DMA_FLAG_TE2 DMA Channel2 transfer error flag.
+ * @arg DMA_FLAG_GL3 DMA Channel3 global flag.
+ * @arg DMA_FLAG_TC3 DMA Channel3 transfer complete flag.
+ * @arg DMA_FLAG_HT3 DMA Channel3 half transfer flag.
+ * @arg DMA_FLAG_TE3 DMA Channel3 transfer error flag.
+ * @arg DMA_FLAG_GL4 DMA Channel4 global flag.
+ * @arg DMA_FLAG_TC4 DMA Channel4 transfer complete flag.
+ * @arg DMA_FLAG_HT4 DMA Channel4 half transfer flag.
+ * @arg DMA_FLAG_TE4 DMA Channel4 transfer error flag.
+ * @arg DMA_FLAG_GL5 DMA Channel5 global flag.
+ * @arg DMA_FLAG_TC5 DMA Channel5 transfer complete flag.
+ * @arg DMA_FLAG_HT5 DMA Channel5 half transfer flag.
+ * @arg DMA_FLAG_TE5 DMA Channel5 transfer error flag.
+ * @arg DMA_FLAG_GL6 DMA Channel6 global flag.
+ * @arg DMA_FLAG_TC6 DMA Channel6 transfer complete flag.
+ * @arg DMA_FLAG_HT6 DMA Channel6 half transfer flag.
+ * @arg DMA_FLAG_TE6 DMA Channel6 transfer error flag.
+ * @arg DMA_FLAG_GL7 DMA Channel7 global flag.
+ * @arg DMA_FLAG_TC7 DMA Channel7 transfer complete flag.
+ * @arg DMA_FLAG_HT7 DMA Channel7 half transfer flag.
+ * @arg DMA_FLAG_TE7 DMA Channel7 transfer error flag.
+ * @arg DMA_FLAG_GL8 DMA Channel8 global flag.
+ * @arg DMA_FLAG_TC8 DMA Channel8 transfer complete flag.
+ * @arg DMA_FLAG_HT8 DMA Channel8 half transfer flag.
+ * @arg DMA_FLAG_TE8 DMA Channel8 transfer error flag.
+ * @param DMA DMA
+ * This parameter can be one of the following values:
+ * @arg DMA .
+ */
+void DMA_ClearFlag(uint32_t DMAFlag, DMA_Module* DMAy)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_CLEAR_FLAG(DMAFlag));
+
+ /* Calculate the used DMAy */
+ /* Clear the selected DMAy flags */
+ DMAy->INTCLR = DMAFlag;
+}
+
+/**
+ * @brief Checks whether the specified DMA Channelx interrupt has occurred or not.
+ * @param DMA_IT specifies the DMAy interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DMA_INT_GLB1 DMA Channel1 global interrupt.
+ * @arg DMA_INT_TXC1 DMA Channel1 transfer complete interrupt.
+ * @arg DMA_INT_HTX1 DMA Channel1 half transfer interrupt.
+ * @arg DMA_INT_ERR1 DMA Channel1 transfer error interrupt.
+ * @arg DMA_INT_GLB2 DMA Channel2 global interrupt.
+ * @arg DMA_INT_TXC2 DMA Channel2 transfer complete interrupt.
+ * @arg DMA_INT_HTX2 DMA Channel2 half transfer interrupt.
+ * @arg DMA_INT_ERR2 DMA Channel2 transfer error interrupt.
+ * @arg DMA_INT_GLB3 DMA Channel3 global interrupt.
+ * @arg DMA_INT_TXC3 DMA Channel3 transfer complete interrupt.
+ * @arg DMA_INT_HTX3 DMA Channel3 half transfer interrupt.
+ * @arg DMA_INT_ERR3 DMA Channel3 transfer error interrupt.
+ * @arg DMA_INT_GLB4 DMA Channel4 global interrupt.
+ * @arg DMA_INT_TXC4 DMA Channel4 transfer complete interrupt.
+ * @arg DMA_INT_HTX4 DMA Channel4 half transfer interrupt.
+ * @arg DMA_INT_ERR4 DMA Channel4 transfer error interrupt.
+ * @arg DMA_INT_GLB5 DMA Channel5 global interrupt.
+ * @arg DMA_INT_TXC5 DMA Channel5 transfer complete interrupt.
+ * @arg DMA_INT_HTX5 DMA Channel5 half transfer interrupt.
+ * @arg DMA_INT_ERR5 DMA Channel5 transfer error interrupt.
+ * @arg DMA_INT_GLB6 DMA Channel6 global interrupt.
+ * @arg DMA_INT_TXC6 DMA Channel6 transfer complete interrupt.
+ * @arg DMA_INT_HTX6 DMA Channel6 half transfer interrupt.
+ * @arg DMA_INT_ERR6 DMA Channel6 transfer error interrupt.
+ * @arg DMA_INT_GLB7 DMA Channel7 global interrupt.
+ * @arg DMA_INT_TXC7 DMA Channel7 transfer complete interrupt.
+ * @arg DMA_INT_HTX7 DMA Channel7 half transfer interrupt.
+ * @arg DMA_INT_ERR7 DMA Channel7 transfer error interrupt.
+ * @arg DMA_INT_GLB8 DMA Channel8 global interrupt.
+ * @arg DMA_INT_TXC8 DMA Channel8 transfer complete interrupt.
+ * @arg DMA_INT_HTX8 DMA Channel8 half transfer interrupt.
+ * @arg DMA_INT_ERR8 DMA Channel8 transfer error interrupt.
+ * @param DMA DMA
+ * This parameter can be one of the following values:
+ * @arg DMA .
+ * @return The new state of DMA_IT (SET or RESET).
+ */
+INTStatus DMA_GetIntStatus(uint32_t DMA_IT, DMA_Module* DMAy)
+{
+ INTStatus bitstatus = RESET;
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_GET_IT(DMA_IT));
+
+ /* Calculate the used DMA */
+ /* Get DMAy INTSTS register value */
+ tmpregister = DMAy->INTSTS;
+
+ /* Check the status of the specified DMAy interrupt */
+ if ((tmpregister & DMA_IT) != (uint32_t)RESET)
+ {
+ /* DMAy_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DMAy_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the DMAInt status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the DMA Channelx's interrupt pending bits.
+ * @param DMA_IT specifies the DMA interrupt pending bit to clear.
+ * This parameter can be any combination (for the same DMA) of the following values:
+ * @arg DMA_INT_GLB1 DMA Channel1 global interrupt.
+ * @arg DMA_INT_TXC1 DMA Channel1 transfer complete interrupt.
+ * @arg DMA_INT_HTX1 DMA Channel1 half transfer interrupt.
+ * @arg DMA_INT_ERR1 DMA Channel1 transfer error interrupt.
+ * @arg DMA_INT_GLB2 DMA Channel2 global interrupt.
+ * @arg DMA_INT_TXC2 DMA Channel2 transfer complete interrupt.
+ * @arg DMA_INT_HTX2 DMA Channel2 half transfer interrupt.
+ * @arg DMA_INT_ERR2 DMA Channel2 transfer error interrupt.
+ * @arg DMA_INT_GLB3 DMA Channel3 global interrupt.
+ * @arg DMA_INT_TXC3 DMA Channel3 transfer complete interrupt.
+ * @arg DMA_INT_HTX3 DMA Channel3 half transfer interrupt.
+ * @arg DMA_INT_ERR3 DMA Channel3 transfer error interrupt.
+ * @arg DMA_INT_GLB4 DMA Channel4 global interrupt.
+ * @arg DMA_INT_TXC4 DMA Channel4 transfer complete interrupt.
+ * @arg DMA_INT_HTX4 DMA Channel4 half transfer interrupt.
+ * @arg DMA_INT_ERR4 DMA Channel4 transfer error interrupt.
+ * @arg DMA_INT_GLB5 DMA Channel5 global interrupt.
+ * @arg DMA_INT_TXC5 DMA Channel5 transfer complete interrupt.
+ * @arg DMA_INT_HTX5 DMA Channel5 half transfer interrupt.
+ * @arg DMA_INT_ERR5 DMA Channel5 transfer error interrupt.
+ * @arg DMA_INT_GLB6 DMA Channel6 global interrupt.
+ * @arg DMA_INT_TXC6 DMA Channel6 transfer complete interrupt.
+ * @arg DMA_INT_HTX6 DMA Channel6 half transfer interrupt.
+ * @arg DMA_INT_ERR6 DMA Channel6 transfer error interrupt.
+ * @arg DMA_INT_GLB7 DMA Channel7 global interrupt.
+ * @arg DMA_INT_TXC7 DMA Channel7 transfer complete interrupt.
+ * @arg DMA_INT_HTX7 DMA Channel7 half transfer interrupt.
+ * @arg DMA_INT_ERR7 DMA Channel7 transfer error interrupt.
+ * @arg DMA_INT_GLB8 DMA Channel8 global interrupt.
+ * @arg DMA_INT_TXC8 DMA Channel8 transfer complete interrupt.
+ * @arg DMA_INT_HTX8 DMA Channel8 half transfer interrupt.
+ * @arg DMA_INT_ERR8 DMA Channel8 transfer error interrupt.
+ * @param DMAy DMA
+ * This parameter can be one of the following values:
+ * @arg DMA .
+ */
+void DMA_ClrIntPendingBit(uint32_t DMA_IT, DMA_Module* DMAy)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_CLR_INT(DMA_IT));
+
+ /* Calculate the used DMA */
+ /* Clear the selected DMA interrupt pending bits */
+ DMAy->INTCLR = DMA_IT;
+}
+
+/**
+ * @brief Set the DMA Channelx's remap request.
+ * @param DMA_REMAP specifies the DMA request.
+ * This parameter can be set by the following values:
+ * @arg DMA_REMAP_ADC1 DMA Request For ADC1.
+ * @arg DMA_REMAP_USART1_TX DMA Request For USART1_TX.
+ * @arg DMA_REMAP_USART1_RX DMA Request For USART1_RX.
+ * @arg DMA_REMAP_USART2_TX DMA Request For USART2_TX.
+ * @arg DMA_REMAP_USART2_RX DMA Request For USART2_RX.
+ * @arg DMA_REMAP_USART3_TX DMA Request For USART3_TX.
+ * @arg DMA_REMAP_USART3_RX DMA Request For USART3_RX.
+ * @arg DMA_REMAP_UART4_TX DMA Request For UART4_TX.
+ * @arg DMA_REMAP_UART4_RX DMA Request For UART4_RX.
+ * @arg DMA_REMAP_UART5_TX DMA Request For UART5_TX.
+ * @arg DMA_REMAP_UART5_RX DMA Request For UART5_RX.
+ * @arg DMA_REMAP_LPUART_TX DMA Request For LPUART_TX.
+ * @arg DMA_REMAP_LPUART_RX DMA Request For LPUART_RX.
+ * @arg DMA_REMAP_SPI1_TX DMA Request For SPI1_TX.
+ * @arg DMA_REMAP_SPI1_RX DMA Request For SPI1_RX.
+ * @arg DMA_REMAP_SPI2_TX DMA Request For SPI2_TX.
+ * @arg DMA_REMAP_SPI2_RX DMA Request For SPI2_RX.
+ * @arg DMA_REMAP_I2C1_TX DMA Request For I2C1_TX.
+ * @arg DMA_REMAP_I2C1_RX DMA Request For I2C1_RX.
+ * @arg DMA_REMAP_I2C2_TX DMA Request For I2C2_TX.
+ * @arg DMA_REMAP_I2C2_RX DMA Request For I2C2_RX.
+ * @arg DMA_REMAP_DAC1 DMA Request For DAC1.
+ * @arg DMA_REMAP_TIM1_CH1 DMA Request For TIM1_CH1.
+ * @arg DMA_REMAP_TIM1_CH2 DMA Request For TIM1_CH2.
+ * @arg DMA_REMAP_TIM1_CH3 DMA Request For TIM1_CH3.
+ * @arg DMA_REMAP_TIM1_CH4 DMA Request For TIM1_CH4.
+ * @arg DMA_REMAP_TIM1_COM DMA Request For TIM1_COM.
+ * @arg DMA_REMAP_TIM1_UP DMA Request For TIM1_UP.
+ * @arg DMA_REMAP_TIM1_TRIG DMA Request For TIM1_TRIG.
+ * @arg DMA_REMAP_TIM2_CH1 DMA Request For TIM2_CH1.
+ * @arg DMA_REMAP_TIM2_CH2 DMA Request For TIM2_CH2.
+ * @arg DMA_REMAP_TIM2_CH3 DMA Request For TIM2_CH3.
+ * @arg DMA_REMAP_TIM2_CH4 DMA Request For TIM3_TRIG.
+ * @arg DMA_REMAP_TIM2_UP DMA Request For TIM2_UP.
+ * @arg DMA_REMAP_TIM3_CH1 DMA Request For TIM3_CH1.
+ * @arg DMA_REMAP_TIM3_CH3 DMA Request For TIM3_CH3.
+ * @arg DMA_REMAP_TIM3_CH4 DMA Request For TIM3_CH4.
+ * @arg DMA_REMAP_TIM3_UP DMA Request For TIM3_UP.
+ * @arg DMA_REMAP_TIM3_TRIG DMA Request For TIM3_TRIG.
+ * @arg DMA_REMAP_TIM4_CH1 DMA Request For TIM4_CH1.
+ * @arg DMA_REMAP_TIM4_CH2 DMA Request For TIM4_CH2.
+ * @arg DMA_REMAP_TIM4_CH3 DMA Request For TIM4_CH3.
+ * @arg DMA_REMAP_TIM4_UP DMA Request For TIM4_UP.
+ * @arg DMA_REMAP_TIM5_CH1 DMA Request For TIM5_CH1.
+ * @arg DMA_REMAP_TIM5_CH2 DMA Request For TIM5_CH2.
+ * @arg DMA_REMAP_TIM5_CH3 DMA Request For TIM5_CH3.
+ * @arg DMA_REMAP_TIM5_CH4 DMA Request For TIM5_CH4.
+ * @arg DMA_REMAP_TIM5_UP DMA Request For TIM5_UP.
+ * @arg DMA_REMAP_TIM5_TRIG DMA Request For TIM5_TRIG.
+ * @arg DMA_REMAP_TIM6_UP DMA Request For TIM6_UP.
+ * @arg DMA_REMAP_TIM7_UP DMA Request For TIM7_UP.
+ * @arg DMA_REMAP_TIM8_CH1 DMA Request For TIM8_CH1.
+ * @arg DMA_REMAP_TIM8_CH2 DMA Request For TIM8_CH2.
+ * @arg DMA_REMAP_TIM8_CH3 DMA Request For TIM8_CH3.
+ * @arg DMA_REMAP_TIM8_CH4 DMA Request For TIM8_CH4.
+ * @arg DMA_REMAP_TIM8_COM DMA Request For TIM8_COM.
+ * @arg DMA_REMAP_TIM8_UP DMA Request For TIM8_UP.
+ * @arg DMA_REMAP_TIM8_TRIG DMA Request For TIM8_TRIG.
+ * @arg DMA_REMAP_TIM9_CH1 DMA Request For TIM9_CH1.
+ * @arg DMA_REMAP_TIM9_TRIG DMA Request For TIM9_TRIG.
+ * @arg DMA_REMAP_TIM9_CH3 DMA Request For TIM9_CH3.
+ * @arg DMA_REMAP_TIM9_CH4 DMA Request For TIM9_CH4.
+ * @arg DMA_REMAP_TIM9_UP DMA Request For TIM9_UP.
+ * @param DMAy DMA
+ * This parameter can be one of the following values:
+ * @arg DMA .
+ * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel.
+ * @param Cmd new state of the DMA Channelx.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DMA_RequestRemap(uint32_t DMA_REMAP, DMA_Module* DMAy, DMA_ChannelType* DMAChx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_REMAP(DMA_REMAP));
+
+ if (Cmd != DISABLE)
+ {
+ /* Calculate the used DMAy */
+ /* Set the selected DMAy remap request */
+ DMAChx->CHSEL = DMA_REMAP;
+ }
+ else
+ {
+ /* Clear DMAy remap */
+ DMAChx->CHSEL = 0;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_exti.c b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_exti.c
new file mode 100644
index 0000000000..72efa8c948
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_exti.c
@@ -0,0 +1,286 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_exti.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l40x_exti.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup EXTI
+ * @brief EXTI driver modules
+ * @{
+ */
+
+/** @addtogroup EXTI_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Private_Defines
+ * @{
+ */
+
+#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the EXTI peripheral registers to their default reset values.
+ */
+void EXTI_DeInit(void)
+{
+ EXTI->IMASK = 0x00000000;
+ EXTI->EMASK = 0x00000000;
+ EXTI->RT_CFG = 0x00000000;
+ EXTI->FT_CFG = 0x00000000;
+ EXTI->PEND = 0x0FFFFFFF;
+}
+
+/**
+ * @brief Initializes the EXTI peripheral according to the specified
+ * parameters in the EXTI_InitStruct.
+ * @param EXTI_InitStruct pointer to a EXTI_InitType structure
+ * that contains the configuration information for the EXTI peripheral.
+ */
+void EXTI_InitPeripheral(EXTI_InitType* EXTI_InitStruct)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
+ assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
+ assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
+ assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
+
+ tmp = (uint32_t)EXTI_BASE;
+
+ if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
+ {
+ /* Clear EXTI line configuration */
+ EXTI->IMASK &= ~EXTI_InitStruct->EXTI_Line;
+ EXTI->EMASK &= ~EXTI_InitStruct->EXTI_Line;
+
+ tmp += EXTI_InitStruct->EXTI_Mode;
+
+ *(__IO uint32_t*)tmp |= EXTI_InitStruct->EXTI_Line;
+
+ /* Clear Rising Falling edge configuration */
+ EXTI->RT_CFG &= ~EXTI_InitStruct->EXTI_Line;
+ EXTI->FT_CFG &= ~EXTI_InitStruct->EXTI_Line;
+
+ /* Select the trigger for the selected external interrupts */
+ if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
+ {
+ /* Rising Falling edge */
+ EXTI->RT_CFG |= EXTI_InitStruct->EXTI_Line;
+ EXTI->FT_CFG |= EXTI_InitStruct->EXTI_Line;
+ }
+ else
+ {
+ tmp = (uint32_t)EXTI_BASE;
+ tmp += EXTI_InitStruct->EXTI_Trigger;
+
+ *(__IO uint32_t*)tmp |= EXTI_InitStruct->EXTI_Line;
+ }
+ }
+ else
+ {
+ tmp += EXTI_InitStruct->EXTI_Mode;
+
+ /* Disable the selected external lines */
+ *(__IO uint32_t*)tmp &= ~EXTI_InitStruct->EXTI_Line;
+ }
+}
+
+/**
+ * @brief Fills each EXTI_InitStruct member with its reset value.
+ * @param EXTI_InitStruct pointer to a EXTI_InitType structure which will
+ * be initialized.
+ */
+void EXTI_InitStruct(EXTI_InitType* EXTI_InitStruct)
+{
+ EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
+ EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
+ EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
+ EXTI_InitStruct->EXTI_LineCmd = DISABLE;
+}
+
+/**
+ * @brief Generates a Software interrupt.
+ * @param EXTI_Line specifies the EXTI lines to be enabled or disabled.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..27).
+ */
+void EXTI_TriggerSWInt(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(EXTI_Line));
+
+ EXTI->SWIE |= EXTI_Line;
+}
+
+/**
+ * @brief Checks whether the specified EXTI line flag is set or not.
+ * @param EXTI_Line specifies the EXTI line flag to check.
+ * This parameter can be:
+ * @arg EXTI_Linex External interrupt line x where x(0..27)
+ * @return The new state of EXTI_Line (SET or RESET).
+ */
+FlagStatus EXTI_GetStatusFlag(uint32_t EXTI_Line)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+ if ((EXTI->PEND & EXTI_Line) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the EXTI's line pending flags.
+ * @param EXTI_Line specifies the EXTI lines flags to clear.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..27).
+ */
+void EXTI_ClrStatusFlag(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(EXTI_Line));
+
+ EXTI->PEND = EXTI_Line;
+}
+
+/**
+ * @brief Checks whether the specified EXTI line is asserted or not.
+ * @param EXTI_Line specifies the EXTI line to check.
+ * This parameter can be:
+ * @arg EXTI_Linex External interrupt line x where x(0..27)
+ * @return The new state of EXTI_Line (SET or RESET).
+ */
+INTStatus EXTI_GetITStatus(uint32_t EXTI_Line)
+{
+ INTStatus bitstatus = RESET;
+ uint32_t enablestatus = 0;
+ /* Check the parameters */
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+ enablestatus = EXTI->IMASK & EXTI_Line;
+ if (((EXTI->PEND & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the EXTI's line pending bits.
+ * @param EXTI_Line specifies the EXTI lines to clear.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..27).
+ */
+void EXTI_ClrITPendBit(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(EXTI_Line));
+
+ EXTI->PEND = EXTI_Line;
+}
+
+/**
+ * @brief Select one of EXTI inputs to the RTC TimeStamp event.
+ * @param EXTI_TSSEL_Line specifies the EXTI lines to select.
+ * This parameter can be any combination of EXTI_TSSEL_Line where x can be (0..15).
+ */
+void EXTI_RTCTimeStampSel(uint32_t EXTI_TSSEL_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_TSSEL_LINE(EXTI_TSSEL_Line));
+
+ EXTI->TS_SEL &= EXTI_TSSEL_LINE_MASK;
+ EXTI->TS_SEL |= EXTI_TSSEL_Line;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_flash.c b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_flash.c
new file mode 100644
index 0000000000..ffa1ba6377
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_flash.c
@@ -0,0 +1,1565 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_flash.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l40x_flash.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @brief FLASH driver modules
+ * @{
+ */
+
+/** @addtogroup FLASH_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Defines
+ * @{
+ */
+
+/* Flash Access Control Register bits */
+#define AC_LATENCY_MSK ((uint32_t)0x000000F8)
+#define AC_PRFTBE_MSK ((uint32_t)0xFFFFFFEF)
+#define AC_ICAHEN_MSK ((uint32_t)0xFFFFFF7F)
+#define AC_LVMEN_MSK ((uint32_t)0xFFFFFDFF)
+#define AC_SLMEN_MSK ((uint32_t)0xFFFFF7FF)
+
+/* Flash Access Control Register bits */
+#define AC_PRFTBS_MSK ((uint32_t)0x00000020)
+#define AC_ICAHRST_MSK ((uint32_t)0x00000040)
+#define AC_LVMF_MSK ((uint32_t)0x00000100)
+#define AC_SLMF_MSK ((uint32_t)0x00000400)
+
+/* Flash Control Register bits */
+#define CTRL_Set_PG ((uint32_t)0x00000001)
+#define CTRL_Reset_PG ((uint32_t)0x00003FFE)
+#define CTRL_Set_PER ((uint32_t)0x00000002)
+#define CTRL_Reset_PER ((uint32_t)0x00003FFD)
+#define CTRL_Set_MER ((uint32_t)0x00000004)
+#define CTRL_Reset_MER ((uint32_t)0x00003FFB)
+#define CTRL_Set_OPTPG ((uint32_t)0x00000010)
+#define CTRL_Reset_OPTPG ((uint32_t)0x00003FEF)
+#define CTRL_Set_OPTER ((uint32_t)0x00000020)
+#define CTRL_Reset_OPTER ((uint32_t)0x00003FDF)
+#define CTRL_Set_START ((uint32_t)0x00000040)
+#define CTRL_Set_LOCK ((uint32_t)0x00000080)
+#define CTRL_Reset_SMPSEL ((uint32_t)0x00003EFF)
+#define CTRL_SMPSEL_SMP1 ((uint32_t)0x00000000)
+#define CTRL_SMPSEL_SMP2 ((uint32_t)0x00000100)
+
+/* FLASH Mask */
+#define RDPRTL1_MSK ((uint32_t)0x00000002)
+#define RDPRTL2_MSK ((uint32_t)0x80000000)
+#define OBR_USER_MSK ((uint32_t)0x0000001C)
+#define WRP0_MSK ((uint32_t)0x000000FF)
+#define WRP1_MSK ((uint32_t)0x0000FF00)
+#define WRP2_MSK ((uint32_t)0x00FF0000)
+#define WRP3_MSK ((uint32_t)0xFF000000)
+
+/* FLASH Keys */
+#define L1_RDP_Key ((uint32_t)0xFFFF00A5)
+#define RDP_USER_Key ((uint32_t)0xFFF000A5)
+#define L2_RDP_Key ((uint32_t)0xFFFF33CC)
+#define FLASH_KEY1 ((uint32_t)0x45670123)
+#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
+
+/* Delay definition */
+#define EraseTimeout ((uint32_t)0x000B0000)
+#define ProgramTimeout ((uint32_t)0x00002000)
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Sets the code latency value.
+ * @note This function can be used for n32l40x devices.
+ * @param FLASH_Latency specifies the FLASH Latency value.
+ * This parameter can be one of the following values:
+ * @arg FLASH_LATENCY_0 FLASH Zero Latency cycle
+ * @arg FLASH_LATENCY_1 FLASH One Latency cycle
+ * @arg FLASH_LATENCY_2 FLASH Two Latency cycles
+ * @arg FLASH_LATENCY_3 FLASH Three Latency cycles
+ */
+void FLASH_SetLatency(uint32_t FLASH_Latency)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_LATENCY(FLASH_Latency));
+
+ /* Read the ACR register */
+ tmpregister = FLASH->AC;
+
+ /* Sets the Latency value */
+ tmpregister &= AC_LATENCY_MSK;
+ tmpregister |= FLASH_Latency;
+
+ /* Write the ACR register */
+ FLASH->AC = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the Prefetch Buffer.
+ * @note This function can be used for n32l40x devices.
+ * @param FLASH_PrefetchBuf specifies the Prefetch buffer status.
+ * This parameter can be one of the following values:
+ * @arg FLASH_PrefetchBuf_EN FLASH Prefetch Buffer Enable
+ * @arg FLASH_PrefetchBuf_DIS FLASH Prefetch Buffer Disable
+ */
+void FLASH_PrefetchBufSet(uint32_t FLASH_PrefetchBuf)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_PREFETCHBUF_STATE(FLASH_PrefetchBuf));
+
+ /* Enable or disable the Prefetch Buffer */
+ FLASH->AC &= AC_PRFTBE_MSK;
+ FLASH->AC |= FLASH_PrefetchBuf;
+}
+
+/**
+ * @brief ICache Reset.
+ * @note This function can be used for n32l40x devices.
+ */
+void FLASH_iCacheRST(void)
+{
+ /* ICache Reset */
+ FLASH->AC |= FLASH_AC_ICAHRST;
+}
+
+/**
+ * @brief Enables or disables the iCache.
+ * @note This function can be used for n32l40x devices.
+ * @param FLASH_iCache specifies the iCache status.
+ * This parameter can be one of the following values:
+ * @arg FLASH_iCache_EN FLASH iCache Enable
+ * @arg FLASH_iCache_DIS FLASH iCache Disable
+ */
+void FLASH_iCacheCmd(uint32_t FLASH_iCache)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_ICACHE_STATE(FLASH_iCache));
+
+ /* Enable or disable the iCache */
+ FLASH->AC &= AC_ICAHEN_MSK;
+ FLASH->AC |= FLASH_iCache;
+}
+
+/**
+ * @brief Enables or disables the Low Voltage Mode.
+ * @note This function can be used for n32l40x devices.
+ * @param FLASH_LVM specifies the Low Voltage Mode status.
+ * This parameter can be one of the following values:
+ * @arg FLASH_LVM_EN FLASH Low Voltage Mode Enable
+ * @arg FLASH_LVM_DIS FLASH Low Voltage Mode Disable
+ */
+void FLASH_LowVoltageModeCmd(uint32_t FLASH_LVM)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_LVM(FLASH_LVM));
+
+ /* Enable or disable LVM */
+ FLASH->AC &= AC_LVMEN_MSK;
+ FLASH->AC |= FLASH_LVM;
+}
+
+/**
+ * @brief Checks whether the Low Voltage Mode status is SET or RESET.
+ * @note This function can be used for n32l40x devices.
+ * @return Low Voltage Mode Status (SET or RESET).
+ */
+FlagStatus FLASH_GetLowVoltageModeSTS(void)
+{
+ FlagStatus bitstatus = RESET;
+
+ if ((FLASH->AC & AC_LVMF_MSK) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the new state of FLASH Low Voltage Mode Status (SET or RESET) */
+ return bitstatus;
+}
+
+/**
+ * @brief Enables or disables the FLASH Sleep Mode.
+ * @note This function can be used for n32l40x devices.
+ * @param FLASH_SLM specifies the FLASH Sleep Mode status.
+ * This parameter can be one of the following values:
+ * @arg FLASH_SLM_EN FLASH iCache Enable
+ * @arg FLASH_SLM_DIS FLASH iCache Disable
+ */
+void FLASH_FLASHSleepModeCmd(uint32_t FLASH_SLM)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_SLM(FLASH_SLM));
+
+ /* Enable or disable SLM */
+ FLASH->AC &= AC_SLMEN_MSK;
+ FLASH->AC |= FLASH_SLM;
+}
+
+/**
+ * @brief Checks whether the FLASH Sleep Mode status is SET or RESET.
+ * @note This function can be used for n32l40x devices.
+ * @return FLASH Sleep Mode Status (SET or RESET).
+ */
+FlagStatus FLASH_GetFLASHSleepModeSTS(void)
+{
+ FlagStatus bitstatus = RESET;
+
+ if ((FLASH->AC & AC_SLMF_MSK) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the new state of FLASH Sleep Mode Status (SET or RESET) */
+ return bitstatus;
+}
+
+/**
+ * @brief Checks whether the FLASH SMPSEL is SMP1 or SMP2.
+ * @note This function can be used for n32l40x devices.
+ * @param FLASH_smpsel FLASH_SMPSEL_SMP1 or FLASH_SMPSEL_SMP2
+ */
+void FLASH_SetSMPSELStatus(uint32_t FLASH_smpsel)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_SMPSEL_STATE(FLASH_smpsel));
+
+ /* SMP1 or SMP2 */
+ FLASH->CTRL &= CTRL_Reset_SMPSEL;
+ FLASH->CTRL |= FLASH_smpsel;
+}
+
+/**
+ * @brief Configures the Internal High Speed oscillator
+ * to program/erase FLASH.
+ * @note This function can be used for n32l40x devices.
+ * - For n32l40x devices this function enable HSI.
+ * @return FLASH_HSICLOCK (FLASH_HSICLOCK_ENABLE or FLASH_HSICLOCK_DISABLE).
+ */
+FLASH_HSICLOCK FLASH_ClockInit(void)
+{
+ bool HSIStatus = 0;
+ __IO uint32_t StartUpCounter = 0;
+ FLASH_HSICLOCK hsiclock_status = FLASH_HSICLOCK_ENABLE;
+
+ if ((RCC->CTRL & RCC_CTRL_HSIRDF) == RESET)
+ {
+ /* Enable HSI */
+ RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
+
+ /* Wait till HSI is ready and if Time out is reached exit */
+ do
+ {
+ HSIStatus = RCC->CTRL & RCC_CTRL_HSIRDF;
+ StartUpCounter++;
+ } while ((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));
+
+ HSIStatus = ((RCC->CTRL & RCC_CTRL_HSIRDF) != RESET);
+ if (!HSIStatus)
+ {
+ hsiclock_status = FLASH_HSICLOCK_DISABLE;
+ }
+ }
+ return hsiclock_status;
+}
+
+/**
+ * @brief Unlocks the FLASH Program Erase Controller.
+ * @note This function can be used for n32l40x devices.
+ * - For n32l40x devices this function unlocks Bank.
+ * to FLASH_Unlock function..
+ */
+void FLASH_Unlock(void)
+{
+ /* Unlocks the FLASH Program Erase Controller */
+ FLASH->KEYR = FLASH_KEY1;
+ FLASH->KEYR = FLASH_KEY2;
+}
+
+/**
+ * @brief Locks the FLASH Program Erase Controller.
+ * @note This function can be used for n32l40x devices.
+ * - For n32l40x devices this function Locks Bank.
+ * to FLASH_Lock function.
+ */
+void FLASH_Lock(void)
+{
+ /* Set the Lock Bit to lock the FLASH Program Erase Controller */
+ FLASH->CTRL |= CTRL_Set_LOCK;
+}
+
+/**
+ * @brief Erases a specified FLASH page.
+ * @note This function can be used for n32l40x devices.
+ * @param Page_Address The page address to be erased.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_EraseOnePage(uint32_t Page_Address)
+{
+ FLASH_STS status = FLASH_COMPL;
+ /* Check the parameters */
+ assert_param(IS_FLASH_ADDRESS(Page_Address));
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* if the previous operation is completed, proceed to erase the page */
+ FLASH->CTRL |= CTRL_Set_PER;
+ FLASH->ADD = Page_Address;
+ FLASH->CTRL |= CTRL_Set_START;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ /* Disable the PER Bit */
+ FLASH->CTRL &= CTRL_Reset_PER;
+ }
+
+ /* Return the Erase Status */
+ return status;
+}
+
+/**
+ * @brief Erases all FLASH pages.
+ * @note This function can be used for all n32l40x devices.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_MassErase(void)
+{
+ FLASH_STS status = FLASH_COMPL;
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+ if (status == FLASH_COMPL)
+ {
+ /* if the previous operation is completed, proceed to erase all pages */
+ FLASH->CTRL |= CTRL_Set_MER;
+ FLASH->CTRL |= CTRL_Set_START;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ /* Disable the MER Bit */
+ FLASH->CTRL &= CTRL_Reset_MER;
+ }
+
+ /* Return the Erase Status */
+ return status;
+}
+
+/**
+ * @brief Erases the FLASH option bytes.
+ * @note This functions erases all option bytes except the Read protection (RDP).
+ * @note This function can be used for n32l40x devices.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_EraseOB(void)
+{
+ uint32_t rdptmp = L1_RDP_Key;
+
+ FLASH_STS status = FLASH_COMPL;
+
+ /* Get the actual read protection L2 Option Byte value */
+ if (FLASH_GetReadOutProtectionL2STS() != RESET)
+ {
+ status = FLASH_ERR_RDP2;
+ return status;
+ }
+
+ /* Get the actual read protection Option Byte value */
+ if (FLASH_GetReadOutProtectionSTS() != RESET)
+ {
+ rdptmp = FLASH_USER_USER;
+ }
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Authorize the small information block programming */
+ FLASH->OPTKEY = FLASH_KEY1;
+ FLASH->OPTKEY = FLASH_KEY2;
+
+ /* if the previous operation is completed, proceed to erase the option bytes */
+ FLASH->CTRL |= CTRL_Set_OPTER;
+ FLASH->CTRL |= CTRL_Set_START;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* if the erase operation is completed, disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CTRL |= CTRL_Set_OPTPG;
+ /* Restore the last read protection Option Byte value */
+ OBT->USER_RDP = (uint32_t)rdptmp;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTPG;
+ }
+ }
+ else
+ {
+ if (status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+ }
+ }
+ }
+ /* Return the erase status */
+ return status;
+}
+
+
+/**
+ * @brief Programs the FLASH User Option Byte:
+ * RDP1 / IWDG_SW / RST_STOP2 / RST_STDBY / RST_PD / OB_Data0 / OB_Data1
+ * WRP_Pages / RDP2 / nBOOT0 / nBOOT1 / nSWBOOT0 / BOR_LEV[2:0].
+ * @note This function can be used for n32l40x devices.
+ * @param OB_RDP1
+ * This parameter can be one of the following values:
+ * @arg OB_RDP1_ENABLE
+ * @arg OB_RDP1_DISABLE
+ * @param OB_IWDG Selects the IWDG mode
+ * This parameter can be one of the following values:
+ * @arg OB_IWDG_SW Software IWDG selected
+ * @arg OB_IWDG_HW Hardware IWDG selected
+ * @param OB_STOP2 Reset event when entering STOP2 mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STOP2_NORST No reset generated when entering in STOP2
+ * @arg OB_STOP2_RST Reset generated when entering in STOP2
+ * @param OB_STDBY Reset event when entering Standby mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STDBY_NORST No reset generated when entering in STANDBY
+ * @arg OB_STDBY_RST Reset generated when entering in STANDBY
+ * @param OB_PD Reset event when entering PowerDown mode.
+ * This parameter can be one of the following values:
+ * @arg OB_PD_NORST No reset generated when entering in PowerDown
+ * @arg OB_PD_RST Reset generated when entering in PowerDown
+ * @param OB_Data0
+ * This parameter can be one of the following values:
+ * @arg 0x00 ~ 0xFF
+ * @param OB_Data1
+ * This parameter can be one of the following values:
+ * @arg 0x00 ~ 0xFF
+ * @param WRP_Pages specifies the address of the pages to be write protected.
+ * This parameter can be:
+ * @arg For @b n32l40x_devices: value between FLASH_WRP_Pages0to1 and
+ * FLASH_WRP_Pages62to63 or FLASH_WRP_AllPages or (~FLASH_WRP_AllPages)
+ * @param OB_RDP2
+ * This parameter can be one of the following values:
+ * @arg OB_RDP2_ENABLE
+ * @arg OB_RDP2_DISABLE
+ * @param OB2_nBOOT0
+ * This parameter can be one of the following values:
+ * @arg OB2_NBOOT0_SET Set nBOOT0
+ * @arg OB2_NBOOT0_CLR Clear nBOOT0
+ * @param OB2_nBOOT1
+ * This parameter can be one of the following values:
+ * @arg OB2_NBOOT1_SET Set nBOOT1
+ * @arg OB2_NBOOT1_CLR Clear nBOOT1
+ * @param OB2_nSWBOOT0
+ * This parameter can be one of the following values:
+ * @arg OB2_NSWBOOT0_SET Set nSWBOOT0
+ * @arg OB2_NSWBOOT0_CLR Clear nSWBOOT0
+* @param OB2_BOR_LEV[2:0]
+ * This parameter can be one of the following values:
+ * @arg OB2_BOR_LEV0
+ * @arg OB2_BOR_LEV1
+ * @arg OB2_BOR_LEV2
+ * @arg OB2_BOR_LEV3
+ * @arg OB2_BOR_LEV4
+ * @arg OB2_BOR_LEV5
+ * @arg OB2_BOR_LEV6
+ * @arg OB2_BOR_LEV7
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ConfigALLOptionByte(uint8_t OB_RDP1, uint8_t OB_IWDG, uint8_t OB_STOP2,
+ uint8_t OB_STDBY, uint8_t OB_PD, uint8_t OB_Data0,
+ uint8_t OB_Data1, uint32_t WRP_Pages, uint8_t OB_RDP2,
+ uint8_t OB2_nBOOT0, uint8_t OB2_nBOOT1, uint8_t OB2_nSWBOOT0,
+ uint8_t OB2_BOR_LEV)
+{
+ uint32_t rdpuser_tmp, data0data1_tmp, wrp0wrp1_tmp, wrp2wrp3_tmp, rdp2user2_tmp;
+
+ FLASH_STS status = FLASH_COMPL;
+
+ /* Check the parameters */
+ assert_param(IS_OB_RDP1_SOURCE(OB_RDP1));
+ assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
+ assert_param(IS_OB_STOP2_SOURCE(OB_STOP2));
+ assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
+ assert_param(IS_OB_PD_SOURCE(OB_PD));
+ assert_param(IS_FLASH_WRP_PAGE(WRP_Pages));
+ assert_param(IS_OB_RDP2_SOURCE(OB_RDP2));
+ assert_param(IS_OB2_NBOOT0_SOURCE(OB2_nBOOT0));
+ assert_param(IS_OB2_NBOOT1_SOURCE(OB2_nBOOT1));
+ assert_param(IS_OB2_NSWBOOT0_SOURCE(OB2_nSWBOOT0));
+ assert_param(IS_OB2_BOR_LEV_SOURCE(OB2_BOR_LEV));
+
+ /* Get the actual read protection L2 Option Byte value */
+ if (FLASH_GetReadOutProtectionL2STS() != RESET)
+ {
+ status = FLASH_ERR_RDP2;
+ return status;
+ }
+
+ WRP_Pages = (uint32_t)(~WRP_Pages);
+ rdpuser_tmp = (((uint32_t)OB_RDP1) | (((uint32_t)(OB_IWDG | OB_STOP2 | OB_STDBY | OB_PD)) << 16));
+ data0data1_tmp = (((uint32_t)OB_Data0) | (((uint32_t)OB_Data0) << 16));
+ wrp0wrp1_tmp = ((WRP_Pages & FLASH_WRP0_WRP0) | ((WRP_Pages << 8) & FLASH_WRP1_WRP1));
+ wrp2wrp3_tmp = (((WRP_Pages >> 16) & FLASH_WRP2_WRP2) | ((WRP_Pages >> 8) & FLASH_WRP3_WRP3));
+ rdp2user2_tmp = (((uint32_t)OB_RDP2) | (((uint32_t)(OB2_nBOOT0 | OB2_nBOOT1 | OB2_nSWBOOT0 | OB2_BOR_LEV)) << 16));
+
+ /* Authorize the small information block programming */
+ FLASH->OPTKEY = FLASH_KEY1;
+ FLASH->OPTKEY = FLASH_KEY2;
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+ if (status == FLASH_COMPL)
+ {
+ /* if the previous operation is completed, proceed to erase the option bytes */
+ FLASH->CTRL |= CTRL_Set_OPTER;
+ FLASH->CTRL |= CTRL_Set_START;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* if the erase operation is completed, disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CTRL |= CTRL_Set_OPTPG;
+
+ /* Program USER_RDP Option Byte value */
+ OBT->USER_RDP = (uint32_t)rdpuser_tmp;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* Program Data1_Data0 Option Byte value */
+ OBT->Data1_Data0 = (uint32_t)data0data1_tmp;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* Program WRP1_WRP0 Option Byte value */
+ OBT->WRP1_WRP0 = (uint32_t)wrp0wrp1_tmp;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* Program WRP3_WRP2 Option Byte value */
+ OBT->WRP3_WRP2 = (uint32_t)wrp2wrp3_tmp;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* Program USER2_RDP2 Option Byte value */
+ OBT->USER2_RDP2 = (uint32_t)rdp2user2_tmp;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+ }
+ }
+ }
+ }
+
+ if (status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTPG;
+ }
+ }
+ else
+ {
+ if (status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+ }
+ }
+ }
+
+ /* Return the Option Byte program Status */
+ return status;
+}
+
+/**
+ * @brief Programs a word at a specified address.
+ * @note This function can be used for n32l40x devices.
+ * @param Address specifies the address to be programmed.
+ * @param Data specifies the data to be programmed.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_ADD or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ProgramWord(uint32_t Address, uint32_t Data)
+{
+ FLASH_STS status = FLASH_COMPL;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_ADDRESS(Address));
+
+ if ((Address & (uint32_t)0x3) != 0)
+ {
+ /* The programming address is not a multiple of 4 */
+ status = FLASH_ERR_ADD;
+ return status;
+ }
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* if the previous operation is completed, proceed to program the new word */
+ FLASH->CTRL |= CTRL_Set_PG;
+
+ *(__IO uint32_t*)Address = (uint32_t)Data;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ /* Disable the PG Bit */
+ FLASH->CTRL &= CTRL_Reset_PG;
+ }
+
+ /* Return the Program Status */
+ return status;
+}
+
+/**
+ * @brief Programs a half word at a specified Option Byte Data address.
+ * @note This function can be used for n32l40x devices.
+ * @param Address specifies the address to be programmed.
+ * This parameter can be 0x1FFFF804.
+ * @param Data specifies the data to be programmed(Data0 and Data1).
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ProgramOBData(uint32_t Address, uint32_t Data)
+{
+ FLASH_STS status = FLASH_COMPL;
+ /* Check the parameters */
+ assert_param(IS_OB_DATA_ADDRESS(Address));
+
+ /* Get the actual read protection L2 Option Byte value */
+ if (FLASH_GetReadOutProtectionL2STS() != RESET)
+ {
+ status = FLASH_ERR_RDP2;
+ return status;
+ }
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Authorize the small information block programming */
+ FLASH->OPTKEY = FLASH_KEY1;
+ FLASH->OPTKEY = FLASH_KEY2;
+ /* Enables the Option Bytes Programming operation */
+ FLASH->CTRL |= CTRL_Set_OPTPG;
+ *(__IO uint32_t*)Address = (uint32_t)Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+ if (status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTPG;
+ }
+ }
+ /* Return the Option Byte Data Program Status */
+ return status;
+}
+
+/**
+ * @brief Write protects the desired pages
+ * @note This function can be used for n32l40x devices.
+ * @param FLASH_Pages specifies the address of the pages to be write protected.
+ * This parameter can be:
+ * @arg For @b n32l40x_devices: value between FLASH_WRP_Pages0to1 and
+ * FLASH_WRP_Pages60to61 or FLASH_WRP_Pages62to63
+ * @arg FLASH_WRP_AllPages
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_EnWriteProtection(uint32_t FLASH_Pages)
+{
+ uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
+
+ FLASH_STS status = FLASH_COMPL;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_WRP_PAGE(FLASH_Pages));
+
+ /* Get the actual read protection L2 Option Byte value */
+ if (FLASH_GetReadOutProtectionL2STS() != RESET)
+ {
+ status = FLASH_ERR_RDP2;
+ return status;
+ }
+
+ FLASH_Pages = (uint32_t)(~FLASH_Pages);
+ WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_MSK);
+ WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_MSK) >> 8);
+ WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_MSK) >> 16);
+ WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_MSK) >> 24);
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Authorizes the small information block programming */
+ FLASH->OPTKEY = FLASH_KEY1;
+ FLASH->OPTKEY = FLASH_KEY2;
+ FLASH->CTRL |= CTRL_Set_OPTPG;
+
+ if ((WRP0_Data != 0xFF) || (WRP1_Data != 0xFF))
+ {
+ OBT->WRP1_WRP0 = (((uint32_t)WRP0_Data) | (((uint32_t)WRP1_Data) << 16));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+ }
+
+ if (((WRP2_Data != 0xFF) || (WRP3_Data != 0xFF)) && (status == FLASH_COMPL))
+ {
+ OBT->WRP3_WRP2 = (((uint32_t)WRP2_Data) | (((uint32_t)WRP3_Data) << 16));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+ }
+
+ if (status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTPG;
+ }
+ }
+ /* Return the write protection operation Status */
+ return status;
+}
+
+/**
+ * @brief Enables or disables the read out protection.
+ * @note If the user has already programmed the other option bytes before calling
+ * this function, he must re-program them since this function erases all option bytes.
+ * @note This function can be used for n32l40x devices.
+ * @param Cmd new state of the ReadOut Protection.
+ * This parameter can be: ENABLE or DISABLE.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ReadOutProtectionL1(FunctionalState Cmd)
+{
+ uint32_t usertmp;
+ FLASH_STS status = FLASH_COMPL;
+
+ usertmp = ((OBR_USER_MSK & FLASH->OB) << 0x0E);
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ /* Get the actual read protection L2 Option Byte value */
+ if (FLASH_GetReadOutProtectionL2STS() != RESET)
+ {
+ status = FLASH_ERR_RDP2;
+ return status;
+ }
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Authorizes the small information block programming */
+ FLASH->OPTKEY = FLASH_KEY1;
+ FLASH->OPTKEY = FLASH_KEY2;
+ FLASH->CTRL |= CTRL_Set_OPTER;
+ FLASH->CTRL |= CTRL_Set_START;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* if the erase operation is completed, disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CTRL |= CTRL_Set_OPTPG;
+ if (Cmd != DISABLE)
+ {
+ OBT->USER_RDP = (FLASH_USER_USER & usertmp);
+ }
+ else
+ {
+ OBT->USER_RDP = ((L1_RDP_Key & FLASH_RDP_RDP1) | usertmp);
+ }
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTPG;
+ }
+ }
+ else
+ {
+ if (status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+ }
+ }
+ }
+ /* Return the protection operation Status */
+ return status;
+}
+
+/**
+ * @brief Enables or disables the read out protection L2.
+ * @note If the user has already programmed the other option bytes before calling
+ * this function, he must re-program them since this function erases all option bytes.
+ * @note This function can be used for n32l40x devices.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ReadOutProtectionL2_ENABLE(void)
+{
+ uint32_t usertmp;
+ FLASH_STS status = FLASH_COMPL;
+
+ usertmp = ((OBR_USER_MSK & FLASH->OB) << 0x0E);
+
+ /* Get the actual read protection L1 Option Byte value */
+ if (FLASH_GetReadOutProtectionSTS() == RESET)
+ {
+ usertmp |= (L1_RDP_Key & FLASH_RDP_RDP1);
+ }
+ /* Get the actual read protection L2 Option Byte value */
+ if (FLASH_GetReadOutProtectionL2STS() != RESET)
+ {
+ status = FLASH_ERR_RDP2;
+ return status;
+ }
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Authorizes the small information block programming */
+ FLASH->OPTKEY = FLASH_KEY1;
+ FLASH->OPTKEY = FLASH_KEY2;
+ FLASH->CTRL |= CTRL_Set_OPTER;
+ FLASH->CTRL |= CTRL_Set_START;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* if the erase operation is completed, disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CTRL |= CTRL_Set_OPTPG;
+
+ OBT->USER_RDP = usertmp;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* Enables the read out protection L2 */
+ OBT->USER2_RDP2 = L2_RDP_Key;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+ }
+
+ if (status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTPG;
+ }
+ }
+ else
+ {
+ if (status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+ }
+ }
+ }
+ /* Return the protection operation Status */
+ return status;
+}
+
+/**
+ * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
+ * @note This function can be used for n32l40x devices.
+ * @param OB_IWDG Selects the IWDG mode
+ * This parameter can be one of the following values:
+ * @arg OB_IWDG_SW Software IWDG selected
+ * @arg OB_IWDG_HW Hardware IWDG selected
+ * @param OB_STOP2 Reset event when entering STOP2 mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STOP2_NORST No reset generated when entering in STOP2
+ * @arg OB_STOP2_RST Reset generated when entering in STOP2
+ * @param OB_STDBY Reset event when entering Standby mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STDBY_NORST No reset generated when entering in STANDBY
+ * @arg OB_STDBY_RST Reset generated when entering in STANDBY
+ * @param OB_PD Reset event when entering PowerDown mode.
+ * This parameter can be one of the following values:
+ * @arg OB_PD_NORST No reset generated when entering in PowerDown
+ * @arg OB_PD_RST Reset generated when entering in PowerDown
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ConfigUserOB(uint8_t OB_IWDG, uint8_t OB_STOP2, uint8_t OB_STDBY, uint8_t OB_PD)
+{
+ uint32_t rdpuser_tmp = RDP_USER_Key;
+
+ FLASH_STS status = FLASH_COMPL;
+
+ /* Check the parameters */
+ assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
+ assert_param(IS_OB_STOP2_SOURCE(OB_STOP2));
+ assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
+ assert_param(IS_OB_PD_SOURCE(OB_PD));
+
+ /* Get the actual read protection L2 Option Byte value */
+ if (FLASH_GetReadOutProtectionL2STS() != RESET)
+ {
+ status = FLASH_ERR_RDP2;
+ return status;
+ }
+
+ /* Get the actual read protection Option Byte value */
+ if (FLASH_GetReadOutProtectionSTS() != RESET)
+ {
+ rdpuser_tmp = 0xFFF00000;
+ }
+
+ /* Authorize the small information block programming */
+ FLASH->OPTKEY = FLASH_KEY1;
+ FLASH->OPTKEY = FLASH_KEY2;
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* if the previous operation is completed, proceed to erase the option bytes */
+ FLASH->CTRL |= CTRL_Set_OPTER;
+ FLASH->CTRL |= CTRL_Set_START;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* if the erase operation is completed, disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CTRL |= CTRL_Set_OPTPG;
+ /* Restore the last read protection Option Byte value */
+ OBT->USER_RDP =
+ (uint32_t)rdpuser_tmp
+ | (((uint32_t)(OB_IWDG | OB_STOP2 | OB_STDBY | OB_PD)) << 16);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTPG;
+ }
+ }
+ else
+ {
+ if (status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+ }
+ }
+ }
+
+ /* Return the Option Byte program Status */
+ return status;
+}
+
+/**
+ * @brief Programs the FLASH User Option Byte: nBOOT0 / nBOOT1 / nSWBOOT0 / BOR_LEV[2:0].
+ * @note This function can be used for n32l40x devices.
+ * @param OB2_nBOOT0
+ * This parameter can be one of the following values:
+ * @arg OB2_NBOOT0_SET Set nBOOT0
+ * @arg OB2_NBOOT0_CLR Clear nBOOT0
+ * @param OB2_nBOOT1
+ * This parameter can be one of the following values:
+ * @arg OB2_NBOOT1_SET Set nBOOT1
+ * @arg OB2_NBOOT1_CLR Clear nBOOT1
+ * @param OB2_nSWBOOT0
+ * This parameter can be one of the following values:
+ * @arg OB2_NSWBOOT0_SET Set nSWBOOT0
+ * @arg OB2_NSWBOOT0_CLR Clear nSWBOOT0
+* @param OB2_BOR_LEV[2:0]
+ * This parameter can be one of the following values:
+ * @arg OB2_BOR_LEV0
+ * @arg OB2_BOR_LEV1
+ * @arg OB2_BOR_LEV2
+ * @arg OB2_BOR_LEV3
+ * @arg OB2_BOR_LEV4
+ * @arg OB2_BOR_LEV5
+ * @arg OB2_BOR_LEV6
+ * @arg OB2_BOR_LEV7
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ConfigUserOB2(uint8_t OB2_nBOOT0, uint8_t OB2_nBOOT1,
+ uint8_t OB2_nSWBOOT0, uint8_t OB2_BOR_LEV)
+{
+ uint32_t rdpuser_tmp = (RDP_USER_Key | FLASH_USER_USER);
+ uint32_t rdp2user2_tmp = 0xFF00FFFF;
+
+ FLASH_STS status = FLASH_COMPL;
+
+ /* Check the parameters */
+ assert_param(IS_OB2_NBOOT0_SOURCE(OB2_nBOOT0));
+ assert_param(IS_OB2_NBOOT1_SOURCE(OB2_nBOOT1));
+ assert_param(IS_OB2_NSWBOOT0_SOURCE(OB2_nSWBOOT0));
+ assert_param(IS_OB2_BOR_LEV_SOURCE(OB2_BOR_LEV));
+
+ /* Get the actual read protection L2 Option Byte value */
+ if (FLASH_GetReadOutProtectionL2STS() != RESET)
+ {
+ status = FLASH_ERR_RDP2;
+ return status;
+ }
+
+ /* Get the actual read protection Option Byte value */
+ if (FLASH_GetReadOutProtectionSTS() != RESET)
+ {
+ rdpuser_tmp = 0xFFFF0000;
+ }
+
+ /* Authorize the small information block programming */
+ FLASH->OPTKEY = FLASH_KEY1;
+ FLASH->OPTKEY = FLASH_KEY2;
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* if the previous operation is completed, proceed to erase the option bytes */
+ FLASH->CTRL |= CTRL_Set_OPTER;
+ FLASH->CTRL |= CTRL_Set_START;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* if the erase operation is completed, disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CTRL |= CTRL_Set_OPTPG;
+
+ /* Restore the last RDP1 Option Byte value */
+ OBT->USER_RDP = (uint32_t)rdpuser_tmp;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* Restore the last RDP2 Option Byte value */
+ OBT->USER2_RDP2 = (uint32_t)rdp2user2_tmp | (((uint32_t)(OB2_nBOOT0) | (uint32_t)(OB2_nBOOT1) \
+ | (uint32_t)(OB2_nSWBOOT0) | (uint32_t)(OB2_BOR_LEV)) << 16);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+ }
+
+ if (status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTPG;
+ }
+ }
+ else
+ {
+ if (status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+ }
+ }
+ }
+
+ /* Return the Option Byte program Status */
+ return status;
+}
+
+/**
+ * @brief Returns the FLASH User Option Bytes values.
+ * @note This function can be used for n32l40x devices.
+ * @return The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
+ * and RST_STDBY(Bit2).
+ */
+uint32_t FLASH_GetUserOB(void)
+{
+ /* Return the User Option Byte */
+ return (uint32_t)(FLASH->OB >> 2);
+}
+
+/**
+ * @brief Returns the FLASH Write Protection Option Bytes Register value.
+ * @note This function can be used for n32l40x devices.
+ * @return The FLASH Write Protection Option Bytes Register value
+ */
+uint32_t FLASH_GetWriteProtectionOB(void)
+{
+ /* Return the Flash write protection Register value */
+ return (uint32_t)(FLASH->WRP);
+}
+
+/**
+ * @brief Checks whether the FLASH Read Out Protection Status is set or not.
+ * @note This function can be used for n32l40x devices.
+ * @return FLASH ReadOut Protection Status(SET or RESET)
+ */
+FlagStatus FLASH_GetReadOutProtectionSTS(void)
+{
+ FlagStatus readoutstatus = RESET;
+ if ((FLASH->OB & RDPRTL1_MSK) != (uint32_t)RESET)
+ {
+ readoutstatus = SET;
+ }
+ else
+ {
+ readoutstatus = RESET;
+ }
+ return readoutstatus;
+}
+
+/**
+ * @brief Checks whether the FLASH Read Out Protection L2 Status is set or not.
+ * @note This function can be used for n32l40x devices.
+ * @return FLASH ReadOut Protection L2 Status(SET or RESET)
+ */
+FlagStatus FLASH_GetReadOutProtectionL2STS(void)
+{
+ FlagStatus readoutstatus = RESET;
+ if ((FLASH->OB & RDPRTL2_MSK) != (uint32_t)RESET)
+ {
+ readoutstatus = SET;
+ }
+ else
+ {
+ readoutstatus = RESET;
+ }
+ return readoutstatus;
+}
+
+/**
+ * @brief Checks whether the FLASH Prefetch Buffer status is set or not.
+ * @note This function can be used for n32l40x devices.
+ * @return FLASH Prefetch Buffer Status (SET or RESET).
+ */
+FlagStatus FLASH_GetPrefetchBufSTS(void)
+{
+ FlagStatus bitstatus = RESET;
+
+ if ((FLASH->AC & AC_PRFTBS_MSK) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */
+ return bitstatus;
+}
+
+/**
+ * @brief Checks whether the FLASH SMPSEL is SMP1 or SMP2.
+ * @note This function can be used for n32l40x devices.
+ * @return FLASH SMPSEL (FLASH_SMP1 or FLASH_SMP2).
+ */
+FLASH_SMPSEL FLASH_GetSMPSELStatus(void)
+{
+ FLASH_SMPSEL bitstatus = FLASH_SMP1;
+
+ if ((FLASH->CTRL & CTRL_Reset_SMPSEL) != (uint32_t)FLASH_SMP1)
+ {
+ bitstatus = FLASH_SMP2;
+ }
+ else
+ {
+ bitstatus = FLASH_SMP1;
+ }
+ /* Return the new state of FLASH SMPSEL (FLASH_SMP1 or FLASH_SMP2) */
+ return bitstatus;
+}
+
+/**
+ * @brief Enables or disables the specified FLASH interrupts.
+ * @note This function can be used for n32l40x devices.
+ * @param FLASH_INT specifies the FLASH interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_ERROR FLASH Error Interrupt
+ * @arg FLASH_INT_FERR EVERR PVERR Interrupt
+ * @arg FLASH_INT_EOP FLASH end of operation Interrupt
+ * @param Cmd new state of the specified Flash interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void FLASH_INTConfig(uint32_t FLASH_INT, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_INT(FLASH_INT));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the interrupt sources */
+ FLASH->CTRL |= FLASH_INT;
+ }
+ else
+ {
+ /* Disable the interrupt sources */
+ FLASH->CTRL &= ~(uint32_t)FLASH_INT;
+ }
+}
+
+/**
+ * @brief Checks whether the specified FLASH flag is set or not.
+ * @note This function can be used for n32l40x devices.
+ * @param FLASH_FLAG specifies the FLASH flag to check.
+ * This parameter can be one of the following values:
+ * @arg FLASH_FLAG_BUSY FLASH Busy flag
+ * @arg FLASH_FLAG_PGERR FLASH Program error flag
+ * @arg FLASH_FLAG_PVERR FLASH Program Verify ERROR flag
+ * @arg FLASH_FLAG_WRPERR FLASH Write protected error flag
+ * @arg FLASH_FLAG_EOP FLASH End of Operation flag
+ * @arg FLASH_FLAG_EVERR FLASH Erase Verify ERROR flag
+ * @arg FLASH_FLAG_OBERR FLASH Option Byte error flag
+ * @return The new state of FLASH_FLAG (SET or RESET).
+ */
+FlagStatus FLASH_GetFlagSTS(uint32_t FLASH_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));
+ if (FLASH_FLAG == FLASH_FLAG_OBERR)
+ {
+ if ((FLASH->OB & FLASH_FLAG_OBERR) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+ else
+ {
+ if ((FLASH->STS & FLASH_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+
+ /* Return the new state of FLASH_FLAG (SET or RESET) */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the FLASH's pending flags.
+ * @note This function can be used for n32l40x devices.
+ * @param FLASH_FLAG specifies the FLASH flags to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_FLAG_PGERR FLASH Program error flag
+ * @arg FLASH_FLAG_PVERR FLASH Program Verify ERROR flag
+ * @arg FLASH_FLAG_WRPERR FLASH Write protected error flag
+ * @arg FLASH_FLAG_EOP FLASH End of Operation flag
+ * @arg FLASH_FLAG_EVERR FLASH Erase Verify ERROR flag
+ */
+void FLASH_ClearFlag(uint32_t FLASH_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));
+
+ /* Clear the flags */
+ FLASH->STS |= FLASH_FLAG;
+}
+
+/**
+ * @brief Returns the FLASH Status.
+ * @note This function can be used for n32l40x devices, it is equivalent
+ * to FLASH_GetBank1Status function.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_GetSTS(void)
+{
+ FLASH_STS flashstatus = FLASH_COMPL;
+
+ if ((FLASH->STS & FLASH_FLAG_BUSY) == FLASH_FLAG_BUSY)
+ {
+ flashstatus = FLASH_BUSY;
+ }
+ else
+ {
+ if ((FLASH->STS & FLASH_FLAG_PGERR) != 0)
+ {
+ flashstatus = FLASH_ERR_PG;
+ }
+ else
+ {
+ if ((FLASH->STS & FLASH_FLAG_PVERR) != 0)
+ {
+ flashstatus = FLASH_ERR_PV;
+ }
+ else
+ {
+ if ((FLASH->STS & FLASH_FLAG_WRPERR) != 0)
+ {
+ flashstatus = FLASH_ERR_WRP;
+ }
+ else
+ {
+ if ((FLASH->STS & FLASH_FLAG_EVERR) != 0)
+ {
+ flashstatus = FLASH_ERR_EV;
+ }
+ else
+ {
+ flashstatus = FLASH_COMPL;
+ }
+ }
+ }
+ }
+ }
+
+ /* Return the Flash Status */
+ return flashstatus;
+}
+
+/**
+ * @brief Waits for a Flash operation to complete or a TIMEOUT to occur.
+ * @note This function can be used for n32l40x devices,
+ * it is equivalent to FLASH_WaitForLastBank1Operation..
+ * @param Timeout FLASH programming Timeout
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_WaitForLastOpt(uint32_t Timeout)
+{
+ FLASH_STS status = FLASH_COMPL;
+
+ /* Check for the Flash Status */
+ status = FLASH_GetSTS();
+ /* Wait for a Flash operation to complete or a TIMEOUT to occur */
+ while ((status == FLASH_BUSY) && (Timeout != 0x00))
+ {
+ status = FLASH_GetSTS();
+ Timeout--;
+ }
+ if (Timeout == 0x00)
+ {
+ status = FLASH_TIMEOUT;
+ }
+ /* Return the operation status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_gpio.c b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_gpio.c
new file mode 100644
index 0000000000..306ec598ef
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_gpio.c
@@ -0,0 +1,768 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_gpio.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l40x_gpio.h"
+#include "n32l40x_rcc.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @brief GPIO driver modules
+ * @{
+ */
+
+/** @addtogroup GPIO_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Private_Defines
+ * @{
+ */
+
+/* ------------ RCC registers bit address in the alias region ----------------*/
+#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)
+
+/* --- Event control register -----*/
+
+/* Alias word address of EVOE bit */
+#define EVCR_OFFSET (AFIO_OFFSET + 0x00)
+#define EVOE_BitNumber ((uint8_t)0x07)
+#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
+
+
+#define GPIO_MODE ((uint32_t)0x00000003)
+#define EXTI_MODE ((uint32_t)0x10000000)
+#define GPIO_MODE_IT ((uint32_t)0x00010000)
+#define GPIO_MODE_EVT ((uint32_t)0x00020000)
+#define RISING_EDGE ((uint32_t)0x00100000)
+#define FALLING_EDGE ((uint32_t)0x00200000)
+#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
+#define GPIO_PULLUP_PULLDOWN ((uint32_t)0x00000300)
+#define GPIO_NUMBER ((uint32_t)16)
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the GPIOx peripheral registers to their default reset values.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ */
+void GPIO_DeInit(GPIO_Module* GPIOx)
+{
+
+ uint32_t position = 0x00U;
+ uint32_t iocurrent = 0x00U;
+ uint32_t tmp = 0x00U;
+ uint32_t GPIO_Pin = GPIO_PIN_ALL;
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin));
+
+ if (GPIOx == GPIOA)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOA, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOA, DISABLE);
+ }
+ else if (GPIOx == GPIOB)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOB, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOB, DISABLE);
+ }
+ else if (GPIOx == GPIOC)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOC, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOC, DISABLE);
+ }
+ else if (GPIOx == GPIOD)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOD, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOD, DISABLE);
+ }
+ else
+ {
+ return;
+ }
+
+ /* Configure the port pins */
+ while ((GPIO_Pin >> position) != 0)
+ {
+ /* Get the IO position */
+ iocurrent = (GPIO_Pin) & ((uint32_t)0x01 << position);
+
+ if (iocurrent)
+ {
+ /*------------------------- EXTI Mode Configuration --------------------*/
+ /* Clear the External Interrupt or Event for the current IO */
+ tmp = AFIO->EXTI_CFG[position>>2];
+ tmp &= (0x0FuL << (4u*(position & 0x03u)));
+ if (tmp == (GPIO_GET_INDEX(GPIOx)<<(4u * (position & 0x03u))))
+ {
+ /* Clear EXTI line configuration */
+ EXTI->IMASK &= ~(iocurrent);
+ EXTI->EMASK &= ~(iocurrent);
+
+ /* Clear Rising Falling edge configuration */
+ EXTI->RT_CFG &= ~(iocurrent);
+ EXTI->FT_CFG &= ~(iocurrent);
+ tmp = 0x0FuL << (4u * (position & 0x03u));
+ AFIO->EXTI_CFG[position >> 2u] &= ~tmp;
+ }
+
+
+ /*------------------------- GPIO Mode Configuration --------------------*/
+ /* Configure IO Direction in Input Floting Mode */
+ GPIOx->PMODE &= ~(GPIO_PMODE0_Msk << (position * 2U));
+
+ /* Configure the default Alternate Function in current IO */
+ if (position & 0x08)
+ GPIOx->AFH |= ((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4U));
+ else
+ GPIOx->AFL |= ((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4U));
+
+ /* Configure the default value IO Output Type */
+ GPIOx->POTYPE &= ~(GPIO_POTYPE_POT_0 << position) ;
+
+ /* Deactivate the Pull-up oand Pull-down resistor for the current IO */
+ GPIOx->PUPD &= ~(GPIO_PUPD0_Msk << (position * 2U));
+
+ }
+ position++;
+ }
+}
+
+
+/**
+ * @brief Deinitializes the Alternate Functions (remap, event control
+ * and EXTI configuration) registers to their default reset values.
+ */
+void GPIO_AFIOInitDefault(void)
+{
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_AFIO, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_AFIO, DISABLE);
+}
+
+/**
+ * @brief Initializes the GPIOx peripheral according to the specified
+ * parameters in the GPIO_InitStruct.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param GPIO_InitStruct pointer to a GPIO_InitType structure that
+ * contains the configuration information for the specified GPIO peripheral.
+ */
+
+void GPIO_InitPeripheral(GPIO_Module* GPIOx, GPIO_InitType * GPIO_InitStruct)
+{
+ uint32_t pinpos = 0x00U;
+ uint32_t tmp = 0x00U,tmpregister=0x00U;
+ uint32_t position = 0x00U;
+ uint32_t iocurrent = 0x00U;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
+ assert_param(IS_GPIO_PIN(GPIO_InitStruct->Pin));
+ assert_param(IS_GPIO_PULL(GPIO_InitStruct->GPIO_Pull));
+ assert_param(IS_GPIO_SLEW_RATE(GPIO_InitStruct->GPIO_Slew_Rate));
+
+ /*---------------------------- GPIO Mode Configuration -----------------------*/
+
+ /*---------------------------- GPIO PL_CFG Configuration ------------------------*/
+
+ while (((GPIO_InitStruct->Pin)>>position) != 0)
+ {
+ iocurrent = (GPIO_InitStruct->Pin)&(1U<GPIO_Mode == GPIO_Mode_AF_PP) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF_OD) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_Input) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_Analog))
+ {
+ /* Check if the Alternate function is compliant with the GPIO in use */
+ assert_param(IS_GPIO_AF(GPIO_InitStruct->GPIO_Alternate));
+ /* Configure Alternate function mapped with the current IO */
+ if (position & 0x08)
+ {
+ tmp = GPIOx->AFH;
+ tmp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4U));
+ tmp |= ((uint32_t)(GPIO_InitStruct->GPIO_Alternate) << ((uint32_t)(position & (uint32_t)0x07) * 4U)) ;
+ GPIOx->AFH = tmp;
+ }
+ else
+ {
+ tmp = GPIOx->AFL;
+ tmp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4U)) ;
+ tmp |= ((uint32_t)(GPIO_InitStruct->GPIO_Alternate) << ((uint32_t)(position & (uint32_t)0x07) * 4U)) ;
+ GPIOx->AFL = tmp;
+ }
+ }
+ /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+ tmpregister = GPIOx->PMODE;
+ tmp = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
+ tmpregister &= ~(((uint32_t)0x03) << pinpos);
+ tmpregister |=( tmp << pinpos);
+ GPIOx->PMODE = tmpregister;
+
+ /* Configure pull-down mode */
+ tmpregister = GPIOx->PUPD;
+ tmp = (GPIO_InitStruct->GPIO_Pull & (uint32_t)0x03);
+ tmpregister &=~(((uint32_t)0x03) << pinpos);
+ tmpregister |= (tmp <PUPD = tmpregister;
+
+
+ /* Configure driver current*/
+ if ((GPIO_InitStruct->GPIO_Mode & GPIO_MODE) && (GPIO_InitStruct->GPIO_Mode != GPIO_Mode_Analog))
+ {
+ assert_param(IS_GPIO_CURRENT(GPIO_InitStruct->GPIO_Current));
+ tmpregister = GPIOx->DS;
+ tmp = (GPIO_InitStruct->GPIO_Current &((uint32_t)0x03));
+ tmpregister &= ~(((uint32_t)0x03) << pinpos);
+ tmpregister |= (tmp<DS = tmpregister;
+ }
+ /* Configure slew rate*/
+ tmp = GPIOx->SR;
+ tmp &=((uint32_t)(~((uint16_t)0x01 << position)));
+ tmp |= (GPIO_InitStruct->GPIO_Slew_Rate &((uint32_t)0x01))<SR = tmp;
+ /*Configure Set/Reset register*/
+ if (GPIO_InitStruct->GPIO_Pull == GPIO_Pull_Down)
+ {
+ GPIOx->PBC |= (((uint32_t)0x01) << position);
+ }
+ else
+ {
+ /* Set the corresponding POD bit */
+ if (GPIO_InitStruct->GPIO_Pull == GPIO_Pull_Up)
+ {
+ GPIOx->PBSC |= (((uint32_t)0x01) << position);
+ }
+ }
+
+ /* In case of Output or Alternate function mode selection */
+ if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_Out_PP) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF_PP) ||
+ (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_Out_OD) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF_OD))
+ {
+ /* Configure the IO Output Type */
+
+ tmp= GPIOx->POTYPE;
+ tmp &= ~(((uint32_t)0x01U) << position) ;
+ tmp |= (((GPIO_InitStruct->GPIO_Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
+ GPIOx->POTYPE = tmp;
+ }
+ /*--------------------- EXTI Mode Configuration ------------------------*/
+ /* Configure the External Interrupt or event for the current IO */
+ if (GPIO_InitStruct->GPIO_Mode & EXTI_MODE)
+ {
+ /* Clear EXTI line configuration */
+ tmp = EXTI->IMASK;
+ tmp &= ~((uint32_t)0x01<GPIO_Mode & GPIO_MODE_IT)== GPIO_MODE_IT)
+ {
+ tmp |= ((uint32_t)0x01 << position);
+ }
+ EXTI->IMASK = tmp;
+
+ tmp = EXTI->EMASK;
+ tmp &= ~((uint32_t)0x01<GPIO_Mode & GPIO_MODE_EVT)== GPIO_MODE_EVT)
+ {
+ tmp |= ((uint32_t)0x01 << position);
+ }
+ EXTI->EMASK = tmp;
+
+ /* Clear Rising Falling edge configuration */
+
+ tmp = EXTI->RT_CFG;
+ tmp &= ~((uint32_t)0x01<GPIO_Mode & RISING_EDGE)== RISING_EDGE)
+ {
+ tmp |= ((uint32_t)0x01 << position);
+ }
+ EXTI->RT_CFG = tmp;
+
+ tmp = EXTI->FT_CFG;
+ tmp &= ~((uint32_t)0x01<GPIO_Mode & FALLING_EDGE)== FALLING_EDGE)
+ {
+ tmp |= ((uint32_t)0x01 << position);
+ }
+ EXTI->FT_CFG = tmp;
+ }
+ }
+ position++;
+ }
+}
+
+/**
+ * @brief Fills each GPIO_InitStruct member with its default value.
+ * @param GPIO_InitStruct pointer to a GPIO_InitType structure which will
+ * be initialized.
+ */
+void GPIO_InitStruct(GPIO_InitType* GPIO_InitStruct)
+{
+ /* Reset GPIO init structure parameters values */
+ GPIO_InitStruct->Pin = GPIO_PIN_ALL;
+ GPIO_InitStruct->GPIO_Slew_Rate = GPIO_Slew_Rate_High;
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_Input;
+ GPIO_InitStruct->GPIO_Alternate = GPIO_NO_AF;
+ GPIO_InitStruct->GPIO_Pull = GPIO_No_Pull;
+ GPIO_InitStruct->GPIO_Current = GPIO_DC_2mA;
+}
+
+/**
+ * @brief Reads the specified input port pin.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param Pin specifies the port bit to read.
+ * This parameter can be GPIO_Pin_x where x can be (0..15).
+ * @return The input port pin value.
+ */
+uint8_t GPIO_ReadInputDataBit(GPIO_Module* GPIOx, uint16_t Pin)
+{
+ uint8_t bitstatus = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(Pin));
+
+ if ((GPIOx->PID & Pin) != (uint32_t)Bit_RESET)
+ {
+ bitstatus = (uint8_t)Bit_SET;
+ }
+ else
+ {
+ bitstatus = (uint8_t)Bit_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Reads the specified GPIO input data port.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @return GPIO input data port value.
+ */
+uint16_t GPIO_ReadInputData(GPIO_Module* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ return ((uint16_t)GPIOx->PID);
+}
+
+/**
+ * @brief Reads the specified output data port bit.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param Pin specifies the port bit to read.
+ * This parameter can be GPIO_Pin_x where x can be (0..15).
+ * @return The output port pin value.
+ */
+uint8_t GPIO_ReadOutputDataBit(GPIO_Module* GPIOx, uint16_t Pin)
+{
+ uint8_t bitstatus = 0x00;
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(Pin));
+
+ if ((GPIOx->POD & Pin) != (uint32_t)Bit_RESET)
+ {
+ bitstatus = (uint8_t)Bit_SET;
+ }
+ else
+ {
+ bitstatus = (uint8_t)Bit_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Reads the specified GPIO output data port.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @return GPIO output data port value.
+ */
+uint16_t GPIO_ReadOutputData(GPIO_Module* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ return ((uint16_t)GPIOx->POD);
+}
+
+/**
+ * @brief Sets the selected data port bits.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param Pin specifies the port bits to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ */
+void GPIO_SetBits(GPIO_Module* GPIOx, uint16_t Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(Pin));
+
+ GPIOx->PBSC = Pin;
+}
+void GPIO_SetBitsHigh16(GPIO_Module* GPIOx, uint32_t Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ // assert_param(IS_GPIO_PIN(Pin));
+
+ GPIOx->PBSC = Pin;
+}
+
+/**
+ * @brief Clears the selected data port bits.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param Pin specifies the port bits to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ */
+void GPIO_ResetBits(GPIO_Module* GPIOx, uint16_t Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(Pin));
+
+ GPIOx->PBC = Pin;
+}
+
+/**
+ * @brief Sets or clears the selected data port bit.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param Pin specifies the port bit to be written.
+ * This parameter can be one of GPIO_Pin_x where x can be (0..15).
+ * @param BitCmd specifies the value to be written to the selected bit.
+ * This parameter can be one of the Bit_OperateType enum values:
+ * @arg Bit_RESET to clear the port pin
+ * @arg Bit_SET to set the port pin
+ */
+void GPIO_WriteBit(GPIO_Module* GPIOx, uint16_t Pin, Bit_OperateType BitCmd)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(Pin));
+ assert_param(IS_GPIO_BIT_OPERATE(BitCmd));
+
+ if (BitCmd != Bit_RESET)
+ {
+ GPIOx->PBSC = Pin;
+ }
+ else
+ {
+ GPIOx->PBC = Pin;
+ }
+}
+
+/**
+ * @brief Writes data to the specified GPIO data port.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param PortVal specifies the value to be written to the port output data register.
+ */
+void GPIO_Write(GPIO_Module* GPIOx, uint16_t PortVal)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ GPIOx->POD = PortVal;
+}
+
+/**
+ * @brief Locks GPIO Pins configuration registers.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param Pin specifies the port bit to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ */
+void GPIO_ConfigPinLock(GPIO_Module* GPIOx, uint16_t Pin)
+{
+ uint32_t tmp = 0x00010000;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(Pin));
+
+ tmp |= Pin;
+ /* Set LCKK bit */
+ GPIOx->PLOCK = tmp;
+ /* Reset LCKK bit */
+ GPIOx->PLOCK = Pin;
+ /* Set LCKK bit */
+ GPIOx->PLOCK = tmp;
+ /* Read LCKK bit*/
+ tmp = GPIOx->PLOCK;
+ /* Read LCKK bit*/
+ tmp = GPIOx->PLOCK;
+}
+
+
+
+/**
+ * @brief Changes the mapping of the specified pin.
+ * @param PortSource selects the GPIO port to be used.
+ * @param PinSource specifies the pin for the remaping.
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).
+ * @param AlternateFunction specifies the alternate function for the remaping.
+ */
+void GPIO_ConfigPinRemap(uint8_t PortSource, uint8_t PinSource, uint32_t AlternateFunction)
+{
+ uint32_t tmp = 0x00, tmpregister = 0x00;
+ GPIO_Module *GPIOx;
+ /* Check the parameters */
+ assert_param(IS_GPIO_REMAP_PORT_SOURCE(PortSource));
+ assert_param(IS_GPIO_PIN_SOURCE(PinSource));
+ assert_param(IS_GPIO_AF(AlternateFunction));
+ /*Get Peripheral point*/
+ GPIOx = GPIO_GET_PERIPH(PortSource);
+ /**/
+ if (PinSource & (uint8_t)0x08)
+ {
+ tmp = (uint32_t)(PinSource & (uint8_t)0x07);
+ /*Read GPIO_AFH register*/
+ tmpregister = GPIOx->AFH;
+ /*Reset corresponding bits*/
+ tmpregister &=~((uint32_t)0x0F <<(tmp*4U));
+ /*Set corresponding bits*/
+ tmpregister |= AlternateFunction << (tmp*4U);
+ /*Write to the GPIO_AFH register*/
+ GPIOx->AFH = tmpregister;
+ }
+ else
+ {
+ tmp = (uint32_t)(PinSource & (uint8_t)0x07);
+ /*Read GPIO_AFL register*/
+ tmpregister = GPIOx->AFL;
+ /*Reset corresponding bits*/
+ tmpregister &=~((uint32_t)0x0F <<(tmp*4U));
+ /*Set corresponding bits*/
+ tmpregister |= AlternateFunction << (tmp*4U);
+ /*Write to the GPIO_AFL register*/
+ GPIOx->AFL = tmpregister;
+ }
+}
+
+/**
+ * @brief Selects the GPIO pin used as Event output.
+ * @param PortSource selects the GPIO port to be used as source
+ * for Event output.
+ * This parameter can be GPIO_PortSourceGPIOx where x can be (A..D).
+ * @param PinSource specifies the pin for the Event output.
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).
+ */
+void GPIO_ConfigEventOutput(uint8_t PortSource, uint8_t PinSource)
+{
+ uint32_t tmpregister = 0x00,tmp = 0x00;
+ GPIO_Module *GPIOx;
+ /* Check the parameters */
+ assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(PortSource));
+ assert_param(IS_GPIO_PIN_SOURCE(PinSource));
+
+ /*Get Peripheral structure point*/
+ GPIOx = GPIO_GET_PERIPH(PortSource);
+ if (PinSource & (uint8_t)0x08)
+ {
+ tmp = (uint32_t)(PinSource & (uint8_t)0x07);
+ /*Read GPIO_AFH register*/
+ tmpregister = GPIOx->AFH;
+ /*Reset corresponding bits*/
+ tmpregister &=~((uint32_t)0x0F <<(tmp*4U));
+ /*Set corresponding bits*/
+ tmpregister |= GPIO_AF3_EVENTOUT;
+ /*Write to the GPIO_AFH register*/
+ GPIOx->AFH = tmpregister;
+ }
+ else
+ {
+ tmp = (uint32_t)(PinSource & (uint8_t)0x07);
+ /*Read GPIO_AFL register*/
+ tmpregister = GPIOx->AFL;
+ /*Reset corresponding bits*/
+ tmpregister &=~((uint32_t)0x0F <<(tmp*4U));
+ /*Set corresponding bits*/
+ tmpregister |= GPIO_AF3_EVENTOUT;
+ /*Write to the GPIO_AFL register*/
+ GPIOx->AFL = tmpregister;
+ }
+}
+
+/**
+ * @brief Enables or disables the Event Output.
+ * @param Cmd new state of the Event output.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void GPIO_CtrlEventOutput(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ *(__IO uint32_t*)EVCR_EVOE_BB = (uint32_t)Cmd;
+}
+
+
+/**
+ * @brief Selects the GPIO pin used as EXTI Line.
+ * @param PortSource selects the GPIO port to be used as source for EXTI lines.
+ * This parameter can be GPIO_PortSourceGPIOx where x can be (A..D).
+ * @param PinSource specifies the EXTI line to be configured.
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).
+ */
+void GPIO_ConfigEXTILine(uint8_t PortSource, uint8_t PinSource)
+{
+ uint32_t port = (uint32_t)PortSource;
+ /* Check the parameters */
+ assert_param(IS_GPIO_EXTI_PORT_SOURCE(PortSource));
+ assert_param(IS_GPIO_PIN_SOURCE(PinSource));
+
+ AFIO->EXTI_CFG[(PinSource >> 0x02)] &= ~(((uint32_t)0x03) << ((PinSource & (uint8_t)0x03)*4u));
+ AFIO->EXTI_CFG[(PinSource >> 0x02)] |= (port << ((PinSource & (uint8_t)0x03) *4u));
+}
+
+/**
+ * @brief Selects the alternate function SPIx NSS mode.
+ * @param AFIO_SPIx_NSS choose which SPI configuration.
+ * This parameter can be AFIO_SPI1_NSS and AFIO_SPI2_NSS.
+ * @param SpiNssType specifies the SPI_NSS mode to be configured.
+ * This parameter can be AFIO_SPI1_NSS_High_IMPEDANCE and AFIO_SPI1_NSS_High_LEVEL.
+ */
+void AFIO_ConfigSPINSSMode(uint32_t AFIO_SPIx_NSS,AFIO_SPI_NSSType SpiNssType)
+{
+ uint32_t tmp = 0x00;
+ /* Check the parameters */
+ assert_param(IS_AFIO_SPIX(AFIO_SPIx_NSS));
+ assert_param(IS_AFIO_SPI_NSS(SpiNssType));
+ tmp = AFIO->RMP_CFG;
+ tmp &=(~(0x01U << AFIO_SPIx_NSS));
+ tmp |=(SpiNssType << AFIO_SPIx_NSS);
+ AFIO->RMP_CFG = tmp;
+}
+
+/**
+ * @brief Configur ADC external trigger.
+ * @param ADCETRType choose whether to configure rule conversion or injection conversion .
+ * This parameter can be AFIO_ADC_ETRI and AFIO_ADC_ETRR.
+ * @param ADCTrigRemap specifies the external trigger line be configured.
+ * This parameter can be AFIO_ADC_TRIG_EXTI_x where x can be (0..15) or AFIO_ADC_TRIG_TIM8_CHy where y can be(3..4).
+ */
+void AFIO_ConfigADCExternalTrigRemap(AFIO_ADC_ETRType ADCETRType,AFIO_ADC_Trig_RemapType ADCTrigRemap)
+{
+ uint32_t tmp = 0x00;
+ /* Check the parameters */
+ assert_param(IS_AFIO_ADC_ETR(ADCETRType));
+ if (ADCETRType == AFIO_ADC_ETRI)
+ {
+ /* Check the parameters */
+ assert_param(IS_AFIO_ADC_ETRI(ADCTrigRemap));
+ tmp = AFIO->RMP_CFG;
+ /* clear AFIO_RMP_CFG register ETRI bit*/
+ tmp &= (~(0x01U << AFIO_ADC_ETRI));
+ /* if ADCETRType is AFIO_ADC_ETRI then ADCTrigRemap cannot be AFIO_ADC_TRIG_TIM8_CH3*/
+ if (ADCTrigRemap == AFIO_ADC_TRIG_TIM8_CH4)
+ {
+ /* select TIM8_CH4 line to connect*/
+ tmp |= (0x01U << AFIO_ADC_ETRI);
+ }
+ else
+ {
+ /* select which external line is connected*/
+ tmp &=(~(0x0FU<<4U));
+ tmp |= (ADCTrigRemap<<4U);
+ }
+ AFIO->RMP_CFG = tmp;
+ }
+ else
+ {
+ if (ADCETRType == AFIO_ADC_ETRR)
+ {
+ /* Check the parameters */
+ assert_param(IS_AFIO_ADC_ETRR(ADCTrigRemap));
+ tmp = AFIO->RMP_CFG;
+ /* clear AFIO_RMP_CFG register ETRR bit*/
+ tmp &= (~(0x01U << AFIO_ADC_ETRR));
+ /* if ADCETRType is AFIO_ADC_ETRR then ADCTrigRemap cannot be AFIO_ADC_TRIG_TIM8_CH4*/
+ if (ADCTrigRemap == AFIO_ADC_TRIG_TIM8_CH3)
+ {
+ /* select TIM8_CH3 line to connect*/
+ tmp |= (0x01U << AFIO_ADC_ETRR);
+ }
+ else
+ {
+ /* select which external line is connected*/
+ tmp &=(~(0x0FU<<0));
+ tmp |= ADCTrigRemap;
+ }
+ AFIO->RMP_CFG = tmp;
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_i2c.c b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_i2c.c
new file mode 100644
index 0000000000..e056e7de51
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_i2c.c
@@ -0,0 +1,1301 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_i2c.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l40x_i2c.h"
+#include "n32l40x_rcc.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @brief I2C driver modules
+ * @{
+ */
+
+/** @addtogroup I2C_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_Defines
+ * @{
+ */
+
+/* I2C SPE mask */
+#define CTRL1_SPEN_SET ((uint16_t)0x0001)
+#define CTRL1_SPEN_RESET ((uint16_t)0xFFFE)
+
+/* I2C START mask */
+#define CTRL1_START_SET ((uint16_t)0x0100)
+#define CTRL1_START_RESET ((uint16_t)0xFEFF)
+
+/* I2C STOP mask */
+#define CTRL1_STOP_SET ((uint16_t)0x0200)
+#define CTRL1_STOP_RESET ((uint16_t)0xFDFF)
+
+/* I2C ACK mask */
+#define CTRL1_ACK_SET ((uint16_t)0x0400)
+#define CTRL1_ACK_RESET ((uint16_t)0xFBFF)
+
+/* I2C ENGC mask */
+#define CTRL1_GCEN_SET ((uint16_t)0x0040)
+#define CTRL1_GCEN_RESET ((uint16_t)0xFFBF)
+
+/* I2C SWRST mask */
+#define CTRL1_SWRESET_SET ((uint16_t)0x8000)
+#define CTRL1_SWRESET_RESET ((uint16_t)0x7FFF)
+
+/* I2C PEC mask */
+#define CTRL1_PEC_SET ((uint16_t)0x1000)
+#define CTRL1_PEC_RESET ((uint16_t)0xEFFF)
+
+/* I2C ENPEC mask */
+#define CTRL1_PECEN_SET ((uint16_t)0x0020)
+#define CTRL1_PECEN_RESET ((uint16_t)0xFFDF)
+
+/* I2C ENARP mask */
+#define CTRL1_ARPEN_SET ((uint16_t)0x0010)
+#define CTRL1_ARPEN_RESET ((uint16_t)0xFFEF)
+
+/* I2C NOSTRETCH mask */
+#define CTRL1_NOEXTEND_SET ((uint16_t)0x0080)
+#define CTRL1_NOEXTEND_RESET ((uint16_t)0xFF7F)
+
+/* I2C registers Masks */
+#define CTRL1_CLR_MASK ((uint16_t)0xFBF5)
+
+/* I2C DMAEN mask */
+#define CTRL2_DMAEN_SET ((uint16_t)0x0800)
+#define CTRL2_DMAEN_RESET ((uint16_t)0xF7FF)
+
+/* I2C LAST mask */
+#define CTRL2_DMALAST_SET ((uint16_t)0x1000)
+#define CTRL2_DMALAST_RESET ((uint16_t)0xEFFF)
+
+/* I2C FREQ mask */
+#define CTRL2_CLKFREQ_RESET ((uint16_t)0xFFC0)
+
+/* I2C ADD0 mask */
+#define OADDR1_ADDR0_SET ((uint16_t)0x0001)
+#define OADDR1_ADDR0_RESET ((uint16_t)0xFFFE)
+
+/* I2C ENDUAL mask */
+#define OADDR2_DUALEN_SET ((uint16_t)0x0001)
+#define OADDR2_DUALEN_RESET ((uint16_t)0xFFFE)
+
+/* I2C ADD2 mask */
+#define OADDR2_ADDR2_RESET ((uint16_t)0xFF01)
+
+/* I2C F/S mask */
+#define CLKCTRL_FSMODE_SET ((uint16_t)0x8000)
+
+/* I2C CHCFG mask */
+#define CLKCTRL_CLKCTRL_SET ((uint16_t)0x0FFF)
+
+/* I2C FLAG mask */
+#define FLAG_MASK ((uint32_t)0x00FFFFFF)
+
+/* I2C Interrupt Enable mask */
+#define INTEN_MASK ((uint32_t)0x07000000)
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the I2Cx peripheral registers to their default reset values.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ */
+void I2C_DeInit(I2C_Module* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+
+ if (I2Cx == I2C1)
+ {
+ /* Enable I2C1 reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C1, ENABLE);
+ /* Release I2C1 from reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C1, DISABLE);
+ }
+ else
+ {
+ /* Enable I2C2 reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C2, ENABLE);
+ /* Release I2C2 from reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C2, DISABLE);
+ }
+}
+
+/**
+ * @brief Initializes the I2Cx peripheral according to the specified
+ * parameters in the I2C_InitStruct.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_InitStruct pointer to a I2C_InitType structure that
+ * contains the configuration information for the specified I2C peripheral.
+ */
+void I2C_Init(I2C_Module* I2Cx, I2C_InitType* I2C_InitStruct)
+{
+ uint16_t tmpregister = 0, freqrange = 0;
+ uint16_t result = 0x04;
+ uint32_t pclk1 = 8000000;
+ RCC_ClocksType rcc_clocks;
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_CLK_SPEED(I2C_InitStruct->ClkSpeed));
+ assert_param(IS_I2C_BUS_MODE(I2C_InitStruct->BusMode));
+ assert_param(IS_I2C_FM_DUTY_CYCLE(I2C_InitStruct->FmDutyCycle));
+ assert_param(IS_I2C_OWN_ADDR1(I2C_InitStruct->OwnAddr1));
+ assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->AckEnable));
+ assert_param(IS_I2C_ADDR_MODE(I2C_InitStruct->AddrMode));
+
+ /*---------------------------- I2Cx CTRL2 Configuration ------------------------*/
+ /* Get the I2Cx CTRL2 value */
+ tmpregister = I2Cx->CTRL2;
+ /* Clear frequency FREQ[5:0] bits */
+ tmpregister &= CTRL2_CLKFREQ_RESET;
+ /* Get pclk1 frequency value */
+ RCC_GetClocksFreqValue(&rcc_clocks);
+ pclk1 = rcc_clocks.Pclk1Freq;
+ /* Set frequency bits depending on pclk1 value */
+ freqrange = (uint16_t)(pclk1 / 1000000);
+ tmpregister |= freqrange;
+ /* Write to I2Cx CTRL2 */
+ I2Cx->CTRL2 = tmpregister;
+
+ /*---------------------------- I2Cx CHCFG Configuration ------------------------*/
+ /* Disable the selected I2C peripheral to configure TMRISE */
+ I2Cx->CTRL1 &= CTRL1_SPEN_RESET;
+ /* Reset tmpregister value */
+ /* Clear F/S, DUTY and CHCFG[11:0] bits */
+ tmpregister = 0;
+
+ /* Configure speed in standard mode */
+ if (I2C_InitStruct->ClkSpeed <= 100000)
+ {
+ /* Standard mode speed calculate */
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->ClkSpeed << 1));
+ /* Test if CHCFG value is under 0x4*/
+ if (result < 0x04)
+ {
+ /* Set minimum allowed value */
+ result = 0x04;
+ }
+ /* Set speed value for standard mode */
+ tmpregister |= result;
+ /* Set Maximum Rise Time for standard mode */
+ I2Cx->TMRISE = freqrange + 1;
+ }
+ /* Configure speed in fast mode */
+ // else if ((I2C_InitStruct->ClkSpeed > 100000)&&(I2C_InitStruct->ClkSpeed <= 400000))/*(I2C_InitStruct->ClkSpeed <=
+ // 400000)*/
+ else
+ {
+ if (I2C_InitStruct->FmDutyCycle == I2C_FMDUTYCYCLE_2)
+ {
+ /* Fast mode speed calculate: Tlow/Thigh = 2 */
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->ClkSpeed * 3));
+ }
+ else /*I2C_InitStruct->FmDutyCycle == I2C_FMDUTYCYCLE_16_9*/
+ {
+ /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->ClkSpeed * 25));
+ /* Set DUTY bit */
+ result |= I2C_FMDUTYCYCLE_16_9;
+ }
+
+ /* Test if CHCFG value is under 0x1*/
+ if ((result & CLKCTRL_CLKCTRL_SET) == 0)
+ {
+ /* Set minimum allowed value */
+ result |= (uint16_t)0x0001;
+ }
+ /* Set speed value and set F/S bit for fast mode */
+ tmpregister |= (uint16_t)(result | CLKCTRL_FSMODE_SET);
+ /* Set Maximum Rise Time for fast mode */
+ // if (I2C_InitStruct->ClkSpeed <= 400000)
+ {
+ I2Cx->TMRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
+ }
+ // else//add test
+ //{
+ // I2Cx->TMRISE = (uint16_t)(((freqrange * (uint16_t)100) / (uint16_t)1000) + (uint16_t)1);
+ //}
+ }
+ /* Write to I2Cx CHCFG */
+ I2Cx->CLKCTRL = tmpregister;
+ /* Enable the selected I2C peripheral */
+ I2Cx->CTRL1 |= CTRL1_SPEN_SET;
+
+ /*---------------------------- I2Cx CTRL1 Configuration ------------------------*/
+ /* Get the I2Cx CTRL1 value */
+ tmpregister = I2Cx->CTRL1;
+ /* Clear ACK, SMBTYPE and SMBUS bits */
+ tmpregister &= CTRL1_CLR_MASK;
+ /* Configure I2Cx: mode and acknowledgement */
+ /* Set SMBTYPE and SMBUS bits according to BusMode value */
+ /* Set ACK bit according to AckEnable value */
+ tmpregister |= (uint16_t)((uint32_t)I2C_InitStruct->BusMode | I2C_InitStruct->AckEnable);
+ /* Write to I2Cx CTRL1 */
+ I2Cx->CTRL1 = tmpregister;
+
+ /*---------------------------- I2Cx OADDR1 Configuration -----------------------*/
+ /* Set I2Cx Own Address1 and acknowledged address */
+ I2Cx->OADDR1 = (I2C_InitStruct->AddrMode | I2C_InitStruct->OwnAddr1);
+}
+
+/**
+ * @brief Fills each I2C_InitStruct member with its default value.
+ * @param I2C_InitStruct pointer to an I2C_InitType structure which will be initialized.
+ */
+void I2C_InitStruct(I2C_InitType* I2C_InitStruct)
+{
+ /*---------------- Reset I2C init structure parameters values ----------------*/
+ /* initialize the ClkSpeed member */
+ I2C_InitStruct->ClkSpeed = 5000;
+ /* Initialize the BusMode member */
+ I2C_InitStruct->BusMode = I2C_BUSMODE_I2C;
+ /* Initialize the FmDutyCycle member */
+ I2C_InitStruct->FmDutyCycle = I2C_FMDUTYCYCLE_2;
+ /* Initialize the OwnAddr1 member */
+ I2C_InitStruct->OwnAddr1 = 0;
+ /* Initialize the AckEnable member */
+ I2C_InitStruct->AckEnable = I2C_ACKDIS;
+ /* Initialize the AddrMode member */
+ I2C_InitStruct->AddrMode = I2C_ADDR_MODE_7BIT;
+}
+
+/**
+ * @brief Enables or disables the specified I2C peripheral.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2Cx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_Enable(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected I2C peripheral */
+ I2Cx->CTRL1 |= CTRL1_SPEN_SET;
+ }
+ else
+ {
+ /* Disable the selected I2C peripheral */
+ I2Cx->CTRL1 &= CTRL1_SPEN_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C DMA requests.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C DMA transfer.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableDMA(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected I2C DMA requests */
+ I2Cx->CTRL2 |= CTRL2_DMAEN_SET;
+ }
+ else
+ {
+ /* Disable the selected I2C DMA requests */
+ I2Cx->CTRL2 &= CTRL2_DMAEN_RESET;
+ }
+}
+
+/**
+ * @brief Specifies if the next DMA transfer will be the last one.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C DMA last transfer.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableDmaLastSend(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Next DMA transfer is the last transfer */
+ I2Cx->CTRL2 |= CTRL2_DMALAST_SET;
+ }
+ else
+ {
+ /* Next DMA transfer is not the last transfer */
+ I2Cx->CTRL2 &= CTRL2_DMALAST_RESET;
+ }
+}
+
+/**
+ * @brief Generates I2Cx communication START condition.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C START condition generation.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_GenerateStart(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Generate a START condition */
+ I2Cx->CTRL1 |= CTRL1_START_SET;
+ }
+ else
+ {
+ /* Disable the START condition generation */
+ I2Cx->CTRL1 &= CTRL1_START_RESET;
+ }
+}
+
+/**
+ * @brief Generates I2Cx communication STOP condition.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C STOP condition generation.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_GenerateStop(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Generate a STOP condition */
+ I2Cx->CTRL1 |= CTRL1_STOP_SET;
+ }
+ else
+ {
+ /* Disable the STOP condition generation */
+ I2Cx->CTRL1 &= CTRL1_STOP_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C acknowledge feature.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C Acknowledgement.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_ConfigAck(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the acknowledgement */
+ I2Cx->CTRL1 |= CTRL1_ACK_SET;
+ }
+ else
+ {
+ /* Disable the acknowledgement */
+ I2Cx->CTRL1 &= CTRL1_ACK_RESET;
+ }
+}
+
+/**
+ * @brief Configures the specified I2C own address2.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Address specifies the 7bit I2C own address2.
+ */
+void I2C_ConfigOwnAddr2(I2C_Module* I2Cx, uint8_t Address)
+{
+ uint16_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+
+ /* Get the old register value */
+ tmpregister = I2Cx->OADDR2;
+
+ /* Reset I2Cx Own address2 bit [7:1] */
+ tmpregister &= OADDR2_ADDR2_RESET;
+
+ /* Set I2Cx Own address2 */
+ tmpregister |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
+
+ /* Store the new register value */
+ I2Cx->OADDR2 = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the specified I2C dual addressing mode.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C dual addressing mode.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableDualAddr(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable dual addressing mode */
+ I2Cx->OADDR2 |= OADDR2_DUALEN_SET;
+ }
+ else
+ {
+ /* Disable dual addressing mode */
+ I2Cx->OADDR2 &= OADDR2_DUALEN_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C general call feature.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C General call.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableGeneralCall(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable generall call */
+ I2Cx->CTRL1 |= CTRL1_GCEN_SET;
+ }
+ else
+ {
+ /* Disable generall call */
+ I2Cx->CTRL1 &= CTRL1_GCEN_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C interrupts.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT specifies the I2C interrupts sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_INT_BUF Buffer interrupt mask
+ * @arg I2C_INT_EVENT Event interrupt mask
+ * @arg I2C_INT_ERR Error interrupt mask
+ * @param Cmd new state of the specified I2C interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_ConfigInt(I2C_Module* I2Cx, uint16_t I2C_IT, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ assert_param(IS_I2C_CFG_INT(I2C_IT));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected I2C interrupts */
+ I2Cx->CTRL2 |= I2C_IT;
+ }
+ else
+ {
+ /* Disable the selected I2C interrupts */
+ I2Cx->CTRL2 &= (uint16_t)~I2C_IT;
+ }
+}
+
+/**
+ * @brief Sends a data byte through the I2Cx peripheral.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Data Byte to be transmitted..
+ */
+void I2C_SendData(I2C_Module* I2Cx, uint8_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ /* Write in the DAT register the data to be sent */
+ I2Cx->DAT = Data;
+}
+
+/**
+ * @brief Returns the most recent received data by the I2Cx peripheral.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @return The value of the received data.
+ */
+uint8_t I2C_RecvData(I2C_Module* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ /* Return the data in the DAT register */
+ return (uint8_t)I2Cx->DAT;
+}
+
+/**
+ * @brief Transmits the address byte to select the slave device.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Address specifies the slave address which will be transmitted
+ * @param I2C_Direction specifies whether the I2C device will be a
+ * Transmitter or a Receiver. This parameter can be one of the following values
+ * @arg I2C_DIRECTION_SEND Transmitter mode
+ * @arg I2C_DIRECTION_RECV Receiver mode
+ */
+void I2C_SendAddr7bit(I2C_Module* I2Cx, uint8_t Address, uint8_t I2C_Direction)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_DIRECTION(I2C_Direction));
+ /* Test on the direction to set/reset the read/write bit */
+ if (I2C_Direction != I2C_DIRECTION_SEND)
+ {
+ /* Set the address bit0 for read */
+ Address |= OADDR1_ADDR0_SET;
+ }
+ else
+ {
+ /* Reset the address bit0 for write */
+ Address &= OADDR1_ADDR0_RESET;
+ }
+ /* Send the address */
+ I2Cx->DAT = Address;
+}
+
+/**
+ * @brief Reads the specified I2C register and returns its value.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_Register specifies the register to read.
+ * This parameter can be one of the following values:
+ * @arg I2C_REG_CTRL1 CTRL1 register.
+ * @arg I2C_REG_CTRL2 CTRL2 register.
+ * @arg I2C_REG_OADDR1 OADDR1 register.
+ * @arg I2C_REG_OADDR2 OADDR2 register.
+ * @arg I2C_REG_DAT DAT register.
+ * @arg I2C_REG_STS1 STS1 register.
+ * @arg I2C_REG_STS2 STS2 register.
+ * @arg I2C_REG_CLKCTRL CHCFG register.
+ * @arg I2C_REG_TMRISE TMRISE register.
+ * @return The value of the read register.
+ */
+uint16_t I2C_GetRegister(I2C_Module* I2Cx, uint8_t I2C_Register)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_REG(I2C_Register));
+
+ tmp = (uint32_t)I2Cx;
+ tmp += I2C_Register;
+
+ /* Return the selected register value */
+ return (*(__IO uint16_t*)tmp);
+}
+
+/**
+ * @brief Enables or disables the specified I2C software reset.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C software reset.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableSoftwareReset(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Peripheral under reset */
+ I2Cx->CTRL1 |= CTRL1_SWRESET_SET;
+ }
+ else
+ {
+ /* Peripheral not under reset */
+ I2Cx->CTRL1 &= CTRL1_SWRESET_RESET;
+ }
+}
+
+/**
+ * @brief Selects the specified I2C NACK position in master receiver mode.
+ * This function is useful in I2C Master Receiver mode when the number
+ * of data to be received is equal to 2. In this case, this function
+ * should be called (with parameter I2C_NACK_POS_NEXT) before data
+ * reception starts,as described in the 2-byte reception procedure
+ * recommended in Reference Manual in Section: Master receiver.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_NACKPosition specifies the NACK position.
+ * This parameter can be one of the following values:
+ * @arg I2C_NACK_POS_NEXT indicates that the next byte will be the last
+ * received byte.
+ * @arg I2C_NACK_POS_CURRENT indicates that current byte is the last
+ * received byte.
+ *
+ * @note This function configures the same bit (POS) as I2C_ConfigPecLocation()
+ * but is intended to be used in I2C mode while I2C_ConfigPecLocation()
+ * is intended to used in SMBUS mode.
+ *
+ */
+void I2C_ConfigNackLocation(I2C_Module* I2Cx, uint16_t I2C_NACKPosition)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_NACK_POS(I2C_NACKPosition));
+
+ /* Check the input parameter */
+ if (I2C_NACKPosition == I2C_NACK_POS_NEXT)
+ {
+ /* Next byte in shift register is the last received byte */
+ I2Cx->CTRL1 |= I2C_NACK_POS_NEXT;
+ }
+ else
+ {
+ /* Current byte in shift register is the last received byte */
+ I2Cx->CTRL1 &= I2C_NACK_POS_CURRENT;
+ }
+}
+
+/**
+ * @brief Drives the SMBusAlert pin high or low for the specified I2C.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_SMBusAlert specifies SMBAlert pin level.
+ * This parameter can be one of the following values:
+ * @arg I2C_SMBALERT_LOW SMBAlert pin driven low
+ * @arg I2C_SMBALERT_HIGH SMBAlert pin driven high
+ */
+void I2C_ConfigSmbusAlert(I2C_Module* I2Cx, uint16_t I2C_SMBusAlert)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_SMB_ALERT(I2C_SMBusAlert));
+ if (I2C_SMBusAlert == I2C_SMBALERT_LOW)
+ {
+ /* Drive the SMBusAlert pin Low */
+ I2Cx->CTRL1 |= I2C_SMBALERT_LOW;
+ }
+ else
+ {
+ /* Drive the SMBusAlert pin High */
+ I2Cx->CTRL1 &= I2C_SMBALERT_HIGH;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C PEC transfer.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C PEC transmission.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_SendPEC(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected I2C PEC transmission */
+ I2Cx->CTRL1 |= CTRL1_PEC_SET;
+ }
+ else
+ {
+ /* Disable the selected I2C PEC transmission */
+ I2Cx->CTRL1 &= CTRL1_PEC_RESET;
+ }
+}
+
+/**
+ * @brief Selects the specified I2C PEC position.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_PECPosition specifies the PEC position.
+ * This parameter can be one of the following values:
+ * @arg I2C_PEC_POS_NEXT indicates that the next byte is PEC
+ * @arg I2C_PEC_POS_CURRENT indicates that current byte is PEC
+ *
+ * @note This function configures the same bit (POS) as I2C_ConfigNackLocation()
+ * but is intended to be used in SMBUS mode while I2C_ConfigNackLocation()
+ * is intended to used in I2C mode.
+ *
+ */
+void I2C_ConfigPecLocation(I2C_Module* I2Cx, uint16_t I2C_PECPosition)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_PEC_POS(I2C_PECPosition));
+ if (I2C_PECPosition == I2C_PEC_POS_NEXT)
+ {
+ /* Next byte in shift register is PEC */
+ I2Cx->CTRL1 |= I2C_PEC_POS_NEXT;
+ }
+ else
+ {
+ /* Current byte in shift register is PEC */
+ I2Cx->CTRL1 &= I2C_PEC_POS_CURRENT;
+ }
+}
+
+/**
+ * @brief Enables or disables the PEC value calculation of the transferred bytes.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2Cx PEC value calculation.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_ComputePec(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected I2C PEC calculation */
+ I2Cx->CTRL1 |= CTRL1_PECEN_SET;
+ }
+ else
+ {
+ /* Disable the selected I2C PEC calculation */
+ I2Cx->CTRL1 &= CTRL1_PECEN_RESET;
+ }
+}
+
+/**
+ * @brief Returns the PEC value for the specified I2C.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @return The PEC value.
+ */
+uint8_t I2C_GetPec(I2C_Module* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ /* Return the selected I2C PEC value */
+ return ((I2Cx->STS2) >> 8);
+}
+
+/**
+ * @brief Enables or disables the specified I2C ARP.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2Cx ARP.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableArp(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected I2C ARP */
+ I2Cx->CTRL1 |= CTRL1_ARPEN_SET;
+ }
+ else
+ {
+ /* Disable the selected I2C ARP */
+ I2Cx->CTRL1 &= CTRL1_ARPEN_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C Clock stretching.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2Cx Clock stretching.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableExtendClk(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd == DISABLE)
+ {
+ /* Enable the selected I2C Clock stretching */
+ I2Cx->CTRL1 |= CTRL1_NOEXTEND_SET;
+ }
+ else
+ {
+ /* Disable the selected I2C Clock stretching */
+ I2Cx->CTRL1 &= CTRL1_NOEXTEND_RESET;
+ }
+}
+
+/**
+ * @brief Selects the specified I2C fast mode duty cycle.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param FmDutyCycle specifies the fast mode duty cycle.
+ * This parameter can be one of the following values:
+ * @arg I2C_FMDUTYCYCLE_2 I2C fast mode Tlow/Thigh = 2
+ * @arg I2C_FMDUTYCYCLE_16_9 I2C fast mode Tlow/Thigh = 16/9
+ */
+void I2C_ConfigFastModeDutyCycle(I2C_Module* I2Cx, uint16_t FmDutyCycle)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_FM_DUTY_CYCLE(FmDutyCycle));
+ if (FmDutyCycle != I2C_FMDUTYCYCLE_16_9)
+ {
+ /* I2C fast mode Tlow/Thigh=2 */
+ I2Cx->CLKCTRL &= I2C_FMDUTYCYCLE_2;
+ }
+ else
+ {
+ /* I2C fast mode Tlow/Thigh=16/9 */
+ I2Cx->CLKCTRL |= I2C_FMDUTYCYCLE_16_9;
+ }
+}
+
+/**
+ * @brief
+ ****************************************************************************************
+ *
+ * I2C State Monitoring Functions
+ *
+ ****************************************************************************************
+ * This I2C driver provides three different ways for I2C state monitoring
+ * depending on the application requirements and constraints:
+ *
+ *
+ * 1) Basic state monitoring:
+ * Using I2C_CheckEvent() function:
+ * It compares the status registers (STS1 and STS2) content to a given event
+ * (can be the combination of one or more flags).
+ * It returns SUCCESS if the current status includes the given flags
+ * and returns ERROR if one or more flags are missing in the current status.
+ * - When to use:
+ * - This function is suitable for most applications as well as for startup
+ * activity since the events are fully described in the product reference manual
+ * (RM0008).
+ * - It is also suitable for users who need to define their own events.
+ * - Limitations:
+ * - If an error occurs (ie. error flags are set besides to the monitored flags),
+ * the I2C_CheckEvent() function may return SUCCESS despite the communication
+ * hold or corrupted real state.
+ * In this case, it is advised to use error interrupts to monitor the error
+ * events and handle them in the interrupt IRQ handler.
+ *
+ * @note
+ * For error management, it is advised to use the following functions:
+ * - I2C_ConfigInt() to configure and enable the error interrupts (I2C_INT_ERR).
+ * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
+ * Where x is the peripheral instance (I2C1, I2C2 ...)
+ * - I2C_GetFlag() or I2C_GetIntStatus() to be called into I2Cx_ER_IRQHandler()
+ * in order to determine which error occured.
+ * - I2C_ClrFlag() or I2C_ClrIntPendingBit() and/or I2C_EnableSoftwareReset()
+ * and/or I2C_GenerateStop() in order to clear the error flag and source,
+ * and return to correct communication status.
+ *
+ *
+ * 2) Advanced state monitoring:
+ * Using the function I2C_GetLastEvent() which returns the image of both status
+ * registers in a single word (uint32_t) (Status Register 2 value is shifted left
+ * by 16 bits and concatenated to Status Register 1).
+ * - When to use:
+ * - This function is suitable for the same applications above but it allows to
+ * overcome the mentioned limitation of I2C_GetFlag() function.
+ * The returned value could be compared to events already defined in the
+ * library (n32l40x_i2c.h) or to custom values defined by user.
+ * - This function is suitable when multiple flags are monitored at the same time.
+ * - At the opposite of I2C_CheckEvent() function, this function allows user to
+ * choose when an event is accepted (when all events flags are set and no
+ * other flags are set or just when the needed flags are set like
+ * I2C_CheckEvent() function).
+ * - Limitations:
+ * - User may need to define his own events.
+ * - Same remark concerning the error management is applicable for this
+ * function if user decides to check only regular communication flags (and
+ * ignores error flags).
+ *
+ *
+ * 3) Flag-based state monitoring:
+ * Using the function I2C_GetFlag() which simply returns the status of
+ * one single flag (ie. I2C_FLAG_RXDATNE ...).
+ * - When to use:
+ * - This function could be used for specific applications or in debug phase.
+ * - It is suitable when only one flag checking is needed (most I2C events
+ * are monitored through multiple flags).
+ * - Limitations:
+ * - When calling this function, the Status register is accessed. Some flags are
+ * cleared when the status register is accessed. So checking the status
+ * of one Flag, may clear other ones.
+ * - Function may need to be called twice or more in order to monitor one
+ * single event.
+ *
+ * For detailed description of Events, please refer to section I2C_Events in
+ * n32l40x_i2c.h file.
+ *
+ */
+
+/**
+ * @brief Checks whether the last I2Cx Event is equal to the one passed
+ * as parameter.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_EVENT specifies the event to be checked.
+ * This parameter can be one of the following values:
+ * @arg I2C_EVT_SLAVE_SEND_ADDR_MATCHED EV1
+ * @arg I2C_EVT_SLAVE_RECV_ADDR_MATCHED EV1
+ * @arg I2C_EVT_SLAVE_SEND_ADDR2_MATCHED EV1
+ * @arg I2C_EVT_SLAVE_RECV_ADDR2_MATCHED EV1
+ * @arg I2C_EVT_SLAVE_GCALLADDR_MATCHED EV1
+ * @arg I2C_EVT_SLAVE_DATA_RECVD EV2
+ * @arg (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_DUALFLAG) EV2
+ * @arg (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_GCALLADDR) EV2
+ * @arg I2C_EVT_SLAVE_DATA_SENDED EV3
+ * @arg (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_DUALFLAG) EV3
+ * @arg (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_GCALLADDR) EV3
+ * @arg I2C_EVT_SLAVE_ACK_MISS EV3_2
+ * @arg I2C_EVT_SLAVE_STOP_RECVD EV4
+ * @arg I2C_EVT_MASTER_MODE_FLAG EV5
+ * @arg I2C_EVT_MASTER_TXMODE_FLAG EV6
+ * @arg I2C_EVT_MASTER_RXMODE_FLAG EV6
+ * @arg I2C_EVT_MASTER_DATA_RECVD_FLAG EV7
+ * @arg I2C_EVT_MASTER_DATA_SENDING EV8
+ * @arg I2C_EVT_MASTER_DATA_SENDED EV8_2
+ * @arg I2C_EVT_MASTER_MODE_ADDRESS10_FLAG EV9
+ *
+ * @note: For detailed description of Events, please refer to section
+ * I2C_Events in n32l40x_i2c.h file.
+ *
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: Last event is equal to the I2C_EVENT
+ * - ERROR: Last event is different from the I2C_EVENT
+ */
+ErrorStatus I2C_CheckEvent(I2C_Module* I2Cx, uint32_t I2C_EVENT)
+{
+ uint32_t lastevent = 0;
+ uint32_t flag1 = 0, flag2 = 0;
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_EVT(I2C_EVENT));
+
+ /* Read the I2Cx status register */
+ flag1 = I2Cx->STS1;
+ flag2 = I2Cx->STS2;
+ flag2 = flag2 << 16;
+
+ /* Get the last event value from I2C status register */
+ lastevent = (flag1 | flag2) & FLAG_MASK;
+
+ /* Check whether the last event contains the I2C_EVENT */
+ if ((lastevent & I2C_EVENT) == I2C_EVENT)
+ {
+ /* SUCCESS: last event is equal to I2C_EVENT */
+ status = SUCCESS;
+ }
+ else
+ {
+ /* ERROR: last event is different from I2C_EVENT */
+ status = ERROR;
+ }
+ /* Return status */
+ return status;
+}
+
+/**
+ * @brief Returns the last I2Cx Event.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ *
+ * @note: For detailed description of Events, please refer to section
+ * I2C_Events in n32l40x_i2c.h file.
+ *
+ * @return The last event
+ */
+uint32_t I2C_GetLastEvent(I2C_Module* I2Cx)
+{
+ uint32_t lastevent = 0;
+ uint32_t flag1 = 0, flag2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+
+ /* Read the I2Cx status register */
+ flag1 = I2Cx->STS1;
+ flag2 = I2Cx->STS2;
+ flag2 = flag2 << 16;
+
+ /* Get the last event value from I2C status register */
+ lastevent = (flag1 | flag2) & FLAG_MASK;
+
+ /* Return status */
+ return lastevent;
+}
+
+/**
+ * @brief Checks whether the specified I2C flag is set or not.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_FLAG specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg I2C_FLAG_DUALFLAG Dual flag (Slave mode)
+ * @arg I2C_FLAG_SMBHADDR SMBus host header (Slave mode)
+ * @arg I2C_FLAG_SMBDADDR SMBus default header (Slave mode)
+ * @arg I2C_FLAG_GCALLADDR General call header flag (Slave mode)
+ * @arg I2C_FLAG_TRF Transmitter/Receiver flag
+ * @arg I2C_FLAG_BUSY Bus busy flag
+ * @arg I2C_FLAG_MSMODE Master/Slave flag
+ * @arg I2C_FLAG_SMBALERT SMBus Alert flag
+ * @arg I2C_FLAG_TIMOUT Timeout or Tlow error flag
+ * @arg I2C_FLAG_PECERR PEC error in reception flag
+ * @arg I2C_FLAG_OVERRUN Overrun/Underrun flag (Slave mode)
+ * @arg I2C_FLAG_ACKFAIL Acknowledge failure flag
+ * @arg I2C_FLAG_ARLOST Arbitration lost flag (Master mode)
+ * @arg I2C_FLAG_BUSERR Bus error flag
+ * @arg I2C_FLAG_TXDATE Data register empty flag (Transmitter)
+ * @arg I2C_FLAG_RXDATNE Data register not empty (Receiver) flag
+ * @arg I2C_FLAG_STOPF Stop detection flag (Slave mode)
+ * @arg I2C_FLAG_ADDR10F 10-bit header sent flag (Master mode)
+ * @arg I2C_FLAG_BYTEF Byte transfer finished flag
+ * @arg I2C_FLAG_ADDRF Address sent flag (Master mode) "ADSL"
+ * Address matched flag (Slave mode)"ENDA"
+ * @arg I2C_FLAG_STARTBF Start bit flag (Master mode)
+ * @return The new state of I2C_FLAG (SET or RESET).
+ */
+FlagStatus I2C_GetFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ __IO uint32_t i2creg = 0, i2cxbase = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
+
+ /* Get the I2Cx peripheral base address */
+ i2cxbase = (uint32_t)I2Cx;
+
+ /* Read flag register index */
+ i2creg = I2C_FLAG >> 28;
+
+ /* Get bit[23:0] of the flag */
+ I2C_FLAG &= FLAG_MASK;
+
+ if (i2creg != 0)
+ {
+ /* Get the I2Cx STS1 register address */
+ i2cxbase += 0x14;
+ }
+ else
+ {
+ /* Flag in I2Cx STS2 Register */
+ I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
+ /* Get the I2Cx STS2 register address */
+ i2cxbase += 0x18;
+ }
+
+ if (((*(__IO uint32_t*)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
+ {
+ /* I2C_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* I2C_FLAG is reset */
+ bitstatus = RESET;
+ }
+
+ /* Return the I2C_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the I2Cx's pending flags.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_FLAG specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_FLAG_SMBALERT SMBus Alert flag
+ * @arg I2C_FLAG_TIMOUT Timeout or Tlow error flag
+ * @arg I2C_FLAG_PECERR PEC error in reception flag
+ * @arg I2C_FLAG_OVERRUN Overrun/Underrun flag (Slave mode)
+ * @arg I2C_FLAG_ACKFAIL Acknowledge failure flag
+ * @arg I2C_FLAG_ARLOST Arbitration lost flag (Master mode)
+ * @arg I2C_FLAG_BUSERR Bus error flag
+ *
+ * @note
+ * - STOPF (STOP detection) is cleared by software sequence: a read operation
+ * to I2C_STS1 register (I2C_GetFlag()) followed by a write operation
+ * to I2C_CTRL1 register (I2C_Enable() to re-enable the I2C peripheral).
+ * - ADD10 (10-bit header sent) is cleared by software sequence: a read
+ * operation to I2C_STS1 (I2C_GetFlag()) followed by writing the
+ * second byte of the address in DAT register.
+ * - BTF (Byte Transfer Finished) is cleared by software sequence: a read
+ * operation to I2C_STS1 register (I2C_GetFlag()) followed by a
+ * read/write to I2C_DAT register (I2C_SendData()).
+ * - ADDR (Address sent) is cleared by software sequence: a read operation to
+ * I2C_STS1 register (I2C_GetFlag()) followed by a read operation to
+ * I2C_STS2 register ((void)(I2Cx->STS2)).
+ * - SB (Start Bit) is cleared software sequence: a read operation to I2C_STS1
+ * register (I2C_GetFlag()) followed by a write operation to I2C_DAT
+ * register (I2C_SendData()).
+ */
+void I2C_ClrFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG)
+{
+ uint32_t flagpos = 0;
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_CLR_FLAG(I2C_FLAG));
+ /* Get the I2C flag position */
+ flagpos = I2C_FLAG & FLAG_MASK;
+ /* Clear the selected I2C flag */
+ I2Cx->STS1 = (uint16_t)~flagpos;
+}
+
+/**
+ * @brief Checks whether the specified I2C interrupt has occurred or not.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT specifies the interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg I2C_INT_SMBALERT SMBus Alert flag
+ * @arg I2C_INT_TIMOUT Timeout or Tlow error flag
+ * @arg I2C_INT_PECERR PEC error in reception flag
+ * @arg I2C_INT_OVERRUN Overrun/Underrun flag (Slave mode)
+ * @arg I2C_INT_ACKFAIL Acknowledge failure flag
+ * @arg I2C_INT_ARLOST Arbitration lost flag (Master mode)
+ * @arg I2C_INT_BUSERR Bus error flag
+ * @arg I2C_INT_TXDATE Data register empty flag (Transmitter)
+ * @arg I2C_INT_RXDATNE Data register not empty (Receiver) flag
+ * @arg I2C_INT_STOPF Stop detection flag (Slave mode)
+ * @arg I2C_INT_ADDR10F 10-bit header sent flag (Master mode)
+ * @arg I2C_INT_BYTEF Byte transfer finished flag
+ * @arg I2C_INT_ADDRF Address sent flag (Master mode) "ADSL"
+ * Address matched flag (Slave mode)"ENDAD"
+ * @arg I2C_INT_STARTBF Start bit flag (Master mode)
+ * @return The new state of I2C_IT (SET or RESET).
+ */
+INTStatus I2C_GetIntStatus(I2C_Module* I2Cx, uint32_t I2C_IT)
+{
+ INTStatus bitstatus = RESET;
+ uint32_t enablestatus = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_GET_INT(I2C_IT));
+
+ /* Check if the interrupt source is enabled or not */
+ enablestatus = (uint32_t)(((I2C_IT & INTEN_MASK) >> 16) & (I2Cx->CTRL2));
+
+ /* Get bit[23:0] of the flag */
+ I2C_IT &= FLAG_MASK;
+
+ /* Check the status of the specified I2C flag */
+ if (((I2Cx->STS1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
+ {
+ /* I2C_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* I2C_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the I2C_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the I2Cx's interrupt pending bits.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_INT_SMBALERT SMBus Alert interrupt
+ * @arg I2C_INT_TIMOUT Timeout or Tlow error interrupt
+ * @arg I2C_INT_PECERR PEC error in reception interrupt
+ * @arg I2C_INT_OVERRUN Overrun/Underrun interrupt (Slave mode)
+ * @arg I2C_INT_ACKFAIL Acknowledge failure interrupt
+ * @arg I2C_INT_ARLOST Arbitration lost interrupt (Master mode)
+ * @arg I2C_INT_BUSERR Bus error interrupt
+ *
+ * @note
+ * - STOPF (STOP detection) is cleared by software sequence: a read operation
+ * to I2C_STS1 register (I2C_GetIntStatus()) followed by a write operation to
+ * I2C_CTRL1 register (I2C_Enable() to re-enable the I2C peripheral).
+ * - ADD10 (10-bit header sent) is cleared by software sequence: a read
+ * operation to I2C_STS1 (I2C_GetIntStatus()) followed by writing the second
+ * byte of the address in I2C_DAT register.
+ * - BTF (Byte Transfer Finished) is cleared by software sequence: a read
+ * operation to I2C_STS1 register (I2C_GetIntStatus()) followed by a
+ * read/write to I2C_DAT register (I2C_SendData()).
+ * - ADDR (Address sent) is cleared by software sequence: a read operation to
+ * I2C_STS1 register (I2C_GetIntStatus()) followed by a read operation to
+ * I2C_STS2 register ((void)(I2Cx->STS2)).
+ * - SB (Start Bit) is cleared by software sequence: a read operation to
+ * I2C_STS1 register (I2C_GetIntStatus()) followed by a write operation to
+ * I2C_DAT register (I2C_SendData()).
+ */
+void I2C_ClrIntPendingBit(I2C_Module* I2Cx, uint32_t I2C_IT)
+{
+ uint32_t flagpos = 0;
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_CLR_INT(I2C_IT));
+ /* Get the I2C flag position */
+ flagpos = I2C_IT & FLAG_MASK;
+ /* Clear the selected I2C flag */
+ I2Cx->STS1 = (uint16_t)~flagpos;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_iwdg.c b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_iwdg.c
new file mode 100644
index 0000000000..9c3c91d4e5
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_iwdg.c
@@ -0,0 +1,193 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_iwdg.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l40x_iwdg.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup IWDG
+ * @brief IWDG driver modules
+ * @{
+ */
+
+/** @addtogroup IWDG_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Private_Defines
+ * @{
+ */
+
+/* ---------------------- IWDG registers bit mask ----------------------------*/
+
+/* KEY register bit mask */
+#define KEY_ReloadKey ((uint16_t)0xAAAA)
+#define KEY_EnableKey ((uint16_t)0xCCCC)
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
+ * @param IWDG_WriteAccess new state of write access to IWDG_PR and IWDG_RLR registers.
+ * This parameter can be one of the following values:
+ * @arg IWDG_WRITE_ENABLE Enable write access to IWDG_PR and IWDG_RLR registers
+ * @arg IWDG_WRITE_DISABLE Disable write access to IWDG_PR and IWDG_RLR registers
+ */
+void IWDG_WriteConfig(uint16_t IWDG_WriteAccess)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_WRITE(IWDG_WriteAccess));
+ IWDG->KEY = IWDG_WriteAccess;
+}
+
+/**
+ * @brief Sets IWDG Prescaler value.
+ * @param IWDG_Prescaler specifies the IWDG Prescaler value.
+ * This parameter can be one of the following values:
+ * @arg IWDG_PRESCALER_DIV4 IWDG prescaler set to 4
+ * @arg IWDG_PRESCALER_DIV8 IWDG prescaler set to 8
+ * @arg IWDG_PRESCALER_DIV16 IWDG prescaler set to 16
+ * @arg IWDG_PRESCALER_DIV32 IWDG prescaler set to 32
+ * @arg IWDG_PRESCALER_DIV64 IWDG prescaler set to 64
+ * @arg IWDG_PRESCALER_DIV128 IWDG prescaler set to 128
+ * @arg IWDG_PRESCALER_DIV256 IWDG prescaler set to 256
+ */
+void IWDG_SetPrescalerDiv(uint8_t IWDG_Prescaler)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_PRESCALER_DIV(IWDG_Prescaler));
+ IWDG->PREDIV = IWDG_Prescaler;
+}
+
+/**
+ * @brief Sets IWDG Reload value.
+ * @param Reload specifies the IWDG Reload value.
+ * This parameter must be a number between 0 and 0x0FFF.
+ */
+void IWDG_CntReload(uint16_t Reload)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_RELOAD(Reload));
+ IWDG->RELV = Reload;
+}
+
+/**
+ * @brief Reloads IWDG counter with value defined in the reload register
+ * (write access to IWDG_PR and IWDG_RLR registers disabled).
+ */
+void IWDG_ReloadKey(void)
+{
+ IWDG->KEY = KEY_ReloadKey;
+}
+
+/**
+ * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
+ */
+void IWDG_Enable(void)
+{
+ IWDG->KEY = KEY_EnableKey;
+}
+
+/**
+ * @brief Checks whether the specified IWDG flag is set or not.
+ * @param IWDG_FLAG specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg IWDG_PVU_FLAG Prescaler Value Update on going
+ * @arg IWDG_CRVU_FLAG Reload Value Update on going
+ * @return The new state of IWDG_FLAG (SET or RESET).
+ */
+FlagStatus IWDG_GetStatus(uint16_t IWDG_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_IWDG_FLAG(IWDG_FLAG));
+ if ((IWDG->STS & IWDG_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_lcd.c b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_lcd.c
new file mode 100644
index 0000000000..c5e0972938
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_lcd.c
@@ -0,0 +1,406 @@
+/*****************************************************************************
+* Copyright (c) 2022, Nations Technologies Inc.
+*
+* All rights reserved.
+* ****************************************************************************
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* - Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the disclaimer below.
+*
+* Nations' name may not be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ****************************************************************************/
+
+/**
+ * @file n32l40x_lcd.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+
+#include "n32l40x_lcd.h"
+
+/** @addtogroup N32L40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup LCD
+ * @brief LCD driver modules
+ * @{
+ */
+
+/** @addtogroup LCD_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup LCD_Private_Defines
+ * @{
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @brief Initialize the LCD peripheral according to the specified parameters
+ * in the LCD_InitStruct.
+ * @param LCD_InitStructure LCD initialize structure parameters
+ * @retval LCD error code
+ */
+LCD_ErrorTypeDef LCD_Init(LCD_InitType *LCD_InitStructure )
+{
+ uint32_t tmp, timeout;
+
+ /* Check function parameters */
+ assert_param(IS_LCD_BIAS(LCD_InitStructure->Bias));
+ assert_param(IS_LCD_BLINKFREQ(LCD_InitStructure->BlinkFreq));
+ assert_param(IS_LCD_BLINKMODE(LCD_InitStructure->BlinkMode));
+ assert_param(IS_LCD_CONTRASTLEVEL(LCD_InitStructure->Contrast));
+ assert_param(IS_LCD_DEADTIME(LCD_InitStructure->DeadTime));
+ assert_param(IS_LCD_DIVIDER(LCD_InitStructure->Divider));
+ assert_param(IS_LCD_DUTY(LCD_InitStructure->Duty));
+ assert_param(IS_LCD_HIGHDRIVE(LCD_InitStructure->HighDrive));
+ assert_param(IS_LCD_HIGHDRIVEBUFFER(LCD_InitStructure->HighDriveBuffer));
+ assert_param(IS_LCD_MUXSEGMENT(LCD_InitStructure->MuxSegment));
+ assert_param(IS_LCD_PRESCALER(LCD_InitStructure->Prescaler));
+ assert_param(IS_LCD_PULSEONDURATION(LCD_InitStructure->PulseOnDuration));
+ assert_param(IS_LCD_VOLTAGESOURCE(LCD_InitStructure->VoltageSource));
+
+ /*Disable LCD controller*/
+ __LCD_DISABLE();
+
+ /*During 1/8 duty mode, 1/4 bias is not supported,use 1/3 bias instead*/
+ if (LCD_DUTY_1_8 == LCD_InitStructure->Duty)
+ {
+ if (LCD_BIAS_1_4 == LCD_InitStructure->Bias)
+ LCD_InitStructure->Bias = LCD_BIAS_1_3;
+ }
+
+ /* set the bits of LCD_CTRL register with corresonding parameters */
+ tmp = 0;
+ tmp |= LCD_InitStructure->HighDriveBuffer;
+ tmp |= LCD_InitStructure->MuxSegment;
+ tmp |= LCD_InitStructure->Bias;
+ tmp |= LCD_InitStructure->Duty;
+ tmp |= LCD_InitStructure->VoltageSource;
+ LCD->CTRL = tmp;
+
+ /*If High driver enable, PulseOnDuration must be LCD_PulseOnDuration_1*/
+ if (LCD_InitStructure->HighDrive == LCD_HIGHDRIVE_ENABLE)
+ {
+ LCD_InitStructure->PulseOnDuration = LCD_PULSEONDURATION_1;
+ }
+
+ /* set the bits of LCD_FCTRL register with corresonding parameters */
+ tmp = 0;
+ tmp |= LCD_InitStructure->Prescaler;
+ tmp |= LCD_InitStructure->Divider;
+ tmp |= LCD_InitStructure->BlinkMode;
+ tmp |= LCD_InitStructure->BlinkFreq;
+ tmp |= LCD_InitStructure->Contrast;
+ tmp |= LCD_InitStructure->DeadTime;
+ tmp |= LCD_InitStructure->HighDrive;
+ tmp |= LCD_InitStructure->PulseOnDuration;
+ LCD->FCTRL = tmp;
+
+ /*Clear LCD display ram, and set the update request flag*/
+ LCD_RamClear();
+ __LCD_UPDATE_REQUEST();
+
+ /*Enable LCD controller*/
+ __LCD_ENABLE();
+
+ /*Check the LCD ENSTS status*/
+ timeout = 0;
+ while (RESET == (__LCD_GET_FLAG(LCD_FLAG_ENSTS)))
+ {
+ if (++timeout >= LCD_TIME_OUT)
+ return LCD_ERROR_ENSTS;
+ }
+
+ /*Wait VLCD stable*/
+ timeout = 0;
+ while (RESET == (__LCD_GET_FLAG(LCD_FLAG_RDY)))
+ {
+ if (++timeout >= LCD_TIME_OUT)
+ return LCD_ERROR_RDY;
+ }
+
+ return (LCD_WaitForSynchro());
+}
+
+/**
+ * @brief DeInitialize the LCD peripheral
+ * @param None
+ * @retval None
+ */
+void LCD_DeInit(void)
+{
+ RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LCD,ENABLE);
+ RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LCD,DISABLE);
+}
+
+/**
+ * @brief Config the clock source of LCD
+ * @param LCD_ClkSource specifies the clock source of LCD
+ * This parameter can be one of the following values:
+ * @arg LCD_CLK_SRC_LSI: LCD clock source is LSI
+ * @arg LCD_CLK_SRC_LSE: LCD clock source is LSE,and LSE is oscillator
+ * @arg LCD_CLK_SRC_LSE_BYPASS: LCD clock source is LSE,and LSE is extennal clock
+ * @arg LCD_CLK_SRC_HSE_DIV32: LCD clock source is HSE/32,and HSE is oscillator
+ * @arg LCD_CLK_SRC_HSE_BYPASS_DIV32: LCD clock source is HSE/32,and HSE is extennal clock
+ * @retval LCD error code
+ * note: LCD clock is the same with RTC
+ */
+LCD_ErrorTypeDef LCD_ClockConfig(uint32_t LCD_ClkSource)
+{
+ uint32_t timeout;
+
+ /*Enable PWR peripheral Clock*/
+ RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR,ENABLE);
+
+ if (LCD_CLK_SRC_LSI == LCD_ClkSource)
+ {
+ /*enable LSI clock*/
+ RCC_EnableLsi(ENABLE);
+
+ /*Wait LSI stable*/
+ timeout = 0;
+ while (RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_LSIRD) == RESET)
+ {
+ if (++timeout >LCD_TIME_OUT)
+ return LCD_ERROR_CLK;
+ }
+ }
+ else if ((LCD_CLK_SRC_LSE==LCD_ClkSource)||(LCD_CLK_SRC_LSE_BYPASS==LCD_ClkSource))
+ {
+ if (RCC_GetFlagStatus(RCC_LDCTRL_FLAG_LSERD)==RESET)
+ {
+ RCC_ConfigLse((LCD_ClkSource & (~RCC_LDCTRL_RTCSEL)),0x28);
+ timeout = 0;
+ while (RCC_GetFlagStatus(RCC_LDCTRL_FLAG_LSERD) == RESET)
+ {
+ if (++timeout >LCD_TIME_OUT)
+ return LCD_ERROR_CLK;
+ }
+ }
+ }
+ else if ((LCD_CLK_SRC_HSE_DIV32==LCD_ClkSource)||(LCD_CLK_SRC_HSE_BYPASS_DIV32==LCD_ClkSource))
+ {
+ if (RCC_GetFlagStatus(RCC_CTRL_FLAG_HSERDF)==RESET)
+ {
+ RCC_ConfigHse(LCD_ClkSource & (~RCC_LDCTRL_RTCSEL));
+ if (RCC_WaitHseStable()!=SUCCESS)
+ return LCD_ERROR_CLK;
+ }
+ }
+ else
+ return LCD_ERROR_PARAM;
+
+ // Set bit 8 of PWR_CTRL1.Open PWR DBP.
+ PWR_BackupAccessEnable(ENABLE); //PWR->CTRL1 |= 0x100;
+
+ /*set LSI as RTC clock source*/
+ RCC_ConfigRtcClk(LCD_ClkSource & RCC_LDCTRL_RTCSEL);
+
+ /*Enable RTC clk*/
+ RCC_EnableRtcClk(ENABLE);
+
+ /*Enable LCD clk*/
+ RCC_EnableRETPeriphClk(RCC_RET_PERIPH_LCD,ENABLE);
+
+ return LCD_ERROR_OK;
+}
+
+/**
+ * @brief Clear LCD ram register.
+ * @param None
+ * @retval None
+ */
+void LCD_RamClear(void)
+{
+ uint32_t counter;
+
+ /*Clear lcd ram*/
+ for(counter = LCD_RAM1_COM0; counter <= LCD_RAM2_COM7; counter++)
+ {
+ LCD->RAM_COM[counter] = 0x0U;
+ }
+}
+
+/**
+ * @brief Update Display request.
+ * @param None
+ * @retval LCD error code
+ */
+LCD_ErrorTypeDef LCD_UpdateDisplayRequest(void)
+{
+ uint32_t timeout;
+
+ /*Clear UDD flag*/
+ __LCD_CLEAR_FLAG(LCD_FLAG_UDD_CLEAR);
+
+ /* set update display request bit*/
+ __LCD_UPDATE_REQUEST();
+
+ /* Wait update complete */
+ timeout = 0;
+ while (RESET == (__LCD_GET_FLAG(LCD_FLAG_UDD)))
+ {
+ if (++timeout >= LCD_TIME_OUT)
+ return LCD_ERROR_UDD;
+ }
+
+ return LCD_ERROR_OK;
+}
+
+/**
+ * @brief write to the lcd ram register.
+ * @param RAMRegisterIndex RAM register index,
+ * this parameter can be LCD_RAM_COMx_y where x can be (0..7) and y can be (1..2).
+ * @param RAMRegisterMask specifies the LCD RAM Register Data Mask.
+ * @param RAMData value written to RAM.
+ * @retval LCD error code
+ */
+LCD_ErrorTypeDef LCD_Write(uint32_t RAMRegisterIndex,uint32_t RAMRegisterMask,uint32_t RAMData)
+{
+ uint32_t timeout;
+
+ /* Check function parameters */
+ assert_param(IS_LCD_RAM_REGISTER_INDEX(RAMRegisterIndex));
+
+ if (RAMRegisterIndex > LCD_RAM2_COM7)
+ return LCD_ERROR_PARAM;
+
+ /* Wait VLCD request flag clear */
+ timeout = 0;
+ while (__LCD_GET_FLAG(LCD_FLAG_UDR))
+ {
+ if (++timeout >= LCD_TIME_OUT)
+ {
+ return LCD_ERROR_UDR;
+ }
+ }
+
+ /* Write lcd RAMData */
+ MODIFY_REG(LCD->RAM_COM[RAMRegisterIndex], ~(RAMRegisterMask), RAMData &(~(RAMRegisterMask)));
+
+ return LCD_ERROR_OK;
+
+}
+
+/**
+ * @brief set some bits of lcd ram register.
+ * @param RAMRegisterIndex: RAM register index,
+ * this parameter can be LCD_RAM_COMx_y where x can be (0..7) and y can be (1..2).
+ * @param RAMData: value to be set
+ * @retval LCD error code
+ */
+LCD_ErrorTypeDef LCD_SetBit(uint32_t RAMRegisterIndex,uint32_t RAMData)
+{
+ uint32_t timeout;
+ /* Check function parameters */
+ assert_param(IS_LCD_RAM_REGISTER_INDEX(RAMRegisterIndex));
+
+ if (RAMRegisterIndex > LCD_RAM2_COM7)
+ return LCD_ERROR_PARAM;
+
+ /* Wait VLCD request flag clear */
+ timeout = 0;
+ while (__LCD_GET_FLAG(LCD_FLAG_UDR))
+ {
+ if (++timeout >= LCD_TIME_OUT)
+ {
+ return LCD_ERROR_UDR;
+ }
+ }
+
+ /* Write lcd RAMData */
+ SET_BIT(LCD->RAM_COM[RAMRegisterIndex], RAMData);
+ return LCD_ERROR_OK;
+}
+
+/**
+ * @brief clear some bits of lcd ram register.
+ * @param RAMRegisterIndex: RAM register index,
+ * this parameter can be LCD_RAM_COMx_y where x can be (0..7) and y can be (1..2).
+ * @param RAMData: value to be clear
+ * @retval LCD error code
+ */
+LCD_ErrorTypeDef LCD_ClearBit(uint32_t RAMRegisterIndex,uint32_t RAMData)
+{
+ uint32_t timeout;
+ /* Check function parameters */
+ assert_param(IS_LCD_RAM_REGISTER_INDEX(RAMRegisterIndex));
+
+ if (RAMRegisterIndex > LCD_RAM2_COM7)
+ return LCD_ERROR_PARAM;
+
+ /* Wait VLCD request flag clear */
+ timeout = 0;
+ while (__LCD_GET_FLAG(LCD_FLAG_UDR))
+ {
+ if (++timeout >= LCD_TIME_OUT)
+ {
+ return LCD_ERROR_UDR;
+ }
+ }
+
+ /* Write lcd RAMData */
+ CLEAR_BIT(LCD->RAM_COM[RAMRegisterIndex], RAMData);
+ return LCD_ERROR_OK;
+}
+
+
+/**
+ * @brief Wait until the LCD FCTRL register is synchronized in the LCDCLK domain.
+ * This function must be called after any write operation to LCD_FCTRL register.
+ * @param RAMData: None
+ * @retval LCD error code
+ */
+LCD_ErrorTypeDef LCD_WaitForSynchro(void)
+{
+ uint32_t timeout;
+
+ /* Loop until FCRSF flag is set */
+ timeout = 0;
+ while (RESET == (__LCD_GET_FLAG(LCD_FLAG_FCRSF)))
+ {
+ if (++timeout >= LCD_TIME_OUT)
+ {
+ return LCD_ERROR_FCRSF;
+ }
+ }
+
+ return LCD_ERROR_OK;
+}
+
+/**
+* @}
+*/
+/**
+* @}
+*/
+
+
+
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_lptim.c b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_lptim.c
new file mode 100644
index 0000000000..434bbf89c5
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_lptim.c
@@ -0,0 +1,1258 @@
+/** ----------------------------------------------------------------------------
+ * Nationz Technology Software Support - NATIONZ -
+ * -----------------------------------------------------------------------------
+ * Copyright (c) 2022, Nationz Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaiimer below.
+ *
+ * - Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the disclaimer below in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * Nationz's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+ * -----------------------------------------------------------------------------
+ */
+
+/** ****************************************************************************
+ * @copyright Nationz Co.,Ltd
+ * Copyright (c) 2019 All Rights Reserved
+ *******************************************************************************
+ * @file n32l40x_lptim.c
+ * @author
+ * @date
+ * @version v1.2.0
+ * @brief
+ ******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "n32l40x_lptim.h"
+#include "n32l40x_rcc.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup LPTIM
+ * @brief LPTIM driver modules
+ * @{
+ */
+
+/** @defgroup LPTIM_Private_TypesDefinitions
+ * @{
+ */
+/**
+ * @}
+ */
+//#define LPTIM
+//#if defined (LPTIM)//LPTIM
+
+/** @defgroup RCC_EC_LPTIM1 Peripheral LPTIM get clock source
+ * @{
+ */
+#define RCC_LPTIM_CLKSOURCE ((uint32_t)0x00000007)/*!< LPTIM1 clock source selection bits */
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup LPTIM_Private_Macros
+ * @{
+ */
+#define IS_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LPTIM_CLK_SOURCE_INTERNAL) \
+ || ((__VALUE__) == LPTIM_CLK_SOURCE_EXTERNAL))
+
+#define IS_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LPTIM_PRESCALER_DIV1) \
+ || ((__VALUE__) == LPTIM_PRESCALER_DIV2) \
+ || ((__VALUE__) == LPTIM_PRESCALER_DIV4) \
+ || ((__VALUE__) == LPTIM_PRESCALER_DIV8) \
+ || ((__VALUE__) == LPTIM_PRESCALER_DIV16) \
+ || ((__VALUE__) == LPTIM_PRESCALER_DIV32) \
+ || ((__VALUE__) == LPTIM_PRESCALER_DIV64) \
+ || ((__VALUE__) == LPTIM_PRESCALER_DIV128))
+
+#define IS_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LPTIM_OUTPUT_WAVEFORM_PWM) \
+ || ((__VALUE__) == LPTIM_OUTPUT_WAVEFORM_SETONCE))
+
+#define IS_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LPTIM_OUTPUT_POLARITY_REGULAR) \
+ || ((__VALUE__) == LPTIM_OUTPUT_POLARITY_INVERSE))
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
+ * @{
+ */
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup LPTIM_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup LPTIM_EF_Init
+ * @{
+ */
+
+/**
+ * @brief Set LPTIMx registers to their reset values.
+ * @param LPTIMx LP Timer instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: LPTIMx registers are de-initialized
+ * - ERROR: invalid LPTIMx instance
+ */
+void LPTIM_DeInit(LPTIM_Module* LPTIMx)
+{
+ if (LPTIMx == LPTIM)
+ {
+ RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LPTIM,ENABLE);
+ RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LPTIM,DISABLE);
+ }
+}
+
+/**
+ * @brief Set each fields of the LPTIM_InitStruct structure to its default
+ * value.
+ * @param LPTIM_InitStruct pointer to a @ref LPTIM_InitType structure
+ * @retval None
+ */
+void LPTIM_StructInit(LPTIM_InitType* LPTIM_InitStruct)
+{
+ /* Set the default configuration */
+ LPTIM_InitStruct->ClockSource = LPTIM_CLK_SOURCE_INTERNAL;
+ LPTIM_InitStruct->Prescaler = LPTIM_PRESCALER_DIV1;
+ LPTIM_InitStruct->Waveform = LPTIM_OUTPUT_WAVEFORM_PWM;
+ LPTIM_InitStruct->Polarity = LPTIM_OUTPUT_POLARITY_REGULAR;
+}
+
+/**
+ * @brief Configure the LPTIMx peripheral according to the specified parameters.
+ * @note LPTIM_Init can only be called when the LPTIM instance is disabled.
+ * @note LPTIMx can be disabled using unitary function @ref LPTIM_Disable().
+ * @param LPTIMx LP Timer Instance
+ * @param LPTIM_InitStruct pointer to a @ref LPTIM_InitType structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: LPTIMx instance has been initialized
+ * - ERROR: LPTIMx instance hasn't been initialized
+ */
+ErrorStatus LPTIM_Init(LPTIM_Module * LPTIMx, LPTIM_InitType* LPTIM_InitStruct)
+{
+ ErrorStatus result = SUCCESS;
+ /* Check the parameters */
+ assert_param(IS_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource));
+ assert_param(IS_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler));
+ assert_param(IS_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform));
+ assert_param(IS_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity));
+
+ /* The LPTIMx_CFG register must only be modified when the LPTIM is disabled
+ (ENABLE bit is reset to 0).
+ */
+ if (LPTIM_IsEnabled(LPTIMx) == 1UL)
+ {
+ result = ERROR;
+ }
+ else
+ {
+ /* Set CKSEL bitfield according to ClockSource value */
+ /* Set PRESC bitfield according to Prescaler value */
+ /* Set WAVE bitfield according to Waveform value */
+ /* Set WAVEPOL bitfield according to Polarity value */
+ MODIFY_REG(LPTIMx->CFG,
+ (LPTIM_CFG_CLKSEL | LPTIM_CFG_CLKPOL | LPTIM_CFG_WAVE| LPTIM_CFG_WAVEPOL),
+ LPTIM_InitStruct->ClockSource | \
+ LPTIM_InitStruct->Prescaler | \
+ LPTIM_InitStruct->Waveform | \
+ LPTIM_InitStruct->Polarity);
+ }
+
+ return result;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @brief Disable the LPTIM instance
+ * @rmtoll CR ENABLE LPTIM_Disable
+ * @param LPTIMx Low-Power Timer instance
+ * @note
+ * @retval None
+ */
+void LPTIM_Disable(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->CTRL, LPTIM_CTRL_LPTIMEN);
+}
+
+/** @defgroup LPTIM_EF_LPTIM_Configuration LPTIM Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable the LPTIM instance
+ * @note After setting the ENABLE bit, a delay of two counter clock is needed
+ * before the LPTIM instance is actually enabled.
+ * @rmtoll CR ENABLE LPTIM_Enable
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_Enable(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->CTRL, LPTIM_CTRL_LPTIMEN);
+}
+
+/**
+ * @brief Indicates whether the LPTIM instance is enabled.
+ * @rmtoll CR ENABLE LPTIM_IsEnabled
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsEnabled(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->CTRL, LPTIM_CTRL_LPTIMEN) == LPTIM_CTRL_LPTIMEN)? 1UL : 0UL));
+}
+
+/**
+ * @brief Starts the LPTIM counter in the desired mode.
+ * @note LPTIM instance must be enabled before starting the counter.
+ * @note It is possible to change on the fly from One Shot mode to
+ * Continuous mode.
+ * @rmtoll CR CNTSTRT LPTIM_StartCounter\n
+ * CR SNGSTRT LPTIM_StartCounter
+ * @param LPTIMx Low-Power Timer instance
+ * @param OperatingMode This parameter can be one of the following values:
+ * @arg @ref LPTIM_OPERATING_MODE_CONTINUOUS
+ * @arg @ref LPTIM_OPERATING_MODE_ONESHOT
+ * @retval None
+ */
+void LPTIM_StartCounter(LPTIM_Module *LPTIMx, uint32_t OperatingMode)
+{
+ MODIFY_REG(LPTIMx->CTRL, LPTIM_CTRL_TSTCM | LPTIM_CTRL_SNGMST, OperatingMode);
+}
+
+/**
+ * @brief Set the LPTIM registers update mode (enable/disable register preload)
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @rmtoll CFG PRELOAD LPTIM_SetUpdateMode
+ * @param LPTIMx Low-Power Timer instance
+ * @param UpdateMode This parameter can be one of the following values:
+ * @arg @ref LPTIM_UPDATE_MODE_IMMEDIATE
+ * @arg @ref LPTIM_UPDATE_MODE_ENDOFPERIOD
+ * @retval None
+ */
+void LPTIM_SetUpdateMode(LPTIM_Module *LPTIMx, uint32_t UpdateMode)
+{
+ MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_RELOAD, UpdateMode);
+}
+
+/**
+ * @brief Get the LPTIM registers update mode
+ * @rmtoll CFG PRELOAD LPTIM_GetUpdateMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_UPDATE_MODE_IMMEDIATE
+ * @arg @ref LPTIM_UPDATE_MODE_ENDOFPERIOD
+ */
+uint32_t LPTIM_GetUpdateMode(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_RELOAD));
+}
+
+/**
+ * @brief Set the auto reload value
+ * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
+ * @note After a write to the LPTIMx_ARR register a new write operation to the
+ * same register can only be performed when the previous write operation
+ * is completed. Any successive write before the ARROK flag be set, will
+ * lead to unpredictable results.
+ * @note autoreload value be strictly greater than the compare value.
+ * @rmtoll ARR ARR LPTIM_SetAutoReload
+ * @param LPTIMx Low-Power Timer instance
+ * @param AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
+ * @retval None
+ */
+void LPTIM_SetAutoReload(LPTIM_Module *LPTIMx, uint32_t AutoReload)
+{
+ MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARRVAL, AutoReload);
+}
+
+/**
+ * @brief Get actual auto reload value
+ * @rmtoll ARR ARR LPTIM_GetAutoReload
+ * @param LPTIMx Low-Power Timer instance
+ * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+uint32_t LPTIM_GetAutoReload(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARRVAL));
+}
+
+/**
+ * @brief Set the compare value
+ * @note After a write to the LPTIMx_CMP register a new write operation to the
+ * same register can only be performed when the previous write operation
+ * is completed. Any successive write before the CMPOK flag be set, will
+ * lead to unpredictable results.
+ * @rmtoll CMP CMP LPTIM_SetCompare
+ * @param LPTIMx Low-Power Timer instance
+ * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
+ * @retval None
+ */
+void LPTIM_SetCompare(LPTIM_Module *LPTIMx, uint32_t CompareValue)
+{
+ MODIFY_REG(LPTIMx->COMPx, LPTIM_COMP_CMPVAL, CompareValue);
+}
+
+/**
+ * @brief Get actual compare value
+ * @rmtoll CMP CMP LPTIM_GetCompare
+ * @param LPTIMx Low-Power Timer instance
+ * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+uint32_t LPTIM_GetCompare(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->COMPx, LPTIM_COMP_CMPVAL));
+}
+
+/**
+ * @brief Get actual counter value
+ * @note When the LPTIM instance is running with an asynchronous clock, reading
+ * the LPTIMx_CNT register may return unreliable values. So in this case
+ * it is necessary to perform two consecutive read accesses and verify
+ * that the two returned values are identical.
+ * @rmtoll CNT CNT LPTIM_GetCounter
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Counter value
+ */
+uint32_t LPTIM_GetCounter(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNTVAL));
+}
+
+/**
+ * @brief Set the counter mode (selection of the LPTIM counter clock source).
+ * @note The counter mode can be set only when the LPTIM instance is disabled.
+ * @rmtoll CFG COUNTMODE LPTIM_SetCounterMode
+ * @param LPTIMx Low-Power Timer instance
+ * @param CounterMode This parameter can be one of the following values:
+ * @arg @ref LPTIM_COUNTER_MODE_INTERNAL
+ * @arg @ref LPTIM_COUNTER_MODE_EXTERNAL
+ * @retval None
+ */
+void LPTIM_SetCounterMode(LPTIM_Module *LPTIMx, uint32_t CounterMode)
+{
+ MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CNTMEN, CounterMode);
+}
+
+/**
+ * @brief Get the counter mode
+ * @rmtoll CFG COUNTMODE LPTIM_GetCounterMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_COUNTER_MODE_INTERNAL
+ * @arg @ref LPTIM_COUNTER_MODE_EXTERNAL
+ */
+uint32_t LPTIM_GetCounterMode(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CNTMEN));
+}
+
+/**
+ * @brief Configure the LPTIM instance output (LPTIMx_OUT)
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note Regarding the LPTIM output polarity the change takes effect
+ * immediately, so the output default value will change immediately after
+ * the polarity is re-configured, even before the timer is enabled.
+ * @rmtoll CFG WAVE LPTIM_ConfigOutput\n
+ * CFG WAVPOL LPTIM_ConfigOutput
+ * @param LPTIMx Low-Power Timer instance
+ * @param Waveform This parameter can be one of the following values:
+ * @arg @ref LPTIM_OUTPUT_WAVEFORM_PWM
+ * @arg @ref LPTIM_OUTPUT_WAVEFORM_SETONCE
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LPTIM_OUTPUT_POLARITY_REGULAR
+ * @arg @ref LPTIM_OUTPUT_POLARITY_INVERSE
+ * @retval None
+ */
+void LPTIM_ConfigOutput(LPTIM_Module *LPTIMx, uint32_t Waveform, uint32_t Polarity)
+{
+ MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_WAVE | LPTIM_CFG_WAVEPOL, Waveform | Polarity);
+}
+
+/**
+ * @brief Set waveform shape
+ * @rmtoll CFG WAVE LPTIM_SetWaveform
+ * @param LPTIMx Low-Power Timer instance
+ * @param Waveform This parameter can be one of the following values:
+ * @arg @ref LPTIM_OUTPUT_WAVEFORM_PWM
+ * @arg @ref LPTIM_OUTPUT_WAVEFORM_SETONCE
+ * @retval None
+ */
+void LPTIM_SetWaveform(LPTIM_Module *LPTIMx, uint32_t Waveform)
+{
+ MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_WAVE, Waveform);
+}
+
+/**
+ * @brief Get actual waveform shape
+ * @rmtoll CFG WAVE LPTIM_GetWaveform
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_OUTPUT_WAVEFORM_PWM
+ * @arg @ref LPTIM_OUTPUT_WAVEFORM_SETONCE
+ */
+uint32_t LPTIM_GetWaveform(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_WAVE));
+}
+
+/**
+ * @brief Set output polarity
+ * @rmtoll CFG WAVPOL LPTIM_SetPolarity
+ * @param LPTIMx Low-Power Timer instance
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LPTIM_OUTPUT_POLARITY_REGULAR
+ * @arg @ref LPTIM_OUTPUT_POLARITY_INVERSE
+ * @retval None
+ */
+void LPTIM_SetPolarity(LPTIM_Module *LPTIMx, uint32_t Polarity)
+{
+ MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_WAVEPOL, Polarity);
+}
+
+/**
+ * @brief Get actual output polarity
+ * @rmtoll CFG WAVPOL LPTIM_GetPolarity
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_OUTPUT_POLARITY_REGULAR
+ * @arg @ref LPTIM_OUTPUT_POLARITY_INVERSE
+ */
+uint32_t LPTIM_GetPolarity(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_WAVEPOL));
+}
+
+/**
+ * @brief Set actual prescaler division ratio.
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note When the LPTIM is configured to be clocked by an internal clock source
+ * and the LPTIM counter is configured to be updated by active edges
+ * detected on the LPTIM external Input1, the internal clock provided to
+ * the LPTIM must be not be prescaled.
+ * @rmtoll CFG PRESC LPTIM_SetPrescaler
+ * @param LPTIMx Low-Power Timer instance
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LPTIM_PRESCALER_DIV1
+ * @arg @ref LPTIM_PRESCALER_DIV2
+ * @arg @ref LPTIM_PRESCALER_DIV4
+ * @arg @ref LPTIM_PRESCALER_DIV8
+ * @arg @ref LPTIM_PRESCALER_DIV16
+ * @arg @ref LPTIM_PRESCALER_DIV32
+ * @arg @ref LPTIM_PRESCALER_DIV64
+ * @arg @ref LPTIM_PRESCALER_DIV128
+ * @retval None
+ */
+void LPTIM_SetPrescaler(LPTIM_Module *LPTIMx, uint32_t Prescaler)
+{
+ MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKPRE, Prescaler);
+}
+
+/**
+ * @brief Get actual prescaler division ratio.
+ * @rmtoll CFG PRESC LPTIM_GetPrescaler
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_PRESCALER_DIV1
+ * @arg @ref LPTIM_PRESCALER_DIV2
+ * @arg @ref LPTIM_PRESCALER_DIV4
+ * @arg @ref LPTIM_PRESCALER_DIV8
+ * @arg @ref LPTIM_PRESCALER_DIV16
+ * @arg @ref LPTIM_PRESCALER_DIV32
+ * @arg @ref LPTIM_PRESCALER_DIV64
+ * @arg @ref LPTIM_PRESCALER_DIV128
+ */
+uint32_t LPTIM_GetPrescaler(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKPRE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_EF_Trigger_Configuration Trigger Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable the timeout function
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note The first trigger event will start the timer, any successive trigger
+ * event will reset the counter and the timer will restart.
+ * @note The timeout value corresponds to the compare value; if no trigger
+ * occurs within the expected time frame, the MCU is waked-up by the
+ * compare match event.
+ * @rmtoll CFG TIMOUT LPTIM_EnableTimeout
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_EnableTimeout(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->CFG, LPTIM_CFG_TIMOUTEN);
+}
+
+/**
+ * @brief Disable the timeout function
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note A trigger event arriving when the timer is already started will be
+ * ignored.
+ * @rmtoll CFG TIMOUT LPTIM_DisableTimeout
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_DisableTimeout(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->CFG, LPTIM_CFG_TIMOUTEN);
+}
+
+/**
+ * @brief Indicate whether the timeout function is enabled.
+ * @rmtoll CFG TIMOUT LPTIM_IsEnabledTimeout
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsEnabledTimeout(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->CFG, LPTIM_CFG_TIMOUTEN) == LPTIM_CFG_TIMOUTEN)? 1UL : 0UL));
+}
+
+/**
+ * @brief Start the LPTIM counter
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @rmtoll CFG TRIGEN LPTIM_TrigSw
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_TrigSw(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->CFG, LPTIM_CFG_TRGEN);
+}
+
+/**
+ * @brief Configure the external trigger used as a trigger event for the LPTIM.
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note An internal clock source must be present when a digital filter is
+ * required for the trigger.
+ * @rmtoll CFG TRIGSEL LPTIM_ConfigTrigger\n
+ * CFG TRGFLT LPTIM_ConfigTrigger\n
+ * CFG TRIGEN LPTIM_ConfigTrigger
+ * @param LPTIMx Low-Power Timer instance
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LPTIM_TRIG_SOURCE_GPIO
+ * @arg @ref LPTIM_TRIG_SOURCE_RTCALARMA
+ * @arg @ref LPTIM_TRIG_SOURCE_RTCALARMB
+ * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP1 (*)
+ * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP2
+ * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP3 (*)
+ * @arg @ref LPTIM_TRIG_SOURCE_COMP1
+ * @arg @ref LPTIM_TRIG_SOURCE_COMP2
+ *
+ * (*) Value not defined in all devices. \n
+ *
+ * @param Filter This parameter can be one of the following values:
+ * @arg @ref LPTIM_TRIG_FILTER_NONE
+ * @arg @ref LPTIM_TRIG_FILTER_2
+ * @arg @ref LPTIM_TRIG_FILTER_4
+ * @arg @ref LPTIM_TRIG_FILTER_8
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LPTIM_TRIG_POLARITY_RISING
+ * @arg @ref LPTIM_TRIG_POLARITY_FALLING
+ * @arg @ref LPTIM_TRIG_POLARITY_RISING_FALLING
+ * @retval None
+ */
+void LPTIM_ConfigTrigger(LPTIM_Module *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
+{
+ MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_TRGSEL | LPTIM_CFG_TRIGFLT | LPTIM_CFG_TRGEN, Source | Filter | Polarity);
+}
+
+/**
+ * @brief Get actual external trigger source.
+ * @rmtoll CFG TRIGSEL LPTIM_GetTriggerSource
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_TRIG_SOURCE_GPIO
+ * @arg @ref LPTIM_TRIG_SOURCE_RTCALARMA
+ * @arg @ref LPTIM_TRIG_SOURCE_RTCALARMB
+ * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP1 (*)
+ * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP2
+ * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP3 (*)
+ * @arg @ref LPTIM_TRIG_SOURCE_COMP1
+ * @arg @ref LPTIM_TRIG_SOURCE_COMP2
+ *
+ * (*) Value not defined in all devices. \n
+ *
+ */
+uint32_t LPTIM_GetTriggerSource(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_TRGSEL));
+}
+
+/**
+ * @brief Get actual external trigger filter.
+ * @rmtoll CFG TRGFLT LPTIM_GetTriggerFilter
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_TRIG_FILTER_NONE
+ * @arg @ref LPTIM_TRIG_FILTER_2
+ * @arg @ref LPTIM_TRIG_FILTER_4
+ * @arg @ref LPTIM_TRIG_FILTER_8
+ */
+uint32_t LPTIM_GetTriggerFilter(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_TRIGFLT));
+}
+
+/**
+ * @brief Get actual external trigger polarity.
+ * @rmtoll CFG TRIGEN LPTIM_GetTriggerPolarity
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_TRIG_POLARITY_RISING
+ * @arg @ref LPTIM_TRIG_POLARITY_FALLING
+ * @arg @ref LPTIM_TRIG_POLARITY_RISING_FALLING
+ */
+uint32_t LPTIM_GetTriggerPolarity(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_TRGEN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_EF_Clock_Configuration Clock Configuration
+ * @{
+ */
+
+/**
+ * @brief Set the source of the clock used by the LPTIM instance.
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @rmtoll CFG CKSEL LPTIM_SetClockSource
+ * @param LPTIMx Low-Power Timer instance
+ * @param ClockSource This parameter can be one of the following values:
+ * @arg @ref LPTIM_CLK_SOURCE_INTERNAL
+ * @arg @ref LPTIM_CLK_SOURCE_EXTERNAL
+ * @retval None
+ */
+void LPTIM_SetClockSource(LPTIM_Module *LPTIMx, uint32_t ClockSource)
+{
+ MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKSEL, ClockSource);
+}
+
+/**
+ * @brief Get actual LPTIM instance clock source.
+ * @rmtoll CFG CKSEL LPTIM_GetClockSource
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_CLK_SOURCE_INTERNAL
+ * @arg @ref LPTIM_CLK_SOURCE_EXTERNAL
+ */
+uint32_t LPTIM_GetClockSource(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKSEL));
+}
+
+/**
+ * @brief Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note When both external clock signal edges are considered active ones,
+ * the LPTIM must also be clocked by an internal clock source with a
+ * frequency equal to at least four times the external clock frequency.
+ * @note An internal clock source must be present when a digital filter is
+ * required for external clock.
+ * @rmtoll CFG CKFLT LPTIM_ConfigClock\n
+ * CFG CKPOL LPTIM_ConfigClock
+ * @param LPTIMx Low-Power Timer instance
+ * @param ClockFilter This parameter can be one of the following values:
+ * @arg @ref LPTIM_CLK_FILTER_NONE
+ * @arg @ref LPTIM_CLK_FILTER_2
+ * @arg @ref LPTIM_CLK_FILTER_4
+ * @arg @ref LPTIM_CLK_FILTER_8
+ * @param ClockPolarity This parameter can be one of the following values:
+ * @arg @ref LPTIM_CLK_POLARITY_RISING
+ * @arg @ref LPTIM_CLK_POLARITY_FALLING
+ * @arg @ref LPTIM_CLK_POLARITY_RISING_FALLING
+ * @retval None
+ */
+void LPTIM_ConfigClock(LPTIM_Module *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
+{
+ MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKFLT | LPTIM_CFG_CLKPOL, ClockFilter | ClockPolarity);
+}
+
+/**
+ * @brief Get actual clock polarity
+ * @rmtoll CFG CKPOL LPTIM_GetClockPolarity
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_CLK_POLARITY_RISING
+ * @arg @ref LPTIM_CLK_POLARITY_FALLING
+ * @arg @ref LPTIM_CLK_POLARITY_RISING_FALLING
+ */
+uint32_t LPTIM_GetClockPolarity(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKPOL));
+}
+
+/**
+ * @brief Get actual clock digital filter
+ * @rmtoll CFG CKFLT LPTIM_GetClockFilter
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_CLK_FILTER_NONE
+ * @arg @ref LPTIM_CLK_FILTER_2
+ * @arg @ref LPTIM_CLK_FILTER_4
+ * @arg @ref LPTIM_CLK_FILTER_8
+ */
+uint32_t LPTIM_GetClockFilter(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKFLT));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_EF_Encoder_Mode Encoder Mode
+ * @{
+ */
+
+/**
+ * @brief Configure the encoder mode.
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @rmtoll CFG CKPOL LPTIM_SetEncoderMode
+ * @param LPTIMx Low-Power Timer instance
+ * @param EncoderMode This parameter can be one of the following values:
+ * @arg @ref LPTIM_ENCODER_MODE_RISING
+ * @arg @ref LPTIM_ENCODER_MODE_FALLING
+ * @arg @ref LPTIM_ENCODER_MODE_RISING_FALLING
+ * @retval None
+ */
+void LPTIM_SetEncoderMode(LPTIM_Module *LPTIMx, uint32_t EncoderMode)
+{
+ MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKPOL, EncoderMode);
+}
+
+/**
+ * @brief Get actual encoder mode.
+ * @rmtoll CFG CKPOL LPTIM_GetEncoderMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_ENCODER_MODE_RISING
+ * @arg @ref LPTIM_ENCODER_MODE_FALLING
+ * @arg @ref LPTIM_ENCODER_MODE_RISING_FALLING
+ */
+uint32_t LPTIM_GetEncoderMode(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKPOL));
+}
+
+/**
+ * @brief Enable the encoder mode
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note In this mode the LPTIM instance must be clocked by an internal clock
+ * source. Also, the prescaler division ratio must be equal to 1.
+ * @note LPTIM instance must be configured in continuous mode prior enabling
+ * the encoder mode.
+ * @rmtoll CFG ENC LPTIM_EnableEncoderMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_EnableEncoderMode(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->CFG, LPTIM_CFG_ENC);
+}
+/**
+ * @brief Enable the encoder mode
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note In this mode the LPTIM instance must be clocked by an internal clock
+ * source. Also, the prescaler division ratio must be equal to 1.
+ * @note LPTIM instance must be configured in continuous mode prior enabling
+ * the encoder mode.
+ * @rmtoll CFG ENC LPTIM_EnableEncoderMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_EnableNoEncoderMode(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->CFG, LPTIM_CFG_NENC);
+}
+/**
+ * @brief Disable the encoder mode
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @rmtoll CFG ENC LPTIM_DisableEncoderMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_DisableEncoderMode(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->CFG, LPTIM_CFG_ENC);
+}
+
+/**
+ * @brief Indicates whether the LPTIM operates in encoder mode.
+ * @rmtoll CFG ENC LPTIM_IsEnabledEncoderMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsEnabledEncoderMode(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->CFG, LPTIM_CFG_ENC) == LPTIM_CFG_ENC)? 1UL : 0UL));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_EF_FLAG_Management FLAG Management
+ * @{
+ */
+
+/**
+ * @brief Clear the compare match flag (CMPMCF)
+ * @rmtoll ICR CMPMCF LPTIM_ClearFLAG_CMPM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_ClearFLAG_CMPM(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_CMPMCF);
+}
+
+/**
+ * @brief Inform application whether a compare match interrupt has occurred.
+ * @rmtoll ISR CMPM LPTIM_IsActiveFlag_CMPM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsActiveFlag_CMPM(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_CMPM) ==LPTIM_INTSTS_CMPM)? 1UL : 0UL));
+}
+
+/**
+ * @brief Clear the autoreload match flag (ARRMCF)
+ * @rmtoll ICR ARRMCF LPTIM_ClearFLAG_ARRM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_ClearFLAG_ARRM(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_ARRMCF);
+}
+
+/**
+ * @brief Inform application whether a autoreload match interrupt has occured.
+ * @rmtoll ISR ARRM LPTIM_IsActiveFlag_ARRM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsActiveFlag_ARRM(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_ARRM) ==LPTIM_INTSTS_ARRM)? 1UL : 0UL));
+}
+
+/**
+ * @brief Clear the external trigger valid edge flag(EXTTRIGCF).
+ * @rmtoll ICR EXTTRIGCF LPTIM_ClearFlag_EXTTRIG
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_ClearFlag_EXTTRIG(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_EXTRIGCF);
+}
+
+/**
+ * @brief Inform application whether a valid edge on the selected external trigger input has occurred.
+ * @rmtoll ISR EXTTRIG LPTIM_IsActiveFlag_EXTTRIG
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsActiveFlag_EXTTRIG(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_EXTRIG) ==LPTIM_INTSTS_EXTRIG)? 1UL : 0UL));
+}
+
+/**
+ * @brief Clear the compare register update interrupt flag (CMPOKCF).
+ * @rmtoll ICR CMPOKCF LPTIM_ClearFlag_CMPOK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_ClearFlag_CMPOK(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_CMPUPDCF);
+}
+
+/**
+ * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed. If so, a new one can be initiated.
+ * @rmtoll ISR CMPOK LPTIM_IsActiveFlag_CMPOK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsActiveFlag_CMPOK(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_CMPUPD) ==LPTIM_INTSTS_CMPUPD)? 1UL : 0UL));
+}
+
+/**
+ * @brief Clear the autoreload register update interrupt flag (ARROKCF).
+ * @rmtoll ICR ARROKCF LPTIM_ClearFlag_ARROK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_ClearFlag_ARROK(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_ARRUPDCF);
+}
+
+/**
+ * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed. If so, a new one can be initiated.
+ * @rmtoll ISR ARROK LPTIM_IsActiveFlag_ARROK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsActiveFlag_ARROK(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_ARRUPD) ==LPTIM_INTSTS_ARRUPD)? 1UL : 0UL));
+}
+
+/**
+ * @brief Clear the counter direction change to up interrupt flag (UPCF).
+ * @rmtoll ICR UPCF LPTIM_ClearFlag_UP
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_ClearFlag_UP(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_UPCF);
+}
+
+/**
+ * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).
+ * @rmtoll ISR UP LPTIM_IsActiveFlag_UP
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsActiveFlag_UP(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTSTS, LPTIM_INTSTS_UP) == LPTIM_INTSTS_UP)? 1UL : 0UL));
+}
+
+/**
+ * @brief Clear the counter direction change to down interrupt flag (DOWNCF).
+ * @rmtoll ICR DOWNCF LPTIM_ClearFlag_DOWN
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_ClearFlag_DOWN(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_DOWNCF);
+}
+
+/**
+ * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).
+ * @rmtoll ISR DOWN LPTIM_IsActiveFlag_DOWN
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsActiveFlag_DOWN(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_DOWN) ==LPTIM_INTSTS_DOWN)? 1UL : 0UL));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_EF_IT_Management Interrupt Management
+ * @{
+ */
+
+/**
+ * @brief Enable compare match interrupt (CMPMIE).
+ * @rmtoll IER CMPMIE LPTIM_EnableIT_CMPM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_EnableIT_CMPM(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPMIE);
+}
+
+/**
+ * @brief Disable compare match interrupt (CMPMIE).
+ * @rmtoll IER CMPMIE LPTIM_DisableIT_CMPM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_DisableIT_CMPM(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPMIE);
+}
+
+/**
+ * @brief Indicates whether the compare match interrupt (CMPMIE) is enabled.
+ * @rmtoll IER CMPMIE LPTIM_IsEnabledIT_CMPM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsEnabledIT_CMPM(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPMIE) == LPTIM_INTEN_CMPMIE)? 1UL : 0UL));
+}
+
+/**
+ * @brief Enable autoreload match interrupt (ARRMIE).
+ * @rmtoll IER ARRMIE LPTIM_EnableIT_ARRM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_EnableIT_ARRM(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRMIE);
+}
+
+/**
+ * @brief Disable autoreload match interrupt (ARRMIE).
+ * @rmtoll IER ARRMIE LPTIM_DisableIT_ARRM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_DisableIT_ARRM(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRMIE);
+}
+
+/**
+ * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
+ * @rmtoll IER ARRMIE LPTIM_IsEnabledIT_ARRM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsEnabledIT_ARRM(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRMIE) == LPTIM_INTEN_ARRMIE)? 1UL : 0UL));
+}
+
+/**
+ * @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
+ * @rmtoll IER EXTTRIGIE LPTIM_EnableIT_EXTTRIG
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_EnableIT_EXTTRIG(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_EXTRIGIE);
+}
+
+/**
+ * @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
+ * @rmtoll IER EXTTRIGIE LPTIM_DisableIT_EXTTRIG
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_DisableIT_EXTTRIG(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_EXTRIGIE);
+}
+
+/**
+ * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
+ * @rmtoll IER EXTTRIGIE LPTIM_IsEnabledIT_EXTTRIG
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsEnabledIT_EXTTRIG(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_EXTRIGIE) == LPTIM_INTEN_EXTRIGIE)? 1UL : 0UL));
+}
+
+/**
+ * @brief Enable compare register write completed interrupt (CMPOKIE).
+ * @rmtoll IER CMPOKIE LPTIM_EnableIT_CMPOK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_EnableIT_CMPOK(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPUPDIE);
+}
+
+/**
+ * @brief Disable compare register write completed interrupt (CMPOKIE).
+ * @rmtoll IER CMPOKIE LPTIM_DisableIT_CMPOK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_DisableIT_CMPOK(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPUPDIE);
+}
+
+/**
+ * @brief Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
+ * @rmtoll IER CMPOKIE LPTIM_IsEnabledIT_CMPOK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsEnabledIT_CMPOK(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPUPDIE) == LPTIM_INTEN_CMPUPDIE)? 1UL : 0UL));
+}
+
+/**
+ * @brief Enable autoreload register write completed interrupt (ARROKIE).
+ * @rmtoll IER ARROKIE LPTIM_EnableIT_ARROK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_EnableIT_ARROK(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRUPDIE);
+}
+
+/**
+ * @brief Disable autoreload register write completed interrupt (ARROKIE).
+ * @rmtoll IER ARROKIE LPTIM_DisableIT_ARROK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_DisableIT_ARROK(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRUPDIE);
+}
+
+/**
+ * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
+ * @rmtoll IER ARROKIE LPTIM_IsEnabledIT_ARROK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsEnabledIT_ARROK(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRUPDIE) == LPTIM_INTEN_ARRUPDIE)? 1UL : 0UL));
+}
+
+/**
+ * @brief Enable direction change to up interrupt (UPIE).
+ * @rmtoll IER UPIE LPTIM_EnableIT_UP
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_EnableIT_UP(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_UPIE);
+}
+
+/**
+ * @brief Disable direction change to up interrupt (UPIE).
+ * @rmtoll IER UPIE LPTIM_DisableIT_UP
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_DisableIT_UP(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_UPIE);
+}
+
+/**
+ * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
+ * @rmtoll IER UPIE LPTIM_IsEnabledIT_UP
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsEnabledIT_UP(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_UPIE) == LPTIM_INTEN_UPIE)? 1UL : 0UL));
+}
+
+/**
+ * @brief Enable direction change to down interrupt (DOWNIE).
+ * @rmtoll IER DOWNIE LPTIM_EnableIT_DOWN
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_EnableIT_DOWN(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_DOWNIE);
+}
+
+/**
+ * @brief Disable direction change to down interrupt (DOWNIE).
+ * @rmtoll IER DOWNIE LPTIM_DisableIT_DOWN
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_DisableIT_DOWN(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_DOWNIE);
+}
+
+/**
+ * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
+ * @rmtoll IER DOWNIE LPTIM_IsEnabledIT_DOWN
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsEnabledIT_DOWN(LPTIM_Module *LPTIMx)
+{
+ return ((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_DOWNIE) == LPTIM_INTEN_DOWNIE)? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+
+//#endif /* LPTIM */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/******************* (C) COPYRIGHT 2019 NATIONZ *****END OF FILE****/
+
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_lpuart.c b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_lpuart.c
new file mode 100644
index 0000000000..9fd881e25e
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_lpuart.c
@@ -0,0 +1,532 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_lpuart.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l40x_lpuart.h"
+#include "n32l40x_rcc.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup LPUART
+ * @brief LPUART driver modules
+ * @{
+ */
+
+/** @addtogroup LPUART_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Private_Defines
+ * @{
+ */
+
+#define STS_CLR_MASK ((uint16_t)0x01BF) /*!< LPUART STS Mask */
+
+#define INTEN_CLR_MASK ((uint16_t)0x0000) /*!< LPUART INTEN Mask */
+#define INT_MASK ((uint16_t)0x007F) /*!< LPUART Interrupt Mask */
+
+#define CTRL_CLR_MASK ((uint16_t)0x70F4) /*!< LPUART CTRL Mask */
+#define CTRL_SMPCNT_MASK ((uint16_t)0x3FFF) /*!< LPUART Sampling Method Mask */
+#define CTRL_WUSTP_MASK ((uint16_t)0x4FFF) /*!< LPUART WakeUp Method Mask */
+#define CTRL_WUSTP_SET ((uint16_t)0x0080) /*!< LPUART stop mode Enable Mask */
+#define CTRL_WUSTP_RESET ((uint16_t)0x7F7F) /*!< LPUART stop mode Disable Mask */
+#define CTRL_LOOPBACK_SET ((uint16_t)0x0010) /*!< LPUART Loopback Test Enable Mask */
+#define CTRL_LOOPBACK_RESET ((uint16_t)0xFFEF) /*!< LPUART Loopback Test Disable Mask */
+#define CTRL_FLUSH_SET ((uint16_t)0x0004) /*!< LPUART Flush Receiver FIFO Enable Mask */
+#define CTRL_FLUSH_RESET ((uint16_t)0x7FFB) /*!< LPUART Flush Receiver FIFO Disable Mask */
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the LPUART peripheral registers to their default reset values.
+ */
+void LPUART_DeInit(void)
+{
+ RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LPUART, ENABLE);
+ RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LPUART, DISABLE);
+}
+
+/**
+ * @brief Initializes the LPUART peripheral according to the specified
+ * parameters in the LPUART_InitStruct.
+ * @param LPUART_InitStruct pointer to a LPUART_InitType structure
+ * that contains the configuration information for the specified LPUART
+ * peripheral.
+ */
+void LPUART_Init(LPUART_InitType* LPUART_InitStruct)
+{
+ uint32_t tmpregister = 0x00, clocksrc = 0x00, apbclock = 0x00;
+ uint32_t integerdivider = 0x00;
+ uint32_t fractionaldivider = 0x00;
+ uint32_t tmpdivider = 0x00, lastdivider = 0x00, i = 0x00;
+ RCC_ClocksType RCC_ClocksStatus;
+
+ /* Check the parameters */
+ // assert_param(IS_LPUART_BAUDRATE(LPUART_InitStruct->BaudRate));
+ assert_param(IS_LPUART_PARITY(LPUART_InitStruct->Parity));
+ assert_param(IS_LPUART_MODE(LPUART_InitStruct->Mode));
+ assert_param(IS_LPUART_RTSTHRESHOLD(LPUART_InitStruct->RtsThreshold));
+ assert_param(IS_LPUART_HARDWARE_FLOW_CONTROL(LPUART_InitStruct->HardwareFlowControl));
+
+ // 时钟æºåˆ¤æ–，波特率范围
+
+ /*---------------------------- LPUART CTRL Configuration -----------------------*/
+ tmpregister = LPUART->CTRL;
+ /* Clear FC_RXEN, FC_TXEN, RTS_THSEL[1:0], PCDIS, TRS and PSEL bits */
+ tmpregister &= CTRL_CLR_MASK;
+ /* Configure the LPUART Parity, Mode, RtsThrehold and HardwareFlowControl ----------------------- */
+ /* Set PCDIS and PSEL bits according to Parity value */
+ /* Set the TRS bit according to Mode */
+ /* Set RTS_THSEL[1:0] bits according to RtsThrehold */
+ /* Set FC_RXEN and FC_TXEN bits according to HardwareFlowControl */
+ tmpregister |= (uint32_t)LPUART_InitStruct->Parity | LPUART_InitStruct->Mode | LPUART_InitStruct->RtsThreshold | LPUART_InitStruct->HardwareFlowControl;
+ /* Write to LPUART CTRL */
+ LPUART->CTRL = (uint16_t)tmpregister;
+
+ /*---------------------------- LPUART BRCFG1 & 2 Configuration -----------------------*/
+ /* Configure the LPUART Baud Rate -------------------------------------------*/
+ clocksrc = RCC_GetLPUARTClkSrc();
+ if (clocksrc == RCC_LPUARTCLK_SRC_LSE)
+ {
+ apbclock = 0x8000; // 32.768kHz
+ }
+ else if (clocksrc == RCC_LPUARTCLK_SRC_HSI)
+ {
+ apbclock = 0xF42400; // 16MHz
+ }
+ else if (clocksrc == RCC_LPUARTCLK_SRC_SYSCLK)
+ {
+ RCC_GetClocksFreqValue(&RCC_ClocksStatus);
+ apbclock = RCC_ClocksStatus.SysclkFreq;
+ }
+ else //(clocksrc ==RCC_LPUARTCLK_SRC_APB1)
+ {
+ RCC_GetClocksFreqValue(&RCC_ClocksStatus);
+ apbclock = RCC_ClocksStatus.Pclk1Freq;
+ }
+
+ /* Determine the integer part */
+ integerdivider = apbclock / (LPUART_InitStruct->BaudRate);
+
+ /* Configure sampling method */
+ if (integerdivider <= 10)
+ {
+ LPUART_ConfigSamplingMethod(LPUART_SMPCNT_1B);
+ }
+ else
+ {
+ LPUART_ConfigSamplingMethod(LPUART_SMPCNT_3B);
+ }
+
+ /* Check baudrate */
+ assert_param(IS_LPUART_BAUDRATE(integerdivider));
+ /* Write to LPUART BRCFG1 */
+ LPUART->BRCFG1 = (uint16_t)integerdivider;
+
+ /* Determine the fractional part */
+ fractionaldivider = ((apbclock % (LPUART_InitStruct->BaudRate)) * 10000) / (LPUART_InitStruct->BaudRate);
+
+ tmpregister = 0x00;
+ tmpdivider = fractionaldivider;
+ /* Implement the fractional part in the register */
+ for( i = 0; i < 8; i++)
+ {
+ lastdivider = tmpdivider;
+ tmpdivider = lastdivider + fractionaldivider;
+ if ((tmpdivider / 10000) ^ (lastdivider / 10000))
+ {
+ tmpregister |= (0x01 << i);
+ }
+ }
+ /* Write to LPUART BRCFG2 */
+ LPUART->BRCFG2 = (uint8_t)tmpregister;
+}
+
+/**
+ * @brief Fills each LPUART_InitStruct member with its default value.
+ * @param LPUART_InitStruct pointer to a LPUART_InitType structure
+ * which will be initialized.
+ */
+void LPUART_StructInit(LPUART_InitType* LPUART_InitStruct)
+{
+ /* LPUART_InitStruct members default value */
+ LPUART_InitStruct->BaudRate = 9600;
+ LPUART_InitStruct->Parity = LPUART_PE_NO;
+ LPUART_InitStruct->Mode = LPUART_MODE_RX | LPUART_MODE_TX;
+ LPUART_InitStruct->RtsThreshold = LPUART_RTSTH_FIFOFU;
+ LPUART_InitStruct->HardwareFlowControl = LPUART_HFCTRL_NONE;
+}
+
+/**
+ * @brief Flushes Receiver FIFO.
+ */
+void LPUART_FlushRxFifo(void)
+{
+ /* Clear LPUART Flush Receiver FIFO */
+ LPUART->CTRL |= CTRL_FLUSH_SET;
+ while (LPUART_GetFlagStatus(LPUART_FLAG_FIFO_NE) != RESET)
+ {
+ }
+ LPUART->CTRL &= CTRL_FLUSH_RESET;
+}
+
+/**
+ * @brief Enables or disables the specified LPUART interrupts.
+ * @param LPUART_INT specifies the LPUART interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg LPUART_INT_WUF Wake-Up Interrupt
+ * @arg LPUART_INT_FIFO_NE FIFO Non-Empty Interrupt
+ * @arg LPUART_INT_FIFO_HF FIFO Half Full Interrupt
+ * @arg LPUART_INT_FIFO_FU FIFO Full Interrupt Enable
+ * @arg LPUART_INT_FIFO_OV FIFO Overflow Interrupt
+ * @arg LPUART_INT_TXC TX Complete Interrupt
+ * @arg LPUART_INT_PE Parity Check Error Interrupt
+ * @param Cmd new state of the specified LPUART interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void LPUART_ConfigInt(uint16_t LPUART_INT, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_LPUART_CFG_INT(LPUART_INT));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ LPUART->INTEN |= (uint8_t)LPUART_INT;
+ }
+ else
+ {
+ LPUART->INTEN &= (uint8_t)(~LPUART_INT);
+ }
+}
+
+/**
+ * @brief Enables or disables the LPUART's DMA interface.
+ * @param LPUART_DMAReq specifies the DMA request.
+ * This parameter can be any combination of the following values:
+ * @arg LPUART_DMAREQ_TX LPUART DMA transmit request
+ * @arg LPUART_DMAREQ_RX LPUART DMA receive request
+ * @param Cmd new state of the DMA Request sources.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void LPUART_EnableDMA(uint16_t LPUART_DMAReq, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_LPUART_DMAREQ(LPUART_DMAReq));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the DMA transfer by setting the DMA_RXEN and/or DMA_TXEN bits in the LPUART_CTRL register */
+ LPUART->CTRL |= LPUART_DMAReq;
+ }
+ else
+ {
+ /* Disable the DMA transfer by clearing the DMA_RXEN and/or DMA_TXEN bits in the LPUART_CTRL register */
+ LPUART->CTRL &= (uint16_t)(~LPUART_DMAReq);
+ }
+}
+
+/**
+ * @brief Selects the LPUART WakeUp method.
+ * @param LPUART_WakeUpMethod specifies the LPUART wakeup method.
+ * This parameter can be one of the following values:
+ * @arg LPUART_WUSTP_STARTBIT WakeUp by Start Bit Detection
+ * @arg LPUART_WUSTP_RXNE WakeUp by RXNE Detection
+ * @arg LPUART_WUSTP_BYTE WakeUp by A Configurable Received Byte
+ * @arg LPUART_WUSTP_FRAME WakeUp by A Programmed 4-Byte Frame
+ */
+void LPUART_ConfigWakeUpMethod(uint16_t LPUART_WakeUpMethod)
+{
+ /* Check the parameters */
+ assert_param(IS_LPUART_WAKEUP(LPUART_WakeUpMethod));
+
+ LPUART->CTRL &= CTRL_WUSTP_MASK;
+ LPUART->CTRL |= LPUART_WakeUpMethod;
+}
+
+/**
+ * @brief Enables or disables LPUART Wakeup in STOP2 mode.
+ * @param Cmd new state of the LPUART Wakeup in STOP2 mode.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void LPUART_EnableWakeUpStop(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable Wakeup in STOP2 mode by setting the WUSTP bit in the CTRL register */
+ LPUART->CTRL |= CTRL_WUSTP_SET;
+ }
+ else
+ {
+ /* Disable Wakeup in STOP2 mode by clearing the WUSTP bit in the CTRL register */
+ LPUART->CTRL &= CTRL_WUSTP_RESET;
+ }
+}
+
+/**
+ * @brief Selects the LPUART Sampling method.
+ * @param LPUART_SamplingMethod specifies the LPAURT sampling method.
+ * This parameter can be one of the following values:
+ * @arg LPUART_SMPCNT_3B 3 Sample bit
+ * @arg LPUART_SMPCNT_1B 1 Sample bit
+ */
+void LPUART_ConfigSamplingMethod(uint16_t LPUART_SamplingMethod)
+{
+ /* Check the parameters */
+ assert_param(IS_LPUART_SAMPLING(LPUART_SamplingMethod));
+
+ LPUART->CTRL &= CTRL_SMPCNT_MASK;
+ LPUART->CTRL |= LPUART_SamplingMethod;
+}
+
+/**
+ * @brief Enables or disables LPUART Loop Back Self-Test.
+ * @param Cmd new state of the LPUART Loop Back Self-Test.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void LPUART_EnableLoopBack(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable LPUART Loop Back Self-Test by setting the LOOKBACK bit in the CTRL register */
+ LPUART->CTRL |= CTRL_LOOPBACK_SET;
+ }
+ else
+ {
+ /* Disable LPUART Loop Back Self-Test by clearing the LOOKBACK bit in the CTRL register */
+ LPUART->CTRL &= CTRL_LOOPBACK_RESET;
+ }
+}
+
+/**
+ * @brief Transmits single data through the LPUART peripheral.
+ * @param Data the data to transmit.
+ */
+void LPUART_SendData(uint8_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_LPUART_DATA(Data));
+
+ /* Transmit Data */
+ LPUART->DAT = (Data & (uint8_t)0xFF);
+}
+
+/**
+ * @brief Returns the most recent received data by the LPUART peripheral.
+ * @return The received data.
+ */
+uint8_t LPUART_ReceiveData(void)
+{
+ /* Receive Data */
+ return (uint8_t)(LPUART->DAT & (uint8_t)0xFF);
+}
+
+/**
+ * @brief SConfigures LPUART detected byte or frame match for wakeup CPU from STOPS mode.
+ * @param LPUART_WakeUpData specifies the LPUART detected byte or frame match for wakeup CPU from STOP2 mode.
+ */
+void LPUART_ConfigWakeUpData(uint32_t LPUART_WakeUpData)
+{
+ LPUART->WUDAT = LPUART_WakeUpData;
+}
+
+/**
+ * @brief Checks whether the specified LPUART flag is set or not.
+ * @param LPUART_FLAG specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg LPUART_FLAG_PEF Parity Check Error Flag.
+ * @arg LPUART_FLAG_TXC TX Complete Flag.
+ * @arg LPUART_FLAG_FIFO_OV FIFO Overflow Flag.
+ * @arg LPUART_FLAG_FIFO_FU FIFO Full Flag.
+ * @arg LPUART_FLAG_FIFO_HF FIFO Half Full Flag.
+ * @arg LPUART_FLAG_FIFO_NE FIFO Non-Empty Flag.
+ * @arg LPUART_FLAG_CTS CTS Change(Hardware Flow Control) Flag.
+ * @arg LPUART_FLAG_WUFWakeup from STOP2 mode Flag.
+ * @arg LPUART_FLAG_NF Noise Detection Flag.
+ * @return The new state of LPUART_FLAG (SET or RESET).
+ */
+FlagStatus LPUART_GetFlagStatus(uint16_t LPUART_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_LPUART_FLAG(LPUART_FLAG));
+
+ if ((LPUART->STS & LPUART_FLAG) != (uint16_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the LPUART's pending flags.
+ * @param LPUART_FLAG specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg LPUART_FLAG_PEF Parity Check Error Flag.
+ * @arg LPUART_FLAG_TXC TX Complete Flag.
+ * @arg LPUART_FLAG_FIFO_OV FIFO Overflow Flag.
+ * @arg LPUART_FLAG_FIFO_FU FIFO Full Flag.
+ * @arg LPUART_FLAG_FIFO_HF FIFO Half Full Flag.
+ * @arg LPUART_FLAG_FIFO_NE FIFO Non-Empty Flag.
+ * @arg LPUART_FLAG_CTS CTS Change(Hardware Flow Control) Flag.
+ * @arg LPUART_FLAG_WUFWakeup from STOP2 mode Flag.
+ * @arg LPUART_FLAG_NF Noise Detection Flag.
+ */
+void LPUART_ClrFlag(uint16_t LPUART_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_LPUART_CLEAR_FLAG(LPUART_FLAG));
+
+ LPUART->STS = (uint16_t)LPUART_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified LPUART interrupt has occurred or not.
+ * @param LPUART_INT specifies the LPUART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg LPUART_INT_WUF Wake-Up Interrupt
+ * @arg LPUART_INT_FIFO_NE FIFO Non-Empty Interrupt
+ * @arg LPUART_INT_FIFO_HF FIFO Half Full Interrupt
+ * @arg LPUART_INT_FIFO_FU FIFO Full Interrupt Enable
+ * @arg LPUART_INT_FIFO_OV FIFO Overflow Interrupt
+ * @arg LPUART_INT_TXC TX Complete Interrupt
+ * @arg LPUART_INT_PE Parity Check Error Interrupt
+ * @return The new state of LPUART_INT (SET or RESET).
+ */
+INTStatus LPUART_GetIntStatus(uint16_t LPUART_INT)
+{
+ uint32_t bitpos = 0x00, itmask = 0x00;
+ INTStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_LPUART_GET_INT(LPUART_INT));
+
+ /* Get the interrupt position */
+ itmask = (uint8_t)(LPUART_INT >> 0x08) & INT_MASK;
+ itmask = (uint32_t)0x01 << itmask;
+ itmask &= LPUART->INTEN;
+
+ bitpos = ((uint8_t)LPUART_INT) & 0xFF;
+ if (LPUART_INT_WUF == LPUART_INT){
+ bitpos = (bitpos << 0x01);
+ }
+ bitpos &= LPUART->STS;
+ if ((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the LPUART's interrupt pending bits.
+ * @param LPUART_INT specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg LPUART_INT_WUF Wake-Up Interrupt
+ * @arg LPUART_INT_FIFO_NE FIFO Non-Empty Interrupt
+ * @arg LPUART_INT_FIFO_HF FIFO Half Full Interrupt
+ * @arg LPUART_INT_FIFO_FU FIFO Full Interrupt Enable
+ * @arg LPUART_INT_FIFO_OV FIFO Overflow Interrupt
+ * @arg LPUART_INT_TXC TX Complete Interrupt
+ * @arg LPUART_INT_PE Parity Check Error Interrupt
+ */
+void LPUART_ClrIntPendingBit(uint16_t LPUART_INT)
+{
+ uint16_t itmask = 0x00;
+ /* Check the parameters */
+ assert_param(IS_LPUART_CLR_INT(LPUART_INT));
+
+ itmask = ((uint8_t)LPUART_INT) & 0xFF;
+ LPUART->STS = (uint16_t)itmask;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_opamp.c b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_opamp.c
new file mode 100644
index 0000000000..f06084ac0e
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_opamp.c
@@ -0,0 +1,198 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_opamp.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l40x_opamp.h"
+#include "n32l40x_rcc.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup OPAMP
+ * @brief OPAMP driver modules
+ * @{
+ */
+
+/** @addtogroup OPAMP_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup OPAMP_Private_Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup OPAMP_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup OPAMP_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup OPAMP_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup OPAMP_Private_Functions
+ * @{
+ */
+#define SetBitMsk(reg, bit, msk) ((reg) = (((reg) & ~(msk)) | (bit)))
+#define ClrBit(reg, bit) ((reg) &= ~(bit))
+#define SetBit(reg, bit) ((reg) |= (bit))
+#define GetBit(reg, bit) ((reg) & (bit))
+/**
+ * @brief Deinitializes the OPAMP peripheral registers to their default reset values.
+ */
+void OPAMP_DeInit(void)
+{
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_OPAMP, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_OPAMP, DISABLE);
+}
+void OPAMP_StructInit(OPAMP_InitType* OPAMP_InitStruct)
+{
+ OPAMP_InitStruct->Opa2SrcSel = OPAMP2_CS_TIMSRCSEL_TIM1CC6;
+ OPAMP_InitStruct->Gain = OPAMP_CS_PGA_GAIN_2;
+ OPAMP_InitStruct->HighVolRangeEn = ENABLE;
+ OPAMP_InitStruct->TimeAutoMuxEn = DISABLE;
+ OPAMP_InitStruct->Mod = OPAMP_CS_PGA_EN;
+}
+void OPAMP_Init(OPAMPX OPAMPx, OPAMP_InitType* OPAMP_InitStruct)
+{
+ __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+ __IO uint32_t tmp = *pCs;
+ if (OPAMPx == OPAMP2)
+ SetBitMsk(tmp, OPAMP_InitStruct->Opa2SrcSel, OPAMP_CS_OPAMP2_TIMSRCSEL);
+ SetBitMsk(tmp, OPAMP_InitStruct->Gain, OPAMP_CS_PGA_GAIN_MASK);
+ if (OPAMP_InitStruct->HighVolRangeEn==ENABLE)
+ SetBitMsk(tmp, OPAMP_CS_RANGE_MASK, OPAMP_CS_RANGE_MASK);
+ else
+ ClrBit(tmp,OPAMP_CS_RANGE_MASK);
+ if (OPAMP_InitStruct->TimeAutoMuxEn==ENABLE)
+ SetBitMsk(tmp,OPAMP_CS_TCMEN_MASK, OPAMP_CS_TCMEN_MASK);
+ else
+ ClrBit(tmp,OPAMP_CS_TCMEN_MASK);
+ SetBitMsk(tmp, OPAMP_InitStruct->Mod, OPAMP_CS_MOD_MASK);
+ *pCs = tmp;
+}
+void OPAMP_Enable(OPAMPX OPAMPx, FunctionalState en)
+{
+ __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+ if (en)
+ SetBit(*pCs, OPAMP_CS_EN_MASK);
+ else
+ ClrBit(*pCs, OPAMP_CS_EN_MASK);
+}
+
+void OPAMP_SetPgaGain(OPAMPX OPAMPx, OPAMP_CS_PGA_GAIN Gain)
+{
+ __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+ __IO uint32_t tmp = *pCs;
+ SetBitMsk(tmp, Gain, OPAMP_CS_PGA_GAIN_MASK);
+ *pCs = tmp;
+}
+void OPAMP_SetVpSecondSel(OPAMPX OPAMPx, OPAMP_CS_VPSSEL VpSSel)
+{
+ __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+ __IO uint32_t tmp = *pCs;
+ SetBitMsk(tmp, VpSSel, OPAMP_CS_VPSEL_SECOND_MASK);
+ *pCs = tmp;
+}
+void OPAMP_SetVmSecondSel(OPAMPX OPAMPx, OPAMP_CS_VMSSEL VmSSel)
+{
+ __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+ __IO uint32_t tmp = *pCs;
+ SetBitMsk(tmp, VmSSel, OPAMP_CS_VMSEL_SECOND_MASK);
+ *pCs = tmp;
+}
+void OPAMP_SetVpSel(OPAMPX OPAMPx, OPAMP_CS_VPSEL VpSel)
+{
+ __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+ __IO uint32_t tmp = *pCs;
+ SetBitMsk(tmp, VpSel, OPAMP_CS_VPSEL_MASK);
+ *pCs = tmp;
+}
+void OPAMP_SetVmSel(OPAMPX OPAMPx, OPAMP_CS_VMSEL VmSel)
+{
+ __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+ __IO uint32_t tmp = *pCs;
+ SetBitMsk(tmp, VmSel, OPAMP_CS_VMSEL_MASK);
+ *pCs = tmp;
+}
+bool OPAMP_IsCalOutHigh(OPAMPX OPAMPx)
+{
+ __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+ return (GetBit(*pCs, OPAMP_CS_CALOUT_MASK)) ? true : false;
+}
+void OPAMP_CalibrationEnable(OPAMPX OPAMPx, FunctionalState en)
+{
+ __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+ if (en)
+ SetBit(*pCs, OPAMP_CS_CALON_MASK);
+ else
+ ClrBit(*pCs, OPAMP_CS_CALON_MASK);
+}
+// Lock see @OPAMP_LOCK
+void OPAMP_SetLock(uint32_t Lock)
+{
+ OPAMP->LOCK = Lock;
+}
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_pwr.c b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_pwr.c
new file mode 100644
index 0000000000..de41d2c9ca
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_pwr.c
@@ -0,0 +1,572 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_pwr.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l40x_pwr.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup PWR
+ * @brief PWR driver modules
+ * @{
+ */
+
+/** @addtogroup PWR_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Private_Defines
+ * @{
+ */
+
+/* --------- PWR registers bit address in the alias region ---------- */
+#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
+
+/* --- CTRL Register ---*/
+
+/* Alias word address of DBKP bit */
+#define CTRL_OFFSET (PWR_OFFSET + 0x00)
+#define DBKP_BITN 0x08
+#define CTRL_DBKP_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (DBKP_BITN * 4))
+
+/* Alias word address of PVDEN bit */
+#define PVDEN_BITN 0x04
+#define CTRL_PVDEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (PVDEN_BITN * 4))
+
+/* --- CTRLSTS Register ---*/
+
+/* Alias word address of WKUPEN bit */
+#define CTRLSTS_OFFSET (PWR_OFFSET + 0x04)
+#define WKUPEN_BITN 0x08
+#define CTRLSTS_WKUPEN_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (WKUPEN_BITN * 4))
+
+/* ------------------ PWR registers bit mask ------------------------ */
+
+
+void SetSysClock_MSI(void);
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the PWR peripheral registers to their default reset values.
+ */
+void PWR_DeInit(void)
+{
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_PWR, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_PWR, DISABLE);
+}
+
+/**
+ * @brief Enables or disables access to the RTC and backup registers.
+ * @param Cmd new state of the access to the RTC and backup registers.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void PWR_BackupAccessEnable(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)CTRL_DBKP_BB = (uint32_t)Cmd;
+}
+/**
+ * @brief MR voltage selection.
+ * @param voltage value: 1.0V and 1.1V.
+ * This parameter can be: MR_1V0 or MR_1V1.
+ */
+void PWR_MRconfig(uint8_t voltage)
+{
+ uint32_t tmpreg = 0;
+
+ tmpreg = PWR->CTRL1;
+ /* Clear MRSEL bits */
+ tmpreg &= (~PWR_CTRL1_MRSELMASK);
+ /* Set voltage*/
+ tmpreg |= (uint32_t)(voltage << 9);
+ PWR->CTRL1 = tmpreg;
+}
+/**
+ * @brief Get MR voltage value.
+ * @param voltage value: 1.0V and 1.1V.
+ * @return The value of voltage.
+ */
+uint8_t GetMrVoltage(void)
+{
+ uint8_t tmp = 0;
+
+ tmp = (uint8_t)((PWR->CTRL1 >> 9) & 0x03);//2bits
+ return tmp ;
+}
+/**
+ * @brief Enables or disables the Power Voltage Detector(PVD).
+ * @param Cmd new state of the PVD.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void PWR_PvdEnable(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ //*(__IO uint32_t*)CTRL_PVDEN_BB = (uint32_t)Cmd; //Can not enable the PVD bit
+ PWR->CTRL2 |= Cmd;
+
+}
+
+/**
+ * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+ * @param PWR_PVDLevel: specifies the PVD detection level
+ * This parameter can be one of the following values:
+ * @arg PWR_CTRL2_PLS1: PVD detection level set to 2.1V
+ * @arg PWR_CTRL2_PLS2: PVD detection level set to 2.25V
+ * @arg PWR_CTRL2_PLS3: PVD detection level set to 2.4V
+ * @arg PWR_CTRL2_PLS4: PVD detection level set to 2.55V
+ * @arg PWR_CTRL2_PLS5: PVD detection level set to 2.7V
+ * @arg PWR_CTRL2_PLS6: PVD detection level set to 2.85V
+ * @arg PWR_CTRL2_PLS7: PVD detection level set to 2.95V
+ * @arg PWR_CTRL2_PLS8: external input analog voltage PVD_IN (compared internally to VREFINT)
+ * @retval None
+ */
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
+ tmpregister = PWR->CTRL2;
+ /* Clear PLS[7:5] bits */
+ tmpregister &= (~PWR_CTRL2_PLSMASK);
+ /* Set PRS[7:5] bits according to PWR_PVDLevel value */
+ tmpregister |= PWR_PVDLevel;
+ /* Store the new value */
+ PWR->CTRL2 = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the WakeUp Pin functionality.
+ * @param Pin: which PIN select to wakeup.
+ * This parameter can be one of the following values:
+ * @arg WAKEUP_PIN0
+ * @arg WAKEUP_PIN1
+ * @arg WAKEUP_PIN2
+ * @param Cmd new state of the WakeUp Pin functionality.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void PWR_WakeUpPinEnable(WAKEUP_PINX WKUP_Pin,FunctionalState Cmd)
+{
+ uint32_t Temp = 0;
+ Temp = PWR->CTRL3;
+ if (ENABLE==Cmd)
+ {
+ Temp &= (~(PWR_CTRL3_WKUP0EN|PWR_CTRL3_WKUP1EN|PWR_CTRL3_WKUP2EN));
+ Temp |= (WKUP_Pin);
+ PWR->CTRL3 = Temp;
+ }
+ else
+ {
+ Temp &= (~(WKUP_Pin));
+ PWR->CTRL3 = Temp;
+ }
+}
+
+/**
+ * @brief Enters SLEEP mode.
+ * @param SLEEPONEXIT: specifies the SLEEPONEXIT state in SLEEP mode.
+ * This parameter can be one of the following values:
+ * @arg 0: SLEEP mode with SLEEPONEXIT disable
+ * @arg 1: SLEEP mode with SLEEPONEXIT enable
+ * @param PWR_STOPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.
+ * This parameter can be one of the following values:
+ * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction
+ * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction
+ * @retval None
+ */
+void PWR_EnterSLEEPMode(uint8_t SLEEPONEXIT, uint8_t PWR_SLEEPEntry)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));
+
+ /* CLEAR SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
+
+ /* Select SLEEPONEXIT mode entry --------------------------------------------------*/
+ if (SLEEPONEXIT == 1)
+ {
+ /* the MCU enters Sleep mode as soon as it exits the lowest priority ISR */
+ SCB->SCR |= SCB_SCR_SLEEPONEXIT;
+ }
+ else if (SLEEPONEXIT == 0)
+ {
+ /* Sleep-now */
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPONEXIT);
+ }
+
+ /* Select SLEEP mode entry --------------------------------------------------*/
+ if (PWR_SLEEPEntry == PWR_SLEEPENTRY_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+}
+
+
+
+/**
+ * @brief Enters STOP2 mode.
+ * @param PWR_STOPEntry specifies if STOP2 mode in entered with WFI or WFE instruction.
+ * This parameter can be one of the following values:
+ * @arg PWR_STOPENTRY_WFI enter STOP2 mode with WFI instruction
+ * @arg PWR_STOPENTRY_WFE enter STOP2 mode with WFE instruction
+ * @param RetentionMode: PWR_CTRL3_RAM1RET or PWR_CTRL3_RAM2RET
+ */
+void PWR_EnterSTOP2Mode(uint8_t PWR_STOPEntry,uint32_t RetentionMode)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
+ /* Wait MR Voltage Adjust Complete */
+ while ((PWR->STS2 &0X2) != 2);
+ tmpreg = PWR->CTRL3;
+ /* Clear SRAMRET bits */
+ tmpreg &= (~PWR_CTRL3_RAMRETMASK);
+ /* Set SRAM1/2 select */
+ tmpreg |= RetentionMode;
+ PWR->CTRL3 = tmpreg;
+ /* Select the regulator state in STOP2 mode ---------------------------------*/
+ tmpreg = PWR->CTRL1;
+ /* Clear LPMS bits */
+ tmpreg &= (~PWR_CTRL1_LPMSELMASK);
+ /* Set stop2 mode select */
+ tmpreg |= PWR_CTRL1_STOP2;
+ /* Store the new value */
+ PWR->CTRL1 = tmpreg;
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP;
+
+ /* Select STOP mode entry --------------------------------------------------*/
+ if (PWR_STOPEntry == PWR_STOPENTRY_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
+}
+
+
+/**
+ * @brief Enters Low power run mode.
+ * @param
+ * @arg
+ * @arg
+ * @retval None
+ */
+void PWR_EnterLowPowerRunMode(void)
+{
+ uint32_t tmpreg = 0;
+
+ SetSysClock_MSI();
+ FLASH_SetLatency(FLASH_LATENCY_2); //Configure the Flash read latency to be grater than 2, so LVE/SE timing requirement is guaranteed
+ //config FLASH enter the low power voltage mode
+ FLASH->AC |= FLASH_AC_LVMEN;
+ while ((FLASH->AC & FLASH_AC_LVMF) != FLASH_AC_LVMF);
+ FLASH_SetLatency(FLASH_LATENCY_0); //Configure the latency of Flash read cycle to proper value which depends on the Flash read access time.
+
+ _SetLprunSramVoltage(0);
+ _SetBandGapMode(0);
+ _SetPvdBorMode(0);
+ /* Select the regulator state in LPRUN mode ---------------------------------*/
+ tmpreg = PWR->CTRL1;
+ /* Clear LPMS bits */
+ tmpreg &= (~PWR_CTRL1_LPMSELMASK);
+ /* Set lpr to run the main power domain*/
+ tmpreg |= PWR_CTRL1_LPREN;
+ /* Store the new value */
+ PWR->CTRL1 = tmpreg;
+ while ((PWR->STS2 &PWR_STS2_LPRUNF) != 0);//LPRCNT flag ready
+}
+
+/**
+ * @brief Enters Low power run mode.
+ * @param
+ * @arg
+ * @arg
+ * @retval None
+ */
+void PWR_ExitLowPowerRunMode(void)
+{
+ PWR->CTRL1 &= ~PWR_CTRL1_LPREN;
+ _SetLprunswitch(3);
+ while ((PWR->STS2 &PWR_STS2_MRF) != PWR_STS2_MRF);
+ while ((PWR->STS2 &PWR_STS2_LPRUNF) != PWR_STS2_LPRUNF);
+ FLASH_SetLatency(FLASH_LATENCY_2); //Configure the Flash read latency to be grater than 2, so LVE/SE timing requirement is guaranteed
+ FLASH->AC &= ~FLASH_AC_LVMEN; //clear LVMREQ
+ while ((FLASH->AC &FLASH_AC_LVMF) != 0); //wait LVE is deasserted by polling the LVMVLD bit
+
+ FLASH_SetLatency(FLASH_LATENCY_0); //Configure the latency of Flash read cycle to proper value which depends on the Flash read access time.
+ _SetLprunswitch(2);
+ while ((PWR->STS2 &0X2) != 0) // wait MF to be 0 first
+ {
+ }
+ while ((PWR->STS2 &0X2) != 2) // wait MF to be 1 then
+ {
+ }
+}
+
+/**
+ * @brief Enters LP_SLEEP mode.
+ * @param SLEEPONEXIT: specifies the SLEEPONEXIT state in SLEEP mode.
+ * This parameter can be one of the following values:
+ * @arg 0: SLEEP mode with SLEEPONEXIT disable
+ * @arg 1: SLEEP mode with SLEEPONEXIT enable
+ * @param PWR_STOPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.
+ * This parameter can be one of the following values:
+ * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction
+ * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction
+ * @retval None
+ */
+void PWR_EnterLowPowerSleepMode(uint8_t SLEEPONEXIT, uint8_t PWR_SLEEPEntry)
+{
+ PWR_EnterLowPowerRunMode();
+ PWR_EnterSLEEPMode(SLEEPONEXIT, PWR_SLEEPEntry);
+}
+
+ /**
+ * @brief Enters STANDBY mode.
+ * @param PWR_STANDBYEntry: specifies if STANDBY mode in entered with WFI or WFE instruction.
+ * This parameter can be one of the following values:
+ * @arg PWR_STANDBYEntry_WFI: enter STANDBY mode with WFI instruction
+ * @arg PWR_CTRL3_RAM2RET: SRAM2 whether to retention
+ * @retval None
+ */
+void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry,uint32_t Sam2Ret)
+{
+ uint32_t tmpreg;
+ /* Clear Wake-up flag */
+ PWR->STSCLR |= PWR_STSCLR_CLRWKUP0;
+ PWR->STSCLR |= PWR_STSCLR_CLRWKUP1;
+ PWR->STSCLR |= PWR_STSCLR_CLRWKUP2;
+ tmpreg = PWR->CTRL3;
+ /* Clear SRAMRET bits */
+ tmpreg &= (~PWR_CTRL3_RAMRETMASK);
+ /* Set SRAM1/2 select */
+ tmpreg |= Sam2Ret;
+ PWR->CTRL3 = tmpreg;
+
+ tmpreg = PWR->CTRL1;
+ /* Clear LPMS bits */
+ tmpreg &= (~PWR_CTRL1_LPMSELMASK);
+ /* Select STANDBY mode */
+ tmpreg |= PWR_CTRL1_STANDBY;
+ PWR->CTRL1 = tmpreg;
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP;
+/* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM )
+ __force_stores();
+#endif
+ /* Select STANDBY mode entry --------------------------------------------------*/
+ if (PWR_STANDBYEntry == PWR_STOPENTRY_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+}
+
+
+
+/**
+ * @brief Checks whether the specified PWR flag is set or not.
+ * @param PWR_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg PWR_WKUP0_FLAG/PWR_WKUP1_FLAG/PWR_WKUP2_FLAG: Wake Up flag
+ * @arg PWR_STBY_FLAG: StandBy flag
+ * @arg PWR_LPRUN_FLAG: low power work flag
+ * @arg PWR_MR_FLAG: MR work statue flag
+ * @arg PWR_PVDO_FLAG: PVD output flag
+ * @retval The new state of PWR_FLAG (SET or RESET).
+ */
+FlagStatus PWR_GetFlagStatus(uint8_t STS,uint32_t PWR_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
+ if (STS == 1)
+ {
+ if ((PWR->STS1 & PWR_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ }
+ else
+ {
+ if ((PWR->STS2 & PWR_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ }
+
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the PWR's pending flags.
+ * @param PWR_FLAG specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg PWR_WKUP1_FLAG/PWR_WKUP2_FLAG/PWR_WKUP3_FLAG: Wake Up flag
+ * @arg PWR_STBY_FLAG: StandBy flag
+ */
+void PWR_ClearFlag(uint32_t PWR_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
+
+ PWR->STSCLR |= PWR_FLAG ;
+}
+
+
+/**
+ * @brief set system clock with MSI.
+ * @param void.
+ */
+
+void SetSysClock_MSI(void)
+{
+ RCC_DeInit();
+
+ if (RESET == RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_MSIRD))
+ {
+ /* Enable MSI and Config Clock */
+ RCC_ConfigMsi(RCC_MSI_ENABLE, RCC_MSI_RANGE_4M);
+ /* Waits for MSI start-up */
+ while (SUCCESS != RCC_WaitMsiStable());
+ }
+
+ /* Enable Prefetch Buffer */
+ FLASH_PrefetchBufSet(FLASH_PrefetchBuf_EN);
+
+ /* Select MSI as system clock source */
+ RCC_ConfigSysclk(RCC_SYSCLK_SRC_MSI);
+
+ /* Wait till MSI is used as system clock source */
+ while (RCC_GetSysclkSrc() != 0x00)
+ {
+ }
+
+ /* Flash 0 wait state */
+ //FLASH_SetLatency(FLASH_LATENCY_0);
+
+ /* HCLK = SYSCLK */
+ RCC_ConfigHclk(RCC_SYSCLK_DIV1);
+
+ /* PCLK2 = HCLK */
+ RCC_ConfigPclk2(RCC_HCLK_DIV1);
+
+ /* PCLK1 = HCLK */
+ RCC_ConfigPclk1(RCC_HCLK_DIV1);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_rcc.c b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_rcc.c
new file mode 100644
index 0000000000..c93e00923e
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_rcc.c
@@ -0,0 +1,1943 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_rcc.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l40x_rcc.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RCC
+ * @brief RCC driver modules
+ * @{
+ */
+
+/** @addtogroup RCC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_Defines
+ * @{
+ */
+
+/* ------------ RCC registers bit address in the alias region ----------- */
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
+
+/* --- CTRL Register ---*/
+
+/* Alias word address of HSIEN bit */
+#define CTRL_OFFSET (RCC_OFFSET + 0x00)
+#define HSIEN_BITN 0x00
+#define CTRL_HSIEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (HSIEN_BITN * 4))
+
+/* Alias word address of PLLEN bit */
+#define PLLEN_BITN 0x18
+#define CTRL_PLLEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (PLLEN_BITN * 4))
+
+/* Alias word address of CLKSSEN bit */
+#define CLKSSEN_BITN 0x13
+#define CTRL_CLKSSEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (CLKSSEN_BITN * 4))
+
+/* --- CFG Register ---*/
+
+/* Alias word address of USBPRES bit */
+#define CFG_OFFSET (RCC_OFFSET + 0x04)
+
+#define USBPRES_BITN 0x16
+#define CFG_USBPRES_BB (PERIPH_BB_BASE + (CFG_OFFSET * 32) + (USBPRES_BITN * 4))
+
+#define USBPRE_Bit1Number 0x17
+#define CFGR_USBPRE_BB_BIT1 (PERIPH_BB_BASE + (CFG_OFFSET * 32) + (USBPRE_Bit1Number * 4))
+
+/* --- CLKINT Register ---*/
+
+#define CLKINT_OFFSET (RCC_OFFSET + 0x08)
+
+/* Alias word address of LSIRDIF bit */
+#define LSIRDIF_BITN 0x00
+#define CLKINT_LSIRDIF_BB (PERIPH_BB_BASE + (CLKINT_OFFSET * 32) + (LSIRDIF_BITN * 4))
+
+/* --- LDCTRL Register ---*/
+
+/* Alias word address of LSECLKSSEN bit */
+#define LSECLKSSEN_BITN 0x03
+#define LDCTRL_LSECLKSSEN_BB (PERIPH_BB_BASE + (LDCTRL_OFFSET * 32) + (LSECLKSSEN_BITN * 4))
+
+/* Alias word address of RTCEN bit */
+#define LDCTRL_OFFSET (RCC_OFFSET + 0x20)
+#define RTCEN_BITN 0x0F
+#define LDCTRL_RTCEN_BB (PERIPH_BB_BASE + (LDCTRL_OFFSET * 32) + (RTCEN_BITN * 4))
+
+/* Alias word address of LDSFTRST bit */
+#define LDSFTRST_BITN 0x10
+#define LDCTRL_LDSFTRST_BB (PERIPH_BB_BASE + (LDCTRL_OFFSET * 32) + (LDSFTRST_BITN * 4))
+
+/* --- CTRLSTS Register ---*/
+
+/* Alias word address of LSIEN bit */
+#define CTRLSTS_OFFSET (RCC_OFFSET + 0x24)
+#define LSIEN_BITNUMBER 0x00
+#define CTRLSTS_LSIEN_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (LSIEN_BITNUMBER * 4))
+
+/* Alias word address of MSIEN bit */
+#define MSIEN_BITNUMBER 0x02
+#define CTRLSTS_MSIEN_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (MSIEN_BITNUMBER * 4))
+
+/* ---------------------- RCC registers bit mask ------------------------ */
+
+/* CTRL register bit mask */
+#define CTRL_HSEBP_RESET ((uint32_t)0xFFFBFFFF)
+#define CTRL_HSEBP_SET ((uint32_t)0x00040000)
+#define CTRL_HSEEN_RESET ((uint32_t)0xFFFEFFFF)
+#define CTRL_HSEEN_SET ((uint32_t)0x00010000)
+#define CTRL_HSITRIM_MASK ((uint32_t)0xFFFFFF83)
+#define CTRL_HSIEN_RESET ((uint32_t)0xFFFFFFFE)
+#define CTRL_HSIEN_SET ((uint32_t)0x00000001)
+
+/* CTRLSTS register bit mask */
+#define CTRLSTS_MSITRIM_MASK ((uint32_t)0xFF807FFF)
+#define CTRLSTS_MSIEN_RESET ((uint32_t)0xFFFFFFFB)
+#define CTRLSTS_MSIEN_SET ((uint32_t)0x00000004)
+
+#define CTRLSTS_MSIRANGE_MASK ((uint32_t)0xFFFFFF8F)
+#define CTRLSTS_MSIRANGE_RESET ((uint32_t)0x00000060) /* 4MHz */
+
+/* CFG register bit mask */
+#define CFG_PLL_MASK ((uint32_t)0xF7C0FFFF)
+
+#define CFG_PLLMULFCT_MASK ((uint32_t)0x083C0000)
+#define CFG_PLLSRC_MASK ((uint32_t)0x00010000)
+#define CFG_PLLHSEPRES_MASK ((uint32_t)0x00020000)
+#define CFG_SCLKSTS_MASK ((uint32_t)0x0000000C)
+#define CFG_SCLKSW_MASK ((uint32_t)0xFFFFFFFC)
+#define CFG_AHBPRES_RESET_MASK ((uint32_t)0xFFFFFF0F)
+#define CFG_AHBPRES_SET_MASK ((uint32_t)0x000000F0)
+#define CFG_APB1PRES_RESET_MASK ((uint32_t)0xFFFFF8FF)
+#define CFG_APB1PRES_SET_MASK ((uint32_t)0x00000700)
+#define CFG_APB2PRES_RESET_MASK ((uint32_t)0xFFFFC7FF)
+#define CFG_APB2PRES_SET_MASK ((uint32_t)0x00003800)
+
+/* CFG2 register bit mask */
+#define CFG2_TIM18CLKSEL_SET_MASK ((uint32_t)0x20000000)
+#define CFG2_TIM18CLKSEL_RESET_MASK ((uint32_t)0xDFFFFFFF)
+#define CFG2_RNGCPRES_SET_MASK ((uint32_t)0x1F000000)
+#define CFG2_RNGCPRES_RESET_MASK ((uint32_t)0xE0FFFFFF)
+#define CFG2_ETHCLKSEL_SET_MASK ((uint32_t)0x00100000)
+#define CFG2_ETHCLKSEL_RESET_MASK ((uint32_t)0xFFEFFFFF)
+#define CFG2_ADC1MSEL_SET_MASK ((uint32_t)0x00020000)
+#define CFG2_ADC1MSEL_RESET_MASK ((uint32_t)0xFFFDFFFF)
+#define CFG2_ADC1MPRES_SET_MASK ((uint32_t)0x0001F000)
+#define CFG2_ADC1MPRES_RESET_MASK ((uint32_t)0xFFFE0FFF)
+#define CFG2_ADCPLLPRES_SET_MASK ((uint32_t)0x000001F0)
+#define CFG2_ADCPLLPRES_RESET_MASK ((uint32_t)0xFFFFFE0F)
+#define CFG2_ADCHPRES_SET_MASK ((uint32_t)0x0000000F)
+#define CFG2_ADCHPRES_RESET_MASK ((uint32_t)0xFFFFFFF0)
+
+/* CFG3 register bit mask */
+#define CFGR3_TRNG1MSEL_SET_MASK ((uint32_t)0x00020000)
+#define CFGR3_TRNG1MSEL_RESET_MASK ((uint32_t)0xFFFDFFFF)
+#define CFGR3_TRNG1MPRES_SET_MASK ((uint32_t)0x0000F800)
+#define CFGR3_TRNG1MPRES_RESET_MASK ((uint32_t)0xFFFF07FF)
+
+/* CTRLSTS register bit mask */
+#define CSR_RMRSTF_SET ((uint32_t)0x01000000)
+#define CSR_RMVF_Reset ((uint32_t)0xfeffffff)
+
+/* RCC Flag Mask */
+#define FLAG_MASK ((uint8_t)0x1F)
+
+/* CLKINT register(Bits[31:0]) base address */
+#define CLKINT_ADDR ((uint32_t)0x40021008)
+
+/* LDCTRL register base address */
+#define LDCTRL_ADDR (PERIPH_BASE + LDCTRL_OFFSET)
+
+/* RDCTRL register bit mask */
+#define RDCTRL_LPTIMCLKSEL_MASK ((uint32_t)0x00000007)
+#define RDCTRL_LPUARTCLKSEL_MASK ((uint32_t)0x00000018)
+
+/* PLLHSIPRE register bit mask */
+#define PLLHSIPRE_PLLHSI_PRE_MASK ((uint32_t)0x00000001)
+#define PLLHSIPRE_PLLSRCDIV_MASK ((uint32_t)0x00000002)
+
+#define LSE_TRIMR_ADDR ((uint32_t)0x40001808)
+
+#define LSE_GM_MASK_VALUE (0x1FF)
+#define LSE_GM_MAX_VALUE (0x1FF)
+#define LSE_GM_DEFAULT_VALUE (0x1FF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_Variables
+ * @{
+ */
+
+static const uint8_t s_ApbAhbPresTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+static const uint8_t s_AdcHclkPresTable[16] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 32, 32, 32, 32, 32, 32, 32};
+static const uint16_t s_AdcPllClkPresTable[16] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256, 256, 256, 256, 256};
+static const uint32_t s_msiClockTable[7] = {MSI_VALUE_L0, MSI_VALUE_L1, MSI_VALUE_L2, MSI_VALUE_L3,
+ MSI_VALUE_L4, MSI_VALUE_L5, MSI_VALUE_L6};
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Resets the RCC clock configuration to the default reset state.
+ */
+void RCC_DeInit(void)
+{
+ /* Set MSIEN bit */
+ RCC->CTRLSTS |= (uint32_t)0x00000004;
+
+ /* Reset SW, HPRE, PPRE1, PPRE2 and MCO bits */
+ RCC->CFG &= (uint32_t)0xF8FFC000;
+
+ /* Reset HSIEN, HSEEN, CLKSSEN and PLLEN bits */
+ RCC->CTRL &= (uint32_t)0xFEF6FFFE;
+
+ /* Reset HSEBYP bit */
+ RCC->CTRL &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRES bits */
+ RCC->CFG &= (uint32_t)0xF700FFFF;
+
+ /* Reset CFG2 register */
+ RCC->CFG2 = 0x00007000;
+
+ /* Reset CFG3 register */
+ RCC->CFG3 = 0x00003800;
+
+ /* Reset RDCTRL register */
+ RCC->RDCTRL = 0x00000000;
+
+ /* Reset PLLHSIPRE register */
+ RCC->PLLHSIPRE = 0x00000000;
+
+ /* Disable all interrupts and clear pending bits */
+ RCC->CLKINT = 0x04BF8000;
+}
+
+/**
+ * @brief Configures the External High Speed oscillator (HSE).
+ * @note HSE can not be stopped if it is used directly or through the PLL as system clock.
+ * @param RCC_HSE specifies the new state of the HSE.
+ * This parameter can be one of the following values:
+ * @arg RCC_HSE_DISABLE HSE oscillator OFF
+ * @arg RCC_HSE_ENABLE HSE oscillator ON
+ * @arg RCC_HSE_BYPASS HSE oscillator bypassed with external clock
+ */
+void RCC_ConfigHse(uint32_t RCC_HSE)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_HSE(RCC_HSE));
+ /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
+ /* Reset HSEON bit */
+ RCC->CTRL &= CTRL_HSEEN_RESET;
+ /* Reset HSEBYP bit */
+ RCC->CTRL &= CTRL_HSEBP_RESET;
+ /* Configure HSE (RCC_HSE_DISABLE is already covered by the code section above) */
+ switch (RCC_HSE)
+ {
+ case RCC_HSE_ENABLE:
+ /* Set HSEEN bit */
+ RCC->CTRL |= CTRL_HSEEN_SET;
+ break;
+
+ case RCC_HSE_BYPASS:
+ /* Set HSEBYP and HSEEN bits */
+ RCC->CTRL |= CTRL_HSEBP_SET | CTRL_HSEEN_SET;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Waits for HSE start-up.
+ * @return An ErrorStatus enumuration value:
+ * - SUCCESS: HSE oscillator is stable and ready to use
+ * - ERROR: HSE oscillator not yet ready
+ */
+ErrorStatus RCC_WaitHseStable(void)
+{
+ __IO uint32_t StartUpCounter = 0;
+ ErrorStatus status = ERROR;
+ FlagStatus HSEStatus = RESET;
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC_GetFlagStatus(RCC_CTRL_FLAG_HSERDF);
+ StartUpCounter++;
+ } while ((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
+
+ if (RCC_GetFlagStatus(RCC_CTRL_FLAG_HSERDF) != RESET)
+ {
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+ return (status);
+}
+
+/**
+ * @brief Configures the Internal High Speed oscillator (HSI).
+ * @note HSI can not be stopped if it is used directly or through the PLL as system clock.
+ * @param RCC_HSI specifies the new state of the HSI.
+ * This parameter can be one of the following values:
+ * @arg RCC_HSI_DISABLE HSI oscillator OFF
+ * @arg RCC_HSI_ENABLE HSI oscillator ON
+ */
+void RCC_ConfigHsi(uint32_t RCC_HSI)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_HSI(RCC_HSI));
+ /* Reset HSIEN bit */
+ RCC->CTRL &= CTRL_HSIEN_RESET;
+ /* Configure HSI */
+ switch (RCC_HSI)
+ {
+ case RCC_HSI_ENABLE:
+ /* Set HSIEN bit */
+ RCC->CTRL |= CTRL_HSIEN_SET;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Waits for HSI start-up.
+ * @return An ErrorStatus enumuration value:
+ * - SUCCESS: HSI oscillator is stable and ready to use
+ * - ERROR: HSI oscillator not yet ready
+ */
+ErrorStatus RCC_WaitHsiStable(void)
+{
+ __IO uint32_t StartUpCounter = 0;
+ ErrorStatus status = ERROR;
+ FlagStatus HSIStatus = RESET;
+
+ /* Wait till HSI is ready and if Time out is reached exit */
+ do
+ {
+ HSIStatus = RCC_GetFlagStatus(RCC_CTRL_FLAG_HSIRDF);
+ StartUpCounter++;
+ } while ((StartUpCounter != HSI_STARTUP_TIMEOUT) && (HSIStatus == RESET));
+
+ if (RCC_GetFlagStatus(RCC_CTRL_FLAG_HSIRDF) != RESET)
+ {
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+ return (status);
+}
+
+/**
+ * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
+ * @param HSICalibrationValue specifies the calibration trimming value.
+ * This parameter must be a number between 0 and 0x1F.
+ */
+void RCC_SetHsiCalibValue(uint8_t HSICalibrationValue)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_CALIB_VALUE(HSICalibrationValue));
+ tmpregister = RCC->CTRL;
+ /* Clear HSITRIM[4:0] bits */
+ tmpregister &= CTRL_HSITRIM_MASK;
+ /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
+ tmpregister |= (uint32_t)HSICalibrationValue << 2;
+ /* Store the new value */
+ RCC->CTRL = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the Internal High Speed oscillator (HSI).
+ * @note HSI can not be stopped if it is used directly or through the PLL as system clock.
+ * @param Cmd new state of the HSI. This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableHsi(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)CTRL_HSIEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Configures the Multi Speed oscillator (MSI).
+ * @param RCC_MSI specifies the new state of the MSI.
+ * This parameter can be one of the following values:
+ * @arg RCC_MSI_DISABLE MSI oscillator OFF
+ * @arg RCC_MSI_ENABLE MSI oscillator ON
+ * @param RCC_MSI_Range specifies the clock of the MSI.
+ * This parameter can be one of the following values:
+ * @arg RCC_MSI_RANGE_100K 100KHz
+ * @arg RCC_MSI_RANGE_200K 200KHz
+ * @arg RCC_MSI_RANGE_400K 400KHz
+ * @arg RCC_MSI_RANGE_800K 800KHz
+ * @arg RCC_MSI_RANGE_1M 1MHz
+ * @arg RCC_MSI_RANGE_2M 2MHz
+ * @arg RCC_MSI_RANGE_4M 4MHz
+ */
+void RCC_ConfigMsi(uint32_t RCC_MSI, uint32_t RCC_MSI_Range)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_MSI(RCC_MSI));
+ assert_param(IS_RCC_MSI_RANGE(RCC_MSI_Range));
+ /* Set MSIRANGE[2:0] bit */
+ RCC->CTRLSTS &= CTRLSTS_MSIRANGE_MASK;
+ RCC->CTRLSTS |= RCC_MSI_Range;
+ /* Configure MSI */
+ switch (RCC_MSI)
+ {
+ case RCC_MSI_ENABLE:
+ /* Set MSIEN bit */
+ RCC->CTRLSTS |= CTRLSTS_MSIEN_SET;
+ break;
+ case RCC_MSI_DISABLE:
+ /* Reset MSIEN bit */
+ RCC->CTRLSTS &= CTRLSTS_MSIEN_RESET;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Waits for MSI start-up.
+ * @return An ErrorStatus enumuration value:
+ * - SUCCESS: MSI oscillator is stable and ready to use
+ * - ERROR: MSI oscillator not yet ready
+ */
+ErrorStatus RCC_WaitMsiStable(void)
+{
+ __IO uint32_t StartUpCounter = 0;
+ ErrorStatus status = ERROR;
+ FlagStatus MSIStatus = RESET;
+
+ /* Wait till MSI is ready and if Time out is reached exit */
+ do
+ {
+ MSIStatus = RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_MSIRD);
+ StartUpCounter++;
+ } while ((StartUpCounter != MSI_STARTUP_TIMEOUT) && (MSIStatus == RESET));
+
+ if (RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_MSIRD) != RESET)
+ {
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+ return (status);
+}
+
+/**
+ * @brief Adjusts the Multi Speed oscillator (MSI) calibration value.
+ * @param MSICalibrationValue specifies the calibration trimming value.
+ * This parameter must be a number between 0 and 0xFF.
+ */
+void RCC_SetMsiCalibValue(uint8_t MSICalibrationValue)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ //assert_param(IS_RCC_MSICALIB_VALUE(MSICalibrationValue));
+ tmpregister = RCC->CTRLSTS;
+ /* Clear MSITRIM[7:0] bits */
+ tmpregister &= CTRLSTS_MSITRIM_MASK;
+ /* Set the MSITRIM[7:0] bits according to MSICalibrationValue value */
+ tmpregister |= (uint32_t)MSICalibrationValue << 15;
+ /* Store the new value */
+ RCC->CTRLSTS = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the Multi Speed oscillator (MSI).
+ * @param Cmd new state of the MSI. This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableMsi(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)CTRLSTS_MSIEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Configures the PLL clock source and multiplication factor.
+ * @note This function must be used only when the PLL is disabled.
+ * @param RCC_PLLSource specifies the PLL entry clock source.
+ * this parameter can be one of the following values:
+ * @arg RCC_PLL_HSI_PRE_DIV1 HSI oscillator clock selected as PLL clock entry
+ * @arg RCC_PLL_HSI_PRE_DIV2 HSI oscillator clock divided by 2 selected as PLL clock entry
+ * @arg RCC_PLL_SRC_HSE_DIV1 HSE oscillator clock selected as PLL clock entry
+ * @arg RCC_PLL_SRC_HSE_DIV2 HSE oscillator clock divided by 2 selected as PLL clock entry
+ * @param RCC_PLLMul specifies the PLL multiplication factor.
+ * this parameter can be RCC_PLLMul_x where x:[2,32]
+ * @param RCC_PLLDIVCLK specifies the PLL divider feedback clock source.
+ * this parameter can be one of the following values:
+ * @arg RCC_PLLDIVCLK_DISABLE PLLSource clock selected as PLL clock entry
+ * @arg RCC_PLLDIVCLK_ENABLE PLLSource clock divided by 2 selected as PLL clock entry
+ */
+void RCC_ConfigPll(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul, uint32_t RCC_PLLDIVCLK)
+{
+ uint32_t tmpregister = 0;
+ uint32_t pllhsipreregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL_SRC(RCC_PLLSource));
+ assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
+ assert_param(IS_RCC_PLL_DIVCLK(RCC_PLLDIVCLK));
+
+ tmpregister = RCC->CFG;
+ pllhsipreregister = RCC->PLLHSIPRE;
+ /* Clear PLLSRC, PLLXTPRE and PLLMUL[4:0] bits */
+ tmpregister &= CFG_PLL_MASK;
+ /* Clear PLLHSIPRE, PLLSRCDIV bits */
+ pllhsipreregister &= (~(PLLHSIPRE_PLLHSI_PRE_MASK | PLLHSIPRE_PLLSRCDIV_MASK));
+ /* Set the PLL configuration bits */
+ if ((RCC_PLLSource == RCC_PLL_HSI_PRE_DIV1) || (RCC_PLLSource == RCC_PLL_HSI_PRE_DIV2))
+ {
+ tmpregister |= RCC_PLLMul;
+ pllhsipreregister |= RCC_PLLSource | RCC_PLLDIVCLK;
+ }
+ /* (RCC_PLLSource == RCC_PLL_SRC_HSE_DIV1) || (RCC_PLLSource == RCC_PLL_SRC_HSE_DIV2) */
+ else
+ {
+ tmpregister |= RCC_PLLSource | RCC_PLLMul;
+ pllhsipreregister |= RCC_PLLDIVCLK;
+ }
+ /* Store the new value */
+ RCC->CFG = tmpregister;
+ RCC->PLLHSIPRE = pllhsipreregister;
+}
+
+/**
+ * @brief Enables or disables the PLL.
+ * @note The PLL can not be disabled if it is used as system clock.
+ * @param Cmd new state of the PLL. This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnablePll(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ *(__IO uint32_t*)CTRL_PLLEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Configures the system clock (SYSCLK).
+ * @param RCC_SYSCLKSource specifies the clock source used as system clock.
+ * This parameter can be one of the following values:
+ * @arg RCC_SYSCLK_SRC_MSI HSI selected as system clock
+ * @arg RCC_SYSCLK_SRC_HSI HSI selected as system clock
+ * @arg RCC_SYSCLK_SRC_HSE HSE selected as system clock
+ * @arg RCC_SYSCLK_SRC_PLLCLK PLL selected as system clock
+ */
+void RCC_ConfigSysclk(uint32_t RCC_SYSCLKSource)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_SYSCLK_SRC(RCC_SYSCLKSource));
+ tmpregister = RCC->CFG;
+ /* Clear SW[1:0] bits */
+ tmpregister &= CFG_SCLKSW_MASK;
+ /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
+ tmpregister |= RCC_SYSCLKSource;
+ /* Store the new value */
+ RCC->CFG = tmpregister;
+}
+
+/**
+ * @brief Returns the clock source used as system clock.
+ * @return The clock source used as system clock. The returned value can
+ * be one of the following:
+ * - 0x00: MSI used as system clock
+ * - 0x04: HSI used as system clock
+ * - 0x08: HSE used as system clock
+ * - 0x0C: PLL used as system clock
+ */
+uint8_t RCC_GetSysclkSrc(void)
+{
+ return ((uint8_t)(RCC->CFG & CFG_SCLKSTS_MASK));
+}
+
+/**
+ * @brief Configures the AHB clock (HCLK).
+ * @param RCC_SYSCLK defines the AHB clock divider. This clock is derived from
+ * the system clock (SYSCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_SYSCLK_DIV1 AHB clock = SYSCLK
+ * @arg RCC_SYSCLK_DIV2 AHB clock = SYSCLK/2
+ * @arg RCC_SYSCLK_DIV4 AHB clock = SYSCLK/4
+ * @arg RCC_SYSCLK_DIV8 AHB clock = SYSCLK/8
+ * @arg RCC_SYSCLK_DIV16 AHB clock = SYSCLK/16
+ * @arg RCC_SYSCLK_DIV64 AHB clock = SYSCLK/64
+ * @arg RCC_SYSCLK_DIV128 AHB clock = SYSCLK/128
+ * @arg RCC_SYSCLK_DIV256 AHB clock = SYSCLK/256
+ * @arg RCC_SYSCLK_DIV512 AHB clock = SYSCLK/512
+ */
+void RCC_ConfigHclk(uint32_t RCC_SYSCLK)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_SYSCLK_DIV(RCC_SYSCLK));
+ tmpregister = RCC->CFG;
+ /* Clear HPRE[3:0] bits */
+ tmpregister &= CFG_AHBPRES_RESET_MASK;
+ /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
+ tmpregister |= RCC_SYSCLK;
+ /* Store the new value */
+ RCC->CFG = tmpregister;
+}
+
+/**
+ * @brief Configures the Low Speed APB clock (PCLK1).
+ * @param RCC_HCLK defines the APB1 clock divider. This clock is derived from
+ * the AHB clock (HCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_HCLK_DIV1 APB1 clock = HCLK
+ * @arg RCC_HCLK_DIV2 APB1 clock = HCLK/2
+ * @arg RCC_HCLK_DIV4 APB1 clock = HCLK/4
+ * @arg RCC_HCLK_DIV8 APB1 clock = HCLK/8
+ * @arg RCC_HCLK_DIV16 APB1 clock = HCLK/16
+ */
+void RCC_ConfigPclk1(uint32_t RCC_HCLK)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_HCLK_DIV(RCC_HCLK));
+ tmpregister = RCC->CFG;
+ /* Clear PPRE1[2:0] bits */
+ tmpregister &= CFG_APB1PRES_RESET_MASK;
+ /* Set PPRE1[2:0] bits according to RCC_HCLK value */
+ tmpregister |= RCC_HCLK;
+ /* Store the new value */
+ RCC->CFG = tmpregister;
+}
+
+/**
+ * @brief Configures the High Speed APB clock (PCLK2).
+ * @param RCC_HCLK defines the APB2 clock divider. This clock is derived from
+ * the AHB clock (HCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_HCLK_DIV1 APB2 clock = HCLK
+ * @arg RCC_HCLK_DIV2 APB2 clock = HCLK/2
+ * @arg RCC_HCLK_DIV4 APB2 clock = HCLK/4
+ * @arg RCC_HCLK_DIV8 APB2 clock = HCLK/8
+ * @arg RCC_HCLK_DIV16 APB2 clock = HCLK/16
+ */
+void RCC_ConfigPclk2(uint32_t RCC_HCLK)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_HCLK_DIV(RCC_HCLK));
+ tmpregister = RCC->CFG;
+ /* Clear PPRE2[2:0] bits */
+ tmpregister &= CFG_APB2PRES_RESET_MASK;
+ /* Set PPRE2[2:0] bits according to RCC_HCLK value */
+ tmpregister |= RCC_HCLK << 3;
+ /* Store the new value */
+ RCC->CFG = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the specified RCC interrupts.
+ * @param RccInt specifies the RCC interrupt sources to be enabled or disabled.
+ *
+ * this parameter can be any combination of the following values
+ * @arg RCC_INT_LSIRDIF LSI ready interrupt
+ * @arg RCC_INT_LSERDIF LSE ready interrupt
+ * @arg RCC_INT_HSIRDIF HSI ready interrupt
+ * @arg RCC_INT_HSERDIF HSE ready interrupt
+ * @arg RCC_INT_PLLRDIF PLL ready interrupt
+ * @arg RCC_INT_BORIF BOR interrupt
+ * @arg RCC_INT_MSIRDIF MSI ready interrupt
+ *
+ * @param Cmd new state of the specified RCC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_ConfigInt(uint8_t RccInt, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_INT(RccInt));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Perform Byte access to RCC_CLKINT bits to enable the selected interrupts */
+ *(__IO uint32_t*)CLKINT_ADDR |= (((uint32_t)RccInt) << 8);
+ }
+ else
+ {
+ /* Perform Byte access to RCC_CLKINT bits to disable the selected interrupts */
+ *(__IO uint32_t*)CLKINT_ADDR &= (~(((uint32_t)RccInt) << 8));
+ }
+}
+
+/**
+ * @brief Configures the USB clock (USBCLK).
+ * @param RCC_USBCLKSource specifies the USB clock source. This clock is
+ * derived from the PLL output.
+ * This parameter can be one of the following values:
+ * @arg RCC_USBCLK_SRC_PLLCLK_DIV1_5 PLL clock divided by 1,5 selected as USB clock source
+ * @arg RCC_USBCLK_SRC_PLLCLK_DIV1 PLL clock divided by 1 selected as USB clock source
+ * @arg RCC_USBCLK_SRC_PLLCLK_DIV2 PLL clock divided by 2 selected as USB clock source
+ * @arg RCC_USBCLK_SRC_PLLCLK_DIV3 PLL clock divided by 3 selected as USB clock source
+ */
+void RCC_ConfigUsbClk(uint32_t RCC_USBCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_USBCLK_SRC(RCC_USBCLKSource));
+
+ *(__IO uint32_t*)CFG_USBPRES_BB = RCC_USBCLKSource;
+ *(__IO uint32_t*)CFGR_USBPRE_BB_BIT1 = RCC_USBCLKSource >> 1;
+}
+
+/**
+ * @brief Configures the TIM1/8 clock (TIM1/8CLK).
+ * @param RCC_TIM18CLKSource specifies the TIM1/8 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_TIM18CLK_SRC_TIM18CLK
+ * @arg RCC_TIM18CLK_SRC_SYSCLK
+ */
+void RCC_ConfigTim18Clk(uint32_t RCC_TIM18CLKSource)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_TIM18CLKSRC(RCC_TIM18CLKSource));
+
+ tmpregister = RCC->CFG2;
+ /* Clear TIMCLK_SEL bits */
+ tmpregister &= CFG2_TIM18CLKSEL_RESET_MASK;
+ /* Set TIMCLK_SEL bits according to RCC_TIM18CLKSource value */
+ tmpregister |= RCC_TIM18CLKSource;
+
+ /* Store the new value */
+ RCC->CFG2 = tmpregister;
+}
+
+/**
+ * @brief Configures the RNGCCLK prescaler.
+ * @param RCC_RNGCCLKPrescaler specifies the RNGCCLK prescaler.
+ * This parameter can be one of the following values:
+ * @arg RCC_RNGCCLK_SYSCLK_DIV1 RNGCPRE[24:28] = 00000, SYSCLK Divided By 1
+ * @arg RCC_RNGCCLK_SYSCLK_DIV2 RNGCPRE[24:28] = 00001, SYSCLK Divided By 2
+ * @arg RCC_RNGCCLK_SYSCLK_DIV3 RNGCPRE[24:28] = 00002, SYSCLK Divided By 3
+ * ...
+ * @arg RCC_RNGCCLK_SYSCLK_DIV31 RNGCPRE[24:28] = 11110, SYSCLK Divided By 31
+ * @arg RCC_RNGCCLK_SYSCLK_DIV32 RNGCPRE[24:28] = 11111, SYSCLK Divided By 32
+ */
+void RCC_ConfigRngcClk(uint32_t RCC_RNGCCLKPrescaler)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_RNGCCLKPRE(RCC_RNGCCLKPrescaler));
+
+ tmpregister = RCC->CFG2;
+ /* Clear RNGCPRE[3:0] bits */
+ tmpregister &= CFG2_RNGCPRES_RESET_MASK;
+ /* Set RNGCPRE[3:0] bits according to RCC_RNGCCLKPrescaler value */
+ tmpregister |= RCC_RNGCCLKPrescaler;
+
+ /* Store the new value */
+ RCC->CFG2 = tmpregister;
+}
+
+/**
+ * @brief Configures the ADCx 1M clock (ADC1MCLK).
+ * @param RCC_ADC1MCLKSource specifies the ADC1M clock source.
+ * This parameter can be on of the following values:
+ * @arg RCC_ADC1MCLK_SRC_HSI
+ * @arg RCC_ADC1MCLK_SRC_HSE
+ *
+ * @param RCC_ADC1MPrescaler specifies the ADC1M clock prescaler.
+ * This parameter can be on of the following values:
+ * @arg RCC_ADC1MCLK_DIV1 ADC1M clock = RCC_ADC1MCLKSource_xxx/1
+ * @arg RCC_ADC1MCLK_DIV2 ADC1M clock = RCC_ADC1MCLKSource_xxx/2
+ * @arg RCC_ADC1MCLK_DIV3 ADC1M clock = RCC_ADC1MCLKSource_xxx/3
+ * ...
+ * @arg RCC_ADC1MCLK_DIV31 ADC1M clock = RCC_ADC1MCLKSource_xxx/31
+ * @arg RCC_ADC1MCLK_DIV32 ADC1M clock = RCC_ADC1MCLKSource_xxx/32
+ */
+void RCC_ConfigAdc1mClk(uint32_t RCC_ADC1MCLKSource, uint32_t RCC_ADC1MPrescaler)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_ADC1MCLKSRC(RCC_ADC1MCLKSource));
+ assert_param(IS_RCC_ADC1MCLKPRE(RCC_ADC1MPrescaler));
+
+ tmpregister = RCC->CFG2;
+ /* Clear ADC1MSEL and ADC1MPRE[4:0] bits */
+ tmpregister &= CFG2_ADC1MSEL_RESET_MASK;
+ tmpregister &= CFG2_ADC1MPRES_RESET_MASK;
+ /* Set ADC1MSEL bits according to RCC_ADC1MCLKSource value */
+ tmpregister |= RCC_ADC1MCLKSource;
+ /* Set ADC1MPRE[4:0] bits according to RCC_ADC1MPrescaler value */
+ tmpregister |= RCC_ADC1MPrescaler;
+
+ /* Store the new value */
+ RCC->CFG2 = tmpregister;
+}
+
+/**
+ * @brief Configures the ADCPLLCLK prescaler, and enable/disable ADCPLLCLK.
+ * @param RCC_ADCPLLCLKPrescaler specifies the ADCPLLCLK prescaler.
+ * This parameter can be on of the following values:
+ * @arg RCC_ADCPLLCLK_DIV1 ADCPLLCLKPRES[4:0] = 10000, Pll Clock Divided By 1
+ * @arg RCC_ADCPLLCLK_DIV2 ADCPLLCLKPRES[4:0] = 10001, Pll Clock Divided By 2
+ * @arg RCC_ADCPLLCLK_DIV4 ADCPLLCLKPRES[4:0] = 10010, Pll Clock Divided By 4
+ * @arg RCC_ADCPLLCLK_DIV6 ADCPLLCLKPRES[4:0] = 10011, Pll Clock Divided By 6
+ * @arg RCC_ADCPLLCLK_DIV8 ADCPLLCLKPRES[4:0] = 10100, Pll Clock Divided By 8
+ * @arg RCC_ADCPLLCLK_DIV10 ADCPLLCLKPRES[4:0] = 10101, Pll Clock Divided By 10
+ * @arg RCC_ADCPLLCLK_DIV12 ADCPLLCLKPRES[4:0] = 10110, Pll Clock Divided By 12
+ * @arg RCC_ADCPLLCLK_DIV16 ADCPLLCLKPRES[4:0] = 10111, Pll Clock Divided By 16
+ * @arg RCC_ADCPLLCLK_DIV32 ADCPLLCLKPRES[4:0] = 11000, Pll Clock Divided By 32
+ * @arg RCC_ADCPLLCLK_DIV64 ADCPLLCLKPRES[4:0] = 11001, Pll Clock Divided By 64
+ * @arg RCC_ADCPLLCLK_DIV128 ADCPLLCLKPRES[4:0] = 11010, Pll Clock Divided By 128
+ * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = 11011, Pll Clock Divided By 256
+ * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = others, Pll Clock Divided By 256
+ *
+ * @param Cmd specifies the ADCPLLCLK enable/disable selection.
+ * This parameter can be on of the following values:
+ * @arg ENABLE enable ADCPLLCLK
+ * @arg DISABLE disable ADCPLLCLK ADCPLLCLKPRES[4:0] = 0xxxx, ADC Pll Clock Disable
+ */
+void RCC_ConfigAdcPllClk(uint32_t RCC_ADCPLLCLKPrescaler, FunctionalState Cmd)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_ADCPLLCLKPRE(RCC_ADCPLLCLKPrescaler));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ tmpregister = RCC->CFG2;
+ /* Clear ADCPLLPRES[4:0] bits */
+ tmpregister &= CFG2_ADCPLLPRES_RESET_MASK;
+
+ if (Cmd != DISABLE)
+ {
+ tmpregister |= RCC_ADCPLLCLKPrescaler;
+ }
+ else
+ {
+ tmpregister |= RCC_ADCPLLCLKPrescaler;
+ tmpregister &= RCC_ADCPLLCLK_DISABLE;
+ }
+
+ /* Store the new value */
+ RCC->CFG2 = tmpregister;
+}
+
+/**
+ * @brief Configures the ADCHCLK prescaler.
+ * @param RCC_ADCHCLKPrescaler specifies the ADCHCLK prescaler.
+ * This parameter can be on of the following values:
+ * @arg RCC_ADCHCLK_DIV1 ADCHCLKPRE[3:0] = 0000, HCLK Clock Divided By 1
+ * @arg RCC_ADCHCLK_DIV2 ADCHCLKPRE[3:0] = 0001, HCLK Clock Divided By 2
+ * @arg RCC_ADCHCLK_DIV4 ADCHCLKPRE[3:0] = 0010, HCLK Clock Divided By 4
+ * @arg RCC_ADCHCLK_DIV6 ADCHCLKPRE[3:0] = 0011, HCLK Clock Divided By 6
+ * @arg RCC_ADCHCLK_DIV8 ADCHCLKPRE[3:0] = 0100, HCLK Clock Divided By 8
+ * @arg RCC_ADCHCLK_DIV10 ADCHCLKPRE[3:0] = 0101, HCLK Clock Divided By 10
+ * @arg RCC_ADCHCLK_DIV12 ADCHCLKPRE[3:0] = 0110, HCLK Clock Divided By 12
+ * @arg RCC_ADCHCLK_DIV16 ADCHCLKPRE[3:0] = 0111, HCLK Clock Divided By 16
+ * @arg RCC_ADCHCLK_DIV32 ADCHCLKPRE[3:0] = 1000, HCLK Clock Divided By 32
+ * @arg RCC_ADCHCLK_DIV_OTHERS ADCHCLKPRE[3:0] = others, HCLK Clock Divided By 32
+ */
+void RCC_ConfigAdcHclk(uint32_t RCC_ADCHCLKPrescaler)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_ADCHCLKPRE(RCC_ADCHCLKPrescaler));
+
+ tmpregister = RCC->CFG2;
+ /* Clear ADCHPRE[3:0] bits */
+ tmpregister &= CFG2_ADCHPRES_RESET_MASK;
+ /* Set ADCHPRE[3:0] bits according to RCC_ADCHCLKPrescaler value */
+ tmpregister |= RCC_ADCHCLKPrescaler;
+
+ /* Store the new value */
+ RCC->CFG2 = tmpregister;
+}
+
+/**
+ * @brief Configures the TRNG 1M clock (TRNG1MCLK).
+ * @param RCC_TRNG1MCLKSource specifies the TRNG1M clock source.
+ * This parameter can be on of the following values:
+ * @arg RCC_TRNG1MCLK_SRC_HSI
+ * @arg RCC_TRNG1MCLK_SRC_HSE
+ *
+ * @param RCC_TRNG1MPrescaler specifies the TRNG1M prescaler.
+ * This parameter can be on of the following values:
+ * @arg RCC_TRNG1MCLK_DIV2 TRNG1M clock = RCC_TRNG1MCLK_SRC_HSE/2
+ * @arg RCC_TRNG1MCLK_DIV4 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/4
+ * @arg RCC_TRNG1MCLK_DIV6 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/6
+ * ...
+ * @arg RCC_TRNG1MCLK_DIV60 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/60
+ * @arg RCC_TRNG1MCLK_DIV62 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/62
+ */
+void RCC_ConfigTrng1mClk(uint32_t RCC_TRNG1MCLKSource, uint32_t RCC_TRNG1MPrescaler)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_TRNG1MCLK_SRC(RCC_TRNG1MCLKSource));
+ assert_param(IS_RCC_TRNG1MCLKPRE(RCC_TRNG1MPrescaler));
+
+ tmpregister = RCC->CFG3;
+ /* Clear TRNG1MSEL and TRNG1MPRE[4:0] bits */
+ tmpregister &= CFGR3_TRNG1MSEL_RESET_MASK;
+ tmpregister &= CFGR3_TRNG1MPRES_RESET_MASK;
+ /* Set TRNG1MSEL bits according to RCC_TRNG1MCLKSource value */
+ tmpregister |= RCC_TRNG1MCLKSource;
+ /* Set TRNG1MPRE[4:0] bits according to RCC_TRNG1MPrescaler value */
+ tmpregister |= RCC_TRNG1MPrescaler;
+
+ /* Store the new value */
+ RCC->CFG3 = tmpregister;
+}
+
+/**
+ * @brief Enable/disable TRNG clock (TRNGCLK).
+ * @param Cmd specifies the TRNGCLK enable/disable selection.
+ * This parameter can be on of the following values:
+ * @arg ENABLE enable TRNGCLK
+ * @arg DISABLE disable TRNGCLK
+ */
+void RCC_EnableTrng1mClk(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ RCC->CFG3 |= RCC_TRNG1MCLK_ENABLE;
+ }
+ else
+ {
+ RCC->CFG3 &= RCC_TRNG1MCLK_DISABLE;
+ }
+}
+
+/**
+ * @brief Configures the UCDR clock.
+ * @param RCC_UCDR300MSource specifies the UCDR clock source.
+ * This parameter can be on of the following values:
+ * @arg RCC_UCDR300M_SRC_OSC300M
+ * @arg RCC_UCDR300M_SRC_PLLVCO
+ *
+ * @param Cmd enable/disable selection.
+ * This parameter can be on of the following values:
+ * @arg ENABLE enable UCDR
+ * @arg DISABLE disable UCDR
+ */
+void RCC_ConfigUCDRClk(uint32_t RCC_UCDR300MSource, FunctionalState Cmd)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_UCDR300M_SRC(RCC_UCDR300MSource));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ tmpregister = RCC->CFG3;
+ /* Clear UCDR300MSEL bits */
+ tmpregister &= RCC_UCDR300MSource_MASK;
+ /* Set UCDR300MSEL bits */
+ tmpregister |= RCC_UCDR300MSource;
+
+ /* Store the new value */
+ RCC->CFG3 = tmpregister;
+
+ if (Cmd != DISABLE)
+ {
+ RCC->CFG3 |= RCC_UCDR_ENABLE;
+ }
+ else
+ {
+ RCC->CFG3 &= RCC_UCDR_DISABLE;
+ }
+}
+
+/**
+ * @brief Configures the USB Crystal Mode.
+ * @param RCC_USBXTALESSMode specifies the USB Crystal Mode.
+ * This parameter can be one of the following values:
+ * @arg RCC_USBXTALESS_MODE USB work in crystal mode
+ * @arg RCC_USBXTALESS_LESSMODE USB work in crystalless mode
+ */
+void RCC_ConfigUSBXTALESSMode(uint32_t RCC_USBXTALESSMode)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_USBXTALESS_MODE(RCC_USBXTALESSMode));
+
+ /* Clear the USB Crystal Mode bit */
+ RCC->CFG3 &= RCC_USBXTALESSMode_MASK;
+
+ /* Select the USB Crystal Mode */
+ RCC->CFG3 |= RCC_USBXTALESSMode;
+}
+
+/**
+ * @brief Enables or disables the RET peripheral clock.
+ * @param RCC_RETPeriph specifies the RET peripheral to gates its clock.
+ *
+ * this parameter can be any combination of the following values:
+ * @arg RCC_RET_PERIPH_LPTIM
+ * @arg RCC_RET_PERIPH_LPUART
+ * @arg RCC_RET_PERIPH_LCD
+ *
+ * @param Cmd new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableRETPeriphClk(uint32_t RCC_RETPeriph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_RET_PERIPH(RCC_RETPeriph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ RCC->RDCTRL |= RCC_RETPeriph;
+ }
+ else
+ {
+ RCC->RDCTRL &= ~RCC_RETPeriph;
+ }
+}
+
+/**
+ * @brief Forces or releases RET peripheral reset.
+ * @param RCC_RETPeriph specifies the RET peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_RET_PERIPH_LPTIM.
+ * RCC_RET_PERIPH_LPUART.
+ * RCC_RET_PERIPH_LCD.
+ * @param Cmd new state of the specified peripheral reset. This parameter can be ENABLE or DISABLE.
+ */
+void RCC_EnableRETPeriphReset(uint32_t RCC_RETPeriph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_RET_PERIPH(RCC_RETPeriph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ RCC->RDCTRL |= (RCC_RETPeriph << 4);
+ }
+ else
+ {
+ RCC->RDCTRL &= ~(RCC_RETPeriph << 4);
+ }
+}
+
+/**
+ * @brief Configures the LPTIM clock (LPTIMCLK).
+ * @param RCC_LPTIMCLKSource specifies the LPTIM clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_LPTIMCLK_SRC_APB1 APB1 clock selected as LPTIM clock
+ * @arg RCC_LPTIMCLK_SRC_LSI LSI selected as LPTIM clock
+ * @arg RCC_LPTIMCLK_SRC_HSI HSI selected as LPTIM clock
+ * @arg RCC_LPTIMCLK_SRC_LSE LSE selected as LPTIM clock
+ * @arg RCC_LPTIMCLK_SRC_COMP1 COMP1 output selected as LPTIM clock
+ * @arg RCC_LPTIMCLK_SRC_COMP2 COMP2 output selected as LPTIM clock
+ * @note When switching from comparator1/2 to other clock sources,
+ * it is suggested to disable comparators first.
+ */
+void RCC_ConfigLPTIMClk(uint32_t RCC_LPTIMCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_LPTIM_CLK(RCC_LPTIMCLKSource));
+ //PWR DBP set 1
+ RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR, ENABLE);
+ PWR->CTRL1 |= 0x100;
+ /* Clear the LPTIM clock source */
+ RCC->RDCTRL &= RCC_LPTIMCLK_SRC_MASK;
+
+ /* Select the LPTIM clock source */
+ RCC->RDCTRL |= RCC_LPTIMCLKSource;
+}
+
+/**
+ * @brief Returns the clock source used as LPTIM clock (LPTIMCLK).
+ * @return The clock source used as system clock. The returned value can
+ * be one of the following:
+ * - RCC_LPTIMCLK_SRC_APB1 APB1 clock selected as LPTIM clock
+ * - RCC_LPTIMCLK_SRC_LSI LSI selected as LPTIM clock
+ * - RCC_LPTIMCLK_SRC_HSI HSI selected as LPTIM clock
+ * - RCC_LPTIMCLK_SRC_LSE LSE selected as LPTIM clock
+ * - RCC_LPTIMCLK_SRC_COMP1 COMP1 output selected as LPTIM clock
+ * - RCC_LPTIMCLK_SRC_COMP2 COMP2 output selected as LPTIM clock
+ */
+uint32_t RCC_GetLPTIMClkSrc(void)
+{
+ return ((uint32_t)(RCC->RDCTRL & RDCTRL_LPTIMCLKSEL_MASK));
+}
+
+/**
+ * @brief Configures the LPUART clock (LPUARTCLK).
+ * @param RCC_LPUARTCLKSource specifies the LPUART clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_LPUARTCLK_SRC_APB1 APB1 clock selected as LPTIM clock
+ * @arg RCC_LPUARTCLK_SRC_SYSCLK SYSCLK selected as LPTIM clock
+ * @arg RCC_LPUARTCLK_SRC_HSI HSI selected as LPTIM clock
+ * @arg RCC_LPUARTCLK_SRC_LSE LSE selected as LPTIM clock
+ */
+void RCC_ConfigLPUARTClk(uint32_t RCC_LPUARTCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_LPUART_CLK(RCC_LPUARTCLKSource));
+
+ /* Clear the LPUART clock source */
+ RCC->RDCTRL &= RCC_LPUARTCLK_SRC_MASK;
+
+ /* Select the LPTIM clock source */
+ RCC->RDCTRL |= RCC_LPUARTCLKSource;
+}
+
+/**
+ * @brief Returns the clock source used as LPUART clock.
+ * @return The clock source used as system clock. The returned value can
+ * be one of the following:
+ * - RCC_RDCTRL_LPUARTSEL_APB1: APB1 used as LPUART clock
+ * - RCC_RDCTRL_LPUARTSEL_SYSCLK: SYSCLK used as LPUART clock
+ * - RCC_RDCTRL_LPUARTSEL_HSI: HSI used as LPUART clock
+ * - RCC_RDCTRL_LPUARTSEL_LSE: LSE used as LPUART clock
+ */
+uint32_t RCC_GetLPUARTClkSrc(void)
+{
+ return ((uint32_t)(RCC->RDCTRL & RDCTRL_LPUARTCLKSEL_MASK));
+}
+
+/**
+ * @brief Enables or disables the specified SRAM1/2 parity error interrupts.
+ * @param SramErrorInt specifies the SRAM1/2 interrupt sources to be enabled or disabled.
+ *
+ * this parameter can be any combination of the following values
+ * @arg SRAM1_PARITYERROR_INT SRAM1 parity interrupt
+ * @arg SRAM2_PARITYERROR_INT SRAM2 parity interrupt
+ *
+ * @param Cmd new state of the specified SRAM1/2 parity error interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_ConfigSRAMParityErrorInt(uint32_t SramErrorInt, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_SRAMERRORINT(SramErrorInt));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set ERR1EN/ERR2EN bit to enable the selected parity error interrupts */
+ RCC->SRAM_CTRLSTS |= SramErrorInt;
+ }
+ else
+ {
+ /* Clear ERR1EN/ERR2EN bit to disable the selected parity error interrupts */
+ RCC->SRAM_CTRLSTS &= (~SramErrorInt);
+ }
+}
+
+/**
+ * @brief Enables or disables the specified SRAM1/2 parity error reset.
+ * @param SramErrorReset specifies the SRAM1/2 parity error reset to be enabled or disabled.
+ *
+ * this parameter can be any combination of the following values
+ * @arg SRAM1_PARITYERROR_RESET SRAM1 parity error reset
+ * @arg SRAM2_PARITYERROR_RESET SRAM2 parity error reset
+ *
+ * @param Cmd new state of the specified SRAM1/2 parity error reset.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_ConfigSRAMParityErrorRESET(uint32_t SramErrorReset, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_SRAMERRORRESET(SramErrorReset));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set ERR1EN/ERR2EN bit to enable SRAM1/2 parity error reset */
+ RCC->SRAM_CTRLSTS |= SramErrorReset;
+ }
+ else
+ {
+ /* Clear ERR1EN/ERR2EN bit to disable SRAM1/2 parity error reset */
+ RCC->SRAM_CTRLSTS &= (~SramErrorReset);
+ }
+}
+
+/**
+ * @brief Clears the specified SRAM1/2 parity error flag.
+ * @param SramErrorReset specifies the SRAM1/2 parity error flag.
+ *
+ * this parameter can be any combination of the following values
+ * @arg SRAM1_PARITYERROR_FLAG SRAM1 parity error flag
+ * @arg SRAM2_PARITYERROR_FLAG SRAM2 parity error flag
+ */
+void RCC_ClrSRAMParityErrorFlag(uint32_t SramErrorflag)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_SRAMERRORFLAG(SramErrorflag));
+ RCC->SRAM_CTRLSTS |= SramErrorflag;
+}
+
+/**
+ * @brief Configures the External Low Speed oscillator (LSE) Xtal bias.
+ * @param LSE_Trim specifies LSE Driver Trim Level.
+ * Trim value rang 0x0~0x1FF
+ */
+void LSE_XtalConfig(uint16_t LSE_Trim)
+{
+ uint32_t tmpregister = 0;
+ tmpregister = *(__IO uint32_t*)LSE_TRIMR_ADDR;
+ //clear lse trim[8:0]
+ tmpregister &= (~(LSE_GM_MASK_VALUE));
+ (LSE_Trim>LSE_GM_MAX_VALUE) ? (LSE_Trim=LSE_GM_DEFAULT_VALUE):(LSE_Trim&=LSE_GM_MASK_VALUE);
+ tmpregister |= LSE_Trim;
+ *(__IO uint32_t*)LSE_TRIMR_ADDR = tmpregister;
+}
+
+/**
+ * @brief Configures the External Low Speed oscillator (LSE).
+ * @param RCC_LSE specifies the new state of the LSE.
+ * This parameter can be one of the following values:
+ * @arg RCC_LSE_DISABLE LSE oscillator OFF
+ * @arg RCC_LSE_ENABLE LSE oscillator ON
+ * @arg RCC_LSE_BYPASS LSE oscillator bypassed with external clock
+ * @param LSE_Trim specifies LSE Driver Trim Level.
+ * Trim value rang 0x00~0x1FF
+ */
+void RCC_ConfigLse(uint8_t RCC_LSE,uint16_t LSE_Trim)
+{
+ //PWR DBP set 1
+ /* Enable PWR Clock */
+ RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR, ENABLE);
+ PWR->CTRL1 |= 0x100;
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE(RCC_LSE));
+ /* Reset LSEEN LSEBYP and LSECLKSSEN bits before configuring the LSE ------------------*/
+ *(__IO uint32_t*)LDCTRL_ADDR &= (~(RCC_LDCTRL_LSEEN | RCC_LDCTRL_LSEBP | RCC_LDCTRL_LSECLKSSEN));
+ /* Configure LSE (RCC_LSE_DISABLE is already covered by the code section above) */
+ switch (RCC_LSE)
+ {
+ case RCC_LSE_ENABLE:
+ /* Set LSEON bit */
+ *(__IO uint32_t*)LDCTRL_ADDR |= RCC_LSE_ENABLE;
+ LSE_XtalConfig(LSE_Trim);
+ break;
+ case RCC_LSE_BYPASS:
+ /* Set LSEBYP and LSEON bits */
+ *(__IO uint32_t*)LDCTRL_ADDR |= (RCC_LSE_BYPASS | RCC_LSE_ENABLE);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Enables or disables the Internal Low Speed oscillator (LSI).
+ * @note LSI can not be disabled if the IWDG is running.
+ * @param Cmd new state of the LSI. This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableLsi(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)CTRLSTS_LSIEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Configures the RTC clock (RTCCLK).
+ * @note Once the RTC clock is selected it can't be changed unless the LowPower domain is reset.
+ * @param RCC_RTCCLKSource specifies the RTC clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_RTCCLK_SRC_NONE: No clock selected as RTC clock
+ * @arg RCC_RTCCLK_SRC_LSE: LSE selected as RTC clock
+ * @arg RCC_RTCCLK_SRC_LSI: LSI selected as RTC clock
+ * @arg RCC_RTCCLK_SRC_HSE_DIV32: HSE clock divided by 32 selected as RTC clock
+ */
+void RCC_ConfigRtcClk(uint32_t RCC_RTCCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_RTCCLK_SRC(RCC_RTCCLKSource));
+
+ /* Clear the RTC clock source */
+ RCC->LDCTRL &= (~RCC_LDCTRL_RTCSEL);
+
+ /* Select the RTC clock source */
+ RCC->LDCTRL |= RCC_RTCCLKSource;
+}
+
+/**
+ * @brief Returns the clock source used as RTC clock (RTCCLK).
+ * @return The clock source used as system clock. The returned value can
+ * be one of the following:
+ * - RCC_RTCCLK_SRC_NONE: No clock used as RTC clock (RTCCLK)
+ * - RCC_RTCCLK_SRC_LSE: LSE used as RTC clock (RTCCLK)
+ * - RCC_RTCCLK_SRC_LSI: LSI used as RTC clock (RTCCLK)
+ * - RCC_RTCCLK_SRC_HSE_DIV32: HSE clock divided by 32 used as RTC clock (RTCCLK)
+ */
+uint32_t RCC_GetRTCClkSrc(void)
+{
+ return ((uint32_t)(RCC->LDCTRL & RCC_LDCTRL_RTCSEL));
+}
+
+/**
+ * @brief Enables or disables the RTC clock.
+ * @note This function must be used only after the RTC clock was selected using the RCC_ConfigRtcClk function.
+ * @param Cmd new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableRtcClk(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)LDCTRL_RTCEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Configures the LSX clock (for TSC).
+ * @note Once the LSX clock is selected it can't be changed unless the LowPower domain is reset.
+ * @param RCC_RTCCLKSource specifies the RTC clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_LSXCLK_SRC_LSI LSI selected as RTC clock
+ * @arg RCC_LSXCLK_SRC_LSE LSE selected as RTC clock
+ */
+void RCC_ConfigLSXClk(uint32_t RCC_LSXCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_LSXCLK_SRC(RCC_LSXCLKSource));
+
+ /* Clear the LSX clock source */
+ RCC->LDCTRL &= (~RCC_LDCTRL_LSXSEL);
+
+ /* Select the LSX clock source */
+ RCC->LDCTRL |= RCC_LSXCLKSource;
+}
+
+/**
+ * @brief Returns the clock source used as LSX clock (for TSC).
+ * @return The clock source used as system clock. The returned value can
+ * be one of the following:
+ * - RCC_LSXCLK_SRC_LSI: LSI used as LSX clock (for TSC)
+ * - RCC_LSXCLK_SRC_LSE: LSE used as LSX clock (for TSC)
+ */
+uint32_t RCC_GetLSXClkSrc(void)
+{
+ return ((uint32_t)(RCC->LDCTRL & RCC_LDCTRL_LSXSEL));
+}
+
+/**
+ * @brief Returns the frequencies of different on chip clocks.
+ * @param RCC_Clocks pointer to a RCC_ClocksType structure which will hold
+ * the clocks frequencies.
+ * @note The result of this function could be not correct when using
+ * fractional value for HSE crystal.
+ */
+void RCC_GetClocksFreqValue(RCC_ClocksType* RCC_Clocks)
+{
+ uint32_t tmp = 0, pllclk = 0, pllmull = 0, pllsource = 0, presc = 0;
+ uint8_t msi_clk = 0;
+
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFG & CFG_PLLMULFCT_MASK;
+ pllsource = RCC->CFG & CFG_PLLSRC_MASK;
+ /* Get MSI clock --------------------------------------------------------*/
+ msi_clk = (uint8_t) ((RCC->CTRLSTS & RCC_CTRLSTS_MSIRANGE)>>4);
+
+ if ((pllmull & RCC_CFG_PLLMULFCT_4) == 0)
+ {
+ pllmull = (pllmull >> 18) + 2; // PLLMUL[4]=0
+ }
+ else
+ {
+ pllmull = ((pllmull >> 18) - 496) + 1; // PLLMUL[4]=1
+ }
+
+ if (pllsource == 0x00)
+ {
+ /* HSI selected as PLL clock entry */
+ if ((RCC->PLLHSIPRE & PLLHSIPRE_PLLHSI_PRE_MASK) != (uint32_t)RESET)
+ { /* HSI oscillator clock divided by 2 */
+ pllclk = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ pllclk = HSI_VALUE * pllmull;
+ }
+
+ }
+ else
+ {
+ /* HSE selected as PLL clock entry */
+ if ((RCC->CFG & CFG_PLLHSEPRES_MASK) != (uint32_t)RESET)
+ { /* HSE oscillator clock divided by 2 */
+ pllclk = (HSE_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ pllclk = HSE_VALUE * pllmull;
+ }
+ }
+
+ /* PLL Div clock */
+ if ((RCC->PLLHSIPRE & PLLHSIPRE_PLLSRCDIV_MASK) != (uint32_t)RESET)
+ { /* PLL clock divided by 2 */
+ pllclk = (pllclk >> 1);
+ }
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFG & CFG_SCLKSTS_MASK;
+
+ switch (tmp)
+ {
+ case 0x00: /* MSI used as system clock */
+ RCC_Clocks->SysclkFreq = s_msiClockTable[msi_clk];
+ break;
+ case 0x04: /* HSI used as system clock */
+ RCC_Clocks->SysclkFreq = HSI_VALUE;
+ break;
+ case 0x08: /* HSE used as system clock */
+ RCC_Clocks->SysclkFreq = HSE_VALUE;
+ break;
+ case 0x0C: /* PLL used as system clock */
+ RCC_Clocks->SysclkFreq = pllclk;
+ break;
+
+ default:
+ RCC_Clocks->SysclkFreq = s_msiClockTable[msi_clk];
+ break;
+ }
+
+ /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
+ /* Get HCLK prescaler */
+ tmp = RCC->CFG & CFG_AHBPRES_SET_MASK;
+ tmp = tmp >> 4;
+ presc = s_ApbAhbPresTable[tmp];
+ /* HCLK clock frequency */
+ RCC_Clocks->HclkFreq = RCC_Clocks->SysclkFreq >> presc;
+ /* Get PCLK1 prescaler */
+ tmp = RCC->CFG & CFG_APB1PRES_SET_MASK;
+ tmp = tmp >> 8;
+ presc = s_ApbAhbPresTable[tmp];
+ /* PCLK1 clock frequency */
+ RCC_Clocks->Pclk1Freq = RCC_Clocks->HclkFreq >> presc;
+ /* Get PCLK2 prescaler */
+ tmp = RCC->CFG & CFG_APB2PRES_SET_MASK;
+ tmp = tmp >> 11;
+ presc = s_ApbAhbPresTable[tmp];
+ /* PCLK2 clock frequency */
+ RCC_Clocks->Pclk2Freq = RCC_Clocks->HclkFreq >> presc;
+
+ /* Get ADCHCLK prescaler */
+ tmp = RCC->CFG2 & CFG2_ADCHPRES_SET_MASK;
+ presc = s_AdcHclkPresTable[tmp];
+ /* ADCHCLK clock frequency */
+ RCC_Clocks->AdcHclkFreq = RCC_Clocks->HclkFreq / presc;
+ /* Get ADCPLLCLK prescaler */
+ tmp = RCC->CFG2 & CFG2_ADCPLLPRES_SET_MASK;
+ tmp = tmp >> 4;
+ presc = s_AdcPllClkPresTable[(tmp & 0xF)]; // ignore BIT5
+ /* ADCPLLCLK clock frequency */
+ RCC_Clocks->AdcPllClkFreq = pllclk / presc;
+}
+
+/**
+ * @brief Enables or disables the AHB peripheral clock.
+ * @param RCC_AHBPeriph specifies the AHB peripheral to gates its clock.
+ *
+ * this parameter can be any combination of the following values:
+ * @arg RCC_AHB_PERIPH_DMA
+ * @arg RCC_AHB_PERIPH_SRAM
+ * @arg RCC_AHB_PERIPH_FLITF
+ * @arg RCC_AHB_PERIPH_CRC
+ * @arg RCC_AHB_PERIPH_RNGC
+ * @arg RCC_AHB_PERIPH_SAC
+ * @arg RCC_AHB_PERIPH_ADC
+ *
+ * @note SRAM and FLITF clock can be disabled only during sleep mode.
+ * @param Cmd new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableAHBPeriphClk(uint32_t RCC_AHBPeriph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ RCC->AHBPCLKEN |= RCC_AHBPeriph;
+ }
+ else
+ {
+ RCC->AHBPCLKEN &= ~RCC_AHBPeriph;
+ }
+}
+
+/**
+ * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
+ * @param RCC_APB2Periph specifies the APB2 peripheral to gates its clock.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB2_PERIPH_AFIO, RCC_APB2_PERIPH_GPIOA, RCC_APB2_PERIPH_GPIOB,
+ * RCC_APB2_PERIPH_GPIOC, RCC_APB2_PERIPH_GPIOD, RCC_APB2_PERIPH_TIM1,
+ * RCC_APB2_PERIPH_SPI1, RCC_APB2_PERIPH_TIM8, RCC_APB2_PERIPH_USART1,
+ * RCC_APB2_PERIPH_UART4, RCC_APB2_PERIPH_UART5, RCC_APB2_PERIPH_SPI2
+ * @param Cmd new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableAPB2PeriphClk(uint32_t RCC_APB2Periph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ RCC->APB2PCLKEN |= RCC_APB2Periph;
+ }
+ else
+ {
+ RCC->APB2PCLKEN &= ~RCC_APB2Periph;
+ }
+}
+
+/**
+ * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
+ * @param RCC_APB1Periph specifies the APB1 peripheral to gates its clock.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB1_PERIPH_TIM2, RCC_APB1_PERIPH_TIM3, RCC_APB1_PERIPH_TIM4,
+ * RCC_APB1_PERIPH_TIM5, RCC_APB1_PERIPH_TIM6, RCC_APB1_PERIPH_TIM7,
+ * RCC_APB1_PERIPH_COMP, RCC_APB1_PERIPH_COMP_FILT, RCC_APB1_PERIPH_AFEC,
+ * RCC_APB1_PERIPH_TIM9, RCC_APB1_PERIPH_TSC, RCC_APB1_PERIPH_WWDG,
+ * RCC_APB1_PERIPH_USART2, RCC_APB1_PERIPH_USART3, RCC_APB1_PERIPH_I2C1,
+ * RCC_APB1_PERIPH_I2C2, RCC_APB1_PERIPH_USB, RCC_APB1_PERIPH_CAN,
+ * RCC_APB1_PERIPH_PWR, RCC_APB1_PERIPH_DAC, RCC_APB1_PERIPH_OPAMP
+ *
+ * @param Cmd new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableAPB1PeriphClk(uint32_t RCC_APB1Periph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ RCC->APB1PCLKEN |= RCC_APB1Periph;
+ }
+ else
+ {
+ RCC->APB1PCLKEN &= ~RCC_APB1Periph;
+ }
+}
+
+/**
+ * @brief Forces or releases AHB peripheral reset.
+ * @param RCC_AHBPeriph specifies the AHB peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_AHB_PERIPH_ADC.
+ * RCC_AHB_PERIPH_SAC.
+ * RCC_AHB_PERIPH_RNGC.
+ * @param Cmd new state of the specified peripheral reset. This parameter can be ENABLE or DISABLE.
+ */
+void RCC_EnableAHBPeriphReset(uint32_t RCC_AHBPeriph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ RCC->AHBPRST |= RCC_AHBPeriph;
+ }
+ else
+ {
+ RCC->AHBPRST &= ~RCC_AHBPeriph;
+ }
+}
+
+/**
+ * @brief Forces or releases High Speed APB (APB2) peripheral reset.
+ * @param RCC_APB2Periph specifies the APB2 peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB2_PERIPH_AFIO, RCC_APB2_PERIPH_GPIOA, RCC_APB2_PERIPH_GPIOB,
+ * RCC_APB2_PERIPH_GPIOC, RCC_APB2_PERIPH_GPIOD, RCC_APB2_PERIPH_TIM1,
+ * RCC_APB2_PERIPH_SPI1, RCC_APB2_PERIPH_TIM8, RCC_APB2_PERIPH_USART1,
+ * RCC_APB2_PERIPH_UART4, RCC_APB2_PERIPH_UART5, RCC_APB2_PERIPH_SPI2
+ * @param Cmd new state of the specified peripheral reset.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableAPB2PeriphReset(uint32_t RCC_APB2Periph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ RCC->APB2PRST |= RCC_APB2Periph;
+ }
+ else
+ {
+ RCC->APB2PRST &= ~RCC_APB2Periph;
+ }
+}
+
+/**
+ * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
+ * @param RCC_APB1Periph specifies the APB1 peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB1_PERIPH_TIM2, RCC_APB1_PERIPH_TIM3, RCC_APB1_PERIPH_TIM4,
+ * RCC_APB1_PERIPH_TIM5, RCC_APB1_PERIPH_TIM6, RCC_APB1_PERIPH_TIM7,
+ * RCC_APB1_PERIPH_COMP, RCC_APB1_PERIPH_COMP_FILT, RCC_APB1_PERIPH_AFEC,
+ * RCC_APB1_PERIPH_TIM9, RCC_APB1_PERIPH_TSC, RCC_APB1_PERIPH_WWDG,
+ * RCC_APB1_PERIPH_USART2, RCC_APB1_PERIPH_USART3, RCC_APB1_PERIPH_I2C1,
+ * RCC_APB1_PERIPH_I2C2, RCC_APB1_PERIPH_USB, RCC_APB1_PERIPH_CAN,
+ * RCC_APB1_PERIPH_PWR, RCC_APB1_PERIPH_DAC, RCC_APB1_PERIPH_OPAMP
+ * @param Cmd new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableAPB1PeriphReset(uint32_t RCC_APB1Periph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ RCC->APB1PRST |= RCC_APB1Periph;
+ }
+ else
+ {
+ RCC->APB1PRST &= ~RCC_APB1Periph;
+ }
+}
+
+/**
+ * @brief Forces or releases the LowPower domain reset.
+ * @param Cmd new state of the Backup domain reset.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableLowPowerReset(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)LDCTRL_LDSFTRST_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Enables or disables the Clock Security System.
+ * @param Cmd new state of the Clock Security System..
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableClockSecuritySystem(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)CTRL_CLKSSEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Enables or disables the LSE Clock Security System.
+ * @param Cmd new state of the LSE Clock Security System..
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableLSEClockSecuritySystem(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)LDCTRL_LSECLKSSEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Get LSE Clock Security System failure status.
+ * @return LSE Clock Security System failure status (SET or RESET).
+ */
+FlagStatus RCC_GetLSEClockSecuritySystemStatus(void)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the status of LSE Clock Security System */
+ if ((RCC->LDCTRL & RCC_LDCTRL_LSECLKSSF) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ /* Return LSE Clock Security System status */
+ return bitstatus;
+}
+
+/**
+ * @brief Configures the MCO PLL clock prescaler.
+ * @param RCC_MCOPLLCLKPrescaler specifies the MCO PLL clock prescaler.
+ * This parameter can be on of the following values:
+ * @arg RCC_MCO_CLK_NUM0 MCOPRE[3:0] = 0000, PLL Clock Divided By 1, Duty cycle = clock source
+ * @arg RCC_MCO_CLK_NUM1 MCOPRE[3:0] = 0001, PLL Clock Divided By 2, Duty cycle = 1/((MCOPRE[3:0]+1)*2)
+ * @arg RCC_MCO_CLK_NUM2 MCOPRE[3:0] = 0010, PLL Clock Divided By 3, Duty cycle = 1/((MCOPRE[3:0]+1)*2)
+ * @arg RCC_MCO_CLK_NUM3 MCOPRE[3:0] = 0011, PLL Clock Divided By 4, Duty cycle = 1/((MCOPRE[3:0]+1)*2)
+ * @arg RCC_MCO_CLK_NUM4 MCOPRE[3:0] = 0100, PLL Clock Divided By 5, Duty cycle = 1/((MCOPRE[3:0]+1)*2)
+ * @arg RCC_MCO_CLK_NUM5 MCOPRE[3:0] = 0101, PLL Clock Divided By 6, Duty cycle = 1/((MCOPRE[3:0]+1)*2)
+ * @arg RCC_MCO_CLK_NUM6 MCOPRE[3:0] = 0110, PLL Clock Divided By 7, Duty cycle = 1/((MCOPRE[3:0]+1)*2)
+ * @arg RCC_MCO_CLK_NUM7 MCOPRE[3:0] = 0111, PLL Clock Divided By 8, Duty cycle = 1/((MCOPRE[3:0]+1)*2)
+ * @arg RCC_MCO_CLK_NUM8 MCOPRE[3:0] = 1000, PLL Clock Divided By 2, Duty cycle = 50%
+ * @arg RCC_MCO_CLK_NUM9 MCOPRE[3:0] = 1001, PLL Clock Divided By 4, Duty cycle = 50%
+ * @arg RCC_MCO_CLK_NUM10 MCOPRE[3:0] = 1010, PLL Clock Divided By 6, Duty cycle = 50%
+ * @arg RCC_MCO_CLK_NUM11 MCOPRE[3:0] = 1011, PLL Clock Divided By 8, Duty cycle = 50%
+ * @arg RCC_MCO_CLK_NUM12 MCOPRE[3:0] = 1100, PLL Clock Divided By 10, Duty cycle = 50%
+ * @arg RCC_MCO_CLK_NUM13 MCOPRE[3:0] = 1101, PLL Clock Divided By 12, Duty cycle = 50%
+ * @arg RCC_MCO_CLK_NUM14 MCOPRE[3:0] = 1110, PLL Clock Divided By 14, Duty cycle = 50%
+ * @arg RCC_MCO_CLK_NUM15 MCOPRE[3:0] = 1111, PLL Clock Divided By 16, Duty cycle = 50%
+ */
+void RCC_ConfigMcoClkPre(uint32_t RCC_MCOCLKPrescaler)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_MCOCLKPRE(RCC_MCOCLKPrescaler));
+
+ tmpregister = RCC->CFG;
+ /* Clear MCOPRE[3:0] bits */
+ tmpregister &= ((uint32_t)0x0FFFFFFF);
+ /* Set MCOPRE[3:0] bits according to RCC_ADCHCLKPrescaler value */
+ tmpregister |= RCC_MCOCLKPrescaler;
+
+ /* Store the new value */
+ RCC->CFG = tmpregister;
+}
+
+/**
+ * @brief Selects the clock source to output on MCO pin.
+ * @param RCC_MCO specifies the clock source to output.
+ *
+ * this parameter can be one of the following values:
+ * @arg RCC_MCO_NOCLK No clock selected
+ * @arg RCC_MCO_LSI LSI oscillator clock selected
+ * @arg RCC_MCO_LSE LSE oscillator clock selected
+ * @arg RCC_MCO_MSI MSI oscillator clock selected
+ * @arg RCC_MCO_SYSCLK System clock selected
+ * @arg RCC_MCO_HSI HSI oscillator clock selected
+ * @arg RCC_MCO_HSE HSE oscillator clock selected
+ * @arg RCC_MCO_PLLCLK PLL clock selected
+ *
+ */
+void RCC_ConfigMco(uint8_t RCC_MCO)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_MCO(RCC_MCO));
+
+ tmpregister = RCC->CFG;
+ /* Clear MCO[2:0] bits */
+ tmpregister &= ((uint32_t)0xF8FFFFFF);
+ /* Set MCO[2:0] bits according to RCC_MCO value */
+ tmpregister |= ((uint32_t)(RCC_MCO << 24));
+
+ /* Store the new value */
+ RCC->CFG = tmpregister;
+}
+
+/**
+ * @brief Checks whether the specified RCC flag is set or not.
+ * @param RCC_FLAG specifies the flag to check.
+ *
+ * this parameter can be one of the following values:
+ * @arg RCC_CTRL_FLAG_HSIRDF HSI oscillator clock ready
+ * @arg RCC_CTRL_FLAG_HSERDF HSE oscillator clock ready
+ * @arg RCC_CTRL_FLAG_PLLRDF PLL clock ready
+ * @arg RCC_LDCTRL_FLAG_LSERD LSE oscillator clock ready
+ * @arg RCC_LDCTRL_FLAG_LSECLKSSF LSE Clock Security System failure status
+ * @arg RCC_LDCTRL_FLAG_BORRSTF BOR reset flag
+ * @arg RCC_LDCTRL_FLAG_LDEMCRSTF LowPower EMC reset flag
+ * @arg RCC_CTRLSTS_FLAG_LSIRD LSI oscillator clock ready
+ * @arg RCC_CTRLSTS_FLAG_MSIRD MSI oscillator clock ready
+ * @arg RCC_CTRLSTS_FLAG_RAMRSTF RAM reset flag
+ * @arg RCC_CTRLSTS_FLAG_MMURSTF MMU reset flag
+ * @arg RCC_CTRLSTS_FLAG_PINRSTF Pin reset
+ * @arg RCC_CTRLSTS_FLAG_PORRSTF POR reset
+ * @arg RCC_CTRLSTS_FLAG_SFTRSTF Software reset
+ * @arg RCC_CTRLSTS_FLAG_IWDGRSTF Independent Watchdog reset
+ * @arg RCC_CTRLSTS_FLAG_WWDGRSTF Window Watchdog reset
+ * @arg RCC_CTRLSTS_FLAG_LPWRRSTF Low Power reset
+ *
+ * @return The new state of RCC_FLAG (SET or RESET).
+ */
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
+{
+ uint32_t tmp = 0;
+ uint32_t statusreg = 0;
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_RCC_FLAG(RCC_FLAG));
+
+ /* Get the RCC register index */
+ tmp = RCC_FLAG >> 5;
+ if (tmp == 1) /* The flag to check is in CTRL register */
+ {
+ statusreg = RCC->CTRL;
+ }
+ else if (tmp == 2) /* The flag to check is in BDCTRL register */
+ {
+ statusreg = RCC->LDCTRL;
+ }
+ else /* The flag to check is in CTRLSTS register */
+ {
+ statusreg = RCC->CTRLSTS;
+ }
+
+ /* Get the flag position */
+ tmp = RCC_FLAG & FLAG_MASK;
+ if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RCC reset flags.
+ * @note The reset flags are: RCC_FLAG_LPEMCRST, RCC_FLAG_BORRST, RCC_FLAG_RAMRST, RCC_FLAG_MMURST,
+ * RCC_FLAG_PINRST, RCC_FLAG_PORRST,RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST,
+ * RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
+ */
+void RCC_ClrFlag(void)
+{
+ /* Set RMVF bit to clear the reset flags */
+ RCC->CTRLSTS |= CSR_RMRSTF_SET;
+ /* RMVF bit should be reset */
+ RCC->CTRLSTS &= CSR_RMVF_Reset;
+}
+
+/**
+ * @brief Checks whether the specified RCC interrupt has occurred or not.
+ * @param RccInt specifies the RCC interrupt source to check.
+ *
+ * this parameter can be one of the following values:
+ * @arg RCC_INT_LSIRDIF LSI ready interrupt
+ * @arg RCC_INT_LSERDIF LSE ready interrupt
+ * @arg RCC_INT_HSIRDIF HSI ready interrupt
+ * @arg RCC_INT_HSERDIF HSE ready interrupt
+ * @arg RCC_INT_PLLRDIF PLL ready interrupt
+ * @arg RCC_INT_BORIF interrupt
+ * @arg RCC_INT_MSIRDIF MSI ready interrupt
+ * @arg RCC_INT_CLKSSIF Clock Security System interrupt
+ *
+ * @return The new state of RccInt (SET or RESET).
+ */
+INTStatus RCC_GetIntStatus(uint8_t RccInt)
+{
+ INTStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_RCC_GET_INT(RccInt));
+
+ /* Check the status of the specified RCC interrupt */
+ if ((RCC->CLKINT & RccInt) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ /* Return the RccInt status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RCC's interrupt pending bits.
+ * @param RccInt specifies the interrupt pending bit to clear.
+ *
+ * this parameter can be any combination of the
+ * following values:
+ * @arg RCC_CLR_MSIRDIF Clear MSI ready interrupt flag
+ * @arg RCC_CLR_LSIRDIF Clear LSI ready interrupt flag
+ * @arg RCC_CLR_LSERDIF Clear LSE ready interrupt flag
+ * @arg RCC_CLR_HSIRDIF Clear HSI ready interrupt flag
+ * @arg RCC_CLR_HSERDIF Clear HSE ready interrupt flag
+ * @arg RCC_CLR_PLLRDIF Clear PLL ready interrupt flag
+ * @arg RCC_CLR_BORIF Clear BOR interrupt flag
+ * @arg RCC_CLR_CLKSSIF Clear Clock Security System interrupt flag
+ */
+void RCC_ClrIntPendingBit(uint32_t RccClrInt)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_CLR_INTF(RccClrInt));
+ /* Software set this bit to clear INT flag. */
+ RCC->CLKINT |= RccClrInt;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_rtc.c b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_rtc.c
new file mode 100644
index 0000000000..bb733784a3
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_rtc.c
@@ -0,0 +1,2339 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_rtc.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l40x_rtc.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RTC
+ * @brief RTC driver modules
+ * @{
+ */
+
+/* Masks Definition */
+#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
+#define RTC_DATE_RESERVED_MASK ((uint32_t)0x00FFFF3F)
+
+#define RTC_RSF_MASK ((uint32_t)0xFFFFFFDF)
+#define RTC_FLAGS_MASK \
+ ((uint32_t)(RTC_FLAG_TISOVF | RTC_FLAG_TISF | RTC_FLAG_WTF | RTC_FLAG_ALBF | RTC_FLAG_ALAF | RTC_FLAG_INITF \
+ | RTC_FLAG_RSYF | RTC_FLAG_INITSF | RTC_FLAG_WTWF | RTC_FLAG_ALBWF | RTC_FLAG_ALAWF | RTC_FLAG_RECPF \
+ | RTC_FLAG_SHOPF))
+
+#define INITMODE_TIMEOUT ((uint32_t)0x00002000)
+#define SYNCHRO_TIMEOUT ((uint32_t)0x00008000)
+#define RECALPF_TIMEOUT ((uint32_t)0x00001000)
+#define SHPF_TIMEOUT ((uint32_t)0x00002000)
+
+static uint8_t RTC_ByteToBcd2(uint8_t Value);
+static uint8_t RTC_Bcd2ToByte(uint8_t Value);
+
+/** @addtogroup RTC_Private_Functions
+ * @{
+ */
+
+/** @addtogroup RTC_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This section provide functions allowing to initialize and configure the
+ RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
+ RTC registers Write protection, enter and exit the RTC initialization mode,
+ RTC registers synchronization check and reference clock detection enable.
+ (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
+ It is split into 2 programmable prescalers to minimize power consumption.
+ (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler.
+ (++) When both prescalers are used, it is recommended to configure the
+ asynchronous prescaler to a high value to minimize consumption.
+ (#) All RTC registers are Write protected. Writing to the RTC registers
+ is enabled by writing a key into the Write Protection register, RTC_WRP.
+ (#) To Configure the RTC Calendar, user application should enter
+ initialization mode. In this mode, the calendar counter is stopped
+ and its value can be updated. When the initialization sequence is
+ complete, the calendar restarts counting after 4 RTCCLK cycles.
+ (#) To read the calendar through the shadow registers after Calendar
+ initialization, calendar update or after wakeup from low power modes
+ the software must first clear the RSYF flag. The software must then
+ wait until it is set again before reading the calendar, which means
+ that the calendar registers have been correctly copied into the
+ RTC_TSH and RTC_DATE shadow registers.The RTC_WaitForSynchro() function
+ implements the above software sequence (RSYF clear and RSYF check).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the RTC registers to their default reset values.
+ * @note This function doesn't reset the RTC Clock source and RTC Backup Data
+ * registers.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are deinitialized
+ * - ERROR: RTC registers are not deinitialized
+ */
+ErrorStatus RTC_DeInit(void)
+{
+ __IO uint32_t wutcounter = 0x00;
+ uint32_t wutwfstatus = 0x00;
+ ErrorStatus status = ERROR;
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Set Initialization mode */
+ if (RTC_EnterInitMode() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ /* Reset TSH, DAT and CTRL registers */
+ RTC->TSH = (uint32_t)0x00000000;
+ RTC->DATE = (uint32_t)0x00002101;
+
+ /* Reset All CTRL bits except CTRL[2:0] */
+ RTC->CTRL &= (uint32_t)0x00000007;
+
+ /* Wait till RTC WTWF flag is set and if Time out is reached exit */
+ do
+ {
+ wutwfstatus = RTC->INITSTS & RTC_INITSTS_WTWF;
+ wutcounter++;
+ } while ((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
+
+ if ((RTC->INITSTS & RTC_INITSTS_WTWF) == RESET)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ /* Reset all RTC CTRL register bits */
+ RTC->CTRL &= (uint32_t)0x00000000;
+ RTC->WKUPT = (uint32_t)0x0000FFFF;
+ RTC->PRE = (uint32_t)0x007F00FF;
+ RTC->ALARMA = (uint32_t)0x00000000;
+ RTC->ALARMB = (uint32_t)0x00000000;
+ RTC->SCTRL = (uint32_t)0x00000000;
+ RTC->CALIB = (uint32_t)0x00000000;
+ RTC->ALRMASS = (uint32_t)0x00000000;
+ RTC->ALRMBSS = (uint32_t)0x00000000;
+
+ /* Reset INTSTS register and exit initialization mode */
+ RTC->INITSTS = (uint32_t)0x00000000;
+
+ RTC->OPT = (uint32_t)0x00000000;
+ RTC->TSCWKUPCTRL = (uint32_t)0x00000008;
+ RTC->TSCWKUPCNT = (uint32_t)0x000002FE;
+
+ /* Wait till the RTC RSYF flag is set */
+ if (RTC_WaitForSynchro() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+
+ return status;
+}
+
+/**
+ * @brief Initializes the RTC registers according to the specified parameters
+ * in RTC_InitStruct.
+ * @param RTC_InitStruct pointer to a RTC_InitType structure that contains
+ * the configuration information for the RTC peripheral.
+ * @note The RTC Prescaler register is write protected and can be written in
+ * initialization mode only.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are initialized
+ * - ERROR: RTC registers are not initialized
+ */
+ErrorStatus RTC_Init(RTC_InitType* RTC_InitStruct)
+{
+ ErrorStatus status = ERROR;
+ uint32_t i =0;
+ /* Check the parameters */
+ assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat));
+ assert_param(IS_RTC_PREDIV_ASYNCH(RTC_InitStruct->RTC_AsynchPrediv));
+ assert_param(IS_RTC_PREDIV_SYNCH(RTC_InitStruct->RTC_SynchPrediv));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Set Initialization mode */
+ if (RTC_EnterInitMode() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ /* Clear RTC CTRL HFMT Bit */
+ RTC->CTRL &= ((uint32_t) ~(RTC_CTRL_HFMT));
+ /* Set RTC_CTRL register */
+ RTC->CTRL |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat));
+
+ /* Configure the RTC PRE */
+ RTC->PRE = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv);
+ RTC->PRE |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16);
+
+ /* Exit Initialization mode */
+ RTC_ExitInitMode();
+
+ status = SUCCESS;
+ }
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+ /* Delay for the RTC prescale effect */
+ for(i=0;i<0x2FF;i++);
+ return status;
+}
+
+/**
+ * @brief Fills each RTC_InitStruct member with its default value.
+ * @param RTC_InitStruct pointer to a RTC_InitType structure which will be
+ * initialized.
+ */
+void RTC_StructInit(RTC_InitType* RTC_InitStruct)
+{
+ /* Initialize the RTC_HourFormat member */
+ RTC_InitStruct->RTC_HourFormat = RTC_24HOUR_FORMAT;
+
+ /* Initialize the RTC_AsynchPrediv member */
+ RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F;
+
+ /* Initialize the RTC_SynchPrediv member */
+ RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF;
+}
+
+/**
+ * @brief Enables or disables the RTC registers write protection.
+ * @note All the RTC registers are write protected except for RTC_INITSTS[13:8].
+ * @note Writing a wrong key reactivates the write protection.
+ * @note The protection mechanism is not affected by system reset.
+ * @param Cmd new state of the write protection.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RTC_EnableWriteProtection(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+ }
+ else
+ {
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+ }
+}
+
+/**
+ * @brief Enters the RTC Initialization mode.
+ * @note The RTC Initialization mode is write protected, use the
+ * RTC_EnableWriteProtection(DISABLE) before calling this function.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC is in Init mode
+ * - ERROR: RTC is not in Init mode
+ */
+ErrorStatus RTC_EnterInitMode(void)
+{
+ __IO uint32_t initcounter = 0x00;
+ ErrorStatus status = ERROR;
+ uint32_t initstatus = 0x00;
+
+ /* Check if the Initialization mode is set */
+ if ((RTC->INITSTS & RTC_INITSTS_INITF) == (uint32_t)RESET)
+ {
+ /* Set the Initialization mode */
+ RTC->INITSTS = (uint32_t)RTC_INITSTS_INITM;
+
+ /* Wait till RTC is in INIT state and if Time out is reached exit */
+ do
+ {
+ initstatus = RTC->INITSTS & RTC_INITSTS_INITF;
+ initcounter++;
+ } while ((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));
+
+ if ((RTC->INITSTS & RTC_INITSTS_INITF) != RESET)
+ {
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Exits the RTC Initialization mode.
+ * @note When the initialization sequence is complete, the calendar restarts
+ * counting after 4 RTCCLK cycles.
+ * @note The RTC Initialization mode is write protected, use the
+ * RTC_EnableWriteProtection(DISABLE) before calling this function.
+ */
+void RTC_ExitInitMode(void)
+{
+ /* Exit Initialization mode */
+ RTC->INITSTS &= (uint32_t)~RTC_INITSTS_INITM;
+}
+
+/**
+ * @brief Waits until the RTC Time and Date registers (RTC_TSH and RTC_DATE) are
+ * synchronized with RTC APB clock.
+ * @note The RTC Resynchronization mode is write protected, use the
+ * RTC_EnableWriteProtection(DISABLE) before calling this function.
+ * @note To read the calendar through the shadow registers after Calendar
+ * initialization, calendar update or after wakeup from low power modes
+ * the software must first clear the RSYF flag.
+ * The software must then wait until it is set again before reading
+ * the calendar, which means that the calendar registers have been
+ * correctly copied into the RTC_TSH and RTC_DATE shadow registers.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are synchronised
+ * - ERROR: RTC registers are not synchronised
+ */
+ErrorStatus RTC_WaitForSynchro(void)
+{
+ __IO uint32_t synchrocounter = 0;
+ ErrorStatus status = ERROR;
+ uint32_t synchrostatus = 0x00;
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Clear RSYF flag */
+ RTC->INITSTS &= (uint32_t)RTC_RSF_MASK;
+
+ /* Wait the registers to be synchronised */
+ do
+ {
+ synchrostatus = RTC->INITSTS & RTC_INITSTS_RSYF;
+ synchrocounter++;
+ } while ((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));
+
+ if ((RTC->INITSTS & RTC_INITSTS_RSYF) != RESET)
+ {
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+
+ return (status);
+}
+
+/**
+ * @brief Enables or disables the RTC reference clock detection.
+ * @param Cmd new state of the RTC reference clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC reference clock detection is enabled
+ * - ERROR: RTC reference clock detection is disabled
+ */
+ErrorStatus RTC_EnableRefClock(FunctionalState Cmd)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Set Initialization mode */
+ if (RTC_EnterInitMode() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ if (Cmd != DISABLE)
+ {
+ /* Enable the RTC reference clock detection */
+ RTC->CTRL |= RTC_CTRL_REFCLKEN;
+ }
+ else
+ {
+ /* Disable the RTC reference clock detection */
+ RTC->CTRL &= ~RTC_CTRL_REFCLKEN;
+ }
+ /* Exit Initialization mode */
+ RTC_ExitInitMode();
+
+ status = SUCCESS;
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+
+ return status;
+}
+
+/**
+ * @brief Enables or Disables the Bypass Shadow feature.
+ * @note When the Bypass Shadow is enabled the calendar value are taken
+ * directly from the Calendar counter.
+ * @param Cmd new state of the Bypass Shadow feature.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RTC_EnableBypassShadow(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ if (Cmd != DISABLE)
+ {
+ /* Set the BYPS bit */
+ RTC->CTRL |= (uint8_t)RTC_CTRL_BYPS;
+ }
+ else
+ {
+ /* Reset the BYPS bit */
+ RTC->CTRL &= (uint8_t)~RTC_CTRL_BYPS;
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group2 Time and Date configuration functions
+ * @brief Time and Date configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Time and Date configuration functions #####
+ ===============================================================================
+ [..] This section provide functions allowing to program and read the RTC
+ Calendar (Time and Date).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set the RTC current time.
+ * @param RTC_Format specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN Binary data format.
+ * @arg RTC_FORMAT_BCD BCD data format.
+ * @param RTC_TimeStruct pointer to a RTC_TimeType structure that contains
+ * the time configuration information for the RTC.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Time register is configured
+ * - ERROR: RTC Time register is not configured
+ */
+ErrorStatus RTC_ConfigTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct)
+{
+ uint32_t tmpregister = 0;
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+
+ if (RTC_Format == RTC_FORMAT_BIN)
+ {
+ if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET)
+ {
+ assert_param(IS_RTC_12HOUR(RTC_TimeStruct->Hours));
+ assert_param(IS_RTC_H12(RTC_TimeStruct->H12));
+ }
+ else
+ {
+ RTC_TimeStruct->H12 = 0x00;
+ assert_param(IS_RTC_24HOUR(RTC_TimeStruct->Hours));
+ }
+ assert_param(IS_RTC_MINUTES(RTC_TimeStruct->Minutes));
+ assert_param(IS_RTC_SECONDS(RTC_TimeStruct->Seconds));
+ }
+ else
+ {
+ if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET)
+ {
+ tmpregister = RTC_Bcd2ToByte(RTC_TimeStruct->Hours);
+ assert_param(IS_RTC_12HOUR(tmpregister));
+ assert_param(IS_RTC_H12(RTC_TimeStruct->H12));
+ }
+ else
+ {
+ RTC_TimeStruct->H12 = 0x00;
+ assert_param(IS_RTC_24HOUR(RTC_Bcd2ToByte(RTC_TimeStruct->Hours)));
+ }
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->Seconds)));
+ }
+
+ /* Check the input parameters format */
+ if (RTC_Format != RTC_FORMAT_BIN)
+ {
+ tmpregister = (((uint32_t)(RTC_TimeStruct->Hours) << 16) | ((uint32_t)(RTC_TimeStruct->Minutes) << 8)
+ | ((uint32_t)RTC_TimeStruct->Seconds) | ((uint32_t)(RTC_TimeStruct->H12) << 16));
+ }
+ else
+ {
+ tmpregister =
+ (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->Hours) << 16)
+ | ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->Minutes) << 8)
+ | ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->Seconds)) | (((uint32_t)RTC_TimeStruct->H12) << 16));
+ }
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Set Initialization mode */
+ if (RTC_EnterInitMode() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ /* Set the RTC_TSH register */
+ RTC->TSH = (uint32_t)(tmpregister & RTC_TR_RESERVED_MASK);
+
+ /* Exit Initialization mode */
+ RTC_ExitInitMode();
+
+ /* If RTC_CTRL_BYPS bit = 0, wait for synchro else this check is not needed */
+ if ((RTC->CTRL & RTC_CTRL_BYPS) == RESET)
+ {
+ if (RTC_WaitForSynchro() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+ /* Waits until the RTC Time and Date registers
+ (RTC_TSH and RTC_DATE) are synchronized with RTC APB clock. */
+ status=RTC_WaitForSynchro();
+ return status;
+}
+
+/**
+ * @brief Fills each RTC_TimeStruct member with its default value
+ * (Time = 00h:00min:00sec).
+ * @param RTC_TimeStruct pointer to a RTC_TimeType structure which will be
+ * initialized.
+ */
+void RTC_TimeStructInit(RTC_TimeType* RTC_TimeStruct)
+{
+ /* Time = 00h:00min:00sec */
+ RTC_TimeStruct->H12 = RTC_AM_H12;
+ RTC_TimeStruct->Hours = 0;
+ RTC_TimeStruct->Minutes = 0;
+ RTC_TimeStruct->Seconds = 0;
+}
+
+/**
+ * @brief Get the RTC current Time.
+ * @param RTC_Format specifies the format of the returned parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN Binary data format.
+ * @arg RTC_FORMAT_BCD BCD data format.
+ * @param RTC_TimeStruct pointer to a RTC_TimeType structure that will
+ * contain the returned current time configuration.
+ */
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+
+ /* Get the RTC_TSH register */
+ tmpregister = (uint32_t)(RTC->TSH & RTC_TR_RESERVED_MASK);
+
+ /* Fill the structure fields with the read parameters */
+ RTC_TimeStruct->Hours = (uint8_t)((tmpregister & (RTC_TSH_HOT | RTC_TSH_HOU)) >> 16);
+ RTC_TimeStruct->Minutes = (uint8_t)((tmpregister & (RTC_TSH_MIT | RTC_TSH_MIU)) >> 8);
+ RTC_TimeStruct->Seconds = (uint8_t)(tmpregister & (RTC_TSH_SCT | RTC_TSH_SCU));
+ RTC_TimeStruct->H12 = (uint8_t)((tmpregister & (RTC_TSH_APM)) >> 16);
+
+ /* Check the input parameters format */
+ if (RTC_Format == RTC_FORMAT_BIN)
+ {
+ /* Convert the structure parameters to Binary format */
+ RTC_TimeStruct->Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->Hours);
+ RTC_TimeStruct->Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->Minutes);
+ RTC_TimeStruct->Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->Seconds);
+ }
+}
+
+/**
+ * @brief Gets the RTC current Calendar Subseconds value.
+ * @return RTC current Calendar Subseconds value.
+ */
+uint32_t RTC_GetSubSecond(void)
+{
+ uint32_t tmpregister = 0;
+
+ /* Get subseconds values from the correspondent registers*/
+ tmpregister = (uint32_t)(RTC->SUBS);
+
+ return (tmpregister);
+}
+
+/**
+ * @brief Set the RTC current date.
+ * @param RTC_Format specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN Binary data format.
+ * @arg RTC_FORMAT_BCD BCD data format.
+ * @param RTC_DateStruct pointer to a RTC_DateType structure that contains
+ * the date configuration information for the RTC.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Date register is configured
+ * - ERROR: RTC Date register is not configured
+ */
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct)
+{
+ uint32_t tmpregister = 0;
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+
+ if ((RTC_Format == RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10) == 0x10))
+ {
+ RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint32_t) ~(0x10)) + 0x0A;
+ }
+ if (RTC_Format == RTC_FORMAT_BIN)
+ {
+ assert_param(IS_RTC_YEAR(RTC_DateStruct->Year));
+ assert_param(IS_RTC_MONTH(RTC_DateStruct->Month));
+ assert_param(IS_RTC_DATE(RTC_DateStruct->Date));
+ }
+ else
+ {
+ assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->Year)));
+ tmpregister = RTC_Bcd2ToByte(RTC_DateStruct->Month);
+ assert_param(IS_RTC_MONTH(tmpregister));
+ tmpregister = RTC_Bcd2ToByte(RTC_DateStruct->Date);
+ assert_param(IS_RTC_DATE(tmpregister));
+ }
+ assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->WeekDay));
+
+ /* Check the input parameters format */
+ if (RTC_Format != RTC_FORMAT_BIN)
+ {
+ tmpregister = ((((uint32_t)RTC_DateStruct->Year) << 16) | (((uint32_t)RTC_DateStruct->Month) << 8)
+ | ((uint32_t)RTC_DateStruct->Date) | (((uint32_t)RTC_DateStruct->WeekDay) << 13));
+ }
+ else
+ {
+ tmpregister = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->Year) << 16)
+ | ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->Month) << 8)
+ | ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->Date)) | ((uint32_t)RTC_DateStruct->WeekDay << 13));
+ }
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Set Initialization mode */
+ if (RTC_EnterInitMode() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ /* Set the RTC_DATE register */
+ RTC->DATE = (uint32_t)(tmpregister & RTC_DATE_RESERVED_MASK);
+
+ /* Exit Initialization mode */
+ RTC_ExitInitMode();
+
+ /* If RTC_CTRL_BYPS bit = 0, wait for synchro else this check is not needed */
+ if ((RTC->CTRL & RTC_CTRL_BYPS) == RESET)
+ {
+ if (RTC_WaitForSynchro() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+ /* Waits until the RTC Time and Date registers
+ (RTC_TSH and RTC_DATE) are synchronized with RTC APB clock. */
+ status=RTC_WaitForSynchro();
+ return status;
+}
+
+/**
+ * @brief Fills each RTC_DateStruct member with its default value
+ * (Monday, January 01 xx00).
+ * @param RTC_DateStruct pointer to a RTC_DateType structure which will be
+ * initialized.
+ */
+void RTC_DateStructInit(RTC_DateType* RTC_DateStruct)
+{
+ /* Monday, January 01 xx00 */
+ RTC_DateStruct->WeekDay = RTC_WEEKDAY_MONDAY;
+ RTC_DateStruct->Date = 1;
+ RTC_DateStruct->Month = RTC_MONTH_JANUARY;
+ RTC_DateStruct->Year = 0;
+}
+
+/**
+ * @brief Get the RTC current date.
+ * @param RTC_Format specifies the format of the returned parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN Binary data format.
+ * @arg RTC_FORMAT_BCD BCD data format.
+ * @param RTC_DateStruct pointer to a RTC_DateType structure that will
+ * contain the returned current date configuration.
+ */
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+
+ /* Get the RTC_TSH register */
+ tmpregister = (uint32_t)(RTC->DATE & RTC_DATE_RESERVED_MASK);
+
+ /* Fill the structure fields with the read parameters */
+ RTC_DateStruct->Year = (uint8_t)((tmpregister & (RTC_DATE_YRT | RTC_DATE_YRU)) >> 16);
+ RTC_DateStruct->Month = (uint8_t)((tmpregister & (RTC_DATE_MOT | RTC_DATE_MOU)) >> 8);
+ RTC_DateStruct->Date = (uint8_t)(tmpregister & (RTC_DATE_DAT | RTC_DATE_DAU));
+ RTC_DateStruct->WeekDay = (uint8_t)((tmpregister & (RTC_DATE_WDU)) >> 13);
+
+ /* Check the input parameters format */
+ if (RTC_Format == RTC_FORMAT_BIN)
+ {
+ /* Convert the structure parameters to Binary format */
+ RTC_DateStruct->Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->Year);
+ RTC_DateStruct->Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->Month);
+ RTC_DateStruct->Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->Date);
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group3 Alarms configuration functions
+ * @brief Alarms (Alarm A and Alarm B) configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Alarms (Alarm A and Alarm B) configuration functions #####
+ ===============================================================================
+ [..] This section provide functions allowing to program and read the RTC
+ Alarms.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set the specified RTC Alarm.
+ * @note The Alarm register can only be written when the corresponding Alarm
+ * is disabled (Use the RTC_EnableAlarm(DISABLE)).
+ * @param RTC_Format specifies the format of the returned parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN Binary data format.
+ * @arg RTC_FORMAT_BCD BCD data format.
+ * @param RTC_Alarm specifies the alarm to be configured.
+ * This parameter can be one of the following values:
+ * @arg RTC_A_ALARM to select Alarm A.
+ * @arg RTC_B_ALARM to select Alarm B.
+ * @param RTC_AlarmStruct pointer to a RTC_AlarmType structure that
+ * contains the alarm configuration parameters.
+ */
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+ assert_param(IS_RTC_ALARM_SEL(RTC_Alarm));
+ assert_param(IS_ALARM_MASK(RTC_AlarmStruct->AlarmMask));
+ assert_param(IS_RTC_ALARM_WEEKDAY_SEL(RTC_AlarmStruct->DateWeekMode));
+
+ if (RTC_Format == RTC_FORMAT_BIN)
+ {
+ if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET)
+ {
+ assert_param(IS_RTC_12HOUR(RTC_AlarmStruct->AlarmTime.Hours));
+ assert_param(IS_RTC_H12(RTC_AlarmStruct->AlarmTime.H12));
+ }
+ else
+ {
+ RTC_AlarmStruct->AlarmTime.H12 = 0x00;
+ assert_param(IS_RTC_24HOUR(RTC_AlarmStruct->AlarmTime.Hours));
+ }
+ assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
+ assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
+
+ if (RTC_AlarmStruct->DateWeekMode == RTC_ALARM_SEL_WEEKDAY_DATE)
+ {
+ assert_param(IS_RTC_ALARM_WEEKDAY_DATE(RTC_AlarmStruct->DateWeekValue));
+ }
+ else
+ {
+ assert_param(IS_RTC_ALARM_WEEKDAY_WEEKDAY(RTC_AlarmStruct->DateWeekValue));
+ }
+ }
+ else
+ {
+ if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET)
+ {
+ tmpregister = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Hours);
+ assert_param(IS_RTC_12HOUR(tmpregister));
+ assert_param(IS_RTC_H12(RTC_AlarmStruct->AlarmTime.H12));
+ }
+ else
+ {
+ RTC_AlarmStruct->AlarmTime.H12 = 0x00;
+ assert_param(IS_RTC_24HOUR(RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Hours)));
+ }
+
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Seconds)));
+
+ if (RTC_AlarmStruct->DateWeekMode == RTC_ALARM_SEL_WEEKDAY_DATE)
+ {
+ tmpregister = RTC_Bcd2ToByte(RTC_AlarmStruct->DateWeekValue);
+ assert_param(IS_RTC_ALARM_WEEKDAY_DATE(tmpregister));
+ }
+ else
+ {
+ tmpregister = RTC_Bcd2ToByte(RTC_AlarmStruct->DateWeekValue);
+ assert_param(IS_RTC_ALARM_WEEKDAY_WEEKDAY(tmpregister));
+ }
+ }
+
+ /* Check the input parameters format */
+ if (RTC_Format != RTC_FORMAT_BIN)
+ {
+ tmpregister =
+ (((uint32_t)(RTC_AlarmStruct->AlarmTime.Hours) << 16)
+ | ((uint32_t)(RTC_AlarmStruct->AlarmTime.Minutes) << 8) | ((uint32_t)RTC_AlarmStruct->AlarmTime.Seconds)
+ | ((uint32_t)(RTC_AlarmStruct->AlarmTime.H12) << 16) | ((uint32_t)(RTC_AlarmStruct->DateWeekValue) << 24)
+ | ((uint32_t)RTC_AlarmStruct->DateWeekMode) | ((uint32_t)RTC_AlarmStruct->AlarmMask));
+ }
+ else
+ {
+ tmpregister = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->AlarmTime.Hours) << 16)
+ | ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->AlarmTime.Minutes) << 8)
+ | ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->AlarmTime.Seconds))
+ | ((uint32_t)(RTC_AlarmStruct->AlarmTime.H12) << 16)
+ | ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->DateWeekValue) << 24)
+ | ((uint32_t)RTC_AlarmStruct->DateWeekMode) | ((uint32_t)RTC_AlarmStruct->AlarmMask));
+ }
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Configure the Alarm register */
+ if (RTC_Alarm == RTC_A_ALARM)
+ {
+ RTC->ALARMA = (uint32_t)tmpregister;
+ }
+ else
+ {
+ RTC->ALARMB = (uint32_t)tmpregister;
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Fills each RTC_AlarmStruct member with its default value
+ * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask =
+ * all fields are masked).
+ * @param RTC_AlarmStruct pointer to a @ref RTC_AlarmType structure which
+ * will be initialized.
+ */
+void RTC_AlarmStructInit(RTC_AlarmType* RTC_AlarmStruct)
+{
+ /* Alarm Time Settings : Time = 00h:00mn:00sec */
+ RTC_AlarmStruct->AlarmTime.H12 = RTC_AM_H12;
+ RTC_AlarmStruct->AlarmTime.Hours = 0;
+ RTC_AlarmStruct->AlarmTime.Minutes = 0;
+ RTC_AlarmStruct->AlarmTime.Seconds = 0;
+
+ /* Alarm Date Settings : Date = 1st day of the month */
+ RTC_AlarmStruct->DateWeekMode = RTC_ALARM_SEL_WEEKDAY_DATE;
+ RTC_AlarmStruct->DateWeekValue = 1;
+
+ /* Alarm Masks Settings : Mask = all fields are not masked */
+ RTC_AlarmStruct->AlarmMask = RTC_ALARMMASK_NONE;
+}
+
+/**
+ * @brief Get the RTC Alarm value and masks.
+ * @param RTC_Format specifies the format of the output parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN Binary data format.
+ * @arg RTC_FORMAT_BCD BCD data format.
+ * @param RTC_Alarm specifies the alarm to be read.
+ * This parameter can be one of the following values:
+ * @arg RTC_A_ALARM to select Alarm A.
+ * @arg RTC_B_ALARM to select Alarm B.
+ * @param RTC_AlarmStruct pointer to a RTC_AlarmType structure that will
+ * contains the output alarm configuration values.
+ */
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+ assert_param(IS_RTC_ALARM_SEL(RTC_Alarm));
+
+ /* Get the RTC_ALARMx register */
+ if (RTC_Alarm == RTC_A_ALARM)
+ {
+ tmpregister = (uint32_t)(RTC->ALARMA);
+ }
+ else
+ {
+ tmpregister = (uint32_t)(RTC->ALARMB);
+ }
+
+ /* Fill the structure with the read parameters */
+ RTC_AlarmStruct->AlarmTime.Hours = (uint32_t)((tmpregister & (RTC_ALARMA_HOT | RTC_ALARMA_HOU)) >> 16);
+ RTC_AlarmStruct->AlarmTime.Minutes = (uint32_t)((tmpregister & (RTC_ALARMA_MIT | RTC_ALARMA_MIU)) >> 8);
+ RTC_AlarmStruct->AlarmTime.Seconds = (uint32_t)(tmpregister & (RTC_ALARMA_SET | RTC_ALARMA_SEU));
+ RTC_AlarmStruct->AlarmTime.H12 = (uint32_t)((tmpregister & RTC_ALARMA_APM) >> 16);
+ RTC_AlarmStruct->DateWeekValue = (uint32_t)((tmpregister & (RTC_ALARMA_DTT | RTC_ALARMA_DTU)) >> 24);
+ RTC_AlarmStruct->DateWeekMode = (uint32_t)(tmpregister & RTC_ALARMA_WKDSEL);
+ RTC_AlarmStruct->AlarmMask = (uint32_t)(tmpregister & RTC_ALARMMASK_ALL);
+
+ if (RTC_Format == RTC_FORMAT_BIN)
+ {
+ RTC_AlarmStruct->AlarmTime.Hours = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Hours);
+ RTC_AlarmStruct->AlarmTime.Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Minutes);
+ RTC_AlarmStruct->AlarmTime.Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Seconds);
+ RTC_AlarmStruct->DateWeekValue = RTC_Bcd2ToByte(RTC_AlarmStruct->DateWeekValue);
+ }
+}
+
+/**
+ * @brief Enables or disables the specified RTC Alarm.
+ * @param RTC_Alarm specifies the alarm to be configured.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_A_ALARM to select Alarm A.
+ * @arg RTC_B_ALARM to select Alarm B.
+ * @param Cmd new state of the specified alarm.
+ * This parameter can be: ENABLE or DISABLE.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Alarm is enabled/disabled
+ * - ERROR: RTC Alarm is not enabled/disabled
+ */
+ErrorStatus RTC_EnableAlarm(uint32_t RTC_Alarm, FunctionalState Cmd)
+{
+ __IO uint32_t alarmcounter = 0x00;
+ uint32_t alarmstatus = 0x00;
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALARM_ENABLE(RTC_Alarm));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Configure the Alarm state */
+ if (Cmd != DISABLE)
+ {
+ RTC->CTRL |= (uint32_t)RTC_Alarm;
+
+ status = SUCCESS;
+ }
+ else
+ {
+ /* Disable the Alarm in RTC_CTRL register */
+ RTC->CTRL &= (uint32_t)~RTC_Alarm;
+
+ /* Wait till RTC ALxWF flag is set and if Time out is reached exit */
+ do
+ {
+ alarmstatus = RTC->INITSTS & (RTC_Alarm >> 8);
+ alarmcounter++;
+ } while ((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00));
+
+ if ((RTC->INITSTS & (RTC_Alarm >> 8)) == RESET)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+
+ return status;
+}
+
+/**
+ * @brief Configure the RTC AlarmA/B Subseconds value and mask.*
+ * @note This function is performed only when the Alarm is disabled.
+ * @param RTC_Alarm specifies the alarm to be configured.
+ * This parameter can be one of the following values:
+ * @arg RTC_A_ALARM to select Alarm A.
+ * @arg RTC_B_ALARM to select Alarm B.
+ * @param RTC_AlarmSubSecondValue specifies the Subseconds value.
+ * This parameter can be a value from 0 to 0x00007FFF.
+ * @param RTC_AlarmSubSecondMask specifies the Subseconds Mask.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_SUBS_MASK_ALL All Alarm SS fields are masked.
+ * There is no comparison on sub seconds for Alarm.
+ * @arg RTC_SUBS_MASK_SS14_1 SS[14:1] are don't care in Alarm comparison.
+ * Only SS[0] is compared
+ * @arg RTC_SUBS_MASK_SS14_2 SS[14:2] are don't care in Alarm comparison.
+ * Only SS[1:0] are compared
+ * @arg RTC_SUBS_MASK_SS14_3 SS[14:3] are don't care in Alarm comparison.
+ * Only SS[2:0] are compared
+ * @arg RTC_SUBS_MASK_SS14_4 SS[14:4] are don't care in Alarm comparison.
+ * Only SS[3:0] are compared
+ * @arg RTC_SUBS_MASK_SS14_5 SS[14:5] are don't care in Alarm comparison.
+ * Only SS[4:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_6 SS[14:6] are don't care in Alarm comparison.
+ * Only SS[5:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_7 SS[14:7] are don't care in Alarm comparison.
+ * Only SS[6:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_8 SS[14:8] are don't care in Alarm comparison.
+ * Only SS[7:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_9 SS[14:9] are don't care in Alarm comparison.
+ * Only SS[8:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_10 SS[14:10] are don't care in Alarm comparison.
+ * Only SS[9:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_11 SS[14:11] are don't care in Alarm comparison.
+ * Only SS[10:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_12 SS[14:12] are don't care in Alarm comparison.
+ * Only SS[11:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_13 SS[14:13] are don't care in Alarm comparison.
+ * Only SS[12:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_14 SS[14] is don't care in Alarm comparison.
+ * Only SS[13:0] are compared.
+ * @arg RTC_SUBS_MASK_NONE SS[14:0] are compared and must match
+ * to activate alarm.
+ */
+void RTC_ConfigAlarmSubSecond(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALARM_SEL(RTC_Alarm));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_MASK_MODE(RTC_AlarmSubSecondMask));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Configure the Alarm A or Alarm B SubSecond registers */
+ tmpregister = (uint32_t)(uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask);
+
+ if (RTC_Alarm == RTC_A_ALARM)
+ {
+ /* Configure the AlarmA SubSecond register */
+ RTC->ALRMASS = tmpregister;
+ }
+ else
+ {
+ /* Configure the Alarm B SubSecond register */
+ RTC->ALRMBSS = tmpregister;
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Gets the RTC Alarm Subseconds value.
+ * @param RTC_Alarm specifies the alarm to be read.
+ * This parameter can be one of the following values:
+ * @arg RTC_A_ALARM to select Alarm A.
+ * @arg RTC_B_ALARM to select Alarm B.
+ * @return RTC Alarm Subseconds value.
+ */
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm)
+{
+ uint32_t tmpregister = 0;
+
+ /* Get the RTC_ALARMx register */
+ if (RTC_Alarm == RTC_A_ALARM)
+ {
+ tmpregister = (uint32_t)((RTC->ALRMASS) & RTC_ALRMASS_SSV);
+ }
+ else
+ {
+ tmpregister = (uint32_t)((RTC->ALRMBSS) & RTC_ALRMBSS_SSV);
+ }
+
+ return (tmpregister);
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group4 WakeUp Timer configuration functions
+ * @brief WakeUp Timer configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### WakeUp Timer configuration functions #####
+ ===============================================================================
+ [..] This section provide functions allowing to program and read the RTC WakeUp.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the RTC Wakeup clock source.
+ * @note The WakeUp Clock source can only be changed when the RTC WakeUp
+ * is disabled (Use the RTC_EnableWakeUp(DISABLE)).
+ * @param RTC_WakeUpClock Wakeup Clock source.
+ * This parameter can be one of the following values:
+ * @arg RTC_WKUPCLK_RTCCLK_DIV16 RTC Wakeup Counter Clock = RTCCLK/16.
+ * @arg RTC_WKUPCLK_RTCCLK_DIV8 RTC Wakeup Counter Clock = RTCCLK/8.
+ * @arg RTC_WKUPCLK_RTCCLK_DIV4 RTC Wakeup Counter Clock = RTCCLK/4.
+ * @arg RTC_WKUPCLK_RTCCLK_DIV2 RTC Wakeup Counter Clock = RTCCLK/2.
+ * @arg RTC_WKUPCLK_CK_SPRE_16BITS RTC Wakeup Counter Clock = CK_SPRE.
+ * @arg RTC_WKUPCLK_CK_SPRE_17BITS RTC Wakeup Counter Clock = CK_SPRE.
+ */
+void RTC_ConfigWakeUpClock(uint32_t RTC_WakeUpClock)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_WKUP_CLOCK(RTC_WakeUpClock));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Clear the Wakeup Timer clock source bits in CTRL register */
+ RTC->CTRL &= (uint32_t)~RTC_CTRL_WKUPSEL;
+
+ /* Configure the clock source */
+ RTC->CTRL |= (uint32_t)RTC_WakeUpClock;
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Configures the RTC Wakeup counter.
+ * @note The RTC WakeUp counter can only be written when the RTC WakeUp.
+ * is disabled (Use the RTC_EnableWakeUp(DISABLE)).
+ * @param RTC_WakeUpCounter specifies the WakeUp counter.
+ * This parameter can be a value from 0x0000 to 0xFFFF.
+ */
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_WKUP_COUNTER(RTC_WakeUpCounter));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Configure the Wakeup Timer counter */
+ RTC->WKUPT = (uint32_t)RTC_WakeUpCounter;
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Returns the RTC WakeUp timer counter value.
+ * @return The RTC WakeUp Counter value.
+ */
+uint32_t RTC_GetWakeUpCounter(void)
+{
+ /* Get the counter value */
+ return ((uint32_t)(RTC->WKUPT & RTC_WKUPT_WKUPT));
+}
+
+/**
+ * @brief Enables or Disables the RTC WakeUp timer.
+ * @param Cmd new state of the WakeUp timer.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+ErrorStatus RTC_EnableWakeUp(FunctionalState Cmd)
+{
+ __IO uint32_t wutcounter = 0x00;
+ uint32_t wutwfstatus = 0x00;
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the Wakeup Timer */
+ RTC->CTRL |= (uint32_t)RTC_CTRL_WTEN;
+ status = SUCCESS;
+ }
+ else
+ {
+ /* Disable the Wakeup Timer */
+ RTC->CTRL &= (uint32_t)~RTC_CTRL_WTEN;
+ /* Wait till RTC WTWF flag is set and if Time out is reached exit */
+ do
+ {
+ wutwfstatus = RTC->INITSTS & RTC_INITSTS_WTWF;
+ wutcounter++;
+ } while ((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
+
+ if ((RTC->INITSTS & RTC_INITSTS_WTWF) == RESET)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group5 Daylight Saving configuration functions
+ * @brief Daylight Saving configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Daylight Saving configuration functions #####
+ ===============================================================================
+ [..] This section provide functions allowing to configure the RTC DayLight Saving.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Adds or substract one hour from the current time.
+ * @param RTC_DayLightSaving the value of hour adjustment.
+ * This parameter can be one of the following values:
+ * @arg RTC_DAYLIGHT_SAVING_SUB1H Substract one hour (winter time).
+ * @arg RTC_DAYLIGHT_SAVING_ADD1H Add one hour (summer time).
+ * @param RTC_StoreOperation Specifies the value to be written in the BCK bit
+ * in CTRL register to store the operation.
+ * This parameter can be one of the following values:
+ * @arg RTC_STORE_OPERATION_RESET BCK Bit Reset.
+ * @arg RTC_STORE_OPERATION_SET BCK Bit Set.
+ */
+void RTC_ConfigDayLightSaving(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving));
+ assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Clear the bits to be configured */
+ RTC->CTRL &= (uint32_t) ~(RTC_CTRL_BAKP);
+ /* Clear the SU1H and AD1H bits to be configured */
+ RTC->CTRL &= (uint32_t) ~(RTC_CTRL_SU1H & RTC_CTRL_AD1H);
+ /* Configure the RTC_CTRL register */
+ RTC->CTRL |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation);
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Returns the RTC Day Light Saving stored operation.
+ * @return RTC Day Light Saving stored operation.
+ * - RTC_STORE_OPERATION_RESET
+ * - RTC_STORE_OPERATION_SET
+ */
+uint32_t RTC_GetStoreOperation(void)
+{
+ return (RTC->CTRL & RTC_CTRL_BAKP);
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group6 Output pin Configuration function
+ * @brief Output pin Configuration function
+ *
+@verbatim
+ ===============================================================================
+ ##### Output pin Configuration function #####
+ ===============================================================================
+ [..] This section provide functions allowing to configure the RTC Output source.
+
+@endverbatim
+ * @{
+ */
+
+
+
+/**
+ * @brief Configures the RTC output source (AFO_ALARM).
+ * @param RTC_Output Specifies which signal will be routed to the RTC output.
+ * This parameter can be one of the following values:
+ * @arg RTC_OUTPUT_DIS No output selected
+ * @arg RTC_OUTPUT_ALA signal of AlarmA mapped to output.
+ * @arg RTC_OUTPUT_ALB signal of AlarmB mapped to output.
+ * @arg RTC_OUTPUT_WKUP signal of WakeUp mapped to output.
+ * @param RTC_OutputPolarity Specifies the polarity of the output signal.
+ * This parameter can be one of the following:
+ * @arg RTC_OUTPOL_HIGH The output pin is high when the
+ * ALRAF/ALRBF/WUTF is high (depending on OSEL).
+ * @arg RTC_OUTPOL_LOW The output pin is low when the
+ * ALRAF/ALRBF/WUTF is high (depending on OSEL).
+ */
+void RTC_ConfigOutput(uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_OUTPUT_MODE(RTC_Output));
+ assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Clear the bits to be configured */
+ RTC->CTRL &= (uint32_t) ~(RTC_CTRL_OUTSEL | RTC_CTRL_OPOL);
+
+ /* Configure the output selection and polarity */
+ RTC->CTRL |= (uint32_t)(RTC_Output | RTC_OutputPolarity);
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group7 Coarse and Smooth Calibrations configuration functions
+ * @brief Coarse and Smooth Calibrations configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Coarse and Smooth Calibrations configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the RTC clock to be output through the relative
+ * pin.
+ * @param Cmd new state of the coarse calibration Output.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RTC_EnableCalibOutput(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the RTC clock output */
+ RTC->CTRL |= (uint32_t)RTC_CTRL_COEN;
+ }
+ else
+ {
+ /* Disable the RTC clock output */
+ RTC->CTRL &= (uint32_t)~RTC_CTRL_COEN;
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ * @param RTC_CalibOutput Select the Calibration output Selection .
+ * This parameter can be one of the following values:
+ * @arg RTC_CALIB_OUTPUT_256HZ A signal has a regular waveform at 256Hz.
+ * @arg RTC_CALIB_OUTPUT_1HZ A signal has a regular waveform at 1Hz.
+ */
+void RTC_ConfigCalibOutput(uint32_t RTC_CalibOutput)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /*clear flags before config*/
+ RTC->CTRL &= (uint32_t) ~(RTC_CTRL_CALOSEL);
+
+ /* Configure the RTC_CTRL register */
+ RTC->CTRL |= (uint32_t)RTC_CalibOutput;
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Configures the Smooth Calibration Settings.
+ * @param RTC_SmoothCalibPeriod Select the Smooth Calibration Period.
+ * This parameter can be can be one of the following values:
+ * @arg SMOOTH_CALIB_32SEC The smooth calibration periode is 32s.
+ * @arg SMOOTH_CALIB_16SEC The smooth calibration periode is 16s.
+ * @arg SMOOTH_CALIB_8SEC The smooth calibartion periode is 8s.
+ * @param RTC_SmoothCalibPlusPulses Select to Set or reset the CALP bit.
+ * This parameter can be one of the following values:
+ * @arg RTC_SMOOTH_CALIB_PLUS_PULSES_SET Add one RTCCLK puls every 2**11 pulses.
+ * @arg RTC_SMOOTH_CALIB_PLUS_PULSES__RESET No RTCCLK pulses are added.
+ * @param RTC_SmouthCalibMinusPulsesValue Select the value of CALM[8:0] bits.
+ * This parameter can be one any value from 0 to 0x000001FF.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Calib registers are configured
+ * - ERROR: RTC Calib registers are not configured
+ */
+ErrorStatus RTC_ConfigSmoothCalib(uint32_t RTC_SmoothCalibPeriod,
+ uint32_t RTC_SmoothCalibPlusPulses,
+ uint32_t RTC_SmouthCalibMinusPulsesValue)
+{
+ ErrorStatus status = ERROR;
+ uint32_t recalpfcount = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_SMOOTH_CALIB_PERIOD_SEL(RTC_SmoothCalibPeriod));
+ assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses));
+ assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* check if a calibration is pending*/
+ if ((RTC->INITSTS & RTC_INITSTS_RECPF) != RESET)
+ {
+ /* wait until the Calibration is completed*/
+ while (((RTC->INITSTS & RTC_INITSTS_RECPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT))
+ {
+ recalpfcount++;
+ }
+ }
+
+ /* check if the calibration pending is completed or if there is no calibration operation at all*/
+ if ((RTC->INITSTS & RTC_INITSTS_RECPF) == RESET)
+ {
+ /* Configure the Smooth calibration settings */
+ RTC->CALIB = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses
+ | (uint32_t)RTC_SmouthCalibMinusPulsesValue);
+
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+
+ return (ErrorStatus)(status);
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group8 TimeStamp configuration functions
+ * @brief TimeStamp configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### TimeStamp configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or Disables the RTC TimeStamp functionality with the
+ * specified time stamp pin stimulating edge.
+ * @param RTC_TimeStampEdge Specifies the pin edge on which the TimeStamp is
+ * activated.
+ * This parameter can be one of the following:
+ * @arg RTC_TIMESTAMP_EDGE_RISING the Time stamp event occurs on the rising
+ * edge of the related pin.
+ * @arg RTC_TIMESTAMP_EDGE_FALLING the Time stamp event occurs on the
+ * falling edge of the related pin.
+ * @param Cmd new state of the TimeStamp.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RTC_EnableTimeStamp(uint32_t RTC_TimeStampEdge, FunctionalState Cmd)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_TIMESTAMP_EDGE_MODE(RTC_TimeStampEdge));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ /* Get the RTC_CTRL register and clear the bits to be configured */
+ tmpregister = (uint32_t)(RTC->CTRL & (uint32_t) ~(RTC_CTRL_TEDGE | RTC_CTRL_TSEN));
+
+ /* Get the new configuration */
+ if (Cmd != DISABLE)
+ {
+ tmpregister |= (uint32_t)(RTC_TimeStampEdge | RTC_CTRL_TSEN);
+ }
+ else
+ {
+ tmpregister |= (uint32_t)(RTC_TimeStampEdge);
+ }
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Configure the Time Stamp TSEDGE and Enable bits */
+ RTC->CTRL = (uint32_t)tmpregister;
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Get the RTC TimeStamp value and masks.
+ * @param RTC_Format specifies the format of the output parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN Binary data format
+ * @arg RTC_FORMAT_BCD BCD data format
+ * @param RTC_StampTimeStruct pointer to a RTC_TimeType structure that will
+ * contains the TimeStamp time values.
+ * @param RTC_StampDateStruct pointer to a RTC_DateType structure that will
+ * contains the TimeStamp date values.
+ */
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeType* RTC_StampTimeStruct, RTC_DateType* RTC_StampDateStruct)
+{
+ uint32_t tmptime = 0, tmpdate = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+
+ /* Get the TimeStamp time and date registers values */
+ tmptime = (uint32_t)(RTC->TST & RTC_TR_RESERVED_MASK);
+ tmpdate = (uint32_t)(RTC->TSD & RTC_DATE_RESERVED_MASK);
+
+ /* Fill the Time structure fields with the read parameters */
+ RTC_StampTimeStruct->Hours = (uint8_t)((tmptime & (RTC_TSH_HOT | RTC_TSH_HOU)) >> 16);
+ RTC_StampTimeStruct->Minutes = (uint8_t)((tmptime & (RTC_TSH_MIT | RTC_TSH_MIU)) >> 8);
+ RTC_StampTimeStruct->Seconds = (uint8_t)(tmptime & (RTC_TSH_SCT | RTC_TSH_SCU));
+ RTC_StampTimeStruct->H12 = (uint8_t)((tmptime & (RTC_TSH_APM)) >> 16);
+
+ /* Fill the Date structure fields with the read parameters */
+ RTC_StampDateStruct->Year = (uint8_t)((tmpdate & (RTC_DATE_YRT | RTC_DATE_YRU)) >> 16);
+ RTC_StampDateStruct->Month = (uint8_t)((tmpdate & (RTC_DATE_MOT | RTC_DATE_MOU)) >> 8);
+ RTC_StampDateStruct->Date = (uint8_t)(tmpdate & (RTC_DATE_DAT | RTC_DATE_DAU));
+ RTC_StampDateStruct->WeekDay = (uint8_t)((tmpdate & (RTC_DATE_WDU)) >> 13);
+
+ /* Check the input parameters format */
+ if (RTC_Format == RTC_FORMAT_BIN)
+ {
+ /* Convert the Time structure parameters to Binary format */
+ RTC_StampTimeStruct->Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->Hours);
+ RTC_StampTimeStruct->Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->Minutes);
+ RTC_StampTimeStruct->Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->Seconds);
+
+ /* Convert the Date structure parameters to Binary format */
+ RTC_StampDateStruct->Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->Month);
+ RTC_StampDateStruct->Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->Date);
+ RTC_StampDateStruct->WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->WeekDay);
+ }
+}
+
+/**
+ * @brief Get the RTC timestamp Subseconds value.
+ * @return RTC current timestamp Subseconds value.
+ */
+uint32_t RTC_GetTimeStampSubSecond(void)
+{
+ /* Get timestamp subseconds values from the correspondent registers */
+ return (uint32_t)(RTC->TSSS);
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group11 Output Type Config configuration functions
+ * @brief Output Type Config configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Output Type Config configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the RTC Output Pin mode.
+ * @param RTC_OutputType specifies the RTC Output (PC13) pin mode.
+ * This parameter can be one of the following values:
+ * @arg RTC_OUTPUT_OPENDRAIN RTC Output (PC13) is configured in
+ * Open Drain mode.
+ * @arg RTC_OUTPUT_PUSHPULL RTC Output (PC13) is configured in
+ * Push Pull mode.
+ */
+void RTC_ConfigOutputType(uint32_t RTC_OutputType)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType));
+
+ RTC->OPT &= (uint32_t) ~(RTC_OPT_TYPE);
+ RTC->OPT |= (uint32_t)(RTC_OutputType);
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group12 Shift control synchronisation functions
+ * @brief Shift control synchronisation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Shift control synchronisation functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the Synchronization Shift Control Settings.
+ * @note When REFCKON is set, firmware must not write to Shift control register
+ * @param RTC_ShiftAdd1S Select to add or not 1 second to the time Calendar.
+ * This parameter can be one of the following values :
+ * @arg RTC_SHIFT_ADD1S_ENABLE Add one second to the clock calendar.
+ * @arg RTC_SHIFT_ADD1S_DISABLE No effect.
+ * @param RTC_ShiftSubFS Select the number of Second Fractions to Substitute.
+ * This parameter can be one any value from 0 to 0x7FFF.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Shift registers are configured
+ * - ERROR: RTC Shift registers are not configured
+ */
+ErrorStatus RTC_ConfigSynchroShift(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS)
+{
+ ErrorStatus status = ERROR;
+ uint32_t shpfcount = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S));
+ assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Check if a Shift is pending*/
+ if ((RTC->INITSTS & RTC_INITSTS_SHOPF) != RESET)
+ {
+ /* Wait until the shift is completed*/
+ while (((RTC->INITSTS & RTC_INITSTS_SHOPF) != RESET) && (shpfcount != SHPF_TIMEOUT))
+ {
+ shpfcount++;
+ }
+ }
+
+ /* Check if the Shift pending is completed or if there is no Shift operation at all*/
+ if ((RTC->INITSTS & RTC_INITSTS_SHOPF) == RESET)
+ {
+ /* check if the reference clock detection is disabled */
+ if ((RTC->CTRL & RTC_CTRL_REFCLKEN) == RESET)
+ {
+ /* Configure the Shift settings */
+ RTC->SCTRL = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S);
+
+ if (RTC_WaitForSynchro() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ else
+ {
+ status = ERROR;
+ }
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+
+ return (ErrorStatus)(status);
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group13 Interrupts and flags management functions
+ * @brief Interrupts and flags management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupts and flags management functions #####
+ ===============================================================================
+ [..] All RTC interrupts are connected to the EXTI controller.
+ (+) To enable the RTC Alarm interrupt, the following sequence is required:
+ (+) Configure and enable the EXTI Line 17 in interrupt mode and select
+ the rising edge sensitivity using the EXTI_InitPeripheral() function.
+ (+) Configure and enable the RTC_Alarm IRQ channel in the NVIC using
+ the NVIC_Init() function.
+ (+) Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B)
+ using the RTC_SetAlarm() and RTC_EnableAlarm() functions.
+
+ (+) To enable the RTC Wakeup interrupt, the following sequence is required:
+ (+) Configure and enable the EXTI Line 20 in interrupt mode and select
+ the rising edge sensitivity using the EXTI_InitPeripheral() function.
+ (+) Configure and enable the RTC_WKUP IRQ channel in the NVIC using the
+ NVIC_Init() function.
+ (+) Configure the RTC to generate the RTC wakeup timer event using the
+ RTC_ConfigWakeUpClock(), RTC_SetWakeUpCounter() and RTC_EnableWakeUp()
+ functions.
+
+ (+) To enable the RTC Tamper interrupt, the following sequence is required:
+ (+) Configure and enable the EXTI Line 19 in interrupt mode and select
+ the rising edge sensitivity using the EXTI_InitPeripheral() function.
+ (+) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using
+ the NVIC_Init() function.
+ (+) Configure the RTC to detect the RTC tamper event using the
+ RTC_TamperTriggerConfig() and RTC_TamperCmd() functions.
+
+ (+) To enable the RTC TimeStamp interrupt, the following sequence is
+ required:
+ (+) Configure and enable the EXTI Line 19 in interrupt mode and select
+ the rising edge sensitivity using the EXTI_InitPeripheral() function.
+ (+) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using
+ the NVIC_Init() function.
+ (+) Configure the RTC to detect the RTC time-stamp event using the
+ RTC_EnableTimeStamp() functions.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the specified RTC interrupts.
+ * @param RTC_INT specifies the RTC interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_INT_TS Time Stamp interrupt mask.
+ * @arg RTC_INT_WUT WakeUp Timer interrupt mask.
+ * @arg RTC_INT_ALRB Alarm B interrupt mask.
+ * @arg RTC_INT_ALRA Alarm A interrupt mask.
+ * @param Cmd new state of the specified RTC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RTC_ConfigInt(uint32_t RTC_INT, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_CONFIG_INT(RTC_INT));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ if (Cmd != DISABLE)
+ {
+ /* Configure the Interrupts in the RTC_CTRL register */
+ RTC->CTRL |= (uint32_t)(RTC_INT & ~RTC_TMPCFG_TPINTEN);
+ }
+ else
+ {
+ /* Configure the Interrupts in the RTC_CTRL register */
+ RTC->CTRL &= (uint32_t) ~(RTC_INT & (uint32_t)~RTC_TMPCFG_TPINTEN);
+ }
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Checks whether the specified RTC flag is set or not.
+ * @param RTC_FLAG specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg RTC_FLAG_RECPF RECALPF event flag.
+ * @arg RTC_FLAG_TAMP3F: Tamper 3 event flag.
+ * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag.
+ * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag.
+ * @arg RTC_FLAG_TISOVF Time Stamp OverFlow flag.
+ * @arg RTC_FLAG_TISF Time Stamp event flag.
+ * @arg RTC_FLAG_WTF WakeUp Timer flag.
+ * @arg RTC_FLAG_ALBF Alarm B flag.
+ * @arg RTC_FLAG_ALAF Alarm A flag.
+ * @arg RTC_FLAG_INITF Initialization mode flag.
+ * @arg RTC_FLAG_RSYF Registers Synchronized flag.
+ * @arg RTC_FLAG_INITSF Registers Configured flag.
+ * @arg RTC_FLAG_SHOPF Shift operation pending flag.
+ * @arg RTC_FLAG_WTWF WakeUp Timer Write flag.
+ * @arg RTC_FLAG_ALBWF Alarm B Write flag.
+ * @arg RTC_FLAG_ALAWF Alarm A write flag.
+ * @return The new state of RTC_FLAG (SET or RESET).
+ */
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
+
+ /* Get all the flags */
+ tmpregister = (uint32_t)(RTC->INITSTS & RTC_FLAGS_MASK);
+
+ /* Return the status of the flag */
+ if ((tmpregister & RTC_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RTC's pending flags.
+ * @param RTC_FLAG specifies the RTC flag to clear.
+ * This parameter can be any combination of the following values:.
+ * @arg RTC_FLAG_TAMP3F: Tamper 3 event flag.
+ * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag.
+ * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag.
+ * @arg RTC_FLAG_TISOVF Time Stamp Overflow flag.
+ * @arg RTC_FLAG_TISF Time Stamp event flag.
+ * @arg RTC_FLAG_WTF WakeUp Timer flag.
+ * @arg RTC_FLAG_ALBF Alarm B flag.
+ * @arg RTC_FLAG_ALAF Alarm A flag.
+ * @arg RTC_FLAG_RSYF Registers Synchronized flag.
+ */
+void RTC_ClrFlag(uint32_t RTC_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
+
+ /* Clear the Flags in the RTC_INITSTS register */
+ RTC->INITSTS = (uint32_t)(
+ (uint32_t)(~((RTC_FLAG | RTC_INITSTS_INITM) & 0x0001FFFF) | (uint32_t)(RTC->INITSTS & RTC_INITSTS_INITM)));
+}
+
+/**
+ * @brief Checks whether the specified RTC interrupt has occurred or not.
+ * @param RTC_INT specifies the RTC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg RTC_INT_TS Time Stamp interrupt.
+ * @arg RTC_INT_WUT WakeUp Timer interrupt.
+ * @arg RTC_INT_ALRB Alarm B interrupt.
+ * @arg RTC_INT_ALRA Alarm A interrupt.
+ * @return The new state of RTC_INT (SET or RESET).
+ */
+INTStatus RTC_GetITStatus(uint32_t RTC_INT)
+{
+ INTStatus bitstatus = RESET;
+ uint32_t tmpregister = 0, enablestatus = 0;
+ uint8_t tamperEnable = 0;
+ /* Check the parameters */
+ assert_param(IS_RTC_GET_INT(RTC_INT));
+
+ /* Get the Interrupt enable Status */
+ if ((RTC_INT == RTC_INT_TAMP1) || (RTC_INT == RTC_INT_TAMP2)|| (RTC_INT == RTC_INT_TAMP3))
+ {
+ tamperEnable = ((RTC->TMPCFG & 0x00ff0000)>>16);
+ if (tamperEnable > 0)
+ {
+ enablestatus = SET;
+ }
+
+ }
+ else
+ {
+ enablestatus = (uint32_t)((RTC->CTRL & RTC_INT));
+
+ }
+ /* Get the Interrupt pending bit */
+ tmpregister = (uint32_t)((RTC->INITSTS & (uint32_t)(RTC_INT >> 4)));
+
+ /* Get the status of the Interrupt */
+ if ((enablestatus != (uint32_t)RESET) && ((tmpregister & 0x0000FFFF) != (uint32_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RTC's interrupt pending bits.
+ * @param RTC_INT specifies the RTC interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_INT_TS Time Stamp interrupt
+ * @arg RTC_INT_WUT WakeUp Timer interrupt
+ * @arg RTC_INT_ALRB Alarm B interrupt
+ * @arg RTC_INT_ALRA Alarm A interrupt
+ */
+void RTC_ClrIntPendingBit(uint32_t RTC_INT)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_CLEAR_INT(RTC_INT));
+
+ /* Get the RTC_INITSTS Interrupt pending bits mask */
+ tmpregister = (uint32_t)(RTC_INT >> 4);
+
+ /* Clear the interrupt pending bits in the RTC_INITSTS register */
+ RTC->INITSTS = (uint32_t)(
+ (uint32_t)(~((tmpregister | RTC_INITSTS_INITM) & 0x0000FFFF) | (uint32_t)(RTC->INITSTS & RTC_INITSTS_INITM)));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief Converts a 2 digit decimal to BCD format.
+ * @param Value Byte to be converted.
+ * @return Converted byte
+ */
+static uint8_t RTC_ByteToBcd2(uint8_t Value)
+{
+ uint8_t bcdhigh = 0;
+
+ while (Value >= 10)
+ {
+ bcdhigh++;
+ Value -= 10;
+ }
+
+ return ((uint8_t)(bcdhigh << 4) | Value);
+}
+
+/**
+ * @brief Convert from 2 digit BCD to Binary.
+ * @param Value BCD value to be converted.
+ * @return Converted word
+ */
+static uint8_t RTC_Bcd2ToByte(uint8_t Value)
+{
+ uint8_t tmp = 0;
+ tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
+ return (tmp + (Value & (uint8_t)0x0F));
+}
+/**
+ * @brief Enable wakeup tsc functionand wakeup by the set time
+ * @param count wakeup time.
+ */
+void RTC_EnableWakeUpTsc(uint32_t count)
+{
+ // Wait until bit RTC_TSCWKUPCTRL_WKUPOFF is 1
+ while (!(RTC->TSCWKUPCTRL & RTC_TSCWKUPCTRL_WKUPOFF))
+ {
+ }
+ // enter config wakeup cnt mode
+ RTC->TSCWKUPCTRL = RTC_TSCWKUPCTRL_WKUPCNF;
+ // config tsc wakeup cnt ,tsc wakeup module counting cycle = WAKUPCNT * LSE/LSI
+ RTC->TSCWKUPCNT = count;
+ // exit config wakeup cnt mode
+ RTC->TSCWKUPCTRL &= ~(RTC_TSCWKUPCTRL_WKUPCNF);
+ while (!(RTC->TSCWKUPCTRL & RTC_TSCWKUPCTRL_WKUPOFF))
+ {
+ }
+ // TSC wakeup enable
+ RTC->TSCWKUPCTRL = RTC_TSCWKUPCTRL_WKUPEN;
+}
+
+/** @defgroup RTC_Group9 Tampers configuration functions
+ * @brief Tampers configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Tampers configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the select Tamper pin edge.
+ * @param RTC_Tamper: Selected tamper pin.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_Tamper_1: Select Tamper 1.
+ * @arg RTC_Tamper_2: Select Tamper 2.
+ * @arg RTC_Tamper_3: Select Tamper 3.
+ * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that
+ * stimulates tamper event.
+ * This parameter can be one of the following values:
+ * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event.
+ * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event.
+ * @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event.
+ * @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event.
+ * @retval None
+ */
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER(RTC_Tamper));
+ assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger));
+ if (RTC_Tamper == RTC_TAMPER_3)
+ {
+ RTC_TamperTrigger <<= 5;
+ }
+ else if (RTC_Tamper == RTC_TAMPER_2)
+ {
+ RTC_TamperTrigger <<= 3;
+ }
+ /* Configure the RTC_TAMPCR register */
+ RTC->TMPCFG |= (uint32_t)(RTC_Tamper | RTC_TamperTrigger);
+
+}
+
+/**
+ * @brief Enables or Disables the Tamper detection.
+ * @param RTC_Tamper: Selected tamper pin.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_TAMPER_1: Select Tamper 1.
+ * @arg RTC_TAMPER_2: Select Tamper 2.
+ * @arg RTC_TAMPER_3: Select Tamper 3.
+ * @param NewState: new state of the tamper pin.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER(RTC_Tamper));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected Tamper pin */
+ RTC->TMPCFG |= (uint32_t)RTC_Tamper;
+ }
+ else
+ {
+ /* Disable the selected Tamper pin */
+ RTC->TMPCFG &= (uint32_t)~RTC_Tamper;
+ }
+}
+
+/**
+ * @brief Configures the Tampers Filter.
+ * @param RTC_TamperFilter: Specifies the tampers filter.
+ * This parameter can be one of the following values:
+ * @arg RTC_TamperFilter_Disable: Tamper filter is disabled.
+ * @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive
+ * samples at the active level.
+ * @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive
+ * samples at the active level.
+ * @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive
+ * samples at the active level.
+ * @retval None
+ */
+void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter));
+
+ /* Clear TAMPFLT[1:0] bits in the RTC_TAMPCR register */
+ RTC->TMPCFG &= (uint32_t)~(RTC_TMPCFG_TPFLT);
+
+ /* Configure the RTC_TAMPCR register */
+ RTC->TMPCFG |= (uint32_t)RTC_TamperFilter;
+}
+
+/**
+ * @brief Configures the Tampers Sampling Frequency.
+ * @param RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency.
+ * This parameter can be one of the following values:
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 32768
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 16384
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 8192
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 4096
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 2048
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 1024
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 512
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 256
+ * @retval None
+ */
+void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq));
+
+ /* Clear TAMPFREQ[2:0] bits in the RTC_TAMPCR register */
+ RTC->TMPCFG &= (uint32_t)~(RTC_TAMPCR_TAMPFREQ);
+
+ /* Configure the RTC_TAMPCR register */
+ RTC->TMPCFG |= (uint32_t)RTC_TamperSamplingFreq;
+}
+
+/**
+ * @brief Configures the Tampers Pins input Precharge Duration.
+ * @param RTC_TamperPrechargeDuration: Specifies the Tampers Pins input
+ * Precharge Duration.
+ * This parameter can be one of the following values:
+ * @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle.
+ * @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle.
+ * @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle.
+ * @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle.
+ * @retval None
+ */
+void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration));
+
+ /* Clear TAMPPRCH[1:0] bits in the RTC_TAMPCR register */
+ RTC->TMPCFG &= (uint32_t)~(RTC_TMPCFG_TPPRCH);
+
+ /* Configure the RTC_TAMPCR register */
+ RTC->TMPCFG |= (uint32_t)RTC_TamperPrechargeDuration;
+}
+
+/**
+ * @brief Enables or Disables the TimeStamp on Tamper Detection Event.
+ * @note The timestamp is valid even the TSEN bit in tamper control register
+ * is reset.
+ * @param NewState: new state of the timestamp on tamper event.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Save timestamp on tamper detection event */
+ RTC->TMPCFG |= (uint32_t)RTC_TMPCFG_TPTS;
+ }
+ else
+ {
+ /* Tamper detection does not cause a timestamp to be saved */
+ RTC->TMPCFG &= (uint32_t)~RTC_TMPCFG_TPTS;
+ }
+}
+
+/**
+ * @brief Enables or Disables the Precharge of Tamper pin.
+ * @param NewState: new state of tamper pull up.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RTC_TamperPullUpCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable precharge of the selected Tamper pin */
+ RTC->TMPCFG &= (uint32_t)~RTC_TMPCFG_TPPUDIS;
+ }
+ else
+ {
+ /* Disable precharge of the selected Tamper pin */
+ RTC->TMPCFG |= (uint32_t)RTC_TMPCFG_TPPUDIS;
+ }
+}
+
+/**
+ * @brief Enables or Disables the TAMPTS.
+ * @param NewState: new state of TAMPTS.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RTC_TamperTAMPTSCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable precharge of the selected Tamper pin */
+ RTC->TMPCFG |= (uint32_t)RTC_TMPCFG_TPTS;
+ }
+ else
+ {
+ /* Disable precharge of the selected Tamper pin */
+ RTC->TMPCFG &= (uint32_t)~RTC_TMPCFG_TPTS;
+ }
+}
+
+/**
+ * @brief Enables or Disables the Tamper detection.
+ * @param RTC_Tamper: Selected tamper pin.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_TAMPER1_INT: Select Tamper 1.
+ * @arg RTC_TAMPER2_INT: Select Tamper 2.
+ * @arg RTC_TAMPER3_INT: Select Tamper 3.
+ * @param NewState: new state of the tamper pin.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RTC_TamperIECmd(uint32_t TAMPxIE, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER(TAMPxIE));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected Tamper pin */
+ RTC->TMPCFG |= (uint32_t)TAMPxIE;
+ }
+ else
+ {
+ /* Disable the selected Tamper pin */
+ RTC->TMPCFG &= (uint32_t)~TAMPxIE;
+ }
+}
+
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_spi.c b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_spi.c
new file mode 100644
index 0000000000..961acd7a84
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_spi.c
@@ -0,0 +1,853 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_spi.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l40x_spi.h"
+#include "n32l40x_rcc.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @brief SPI driver modules
+ * @{
+ */
+
+/** @addtogroup SPI_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_Defines
+ * @{
+ */
+
+/* SPI SPIEN mask */
+#define CTRL1_SPIEN_ENABLE ((uint16_t)0x0040)
+#define CTRL1_SPIEN_DISABLE ((uint16_t)0xFFBF)
+
+/* I2S I2SEN mask */
+#define I2SCFG_I2SEN_ENABLE ((uint16_t)0x0400)
+#define I2SCFG_I2SEN_DISABLE ((uint16_t)0xFBFF)
+
+/* SPI CRCNEXT mask */
+#define CTRL1_CRCNEXT_ENABLE ((uint16_t)0x1000)
+
+/* SPI CRCEN mask */
+#define CTRL1_CRCEN_ENABLE ((uint16_t)0x2000)
+#define CTRL1_CRCEN_DISABLE ((uint16_t)0xDFFF)
+
+/* SPI SSOE mask */
+#define CTRL2_SSOEN_ENABLE ((uint16_t)0x0004)
+#define CTRL2_SSOEN_DISABLE ((uint16_t)0xFFFB)
+
+/* SPI registers Masks */
+#define CTRL1_CLR_MASK ((uint16_t)0x3040)
+#define I2SCFG_CLR_MASK ((uint16_t)0xF040)
+
+/* SPI or I2S mode selection masks */
+#define SPI_MODE_ENABLE ((uint16_t)0xF7FF)
+#define I2S_MODE_ENABLE ((uint16_t)0x0800)
+
+/* I2S clock source selection masks */
+#define I2S1_CLKSRC ((uint32_t)(0x00020000))
+#define I2S2_CLKSRC ((uint32_t)(0x00040000))
+#define I2S_MUL_MASK ((uint32_t)(0x0000F000))
+#define I2S_DIV_MASK ((uint32_t)(0x000000F0))
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the SPIx peripheral registers to their default
+ * reset values (Affects also the I2Ss).
+ * @param SPIx where x can be 1, 2 to select the SPI peripheral.
+ */
+void SPI_I2S_DeInit(SPI_Module* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+
+ if (SPIx == SPI1)
+ {
+ /* Enable SPI1 reset state */
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI1, ENABLE);
+ /* Release SPI1 from reset state */
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI1, DISABLE);
+ }
+ else if (SPIx == SPI2)
+ {
+ /* Enable SPI2 reset state */
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI2, ENABLE);
+ /* Release SPI2 from reset state */
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI2, DISABLE);
+ }
+
+}
+
+/**
+ * @brief Initializes the SPIx peripheral according to the specified
+ * parameters in the SPI_InitStruct.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param SPI_InitStruct pointer to a SPI_InitType structure that
+ * contains the configuration information for the specified SPI peripheral.
+ */
+void SPI_Init(SPI_Module* SPIx, SPI_InitType* SPI_InitStruct)
+{
+ uint16_t tmpregister = 0;
+
+ /* check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+
+ /* Check the SPI parameters */
+ assert_param(IS_SPI_DIR_MODE(SPI_InitStruct->DataDirection));
+ assert_param(IS_SPI_MODE(SPI_InitStruct->SpiMode));
+ assert_param(IS_SPI_DATASIZE(SPI_InitStruct->DataLen));
+ assert_param(IS_SPI_CLKPOL(SPI_InitStruct->CLKPOL));
+ assert_param(IS_SPI_CLKPHA(SPI_InitStruct->CLKPHA));
+ assert_param(IS_SPI_NSS(SPI_InitStruct->NSS));
+ assert_param(IS_SPI_BR_PRESCALER(SPI_InitStruct->BaudRatePres));
+ assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->FirstBit));
+ assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
+
+ /*---------------------------- SPIx CTRL1 Configuration ------------------------*/
+ /* Get the SPIx CTRL1 value */
+ tmpregister = SPIx->CTRL1;
+ /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
+ tmpregister &= CTRL1_CLR_MASK;
+ /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
+ master/salve mode, CPOL and CPHA */
+ /* Set BIDImode, BIDIOE and RxONLY bits according to DataDirection value */
+ /* Set SSM, SSI and MSTR bits according to SpiMode and NSS values */
+ /* Set LSBFirst bit according to FirstBit value */
+ /* Set BR bits according to BaudRatePres value */
+ /* Set CPOL bit according to CLKPOL value */
+ /* Set CPHA bit according to CLKPHA value */
+ tmpregister |= (uint16_t)((uint32_t)SPI_InitStruct->DataDirection | SPI_InitStruct->SpiMode
+ | SPI_InitStruct->DataLen | SPI_InitStruct->CLKPOL | SPI_InitStruct->CLKPHA
+ | SPI_InitStruct->NSS | SPI_InitStruct->BaudRatePres | SPI_InitStruct->FirstBit);
+ /* Write to SPIx CTRL1 */
+ SPIx->CTRL1 = tmpregister;
+
+ /* Activate the SPI mode (Reset I2SMOD bit in I2SCFG register) */
+ SPIx->I2SCFG &= SPI_MODE_ENABLE;
+
+ /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
+ /* Write to SPIx CRCPOLY */
+ SPIx->CRCPOLY = SPI_InitStruct->CRCPoly;
+}
+
+/**
+ * @brief Initializes the SPIx peripheral according to the specified
+ * parameters in the I2S_InitStruct.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral
+ * (configured in I2S mode).
+ * @param I2S_InitStruct pointer to an I2S_InitType structure that
+ * contains the configuration information for the specified SPI peripheral
+ * configured in I2S mode.
+ * @note
+ * The function calculates the optimal prescaler needed to obtain the most
+ * accurate audio frequency (depending on the I2S clock source, the PLL values
+ * and the product configuration). But in case the prescaler value is greater
+ * than 511, the default value (0x02) will be configured instead. *
+ */
+void I2S_Init(SPI_Module* SPIx, I2S_InitType* I2S_InitStruct)
+{
+ uint16_t tmpregister = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
+ uint32_t tmp = 0;
+ RCC_ClocksType RCC_Clocks;
+ uint32_t sourceclock = 0;
+
+ /* Check the I2S parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_I2S_MODE(I2S_InitStruct->I2sMode));
+ assert_param(IS_I2S_STANDARD(I2S_InitStruct->Standard));
+ assert_param(IS_I2S_DATA_FMT(I2S_InitStruct->DataFormat));
+ assert_param(IS_I2S_MCLK_ENABLE(I2S_InitStruct->MCLKEnable));
+ assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFrequency));
+ assert_param(IS_I2S_CLKPOL(I2S_InitStruct->CLKPOL));
+
+ /*----------------------- SPIx I2SCFG & I2SPREDIV Configuration -----------------*/
+ /* Clear I2SMOD, I2SE, MODCFG, PCMSYNC, STDSEL, CKPOL, TDATLEN and CHLEN bits */
+ SPIx->I2SCFG &= I2SCFG_CLR_MASK;
+ SPIx->I2SPREDIV = 0x0002;
+
+ /* Get the I2SCFG register value */
+ tmpregister = SPIx->I2SCFG;
+
+ /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
+ if (I2S_InitStruct->AudioFrequency == I2S_AUDIO_FREQ_DEFAULT)
+ {
+ i2sodd = (uint16_t)0;
+ i2sdiv = (uint16_t)2;
+ }
+ /* If the requested audio frequency is not the default, compute the prescaler */
+ else
+ {
+ /* Check the frame length (For the Prescaler computing) */
+ if (I2S_InitStruct->DataFormat == I2S_DATA_FMT_16BITS)
+ {
+ /* Packet length is 16 bits */
+ packetlength = 1;
+ }
+ else
+ {
+ /* Packet length is 32 bits */
+ packetlength = 2;
+ }
+
+ /* Get the I2S clock source mask depending on the peripheral number */
+ if (((uint32_t)SPIx) == SPI2_BASE)
+ {
+ /* The mask is relative to I2S1 */
+ tmp = I2S1_CLKSRC;
+ }
+ else
+ {
+ /* The mask is relative to I2S2 */
+ tmp = I2S2_CLKSRC;
+ }
+
+ /* I2S Clock source is System clock: Get System Clock frequency */
+ RCC_GetClocksFreqValue(&RCC_Clocks);
+
+ /* Get the source clock value: based on System Clock value */
+ sourceclock = RCC_Clocks.SysclkFreq;
+
+ /* Compute the Real divider depending on the MCLK output state with a floating point */
+ if (I2S_InitStruct->MCLKEnable == I2S_MCLK_ENABLE)
+ {
+ /* MCLK output is enabled */
+ tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->AudioFrequency)) + 5);
+ }
+ else
+ {
+ /* MCLK output is disabled */
+ tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) * 10) / I2S_InitStruct->AudioFrequency)) + 5);
+ }
+
+ /* Remove the floating point */
+ tmp = tmp / 10;
+
+ /* Check the parity of the divider */
+ i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
+
+ /* Compute the i2sdiv prescaler */
+ i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
+
+ /* Get the Mask for the Odd bit (SPI_I2SPREDIV[8]) register */
+ i2sodd = (uint16_t)(i2sodd << 8);
+ }
+
+ /* Test if the divider is 1 or 0 or greater than 0xFF */
+ if ((i2sdiv < 2) || (i2sdiv > 0xFF))
+ {
+ /* Set the default values */
+ i2sdiv = 2;
+ i2sodd = 0;
+ }
+
+ /* Write to SPIx I2SPREDIV register the computed value */
+ SPIx->I2SPREDIV = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->MCLKEnable));
+
+ /* Configure the I2S with the SPI_InitStruct values */
+ tmpregister |= (uint16_t)(
+ I2S_MODE_ENABLE
+ | (uint16_t)(I2S_InitStruct->I2sMode
+ | (uint16_t)(I2S_InitStruct->Standard
+ | (uint16_t)(I2S_InitStruct->DataFormat | (uint16_t)I2S_InitStruct->CLKPOL))));
+
+ /* Write to SPIx I2SCFG */
+ SPIx->I2SCFG = tmpregister;
+}
+
+/**
+ * @brief Fills each SPI_InitStruct member with its default value.
+ * @param SPI_InitStruct pointer to a SPI_InitType structure which will be initialized.
+ */
+void SPI_InitStruct(SPI_InitType* SPI_InitStruct)
+{
+ /*--------------- Reset SPI init structure parameters values -----------------*/
+ /* Initialize the DataDirection member */
+ SPI_InitStruct->DataDirection = SPI_DIR_DOUBLELINE_FULLDUPLEX;
+ /* initialize the SpiMode member */
+ SPI_InitStruct->SpiMode = SPI_MODE_SLAVE;
+ /* initialize the DataLen member */
+ SPI_InitStruct->DataLen = SPI_DATA_SIZE_8BITS;
+ /* Initialize the CLKPOL member */
+ SPI_InitStruct->CLKPOL = SPI_CLKPOL_LOW;
+ /* Initialize the CLKPHA member */
+ SPI_InitStruct->CLKPHA = SPI_CLKPHA_FIRST_EDGE;
+ /* Initialize the NSS member */
+ SPI_InitStruct->NSS = SPI_NSS_HARD;
+ /* Initialize the BaudRatePres member */
+ SPI_InitStruct->BaudRatePres = SPI_BR_PRESCALER_2;
+ /* Initialize the FirstBit member */
+ SPI_InitStruct->FirstBit = SPI_FB_MSB;
+ /* Initialize the CRCPoly member */
+ SPI_InitStruct->CRCPoly = 7;
+}
+
+/**
+ * @brief Fills each I2S_InitStruct member with its default value.
+ * @param I2S_InitStruct pointer to a I2S_InitType structure which will be initialized.
+ */
+void I2S_InitStruct(I2S_InitType* I2S_InitStruct)
+{
+ /*--------------- Reset I2S init structure parameters values -----------------*/
+ /* Initialize the I2sMode member */
+ I2S_InitStruct->I2sMode = I2S_MODE_SlAVE_TX;
+
+ /* Initialize the Standard member */
+ I2S_InitStruct->Standard = I2S_STD_PHILLIPS;
+
+ /* Initialize the DataFormat member */
+ I2S_InitStruct->DataFormat = I2S_DATA_FMT_16BITS;
+
+ /* Initialize the MCLKEnable member */
+ I2S_InitStruct->MCLKEnable = I2S_MCLK_DISABLE;
+
+ /* Initialize the AudioFrequency member */
+ I2S_InitStruct->AudioFrequency = I2S_AUDIO_FREQ_DEFAULT;
+
+ /* Initialize the CLKPOL member */
+ I2S_InitStruct->CLKPOL = I2S_CLKPOL_LOW;
+}
+
+/**
+ * @brief Enables or disables the specified SPI peripheral.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param Cmd new state of the SPIx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void SPI_Enable(SPI_Module* SPIx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected SPI peripheral */
+ SPIx->CTRL1 |= CTRL1_SPIEN_ENABLE;
+ }
+ else
+ {
+ /* Disable the selected SPI peripheral */
+ SPIx->CTRL1 &= CTRL1_SPIEN_DISABLE;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified SPI peripheral (in I2S mode).
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param Cmd new state of the SPIx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2S_Enable(SPI_Module* SPIx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected SPI peripheral (in I2S mode) */
+ SPIx->I2SCFG |= I2SCFG_I2SEN_ENABLE;
+ }
+ else
+ {
+ /* Disable the selected SPI peripheral (in I2S mode) */
+ SPIx->I2SCFG &= I2SCFG_I2SEN_DISABLE;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified SPI/I2S interrupts.
+ * @param SPIx where x can be
+ * - 1 or 2 in SPI mode
+ * - 1 or 2 in I2S mode
+ * @param SPI_I2S_IT specifies the SPI/I2S interrupt source to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg SPI_I2S_INT_TE Tx buffer empty interrupt mask
+ * @arg SPI_I2S_INT_RNE Rx buffer not empty interrupt mask
+ * @arg SPI_I2S_INT_ERR Error interrupt mask
+ * @param Cmd new state of the specified SPI/I2S interrupt.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void SPI_I2S_EnableInt(SPI_Module* SPIx, uint8_t SPI_I2S_IT, FunctionalState Cmd)
+{
+ uint16_t itpos = 0, itmask = 0;
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ assert_param(IS_SPI_I2S_CONFIG_INT(SPI_I2S_IT));
+
+ /* Get the SPI/I2S IT index */
+ itpos = SPI_I2S_IT >> 4;
+
+ /* Set the IT mask */
+ itmask = (uint16_t)1 << (uint16_t)itpos;
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected SPI/I2S interrupt */
+ SPIx->CTRL2 |= itmask;
+ }
+ else
+ {
+ /* Disable the selected SPI/I2S interrupt */
+ SPIx->CTRL2 &= (uint16_t)~itmask;
+ }
+}
+
+/**
+ * @brief Enables or disables the SPIx/I2Sx DMA interface.
+ * @param SPIx where x can be
+ * - 1 or 2 in SPI mode
+ * - 1 or 2 in I2S mode
+ * @param SPI_I2S_DMAReq specifies the SPI/I2S DMA transfer request to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg SPI_I2S_DMA_TX Tx buffer DMA transfer request
+ * @arg SPI_I2S_DMA_RX Rx buffer DMA transfer request
+ * @param Cmd new state of the selected SPI/I2S DMA transfer request.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void SPI_I2S_EnableDma(SPI_Module* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ assert_param(IS_SPI_I2S_DMA(SPI_I2S_DMAReq));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected SPI/I2S DMA requests */
+ SPIx->CTRL2 |= SPI_I2S_DMAReq;
+ }
+ else
+ {
+ /* Disable the selected SPI/I2S DMA requests */
+ SPIx->CTRL2 &= (uint16_t)~SPI_I2S_DMAReq;
+ }
+}
+
+/**
+ * @brief Transmits a Data through the SPIx/I2Sx peripheral.
+ * @param SPIx where x can be
+ * - 1 or 2 in SPI mode
+ * - 1 or 2 in I2S mode
+ * @param Data Data to be transmitted.
+ */
+void SPI_I2S_TransmitData(SPI_Module* SPIx, uint16_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+
+ /* Write in the DAT register the data to be sent */
+ SPIx->DAT = Data;
+}
+
+/**
+ * @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
+ * @param SPIx where x can be
+ * - 1 or 2 in SPI mode
+ * - 1 or 2 in I2S mode
+ * @return The value of the received data.
+ */
+uint16_t SPI_I2S_ReceiveData(SPI_Module* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+
+ /* Return the data in the DAT register */
+ return SPIx->DAT;
+}
+
+/**
+ * @brief Configures internally by software the NSS pin for the selected SPI.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param SPI_NSSInternalSoft specifies the SPI NSS internal state.
+ * This parameter can be one of the following values:
+ * @arg SPI_NSS_HIGH Set NSS pin internally
+ * @arg SPI_NSS_LOW Reset NSS pin internally
+ */
+void SPI_SetNssLevel(SPI_Module* SPIx, uint16_t SPI_NSSInternalSoft)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_NSS_LEVEL(SPI_NSSInternalSoft));
+ if (SPI_NSSInternalSoft != SPI_NSS_LOW)
+ {
+ /* Set NSS pin internally by software */
+ SPIx->CTRL1 |= SPI_NSS_HIGH;
+ }
+ else
+ {
+ /* Reset NSS pin internally by software */
+ SPIx->CTRL1 &= SPI_NSS_LOW;
+ }
+}
+
+/**
+ * @brief Enables or disables the SS output for the selected SPI.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param Cmd new state of the SPIx SS output.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void SPI_SSOutputEnable(SPI_Module* SPIx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected SPI SS output */
+ SPIx->CTRL2 |= CTRL2_SSOEN_ENABLE;
+ }
+ else
+ {
+ /* Disable the selected SPI SS output */
+ SPIx->CTRL2 &= CTRL2_SSOEN_DISABLE;
+ }
+}
+
+/**
+ * @brief Configures the data size for the selected SPI.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param DataLen specifies the SPI data size.
+ * This parameter can be one of the following values:
+ * @arg SPI_DATA_SIZE_16BITS Set data frame format to 16bit
+ * @arg SPI_DATA_SIZE_8BITS Set data frame format to 8bit
+ */
+void SPI_ConfigDataLen(SPI_Module* SPIx, uint16_t DataLen)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_DATASIZE(DataLen));
+ /* Clear DFF bit */
+ SPIx->CTRL1 &= (uint16_t)~SPI_DATA_SIZE_16BITS;
+ /* Set new DFF bit value */
+ SPIx->CTRL1 |= DataLen;
+}
+
+/**
+ * @brief Transmit the SPIx CRC value.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ */
+void SPI_TransmitCrcNext(SPI_Module* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+
+ /* Enable the selected SPI CRC transmission */
+ SPIx->CTRL1 |= CTRL1_CRCNEXT_ENABLE;
+}
+
+/**
+ * @brief Enables or disables the CRC value calculation of the transferred bytes.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param Cmd new state of the SPIx CRC value calculation.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void SPI_EnableCalculateCrc(SPI_Module* SPIx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected SPI CRC calculation */
+ SPIx->CTRL1 |= CTRL1_CRCEN_ENABLE;
+ }
+ else
+ {
+ /* Disable the selected SPI CRC calculation */
+ SPIx->CTRL1 &= CTRL1_CRCEN_DISABLE;
+ }
+}
+
+/**
+ * @brief Returns the transmit or the receive CRC register value for the specified SPI.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param SPI_CRC specifies the CRC register to be read.
+ * This parameter can be one of the following values:
+ * @arg SPI_CRC_TX Selects Tx CRC register
+ * @arg SPI_CRC_RX Selects Rx CRC register
+ * @return The selected CRC register value..
+ */
+uint16_t SPI_GetCRCDat(SPI_Module* SPIx, uint8_t SPI_CRC)
+{
+ uint16_t crcreg = 0;
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_CRC(SPI_CRC));
+ if (SPI_CRC != SPI_CRC_RX)
+ {
+ /* Get the Tx CRC register */
+ crcreg = SPIx->CRCTDAT;
+ }
+ else
+ {
+ /* Get the Rx CRC register */
+ crcreg = SPIx->CRCRDAT;
+ }
+ /* Return the selected CRC register */
+ return crcreg;
+}
+
+/**
+ * @brief Returns the CRC Polynomial register value for the specified SPI.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @return The CRC Polynomial register value.
+ */
+uint16_t SPI_GetCRCPoly(SPI_Module* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+
+ /* Return the CRC polynomial register */
+ return SPIx->CRCPOLY;
+}
+
+/**
+ * @brief Selects the data transfer direction in bi-directional mode for the specified SPI.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param DataDirection specifies the data transfer direction in bi-directional mode.
+ * This parameter can be one of the following values:
+ * @arg SPI_BIDIRECTION_TX Selects Tx transmission direction
+ * @arg SPI_BIDIRECTION_RX Selects Rx receive direction
+ */
+void SPI_ConfigBidirectionalMode(SPI_Module* SPIx, uint16_t DataDirection)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_BIDIRECTION(DataDirection));
+ if (DataDirection == SPI_BIDIRECTION_TX)
+ {
+ /* Set the Tx only mode */
+ SPIx->CTRL1 |= SPI_BIDIRECTION_TX;
+ }
+ else
+ {
+ /* Set the Rx only mode */
+ SPIx->CTRL1 &= SPI_BIDIRECTION_RX;
+ }
+}
+
+/**
+ * @brief Checks whether the specified SPI/I2S flag is set or not.
+ * @param SPIx where x can be
+ * - 1 or 2 in SPI mode
+ * - 1 or 2 in I2S mode
+ * @param SPI_I2S_FLAG specifies the SPI/I2S flag to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_I2S_TE_FLAG Transmit buffer empty flag.
+ * @arg SPI_I2S_RNE_FLAG Receive buffer not empty flag.
+ * @arg SPI_I2S_BUSY_FLAG Busy flag.
+ * @arg SPI_I2S_OVER_FLAG Overrun flag.
+ * @arg SPI_MODERR_FLAG Mode Fault flag.
+ * @arg SPI_CRCERR_FLAG CRC Error flag.
+ * @arg I2S_UNDER_FLAG Underrun Error flag.
+ * @arg I2S_CHSIDE_FLAG Channel Side flag.
+ * @return The new state of SPI_I2S_FLAG (SET or RESET).
+ */
+FlagStatus SPI_I2S_GetStatus(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
+ /* Check the status of the specified SPI/I2S flag */
+ if ((SPIx->STS & SPI_I2S_FLAG) != (uint16_t)RESET)
+ {
+ /* SPI_I2S_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* SPI_I2S_FLAG is reset */
+ bitstatus = RESET;
+ }
+ /* Return the SPI_I2S_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the SPIx CRC Error (CRCERR) flag.
+ * @param SPIx where x can be
+ * - 1 or 2 in SPI mode
+ * @param SPI_I2S_FLAG specifies the SPI flag to clear.
+ * This function clears only CRCERR flag.
+ * @note
+ * - OVR (OverRun error) flag is cleared by software sequence: a read
+ * operation to SPI_DAT register (SPI_I2S_ReceiveData()) followed by a read
+ * operation to SPI_STS register (SPI_I2S_GetStatus()).
+ * - UDR (UnderRun error) flag is cleared by a read operation to
+ * SPI_STS register (SPI_I2S_GetStatus()).
+ * - MODF (Mode Fault) flag is cleared by software sequence: a read/write
+ * operation to SPI_STS register (SPI_I2S_GetStatus()) followed by a
+ * write operation to SPI_CTRL1 register (SPI_Enable() to enable the SPI).
+ */
+void SPI_I2S_ClrCRCErrFlag(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_CLR_FLAG(SPI_I2S_FLAG));
+
+ /* Clear the selected SPI CRC Error (CRCERR) flag */
+ SPIx->STS = (uint16_t)~SPI_I2S_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified SPI/I2S interrupt has occurred or not.
+ * @param SPIx where x can be
+ * - 1 or 2 in SPI mode
+ * - 1 or 2 in I2S mode
+ * @param SPI_I2S_IT specifies the SPI/I2S interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_I2S_INT_TE Transmit buffer empty interrupt.
+ * @arg SPI_I2S_INT_RNE Receive buffer not empty interrupt.
+ * @arg SPI_I2S_INT_OVER Overrun interrupt.
+ * @arg SPI_INT_MODERR Mode Fault interrupt.
+ * @arg SPI_INT_CRCERR CRC Error interrupt.
+ * @arg I2S_INT_UNDER Underrun Error interrupt.
+ * @return The new state of SPI_I2S_IT (SET or RESET).
+ */
+INTStatus SPI_I2S_GetIntStatus(SPI_Module* SPIx, uint8_t SPI_I2S_IT)
+{
+ INTStatus bitstatus = RESET;
+ uint16_t itpos = 0, itmask = 0, enablestatus = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_GET_INT(SPI_I2S_IT));
+
+ /* Get the SPI/I2S IT index */
+ itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+
+ /* Get the SPI/I2S IT mask */
+ itmask = SPI_I2S_IT >> 4;
+
+ /* Set the IT mask */
+ itmask = 0x01 << itmask;
+
+ /* Get the SPI_I2S_IT enable bit status */
+ enablestatus = (SPIx->CTRL2 & itmask);
+
+ /* Check the status of the specified SPI/I2S interrupt */
+ if (((SPIx->STS & itpos) != (uint16_t)RESET) && enablestatus)
+ {
+ /* SPI_I2S_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* SPI_I2S_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the SPI_I2S_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
+ * @param SPIx where x can be
+ * - 1 or 2 in SPI mode
+ * @param SPI_I2S_IT specifies the SPI interrupt pending bit to clear.
+ * This function clears only CRCERR interrupt pending bit.
+ * @note
+ * - OVR (OverRun Error) interrupt pending bit is cleared by software
+ * sequence: a read operation to SPI_DAT register (SPI_I2S_ReceiveData())
+ * followed by a read operation to SPI_STS register (SPI_I2S_GetIntStatus()).
+ * - UDR (UnderRun Error) interrupt pending bit is cleared by a read
+ * operation to SPI_STS register (SPI_I2S_GetIntStatus()).
+ * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
+ * a read/write operation to SPI_STS register (SPI_I2S_GetIntStatus())
+ * followed by a write operation to SPI_CTRL1 register (SPI_Enable() to enable
+ * the SPI).
+ */
+void SPI_I2S_ClrITPendingBit(SPI_Module* SPIx, uint8_t SPI_I2S_IT)
+{
+ uint16_t itpos = 0;
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_CLR_INT(SPI_I2S_IT));
+
+ /* Get the SPI IT index */
+ itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+
+ /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
+ SPIx->STS = (uint16_t)~itpos;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_tim.c b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_tim.c
new file mode 100644
index 0000000000..d922e5c3c7
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_tim.c
@@ -0,0 +1,3290 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_tim.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l40x_tim.h"
+#include "n32l40x_rcc.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup TIM
+ * @brief TIM driver modules
+ * @{
+ */
+
+/** @addtogroup TIM_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Defines
+ * @{
+ */
+
+/* ---------------------- TIM registers bit mask ------------------------ */
+#define SMCTRL_ETR_MASK ((uint16_t)0x00FF)
+#define CAPCMPMOD_OFFSET ((uint16_t)0x0018)
+#define CAPCMPEN_CCE_SET ((uint16_t)0x0001)
+#define CAPCMPEN_CCNE_SET ((uint16_t)0x0004)
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_FunctionPrototypes
+ * @{
+ */
+
+static void ConfigTI1(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter);
+static void ConfigTI2(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter);
+static void ConfigTI3(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter);
+static void ConfigTI4(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the TIMx peripheral registers to their default reset values.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ */
+void TIM_DeInit(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+
+ if (TIMx == TIM1)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM1, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM1, DISABLE);
+ }
+ else if (TIMx == TIM2)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM2, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM2, DISABLE);
+ }
+ else if (TIMx == TIM3)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM3, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM3, DISABLE);
+ }
+ else if (TIMx == TIM4)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM4, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM4, DISABLE);
+ }
+ else if (TIMx == TIM5)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM5, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM5, DISABLE);
+ }
+ else if (TIMx == TIM6)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM6, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM6, DISABLE);
+ }
+ else if (TIMx == TIM7)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM7, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM7, DISABLE);
+ }
+ else if (TIMx == TIM8)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM8, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM8, DISABLE);
+ }
+ else if (TIMx == TIM9)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM9, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM9, DISABLE);
+ }
+}
+
+/**
+ * @brief Initializes the TIMx Time Base Unit peripheral according to
+ * the specified parameters in the TIM_TimeBaseInitStruct.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_TimeBaseInitStruct pointer to a TIM_TimeBaseInitType
+ * structure that contains the configuration information for the
+ * specified TIM peripheral.
+ */
+void TIM_InitTimeBase(TIM_Module* TIMx, TIM_TimeBaseInitType* TIM_TimeBaseInitStruct)
+{
+ uint32_t tmpcr1 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimCntMode(TIM_TimeBaseInitStruct->CntMode));
+ assert_param(IsTimClkDiv(TIM_TimeBaseInitStruct->ClkDiv));
+
+ tmpcr1 = TIMx->CTRL1;
+
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9))
+ {
+ /* Select the Counter Mode */
+ tmpcr1 &= (uint32_t)(~((uint32_t)(TIM_CTRL1_DIR | TIM_CTRL1_CAMSEL)));
+ tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->CntMode;
+ }
+
+ if ((TIMx != TIM6) && (TIMx != TIM7))
+ {
+ /* Set the clock division */
+ tmpcr1 &= (uint32_t)(~((uint32_t)TIM_CTRL1_CLKD));
+ tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->ClkDiv;
+ }
+
+ TIMx->CTRL1 = tmpcr1;
+
+ /* Set the Autoreload value */
+ TIMx->AR = TIM_TimeBaseInitStruct->Period;
+
+ /* Set the Prescaler value */
+ TIMx->PSC = TIM_TimeBaseInitStruct->Prescaler;
+
+ if ((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ /* Set the Repetition Counter value */
+ TIMx->REPCNT = TIM_TimeBaseInitStruct->RepetCnt;
+ }
+
+ /* Generate an update event to reload the Prescaler and the Repetition counter
+ values immediately */
+ TIMx->EVTGEN = TIM_PSC_RELOAD_MODE_IMMEDIATE;
+
+ /*channel input from comp or iom*/
+ tmpcr1 = TIMx->CTRL1;
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9))
+ {
+ if (TIM_TimeBaseInitStruct->CapCh1FromCompEn)
+ tmpcr1 |= (0x01L << 11);
+ else
+ tmpcr1 &= ~(0x01L << 11);
+ }
+ if (TIMx==TIM9)
+ {
+ if (TIM_TimeBaseInitStruct->CapCh2FromCompEn)
+ tmpcr1 |= (0x01L << 12);
+ else
+ tmpcr1 &= ~(0x01L << 12);
+ if (TIM_TimeBaseInitStruct->CapCh3FromCompEn)
+ tmpcr1 |= (0x01L << 13);
+ else
+ tmpcr1 &= ~(0x01L << 13);
+ if (TIM_TimeBaseInitStruct->CapCh4FromCompEn)
+ tmpcr1 |= (0x01L << 14);
+ else
+ tmpcr1 &= ~(0x01L << 14);
+ }
+ /*etr input from comp or iom*/
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM9))
+ {
+ if (TIM_TimeBaseInitStruct->CapEtrClrFromCompEn)
+ tmpcr1 |= (0x01L << 15);
+ else
+ tmpcr1 &= ~(0x01L << 15);
+ }
+ TIMx->CTRL1 = tmpcr1;
+ /*sel etr from iom or tsc*/
+ tmpcr1 = TIMx->CTRL2;
+ if ((TIMx == TIM2) || (TIMx == TIM4))
+ {
+ if (TIM_TimeBaseInitStruct->CapEtrSelFromTscEn)
+ tmpcr1 |= (0x01L << 8);
+ else
+ tmpcr1 &= ~(0x01L << 8);
+ }
+ TIMx->CTRL2 = tmpcr1;
+}
+
+/**
+ * @brief Initializes the TIMx Channel1 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_InitOc1(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0;
+ uint32_t tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode));
+ assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState));
+ assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity));
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCEN &= (uint32_t)(~(uint32_t)TIM_CCEN_CC1EN);
+ /* Get the TIMx CCEN register value */
+ tmpccer = TIMx->CCEN;
+ /* Get the TIMx CTRL2 register value */
+ tmpcr2 = TIMx->CTRL2;
+
+ /* Get the TIMx CCMOD1 register value */
+ tmpccmrx = TIMx->CCMOD1;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_OC1M));
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_CC1SEL));
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= TIM_OCInitStruct->OcMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC1P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= TIM_OCInitStruct->OcPolarity;
+
+ /* Set the Output State */
+ tmpccer |= TIM_OCInitStruct->OutputState;
+
+ if ((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IsTimOutputNState(TIM_OCInitStruct->OutputNState));
+ assert_param(IsTimOcnPolarity(TIM_OCInitStruct->OcNPolarity));
+ assert_param(IsTimOcnIdleState(TIM_OCInitStruct->OcNIdleState));
+ assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC1NP));
+ /* Set the Output N Polarity */
+ tmpccer |= TIM_OCInitStruct->OcNPolarity;
+
+ /* Reset the Output N State */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC1NEN));
+ /* Set the Output N State */
+ tmpccer |= TIM_OCInitStruct->OutputNState;
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI1));
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI1N));
+
+ /* Set the Output Idle state */
+ tmpcr2 |= TIM_OCInitStruct->OcIdleState;
+ /* Set the Output N Idle state */
+ tmpcr2 |= TIM_OCInitStruct->OcNIdleState;
+ }
+ /* Write to TIMx CTRL2 */
+ TIMx->CTRL2 = tmpcr2;
+
+ /* Write to TIMx CCMOD1 */
+ TIMx->CCMOD1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCDAT1 = TIM_OCInitStruct->Pulse;
+
+ /* Write to TIMx CCEN */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel2 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select
+ * the TIM peripheral.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_InitOc2(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0;
+ uint32_t tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode));
+ assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState));
+ assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity));
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC2EN));
+
+ /* Get the TIMx CCEN register value */
+ tmpccer = TIMx->CCEN;
+ /* Get the TIMx CTRL2 register value */
+ tmpcr2 = TIMx->CTRL2;
+
+ /* Get the TIMx CCMOD1 register value */
+ tmpccmrx = TIMx->CCMOD1;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_OC2M));
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_CC2SEL));
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC2P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 4);
+
+ /* Set the Output State */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 4);
+
+ if ((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IsTimOutputNState(TIM_OCInitStruct->OutputNState));
+ assert_param(IsTimOcnPolarity(TIM_OCInitStruct->OcNPolarity));
+ assert_param(IsTimOcnIdleState(TIM_OCInitStruct->OcNIdleState));
+ assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC2NP));
+ /* Set the Output N Polarity */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OcNPolarity << 4);
+
+ /* Reset the Output N State */
+ tmpccer &= (uint32_t)(~((uint16_t)TIM_CCEN_CC2NEN));
+ /* Set the Output N State */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputNState << 4);
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI2));
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI2N));
+
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 2);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcNIdleState << 2);
+ }
+ /* Write to TIMx CTRL2 */
+ TIMx->CTRL2 = tmpcr2;
+
+ /* Write to TIMx CCMOD1 */
+ TIMx->CCMOD1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCDAT2 = TIM_OCInitStruct->Pulse;
+
+ /* Write to TIMx CCEN */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel3 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_InitOc3(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0;
+ uint32_t tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode));
+ assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState));
+ assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity));
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC3EN));
+
+ /* Get the TIMx CCEN register value */
+ tmpccer = TIMx->CCEN;
+ /* Get the TIMx CTRL2 register value */
+ tmpcr2 = TIMx->CTRL2;
+
+ /* Get the TIMx CCMOD2 register value */
+ tmpccmrx = TIMx->CCMOD2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_OC3MD));
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_CC3SEL));
+ /* Select the Output Compare Mode */
+ tmpccmrx |= TIM_OCInitStruct->OcMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)(~((uint16_t)TIM_CCEN_CC3P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 8);
+
+ /* Set the Output State */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 8);
+
+ if ((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IsTimOutputNState(TIM_OCInitStruct->OutputNState));
+ assert_param(IsTimOcnPolarity(TIM_OCInitStruct->OcNPolarity));
+ assert_param(IsTimOcnIdleState(TIM_OCInitStruct->OcNIdleState));
+ assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC3NP));
+ /* Set the Output N Polarity */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OcNPolarity << 8);
+ /* Reset the Output N State */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC3NEN));
+
+ /* Set the Output N State */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputNState << 8);
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI3));
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI3N));
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 4);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcNIdleState << 4);
+ }
+ /* Write to TIMx CTRL2 */
+ TIMx->CTRL2 = tmpcr2;
+
+ /* Write to TIMx CCMOD2 */
+ TIMx->CCMOD2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCDAT3 = TIM_OCInitStruct->Pulse;
+
+ /* Write to TIMx CCEN */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel4 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_InitOc4(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0;
+ uint32_t tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode));
+ assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState));
+ assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity));
+ /* Disable the Channel 2: Reset the CC4E Bit */
+ TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC4EN));
+
+ /* Get the TIMx CCEN register value */
+ tmpccer = TIMx->CCEN;
+ /* Get the TIMx CTRL2 register value */
+ tmpcr2 = TIMx->CTRL2;
+
+ /* Get the TIMx CCMOD2 register value */
+ tmpccmrx = TIMx->CCMOD2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_OC4MD));
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_CC4SEL));
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC4P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 12);
+
+ /* Set the Output State */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 12);
+
+ if ((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState));
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI4));
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 6);
+ }
+ /* Write to TIMx CTRL2 */
+ TIMx->CTRL2 = tmpcr2;
+
+ /* Write to TIMx CCMOD2 */
+ TIMx->CCMOD2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCDAT4 = TIM_OCInitStruct->Pulse;
+
+ /* Write to TIMx CCEN */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel5 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_InitOc5(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0;
+ uint32_t tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode));
+ assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState));
+ assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity));
+ /* Disable the Channel 5: Reset the CC5E Bit */
+ TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC5EN));
+
+ /* Get the TIMx CCEN register value */
+ tmpccer = TIMx->CCEN;
+ /* Get the TIMx CTRL2 register value */
+ tmpcr2 = TIMx->CTRL2;
+
+ /* Get the TIMx CCMOD3 register value */
+ tmpccmrx = TIMx->CCMOD3;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD3_OC5MD));
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC5P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 16);
+
+ /* Set the Output State */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 16);
+
+ if ((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState));
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI5));
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 8);
+ }
+ /* Write to TIMx CTRL2 */
+ TIMx->CTRL2 = tmpcr2;
+
+ /* Write to TIMx CCMOD3 */
+ TIMx->CCMOD3 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCDAT5 = TIM_OCInitStruct->Pulse;
+
+ /* Write to TIMx CCEN */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel6 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_InitOc6(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0;
+ uint32_t tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode));
+ assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState));
+ assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity));
+ /* Disable the Channel 6: Reset the CC6E Bit */
+ TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC6EN));
+
+ /* Get the TIMx CCEN register value */
+ tmpccer = TIMx->CCEN;
+ /* Get the TIMx CTRL2 register value */
+ tmpcr2 = TIMx->CTRL2;
+
+ /* Get the TIMx CCMOD3 register value */
+ tmpccmrx = TIMx->CCMOD3;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD3_OC6MD));
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC6P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 20);
+
+ /* Set the Output State */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 20);
+
+ if ((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState));
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI6));
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 10);
+ }
+ /* Write to TIMx CTRL2 */
+ TIMx->CTRL2 = tmpcr2;
+
+ /* Write to TIMx CCMOD3 */
+ TIMx->CCMOD3 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCDAT6 = TIM_OCInitStruct->Pulse;
+
+ /* Write to TIMx CCEN */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIM peripheral according to the specified
+ * parameters in the TIM_ICInitStruct.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_ICInitStruct pointer to a TIM_ICInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_ICInit(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IsTimCh(TIM_ICInitStruct->Channel));
+ assert_param(IsTimIcSelection(TIM_ICInitStruct->IcSelection));
+ assert_param(IsTimIcPrescaler(TIM_ICInitStruct->IcPrescaler));
+ assert_param(IsTimInCapFilter(TIM_ICInitStruct->IcFilter));
+
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9))
+ {
+ assert_param(IsTimIcPalaritySingleEdge(TIM_ICInitStruct->IcPolarity));
+ }
+ else
+ {
+ assert_param(IsTimIcPolarityAnyEdge(TIM_ICInitStruct->IcPolarity));
+ }
+ if (TIM_ICInitStruct->Channel == TIM_CH_1)
+ {
+ assert_param(IsTimList8Module(TIMx));
+ /* TI1 Configuration */
+ ConfigTI1(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap1Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ }
+ else if (TIM_ICInitStruct->Channel == TIM_CH_2)
+ {
+ assert_param(IsTimList6Module(TIMx));
+ /* TI2 Configuration */
+ ConfigTI2(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap2Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ }
+ else if (TIM_ICInitStruct->Channel == TIM_CH_3)
+ {
+ assert_param(IsTimList3Module(TIMx));
+ /* TI3 Configuration */
+ ConfigTI3(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap3Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ }
+ else
+ {
+ assert_param(IsTimList3Module(TIMx));
+ /* TI4 Configuration */
+ ConfigTI4(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap4Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ }
+}
+
+/**
+ * @brief Configures the TIM peripheral according to the specified
+ * parameters in the TIM_ICInitStruct to measure an external PWM signal.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param TIM_ICInitStruct pointer to a TIM_ICInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_ConfigPwmIc(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct)
+{
+ uint16_t icoppositepolarity = TIM_IC_POLARITY_RISING;
+ uint16_t icoppositeselection = TIM_IC_SELECTION_DIRECTTI;
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ /* Select the Opposite Input Polarity */
+ if (TIM_ICInitStruct->IcPolarity == TIM_IC_POLARITY_RISING)
+ {
+ icoppositepolarity = TIM_IC_POLARITY_FALLING;
+ }
+ else
+ {
+ icoppositepolarity = TIM_IC_POLARITY_RISING;
+ }
+ /* Select the Opposite Input */
+ if (TIM_ICInitStruct->IcSelection == TIM_IC_SELECTION_DIRECTTI)
+ {
+ icoppositeselection = TIM_IC_SELECTION_INDIRECTTI;
+ }
+ else
+ {
+ icoppositeselection = TIM_IC_SELECTION_DIRECTTI;
+ }
+ if (TIM_ICInitStruct->Channel == TIM_CH_1)
+ {
+ /* TI1 Configuration */
+ ConfigTI1(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap1Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ /* TI2 Configuration */
+ ConfigTI2(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap2Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ }
+ else
+ {
+ /* TI2 Configuration */
+ ConfigTI2(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap2Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ /* TI1 Configuration */
+ ConfigTI1(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap1Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ }
+}
+
+/**
+ * @brief Configures the: Break feature, dead time, Lock level, the OSSI,
+ * the OSSR State and the AOE(automatic output enable).
+ * @param TIMx where x can be 1 or 8 to select the TIM
+ * @param TIM_BDTRInitStruct pointer to a TIM_BDTRInitType structure that
+ * contains the BKDT Register configuration information for the TIM peripheral.
+ */
+void TIM_ConfigBkdt(TIM_Module* TIMx, TIM_BDTRInitType* TIM_BDTRInitStruct)
+{
+ uint32_t tmp;
+ /* Check the parameters */
+ assert_param(IsTimList2Module(TIMx));
+ assert_param(IsTimOssrState(TIM_BDTRInitStruct->OssrState));
+ assert_param(IsTimOssiState(TIM_BDTRInitStruct->OssiState));
+ assert_param(IsTimLockLevel(TIM_BDTRInitStruct->LockLevel));
+ assert_param(IsTimBreakInState(TIM_BDTRInitStruct->Break));
+ assert_param(IsTimBreakPalarity(TIM_BDTRInitStruct->BreakPolarity));
+ assert_param(IsTimAutoOutputState(TIM_BDTRInitStruct->AutomaticOutput));
+ /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */
+ TIMx->BKDT = (uint32_t)TIM_BDTRInitStruct->OssrState | TIM_BDTRInitStruct->OssiState | TIM_BDTRInitStruct->LockLevel
+ | TIM_BDTRInitStruct->DeadTime | TIM_BDTRInitStruct->Break | TIM_BDTRInitStruct->BreakPolarity
+ | TIM_BDTRInitStruct->AutomaticOutput;
+
+ /*cofigure other break in*/
+ tmp = TIMx->CTRL1;
+ /*IOMBKPEN 0 meaning iom as break enable*/
+ if (TIM_BDTRInitStruct->IomBreakEn)
+ tmp &= ~(0x01L << 10);
+ else
+ tmp |= (0x01L << 10);
+ if (TIM_BDTRInitStruct->LockUpBreakEn)
+ tmp |= (0x01L << 16);
+ else
+ tmp &= ~(0x01L << 16);
+ if (TIM_BDTRInitStruct->PvdBreakEn)
+ tmp |= (0x01L << 17);
+ else
+ tmp &= ~(0x01L << 17);
+ TIMx->CTRL1 = tmp;
+}
+
+/**
+ * @brief Fills each TIM_TimeBaseInitStruct member with its default value.
+ * @param TIM_TimeBaseInitStruct pointer to a TIM_TimeBaseInitType
+ * structure which will be initialized.
+ */
+void TIM_InitTimBaseStruct(TIM_TimeBaseInitType* TIM_TimeBaseInitStruct)
+{
+ /* Set the default configuration */
+ TIM_TimeBaseInitStruct->Period = 0xFFFF;
+ TIM_TimeBaseInitStruct->Prescaler = 0x0000;
+ TIM_TimeBaseInitStruct->ClkDiv = TIM_CLK_DIV1;
+ TIM_TimeBaseInitStruct->CntMode = TIM_CNT_MODE_UP;
+ TIM_TimeBaseInitStruct->RepetCnt = 0x0000;
+
+ TIM_TimeBaseInitStruct->CapCh1FromCompEn = false;
+ TIM_TimeBaseInitStruct->CapCh2FromCompEn = false;
+ TIM_TimeBaseInitStruct->CapCh3FromCompEn = false;
+ TIM_TimeBaseInitStruct->CapCh4FromCompEn = false;
+ TIM_TimeBaseInitStruct->CapEtrClrFromCompEn = false;
+ TIM_TimeBaseInitStruct->CapEtrSelFromTscEn = false;
+}
+
+/**
+ * @brief Fills each TIM_OCInitStruct member with its default value.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure which will
+ * be initialized.
+ */
+void TIM_InitOcStruct(OCInitType* TIM_OCInitStruct)
+{
+ /* Set the default configuration */
+ TIM_OCInitStruct->OcMode = TIM_OCMODE_TIMING;
+ TIM_OCInitStruct->OutputState = TIM_OUTPUT_STATE_DISABLE;
+ TIM_OCInitStruct->OutputNState = TIM_OUTPUT_NSTATE_DISABLE;
+ TIM_OCInitStruct->Pulse = 0x0000;
+ TIM_OCInitStruct->OcPolarity = TIM_OC_POLARITY_HIGH;
+ TIM_OCInitStruct->OcNPolarity = TIM_OC_POLARITY_HIGH;
+ TIM_OCInitStruct->OcIdleState = TIM_OC_IDLE_STATE_RESET;
+ TIM_OCInitStruct->OcNIdleState = TIM_OCN_IDLE_STATE_RESET;
+}
+
+/**
+ * @brief Fills each TIM_ICInitStruct member with its default value.
+ * @param TIM_ICInitStruct pointer to a TIM_ICInitType structure which will
+ * be initialized.
+ */
+void TIM_InitIcStruct(TIM_ICInitType* TIM_ICInitStruct)
+{
+ /* Set the default configuration */
+ TIM_ICInitStruct->Channel = TIM_CH_1;
+ TIM_ICInitStruct->IcPolarity = TIM_IC_POLARITY_RISING;
+ TIM_ICInitStruct->IcSelection = TIM_IC_SELECTION_DIRECTTI;
+ TIM_ICInitStruct->IcPrescaler = TIM_IC_PSC_DIV1;
+ TIM_ICInitStruct->IcFilter = 0x00;
+}
+
+/**
+ * @brief Fills each TIM_BDTRInitStruct member with its default value.
+ * @param TIM_BDTRInitStruct pointer to a TIM_BDTRInitType structure which
+ * will be initialized.
+ */
+void TIM_InitBkdtStruct(TIM_BDTRInitType* TIM_BDTRInitStruct)
+{
+ /* Set the default configuration */
+ TIM_BDTRInitStruct->OssrState = TIM_OSSR_STATE_DISABLE;
+ TIM_BDTRInitStruct->OssiState = TIM_OSSI_STATE_DISABLE;
+ TIM_BDTRInitStruct->LockLevel = TIM_LOCK_LEVEL_OFF;
+ TIM_BDTRInitStruct->DeadTime = 0x00;
+ TIM_BDTRInitStruct->Break = TIM_BREAK_IN_DISABLE;
+ TIM_BDTRInitStruct->BreakPolarity = TIM_BREAK_POLARITY_LOW;
+ TIM_BDTRInitStruct->AutomaticOutput = TIM_AUTO_OUTPUT_DISABLE;
+}
+
+/**
+ * @brief Enables or disables the specified TIM peripheral.
+ * @param TIMx where x can be 1 to 8 to select the TIMx peripheral.
+ * @param Cmd new state of the TIMx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_Enable(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the TIM Counter */
+ TIMx->CTRL1 |= TIM_CTRL1_CNTEN;
+ }
+ else
+ {
+ /* Disable the TIM Counter */
+ TIMx->CTRL1 &= (uint32_t)(~((uint32_t)TIM_CTRL1_CNTEN));
+ }
+}
+
+/**
+ * @brief Enables or disables the TIM peripheral Main Outputs.
+ * @param TIMx where x can be 1, 8 to select the TIMx peripheral.
+ * @param Cmd new state of the TIM peripheral Main Outputs.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_EnableCtrlPwmOutputs(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimList2Module(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the TIM Main Output */
+ TIMx->BKDT |= TIM_BKDT_MOEN;
+ }
+ else
+ {
+ /* Disable the TIM Main Output */
+ TIMx->BKDT &= (uint16_t)(~((uint16_t)TIM_BKDT_MOEN));
+ }
+}
+
+/**
+ * @brief Enables or disables the specified TIM interrupts.
+ * @param TIMx where x can be 1 to 8 to select the TIMx peripheral.
+ * @param TIM_IT specifies the TIM interrupts sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_INT_UPDATE TIM update Interrupt source
+ * @arg TIM_INT_CC1 TIM Capture Compare 1 Interrupt source
+ * @arg TIM_INT_CC2 TIM Capture Compare 2 Interrupt source
+ * @arg TIM_INT_CC3 TIM Capture Compare 3 Interrupt source
+ * @arg TIM_INT_CC4 TIM Capture Compare 4 Interrupt source
+ * @arg TIM_INT_COM TIM Commutation Interrupt source
+ * @arg TIM_INT_TRIG TIM Trigger Interrupt source
+ * @arg TIM_INT_BREAK TIM Break Interrupt source
+ * @note
+ * - TIM6 and TIM7 can only generate an update interrupt.
+ * - TIM_INT_BREAK is used only with TIM1, TIM8.
+ * - TIM_INT_COM is used only with TIM1, TIM8.
+ * @param Cmd new state of the TIM interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_ConfigInt(TIM_Module* TIMx, uint16_t TIM_IT, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimInt(TIM_IT));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the Interrupt sources */
+ TIMx->DINTEN |= TIM_IT;
+ }
+ else
+ {
+ /* Disable the Interrupt sources */
+ TIMx->DINTEN &= (uint16_t)~TIM_IT;
+ }
+}
+
+/**
+ * @brief Configures the TIMx event to be generate by software.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_EventSource specifies the event source.
+ * This parameter can be one or more of the following values:
+ * @arg TIM_EVT_SRC_UPDATE Timer update Event source
+ * @arg TIM_EVT_SRC_CC1 Timer Capture Compare 1 Event source
+ * @arg TIM_EVT_SRC_CC2 Timer Capture Compare 2 Event source
+ * @arg TIM_EVT_SRC_CC3 Timer Capture Compare 3 Event source
+ * @arg TIM_EVT_SRC_CC4 Timer Capture Compare 4 Event source
+ * @arg TIM_EVT_SRC_COM Timer COM event source
+ * @arg TIM_EVT_SRC_TRIG Timer Trigger Event source
+ * @arg TIM_EVT_SRC_BREAK Timer Break event source
+ * @note
+ * - TIM6 and TIM7 can only generate an update event.
+ * - TIM_EVT_SRC_COM and TIM_EVT_SRC_BREAK are used only with TIM1 and TIM8.
+ */
+void TIM_GenerateEvent(TIM_Module* TIMx, uint16_t TIM_EventSource)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimEvtSrc(TIM_EventSource));
+
+ /* Set the event sources */
+ TIMx->EVTGEN = TIM_EventSource;
+}
+
+/**
+ * @brief Configures the TIMx's DMA interface.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select
+ * the TIM peripheral.
+ * @param TIM_DMABase DMA Base address.
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABase_CR, TIM_DMABASE_CTRL2, TIM_DMABASE_SMCTRL,
+ * TIM_DMABASE_DMAINTEN, TIM1_DMABase_SR, TIM_DMABASE_EVTGEN,
+ * TIM_DMABASE_CAPCMPMOD1, TIM_DMABASE_CAPCMPMOD2, TIM_DMABASE_CAPCMPEN,
+ * TIM_DMABASE_CNT, TIM_DMABASE_PSC, TIM_DMABASE_AR,
+ * TIM_DMABASE_REPCNT, TIM_DMABASE_CAPCMPDAT1, TIM_DMABASE_CAPCMPDAT2,
+ * TIM_DMABASE_CAPCMPDAT3, TIM_DMABASE_CAPCMPDAT4, TIM_DMABASE_BKDT,
+ * TIM_DMABASE_DMACTRL.
+ * @param TIM_DMABurstLength DMA Burst length.
+ * This parameter can be one value between:
+ * TIM_DMABURST_LENGTH_1TRANSFER and TIM_DMABURST_LENGTH_18TRANSFERS.
+ */
+void TIM_ConfigDma(TIM_Module* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
+{
+ /* Check the parameters */
+ assert_param(IsTimList4Module(TIMx));
+ assert_param(IsTimDmaBase(TIM_DMABase));
+ assert_param(IsTimDmaLength(TIM_DMABurstLength));
+ /* Set the DMA Base and the DMA Burst Length */
+ TIMx->DCTRL = TIM_DMABase | TIM_DMABurstLength;
+}
+
+/**
+ * @brief Enables or disables the TIMx's DMA Requests.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 6, 7, 8
+ * to select the TIM peripheral.
+ * @param TIM_DMASource specifies the DMA Request sources.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_DMA_UPDATE TIM update Interrupt source
+ * @arg TIM_DMA_CC1 TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2 TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3 TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4 TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM TIM Commutation DMA source
+ * @arg TIM_DMA_TRIG TIM Trigger DMA source
+ * @param Cmd new state of the DMA Request sources.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_EnableDma(TIM_Module* TIMx, uint16_t TIM_DMASource, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimList9Module(TIMx));
+ assert_param(IsTimDmaSrc(TIM_DMASource));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the DMA sources */
+ TIMx->DINTEN |= TIM_DMASource;
+ }
+ else
+ {
+ /* Disable the DMA sources */
+ TIMx->DINTEN &= (uint16_t)~TIM_DMASource;
+ }
+}
+
+/**
+ * @brief Configures the TIMx internal Clock
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8
+ * to select the TIM peripheral.
+ */
+void TIM_ConfigInternalClk(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ /* Disable slave mode to clock the prescaler directly with the internal clock */
+ TIMx->SMCTRL &= (uint16_t)(~((uint16_t)TIM_SMCTRL_SMSEL));
+}
+
+/**
+ * @brief Configures the TIMx Internal Trigger as External Clock
+ * @param TIMx where x can be 1, 2, 3, 4, 5 to select the TIM peripheral.
+ * @param TIM_InputTriggerSource Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TRIG_SEL_IN_TR0 Internal Trigger 0
+ * @arg TIM_TRIG_SEL_IN_TR1 Internal Trigger 1
+ * @arg TIM_TRIG_SEL_IN_TR2 Internal Trigger 2
+ * @arg TIM_TRIG_SEL_IN_TR3 Internal Trigger 3
+ */
+void TIM_ConfigInternalTrigToExt(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimInterTrigSel(TIM_InputTriggerSource));
+ /* Select the Internal Trigger */
+ TIM_SelectInputTrig(TIMx, TIM_InputTriggerSource);
+ /* Select the External clock mode1 */
+ TIMx->SMCTRL |= TIM_SLAVE_MODE_EXT1;
+}
+
+/**
+ * @brief Configures the TIMx Trigger as External Clock
+ * @param TIMx where x can be 1, 2, 3, 4, 5 to select the TIM peripheral.
+ * @param TIM_TIxExternalCLKSource Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_EXT_CLK_SRC_TI1ED TI1 Edge Detector
+ * @arg TIM_EXT_CLK_SRC_TI1 Filtered Timer Input 1
+ * @arg TIM_EXT_CLK_SRC_TI2 Filtered Timer Input 2
+ * @param IcPolarity specifies the TIx Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_POLARITY_RISING
+ * @arg TIM_IC_POLARITY_FALLING
+ * @param ICFilter specifies the filter value.
+ * This parameter must be a value between 0x0 and 0xF.
+ */
+void TIM_ConfigExtTrigAsClk(TIM_Module* TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t IcPolarity, uint16_t ICFilter)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimExtClkSrc(TIM_TIxExternalCLKSource));
+ assert_param(IsTimIcPalaritySingleEdge(IcPolarity));
+ assert_param(IsTimInCapFilter(ICFilter));
+ /* Configure the Timer Input Clock Source */
+ if (TIM_TIxExternalCLKSource == TIM_EXT_CLK_SRC_TI2)
+ {
+ ConfigTI2(TIMx, IcPolarity, TIM_IC_SELECTION_DIRECTTI, ICFilter);
+ }
+ else
+ {
+ ConfigTI1(TIMx, IcPolarity, TIM_IC_SELECTION_DIRECTTI, ICFilter);
+ }
+ /* Select the Trigger source */
+ TIM_SelectInputTrig(TIMx, TIM_TIxExternalCLKSource);
+ /* Select the External clock mode1 */
+ TIMx->SMCTRL |= TIM_SLAVE_MODE_EXT1;
+}
+
+/**
+ * @brief Configures the External clock Mode1
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_EXT_TRG_PSC_OFF ETRP Prescaler OFF.
+ * @arg TIM_EXT_TRG_PSC_DIV2 ETRP frequency divided by 2.
+ * @arg TIM_EXT_TRG_PSC_DIV4 ETRP frequency divided by 4.
+ * @arg TIM_EXT_TRG_PSC_DIV8 ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_EXT_TRIG_POLARITY_INVERTED active low or falling edge active.
+ * @arg TIM_EXT_TRIG_POLARITY_NONINVERTED active high or rising edge active.
+ * @param ExtTRGFilter External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ */
+void TIM_ConfigExtClkMode1(TIM_Module* TIMx,
+ uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter)
+{
+ uint16_t tmpsmcr = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimExtPreDiv(TIM_ExtTRGPrescaler));
+ assert_param(IsTimExtTrigPolarity(TIM_ExtTRGPolarity));
+ assert_param(IsTimExtTrigFilter(ExtTRGFilter));
+ /* Configure the ETR Clock source */
+ TIM_ConfigExtTrig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+
+ /* Get the TIMx SMCTRL register value */
+ tmpsmcr = TIMx->SMCTRL;
+ /* Reset the SMS Bits */
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_SMSEL));
+ /* Select the External clock mode1 */
+ tmpsmcr |= TIM_SLAVE_MODE_EXT1;
+ /* Select the Trigger selection : ETRF */
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_TSEL));
+ tmpsmcr |= TIM_TRIG_SEL_ETRF;
+ /* Write to TIMx SMCTRL */
+ TIMx->SMCTRL = tmpsmcr;
+}
+
+/**
+ * @brief Configures the External clock Mode2
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_EXT_TRG_PSC_OFF ETRP Prescaler OFF.
+ * @arg TIM_EXT_TRG_PSC_DIV2 ETRP frequency divided by 2.
+ * @arg TIM_EXT_TRG_PSC_DIV4 ETRP frequency divided by 4.
+ * @arg TIM_EXT_TRG_PSC_DIV8 ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_EXT_TRIG_POLARITY_INVERTED active low or falling edge active.
+ * @arg TIM_EXT_TRIG_POLARITY_NONINVERTED active high or rising edge active.
+ * @param ExtTRGFilter External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ */
+void TIM_ConfigExtClkMode2(TIM_Module* TIMx,
+ uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter)
+{
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimExtPreDiv(TIM_ExtTRGPrescaler));
+ assert_param(IsTimExtTrigPolarity(TIM_ExtTRGPolarity));
+ assert_param(IsTimExtTrigFilter(ExtTRGFilter));
+ /* Configure the ETR Clock source */
+ TIM_ConfigExtTrig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+ /* Enable the External clock mode2 */
+ TIMx->SMCTRL |= TIM_SMCTRL_EXCEN;
+}
+
+/**
+ * @brief Configures the TIMx External Trigger (ETR).
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_EXT_TRG_PSC_OFF ETRP Prescaler OFF.
+ * @arg TIM_EXT_TRG_PSC_DIV2 ETRP frequency divided by 2.
+ * @arg TIM_EXT_TRG_PSC_DIV4 ETRP frequency divided by 4.
+ * @arg TIM_EXT_TRG_PSC_DIV8 ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_EXT_TRIG_POLARITY_INVERTED active low or falling edge active.
+ * @arg TIM_EXT_TRIG_POLARITY_NONINVERTED active high or rising edge active.
+ * @param ExtTRGFilter External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ */
+void TIM_ConfigExtTrig(TIM_Module* TIMx,
+ uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter)
+{
+ uint16_t tmpsmcr = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimExtPreDiv(TIM_ExtTRGPrescaler));
+ assert_param(IsTimExtTrigPolarity(TIM_ExtTRGPolarity));
+ assert_param(IsTimExtTrigFilter(ExtTRGFilter));
+ tmpsmcr = TIMx->SMCTRL;
+ /* Reset the ETR Bits */
+ tmpsmcr &= SMCTRL_ETR_MASK;
+ /* Set the Prescaler, the Filter value and the Polarity */
+ tmpsmcr |=
+ (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
+ /* Write to TIMx SMCTRL */
+ TIMx->SMCTRL = tmpsmcr;
+}
+
+/**
+ * @brief Configures the TIMx Prescaler.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param Prescaler specifies the Prescaler Register value
+ * @param TIM_PSCReloadMode specifies the TIM Prescaler Reload mode
+ * This parameter can be one of the following values:
+ * @arg TIM_PSC_RELOAD_MODE_UPDATE The Prescaler is loaded at the update event.
+ * @arg TIM_PSC_RELOAD_MODE_IMMEDIATE The Prescaler is loaded immediately.
+ */
+void TIM_ConfigPrescaler(TIM_Module* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimPscReloadMode(TIM_PSCReloadMode));
+ /* Set the Prescaler value */
+ TIMx->PSC = Prescaler;
+ /* Set or reset the UG Bit */
+ TIMx->EVTGEN = TIM_PSCReloadMode;
+}
+
+/**
+ * @brief Specifies the TIMx Counter Mode to be used.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param CntMode specifies the Counter Mode to be used
+ * This parameter can be one of the following values:
+ * @arg TIM_CNT_MODE_UP TIM Up Counting Mode
+ * @arg TIM_CNT_MODE_DOWN TIM Down Counting Mode
+ * @arg TIM_CNT_MODE_CENTER_ALIGN1 TIM Center Aligned Mode1
+ * @arg TIM_CNT_MODE_CENTER_ALIGN2 TIM Center Aligned Mode2
+ * @arg TIM_CNT_MODE_CENTER_ALIGN3 TIM Center Aligned Mode3
+ */
+void TIM_ConfigCntMode(TIM_Module* TIMx, uint16_t CntMode)
+{
+ uint32_t tmpcr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimCntMode(CntMode));
+ tmpcr1 = TIMx->CTRL1;
+ /* Reset the CMS and DIR Bits */
+ tmpcr1 &= (uint32_t)(~((uint32_t)(TIM_CTRL1_DIR | TIM_CTRL1_CAMSEL)));
+ /* Set the Counter Mode */
+ tmpcr1 |= CntMode;
+ /* Write to TIMx CTRL1 register */
+ TIMx->CTRL1 = tmpcr1;
+}
+
+/**
+ * @brief Selects the Input Trigger source
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param TIM_InputTriggerSource The Input Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TRIG_SEL_IN_TR0 Internal Trigger 0
+ * @arg TIM_TRIG_SEL_IN_TR1 Internal Trigger 1
+ * @arg TIM_TRIG_SEL_IN_TR2 Internal Trigger 2
+ * @arg TIM_TRIG_SEL_IN_TR3 Internal Trigger 3
+ * @arg TIM_TRIG_SEL_TI1F_ED TI1 Edge Detector
+ * @arg TIM_TRIG_SEL_TI1FP1 Filtered Timer Input 1
+ * @arg TIM_TRIG_SEL_TI2FP2 Filtered Timer Input 2
+ * @arg TIM_TRIG_SEL_ETRF External Trigger input
+ */
+void TIM_SelectInputTrig(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource)
+{
+ uint16_t tmpsmcr = 0;
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimTrigSel(TIM_InputTriggerSource));
+ /* Get the TIMx SMCTRL register value */
+ tmpsmcr = TIMx->SMCTRL;
+ /* Reset the TS Bits */
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_TSEL));
+ /* Set the Input Trigger source */
+ tmpsmcr |= TIM_InputTriggerSource;
+ /* Write to TIMx SMCTRL */
+ TIMx->SMCTRL = tmpsmcr;
+}
+
+/**
+ * @brief Configures the TIMx Encoder Interface.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_EncoderMode specifies the TIMx Encoder Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_ENCODE_MODE_TI1 Counter counts on TI1FP1 edge depending on TI2FP2 level.
+ * @arg TIM_ENCODE_MODE_TI2 Counter counts on TI2FP2 edge depending on TI1FP1 level.
+ * @arg TIM_ENCODE_MODE_TI12 Counter counts on both TI1FP1 and TI2FP2 edges depending
+ * on the level of the other input.
+ * @param TIM_IC1Polarity specifies the IC1 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_POLARITY_FALLING IC Falling edge.
+ * @arg TIM_IC_POLARITY_RISING IC Rising edge.
+ * @param TIM_IC2Polarity specifies the IC2 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_POLARITY_FALLING IC Falling edge.
+ * @arg TIM_IC_POLARITY_RISING IC Rising edge.
+ */
+void TIM_ConfigEncoderInterface(TIM_Module* TIMx,
+ uint16_t TIM_EncoderMode,
+ uint16_t TIM_IC1Polarity,
+ uint16_t TIM_IC2Polarity)
+{
+ uint16_t tmpsmcr = 0;
+ uint16_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList5Module(TIMx));
+ assert_param(IsTimEncodeMode(TIM_EncoderMode));
+ assert_param(IsTimIcPalaritySingleEdge(TIM_IC1Polarity));
+ assert_param(IsTimIcPalaritySingleEdge(TIM_IC2Polarity));
+
+ /* Get the TIMx SMCTRL register value */
+ tmpsmcr = TIMx->SMCTRL;
+
+ /* Get the TIMx CCMOD1 register value */
+ tmpccmr1 = TIMx->CCMOD1;
+
+ /* Get the TIMx CCEN register value */
+ tmpccer = TIMx->CCEN;
+
+ /* Set the encoder Mode */
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_SMSEL));
+ tmpsmcr |= TIM_EncoderMode;
+
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+ tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD1_CC1SEL)) & (uint16_t)(~((uint16_t)TIM_CCMOD1_CC2SEL)));
+ tmpccmr1 |= TIM_CCMOD1_CC1SEL_0 | TIM_CCMOD1_CC2SEL_0;
+
+ /* Set the TI1 and the TI2 Polarities */
+ tmpccer &= (uint32_t)(((uint32_t) ~((uint32_t)TIM_CCEN_CC1P)) & ((uint32_t) ~((uint32_t)TIM_CCEN_CC2P)));
+ tmpccer |= (uint32_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
+
+ /* Write to TIMx SMCTRL */
+ TIMx->SMCTRL = tmpsmcr;
+ /* Write to TIMx CCMOD1 */
+ TIMx->CCMOD1 = tmpccmr1;
+ /* Write to TIMx CCEN */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Forces the TIMx output 1 waveform to active or inactive level.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC1REF
+ * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC1REF.
+ */
+void TIM_ConfigForcedOc1(TIM_Module* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimForceActive(TIM_ForcedAction));
+ tmpccmr1 = TIMx->CCMOD1;
+ /* Reset the OC1M Bits */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1M);
+ /* Configure The Forced output Mode */
+ tmpccmr1 |= TIM_ForcedAction;
+ /* Write to TIMx CCMOD1 register */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Forces the TIMx output 2 waveform to active or inactive level.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC2REF
+ * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC2REF.
+ */
+void TIM_ConfigForcedOc2(TIM_Module* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimForceActive(TIM_ForcedAction));
+ tmpccmr1 = TIMx->CCMOD1;
+ /* Reset the OC2M Bits */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2M);
+ /* Configure The Forced output Mode */
+ tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
+ /* Write to TIMx CCMOD1 register */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Forces the TIMx output 3 waveform to active or inactive level.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC3REF
+ * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC3REF.
+ */
+void TIM_ConfigForcedOc3(TIM_Module* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimForceActive(TIM_ForcedAction));
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC1M Bits */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3MD);
+ /* Configure The Forced output Mode */
+ tmpccmr2 |= TIM_ForcedAction;
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Forces the TIMx output 4 waveform to active or inactive level.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC4REF
+ * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC4REF.
+ */
+void TIM_ConfigForcedOc4(TIM_Module* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimForceActive(TIM_ForcedAction));
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC2M Bits */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4MD);
+ /* Configure The Forced output Mode */
+ tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Forces the TIMx output 5 waveform to active or inactive level.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC5REF
+ * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC5REF.
+ */
+void TIM_ConfigForcedOc5(TIM_Module* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimForceActive(TIM_ForcedAction));
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC2M Bits */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5MD);
+ /* Configure The Forced output Mode */
+ tmpccmr3 |= (uint16_t)(TIM_ForcedAction);
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Forces the TIMx output 6 waveform to active or inactive level.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC6REF
+ * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC6REF.
+ */
+void TIM_ConfigForcedOc6(TIM_Module* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimForceActive(TIM_ForcedAction));
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC2M Bits */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6MD);
+ /* Configure The Forced output Mode */
+ tmpccmr3 |= (uint16_t)(TIM_ForcedAction << 8);
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Enables or disables TIMx peripheral Preload register on AR.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param Cmd new state of the TIMx peripheral Preload register
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_ConfigArPreload(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set the AR Preload Bit */
+ TIMx->CTRL1 |= TIM_CTRL1_ARPEN;
+ }
+ else
+ {
+ /* Reset the AR Preload Bit */
+ TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_ARPEN);
+ }
+}
+
+/**
+ * @brief Selects the TIM peripheral Commutation event.
+ * @param TIMx where x can be 1, 8 to select the TIMx peripheral
+ * @param Cmd new state of the Commutation event.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_SelectComEvt(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimList2Module(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set the COM Bit */
+ TIMx->CTRL2 |= TIM_CTRL2_CCUSEL;
+ }
+ else
+ {
+ /* Reset the COM Bit */
+ TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_CCUSEL);
+ }
+}
+
+/**
+ * @brief Selects the TIMx peripheral Capture Compare DMA source.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select
+ * the TIM peripheral.
+ * @param Cmd new state of the Capture Compare DMA source
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_SelectCapCmpDmaSrc(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimList4Module(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set the CCDS Bit */
+ TIMx->CTRL2 |= TIM_CTRL2_CCDSEL;
+ }
+ else
+ {
+ /* Reset the CCDS Bit */
+ TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_CCDSEL);
+ }
+}
+
+/**
+ * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8
+ * to select the TIMx peripheral
+ * @param Cmd new state of the Capture Compare Preload Control bit
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_EnableCapCmpPreloadControl(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimList5Module(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set the CCPC Bit */
+ TIMx->CTRL2 |= TIM_CTRL2_CCPCTL;
+ }
+ else
+ {
+ /* Reset the CCPC Bit */
+ TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_CCPCTL);
+ }
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCDAT1.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_OCPreload new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_PRE_LOAD_ENABLE
+ * @arg TIM_OC_PRE_LOAD_DISABLE
+ */
+void TIM_ConfigOc1Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimOcPreLoadState(TIM_OCPreload));
+ tmpccmr1 = TIMx->CCMOD1;
+ /* Reset the OC1PE Bit */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1PEN);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr1 |= TIM_OCPreload;
+ /* Write to TIMx CCMOD1 register */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCDAT2.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select
+ * the TIM peripheral.
+ * @param TIM_OCPreload new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_PRE_LOAD_ENABLE
+ * @arg TIM_OC_PRE_LOAD_DISABLE
+ */
+void TIM_ConfigOc2Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimOcPreLoadState(TIM_OCPreload));
+ tmpccmr1 = TIMx->CCMOD1;
+ /* Reset the OC2PE Bit */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2PEN);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
+ /* Write to TIMx CCMOD1 register */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCDAT3.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_PRE_LOAD_ENABLE
+ * @arg TIM_OC_PRE_LOAD_DISABLE
+ */
+void TIM_ConfigOc3Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcPreLoadState(TIM_OCPreload));
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC3PE Bit */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3PEN);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr2 |= TIM_OCPreload;
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCDAT4.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_PRE_LOAD_ENABLE
+ * @arg TIM_OC_PRE_LOAD_DISABLE
+ */
+void TIM_ConfigOc4Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcPreLoadState(TIM_OCPreload));
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC4PE Bit */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4PEN);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCDAT5.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_PRE_LOAD_ENABLE
+ * @arg TIM_OC_PRE_LOAD_DISABLE
+ */
+void TIM_ConfigOc5Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcPreLoadState(TIM_OCPreload));
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC5PE Bit */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5PEN);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr3 |= (uint16_t)(TIM_OCPreload);
+ /* Write to TIMx CCMOD3 register */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCDAT6.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_PRE_LOAD_ENABLE
+ * @arg TIM_OC_PRE_LOAD_DISABLE
+ */
+void TIM_ConfigOc6Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcPreLoadState(TIM_OCPreload));
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC6PE Bit */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6PEN);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr3 |= (uint16_t)(TIM_OCPreload << 8);
+ /* Write to TIMx CCMOD3 register */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 1 Fast feature.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_OCFast new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable
+ * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable
+ */
+void TIM_ConfigOc1Fast(TIM_Module* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimOcFastState(TIM_OCFast));
+ /* Get the TIMx CCMOD1 register value */
+ tmpccmr1 = TIMx->CCMOD1;
+ /* Reset the OC1FE Bit */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1FEN);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr1 |= TIM_OCFast;
+ /* Write to TIMx CCMOD1 */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 2 Fast feature.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select
+ * the TIM peripheral.
+ * @param TIM_OCFast new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable
+ * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable
+ */
+void TIM_ConfigOc2Fast(TIM_Module* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimOcFastState(TIM_OCFast));
+ /* Get the TIMx CCMOD1 register value */
+ tmpccmr1 = TIMx->CCMOD1;
+ /* Reset the OC2FE Bit */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2FEN);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
+ /* Write to TIMx CCMOD1 */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 3 Fast feature.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable
+ * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable
+ */
+void TIM_ConfigOc3Fast(TIM_Module* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcFastState(TIM_OCFast));
+ /* Get the TIMx CCMOD2 register value */
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC3FE Bit */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3FEN);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr2 |= TIM_OCFast;
+ /* Write to TIMx CCMOD2 */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 4 Fast feature.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable
+ * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable
+ */
+void TIM_ConfigOc4Fast(TIM_Module* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcFastState(TIM_OCFast));
+ /* Get the TIMx CCMOD2 register value */
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC4FE Bit */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4FEN);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
+ /* Write to TIMx CCMOD2 */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 5 Fast feature.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable
+ * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable
+ */
+void TIM_ConfigOc5Fast(TIM_Module* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcFastState(TIM_OCFast));
+ /* Get the TIMx CCMOD2 register value */
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC4FE Bit */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5FEN);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr3 |= (uint16_t)(TIM_OCFast);
+ /* Write to TIMx CCMOD3 */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 6 Fast feature.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable
+ * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable
+ */
+void TIM_ConfigOc6Fast(TIM_Module* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcFastState(TIM_OCFast));
+ /* Get the TIMx CCMOD2 register value */
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC4FE Bit */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6FEN);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr3 |= (uint16_t)(TIM_OCFast << 8);
+ /* Write to TIMx CCMOD3 */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF1 signal on an external event
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_CLR_ENABLE TIM Output clear enable
+ * @arg TIM_OC_CLR_DISABLE TIM Output clear disable
+ */
+void TIM_ClrOc1Ref(TIM_Module* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcClrState(TIM_OCClear));
+
+ tmpccmr1 = TIMx->CCMOD1;
+
+ /* Reset the OC1CE Bit */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1CEN);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr1 |= TIM_OCClear;
+ /* Write to TIMx CCMOD1 register */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF2 signal on an external event
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_CLR_ENABLE TIM Output clear enable
+ * @arg TIM_OC_CLR_DISABLE TIM Output clear disable
+ */
+void TIM_ClrOc2Ref(TIM_Module* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcClrState(TIM_OCClear));
+ tmpccmr1 = TIMx->CCMOD1;
+ /* Reset the OC2CE Bit */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2CEN);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
+ /* Write to TIMx CCMOD1 register */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF3 signal on an external event
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_CLR_ENABLE TIM Output clear enable
+ * @arg TIM_OC_CLR_DISABLE TIM Output clear disable
+ */
+void TIM_ClrOc3Ref(TIM_Module* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcClrState(TIM_OCClear));
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC3CE Bit */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3CEN);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr2 |= TIM_OCClear;
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF4 signal on an external event
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_CLR_ENABLE TIM Output clear enable
+ * @arg TIM_OC_CLR_DISABLE TIM Output clear disable
+ */
+void TIM_ClrOc4Ref(TIM_Module* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcClrState(TIM_OCClear));
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC4CE Bit */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4CEN);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF5 signal on an external event
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_CLR_ENABLE TIM Output clear enable
+ * @arg TIM_OC_CLR_DISABLE TIM Output clear disable
+ */
+void TIM_ClrOc5Ref(TIM_Module* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcClrState(TIM_OCClear));
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC4CE Bit */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5CEN);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr3 |= (uint16_t)(TIM_OCClear);
+ /* Write to TIMx CCMOD3 register */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF6 signal on an external event
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_CLR_ENABLE TIM Output clear enable
+ * @arg TIM_OC_CLR_DISABLE TIM Output clear disable
+ */
+void TIM_ClrOc6Ref(TIM_Module* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcClrState(TIM_OCClear));
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC4CE Bit */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6CEN);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr3 |= (uint16_t)(TIM_OCClear << 8);
+ /* Write to TIMx CCMOD3 register */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Configures the TIMx channel 1 polarity.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param OcPolarity specifies the OC1 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OC_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc1Polarity(TIM_Module* TIMx, uint16_t OcPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimOcPolarity(OcPolarity));
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC1P Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC1P);
+ tmpccer |= OcPolarity;
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx Channel 1N polarity.
+ * @param TIMx where x can be 1, 8 to select the TIM peripheral.
+ * @param OcNPolarity specifies the OC1N Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCN_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OCN_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc1NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList2Module(TIMx));
+ assert_param(IsTimOcnPolarity(OcNPolarity));
+
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC1NP Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC1NP);
+ tmpccer |= OcNPolarity;
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 2 polarity.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param OcPolarity specifies the OC2 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OC_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc2Polarity(TIM_Module* TIMx, uint16_t OcPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimOcPolarity(OcPolarity));
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC2P Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC2P);
+ tmpccer |= (uint32_t)(OcPolarity << 4);
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx Channel 2N polarity.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param OcNPolarity specifies the OC2N Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCN_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OCN_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc2NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcnPolarity(OcNPolarity));
+
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC2NP Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC2NP);
+ tmpccer |= (uint32_t)(OcNPolarity << 4);
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 3 polarity.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param OcPolarity specifies the OC3 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OC_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc3Polarity(TIM_Module* TIMx, uint16_t OcPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcPolarity(OcPolarity));
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC3P Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC3P);
+ tmpccer |= (uint32_t)(OcPolarity << 8);
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx Channel 3N polarity.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param OcNPolarity specifies the OC3N Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCN_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OCN_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc3NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity)
+{
+ uint32_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcnPolarity(OcNPolarity));
+
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC3NP Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC3NP);
+ tmpccer |= (uint32_t)(OcNPolarity << 8);
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 4 polarity.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param OcPolarity specifies the OC4 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OC_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc4Polarity(TIM_Module* TIMx, uint16_t OcPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcPolarity(OcPolarity));
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC4P Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC4P);
+ tmpccer |= (uint32_t)(OcPolarity << 12);
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 5 polarity.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param OcPolarity specifies the OC5 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OC_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc5Polarity(TIM_Module* TIMx, uint16_t OcPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcPolarity(OcPolarity));
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC5P Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC5P);
+ tmpccer |= (uint32_t)(OcPolarity << 16);
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 6 polarity.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param OcPolarity specifies the OC6 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OC_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc6Polarity(TIM_Module* TIMx, uint16_t OcPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcPolarity(OcPolarity));
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC6P Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC6P);
+ tmpccer |= (uint32_t)(OcPolarity << 20);
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel x.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CH_1 TIM Channel 1
+ * @arg TIM_CH_2 TIM Channel 2
+ * @arg TIM_CH_3 TIM Channel 3
+ * @arg TIM_CH_4 TIM Channel 4
+ * @param TIM_CCx specifies the TIM Channel CCxE bit new state.
+ * This parameter can be: TIM_CAP_CMP_ENABLE or TIM_CAP_CMP_DISABLE.
+ */
+void TIM_EnableCapCmpCh(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCx)
+{
+ uint16_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimCh(Channel));
+ assert_param(IsTimCapCmpState(TIM_CCx));
+
+ tmp = CAPCMPEN_CCE_SET << Channel;
+
+ /* Reset the CCxE Bit */
+ TIMx->CCEN &= (uint32_t)~tmp;
+
+ /* Set or reset the CCxE Bit */
+ TIMx->CCEN |= (uint32_t)(TIM_CCx << Channel);
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel xN.
+ * @param TIMx where x can be 1, 8 to select the TIM peripheral.
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CH_1 TIM Channel 1
+ * @arg TIM_CH_2 TIM Channel 2
+ * @arg TIM_CH_3 TIM Channel 3
+ * @param TIM_CCxN specifies the TIM Channel CCxNE bit new state.
+ * This parameter can be: TIM_CAP_CMP_N_ENABLE or TIM_CAP_CMP_N_DISABLE.
+ */
+void TIM_EnableCapCmpChN(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCxN)
+{
+ uint16_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList2Module(TIMx));
+ assert_param(IsTimComplementaryCh(Channel));
+ assert_param(IsTimCapCmpNState(TIM_CCxN));
+
+ tmp = CAPCMPEN_CCNE_SET << Channel;
+
+ /* Reset the CCxNE Bit */
+ TIMx->CCEN &= (uint32_t)~tmp;
+
+ /* Set or reset the CCxNE Bit */
+ TIMx->CCEN |= (uint32_t)(TIM_CCxN << Channel);
+}
+
+/**
+ * @brief Selects the TIM Output Compare Mode.
+ * @note This function disables the selected channel before changing the Output
+ * Compare Mode.
+ * User has to enable this channel using TIM_EnableCapCmpCh and TIM_EnableCapCmpChN functions.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CH_1 TIM Channel 1
+ * @arg TIM_CH_2 TIM Channel 2
+ * @arg TIM_CH_3 TIM Channel 3
+ * @arg TIM_CH_4 TIM Channel 4
+ * @param OcMode specifies the TIM Output Compare Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCMODE_TIMING
+ * @arg TIM_OCMODE_ACTIVE
+ * @arg TIM_OCMODE_TOGGLE
+ * @arg TIM_OCMODE_PWM1
+ * @arg TIM_OCMODE_PWM2
+ * @arg TIM_FORCED_ACTION_ACTIVE
+ * @arg TIM_FORCED_ACTION_INACTIVE
+ */
+void TIM_SelectOcMode(TIM_Module* TIMx, uint16_t Channel, uint16_t OcMode)
+{
+ uint32_t tmp = 0;
+ uint16_t tmp1 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimCh(Channel));
+ assert_param(IsTimOc(OcMode));
+
+ tmp = (uint32_t)TIMx;
+ tmp += CAPCMPMOD_OFFSET;
+
+ tmp1 = CAPCMPEN_CCE_SET << (uint16_t)Channel;
+
+ /* Disable the Channel: Reset the CCxE Bit */
+ TIMx->CCEN &= (uint16_t)~tmp1;
+
+ if ((Channel == TIM_CH_1) || (Channel == TIM_CH_3))
+ {
+ tmp += (Channel >> 1);
+
+ /* Reset the OCxM bits in the CCMRx register */
+ *(__IO uint32_t*)tmp &= (uint32_t) ~((uint32_t)TIM_CCMOD1_OC1M);
+
+ /* Configure the OCxM bits in the CCMRx register */
+ *(__IO uint32_t*)tmp |= OcMode;
+ }
+ else
+ {
+ tmp += (uint16_t)(Channel - (uint16_t)4) >> (uint16_t)1;
+
+ /* Reset the OCxM bits in the CCMRx register */
+ *(__IO uint32_t*)tmp &= (uint32_t) ~((uint32_t)TIM_CCMOD1_OC2M);
+
+ /* Configure the OCxM bits in the CCMRx register */
+ *(__IO uint32_t*)tmp |= (uint16_t)(OcMode << 8);
+ }
+}
+
+/**
+ * @brief Enables or Disables the TIMx Update event.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param Cmd new state of the TIMx UDIS bit
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_EnableUpdateEvt(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set the Update Disable Bit */
+ TIMx->CTRL1 |= TIM_CTRL1_UPDIS;
+ }
+ else
+ {
+ /* Reset the Update Disable Bit */
+ TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_UPDIS);
+ }
+}
+
+/**
+ * @brief Configures the TIMx Update Request Interrupt source.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_UpdateSource specifies the Update source.
+ * This parameter can be one of the following values:
+ * @arg TIM_UPDATE_SRC_REGULAr Source of update is the counter overflow/underflow
+ or the setting of UG bit, or an update generation
+ through the slave mode controller.
+ * @arg TIM_UPDATE_SRC_GLOBAL Source of update is counter overflow/underflow.
+ */
+void TIM_ConfigUpdateRequestIntSrc(TIM_Module* TIMx, uint16_t TIM_UpdateSource)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimUpdateSrc(TIM_UpdateSource));
+ if (TIM_UpdateSource != TIM_UPDATE_SRC_GLOBAL)
+ {
+ /* Set the URS Bit */
+ TIMx->CTRL1 |= TIM_CTRL1_UPRS;
+ }
+ else
+ {
+ /* Reset the URS Bit */
+ TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_UPRS);
+ }
+}
+
+/**
+ * @brief Enables or disables the TIMx's Hall sensor interface.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param Cmd new state of the TIMx Hall sensor interface.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_SelectHallSensor(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set the TI1S Bit */
+ TIMx->CTRL2 |= TIM_CTRL2_TI1SEL;
+ }
+ else
+ {
+ /* Reset the TI1S Bit */
+ TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_TI1SEL);
+ }
+}
+
+/**
+ * @brief Selects the TIMx's One Pulse Mode.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_OPMode specifies the OPM Mode to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_OPMODE_SINGLE
+ * @arg TIM_OPMODE_REPET
+ */
+void TIM_SelectOnePulseMode(TIM_Module* TIMx, uint16_t TIM_OPMode)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimOpMOde(TIM_OPMode));
+ /* Reset the OPM Bit */
+ TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_ONEPM);
+ /* Configure the OPM Mode */
+ TIMx->CTRL1 |= TIM_OPMode;
+}
+
+/**
+ * @brief Selects the TIMx Trigger Output Mode.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 6, 7, 8 to select the TIM peripheral.
+ * @param TIM_TRGOSource specifies the Trigger Output source.
+ * This paramter can be one of the following values:
+ *
+ * - For all TIMx
+ * @arg TIM_TRGO_SRC_RESET The UG bit in the TIM_EVTGEN register is used as the trigger output (TRGO).
+ * @arg TIM_TRGO_SRC_ENABLE The Counter Enable CEN is used as the trigger output (TRGO).
+ * @arg TIM_TRGO_SRC_UPDATE The update event is selected as the trigger output (TRGO).
+ *
+ * - For all TIMx except TIM6 and TIM7
+ * @arg TIM_TRGO_SRC_OC1 The trigger output sends a positive pulse when the CC1IF flag
+ * is to be set, as soon as a capture or compare match occurs (TRGO).
+ * @arg TIM_TRGO_SRC_OC1REF OC1REF signal is used as the trigger output (TRGO).
+ * @arg TIM_TRGO_SRC_OC2REF OC2REF signal is used as the trigger output (TRGO).
+ * @arg TIM_TRGO_SRC_OC3REF OC3REF signal is used as the trigger output (TRGO).
+ * @arg TIM_TRGO_SRC_OC4REF OC4REF signal is used as the trigger output (TRGO).
+ *
+ */
+void TIM_SelectOutputTrig(TIM_Module* TIMx, uint16_t TIM_TRGOSource)
+{
+ /* Check the parameters */
+ assert_param(IsTimList7Module(TIMx));
+ assert_param(IsTimTrgoSrc(TIM_TRGOSource));
+ /* Reset the MMS Bits */
+ TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_MMSEL);
+ /* Select the TRGO source */
+ TIMx->CTRL2 |= TIM_TRGOSource;
+}
+
+/**
+ * @brief Selects the TIMx Slave Mode.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param TIM_SlaveMode specifies the Timer Slave Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_SLAVE_MODE_RESET Rising edge of the selected trigger signal (TRGI) re-initializes
+ * the counter and triggers an update of the registers.
+ * @arg TIM_SLAVE_MODE_GATED The counter clock is enabled when the trigger signal (TRGI) is high.
+ * @arg TIM_SLAVE_MODE_TRIG The counter starts at a rising edge of the trigger TRGI.
+ * @arg TIM_SLAVE_MODE_EXT1 Rising edges of the selected trigger (TRGI) clock the counter.
+ */
+void TIM_SelectSlaveMode(TIM_Module* TIMx, uint16_t TIM_SlaveMode)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimSlaveMode(TIM_SlaveMode));
+ /* Reset the SMS Bits */
+ TIMx->SMCTRL &= (uint16_t) ~((uint16_t)TIM_SMCTRL_SMSEL);
+ /* Select the Slave Mode */
+ TIMx->SMCTRL |= TIM_SlaveMode;
+}
+
+/**
+ * @brief Sets or Resets the TIMx Master/Slave Mode.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param TIM_MasterSlaveMode specifies the Timer Master Slave Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_MASTER_SLAVE_MODE_ENABLE synchronization between the current timer
+ * and its slaves (through TRGO).
+ * @arg TIM_MASTER_SLAVE_MODE_DISABLE No action
+ */
+void TIM_SelectMasterSlaveMode(TIM_Module* TIMx, uint16_t TIM_MasterSlaveMode)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimMasterSlaveMode(TIM_MasterSlaveMode));
+ /* Reset the MSM Bit */
+ TIMx->SMCTRL &= (uint16_t) ~((uint16_t)TIM_SMCTRL_MSMD);
+
+ /* Set or Reset the MSM Bit */
+ TIMx->SMCTRL |= TIM_MasterSlaveMode;
+}
+
+/**
+ * @brief Sets the TIMx Counter Register value
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param Counter specifies the Counter register new value.
+ */
+void TIM_SetCnt(TIM_Module* TIMx, uint16_t Counter)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ /* Set the Counter Register value */
+ TIMx->CNT = Counter;
+}
+
+/**
+ * @brief Sets the TIMx Autoreload Register value
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param Autoreload specifies the Autoreload register new value.
+ */
+void TIM_SetAutoReload(TIM_Module* TIMx, uint16_t Autoreload)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ /* Set the Autoreload Register value */
+ TIMx->AR = Autoreload;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare1 Register value
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param Compare1 specifies the Capture Compare1 register new value.
+ */
+void TIM_SetCmp1(TIM_Module* TIMx, uint16_t Compare1)
+{
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ /* Set the Capture Compare1 Register value */
+ TIMx->CCDAT1 = Compare1;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare2 Register value
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param Compare2 specifies the Capture Compare2 register new value.
+ */
+void TIM_SetCmp2(TIM_Module* TIMx, uint16_t Compare2)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ /* Set the Capture Compare2 Register value */
+ TIMx->CCDAT2 = Compare2;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare3 Register value
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param Compare3 specifies the Capture Compare3 register new value.
+ */
+void TIM_SetCmp3(TIM_Module* TIMx, uint16_t Compare3)
+{
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ /* Set the Capture Compare3 Register value */
+ TIMx->CCDAT3 = Compare3;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare4 Register value
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param Compare4 specifies the Capture Compare4 register new value.
+ */
+void TIM_SetCmp4(TIM_Module* TIMx, uint16_t Compare4)
+{
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ /* Set the Capture Compare4 Register value */
+ TIMx->CCDAT4 = Compare4;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare5 Register value
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param Compare5 specifies the Capture Compare5 register new value.
+ */
+void TIM_SetCmp5(TIM_Module* TIMx, uint16_t Compare5)
+{
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ /* Set the Capture Compare4 Register value */
+ TIMx->CCDAT5 = Compare5;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare4 Register value
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param Compare6 specifies the Capture Compare6 register new value.
+ */
+void TIM_SetCmp6(TIM_Module* TIMx, uint16_t Compare6)
+{
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ /* Set the Capture Compare4 Register value */
+ TIMx->CCDAT6 = Compare6;
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 1 prescaler.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_ICPSC specifies the Input Capture1 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_PSC_DIV1 no prescaler
+ * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events
+ * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events
+ * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events
+ */
+void TIM_SetInCap1Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimIcPrescaler(TIM_ICPSC));
+ /* Reset the IC1PSC Bits */
+ TIMx->CCMOD1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_IC1PSC);
+ /* Set the IC1PSC value */
+ TIMx->CCMOD1 |= TIM_ICPSC;
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 2 prescaler.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param TIM_ICPSC specifies the Input Capture2 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_PSC_DIV1 no prescaler
+ * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events
+ * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events
+ * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events
+ */
+void TIM_SetInCap2Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimIcPrescaler(TIM_ICPSC));
+ /* Reset the IC2PSC Bits */
+ TIMx->CCMOD1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_IC2PSC);
+ /* Set the IC2PSC value */
+ TIMx->CCMOD1 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 3 prescaler.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPSC specifies the Input Capture3 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_PSC_DIV1 no prescaler
+ * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events
+ * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events
+ * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events
+ */
+void TIM_SetInCap3Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimIcPrescaler(TIM_ICPSC));
+ /* Reset the IC3PSC Bits */
+ TIMx->CCMOD2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_IC3PSC);
+ /* Set the IC3PSC value */
+ TIMx->CCMOD2 |= TIM_ICPSC;
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 4 prescaler.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPSC specifies the Input Capture4 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_PSC_DIV1 no prescaler
+ * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events
+ * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events
+ * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events
+ */
+void TIM_SetInCap4Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimIcPrescaler(TIM_ICPSC));
+ /* Reset the IC4PSC Bits */
+ TIMx->CCMOD2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_IC4PSC);
+ /* Set the IC4PSC value */
+ TIMx->CCMOD2 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/**
+ * @brief Sets the TIMx Clock Division value.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select
+ * the TIM peripheral.
+ * @param TIM_CKD specifies the clock division value.
+ * This parameter can be one of the following value:
+ * @arg TIM_CLK_DIV1 TDTS = Tck_tim
+ * @arg TIM_CLK_DIV2 TDTS = 2*Tck_tim
+ * @arg TIM_CLK_DIV4 TDTS = 4*Tck_tim
+ */
+void TIM_SetClkDiv(TIM_Module* TIMx, uint16_t TIM_CKD)
+{
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimClkDiv(TIM_CKD));
+ /* Reset the CKD Bits */
+ TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_CLKD);
+ /* Set the CKD value */
+ TIMx->CTRL1 |= TIM_CKD;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 1 value.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @return Capture Compare 1 Register value.
+ */
+uint16_t TIM_GetCap1(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ /* Get the Capture 1 Register value */
+ return TIMx->CCDAT1;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 2 value.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @return Capture Compare 2 Register value.
+ */
+uint16_t TIM_GetCap2(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ /* Get the Capture 2 Register value */
+ return TIMx->CCDAT2;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 3 value.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @return Capture Compare 3 Register value.
+ */
+uint16_t TIM_GetCap3(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ /* Get the Capture 3 Register value */
+ return TIMx->CCDAT3;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 4 value.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @return Capture Compare 4 Register value.
+ */
+uint16_t TIM_GetCap4(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ /* Get the Capture 4 Register value */
+ return TIMx->CCDAT4;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 5 value.
+ * @param TIMx where x can be 1 8 to select the TIM peripheral.
+ * @return Capture Compare 5 Register value.
+ */
+uint16_t TIM_GetCap5(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ /* Get the Capture 5 Register value */
+ return TIMx->CCDAT5;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 6 value.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @return Capture Compare 6 Register value.
+ */
+uint16_t TIM_GetCap6(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ /* Get the Capture 6 Register value */
+ return TIMx->CCDAT6;
+}
+
+/**
+ * @brief Gets the TIMx Counter value.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @return Counter Register value.
+ */
+uint16_t TIM_GetCnt(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ /* Get the Counter Register value */
+ return TIMx->CNT;
+}
+
+/**
+ * @brief Gets the TIMx Prescaler value.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @return Prescaler Register value.
+ */
+uint16_t TIM_GetPrescaler(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ /* Get the Prescaler Register value */
+ return TIMx->PSC;
+}
+
+/**
+ * @brief Gets the TIMx Prescaler value.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @return Prescaler Register value.
+ */
+uint16_t TIM_GetAutoReload(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ /* Get the Prescaler Register value */
+ return TIMx->AR;
+}
+
+/**
+ * @brief Checks whether the specified TIM flag is set or not.
+ * @param TIMx where x can be 1 to 5 , 8 ,9 to select the TIM peripheral.
+ * @param TIM_CCEN specifies the Bit to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_CC1EN CC1EN Bit
+ * @arg TIM_CC1NEN CC1NEN Bit
+ * @arg TIM_CC2EN CC2EN Bit
+ * @arg TIM_CC2NEN CC2NEN Bit
+ * @arg TIM_CC3EN CC3EN Bit
+ * @arg TIM_CC3NEN CC3NEN Bit
+ * @arg TIM_CC4EN CC4EN Bit
+ * @arg TIM_CC5EN CC5EN Bit
+ * @arg TIM_CC6EN CC6EN Bit
+ * @note
+ * - TIM_CC1NEN TIM_CC2NEN TIM_CC3NEN is used only with TIM1, TIM8.
+ * @return The new state of TIM_FLAG (SET or RESET).
+ */
+FlagStatus TIM_GetCCENStatus(TIM_Module* TIMx, uint32_t TIM_CCEN)
+{
+ INTStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+
+ if (TIMx==TIM1 || TIMx==TIM8){
+ assert_param(IsAdvancedTimCCENFlag(TIM_CCEN));
+ if ((TIMx->CCEN & TIM_CCEN) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }else if (TIMx==TIM2 || TIMx==TIM3 || TIMx==TIM4 || TIMx==TIM5 || TIMx==TIM9){
+ assert_param(IsGeneralTimCCENFlag(TIM_CCEN));
+ if ((TIMx->CCEN & TIM_CCEN) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+
+ return bitstatus;
+}
+
+/**
+ * @brief Checks whether the specified TIM flag is set or not.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_FLAG specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_FLAG_UPDATE TIM update Flag
+ * @arg TIM_FLAG_CC1 TIM Capture Compare 1 Flag
+ * @arg TIM_FLAG_CC2 TIM Capture Compare 2 Flag
+ * @arg TIM_FLAG_CC3 TIM Capture Compare 3 Flag
+ * @arg TIM_FLAG_CC4 TIM Capture Compare 4 Flag
+ * @arg TIM_FLAG_COM TIM Commutation Flag
+ * @arg TIM_FLAG_TRIG TIM Trigger Flag
+ * @arg TIM_FLAG_BREAK TIM Break Flag
+ * @arg TIM_FLAG_CC1OF TIM Capture Compare 1 overcapture Flag
+ * @arg TIM_FLAG_CC2OF TIM Capture Compare 2 overcapture Flag
+ * @arg TIM_FLAG_CC3OF TIM Capture Compare 3 overcapture Flag
+ * @arg TIM_FLAG_CC4OF TIM Capture Compare 4 overcapture Flag
+ * @arg TIM_FLAG_CC5 TIM Capture Compare 5 Flag
+ * @arg TIM_FLAG_CC6 TIM Capture Compare 6 Flag
+ * @note
+ * - TIM6 and TIM7 can have only one update flag.
+ * - TIM_FLAG_BREAK is used only with TIM1, TIM8.
+ * - TIM_FLAG_COM is used only with TIM1, TIM8.
+ * @return The new state of TIM_FLAG (SET or RESET).
+ */
+FlagStatus TIM_GetFlagStatus(TIM_Module* TIMx, uint32_t TIM_FLAG)
+{
+ INTStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimGetFlag(TIM_FLAG));
+
+ if ((TIMx->STS & TIM_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the TIMx's pending flags.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_FLAG specifies the flag bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_FLAG_UPDATE TIM update Flag
+ * @arg TIM_FLAG_CC1 TIM Capture Compare 1 Flag
+ * @arg TIM_FLAG_CC2 TIM Capture Compare 2 Flag
+ * @arg TIM_FLAG_CC3 TIM Capture Compare 3 Flag
+ * @arg TIM_FLAG_CC4 TIM Capture Compare 4 Flag
+ * @arg TIM_FLAG_COM TIM Commutation Flag
+ * @arg TIM_FLAG_TRIG TIM Trigger Flag
+ * @arg TIM_FLAG_BREAK TIM Break Flag
+ * @arg TIM_FLAG_CC1OF TIM Capture Compare 1 overcapture Flag
+ * @arg TIM_FLAG_CC2OF TIM Capture Compare 2 overcapture Flag
+ * @arg TIM_FLAG_CC3OF TIM Capture Compare 3 overcapture Flag
+ * @arg TIM_FLAG_CC4OF TIM Capture Compare 4 overcapture Flag
+ * @note
+ * - TIM6 and TIM7 can have only one update flag.
+ * - TIM_FLAG_BREAK is used only with TIM1, TIM8.
+ * - TIM_FLAG_COM is used only with TIM1, TIM8.
+ */
+void TIM_ClearFlag(TIM_Module* TIMx, uint32_t TIM_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimClrFlag(TIM_FLAG));
+
+ /* Clear the flags */
+ TIMx->STS = (uint32_t)~TIM_FLAG;
+}
+
+/**
+ * @brief Checks whether the TIM interrupt has occurred or not.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_IT specifies the TIM interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_INT_UPDATE TIM update Interrupt source
+ * @arg TIM_INT_CC1 TIM Capture Compare 1 Interrupt source
+ * @arg TIM_INT_CC2 TIM Capture Compare 2 Interrupt source
+ * @arg TIM_INT_CC3 TIM Capture Compare 3 Interrupt source
+ * @arg TIM_INT_CC4 TIM Capture Compare 4 Interrupt source
+ * @arg TIM_INT_COM TIM Commutation Interrupt source
+ * @arg TIM_INT_TRIG TIM Trigger Interrupt source
+ * @arg TIM_INT_BREAK TIM Break Interrupt source
+ * @note
+ * - TIM6 and TIM7 can generate only an update interrupt.
+ * - TIM_INT_BREAK is used only with TIM1, TIM8.
+ * - TIM_INT_COM is used only with TIM1, TIM8.
+ * @return The new state of the TIM_IT(SET or RESET).
+ */
+INTStatus TIM_GetIntStatus(TIM_Module* TIMx, uint32_t TIM_IT)
+{
+ INTStatus bitstatus = RESET;
+ uint32_t itstatus = 0x0, itenable = 0x0;
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimGetInt(TIM_IT));
+
+ itstatus = TIMx->STS & TIM_IT;
+
+ itenable = TIMx->DINTEN & TIM_IT;
+ if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the TIMx's interrupt pending bits.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_IT specifies the pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_INT_UPDATE TIM1 update Interrupt source
+ * @arg TIM_INT_CC1 TIM Capture Compare 1 Interrupt source
+ * @arg TIM_INT_CC2 TIM Capture Compare 2 Interrupt source
+ * @arg TIM_INT_CC3 TIM Capture Compare 3 Interrupt source
+ * @arg TIM_INT_CC4 TIM Capture Compare 4 Interrupt source
+ * @arg TIM_INT_COM TIM Commutation Interrupt source
+ * @arg TIM_INT_TRIG TIM Trigger Interrupt source
+ * @arg TIM_INT_BREAK TIM Break Interrupt source
+ * @note
+ * - TIM6 and TIM7 can generate only an update interrupt.
+ * - TIM_INT_BREAK is used only with TIM1, TIM8.
+ * - TIM_INT_COM is used only with TIM1, TIM8.
+ */
+void TIM_ClrIntPendingBit(TIM_Module* TIMx, uint32_t TIM_IT)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimInt(TIM_IT));
+ /* Clear the IT pending Bit */
+ TIMx->STS = (uint32_t)~TIM_IT;
+}
+
+/**
+ * @brief Configure the TI1 as Input.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param IcPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_POLARITY_RISING
+ * @arg TIM_IC_POLARITY_FALLING
+ * @param IcSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 1 is selected to be connected to IC1.
+ * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 1 is selected to be connected to IC2.
+ * @arg TIM_IC_SELECTION_TRC TIM Input 1 is selected to be connected to TRC.
+ * @param IcFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ */
+static void ConfigTI1(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter)
+{
+ uint16_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0;
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC1EN);
+ tmpccmr1 = TIMx->CCMOD1;
+ tmpccer = TIMx->CCEN;
+ /* Select the Input and set the filter */
+ tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD1_CC1SEL)) & ((uint16_t) ~((uint16_t)TIM_CCMOD1_IC1F)));
+ tmpccmr1 |= (uint16_t)(IcSelection | (uint16_t)(IcFilter << (uint16_t)4));
+
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9))
+ {
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC1P));
+ tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC1EN);
+ }
+ else
+ {
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC1P | TIM_CCEN_CC1NP));
+ tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC1EN);
+ }
+
+ /* Write to TIMx CCMOD1 and CCEN registers */
+ TIMx->CCMOD1 = tmpccmr1;
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configure the TI2 as Input.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param IcPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_POLARITY_RISING
+ * @arg TIM_IC_POLARITY_FALLING
+ * @param IcSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 2 is selected to be connected to IC2.
+ * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 2 is selected to be connected to IC1.
+ * @arg TIM_IC_SELECTION_TRC TIM Input 2 is selected to be connected to TRC.
+ * @param IcFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ */
+static void ConfigTI2(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter)
+{
+ uint16_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0, tmp = 0;
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC2EN);
+ tmpccmr1 = TIMx->CCMOD1;
+ tmpccer = TIMx->CCEN;
+ tmp = (uint32_t)(IcPolarity << 4);
+ /* Select the Input and set the filter */
+ tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD1_CC2SEL)) & ((uint16_t) ~((uint16_t)TIM_CCMOD1_IC2F)));
+ tmpccmr1 |= (uint16_t)(IcFilter << 12);
+ tmpccmr1 |= (uint16_t)(IcSelection << 8);
+
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9))
+ {
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC2P));
+ tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCEN_CC2EN);
+ }
+ else
+ {
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC2P | TIM_CCEN_CC2NP));
+ tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC2EN);
+ }
+
+ /* Write to TIMx CCMOD1 and CCEN registers */
+ TIMx->CCMOD1 = tmpccmr1;
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configure the TI3 as Input.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param IcPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_POLARITY_RISING
+ * @arg TIM_IC_POLARITY_FALLING
+ * @param IcSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 3 is selected to be connected to IC3.
+ * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 3 is selected to be connected to IC4.
+ * @arg TIM_IC_SELECTION_TRC TIM Input 3 is selected to be connected to TRC.
+ * @param IcFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ */
+static void ConfigTI3(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter)
+{
+ uint16_t tmpccmr2 = 0;
+ uint32_t tmpccer = 0, tmp = 0;
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC3EN);
+ tmpccmr2 = TIMx->CCMOD2;
+ tmpccer = TIMx->CCEN;
+ tmp = (uint32_t)(IcPolarity << 8);
+ /* Select the Input and set the filter */
+ tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD2_CC3SEL)) & ((uint16_t) ~((uint16_t)TIM_CCMOD2_IC3F)));
+ tmpccmr2 |= (uint16_t)(IcSelection | (uint16_t)(IcFilter << (uint16_t)4));
+
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9))
+ {
+ /* Select the Polarity and set the CC3E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC3P));
+ tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCEN_CC3EN);
+ }
+ else
+ {
+ /* Select the Polarity and set the CC3E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC3P | TIM_CCEN_CC3NP));
+ tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC3EN);
+ }
+
+ /* Write to TIMx CCMOD2 and CCEN registers */
+ TIMx->CCMOD2 = tmpccmr2;
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configure the TI4 as Input.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param IcPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_POLARITY_RISING
+ * @arg TIM_IC_POLARITY_FALLING
+ * @param IcSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 4 is selected to be connected to IC4.
+ * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 4 is selected to be connected to IC3.
+ * @arg TIM_IC_SELECTION_TRC TIM Input 4 is selected to be connected to TRC.
+ * @param IcFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ */
+static void ConfigTI4(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter)
+{
+ uint16_t tmpccmr2 = 0;
+ uint32_t tmpccer = 0, tmp = 0;
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC4EN);
+ tmpccmr2 = TIMx->CCMOD2;
+ tmpccer = TIMx->CCEN;
+ tmp = (uint32_t)(IcPolarity << 12);
+ /* Select the Input and set the filter */
+ tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMOD2_CC4SEL) & ((uint16_t) ~((uint16_t)TIM_CCMOD2_IC4F)));
+ tmpccmr2 |= (uint16_t)(IcSelection << 8);
+ tmpccmr2 |= (uint16_t)(IcFilter << 12);
+
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9))
+ {
+ /* Select the Polarity and set the CC4E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC4P));
+ tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCEN_CC4EN);
+ }
+ else
+ {
+ /* Select the Polarity and set the CC4E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC4P));
+ tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC4EN);
+ }
+ /* Write to TIMx CCMOD2 and CCEN registers */
+ TIMx->CCMOD2 = tmpccmr2;
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_tsc.c b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_tsc.c
new file mode 100644
index 0000000000..b07cd2038d
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_tsc.c
@@ -0,0 +1,279 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_tsc.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l40x.h"
+#include "n32l40x_tsc.h"
+
+/**
+* @brief Init TSC config
+* @param InitParam: TSC initialize structure
+* @return : TSC_ErrorTypeDef
+*/
+TSC_ErrorTypeDef TSC_Init(TSC_InitType* InitParam)
+{
+ uint32_t tempreg,timeout;
+
+ assert_param(IS_TSC_DET_MODE(InitParam->Mode));
+ assert_param(IS_TSC_PAD_OPTION(InitParam->PadOpt));
+ assert_param(IS_TSC_PAD_SPEED(InitParam->Speed));
+
+ /* waiting tsc hw for idle status.*/
+ timeout = 0;
+ do
+ {
+ __TSC_HW_DISABLE();
+
+ if (++timeout > TSC_TIMEOUT)
+ return TSC_ERROR_HW_MODE;
+ }while (__TSC_GET_HW_MODE());
+
+ /*TSC_CTRL config*/
+ tempreg = 0;
+ if (InitParam->Mode == TSC_HW_DETECT_MODE)
+ {
+ assert_param(IS_TSC_DET_PERIOD(InitParam->Period));
+ assert_param(IS_TSC_FILTER(InitParam->Filter));
+ assert_param(IS_TSC_DET_TYPE(InitParam->Type));
+ assert_param(IS_TSC_INT(InitParam->Int));
+
+ tempreg |= InitParam->Period;
+ tempreg |= InitParam->Filter;
+ tempreg |= InitParam->Type;
+ tempreg |= InitParam->Int;
+ }
+ else
+ {
+ assert_param(IS_TSC_OUT(InitParam->Out));
+ tempreg |= InitParam->Out;
+ }
+
+ TSC->CTRL = tempreg;
+
+ /*TSC_ANA_SEL config*/
+ TSC->ANA_SEL = InitParam->PadOpt | InitParam->Speed;
+
+ return TSC_ERROR_OK;
+}
+
+/**
+ * @brief Config the clock source of TSC
+ * @param TSC_ClkSource specifies the clock source of TSC
+ * This parameter can be one of the following values:
+ * @arg TSC_CLK_SRC_LSI: TSC clock source is LSI(default)
+ * @arg TSC_CLK_SRC_LSE: TSC clock source is LSE,and LSE is oscillator
+ * @arg TSC_CLK_SRC_LSE_BYPASS: TSC clock source is LSE,and LSE is extennal clock
+ * @retval TSC error code
+ */
+TSC_ErrorTypeDef TSC_ClockConfig(uint32_t TSC_ClkSource)
+{
+ uint32_t timeout;
+
+ /*Enable PWR peripheral Clock*/
+ RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR,ENABLE);
+
+ if (TSC_CLK_SRC_LSI == TSC_ClkSource)
+ {
+ /*enable LSI clock*/
+ RCC_EnableLsi(ENABLE);
+
+ /*Wait LSI stable*/
+ timeout = 0;
+ while (RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_LSIRD) == RESET)
+ {
+ if (++timeout >TSC_TIMEOUT)
+ return TSC_ERROR_CLOCK;
+ }
+ }
+ else if ((TSC_CLK_SRC_LSE_BYPASS==TSC_ClkSource)||(TSC_CLK_SRC_LSE==TSC_ClkSource))
+ {
+ if (RCC_GetFlagStatus(RCC_LDCTRL_FLAG_LSERD)==RESET)
+ {
+ RCC_ConfigLse((TSC_ClkSource & (~RCC_LDCTRL_LSXSEL)),0x28);
+ timeout = 0;
+ while (RCC_GetFlagStatus(RCC_LDCTRL_FLAG_LSERD) == RESET)
+ {
+ if (++timeout >TSC_TIMEOUT)
+ return TSC_ERROR_CLOCK;
+ }
+ }
+ }
+ else
+ return TSC_ERROR_PARAMETER;
+
+ // Set bit 8 of PWR_CTRL1.Open PWR DBP.
+ PWR_BackupAccessEnable(ENABLE); //PWR->CTRL1 |= 0x100;
+
+ /*set LSI as TSC clock source*/
+ RCC_ConfigLSXClk(TSC_ClkSource & RCC_LDCTRL_LSXSEL);
+
+ /*Enable TSC clk*/
+ RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TSC,ENABLE);
+
+ return TSC_ERROR_OK;
+}
+
+/**
+* @brief Configure internal charge resistor for some channels
+* @param res: internal resistor selecte
+* This parameter can be one of the following values:
+* @arg TSC_RESR_CHN_RESIST_0: 1M OHM
+* @arg TSC_RESR_CHN_RESIST_1: 882K OHM
+* @arg TSC_RESR_CHN_RESIST_2: 756K OHM
+* @arg TSC_RESR_CHN_RESIST_3: 630K OHM
+* @arg TSC_RESR_CHN_RESIST_4: 504K OHM
+* @arg TSC_RESR_CHN_RESIST_5: 378K OHM
+* @arg TSC_RESR_CHN_RESIST_6: 252K OHM
+* @arg TSC_RESR_CHN_RESIST_7: 126K OHM
+* @param Channels: channels to be configed, as TSC_CHNEN defined
+* This parameter:bit[0:23] used,bit[24:31] must be 0
+* bitx: TSC channel x
+* @return: none
+*/
+TSC_ErrorTypeDef TSC_ConfigInternalResistor(uint32_t Channels, uint32_t res )
+{
+ uint32_t i,chn,timeout,nReg,nPos;
+
+ assert_param(IS_TSC_CHN(Channels));
+ assert_param(IS_TSC_RESISTOR_VALUE(res));
+
+ /*Check charge resistor value */
+ if (res > TSC_RESRx_CHN_RESIST_7)
+ return TSC_ERROR_PARAMETER;
+
+ /* waiting tsc hw for idle status.*/
+ timeout = 0;
+ do
+ {
+ __TSC_HW_DISABLE();
+
+ if (++timeout > TSC_TIMEOUT)
+ return TSC_ERROR_HW_MODE;
+ }while (__TSC_GET_HW_MODE());
+
+ /* Mask invalie bits*/
+ chn = Channels & TSC_CHNEN_CHN_SELx_Msk;
+
+ /* Set resistance for each channel one by one*/
+ for (i = 0; i> 3;
+ nPos = (i & 0x7UL)*4;
+ MODIFY_REG(TSC->RESR[nReg],TSC_RESRx_CHN_RESIST_Msk<>= 1;
+ }
+
+ return TSC_ERROR_OK;
+}
+
+/**
+* @brief Configure threshold value for some channels
+* @param Channels: channels to be configed, as TSC_CHNEN defined
+* This parameter:bit[0:23] used,bit[24:31] must be 0
+* bitx: TSC channel x
+* @param base: base value of threshold, 0-MAX_TSC_THRESHOLD_BASE
+* @param delta: delta value of threshold,0-MAX_TSC_THRESHOLD_DELRA
+* @return: None
+*/
+TSC_ErrorTypeDef TSC_ConfigThreshold( uint32_t Channels, uint32_t base, uint32_t delta)
+{
+ uint32_t i, chn,timeout;
+ assert_param(IS_TSC_CHN(Channels));
+ assert_param(IS_TSC_THRESHOLD_BASE(base));
+ assert_param(IS_TSC_THRESHOLD_DELTA(delta));
+
+ /*Check the base and delta value*/
+ if ( (base>MAX_TSC_THRESHOLD_BASE)||(delta>MAX_TSC_THRESHOLD_DELTA))
+ return TSC_ERROR_PARAMETER;
+
+ /* waiting tsc hw for idle status.*/
+ timeout = 0;
+ do
+ {
+ __TSC_HW_DISABLE();
+
+ if (++timeout > TSC_TIMEOUT)
+ return TSC_ERROR_HW_MODE;
+ }while (__TSC_GET_HW_MODE());
+
+ /*Mask invalie bits*/
+ chn = Channels & TSC_CHNEN_CHN_SELx_Msk;
+
+ /* Set the base and delta for each channnel one by one*/
+ for (i = 0; iTHRHD[i] = (base<>= 1;
+ }
+
+ return TSC_ERROR_OK;
+}
+
+
+/**
+* @brief Get parameters of one channel.
+* @param ChnCfg: Pointer of TSC_ChnCfg structure.
+* @param ChannelNum: The channel number of which we want to get parameters,must be less then MAX_TSC_HW_CHN
+* @return: None
+*/
+TSC_ErrorTypeDef TSC_GetChannelCfg( TSC_ChnCfg* ChnCfg, uint32_t ChannelNum)
+{
+ uint32_t nReg,nPos;
+
+ assert_param(IS_TSC_CHN_NUMBER(ChannelNum));
+
+ /*Check channel number*/
+ if (!(IS_TSC_CHN_NUMBER(ChannelNum)))
+ return TSC_ERROR_PARAMETER;
+
+ /* Get the base and delta value for a channel*/
+ ChnCfg->TSC_Base = (TSC->THRHD[ChannelNum] & TSC_THRHDx_BASE_Msk) >> TSC_THRHDx_BASE_Pos;
+ ChnCfg->TSC_Delta = (TSC->THRHD[ChannelNum] & TSC_THRHDx_DELTA_Msk)>> TSC_THRHDx_DELTA_Pos;
+
+ /* Get the charge resistor type for a channel*/
+ nReg = ChannelNum>>3;
+ nPos = (ChannelNum & 0x7UL)*4;
+ ChnCfg->TSC_Resistor = (TSC->RESR[nReg] >> nPos) & TSC_RESRx_CHN_RESIST_Msk;
+
+ return TSC_ERROR_OK;
+}
+
+
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_usart.c b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_usart.c
new file mode 100644
index 0000000000..00b64f91da
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_usart.c
@@ -0,0 +1,956 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_usart.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l40x_usart.h"
+#include "n32l40x_rcc.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup USART
+ * @brief USART driver modules
+ * @{
+ */
+
+/** @addtogroup USART_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Private_Defines
+ * @{
+ */
+
+#define CTRL1_UEN_SET ((uint16_t)0x2000) /*!< USART Enable Mask */
+#define CTRL1_UEN_RESET ((uint16_t)0xDFFF) /*!< USART Disable Mask */
+
+#define CTRL1_WUM_MASK ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */
+
+#define CTRL1_RCVWU_SET ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */
+#define CTRL1_RCVWU_RESET ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */
+#define CTRL1_SDBRK_SET ((uint16_t)0x0001) /*!< USART Break Character send Mask */
+#define CTRL1_CLR_MASK ((uint16_t)0xE9F3) /*!< USART CTRL1 Mask */
+#define CTRL2_ADDR_MASK ((uint16_t)0xFFF0) /*!< USART address Mask */
+
+#define CTRL2_LINMEN_SET ((uint16_t)0x4000) /*!< USART LIN Enable Mask */
+#define CTRL2_LINMEN_RESET ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */
+
+#define CTRL2_LINBDL_MASK ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */
+#define CTRL2_STPB_CLR_MASK ((uint16_t)0xCFFF) /*!< USART CTRL2 STOP Bits Mask */
+#define CTRL2_CLOCK_CLR_MASK ((uint16_t)0xF0FF) /*!< USART CTRL2 Clock Mask */
+
+#define CTRL3_SCMEN_SET ((uint16_t)0x0020) /*!< USART SC Enable Mask */
+#define CTRL3_SCMEN_RESET ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */
+
+#define CTRL3_SCNACK_SET ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */
+#define CTRL3_SCNACK_RESET ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */
+
+#define CTRL3_HDMEN_SET ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */
+#define CTRL3_HDMEN_RESET ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */
+
+#define CTRL3_IRDALP_MASK ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */
+#define CTRL3_CLR_MASK ((uint16_t)0xFCFF) /*!< USART CTRL3 Mask */
+
+#define CTRL3_IRDAMEN_SET ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */
+#define CTRL3_IRDAMEN_RESET ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */
+#define GTP_LSB_MASK ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */
+#define GTP_MSB_MASK ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */
+#define INT_MASK ((uint16_t)0x001F) /*!< USART Interrupt Mask */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the USARTx peripheral registers to their default reset values.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ */
+void USART_DeInit(USART_Module* USARTx)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ if (USARTx == USART1)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_USART1, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_USART1, DISABLE);
+ }
+ else if (USARTx == USART2)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART2, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART2, DISABLE);
+ }
+ else if (USARTx == USART3)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART3, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART3, DISABLE);
+ }
+ else if (USARTx == UART4)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART4, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART4, DISABLE);
+ }
+ else if (USARTx == UART5)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART5, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART5, DISABLE);
+ }
+}
+
+/**
+ * @brief Initializes the USARTx peripheral according to the specified
+ * parameters in the USART_InitStruct .
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_InitStruct pointer to a USART_InitType structure
+ * that contains the configuration information for the specified USART
+ * peripheral.
+ */
+void USART_Init(USART_Module* USARTx, USART_InitType* USART_InitStruct)
+{
+ uint32_t tmpregister = 0x00, apbclock = 0x00;
+ uint32_t integerdivider = 0x00;
+ uint32_t fractionaldivider = 0x00;
+ uint32_t usartxbase = 0;
+ RCC_ClocksType RCC_ClocksStatus;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_BAUDRATE(USART_InitStruct->BaudRate));
+ assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->WordLength));
+ assert_param(IS_USART_STOPBITS(USART_InitStruct->StopBits));
+ assert_param(IS_USART_PARITY(USART_InitStruct->Parity));
+ assert_param(IS_USART_MODE(USART_InitStruct->Mode));
+ assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->HardwareFlowControl));
+ /* The hardware flow control is available only for USART1, USART2 and USART3 */
+ if (USART_InitStruct->HardwareFlowControl != USART_HFCTRL_NONE)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ usartxbase = (uint32_t)USARTx;
+
+ /*---------------------------- USART CTRL2 Configuration -----------------------*/
+ tmpregister = USARTx->CTRL2;
+ /* Clear STOP[13:12] bits */
+ tmpregister &= CTRL2_STPB_CLR_MASK;
+ /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
+ /* Set STOP[13:12] bits according to StopBits value */
+ tmpregister |= (uint32_t)USART_InitStruct->StopBits;
+
+ /* Write to USART CTRL2 */
+ USARTx->CTRL2 = (uint16_t)tmpregister;
+
+ /*---------------------------- USART CTRL1 Configuration -----------------------*/
+ tmpregister = USARTx->CTRL1;
+ /* Clear M, PCE, PS, TE and RE bits */
+ tmpregister &= CTRL1_CLR_MASK;
+ /* Configure the USART Word Length, Parity and mode ----------------------- */
+ /* Set the M bits according to WordLength value */
+ /* Set PCE and PS bits according to Parity value */
+ /* Set TE and RE bits according to Mode value */
+ tmpregister |= (uint32_t)USART_InitStruct->WordLength | USART_InitStruct->Parity | USART_InitStruct->Mode;
+ /* Write to USART CTRL1 */
+ USARTx->CTRL1 = (uint16_t)tmpregister;
+
+ /*---------------------------- USART CTRL3 Configuration -----------------------*/
+ tmpregister = USARTx->CTRL3;
+ /* Clear CTSE and RTSE bits */
+ tmpregister &= CTRL3_CLR_MASK;
+ /* Configure the USART HFC -------------------------------------------------*/
+ /* Set CTSE and RTSE bits according to HardwareFlowControl value */
+ tmpregister |= USART_InitStruct->HardwareFlowControl;
+ /* Write to USART CTRL3 */
+ USARTx->CTRL3 = (uint16_t)tmpregister;
+
+ /*---------------------------- USART PBC Configuration -----------------------*/
+ /* Configure the USART Baud Rate -------------------------------------------*/
+ RCC_GetClocksFreqValue(&RCC_ClocksStatus);
+ if ((usartxbase == USART1_BASE) || (usartxbase == UART4_BASE) || (usartxbase == UART5_BASE))
+ {
+ apbclock = RCC_ClocksStatus.Pclk2Freq;
+ }
+ else
+ {
+ apbclock = RCC_ClocksStatus.Pclk1Freq;
+ }
+
+ /* Determine the integer part */
+ integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->BaudRate)));
+ tmpregister = (integerdivider / 100) << 4;
+
+ /* Determine the fractional part */
+ fractionaldivider = integerdivider - (100 * (tmpregister >> 4));
+
+ /* Implement the fractional part in the register */
+ tmpregister |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
+
+ /* Write to USART PBC */
+ USARTx->BRCF = (uint16_t)tmpregister;
+}
+
+/**
+ * @brief Fills each USART_InitStruct member with its default value.
+ * @param USART_InitStruct pointer to a USART_InitType structure
+ * which will be initialized.
+ */
+void USART_StructInit(USART_InitType* USART_InitStruct)
+{
+ /* USART_InitStruct members default value */
+ USART_InitStruct->BaudRate = 9600;
+ USART_InitStruct->WordLength = USART_WL_8B;
+ USART_InitStruct->StopBits = USART_STPB_1;
+ USART_InitStruct->Parity = USART_PE_NO;
+ USART_InitStruct->Mode = USART_MODE_RX | USART_MODE_TX;
+ USART_InitStruct->HardwareFlowControl = USART_HFCTRL_NONE;
+}
+
+/**
+ * @brief Initializes the USARTx peripheral Clock according to the
+ * specified parameters in the USART_ClockInitStruct .
+ * @param USARTx where x can be 1, 2, 3 to select the USART peripheral.
+ * @param USART_ClockInitStruct pointer to a USART_ClockInitType
+ * structure that contains the configuration information for the specified
+ * USART peripheral.
+ * @note The Smart Card and Synchronous modes are not available for UART4/UART5.
+ */
+void USART_ClockInit(USART_Module* USARTx, USART_ClockInitType* USART_ClockInitStruct)
+{
+ uint32_t tmpregister = 0x00;
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ assert_param(IS_USART_CLOCK(USART_ClockInitStruct->Clock));
+ assert_param(IS_USART_CPOL(USART_ClockInitStruct->Polarity));
+ assert_param(IS_USART_CPHA(USART_ClockInitStruct->Phase));
+ assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->LastBit));
+
+ /*---------------------------- USART CTRL2 Configuration -----------------------*/
+ tmpregister = USARTx->CTRL2;
+ /* Clear CLKEN, CPOL, CPHA and LBCL bits */
+ tmpregister &= CTRL2_CLOCK_CLR_MASK;
+ /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/
+ /* Set CLKEN bit according to Clock value */
+ /* Set CPOL bit according to Polarity value */
+ /* Set CPHA bit according to Phase value */
+ /* Set LBCL bit according to LastBit value */
+ tmpregister |= (uint32_t)USART_ClockInitStruct->Clock | USART_ClockInitStruct->Polarity
+ | USART_ClockInitStruct->Phase | USART_ClockInitStruct->LastBit;
+ /* Write to USART CTRL2 */
+ USARTx->CTRL2 = (uint16_t)tmpregister;
+}
+
+/**
+ * @brief Fills each USART_ClockInitStruct member with its default value.
+ * @param USART_ClockInitStruct pointer to a USART_ClockInitType
+ * structure which will be initialized.
+ */
+void USART_ClockStructInit(USART_ClockInitType* USART_ClockInitStruct)
+{
+ /* USART_ClockInitStruct members default value */
+ USART_ClockInitStruct->Clock = USART_CLK_DISABLE;
+ USART_ClockInitStruct->Polarity = USART_CLKPOL_LOW;
+ USART_ClockInitStruct->Phase = USART_CLKPHA_1EDGE;
+ USART_ClockInitStruct->LastBit = USART_CLKLB_DISABLE;
+}
+
+/**
+ * @brief Enables or disables the specified USART peripheral.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param Cmd new state of the USARTx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void USART_Enable(USART_Module* USARTx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected USART by setting the UE bit in the CTRL1 register */
+ USARTx->CTRL1 |= CTRL1_UEN_SET;
+ }
+ else
+ {
+ /* Disable the selected USART by clearing the UE bit in the CTRL1 register */
+ USARTx->CTRL1 &= CTRL1_UEN_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified USART interrupts.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_INT specifies the USART interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg USART_INT_CTSF CTS change interrupt (not available for UART4 and UART5)
+ * @arg USART_INT_LINBD LIN Break detection interrupt
+ * @arg USART_INT_TXDE Transmit Data Register empty interrupt
+ * @arg USART_INT_TXC Transmission complete interrupt
+ * @arg USART_INT_RXDNE Receive Data register not empty interrupt
+ * @arg USART_INT_IDLEF Idle line detection interrupt
+ * @arg USART_INT_PEF Parity Error interrupt
+ * @arg USART_INT_ERRF Error interrupt(Frame error, noise error, overrun error)
+ * @param Cmd new state of the specified USARTx interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void USART_ConfigInt(USART_Module* USARTx, uint16_t USART_INT, FunctionalState Cmd)
+{
+ uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
+ uint32_t usartxbase = 0x00;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_CFG_INT(USART_INT));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ /* The CTS interrupt is not available for UART4/UART5 */
+ if (USART_INT == USART_INT_CTSF)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ usartxbase = (uint32_t)USARTx;
+
+ /* Get the USART register index */
+ usartreg = (((uint8_t)USART_INT) >> 0x05);
+
+ /* Get the interrupt position */
+ itpos = USART_INT & INT_MASK;
+ itmask = (((uint32_t)0x01) << itpos);
+
+ if (usartreg == 0x01) /* The IT is in CTRL1 register */
+ {
+ usartxbase += 0x0C;
+ }
+ else if (usartreg == 0x02) /* The IT is in CTRL2 register */
+ {
+ usartxbase += 0x10;
+ }
+ else /* The IT is in CTRL3 register */
+ {
+ usartxbase += 0x14;
+ }
+ if (Cmd != DISABLE)
+ {
+ *(__IO uint32_t*)usartxbase |= itmask;
+ }
+ else
+ {
+ *(__IO uint32_t*)usartxbase &= ~itmask;
+ }
+}
+
+/**
+ * @brief Enables or disables the USART's DMA interface.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_DMAReq specifies the DMA request.
+ * This parameter can be any combination of the following values:
+ * @arg USART_DMAREQ_TX USART DMA transmit request
+ * @arg USART_DMAREQ_RX USART DMA receive request
+ * @param Cmd new state of the DMA Request sources.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void USART_EnableDMA(USART_Module* USARTx, uint16_t USART_DMAReq, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_DMAREQ(USART_DMAReq));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the DMA transfer for selected requests by setting the DMAT and/or
+ DADDR bits in the USART CTRL3 register */
+ USARTx->CTRL3 |= USART_DMAReq;
+ }
+ else
+ {
+ /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
+ DADDR bits in the USART CTRL3 register */
+ USARTx->CTRL3 &= (uint16_t)~USART_DMAReq;
+ }
+}
+
+/**
+ * @brief Sets the address of the USART node.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_Addr Indicates the address of the USART node.
+ */
+void USART_SetAddr(USART_Module* USARTx, uint8_t USART_Addr)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_ADDRESS(USART_Addr));
+
+ /* Clear the USART address */
+ USARTx->CTRL2 &= CTRL2_ADDR_MASK;
+ /* Set the USART address node */
+ USARTx->CTRL2 |= USART_Addr;
+}
+
+/**
+ * @brief Selects the USART WakeUp method.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_WakeUpMode specifies the USART wakeup method.
+ * This parameter can be one of the following values:
+ * @arg USART_WUM_IDLELINE WakeUp by an idle line detection
+ * @arg USART_WUM_ADDRMASK WakeUp by an address mark
+ */
+void USART_ConfigWakeUpMode(USART_Module* USARTx, uint16_t USART_WakeUpMode)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_WAKEUP(USART_WakeUpMode));
+
+ USARTx->CTRL1 &= CTRL1_WUM_MASK;
+ USARTx->CTRL1 |= USART_WakeUpMode;
+}
+
+/**
+ * @brief Determines if the USART is in mute mode or not.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param Cmd new state of the USART mute mode.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void USART_EnableRcvWakeUp(USART_Module* USARTx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the USART mute mode by setting the RWU bit in the CTRL1 register */
+ USARTx->CTRL1 |= CTRL1_RCVWU_SET;
+ }
+ else
+ {
+ /* Disable the USART mute mode by clearing the RWU bit in the CTRL1 register */
+ USARTx->CTRL1 &= CTRL1_RCVWU_RESET;
+ }
+}
+
+/**
+ * @brief Sets the USART LIN Break detection length.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_LINBreakDetectLength specifies the LIN break detection length.
+ * This parameter can be one of the following values:
+ * @arg USART_LINBDL_10B 10-bit break detection
+ * @arg USART_LINBDL_11B 11-bit break detection
+ */
+void USART_ConfigLINBreakDetectLength(USART_Module* USARTx, uint16_t USART_LINBreakDetectLength)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
+
+ USARTx->CTRL2 &= CTRL2_LINBDL_MASK;
+ USARTx->CTRL2 |= USART_LINBreakDetectLength;
+}
+
+/**
+ * @brief Enables or disables the USART's LIN mode.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param Cmd new state of the USART LIN mode.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void USART_EnableLIN(USART_Module* USARTx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the LIN mode by setting the LINEN bit in the CTRL2 register */
+ USARTx->CTRL2 |= CTRL2_LINMEN_SET;
+ }
+ else
+ {
+ /* Disable the LIN mode by clearing the LINEN bit in the CTRL2 register */
+ USARTx->CTRL2 &= CTRL2_LINMEN_RESET;
+ }
+}
+
+/**
+ * @brief Transmits single data through the USARTx peripheral.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param Data the data to transmit.
+ */
+void USART_SendData(USART_Module* USARTx, uint16_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_DATA(Data));
+
+ /* Transmit Data */
+ USARTx->DAT = (Data & (uint16_t)0x01FF);
+}
+
+/**
+ * @brief Returns the most recent received data by the USARTx peripheral.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @return The received data.
+ */
+uint16_t USART_ReceiveData(USART_Module* USARTx)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ /* Receive Data */
+ return (uint16_t)(USARTx->DAT & (uint16_t)0x01FF);
+}
+
+/**
+ * @brief Transmits break characters.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ */
+void USART_SendBreak(USART_Module* USARTx)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ /* Send break characters */
+ USARTx->CTRL1 |= CTRL1_SDBRK_SET;
+}
+
+/**
+ * @brief Sets the specified USART guard time.
+ * @param USARTx where x can be 1, 2 or 3 to select the USART peripheral.
+ * @param USART_GuardTime specifies the guard time.
+ * @note The guard time bits are not available for UART4/UART5.
+ */
+void USART_SetGuardTime(USART_Module* USARTx, uint8_t USART_GuardTime)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+
+ /* Clear the USART Guard time */
+ USARTx->GTP &= GTP_LSB_MASK;
+ /* Set the USART guard time */
+ USARTx->GTP |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
+}
+
+/**
+ * @brief Sets the system clock prescaler.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_Prescaler specifies the prescaler clock.
+ * @note The function is used for IrDA mode with UART4 and UART5.
+ */
+void USART_SetPrescaler(USART_Module* USARTx, uint8_t USART_Prescaler)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ /* Clear the USART prescaler */
+ USARTx->GTP &= GTP_MSB_MASK;
+ /* Set the USART prescaler */
+ USARTx->GTP |= USART_Prescaler;
+}
+
+/**
+ * @brief Enables or disables the USART's Smart Card mode.
+ * @param USARTx where x can be 1, 2 or 3 to select the USART peripheral.
+ * @param Cmd new state of the Smart Card mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note The Smart Card mode is not available for UART4/UART5.
+ */
+void USART_EnableSmartCard(USART_Module* USARTx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the SC mode by setting the SCEN bit in the CTRL3 register */
+ USARTx->CTRL3 |= CTRL3_SCMEN_SET;
+ }
+ else
+ {
+ /* Disable the SC mode by clearing the SCEN bit in the CTRL3 register */
+ USARTx->CTRL3 &= CTRL3_SCMEN_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables NACK transmission.
+ * @param USARTx where x can be 1, 2 or 3 to select the USART peripheral.
+ * @param Cmd new state of the NACK transmission.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note The Smart Card mode is not available for UART4/UART5.
+ */
+void USART_SetSmartCardNACK(USART_Module* USARTx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the NACK transmission by setting the NACK bit in the CTRL3 register */
+ USARTx->CTRL3 |= CTRL3_SCNACK_SET;
+ }
+ else
+ {
+ /* Disable the NACK transmission by clearing the NACK bit in the CTRL3 register */
+ USARTx->CTRL3 &= CTRL3_SCNACK_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the USART's Half Duplex communication.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param Cmd new state of the USART Communication.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void USART_EnableHalfDuplex(USART_Module* USARTx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CTRL3 register */
+ USARTx->CTRL3 |= CTRL3_HDMEN_SET;
+ }
+ else
+ {
+ /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CTRL3 register */
+ USARTx->CTRL3 &= CTRL3_HDMEN_RESET;
+ }
+}
+
+/**
+ * @brief Configures the USART's IrDA interface.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_IrDAMode specifies the IrDA mode.
+ * This parameter can be one of the following values:
+ * @arg USART_IRDAMODE_LOWPPWER
+ * @arg USART_IRDAMODE_NORMAL
+ */
+void USART_ConfigIrDAMode(USART_Module* USARTx, uint16_t USART_IrDAMode)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
+
+ USARTx->CTRL3 &= CTRL3_IRDALP_MASK;
+ USARTx->CTRL3 |= USART_IrDAMode;
+}
+
+/**
+ * @brief Enables or disables the USART's IrDA interface.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param Cmd new state of the IrDA mode.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void USART_EnableIrDA(USART_Module* USARTx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the IrDA mode by setting the IREN bit in the CTRL3 register */
+ USARTx->CTRL3 |= CTRL3_IRDAMEN_SET;
+ }
+ else
+ {
+ /* Disable the IrDA mode by clearing the IREN bit in the CTRL3 register */
+ USARTx->CTRL3 &= CTRL3_IRDAMEN_RESET;
+ }
+}
+
+/**
+ * @brief Checks whether the specified USART flag is set or not.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_FLAG specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg USART_FLAG_CTSF CTS Change flag (not available for UART4 and UART5)
+ * @arg USART_FLAG_LINBD LIN Break detection flag
+ * @arg USART_FLAG_TXDE Transmit data register empty flag
+ * @arg USART_FLAG_TXC Transmission Complete flag
+ * @arg USART_FLAG_RXDNE Receive data register not empty flag
+ * @arg USART_FLAG_IDLEF Idle Line detection flag
+ * @arg USART_FLAG_OREF OverRun Error flag
+ * @arg USART_FLAG_NEF Noise Error flag
+ * @arg USART_FLAG_FEF Framing Error flag
+ * @arg USART_FLAG_PEF Parity Error flag
+ * @return The new state of USART_FLAG (SET or RESET).
+ */
+FlagStatus USART_GetFlagStatus(USART_Module* USARTx, uint16_t USART_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_FLAG(USART_FLAG));
+ /* The CTS flag is not available for UART4/UART5 */
+ if (USART_FLAG == USART_FLAG_CTSF)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ if ((USARTx->STS & USART_FLAG) != (uint16_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the USARTx's pending flags.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_FLAG specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg USART_FLAG_CTSF CTS Change flag (not available for UART4 and UART5).
+ * @arg USART_FLAG_LINBD LIN Break detection flag.
+ * @arg USART_FLAG_TXC Transmission Complete flag.
+ * @arg USART_FLAG_RXDNE Receive data register not empty flag.
+ *
+ * @note
+ * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ * error) and IDLE (Idle line detected) flags are cleared by software
+ * sequence: a read operation to USART_SR register (USART_GetFlagStatus())
+ * followed by a read operation to USART_DR register (USART_ReceiveData()).
+ * - RXNE flag can be also cleared by a read to the USART_DR register
+ * (USART_ReceiveData()).
+ * - TC flag can be also cleared by software sequence: a read operation to
+ * USART_SR register (USART_GetFlagStatus()) followed by a write operation
+ * to USART_DR register (USART_SendData()).
+ * - TXE flag is cleared only by a write to the USART_DR register
+ * (USART_SendData()).
+ */
+void USART_ClrFlag(USART_Module* USARTx, uint16_t USART_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
+ /* The CTS flag is not available for UART4/UART5 */
+ if ((USART_FLAG & USART_FLAG_CTSF) == USART_FLAG_CTSF)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ USARTx->STS = (uint16_t)~USART_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified USART interrupt has occurred or not.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_INT specifies the USART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg USART_INT_CTSF CTS change interrupt (not available for UART4 and UART5)
+ * @arg USART_INT_LINBD LIN Break detection interrupt
+ * @arg USART_INT_TXDE Tansmit Data Register empty interrupt
+ * @arg USART_INT_TXC Transmission complete interrupt
+ * @arg USART_INT_RXDNE Receive Data register not empty interrupt
+ * @arg USART_INT_IDLEF Idle line detection interrupt
+ * @arg USART_INT_OREF OverRun Error interrupt
+ * @arg USART_INT_NEF Noise Error interrupt
+ * @arg USART_INT_FEF Framing Error interrupt
+ * @arg USART_INT_PEF Parity Error interrupt
+ * @return The new state of USART_INT (SET or RESET).
+ */
+INTStatus USART_GetIntStatus(USART_Module* USARTx, uint16_t USART_INT)
+{
+ uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
+ INTStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_GET_INT(USART_INT));
+ /* The CTS interrupt is not available for UART4/UART5 */
+ if (USART_INT == USART_INT_CTSF)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ /* Get the USART register index */
+ usartreg = (((uint8_t)USART_INT) >> 0x05);
+ /* Get the interrupt position */
+ itmask = USART_INT & INT_MASK;
+ itmask = (uint32_t)0x01 << itmask;
+
+ if (usartreg == 0x01) /* The IT is in CTRL1 register */
+ {
+ itmask &= USARTx->CTRL1;
+ }
+ else if (usartreg == 0x02) /* The IT is in CTRL2 register */
+ {
+ itmask &= USARTx->CTRL2;
+ }
+ else /* The IT is in CTRL3 register */
+ {
+ itmask &= USARTx->CTRL3;
+ }
+
+ bitpos = USART_INT >> 0x08;
+ bitpos = (uint32_t)0x01 << bitpos;
+ bitpos &= USARTx->STS;
+ if ((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the USARTx's interrupt pending bits.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_INT specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg USART_INT_CTSF CTS change interrupt (not available for UART4 and UART5)
+ * @arg USART_INT_LINBD LIN Break detection interrupt
+ * @arg USART_INT_TXC Transmission complete interrupt.
+ * @arg USART_INT_RXDNE Receive Data register not empty interrupt.
+ *
+ * @note
+ * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ * error) and IDLE (Idle line detected) pending bits are cleared by
+ * software sequence: a read operation to USART_SR register
+ * (USART_GetIntStatus()) followed by a read operation to USART_DR register
+ * (USART_ReceiveData()).
+ * - RXNE pending bit can be also cleared by a read to the USART_DR register
+ * (USART_ReceiveData()).
+ * - TC pending bit can be also cleared by software sequence: a read
+ * operation to USART_SR register (USART_GetIntStatus()) followed by a write
+ * operation to USART_DR register (USART_SendData()).
+ * - TXE pending bit is cleared only by a write to the USART_DR register
+ * (USART_SendData()).
+ */
+void USART_ClrIntPendingBit(USART_Module* USARTx, uint16_t USART_INT)
+{
+ uint16_t bitpos = 0x00, itmask = 0x00;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_CLR_INT(USART_INT));
+ /* The CTS interrupt is not available for UART4/UART5 */
+ if (USART_INT == USART_INT_CTSF)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ bitpos = USART_INT >> 0x08;
+ itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
+ USARTx->STS = (uint16_t)~itmask;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_wwdg.c b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_wwdg.c
new file mode 100644
index 0000000000..d4a550d411
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_wwdg.c
@@ -0,0 +1,223 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l40x_wwdg.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l40x_wwdg.h"
+#include "n32l40x_rcc.h"
+
+/** @addtogroup n32l40x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup WWDG
+ * @brief WWDG driver modules
+ * @{
+ */
+
+/** @addtogroup WWDG_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Private_Defines
+ * @{
+ */
+
+/* ----------- WWDG registers bit address in the alias region ----------- */
+#define WWDG_OFFADDR (WWDG_BASE - PERIPH_BASE)
+
+/* Alias word address of EWI bit */
+#define CFG_OFFADDR (WWDG_OFFADDR + 0x04)
+#define EWINT_BIT 0x09
+#define CFG_EWINT_BB (PERIPH_BB_BASE + (CFG_OFFADDR * 32) + (EWINT_BIT * 4))
+
+/* --------------------- WWDG registers bit mask ------------------------ */
+
+/* CTRL register bit mask */
+#define CTRL_ACTB_SET ((uint32_t)0x00000080)
+
+/* CFG register bit mask */
+#define CFG_TIMERB_MASK ((uint32_t)0xFFFFFE7F)
+#define CFG_W_MASK ((uint32_t)0xFFFFFF80)
+#define BIT_MASK ((uint8_t)0x7F)
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the WWDG peripheral registers to their default reset values.
+ */
+void WWDG_DeInit(void)
+{
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_WWDG, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_WWDG, DISABLE);
+}
+
+/**
+ * @brief Sets the WWDG Prescaler.
+ * @param WWDG_Prescaler specifies the WWDG Prescaler.
+ * This parameter can be one of the following values:
+ * @arg WWDG_PRESCALER_DIV1 WWDG counter clock = (PCLK1/4096)/1
+ * @arg WWDG_PRESCALER_DIV2 WWDG counter clock = (PCLK1/4096)/2
+ * @arg WWDG_PRESCALER_DIV4 WWDG counter clock = (PCLK1/4096)/4
+ * @arg WWDG_PRESCALER_DIV8 WWDG counter clock = (PCLK1/4096)/8
+ */
+void WWDG_SetPrescalerDiv(uint32_t WWDG_Prescaler)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_WWDG_PRESCALER_DIV(WWDG_Prescaler));
+ /* Clear WDGTB[1:0] bits */
+ tmpregister = WWDG->CFG & CFG_TIMERB_MASK;
+ /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
+ tmpregister |= WWDG_Prescaler;
+ /* Store the new value */
+ WWDG->CFG = tmpregister;
+}
+
+/**
+ * @brief Sets the WWDG window value.
+ * @param WindowValue specifies the window value to be compared to the downcounter.
+ * This parameter value must be lower than 0x80.
+ */
+void WWDG_SetWValue(uint8_t WindowValue)
+{
+ __IO uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_WWDG_WVALUE(WindowValue));
+ /* Clear W[6:0] bits */
+
+ tmpregister = WWDG->CFG & CFG_W_MASK;
+
+ /* Set W[6:0] bits according to WindowValue value */
+ tmpregister |= WindowValue & (uint32_t)BIT_MASK;
+
+ /* Store the new value */
+ WWDG->CFG = tmpregister;
+}
+
+/**
+ * @brief Enables the WWDG Early Wakeup interrupt(EWI).
+ */
+void WWDG_EnableInt(void)
+{
+ *(__IO uint32_t*)CFG_EWINT_BB = (uint32_t)ENABLE;
+}
+
+/**
+ * @brief Sets the WWDG counter value.
+ * @param Counter specifies the watchdog counter value.
+ * This parameter must be a number between 0x40 and 0x7F.
+ */
+void WWDG_SetCnt(uint8_t Counter)
+{
+ /* Check the parameters */
+ assert_param(IS_WWDG_CNT(Counter));
+ /* Write to T[6:0] bits to configure the counter value, no need to do
+ a read-modify-write; writing a 0 to WDGA bit does nothing */
+ WWDG->CTRL = Counter & BIT_MASK;
+}
+
+/**
+ * @brief Enables WWDG and load the counter value.
+ * @param Counter specifies the watchdog counter value.
+ * This parameter must be a number between 0x40 and 0x7F.
+ */
+void WWDG_Enable(uint8_t Counter)
+{
+ /* Check the parameters */
+ assert_param(IS_WWDG_CNT(Counter));
+ WWDG->CTRL = CTRL_ACTB_SET | Counter;
+}
+
+/**
+ * @brief Checks whether the Early Wakeup interrupt flag is set or not.
+ * @return The new state of the Early Wakeup interrupt flag (SET or RESET)
+ */
+FlagStatus WWDG_GetEWINTF(void)
+{
+ return (FlagStatus)(WWDG->STS);
+}
+
+/**
+ * @brief Clears Early Wakeup interrupt flag.
+ */
+void WWDG_ClrEWINTF(void)
+{
+ WWDG->STS = (uint32_t)RESET;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_core.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_core.h
new file mode 100644
index 0000000000..180d07c9df
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_core.h
@@ -0,0 +1,264 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_core.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_CORE_H__
+#define __USB_CORE_H__
+
+#include "n32l40x.h"
+
+/**
+ * @addtogroup N32L40X_USB_Driver
+ * @brief N32L40x USB low level driver
+ * @{
+ */
+
+typedef enum _CONTROL_STATE
+{
+ WaitSetup, /* 0 */
+ SettingUp, /* 1 */
+ InData, /* 2 */
+ OutData, /* 3 */
+ LastInData, /* 4 */
+ LastOutData, /* 5 */
+ WaitStatusIn, /* 6 */
+ WaitStatusOut, /* 7 */
+ Stalled, /* 8 */
+ Pause /* 9 */
+} USB_ControlState; /* The state machine states of a control pipe */
+
+typedef struct OneDescriptor
+{
+ uint8_t* Descriptor;
+ uint16_t Descriptor_Size;
+} USB_OneDescriptor, *PONE_DESCRIPTOR;
+/* All the request process routines return a value of this type
+ If the return value is not SUCCESS or NOT_READY,
+ the software will STALL the correspond endpoint */
+typedef enum _RESULT
+{
+ Success = 0, /* Process successfully */
+ Error,
+ UnSupport,
+ Not_Ready /* The process has not been finished, endpoint will be
+ NAK to further request */
+} USB_Result;
+
+/*-*-*-*-*-*-*-*-*-*-* Definitions for endpoint level -*-*-*-*-*-*-*-*-*-*-*-*/
+typedef struct _ENDPOINT_INFO
+{
+ /* When send data out of the device,
+ CopyData() is used to get data buffer 'Length' bytes data
+ if Length is 0,
+ CopyData() returns the total length of the data
+ if the request is not supported, returns 0
+ (NEW Feature )
+ if CopyData() returns -1, the calling routine should not proceed
+ further and will resume the SETUP process by the class device
+ if Length is not 0,
+ CopyData() returns a pointer to indicate the data location
+ Usb_wLength is the data remain to be sent,
+ Usb_wOffset is the Offset of original data
+ When receive data from the host,
+ CopyData() is used to get user data buffer which is capable
+ of Length bytes data to copy data from the endpoint buffer.
+ if Length is 0,
+ CopyData() returns the available data length,
+ if Length is not 0,
+ CopyData() returns user buffer address
+ Usb_rLength is the data remain to be received,
+ Usb_rPointer is the Offset of data buffer
+ */
+ uint16_t Usb_wLength;
+ uint16_t Usb_wOffset;
+ uint16_t PacketSize;
+ uint8_t* (*CopyData)(uint16_t Length);
+} USB_EndpointMess;
+
+/*-*-*-*-*-*-*-*-*-*-*-* Definitions for device level -*-*-*-*-*-*-*-*-*-*-*-*/
+
+typedef struct _DEVICE
+{
+ uint8_t TotalEndpoint; /* Number of endpoints that are used */
+ uint8_t TotalConfiguration; /* Number of configuration available */
+} USB_Device;
+
+typedef union
+{
+ uint16_t w;
+ struct BW
+ {
+ uint8_t bb1;
+ uint8_t bb0;
+ } bw;
+} uint16_t_uint8_t;
+
+typedef struct _DEVICE_INFO
+{
+ uint8_t bmRequestType; /* bmRequestType */
+ uint8_t bRequest; /* bRequest */
+ uint16_t_uint8_t wValues; /* wValue */
+ uint16_t_uint8_t wIndexs; /* wIndex */
+ uint16_t_uint8_t wLengths; /* wLength */
+
+ uint8_t CtrlState; /* of type USB_ControlState */
+ uint8_t CurrentFeature;
+ uint8_t CurrentConfiguration; /* Selected configuration */
+ uint8_t CurrentInterface; /* Selected interface of current configuration */
+ uint8_t CurrentAlternateSetting; /* Selected Alternate Setting of current
+ interface*/
+
+ USB_EndpointMess Ctrl_Info;
+} USB_DeviceMess;
+
+typedef struct _DEVICE_PROP
+{
+ void (*Init)(void); /* Initialize the device */
+ void (*Reset)(void); /* Reset routine of this device */
+
+ /* Device dependent process after the status stage */
+ void (*Process_Status_IN)(void);
+ void (*Process_Status_OUT)(void);
+
+ /* Procedure of process on setup stage of a class specified request with data stage */
+ /* All class specified requests with data stage are processed in Class_Data_Setup
+ Class_Data_Setup()
+ responses to check all special requests and fills USB_EndpointMess
+ according to the request
+ If IN tokens are expected, then wLength & wOffset will be filled
+ with the total transferring bytes and the starting position
+ If OUT tokens are expected, then rLength & rOffset will be filled
+ with the total expected bytes and the starting position in the buffer
+
+ If the request is valid, Class_Data_Setup returns SUCCESS, else UNSUPPORT
+
+ CAUTION:
+ Since GET_CONFIGURATION & GET_INTERFACE are highly related to
+ the individual classes, they will be checked and processed here.
+ */
+ USB_Result (*Class_Data_Setup)(uint8_t RequestNo);
+
+ /* Procedure of process on setup stage of a class specified request without data stage */
+ /* All class specified requests without data stage are processed in Class_NoData_Setup
+ Class_NoData_Setup
+ responses to check all special requests and perform the request
+
+ CAUTION:
+ Since SET_CONFIGURATION & SET_INTERFACE are highly related to
+ the individual classes, they will be checked and processed here.
+ */
+ USB_Result (*Class_NoData_Setup)(uint8_t RequestNo);
+
+ /*Class_Get_Interface_Setting
+ This function is used by the file usb_core.c to test if the selected Interface
+ and Alternate Setting (uint8_t Interface, uint8_t AlternateSetting) are supported by
+ the application.
+ This function is writing by user. It should return "SUCCESS" if the Interface
+ and Alternate Setting are supported by the application or "UNSUPPORT" if they
+ are not supported. */
+
+ USB_Result (*Class_Get_Interface_Setting)(uint8_t Interface, uint8_t AlternateSetting);
+
+ uint8_t* (*GetDeviceDescriptor)(uint16_t Length);
+ uint8_t* (*GetConfigDescriptor)(uint16_t Length);
+ uint8_t* (*GetStringDescriptor)(uint16_t Length);
+
+ /* This field is not used in current library version. It is kept only for
+ compatibility with previous versions */
+ void* RxEP_buffer;
+
+ uint8_t MaxPacketSize;
+
+} DEVICE_PROP;
+
+typedef struct _USER_STANDARD_REQUESTS
+{
+ void (*User_GetConfiguration)(void); /* Get Configuration */
+ void (*User_SetConfiguration)(void); /* Set Configuration */
+ void (*User_GetInterface)(void); /* Get Interface */
+ void (*User_SetInterface)(void); /* Set Interface */
+ void (*User_GetStatus)(void); /* Get Status */
+ void (*User_ClearFeature)(void); /* Clear Feature */
+ void (*User_SetEndPointFeature)(void); /* Set Endpoint Feature */
+ void (*User_SetDeviceFeature)(void); /* Set Device Feature */
+ void (*User_SetDeviceAddress)(void); /* Set Device Address */
+} USER_STANDARD_REQUESTS;
+
+#define Type_Recipient (pInformation->bmRequestType & (REQUEST_TYPE | RECIPIENT))
+
+#define Usb_rLength Usb_wLength
+#define Usb_rOffset Usb_wOffset
+
+#define USBwValue wValues.w
+#define USBwValue0 wValues.bw.bb0
+#define USBwValue1 wValues.bw.bb1
+#define USBwIndex wIndexs.w
+#define USBwIndex0 wIndexs.bw.bb0
+#define USBwIndex1 wIndexs.bw.bb1
+#define USBwLength wLengths.w
+#define USBwLength0 wLengths.bw.bb0
+#define USBwLength1 wLengths.bw.bb1
+
+uint8_t USB_ProcessSetup0(void);
+uint8_t USB_ProcessPost0(void);
+uint8_t USB_ProcessOut0(void);
+uint8_t USB_ProcessIn0(void);
+
+USB_Result Standard_SetEndPointFeature(void);
+USB_Result Standard_SetDeviceFeature(void);
+
+uint8_t* Standard_GetConfiguration(uint16_t Length);
+USB_Result Standard_SetConfiguration(void);
+uint8_t* Standard_GetInterface(uint16_t Length);
+USB_Result Standard_SetInterface(void);
+uint8_t* Standard_GetDescriptorData(uint16_t Length, PONE_DESCRIPTOR pDesc);
+
+uint8_t* Standard_GetStatus(uint16_t Length);
+USB_Result Standard_ClearFeature(void);
+void USB_SetDeviceAddress(uint8_t);
+void USB_ProcessNop(void);
+
+extern DEVICE_PROP Device_Property;
+extern USER_STANDARD_REQUESTS User_Standard_Requests;
+extern USB_Device Device_Table;
+extern USB_DeviceMess Device_Info;
+
+/* cells saving status during interrupt servicing */
+extern __IO uint16_t SaveRState;
+extern __IO uint16_t SaveTState;
+
+/**
+ * @}
+ */
+
+#endif /* __USB_CORE_H__ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_def.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_def.h
new file mode 100644
index 0000000000..437f6e51cd
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_def.h
@@ -0,0 +1,98 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_def.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_DEF_H__
+#define __USB_DEF_H__
+
+/**
+ * @addtogroup N32L40X_USB_Driver
+ * @{
+ */
+
+typedef enum _RECIPIENT_TYPE
+{
+ DEVICE_RECIPIENT, /* Recipient device */
+ INTERFACE_RECIPIENT, /* Recipient interface */
+ ENDPOINT_RECIPIENT, /* Recipient endpoint */
+ OTHER_RECIPIENT
+} RECIPIENT_TYPE;
+
+typedef enum _STANDARD_REQUESTS
+{
+ GET_STATUS = 0,
+ CLR_FEATURE,
+ RESERVED1,
+ SET_FEATURE,
+ RESERVED2,
+ SET_ADDRESS,
+ GET_DESCRIPTOR,
+ SET_DESCRIPTOR,
+ GET_CONFIGURATION,
+ SET_CONFIGURATION,
+ GET_INTERFACE,
+ SET_INTERFACE,
+ TOTAL_SREQUEST, /* Total number of Standard request */
+ SYNCH_FRAME = 12
+} STANDARD_REQUESTS;
+
+/* Definition of "USBwValue" */
+typedef enum _DESCRIPTOR_TYPE
+{
+ DEVICE_DESCRIPTOR = 1,
+ CONFIG_DESCRIPTOR,
+ STRING_DESCRIPTOR,
+ INTERFACE_DESCRIPTOR,
+ ENDPOINT_DESCRIPTOR
+} DESCRIPTOR_TYPE;
+
+/* Feature selector of a SET_FEATURE or CLR_FEATURE */
+typedef enum _FEATURE_SELECTOR
+{
+ ENDPOINT_STALL,
+ DEVICE_REMOTE_WAKEUP
+} FEATURE_SELECTOR;
+
+/* Definition of "bmRequestType" */
+#define REQUEST_TYPE 0x60 /* Mask to get request type */
+#define STANDARD_REQUEST 0x00 /* Standard request */
+#define CLASS_REQUEST 0x20 /* Class request */
+#define VENDOR_REQUEST 0x40 /* Vendor request */
+
+#define RECIPIENT 0x1F /* Mask to get recipient */
+
+/**
+ * @}
+ */
+
+#endif /* __USB_DEF_H__ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_init.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_init.h
new file mode 100644
index 0000000000..c9ae6f638b
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_init.h
@@ -0,0 +1,71 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_init.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_INIT_H__
+#define __USB_INIT_H__
+
+#include "n32l40x.h"
+#include "usb_core.h"
+
+/**
+ * @addtogroup N32L40x_USB_Driver
+ * @{
+ */
+
+void USB_Init(void);
+
+/* The number of current endpoint, it will be used to specify an endpoint */
+extern uint8_t EPindex;
+/* The number of current device, it is an index to the Device_Table */
+/*extern uint8_t Device_no; */
+/* Points to the USB_DeviceMess structure of current device */
+/* The purpose of this register is to speed up the execution */
+extern USB_DeviceMess* pInformation;
+/* Points to the DEVICE_PROP structure of current device */
+/* The purpose of this register is to speed up the execution */
+extern DEVICE_PROP* pProperty;
+/* Temporary save the state of Rx & Tx status. */
+/* Whenever the Rx or Tx state is changed, its value is saved */
+/* in this variable first and will be set to the EPRB or EPRA */
+/* at the end of interrupt process */
+extern USER_STANDARD_REQUESTS* pUser_Standard_Requests;
+
+extern uint16_t SaveState;
+extern uint16_t wInterrupt_Mask;
+
+/**
+ * @}
+ */
+
+#endif /* __USB_INIT_H__ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_int.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_int.h
new file mode 100644
index 0000000000..2dc58c4e14
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_int.h
@@ -0,0 +1,50 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_int.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_INT_H__
+#define __USB_INT_H__
+
+/**
+ * @addtogroup N32L40x_USB_Driver
+ * @{
+ */
+
+void USB_CorrectTransferLp(void);
+void USB_CorrectTransferHp(void);
+
+/**
+ * @}
+ */
+
+#endif /* __USB_INT_H__ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_lib.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_lib.h
new file mode 100644
index 0000000000..0b1a044c89
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_lib.h
@@ -0,0 +1,47 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_lib.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_LIB_H__
+#define __USB_LIB_H__
+
+#include "usb_type.h"
+#include "usb_regs.h"
+#include "usb_def.h"
+#include "usb_core.h"
+#include "usb_init.h"
+#include "usb_sil.h"
+#include "usb_mem.h"
+#include "usb_int.h"
+
+#endif /* __USB_LIB_H__ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_mem.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_mem.h
new file mode 100644
index 0000000000..79fe49a1c6
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_mem.h
@@ -0,0 +1,52 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_mem.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_MEM_H__
+#define __USB_MEM_H__
+
+#include "n32l40x.h"
+
+/**
+ * @addtogroup N32L40x_USB_Driver
+ * @{
+ */
+
+void USB_CopyUserToPMABuf(uint8_t* pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+void USB_CopyPMAToUserBuf(uint8_t* pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+
+/**
+ * @}
+ */
+
+#endif /*__USB_MEM_H__*/
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_regs.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_regs.h
new file mode 100644
index 0000000000..37cdd01248
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_regs.h
@@ -0,0 +1,716 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_regs.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_REGS_H__
+#define __USB_REGS_H__
+
+#include "n32l40x.h"
+
+/**
+ * @addtogroup N32L40X_USB_Driver
+ * @{
+ */
+
+typedef enum _EP_DBUF_DIR
+{
+ /* double buffered endpoint direction */
+ EP_DBUF_ERR,
+ EP_DBUF_OUT,
+ EP_DBUF_IN
+} EP_DBUF_DIR;
+
+/* endpoint buffer number */
+enum EP_BUF_NUM
+{
+ EP_NOBUF,
+ EP_BUF0,
+ EP_BUF1
+};
+
+#define RegBase (0x40005C00L) /* USB_IP Peripheral Registers base address */
+#define PMAAddr (0x40006000L) /* USB_IP Packet Memory Area base address */
+
+/******************************************************************************/
+/* Special registers */
+/******************************************************************************/
+/* Pull up controller register */
+#define DP_CTRL ((__IO unsigned*)(0x40001824))
+
+#define _ClrDPCtrl() (*DP_CTRL = (*DP_CTRL) & (~0x8000000));
+#define _EnPortPullup() (*DP_CTRL = (*DP_CTRL) | 0x02000000);
+#define _DisPortPullup() (*DP_CTRL = (*DP_CTRL) & 0xFDFFFFFF);
+
+/******************************************************************************/
+/* General registers */
+/******************************************************************************/
+
+/* Control register */
+#define USB_CTRL ((__IO unsigned*)(RegBase + 0x40))
+/* Interrupt status register */
+#define USB_STS ((__IO unsigned*)(RegBase + 0x44))
+/* Frame number register */
+#define USB_FN ((__IO unsigned*)(RegBase + 0x48))
+/* Device address register */
+#define USB_ADDR ((__IO unsigned*)(RegBase + 0x4C))
+/* Buffer Table address register */
+#define USB_BUFTAB ((__IO unsigned*)(RegBase + 0x50))
+/******************************************************************************/
+/* Endpoint registers */
+/******************************************************************************/
+#define EP0REG ((__IO unsigned*)(RegBase)) /* endpoint 0 register address */
+
+/* Endpoint Addresses (w/direction) */
+#define EP0_OUT ((uint8_t)0x00)
+#define EP0_IN ((uint8_t)0x80)
+#define EP1_OUT ((uint8_t)0x01)
+#define EP1_IN ((uint8_t)0x81)
+#define EP2_OUT ((uint8_t)0x02)
+#define EP2_IN ((uint8_t)0x82)
+#define EP3_OUT ((uint8_t)0x03)
+#define EP3_IN ((uint8_t)0x83)
+#define EP4_OUT ((uint8_t)0x04)
+#define EP4_IN ((uint8_t)0x84)
+#define EP5_OUT ((uint8_t)0x05)
+#define EP5_IN ((uint8_t)0x85)
+#define EP6_OUT ((uint8_t)0x06)
+#define EP6_IN ((uint8_t)0x86)
+#define EP7_OUT ((uint8_t)0x07)
+#define EP7_IN ((uint8_t)0x87)
+
+/* endpoints enumeration */
+#define ENDP0 ((uint8_t)0)
+#define ENDP1 ((uint8_t)1)
+#define ENDP2 ((uint8_t)2)
+#define ENDP3 ((uint8_t)3)
+#define ENDP4 ((uint8_t)4)
+#define ENDP5 ((uint8_t)5)
+#define ENDP6 ((uint8_t)6)
+#define ENDP7 ((uint8_t)7)
+
+/******************************************************************************/
+/* USB_STS interrupt events */
+/******************************************************************************/
+#define STS_CTRS (0x8000) /* Correct TRansfer (clear-only bit) */
+#define STS_DOVR (0x4000) /* DMA OVeR/underrun (clear-only bit) */
+#define STS_ERROR (0x2000) /* ERRor (clear-only bit) */
+#define STS_WKUP (0x1000) /* WaKe UP (clear-only bit) */
+#define STS_SUSPD (0x0800) /* SUSPend (clear-only bit) */
+#define STS_RST (0x0400) /* RESET (clear-only bit) */
+#define STS_SOF (0x0200) /* Start Of Frame (clear-only bit) */
+#define STS_ESOF (0x0100) /* Expected Start Of Frame (clear-only bit) */
+
+#define STS_DIR (0x0010) /* DIRection of transaction (read-only bit) */
+#define STS_EP_ID (0x000F) /* EndPoint IDentifier (read-only bit) */
+
+#define CLR_CTRS (~STS_CTRS) /* clear Correct TRansfer bit */
+#define CLR_DOVR (~STS_DOVR) /* clear DMA OVeR/underrun bit*/
+#define CLR_ERROR (~STS_ERROR) /* clear ERRor bit */
+#define CLR_WKUP (~STS_WKUP) /* clear WaKe UP bit */
+#define CLR_SUSPD (~STS_SUSPD) /* clear SUSPend bit */
+#define CLR_RST (~STS_RST) /* clear RESET bit */
+#define CLR_SOF (~STS_SOF) /* clear Start Of Frame bit */
+#define CLR_ESOF (~STS_ESOF) /* clear Expected Start Of Frame bit */
+
+/******************************************************************************/
+/* USB_CTRL control register bits definitions */
+/******************************************************************************/
+#define CTRL_CTRSM (0x8000) /* Correct TRansfer Mask */
+#define CTRL_DOVRM (0x4000) /* DMA OVeR/underrun Mask */
+#define CTRL_ERRORM (0x2000) /* ERRor Mask */
+#define CTRL_WKUPM (0x1000) /* WaKe UP Mask */
+#define CTRL_SUSPDM (0x0800) /* SUSPend Mask */
+#define CTRL_RSTM (0x0400) /* RESET Mask */
+#define CTRL_SOFM (0x0200) /* Start Of Frame Mask */
+#define CTRL_ESOFM (0x0100) /* Expected Start Of Frame Mask */
+
+#define CTRL_RESUM (0x0010) /* RESUME request */
+#define CTRL_FSUSPD (0x0008) /* Force SUSPend */
+#define CTRL_LP_MODE (0x0004) /* Low-power MODE */
+#define CTRL_PD (0x0002) /* Power DoWN */
+#define CTRL_FRST (0x0001) /* Force USB RESet */
+
+/******************************************************************************/
+/* USB_FN Frame Number Register bit definitions */
+/******************************************************************************/
+#define FN_RXDP (0x8000) /* status of D+ data line */
+#define FN_RXDM (0x4000) /* status of D- data line */
+#define FN_LCK (0x2000) /* LoCKed */
+#define FN_LSOF (0x1800) /* Lost SOF */
+#define FN_FNUM (0x07FF) /* Frame Number */
+/******************************************************************************/
+/* USB_ADDR Device ADDRess bit definitions */
+/******************************************************************************/
+#define ADDR_EFUC (0x80)
+#define ADDR_ADDR (0x7F)
+/******************************************************************************/
+/* Endpoint register */
+/******************************************************************************/
+/* bit positions */
+#define EP_CTRS_RX (0x8000) /* EndPoint Correct TRansfer RX */
+#define EP_DATTOG_RX (0x4000) /* EndPoint Data TOGGLE RX */
+#define EPRX_STS (0x3000) /* EndPoint RX STATus bit field */
+#define EP_SETUP (0x0800) /* EndPoint SETUP */
+#define EP_T_FIELD (0x0600) /* EndPoint TYPE */
+#define EP_KIND (0x0100) /* EndPoint KIND */
+#define EP_CTRS_TX (0x0080) /* EndPoint Correct TRansfer TX */
+#define EP_DATTOG_TX (0x0040) /* EndPoint Data TOGGLE TX */
+#define EPTX_STS (0x0030) /* EndPoint TX STATus bit field */
+#define EPADDR_FIELD (0x000F) /* EndPoint ADDRess FIELD */
+
+/* EndPoint REGister INTEN (no toggle fields) */
+#define EPREG_MASK (EP_CTRS_RX | EP_SETUP | EP_T_FIELD | EP_KIND | EP_CTRS_TX | EPADDR_FIELD)
+
+/* EP_TYPE[1:0] EndPoint TYPE */
+#define EP_TYPE_MASK (0x0600) /* EndPoint TYPE Mask */
+#define EP_BULK (0x0000) /* EndPoint BULK */
+#define EP_CONTROL (0x0200) /* EndPoint CONTROL */
+#define EP_ISOCHRONOUS (0x0400) /* EndPoint ISOCHRONOUS */
+#define EP_INTERRUPT (0x0600) /* EndPoint INTERRUPT */
+#define EP_T_MASK (~EP_T_FIELD & EPREG_MASK)
+
+/* EP_KIND EndPoint KIND */
+#define EPKIND_MASK (~EP_KIND & EPREG_MASK)
+
+/* STAT_TX[1:0] STATus for TX transfer */
+#define EP_TX_DIS (0x0000) /* EndPoint TX DISabled */
+#define EP_TX_STALL (0x0010) /* EndPoint TX STALLed */
+#define EP_TX_NAK (0x0020) /* EndPoint TX NAKed */
+#define EP_TX_VALID (0x0030) /* EndPoint TX VALID */
+#define EPTX_DATTOG1 (0x0010) /* EndPoint TX Data TOGgle bit1 */
+#define EPTX_DATTOG2 (0x0020) /* EndPoint TX Data TOGgle bit2 */
+#define EPTX_DATTOGMASK (EPTX_STS | EPREG_MASK)
+
+/* STAT_RX[1:0] STATus for RX transfer */
+#define EP_RX_DIS (0x0000) /* EndPoint RX DISabled */
+#define EP_RX_STALL (0x1000) /* EndPoint RX STALLed */
+#define EP_RX_NAK (0x2000) /* EndPoint RX NAKed */
+#define EP_RX_VALID (0x3000) /* EndPoint RX VALID */
+#define EPRX_DATTOG1 (0x1000) /* EndPoint RX Data TOGgle bit1 */
+#define EPRX_DATTOG2 (0x2000) /* EndPoint RX Data TOGgle bit1 */
+#define EPRX_DATTOGMASK (EPRX_STS | EPREG_MASK)
+
+/* USB_SetCtrl */
+#define _SetCNTR(wRegValue) (*USB_CTRL = (uint16_t)wRegValue)
+
+/* USB_SetSts */
+#define _SetISTR(wRegValue) (*USB_STS = (uint16_t)wRegValue)
+
+/* USB_SetAddr */
+#define _SetDADDR(wRegValue) (*USB_ADDR = (uint16_t)wRegValue)
+
+/* USB_SetBuftab */
+#define _SetBTABLE(wRegValue) (*USB_BUFTAB = (uint16_t)(wRegValue & 0xFFF8))
+
+/* USB_GetCtrl */
+#define _GetCNTR() ((uint16_t)*USB_CTRL)
+
+/* USB_GetSts */
+#define _GetISTR() ((uint16_t)*USB_STS)
+
+/* USB_GetFn */
+#define _GetFNR() ((uint16_t)*USB_FN)
+
+/* USB_GetAddr */
+#define _GetDADDR() ((uint16_t)*USB_ADDR)
+
+/* USB_GetBTABLE */
+#define _GetBTABLE() ((uint16_t)*USB_BUFTAB)
+
+/* USB_SetEndPoint */
+#define _SetENDPOINT(bEpNum, wRegValue) (*(EP0REG + bEpNum) = (uint16_t)wRegValue)
+
+/* USB_GetEndPoint */
+#define _GetENDPOINT(bEpNum) ((uint16_t)(*(EP0REG + bEpNum)))
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpType
+ * Description : sets the type in the endpoint register(bits EP_TYPE[1:0])
+ * Input : bEpNum: Endpoint Number.
+ * wType
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPType(bEpNum, wType) (_SetENDPOINT(bEpNum, ((_GetENDPOINT(bEpNum) & EP_T_MASK) | wType)))
+
+/*******************************************************************************
+ * Macro Name : USB_GetEpType
+ * Description : gets the type in the endpoint register(bits EP_TYPE[1:0])
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : Endpoint Type
+ *******************************************************************************/
+#define _GetEPType(bEpNum) (_GetENDPOINT(bEpNum) & EP_T_FIELD)
+
+/*******************************************************************************
+ * Macro Name : SetEPTxStatus
+ * Description : sets the status for tx transfer (bits STAT_TX[1:0]).
+ * Input : bEpNum: Endpoint Number.
+ * wState: new state
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPTxStatus(bEpNum, wState) \
+ { \
+ register uint16_t _wRegVal; \
+ _wRegVal = _GetENDPOINT(bEpNum) & EPTX_DATTOGMASK; \
+ /* toggle first bit ? */ \
+ if ((EPTX_DATTOG1 & wState) != 0) \
+ _wRegVal ^= EPTX_DATTOG1; \
+ /* toggle second bit ? */ \
+ if ((EPTX_DATTOG2 & wState) != 0) \
+ _wRegVal ^= EPTX_DATTOG2; \
+ _SetENDPOINT(bEpNum, (_wRegVal | EP_CTRS_RX | EP_CTRS_TX)); \
+ } /* _SetEPTxStatus */
+
+/*******************************************************************************
+ * Macro Name : SetEPRxStatus
+ * Description : sets the status for rx transfer (bits STAT_TX[1:0])
+ * Input : bEpNum: Endpoint Number.
+ * wState: new state.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPRxStatus(bEpNum, wState) \
+ { \
+ register uint16_t _wRegVal; \
+ \
+ _wRegVal = _GetENDPOINT(bEpNum) & EPRX_DATTOGMASK; \
+ /* toggle first bit ? */ \
+ if ((EPRX_DATTOG1 & wState) != 0) \
+ _wRegVal ^= EPRX_DATTOG1; \
+ /* toggle second bit ? */ \
+ if ((EPRX_DATTOG2 & wState) != 0) \
+ _wRegVal ^= EPRX_DATTOG2; \
+ _SetENDPOINT(bEpNum, (_wRegVal | EP_CTRS_RX | EP_CTRS_TX)); \
+ } /* _SetEPRxStatus */
+
+/*******************************************************************************
+ * Macro Name : SetEPRxTxStatus
+ * Description : sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
+ * Input : bEpNum: Endpoint Number.
+ * wStaterx: new state.
+ * wStatetx: new state.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPRxTxStatus(bEpNum, wStaterx, wStatetx) \
+ { \
+ register uint32_t _wRegVal; \
+ \
+ _wRegVal = _GetENDPOINT(bEpNum) & (EPRX_DATTOGMASK | EPTX_STS); \
+ /* toggle first bit ? */ \
+ if ((EPRX_DATTOG1 & wStaterx) != 0) \
+ _wRegVal ^= EPRX_DATTOG1; \
+ /* toggle second bit ? */ \
+ if ((EPRX_DATTOG2 & wStaterx) != 0) \
+ _wRegVal ^= EPRX_DATTOG2; \
+ /* toggle first bit ? */ \
+ if ((EPTX_DATTOG1 & wStatetx) != 0) \
+ _wRegVal ^= EPTX_DATTOG1; \
+ /* toggle second bit ? */ \
+ if ((EPTX_DATTOG2 & wStatetx) != 0) \
+ _wRegVal ^= EPTX_DATTOG2; \
+ _SetENDPOINT(bEpNum, _wRegVal | EP_CTRS_RX | EP_CTRS_TX); \
+ } /* _SetEPRxTxStatus */
+/*******************************************************************************
+ * Macro Name : USB_GetEpTxSts / USB_GetEpRxSts
+ * Description : gets the status for tx/rx transfer (bits STAT_TX[1:0]
+ * /STAT_RX[1:0])
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : status .
+ *******************************************************************************/
+#define _GetEPTxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EPTX_STS)
+
+#define _GetEPRxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EPRX_STS)
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpTxValid / USB_SetEpRxValid
+ * Description : sets directly the VALID tx/rx-status into the enpoint register
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPTxValid(bEpNum) (_SetEPTxStatus(bEpNum, EP_TX_VALID))
+
+#define _SetEPRxValid(bEpNum) (_SetEPRxStatus(bEpNum, EP_RX_VALID))
+
+/*******************************************************************************
+ * Macro Name : USB_GetTxStallSts / USB_GetRxStallSts.
+ * Description : checks stall condition in an endpoint.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : TRUE = endpoint in stall condition.
+ *******************************************************************************/
+#define _GetTxStallStatus(bEpNum) (_GetEPTxStatus(bEpNum) == EP_TX_STALL)
+#define _GetRxStallStatus(bEpNum) (_GetEPRxStatus(bEpNum) == EP_RX_STALL)
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpKind / USB_ClrEpKind.
+ * Description : set & clear EP_KIND bit.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEP_KIND(bEpNum) \
+ (_SetENDPOINT(bEpNum, (EP_CTRS_RX | EP_CTRS_TX | ((_GetENDPOINT(bEpNum) | EP_KIND) & EPREG_MASK))))
+#define _ClearEP_KIND(bEpNum) (_SetENDPOINT(bEpNum, (EP_CTRS_RX | EP_CTRS_TX | (_GetENDPOINT(bEpNum) & EPKIND_MASK))))
+
+/*******************************************************************************
+ * Macro Name : USB_SetStsOut / USB_ClrStsOut.
+ * Description : Sets/clears directly STATUS_OUT bit in the endpoint register.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _Set_Status_Out(bEpNum) _SetEP_KIND(bEpNum)
+#define _Clear_Status_Out(bEpNum) _ClearEP_KIND(bEpNum)
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpDoubleBufer / USB_ClrEpDoubleBufer.
+ * Description : Sets/clears directly EP_KIND bit in the endpoint register.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPDoubleBuff(bEpNum) _SetEP_KIND(bEpNum)
+#define _ClearEPDoubleBuff(bEpNum) _ClearEP_KIND(bEpNum)
+
+/*******************************************************************************
+ * Macro Name : USB_ClrEpCtrsRx / USB_ClrEpCtrsTx.
+ * Description : Clears bit CTR_RX / CTR_TX in the endpoint register.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _ClearEP_CTR_RX(bEpNum) (_SetENDPOINT(bEpNum, _GetENDPOINT(bEpNum) & 0x7FFF & EPREG_MASK))
+#define _ClearEP_CTR_TX(bEpNum) (_SetENDPOINT(bEpNum, _GetENDPOINT(bEpNum) & 0xFF7F & EPREG_MASK))
+
+/*******************************************************************************
+ * Macro Name : USB_DattogRx / USB_DattogTx .
+ * Description : Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _ToggleDTOG_RX(bEpNum) \
+ (_SetENDPOINT(bEpNum, EP_CTRS_RX | EP_CTRS_TX | EP_DATTOG_RX | (_GetENDPOINT(bEpNum) & EPREG_MASK)))
+#define _ToggleDTOG_TX(bEpNum) \
+ (_SetENDPOINT(bEpNum, EP_CTRS_RX | EP_CTRS_TX | EP_DATTOG_TX | (_GetENDPOINT(bEpNum) & EPREG_MASK)))
+
+/*******************************************************************************
+ * Macro Name : USB_ClrDattogRx / USB_ClrDattogTx.
+ * Description : Clears DTOG_RX / DTOG_TX bit in the endpoint register.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _ClearDTOG_RX(bEpNum) \
+ if ((_GetENDPOINT(bEpNum) & EP_DATTOG_RX) != 0) \
+ _ToggleDTOG_RX(bEpNum)
+#define _ClearDTOG_TX(bEpNum) \
+ if ((_GetENDPOINT(bEpNum) & EP_DATTOG_TX) != 0) \
+ _ToggleDTOG_TX(bEpNum)
+/*******************************************************************************
+ * Macro Name : USB_SetEpAddress.
+ * Description : Sets address in an endpoint register.
+ * Input : bEpNum: Endpoint Number.
+ * bAddr: Address.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPAddress(bEpNum, bAddr) \
+ _SetENDPOINT(bEpNum, EP_CTRS_RX | EP_CTRS_TX | (_GetENDPOINT(bEpNum) & EPREG_MASK) | bAddr)
+
+/*******************************************************************************
+ * Macro Name : USB_GetEpAddress.
+ * Description : Gets address in an endpoint register.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _GetEPAddress(bEpNum) ((uint8_t)(_GetENDPOINT(bEpNum) & EPADDR_FIELD))
+
+#define _pEPTxAddr(bEpNum) ((uint32_t*)((_GetBTABLE() + bEpNum * 8) * 2 + PMAAddr))
+#define _pEPTxCount(bEpNum) ((uint32_t*)((_GetBTABLE() + bEpNum * 8 + 2) * 2 + PMAAddr))
+#define _pEPRxAddr(bEpNum) ((uint32_t*)((_GetBTABLE() + bEpNum * 8 + 4) * 2 + PMAAddr))
+#define _pEPRxCount(bEpNum) ((uint32_t*)((_GetBTABLE() + bEpNum * 8 + 6) * 2 + PMAAddr))
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpTxAddr / USB_SetEpRxAddr.
+ * Description : sets address of the tx/rx buffer.
+ * Input : bEpNum: Endpoint Number.
+ * wAddr: address to be set (must be word aligned).
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPTxAddr(bEpNum, wAddr) (*_pEPTxAddr(bEpNum) = ((wAddr >> 1) << 1))
+#define _SetEPRxAddr(bEpNum, wAddr) (*_pEPRxAddr(bEpNum) = ((wAddr >> 1) << 1))
+
+/*******************************************************************************
+ * Macro Name : USB_GetEpTxAddr / USB_GetEpRxAddr.
+ * Description : Gets address of the tx/rx buffer.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : address of the buffer.
+ *******************************************************************************/
+#define _GetEPTxAddr(bEpNum) ((uint16_t)*_pEPTxAddr(bEpNum))
+#define _GetEPRxAddr(bEpNum) ((uint16_t)*_pEPRxAddr(bEpNum))
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpCntRxReg.
+ * Description : Sets counter of rx buffer with no. of blocks.
+ * Input : pdwReg: pointer to counter.
+ * wCount: Counter.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _BlocksOf32(dwReg, wCount, wNBlocks) \
+ { \
+ wNBlocks = wCount >> 5; \
+ if ((wCount & 0x1f) == 0) \
+ wNBlocks--; \
+ *pdwReg = (uint32_t)((wNBlocks << 10) | 0x8000); \
+ } /* _BlocksOf32 */
+
+#define _BlocksOf2(dwReg, wCount, wNBlocks) \
+ { \
+ wNBlocks = wCount >> 1; \
+ if ((wCount & 0x1) != 0) \
+ wNBlocks++; \
+ *pdwReg = (uint32_t)(wNBlocks << 10); \
+ } /* _BlocksOf2 */
+
+#define _SetEPCountRxReg(dwReg, wCount) \
+ { \
+ uint16_t wNBlocks; \
+ if (wCount > 62) \
+ { \
+ _BlocksOf32(dwReg, wCount, wNBlocks); \
+ } \
+ else \
+ { \
+ _BlocksOf2(dwReg, wCount, wNBlocks); \
+ } \
+ } /* _SetEPCountRxReg */
+
+#define _SetEPRxDblBuf0Count(bEpNum, wCount) \
+ { \
+ uint32_t* pdwReg = _pEPTxCount(bEpNum); \
+ _SetEPCountRxReg(pdwReg, wCount); \
+ }
+/*******************************************************************************
+ * Macro Name : USB_SetEpTxCnt / USB_SetEpRxCnt.
+ * Description : sets counter for the tx/rx buffer.
+ * Input : bEpNum: endpoint number.
+ * wCount: Counter value.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPTxCount(bEpNum, wCount) (*_pEPTxCount(bEpNum) = wCount)
+#define _SetEPRxCount(bEpNum, wCount) \
+ { \
+ uint32_t* pdwReg = _pEPRxCount(bEpNum); \
+ _SetEPCountRxReg(pdwReg, wCount); \
+ }
+/*******************************************************************************
+ * Macro Name : USB_GetEpTxCnt / USB_GetEpRxCnt.
+ * Description : gets counter of the tx buffer.
+ * Input : bEpNum: endpoint number.
+ * Output : None.
+ * Return : Counter value.
+ *******************************************************************************/
+#define _GetEPTxCount(bEpNum) ((uint16_t)(*_pEPTxCount(bEpNum)) & 0x3ff)
+#define _GetEPRxCount(bEpNum) ((uint16_t)(*_pEPRxCount(bEpNum)) & 0x3ff)
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpDblBuf0Addr / USB_SetEpDblBuf1Addr.
+ * Description : Sets buffer 0/1 address in a double buffer endpoint.
+ * Input : bEpNum: endpoint number.
+ * : wBuf0Addr: buffer 0 address.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPDblBuf0Addr(bEpNum, wBuf0Addr) \
+ { \
+ _SetEPTxAddr(bEpNum, wBuf0Addr); \
+ }
+#define _SetEPDblBuf1Addr(bEpNum, wBuf1Addr) \
+ { \
+ _SetEPRxAddr(bEpNum, wBuf1Addr); \
+ }
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpDblBuferAddr.
+ * Description : Sets addresses in a double buffer endpoint.
+ * Input : bEpNum: endpoint number.
+ * : wBuf0Addr: buffer 0 address.
+ * : wBuf1Addr = buffer 1 address.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPDblBuffAddr(bEpNum, wBuf0Addr, wBuf1Addr) \
+ { \
+ _SetEPDblBuf0Addr(bEpNum, wBuf0Addr); \
+ _SetEPDblBuf1Addr(bEpNum, wBuf1Addr); \
+ } /* _SetEPDblBuffAddr */
+
+/*******************************************************************************
+ * Macro Name : USB_GetEpDblBuf0Addr / USB_GetEpDblBuf1Addr.
+ * Description : Gets buffer 0/1 address of a double buffer endpoint.
+ * Input : bEpNum: endpoint number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _GetEPDblBuf0Addr(bEpNum) (_GetEPTxAddr(bEpNum))
+#define _GetEPDblBuf1Addr(bEpNum) (_GetEPRxAddr(bEpNum))
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpDblBuferCnt / USB_SetEpDblBuf0Cnt / USB_SetEpDblBuf1Cnt.
+ * Description : Gets buffer 0/1 address of a double buffer endpoint.
+ * Input : bEpNum: endpoint number.
+ * : bDir: endpoint dir EP_DBUF_OUT = OUT
+ * EP_DBUF_IN = IN
+ * : wCount: Counter value
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPDblBuf0Count(bEpNum, bDir, wCount) \
+ { \
+ if (bDir == EP_DBUF_OUT) \
+ /* OUT endpoint */ \
+ { \
+ _SetEPRxDblBuf0Count(bEpNum, wCount); \
+ } \
+ else if (bDir == EP_DBUF_IN) \
+ /* IN endpoint */ \
+ *_pEPTxCount(bEpNum) = (uint32_t)wCount; \
+ } /* USB_SetEpDblBuf0Cnt*/
+
+#define _SetEPDblBuf1Count(bEpNum, bDir, wCount) \
+ { \
+ if (bDir == EP_DBUF_OUT) \
+ /* OUT endpoint */ \
+ { \
+ _SetEPRxCount(bEpNum, wCount); \
+ } \
+ else if (bDir == EP_DBUF_IN) \
+ /* IN endpoint */ \
+ *_pEPRxCount(bEpNum) = (uint32_t)wCount; \
+ } /* USB_SetEpDblBuf1Cnt */
+
+#define _SetEPDblBuffCount(bEpNum, bDir, wCount) \
+ { \
+ _SetEPDblBuf0Count(bEpNum, bDir, wCount); \
+ _SetEPDblBuf1Count(bEpNum, bDir, wCount); \
+ } /* _SetEPDblBuffCount */
+
+/*******************************************************************************
+ * Macro Name : USB_GetEpDblBuf0Cnt / USB_GetEpDblBuf1Cnt.
+ * Description : Gets buffer 0/1 rx/tx counter for double buffering.
+ * Input : bEpNum: endpoint number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _GetEPDblBuf0Count(bEpNum) (_GetEPTxCount(bEpNum))
+#define _GetEPDblBuf1Count(bEpNum) (_GetEPRxCount(bEpNum))
+
+extern __IO uint16_t wIstr; /* USB_STS register last read value */
+
+void USB_SetCtrl(uint16_t /*wRegValue*/);
+void USB_SetSts(uint16_t /*wRegValue*/);
+void USB_SetAddr(uint16_t /*wRegValue*/);
+void USB_SetBuftab(uint16_t /*wRegValue*/);
+void USB_SetBuftab(uint16_t /*wRegValue*/);
+uint16_t USB_GetCtrl(void);
+uint16_t USB_GetSts(void);
+uint16_t USB_GetFn(void);
+uint16_t USB_GetAddr(void);
+uint16_t USB_GetBTABLE(void);
+void USB_SetEndPoint(uint8_t /*bEpNum*/, uint16_t /*wRegValue*/);
+uint16_t USB_GetEndPoint(uint8_t /*bEpNum*/);
+void USB_SetEpType(uint8_t /*bEpNum*/, uint16_t /*wType*/);
+uint16_t USB_GetEpType(uint8_t /*bEpNum*/);
+void SetEPTxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/);
+void SetEPRxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/);
+void USB_SetDouBleBuferEpStall(uint8_t /*bEpNum*/, uint8_t bDir);
+uint16_t USB_GetEpTxSts(uint8_t /*bEpNum*/);
+uint16_t USB_GetEpRxSts(uint8_t /*bEpNum*/);
+void USB_SetEpTxValid(uint8_t /*bEpNum*/);
+void USB_SetEpRxValid(uint8_t /*bEpNum*/);
+uint16_t USB_GetTxStallSts(uint8_t /*bEpNum*/);
+uint16_t USB_GetRxStallSts(uint8_t /*bEpNum*/);
+void USB_SetEpKind(uint8_t /*bEpNum*/);
+void USB_ClrEpKind(uint8_t /*bEpNum*/);
+void USB_SetStsOut(uint8_t /*bEpNum*/);
+void USB_ClrStsOut(uint8_t /*bEpNum*/);
+void USB_SetEpDoubleBufer(uint8_t /*bEpNum*/);
+void USB_ClrEpDoubleBufer(uint8_t /*bEpNum*/);
+void USB_ClrEpCtrsRx(uint8_t /*bEpNum*/);
+void USB_ClrEpCtrsTx(uint8_t /*bEpNum*/);
+void USB_DattogRx(uint8_t /*bEpNum*/);
+void USB_DattogTx(uint8_t /*bEpNum*/);
+void USB_ClrDattogRx(uint8_t /*bEpNum*/);
+void USB_ClrDattogTx(uint8_t /*bEpNum*/);
+void USB_SetEpAddress(uint8_t /*bEpNum*/, uint8_t /*bAddr*/);
+uint8_t USB_GetEpAddress(uint8_t /*bEpNum*/);
+void USB_SetEpTxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/);
+void USB_SetEpRxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/);
+uint16_t USB_GetEpTxAddr(uint8_t /*bEpNum*/);
+uint16_t USB_GetEpRxAddr(uint8_t /*bEpNum*/);
+void USB_SetEpCntRxReg(uint32_t* /*pdwReg*/, uint16_t /*wCount*/);
+void USB_SetEpTxCnt(uint8_t /*bEpNum*/, uint16_t /*wCount*/);
+void USB_SetEpRxCnt(uint8_t /*bEpNum*/, uint16_t /*wCount*/);
+uint16_t USB_GetEpTxCnt(uint8_t /*bEpNum*/);
+uint16_t USB_GetEpRxCnt(uint8_t /*bEpNum*/);
+void USB_SetEpDblBuf0Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/);
+void USB_SetEpDblBuf1Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf1Addr*/);
+void USB_SetEpDblBuferAddr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/, uint16_t /*wBuf1Addr*/);
+uint16_t USB_GetEpDblBuf0Addr(uint8_t /*bEpNum*/);
+uint16_t USB_GetEpDblBuf1Addr(uint8_t /*bEpNum*/);
+void USB_SetEpDblBuferCnt(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
+void USB_SetEpDblBuf0Cnt(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
+void USB_SetEpDblBuf1Cnt(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
+uint16_t USB_GetEpDblBuf0Cnt(uint8_t /*bEpNum*/);
+uint16_t USB_GetEpDblBuf1Cnt(uint8_t /*bEpNum*/);
+EP_DBUF_DIR GetEPDblBufDir(uint8_t /*bEpNum*/);
+void USB_FreeUserBuf(uint8_t bEpNum /*bEpNum*/, uint8_t bDir);
+uint16_t USB_ToWord(uint8_t, uint8_t);
+uint16_t USB_ByteSwap(uint16_t);
+
+/**
+ * @}
+ */
+
+#endif /* __USB_REGS_H__ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_sil.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_sil.h
new file mode 100644
index 0000000000..4990c97257
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_sil.h
@@ -0,0 +1,53 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_sil.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_SIL_H__
+#define __USB_SIL_H__
+
+#include "n32l40x.h"
+
+/**
+ * @addtogroup N32L40x_USB_Driver
+ * @{
+ */
+
+uint32_t USB_SilInit(void);
+uint32_t USB_SilWrite(uint8_t bEpAddr, uint8_t* pBufferPointer, uint32_t wBufferSize);
+uint32_t USB_SilRead(uint8_t bEpAddr, uint8_t* pBufferPointer);
+
+/**
+ * @}
+ */
+
+#endif /* __USB_SIL_H__ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_type.h b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_type.h
new file mode 100644
index 0000000000..4a4c70ec14
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_type.h
@@ -0,0 +1,54 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_type.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_TYPE_H__
+#define __USB_TYPE_H__
+
+#include "usb_conf.h"
+#include
+
+/**
+ * @addtogroup N32L40X_USB_Driver
+ * @{
+ */
+
+#ifndef NULL
+#define NULL ((void*)0)
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* __USB_TYPE_H__ */
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_core.c b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_core.c
new file mode 100644
index 0000000000..77ece332a8
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_core.c
@@ -0,0 +1,950 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_core.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "usb_lib.h"
+
+#define ValBit(VAR, Place) (VAR & (1 << Place))
+#define SetBit(VAR, Place) (VAR |= (1 << Place))
+#define ClrBit(VAR, Place) (VAR &= ((1 << Place) ^ 255))
+
+#define Send0LengthData() \
+ { \
+ _SetEPTxCount(ENDP0, 0); \
+ vSetEPTxStatus(EP_TX_VALID); \
+ }
+
+#define vSetEPRxStatus(st) (SaveRState = st)
+#define vSetEPTxStatus(st) (SaveTState = st)
+
+#define USB_StatusIn() Send0LengthData()
+#define USB_StatusOut() vSetEPRxStatus(EP_RX_VALID)
+
+#define StatusInfo0 StatusInfo.bw.bb1 /* Reverse bb0 & bb1 */
+#define StatusInfo1 StatusInfo.bw.bb0
+
+uint16_t_uint8_t StatusInfo;
+
+bool Data_Mul_MaxPacketSize = false;
+
+static void DataStageOut(void);
+static void DataStageIn(void);
+static void NoData_Setup0(void);
+static void Data_Setup0(void);
+
+/**
+ * @brief Return the current configuration variable address.
+ * Input : Length - How many bytes are needed.
+ * @return Return 1 , if the request is invalid when "Length" is 0.
+ * Return "Buffer" if the "Length" is not 0.
+ */
+uint8_t* Standard_GetConfiguration(uint16_t Length)
+{
+ if (Length == 0)
+ {
+ pInformation->Ctrl_Info.Usb_wLength = sizeof(pInformation->CurrentConfiguration);
+ return 0;
+ }
+ pUser_Standard_Requests->User_GetConfiguration();
+ return (uint8_t*)&pInformation->CurrentConfiguration;
+}
+
+/**
+ * @brief This routine is called to set the configuration value
+ * Then each class should configure device itself.
+ * @return
+ * - Success, if the request is performed.
+ * - UnSupport, if the request is invalid.
+ */
+USB_Result Standard_SetConfiguration(void)
+{
+ if ((pInformation->USBwValue0 <= Device_Table.TotalConfiguration) && (pInformation->USBwValue1 == 0)
+ && (pInformation->USBwIndex == 0)) /*call Back usb spec 2.0*/
+ {
+ pInformation->CurrentConfiguration = pInformation->USBwValue0;
+ pUser_Standard_Requests->User_SetConfiguration();
+ return Success;
+ }
+ else
+ {
+ return UnSupport;
+ }
+}
+
+/**
+ * @brief Return the Alternate Setting of the current interface.
+ * Input : Length - How many bytes are needed.
+ * @return
+ * - NULL, if the request is invalid when "Length" is 0.
+ * - "Buffer" if the "Length" is not 0.
+ */
+uint8_t* Standard_GetInterface(uint16_t Length)
+{
+ if (Length == 0)
+ {
+ pInformation->Ctrl_Info.Usb_wLength = sizeof(pInformation->CurrentAlternateSetting);
+ return 0;
+ }
+ pUser_Standard_Requests->User_GetInterface();
+ return (uint8_t*)&pInformation->CurrentAlternateSetting;
+}
+
+/**
+ * @brief This routine is called to set the interface.
+ * Then each class should configure the interface them self.
+ * @return
+ * - Success, if the request is performed.
+ * - UnSupport, if the request is invalid.
+ */
+USB_Result Standard_SetInterface(void)
+{
+ USB_Result Re;
+ /*Test if the specified Interface and Alternate Setting are supported by
+ the application Firmware*/
+ Re = (*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, pInformation->USBwValue0);
+
+ if (pInformation->CurrentConfiguration != 0)
+ {
+ if ((Re != Success) || (pInformation->USBwIndex1 != 0) || (pInformation->USBwValue1 != 0))
+ {
+ return UnSupport;
+ }
+ else if (Re == Success)
+ {
+ pUser_Standard_Requests->User_SetInterface();
+ pInformation->CurrentInterface = pInformation->USBwIndex0;
+ pInformation->CurrentAlternateSetting = pInformation->USBwValue0;
+ return Success;
+ }
+ }
+
+ return UnSupport;
+}
+
+/**
+ * @brief Copy the device request data to "StatusInfo buffer".
+ * Input : - Length - How many bytes are needed.
+ * @return Return 0, if the request is at end of data block,
+ * or is invalid when "Length" is 0.
+ */
+uint8_t* Standard_GetStatus(uint16_t Length)
+{
+ if (Length == 0)
+ {
+ pInformation->Ctrl_Info.Usb_wLength = 2;
+ return 0;
+ }
+
+ /* Reset Status Information */
+ StatusInfo.w = 0;
+
+ if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+ {
+ /*Get Device Status */
+ uint8_t Feature = pInformation->CurrentFeature;
+
+ /* Remote Wakeup enabled */
+ if (ValBit(Feature, 5))
+ {
+ SetBit(StatusInfo0, 1);
+ }
+ else
+ {
+ ClrBit(StatusInfo0, 1);
+ }
+
+ /* Bus-powered */
+ if (ValBit(Feature, 6))
+ {
+ SetBit(StatusInfo0, 0);
+ }
+ else /* Self-powered */
+ {
+ ClrBit(StatusInfo0, 0);
+ }
+ }
+ /*Interface Status*/
+ else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
+ {
+ return (uint8_t*)&StatusInfo;
+ }
+ /*Get EndPoint Status*/
+ else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+ {
+ uint8_t Related_Endpoint;
+ uint8_t wIndex0 = pInformation->USBwIndex0;
+
+ Related_Endpoint = (wIndex0 & 0x0f);
+ if (ValBit(wIndex0, 7))
+ {
+ /* IN endpoint */
+ if (_GetTxStallStatus(Related_Endpoint))
+ {
+ SetBit(StatusInfo0, 0); /* IN Endpoint stalled */
+ }
+ }
+ else
+ {
+ /* OUT endpoint */
+ if (_GetRxStallStatus(Related_Endpoint))
+ {
+ SetBit(StatusInfo0, 0); /* OUT Endpoint stalled */
+ }
+ }
+ }
+ else
+ {
+ return NULL;
+ }
+ pUser_Standard_Requests->User_GetStatus();
+ return (uint8_t*)&StatusInfo;
+}
+
+/**
+ * @brief Clear or disable a specific feature.
+ * @return - Return Success, if the request is performed.
+ * - Return UnSupport, if the request is invalid.
+ */
+USB_Result Standard_ClearFeature(void)
+{
+ uint32_t Type_Rec = Type_Recipient;
+ uint32_t Status;
+
+ if (Type_Rec == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+ { /*Device Clear Feature*/
+ ClrBit(pInformation->CurrentFeature, 5);
+ return Success;
+ }
+ else if (Type_Rec == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+ { /*EndPoint Clear Feature*/
+ USB_Device* pDev;
+ uint32_t Related_Endpoint;
+ uint32_t wIndex0;
+ uint32_t rEP;
+
+ if ((pInformation->USBwValue != ENDPOINT_STALL) || (pInformation->USBwIndex1 != 0))
+ {
+ return UnSupport;
+ }
+
+ pDev = &Device_Table;
+ wIndex0 = pInformation->USBwIndex0;
+ rEP = wIndex0 & ~0x80;
+ Related_Endpoint = ENDP0 + rEP;
+
+ if (ValBit(pInformation->USBwIndex0, 7))
+ {
+ /*Get Status of endpoint & stall the request if the related_ENdpoint
+ is Disabled*/
+ Status = _GetEPTxStatus(Related_Endpoint);
+ }
+ else
+ {
+ Status = _GetEPRxStatus(Related_Endpoint);
+ }
+
+ if ((rEP >= pDev->TotalEndpoint) || (Status == 0) || (pInformation->CurrentConfiguration == 0))
+ {
+ return UnSupport;
+ }
+
+ if (wIndex0 & 0x80)
+ {
+ /* IN endpoint */
+ if (_GetTxStallStatus(Related_Endpoint))
+ {
+ USB_ClrDattogTx(Related_Endpoint);
+ SetEPTxStatus(Related_Endpoint, EP_TX_VALID);
+ }
+ }
+ else
+ {
+ /* OUT endpoint */
+ if (_GetRxStallStatus(Related_Endpoint))
+ {
+ if (Related_Endpoint == ENDP0)
+ {
+ /* After clear the STALL, enable the default endpoint receiver */
+ USB_SetEpRxCnt(Related_Endpoint, Device_Property.MaxPacketSize);
+ _SetEPRxStatus(Related_Endpoint, EP_RX_VALID);
+ }
+ else
+ {
+ USB_ClrDattogRx(Related_Endpoint);
+ _SetEPRxStatus(Related_Endpoint, EP_RX_VALID);
+ }
+ }
+ }
+ pUser_Standard_Requests->User_ClearFeature();
+ return Success;
+ }
+
+ return UnSupport;
+}
+
+/**
+ * @brief Set or enable a specific feature of EndPoint
+ * @return - Return Success, if the request is performed.
+ * - Return UnSupport, if the request is invalid.
+ */
+USB_Result Standard_SetEndPointFeature(void)
+{
+ uint32_t wIndex0;
+ uint32_t Related_Endpoint;
+ uint32_t rEP;
+ uint32_t Status;
+
+ wIndex0 = pInformation->USBwIndex0;
+ rEP = wIndex0 & ~0x80;
+ Related_Endpoint = ENDP0 + rEP;
+
+ if (ValBit(pInformation->USBwIndex0, 7))
+ {
+ /* get Status of endpoint & stall the request if the related_ENdpoint
+ is Disabled*/
+ Status = _GetEPTxStatus(Related_Endpoint);
+ }
+ else
+ {
+ Status = _GetEPRxStatus(Related_Endpoint);
+ }
+
+ if (Related_Endpoint >= Device_Table.TotalEndpoint || pInformation->USBwValue != 0 || Status == 0
+ || pInformation->CurrentConfiguration == 0)
+ {
+ return UnSupport;
+ }
+ else
+ {
+ if (wIndex0 & 0x80)
+ {
+ /* IN endpoint */
+ _SetEPTxStatus(Related_Endpoint, EP_TX_STALL);
+ }
+
+ else
+ {
+ /* OUT endpoint */
+ _SetEPRxStatus(Related_Endpoint, EP_RX_STALL);
+ }
+ }
+ pUser_Standard_Requests->User_SetEndPointFeature();
+ return Success;
+}
+
+/**
+ * @brief Set or enable a specific feature of Device.
+ * @return - Return Success, if the request is performed.
+ * - Return UnSupport, if the request is invalid.
+ */
+USB_Result Standard_SetDeviceFeature(void)
+{
+ SetBit(pInformation->CurrentFeature, 5);
+ pUser_Standard_Requests->User_SetDeviceFeature();
+ return Success;
+}
+
+/**
+ * @brief Standard_GetDescriptorData is used for descriptors transfer.
+ * : This routine is used for the descriptors resident in Flash
+ * or RAM
+ * pDesc can be in either Flash or RAM
+ * The purpose of this routine is to have a versatile way to
+ * response descriptors request. It allows user to generate
+ * certain descriptors with software or read descriptors from
+ * external storage part by part.
+ * Input : - Length - Length of the data in this transfer.
+ * - pDesc - A pointer points to descriptor struct.
+ * The structure gives the initial address of the descriptor and
+ * its original size.
+ * @return Address of a part of the descriptor pointed by the Usb_
+ * wOffset The buffer pointed by this address contains at least
+ * Length bytes.
+ */
+uint8_t* Standard_GetDescriptorData(uint16_t Length, USB_OneDescriptor* pDesc)
+{
+ uint32_t wOffset;
+
+ wOffset = pInformation->Ctrl_Info.Usb_wOffset;
+ if (Length == 0)
+ {
+ pInformation->Ctrl_Info.Usb_wLength = pDesc->Descriptor_Size - wOffset;
+ return 0;
+ }
+
+ return pDesc->Descriptor + wOffset;
+}
+
+/**
+ * @brief Data stage of a Control Write Transfer.
+ */
+void DataStageOut(void)
+{
+ USB_EndpointMess* pEPinfo = &pInformation->Ctrl_Info;
+ uint32_t save_rLength;
+
+ save_rLength = pEPinfo->Usb_rLength;
+
+ if (pEPinfo->CopyData && save_rLength)
+ {
+ uint8_t* Buffer;
+ uint32_t Length;
+
+ Length = pEPinfo->PacketSize;
+ if (Length > save_rLength)
+ {
+ Length = save_rLength;
+ }
+
+ Buffer = (*pEPinfo->CopyData)(Length);
+ pEPinfo->Usb_rLength -= Length;
+ pEPinfo->Usb_rOffset += Length;
+
+ USB_CopyPMAToUserBuf(Buffer, USB_GetEpRxAddr(ENDP0), Length);
+ }
+
+ if (pEPinfo->Usb_rLength != 0)
+ {
+ vSetEPRxStatus(EP_RX_VALID); /* re-enable for next data reception */
+ USB_SetEpTxCnt(ENDP0, 0);
+ vSetEPTxStatus(EP_TX_VALID); /* Expect the host to abort the data OUT stage */
+ }
+ /* Set the next State*/
+ if (pEPinfo->Usb_rLength >= pEPinfo->PacketSize)
+ {
+ pInformation->CtrlState = OutData;
+ }
+ else
+ {
+ if (pEPinfo->Usb_rLength > 0)
+ {
+ pInformation->CtrlState = LastOutData;
+ }
+ else if (pEPinfo->Usb_rLength == 0)
+ {
+ pInformation->CtrlState = WaitStatusIn;
+ USB_StatusIn();
+ }
+ }
+}
+
+/**
+ * @brief Data stage of a Control Read Transfer.
+ */
+void DataStageIn(void)
+{
+ USB_EndpointMess* pEPinfo = &pInformation->Ctrl_Info;
+ uint32_t save_wLength = pEPinfo->Usb_wLength;
+ uint32_t CtrlState = pInformation->CtrlState;
+
+ uint8_t* DataBuffer;
+ uint32_t Length;
+
+ if ((save_wLength == 0) && (CtrlState == LastInData))
+ {
+ if (Data_Mul_MaxPacketSize == true)
+ {
+ /* No more data to send and empty packet */
+ Send0LengthData();
+ CtrlState = LastInData;
+ Data_Mul_MaxPacketSize = false;
+ }
+ else
+ {
+ /* No more data to send so STALL the TX Status*/
+ CtrlState = WaitStatusOut;
+ vSetEPTxStatus(EP_TX_STALL);
+ }
+
+ goto Expect_Status_Out;
+ }
+
+ Length = pEPinfo->PacketSize;
+ CtrlState = (save_wLength <= Length) ? LastInData : InData;
+
+ if (Length > save_wLength)
+ {
+ Length = save_wLength;
+ }
+
+ DataBuffer = (*pEPinfo->CopyData)(Length);
+
+ USB_CopyUserToPMABuf(DataBuffer, USB_GetEpTxAddr(ENDP0), Length);
+
+ USB_SetEpTxCnt(ENDP0, Length);
+
+ pEPinfo->Usb_wLength -= Length;
+ pEPinfo->Usb_wOffset += Length;
+ vSetEPTxStatus(EP_TX_VALID);
+
+ USB_StatusOut(); /* Expect the host to abort the data IN stage */
+
+Expect_Status_Out:
+ pInformation->CtrlState = CtrlState;
+}
+
+/**
+ * @brief Proceed the processing of setup request without data stage.
+ */
+void NoData_Setup0(void)
+{
+ USB_Result Result = UnSupport;
+ uint32_t RequestNo = pInformation->bRequest;
+ uint32_t CtrlState;
+
+ if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+ {
+ /* Device Request*/
+ /* SET_CONFIGURATION*/
+ if (RequestNo == SET_CONFIGURATION)
+ {
+ Result = Standard_SetConfiguration();
+ }
+
+ /*SET ADDRESS*/
+ else if (RequestNo == SET_ADDRESS)
+ {
+ if ((pInformation->USBwValue0 > 127) || (pInformation->USBwValue1 != 0) || (pInformation->USBwIndex != 0)
+ || (pInformation->CurrentConfiguration != 0))
+ /* Device Address should be 127 or less*/
+ {
+ CtrlState = Stalled;
+ goto exit_NoData_Setup0;
+ }
+ else
+ {
+ Result = Success;
+ }
+ }
+ /*SET FEATURE for Device*/
+ else if (RequestNo == SET_FEATURE)
+ {
+ if ((pInformation->USBwValue0 == DEVICE_REMOTE_WAKEUP) && (pInformation->USBwIndex == 0))
+ {
+ Result = Standard_SetDeviceFeature();
+ }
+ else
+ {
+ Result = UnSupport;
+ }
+ }
+ /*Clear FEATURE for Device */
+ else if (RequestNo == CLR_FEATURE)
+ {
+ if (pInformation->USBwValue0 == DEVICE_REMOTE_WAKEUP && pInformation->USBwIndex == 0
+ && ValBit(pInformation->CurrentFeature, 5))
+ {
+ Result = Standard_ClearFeature();
+ }
+ else
+ {
+ Result = UnSupport;
+ }
+ }
+ }
+
+ /* Interface Request*/
+ else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
+ {
+ /*SET INTERFACE*/
+ if (RequestNo == SET_INTERFACE)
+ {
+ Result = Standard_SetInterface();
+ }
+ }
+
+ /* EndPoint Request*/
+ else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+ {
+ /*CLEAR FEATURE for EndPoint*/
+ if (RequestNo == CLR_FEATURE)
+ {
+ Result = Standard_ClearFeature();
+ }
+ /* SET FEATURE for EndPoint*/
+ else if (RequestNo == SET_FEATURE)
+ {
+ Result = Standard_SetEndPointFeature();
+ }
+ }
+ else
+ {
+ Result = UnSupport;
+ }
+
+ if (Result != Success)
+ {
+ Result = (*pProperty->Class_NoData_Setup)(RequestNo);
+ if (Result == Not_Ready)
+ {
+ CtrlState = Pause;
+ goto exit_NoData_Setup0;
+ }
+ }
+
+ if (Result != Success)
+ {
+ CtrlState = Stalled;
+ goto exit_NoData_Setup0;
+ }
+
+ CtrlState = WaitStatusIn; /* After no data stage SETUP */
+
+ USB_StatusIn();
+
+exit_NoData_Setup0:
+ pInformation->CtrlState = CtrlState;
+ return;
+}
+
+/**
+ * @brief Proceed the processing of setup request with data stage.
+ */
+void Data_Setup0(void)
+{
+ uint8_t* (*CopyRoutine)(uint16_t);
+ USB_Result Result;
+ uint32_t Request_No = pInformation->bRequest;
+
+ uint32_t Related_Endpoint, Reserved;
+ uint32_t wOffset, Status;
+
+ CopyRoutine = NULL;
+ wOffset = 0;
+
+ /*GET DESCRIPTOR*/
+ if (Request_No == GET_DESCRIPTOR)
+ {
+ if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+ {
+ uint8_t wValue1 = pInformation->USBwValue1;
+ if (wValue1 == DEVICE_DESCRIPTOR)
+ {
+ CopyRoutine = pProperty->GetDeviceDescriptor;
+ }
+ else if (wValue1 == CONFIG_DESCRIPTOR)
+ {
+ CopyRoutine = pProperty->GetConfigDescriptor;
+ }
+ else if (wValue1 == STRING_DESCRIPTOR)
+ {
+ CopyRoutine = pProperty->GetStringDescriptor;
+ } /* End of GET_DESCRIPTOR */
+ }
+ }
+
+ /*GET STATUS*/
+ else if ((Request_No == GET_STATUS) && (pInformation->USBwValue == 0) && (pInformation->USBwLength == 0x0002)
+ && (pInformation->USBwIndex1 == 0))
+ {
+ /* GET STATUS for Device*/
+ if ((Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)) && (pInformation->USBwIndex == 0))
+ {
+ CopyRoutine = Standard_GetStatus;
+ }
+
+ /* GET STATUS for Interface*/
+ else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
+ {
+ if (((*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, 0) == Success)
+ && (pInformation->CurrentConfiguration != 0))
+ {
+ CopyRoutine = Standard_GetStatus;
+ }
+ }
+
+ /* GET STATUS for EndPoint*/
+ else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+ {
+ Related_Endpoint = (pInformation->USBwIndex0 & 0x0f);
+ Reserved = pInformation->USBwIndex0 & 0x70;
+
+ if (ValBit(pInformation->USBwIndex0, 7))
+ {
+ /*Get Status of endpoint & stall the request if the related_ENdpoint
+ is Disabled*/
+ Status = _GetEPTxStatus(Related_Endpoint);
+ }
+ else
+ {
+ Status = _GetEPRxStatus(Related_Endpoint);
+ }
+
+ if ((Related_Endpoint < Device_Table.TotalEndpoint) && (Reserved == 0) && (Status != 0))
+ {
+ CopyRoutine = Standard_GetStatus;
+ }
+ }
+ }
+
+ /*GET CONFIGURATION*/
+ else if (Request_No == GET_CONFIGURATION)
+ {
+ if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+ {
+ CopyRoutine = Standard_GetConfiguration;
+ }
+ }
+ /*GET INTERFACE*/
+ else if (Request_No == GET_INTERFACE)
+ {
+ if ((Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT)) && (pInformation->CurrentConfiguration != 0)
+ && (pInformation->USBwValue == 0) && (pInformation->USBwIndex1 == 0) && (pInformation->USBwLength == 0x0001)
+ && ((*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, 0) == Success))
+ {
+ CopyRoutine = Standard_GetInterface;
+ }
+ }
+
+ if (CopyRoutine)
+ {
+ pInformation->Ctrl_Info.Usb_wOffset = wOffset;
+ pInformation->Ctrl_Info.CopyData = CopyRoutine;
+ /* sb in the original the cast to word was directly */
+ /* now the cast is made step by step */
+ (*CopyRoutine)(0);
+ Result = Success;
+ }
+ else
+ {
+ Result = (*pProperty->Class_Data_Setup)(pInformation->bRequest);
+ if (Result == Not_Ready)
+ {
+ pInformation->CtrlState = Pause;
+ return;
+ }
+ }
+
+ if (pInformation->Ctrl_Info.Usb_wLength == 0xFFFF)
+ {
+ /* Data is not ready, wait it */
+ pInformation->CtrlState = Pause;
+ return;
+ }
+ if ((Result == UnSupport) || (pInformation->Ctrl_Info.Usb_wLength == 0))
+ {
+ /* Unsupported request */
+ pInformation->CtrlState = Stalled;
+ return;
+ }
+
+ if (ValBit(pInformation->bmRequestType, 7))
+ {
+ /* Device ==> Host */
+ __IO uint32_t wLength = pInformation->USBwLength;
+
+ /* Restrict the data length to be the one host asks for */
+ if (pInformation->Ctrl_Info.Usb_wLength > wLength)
+ {
+ pInformation->Ctrl_Info.Usb_wLength = wLength;
+ }
+
+ else if (pInformation->Ctrl_Info.Usb_wLength < pInformation->USBwLength)
+ {
+ if (pInformation->Ctrl_Info.Usb_wLength < pProperty->MaxPacketSize)
+ {
+ Data_Mul_MaxPacketSize = false;
+ }
+ else if ((pInformation->Ctrl_Info.Usb_wLength % pProperty->MaxPacketSize) == 0)
+ {
+ Data_Mul_MaxPacketSize = true;
+ }
+ }
+
+ pInformation->Ctrl_Info.PacketSize = pProperty->MaxPacketSize;
+ DataStageIn();
+ }
+ else
+ {
+ pInformation->CtrlState = OutData;
+ vSetEPRxStatus(EP_RX_VALID); /* enable for next data reception */
+ }
+
+ return;
+}
+
+/**
+ * @brief Get the device request data and dispatch to individual process.
+ * @return USB_ProcessPost0.
+ */
+uint8_t USB_ProcessSetup0(void)
+{
+ union
+ {
+ uint8_t* b;
+ uint16_t* w;
+ } pBuf;
+
+ uint16_t offset = 1;
+
+ pBuf.b = PMAAddr + (uint8_t*)(_GetEPRxAddr(ENDP0) * 2); /* *2 for 32 bits addr */
+
+ if (pInformation->CtrlState != Pause)
+ {
+ pInformation->bmRequestType = *pBuf.b++; /* bmRequestType */
+ pInformation->bRequest = *pBuf.b++; /* bRequest */
+ pBuf.w += offset; /* word not accessed because of 32 bits addressing */
+ pInformation->USBwValue = USB_ByteSwap(*pBuf.w++); /* wValue */
+ pBuf.w += offset; /* word not accessed because of 32 bits addressing */
+ pInformation->USBwIndex = USB_ByteSwap(*pBuf.w++); /* wIndex */
+ pBuf.w += offset; /* word not accessed because of 32 bits addressing */
+ pInformation->USBwLength = *pBuf.w; /* wLength */
+ }
+
+ pInformation->CtrlState = SettingUp;
+ if (pInformation->USBwLength == 0)
+ {
+ /* Setup with no data stage */
+ NoData_Setup0();
+ }
+ else
+ {
+ /* Setup with data stage */
+ Data_Setup0();
+ }
+ return USB_ProcessPost0();
+}
+
+/**
+ * @brief Process the IN token on all default endpoint.
+ * @return USB_ProcessPost0.
+ */
+uint8_t USB_ProcessIn0(void)
+{
+ uint32_t CtrlState = pInformation->CtrlState;
+
+ if ((CtrlState == InData) || (CtrlState == LastInData))
+ {
+ DataStageIn();
+ /* CtrlState may be changed outside the function */
+ CtrlState = pInformation->CtrlState;
+ }
+
+ else if (CtrlState == WaitStatusIn)
+ {
+ if ((pInformation->bRequest == SET_ADDRESS) && (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)))
+ {
+ USB_SetDeviceAddress(pInformation->USBwValue0);
+ pUser_Standard_Requests->User_SetDeviceAddress();
+ }
+ (*pProperty->Process_Status_IN)();
+ CtrlState = Stalled;
+ }
+
+ else
+ {
+ CtrlState = Stalled;
+ }
+
+ pInformation->CtrlState = CtrlState;
+
+ return USB_ProcessPost0();
+}
+
+/**
+ * @brief Process the OUT token on all default endpoint.
+ * @return USB_ProcessPost0.
+ */
+uint8_t USB_ProcessOut0(void)
+{
+ uint32_t CtrlState = pInformation->CtrlState;
+
+ if ((CtrlState == InData) || (CtrlState == LastInData))
+ {
+ /* host aborts the transfer before finish */
+ CtrlState = Stalled;
+ }
+ else if ((CtrlState == OutData) || (CtrlState == LastOutData))
+ {
+ DataStageOut();
+ CtrlState = pInformation->CtrlState; /* may be changed outside the function */
+ }
+
+ else if (CtrlState == WaitStatusOut)
+ {
+ (*pProperty->Process_Status_OUT)();
+ CtrlState = Stalled;
+ }
+
+ /* Unexpect state, STALL the endpoint */
+ else
+ {
+ CtrlState = Stalled;
+ }
+
+ pInformation->CtrlState = CtrlState;
+
+ return USB_ProcessPost0();
+}
+
+/**
+ * @brief Stall the Endpoint 0 in case of error.
+ * @return
+ * - 0 if the control State is in Pause
+ * - 1 if not.
+ */
+uint8_t USB_ProcessPost0(void)
+{
+ USB_SetEpRxCnt(ENDP0, Device_Property.MaxPacketSize);
+
+ if (pInformation->CtrlState == Stalled)
+ {
+ vSetEPRxStatus(EP_RX_STALL);
+ vSetEPTxStatus(EP_TX_STALL);
+ }
+ return (pInformation->CtrlState == Pause);
+}
+
+/**
+ * @brief Set the device and all the used Endpoints addresses.
+ * @param Val device address.
+ */
+void USB_SetDeviceAddress(uint8_t Val)
+{
+ uint32_t i;
+ uint32_t nEP = Device_Table.TotalEndpoint;
+
+ /* set address in every used endpoint */
+ for (i = 0; i < nEP; i++)
+ {
+ _SetEPAddress((uint8_t)i, (uint8_t)i);
+ } /* for */
+ _SetDADDR(Val | ADDR_EFUC); /* set device address and enable function */
+}
+
+/**
+ * @brief No operation function.
+ */
+void USB_ProcessNop(void)
+{
+}
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_init.c b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_init.c
new file mode 100644
index 0000000000..1b5bc416af
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_init.c
@@ -0,0 +1,71 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_init.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "usb_lib.h"
+
+/* The number of current endpoint, it will be used to specify an endpoint */
+uint8_t EPindex;
+/* The number of current device, it is an index to the Device_Table */
+/* uint8_t Device_no; */
+/* Points to the USB_DeviceMess structure of current device */
+/* The purpose of this register is to speed up the execution */
+USB_DeviceMess* pInformation;
+/* Points to the DEVICE_PROP structure of current device */
+/* The purpose of this register is to speed up the execution */
+DEVICE_PROP* pProperty;
+/* Temporary save the state of Rx & Tx status. */
+/* Whenever the Rx or Tx state is changed, its value is saved */
+/* in this variable first and will be set to the EPRB or EPRA */
+/* at the end of interrupt process */
+uint16_t SaveState;
+uint16_t wInterrupt_Mask;
+USB_DeviceMess Device_Info;
+USER_STANDARD_REQUESTS* pUser_Standard_Requests;
+
+/**
+ * @brief USB system initialization
+ */
+void USB_Init(void)
+{
+ pInformation = &Device_Info;
+ pInformation->CtrlState = 2;
+ pProperty = &Device_Property;
+ pUser_Standard_Requests = &User_Standard_Requests;
+ /* Initialize devices one by one */
+ pProperty->Init();
+ /*Pull up DP*/
+// _ClrDPCtrl();
+ _EnPortPullup();
+// printf("DP_CTRL=%x\r\n", (*DP_CTRL));
+}
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_int.c b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_int.c
new file mode 100644
index 0000000000..933ed45f29
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_int.c
@@ -0,0 +1,179 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_int.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "usb_lib.h"
+
+__IO uint16_t SaveRState;
+__IO uint16_t SaveTState;
+
+extern void (*pEpInt_IN[7])(void); /* Handles IN interrupts */
+extern void (*pEpInt_OUT[7])(void); /* Handles OUT interrupts */
+
+/**
+ * @brief Low priority Endpoint Correct Transfer interrupt's service routine.
+ */
+void USB_CorrectTransferLp(void)
+{
+ __IO uint16_t wEPVal = 0;
+ /* stay in loop while pending interrupts */
+ while (((wIstr = _GetISTR()) & STS_CTRS) != 0)
+ {
+ /* extract highest priority endpoint number */
+ EPindex = (uint8_t)(wIstr & STS_EP_ID);
+ if (EPindex == 0)
+ {
+ /* Decode and service control endpoint interrupt */
+ /* calling related service routine */
+ /* (USB_ProcessSetup0, USB_ProcessIn0, USB_ProcessOut0) */
+
+ /* save RX & TX status */
+ /* and set both to NAK */
+
+ SaveRState = _GetENDPOINT(ENDP0);
+ SaveTState = SaveRState & EPTX_STS;
+ SaveRState &= EPRX_STS;
+ _SetEPRxTxStatus(ENDP0, EP_RX_NAK, EP_TX_NAK);
+
+ /* DIR bit = origin of the interrupt */
+
+ if ((wIstr & STS_DIR) == 0)
+ {
+ /* DIR = 0 */
+
+ /* DIR = 0 => IN int */
+ /* DIR = 0 implies that (EP_CTRS_TX = 1) always */
+
+ _ClearEP_CTR_TX(ENDP0);
+ USB_ProcessIn0();
+
+ /* before terminate set Tx & Rx status */
+
+ _SetEPRxTxStatus(ENDP0, SaveRState, SaveTState);
+ return;
+ }
+ else
+ {
+ /* DIR = 1 */
+
+ /* DIR = 1 & CTR_RX => SETUP or OUT int */
+ /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
+
+ wEPVal = _GetENDPOINT(ENDP0);
+
+ if ((wEPVal & EP_SETUP) != 0)
+ {
+ _ClearEP_CTR_RX(ENDP0); /* SETUP bit kept frozen while CTR_RX = 1 */
+ USB_ProcessSetup0();
+ /* before terminate set Tx & Rx status */
+
+ _SetEPRxTxStatus(ENDP0, SaveRState, SaveTState);
+ return;
+ }
+
+ else if ((wEPVal & EP_CTRS_RX) != 0)
+ {
+ _ClearEP_CTR_RX(ENDP0);
+ USB_ProcessOut0();
+ /* before terminate set Tx & Rx status */
+
+ _SetEPRxTxStatus(ENDP0, SaveRState, SaveTState);
+ return;
+ }
+ }
+ } /* if (EPindex == 0) */
+ else
+ {
+ /* Decode and service non control endpoints interrupt */
+
+ /* process related endpoint register */
+ wEPVal = _GetENDPOINT(EPindex);
+ if ((wEPVal & EP_CTRS_RX) != 0)
+ {
+ /* clear int flag */
+ _ClearEP_CTR_RX(EPindex);
+
+ /* call OUT service function */
+ (*pEpInt_OUT[EPindex - 1])();
+
+ } /* if ((wEPVal & EP_CTRS_RX) */
+
+ if ((wEPVal & EP_CTRS_TX) != 0)
+ {
+ /* clear int flag */
+ _ClearEP_CTR_TX(EPindex);
+
+ /* call IN service function */
+ (*pEpInt_IN[EPindex - 1])();
+ } /* if ((wEPVal & EP_CTRS_TX) != 0) */
+
+ } /* if (EPindex == 0) else */
+
+ } /* while (...) */
+}
+
+/**
+ * @brief High Priority Endpoint Correct Transfer interrupt's service routine.
+ */
+void USB_CorrectTransferHp(void)
+{
+ uint32_t wEPVal = 0;
+
+ while (((wIstr = _GetISTR()) & STS_CTRS) != 0)
+ {
+ _SetISTR((uint16_t)CLR_CTRS); /* clear CTR flag */
+ /* extract highest priority endpoint number */
+ EPindex = (uint8_t)(wIstr & STS_EP_ID);
+ /* process related endpoint register */
+ wEPVal = _GetENDPOINT(EPindex);
+ if ((wEPVal & EP_CTRS_RX) != 0)
+ {
+ /* clear int flag */
+ _ClearEP_CTR_RX(EPindex);
+
+ /* call OUT service function */
+ (*pEpInt_OUT[EPindex - 1])();
+
+ } /* if ((wEPVal & EP_CTRS_RX) */
+ else if ((wEPVal & EP_CTRS_TX) != 0)
+ {
+ /* clear int flag */
+ _ClearEP_CTR_TX(EPindex);
+
+ /* call IN service function */
+ (*pEpInt_IN[EPindex - 1])();
+
+ } /* if ((wEPVal & EP_CTRS_TX) != 0) */
+
+ } /* while (...) */
+}
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_mem.c b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_mem.c
new file mode 100644
index 0000000000..02768e0307
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_mem.c
@@ -0,0 +1,81 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_mem.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "usb_lib.h"
+u8* EpOutDataPtrTmp;
+u8* EpInDataPtrTmp;
+
+/**
+ * @brief Copy a buffer from user memory area to packet memory area (PMA)
+ * @param pbUsrBuf pointer to user memory area.
+ * @param wPMABufAddr address into PMA.
+ * @param wNBytes no. of bytes to be copied.
+ */
+void USB_CopyUserToPMABuf(uint8_t* pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+ uint32_t n = (wNBytes + 1) >> 1; /* n = (wNBytes + 1) / 2 */
+ uint32_t i, temp1, temp2;
+ uint16_t* pdwVal;
+ pdwVal = (uint16_t*)(wPMABufAddr * 2 + PMAAddr);
+ for (i = n; i != 0; i--)
+ {
+ temp1 = (uint16_t)*pbUsrBuf;
+ pbUsrBuf++;
+ temp2 = temp1 | (uint16_t)*pbUsrBuf << 8;
+ *pdwVal++ = temp2;
+ pdwVal++;
+ pbUsrBuf++;
+ EpInDataPtrTmp = pbUsrBuf;
+ }
+}
+
+/**
+ * @brief Copy a buffer from user memory area to packet memory area (PMA)
+ * @param pbUsrBuf pointer to user memory area.
+ * @param wPMABufAddr address into PMA.
+ * @param wNBytes no. of bytes to be copied.
+ */
+void USB_CopyPMAToUserBuf(uint8_t* pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+ uint32_t n = (wNBytes + 1) >> 1; /* /2*/
+ uint32_t i;
+ uint32_t* pdwVal;
+ pdwVal = (uint32_t*)(wPMABufAddr * 2 + PMAAddr);
+ for (i = n; i != 0; i--)
+ {
+ *(uint16_t*)pbUsrBuf++ = *pdwVal++;
+ pbUsrBuf++;
+ EpOutDataPtrTmp = pbUsrBuf;
+ }
+}
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_regs.c b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_regs.c
new file mode 100644
index 0000000000..457eef62b1
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_regs.c
@@ -0,0 +1,598 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_regs.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "usb_lib.h"
+
+/**
+ * @brief Set the CTRL register value.
+ * @param wRegValue new register value.
+ */
+void USB_SetCtrl(uint16_t wRegValue)
+{
+ _SetCNTR(wRegValue);
+}
+
+/**
+ * @brief returns the CTRL register value.
+ * @return CTRL register Value.
+ */
+uint16_t USB_GetCtrl(void)
+{
+ return (_GetCNTR());
+}
+
+/**
+ * @brief Set the STS register value.
+ * @param wRegValue new register value.
+ */
+void USB_SetSts(uint16_t wRegValue)
+{
+ _SetISTR(wRegValue);
+}
+
+/**
+ * @brief Returns the STS register value.
+ * @return STS register Value
+ */
+uint16_t USB_GetSts(void)
+{
+ return (_GetISTR());
+}
+
+/**
+ * @brief Returns the FN register value.
+ * @return FN register Value
+ */
+uint16_t USB_GetFn(void)
+{
+ return (_GetFNR());
+}
+
+/**
+ * @brief Set the ADDR register value.
+ * @param wRegValue new register value.
+ */
+void USB_SetAddr(uint16_t wRegValue)
+{
+ _SetDADDR(wRegValue);
+}
+
+/**
+ * @brief Returns the ADDR register value.
+ * @return ADDR register Value
+ */
+uint16_t USB_GetAddr(void)
+{
+ return (_GetDADDR());
+}
+
+/**
+ * @brief Set the BUFTAB.
+ * @param wRegValue New register value.
+ */
+void USB_SetBuftab(uint16_t wRegValue)
+{
+ _SetBTABLE(wRegValue);
+}
+
+/**
+ * @brief Returns the BUFTAB register value.
+ * @return BUFTAB address.
+ */
+uint16_t USB_GetBTABLE(void)
+{
+ return (_GetBTABLE());
+}
+
+/**
+ * @brief Set the Endpoint register value.
+ * @param bEpNum Endpoint Number.
+ * @param wRegValue New register value.
+ */
+void USB_SetEndPoint(uint8_t bEpNum, uint16_t wRegValue)
+{
+ _SetENDPOINT(bEpNum, wRegValue);
+}
+
+/**
+ * @brief Return the Endpoint register value.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint register value.
+ */
+uint16_t USB_GetEndPoint(uint8_t bEpNum)
+{
+ return (_GetENDPOINT(bEpNum));
+}
+
+/**
+ * @brief sets the type in the endpoint register.
+ * @param bEpNum Endpoint Number.
+ * @param wType type definition.
+ */
+void USB_SetEpType(uint8_t bEpNum, uint16_t wType)
+{
+ _SetEPType(bEpNum, wType);
+}
+
+/**
+ * @brief Returns the endpoint type.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint Type
+ */
+uint16_t USB_GetEpType(uint8_t bEpNum)
+{
+ return (_GetEPType(bEpNum));
+}
+
+/**
+ * @brief Set the status of Tx endpoint.
+ * @param bEpNum Endpoint Number.
+ * @param wState new state.
+ */
+void SetEPTxStatus(uint8_t bEpNum, uint16_t wState)
+{
+ _SetEPTxStatus(bEpNum, wState);
+}
+
+/**
+ * @brief Set the status of Rx endpoint.
+ * @param bEpNum Endpoint Number.
+ * @param wState new state.
+ */
+void SetEPRxStatus(uint8_t bEpNum, uint16_t wState)
+{
+ _SetEPRxStatus(bEpNum, wState);
+}
+
+/**
+ * @brief sets the status for Double Buffer Endpoint to STALL
+ * @param bEpNum Endpoint Number.
+ * @param bDir Endpoint direction.
+ */
+void USB_SetDouBleBuferEpStall(uint8_t bEpNum, uint8_t bDir)
+{
+ uint16_t Endpoint_DTOG_Status;
+ Endpoint_DTOG_Status = USB_GetEndPoint(bEpNum);
+ if (bDir == EP_DBUF_OUT)
+ { /* OUT double buffered endpoint */
+ _SetENDPOINT(bEpNum, Endpoint_DTOG_Status & ~EPRX_DATTOG1);
+ }
+ else if (bDir == EP_DBUF_IN)
+ { /* IN double buffered endpoint */
+ _SetENDPOINT(bEpNum, Endpoint_DTOG_Status & ~EPTX_DATTOG1);
+ }
+}
+
+/**
+ * @brief Returns the endpoint Tx status.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint TX Status
+ */
+uint16_t USB_GetEpTxSts(uint8_t bEpNum)
+{
+ return (_GetEPTxStatus(bEpNum));
+}
+
+/**
+ * @brief Returns the endpoint Rx status.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint RX Status
+ */
+uint16_t USB_GetEpRxSts(uint8_t bEpNum)
+{
+ return (_GetEPRxStatus(bEpNum));
+}
+
+/**
+ * @brief Valid the endpoint Tx Status.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_SetEpTxValid(uint8_t bEpNum)
+{
+ _SetEPTxStatus(bEpNum, EP_TX_VALID);
+}
+
+/**
+ * @brief Valid the endpoint Rx Status.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_SetEpRxValid(uint8_t bEpNum)
+{
+ _SetEPRxStatus(bEpNum, EP_RX_VALID);
+}
+
+/**
+ * @brief Clear the EP_KIND bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_SetEpKind(uint8_t bEpNum)
+{
+ _SetEP_KIND(bEpNum);
+}
+
+/**
+ * @brief set the EP_KIND bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrEpKind(uint8_t bEpNum)
+{
+ _ClearEP_KIND(bEpNum);
+}
+/**
+ * @brief Clear the Status Out of the related Endpoint
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrStsOut(uint8_t bEpNum)
+{
+ _ClearEP_KIND(bEpNum);
+}
+/**
+ * @brief Set the Status Out of the related Endpoint
+ * @param bEpNum Endpoint Number.
+ */
+void USB_SetStsOut(uint8_t bEpNum)
+{
+ _SetEP_KIND(bEpNum);
+}
+/**
+ * @brief Enable the double buffer feature for the endpoint.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_SetEpDoubleBufer(uint8_t bEpNum)
+{
+ _SetEP_KIND(bEpNum);
+}
+/**
+ * @brief Disable the double buffer feature for the endpoint.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrEpDoubleBufer(uint8_t bEpNum)
+{
+ _ClearEP_KIND(bEpNum);
+}
+/**
+ * @brief Returns the Stall status of the Tx endpoint.
+ * @param bEpNum Endpoint Number.
+ * @return Tx Stall status.
+ */
+uint16_t USB_GetTxStallSts(uint8_t bEpNum)
+{
+ return (_GetTxStallStatus(bEpNum));
+}
+/**
+ * @brief Returns the Stall status of the Rx endpoint.
+ * @param bEpNum Endpoint Number.
+ * @return Rx Stall status.
+ */
+uint16_t USB_GetRxStallSts(uint8_t bEpNum)
+{
+ return (_GetRxStallStatus(bEpNum));
+}
+/**
+ * @brief Clear the CTR_RX bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrEpCtrsRx(uint8_t bEpNum)
+{
+ _ClearEP_CTR_RX(bEpNum);
+}
+/**
+ * @brief Clear the CTR_TX bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrEpCtrsTx(uint8_t bEpNum)
+{
+ _ClearEP_CTR_TX(bEpNum);
+}
+/**
+ * @brief Toggle the DTOG_RX bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_DattogRx(uint8_t bEpNum)
+{
+ _ToggleDTOG_RX(bEpNum);
+}
+/**
+ * @brief Toggle the DTOG_TX bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_DattogTx(uint8_t bEpNum)
+{
+ _ToggleDTOG_TX(bEpNum);
+}
+/**
+ * @brief Clear the DTOG_RX bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrDattogRx(uint8_t bEpNum)
+{
+ _ClearDTOG_RX(bEpNum);
+}
+/**
+ * @brief Clear the DTOG_TX bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrDattogTx(uint8_t bEpNum)
+{
+ _ClearDTOG_TX(bEpNum);
+}
+/**
+ * @brief Set the endpoint address.
+ * @param bEpNum Endpoint Number.
+ * @param bAddr New endpoint address.
+ */
+void USB_SetEpAddress(uint8_t bEpNum, uint8_t bAddr)
+{
+ _SetEPAddress(bEpNum, bAddr);
+}
+/**
+ * @brief Get the endpoint address.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint address.
+ */
+uint8_t USB_GetEpAddress(uint8_t bEpNum)
+{
+ return (_GetEPAddress(bEpNum));
+}
+/**
+ * @brief Set the endpoint Tx buffer address.
+ * @param bEpNum Endpoint Number.
+ * @param wAddr new address.
+ */
+void USB_SetEpTxAddr(uint8_t bEpNum, uint16_t wAddr)
+{
+ _SetEPTxAddr(bEpNum, wAddr);
+}
+/**
+ * @brief Set the endpoint Rx buffer address.
+ * @param bEpNum Endpoint Number.
+ * @param wAddr new address.
+ */
+void USB_SetEpRxAddr(uint8_t bEpNum, uint16_t wAddr)
+{
+ _SetEPRxAddr(bEpNum, wAddr);
+}
+/**
+ * @brief Returns the endpoint Tx buffer address.
+ * @param bEpNum Endpoint Number.
+ * @return Rx buffer address.
+ */
+uint16_t USB_GetEpTxAddr(uint8_t bEpNum)
+{
+ return (_GetEPTxAddr(bEpNum));
+}
+/**
+ * @brief Returns the endpoint Rx buffer address.
+ * @param bEpNum Endpoint Number.
+ * @return Rx buffer address.
+ */
+uint16_t USB_GetEpRxAddr(uint8_t bEpNum)
+{
+ return (_GetEPRxAddr(bEpNum));
+}
+/**
+ * @brief Set the Tx count.
+ * @param bEpNum Endpoint Number.
+ * @param wCount new count value.
+ */
+void USB_SetEpTxCnt(uint8_t bEpNum, uint16_t wCount)
+{
+ _SetEPTxCount(bEpNum, wCount);
+}
+/**
+ * @brief Set the Count Rx Register value.
+ * @param pdwReg point to the register.
+ * @param wCount the new register value.
+ */
+void USB_SetEpCntRxReg(uint32_t* pdwReg, uint16_t wCount)
+{
+ _SetEPCountRxReg(dwReg, wCount);
+}
+/**
+ * @brief Set the Rx count.
+ * @param bEpNum Endpoint Number.
+ * @param wCount the new count value.
+ */
+void USB_SetEpRxCnt(uint8_t bEpNum, uint16_t wCount)
+{
+ _SetEPRxCount(bEpNum, wCount);
+}
+/**
+ * @brief Get the Tx count.
+ * @param bEpNum Endpoint Number.
+ * @return Tx count value.
+ */
+uint16_t USB_GetEpTxCnt(uint8_t bEpNum)
+{
+ return (_GetEPTxCount(bEpNum));
+}
+/**
+ * @brief Get the Rx count.
+ * @param bEpNum Endpoint Number.
+ * @return Rx count value.
+ */
+uint16_t USB_GetEpRxCnt(uint8_t bEpNum)
+{
+ return (_GetEPRxCount(bEpNum));
+}
+/**
+ * @brief Set the addresses of the buffer 0 and 1.
+ * @param bEpNum Endpoint Number.
+ * @param wBuf0Addr new address of buffer 0.
+ * @param wBuf1Addr new address of buffer 1.
+ */
+void USB_SetEpDblBuferAddr(uint8_t bEpNum, uint16_t wBuf0Addr, uint16_t wBuf1Addr)
+{
+ _SetEPDblBuffAddr(bEpNum, wBuf0Addr, wBuf1Addr);
+}
+/**
+ * @brief Set the Buffer 1 address.
+ * @param bEpNum Endpoint Number
+ * @param wBuf0Addr new address.
+ */
+void USB_SetEpDblBuf0Addr(uint8_t bEpNum, uint16_t wBuf0Addr)
+{
+ _SetEPDblBuf0Addr(bEpNum, wBuf0Addr);
+}
+/**
+ * @brief Set the Buffer 1 address.
+ * @param bEpNum Endpoint Number
+ * @param wBuf1Addr new address.
+ */
+void USB_SetEpDblBuf1Addr(uint8_t bEpNum, uint16_t wBuf1Addr)
+{
+ _SetEPDblBuf1Addr(bEpNum, wBuf1Addr);
+}
+/**
+ * @brief Returns the address of the Buffer 0.
+ * @param bEpNum Endpoint Number.
+ */
+uint16_t USB_GetEpDblBuf0Addr(uint8_t bEpNum)
+{
+ return (_GetEPDblBuf0Addr(bEpNum));
+}
+/**
+ * @brief Returns the address of the Buffer 1.
+ * @param bEpNum Endpoint Number.
+ * @return Address of the Buffer 1.
+ */
+uint16_t USB_GetEpDblBuf1Addr(uint8_t bEpNum)
+{
+ return (_GetEPDblBuf1Addr(bEpNum));
+}
+/**
+ * @brief Set the number of bytes for a double Buffer endpoint.
+ * @param bEpNum
+ * @param bDir
+ * @param wCount
+ */
+void USB_SetEpDblBuferCnt(uint8_t bEpNum, uint8_t bDir, uint16_t wCount)
+{
+ _SetEPDblBuffCount(bEpNum, bDir, wCount);
+}
+/**
+ * @brief Set the number of bytes in the buffer 0 of a double Buffer endpoint.
+ * @param bEpNum
+ * @param bDir
+ * @param wCount
+ */
+void USB_SetEpDblBuf0Cnt(uint8_t bEpNum, uint8_t bDir, uint16_t wCount)
+{
+ _SetEPDblBuf0Count(bEpNum, bDir, wCount);
+}
+/**
+ * @brief Set the number of bytes in the buffer 0 of a double Buffer endpoint.
+ * @param bEpNum
+ * @param bDir
+ * @param wCount
+ */
+void USB_SetEpDblBuf1Cnt(uint8_t bEpNum, uint8_t bDir, uint16_t wCount)
+{
+ _SetEPDblBuf1Count(bEpNum, bDir, wCount);
+}
+/**
+ * @brief Returns the number of byte received in the buffer 0 of a double Buffer endpoint.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint Buffer 0 count
+ */
+uint16_t USB_GetEpDblBuf0Cnt(uint8_t bEpNum)
+{
+ return (_GetEPDblBuf0Count(bEpNum));
+}
+/**
+ * @brief Returns the number of data received in the buffer 1 of a double Buffer endpoint.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint Buffer 1 count.
+ */
+uint16_t USB_GetEpDblBuf1Cnt(uint8_t bEpNum)
+{
+ return (_GetEPDblBuf1Count(bEpNum));
+}
+/**
+ * @brief gets direction of the double buffered endpoint
+ * @param bEpNum Endpoint Number.
+ * @return EP_DBUF_OUT, EP_DBUF_IN, EP_DBUF_ERR if the endpoint counter not yet programmed.
+ */
+EP_DBUF_DIR GetEPDblBufDir(uint8_t bEpNum)
+{
+ if ((uint16_t)(*_pEPRxCount(bEpNum) & 0xFC00) != 0)
+ return (EP_DBUF_OUT);
+ else if (((uint16_t)(*_pEPTxCount(bEpNum)) & 0x03FF) != 0)
+ return (EP_DBUF_IN);
+ else
+ return (EP_DBUF_ERR);
+}
+/**
+ * @brief free buffer used from the application realizing it to the line toggles
+ * bit SW_BUF in the double buffered endpoint register
+ * @param bEpNum
+ * @param bDir
+ */
+void USB_FreeUserBuf(uint8_t bEpNum, uint8_t bDir)
+{
+ if (bDir == EP_DBUF_OUT)
+ { /* OUT double buffered endpoint */
+ _ToggleDTOG_TX(bEpNum);
+ }
+ else if (bDir == EP_DBUF_IN)
+ { /* IN double buffered endpoint */
+ _ToggleDTOG_RX(bEpNum);
+ }
+}
+
+/**
+ * @brief merge two byte in a word.
+ * @param bh byte high
+ * @param bl bytes low.
+ * @return resulted word.
+ */
+uint16_t USB_ToWord(uint8_t bh, uint8_t bl)
+{
+ uint16_t wRet;
+ wRet = (uint16_t)bl | ((uint16_t)bh << 8);
+ return (wRet);
+}
+/**
+ * @brief Swap two byte in a word.
+ * @param wSwW word to Swap.
+ * @return resulted word.
+ */
+uint16_t USB_ByteSwap(uint16_t wSwW)
+{
+ uint8_t bTemp;
+ uint16_t wRet;
+ bTemp = (uint8_t)(wSwW & 0xff);
+ wRet = (wSwW >> 8) | ((uint16_t)bTemp << 8);
+ return (wRet);
+}
diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_sil.c b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_sil.c
new file mode 100644
index 0000000000..0cea2761dd
--- /dev/null
+++ b/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_sil.c
@@ -0,0 +1,83 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_sil.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "usb_lib.h"
+
+/**
+ * @brief Initialize the USB Device IP and the Endpoint 0.
+ * @return Status.
+ */
+uint32_t USB_SilInit(void)
+{
+ /* USB interrupts initialization */
+ /* clear pending interrupts */
+ _SetISTR(0);
+ wInterrupt_Mask = IMR_MSK;
+ /* set interrupts mask */
+ _SetCNTR(wInterrupt_Mask);
+ return 0;
+}
+
+/**
+ * @brief Write a buffer of data to a selected endpoint.
+ * @param bEpAddr The address of the non control endpoint.
+ * @param pBufferPointer The pointer to the buffer of data to be written to the endpoint.
+ * @param wBufferSize Number of data to be written (in bytes).
+ * @return Status.
+ */
+uint32_t USB_SilWrite(uint8_t bEpAddr, uint8_t* pBufferPointer, uint32_t wBufferSize)
+{
+ /* Use the memory interface function to write to the selected endpoint */
+ USB_CopyUserToPMABuf(pBufferPointer, USB_GetEpTxAddr(bEpAddr & 0x7F), wBufferSize);
+ /* Update the data length in the control register */
+ USB_SetEpTxCnt((bEpAddr & 0x7F), wBufferSize);
+ return 0;
+}
+
+/**
+ * @brief Write a buffer of data to a selected endpoint.
+ * @param bEpAddr The address of the non control endpoint.
+ * @param pBufferPointer The pointer to which will be saved the received data buffer.
+ * @return Number of received data (in Bytes).
+ */
+uint32_t USB_SilRead(uint8_t bEpAddr, uint8_t* pBufferPointer)
+{
+ uint32_t DataLength = 0;
+ /* Get the number of received data on the selected Endpoint */
+ DataLength = USB_GetEpRxCnt(bEpAddr & 0x7F);
+ /* Use the memory interface function to write to the selected endpoint */
+ USB_CopyPMAToUserBuf(pBufferPointer, USB_GetEpRxAddr(bEpAddr & 0x7F), DataLength);
+ /* Return the number of received data */
+ return DataLength;
+}
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/arm_common_tables.h b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/arm_common_tables.h
new file mode 100644
index 0000000000..68884992bd
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/arm_common_tables.h
@@ -0,0 +1,121 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_common_tables.h
+ * Description: Extern declaration for common tables
+ *
+ * $Date: 09. August 2022
+ * $Revision: V.1.2.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
+#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
+#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
+#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
+#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
+#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
+#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
+#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /* ARM_COMMON_TABLES_H */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/arm_const_structs.h b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/arm_const_structs.h
new file mode 100644
index 0000000000..51accc6964
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/arm_const_structs.h
@@ -0,0 +1,66 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_const_structs.h
+ * Description: Constant structs that are initialized for user convenience.
+ * For example, some can be given as arguments to the arm_cfft_f32() function.
+ *
+ * $Date: 09. August 2022
+ * $Revision: V.1.2.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/arm_math.h b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/arm_math.h
new file mode 100644
index 0000000000..4b69c6c888
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/arm_math.h
@@ -0,0 +1,7157 @@
+/******************************************************************************
+ * @file arm_math.h
+ * @brief Public header file for CMSIS DSP LibraryU
+ * @version V1.2.0
+ * @date 09. August 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ \mainpage CMSIS DSP Software Library
+ *
+ * Introduction
+ * ------------
+ *
+ * This user manual describes the CMSIS DSP software library,
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.
+ *
+ * The library is divided into a number of functions each covering a specific category:
+ * - Basic math functions
+ * - Fast math functions
+ * - Complex math functions
+ * - Filters
+ * - Matrix functions
+ * - Transforms
+ * - Motor control functions
+ * - Statistical functions
+ * - Support functions
+ * - Interpolation functions
+ *
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+ * 32-bit integer and 32-bit floating-point values.
+ *
+ * Using the Library
+ * ------------
+ *
+ * The library installer contains prebuilt versions of the libraries in the Lib folder.
+ * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)
+ * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)
+ * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)
+ * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)
+ * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)
+ * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)
+ * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)
+ * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)
+ * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)
+ * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)
+ * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)
+ * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)
+ * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)
+ * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)
+ * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian)
+ * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian)
+ * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit)
+ * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions)
+ * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
+ *
+ * The library functions are declared in the public file arm_math.h which is placed in the Include folder.
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+ * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+ * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or
+ * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+ * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
+ * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions.
+ *
+ *
+ * Examples
+ * --------
+ *
+ * The library ships with a number of examples which demonstrate how to use the library functions.
+ *
+ * Toolchain Support
+ * ------------
+ *
+ * The library has been developed and tested with MDK version 5.14.0.0
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+ *
+ * Building the Library
+ * ------------
+ *
+ * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP_Lib\\Source\\ARM folder.
+ * - arm_cortexM_math.uvprojx
+ *
+ *
+ * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above.
+ *
+ * Preprocessor Macros
+ * ------------
+ *
+ * Each library project have different preprocessor macros.
+ *
+ * - UNALIGNED_SUPPORT_DISABLE:
+ *
+ * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+ *
+ * - ARM_MATH_BIG_ENDIAN:
+ *
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+ *
+ * - ARM_MATH_MATRIX_CHECK:
+ *
+ * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+ *
+ * - ARM_MATH_ROUNDING:
+ *
+ * Define macro ARM_MATH_ROUNDING for rounding on support functions
+ *
+ * - ARM_MATH_CMx:
+ *
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+ * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+ * ARM_MATH_CM7 for building the library on cortex-M7.
+ *
+ * - ARM_MATH_ARMV8MxL:
+ *
+ * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library
+ * on Armv8-M Mainline target.
+ *
+ * - __FPU_PRESENT:
+ *
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries.
+ *
+ * - __DSP_PRESENT:
+ *
+ * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions.
+ *
+ *
+ * CMSIS-DSP in ARM::CMSIS Pack
+ * -----------------------------
+ *
+ * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories:
+ * |File/Folder |Content |
+ * |------------------------------|------------------------------------------------------------------------|
+ * |\b CMSIS\\Documentation\\DSP | This documentation |
+ * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) |
+ * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions |
+ * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library |
+ *
+ *
+ * Revision History of CMSIS-DSP
+ * ------------
+ * Please refer to \ref ChangeLog_pg.
+ *
+ * Copyright Notice
+ * ------------
+ *
+ * Copyright (C) 2010-2015 Arm Limited. All rights reserved.
+ */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures. For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ *
+ * typedef struct
+ * {
+ * uint16_t numRows; // number of rows of the matrix.
+ * uint16_t numCols; // number of columns of the matrix.
+ * float32_t *pData; // points to the data of the matrix.
+ * } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data. The array is of size numRows X numCols
+ * and the values are arranged in row order. That is, the
+ * matrix element (i, j) is stored at:
+ *
+ * pData[i*numCols + j]
+ *
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function arm_mat_init_f32(), arm_mat_init_q31()
+ * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure. For example:
+ *
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns
+ * specifies the number of columns, and pData points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices. For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns. If the size check fails the functions return:
+ *
+ * ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return
+ *
+ * ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ *
+ * ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined
+ * and size checking is enabled. By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster. With size checking disabled the functions always
+ * return ARM_MATH_SUCCESS.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+/* Compiler specific diagnostic adjustment */
+#if defined ( __CC_ARM )
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+#elif defined ( __ICCARM__ )
+
+#elif defined ( __TI_ARM__ )
+
+#elif defined ( __CSMC__ )
+
+#elif defined ( __TASKING__ )
+
+#else
+ #error Unknown compiler
+#endif
+
+
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+ #include "core_cm7.h"
+ #define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM4)
+ #include "core_cm4.h"
+ #define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM3)
+ #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+ #include "core_cm0.h"
+ #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+ #include "core_cm0plus.h"
+ #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MBL)
+ #include "core_armv8mbl.h"
+ #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MML)
+ #include "core_armv8mml.h"
+ #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1))
+ #define ARM_MATH_DSP
+ #endif
+#else
+ #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML"
+#endif
+
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+ /**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31 (0x100)
+#define DELTA_Q15 0x5
+#define INDEX_MASK 0x0000003F
+#ifndef PI
+ #define PI 3.14159265358979f
+#endif
+
+ /**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define FAST_MATH_TABLE_SIZE 512
+#define FAST_MATH_Q31_SHIFT (32 - 10)
+#define FAST_MATH_Q15_SHIFT (16 - 10)
+#define CONTROLLER_Q31_SHIFT (32 - 9)
+#define TABLE_SPACING_Q31 0x400000
+#define TABLE_SPACING_Q15 0x80
+
+ /**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+ /* 1.31(q31) Fixed value of 2/360 */
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING 0xB60B61
+
+ /**
+ * @brief Macro for Unaligned Support
+ */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+ #define ALIGN4
+#else
+ #if defined (__GNUC__)
+ #define ALIGN4 __attribute__((aligned(4)))
+ #else
+ #define ALIGN4 __align(4)
+ #endif
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /**
+ * @brief Error status returned by some functions in the library.
+ */
+
+ typedef enum
+ {
+ ARM_MATH_SUCCESS = 0, /**< No error */
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
+ } arm_status;
+
+ /**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+ typedef int8_t q7_t;
+
+ /**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+ typedef int16_t q15_t;
+
+ /**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+ typedef int32_t q31_t;
+
+ /**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+ typedef int64_t q63_t;
+
+ /**
+ * @brief 32-bit floating-point type definition.
+ */
+ typedef float float32_t;
+
+ /**
+ * @brief 64-bit floating-point type definition.
+ */
+ typedef double float64_t;
+
+ /**
+ * @brief definition to read/write two 16 bit values.
+ */
+#if defined ( __CC_ARM )
+ #define __SIMD32_TYPE int32_t __packed
+ #define CMSIS_UNUSED __attribute__((unused))
+ #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED __attribute__((unused))
+ #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __GNUC__ )
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED __attribute__((unused))
+ #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ICCARM__ )
+ #define __SIMD32_TYPE int32_t __packed
+ #define CMSIS_UNUSED
+ #define CMSIS_INLINE
+
+#elif defined ( __TI_ARM__ )
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED __attribute__((unused))
+ #define CMSIS_INLINE
+
+#elif defined ( __CSMC__ )
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED
+ #define CMSIS_INLINE
+
+#elif defined ( __TASKING__ )
+ #define __SIMD32_TYPE __unaligned int32_t
+ #define CMSIS_UNUSED
+ #define CMSIS_INLINE
+
+#else
+ #error Unknown compiler
+#endif
+
+#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))
+#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))
+#define __SIMD64(addr) (*(int64_t **) & (addr))
+
+#if !defined (ARM_MATH_DSP)
+ /**
+ * @brief definition to pack two 16 bit values.
+ */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
+
+#endif /* !defined (ARM_MATH_DSP) */
+
+ /**
+ * @brief definition to pack four 8 bit values.
+ */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
+
+#endif
+
+
+ /**
+ * @brief Clips Q63 to Q31 values.
+ */
+ CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+ }
+
+ /**
+ * @brief Clips Q63 to Q15 values.
+ */
+ CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+ }
+
+ /**
+ * @brief Clips Q31 to Q7 values.
+ */
+ CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+ }
+
+ /**
+ * @brief Clips Q31 to Q15 values.
+ */
+ CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+ }
+
+ /**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+
+ CMSIS_INLINE __STATIC_INLINE q63_t mult32x64(
+ q63_t x,
+ q31_t y)
+ {
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+ (((q63_t) (x >> 32) * y)));
+ }
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+ */
+
+ CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31(
+ q31_t in,
+ q31_t * dst,
+ q31_t * pRecipTable)
+ {
+ q31_t out;
+ uint32_t tempVal;
+ uint32_t index, i;
+ uint32_t signBits;
+
+ if (in > 0)
+ {
+ signBits = ((uint32_t) (__CLZ( in) - 1));
+ }
+ else
+ {
+ signBits = ((uint32_t) (__CLZ(-in) - 1));
+ }
+
+ /* Convert input sample to 1.31 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 24);
+ index = (index & INDEX_MASK);
+
+ /* 1.31 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0U; i < 2U; i++)
+ {
+ tempVal = (uint32_t) (((q63_t) in * out) >> 31);
+ tempVal = 0x7FFFFFFFu - tempVal;
+ /* 1.31 with exp 1 */
+ /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
+ out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1U);
+ }
+
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15(
+ q15_t in,
+ q15_t * dst,
+ q15_t * pRecipTable)
+ {
+ q15_t out = 0;
+ uint32_t tempVal = 0;
+ uint32_t index = 0, i = 0;
+ uint32_t signBits = 0;
+
+ if (in > 0)
+ {
+ signBits = ((uint32_t)(__CLZ( in) - 17));
+ }
+ else
+ {
+ signBits = ((uint32_t)(__CLZ(-in) - 17));
+ }
+
+ /* Convert input sample to 1.15 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 8);
+ index = (index & INDEX_MASK);
+
+ /* 1.15 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0U; i < 2U; i++)
+ {
+ tempVal = (uint32_t) (((q31_t) in * out) >> 15);
+ tempVal = 0x7FFFu - tempVal;
+ /* 1.15 with exp 1 */
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);
+ /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1);
+ }
+
+
+/*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+#if !defined (ARM_MATH_DSP)
+
+ /*
+ * @brief C custom defined QADD8 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB8 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */
+ q31_t r = 0, s = 0;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHADD16 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB16 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSUB16 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QASX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHASX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSAX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSAX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSDX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+ /*
+ * @brief C custom defined SMUADX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined QADD for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE int32_t __QADD(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE int32_t __QSUB(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined SMLAD for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLADX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLSDX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALD for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALDX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUAD for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSD for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SXTB16 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16(
+ uint32_t x)
+ {
+ return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
+ ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) ));
+ }
+
+ /*
+ * @brief C custom defined SMMLA for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA(
+ int32_t x,
+ int32_t y,
+ int32_t sum)
+ {
+ return (sum + (int32_t) (((int64_t) x * y) >> 32));
+ }
+
+#endif /* !defined (ARM_MATH_DSP) */
+
+
+ /**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q7;
+
+ /**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] S points to an instance of the Q7 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q7(
+ const arm_fir_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 FIR filter.
+ * @param[in,out] S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ */
+ void arm_fir_init_q7(
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] S points to an instance of the Q15 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR filter.
+ * @param[in,out] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+ * numTaps is not a supported value.
+ */
+ arm_status arm_fir_init_q15(
+ arm_fir_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] S points to an instance of the Q31 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR filter.
+ * @param[in,out] S points to an instance of the Q31 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_q31(
+ arm_fir_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] S points to an instance of the floating-point FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_f32(
+ const arm_fir_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_f32(
+ arm_fir_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q15;
+
+ /**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q31;
+
+ /**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_casd_df1_inst_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float32_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f32;
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float64_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f64;
+
+ /**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q15_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q31_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q31;
+
+
+ /**
+ * @brief Floating-point matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Q31, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+
+ /**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+
+ /**
+ * @brief Q31 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix scaling.
+ * @param[in] pSrc points to the input matrix
+ * @param[in] scale scale factor
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_q31(
+ arm_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t * pData);
+
+
+ /**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_q15(
+ arm_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t * pData);
+
+
+ /**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_f32(
+ arm_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t * pData);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+ typedef struct
+ {
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+#if !defined (ARM_MATH_DSP)
+ q15_t A1;
+ q15_t A2;
+#else
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+ q15_t state[3]; /**< The state array of length 3. */
+ q15_t Kp; /**< The proportional gain. */
+ q15_t Ki; /**< The integral gain. */
+ q15_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+ typedef struct
+ {
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ q31_t A2; /**< The derived gain, A2 = Kd . */
+ q31_t state[3]; /**< The state array of length 3. */
+ q31_t Kp; /**< The proportional gain. */
+ q31_t Ki; /**< The integral gain. */
+ q31_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+ typedef struct
+ {
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ float32_t A2; /**< The derived gain, A2 = Kd . */
+ float32_t state[3]; /**< The state array of length 3. */
+ float32_t Kp; /**< The proportional gain. */
+ float32_t Ki; /**< The integral gain. */
+ float32_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_f32;
+
+
+
+ /**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ */
+ void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S);
+
+
+ /**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ */
+
+ void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S);
+
+
+ /**
+ * @brief Initialization function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the q15 PID Control structure
+ */
+ void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S);
+
+
+ /**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+ typedef struct
+ {
+ uint32_t nValues; /**< nValues */
+ float32_t x1; /**< x1 */
+ float32_t xSpacing; /**< xSpacing */
+ float32_t *pYData; /**< pointer to the table of Y values */
+ } arm_linear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ float32_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q31_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q15_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q7_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q7;
+
+
+ /**
+ * @brief Q7 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q15(
+ arm_cfft_radix2_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q31(
+ arm_cfft_radix2_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q31(
+ const arm_cfft_radix2_instance_q31 * S,
+ q31_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+ void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc);
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_f32(
+ const arm_cfft_radix2_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q15_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_q15;
+
+void arm_cfft_q15(
+ const arm_cfft_instance_q15 * S,
+ q15_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_q31;
+
+void arm_cfft_q31(
+ const arm_cfft_instance_q31 * S,
+ q31_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_f32;
+
+ void arm_cfft_f32(
+ const arm_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q15;
+
+ arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst);
+
+ /**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q31;
+
+ arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint16_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_f32;
+
+ arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_f32(
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+typedef struct
+ {
+ arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
+ uint16_t fftLenRFFT; /**< length of the real sequence */
+ float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
+ } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+ arm_rfft_fast_instance_f32 * S,
+ uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+ arm_rfft_fast_instance_f32 * S,
+ float32_t * p, float32_t * pOut,
+ uint8_t ifftFlag);
+
+ /**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ float32_t normalize; /**< normalizing factor. */
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ float32_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.
+ */
+ arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize);
+
+
+ /**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q31_t normalize; /**< normalizing factor. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ q31_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q31;
+
+
+ /**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31 * S,
+ arm_rfft_instance_q31 * S_RFFT,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q31 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q15_t normalize; /**< normalizing factor. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ q15_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15 * S,
+ arm_rfft_instance_q15 * S_RFFT,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q15 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer);
+
+
+ /**
+ * @brief Floating-point vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_f32(
+ float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q7(
+ q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q15(
+ q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q31(
+ q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result);
+
+
+ /**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result);
+
+
+ /**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q7(
+ q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q15(
+ q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q31(
+ q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_f32(
+ float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q7(
+ q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q15(
+ q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q31(
+ q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point FIR decimator.
+ * @param[in] S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR decimator.
+ * @param[in,out] S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+ arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+ arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q31(
+ arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+ arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+ } arm_fir_interpolate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+ arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+ arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+ arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
+ } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+ /**
+ * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f64;
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f32(
+ const arm_biquad_cascade_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_stereo_df2T_f32(
+ const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f64(
+ const arm_biquad_cascade_df2T_instance_f64 * S,
+ float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_stereo_df2T_init_f32(
+ arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f64(
+ arm_biquad_cascade_df2T_instance_f64 * S,
+ uint8_t numStages,
+ float64_t * pCoeffs,
+ float64_t * pState);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pkCoeffs,
+ float32_t * pvCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pkCoeffs,
+ q31_t * pvCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ */
+ void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pkCoeffs,
+ q15_t * pvCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that controls filter coefficient updates. */
+ } arm_lms_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_init_f32(
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q15(
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q15(
+ const arm_lms_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q31(
+ const arm_lms_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q31(
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that control filter coefficient updates. */
+ float32_t energy; /**< saves previous frame energy. */
+ float32_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q31_t *recipTable; /**< points to the reciprocal initial value table. */
+ q31_t energy; /**< saves previous frame energy. */
+ q31_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< Number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q15_t *recipTable; /**< Points to the reciprocal initial value table. */
+ q15_t energy; /**< saves previous frame energy. */
+ q15_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q15;
+
+
+ /**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+ void arm_correlate_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+ void arm_correlate_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+ void arm_correlate_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+ void arm_correlate_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_correlate_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q7;
+
+
+ /**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cos output.
+ */
+ void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCosVal);
+
+
+ /**
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cosine output.
+ */
+ void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal);
+
+
+ /**
+ * @brief Floating-point complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * S points to an instance of the PID control data structure. in
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ *
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ * A0 = Kp + Ki + Kd
+ * A1 = (-Kp ) - (2 * Kd )
+ * A2 = Kd
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ */
+ CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32(
+ arm_pid_instance_f32 * S,
+ float32_t in)
+ {
+ float32_t out;
+
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
+ out = (S->A0 * in) +
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @brief Process function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+ CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31(
+ arm_pid_instance_q31 * S,
+ q31_t in)
+ {
+ q63_t acc;
+ q31_t out;
+
+ /* acc = A0 * x[n] */
+ acc = (q63_t) S->A0 * in;
+
+ /* acc += A1 * x[n-1] */
+ acc += (q63_t) S->A1 * S->state[0];
+
+ /* acc += A2 * x[n-2] */
+ acc += (q63_t) S->A2 * S->state[1];
+
+ /* convert output to 1.31 format to add y[n-1] */
+ out = (q31_t) (acc >> 31U);
+
+ /* out += y[n-1] */
+ out += S->state[2];
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+
+ /**
+ * @brief Process function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+ CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15(
+ arm_pid_instance_q15 * S,
+ q15_t in)
+ {
+ q63_t acc;
+ q15_t out;
+
+#if defined (ARM_MATH_DSP)
+ __SIMD32_TYPE *vstate;
+
+ /* Implementation of PID controller */
+
+ /* acc = A0 * x[n] */
+ acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ vstate = __SIMD32_CONST(S->state);
+ acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);
+#else
+ /* acc = A0 * x[n] */
+ acc = ((q31_t) S->A0) * in;
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc += (q31_t) S->A1 * S->state[0];
+ acc += (q31_t) S->A2 * S->state[1];
+#endif
+
+ /* acc += y[n-1] */
+ acc += (q31_t) S->state[2] << 15;
+
+ /* saturate the output */
+ out = (q15_t) (__SSAT((acc >> 15), 16));
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+ /**
+ * @} end of PID group
+ */
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f32(
+ const arm_matrix_instance_f32 * src,
+ arm_matrix_instance_f32 * dst);
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f64(
+ const arm_matrix_instance_f64 * src,
+ arm_matrix_instance_f64 * dst);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents
+ * in the two-phase orthogonal stator axis Ialpha and Ibeta.
+ * When Ialpha is superposed with Ia as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta
+ * can be calculated using only Ia and Ib.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where Ia and Ib are the instantaneous stator phases and
+ * pIalpha and pIbeta are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup clarke
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point Clarke transform
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32(
+ float32_t Ia,
+ float32_t Ib,
+ float32_t * pIalpha,
+ float32_t * pIbeta)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+ }
+
+
+ /**
+ * @brief Clarke transform for Q31 version
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31(
+ q31_t Ia,
+ q31_t Ib,
+ q31_t * pIalpha,
+ q31_t * pIbeta)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+ /* pIbeta is calculated by adding the intermediate products */
+ *pIbeta = __QADD(product1, product2);
+ }
+
+ /**
+ * @} end of clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q31(
+ q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where pIa and pIb are the instantaneous stator phases and
+ * Ialpha and Ibeta are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Clarke transform
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] pIa points to output three-phase coordinate a
+ * @param[out] pIb points to output three-phase coordinate b
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pIa,
+ float32_t * pIb)
+ {
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+ *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
+ }
+
+
+ /**
+ * @brief Inverse Clarke transform for Q31 version
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] pIa points to output three-phase coordinate a
+ * @param[out] pIb points to output three-phase coordinate b
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pIa,
+ q31_t * pIb)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+ /* pIb is calculated by subtracting the products */
+ *pIb = __QSUB(product2, product1);
+ }
+
+ /**
+ * @} end of inv_clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q15(
+ q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where Ialpha and Ibeta are the stator vector components,
+ * pId and pIq are rotor vector components and cosVal and sinVal are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Park transform
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_park_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pId,
+ float32_t * pIq,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+ *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+ }
+
+
+ /**
+ * @brief Park transform for Q31 version
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_park_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pId,
+ q31_t * pIq,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Ialpha * cosVal) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * sinVal) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Ialpha * sinVal) */
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * cosVal) */
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+ /* Calculate pId by adding the two intermediate products 1 and 2 */
+ *pId = __QADD(product1, product2);
+
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+ *pIq = __QSUB(product4, product3);
+ }
+
+ /**
+ * @} end of park group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q7_to_float(
+ q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where pIalpha and pIbeta are the stator vector components,
+ * Id and Iq are rotor vector components and cosVal and sinVal are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Park transform
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32(
+ float32_t Id,
+ float32_t Iq,
+ float32_t * pIalpha,
+ float32_t * pIbeta,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+ *pIalpha = Id * cosVal - Iq * sinVal;
+
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+ *pIbeta = Id * sinVal + Iq * cosVal;
+ }
+
+
+ /**
+ * @brief Inverse Park transform for Q31 version
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31(
+ q31_t Id,
+ q31_t Iq,
+ q31_t * pIalpha,
+ q31_t * pIbeta,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Id * cosVal) */
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * sinVal) */
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Id * sinVal) */
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * cosVal) */
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+ *pIalpha = __QSUB(product1, product2);
+
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+ *pIbeta = __QADD(product4, product3);
+ }
+
+ /**
+ * @} end of Inverse park group
+ */
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_float(
+ q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ *
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ * where x0, x1 are nearest values of input x
+ * y0, y1 are nearest values to output y
+ *
+ *
+ * \par
+ * This set of functions implements Linear interpolation process
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
+ * sample of data and each call to the function returns a single processed value.
+ * S points to an instance of the Linear Interpolate function data structure.
+ * x is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+ /**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+ CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32(
+ arm_linear_interp_instance_f32 * S,
+ float32_t x)
+ {
+ float32_t y;
+ float32_t x0, x1; /* Nearest input values */
+ float32_t y0, y1; /* Nearest output values */
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */
+ int32_t i; /* Index variable */
+ float32_t *pYData = S->pYData; /* pointer to output table */
+
+ /* Calculation of index */
+ i = (int32_t) ((x - S->x1) / xSpacing);
+
+ if (i < 0)
+ {
+ /* Iniatilize output for below specified range as least output value of table */
+ y = pYData[0];
+ }
+ else if ((uint32_t)i >= S->nValues)
+ {
+ /* Iniatilize output for above specified range as last output value of table */
+ y = pYData[S->nValues - 1];
+ }
+ else
+ {
+ /* Calculation of nearest input values */
+ x0 = S->x1 + i * xSpacing;
+ x1 = S->x1 + (i + 1) * xSpacing;
+
+ /* Read of nearest output values */
+ y0 = pYData[i];
+ y1 = pYData[i + 1];
+
+ /* Calculation of output */
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+ }
+
+ /* returns output value */
+ return (y);
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q31 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q31 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31(
+ q31_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q31_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (q31_t)0xFFF00000) >> 20);
+
+ if (index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if (index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* shift left by 11 to keep fract in 1.31 format */
+ fract = (x & 0x000FFFFF) << 11;
+
+ /* Read two nearest output values from the index in 1.31(q31) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+ /* Convert y to 1.31 format */
+ return (y << 1U);
+ }
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q15 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15(
+ q15_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q63_t y; /* output */
+ q15_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (int32_t)0xFFF00000) >> 20);
+
+ if (index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if (index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+ y = ((q63_t) y0 * (0xFFFFF - fract));
+
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+ y += ((q63_t) y1 * (fract));
+
+ /* convert y to 1.15 format */
+ return (q15_t) (y >> 20);
+ }
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q7 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+ CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7(
+ q7_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q7_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ uint32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ if (x < 0)
+ {
+ return (pYData[0]);
+ }
+ index = (x >> 20) & 0xfff;
+
+ if (index >= (nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index and are in 1.7(q7) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+ y = ((y0 * (0xFFFFF - fract)));
+
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+ y += (y1 * fract);
+
+ /* convert y to 1.7(q7) format */
+ return (q7_t) (y >> 20);
+ }
+ }
+
+ /**
+ * @} end of LinearInterpolate group
+ */
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+ float32_t arm_sin_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q31_t arm_sin_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q15_t arm_sin_q15(
+ q15_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+ float32_t arm_cos_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q31_t arm_cos_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q15_t arm_cos_q15(
+ q15_t x);
+
+
+ /**
+ * @ingroup groupFastMath
+ */
+
+
+ /**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ *
+ * x1 = x0 - f(x0)/f'(x0)
+ *
+ * where x1 is the current estimate,
+ * x0 is the previous estimate, and
+ * f'(x0) is the derivative of f() evaluated at x0.
+ * For the square root function, the algorithm reduces to:
+ *
+ * x0 = in/2 [initial guess]
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]
+ *
+ */
+
+
+ /**
+ * @addtogroup SQRT
+ * @{
+ */
+
+ /**
+ * @brief Floating-point square root function.
+ * @param[in] in input value.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+ CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32(
+ float32_t in,
+ float32_t * pOut)
+ {
+ if (in >= 0.0f)
+ {
+
+#if (__FPU_USED == 1) && defined ( __CC_ARM )
+ *pOut = __sqrtf(in);
+#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+ *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined(__GNUC__)
+ *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
+ __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
+#else
+ *pOut = sqrtf(in);
+#endif
+
+ return (ARM_MATH_SUCCESS);
+ }
+ else
+ {
+ *pOut = 0.0f;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+ }
+
+
+ /**
+ * @brief Q31 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q31(
+ q31_t in,
+ q31_t * pOut);
+
+
+ /**
+ * @brief Q15 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q15(
+ q15_t in,
+ q15_t * pOut);
+
+ /**
+ * @} end of SQRT group
+ */
+
+
+ /**
+ * @brief floating-point Circular write function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const int32_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+
+ /**
+ * @brief floating-point Circular Read function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ int32_t * dst,
+ int32_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == (int32_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular write function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q15_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular Read function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q15_t * dst,
+ q15_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == (q15_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular write function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q7_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular Read function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q7_t * dst,
+ q7_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == (q7_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Floating-point complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult);
+
+
+ /**
+ * @brief Q31 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult);
+
+
+ /**
+ * @brief Floating-point complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult);
+
+
+ /**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q15(
+ q15_t * pSrcCmplx,
+ q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q31(
+ q31_t * pSrcCmplx,
+ q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_f32(
+ float32_t * pSrcCmplx,
+ float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] result is output pointer
+ * @param[in] index is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * result,
+ uint32_t * index);
+
+
+ /**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[in] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q31(
+ float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q15(
+ float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q7(
+ float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q15(
+ q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q7(
+ q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_float(
+ q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q31(
+ q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q7(
+ q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function f(x, y) is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * Algorithm
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ *
+ * typedef struct
+ * {
+ * uint16_t numRows;
+ * uint16_t numCols;
+ * float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ *
+ *
+ * \par
+ * where numRows specifies the number of rows in the table;
+ * numCols specifies the number of columns in the table;
+ * and pData points to an array of size numRows*numCols values.
+ * The data table pTable is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers.
+ *
+ * \par
+ * Let (x, y) specify the desired interpolation point. Then define:
+ *
+ * XF = floor(x)
+ * YF = floor(y)
+ *
+ * \par
+ * The interpolated output point is computed as:
+ *
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ *
+ * Note that the coordinates (x, y) contain integer and fractional components.
+ * The integer components specify which portion of the table to use while the
+ * fractional components control the interpolation processor.
+ *
+ * \par
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+ */
+
+ /**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+
+ /**
+ *
+ * @brief Floating-point bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate.
+ * @param[in] Y interpolation coordinate.
+ * @return out interpolated value.
+ */
+ CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32(
+ const arm_bilinear_interp_instance_f32 * S,
+ float32_t X,
+ float32_t Y)
+ {
+ float32_t out;
+ float32_t f00, f01, f10, f11;
+ float32_t *pData = S->pData;
+ int32_t xIndex, yIndex, index;
+ float32_t xdiff, ydiff;
+ float32_t b1, b2, b3, b4;
+
+ xIndex = (int32_t) X;
+ yIndex = (int32_t) Y;
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* Calculation of index for two nearest points in X-direction */
+ index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+ /* Read two nearest points in X-direction */
+ f00 = pData[index];
+ f01 = pData[index + 1];
+
+ /* Calculation of index for two nearest points in Y-direction */
+ index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+ /* Read two nearest points in Y-direction */
+ f10 = pData[index];
+ f11 = pData[index + 1];
+
+ /* Calculation of intermediate values */
+ b1 = f00;
+ b2 = f01 - f00;
+ b3 = f10 - f00;
+ b4 = f00 - f01 - f10 + f11;
+
+ /* Calculation of fractional part in X */
+ xdiff = X - xIndex;
+
+ /* Calculation of fractional part in Y */
+ ydiff = Y - yIndex;
+
+ /* Calculation of bi-linear interpolated output */
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+ /* return to application */
+ return (out);
+ }
+
+
+ /**
+ *
+ * @brief Q31 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31(
+ arm_bilinear_interp_instance_q31 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q31_t out; /* Temporary output */
+ q31_t acc = 0; /* output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q31_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q31_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* shift left xfract by 11 to keep 1.31 format */
+ xfract = (X & 0x000FFFFF) << 11U;
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + (int32_t)nCols * (cI) ];
+ x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* shift left yfract by 11 to keep 1.31 format */
+ yfract = (Y & 0x000FFFFF) << 11U;
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ];
+ y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* Convert acc to 1.31(q31) format */
+ return ((q31_t)(acc << 2));
+ }
+
+
+ /**
+ * @brief Q15 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15(
+ arm_bilinear_interp_instance_q15 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q15_t x1, x2, y1, y2; /* Nearest output values */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ int32_t rI, cI; /* Row and column indices */
+ q15_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U);
+ acc = ((q63_t) out * (0xFFFFF - yfract));
+
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U);
+ acc += ((q63_t) out * (xfract));
+
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U);
+ acc += ((q63_t) out * (yfract));
+
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U);
+ acc += ((q63_t) out * (yfract));
+
+ /* acc is in 13.51 format and down shift acc by 36 times */
+ /* Convert out to 1.15 format */
+ return ((q15_t)(acc >> 36));
+ }
+
+
+ /**
+ * @brief Q7 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7(
+ arm_bilinear_interp_instance_q7 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q7_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q7_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+ out = ((x1 * (0xFFFFF - xfract)));
+ acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
+ out = ((x2 * (0xFFFFF - yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y1 * (0xFFFFF - xfract)));
+ acc += (((q63_t) out * (yfract)));
+
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y2 * (yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+ return ((q7_t)(acc >> 40));
+ }
+
+ /**
+ * @} end of BilinearInterpolate group
+ */
+
+
+/* SMMLAR */
+#define multAcc_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMLSR */
+#define multSub_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMULR */
+#define mult_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+/* SMMLA */
+#define multAcc_32x32_keep32(a, x, y) \
+ a += (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMLS */
+#define multSub_32x32_keep32(a, x, y) \
+ a -= (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMUL */
+#define mult_32x32_keep32(a, x, y) \
+ a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM )
+ /* Enter low optimization region - place directly above function definition */
+ #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("push") \
+ _Pragma ("O1")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+ #define LOW_OPTIMIZATION_EXIT \
+ _Pragma ("pop")
+ #else
+ #define LOW_OPTIMIZATION_EXIT
+ #endif
+
+ /* Enter low optimization region - place directly above function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __GNUC__ )
+ #define LOW_OPTIMIZATION_ENTER \
+ __attribute__(( optimize("-O1") ))
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __ICCARM__ )
+ /* Enter low optimization region - place directly above function definition */
+ #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define LOW_OPTIMIZATION_EXIT
+
+ /* Enter low optimization region - place directly above function definition */
+ #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TI_ARM__ )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __CSMC__ )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TASKING__ )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/* Compiler specific diagnostic adjustment */
+#if defined ( __CC_ARM )
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+
+#elif defined ( __ICCARM__ )
+
+#elif defined ( __TI_ARM__ )
+
+#elif defined ( __CSMC__ )
+
+#elif defined ( __TASKING__ )
+
+#else
+ #error Unknown compiler
+#endif
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_armcc.h b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_armcc.h
new file mode 100644
index 0000000000..38bcda7f0f
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_armcc.h
@@ -0,0 +1,865 @@
+/**************************************************************************//**
+ * @file cmsis_armcc.h
+ * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version V1.2.0
+ * @date 09. August 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+ #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
+ (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
+ #define __ARM_ARCH_6M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
+ #define __ARM_ARCH_7M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+ #define __ARM_ARCH_7EM__ 1
+#endif
+
+ /* __ARM_ARCH_8M_BASE__ not applicable */
+ /* __ARM_ARCH_8M_MAIN__ not applicable */
+
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE static __forceinline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __declspec(noreturn)
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT __packed struct
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION __packed union
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); */
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() do {\
+ __schedule_barrier();\
+ __isb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+ __schedule_barrier();\
+ __dsb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+ __schedule_barrier();\
+ __dmb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+ #define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+ return result;
+}
+#endif
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+#else
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+#else
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+#else
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXB(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXH(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXW(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32U) ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_armclang.h b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_armclang.h
new file mode 100644
index 0000000000..b98d2bdb94
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_armclang.h
@@ -0,0 +1,1869 @@
+/**************************************************************************//**
+ * @file cmsis_armclang.h
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version V1.2.0
+ * @date 09. August 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR() ((uint32_t)0U)
+#endif
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __set_FPSCR __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x) ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF);
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF);
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF);
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV(value) __builtin_bswap32(value)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __builtin_arm_rbit
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_compiler.h b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_compiler.h
new file mode 100644
index 0000000000..9e94c3cbfc
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_compiler.h
@@ -0,0 +1,266 @@
+/**************************************************************************//**
+ * @file cmsis_compiler.h
+ * @brief CMSIS compiler generic header file
+ * @version V1.2.0
+ * @date 09. August 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include
+
+/*
+ * Arm Compiler 4/5
+ */
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+ #include
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+ #include
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed))
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed))
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __packed__
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __packed__
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __packed__
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __packed__ T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __align(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+ #include
+
+ #ifndef __ASM
+ #define __ASM _asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ // NO RETURN is automatically detected hence no warning here
+ #define __NO_RETURN
+ #endif
+ #ifndef __USED
+ #warning No compiler specific solution for __USED. __USED is ignored.
+ #define __USED
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __weak
+ #endif
+ #ifndef __PACKED
+ #define __PACKED @packed
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT @packed struct
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION @packed union
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ @packed struct T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+
+#else
+ #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_gcc.h b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_gcc.h
new file mode 100644
index 0000000000..c973695a81
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_gcc.h
@@ -0,0 +1,2085 @@
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS compiler GCC header file
+ * @version V1.2.0
+ * @date 09. August 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+ #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_get_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ return __builtin_arm_get_fpscr();
+#else
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#endif
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ __builtin_arm_set_fpscr(fpscr);
+#else
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP() __ASM volatile ("nop")
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI() __ASM volatile ("wfi")
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE() __ASM volatile ("wfe")
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV() __ASM volatile ("sev")
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (int16_t)__builtin_bswap16(value);
+#else
+ int16_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return result;
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ __extension__ \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_iccarm.h b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_iccarm.h
new file mode 100644
index 0000000000..c7fffa931d
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_iccarm.h
@@ -0,0 +1,935 @@
+/**************************************************************************//**
+ * @file cmsis_iccarm.h
+ * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version V1.2.0
+ * @date 09. August 2022
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2018 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+ #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+ #define __ICCARM_V8 1
+#else
+ #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+ #if __ICCARM_V8
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #elif (__VER__ >= 7080000)
+ /* Needs IAR language extensions */
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #else
+ #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+ #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+ #if __ARM_ARCH == 6
+ #define __ARM_ARCH_6M__ 1
+ #elif __ARM_ARCH == 7
+ #if __ARM_FEATURE_DSP
+ #define __ARM_ARCH_7EM__ 1
+ #else
+ #define __ARM_ARCH_7M__ 1
+ #endif
+ #endif /* __ARM_ARCH */
+ #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+ !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+ #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+ #define __ARM_ARCH_6M__ 1
+ #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+ #define __ARM_ARCH_7M__ 1
+ #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+ #define __ARM_ARCH_7EM__ 1
+ #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #else
+ #error "Unknown target."
+ #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+ #define __IAR_M0_FAMILY 1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+ #define __IAR_M0_FAMILY 1
+#else
+ #define __IAR_M0_FAMILY 0
+#endif
+
+
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+
+#ifndef __NO_RETURN
+ #if __ICCARM_V8
+ #define __NO_RETURN __attribute__((__noreturn__))
+ #else
+ #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+ #endif
+#endif
+
+#ifndef __PACKED
+ #if __ICCARM_V8
+ #define __PACKED __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED __packed
+ #endif
+#endif
+
+#ifndef __PACKED_STRUCT
+ #if __ICCARM_V8
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_STRUCT __packed struct
+ #endif
+#endif
+
+#ifndef __PACKED_UNION
+ #if __ICCARM_V8
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_UNION __packed union
+ #endif
+#endif
+
+#ifndef __RESTRICT
+ #define __RESTRICT restrict
+#endif
+
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+
+#ifndef __FORCEINLINE
+ #define __FORCEINLINE _Pragma("inline=forced")
+#endif
+
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+ return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+ *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+ return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+ *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef __USED
+ #if __ICCARM_V8
+ #define __USED __attribute__((used))
+ #else
+ #define __USED _Pragma("__root")
+ #endif
+#endif
+
+#ifndef __WEAK
+ #if __ICCARM_V8
+ #define __WEAK __attribute__((weak))
+ #else
+ #define __WEAK _Pragma("__weak")
+ #endif
+#endif
+
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+ #define __ICCARM_INTRINSICS_VERSION__ 0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+ #if defined(__CLZ)
+ #undef __CLZ
+ #endif
+ #if defined(__REVSH)
+ #undef __REVSH
+ #endif
+ #if defined(__RBIT)
+ #undef __RBIT
+ #endif
+ #if defined(__SSAT)
+ #undef __SSAT
+ #endif
+ #if defined(__USAT)
+ #undef __USAT
+ #endif
+
+ #include "iccarm_builtin.h"
+
+ #define __disable_fault_irq __iar_builtin_disable_fiq
+ #define __disable_irq __iar_builtin_disable_interrupt
+ #define __enable_fault_irq __iar_builtin_enable_fiq
+ #define __enable_irq __iar_builtin_enable_interrupt
+ #define __arm_rsr __iar_builtin_rsr
+ #define __arm_wsr __iar_builtin_wsr
+
+
+ #define __get_APSR() (__arm_rsr("APSR"))
+ #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
+ #define __get_CONTROL() (__arm_rsr("CONTROL"))
+ #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
+
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ #define __get_FPSCR() (__arm_rsr("FPSCR"))
+ #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
+ #else
+ #define __get_FPSCR() ( 0 )
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #define __get_IPSR() (__arm_rsr("IPSR"))
+ #define __get_MSP() (__arm_rsr("MSP"))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __get_MSPLIM() (0U)
+ #else
+ #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
+ #endif
+ #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
+ #define __get_PSP() (__arm_rsr("PSP"))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __get_PSPLIM() (0U)
+ #else
+ #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
+ #endif
+
+ #define __get_xPSR() (__arm_rsr("xPSR"))
+
+ #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
+ #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
+ #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
+ #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
+ #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __set_MSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
+ #endif
+ #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
+ #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __set_PSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
+ #endif
+
+ #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
+ #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
+ #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
+ #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
+ #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
+ #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
+ #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
+ #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
+ #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
+ #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
+ #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
+ #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
+ #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
+ #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __TZ_get_PSPLIM_NS() (0U)
+ #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+ #else
+ #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
+ #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+ #endif
+
+ #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
+ #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+ #define __NOP __iar_builtin_no_operation
+
+ #define __CLZ __iar_builtin_CLZ
+ #define __CLREX __iar_builtin_CLREX
+
+ #define __DMB __iar_builtin_DMB
+ #define __DSB __iar_builtin_DSB
+ #define __ISB __iar_builtin_ISB
+
+ #define __LDREXB __iar_builtin_LDREXB
+ #define __LDREXH __iar_builtin_LDREXH
+ #define __LDREXW __iar_builtin_LDREX
+
+ #define __RBIT __iar_builtin_RBIT
+ #define __REV __iar_builtin_REV
+ #define __REV16 __iar_builtin_REV16
+
+ __IAR_FT int16_t __REVSH(int16_t val)
+ {
+ return (int16_t) __iar_builtin_REVSH(val);
+ }
+
+ #define __ROR __iar_builtin_ROR
+ #define __RRX __iar_builtin_RRX
+
+ #define __SEV __iar_builtin_SEV
+
+ #if !__IAR_M0_FAMILY
+ #define __SSAT __iar_builtin_SSAT
+ #endif
+
+ #define __STREXB __iar_builtin_STREXB
+ #define __STREXH __iar_builtin_STREXH
+ #define __STREXW __iar_builtin_STREX
+
+ #if !__IAR_M0_FAMILY
+ #define __USAT __iar_builtin_USAT
+ #endif
+
+ #define __WFE __iar_builtin_WFE
+ #define __WFI __iar_builtin_WFI
+
+ #if __ARM_MEDIA__
+ #define __SADD8 __iar_builtin_SADD8
+ #define __QADD8 __iar_builtin_QADD8
+ #define __SHADD8 __iar_builtin_SHADD8
+ #define __UADD8 __iar_builtin_UADD8
+ #define __UQADD8 __iar_builtin_UQADD8
+ #define __UHADD8 __iar_builtin_UHADD8
+ #define __SSUB8 __iar_builtin_SSUB8
+ #define __QSUB8 __iar_builtin_QSUB8
+ #define __SHSUB8 __iar_builtin_SHSUB8
+ #define __USUB8 __iar_builtin_USUB8
+ #define __UQSUB8 __iar_builtin_UQSUB8
+ #define __UHSUB8 __iar_builtin_UHSUB8
+ #define __SADD16 __iar_builtin_SADD16
+ #define __QADD16 __iar_builtin_QADD16
+ #define __SHADD16 __iar_builtin_SHADD16
+ #define __UADD16 __iar_builtin_UADD16
+ #define __UQADD16 __iar_builtin_UQADD16
+ #define __UHADD16 __iar_builtin_UHADD16
+ #define __SSUB16 __iar_builtin_SSUB16
+ #define __QSUB16 __iar_builtin_QSUB16
+ #define __SHSUB16 __iar_builtin_SHSUB16
+ #define __USUB16 __iar_builtin_USUB16
+ #define __UQSUB16 __iar_builtin_UQSUB16
+ #define __UHSUB16 __iar_builtin_UHSUB16
+ #define __SASX __iar_builtin_SASX
+ #define __QASX __iar_builtin_QASX
+ #define __SHASX __iar_builtin_SHASX
+ #define __UASX __iar_builtin_UASX
+ #define __UQASX __iar_builtin_UQASX
+ #define __UHASX __iar_builtin_UHASX
+ #define __SSAX __iar_builtin_SSAX
+ #define __QSAX __iar_builtin_QSAX
+ #define __SHSAX __iar_builtin_SHSAX
+ #define __USAX __iar_builtin_USAX
+ #define __UQSAX __iar_builtin_UQSAX
+ #define __UHSAX __iar_builtin_UHSAX
+ #define __USAD8 __iar_builtin_USAD8
+ #define __USADA8 __iar_builtin_USADA8
+ #define __SSAT16 __iar_builtin_SSAT16
+ #define __USAT16 __iar_builtin_USAT16
+ #define __UXTB16 __iar_builtin_UXTB16
+ #define __UXTAB16 __iar_builtin_UXTAB16
+ #define __SXTB16 __iar_builtin_SXTB16
+ #define __SXTAB16 __iar_builtin_SXTAB16
+ #define __SMUAD __iar_builtin_SMUAD
+ #define __SMUADX __iar_builtin_SMUADX
+ #define __SMMLA __iar_builtin_SMMLA
+ #define __SMLAD __iar_builtin_SMLAD
+ #define __SMLADX __iar_builtin_SMLADX
+ #define __SMLALD __iar_builtin_SMLALD
+ #define __SMLALDX __iar_builtin_SMLALDX
+ #define __SMUSD __iar_builtin_SMUSD
+ #define __SMUSDX __iar_builtin_SMUSDX
+ #define __SMLSD __iar_builtin_SMLSD
+ #define __SMLSDX __iar_builtin_SMLSDX
+ #define __SMLSLD __iar_builtin_SMLSLD
+ #define __SMLSLDX __iar_builtin_SMLSLDX
+ #define __SEL __iar_builtin_SEL
+ #define __QADD __iar_builtin_QADD
+ #define __QSUB __iar_builtin_QSUB
+ #define __PKHBT __iar_builtin_PKHBT
+ #define __PKHTB __iar_builtin_PKHTB
+ #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #define __CLZ __cmsis_iar_clz_not_active
+ #define __SSAT __cmsis_iar_ssat_not_active
+ #define __USAT __cmsis_iar_usat_not_active
+ #define __RBIT __cmsis_iar_rbit_not_active
+ #define __get_APSR __cmsis_iar_get_APSR_not_active
+ #endif
+
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+ #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+ #endif
+
+ #ifdef __INTRINSICS_INCLUDED
+ #error intrinsics.h is already included previously!
+ #endif
+
+ #include
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #undef __CLZ
+ #undef __SSAT
+ #undef __USAT
+ #undef __RBIT
+ #undef __get_APSR
+
+ __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+ {
+ if (data == 0U) { return 32U; }
+
+ uint32_t count = 0U;
+ uint32_t mask = 0x80000000U;
+
+ while ((data & mask) == 0U)
+ {
+ count += 1U;
+ mask = mask >> 1U;
+ }
+ return count;
+ }
+
+ __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+ {
+ uint8_t sc = 31U;
+ uint32_t r = v;
+ for (v >>= 1U; v; v >>= 1U)
+ {
+ r <<= 1U;
+ r |= v & 1U;
+ sc--;
+ }
+ return (r << sc);
+ }
+
+ __STATIC_INLINE uint32_t __get_APSR(void)
+ {
+ uint32_t res;
+ __asm("MRS %0,APSR" : "=r" (res));
+ return res;
+ }
+
+ #endif
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #undef __get_FPSCR
+ #undef __set_FPSCR
+ #define __get_FPSCR() (0)
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #pragma diag_suppress=Pe940
+ #pragma diag_suppress=Pe177
+
+ #define __enable_irq __enable_interrupt
+ #define __disable_irq __disable_interrupt
+ #define __NOP __no_operation
+
+ #define __get_xPSR __get_PSR
+
+ #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+ __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+ {
+ return __LDREX((unsigned long *)ptr);
+ }
+
+ __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+ {
+ return __STREX(value, (unsigned long *)ptr);
+ }
+ #endif
+
+
+ /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+ #if (__CORTEX_M >= 0x03)
+
+ __IAR_FT uint32_t __RRX(uint32_t value)
+ {
+ uint32_t result;
+ __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
+ return(result);
+ }
+
+ __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
+ }
+
+
+ #define __enable_fault_irq __enable_fiq
+ #define __disable_fault_irq __disable_fiq
+
+
+ #endif /* (__CORTEX_M >= 0x03) */
+
+ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+ {
+ return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+ }
+
+ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+ __IAR_FT uint32_t __get_MSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,MSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_MSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR MSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __get_PSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_PSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
+ {
+ __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR PSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_SP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,SP_NS" : "=r" (res));
+ return res;
+ }
+ __IAR_FT void __TZ_set_SP_NS(uint32_t value)
+ {
+ __asm volatile("MSR SP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
+ }
+
+ #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+ __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+ {
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+ }
+
+ __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+ {
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+ }
+#endif
+
+#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+ __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+ {
+ __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+ {
+ __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+ {
+ __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+ }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+
+ __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+ {
+ __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+ {
+ __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+ {
+ __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_version.h b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_version.h
new file mode 100644
index 0000000000..6ffd7ddd26
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_version.h
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file cmsis_version.h
+ * @brief CMSIS Core(M) Version definitions
+ * @version V1.2.0
+ * @date 09. August 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/* CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
+#endif
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/core_cm4.h b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/core_cm4.h
new file mode 100644
index 0000000000..109109cfdd
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/core_cm4.h
@@ -0,0 +1,2129 @@
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V1.2.0
+ * @date 09. August 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M4
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (4U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000U
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/mpu_armv7.h b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/mpu_armv7.h
new file mode 100644
index 0000000000..6acbbefcda
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/mpu_armv7.h
@@ -0,0 +1,270 @@
+/******************************************************************************
+ * @file mpu_armv7.h
+ * @brief CMSIS MPU API for Armv7-M MPU
+ * @version V1.2.0
+ * @date 09. August 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+ (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
+ ((Region) & MPU_RBAR_REGION_Msk) | \
+ (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+*
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
+ ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
+ (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
+ (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
+ (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
+ ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
+ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
+ (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+ ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+* - TEX: 000b
+* - Shareable
+* - Non-cacheable
+* - Non-bufferable
+*/
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+* - TEX: 000b (if non-shareable) or 010b (if shareable)
+* - Shareable or non-shareable
+* - Non-cacheable
+* - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+* - TEX: 1BBb (reflecting outer cacheability rules)
+* - Shareable or non-shareable
+* - Cacheable or non-cacheable (reflecting inner cacheability rules)
+* - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+ uint32_t RBAR; //!< The region base address register value (RBAR)
+ uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+ __DSB();
+ __ISB();
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+ __DSB();
+ __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+ MPU->RNR = rnr;
+ MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+ MPU->RNR = rnr;
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+ uint32_t i;
+ for (i = 0U; i < len; ++i)
+ {
+ dst[i] = src[i];
+ }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+ while (cnt > MPU_TYPE_RALIASES) {
+ orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+ table += MPU_TYPE_RALIASES;
+ cnt -= MPU_TYPE_RALIASES;
+ }
+ orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/n32l43x.h b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/n32l43x.h
new file mode 100644
index 0000000000..4f0e3e1474
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/n32l43x.h
@@ -0,0 +1,8067 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L43X_H__
+#define __N32L43X_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup N32L43x_Library_Basic
+ * @{
+ */
+
+#if !defined USE_STDPERIPH_DRIVER
+/*
+ * Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+#define USE_STDPERIPH_DRIVER
+#endif
+
+/*
+ * In the following line adjust the value of External High Speed oscillator (HSE)
+ used in your application
+
+ Tip: To avoid modifying this file each time you need to use different HSE, you
+ can define the HSE value in your toolchain compiler preprocessor.
+ */
+#if !defined HSE_VALUE
+#define HSE_VALUE (8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+/*
+ * In the following line adjust the External High Speed oscillator (HSE) Startup
+ Timeout value
+ */
+#define HSE_STARTUP_TIMEOUT ((uint16_t)0x2000) /*!< Time out for HSE start up */
+#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */
+#define MSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for MSI start up */
+
+#define MSI_VALUE_L0 (100000) /*!< L0 Value of the Multi oscillator in Hz*/
+#define MSI_VALUE_L1 (200000) /*!< L1 Value of the Multi oscillator in Hz*/
+#define MSI_VALUE_L2 (400000) /*!< L2 Value of the Multi oscillator in Hz*/
+#define MSI_VALUE_L3 (800000) /*!< L3 Value of the Multi oscillator in Hz*/
+#define MSI_VALUE_L4 (1000000) /*!< L4 Value of the Multi oscillator in Hz*/
+#define MSI_VALUE_L5 (2000000) /*!< L5 Value of the Multi oscillator in Hz*/
+#define MSI_VALUE_L6 (4000000) /*!< L6 Value of the Multi oscillator in Hz*/
+
+#define HSI_VALUE (16000000) /*!< Value of the Internal oscillator in Hz*/
+
+#define __N32L43X_STDPERIPH_VERSION_MAIN (0x00) /*!< [31:24] main version */
+#define __N32L43X_STDPERIPH_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */
+#define __N32L43X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __N32L43X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
+
+/**
+ * @brief N32L43x Standard Peripheral Library version number
+ */
+#define __N32L43X_STDPERIPH_VERSION \
+ ((__N32L43X_STDPERIPH_VERSION_MAIN << 24) | (__N32L43X_STDPERIPH_VERSION_SUB1 << 16) \
+ | (__N32L43X_STDPERIPH_VERSION_SUB2 << 8) | (__N32L43X_STDPERIPH_VERSION_RC))
+
+/*
+ * Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#ifdef N32L43X
+#define __MPU_PRESENT 1 /*!< N32L43x devices does not provide an MPU */
+#define __FPU_PRESENT 1 /*!< FPU present */
+#endif /* N32L43x */
+#define __NVIC_PRIO_BITS 4 /*!< N32L43x uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @brief N32L43x Interrupt Number Definition
+ */
+typedef enum IRQn
+{
+ /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+
+ /****** N32L43x specific Interrupt Numbers ********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_IRQn = 2, /*!< RTC Tamper interrupt or Timestamp through EXTI line 19 */
+ RTC_IRQn = 3, /*!< RTC wakeup timer through EXTI line 20 */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA_Channel1_IRQn = 11, /*!< DMA Channel 1 global Interrupt */
+ DMA_Channel2_IRQn = 12, /*!< DMA Channel 2 global Interrupt */
+ DMA_Channel3_IRQn = 13, /*!< DMA Channel 3 global Interrupt */
+ DMA_Channel4_IRQn = 14, /*!< DMA Channel 4 global Interrupt */
+ DMA_Channel5_IRQn = 15, /*!< DMA Channel 5 global Interrupt */
+ DMA_Channel6_IRQn = 16, /*!< DMA Channel 6 global Interrupt */
+ DMA_Channel7_IRQn = 17, /*!< DMA Channel 7 global Interrupt */
+ DMA_Channel8_IRQn = 18, /*!< DMA Channel 8 global Interrupt */
+ ADC_IRQn = 19, /*!< ADC global Interrupt */
+ USB_HP_IRQn = 20, /*!< USB Device High Priority Interrupts */
+ USB_LP_IRQn = 21, /*!< USB Device Low Priority Interrupts */
+ COMP_1_2_IRQn = 22, /*!< COMP1 & COMP2 global Interrupt through EXTI line 21/22 */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+ TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
+ TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
+ TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ UART4_IRQn = 47, /*!< UART4 global Interrupt */
+ UART5_IRQn = 48, /*!< UART5 global Interrupt */
+ LPUART_IRQn = 49, /*!< LPUART global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ TIM6_IRQn = 51, /*!< TIM6 global Interrupt */
+ TIM7_IRQn = 52, /*!< TIM7 global Interrupt */
+ CAN_TX_IRQn = 53, /*!< CAN TX Interrupt */
+ CAN_RX0_IRQn = 54, /*!< CAN RX0 Interrupt */
+ CAN_RX1_IRQn = 55, /*!< CAN RX1 Interrupt */
+ CAN_SCE_IRQn = 56, /*!< CAN SCE Interrupt */
+ LPUART_WKUP_IRQn = 57, /*!< LPUART wakeup interrupt through EXTI line 23 */
+ LPTIM_WKUP_IRQn = 58, /*!< LPTIMER wakeup interrupt through EXTI line 24 */
+ LCD_IRQn = 59, /*!< LCD global interrupt through EXTI line 26 */
+ SAC_IRQn = 60, /*!< SAC global Interrupt */
+ MMU_IRQn = 61, /*!< MMU global Interrupt */
+ TSC_IRQn = 62, /*!< TSC global Interrupt */
+ RAMC_PERR_IRQn = 63, /*!< RAM parity error interrupt */
+ TIM9_IRQn = 64, /*!< TIM9 global interrupt */
+ UCDR_IRQn = 65, /*!< UCDR error interrupt */
+ LPRCNT_IRQn = 152 /*!< LPRCNT turns overflow interrupt */
+} IRQn_Type;
+
+#include "core_cm4.h"
+#include "system_n32l43x.h"
+#include
+#include
+
+typedef int32_t s32;
+typedef int16_t s16;
+typedef int8_t s8;
+
+typedef const int32_t sc32; /*!< Read Only */
+typedef const int16_t sc16; /*!< Read Only */
+typedef const int8_t sc8; /*!< Read Only */
+
+typedef __IO int32_t vs32;
+typedef __IO int16_t vs16;
+typedef __IO int8_t vs8;
+
+typedef __I int32_t vsc32; /*!< Read Only */
+typedef __I int16_t vsc16; /*!< Read Only */
+typedef __I int8_t vsc8; /*!< Read Only */
+
+typedef uint32_t u32;
+typedef uint16_t u16;
+typedef uint8_t u8;
+
+typedef const uint32_t uc32; /*!< Read Only */
+typedef const uint16_t uc16; /*!< Read Only */
+typedef const uint8_t uc8; /*!< Read Only */
+
+typedef __IO uint32_t vu32;
+typedef __IO uint16_t vu16;
+typedef __IO uint8_t vu8;
+
+typedef __I uint32_t vuc32; /*!< Read Only */
+typedef __I uint16_t vuc16; /*!< Read Only */
+typedef __I uint8_t vuc8; /*!< Read Only */
+typedef enum
+{
+ RESET = 0,
+ SET = !RESET
+} FlagStatus,
+ INTStatus;
+
+typedef enum
+{
+ DISABLE = 0,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/* N32L43x Standard Peripheral Library old definitions (maintained for legacy purpose) */
+#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT
+#define HSE_Value HSE_VALUE
+#define HSI_Value HSI_VALUE
+
+/**
+ * @brief Analog to Digital Converter
+ */
+typedef struct
+{
+ __IO uint32_t STS;
+ __IO uint32_t CTRL1;
+ __IO uint32_t CTRL2;
+ __IO uint32_t SAMPT1;
+ __IO uint32_t SAMPT2;
+ __IO uint32_t JOFFSET1;
+ __IO uint32_t JOFFSET2;
+ __IO uint32_t JOFFSET3;
+ __IO uint32_t JOFFSET4;
+ __IO uint32_t WDGHIGH;
+ __IO uint32_t WDGLOW;
+ __IO uint32_t RSEQ1;
+ __IO uint32_t RSEQ2;
+ __IO uint32_t RSEQ3;
+ __IO uint32_t JSEQ;
+ __IO uint32_t JDAT1;
+ __IO uint32_t JDAT2;
+ __IO uint32_t JDAT3;
+ __IO uint32_t JDAT4;
+ __IO uint32_t DAT;
+ __IO uint32_t DIFSEL;
+ __IO uint32_t CALFACT;
+ __IO uint32_t CTRL3;
+ __IO uint32_t SAMPT3;
+} ADC_Module;
+
+/**
+ * @brief OPAMP
+ */
+typedef struct
+{
+ __IO uint32_t CS1;
+ __IO uint32_t RES1[3];
+ __IO uint32_t CS2;
+ __IO uint32_t RES2[3];
+ __IO uint32_t LOCK;
+} OPAMP_Module;
+
+/**
+ * @brief COMP_Single
+ */
+typedef struct
+{
+ __IO uint32_t CTRL;
+ __IO uint32_t FILC;
+ __IO uint32_t FILP;
+} COMP_SingleType;
+
+/**
+ * @brief COMP
+ */
+typedef struct
+{
+ __IO uint32_t INTEN;
+ __IO uint32_t LPCKSEL;
+ __IO uint32_t WINMODE;
+ __IO uint32_t LOCK;
+ COMP_SingleType Cmp1;
+ __IO uint32_t RES;
+ COMP_SingleType Cmp2;
+ __IO uint32_t CMP2OSEL;
+ __IO uint32_t VREFSCL;
+ __IO uint32_t TEST;
+ __IO uint32_t INTSTS;
+} COMP_Module;
+
+/**
+ * @brief AFEC
+ */
+
+typedef struct
+{
+ __IO uint32_t TRIMR0;
+ __IO uint32_t TRIMR1;
+ __IO uint32_t TRIMR2;
+ __IO uint32_t TRIMR3;
+ __IO uint32_t TRIMR4;
+ __IO uint32_t TRIMR5;
+ __IO uint32_t TRIMR6;
+ __IO uint32_t TRIMR7;
+ __IO uint32_t TRIMR8;
+ //uint32_t RESERVED0;
+ __IO uint32_t TESTR0;
+ __IO uint32_t TESTR1;
+} AFEC_Module;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TMI;
+ __IO uint32_t TMDT;
+ __IO uint32_t TMDL;
+ __IO uint32_t TMDH;
+} CAN_TxMailBox_Param;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RMI;
+ __IO uint32_t RMDT;
+ __IO uint32_t RMDL;
+ __IO uint32_t RMDH;
+} CAN_FIFOMailBox_Param;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1;
+ __IO uint32_t FR2;
+} CAN_FilterRegister_Param;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCTRL;
+ __IO uint32_t MSTS;
+ __IO uint32_t TSTS;
+ __IO uint32_t RFF0;
+ __IO uint32_t RFF1;
+ __IO uint32_t INTE;
+ __IO uint32_t ESTS;
+ __IO uint32_t BTIM;
+ uint32_t RESERVED0[88];
+ CAN_TxMailBox_Param sTxMailBox[3];
+ CAN_FIFOMailBox_Param sFIFOMailBox[2];
+ uint32_t RESERVED1[12];
+ __IO uint32_t FMC;
+ __IO uint32_t FM1;
+ uint32_t RESERVED2;
+ __IO uint32_t FS1;
+ uint32_t RESERVED3;
+ __IO uint32_t FFA1;
+ uint32_t RESERVED4;
+ __IO uint32_t FA1;
+ uint32_t RESERVED5[8];
+ CAN_FilterRegister_Param sFilterRegister[14];
+} CAN_Module;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t CRC32DAT; /*!< CRC data register */
+ __IO uint8_t CRC32IDAT; /*!< CRC independent data register*/
+ uint8_t RESERVED0;
+ uint16_t RESERVED1;
+ __IO uint32_t CRC32CTRL; /*!< CRC control register */
+ __IO uint32_t CRC16CTRL;
+ __IO uint8_t CRC16DAT;
+ uint8_t RESERVED2;
+ uint16_t RESERVED3;
+ __IO uint16_t CRC16D;
+ uint16_t RESERVED4;
+ __IO uint8_t LRC;
+ uint8_t RESERVED5;
+ uint16_t RESERVED6;
+} CRC_Module;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CTRL;
+ __IO uint32_t SOTTR;
+ __IO uint32_t DR12CH;
+ __IO uint32_t DL12CH;
+ __IO uint32_t DR8CH;
+ __IO uint32_t DATO;
+
+} DAC_Module;
+/**
+ * @brief USB
+ */
+
+typedef struct
+{
+ __IO uint32_t EP0;
+ __IO uint32_t EP1;
+ __IO uint32_t EP2;
+ __IO uint32_t EP3;
+ __IO uint32_t EP4;
+ __IO uint32_t EP5;
+ __IO uint32_t EP6;
+ __IO uint32_t EP7;
+ __IO uint32_t Reserve20h;
+ __IO uint32_t Reserve24h;
+ __IO uint32_t Reserve28h;
+ __IO uint32_t Reserve2Ch;
+ __IO uint32_t Reserve30h;
+ __IO uint32_t Reserve34h;
+ __IO uint32_t Reserve38h;
+ __IO uint32_t Reserve3Ch;
+ __IO uint32_t CTRL;
+ __IO uint32_t STS;
+ __IO uint32_t FN;
+ __IO uint32_t ADDR;
+ __IO uint32_t BUFTAB;
+} USB_Module;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t ID;
+ __IO uint32_t CTRL;
+} DBG_Module;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CHCFG;
+ __IO uint32_t TXNUM;
+ __IO uint32_t PADDR;
+ __IO uint32_t MADDR;
+ __IO uint32_t CHSEL;
+
+} DMA_ChannelType;
+
+typedef struct
+{
+ __IO uint32_t INTSTS;
+ __IO uint32_t INTCLR;
+ __IO DMA_ChannelType DMA_Channel[8];
+} DMA_Module;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMASK; /*offset 0x00*/
+ __IO uint32_t EMASK; /*offset 0x04*/
+ __IO uint32_t RT_CFG; /*offset 0x08*/
+ __IO uint32_t FT_CFG; /*offset 0x0C*/
+ __IO uint32_t SWIE; /*offset 0x10*/
+ __IO uint32_t PEND; /*offset 0x14*/
+ __IO uint32_t TS_SEL; /*offset 0x18*/
+} EXTI_Module;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t AC;
+ __IO uint32_t KEYR;
+ __IO uint32_t OPTKEY;
+ __IO uint32_t STS;
+ __IO uint32_t CTRL;
+ __IO uint32_t ADD;
+ __IO uint32_t OB2;
+ __IO uint32_t OB;
+ __IO uint32_t WRP;
+ __IO uint32_t RESERVED0;
+ __IO uint32_t RESERVED1;
+ __IO uint32_t RESERVED2;
+ __IO uint32_t CAHR;
+} FLASH_Module;
+
+/**
+ * @brief Option Bytes Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t USER_RDP;
+ __IO uint32_t Data1_Data0;
+ __IO uint32_t WRP1_WRP0;
+ __IO uint32_t WRP3_WRP2;
+ __IO uint32_t USER2_RDP2;
+} OB_Module;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t PMODE; /*offset 0x00*/
+ __IO uint32_t POTYPE; /*offset 0x04*/
+ __IO uint32_t SR; /*offset 0x08*/
+ __IO uint32_t PUPD; /*offset 0x0C*/
+ __IO uint32_t PID; /*offset 0x10*/
+ __IO uint32_t POD; /*offset 0x14*/
+ __IO uint32_t PBSC; /*offset 0x18*/
+ __IO uint32_t PLOCK; /*offset 0x1C*/
+ __IO uint32_t AFL; /*offset 0x20*/
+ __IO uint32_t AFH; /*offset 0x24*/
+ __IO uint32_t PBC; /*offset 0x28*/
+ __IO uint32_t DS; /*offset 0x2C*/
+
+} GPIO_Module;
+
+/**
+ * @brief Alternate Function I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t RMP_CFG;
+ __IO uint32_t EXTI_CFG[4];
+} AFIO_Module;
+/**
+ * @brief Inter Integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint16_t CTRL1;
+ uint16_t RESERVED0;
+ __IO uint16_t CTRL2;
+ uint16_t RESERVED1;
+ __IO uint16_t OADDR1;
+ uint16_t RESERVED2;
+ __IO uint16_t OADDR2;
+ uint16_t RESERVED3;
+ __IO uint16_t DAT;
+ uint16_t RESERVED4;
+ __IO uint16_t STS1;
+ uint16_t RESERVED5;
+ __IO uint16_t STS2;
+ uint16_t RESERVED6;
+ __IO uint16_t CLKCTRL;
+ uint16_t RESERVED7;
+ __IO uint16_t TMRISE;
+ uint16_t RESERVED8;
+} I2C_Module;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KEY;
+ __IO uint32_t PREDIV; /*!< IWDG PREDIV */
+ __IO uint32_t RELV;
+ __IO uint32_t STS;
+} IWDG_Module;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CTRL1;
+ __IO uint32_t CTRL2;
+ __IO uint32_t CTRL3;
+ __IO uint32_t STS1;
+ __IO uint32_t STS2;
+ __IO uint32_t STSCLR;
+} PWR_Module;
+/**
+ * @brief Low-Power Timer
+ */
+typedef struct
+{
+ __IO uint32_t INTSTS;
+ __IO uint32_t INTCLR;
+ __IO uint32_t INTEN;
+ __IO uint32_t CFG;
+ __IO uint32_t CTRL;
+ __IO uint32_t COMPx;
+ __IO uint32_t ARR;
+ __IO uint32_t CNT;
+
+} LPTIM_Module;
+/**
+ * @brief Low-Power RCNT
+ */
+typedef struct
+{
+ __IO uint32_t CTRL;
+ __IO uint32_t INTSTS;
+ __IO uint32_t SCTRL;
+ __IO uint32_t CH0CFG0;
+ __IO uint32_t CH0CFG1;
+ __IO uint32_t CH1CFG0;
+ __IO uint32_t CH1CFG1;
+ __IO uint32_t CH2CFG0;
+ __IO uint32_t CH2CFG1;
+ __IO uint32_t CMD;
+ __IO uint32_t Reserve;
+ __IO uint32_t Reserve1;
+ __IO uint32_t CAL0;
+ __IO uint32_t CAL1;
+ __IO uint32_t CAL2;
+ __IO uint32_t CAL3;
+} LPRCNT_Module;
+
+
+
+
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CTRL;
+ __IO uint32_t CFG;
+ __IO uint32_t CLKINT;
+ __IO uint32_t APB2PRST;
+ __IO uint32_t APB1PRST;
+ __IO uint32_t AHBPCLKEN;
+ __IO uint32_t APB2PCLKEN;
+ __IO uint32_t APB1PCLKEN;
+ __IO uint32_t LDCTRL;
+ __IO uint32_t CTRLSTS;
+ __IO uint32_t AHBPRST;
+ __IO uint32_t CFG2;
+ __IO uint32_t CFG3;
+ __IO uint32_t RDCTRL;
+ __IO uint32_t Reserve0;
+ __IO uint32_t Reserve1;
+ __IO uint32_t PLLHSIPRE;
+ __IO uint32_t SRAM_CTRLSTS;
+} RCC_Module;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TSH; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DATE; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CTRL; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t INITSTS; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRE; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WKUPT; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t reserved0; /*!< Reserved */
+ __IO uint32_t ALARMA; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALARMB; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WRP; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SUBS; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SCTRL; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TST; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSD; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSS; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALIB; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TMPCFG; /*!< RTC tamper configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASS; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSS; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ __IO uint32_t OPT; /*!< RTC option register, Address offset: 0x4C */
+ __IO uint32_t BKP1R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP4R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP5R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP8R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP9R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP12R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP13R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP16R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP17R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP20R; /*!< RTC backup register 19, Address offset: 0x9C */
+ __IO uint32_t TSCWKUPCTRL; /*!< TSC register 1, Address offset: 0xA0 */
+ __IO uint32_t TSCWKUPCNT; /*!< TSC register 2, Address offset: 0xA4 */
+} RTC_Module;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint16_t CTRL1;
+ uint16_t RESERVED0;
+ __IO uint16_t CTRL2;
+ uint16_t RESERVED1;
+ __IO uint16_t STS;
+ uint16_t RESERVED2;
+ __IO uint16_t DAT;
+ uint16_t RESERVED3;
+ __IO uint16_t CRCPOLY;
+ uint16_t RESERVED4;
+ __IO uint16_t CRCRDAT;
+ uint16_t RESERVED5;
+ __IO uint16_t CRCTDAT;
+ uint16_t RESERVED6;
+ __IO uint16_t I2SCFG;
+ uint16_t RESERVED7;
+ __IO uint16_t I2SPREDIV;
+ uint16_t RESERVED8;
+} SPI_Module;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CTRL1;
+ __IO uint32_t CTRL2;
+ __IO uint16_t SMCTRL;
+ uint16_t RESERVED1;
+ __IO uint16_t DINTEN;
+ uint16_t RESERVED2;
+ __IO uint32_t STS;
+ __IO uint16_t EVTGEN;
+ uint16_t RESERVED3;
+ __IO uint16_t CCMOD1;
+ uint16_t RESERVED4;
+ __IO uint16_t CCMOD2;
+ uint16_t RESERVED5;
+ __IO uint32_t CCEN;
+ __IO uint16_t CNT;
+ uint16_t RESERVED6;
+ __IO uint16_t PSC;
+ uint16_t RESERVED7;
+ __IO uint16_t AR;
+ uint16_t RESERVED8;
+ __IO uint16_t REPCNT;
+ uint16_t RESERVED9;
+ __IO uint16_t CCDAT1;
+ uint16_t RESERVED10;
+ __IO uint16_t CCDAT2;
+ uint16_t RESERVED11;
+ __IO uint16_t CCDAT3;
+ uint16_t RESERVED12;
+ __IO uint16_t CCDAT4;
+ uint16_t RESERVED13;
+ __IO uint16_t BKDT;
+ uint16_t RESERVED14;
+ __IO uint16_t DCTRL;
+ uint16_t RESERVED15;
+ __IO uint16_t DADDR;
+ uint16_t RESERVED16;
+ uint32_t RESERVED17;
+ __IO uint16_t CCMOD3;
+ uint16_t RESERVED18;
+ __IO uint16_t CCDAT5;
+ uint16_t RESERVED19;
+ __IO uint16_t CCDAT6;
+ uint16_t RESERVED20;
+} TIM_Module;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint16_t STS;
+ uint16_t RESERVED0;
+ __IO uint16_t DAT;
+ uint16_t RESERVED1;
+ __IO uint16_t BRCF;
+ uint16_t RESERVED2;
+ __IO uint16_t CTRL1;
+ uint16_t RESERVED3;
+ __IO uint16_t CTRL2;
+ uint16_t RESERVED4;
+ __IO uint16_t CTRL3;
+ uint16_t RESERVED5;
+ __IO uint16_t GTP;
+ uint16_t RESERVED6;
+} USART_Module;
+
+/**
+ * @brief Low-power Universal Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint16_t STS;
+ uint16_t RESERVED0;
+ __IO uint8_t INTEN;
+ uint8_t RESERVED1;
+ uint16_t RESERVED2;
+ __IO uint16_t CTRL;
+ uint16_t RESERVED3;
+ __IO uint16_t BRCFG1;
+ uint16_t RESERVED4;
+ __IO uint8_t DAT;
+ uint8_t RESERVED5;
+ uint16_t RESERVED6;
+ __IO uint8_t BRCFG2;
+ uint8_t RESERVED7;
+ uint16_t RESERVED8;
+ __IO uint32_t WUDAT;
+} LPUART_Module;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CTRL;
+ __IO uint32_t CFG;
+ __IO uint32_t STS;
+} WWDG_Module;
+
+/**
+ * @brief LCD Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CTRL;
+ __IO uint32_t FCTRL;
+ __IO uint32_t STS;
+ __IO uint32_t CLR;
+ uint32_t RESERVED;
+ __IO uint32_t RAM_COM[16];
+} LCD_Module;
+
+/**
+ * @brief Touch Sensor Controller
+ */
+typedef struct
+{
+ __IO uint32_t CTRL;
+ __IO uint32_t CHNEN;
+ __IO uint32_t STS;
+ __IO uint32_t RESERVED;
+ __IO uint32_t ANA_CTRL;
+ __IO uint32_t ANA_SEL;
+ __IO uint32_t RESR[3];
+// __IO uint32_t RESR0;
+// __IO uint32_t RESR1;
+// __IO uint32_t RESR2;
+ __IO uint32_t THRHD[24];
+// __IO uint32_t THRHD0;
+// __IO uint32_t THRHD1;
+// __IO uint32_t THRHD2;
+// __IO uint32_t THRHD3;
+// __IO uint32_t THRHD4;
+// __IO uint32_t THRHD5;
+// __IO uint32_t THRHD6;
+// __IO uint32_t THRHD7;
+// __IO uint32_t THRHD8;
+// __IO uint32_t THRHD9;
+// __IO uint32_t THRHD10;
+// __IO uint32_t THRHD11;
+// __IO uint32_t THRHD12;
+// __IO uint32_t THRHD13;
+// __IO uint32_t THRHD14;
+// __IO uint32_t THRHD15;
+// __IO uint32_t THRHD16;
+// __IO uint32_t THRHD17;
+// __IO uint32_t THRHD18;
+// __IO uint32_t THRHD19;
+// __IO uint32_t THRHD20;
+// __IO uint32_t THRHD21;
+// __IO uint32_t THRHD22;
+// __IO uint32_t THRHD23;
+
+} TSC_Module;
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+#define UCID_BASE ((uint32_t)0x1FFFF7C0) /*!< UCID Address : 0x1FFF_F7C0 */
+#define UCID_LENGTH ((uint32_t)0x10) /*!< UCID Length : 16Bytes */
+#define UID_BASE ((uint32_t)0x1FFFF7F0) /*!< UID Address : 0x1FFF_F7F0 */
+#define UID_LENGTH ((uint32_t)0x0C) /*!< UID Length : 12Bytes */
+#define DBGMCU_ID_BASE ((uint32_t)0x1FFFF7FC) /*!< DBGMCU_ID Address */
+#define DBGMCU_ID_LENGTH ((uint8_t)0x04) /*!< DBGMCU_ID Length : 4 Bytes */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE (PERIPH_BASE)
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x18000)
+
+/* APB1 */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
+#define AFEC_BASE (APB1PERIPH_BASE + 0x1800)
+#define OPAMP_BASE (APB1PERIPH_BASE + 0x2000)
+#define COMP_BASE (APB1PERIPH_BASE + 0x2400)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define TSC_BASE (APB1PERIPH_BASE + 0x3400)
+#define LPRCNT_BASE (APB1PERIPH_BASE + 0x3800)
+#define TIM9_BASE (APB1PERIPH_BASE + 0x3C00)
+#define LCD_BASE (APB1PERIPH_BASE + 0x4000)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define LPTIM_BASE (APB1PERIPH_BASE + 0x4C00)
+#define LPUART_BASE (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define USB_BASE (APB1PERIPH_BASE + 0x5C00)
+#define USB_SRAM_BASE (APB1PERIPH_BASE + 0x6000)
+#define CAN_BASE (APB1PERIPH_BASE + 0x6400)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+
+/* APB2 */
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+#define SPI2_BASE (APB2PERIPH_BASE + 0x3C00)
+#define UART4_BASE (APB2PERIPH_BASE + 0x5000)
+#define UART5_BASE (APB2PERIPH_BASE + 0x5400)
+
+/* AHB */
+#define DMA_BASE (AHBPERIPH_BASE + 0x8000)
+#define DMA_CH1_BASE (AHBPERIPH_BASE + 0x8008)
+#define DMA_CH2_BASE (AHBPERIPH_BASE + 0x801C)
+#define DMA_CH3_BASE (AHBPERIPH_BASE + 0x8030)
+#define DMA_CH4_BASE (AHBPERIPH_BASE + 0x8044)
+#define DMA_CH5_BASE (AHBPERIPH_BASE + 0x8058)
+#define DMA_CH6_BASE (AHBPERIPH_BASE + 0x806C)
+#define DMA_CH7_BASE (AHBPERIPH_BASE + 0x8080)
+#define DMA_CH8_BASE (AHBPERIPH_BASE + 0x8094)
+#define ADC_BASE (AHBPERIPH_BASE + 0x8800)
+#define RCC_BASE (AHBPERIPH_BASE + 0x9000)
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0xA000) /*!< Flash registers base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+#define CRC_BASE (AHBPERIPH_BASE + 0xB000)
+#define SAC_BASE (AHBPERIPH_BASE + 0xC000)
+#define SAC_SRAM_BASE (AHBPERIPH_BASE + 0xC400)
+#define MMU_BASE (AHBPERIPH_BASE + 0xCC00)
+
+#define DBG_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+#define TIM2 ((TIM_Module*)TIM2_BASE)
+#define TIM3 ((TIM_Module*)TIM3_BASE)
+#define TIM4 ((TIM_Module*)TIM4_BASE)
+#define TIM5 ((TIM_Module*)TIM5_BASE)
+#define TIM6 ((TIM_Module*)TIM6_BASE)
+#define TIM7 ((TIM_Module*)TIM7_BASE)
+#define AFEC ((AFEC_Module*)AFEC_BASE)
+#define OPAMP ((OPAMP_Module*)OPAMP_BASE)
+#define COMP ((COMP_Module*)COMP_BASE)
+#define RTC ((RTC_Module*)RTC_BASE)
+#define WWDG ((WWDG_Module*)WWDG_BASE)
+#define IWDG ((IWDG_Module*)IWDG_BASE)
+#define TSC ((TSC_Module*)TSC_BASE)
+#define LPRCNT ((LPRCNT_Module*)LPRCNT_BASE)
+#define TIM9 ((TIM_Module*)TIM9_BASE)
+#define LCD ((LCD_Module*)LCD_BASE)
+#define USART2 ((USART_Module*)USART2_BASE)
+#define USART3 ((USART_Module*)USART3_BASE)
+#define LPTIM ((LPTIM_Module*)LPTIM_BASE)
+#define LPUART ((LPUART_Module*)LPUART_BASE)
+#define I2C1 ((I2C_Module*)I2C1_BASE)
+#define I2C2 ((I2C_Module*)I2C2_BASE)
+#define USB ((USB_Module*)USB_BASE)
+#define CAN ((CAN_Module*)CAN_BASE)
+#define PWR ((PWR_Module*)PWR_BASE)
+#define DAC ((DAC_Module*)DAC_BASE)
+#define AFIO ((AFIO_Module*)AFIO_BASE)
+#define EXTI ((EXTI_Module*)EXTI_BASE)
+#define GPIOA ((GPIO_Module*)GPIOA_BASE)
+#define GPIOB ((GPIO_Module*)GPIOB_BASE)
+#define GPIOC ((GPIO_Module*)GPIOC_BASE)
+#define GPIOD ((GPIO_Module*)GPIOD_BASE)
+#define TIM1 ((TIM_Module*)TIM1_BASE)
+#define SPI1 ((SPI_Module*)SPI1_BASE)
+#define TIM8 ((TIM_Module*)TIM8_BASE)
+#define USART1 ((USART_Module*)USART1_BASE)
+#define SPI2 ((SPI_Module*)SPI2_BASE)
+#define UART4 ((USART_Module*)UART4_BASE)
+#define UART5 ((USART_Module*)UART5_BASE)
+#define DMA ((DMA_Module*)DMA_BASE)
+#define DMA_CH1 ((DMA_ChannelType*)DMA_CH1_BASE)
+#define DMA_CH2 ((DMA_ChannelType*)DMA_CH2_BASE)
+#define DMA_CH3 ((DMA_ChannelType*)DMA_CH3_BASE)
+#define DMA_CH4 ((DMA_ChannelType*)DMA_CH4_BASE)
+#define DMA_CH5 ((DMA_ChannelType*)DMA_CH5_BASE)
+#define DMA_CH6 ((DMA_ChannelType*)DMA_CH6_BASE)
+#define DMA_CH7 ((DMA_ChannelType*)DMA_CH7_BASE)
+#define DMA_CH8 ((DMA_ChannelType*)DMA_CH8_BASE)
+#define ADC ((ADC_Module*)ADC_BASE)
+#define RCC ((RCC_Module*)RCC_BASE)
+#define FLASH ((FLASH_Module*)FLASH_R_BASE)
+#define OBT ((OB_Module*)OB_BASE)
+#define CRC ((CRC_Module*)CRC_BASE)
+
+#define DBG ((DBG_Module*)DBG_BASE)
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRC_CRC32DAT register *********************/
+#define CRC32_DAT_DAT ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/******************* Bit definition for CRC_CRC32IDAT register ********************/
+#define CRC32_IDAT_IDAT ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CRC32CTRL register ********************/
+#define CRC32_CTRL_RESET ((uint8_t)0x01) /*!< RESET bit */
+
+/******************** Bit definition for CRC16_CR register ********************/
+#define CRC16_CTRL_LITTLE ((uint8_t)0x02)
+#define CRC16_CTRL_BIG ((uint8_t)0xFD)
+
+#define CRC16_CTRL_RESET ((uint8_t)0x04)
+#define CRC16_CTRL_NO_RESET ((uint8_t)0xFB)
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CTRL1 register ********************/
+#define PWR_CTRL1_LPMSEL ((uint16_t)0x0007) /*!< no low power mode entered */
+#define PWR_CTRL1_STOP2 ((uint16_t)0x0002) /*!< stop2 mode */
+#define PWR_CTRL1_STANDBY ((uint16_t)0x0003) /*!< standby mode */
+
+
+#define PWR_CTRL1_DRBP ((uint16_t)0x0100) /*!< Access to RTC and Backup registers enabled */
+
+#define PWR_CTRL1_MRSEL ((uint16_t)0x0600) /*!< vddd Range Mask */
+#define PWR_CTRL1_MRSEL_bit0 ((uint16_t)0x0200) /*!< vddd Range MRSEL bit0 */
+#define PWR_CTRL1_MRSEL_bit1 ((uint16_t)0x0400) /*!< vddd Range MRSEL bit1 */
+#define PWR_CTRL1_MRSEL2 ((uint16_t)0x0400) /*!< vddd Range2=1.0 V */
+#define PWR_CTRL1_MRSEL1 ((uint16_t)0x0600) /*!< vddd Range1=1.1 V */
+#define PWR_CTRL1_LPREN ((uint16_t)0x4000) /*!< When this bit is set, MR is turned off and LPR is used to run the main power domain. */
+#define PWR_CTRL1_MRSELMASK ((uint16_t)0x0600) /*!< MR voltage mask */
+/******************** Bit definition for PWR_CTRL2 register ********************/
+#define PWR_CTRL2_PVDEN ((uint16_t)0x0001) /*!< Power voltage detector enable */
+#define PWR_CTRL2_PLS1 ((uint16_t)0x0000) /*!< voltage threshold around 2.1 V */
+#define PWR_CTRL2_PLS2 ((uint16_t)0x0002) /*!< voltage threshold around 2.25 V */
+#define PWR_CTRL2_PLS3 ((uint16_t)0x0004) /*!< voltage threshold around 2.4 V */
+#define PWR_CTRL2_PLS4 ((uint16_t)0x0006) /*!< voltage threshold around 2.55 V */
+#define PWR_CTRL2_PLS5 ((uint16_t)0x0008) /*!< voltage threshold around 2.7 V */
+#define PWR_CTRL2_PLS6 ((uint16_t)0x000A) /*!< voltage threshold around 2.85 V */
+#define PWR_CTRL2_PLS7 ((uint16_t)0x000C) /*!< voltage threshold around 2.95 V */
+#define PWR_CTRL2_PLS8 ((uint16_t)0x000E) /*!< external input analog voltage PVD_IN (compared internally to VREFINT) */
+
+#define PWR_CTRL2_PVDFLTEN ((uint16_t)0x0010) /*!< Power voltage detector filter enable */
+
+
+/******************** Bit definition for PWR_CTRL3 register ********************/
+#define PWR_CTRL3_WKUP0EN ((uint16_t)0x0001) /*!< When this bit is set, WKUP0 pin is enable and triggers a wakeup from standby mode. */
+#define PWR_CTRL3_WKUP1EN ((uint16_t)0x0002) /*!< When this bit is set, WKUP1 pin is enable and triggers a wakeup from standby mode. */
+#define PWR_CTRL3_WKUP2EN ((uint16_t)0x0004) /*!< When this bit is set, WKUP2 pin is enable and triggers a wakeup from standby mode. */
+#define PWR_CTRL3_WKUP0PS ((uint16_t)0x0010) /*!< falling edge wake up */
+#define PWR_CTRL3_WKUP1PS ((uint16_t)0x0020) /*!< falling edge wake up */
+#define PWR_CTRL3_WKUP2PS ((uint16_t)0x0040) /*!< falling edge wake up */
+#define PWR_CTRL3_BGDTLPR ((uint16_t)0x0100) /*!< BANDGAP/BG_Buffer/IBIAS duty on in LPRUN */
+#define PWR_CTRL3_BGDTSTP2 ((uint16_t)0x0200) /*!< BANDGAP/BG_Buffer/IBIAS duty on in stop2 */
+#define PWR_CTRL3_BGDTSTBY ((uint16_t)0x0400) /*!< BANDGAP/BG_Buffer/IBIAS duty on in standby */
+#define PWR_CTRL3_RAM1RET ((uint16_t)0x1000) /*!< SRAM1 is powered by the LPR in stop2 mode */
+#define PWR_CTRL3_RAM2RET ((uint16_t)0x2000) /*!< SRAM2 is powered by the LPR in standby mode */
+#define PWR_CTRL3_IWKUPLEN ((uint16_t)0x4000) /*!< internal wakeup line enable */
+
+#define PWR_CTRL3_PBDTLPR ((uint32_t)0x10000) /*!< PVDBOR duty on in LP RUN */
+#define PWR_CTRL3_PBDTSTP2 ((uint32_t)0x20000) /*!< PVDBOR duty on in STOP2 */
+#define PWR_CTRL3_PBDTSTBY ((uint32_t)0x40000) /*!< PVDBOR is iduty on standby */
+#define PWR_CTRL3_PSTSTBY ((uint32_t)0x100000) /*!< PAD in HI-Z state */
+#define PWR_CTRL3_PSTSTP2 ((uint32_t)0x200000) /*!< PAD in HI-Z state */
+
+#define PWR_CTRL3_RAMRETMASK ((uint16_t)0x3000) /*!< SRAM1 and SRAM2 ENABLE */
+#define PWR_CTRL1_LPMSELMASK ((uint16_t)0x0007) /*!< Low power mode selection */
+#define PWR_CTRL2_PLSMASK ((uint16_t)0x000E) /*!< Low power mode selection */
+/******************** Bit definition for PWR_STS1 register ********************/
+#define PWR_STS1_WKUPF0 ((uint16_t)0x0001) /*!< This bit is set when a wakeup event is detected on wakeup pin, WKUP0. */
+#define PWR_STS1_WKUPF1 ((uint16_t)0x0002) /*!< This bit is set when a wakeup event is detected on wakeup pin, WKUP1. */
+#define PWR_STS1_WKUPF2 ((uint16_t)0x0004) /*!< This bit is set when a wakeup event is detected on wakeup pin, WKUP2. */
+#define PWR_STS1_STBYF ((uint16_t)0x0100) /*!< the device entered the standby mode */
+#define PWR_STS1_IWKUPF ((uint16_t)0x8000) /*!< This bit is set when a wakeup is detected on the internal wakeup line. */
+
+/******************** Bit definition for PWR_STS2 register ********************/
+#define PWR_STS2_LPRUNF ((uint16_t)0x0001) /*!< MCU is in low power run mode */
+#define PWR_STS2_MRF ((uint16_t)0x0002) /*!< voltage scaling ready */
+#define PWR_STS2_PVDO ((uint16_t)0x0004) /*!< Power voltage detector output */
+
+/******************** Bit definition for PWR_STSCLR register ********************/
+#define PWR_STSCLR_CLRWKUP0 ((uint16_t)0x0001) /*!< Setting this bit clears the WKPF0 flag in the PWR_STS1 register */
+#define PWR_STSCLR_CLRWKUP1 ((uint16_t)0x0002) /*!< Setting this bit clears the WKPF1 flag in the PWR_STS1 register */
+#define PWR_STSCLR_CLRWKUP2 ((uint16_t)0x0004) /*!< Setting this bit clears the WKPF2 flag in the PWR_STS1 register */
+#define PWR_STSCLR_CLRSTBY ((uint16_t)0x0100) /*!< Setting this bit clears the SBF flag in the PWR_STS1 register */
+
+
+
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for RCC_CTRL register ********************/
+#define RCC_CTRL_HSIEN ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
+#define RCC_CTRL_HSIRDF ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
+#define RCC_CTRL_HSITRIM ((uint32_t)0x0000007C) /*!< Internal High Speed clock trimming */
+#define RCC_CTRL_HSICAL ((uint32_t)0x0000FF80) /*!< Internal High Speed clock Calibration */
+#define RCC_CTRL_HSEEN ((uint32_t)0x00010000) /*!< External High Speed clock enable */
+#define RCC_CTRL_HSERDF ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
+#define RCC_CTRL_HSEBP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
+#define RCC_CTRL_CLKSSEN ((uint32_t)0x00080000) /*!< Clock Security System enable */
+#define RCC_CTRL_PLLEN ((uint32_t)0x01000000) /*!< PLL enable */
+#define RCC_CTRL_PLLRDF ((uint32_t)0x02000000) /*!< PLL clock ready flag */
+
+/******************* Bit definition for RCC_CFG register *******************/
+/*!< SW configuration */
+#define RCC_CFG_SCLKSW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFG_SCLKSW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFG_SCLKSW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFG_SCLKSW_MSI ((uint32_t)0x00000000) /*!< MSI selected as system clock */
+#define RCC_CFG_SCLKSW_HSI ((uint32_t)0x00000001) /*!< HSI selected as system clock */
+#define RCC_CFG_SCLKSW_HSE ((uint32_t)0x00000002) /*!< HSE selected as system clock */
+#define RCC_CFG_SCLKSW_PLL ((uint32_t)0x00000003) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFG_SCLKSTS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFG_SCLKSTS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFG_SCLKSTS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFG_SCLKSTS_MSI ((uint32_t)0x00000000) /*!< MSI oscillator used as system clock */
+#define RCC_CFG_SCLKSTS_HSI ((uint32_t)0x00000004) /*!< HSI oscillator used as system clock */
+#define RCC_CFG_SCLKSTS_HSE ((uint32_t)0x00000008) /*!< HSE oscillator used as system clock */
+#define RCC_CFG_SCLKSTS_PLL ((uint32_t)0x0000000C) /*!< PLL used as system clock */
+
+/*!< AHBPRES configuration */
+#define RCC_CFG_AHBPRES ((uint32_t)0x000000F0) /*!< AHBPRES[3:0] bits (AHB prescaler) */
+#define RCC_CFG_AHBPRES_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFG_AHBPRES_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFG_AHBPRES_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFG_AHBPRES_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFG_AHBPRES_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFG_AHBPRES_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFG_AHBPRES_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFG_AHBPRES_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFG_AHBPRES_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFG_AHBPRES_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFG_AHBPRES_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFG_AHBPRES_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFG_AHBPRES_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< APB1PRES configuration */
+#define RCC_CFG_APB1PRES ((uint32_t)0x00000700) /*!< APB1PRES[2:0] bits (APB1 prescaler) */
+#define RCC_CFG_APB1PRES_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_CFG_APB1PRES_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define RCC_CFG_APB1PRES_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+#define RCC_CFG_APB1PRES_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFG_APB1PRES_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFG_APB1PRES_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFG_APB1PRES_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFG_APB1PRES_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< APB2PRES configuration */
+#define RCC_CFG_APB2PRES ((uint32_t)0x00003800) /*!< APB2PRES[2:0] bits (APB2 prescaler) */
+#define RCC_CFG_APB2PRES_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define RCC_CFG_APB2PRES_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+#define RCC_CFG_APB2PRES_2 ((uint32_t)0x00002000) /*!< Bit 2 */
+
+#define RCC_CFG_APB2PRES_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFG_APB2PRES_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFG_APB2PRES_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFG_APB2PRES_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFG_APB2PRES_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+/*!< PLLSRC configuration */
+#define RCC_CFG_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
+
+#define RCC_CFG_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI clock selected as PLL entry clock source */
+#define RCC_CFG_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */
+
+/*!< PLLXTPRE configuration */
+#define RCC_CFG_PLLHSEPRES ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
+
+#define RCC_CFG_PLLHSEPRES_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
+#define RCC_CFG_PLLHSEPRES_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFG_PLLMULFCT ((uint32_t)0x083C0000) /*!< PLLMUL[4:0] bits (PLL multiplication factor) */
+#define RCC_CFG_PLLMULFCT_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFG_PLLMULFCT_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define RCC_CFG_PLLMULFCT_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+#define RCC_CFG_PLLMULFCT_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+#define RCC_CFG_PLLMULFCT_4 ((uint32_t)0x08000000) /*!< Bit 4 */
+
+#define RCC_CFG_PLLMULFCT2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFG_PLLMULFCT3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
+#define RCC_CFG_PLLMULFCT4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
+#define RCC_CFG_PLLMULFCT5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
+#define RCC_CFG_PLLMULFCT6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
+#define RCC_CFG_PLLMULFCT7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
+#define RCC_CFG_PLLMULFCT8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
+#define RCC_CFG_PLLMULFCT9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
+#define RCC_CFG_PLLMULFCT10 ((uint32_t)0x00200000) /*!< PLL input clock*10 */
+#define RCC_CFG_PLLMULFCT11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
+#define RCC_CFG_PLLMULFCT12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
+#define RCC_CFG_PLLMULFCT13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
+#define RCC_CFG_PLLMULFCT14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
+#define RCC_CFG_PLLMULFCT15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
+#define RCC_CFG_PLLMULFCT16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
+#define RCC_CFG_PLLMULFCT16N ((uint32_t)0x003C0000) /*!< PLL input clock*16 */
+#define RCC_CFG_PLLMULFCT17 ((uint32_t)0x08000000) /*!< PLL input clock*17 */
+#define RCC_CFG_PLLMULFCT18 ((uint32_t)0x08040000) /*!< PLL input clock*18 */
+#define RCC_CFG_PLLMULFCT19 ((uint32_t)0x08080000) /*!< PLL input clock*19 */
+#define RCC_CFG_PLLMULFCT20 ((uint32_t)0x080C0000) /*!< PLL input clock*20 */
+#define RCC_CFG_PLLMULFCT21 ((uint32_t)0x08100000) /*!< PLL input clock*21 */
+#define RCC_CFG_PLLMULFCT22 ((uint32_t)0x08140000) /*!< PLL input clock*22 */
+#define RCC_CFG_PLLMULFCT23 ((uint32_t)0x08180000) /*!< PLL input clock*23 */
+#define RCC_CFG_PLLMULFCT24 ((uint32_t)0x081C0000) /*!< PLL input clock*24 */
+#define RCC_CFG_PLLMULFCT25 ((uint32_t)0x08200000) /*!< PLL input clock*25 */
+#define RCC_CFG_PLLMULFCT26 ((uint32_t)0x08240000) /*!< PLL input clock*26 */
+#define RCC_CFG_PLLMULFCT27 ((uint32_t)0x08280000) /*!< PLL input clock*27 */
+#define RCC_CFG_PLLMULFCT28 ((uint32_t)0x082C0000) /*!< PLL input clock*28 */
+#define RCC_CFG_PLLMULFCT29 ((uint32_t)0x08300000) /*!< PLL input clock*29 */
+#define RCC_CFG_PLLMULFCT30 ((uint32_t)0x08340000) /*!< PLL input clock*30 */
+#define RCC_CFG_PLLMULFCT31 ((uint32_t)0x08380000) /*!< PLL input clock*31 */
+#define RCC_CFG_PLLMULFCT32 ((uint32_t)0x083C0000) /*!< PLL input clock*32 */
+
+/*!< USBPRES configuration */
+#define RCC_CFG_USBPRES ((uint32_t)0x00C00000) /*!< USB Device prescaler */
+#define RCC_CFG_USBPRES_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define RCC_CFG_USBPRES_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define RCC_CFG_USBPRES_PLLDIV1_5 ((uint32_t)0x00000000) /*!< PLL clock is divided by 1.5 */
+#define RCC_CFG_USBPRES_PLLDIV1 ((uint32_t)0x00400000) /*!< PLL clock is not divided */
+#define RCC_CFG_USBPRES_PLLDIV2 ((uint32_t)0x00800000) /*!< PLL clock is divided by 2 */
+#define RCC_CFG_USBPRES_PLLDIV3 ((uint32_t)0x00C00000) /*!< PLL clock is divided by 3 */
+
+/*!< MCO configuration */
+#define RCC_CFG_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define RCC_CFG_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define RCC_CFG_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define RCC_CFG_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define RCC_CFG_MCO_NOCLK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFG_MCO_LSI ((uint32_t)0x01000000) /*!< LSI clock selected as MCO source */
+#define RCC_CFG_MCO_LSE ((uint32_t)0x02000000) /*!< LSE clock selected as MCO source */
+#define RCC_CFG_MCO_MSI ((uint32_t)0x03000000) /*!< MSI clock selected as MCO source */
+#define RCC_CFG_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFG_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFG_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFG_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock selected as MCO source */
+
+/*!< MCOPRE configuration */
+#define RCC_CFG_MCOPRES ((uint32_t)0xF0000000) /*!< MCOPRE[3:0] bits ( PLL prescaler set and cleared by
+ software to generate MCOPRE clock.) */
+#define RCC_CFG_MCOPRES_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define RCC_CFG_MCOPRES_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+#define RCC_CFG_MCOPRES_2 ((uint32_t)0x40000000) /*!< Bit 2 */
+#define RCC_CFG_MCOPRES_3 ((uint32_t)0x80000000) /*!< Bit 3 */
+
+#define RCC_CFG_MCOPRES_PLLDIV1 ((uint32_t)0x00000000) /*!< PLL clock is not divided */
+#define RCC_CFG_MCOPRES_PLLDIV2 ((uint32_t)0x10000000) /*!< PLL clock is divided by 2 */
+#define RCC_CFG_MCOPRES_PLLDIV3 ((uint32_t)0x20000000) /*!< PLL clock is divided by 3 */
+#define RCC_CFG_MCOPRES_PLLDIV4 ((uint32_t)0x30000000) /*!< PLL clock is divided by 4 */
+#define RCC_CFG_MCOPRES_PLLDIV5 ((uint32_t)0x40000000) /*!< PLL clock is divided by 5 */
+#define RCC_CFG_MCOPRES_PLLDIV6 ((uint32_t)0x50000000) /*!< PLL clock is divided by 6 */
+#define RCC_CFG_MCOPRES_PLLDIV7 ((uint32_t)0x60000000) /*!< PLL clock is divided by 7 */
+#define RCC_CFG_MCOPRES_PLLDIV8 ((uint32_t)0x70000000) /*!< PLL clock is divided by 8 */
+#define RCC_CFG_MCOPRES_PLLDIV9 ((uint32_t)0x80000000) /*!< PLL clock is divided by 9 */
+#define RCC_CFG_MCOPRES_PLLDIV10 ((uint32_t)0x90000000) /*!< PLL clock is divided by 10 */
+#define RCC_CFG_MCOPRES_PLLDIV11 ((uint32_t)0xA0000000) /*!< PLL clock is divided by 11 */
+#define RCC_CFG_MCOPRES_PLLDIV12 ((uint32_t)0xB0000000) /*!< PLL clock is divided by 12 */
+#define RCC_CFG_MCOPRES_PLLDIV13 ((uint32_t)0xC0000000) /*!< PLL clock is divided by 13 */
+#define RCC_CFG_MCOPRES_PLLDIV14 ((uint32_t)0xD0000000) /*!< PLL clock is divided by 14 */
+#define RCC_CFG_MCOPRES_PLLDIV15 ((uint32_t)0xE0000000) /*!< PLL clock is divided by 15 */
+#define RCC_CFG_MCOPRES_PLLDIV16 ((uint32_t)0xF0000000) /*!< PLL clock is divided by 16 */
+
+/*!<****************** Bit definition for RCC_CLKINT register ********************/
+#define RCC_CLKINT_LSIRDIF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
+#define RCC_CLKINT_LSERDIF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
+#define RCC_CLKINT_HSIRDIF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
+#define RCC_CLKINT_HSERDIF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
+#define RCC_CLKINT_PLLRDIF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
+#define RCC_CLKINT_BORIF ((uint32_t)0x00000020) /*!< BOR Interrupt flag */
+#define RCC_CLKINT_MSIRDIF ((uint32_t)0x00000040) /*!< MSI Ready Interrupt flag */
+#define RCC_CLKINT_CLKSSIF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
+#define RCC_CLKINT_LSIRDIEN ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
+#define RCC_CLKINT_LSERDIEN ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
+#define RCC_CLKINT_HSIRDIEN ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
+#define RCC_CLKINT_HSERDIEN ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
+#define RCC_CLKINT_PLLRDIEN ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
+#define RCC_CLKINT_BORIEN ((uint32_t)0x00002000) /*!< BOR Interrupt Enable */
+#define RCC_CLKINT_MSIRDIEN ((uint32_t)0x00004000) /*!< MSI Ready Interrupt Enable */
+#define RCC_CLKINT_MSIRDICLR ((uint32_t)0x00008000) /*!< MSI Ready Interrupt Clear */
+#define RCC_CLKINT_LSIRDICLR ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
+#define RCC_CLKINT_LSERDICLR ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
+#define RCC_CLKINT_HSIRDICLR ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
+#define RCC_CLKINT_HSERDICLR ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
+#define RCC_CLKINT_PLLRDICLR ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
+#define RCC_CLKINT_BORICLR ((uint32_t)0x00200000) /*!< BOR Interrupt Clear */
+#define RCC_CLKINT_CLKSSICLR ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
+#define RCC_CLKINT_LSESSIF ((uint32_t)0x01000000) /*!< LSE Security System Interrupt flag */
+#define RCC_CLKINT_LSESSIEN ((uint32_t)0x02000000) /*!< LSE ecurity System Interrupt Enable */
+#define RCC_CLKINT_LSESSICLR ((uint32_t)0x04000000) /*!< LSE ecurity System Interrupt Clear */
+
+/***************** Bit definition for RCC_APB2PRST register *****************/
+#define RCC_APB2PRST_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */
+#define RCC_APB2PRST_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */
+#define RCC_APB2PRST_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */
+#define RCC_APB2PRST_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */
+#define RCC_APB2PRST_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */
+#define RCC_APB2PRST_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */
+#define RCC_APB2PRST_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */
+#define RCC_APB2PRST_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */
+#define RCC_APB2PRST_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
+#define RCC_APB2PRST_UART4RST ((uint32_t)0x00020000) /*!< UART4 reset */
+#define RCC_APB2PRST_UART5RST ((uint32_t)0x00040000) /*!< UART5 reset */
+#define RCC_APB2PRST_SPI2RST ((uint32_t)0x00080000) /*!< SPI2 reset */
+
+/***************** Bit definition for RCC_APB1PRST register *****************/
+#define RCC_APB1PRST_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
+#define RCC_APB1PRST_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
+#define RCC_APB1PRST_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
+#define RCC_APB1PRST_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
+#define RCC_APB1PRST_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
+#define RCC_APB1PRST_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
+#define RCC_APB1PRST_COMPRST ((uint32_t)0x00000040) /*!< COMP reset */
+#define RCC_APB1PRST_TIM9RST ((uint32_t)0x00000200) /*!< Timer 9 reset */
+#define RCC_APB1PRST_TSCRST ((uint32_t)0x00000400) /*!< TSC reset */
+#define RCC_APB1PRST_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
+#define RCC_APB1PRST_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
+#define RCC_APB1PRST_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
+#define RCC_APB1PRST_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
+#define RCC_APB1PRST_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
+#define RCC_APB1PRST_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */
+#define RCC_APB1PRST_UCDRRST ((uint32_t)0x01000000) /*!< UCDR reset */
+#define RCC_APB1PRST_CANRST ((uint32_t)0x02000000) /*!< CAN reset */
+#define RCC_APB1PRST_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
+#define RCC_APB1PRST_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
+#define RCC_APB1PRST_OPARST ((uint32_t)0x80000000) /*!< OPA interface reset */
+
+/****************** Bit definition for RCC_AHBPCLKEN register ******************/
+#define RCC_AHBPCLKEN_DMAEN ((uint32_t)0x00000001) /*!< DMA clock enable */
+#define RCC_AHBPCLKEN_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
+#define RCC_AHBPCLKEN_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
+#define RCC_AHBPCLKEN_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
+#define RCC_AHBPCLKEN_RNGCEN ((uint32_t)0x00000200) /*!< RNGC clock enable */
+#define RCC_AHBPCLKEN_SACEN ((uint32_t)0x00000800) /*!< SAC clock enable */
+#define RCC_AHBPCLKEN_ADCEN ((uint32_t)0x00001000) /*!< ADC clock enable */
+
+/****************** Bit definition for RCC_APB2PCLKEN register *****************/
+#define RCC_APB2PCLKEN_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */
+#define RCC_APB2PCLKEN_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */
+#define RCC_APB2PCLKEN_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */
+#define RCC_APB2PCLKEN_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */
+#define RCC_APB2PCLKEN_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */
+#define RCC_APB2PCLKEN_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */
+#define RCC_APB2PCLKEN_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
+#define RCC_APB2PCLKEN_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */
+#define RCC_APB2PCLKEN_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
+#define RCC_APB2PCLKEN_UART4EN ((uint32_t)0x00020000) /*!< UART4 clock enable */
+#define RCC_APB2PCLKEN_UART5EN ((uint32_t)0x00040000) /*!< UART5 clock enable */
+#define RCC_APB2PCLKEN_SPI2EN ((uint32_t)0x00080000) /*!< SPI2 clock enable */
+
+/***************** Bit definition for RCC_APB1PCLKEN register ******************/
+#define RCC_APB1PCLKEN_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
+#define RCC_APB1PCLKEN_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
+#define RCC_APB1PCLKEN_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
+#define RCC_APB1PCLKEN_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */
+#define RCC_APB1PCLKEN_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
+#define RCC_APB1PCLKEN_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
+#define RCC_APB1PCLKEN_COMPEN ((uint32_t)0x00000040) /*!< COMP clock enable */
+#define RCC_APB1PCLKEN_COMPFILTEN ((uint32_t)0x00000080) /*!< COMPFILT clock enable */
+#define RCC_APB1PCLKEN_AFECEN ((uint32_t)0x00000100) /*!< AFEC clock enable */
+#define RCC_APB1PCLKEN_TIM9EN ((uint32_t)0x00000200) /*!< Timer 9 clock enable */
+#define RCC_APB1PCLKEN_TSCEN ((uint32_t)0x00000400) /*!< TSC clock enable */
+#define RCC_APB1PCLKEN_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
+#define RCC_APB1PCLKEN_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
+#define RCC_APB1PCLKEN_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
+#define RCC_APB1PCLKEN_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
+#define RCC_APB1PCLKEN_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
+#define RCC_APB1PCLKEN_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */
+#define RCC_APB1PCLKEN_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
+#define RCC_APB1PCLKEN_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
+#define RCC_APB1PCLKEN_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
+#define RCC_APB1PCLKEN_OPAMPEN ((uint32_t)0x80000000) /*!< OPAMP interface clock enable */
+
+/******************* Bit definition for RCC_LDCTRL register *******************/
+#define RCC_LDCTRL_LSEEN ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
+#define RCC_LDCTRL_LSERD ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
+#define RCC_LDCTRL_LSEBP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
+
+#define RCC_LDCTRL_LSECLKSSEN ((uint32_t)0x00000008) /*!< LSE Security System enable */
+#define RCC_LDCTRL_LSECLKSSF ((uint32_t)0x00000010) /*!< LSE Security System failure detection */
+#define RCC_LDCTRL_LSXSEL ((uint32_t)0x00000020) /*!< LSXSEL bits (TSC/LPRCNT clock source selection) */
+
+#define RCC_LDCTRL_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_LDCTRL_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_LDCTRL_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< RTC congiguration */
+#define RCC_LDCTRL_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_LDCTRL_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_LDCTRL_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_LDCTRL_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 32 used as RTC clock */
+
+#define RCC_LDCTRL_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
+#define RCC_LDCTRL_LDSFTRST ((uint32_t)0x00010000) /*!< Low power domain software reset */
+#define RCC_LDCTRL_BORRSTF ((uint32_t)0x10000000) /*!< BOR reset flag */
+#define RCC_LDCTRL_LDEMCRSTF ((uint32_t)0x40000000) /*!< Low power EMC reset flag */
+
+/******************* Bit definition for RCC_CTRLSTS register ********************/
+#define RCC_CTRLSTS_LSIEN ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
+#define RCC_CTRLSTS_LSIRD ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
+#define RCC_CTRLSTS_MSIEN ((uint32_t)0x00000004) /*!< Internal Multi Speed oscillator enable */
+#define RCC_CTRLSTS_MSIRD ((uint32_t)0x00000008) /*!< Internal Multi Speed oscillator Ready */
+
+#define RCC_CTRLSTS_MSIRANGE ((uint32_t)0x00000070) /*!< Internal Multi Speed oscillator Clock Range */
+#define RCC_CTRLSTS_MSIRANGE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CTRLSTS_MSIRANGE_1 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define RCC_CTRLSTS_MSIRANGE_2 ((uint32_t)0x00000040) /*!< Bit 0 */
+
+#define RCC_CTRLSTS_MSIRANGE_100KHz ((uint32_t)0x00000000) /*!< Internal Multi Speed oscillator output 100KHz */
+#define RCC_CTRLSTS_MSIRANGE_200KHz ((uint32_t)0x00000010) /*!< Internal Multi Speed oscillator output 200KHz */
+#define RCC_CTRLSTS_MSIRANGE_400KHz ((uint32_t)0x00000020) /*!< Internal Multi Speed oscillator output 400KHz */
+#define RCC_CTRLSTS_MSIRANGE_800KHz ((uint32_t)0x00000030) /*!< Internal Multi Speed oscillator output 800KHz */
+#define RCC_CTRLSTS_MSIRANGE_1MHz ((uint32_t)0x00000040) /*!< Internal Multi Speed oscillator output 1MHz */
+#define RCC_CTRLSTS_MSIRANGE_2MHz ((uint32_t)0x00000050) /*!< Internal Multi Speed oscillator output 2MHz */
+#define RCC_CTRLSTS_MSIRANGE_4MHz ((uint32_t)0x00000060) /*!< Internal Multi Speed oscillator output 4MHz */
+
+#define RCC_CTRLSTS_MSICAL ((uint32_t)0x00007F80) /*!< Internal Multi Speed clock Calibration */
+#define RCC_CTRLSTS_MSITRIM ((uint32_t)0x007F8000) /*!< Internal Multi Speed clock trimming */
+#define RCC_CTRLSTS_RAMRSTF ((uint32_t)0x00800000) /*!< RAM reset flag */
+#define RCC_CTRLSTS_RMRSTF ((uint32_t)0x01000000) /*!< Remove reset flag */
+#define RCC_CTRLSTS_MMURSTF ((uint32_t)0x02000000) /*!< MMU reset flag */
+#define RCC_CTRLSTS_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
+#define RCC_CTRLSTS_PORRSTF ((uint32_t)0x08000000) /*!< POR reset flag */
+#define RCC_CTRLSTS_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
+#define RCC_CTRLSTS_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
+#define RCC_CTRLSTS_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
+#define RCC_CTRLSTS_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
+
+/******************* Bit definition for RCC_AHBPRST register ****************/
+#define RCC_AHBRST_RNGCRST ((uint32_t)0x00000200) /*!< RNGC reset */
+#define RCC_AHBRST_SACRST ((uint32_t)0x00000800) /*!< SAC reset */
+#define RCC_AHBRST_ADCRST ((uint32_t)0x00001000) /*!< ADC reset */
+
+/******************* Bit definition for RCC_CFG2 register ******************/
+/*!< ADCHPRE configuration */
+#define RCC_CFG2_ADCHPRES ((uint32_t)0x0000000F) /*!< ADCHPRE[3:0] bits */
+#define RCC_CFG2_ADCHPRES_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFG2_ADCHPRES_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RCC_CFG2_ADCHPRES_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RCC_CFG2_ADCHPRES_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define RCC_CFG2_ADCHPRES_DIV1 ((uint32_t)0x00000000) /*!< HCLK clock divided by 1 */
+#define RCC_CFG2_ADCHPRES_DIV2 ((uint32_t)0x00000001) /*!< HCLK clock divided by 2 */
+#define RCC_CFG2_ADCHPRES_DIV4 ((uint32_t)0x00000002) /*!< HCLK clock divided by 4 */
+#define RCC_CFG2_ADCHPRES_DIV6 ((uint32_t)0x00000003) /*!< HCLK clock divided by 6 */
+#define RCC_CFG2_ADCHPRES_DIV8 ((uint32_t)0x00000004) /*!< HCLK clock divided by 8 */
+#define RCC_CFG2_ADCHPRES_DIV10 ((uint32_t)0x00000005) /*!< HCLK clock divided by 10 */
+#define RCC_CFG2_ADCHPRES_DIV12 ((uint32_t)0x00000006) /*!< HCLK clock divided by 12 */
+#define RCC_CFG2_ADCHPRES_DIV16 ((uint32_t)0x00000007) /*!< HCLK clock divided by 16 */
+#define RCC_CFG2_ADCHPRES_DIV32 ((uint32_t)0x00000008) /*!< HCLK clock divided by 32 */
+#define RCC_CFG2_ADCHPRES_OTHERS ((uint32_t)0x00000008) /*!< HCLK clock divided by 32 */
+
+/*!< ADCPLLPRES configuration */
+#define RCC_CFG2_ADCPLLPRES ((uint32_t)0x000001F0) /*!< ADCPLLPRES[4:0] bits */
+#define RCC_CFG2_ADCPLLPRES_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFG2_ADCPLLPRES_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFG2_ADCPLLPRES_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFG2_ADCPLLPRES_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+#define RCC_CFG2_ADCPLLPRES_4 ((uint32_t)0x00000100) /*!< Bit 4 */
+
+#define RCC_CFG2_ADCPLLCLK_DISABLE ((uint32_t)0xFFFFFEFF) /*!< ADC PLL clock Disable */
+#define RCC_CFG2_ADCPLLPRES_DIV1 ((uint32_t)0x00000100) /*!< PLL clock divided by 1 */
+#define RCC_CFG2_ADCPLLPRES_DIV2 ((uint32_t)0x00000110) /*!< PLL clock divided by 2 */
+#define RCC_CFG2_ADCPLLPRES_DIV4 ((uint32_t)0x00000120) /*!< PLL clock divided by 4 */
+#define RCC_CFG2_ADCPLLPRES_DIV6 ((uint32_t)0x00000130) /*!< PLL clock divided by 6 */
+#define RCC_CFG2_ADCPLLPRES_DIV8 ((uint32_t)0x00000140) /*!< PLL clock divided by 8 */
+#define RCC_CFG2_ADCPLLPRES_DIV10 ((uint32_t)0x00000150) /*!< PLL clock divided by 10 */
+#define RCC_CFG2_ADCPLLPRES_DIV12 ((uint32_t)0x00000160) /*!< PLL clock divided by 12 */
+#define RCC_CFG2_ADCPLLPRES_DIV16 ((uint32_t)0x00000170) /*!< PLL clock divided by 16 */
+#define RCC_CFG2_ADCPLLPRES_DIV32 ((uint32_t)0x00000180) /*!< PLL clock divided by 32 */
+#define RCC_CFG2_ADCPLLPRES_DIV64 ((uint32_t)0x00000190) /*!< PLL clock divided by 64 */
+#define RCC_CFG2_ADCPLLPRES_DIV128 ((uint32_t)0x000001A0) /*!< PLL clock divided by 128 */
+#define RCC_CFG2_ADCPLLPRES_DIV256 ((uint32_t)0x000001B0) /*!< PLL clock divided by 256 */
+#define RCC_CFG2_ADCPLLPRES_DIV256N ((uint32_t)0x000001C0) /*!< PLL clock divided by 256 */
+
+/*!< ADC1MPRE configuration */
+#define RCC_CFG2_ADC1MPRES ((uint32_t)0x0001F000) /*!< ADC1MPRE[4:0] bits */
+#define RCC_CFG2_ADC1MPRES_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define RCC_CFG2_ADC1MPRES_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define RCC_CFG2_ADC1MPRES_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+#define RCC_CFG2_ADC1MPRES_3 ((uint32_t)0x00008000) /*!< Bit 3 */
+#define RCC_CFG2_ADC1MPRES_4 ((uint32_t)0x00010000) /*!< Bit 4 */
+
+#define RCC_CFG2_ADC1MPRES_DIV1 ((uint32_t)0x00000000) /*!< ADC1M source clock is divided by 1 */
+#define RCC_CFG2_ADC1MPRES_DIV2 ((uint32_t)0x00001000) /*!< ADC1M source clock is divided by 2 */
+#define RCC_CFG2_ADC1MPRES_DIV3 ((uint32_t)0x00002000) /*!< ADC1M source clock is divided by 3 */
+#define RCC_CFG2_ADC1MPRES_DIV4 ((uint32_t)0x00003000) /*!< ADC1M source clock is divided by 4 */
+#define RCC_CFG2_ADC1MPRES_DIV5 ((uint32_t)0x00004000) /*!< ADC1M source clock is divided by 5 */
+#define RCC_CFG2_ADC1MPRES_DIV6 ((uint32_t)0x00005000) /*!< ADC1M source clock is divided by 6 */
+#define RCC_CFG2_ADC1MPRES_DIV7 ((uint32_t)0x00006000) /*!< ADC1M source clock is divided by 7 */
+#define RCC_CFG2_ADC1MPRES_DIV8 ((uint32_t)0x00007000) /*!< ADC1M source clock is divided by 8 */
+#define RCC_CFG2_ADC1MPRES_DIV9 ((uint32_t)0x00008000) /*!< ADC1M source clock is divided by 9 */
+#define RCC_CFG2_ADC1MPRES_DIV10 ((uint32_t)0x00009000) /*!< ADC1M source clock is divided by 10 */
+#define RCC_CFG2_ADC1MPRES_DIV11 ((uint32_t)0x0000A000) /*!< ADC1M source clock is divided by 11 */
+#define RCC_CFG2_ADC1MPRES_DIV12 ((uint32_t)0x0000B000) /*!< ADC1M source clock is divided by 12 */
+#define RCC_CFG2_ADC1MPRES_DIV13 ((uint32_t)0x0000C000) /*!< ADC1M source clock is divided by 13 */
+#define RCC_CFG2_ADC1MPRES_DIV14 ((uint32_t)0x0000D000) /*!< ADC1M source clock is divided by 14 */
+#define RCC_CFG2_ADC1MPRES_DIV15 ((uint32_t)0x0000E000) /*!< ADC1M source clock is divided by 15 */
+#define RCC_CFG2_ADC1MPRES_DIV16 ((uint32_t)0x0000F000) /*!< ADC1M source clock is divided by 16 */
+#define RCC_CFG2_ADC1MPRES_DIV17 ((uint32_t)0x00010000) /*!< ADC1M source clock is divided by 17 */
+#define RCC_CFG2_ADC1MPRES_DIV18 ((uint32_t)0x00011000) /*!< ADC1M source clock is divided by 18 */
+#define RCC_CFG2_ADC1MPRES_DIV19 ((uint32_t)0x00012000) /*!< ADC1M source clock is divided by 19 */
+#define RCC_CFG2_ADC1MPRES_DIV20 ((uint32_t)0x00013000) /*!< ADC1M source clock is divided by 20 */
+#define RCC_CFG2_ADC1MPRES_DIV21 ((uint32_t)0x00014000) /*!< ADC1M source clock is divided by 21 */
+#define RCC_CFG2_ADC1MPRES_DIV22 ((uint32_t)0x00015000) /*!< ADC1M source clock is divided by 22 */
+#define RCC_CFG2_ADC1MPRES_DIV23 ((uint32_t)0x00016000) /*!< ADC1M source clock is divided by 23 */
+#define RCC_CFG2_ADC1MPRES_DIV24 ((uint32_t)0x00017000) /*!< ADC1M source clock is divided by 24 */
+#define RCC_CFG2_ADC1MPRES_DIV25 ((uint32_t)0x00018000) /*!< ADC1M source clock is divided by 25 */
+#define RCC_CFG2_ADC1MPRES_DIV26 ((uint32_t)0x00019000) /*!< ADC1M source clock is divided by 26 */
+#define RCC_CFG2_ADC1MPRES_DIV27 ((uint32_t)0x0001A000) /*!< ADC1M source clock is divided by 27 */
+#define RCC_CFG2_ADC1MPRES_DIV28 ((uint32_t)0x0001B000) /*!< ADC1M source clock is divided by 28 */
+#define RCC_CFG2_ADC1MPRES_DIV29 ((uint32_t)0x0001C000) /*!< ADC1M source clock is divided by 29 */
+#define RCC_CFG2_ADC1MPRES_DIV30 ((uint32_t)0x0001D000) /*!< ADC1M source clock is divided by 30 */
+#define RCC_CFG2_ADC1MPRES_DIV31 ((uint32_t)0x0001E000) /*!< ADC1M source clock is divided by 31 */
+#define RCC_CFG2_ADC1MPRES_DIV32 ((uint32_t)0x0001F000) /*!< ADC1M source clock is divided by 32 */
+
+/*!< ADC1MSEL configuration */
+#define RCC_CFG2_ADC1MSEL ((uint32_t)0x00020000) /*!< ADC1M clock source select */
+
+#define RCC_CFG2_ADC1MSEL_HSI ((uint32_t)0x00000000) /*!< HSI clock selected as ADC1M input clock */
+#define RCC_CFG2_ADC1MSEL_HSE ((uint32_t)0x00020000) /*!< HSE clock selected as ADC1M input clock */
+
+/*!< RNGCPRE configuration */
+#define RCC_CFG2_RNGCPRES ((uint32_t)0x1F000000) /*!< RNGCPRE[4:0] bits */
+#define RCC_CFG2_RNGCPRES_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define RCC_CFG2_RNGCPRES_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define RCC_CFG2_RNGCPRES_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define RCC_CFG2_RNGCPRES_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define RCC_CFG2_RNGCPRES_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+
+#define RCC_CFG2_RNGCPRES_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK source clock is divided by 1 */
+#define RCC_CFG2_RNGCPRES_DIV2 ((uint32_t)0x01000000) /*!< SYSCLK source clock is divided by 2 */
+#define RCC_CFG2_RNGCPRES_DIV3 ((uint32_t)0x02000000) /*!< SYSCLK source clock is divided by 3 */
+#define RCC_CFG2_RNGCPRES_DIV4 ((uint32_t)0x03000000) /*!< SYSCLK source clock is divided by 4 */
+#define RCC_CFG2_RNGCPRES_DIV5 ((uint32_t)0x04000000) /*!< SYSCLK source clock is divided by 5 */
+#define RCC_CFG2_RNGCPRES_DIV6 ((uint32_t)0x05000000) /*!< SYSCLK source clock is divided by 6 */
+#define RCC_CFG2_RNGCPRES_DIV7 ((uint32_t)0x06000000) /*!< SYSCLK source clock is divided by 7 */
+#define RCC_CFG2_RNGCPRES_DIV8 ((uint32_t)0x07000000) /*!< SYSCLK source clock is divided by 8 */
+#define RCC_CFG2_RNGCPRES_DIV9 ((uint32_t)0x08000000) /*!< SYSCLK source clock is divided by 9 */
+#define RCC_CFG2_RNGCPRES_DIV10 ((uint32_t)0x09000000) /*!< SYSCLK source clock is divided by 10 */
+#define RCC_CFG2_RNGCPRES_DIV11 ((uint32_t)0x0A000000) /*!< SYSCLK source clock is divided by 11 */
+#define RCC_CFG2_RNGCPRES_DIV12 ((uint32_t)0x0B000000) /*!< SYSCLK source clock is divided by 12 */
+#define RCC_CFG2_RNGCPRES_DIV13 ((uint32_t)0x0C000000) /*!< SYSCLK source clock is divided by 13 */
+#define RCC_CFG2_RNGCPRES_DIV14 ((uint32_t)0x0D000000) /*!< SYSCLK source clock is divided by 14 */
+#define RCC_CFG2_RNGCPRES_DIV15 ((uint32_t)0x0E000000) /*!< SYSCLK source clock is divided by 15 */
+#define RCC_CFG2_RNGCPRES_DIV16 ((uint32_t)0x0F000000) /*!< SYSCLK source clock is divided by 16 */
+#define RCC_CFG2_RNGCPRES_DIV17 ((uint32_t)0x10000000) /*!< SYSCLK source clock is divided by 17 */
+#define RCC_CFG2_RNGCPRES_DIV18 ((uint32_t)0x11000000) /*!< SYSCLK source clock is divided by 18 */
+#define RCC_CFG2_RNGCPRES_DIV19 ((uint32_t)0x12000000) /*!< SYSCLK source clock is divided by 19 */
+#define RCC_CFG2_RNGCPRES_DIV20 ((uint32_t)0x13000000) /*!< SYSCLK source clock is divided by 20 */
+#define RCC_CFG2_RNGCPRES_DIV21 ((uint32_t)0x14000000) /*!< SYSCLK source clock is divided by 21 */
+#define RCC_CFG2_RNGCPRES_DIV22 ((uint32_t)0x15000000) /*!< SYSCLK source clock is divided by 22 */
+#define RCC_CFG2_RNGCPRES_DIV23 ((uint32_t)0x16000000) /*!< SYSCLK source clock is divided by 23 */
+#define RCC_CFG2_RNGCPRES_DIV24 ((uint32_t)0x17000000) /*!< SYSCLK source clock is divided by 24 */
+#define RCC_CFG2_RNGCPRES_DIV25 ((uint32_t)0x18000000) /*!< SYSCLK source clock is divided by 25 */
+#define RCC_CFG2_RNGCPRES_DIV26 ((uint32_t)0x19000000) /*!< SYSCLK source clock is divided by 26 */
+#define RCC_CFG2_RNGCPRES_DIV27 ((uint32_t)0x1A000000) /*!< SYSCLK source clock is divided by 27 */
+#define RCC_CFG2_RNGCPRES_DIV28 ((uint32_t)0x1B000000) /*!< SYSCLK source clock is divided by 28 */
+#define RCC_CFG2_RNGCPRES_DIV29 ((uint32_t)0x1C000000) /*!< SYSCLK source clock is divided by 29 */
+#define RCC_CFG2_RNGCPRES_DIV30 ((uint32_t)0x1D000000) /*!< SYSCLK source clock is divided by 30 */
+#define RCC_CFG2_RNGCPRES_DIV31 ((uint32_t)0x1E000000) /*!< SYSCLK source clock is divided by 31 */
+#define RCC_CFG2_RNGCPRES_DIV32 ((uint32_t)0x1F000000) /*!< SYSCLK source clock is divided by 32 */
+
+/*!< TIMCLK_SEL configuration */
+#define RCC_CFG2_TIMCLKSEL ((uint32_t)0x20000000) /*!< Timer1/8 clock source select */
+
+#define RCC_CFG2_TIMCLKSEL_TIM18CLK ((uint32_t)0x00000000) /*!< Timer1/8 clock selected as tim1/8_clk input clock */
+#define RCC_CFG2_TIMCLKSEL_SYSCLK ((uint32_t)0x20000000) /*!< Timer1/8 clock selected as sysclk input clock */
+
+/******************* Bit definition for RCC_CFG3 register ******************/
+/*!< UCDREN configuration */
+#define RCC_CFG3_UCDREN ((uint32_t)0x00000080) /*!< UCDR enable */
+
+#define RCC_CFG3_UCDREN_ENABLE ((uint32_t)0x00000080) /*!< UCDREN enable */
+#define RCC_CFG3_UCDREN_DISABLE ((uint32_t)0x00000000) /*!< UCDREN disable */
+
+/*!< USBXTALESS configuration */
+#define RCC_CFG3_USBXTALESS ((uint32_t)0x00000100) /*!< UCDR enable */
+
+#define RCC_CFG3_USBXTALESS_LESSMODE ((uint32_t)0x00000100) /*!< USB Crystalless mode */
+#define RCC_CFG3_USBXTALESS_MODE ((uint32_t)0x00000000) /*!< USB Crystal mode */
+
+/*!< UCDR300MSEL configuration */
+#define RCC_CFG3_UCDR300MSEL ((uint32_t)0x00000200) /*!< UCDR 300M Clock source */
+
+#define RCC_CFG3_UCDR300MSEL_PLLVCO ((uint32_t)0x00000200) /*!< PLL VCO selected as UCDR 300M Clock source */
+#define RCC_CFG3_UCDR300MSEL_OSC300M ((uint32_t)0x00000000) /*!< OSC300M selected as UCDR 300M Clock source */
+
+/*!< TRNG1MPRE configuration */
+#define RCC_CFG3_TRNG1MPRES ((uint32_t)0x0000F800) /*!< TRNG1MPRE[4:0] bits */
+#define RCC_CFG3_TRNG1MPRES_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define RCC_CFG3_TRNG1MPRES_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+#define RCC_CFG3_TRNG1MPRES_2 ((uint32_t)0x00002000) /*!< Bit 2 */
+#define RCC_CFG3_TRNG1MPRES_3 ((uint32_t)0x00004000) /*!< Bit 3 */
+#define RCC_CFG3_TRNG1MPRES_4 ((uint32_t)0x00008000) /*!< Bit 4 */
+
+#define RCC_CFG3_TRNG1MPRES_VAL2 ((uint32_t)0x00000800) /*!< TRNG 1M source clock is divided by 2 */
+#define RCC_CFG3_TRNG1MPRES_VAL3 ((uint32_t)0x00001000) /*!< TRNG 1M source clock is divided by 4 */
+#define RCC_CFG3_TRNG1MPRES_VAL4 ((uint32_t)0x00001800) /*!< TRNG 1M source clock is divided by 6 */
+#define RCC_CFG3_TRNG1MPRES_VAL5 ((uint32_t)0x00002000) /*!< TRNG 1M source clock is divided by 8 */
+#define RCC_CFG3_TRNG1MPRES_VAL6 ((uint32_t)0x00002800) /*!< TRNG 1M source clock is divided by 10 */
+#define RCC_CFG3_TRNG1MPRES_VAL7 ((uint32_t)0x00003000) /*!< TRNG 1M source clock is divided by 12 */
+#define RCC_CFG3_TRNG1MPRES_VAL8 ((uint32_t)0x00003800) /*!< TRNG 1M source clock is divided by 14 */
+#define RCC_CFG3_TRNG1MPRES_VAL9 ((uint32_t)0x00004000) /*!< TRNG 1M source clock is divided by 16 */
+#define RCC_CFG3_TRNG1MPRES_VAL10 ((uint32_t)0x00004800) /*!< TRNG 1M source clock is divided by 18 */
+#define RCC_CFG3_TRNG1MPRES_VAL11 ((uint32_t)0x00005000) /*!< TRNG 1M source clock is divided by 20 */
+#define RCC_CFG3_TRNG1MPRES_VAL12 ((uint32_t)0x00005800) /*!< TRNG 1M source clock is divided by 22 */
+#define RCC_CFG3_TRNG1MPRES_VAL13 ((uint32_t)0x00006000) /*!< TRNG 1M source clock is divided by 24 */
+#define RCC_CFG3_TRNG1MPRES_VAL14 ((uint32_t)0x00006800) /*!< TRNG 1M source clock is divided by 26 */
+#define RCC_CFG3_TRNG1MPRES_VAL15 ((uint32_t)0x00007000) /*!< TRNG 1M source clock is divided by 28 */
+#define RCC_CFG3_TRNG1MPRES_VAL16 ((uint32_t)0x00007800) /*!< TRNG 1M source clock is divided by 30 */
+#define RCC_CFG3_TRNG1MPRES_VAL17 ((uint32_t)0x00008000) /*!< TRNG 1M source clock is divided by 32 */
+#define RCC_CFG3_TRNG1MPRES_VAL18 ((uint32_t)0x00008800) /*!< TRNG 1M source clock is divided by 34 */
+#define RCC_CFG3_TRNG1MPRES_VAL19 ((uint32_t)0x00009000) /*!< TRNG 1M source clock is divided by 36 */
+#define RCC_CFG3_TRNG1MPRES_VAL20 ((uint32_t)0x00009800) /*!< TRNG 1M source clock is divided by 38 */
+#define RCC_CFG3_TRNG1MPRES_VAL21 ((uint32_t)0x0000A000) /*!< TRNG 1M source clock is divided by 40 */
+#define RCC_CFG3_TRNG1MPRES_VAL22 ((uint32_t)0x0000A800) /*!< TRNG 1M source clock is divided by 42 */
+#define RCC_CFG3_TRNG1MPRES_VAL23 ((uint32_t)0x0000B000) /*!< TRNG 1M source clock is divided by 44 */
+#define RCC_CFG3_TRNG1MPRES_VAL24 ((uint32_t)0x0000B800) /*!< TRNG 1M source clock is divided by 46 */
+#define RCC_CFG3_TRNG1MPRES_VAL25 ((uint32_t)0x0000C000) /*!< TRNG 1M source clock is divided by 48 */
+#define RCC_CFG3_TRNG1MPRES_VAL26 ((uint32_t)0x0000C800) /*!< TRNG 1M source clock is divided by 50 */
+#define RCC_CFG3_TRNG1MPRES_VAL27 ((uint32_t)0x0000D000) /*!< TRNG 1M source clock is divided by 52 */
+#define RCC_CFG3_TRNG1MPRES_VAL28 ((uint32_t)0x0000D800) /*!< TRNG 1M source clock is divided by 54 */
+#define RCC_CFG3_TRNG1MPRES_VAL29 ((uint32_t)0x0000E000) /*!< TRNG 1M source clock is divided by 56 */
+#define RCC_CFG3_TRNG1MPRES_VAL30 ((uint32_t)0x0000E800) /*!< TRNG 1M source clock is divided by 58 */
+#define RCC_CFG3_TRNG1MPRES_VAL31 ((uint32_t)0x0000F000) /*!< TRNG 1M source clock is divided by 60 */
+#define RCC_CFG3_TRNG1MPRES_VAL32 ((uint32_t)0x0000F800) /*!< TRNG 1M source clock is divided by 62 */
+
+/*!< TRNG1MSEL configuration */
+#define RCC_CFG3_TRNG1MSEL ((uint32_t)0x00020000) /*!< TRNG_1M clock source select */
+
+#define RCC_CFG3_TRNG1MSEL_HSI ((uint32_t)0x00000000) /*!< HSI clock selected as TRNG_1M input clock */
+#define RCC_CFG3_TRNG1MSEL_HSE ((uint32_t)0x00020000) /*!< HSE clock selected as TRNG_1M input clock */
+
+/*!< TRNG1MEN configuration */
+#define RCC_CFG3_TRNG1MEN ((uint32_t)0x00040000) /*!< TRNG_1M clock enable */
+
+#define RCC_CFG3_TRNG1MEN_DISABLE ((uint32_t)0x00000000) /*!< TRNG_1M clock disable */
+#define RCC_CFG3_TRNG1MEN_ENABLE ((uint32_t)0x00040000) /*!< TRNG_1M clock enable */
+
+/******************* Bit definition for RCC_RDCTRL register ******************/
+/*!< LPTIMSEL congiguration */
+#define RCC_RDCTRL_LPTIMSEL ((uint32_t)0x00000007) /*!< LPTIMSEL[2:0] bits (LPTIM clock source selection) */
+#define RCC_RDCTRL_LPTIMSEL_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_RDCTRL_LPTIMSEL_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RCC_RDCTRL_LPTIMSEL_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define RCC_RDCTRL_LPTIMSEL_APB1 ((uint32_t)0x00000000) /*!< APB1 clock used as LPTIM clock */
+#define RCC_RDCTRL_LPTIMSEL_LSI ((uint32_t)0x00000001) /*!< LSI oscillator clock used as LPTIM clock */
+#define RCC_RDCTRL_LPTIMSEL_HSI ((uint32_t)0x00000002) /*!< HSI oscillator clock used as LPTIM clock */
+#define RCC_RDCTRL_LPTIMSEL_LSE ((uint32_t)0x00000003) /*!< LSE oscillator clock used as LPTIM clock */
+#define RCC_RDCTRL_LPTIMSEL_COMP1 ((uint32_t)0x00000004) /*!< COMP1 output used as LPTIM clock */
+#define RCC_RDCTRL_LPTIMSEL_COMP2 ((uint32_t)0x00000005) /*!< COMP1 output used as LPTIM clock */
+
+/*!< LPUARTSEL congiguration */
+#define RCC_RDCTRL_LPUARTSEL ((uint32_t)0x00000018) /*!< LPUARTSEL[1:0] bits (LPUART clock source selection) */
+#define RCC_RDCTRL_LPUARTSEL_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define RCC_RDCTRL_LPUARTSEL_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+
+#define RCC_RDCTRL_LPUARTSEL_APB1 ((uint32_t)0x00000000) /*!< APB1 clock used as LPUART clock */
+#define RCC_RDCTRL_LPUARTSEL_SYSCLK ((uint32_t)0x00000008) /*!< SYSCLK used as LPUART clock */
+#define RCC_RDCTRL_LPUARTSEL_HSI ((uint32_t)0x00000010) /*!< HSI oscillator clock used as LPUART clock */
+#define RCC_RDCTRL_LPUARTSEL_LSE ((uint32_t)0x00000018) /*!< LSE oscillator clock used as LPUART clock */
+
+#define RCC_RDCTRL_LPTIMEN ((uint32_t)0x00000040) /*!< LPTIM clock enable */
+#define RCC_RDCTRL_LPUARTEN ((uint32_t)0x00000080) /*!< LPUART clock enable */
+#define RCC_RDCTRL_LCDEN ((uint32_t)0x00000100) /*!< LCD clock enable */
+#define RCC_RDCTRL_LPRCNTEN ((uint32_t)0x00000200) /*!< LPRCNT clock enable */
+#define RCC_RDCTRL_LPTIMRST ((uint32_t)0x00000400) /*!< LPTIM reset */
+#define RCC_RDCTRL_LPUARTRST ((uint32_t)0x00000800) /*!< LPUART reset */
+#define RCC_RDCTRL_LCDRST ((uint32_t)0x00001000) /*!< LCD reset */
+#define RCC_RDCTRL_LPRCNTRST ((uint32_t)0x00002000) /*!< LPRCNT reset */
+
+/******************* Bit definition for RCC_PLLHSIPRE register ******************/
+/*!< PLLHSIPRE configuration */
+#define RCC_PLLHSIPRE_PLLHSIPRE ((uint32_t)0x00000001) /*!< HSI divider for PLL entry */
+
+#define RCC_PLLHSIPRE_PLLHSIPRE_HSI ((uint32_t)0x00000000) /*!< HSI clock not divided for PLL entry */
+#define RCC_PLLHSIPRE_PLLHSIPRE_HSI_DIV2 ((uint32_t)0x00000001) /*!< HSI clock divided by 2 for PLL entry */
+
+/*!< PLLSRCDIV configuration */
+#define RCC_PLLHSIPRE_PLLSRCDIV ((uint32_t)0x00000002) /*!< PLL source clock for PLL entry */
+
+#define RCC_PLLHSIPRE_PLLSRCDIV_DISABLE ((uint32_t)0x00000000) /*!< PLL source clock not divided for PLL entry */
+#define RCC_PLLHSIPRE_PLLSRCDIV_ENABLE ((uint32_t)0x00000002) /*!< PLL source clock divided by 2 for PLL entry */
+
+/******************* Bit definition for RCC_SRAM_CTRLSTS register ******************/
+#define RCC_SRAM_CTRLSTS_ERR1EN ((uint32_t)0x00000001) /*!< SRAM1 Parity Error Interrupt Enable */
+#define RCC_SRAM_CTRLSTS_ERR1RSTEN ((uint32_t)0x00000002) /*!< SRAM1 Parity Error Reset Enable */
+#define RCC_SRAM_CTRLSTS_ERR1STS ((uint32_t)0x00000004) /*!< SRAM1 Parity Error Status */
+#define RCC_SRAM_CTRLSTS_ERR2EN ((uint32_t)0x00000008) /*!< SRAM2 Parity Error Interrupt Enable */
+#define RCC_SRAM_CTRLSTS_ERR2RSTEN ((uint32_t)0x00000010) /*!< SRAM2 Parity Error Reset Enable */
+#define RCC_SRAM_CTRLSTS_ERR2STS ((uint32_t)0x00000020) /*!< SRAM2 Parity Error Status */
+
+/******************************************************************************/
+/* */
+/* SystemTick */
+/* */
+/******************************************************************************/
+
+/***************** Bit definition for SysTick_CTRL register *****************/
+#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
+#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
+#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
+#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
+
+/***************** Bit definition for SysTick_LOAD register *****************/
+#define SysTick_LOAD_RELOAD \
+ ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/***************** Bit definition for SysTick_VAL register ******************/
+#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
+
+/***************** Bit definition for SysTick_CALIB register ****************/
+#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
+#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
+#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/* */
+/* Nested Vectored Interrupt Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for NVIC_ISER register *******************/
+#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */
+#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ICER register *******************/
+#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */
+#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ISPR register *******************/
+#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */
+#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ICPR register *******************/
+#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */
+#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_IABR register *******************/
+#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */
+#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_PRI0 register *******************/
+#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
+#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
+#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
+#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
+
+/****************** Bit definition for NVIC_PRI1 register *******************/
+#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
+#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
+#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
+#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
+
+/****************** Bit definition for NVIC_PRI2 register *******************/
+#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
+#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
+#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
+#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
+
+/****************** Bit definition for NVIC_PRI3 register *******************/
+#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
+#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
+#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
+#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
+
+/****************** Bit definition for NVIC_PRI4 register *******************/
+#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
+#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
+#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
+#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
+
+/****************** Bit definition for NVIC_PRI5 register *******************/
+#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
+#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
+#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
+#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
+
+/****************** Bit definition for NVIC_PRI6 register *******************/
+#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
+#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
+#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
+#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
+
+/****************** Bit definition for NVIC_PRI7 register *******************/
+#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
+#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
+#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
+#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
+
+/****************** Bit definition for SCB_CPUID register *******************/
+#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
+#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
+#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
+#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
+#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
+
+/******************* Bit definition for SCB_ICSR register *******************/
+#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active INTSTS number field */
+#define SCB_ICSR_RETTOBASE \
+ ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending INTSTS number field */
+#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
+#define SCB_ICSR_ISRPREEMPT \
+ ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
+#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
+#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
+#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
+#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
+
+/******************* Bit definition for SCB_VTOR register *******************/
+#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
+#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
+
+/*!<***************** Bit definition for SCB_AIRCR register *******************/
+#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
+#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
+#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
+
+#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
+#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+/* prority group configuration */
+#define SCB_AIRCR_PRIGROUP0 \
+ ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define SCB_AIRCR_PRIGROUP1 \
+ ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP2 \
+ ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP3 \
+ ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP4 \
+ ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP5 \
+ ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP6 \
+ ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP7 \
+ ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
+#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/******************* Bit definition for SCB_SCR register ********************/
+#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */
+#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */
+#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */
+
+/******************** Bit definition for SCB_CCR register *******************/
+#define SCB_CCR_NONBASETHRDENA \
+ ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define SCB_CCR_USERSETMPEND \
+ ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a \
+ Main exception */
+#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */
+#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */
+#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */
+#define SCB_CCR_STKALIGN \
+ ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/******************* Bit definition for SCB_SHPR register ********************/
+#define SCB_SHPR_PRI_N \
+ ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define SCB_SHPR_PRI_N1 \
+ ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define SCB_SHPR_PRI_N2 \
+ ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define SCB_SHPR_PRI_N3 \
+ ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/****************** Bit definition for SCB_SHCSR register *******************/
+#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
+#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
+#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
+#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
+#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
+#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
+#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
+#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
+#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
+#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
+#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
+#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
+#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
+#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
+
+/******************* Bit definition for SCB_CFSR register *******************/
+/*!< MFSR */
+#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */
+#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */
+#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */
+#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */
+#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED \
+ ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO \
+ ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/******************* Bit definition for SCB_HFSR register *******************/
+#define SCB_HFSR_VECTTBL \
+ ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
+#define SCB_HFSR_FORCED \
+ ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
+
+/******************* Bit definition for SCB_DFSR register *******************/
+#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */
+#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */
+#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */
+#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */
+#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */
+
+/******************* Bit definition for SCB_MMFAR register ******************/
+#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */
+
+/******************* Bit definition for SCB_BFAR register *******************/
+#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */
+
+/******************* Bit definition for SCB_afsr register *******************/
+#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */
+
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_INTSTS register ********************/
+#define DMA_INTSTS_GLBF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
+#define DMA_INTSTS_TXCF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
+#define DMA_INTSTS_HTXF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
+#define DMA_INTSTS_ERRF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
+#define DMA_INTSTS_GLBF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
+#define DMA_INTSTS_TXCF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
+#define DMA_INTSTS_HTXF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
+#define DMA_INTSTS_ERRF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
+#define DMA_INTSTS_GLBF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
+#define DMA_INTSTS_TXCF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
+#define DMA_INTSTS_HTXF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
+#define DMA_INTSTS_ERRF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
+#define DMA_INTSTS_GLBF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
+#define DMA_INTSTS_TXCF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
+#define DMA_INTSTS_HTXF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
+#define DMA_INTSTS_ERRF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
+#define DMA_INTSTS_GLBF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
+#define DMA_INTSTS_TXCF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
+#define DMA_INTSTS_HTXF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
+#define DMA_INTSTS_ERRF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
+#define DMA_INTSTS_GLBF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
+#define DMA_INTSTS_TXCF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
+#define DMA_INTSTS_HTXF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
+#define DMA_INTSTS_ERRF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
+#define DMA_INTSTS_GLBF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
+#define DMA_INTSTS_TXCF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
+#define DMA_INTSTS_HTXF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
+#define DMA_INTSTS_ERRF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
+#define DMA_INTSTS_GLBF8 ((uint32_t)0x10000000) /*!< Channel 7 Global interrupt flag */
+#define DMA_INTSTS_TXCF8 ((uint32_t)0x20000000) /*!< Channel 7 Transfer Complete flag */
+#define DMA_INTSTS_HTXF8 ((uint32_t)0x40000000) /*!< Channel 7 Half Transfer flag */
+#define DMA_INTSTS_ERRF8 ((uint32_t)0x80000000) /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_INTCLR register *******************/
+#define DMA_INTCLR_CGLBF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
+#define DMA_INTCLR_CTXCF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
+#define DMA_INTCLR_CERRF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
+#define DMA_INTCLR_CGLBF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
+#define DMA_INTCLR_CTXCF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
+#define DMA_INTCLR_CERRF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
+#define DMA_INTCLR_CGLBF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
+#define DMA_INTCLR_CTXCF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
+#define DMA_INTCLR_CERRF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
+#define DMA_INTCLR_CGLBF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
+#define DMA_INTCLR_CTXCF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
+#define DMA_INTCLR_CERRF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
+#define DMA_INTCLR_CGLBF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
+#define DMA_INTCLR_CTXCF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
+#define DMA_INTCLR_CERRF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
+#define DMA_INTCLR_CGLBF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
+#define DMA_INTCLR_CTXCF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
+#define DMA_INTCLR_CERRF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
+#define DMA_INTCLR_CGLBF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
+#define DMA_INTCLR_CTXCF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
+#define DMA_INTCLR_CERRF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
+#define DMA_INTCLR_CGLBF8 ((uint32_t)0x10000000) /*!< Channel 7 Global interrupt clear */
+#define DMA_INTCLR_CTXCF8 ((uint32_t)0x20000000) /*!< Channel 7 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF8 ((uint32_t)0x40000000) /*!< Channel 7 Half Transfer clear */
+#define DMA_INTCLR_CERRF8 ((uint32_t)0x80000000) /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CHCFG1 register *******************/
+#define DMA_CHCFG1_CHEN ((uint16_t)0x0001) /*!< Channel enable*/
+#define DMA_CHCFG1_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG1_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG1_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG1_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CHCFG1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CHCFG1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG1_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */
+#define DMA_CHCFG1_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG1_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/******************* Bit definition for DMA_CHCFG2 register *******************/
+#define DMA_CHCFG2_CHEN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CHCFG2_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG2_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG2_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG2_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CHCFG2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CHCFG2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG2_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CHCFG2_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG2_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/******************* Bit definition for DMA_CHCFG3 register *******************/
+#define DMA_CHCFG3_CHEN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CHCFG3_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG3_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG3_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG3_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CHCFG3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CHCFG3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG3_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CHCFG3_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG3_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/*!<****************** Bit definition for DMA_CHCFG4 register *******************/
+#define DMA_CHCFG4_CHEN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CHCFG4_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG4_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG4_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG4_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CHCFG4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CHCFG4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG4_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CHCFG4_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG4_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CHCFG5 register *******************/
+#define DMA_CHCFG5_CHEN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CHCFG5_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG5_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG5_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG5_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CHCFG5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CHCFG5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG5_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CHCFG5_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG5_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
+
+/******************* Bit definition for DMA_CHCFG6 register *******************/
+#define DMA_CHCFG6_CHEN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CHCFG6_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG6_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG6_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG6_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CHCFG6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CHCFG6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG6_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CHCFG6_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG6_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/******************* Bit definition for DMA_CHCFG7 register *******************/
+#define DMA_CHCFG7_CHEN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CHCFG7_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG7_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG7_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG7_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG7_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CHCFG7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CHCFG7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG7_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CHCFG7_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG7_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
+
+/******************* Bit definition for DMA_CHCFG8 register *******************/
+#define DMA_CHCFG8_CHEN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CHCFG8_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG8_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG8_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG8_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG8_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG8_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG8_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG8_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG8_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CHCFG8_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CHCFG8_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG8_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG8_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG8_PRIOLVL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CHCFG8_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG8_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG8_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
+
+/****************** Bit definition for DMA_TXNUM1 register ******************/
+#define DMA_TXNUM1_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_TXNUM2 register ******************/
+#define DMA_TXNUM2_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_TXNUM3 register ******************/
+#define DMA_TXNUM3_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_TXNUM4 register ******************/
+#define DMA_TXNUM4_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_TXNUM5 register ******************/
+#define DMA_TXNUM5_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_TXNUM6 register ******************/
+#define DMA_TXNUM6_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_TXNUM7 register ******************/
+#define DMA_TXNUM7_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_TXNUM8 register ******************/
+#define DMA_TXNUM8_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_PADDR1 register *******************/
+#define DMA_PADDR1_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_PADDR2 register *******************/
+#define DMA_PADDR2_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_PADDR3 register *******************/
+#define DMA_PADDR3_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_PADDR4 register *******************/
+#define DMA_PADDR4_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_PADDR5 register *******************/
+#define DMA_PADDR5_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_PADDR6 register *******************/
+#define DMA_PADDR6_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_PADDR7 register *******************/
+#define DMA_PADDR7_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_PADDR8 register *******************/
+#define DMA_PADDR8_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_MADDR1 register *******************/
+#define DMA_MADDR1_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_MADDR2 register *******************/
+#define DMA_MADDR2_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_MADDR3 register *******************/
+#define DMA_MADDR3_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_MADDR4 register *******************/
+#define DMA_MADDR4_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_MADDR5 register *******************/
+#define DMA_MADDR5_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_MADDR6 register *******************/
+#define DMA_MADDR6_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_MADDR7 register *******************/
+#define DMA_MADDR7_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_MADDR8 register *******************/
+#define DMA_MADDR8_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for ADC_STS register ********************/
+#define ADC_STS_AWDG ((uint8_t)0x01) /*!< Analog watchdog flag */
+#define ADC_STS_ENDC ((uint8_t)0x02) /*!< End of conversion */
+#define ADC_STS_JENDC ((uint8_t)0x04) /*!< Injected channel end of conversion */
+#define ADC_STS_JSTR ((uint8_t)0x08) /*!< Injected channel Start flag */
+#define ADC_STS_STR ((uint8_t)0x10) /*!< Regular channel Start flag */
+#define ADC_STS_ENDCA ((uint8_t)0x20) /*!< Regular channel any end flag */
+#define ADC_STS_JENDCA ((uint8_t)0x40) /*!< Injected channel any end flag */
+
+
+/******************* Bit definition for ADC_CTRL1 register ********************/
+#define ADC_CTRL1_AWDGCH ((uint32_t)0x0000001F) /*!< AWDG_CH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CTRL1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_CTRL1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_CTRL1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_CTRL1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_CTRL1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_CTRL1_ENDCIEN ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */
+#define ADC_CTRL1_AWDGIEN ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */
+#define ADC_CTRL1_JENDCIEN ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */
+#define ADC_CTRL1_SCANMD ((uint32_t)0x00000100) /*!< Scan mode */
+#define ADC_CTRL1_AWDGSGLEN ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */
+#define ADC_CTRL1_AUTOJC ((uint32_t)0x00000400) /*!< Automatic injected group conversion */
+#define ADC_CTRL1_DREGCH ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */
+#define ADC_CTRL1_DJCH ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */
+
+#define ADC_CTRL1_DCTU ((uint32_t)0x0000E000) /*!< DISC_NUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CTRL1_DCTU_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define ADC_CTRL1_DCTU_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define ADC_CTRL1_DCTU_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+
+#define ADC_CTRL1_AWDGEJCH ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */
+#define ADC_CTRL1_AWDGERCH ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
+
+/******************* Bit definition for ADC_CTRL2 register ********************/
+#define ADC_CTRL2_ON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */
+#define ADC_CTRL2_CTU ((uint32_t)0x00000002) /*!< Continuous Conversion */
+#define ADC_CTRL2_ENCAL ((uint32_t)0x00000004) /*!< A/D Calibration */
+#define ADC_CTRL2_ENDMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */
+#define ADC_CTRL2_ALIG ((uint32_t)0x00000800) /*!< Data Alignment */
+
+#define ADC_CTRL2_EXTJSEL \
+ ((uint32_t)0x00007000) /*!< INJ_EXT_SEL[2:0] bits (External event select for injected group) */
+#define ADC_CTRL2_EXTJSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_CTRL2_EXTJSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_CTRL2_EXTJSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_CTRL2_EXTJTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */
+
+#define ADC_CTRL2_EXTRSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CTRL2_EXTRSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define ADC_CTRL2_EXTRSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define ADC_CTRL2_EXTRSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+
+#define ADC_CTRL2_EXTRTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */
+#define ADC_CTRL2_SWSTRJCH ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */
+#define ADC_CTRL2_SWSTRRCH ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */
+#define ADC_CTRL2_TEMPEN ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */
+
+/****************** Bit definition for ADC_SAMPT1 register *******************/
+#define ADC_SAMPT1_SAMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SAMPT1_SAMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define ADC_SAMPT1_SAMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SAMPT1_SAMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define ADC_SAMPT1_SAMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SAMPT1_SAMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+
+#define ADC_SAMPT1_SAMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SAMPT1_SAMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+
+#define ADC_SAMPT1_SAMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SAMPT1_SAMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_SAMPT1_SAMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SAMPT1_SAMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+
+#define ADC_SAMPT1_SAMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SAMPT1_SAMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+
+#define ADC_SAMPT1_SAMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SAMPT1_SAMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+
+/****************** Bit definition for ADC_SAMPT2 register *******************/
+#define ADC_SAMPT2_SAMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SAMPT2_SAMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SAMPT2_SAMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SAMPT2_SAMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SAMPT2_SAMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SAMPT2_SAMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SAMPT2_SAMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SAMPT2_SAMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SAMPT2_SAMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SAMPT2_SAMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SAMPT2_SAMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */
+
+/****************** Bit definition for ADC_JOFFSET1 register *******************/
+#define ADC_JOFFSET1_OFFSETJCH1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFFSET2 register *******************/
+#define ADC_JOFFSET2_OFFSETJCH2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFFSET3 register *******************/
+#define ADC_JOFFSET3_OFFSETJCH3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFFSET4 register *******************/
+#define ADC_JOFFSET4_OFFSETJCH4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_WDGHIGH register ********************/
+#define ADC_WDGHIGH_HTH ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_WDGLOW register ********************/
+#define ADC_WDGLOW_LTH ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_RSEQ1 register *******************/
+#define ADC_RSEQ1_SEQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_RSEQ1_SEQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_RSEQ1_SEQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_RSEQ1_SEQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_RSEQ1_SEQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_RSEQ1_SEQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_RSEQ1_SEQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_RSEQ1_SEQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_RSEQ1_SEQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_RSEQ1_SEQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_RSEQ1_SEQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_RSEQ1_SEQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_RSEQ1_SEQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_RSEQ1_SEQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_RSEQ1_SEQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_RSEQ1_SEQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_RSEQ1_SEQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_RSEQ1_SEQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_RSEQ1_SEQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_RSEQ1_SEQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_RSEQ1_SEQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_RSEQ1_SEQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_RSEQ1_SEQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_RSEQ1_SEQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_RSEQ1_LEN ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */
+#define ADC_RSEQ1_LEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_RSEQ1_LEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_RSEQ1_LEN_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_RSEQ1_LEN_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+/******************* Bit definition for ADC_RSEQ2 register *******************/
+#define ADC_RSEQ2_SEQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_RSEQ2_SEQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_RSEQ2_SEQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_RSEQ2_SEQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_RSEQ2_SEQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_RSEQ2_SEQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_RSEQ2_SEQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_RSEQ2_SEQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_RSEQ2_SEQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_RSEQ2_SEQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_RSEQ2_SEQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_RSEQ2_SEQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_RSEQ2_SEQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_RSEQ2_SEQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_RSEQ2_SEQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_RSEQ2_SEQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_RSEQ2_SEQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_RSEQ2_SEQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_RSEQ2_SEQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_RSEQ2_SEQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_RSEQ2_SEQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_RSEQ2_SEQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_RSEQ2_SEQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_RSEQ2_SEQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_RSEQ2_SEQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_RSEQ2_SEQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_RSEQ2_SEQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_RSEQ2_SEQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_RSEQ2_SEQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+#define ADC_RSEQ2_SEQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */
+
+#define ADC_RSEQ2_SEQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_RSEQ2_SEQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */
+#define ADC_RSEQ2_SEQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define ADC_RSEQ2_SEQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */
+#define ADC_RSEQ2_SEQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */
+#define ADC_RSEQ2_SEQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */
+
+/******************* Bit definition for ADC_RSEQ3 register *******************/
+#define ADC_RSEQ3_SEQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_RSEQ3_SEQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_RSEQ3_SEQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_RSEQ3_SEQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_RSEQ3_SEQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_RSEQ3_SEQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_RSEQ3_SEQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_RSEQ3_SEQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_RSEQ3_SEQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_RSEQ3_SEQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_RSEQ3_SEQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_RSEQ3_SEQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_RSEQ3_SEQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_RSEQ3_SEQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_RSEQ3_SEQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_RSEQ3_SEQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_RSEQ3_SEQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_RSEQ3_SEQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_RSEQ3_SEQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_RSEQ3_SEQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_RSEQ3_SEQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_RSEQ3_SEQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_RSEQ3_SEQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_RSEQ3_SEQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_RSEQ3_SEQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_RSEQ3_SEQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_RSEQ3_SEQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_RSEQ3_SEQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_RSEQ3_SEQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+#define ADC_RSEQ3_SEQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */
+
+#define ADC_RSEQ3_SEQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_RSEQ3_SEQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */
+#define ADC_RSEQ3_SEQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define ADC_RSEQ3_SEQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */
+#define ADC_RSEQ3_SEQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */
+#define ADC_RSEQ3_SEQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */
+
+/******************* Bit definition for ADC_JSEQ register *******************/
+#define ADC_JSEQ_JSEQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSEQ_JSEQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_JSEQ_JSEQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_JSEQ_JSEQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_JSEQ_JSEQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_JSEQ_JSEQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_JSEQ_JSEQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSEQ_JSEQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_JSEQ_JSEQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_JSEQ_JSEQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_JSEQ_JSEQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_JSEQ_JSEQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_JSEQ_JSEQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSEQ_JSEQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_JSEQ_JSEQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_JSEQ_JSEQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_JSEQ_JSEQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_JSEQ_JSEQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_JSEQ_JSEQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSEQ_JSEQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_JSEQ_JSEQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_JSEQ_JSEQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_JSEQ_JSEQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_JSEQ_JSEQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_JSEQ_JLEN ((uint32_t)0x00300000) /*!< INJ_LEN[1:0] bits (Injected Sequence length) */
+#define ADC_JSEQ_JLEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_JSEQ_JLEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+/******************* Bit definition for ADC_JDAT1 register *******************/
+#define ADC_JDAT1_JDAT ((uint16_t)0xFFFF) /*!< Injected data */
+
+/******************* Bit definition for ADC_JDAT2 register *******************/
+#define ADC_JDAT2_JDAT ((uint16_t)0xFFFF) /*!< Injected data */
+
+/******************* Bit definition for ADC_JDAT3 register *******************/
+#define ADC_JDAT3_JDAT ((uint16_t)0xFFFF) /*!< Injected data */
+
+/******************* Bit definition for ADC_JDAT4 register *******************/
+#define ADC_JDAT4_JDAT ((uint16_t)0xFFFF) /*!< Injected data */
+
+/******************** Bit definition for ADC_DAT register ********************/
+#define ADC_DAT_DAT ((uint32_t)0x0000FFFF) /*!< Regular data */
+
+///******************** Bit definition for ADC_DIFSEL register ********************/
+//#define ADC_DIFSEL_DIFSEL ((uint32_t)0x000FFFFE) /*!< Differential data */
+//#define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000002) /*!< Differential_1 data */
+//#define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000004) /*!< Differential_2 data */
+//#define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000008) /*!< Differential_3 data */
+//#define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000010) /*!< Differential_4 data */
+//#define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000020) /*!< Differential_5 data */
+//#define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000040) /*!< Differential_6 data */
+//#define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000080) /*!< Differential_7 data */
+//#define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000100) /*!< Differential_8 data */
+//#define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000200) /*!< Differential_9 data */
+//#define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000400) /*!< Differential_10 data */
+//#define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000800) /*!< Differential_11 data */
+//#define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00001000) /*!< Differential_12 data */
+//#define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00002000) /*!< Differential_13 data */
+//#define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00004000) /*!< Differential_14 data */
+//#define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00008000) /*!< Differential_15 data */
+//#define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00010000) /*!< Differential_16 data */
+//#define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00020000) /*!< Differential_17 data */
+//#define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00040000) /*!< Differential_18 data */
+//#define ADC_DIFSEL_DIFSEL_18 ((uint32_t)0x00080000) /*!< Differential_19 data */
+
+///******************** Bit definition for ADC_CALFACT register ********************/
+//#define ADC_CALFACT_CALFACTS ((uint32_t)0x0000007F) /*!< Calibration factors in single data */
+//#define ADC_CALFACT_CALFACTS_0 ((uint32_t)0x00000001) /*!< Calibration factors_0 in single data */
+//#define ADC_CALFACT_CALFACTS_1 ((uint32_t)0x00000002) /*!< Calibration factors_1 in single data */
+//#define ADC_CALFACT_CALFACTS_2 ((uint32_t)0x00000004) /*!< Calibration factors_2 in single data */
+//#define ADC_CALFACT_CALFACTS_3 ((uint32_t)0x00000008) /*!< Calibration factors_3 in single data */
+//#define ADC_CALFACT_CALFACTS_4 ((uint32_t)0x00000010) /*!< Calibration factors_4 in single data */
+//#define ADC_CALFACT_CALFACTS_5 ((uint32_t)0x00000020) /*!< Calibration factors_5 in single data */
+//#define ADC_CALFACT_CALFACTS_6 ((uint32_t)0x00000040) /*!< Calibration factors_6 in single data */
+
+//#define ADC_CALFACT_CALFACTD ((uint32_t)0x007F0000) /*!< Calibration factors in differential data */
+//#define ADC_CALFACT_CALFACTD_0 ((uint32_t)0x00010000) /*!< Calibration factors_0 in differential data */
+//#define ADC_CALFACT_CALFACTD_1 ((uint32_t)0x00020000) /*!< Calibration factors_1 in differential data */
+//#define ADC_CALFACT_CALFACTD_2 ((uint32_t)0x00040000) /*!< Calibration factors_2 in differential data */
+//#define ADC_CALFACT_CALFACTD_3 ((uint32_t)0x00080000) /*!< Calibration factors_3 in differential data */
+//#define ADC_CALFACT_CALFACTD_4 ((uint32_t)0x00100000) /*!< Calibration factors_4 in differential data */
+//#define ADC_CALFACT_CALFACTD_5 ((uint32_t)0x00200000) /*!< Calibration factors_5 in differential data */
+//#define ADC_CALFACT_CALFACTD_6 ((uint32_t)0x00400000) /*!< Calibration factors_6 in differential data */
+
+///******************** Bit definition for ADC_CTRL3 register ********************/
+//#define ADC_CTRL3_RES ((uint32_t)0x00000003) /*!< Resolution data */
+//#define ADC_CTRL3_RES_0 ((uint32_t)0x00000001) /*!< Resolution_0 data */
+//#define ADC_CTRL3_RES_1 ((uint32_t)0x00000002) /*!< Resolution_1 data */
+
+//#define ADC_CTRL3_CALDIF ((uint32_t)0x00000004) /*!< Differential mode for calibration enable */
+//#define ADC_CTRL3_CALALD ((uint32_t)0x00000008) /*!< Differential mode for calibration auto reload enable */
+//#define ADC_CTRL3_CKMOD ((uint32_t)0x00000010) /*!< Clock mode selection */
+//#define ADC_CTRL3_RDY ((uint32_t)0x00000020) /*!< Ready flag */
+//#define ADC_CTRL3_PDRDY ((uint32_t)0x00000040) /*!< Powerdown ready flag */
+//#define ADC_CTRL3_BPCAL ((uint32_t)0x00000080) /*!< Bypass calibration */
+//#define ADC_CTRL3_ENDCAIEN ((uint32_t)0x00000100) /*!< Interrupt enable for any regular channels */
+//#define ADC_CTRL3_JENDCAIEN ((uint32_t)0x00000200) /*!< Interrupt enable for any injected channels */
+//#define ADC_CTRL3_DPWMOD ((uint32_t)0x00000400) /*!< Deep Power Mode */
+//#define ADC_CTRL3_VBATMEN ((uint32_t)0x00000800) /*!< Vbat monitor enable */
+
+///******************** Bit definition for ADC_SAMPT3 register ********************/
+//#define ADC_SAMPT3_SAMP18 ((uint32_t)0x00000007) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
+//#define ADC_SAMPT3_SAMP18_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+//#define ADC_SAMPT3_SAMP18_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+//#define ADC_SAMPT3_SAMP18_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+//#define ADC_SAMPT3_SAMPSEL ((uint32_t)0x00000008) /*!< Sample time selection */
+
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DAC_CTRL register ********************/
+#define DAC_CTRL_CHEN ((uint32_t)0x00000001) /*!< DAC channel enable */
+#define DAC_CTRL_BEN ((uint32_t)0x00000002) /*!< DAC channel output buffer enable */
+#define DAC_CTRL_TEN ((uint32_t)0x00000004) /*!< DAC channel Trigger enable */
+
+#define DAC_CTRL_TSEL ((uint32_t)0x00000038) /*!< TSEL[2:0] (DAC channel Trigger selection) */
+#define DAC_CTRL_TSEL_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define DAC_CTRL_TSEL_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define DAC_CTRL_TSEL_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define DAC_CTRL_WEN ((uint32_t)0x000000C0) /*!< WEN[1:0] (DAC channel noise/triangle wave generation enable) */
+#define DAC_CTRL_WEN_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define DAC_CTRL_WEN_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define DAC_CTRL_MASEL ((uint32_t)0x00000F00) /*!< MASEL [3:0] (DAC channel Mask/Amplitude selector) */
+#define DAC_CTRL_MASEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DAC_CTRL_MASEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define DAC_CTRL_MASEL_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define DAC_CTRL_MASEL_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define DAC_CTRL_DMAEN ((uint32_t)0x00001000) /*!< DAC channel DMA enable */
+
+
+
+/***************** Bit definition for DAC_SOTTR register ******************/
+#define DAC_SOTTR_TREN ((uint8_t)0x01) /*!< DAC channel software trigger */
+
+
+/***************** Bit definition for DAC_DR12CH register ******************/
+#define DAC_DR12CH_DACCHD ((uint16_t)0x0FFF) /*!< DAC channel 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DL12CH register ******************/
+#define DAC_DL12CH_DACCHD ((uint16_t)0xFFF0) /*!< DAC channel 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DR8CH register ******************/
+#define DAC_DR8CH_DACCHD ((uint8_t)0xFF) /*!< DAC channel 8-bit Right aligned data */
+
+
+
+
+/******************* Bit definition for DAC_DATO register *******************/
+#define DAC_DATO_DACCHDO ((uint16_t)0x0FFF) /*!< DAC channel data output */
+
+
+
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for TIM_CTRL1 register ********************/
+#define TIM_CTRL1_CNTEN ((uint32_t)0x00000001) /*!< Counter enable */
+#define TIM_CTRL1_UPDIS ((uint32_t)0x00000002) /*!< Update disable */
+#define TIM_CTRL1_UPRS ((uint32_t)0x00000004) /*!< Update request source */
+#define TIM_CTRL1_ONEPM ((uint32_t)0x00000008) /*!< One pulse mode */
+#define TIM_CTRL1_DIR ((uint32_t)0x00000010) /*!< Direction */
+
+#define TIM_CTRL1_CAMSEL ((uint32_t)0x00000060) /*!< CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CTRL1_CAMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define TIM_CTRL1_CAMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+
+#define TIM_CTRL1_ARPEN ((uint32_t)0x00000080) /*!< Auto-reload preload enable */
+
+#define TIM_CTRL1_CLKD ((uint32_t)0x00000300) /*!< CKD[1:0] bits (clock division) */
+#define TIM_CTRL1_CLKD_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define TIM_CTRL1_CLKD_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define TIM_CTRL1_IOMBKPEN ((uint32_t)0x00000400) /*!< Break_in selection from IOM/COMP */
+#define TIM_CTRL1_C1SEL ((uint32_t)0x00000800) /*!< Channel 1 selection from IOM/COMP */
+#define TIM_CTRL1_C2SEL ((uint32_t)0x00001000) /*!< Channel 2 selection from IOM/COMP */
+#define TIM_CTRL1_C3SEL ((uint32_t)0x00002000) /*!< Channel 3 selection from IOM/COMP */
+#define TIM_CTRL1_C4SEL ((uint32_t)0x00004000) /*!< Channel 4 selection from IOM/COMP */
+#define TIM_CTRL1_CLRSEL ((uint32_t)0x00008000) /*!< OCxRef selection from ETR/COMP */
+
+#define TIM_CTRL1_LBKPEN ((uint32_t)0x00010000) /*!< LOCKUP as bkp Enable*/
+#define TIM_CTRL1_PBKPEN ((uint32_t)0x00020000) /*!< PVD as bkp Enable */
+
+/******************* Bit definition for TIM_CTRL2 register ********************/
+#define TIM_CTRL2_CCPCTL ((uint32_t)0x00000001) /*!< Capture/Compare Preloaded Control */
+#define TIM_CTRL2_CCUSEL ((uint32_t)0x00000004) /*!< Capture/Compare Control Update Selection */
+#define TIM_CTRL2_CCDSEL ((uint32_t)0x00000008) /*!< Capture/Compare DMA Selection */
+
+#define TIM_CTRL2_MMSEL ((uint32_t)0x00000070) /*!< MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CTRL2_MMSEL_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define TIM_CTRL2_MMSEL_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define TIM_CTRL2_MMSEL_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+
+#define TIM_CTRL2_TI1SEL ((uint32_t)0x00000080) /*!< TI1 Selection */
+#define TIM_CTRL2_OI1 ((uint32_t)0x00000100) /*!< Output Idle state 1 (OC1 output) */
+#define TIM_CTRL2_OI1N ((uint32_t)0x00000200) /*!< Output Idle state 1 (OC1N output) */
+#define TIM_CTRL2_OI2 ((uint32_t)0x00000400) /*!< Output Idle state 2 (OC2 output) */
+#define TIM_CTRL2_OI2N ((uint32_t)0x00000800) /*!< Output Idle state 2 (OC2N output) */
+#define TIM_CTRL2_OI3 ((uint32_t)0x00001000) /*!< Output Idle state 3 (OC3 output) */
+#define TIM_CTRL2_OI3N ((uint32_t)0x00002000) /*!< Output Idle state 3 (OC3N output) */
+#define TIM_CTRL2_OI4 ((uint32_t)0x00004000) /*!< Output Idle state 4 (OC4 output) */
+
+#define TIM_CTRL2_OI5 ((uint32_t)0x00010000) /*!< Output Idle state 5 (OC5 output) */
+#define TIM_CTRL2_OI6 ((uint32_t)0x00040000) /*!< Output Idle state 6 (OC6 output) */
+
+/******************* Bit definition for TIM_SMCTRL register *******************/
+#define TIM_SMCTRL_SMSEL ((uint16_t)0x0007) /*!< SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCTRL_SMSEL_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_SMCTRL_SMSEL_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define TIM_SMCTRL_SMSEL_2 ((uint16_t)0x0004) /*!< Bit 2 */
+
+#define TIM_SMCTRL_TSEL ((uint16_t)0x0070) /*!< TS[2:0] bits (Trigger selection) */
+#define TIM_SMCTRL_TSEL_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_SMCTRL_TSEL_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_SMCTRL_TSEL_2 ((uint16_t)0x0040) /*!< Bit 2 */
+
+#define TIM_SMCTRL_MSMD ((uint16_t)0x0080) /*!< Master/slave mode */
+
+#define TIM_SMCTRL_EXTF ((uint16_t)0x0F00) /*!< ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCTRL_EXTF_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_SMCTRL_EXTF_1 ((uint16_t)0x0200) /*!< Bit 1 */
+#define TIM_SMCTRL_EXTF_2 ((uint16_t)0x0400) /*!< Bit 2 */
+#define TIM_SMCTRL_EXTF_3 ((uint16_t)0x0800) /*!< Bit 3 */
+
+#define TIM_SMCTRL_EXTPS ((uint16_t)0x3000) /*!< ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCTRL_EXTPS_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_SMCTRL_EXTPS_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define TIM_SMCTRL_EXCEN ((uint16_t)0x4000) /*!< External clock enable */
+#define TIM_SMCTRL_EXTP ((uint16_t)0x8000) /*!< External trigger polarity */
+
+/******************* Bit definition for TIM_DINTEN register *******************/
+#define TIM_DINTEN_UIEN ((uint16_t)0x0001) /*!< Update interrupt enable */
+#define TIM_DINTEN_CC1IEN ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt enable */
+#define TIM_DINTEN_CC2IEN ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt enable */
+#define TIM_DINTEN_CC3IEN ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt enable */
+#define TIM_DINTEN_CC4IEN ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt enable */
+#define TIM_DINTEN_COMIEN ((uint16_t)0x0020) /*!< COM interrupt enable */
+#define TIM_DINTEN_TIEN ((uint16_t)0x0040) /*!< Trigger interrupt enable */
+#define TIM_DINTEN_BIEN ((uint16_t)0x0080) /*!< Break interrupt enable */
+#define TIM_DINTEN_UDEN ((uint16_t)0x0100) /*!< Update DMA request enable */
+#define TIM_DINTEN_CC1DEN ((uint16_t)0x0200) /*!< Capture/Compare 1 DMA request enable */
+#define TIM_DINTEN_CC2DEN ((uint16_t)0x0400) /*!< Capture/Compare 2 DMA request enable */
+#define TIM_DINTEN_CC3DEN ((uint16_t)0x0800) /*!< Capture/Compare 3 DMA request enable */
+#define TIM_DINTEN_CC4DEN ((uint16_t)0x1000) /*!< Capture/Compare 4 DMA request enable */
+#define TIM_DINTEN_COMDEN ((uint16_t)0x2000) /*!< COM DMA request enable */
+#define TIM_DINTEN_TDEN ((uint16_t)0x4000) /*!< Trigger DMA request enable */
+
+/******************** Bit definition for TIM_STS register ********************/
+#define TIM_STS_UDITF ((uint32_t)0x00000001) /*!< Update interrupt Flag */
+#define TIM_STS_CC1ITF ((uint32_t)0x00000002) /*!< Capture/Compare 1 interrupt Flag */
+#define TIM_STS_CC2ITF ((uint32_t)0x00000004) /*!< Capture/Compare 2 interrupt Flag */
+#define TIM_STS_CC3ITF ((uint32_t)0x00000008) /*!< Capture/Compare 3 interrupt Flag */
+#define TIM_STS_CC4ITF ((uint32_t)0x00000010) /*!< Capture/Compare 4 interrupt Flag */
+#define TIM_STS_COMITF ((uint32_t)0x00000020) /*!< COM interrupt Flag */
+#define TIM_STS_TITF ((uint32_t)0x00000040) /*!< Trigger interrupt Flag */
+#define TIM_STS_BITF ((uint32_t)0x00000080) /*!< Break interrupt Flag */
+#define TIM_STS_CC1OCF ((uint32_t)0x00000200) /*!< Capture/Compare 1 Overcapture Flag */
+#define TIM_STS_CC2OCF ((uint32_t)0x00000400) /*!< Capture/Compare 2 Overcapture Flag */
+#define TIM_STS_CC3OCF ((uint32_t)0x00000800) /*!< Capture/Compare 3 Overcapture Flag */
+#define TIM_STS_CC4OCF ((uint32_t)0x00001000) /*!< Capture/Compare 4 Overcapture Flag */
+
+#define TIM_STS_CC5ITF ((uint32_t)0x00010000) /*!< Capture/Compare 5 interrupt Flag */
+#define TIM_STS_CC6ITF ((uint32_t)0x00020000) /*!< Capture/Compare 6 interrupt Flag */
+
+/******************* Bit definition for TIM_EVTGEN register ********************/
+#define TIM_EVTGEN_UDGN ((uint8_t)0x01) /*!< Update Generation */
+#define TIM_EVTGEN_CC1GN ((uint8_t)0x02) /*!< Capture/Compare 1 Generation */
+#define TIM_EVTGEN_CC2GN ((uint8_t)0x04) /*!< Capture/Compare 2 Generation */
+#define TIM_EVTGEN_CC3GN ((uint8_t)0x08) /*!< Capture/Compare 3 Generation */
+#define TIM_EVTGEN_CC4GN ((uint8_t)0x10) /*!< Capture/Compare 4 Generation */
+#define TIM_EVTGEN_CCUDGN ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation */
+#define TIM_EVTGEN_TGN ((uint8_t)0x40) /*!< Trigger Generation */
+#define TIM_EVTGEN_BGN ((uint8_t)0x80) /*!< Break Generation */
+
+/****************** Bit definition for TIM_CCMOD1 register *******************/
+#define TIM_CCMOD1_CC1SEL ((uint16_t)0x0003) /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMOD1_CC1SEL_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_CCMOD1_CC1SEL_1 ((uint16_t)0x0002) /*!< Bit 1 */
+
+#define TIM_CCMOD1_OC1FEN ((uint16_t)0x0004) /*!< Output Compare 1 Fast enable */
+#define TIM_CCMOD1_OC1PEN ((uint16_t)0x0008) /*!< Output Compare 1 Preload enable */
+
+#define TIM_CCMOD1_OC1M ((uint16_t)0x0070) /*!< OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMOD1_OC1M_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMOD1_OC1M_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMOD1_OC1M_2 ((uint16_t)0x0040) /*!< Bit 2 */
+
+#define TIM_CCMOD1_OC1CEN ((uint16_t)0x0080) /*!< Output Compare 1Clear Enable */
+
+#define TIM_CCMOD1_CC2SEL ((uint16_t)0x0300) /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMOD1_CC2SEL_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_CCMOD1_CC2SEL_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define TIM_CCMOD1_OC2FEN ((uint16_t)0x0400) /*!< Output Compare 2 Fast enable */
+#define TIM_CCMOD1_OC2PEN ((uint16_t)0x0800) /*!< Output Compare 2 Preload enable */
+
+#define TIM_CCMOD1_OC2M ((uint16_t)0x7000) /*!< OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMOD1_OC2M_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMOD1_OC2M_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMOD1_OC2M_2 ((uint16_t)0x4000) /*!< Bit 2 */
+
+#define TIM_CCMOD1_OC2CEN ((uint16_t)0x8000) /*!< Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMOD1_IC1PSC ((uint16_t)0x000C) /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMOD1_IC1PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */
+#define TIM_CCMOD1_IC1PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */
+
+#define TIM_CCMOD1_IC1F ((uint16_t)0x00F0) /*!< IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMOD1_IC1F_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMOD1_IC1F_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMOD1_IC1F_2 ((uint16_t)0x0040) /*!< Bit 2 */
+#define TIM_CCMOD1_IC1F_3 ((uint16_t)0x0080) /*!< Bit 3 */
+
+#define TIM_CCMOD1_IC2PSC ((uint16_t)0x0C00) /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMOD1_IC2PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define TIM_CCMOD1_IC2PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define TIM_CCMOD1_IC2F ((uint16_t)0xF000) /*!< IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMOD1_IC2F_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMOD1_IC2F_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMOD1_IC2F_2 ((uint16_t)0x4000) /*!< Bit 2 */
+#define TIM_CCMOD1_IC2F_3 ((uint16_t)0x8000) /*!< Bit 3 */
+
+/****************** Bit definition for TIM_CCMOD2 register *******************/
+#define TIM_CCMOD2_CC3SEL ((uint16_t)0x0003) /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMOD2_CC3SEL_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_CCMOD2_CC3SEL_1 ((uint16_t)0x0002) /*!< Bit 1 */
+
+#define TIM_CCMOD2_OC3FEN ((uint16_t)0x0004) /*!< Output Compare 3 Fast enable */
+#define TIM_CCMOD2_OC3PEN ((uint16_t)0x0008) /*!< Output Compare 3 Preload enable */
+
+#define TIM_CCMOD2_OC3MD ((uint16_t)0x0070) /*!< OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMOD2_OC3MD_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMOD2_OC3MD_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMOD2_OC3MD_2 ((uint16_t)0x0040) /*!< Bit 2 */
+
+#define TIM_CCMOD2_OC3CEN ((uint16_t)0x0080) /*!< Output Compare 3 Clear Enable */
+
+#define TIM_CCMOD2_CC4SEL ((uint16_t)0x0300) /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMOD2_CC4SEL_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_CCMOD2_CC4SEL_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define TIM_CCMOD2_OC4FEN ((uint16_t)0x0400) /*!< Output Compare 4 Fast enable */
+#define TIM_CCMOD2_OC4PEN ((uint16_t)0x0800) /*!< Output Compare 4 Preload enable */
+
+#define TIM_CCMOD2_OC4MD ((uint16_t)0x7000) /*!< OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMOD2_OC4MD_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMOD2_OC4MD_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMOD2_OC4MD_2 ((uint16_t)0x4000) /*!< Bit 2 */
+
+#define TIM_CCMOD2_OC4CEN ((uint16_t)0x8000) /*!< Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMOD2_IC3PSC ((uint16_t)0x000C) /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMOD2_IC3PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */
+#define TIM_CCMOD2_IC3PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */
+
+#define TIM_CCMOD2_IC3F ((uint16_t)0x00F0) /*!< IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMOD2_IC3F_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMOD2_IC3F_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMOD2_IC3F_2 ((uint16_t)0x0040) /*!< Bit 2 */
+#define TIM_CCMOD2_IC3F_3 ((uint16_t)0x0080) /*!< Bit 3 */
+
+#define TIM_CCMOD2_IC4PSC ((uint16_t)0x0C00) /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMOD2_IC4PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define TIM_CCMOD2_IC4PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define TIM_CCMOD2_IC4F ((uint16_t)0xF000) /*!< IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMOD2_IC4F_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMOD2_IC4F_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMOD2_IC4F_2 ((uint16_t)0x4000) /*!< Bit 2 */
+#define TIM_CCMOD2_IC4F_3 ((uint16_t)0x8000) /*!< Bit 3 */
+
+/****************** Bit definition for TIM_CCMOD3 register *******************/
+#define TIM_CCMOD3_OC5FEN ((uint16_t)0x0004) /*!< Output Compare 5 Fast enable */
+#define TIM_CCMOD3_OC5PEN ((uint16_t)0x0008) /*!< Output Compare 5 Preload enable */
+
+#define TIM_CCMOD3_OC5MD ((uint16_t)0x0070) /*!< OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMOD3_OC5MD_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMOD3_OC5MD_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMOD3_OC5MD_2 ((uint16_t)0x0040) /*!< Bit 2 */
+
+#define TIM_CCMOD3_OC5CEN ((uint16_t)0x0080) /*!< Output Compare 5Clear Enable */
+
+#define TIM_CCMOD3_OC6FEN ((uint16_t)0x0400) /*!< Output Compare 6 Fast enable */
+#define TIM_CCMOD3_OC6PEN ((uint16_t)0x0800) /*!< Output Compare 6 Preload enable */
+
+#define TIM_CCMOD3_OC6MD ((uint16_t)0x7000) /*!< OC6M[2:0] bits (Output Compare 6 Mode) */
+#define TIM_CCMOD3_OC6MD_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMOD3_OC6MD_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMOD3_OC6MD_2 ((uint16_t)0x4000) /*!< Bit 2 */
+
+#define TIM_CCMOD3_OC6CEN ((uint16_t)0x8000) /*!< Output Compare 6 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+/******************* Bit definition for TIM_CCEN register *******************/
+#define TIM_CCEN_CC1EN ((uint32_t)0x00000001) /*!< Capture/Compare 1 output enable */
+#define TIM_CCEN_CC1P ((uint32_t)0x00000002) /*!< Capture/Compare 1 output Polarity */
+#define TIM_CCEN_CC1NEN ((uint32_t)0x00000004) /*!< Capture/Compare 1 Complementary output enable */
+#define TIM_CCEN_CC1NP ((uint32_t)0x00000008) /*!< Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCEN_CC2EN ((uint32_t)0x00000010) /*!< Capture/Compare 2 output enable */
+#define TIM_CCEN_CC2P ((uint32_t)0x00000020) /*!< Capture/Compare 2 output Polarity */
+#define TIM_CCEN_CC2NEN ((uint32_t)0x00000040) /*!< Capture/Compare 2 Complementary output enable */
+#define TIM_CCEN_CC2NP ((uint32_t)0x00000080) /*!< Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCEN_CC3EN ((uint32_t)0x00000100) /*!< Capture/Compare 3 output enable */
+#define TIM_CCEN_CC3P ((uint32_t)0x00000200) /*!< Capture/Compare 3 output Polarity */
+#define TIM_CCEN_CC3NEN ((uint32_t)0x00000400) /*!< Capture/Compare 3 Complementary output enable */
+#define TIM_CCEN_CC3NP ((uint32_t)0x00000800) /*!< Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCEN_CC4EN ((uint32_t)0x00001000) /*!< Capture/Compare 4 output enable */
+#define TIM_CCEN_CC4P ((uint32_t)0x00002000) /*!< Capture/Compare 4 output Polarity */
+
+#define TIM_CCEN_CC5EN ((uint32_t)0x00010000) /*!< Capture/Compare 5 output enable */
+#define TIM_CCEN_CC5P ((uint32_t)0x00020000) /*!< Capture/Compare 5 output Polarity */
+#define TIM_CCEN_CC6EN ((uint32_t)0x00100000) /*!< Capture/Compare 6 output enable */
+#define TIM_CCEN_CC6P ((uint32_t)0x00200000) /*!< Capture/Compare 6 output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!< Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!< Prescaler Value */
+
+/******************* Bit definition for TIM_AR register ********************/
+#define TIM_AR_AR ((uint16_t)0xFFFF) /*!< actual auto-reload Value */
+
+/******************* Bit definition for TIM_REPCNT register ********************/
+#define TIM_REPCNT_REPCNT ((uint8_t)0xFF) /*!< Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCDAT1 register *******************/
+#define TIM_CCDAT1_CCDAT1 ((uint16_t)0xFFFF) /*!< Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCDAT2 register *******************/
+#define TIM_CCDAT2_CCDAT2 ((uint16_t)0xFFFF) /*!< Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCDAT3 register *******************/
+#define TIM_CCDAT3_CCDAT3 ((uint16_t)0xFFFF) /*!< Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCDAT4 register *******************/
+#define TIM_CCDAT4_CCDAT4 ((uint16_t)0xFFFF) /*!< Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_CCDAT5 register *******************/
+#define TIM_CCDAT5_CCDAT5 ((uint16_t)0xFFFF) /*!< Capture/Compare 5 Value */
+
+/******************* Bit definition for TIM_CCDAT6 register *******************/
+#define TIM_CCDAT6_CCDAT6 ((uint16_t)0xFFFF) /*!< Capture/Compare 6 Value */
+
+/******************* Bit definition for TIM_BKDT register *******************/
+#define TIM_BKDT_DTGN ((uint16_t)0x00FF) /*!< DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BKDT_DTGN_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_BKDT_DTGN_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define TIM_BKDT_DTGN_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define TIM_BKDT_DTGN_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define TIM_BKDT_DTGN_4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define TIM_BKDT_DTGN_5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define TIM_BKDT_DTGN_6 ((uint16_t)0x0040) /*!< Bit 6 */
+#define TIM_BKDT_DTGN_7 ((uint16_t)0x0080) /*!< Bit 7 */
+
+#define TIM_BKDT_LCKCFG ((uint16_t)0x0300) /*!< LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BKDT_LCKCFG_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_BKDT_LCKCFG_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define TIM_BKDT_OSSI ((uint16_t)0x0400) /*!< Off-State Selection for Idle mode */
+#define TIM_BKDT_OSSR ((uint16_t)0x0800) /*!< Off-State Selection for Run mode */
+#define TIM_BKDT_BKEN ((uint16_t)0x1000) /*!< Break enable */
+#define TIM_BKDT_BKP ((uint16_t)0x2000) /*!< Break Polarity */
+#define TIM_BKDT_AOEN ((uint16_t)0x4000) /*!< Automatic Output enable */
+#define TIM_BKDT_MOEN ((uint16_t)0x8000) /*!< Main Output enable */
+
+/******************* Bit definition for TIM_DCTRL register ********************/
+#define TIM_DCTRL_DBADDR ((uint16_t)0x001F) /*!< DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCTRL_DBADDR_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_DCTRL_DBADDR_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define TIM_DCTRL_DBADDR_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define TIM_DCTRL_DBADDR_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define TIM_DCTRL_DBADDR_4 ((uint16_t)0x0010) /*!< Bit 4 */
+
+#define TIM_DCTRL_DBLEN ((uint16_t)0x1F00) /*!< DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCTRL_DBLEN_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_DCTRL_DBLEN_1 ((uint16_t)0x0200) /*!< Bit 1 */
+#define TIM_DCTRL_DBLEN_2 ((uint16_t)0x0400) /*!< Bit 2 */
+#define TIM_DCTRL_DBLEN_3 ((uint16_t)0x0800) /*!< Bit 3 */
+#define TIM_DCTRL_DBLEN_4 ((uint16_t)0x1000) /*!< Bit 4 */
+
+/******************* Bit definition for TIM_DADDR register *******************/
+#define TIM_DADDR_BURST ((uint16_t)0xFFFF) /*!< DMA register for burst accesses */
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_INTSTS register *******************/
+#define LPTIM_INTSTS_CMPM ((uint32_t)0x00000001) /*!< Compare match */
+#define LPTIM_INTSTS_ARRM ((uint32_t)0x00000002) /*!< Autoreload match */
+#define LPTIM_INTSTS_EXTRIG ((uint32_t)0x00000004) /*!< External trigger edge event */
+#define LPTIM_INTSTS_CMPUPD ((uint32_t)0x00000008) /*!< Compare register update OK */
+#define LPTIM_INTSTS_ARRUPD ((uint32_t)0x00000010) /*!< Autoreload register update OK */
+#define LPTIM_INTSTS_UP ((uint32_t)0x00000020) /*!< Counter direction change down to up */
+#define LPTIM_INTSTS_DOWN ((uint32_t)0x00000040) /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_INTCLR register *******************/
+#define LPTIM_INTCLR_CMPMCF ((uint32_t)0x00000001) /*!< Compare match Clear Flag */
+#define LPTIM_INTCLR_ARRMCF ((uint32_t)0x00000002) /*!< Autoreload match Clear Flag */
+#define LPTIM_INTCLR_EXTRIGCF ((uint32_t)0x00000004) /*!< External trigger edge event Clear Flag */
+#define LPTIM_INTCLR_CMPUPDCF ((uint32_t)0x00000008) /*!< Compare register update OK Clear Flag */
+#define LPTIM_INTCLR_ARRUPDCF ((uint32_t)0x00000010) /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_INTCLR_UPCF ((uint32_t)0x00000020) /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_INTCLR_DOWNCF ((uint32_t)0x00000040) /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_INTEN register ********************/
+#define LPTIM_INTEN_CMPMIE ((uint32_t)0x00000001) /*!< Compare match Interrupt Enable */
+#define LPTIM_INTEN_ARRMIE ((uint32_t)0x00000002) /*!< Autoreload match Interrupt Enable */
+#define LPTIM_INTEN_EXTRIGIE ((uint32_t)0x00000004) /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_INTEN_CMPUPDIE ((uint32_t)0x00000008) /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_INTEN_ARRUPDIE ((uint32_t)0x00000010) /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_INTEN_UPIE ((uint32_t)0x00000020) /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_INTEN_DOWNIE ((uint32_t)0x00000040) /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFG register *******************/
+#define LPTIM_CFG_CLKSEL ((uint32_t)0x00000001) /*!< Clock selector */
+
+#define LPTIM_CFG_CLKPOL ((uint32_t)0x00000006) /*!< CLKP[1:0] bits (Clock polarity) */
+#define LPTIM_CFG_CLKPOL_0 ((uint32_t)0x00000002) /*!< 0x00000002 */
+#define LPTIM_CFG_CLKPOL_1 ((uint32_t)0x00000004) /*!< 0x00000004 */
+
+#define LPTIM_CFG_CLKFLT ((uint32_t)0x00000018) /*!< CFGDFFEXT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFG_CLKFLT_0 ((uint32_t)0x00000008) /*!< 0x00000008 */
+#define LPTIM_CFG_CLKFLT_1 ((uint32_t)0x00000010) /*!< 0x00000010 */
+
+#define LPTIM_CFG_TRIGFLT ((uint32_t)0x000000C0) /*!< CFGDFFTRG[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFG_TRIGFLT_0 ((uint32_t)0x00000040) /*!< 0x00000040 */
+#define LPTIM_CFG_TRIGFLT_1 ((uint32_t)0x00000080) /*!< 0x00000080 */
+
+#define LPTIM_CFG_CLKPRE ((uint32_t)0x00000E00) /*!< CLKPRE[2:0] bits (Clock prescaler) */
+#define LPTIM_CFG_CLKPRE_0 ((uint32_t)0x00000200) /*!< 0x00000200 */
+#define LPTIM_CFG_CLKPRE_1 ((uint32_t)0x00000400) /*!< 0x00000400 */
+#define LPTIM_CFG_CLKPRE_2 ((uint32_t)0x00000800) /*!< 0x00000800 */
+
+#define LPTIM_CFG_TRGSEL ((uint32_t)0x0000E000) /*!< TRGS[2:0]] bits (Trigger selector) */
+#define LPTIM_CFG_TRGSEL_0 ((uint32_t)0x00002000) /*!< 0x00002000 */
+#define LPTIM_CFG_TRGSEL_1 ((uint32_t)0x00004000) /*!< 0x00004000 */
+#define LPTIM_CFG_TRGSEL_2 ((uint32_t)0x00008000) /*!< 0x00008000 */
+
+#define LPTIM_CFG_TRGEN ((uint32_t)0x00060000) /*!< TRGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFG_TRGEN_0 ((uint32_t)0x00020000) /*!< 0x00020000 */
+#define LPTIM_CFG_TRGEN_1 ((uint32_t)0x00040000) /*!< 0x00040000 */
+
+#define LPTIM_CFG_TIMOUTEN ((uint32_t)0x00080000) /*!< Timout enable */
+#define LPTIM_CFG_WAVE ((uint32_t)0x00100000) /*!< Waveform shape */
+#define LPTIM_CFG_WAVEPOL ((uint32_t)0x00200000) /*!< Waveform shape polarity */
+#define LPTIM_CFG_RELOAD ((uint32_t)0x00400000) /*!< Reg update mode */
+#define LPTIM_CFG_CNTMEN ((uint32_t)0x00800000) /*!< Counter mode enable */
+#define LPTIM_CFG_ENC ((uint32_t)0x01000000) /*!< Encoder mode enable */
+#define LPTIM_CFG_NENC ((uint32_t)0x02000000) /*!< NONEncoder mode enable */
+/****************** Bit definition for LPTIM_CTRL register ********************/
+#define LPTIM_CTRL_LPTIMEN ((uint32_t)0x000000001) /*!< LPTIMer enable */
+#define LPTIM_CTRL_SNGMST ((uint32_t)0x000000002) /*!< Timer start in single mode */
+#define LPTIM_CTRL_TSTCM ((uint32_t)0x000000004) /*!< Timer start in continuous mode */
+
+/****************** Bit definition for LPTIM_CMPT register *******************/
+#define LPTIM_COMP_CMPVAL ((uint16_t)0xFFFF) /*!< Compare register */
+
+/****************** Bit definition for LPTIM_AUTRLD register *******************/
+#define LPTIM_ARR_ARRVAL ((uint16_t)0xFFFF) /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNTVAL ((uint16_t)0xFFFF) /*!< Counter register */
+/******************************************************************************/
+/* */
+/* Low-Power RCNT (LPRCNT) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for LPRCNT_CTRL register *******************/
+#define LPRCNT_CTRL_RPTTH ((uint32_t)0x0000FFFF) /*!< threshold of RCNT value, interrupt to wake up CPU when the value reach it */
+#define LPRCNT_CTRL_CLKDIV ((uint32_t)0x00030000) /*!< MSI clock to decide processing precision of sensors */
+#define LPRCNT_CTRL_AVGSEL ((uint32_t)0x000C0000) /*!< auto calculate average data for multi time */
+#define LPRCNT_CTRL_CNTDIR ((uint32_t)0x00100000) /*!< direction mode, turn lprcnt counting to the opposite direction */
+
+#define LPRCNT_CTRL_PWRLVL ((uint32_t)0x00600000) /*!< power level select */
+#define LPRCNT_CTRL_PWRLVL1V5 ((uint32_t)0x00000000) /*!< power level select 1.5V */
+#define LPRCNT_CTRL_PWRLVL1V6 ((uint32_t)0x00200000) /*!< power level select 1.6V */
+#define LPRCNT_CTRL_PWRLVL1V8 ((uint32_t)0x00400000) /*!< power level select 1.8V */
+#define LPRCNT_CTRL_PWRLVL2V ((uint32_t)0x00600000) /*!< power level select 2.0V */
+#define LPRCNT_CTRL_CMPAUT ((uint32_t)0x00800000) /*!< enable to auto detect comparator stop */
+#define LPRCNT_CTRL_RCNTM ((uint32_t)0x01000000) /*!< RCNT RUN mode enable */
+#define LPRCNT_CTRL_CALM ((uint32_t)0x02000000) /*!< sensor data processing mode in RCNT debug mode */
+#define LPRCNT_CTRL_ALMPRD ((uint32_t)0x0C000000) /*!< the alarm sensor prescale */
+#define LPRCNT_CTRL_ALMPRD4 ((uint32_t)0x00000000) /*!< the alarm sensor prescale /4 */
+#define LPRCNT_CTRL_ALMPRD8 ((uint32_t)0x04000000) /*!< the alarm sensor prescale /8 */
+#define LPRCNT_CTRL_ALMPRD16 ((uint32_t)0x08000000) /*!< the alarm sensor prescale /16 */
+#define LPRCNT_CTRL_ALMPRD32 ((uint32_t)0x0C000000) /*!< the alarm sensor prescale /32 */
+
+#define LPRCNT_CTRL_ALMIE ((uint32_t)0x10000000) /*!< the alarm sensor interruput enable */
+#define LPRCNT_CTRL_RPTIE ((uint32_t)0x20000000) /*!< reading interruput enable */
+#define LPRCNT_CTRL_CALIE ((uint32_t)0x40000000) /*!< the sensor debug mode interruput enable */
+
+/******************** Bits definition for LPRCNT_INTSTS register *******************/
+#define LPRCNT_INTSTS_RPTVAL ((uint32_t)0x0000FFFF) /*!< lprcnt counter value report */
+#define LPRCNT_INTSTS_ALMIF ((uint32_t)0x00010000) /*!< RCNT alarm interrupt status*/
+#define LPRCNT_INTSTS_RPTIF ((uint32_t)0x00020000) /*!< RCNT read interrupt status*/
+#define LPRCNT_INTSTS_CALIF ((uint32_t)0x00040000) /*!< RCNT debug interrupt status*/
+
+/******************** Bits definition for LPRCNT_SCTRL register *******************/
+#define LPRCNT_SCTRL_HSPRD ((uint32_t)0x000000FF) /*!< lprcnt high mode scan period */
+#define LPRCNT_SCTRL_SWT ((uint32_t)0x0000FF00) /*!< lprcnt high mode VS low mode switch time */
+#define LPRCNT_SCTRL_LSPRD ((uint32_t)0x03FF0000) /*!< lprcnt low mode scan period */
+
+/******************** Bits definition for LPRCNT_CH0CFG0 register *******************/
+#define LPRCNT_CH0CFG0_DAMTH ((uint32_t)0x000000FF) /*!< sensor channel 0 damped threshold,less than to be detect damped */
+#define LPRCNT_CH0CFG0_UNDTH ((uint32_t)0x0000FF00) /*!< sensor channel 0 undamped threshold,less than to be detect undamped */
+#define LPRCNT_CH0CFG0_DACREF ((uint32_t)0x003F0000) /*!< sensor channel 0 damped threshold,less than to be detect damped */
+
+/******************** Bits definition for LPRCNT_CH0CFG1 register *******************/
+#define LPRCNT_CH0CFG1_CHGDUR ((uint32_t)0x0000003F) /*!< power processing duration length */
+#define LPRCNT_CH0CFG1_DSCDUR ((uint32_t)0x00003F00) /*!< discharge processing duration length */
+#define LPRCNT_CH0CFG1_DAMDUR ((uint32_t)0x00FF0000) /*!< comparator processing duration length */
+/******************** Bits definition for LPRCNT_CH1CFG0 register *******************/
+#define LPRCNT_CH1CFG0_DAMTH ((uint32_t)0x000000FF) /*!< sensor channel 1 damped threshold,less than to be detect damped */
+#define LPRCNT_CH1CFG0_UNDTH ((uint32_t)0x0000FF00) /*!< sensor channel 1 undamped threshold,less than to be detect undamped */
+#define LPRCNT_CH1CFG0_DACREF ((uint32_t)0x003F0000) /*!< sensor channel 1 damped threshold,less than to be detect damped */
+
+/******************** Bits definition for LPRCNT_CH1CFG1 register *******************/
+#define LPRCNT_CH1CFG1_CHGDUR ((uint32_t)0x0000003F) /*!< power processing duration length */
+#define LPRCNT_CH1CFG1_DSCDUR ((uint32_t)0x00003F00) /*!< discharge processing duration length */
+#define LPRCNT_CH1CFG1_DAMDUR ((uint32_t)0x00FF0000) /*!< comparator processing duration length */
+/******************** Bits definition for LPRCNT_CH2CFG0 register *******************/
+#define LPRCNT_CH2CFG0_DAMTH ((uint32_t)0x000000FF) /*!< sensor channel 2 damped threshold,less than to be detect damped */
+#define LPRCNT_CH2CFG0_UNDTH ((uint32_t)0x0000FF00) /*!< sensor channel 2 undamped threshold,less than to be detect undamped */
+#define LPRCNT_CH2CFG0_DACREF ((uint32_t)0x003F0000) /*!< sensor channel 2 damped threshold,less than to be detect damped */
+
+/******************** Bits definition for LPRCNT_CH2CFG1 register *******************/
+#define LPRCNT_CH2CFG1_CHGDUR ((uint32_t)0x0000003F) /*!< power processing duration length */
+#define LPRCNT_CH2CFG1_DSCDUR ((uint32_t)0x00003F00) /*!< discharge processing duration length */
+#define LPRCNT_CH2CFG1_DAMDUR ((uint32_t)0x00FF0000) /*!< comparator processing duration length */
+
+/******************** Bits definition for LPRCNT_CMD register *******************/
+#define LPRCNT_CMD_START ((uint32_t)0x00000001) /*!< start LPRCNT processing */
+#define LPRCNT_CMD_STOP ((uint32_t)0x00000002) /*!< stop LPRCNT processing */
+#define LPRCNT_CMD_CLRCNT ((uint32_t)0x00000004) /*!< clear LPRCNT count */
+
+/******************** Bits definition for LPRCNT_CAL0 register *******************/
+#define LPRCNT_CAL0_CH0CNT ((uint32_t)0x000000FF) /*!< sensor channel 0,comparator output valid count */
+
+#define LPRCNT_CAL0_CH0STS_UND ((uint32_t)0x00000000) /*!< sensor channel 0 undamped state */
+#define LPRCNT_CAL0_CH0STS_MID ((uint32_t)0x00000100) /*!< sensor channel 0 middle state */
+#define LPRCNT_CAL0_CH0STS_DAM ((uint32_t)0x00000200) /*!< sensor channel 0 damped state */
+
+#define LPRCNT_CAL0_CH1CNT ((uint32_t)0x00FF0000) /*!< sensor channel 1,comparator output valid count */
+
+#define LPRCNT_CAL0_CH1STS_UND ((uint32_t)0x00000000) /*!< sensor channel 1 undamped state */
+#define LPRCNT_CAL0_CH1STS_MID ((uint32_t)0x01000000) /*!< sensor channel 1 middle state */
+#define LPRCNT_CAL0_CH1STS_DAM ((uint32_t)0x02000000) /*!< sensor channel 1 damped state */
+/******************** Bits definition for LPRCNT_CAL1 register *******************/
+#define LPRCNT_CAL1_CH2CNT ((uint32_t)0x000000FF) /*!< sensor channel 0,comparator output valid count */
+
+#define LPRCNT_CAL1_CH2STS_UND ((uint32_t)0x00000000) /*!< sensor channel 2 undamped state */
+#define LPRCNT_CAL1_CH2STS_MID ((uint32_t)0x00000100) /*!< sensor channel 2 middle state */
+#define LPRCNT_CAL1_CH2STS_DAM ((uint32_t)0x00000200) /*!< sensor channel 2 damped state */
+
+/******************** Bits definition for LPRCNT_CAL2 register *******************/
+#define LPRCNT_CAL2_DACSET ((uint32_t)0x0000003F) /*!< sensor channel DAC setup time */
+#define LPRCNT_CAL2_CMPSET ((uint32_t)0x00003F00) /*!< sensor channel comparator setup time */
+#define LPRCNT_CAL2_GAP ((uint32_t)0x000F0000) /*!< charge to discharge gap time length */
+#define LPRCNT_CAL2_RCNTADJ ((uint32_t)0x00F00000) /*!< adjust number for slow switch fast lost */
+#define LPRCNT_CAL2_SAMPMODE ((uint32_t)0x02000000) /*!< LPRCNT module sample mode */
+
+/******************** Bits definition for LPRCNT_CAL3 register *******************/
+#define LPRCNT_CAL3_CMP_AUTO_MODE ((uint32_t)0x00000040) /*!< when enter the mode of auto detect comparator stop, the period of duty wait clock */
+#define LPRCNT_CAL3_PWR_DUR_EN ((uint32_t)0x00000080) /*!< LDO powering sensors by time duration */
+#define LPRCNT_CAL3_STAT_CLR_CTRL ((uint32_t)0x00000100) /*!< Whether clear state on fast mode to slow mode */
+#define LPRCNT_CAL3_DAC_CMP_ALWSON ((uint32_t)0x00000200) /*!< DAC & CMP always on enable while 1 round sampling */
+#define LPRCNT_CAL3_CMP_HYSEL ((uint32_t)0x00000C00) /*!< Comparator hysteresis selection */
+#define LPRCNT_CAL3_CMP_HYSEL_NULL ((uint32_t)0x00000000) /*!< Comparator hysteresis disable */
+#define LPRCNT_CAL3_CMP_HYSEL_LOW ((uint32_t)0x00000400) /*!< select low Comparator hysteresis */
+#define LPRCNT_CAL3_CMP_HYSEL_MID ((uint32_t)0x00000800) /*!< select middle Comparator hysteresis */
+#define LPRCNT_CAL3_CMP_HYSEL_HIGH ((uint32_t)0x00000C00) /*!< select high Comparator hysteresis */
+#define LPRCNT_CAL3_CMP_INMSEL ((uint32_t)0x00007000) /*!< COMP input minus selection bits */
+#define LPRCNT_CAL3_CMP_LPEN ((uint32_t)0x00008000) /*!< COMP low power enable */
+
+#define LPRCNT_CAL3_ANGFILEN ((uint32_t)0x00200000) /*!< Analog filtering anable bit */
+#define LPRCNT_CAL3_DIGFILPH ((uint32_t)0x00400000) /*!< Digital filter phase control */
+#define LPRCNT_CAL3_DIGFILPH_P ((uint32_t)0x00000000) /*!< Digital filter phase selection positive */
+#define LPRCNT_CAL3_DIGFILPH_N ((uint32_t)0x00400000) /*!< Digital filter phase selection negative */
+#define LPRCNT_CAL3_FILTH ((uint32_t)0x01800000) /*!< Filter threshold control*/
+#define LPRCNT_CAL3_DIGFILEN ((uint32_t)0x02000000) /*!< Digital filtering anable bit */
+#define LPRCNT_CAL3_CH0MAP ((uint32_t)0x0C000000) /*!< CH0 map to which sensor select */
+#define LPRCNT_CAL3_CH1MAP ((uint32_t)0x30000000) /*!< CH1 map to which sensor select */
+#define LPRCNT_CAL3_CH2MAP ((uint32_t)0xC0000000) /*!< CH2 map to which sensor select */
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TSH register *******************/
+#define RTC_TSH_APM ((uint32_t)0x00400000)
+#define RTC_TSH_HOT ((uint32_t)0x00300000)
+#define RTC_TSH_HOT_0 ((uint32_t)0x00100000)
+#define RTC_TSH_HOT_1 ((uint32_t)0x00200000)
+#define RTC_TSH_HOU ((uint32_t)0x000F0000)
+#define RTC_TSH_HOU_0 ((uint32_t)0x00010000)
+#define RTC_TSH_HOU_1 ((uint32_t)0x00020000)
+#define RTC_TSH_HOU_2 ((uint32_t)0x00040000)
+#define RTC_TSH_HOU_3 ((uint32_t)0x00080000)
+#define RTC_TSH_MIT ((uint32_t)0x00007000)
+#define RTC_TSH_MIT_0 ((uint32_t)0x00001000)
+#define RTC_TSH_MIT_1 ((uint32_t)0x00002000)
+#define RTC_TSH_MIT_2 ((uint32_t)0x00004000)
+#define RTC_TSH_MIU ((uint32_t)0x00000F00)
+#define RTC_TSH_MIU_0 ((uint32_t)0x00000100)
+#define RTC_TSH_MIU_1 ((uint32_t)0x00000200)
+#define RTC_TSH_MIU_2 ((uint32_t)0x00000400)
+#define RTC_TSH_MIU_3 ((uint32_t)0x00000800)
+#define RTC_TSH_SCT ((uint32_t)0x00000070)
+#define RTC_TSH_SCT_0 ((uint32_t)0x00000010)
+#define RTC_TSH_SCT_1 ((uint32_t)0x00000020)
+#define RTC_TSH_SCT_2 ((uint32_t)0x00000040)
+#define RTC_TSH_SCU ((uint32_t)0x0000000F)
+#define RTC_TSH_SCU_0 ((uint32_t)0x00000001)
+#define RTC_TSH_SCU_1 ((uint32_t)0x00000002)
+#define RTC_TSH_SCU_2 ((uint32_t)0x00000004)
+#define RTC_TSH_SCU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_DATE register *******************/
+#define RTC_DATE_YRT ((uint32_t)0x00F00000)
+#define RTC_DATE_YRT_0 ((uint32_t)0x00100000)
+#define RTC_DATE_YRT_1 ((uint32_t)0x00200000)
+#define RTC_DATE_YRT_2 ((uint32_t)0x00400000)
+#define RTC_DATE_YRT_3 ((uint32_t)0x00800000)
+#define RTC_DATE_YRU ((uint32_t)0x000F0000)
+#define RTC_DATE_YRU_0 ((uint32_t)0x00010000)
+#define RTC_DATE_YRU_1 ((uint32_t)0x00020000)
+#define RTC_DATE_YRU_2 ((uint32_t)0x00040000)
+#define RTC_DATE_YRU_3 ((uint32_t)0x00080000)
+#define RTC_DATE_WDU ((uint32_t)0x0000E000)
+#define RTC_DATE_WDU_0 ((uint32_t)0x00002000)
+#define RTC_DATE_WDU_1 ((uint32_t)0x00004000)
+#define RTC_DATE_WDU_2 ((uint32_t)0x00008000)
+#define RTC_DATE_MOT ((uint32_t)0x00001000)
+#define RTC_DATE_MOU ((uint32_t)0x00000F00)
+#define RTC_DATE_MOU_0 ((uint32_t)0x00000100)
+#define RTC_DATE_MOU_1 ((uint32_t)0x00000200)
+#define RTC_DATE_MOU_2 ((uint32_t)0x00000400)
+#define RTC_DATE_MOU_3 ((uint32_t)0x00000800)
+#define RTC_DATE_DAT ((uint32_t)0x00000030)
+#define RTC_DATE_DAT_0 ((uint32_t)0x00000010)
+#define RTC_DATE_DAT_1 ((uint32_t)0x00000020)
+#define RTC_DATE_DAU ((uint32_t)0x0000000F)
+#define RTC_DATE_DAU_0 ((uint32_t)0x00000001)
+#define RTC_DATE_DAU_1 ((uint32_t)0x00000002)
+#define RTC_DATE_DAU_2 ((uint32_t)0x00000004)
+#define RTC_DATE_DAU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_CTRL register *******************/
+#define RTC_CTRL_COEN ((uint32_t)0x00800000)
+#define RTC_CTRL_OUTSEL ((uint32_t)0x00600000)
+#define RTC_CTRL_OUTSEL_0 ((uint32_t)0x00200000)
+#define RTC_CTRL_OUTSEL_1 ((uint32_t)0x00400000)
+#define RTC_CTRL_OPOL ((uint32_t)0x00100000)
+#define RTC_CTRL_CALOSEL ((uint32_t)0x00080000)
+#define RTC_CTRL_BAKP ((uint32_t)0x00040000)
+#define RTC_CTRL_SU1H ((uint32_t)0x00020000)
+#define RTC_CTRL_AD1H ((uint32_t)0x00010000)
+#define RTC_CTRL_TSIEN ((uint32_t)0x00008000)
+#define RTC_CTRL_WTIEN ((uint32_t)0x00004000)
+#define RTC_CTRL_ALBIEN ((uint32_t)0x00002000)
+#define RTC_CTRL_ALAIEN ((uint32_t)0x00001000)
+#define RTC_CTRL_TSEN ((uint32_t)0x00000800)
+#define RTC_CTRL_WTEN ((uint32_t)0x00000400)
+#define RTC_CTRL_ALBEN ((uint32_t)0x00000200)
+#define RTC_CTRL_ALAEN ((uint32_t)0x00000100)
+
+#define RTC_CTRL_HFMT ((uint32_t)0x00000040)
+#define RTC_CTRL_BYPS ((uint32_t)0x00000020)
+#define RTC_CTRL_REFCLKEN ((uint32_t)0x00000010)
+#define RTC_CTRL_TEDGE ((uint32_t)0x00000008)
+#define RTC_CTRL_WKUPSEL ((uint32_t)0x00000007)
+#define RTC_CTRL_WKUPSEL_0 ((uint32_t)0x00000001)
+#define RTC_CTRL_WKUPSEL_1 ((uint32_t)0x00000002)
+#define RTC_CTRL_WKUPSEL_2 ((uint32_t)0x00000004)
+
+/******************** Bits definition for RTC_INITSTS register ******************/
+#define RTC_INITSTS_RECPF ((uint32_t)0x00010000)
+#define RTC_INITSTS_TAM3F ((uint32_t)0x00008000)
+#define RTC_INITSTS_TAM2F ((uint32_t)0x00004000)
+#define RTC_INITSTS_TAM1F ((uint32_t)0x00002000)
+#define RTC_INITSTS_TISOVF ((uint32_t)0x00001000)
+#define RTC_INITSTS_TISF ((uint32_t)0x00000800)
+#define RTC_INITSTS_WTF ((uint32_t)0x00000400)
+#define RTC_INITSTS_ALBF ((uint32_t)0x00000200)
+#define RTC_INITSTS_ALAF ((uint32_t)0x00000100)
+#define RTC_INITSTS_INITM ((uint32_t)0x00000080)
+#define RTC_INITSTS_INITF ((uint32_t)0x00000040)
+#define RTC_INITSTS_RSYF ((uint32_t)0x00000020)
+#define RTC_INITSTS_INITSF ((uint32_t)0x00000010)
+#define RTC_INITSTS_SHOPF ((uint32_t)0x00000008)
+#define RTC_INITSTS_WTWF ((uint32_t)0x00000004)
+#define RTC_INITSTS_ALBWF ((uint32_t)0x00000002)
+#define RTC_INITSTS_ALAWF ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_PRE register *****************/
+#define RTC_PRE_DIVA ((uint32_t)0x007F0000)
+#define RTC_PRE_DIVS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_WKUPT register *****************/
+#define RTC_WKUPT_WKUPT ((uint32_t)0x0000FFFF)
+
+
+/******************** Bits definition for RTC_ALARMA register ***************/
+#define RTC_ALARMA_MASK4 ((uint32_t)0x80000000)
+#define RTC_ALARMA_WKDSEL ((uint32_t)0x40000000)
+#define RTC_ALARMA_DTT ((uint32_t)0x30000000)
+#define RTC_ALARMA_DTT_0 ((uint32_t)0x10000000)
+#define RTC_ALARMA_DTT_1 ((uint32_t)0x20000000)
+#define RTC_ALARMA_DTU ((uint32_t)0x0F000000)
+#define RTC_ALARMA_DTU_0 ((uint32_t)0x01000000)
+#define RTC_ALARMA_DTU_1 ((uint32_t)0x02000000)
+#define RTC_ALARMA_DTU_2 ((uint32_t)0x04000000)
+#define RTC_ALARMA_DTU_3 ((uint32_t)0x08000000)
+#define RTC_ALARMA_MASK3 ((uint32_t)0x00800000)
+#define RTC_ALARMA_APM ((uint32_t)0x00400000)
+#define RTC_ALARMA_HOT ((uint32_t)0x00300000)
+#define RTC_ALARMA_HOT_0 ((uint32_t)0x00100000)
+#define RTC_ALARMA_HOT_1 ((uint32_t)0x00200000)
+#define RTC_ALARMA_HOU ((uint32_t)0x000F0000)
+#define RTC_ALARMA_HOU_0 ((uint32_t)0x00010000)
+#define RTC_ALARMA_HOU_1 ((uint32_t)0x00020000)
+#define RTC_ALARMA_HOU_2 ((uint32_t)0x00040000)
+#define RTC_ALARMA_HOU_3 ((uint32_t)0x00080000)
+#define RTC_ALARMA_MASK2 ((uint32_t)0x00008000)
+#define RTC_ALARMA_MIT ((uint32_t)0x00007000)
+#define RTC_ALARMA_MIT_0 ((uint32_t)0x00001000)
+#define RTC_ALARMA_MIT_1 ((uint32_t)0x00002000)
+#define RTC_ALARMA_MIT_2 ((uint32_t)0x00004000)
+#define RTC_ALARMA_MIU ((uint32_t)0x00000F00)
+#define RTC_ALARMA_MIU_0 ((uint32_t)0x00000100)
+#define RTC_ALARMA_MIU_1 ((uint32_t)0x00000200)
+#define RTC_ALARMA_MIU_2 ((uint32_t)0x00000400)
+#define RTC_ALARMA_MIU_3 ((uint32_t)0x00000800)
+#define RTC_ALARMA_MASK1 ((uint32_t)0x00000080)
+#define RTC_ALARMA_SET ((uint32_t)0x00000070)
+#define RTC_ALARMA_SET_0 ((uint32_t)0x00000010)
+#define RTC_ALARMA_SET_1 ((uint32_t)0x00000020)
+#define RTC_ALARMA_SET_2 ((uint32_t)0x00000040)
+#define RTC_ALARMA_SEU ((uint32_t)0x0000000F)
+#define RTC_ALARMA_SEU_0 ((uint32_t)0x00000001)
+#define RTC_ALARMA_SEU_1 ((uint32_t)0x00000002)
+#define RTC_ALARMA_SEU_2 ((uint32_t)0x00000004)
+#define RTC_ALARMA_SEU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_ALARMB register ***************/
+#define RTC_ALARMB_MASK4 ((uint32_t)0x80000000)
+#define RTC_ALARMB_WKDSEL ((uint32_t)0x40000000)
+#define RTC_ALARMB_DTT ((uint32_t)0x30000000)
+#define RTC_ALARMB_DTT_0 ((uint32_t)0x10000000)
+#define RTC_ALARMB_DTT_1 ((uint32_t)0x20000000)
+#define RTC_ALARMB_DTU ((uint32_t)0x0F000000)
+#define RTC_ALARMB_DTU_0 ((uint32_t)0x01000000)
+#define RTC_ALARMB_DTU_1 ((uint32_t)0x02000000)
+#define RTC_ALARMB_DTU_2 ((uint32_t)0x04000000)
+#define RTC_ALARMB_DTU_3 ((uint32_t)0x08000000)
+#define RTC_ALARMB_MASK3 ((uint32_t)0x00800000)
+#define RTC_ALARMB_APM ((uint32_t)0x00400000)
+#define RTC_ALARMB_HOT ((uint32_t)0x00300000)
+#define RTC_ALARMB_HOT_0 ((uint32_t)0x00100000)
+#define RTC_ALARMB_HOT_1 ((uint32_t)0x00200000)
+#define RTC_ALARMB_HOU ((uint32_t)0x000F0000)
+#define RTC_ALARMB_HOU_0 ((uint32_t)0x00010000)
+#define RTC_ALARMB_HOU_1 ((uint32_t)0x00020000)
+#define RTC_ALARMB_HOU_2 ((uint32_t)0x00040000)
+#define RTC_ALARMB_HOU_3 ((uint32_t)0x00080000)
+#define RTC_ALARMB_MASK2 ((uint32_t)0x00008000)
+#define RTC_ALARMB_MIT ((uint32_t)0x00007000)
+#define RTC_ALARMB_MIT_0 ((uint32_t)0x00001000)
+#define RTC_ALARMB_MIT_1 ((uint32_t)0x00002000)
+#define RTC_ALARMB_MIT_2 ((uint32_t)0x00004000)
+#define RTC_ALARMB_MIU ((uint32_t)0x00000F00)
+#define RTC_ALARMB_MIU_0 ((uint32_t)0x00000100)
+#define RTC_ALARMB_MIU_1 ((uint32_t)0x00000200)
+#define RTC_ALARMB_MIU_2 ((uint32_t)0x00000400)
+#define RTC_ALARMB_MIU_3 ((uint32_t)0x00000800)
+#define RTC_ALARMB_MASK1 ((uint32_t)0x00000080)
+#define RTC_ALARMB_SET ((uint32_t)0x00000070)
+#define RTC_ALARMB_SET_0 ((uint32_t)0x00000010)
+#define RTC_ALARMB_SET_1 ((uint32_t)0x00000020)
+#define RTC_ALARMB_SET_2 ((uint32_t)0x00000040)
+#define RTC_ALARMB_SEU ((uint32_t)0x0000000F)
+#define RTC_ALARMB_SEU_0 ((uint32_t)0x00000001)
+#define RTC_ALARMB_SEU_1 ((uint32_t)0x00000002)
+#define RTC_ALARMB_SEU_2 ((uint32_t)0x00000004)
+#define RTC_ALARMB_SEU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_WRP register ******************/
+#define RTC_WRP_PKEY ((uint32_t)0x000000FF)
+
+/******************** Bits definition for RTC_SUBS register ******************/
+#define RTC_SUBS_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_SCTRL register ***************/
+#define RTC_SCTRL_SUBF ((uint32_t)0x00007FFF)
+#define RTC_SCTRL_AD1S ((uint32_t)0x80000000)
+
+/******************** Bits definition for RTC_TST register *****************/
+#define RTC_TST_APM ((uint32_t)0x00400000)
+#define RTC_TST_HOT ((uint32_t)0x00300000)
+#define RTC_TST_HOT_0 ((uint32_t)0x00100000)
+#define RTC_TST_HOT_1 ((uint32_t)0x00200000)
+#define RTC_TST_HOU ((uint32_t)0x000F0000)
+#define RTC_TST_HOU_0 ((uint32_t)0x00010000)
+#define RTC_TST_HOU_1 ((uint32_t)0x00020000)
+#define RTC_TST_HOU_2 ((uint32_t)0x00040000)
+#define RTC_TST_HOU_3 ((uint32_t)0x00080000)
+#define RTC_TST_MIT ((uint32_t)0x00007000)
+#define RTC_TST_MIT_0 ((uint32_t)0x00001000)
+#define RTC_TST_MIT_1 ((uint32_t)0x00002000)
+#define RTC_TST_MIT_2 ((uint32_t)0x00004000)
+#define RTC_TST_MIU ((uint32_t)0x00000F00)
+#define RTC_TST_MIU_0 ((uint32_t)0x00000100)
+#define RTC_TST_MIU_1 ((uint32_t)0x00000200)
+#define RTC_TST_MIU_2 ((uint32_t)0x00000400)
+#define RTC_TST_MIU_3 ((uint32_t)0x00000800)
+#define RTC_TST_SET ((uint32_t)0x00000070)
+#define RTC_TST_SET_0 ((uint32_t)0x00000010)
+#define RTC_TST_SET_1 ((uint32_t)0x00000020)
+#define RTC_TST_SET_2 ((uint32_t)0x00000040)
+#define RTC_TST_SEU ((uint32_t)0x0000000F)
+#define RTC_TST_SEU_0 ((uint32_t)0x00000001)
+#define RTC_TST_SEU_1 ((uint32_t)0x00000002)
+#define RTC_TST_SEU_2 ((uint32_t)0x00000004)
+#define RTC_TST_SEU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSD register *****************/
+#define RTC_TSD_YRT ((uint32_t)0x00F00000)
+#define RTC_TSD_YRT_0 ((uint32_t)0x00100000)
+#define RTC_TSD_YRT_1 ((uint32_t)0x00200000)
+#define RTC_TSD_YRT_2 ((uint32_t)0x00400000)
+#define RTC_TSD_YRT_3 ((uint32_t)0x00800000)
+#define RTC_TSD_YRU ((uint32_t)0x000F0000)
+#define RTC_TSD_YRU_0 ((uint32_t)0x00010000)
+#define RTC_TSD_YRU_1 ((uint32_t)0x00020000)
+#define RTC_TSD_YRU_2 ((uint32_t)0x00040000)
+#define RTC_TSD_YRU_3 ((uint32_t)0x00080000)
+
+#define RTC_TSD_WDU ((uint32_t)0x0000E000)
+#define RTC_TSD_WDU_0 ((uint32_t)0x00002000)
+#define RTC_TSD_WDU_1 ((uint32_t)0x00004000)
+#define RTC_TSD_WDU_2 ((uint32_t)0x00008000)
+#define RTC_TSD_MOT ((uint32_t)0x00001000)
+#define RTC_TSD_MOU ((uint32_t)0x00000F00)
+#define RTC_TSD_MOU_0 ((uint32_t)0x00000100)
+#define RTC_TSD_MOU_1 ((uint32_t)0x00000200)
+#define RTC_TSD_MOU_2 ((uint32_t)0x00000400)
+#define RTC_TSD_MOU_3 ((uint32_t)0x00000800)
+#define RTC_TSD_DAT ((uint32_t)0x00000030)
+#define RTC_TSD_DAT_0 ((uint32_t)0x00000010)
+#define RTC_TSD_DAT_1 ((uint32_t)0x00000020)
+#define RTC_TSD_DAU ((uint32_t)0x0000000F)
+#define RTC_TSD_DAU_0 ((uint32_t)0x00000001)
+#define RTC_TSD_DAU_1 ((uint32_t)0x00000002)
+#define RTC_TSD_DAU_2 ((uint32_t)0x00000004)
+#define RTC_TSD_DAU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSSS register ****************/
+#define RTC_TSSS_SSE ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CALIB register *****************/
+#define RTC_CALIB_CP ((uint32_t)0x00008000)
+#define RTC_CALIB_CW8 ((uint32_t)0x00004000)
+#define RTC_CALIB_CW16 ((uint32_t)0x00002000)
+#define RTC_CALIB_CM ((uint32_t)0x000001FF)
+#define RTC_CALIB_CM_0 ((uint32_t)0x00000001)
+#define RTC_CALIB_CM_1 ((uint32_t)0x00000002)
+#define RTC_CALIB_CM_2 ((uint32_t)0x00000004)
+#define RTC_CALIB_CM_3 ((uint32_t)0x00000008)
+#define RTC_CALIB_CM_4 ((uint32_t)0x00000010)
+#define RTC_CALIB_CM_5 ((uint32_t)0x00000020)
+#define RTC_CALIB_CM_6 ((uint32_t)0x00000040)
+#define RTC_CALIB_CM_7 ((uint32_t)0x00000080)
+#define RTC_CALIB_CM_8 ((uint32_t)0x00000100)
+
+/******************** Bits definition for RTC_TMPCFG register ****************/
+
+#define RTC_TMPCFG_TP3MF ((uint32_t)0x01000000)
+#define RTC_TMPCFG_TP3NOE ((uint32_t)0x00800000)
+#define RTC_TMPCFG_TP3INTEN ((uint32_t)0x00400000)
+#define RTC_TMPCFG_TP2MF ((uint32_t)0x00200000)
+#define RTC_TMPCFG_TP2NOE ((uint32_t)0x00100000)
+#define RTC_TMPCFG_TP2INTEN ((uint32_t)0x00080000)
+#define RTC_TMPCFG_TP1MF ((uint32_t)0x00040000)
+#define RTC_TMPCFG_TP1NOE ((uint32_t)0x00020000)
+#define RTC_TMPCFG_TP1INTEN ((uint32_t)0x00010000)
+#define RTC_TMPCFG_TPPUDIS ((uint32_t)0x00008000)
+#define RTC_TMPCFG_TPPRCH ((uint32_t)0x00006000)
+#define RTC_TMPCFG_TPPRCH_0 ((uint32_t)0x00002000)
+#define RTC_TMPCFG_TPPRCH_1 ((uint32_t)0x00004000)
+#define RTC_TMPCFG_TPFLT ((uint32_t)0x00001800)
+#define RTC_TMPCFG_TPFLT_0 ((uint32_t)0x00000800)
+#define RTC_TMPCFG_TPFLT_1 ((uint32_t)0x00001000)
+#define RTC_TMPCFG_TPFREQ ((uint32_t)0x00000700)
+#define RTC_TMPCFG_TPFREQ_0 ((uint32_t)0x00000100)
+#define RTC_TMPCFG_TPFREQ_1 ((uint32_t)0x00000200)
+#define RTC_TMPCFG_TPFREQ_2 ((uint32_t)0x00000400)
+#define RTC_TMPCFG_TPTS ((uint32_t)0x00000080)
+#define RTC_TMPCFG_TP3TRG ((uint32_t)0x00000040)
+#define RTC_TMPCFG_TP3EN ((uint32_t)0x00000020)
+#define RTC_TMPCFG_TP2TRG ((uint32_t)0x00000010)
+#define RTC_TMPCFG_TP2EN ((uint32_t)0x00000008)
+#define RTC_TMPCFG_TPINTEN ((uint32_t)0x00000004)
+#define RTC_TMPCFG_TP1TRG ((uint32_t)0x00000002)
+#define RTC_TMPCFG_TP1EN ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_ALRMASS register *************/
+#define RTC_ALRMASS_MASKSSB ((uint32_t)0x0F000000)
+#define RTC_ALRMASS_MASKSSB_0 ((uint32_t)0x01000000)
+#define RTC_ALRMASS_MASKSSB_1 ((uint32_t)0x02000000)
+#define RTC_ALRMASS_MASKSSB_2 ((uint32_t)0x04000000)
+#define RTC_ALRMASS_MASKSSB_3 ((uint32_t)0x08000000)
+#define RTC_ALRMASS_SSV ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_ALRMBSS register *************/
+#define RTC_ALRMBSS_MASKSSB ((uint32_t)0x0F000000)
+#define RTC_ALRMBSS_MASKSSB_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBSS_MASKSSB_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBSS_MASKSSB_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBSS_MASKSSB_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBSS_SSV ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_OPT register *******************/
+#define RTC_OPT_TYPE ((uint32_t)0x00000001)
+/******************** Bits definition for RTC_TSCWKUPCTRL register *******************/
+#define RTC_TSCWKUPCTRL_WKUPOFF ((uint32_t)0x00000008)
+#define RTC_TSCWKUPCTRL_WKUPCNF ((uint32_t)0x00000004)
+#define RTC_TSCWKUPCTRL_WKUPEN ((uint32_t)0x00000001)
+/******************** Bits definition for RTC_TSCWKUPCNT register *******************/
+#define RTC_TSCWKUPCNT_CNT ((uint32_t)0x00003FFF)
+/******************** Bits definition for RTC_BKP1 register ****************/
+#define RTC_BKP1 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP2 register ****************/
+#define RTC_BKP2 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP3 register ****************/
+#define RTC_BKP3 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP4 register ****************/
+#define RTC_BKP4 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP5 register ****************/
+#define RTC_BKP5 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP6 register ****************/
+#define RTC_BKP6 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP7 register ****************/
+#define RTC_BKP7 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP8 register ****************/
+#define RTC_BKP8 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP9 register ****************/
+#define RTC_BKP9 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP10 register ****************/
+#define RTC_BKP10 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP11 register ***************/
+#define RTC_BKP11 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP12register ***************/
+#define RTC_BKP12 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP13 register ***************/
+#define RTC_BKP13 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP14 register ***************/
+#define RTC_BKP14 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP15 register ***************/
+#define RTC_BKP15 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP16 register ***************/
+#define RTC_BKP16 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP17register ***************/
+#define RTC_BKP17 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP18 register ***************/
+#define RTC_BKP18 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP19 register ***************/
+#define RTC_BKP19 ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP20 register ***************/
+#define RTC_BKP20 ((uint32_t)0xFFFFFFFF)
+
+
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for IWDG_KEY register ********************/
+#define IWDG_KEY_KEYV ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PREDIV register ********************/
+#define IWDG_PREDIV_PD ((uint8_t)0x07) /*!< PD[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */
+#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */
+#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */
+
+/******************* Bit definition for IWDG_RELV register *******************/
+#define IWDG_RELV_REL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_STS register ********************/
+#define IWDG_STS_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */
+#define IWDG_STS_CRVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CTRL register ********************/
+#define WWDG_CTRL_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CTRL_T0 ((uint8_t)0x01) /*!< Bit 0 */
+#define WWDG_CTRL_T1 ((uint8_t)0x02) /*!< Bit 1 */
+#define WWDG_CTRL_T2 ((uint8_t)0x04) /*!< Bit 2 */
+#define WWDG_CTRL_T3 ((uint8_t)0x08) /*!< Bit 3 */
+#define WWDG_CTRL_T4 ((uint8_t)0x10) /*!< Bit 4 */
+#define WWDG_CTRL_T5 ((uint8_t)0x20) /*!< Bit 5 */
+#define WWDG_CTRL_T6 ((uint8_t)0x40) /*!< Bit 6 */
+
+#define WWDG_CTRL_ACTB ((uint8_t)0x80) /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFG register *******************/
+#define WWDG_CFG_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFG_W0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define WWDG_CFG_W1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define WWDG_CFG_W2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define WWDG_CFG_W3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define WWDG_CFG_W4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define WWDG_CFG_W5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define WWDG_CFG_W6 ((uint16_t)0x0040) /*!< Bit 6 */
+
+#define WWDG_CFG_TIMERB ((uint16_t)0x0180) /*!< TIMERB[1:0] bits (Timer Base) */
+#define WWDG_CFG_TIMERB0 ((uint16_t)0x0080) /*!< Bit 0 */
+#define WWDG_CFG_TIMERB1 ((uint16_t)0x0100) /*!< Bit 1 */
+
+#define WWDG_CFG_EWINT ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_STS register ********************/
+#define WWDG_STS_EWINTF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Flexible Static Memory Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for XFMC_BCR1 register *******************/
+#define XFMC_BK1CSCTRL1_MBEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
+#define XFMC_BK1CSCTRL1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
+
+#define XFMC_BK1CSCTRL1_MTYPE ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
+#define XFMC_BK1CSCTRL1_MTYPE_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define XFMC_BK1CSCTRL1_MTYPE_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define XFMC_BK1CSCTRL1_MDBW ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
+#define XFMC_BK1CSCTRL1_MDBW_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK1CSCTRL1_MDBW_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define XFMC_BK1CSCTRL1_ACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
+#define XFMC_BK1CSCTRL1_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
+#define XFMC_BK1CSCTRL1_WAITDIR ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
+#define XFMC_BK1CSCTRL1_WRAPEN ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
+#define XFMC_BK1CSCTRL1_WCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
+#define XFMC_BK1CSCTRL1_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
+#define XFMC_BK1CSCTRL1_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
+#define XFMC_BK1CSCTRL1_EXTEN ((uint32_t)0x00004000) /*!< Extended mode enable */
+#define XFMC_BK1CSCTRL1_WAITASYNC ((uint32_t)0x00008000) /*!< Asynchronous wait */
+#define XFMC_BK1CSCTRL1_BURSTWREN ((uint32_t)0x00080000) /*!< Write burst enable */
+
+/****************** Bit definition for XFMC_BCR2 register *******************/
+#define XFMC_BK1CSCTRL2_MBEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
+#define XFMC_BK1CSCTRL2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
+
+#define XFMC_BK1CSCTRL2_MTYPE ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
+#define XFMC_BK1CSCTRL2_MTYPE_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define XFMC_BK1CSCTRL2_MTYPE_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define XFMC_BK1CSCTRL2_MDBW ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
+#define XFMC_BK1CSCTRL2_MDBW_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK1CSCTRL2_MDBW_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define XFMC_BK1CSCTRL2_ACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
+#define XFMC_BK1CSCTRL2_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
+#define XFMC_BK1CSCTRL2_WAITDIR ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
+#define XFMC_BK1CSCTRL2_WRAPEN ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
+#define XFMC_BK1CSCTRL2_WCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
+#define XFMC_BK1CSCTRL2_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
+#define XFMC_BK1CSCTRL2_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
+#define XFMC_BK1CSCTRL2_EXTEN ((uint32_t)0x00004000) /*!< Extended mode enable */
+#define XFMC_BK1CSCTRL2_WAITASYNC ((uint32_t)0x00008000) /*!< Asynchronous wait */
+#define XFMC_BK1CSCTRL2_BURSTWREN ((uint32_t)0x00080000) /*!< Write burst enable */
+
+/****************** Bit definition for XFMC_BTR1 register ******************/
+#define XFMC_BK1TM1_ADDBLD ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define XFMC_BK1TM1_ADDBLD_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_BK1TM1_ADDBLD_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_BK1TM1_ADDBLD_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_BK1TM1_ADDBLD_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define XFMC_BK1TM1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define XFMC_BK1TM1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK1TM1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define XFMC_BK1TM1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define XFMC_BK1TM1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define XFMC_BK1TM1_DATABLD ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define XFMC_BK1TM1_DATABLD_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_BK1TM1_DATABLD_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_BK1TM1_DATABLD_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_BK1TM1_DATABLD_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define XFMC_BK1TM1_BUSRECOVERY ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define XFMC_BK1TM1_BUSRECOVERY_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define XFMC_BK1TM1_BUSRECOVERY_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define XFMC_BK1TM1_BUSRECOVERY_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define XFMC_BK1TM1_BUSRECOVERY_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+
+#define XFMC_BK1TM1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define XFMC_BK1TM1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define XFMC_BK1TM1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define XFMC_BK1TM1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define XFMC_BK1TM1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define XFMC_BK1TM1_DATAHLD ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define XFMC_BK1TM1_DATAHLD_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_BK1TM1_DATAHLD_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_BK1TM1_DATAHLD_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_BK1TM1_DATAHLD_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define XFMC_BK1TM1_ACCMODE ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define XFMC_BK1TM1_ACCMODE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define XFMC_BK1TM1_ACCMODE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for XFMC_BTR2 register *******************/
+#define XFMC_BK1TM2_ADDBLD ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define XFMC_BK1TM2_ADDBLD_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_BK1TM2_ADDBLD_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_BK1TM2_ADDBLD_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_BK1TM2_ADDBLD_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define XFMC_BK1TM2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define XFMC_BK1TM2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK1TM2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define XFMC_BK1TM2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define XFMC_BK1TM2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define XFMC_BK1TM2_DATABLD ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define XFMC_BK1TM2_DATABLD_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_BK1TM2_DATABLD_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_BK1TM2_DATABLD_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_BK1TM2_DATABLD_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define XFMC_BK1TM2_BUSRECOVERY ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define XFMC_BK1TM2_BUSRECOVERY_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define XFMC_BK1TM2_BUSRECOVERY_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define XFMC_BK1TM2_BUSRECOVERY_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define XFMC_BK1TM2_BUSRECOVERY_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+
+#define XFMC_BK1TM2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define XFMC_BK1TM2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define XFMC_BK1TM2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define XFMC_BK1TM2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define XFMC_BK1TM2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define XFMC_BK1TM2_DATAHLD ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define XFMC_BK1TM2_DATAHLD_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_BK1TM2_DATAHLD_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_BK1TM2_DATAHLD_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_BK1TM2_DATAHLD_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define XFMC_BK1TM2_ACCMODE ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define XFMC_BK1TM2_ACCMODE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define XFMC_BK1TM2_ACCMODE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for XFMC_BWTR1 register ******************/
+#define XFMC_BK1WTM1_ADDBLD ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define XFMC_BK1WTM1_ADDBLD_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_BK1WTM1_ADDBLD_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_BK1WTM1_ADDBLD_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_BK1WTM1_ADDBLD_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define XFMC_BK1WTM1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define XFMC_BK1WTM1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK1WTM1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define XFMC_BK1WTM1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define XFMC_BK1WTM1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define XFMC_BK1WTM1_DATABLD ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define XFMC_BK1WTM1_DATABLD_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_BK1WTM1_DATABLD_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_BK1WTM1_DATABLD_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_BK1WTM1_DATABLD_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define XFMC_BK1WTM1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define XFMC_BK1WTM1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define XFMC_BK1WTM1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define XFMC_BK1WTM1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define XFMC_BK1WTM1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define XFMC_BK1WTM1_DATAHLD ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define XFMC_BK1WTM1_DATAHLD_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_BK1WTM1_DATAHLD_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_BK1WTM1_DATAHLD_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_BK1WTM1_DATAHLD_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define XFMC_BK1WTM1_ACCMODE ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define XFMC_BK1WTM1_ACCMODE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define XFMC_BK1WTM1_ACCMODE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for XFMC_BWTR2 register ******************/
+#define XFMC_BK1WTM2_ADDBLD ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define XFMC_BK1WTM2_ADDBLD_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_BK1WTM2_ADDBLD_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_BK1WTM2_ADDBLD_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_BK1WTM2_ADDBLD_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define XFMC_BK1WTM2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define XFMC_BK1WTM2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK1WTM2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define XFMC_BK1WTM2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define XFMC_BK1WTM2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define XFMC_BK1WTM2_DATABLD ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define XFMC_BK1WTM2_DATABLD_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_BK1WTM2_DATABLD_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_BK1WTM2_DATABLD_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_BK1WTM2_DATABLD_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define XFMC_BK1WTM2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define XFMC_BK1WTM2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define XFMC_BK1WTM2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1*/
+#define XFMC_BK1WTM2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define XFMC_BK1WTM2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define XFMC_BK1WTM2_DATAHLD ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define XFMC_BK1WTM2_DATAHLD_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_BK1WTM2_DATAHLD_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_BK1WTM2_DATAHLD_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_BK1WTM2_DATAHLD_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define XFMC_BK1WTM2_ACCMODE ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define XFMC_BK1WTM2_ACCMODE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define XFMC_BK1WTM2_ACCMODE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for XFMC_PCR2 register *******************/
+#define XFMC_BK2CTRL_WAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */
+#define XFMC_BK2CTRL_BANKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */
+#define XFMC_BK2CTRL_MEMTYPE ((uint32_t)0x00000008) /*!< Memory type */
+
+#define XFMC_BK2CTRL_BUSWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define XFMC_BK2CTRL_BUSWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK2CTRL_BUSWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define XFMC_BK2CTRL_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */
+
+#define XFMC_BK2CTRL_CRDLY ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define XFMC_BK2CTRL_CRDLY_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define XFMC_BK2CTRL_CRDLY_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define XFMC_BK2CTRL_CRDLY_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+#define XFMC_BK2CTRL_CRDLY_3 ((uint32_t)0x00001000) /*!< Bit 3 */
+
+#define XFMC_BK2CTRL_ARDLY ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */
+#define XFMC_BK2CTRL_ARDLY_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define XFMC_BK2CTRL_ARDLY_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define XFMC_BK2CTRL_ARDLY_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+#define XFMC_BK2CTRL_ARDLY_3 ((uint32_t)0x00010000) /*!< Bit 3 */
+
+#define XFMC_BK2CTRL_ECCPGS ((uint32_t)0x000E0000) /*!< ECCPS[1:0] bits (ECC page size) */
+#define XFMC_BK2CTRL_ECCPGS_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define XFMC_BK2CTRL_ECCPGS_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define XFMC_BK2CTRL_ECCPGS_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+
+/****************** Bit definition for XFMC_PCR3 register *******************/
+#define XFMC_BK3CTRL_WAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */
+#define XFMC_BK3CTRL_BANKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */
+#define XFMC_BK3CTRL_MEMTYPE ((uint32_t)0x00000008) /*!< Memory type */
+
+#define XFMC_BK3CTRL_BUSWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define XFMC_BK3CTRL_BUSWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK3CTRL_BUSWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define XFMC_BK3CTRL_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */
+
+#define XFMC_BK3CTRL_CRDLY ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define XFMC_BK3CTRL_CRDLY_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define XFMC_BK3CTRL_CRDLY_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define XFMC_BK3CTRL_CRDLY_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+#define XFMC_BK3CTRL_CRDLY_3 ((uint32_t)0x00001000) /*!< Bit 3 */
+
+#define XFMC_BK3CTRL_ARDLY ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */
+#define XFMC_BK3CTRL_ARDLY_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define XFMC_BK3CTRL_ARDLY_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define XFMC_BK3CTRL_ARDLY_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+#define XFMC_BK3CTRL_ARDLY_3 ((uint32_t)0x00010000) /*!< Bit 3 */
+
+#define XFMC_BK3CTRL_ECCPGS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */
+#define XFMC_BK3CTRL_ECCPGS_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define XFMC_BK3CTRL_ECCPGS_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define XFMC_BK3CTRL_ECCPGS_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+
+/******************* Bit definition for XFMC_SR2 register *******************/
+//#define XFMC_SR2_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */
+//#define XFMC_SR2_ILS ((uint8_t)0x02) /*!< Interrupt Level status */
+//#define XFMC_SR2_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */
+//#define XFMC_SR2_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable
+// bit */ #define XFMC_SR2_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection
+// Enable bit */ #define XFMC_SR2_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge
+// detection Enable bit */
+#define XFMC_STS2_FIFOEMPT ((uint8_t)0x40) /*!< DATFIFO empty */
+
+/******************* Bit definition for XFMC_SR3 register *******************/
+//#define XFMC_SR3_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */
+//#define XFMC_SR3_ILS ((uint8_t)0x02) /*!< Interrupt Level status */
+//#define XFMC_SR3_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */
+//#define XFMC_SR3_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable
+// bit */ #define XFMC_SR3_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection
+// Enable bit */ #define XFMC_SR3_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge
+// detection Enable bit */
+#define XFMC_STS3_FIFOEMPT ((uint8_t)0x40) /*!< DATFIFO empty */
+
+/****************** Bit definition for XFMC_PMEM2 register ******************/
+#define XFMC_CMEMTM2_SET ((uint32_t)0x000000FF) /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define XFMC_CMEMTM2_SET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_CMEMTM2_SET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_CMEMTM2_SET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_CMEMTM2_SET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define XFMC_CMEMTM2_SET_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define XFMC_CMEMTM2_SET_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define XFMC_CMEMTM2_SET_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define XFMC_CMEMTM2_SET_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define XFMC_CMEMTM2_WAIT ((uint32_t)0x0000FF00) /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define XFMC_CMEMTM2_WAIT_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_CMEMTM2_WAIT_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_CMEMTM2_WAIT_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_CMEMTM2_WAIT_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define XFMC_CMEMTM2_WAIT_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define XFMC_CMEMTM2_WAIT_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define XFMC_CMEMTM2_WAIT_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define XFMC_CMEMTM2_WAIT_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define XFMC_CMEMTM2_HLD ((uint32_t)0x00FF0000) /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define XFMC_CMEMTM2_HLD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define XFMC_CMEMTM2_HLD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define XFMC_CMEMTM2_HLD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define XFMC_CMEMTM2_HLD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define XFMC_CMEMTM2_HLD_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define XFMC_CMEMTM2_HLD_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define XFMC_CMEMTM2_HLD_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define XFMC_CMEMTM2_HLD_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+
+#define XFMC_CMEMTM2_HIZ ((uint32_t)0xFF000000) /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define XFMC_CMEMTM2_HIZ_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_CMEMTM2_HIZ_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_CMEMTM2_HIZ_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_CMEMTM2_HIZ_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define XFMC_CMEMTM2_HIZ_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define XFMC_CMEMTM2_HIZ_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define XFMC_CMEMTM2_HIZ_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define XFMC_CMEMTM2_HIZ_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/****************** Bit definition for XFMC_PMEM3 register ******************/
+#define XFMC_CMEMTM3_SET ((uint32_t)0x000000FF) /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define XFMC_CMEMTM3_SET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_CMEMTM3_SET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_CMEMTM3_SET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_CMEMTM3_SET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define XFMC_CMEMTM3_SET_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define XFMC_CMEMTM3_SET_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define XFMC_CMEMTM3_SET_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define XFMC_CMEMTM3_SET_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define XFMC_CMEMTM3_WAIT ((uint32_t)0x0000FF00) /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define XFMC_CMEMTM3_WAIT_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_CMEMTM3_WAIT_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_CMEMTM3_WAIT_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_CMEMTM3_WAIT_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define XFMC_CMEMTM3_WAIT_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define XFMC_CMEMTM3_WAIT_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define XFMC_CMEMTM3_WAIT_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define XFMC_CMEMTM3_WAIT_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define XFMC_CMEMTM3_HLD ((uint32_t)0x00FF0000) /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define XFMC_CMEMTM3_HLD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define XFMC_CMEMTM3_HLD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define XFMC_CMEMTM3_HLD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define XFMC_CMEMTM3_HLD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define XFMC_CMEMTM3_HLD_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define XFMC_CMEMTM3_HLD_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define XFMC_CMEMTM3_HLD_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define XFMC_CMEMTM3_HLD_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+
+#define XFMC_CMEMTM3_HIZ ((uint32_t)0xFF000000) /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define XFMC_CMEMTM3_HIZ_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_CMEMTM3_HIZ_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_CMEMTM3_HIZ_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_CMEMTM3_HIZ_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define XFMC_CMEMTM3_HIZ_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define XFMC_CMEMTM3_HIZ_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define XFMC_CMEMTM3_HIZ_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define XFMC_CMEMTM3_HIZ_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/****************** Bit definition for XFMC_PATT2 register ******************/
+#define XFMC_ATTMEMTM2_SET ((uint32_t)0x000000FF) /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define XFMC_ATTMEMTM2_SET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_ATTMEMTM2_SET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_ATTMEMTM2_SET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_ATTMEMTM2_SET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define XFMC_ATTMEMTM2_SET_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define XFMC_ATTMEMTM2_SET_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define XFMC_ATTMEMTM2_SET_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define XFMC_ATTMEMTM2_SET_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define XFMC_ATTMEMTM2_WAIT ((uint32_t)0x0000FF00) /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define XFMC_ATTMEMTM2_WAIT_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_ATTMEMTM2_WAIT_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_ATTMEMTM2_WAIT_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_ATTMEMTM2_WAIT_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define XFMC_ATTMEMTM2_WAIT_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define XFMC_ATTMEMTM2_WAIT_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define XFMC_ATTMEMTM2_WAIT_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define XFMC_ATTMEMTM2_WAIT_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define XFMC_ATTMEMTM2_HLD ((uint32_t)0x00FF0000) /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define XFMC_ATTMEMTM2_HLD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define XFMC_ATTMEMTM2_HLD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define XFMC_ATTMEMTM2_HLD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define XFMC_ATTMEMTM2_HLD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define XFMC_ATTMEMTM2_HLD_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define XFMC_ATTMEMTM2_HLD_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define XFMC_ATTMEMTM2_HLD_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define XFMC_ATTMEMTM2_HLD_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+
+#define XFMC_ATTMEMTM2_HIZ ((uint32_t)0xFF000000) /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define XFMC_ATTMEMTM2_HIZ_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_ATTMEMTM2_HIZ_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_ATTMEMTM2_HIZ_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_ATTMEMTM2_HIZ_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define XFMC_ATTMEMTM2_HIZ_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define XFMC_ATTMEMTM2_HIZ_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define XFMC_ATTMEMTM2_HIZ_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define XFMC_ATTMEMTM2_HIZ_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/****************** Bit definition for XFMC_PATT3 register ******************/
+#define XFMC_ATTMEMTM3_SET ((uint32_t)0x000000FF) /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define XFMC_ATTMEMTM3_SET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_ATTMEMTM3_SET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_ATTMEMTM3_SET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_ATTMEMTM3_SET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define XFMC_ATTMEMTM3_SET_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define XFMC_ATTMEMTM3_SET_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define XFMC_ATTMEMTM3_SET_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define XFMC_ATTMEMTM3_SET_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define XFMC_ATTMEMTM3_WAIT ((uint32_t)0x0000FF00) /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define XFMC_ATTMEMTM3_WAIT_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_ATTMEMTM3_WAIT_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_ATTMEMTM3_WAIT_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_ATTMEMTM3_WAIT_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define XFMC_ATTMEMTM3_WAIT_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define XFMC_ATTMEMTM3_WAIT_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define XFMC_ATTMEMTM3_WAIT_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define XFMC_ATTMEMTM3_WAIT_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define XFMC_ATTMEMTM3_HLD ((uint32_t)0x00FF0000) /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define XFMC_ATTMEMTM3_HLD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define XFMC_ATTMEMTM3_HLD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define XFMC_ATTMEMTM3_HLD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define XFMC_ATTMEMTM3_HLD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define XFMC_ATTMEMTM3_HLD_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define XFMC_ATTMEMTM3_HLD_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define XFMC_ATTMEMTM3_HLD_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define XFMC_ATTMEMTM3_HLD_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+
+#define XFMC_ATTMEMTM3_HIZ ((uint32_t)0xFF000000) /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define XFMC_ATTMEMTM3_HIZ_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_ATTMEMTM3_HIZ_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_ATTMEMTM3_HIZ_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_ATTMEMTM3_HIZ_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define XFMC_ATTMEMTM3_HIZ_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define XFMC_ATTMEMTM3_HIZ_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define XFMC_ATTMEMTM3_HIZ_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define XFMC_ATTMEMTM3_HIZ_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/****************** Bit definition for XFMC_ECCR2 register ******************/
+#define XFMC_ECCR2 ((uint32_t)0xFFFFFFFF) /*!< ECC result */
+
+/****************** Bit definition for XFMC_ECCR3 register ******************/
+#define XFMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!< ECC result */
+
+/******************************************************************************/
+/* */
+/* USB Device FS */
+/* */
+/******************************************************************************/
+
+/*!< Endpoint-specific registers */
+/******************* Bit definition for USB_EP0R register *******************/
+#define USB_EP0_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP0_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP0_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP0_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP0_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP0_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP0_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP0_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP0_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP0_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP0_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP0_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP0_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP0_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP0_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP0_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP1R register *******************/
+#define USB_EP1_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP1_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP1_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP1_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP1_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP1_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP1_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP1_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP1_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP1_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP1_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP1_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP1_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP1_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP1_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP1_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP2R register *******************/
+#define USB_EP2_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP2_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP2_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP2_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP2_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP2_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP2_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP2_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP2_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP2_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP2_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP2_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP2_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP2_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP2_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP2_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP3R register *******************/
+#define USB_EP3_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP3_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP3_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP3_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP3_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP3_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP3_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP3_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP3_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP3_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP3_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP3_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP3_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP3_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP3_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP3_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP4R register *******************/
+#define USB_EP4_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP4_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP4_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP4_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP4_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP4_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP4_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP4_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP4_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP4_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP4_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP4_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP4_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP4_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP4_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP4_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP5R register *******************/
+#define USB_EP5_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP5_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP5_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP5_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP5_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP5_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP5_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP5_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP5_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP5_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP5_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP5_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP5_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP5_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP5_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP5_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP6R register *******************/
+#define USB_EP6_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP6_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP6_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP6_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP6_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP6_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP6_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP6_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP6_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP6_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP6_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP6_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP6_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP6_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP6_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP6_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP7R register *******************/
+#define USB_EP7_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP7_STS_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP7_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP7_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP7_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP7_CTRS_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP7_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP7_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP7_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP7_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP7_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP7_STS_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP7_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP7_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP7_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP7_CTRS_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/*!< Common registers */
+/******************* Bit definition for USB_CNTR register *******************/
+#define USB_CTRL_FRST ((uint16_t)0x0001) /*!< Force USB Reset */
+#define USB_CTRL_PD ((uint16_t)0x0002) /*!< Power down */
+#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power mode */
+#define USB_CTRL_FSUSPD ((uint16_t)0x0008) /*!< Force suspend */
+#define USB_CTRL_RESUM ((uint16_t)0x0010) /*!< Resume request */
+#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Interrupt Mask */
+#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Interrupt Mask */
+#define USB_CTRL_RSTM ((uint16_t)0x0400) /*!< RESET Interrupt Mask */
+#define USB_CTRL_SUSPDM ((uint16_t)0x0800) /*!< Suspend mode Interrupt Mask */
+#define USB_CTRL_WKUPM ((uint16_t)0x1000) /*!< Wakeup Interrupt Mask */
+#define USB_CTRL_ERRORM ((uint16_t)0x2000) /*!< Error Interrupt Mask */
+#define USB_CTRL_PMAOM ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun Interrupt Mask */
+#define USB_CTRL_CTRSM ((uint16_t)0x8000) /*!< Correct Transfer Interrupt Mask */
+
+/******************* Bit definition for USB_ISTR register *******************/
+#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< Endpoint Identifier */
+#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< Direction of transaction */
+#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame */
+#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame */
+#define USB_STS_RST ((uint16_t)0x0400) /*!< USB RESET request */
+#define USB_STS_SUSPD ((uint16_t)0x0800) /*!< Suspend mode request */
+#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< Wake up */
+#define USB_STS_ERROR ((uint16_t)0x2000) /*!< Error */
+#define USB_STS_PMAO ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun */
+#define USB_STS_CTRS ((uint16_t)0x8000) /*!< Correct Transfer */
+
+/******************* Bit definition for USB_FNR register ********************/
+#define USB_FN_FNUM ((uint16_t)0x07FF) /*!< Frame Number */
+#define USB_FN_LSTSOF ((uint16_t)0x1800) /*!< Lost SOF */
+#define USB_FNR_LCK ((uint16_t)0x2000) /*!< Locked */
+#define USB_FN_RXDM_STS ((uint16_t)0x4000) /*!< Receive Data - Line Status */
+#define USB_FN_RXDP_STS ((uint16_t)0x8000) /*!< Receive Data + Line Status */
+
+/****************** Bit definition for USB_DADDR register *******************/
+#define USB_ADDR_ADDR ((uint8_t)0x7F) /*!< ADD[6:0] bits (Device Address) */
+#define USB_ADDR_ADDR0 ((uint8_t)0x01) /*!< Bit 0 */
+#define USB_ADDR_ADDR1 ((uint8_t)0x02) /*!< Bit 1 */
+#define USB_ADDR_ADDR2 ((uint8_t)0x04) /*!< Bit 2 */
+#define USB_ADDR_ADDR3 ((uint8_t)0x08) /*!< Bit 3 */
+#define USB_ADDR_ADDR4 ((uint8_t)0x10) /*!< Bit 4 */
+#define USB_ADDR_ADDR5 ((uint8_t)0x20) /*!< Bit 5 */
+#define USB_ADDR_ADDR6 ((uint8_t)0x40) /*!< Bit 6 */
+
+#define USB_ADDR_EFUC ((uint8_t)0x80) /*!< Enable Function */
+
+/****************** Bit definition for USB_BTABLE register ******************/
+#define USB_BUFTAB_BUFTAB ((uint16_t)0xFFF8) /*!< Buffer Table */
+
+/*!< Buffer descriptor table */
+/***************** Bit definition for USB_ADDR0_TX register *****************/
+#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_TX register *****************/
+#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_TX register *****************/
+#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_TX register *****************/
+#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_TX register *****************/
+#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_TX register *****************/
+#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_TX register *****************/
+#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_TX register *****************/
+#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_TX register ****************/
+#define USB_CNT0_TX_CNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */
+
+/***************** Bit definition for USB_COUNT1_TX register ****************/
+#define USB_CNT1_TX_CNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */
+
+/***************** Bit definition for USB_COUNT2_TX register ****************/
+#define USB_CNT2_TX_CNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */
+
+/***************** Bit definition for USB_COUNT3_TX register ****************/
+#define USB_CNT3_TX_CNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */
+
+/***************** Bit definition for USB_COUNT4_TX register ****************/
+#define USB_CNT4_TX_CNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */
+
+/***************** Bit definition for USB_COUNT5_TX register ****************/
+#define USB_CNT5_TX_CNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */
+
+/***************** Bit definition for USB_COUNT6_TX register ****************/
+#define USB_CNT6_TX_CNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */
+
+/***************** Bit definition for USB_COUNT7_TX register ****************/
+#define USB_CNT7_TX_CNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
+#define USB_CNT0_TX_0_CNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
+
+/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
+#define USB_CNT0_TX_1_CNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
+
+/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
+#define USB_CNT1_TX_0_CNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
+
+/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
+#define USB_CNT1_TX_1_CNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
+
+/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
+#define USB_CNT2_TX_0_CNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
+
+/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
+#define USB_CNT2_TX_1_CNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
+
+/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
+#define USB_CNT3_TX_0_CNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */
+
+/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
+#define USB_CNT3_TX_1_CNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */
+
+/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
+#define USB_CNT4_TX_0_CNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
+
+/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
+#define USB_CNT4_TX_1_CNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
+
+/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
+#define USB_CNT5_TX_0_CNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
+
+/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
+#define USB_CNT5_TX_1_CNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
+
+/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
+#define USB_CNT6_TX_0_CNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
+
+/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
+#define USB_CNT6_TX_1_CNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
+
+/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
+#define USB_CNT7_TX_0_CNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
+
+/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
+#define USB_CNT7_TX_1_CNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_ADDR0_RX register *****************/
+#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_RX register *****************/
+#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_RX register *****************/
+#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_RX register *****************/
+#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_RX register *****************/
+#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_RX register *****************/
+#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_RX register *****************/
+#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_RX register *****************/
+#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_RX register ****************/
+#define USB_CNT0_RX_CNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT0_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT0_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT0_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT0_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT0_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT0_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT1_RX register ****************/
+#define USB_CNT1_RX_CNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT1_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT1_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT1_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT1_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT1_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT1_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT2_RX register ****************/
+#define USB_CNT2_RX_CNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT2_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT2_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT2_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT2_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT2_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT2_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT3_RX register ****************/
+#define USB_CNT3_RX_CNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT3_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT3_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT3_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT3_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT3_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT3_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT4_RX register ****************/
+#define USB_CNT4_RX_CNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT4_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT4_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT4_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT4_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT4_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT4_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT5_RX register ****************/
+#define USB_CNT5_RX_CNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT5_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT5_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT5_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT5_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT5_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT5_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT6_RX register ****************/
+#define USB_CNT6_RX_CNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT6_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT6_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT6_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT6_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT6_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT6_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT7_RX register ****************/
+#define USB_CNT7_RX_CNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT7_RX_NUM_BLK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT7_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT7_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT7_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT7_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT7_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
+#define USB_CNT0_RX_0_CNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT0_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT0_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT0_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT0_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT0_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT0_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
+#define USB_CNT0_RX_1_CNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT0_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT0_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define USB_CNT0_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT0_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT0_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT0_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
+#define USB_CNT1_RX_0_CNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT1_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT1_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT1_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT1_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT1_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT1_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
+#define USB_CNT1_RX_1_CNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT1_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT1_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_CNT1_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT1_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT1_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT1_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
+#define USB_CNT2_RX_0_CNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT2_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT2_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT2_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT2_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT2_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT2_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
+#define USB_CNT2_RX_1_CNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT2_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT2_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_CNT2_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT2_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT2_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT2_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
+#define USB_CNT3_RX_0_CNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT3_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT3_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT3_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT3_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT3_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT3_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
+#define USB_CNT3_RX_1_CNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT3_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT3_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_CNT3_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT3_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT3_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT3_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
+#define USB_CNT4_RX_0_CNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT4_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT4_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT4_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT4_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT4_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT4_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
+#define USB_CNT4_RX_1_CNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT4_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT4_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_CNT4_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT4_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT4_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT4_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
+#define USB_CNT5_RX_0_CNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT5_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT5_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT5_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT5_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT5_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT5_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
+#define USB_CNT5_RX_1_CNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT5_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT5_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_CNT5_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT5_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT5_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT5_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
+#define USB_CNT6_RX_0_CNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT6_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT6_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT6_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT6_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT6_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT6_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
+#define USB_CNT6_RX_1_CNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT6_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT6_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_CNT6_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT6_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT6_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT6_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
+#define USB_CNT7_RX_0_CNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT7_RX_0_NUM_BLK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT7_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT7_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT7_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT7_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT7_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
+#define USB_CNT7_RX_1_CNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT7_RX_1_NUM_BLK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT7_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_CNT7_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT7_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT7_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT7_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+
+/*!< CAN control and status registers */
+/******************* Bit definition for CAN_MCTRL register ********************/
+#define CAN_MCTRL_INIRQ ((uint16_t)0x0001) /*!< Initialization Request */
+#define CAN_MCTRL_SLPRQ ((uint16_t)0x0002) /*!< Sleep Mode Request */
+#define CAN_MCTRL_TXFP ((uint16_t)0x0004) /*!< Transmit DATFIFO Priority */
+#define CAN_MCTRL_RFLM ((uint16_t)0x0008) /*!< Receive DATFIFO Locked Mode */
+#define CAN_MCTRL_NART ((uint16_t)0x0010) /*!< No Automatic Retransmission */
+#define CAN_MCTRL_AWKUM ((uint16_t)0x0020) /*!< Automatic Wakeup Mode */
+#define CAN_MCTRL_ABOM ((uint16_t)0x0040) /*!< Automatic Bus-Off Management */
+#define CAN_MCTRL_TTCM ((uint16_t)0x0080) /*!< Time Triggered Communication Mode */
+#define CAN_MCTRL_MRST ((uint16_t)0x8000) /*!< CAN software master reset */
+#define CAN_MCTRL_DBGF ((uint32_t)0x00010000) /*!< CAN Debug freeze */
+
+/******************* Bit definition for CAN_MSTS register ********************/
+#define CAN_MSTS_INIAK ((uint16_t)0x0001) /*!< Initialization Acknowledge */
+#define CAN_MSTS_SLPAK ((uint16_t)0x0002) /*!< Sleep Acknowledge */
+#define CAN_MSTS_ERRINT ((uint16_t)0x0004) /*!< Error Interrupt */
+#define CAN_MSTS_WKUINT ((uint16_t)0x0008) /*!< Wakeup Interrupt */
+#define CAN_MSTS_SLAKINT ((uint16_t)0x0010) /*!< Sleep Acknowledge Interrupt */
+#define CAN_MSTS_TXMD ((uint16_t)0x0100) /*!< Transmit Mode */
+#define CAN_MSTS_RXMD ((uint16_t)0x0200) /*!< Receive Mode */
+#define CAN_MSTS_LSMP ((uint16_t)0x0400) /*!< Last Sample Point */
+#define CAN_MSTS_RXS ((uint16_t)0x0800) /*!< CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSTS register ********************/
+#define CAN_TSTS_RQCPM0 ((uint32_t)0x00000001) /*!< Request Completed Mailbox0 */
+#define CAN_TSTS_TXOKM0 ((uint32_t)0x00000002) /*!< Transmission OK of Mailbox0 */
+#define CAN_TSTS_ALSTM0 ((uint32_t)0x00000004) /*!< Arbitration Lost for Mailbox0 */
+#define CAN_TSTS_TERRM0 ((uint32_t)0x00000008) /*!< Transmission Error of Mailbox0 */
+#define CAN_TSTS_ABRQM0 ((uint32_t)0x00000080) /*!< Abort Request for Mailbox0 */
+#define CAN_TSTS_RQCPM1 ((uint32_t)0x00000100) /*!< Request Completed Mailbox1 */
+#define CAN_TSTS_TXOKM1 ((uint32_t)0x00000200) /*!< Transmission OK of Mailbox1 */
+#define CAN_TSTS_ALSTM1 ((uint32_t)0x00000400) /*!< Arbitration Lost for Mailbox1 */
+#define CAN_TSTS_TERRM1 ((uint32_t)0x00000800) /*!< Transmission Error of Mailbox1 */
+#define CAN_TSTS_ABRQM1 ((uint32_t)0x00008000) /*!< Abort Request for Mailbox 1 */
+#define CAN_TSTS_RQCPM2 ((uint32_t)0x00010000) /*!< Request Completed Mailbox2 */
+#define CAN_TSTS_TXOKM2 ((uint32_t)0x00020000) /*!< Transmission OK of Mailbox 2 */
+#define CAN_TSTS_ALSTM2 ((uint32_t)0x00040000) /*!< Arbitration Lost for mailbox 2 */
+#define CAN_TSTS_TERRM2 ((uint32_t)0x00080000) /*!< Transmission Error of Mailbox 2 */
+#define CAN_TSTS_ABRQM2 ((uint32_t)0x00800000) /*!< Abort Request for Mailbox 2 */
+#define CAN_TSTS_CODE ((uint32_t)0x03000000) /*!< Mailbox Code */
+
+#define CAN_TSTS_TMEM ((uint32_t)0x1C000000) /*!< TME[2:0] bits */
+#define CAN_TSTS_TMEM0 ((uint32_t)0x04000000) /*!< Transmit Mailbox 0 Empty */
+#define CAN_TSTS_TMEM1 ((uint32_t)0x08000000) /*!< Transmit Mailbox 1 Empty */
+#define CAN_TSTS_TMEM2 ((uint32_t)0x10000000) /*!< Transmit Mailbox 2 Empty */
+
+#define CAN_TSTS_LOWM ((uint32_t)0xE0000000) /*!< LOW[2:0] bits */
+#define CAN_TSTS_LOWM0 ((uint32_t)0x20000000) /*!< Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSTS_LOWM1 ((uint32_t)0x40000000) /*!< Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSTS_LOWM2 ((uint32_t)0x80000000) /*!< Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RFF0 register *******************/
+#define CAN_RFF0_FFMP0 ((uint8_t)0x03) /*!< DATFIFO 0 Message Pending */
+#define CAN_RFF0_FFULL0 ((uint8_t)0x08) /*!< DATFIFO 0 Full */
+#define CAN_RFF0_FFOVR0 ((uint8_t)0x10) /*!< DATFIFO 0 Overrun */
+#define CAN_RFF0_RFFOM0 ((uint8_t)0x20) /*!< Release DATFIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RFF1 register *******************/
+#define CAN_RFF1_FFMP1 ((uint8_t)0x03) /*!< DATFIFO 1 Message Pending */
+#define CAN_RFF1_FFULL1 ((uint8_t)0x08) /*!< DATFIFO 1 Full */
+#define CAN_RFF1_FFOVR1 ((uint8_t)0x10) /*!< DATFIFO 1 Overrun */
+#define CAN_RFF1_RFFOM1 ((uint8_t)0x20) /*!< Release DATFIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_INTE register *******************/
+#define CAN_INTE_TMEITE ((uint32_t)0x00000001) /*!< Transmit Mailbox Empty Interrupt Enable */
+#define CAN_INTE_FMPITE0 ((uint32_t)0x00000002) /*!< DATFIFO Message Pending Interrupt Enable */
+#define CAN_INTE_FFITE0 ((uint32_t)0x00000004) /*!< DATFIFO Full Interrupt Enable */
+#define CAN_INTE_FOVITE0 ((uint32_t)0x00000008) /*!< DATFIFO Overrun Interrupt Enable */
+#define CAN_INTE_FMPITE1 ((uint32_t)0x00000010) /*!< DATFIFO Message Pending Interrupt Enable */
+#define CAN_INTE_FFITE1 ((uint32_t)0x00000020) /*!< DATFIFO Full Interrupt Enable */
+#define CAN_INTE_FOVITE1 ((uint32_t)0x00000040) /*!< DATFIFO Overrun Interrupt Enable */
+#define CAN_INTE_EWGITE ((uint32_t)0x00000100) /*!< Error Warning Interrupt Enable */
+#define CAN_INTE_EPVITE ((uint32_t)0x00000200) /*!< Error Passive Interrupt Enable */
+#define CAN_INTE_BOFITE ((uint32_t)0x00000400) /*!< Bus-Off Interrupt Enable */
+#define CAN_INTE_LECITE ((uint32_t)0x00000800) /*!< Last Error Code Interrupt Enable */
+#define CAN_INTE_ERRITE ((uint32_t)0x00008000) /*!< Error Interrupt Enable */
+#define CAN_INTE_WKUITE ((uint32_t)0x00010000) /*!< Wakeup Interrupt Enable */
+#define CAN_INTE_SLKITE ((uint32_t)0x00020000) /*!< Sleep Interrupt Enable */
+
+/******************** Bit definition for CAN_ESTS register *******************/
+#define CAN_ESTS_EWGFL ((uint32_t)0x00000001) /*!< Error Warning Flag */
+#define CAN_ESTS_EPVFL ((uint32_t)0x00000002) /*!< Error Passive Flag */
+#define CAN_ESTS_BOFFL ((uint32_t)0x00000004) /*!< Bus-Off Flag */
+
+#define CAN_ESTS_LEC ((uint32_t)0x00000070) /*!< LEC[2:0] bits (Last Error Code) */
+#define CAN_ESTS_LEC_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define CAN_ESTS_LEC_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define CAN_ESTS_LEC_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+
+#define CAN_ESTS_TXEC ((uint32_t)0x00FF0000) /*!< Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESTS_RXEC ((uint32_t)0xFF000000) /*!< Receive Error Counter */
+
+/******************* Bit definition for CAN_BTIM register ********************/
+#define CAN_BTIM_BRTP ((uint32_t)0x000003FF) /*!< Baud Rate Prescaler */
+#define CAN_BTIM_TBS1 ((uint32_t)0x000F0000) /*!< Time Segment 1 */
+#define CAN_BTIM_TBS2 ((uint32_t)0x00700000) /*!< Time Segment 2 */
+#define CAN_BTIM_RSJW ((uint32_t)0x03000000) /*!< Resynchronization Jump Width */
+#define CAN_BTIM_LBM ((uint32_t)0x40000000) /*!< Loop Back Mode (Debug) */
+#define CAN_BTIM_SLM ((uint32_t)0x80000000) /*!< Silent Mode */
+
+/*!< Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TMI0_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
+#define CAN_TMI0_RTRQ ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_TMI0_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_TMI0_EXTID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
+#define CAN_TMI0_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TMDT0_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_TMDT0_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */
+#define CAN_TMDT0_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TMDL0_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_TMDL0_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_TMDL0_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_TMDL0_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TMDH0_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_TMDH0_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_TMDH0_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_TMDH0_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TMI1_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
+#define CAN_TMI1_RTRQ ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_TMI1_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_TMI1_EXTID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
+#define CAN_TMI1_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TMDT1_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_TMDT1_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */
+#define CAN_TMDT1_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TMDL1_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_TMDL1_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_TMDL1_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_TMDL1_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TMDH1_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_TMDH1_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_TMDH1_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_TMDH1_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TMI2_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
+#define CAN_TMI2_RTRQ ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_TMI2_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_TMI2_EXTID ((uint32_t)0x001FFFF8) /*!< Extended identifier */
+#define CAN_TMI2_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TMDT2_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_TMDT2_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */
+#define CAN_TMDT2_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TMDL2_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_TMDL2_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_TMDL2_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_TMDL2_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TMDH2_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_TMDH2_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_TMDH2_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_TMDH2_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RMI0_RTRQ ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_RMI0_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_RMI0_EXTID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
+#define CAN_RMI0_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RMDT0_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_RMDT0_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */
+#define CAN_RMDT0_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RMDL0_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_RMDL0_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_RMDL0_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_RMDL0_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RMDH0_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_RMDH0_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_RMDH0_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_RMDH0_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RMI1_RTRQ ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_RMI1_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_RMI1_EXTID ((uint32_t)0x001FFFF8) /*!< Extended identifier */
+#define CAN_RMI1_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RMDT1_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_RMDT1_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */
+#define CAN_RMDT1_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RMDL1_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_RMDL1_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_RMDL1_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_RMDL1_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RMDH1_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_RMDH1_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_RMDH1_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_RMDH1_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/*!< CAN filter registers */
+/******************* Bit definition for CAN_FMC register ********************/
+#define CAN_FMC_FINITM ((uint8_t)0x01) /*!< Filter Init Mode */
+
+/******************* Bit definition for CAN_FM1 register *******************/
+#define CAN_FM1_FB ((uint16_t)0x3FFF) /*!< Filter Mode */
+#define CAN_FM1_FB0 ((uint16_t)0x0001) /*!< Filter Init Mode bit 0 */
+#define CAN_FM1_FB1 ((uint16_t)0x0002) /*!< Filter Init Mode bit 1 */
+#define CAN_FM1_FB2 ((uint16_t)0x0004) /*!< Filter Init Mode bit 2 */
+#define CAN_FM1_FB3 ((uint16_t)0x0008) /*!< Filter Init Mode bit 3 */
+#define CAN_FM1_FB4 ((uint16_t)0x0010) /*!< Filter Init Mode bit 4 */
+#define CAN_FM1_FB5 ((uint16_t)0x0020) /*!< Filter Init Mode bit 5 */
+#define CAN_FM1_FB6 ((uint16_t)0x0040) /*!< Filter Init Mode bit 6 */
+#define CAN_FM1_FB7 ((uint16_t)0x0080) /*!< Filter Init Mode bit 7 */
+#define CAN_FM1_FB8 ((uint16_t)0x0100) /*!< Filter Init Mode bit 8 */
+#define CAN_FM1_FB9 ((uint16_t)0x0200) /*!< Filter Init Mode bit 9 */
+#define CAN_FM1_FB10 ((uint16_t)0x0400) /*!< Filter Init Mode bit 10 */
+#define CAN_FM1_FB11 ((uint16_t)0x0800) /*!< Filter Init Mode bit 11 */
+#define CAN_FM1_FB12 ((uint16_t)0x1000) /*!< Filter Init Mode bit 12 */
+#define CAN_FM1_FB13 ((uint16_t)0x2000) /*!< Filter Init Mode bit 13 */
+
+/******************* Bit definition for CAN_FS1 register *******************/
+#define CAN_FS1_FSC ((uint16_t)0x3FFF) /*!< Filter Scale Configuration */
+#define CAN_FS1_FSC0 ((uint16_t)0x0001) /*!< Filter Scale Configuration bit 0 */
+#define CAN_FS1_FSC1 ((uint16_t)0x0002) /*!< Filter Scale Configuration bit 1 */
+#define CAN_FS1_FSC2 ((uint16_t)0x0004) /*!< Filter Scale Configuration bit 2 */
+#define CAN_FS1_FSC3 ((uint16_t)0x0008) /*!< Filter Scale Configuration bit 3 */
+#define CAN_FS1_FSC4 ((uint16_t)0x0010) /*!< Filter Scale Configuration bit 4 */
+#define CAN_FS1_FSC5 ((uint16_t)0x0020) /*!< Filter Scale Configuration bit 5 */
+#define CAN_FS1_FSC6 ((uint16_t)0x0040) /*!< Filter Scale Configuration bit 6 */
+#define CAN_FS1_FSC7 ((uint16_t)0x0080) /*!< Filter Scale Configuration bit 7 */
+#define CAN_FS1_FSC8 ((uint16_t)0x0100) /*!< Filter Scale Configuration bit 8 */
+#define CAN_FS1_FSC9 ((uint16_t)0x0200) /*!< Filter Scale Configuration bit 9 */
+#define CAN_FS1_FSC10 ((uint16_t)0x0400) /*!< Filter Scale Configuration bit 10 */
+#define CAN_FS1_FSC11 ((uint16_t)0x0800) /*!< Filter Scale Configuration bit 11 */
+#define CAN_FS1_FSC12 ((uint16_t)0x1000) /*!< Filter Scale Configuration bit 12 */
+#define CAN_FS1_FSC13 ((uint16_t)0x2000) /*!< Filter Scale Configuration bit 13 */
+
+/****************** Bit definition for CAN_FFA1 register *******************/
+#define CAN_FFA1_FAF ((uint16_t)0x3FFF) /*!< Filter DATFIFO Assignment */
+#define CAN_FFA1_FAF0 ((uint16_t)0x0001) /*!< Filter DATFIFO Assignment for Filter 0 */
+#define CAN_FFA1_FAF1 ((uint16_t)0x0002) /*!< Filter DATFIFO Assignment for Filter 1 */
+#define CAN_FFA1_FAF2 ((uint16_t)0x0004) /*!< Filter DATFIFO Assignment for Filter 2 */
+#define CAN_FFA1_FAF3 ((uint16_t)0x0008) /*!< Filter DATFIFO Assignment for Filter 3 */
+#define CAN_FFA1_FAF4 ((uint16_t)0x0010) /*!< Filter DATFIFO Assignment for Filter 4 */
+#define CAN_FFA1_FAF5 ((uint16_t)0x0020) /*!< Filter DATFIFO Assignment for Filter 5 */
+#define CAN_FFA1_FAF6 ((uint16_t)0x0040) /*!< Filter DATFIFO Assignment for Filter 6 */
+#define CAN_FFA1_FAF7 ((uint16_t)0x0080) /*!< Filter DATFIFO Assignment for Filter 7 */
+#define CAN_FFA1_FAF8 ((uint16_t)0x0100) /*!< Filter DATFIFO Assignment for Filter 8 */
+#define CAN_FFA1_FAF9 ((uint16_t)0x0200) /*!< Filter DATFIFO Assignment for Filter 9 */
+#define CAN_FFA1_FAF10 ((uint16_t)0x0400) /*!< Filter DATFIFO Assignment for Filter 10 */
+#define CAN_FFA1_FAF11 ((uint16_t)0x0800) /*!< Filter DATFIFO Assignment for Filter 11 */
+#define CAN_FFA1_FAF12 ((uint16_t)0x1000) /*!< Filter DATFIFO Assignment for Filter 12 */
+#define CAN_FFA1_FAF13 ((uint16_t)0x2000) /*!< Filter DATFIFO Assignment for Filter 13 */
+
+/******************* Bit definition for CAN_FA1 register *******************/
+#define CAN_FA1_FAC ((uint16_t)0x3FFF) /*!< Filter Active */
+#define CAN_FA1_FAC0 ((uint16_t)0x0001) /*!< Filter 0 Active */
+#define CAN_FA1_FAC1 ((uint16_t)0x0002) /*!< Filter 1 Active */
+#define CAN_FA1_FAC2 ((uint16_t)0x0004) /*!< Filter 2 Active */
+#define CAN_FA1_FAC3 ((uint16_t)0x0008) /*!< Filter 3 Active */
+#define CAN_FA1_FAC4 ((uint16_t)0x0010) /*!< Filter 4 Active */
+#define CAN_FA1_FAC5 ((uint16_t)0x0020) /*!< Filter 5 Active */
+#define CAN_FA1_FAC6 ((uint16_t)0x0040) /*!< Filter 6 Active */
+#define CAN_FA1_FAC7 ((uint16_t)0x0080) /*!< Filter 7 Active */
+#define CAN_FA1_FAC8 ((uint16_t)0x0100) /*!< Filter 8 Active */
+#define CAN_FA1_FAC9 ((uint16_t)0x0200) /*!< Filter 9 Active */
+#define CAN_FA1_FAC10 ((uint16_t)0x0400) /*!< Filter 10 Active */
+#define CAN_FA1_FAC11 ((uint16_t)0x0800) /*!< Filter 11 Active */
+#define CAN_FA1_FAC12 ((uint16_t)0x1000) /*!< Filter 12 Active */
+#define CAN_FA1_FAC13 ((uint16_t)0x2000) /*!< Filter 13 Active */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F0B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F0B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F0B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F0B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F0B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F0B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F0B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F0B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F0B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F0B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F0B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F0B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F0B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F0B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F0B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F0B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F0B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F0B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F0B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F0B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F0B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F0B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F0B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F0B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F0B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F0B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F0B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F0B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F0B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F0B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F0B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F1B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F1B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F1B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F1B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F1B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F1B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F1B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F1B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F1B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F1B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F1B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F1B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F1B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F1B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F1B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F1B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F1B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F1B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F1B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F1B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F1B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F1B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F1B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F1B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F1B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F1B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F1B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F1B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F1B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F1B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F1B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F2B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F2B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F2B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F2B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F2B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F2B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F2B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F2B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F2B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F2B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F2B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F2B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F2B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F2B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F2B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F2B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F2B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F2B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F2B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F2B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F2B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F2B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F2B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F2B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F2B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F2B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F2B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F2B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F2B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F2B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F2B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F3B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F3B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F3B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F3B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F3B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F3B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F3B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F3B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F3B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F3B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F3B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F3B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F3B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F3B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F3B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F3B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F3B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F3B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F3B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F3B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F3B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F3B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F3B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F3B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F3B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F3B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F3B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F3B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F3B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F3B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F3B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F4B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F4B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F4B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F4B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F4B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F4B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F4B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F4B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F4B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F4B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F4B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F4B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F4B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F4B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F4B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F4B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F4B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F4B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F4B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F4B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F4B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F4B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F4B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F4B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F4B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F4B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F4B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F4B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F4B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F4B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F4B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F5B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F5B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F5B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F5B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F5B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F5B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F5B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F5B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F5B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F5B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F5B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F5B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F5B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F5B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F5B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F5B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F5B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F5B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F5B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F5B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F5B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F5B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F5B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F5B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F5B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F5B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F5B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F5B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F5B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F5B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F5B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F6B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F6B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F6B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F6B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F6B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F6B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F6B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F6B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F6B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F6B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F6B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F6B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F6B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F6B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F6B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F6B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F6B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F6B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F6B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F6B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F6B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F6B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F6B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F6B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F6B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F6B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F6B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F6B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F6B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F6B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F6B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F7B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F7B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F7B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F7B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F7B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F7B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F7B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F7B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F7B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F7B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F7B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F7B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F7B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F7B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F7B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F7B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F7B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F7B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F7B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F7B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F7B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F7B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F7B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F7B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F7B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F7B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F7B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F7B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F7B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F7B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F7B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F8B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F8B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F8B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F8B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F8B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F8B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F8B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F8B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F8B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F8B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F8B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F8B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F8B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F8B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F8B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F8B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F8B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F8B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F8B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F8B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F8B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F8B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F8B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F8B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F8B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F8B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F8B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F8B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F8B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F8B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F8B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F9B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F9B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F9B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F9B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F9B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F9B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F9B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F9B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F9B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F9B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F9B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F9B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F9B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F9B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F9B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F9B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F9B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F9B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F9B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F9B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F9B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F9B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F9B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F9B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F9B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F9B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F9B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F9B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F9B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F9B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F9B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F10B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F10B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F10B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F10B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F10B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F10B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F10B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F10B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F10B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F10B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F10B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F10B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F10B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F10B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F10B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F10B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F10B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F10B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F10B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F10B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F10B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F10B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F10B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F10B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F10B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F10B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F10B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F10B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F10B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F10B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F10B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F11B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F11B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F11B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F11B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F11B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F11B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F11B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F11B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F11B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F11B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F11B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F11B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F11B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F11B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F11B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F11B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F11B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F11B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F11B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F11B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F11B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F11B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F11B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F11B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F11B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F11B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F11B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F11B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F11B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F11B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F11B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F12B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F12B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F12B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F12B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F12B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F12B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F12B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F12B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F12B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F12B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F12B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F12B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F12B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F12B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F12B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F12B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F12B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F12B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F12B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F12B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F12B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F12B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F12B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F12B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F12B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F12B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F12B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F12B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F12B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F12B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F12B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13B1_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F13B1_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F13B1_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F13B1_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F13B1_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F13B1_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F13B1_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F13B1_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F13B1_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F13B1_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F13B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F13B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F13B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F13B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F13B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F13B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F13B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F13B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F13B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F13B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F13B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F13B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F13B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F13B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F13B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F13B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F13B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F13B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F13B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F13B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F13B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F13B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F0B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F0B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F0B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F0B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F0B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F0B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F0B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F0B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F0B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F0B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F0B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F0B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F0B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F0B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F0B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F0B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F0B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F0B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F0B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F0B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F0B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F0B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F0B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F0B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F0B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F0B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F0B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F0B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F0B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F0B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F0B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F1B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F1B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F1B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F1B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F1B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F1B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F1B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F1B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F1B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F1B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F1B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F1B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F1B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F1B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F1B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F1B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F1B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F1B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F1B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F1B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F1B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F1B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F1B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F1B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F1B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F1B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F1B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F1B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F1B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F1B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F1B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F2B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F2B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F2B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F2B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F2B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F2B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F2B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F2B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F2B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F2B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F2B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F2B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F2B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F2B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F2B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F2B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F2B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F2B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F2B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F2B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F2B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F2B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F2B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F2B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F2B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F2B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F2B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F2B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F2B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F2B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F2B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F3B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F3B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F3B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F3B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F3B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F3B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F3B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F3B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F3B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F3B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F3B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F3B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F3B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F3B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F3B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F3B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F3B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F3B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F3B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F3B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F3B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F3B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F3B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F3B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F3B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F3B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F3B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F3B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F3B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F3B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F3B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F4B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F4B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F4B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F4B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F4B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F4B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F4B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F4B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F4B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F4B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F4B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F4B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F4B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F4B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F4B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F4B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F4B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F4B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F4B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F4B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F4B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F4B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F4B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F4B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F4B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F4B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F4B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F4B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F4B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F4B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F4B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F5B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F5B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F5B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F5B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F5B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F5B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F5B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F5B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F5B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F5B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F5B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F5B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F5B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F5B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F5B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F5B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F5B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F5B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F5B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F5B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F5B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F5B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F5B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F5B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F5B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F5B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F5B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F5B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F5B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F5B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F5B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F6B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F6B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F6B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F6B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F6B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F6B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F6B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F6B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F6B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F6B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F6B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F6B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F6B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F6B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F6B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F6B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F6B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F6B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F6B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F6B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F6B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F6B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F6B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F6B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F6B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F6B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F6B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F6B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F6B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F6B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F6B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F7B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F7B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F7B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F7B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F7B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F7B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F7B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F7B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F7B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F7B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F7B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F7B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F7B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F7B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F7B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F7B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F7B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F7B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F7B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F7B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F7B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F7B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F7B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F7B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F7B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F7B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F7B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F7B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F7B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F7B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F7B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F8B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F8B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F8B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F8B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F8B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F8B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F8B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F8B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F8B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F8B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F8B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F8B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F8B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F8B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F8B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F8B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F8B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F8B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F8B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F8B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F8B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F8B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F8B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F8B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F8B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F8B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F8B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F8B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F8B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F8B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F8B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F9B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F9B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F9B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F9B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F9B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F9B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F9B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F9B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F9B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F9B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F9B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F9B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F9B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F9B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F9B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F9B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F9B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F9B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F9B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F9B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F9B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F9B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F9B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F9B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F9B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F9B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F9B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F9B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F9B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F9B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F9B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F10B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F10B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F10B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F10B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F10B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F10B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F10B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F10B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F10B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F10B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F10B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F10B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F10B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F10B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F10B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F10B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F10B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F10B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F10B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F10B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F10B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F10B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F10B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F10B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F10B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F10B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F10B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F10B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F10B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F10B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F10B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F11B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F11B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F11B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F11B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F11B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F11B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F11B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F11B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F11B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F11B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F11B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F11B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F11B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F11B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F11B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F11B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F11B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F11B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F11B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F11B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F11B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F11B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F11B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F11B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F11B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F11B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F11B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F11B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F11B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F11B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F11B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F12B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F12B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F12B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F12B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F12B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F12B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F12B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F12B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F12B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F12B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F12B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F12B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F12B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F12B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F12B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F12B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F12B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F12B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F12B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F12B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F12B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F12B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F12B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F12B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F12B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F12B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F12B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F12B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F12B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F12B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F12B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13B2_FBC0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F13B2_FBC1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F13B2_FBC2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F13B2_FBC3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F13B2_FBC4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F13B2_FBC5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F13B2_FBC6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F13B2_FBC7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F13B2_FBC8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F13B2_FBC9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F13B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F13B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F13B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F13B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F13B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F13B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F13B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F13B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F13B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F13B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F13B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F13B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F13B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F13B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F13B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F13B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F13B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F13B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F13B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F13B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F13B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F13B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for SPI_CTRL1 register ********************/
+#define SPI_CTRL1_CLKPHA ((uint16_t)0x0001) /*!< Clock Phase */
+#define SPI_CTRL1_CLKPOL ((uint16_t)0x0002) /*!< Clock Polarity */
+#define SPI_CTRL1_MSEL ((uint16_t)0x0004) /*!< Master Selection */
+
+#define SPI_CTRL1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CTRL1_BR0 ((uint16_t)0x0008) /*!< Bit 0 */
+#define SPI_CTRL1_BR1 ((uint16_t)0x0010) /*!< Bit 1 */
+#define SPI_CTRL1_BR2 ((uint16_t)0x0020) /*!< Bit 2 */
+
+#define SPI_CTRL1_SPIEN ((uint16_t)0x0040) /*!< SPI Enable */
+#define SPI_CTRL1_LSBFF ((uint16_t)0x0080) /*!< Frame Format */
+#define SPI_CTRL1_SSEL ((uint16_t)0x0100) /*!< Internal slave select */
+#define SPI_CTRL1_SSMEN ((uint16_t)0x0200) /*!< Software slave management */
+#define SPI_CTRL1_RONLY ((uint16_t)0x0400) /*!< Receive only */
+#define SPI_CTRL1_DATFF ((uint16_t)0x0800) /*!< Data Frame Format */
+#define SPI_CTRL1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */
+#define SPI_CTRL1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */
+#define SPI_CTRL1_BIDIROEN ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */
+#define SPI_CTRL1_BIDIRMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CTRL2 register ********************/
+#define SPI_CTRL2_RDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */
+#define SPI_CTRL2_TDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */
+#define SPI_CTRL2_SSOEN ((uint8_t)0x04) /*!< SS Output Enable */
+#define SPI_CTRL2_ERRINTEN ((uint8_t)0x20) /*!< Error Interrupt Enable */
+#define SPI_CTRL2_RNEINTEN ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CTRL2_TEINTEN ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_STS register ********************/
+#define SPI_STS_RNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */
+#define SPI_STS_TE ((uint8_t)0x02) /*!< Transmit buffer Empty */
+#define SPI_STS_CHSIDE ((uint8_t)0x04) /*!< Channel side */
+#define SPI_STS_UNDER ((uint8_t)0x08) /*!< Underrun flag */
+#define SPI_STS_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */
+#define SPI_STS_MODERR ((uint8_t)0x20) /*!< Mode fault */
+#define SPI_STS_OVER ((uint8_t)0x40) /*!< Overrun flag */
+#define SPI_STS_BUSY ((uint8_t)0x80) /*!< Busy flag */
+
+/******************** Bit definition for SPI_DAT register ********************/
+#define SPI_DAT_DAT ((uint16_t)0xFFFF) /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPOLY register ******************/
+#define SPI_CRCPOLY_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_CRCRDAT register ******************/
+#define SPI_CRCRDAT_CRCRDAT ((uint16_t)0xFFFF) /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_CRCTDAT register ******************/
+#define SPI_CRCTDAT_CRCTDAT ((uint16_t)0xFFFF) /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFG register *****************/
+#define SPI_I2SCFG_CHBITS ((uint16_t)0x0001) /*!< Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFG_TDATLEN ((uint16_t)0x0006) /*!< TDATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFG_TDATLEN0 ((uint16_t)0x0002) /*!< Bit 0 */
+#define SPI_I2SCFG_TDATLEN1 ((uint16_t)0x0004) /*!< Bit 1 */
+
+#define SPI_I2SCFG_CLKPOL ((uint16_t)0x0008) /*!< steady state clock polarity */
+
+#define SPI_I2SCFG_STDSEL ((uint16_t)0x0030) /*!< STDSEL[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFG_STDSEL0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define SPI_I2SCFG_STDSEL1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define SPI_I2SCFG_PCMFSYNC ((uint16_t)0x0080) /*!< PCM frame synchronization */
+
+#define SPI_I2SCFG_MODCFG ((uint16_t)0x0300) /*!< MODCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFG_MODCFG0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define SPI_I2SCFG_MODCFG1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define SPI_I2SCFG_I2SEN ((uint16_t)0x0400) /*!< I2S Enable */
+#define SPI_I2SCFG_MODSEL ((uint16_t)0x0800) /*!< I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPREDIV register *******************/
+#define SPI_I2SPREDIV_LDIV ((uint16_t)0x00FF) /*!< I2S Linear prescaler */
+#define SPI_I2SPREDIV_ODD_EVEN ((uint16_t)0x0100) /*!< Odd factor for the prescaler */
+#define SPI_I2SPREDIV_MCLKOEN ((uint16_t)0x0200) /*!< Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CTRL1 register ********************/
+#define I2C_CTRL1_EN ((uint16_t)0x0001) /*!< Peripheral Enable */
+#define I2C_CTRL1_SMBMODE ((uint16_t)0x0002) /*!< SMBus Mode */
+#define I2C_CTRL1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */
+#define I2C_CTRL1_ARPEN ((uint16_t)0x0010) /*!< ARP Enable */
+#define I2C_CTRL1_PECEN ((uint16_t)0x0020) /*!< PEC Enable */
+#define I2C_CTRL1_GCEN ((uint16_t)0x0040) /*!< General Call Enable */
+#define I2C_CTRL1_NOEXTEND ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */
+#define I2C_CTRL1_STARTGEN ((uint16_t)0x0100) /*!< Start Generation */
+#define I2C_CTRL1_STOPGEN ((uint16_t)0x0200) /*!< Stop Generation */
+#define I2C_CTRL1_ACKEN ((uint16_t)0x0400) /*!< Acknowledge Enable */
+#define I2C_CTRL1_ACKPOS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */
+#define I2C_CTRL1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */
+#define I2C_CTRL1_SMBALERT ((uint16_t)0x2000) /*!< SMBus Alert */
+#define I2C_CTRL1_SWRESET ((uint16_t)0x8000) /*!< Software Reset */
+
+/******************* Bit definition for I2C_CTRL2 register ********************/
+#define I2C_CTRL2_CLKFREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CTRL2_CLKFREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define I2C_CTRL2_CLKFREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define I2C_CTRL2_CLKFREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define I2C_CTRL2_CLKFREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define I2C_CTRL2_CLKFREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define I2C_CTRL2_CLKFREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */
+
+#define I2C_CTRL2_ERRINTEN ((uint16_t)0x0100) /*!< Error Interrupt Enable */
+#define I2C_CTRL2_EVTINTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */
+#define I2C_CTRL2_BUFINTEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */
+#define I2C_CTRL2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */
+#define I2C_CTRL2_DMALAST ((uint16_t)0x1000) /*!< DMA Last Transfer */
+
+/******************* Bit definition for I2C_OADDR1 register *******************/
+#define I2C_OADDR1_ADDR1_7 ((uint16_t)0x00FE) /*!< Interface Address */
+#define I2C_OADDR1_ADDR8_9 ((uint16_t)0x0300) /*!< Interface Address */
+
+#define I2C_OADDR1_ADDR0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define I2C_OADDR1_ADDR1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define I2C_OADDR1_ADDR2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define I2C_OADDR1_ADDR3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define I2C_OADDR1_ADDR4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define I2C_OADDR1_ADDR5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define I2C_OADDR1_ADDR6 ((uint16_t)0x0040) /*!< Bit 6 */
+#define I2C_OADDR1_ADDR7 ((uint16_t)0x0080) /*!< Bit 7 */
+#define I2C_OADDR1_ADDR8 ((uint16_t)0x0100) /*!< Bit 8 */
+#define I2C_OADDR1_ADDR9 ((uint16_t)0x0200) /*!< Bit 9 */
+
+#define I2C_OADDR1_ADDRMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OADDR2 register *******************/
+#define I2C_OADDR2_DUALEN ((uint8_t)0x01) /*!< Dual addressing mode enable */
+#define I2C_OADDR2_ADDR2 ((uint8_t)0xFE) /*!< Interface address */
+
+/******************** Bit definition for I2C_DAT register ********************/
+#define I2C_DAT_DATA ((uint8_t)0xFF) /*!< 8-bit Data Register */
+
+/******************* Bit definition for I2C_STS1 register ********************/
+#define I2C_STS1_STARTBF ((uint16_t)0x0001) /*!< Start Bit (Master mode) */
+#define I2C_STS1_ADDRF ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */
+#define I2C_STS1_BSF ((uint16_t)0x0004) /*!< Byte Transfer Finished */
+#define I2C_STS1_ADDR10F ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */
+#define I2C_STS1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */
+#define I2C_STS1_RXDATNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */
+#define I2C_STS1_TXDATE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */
+#define I2C_STS1_BUSERR ((uint16_t)0x0100) /*!< Bus Error */
+#define I2C_STS1_ARLOST ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */
+#define I2C_STS1_ACKFAIL ((uint16_t)0x0400) /*!< Acknowledge Failure */
+#define I2C_STS1_OVERRUN ((uint16_t)0x0800) /*!< Overrun/Underrun */
+#define I2C_STS1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */
+#define I2C_STS1_TIMOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */
+#define I2C_STS1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */
+
+/******************* Bit definition for I2C_STS2 register ********************/
+#define I2C_STS2_MSMODE ((uint16_t)0x0001) /*!< Master/Slave */
+#define I2C_STS2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */
+#define I2C_STS2_TRF ((uint16_t)0x0004) /*!< Transmitter/Receiver */
+#define I2C_STS2_GCALLADDR ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */
+#define I2C_STS2_SMBDADDR ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */
+#define I2C_STS2_SMBHADDR ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */
+#define I2C_STS2_DUALFLAG ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */
+#define I2C_STS2_PECVAL ((uint16_t)0xFF00) /*!< Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CLKCTRL register ********************/
+#define I2C_CLKCTRL_CLKCTRL ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CLKCTRL_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */
+#define I2C_CLKCTRL_FSMODE ((uint16_t)0x8000) /*!< I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TMRISE_TMRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for USART_STS register *******************/
+#define USART_STS_PEF ((uint16_t)0x0001) /*!< Parity Error */
+#define USART_STS_FEF ((uint16_t)0x0002) /*!< Framing Error */
+#define USART_STS_NEF ((uint16_t)0x0004) /*!< Noise Error Flag */
+#define USART_STS_OREF ((uint16_t)0x0008) /*!< OverRun Error */
+#define USART_STS_IDLEF ((uint16_t)0x0010) /*!< IDLE line detected */
+#define USART_STS_RXDNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */
+#define USART_STS_TXC ((uint16_t)0x0040) /*!< Transmission Complete */
+#define USART_STS_TXDE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */
+#define USART_STS_LINBDF ((uint16_t)0x0100) /*!< LIN Break Detection Flag */
+#define USART_STS_CTSF ((uint16_t)0x0200) /*!< CTS Flag */
+
+/******************* Bit definition for USART_DAT register *******************/
+#define USART_DAT_DATV ((uint16_t)0x01FF) /*!< Data value */
+
+/****************** Bit definition for USART_BRCF register *******************/
+#define USART_BRCF_DIV_Decimal ((uint16_t)0x000F) /*!< Fraction of USARTDIV */
+#define USART_BRCF_DIV_Integer ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CTRL1 register *******************/
+#define USART_CTRL1_SDBRK ((uint16_t)0x0001) /*!< Send Break */
+#define USART_CTRL1_RCVWU ((uint16_t)0x0002) /*!< Receiver wakeup */
+#define USART_CTRL1_RXEN ((uint16_t)0x0004) /*!< Receiver Enable */
+#define USART_CTRL1_TXEN ((uint16_t)0x0008) /*!< Transmitter Enable */
+#define USART_CTRL1_IDLEIEN ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */
+#define USART_CTRL1_RXDNEIEN ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */
+#define USART_CTRL1_TXCIEN ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */
+#define USART_CTRL1_TXDEIEN ((uint16_t)0x0080) /*!< PE Interrupt Enable */
+#define USART_CTRL1_PEIEN ((uint16_t)0x0100) /*!< PE Interrupt Enable */
+#define USART_CTRL1_PSEL ((uint16_t)0x0200) /*!< Parity Selection */
+#define USART_CTRL1_PCEN ((uint16_t)0x0400) /*!< Parity Control Enable */
+#define USART_CTRL1_WUM ((uint16_t)0x0800) /*!< Wakeup method */
+#define USART_CTRL1_WL ((uint16_t)0x1000) /*!< Word length */
+#define USART_CTRL1_UEN ((uint16_t)0x2000) /*!< USART Enable */
+
+/****************** Bit definition for USART_CTRL2 register *******************/
+#define USART_CTRL2_ADDR ((uint16_t)0x000F) /*!< Address of the USART node */
+#define USART_CTRL2_LINBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */
+#define USART_CTRL2_LINBDIEN ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */
+#define USART_CTRL2_LBCLK ((uint16_t)0x0100) /*!< Last Bit Clock pulse */
+#define USART_CTRL2_CLKPHA ((uint16_t)0x0200) /*!< Clock Phase */
+#define USART_CTRL2_CLKPOL ((uint16_t)0x0400) /*!< Clock Polarity */
+#define USART_CTRL2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */
+
+#define USART_CTRL2_STPB ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CTRL2_STPB_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USART_CTRL2_STPB_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USART_CTRL2_LINMEN ((uint16_t)0x4000) /*!< LIN mode enable */
+
+/****************** Bit definition for USART_CTRL3 register *******************/
+#define USART_CTRL3_ERRIEN ((uint16_t)0x0001) /*!< Error Interrupt Enable */
+#define USART_CTRL3_IRDAMEN ((uint16_t)0x0002) /*!< IrDA mode Enable */
+#define USART_CTRL3_IRDALP ((uint16_t)0x0004) /*!< IrDA Low-Power */
+#define USART_CTRL3_HDMEN ((uint16_t)0x0008) /*!< Half-Duplex Selection */
+#define USART_CTRL3_SCNACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */
+#define USART_CTRL3_SCMEN ((uint16_t)0x0020) /*!< Smartcard mode enable */
+#define USART_CTRL3_DMARXEN ((uint16_t)0x0040) /*!< DMA Enable Receiver */
+#define USART_CTRL3_DMATXEN ((uint16_t)0x0080) /*!< DMA Enable Transmitter */
+#define USART_CTRL3_RTSEN ((uint16_t)0x0100) /*!< RTS Enable */
+#define USART_CTRL3_CTSEN ((uint16_t)0x0200) /*!< CTS Enable */
+#define USART_CTRL3_CTSIEN ((uint16_t)0x0400) /*!< CTS Interrupt Enable */
+
+/****************** Bit definition for USART_GTP register ******************/
+#define USART_GTP_PSCV ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTP_PSCV_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define USART_GTP_PSCV_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define USART_GTP_PSCV_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define USART_GTP_PSCV_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define USART_GTP_PSCV_4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define USART_GTP_PSCV_5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define USART_GTP_PSCV_6 ((uint16_t)0x0040) /*!< Bit 6 */
+#define USART_GTP_PSCV_7 ((uint16_t)0x0080) /*!< Bit 7 */
+
+#define USART_GTP_GTV ((uint16_t)0xFF00) /*!< Guard time value */
+
+/******************************************************************************/
+/* */
+/* Low-power Universal Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for LPUART_STS register ******************/
+#define LPUART_STS_PEF ((uint16_t)0x0001) /*!< Parity Check Error Flag */
+#define LPUART_STS_TXC ((uint16_t)0x0002) /*!< TX Complete Flag */
+#define LPUART_STS_FIFO_OV ((uint16_t)0x0004) /*!< FIFO Overflow Flag */
+#define LPUART_STS_FIFO_FU ((uint16_t)0x0008) /*!< FIFO Full Flag */
+#define LPUART_STS_FIFO_HF ((uint16_t)0x0010) /*!< FIFO Half Full Flag */
+#define LPUART_STS_FIFO_NE ((uint16_t)0x0020) /*!< FIFO Non-Empty Flag */
+#define LPUART_STS_CTS ((uint16_t)0x0040) /*!< Clear to Send (Hardware Flow Control) Flag */
+#define LPUART_STS_WUF ((uint16_t)0x0080) /*!< Wakeup from Stop mode Flag */
+#define LPUART_STS_NF ((uint16_t)0x0100) /*!< Noise Detected Flag */
+
+/****************** Bit definition for LPUART_INTEN register ******************/
+#define LPUART_INTEN_PEIE ((uint8_t)0x01) /*!< Parity Check Error Interrupt Enable */
+#define LPUART_INTEN_TXCIE ((uint8_t)0x02) /*!< TX Complete Interrupt Enable */
+#define LPUART_INTEN_FIFO_OVIE ((uint8_t)0x04) /*!< FIFO Overflow Interrupt Enable */
+#define LPUART_INTEN_FIFO_FUIE ((uint8_t)0x08) /*!< FIFO Full Interrupt Enable*/
+#define LPUART_INTEN_FIFO_HFIE ((uint8_t)0x10) /*!< FIFO Half Full Interrupt Enable */
+#define LPUART_INTEN_FIFO_NEIE ((uint8_t)0x20) /*!< FIFO Non-Empty Interrupt Enable */
+#define LPUART_INTEN_WUFIE ((uint8_t)0x40) /*!< Wakeup Interrupt Enable */
+
+/****************** Bit definition for LPUART_CTRL register ******************/
+#define LPUART_CTRL_PSEL ((uint16_t)0x0001) /*!< Odd Parity Bit Enable */
+#define LPUART_CTRL_TXEN ((uint16_t)0x0002) /*!< TX Enable */
+#define LPUART_CTRL_FLUSH ((uint16_t)0x0004) /*!< Flush Receiver FIFO Enable */
+#define LPUART_CTRL_PCDIS ((uint16_t)0x0008) /*!< Parity Control Disable */
+#define LPUART_CTRL_LOOPBACK ((uint16_t)0x0010) /*!< Loop Back Self-Test */
+#define LPUART_CTRL_DMA_TXEN ((uint16_t)0x0020) /*!< DMA TX Request Enable */
+#define LPUART_CTRL_DMA_RXEN ((uint16_t)0x0040) /*!< DMA RX Request Enable */
+#define LPUART_CTRL_WUSTP ((uint16_t)0x0080) /*!< LPUART Wakeup Enable in Stop mode */
+#define LPUART_CTRL_RTS_THSEL ((uint16_t)0x0300) /*!< RTS Threshold Selection */
+#define LPUART_CTRL_CTSEN ((uint16_t)0x0400) /*!< Hardware Flow Control TX Enable */
+#define LPUART_CTRL_RTSEN ((uint16_t)0x0800) /*!< Hardware Flow Control RX Enable */
+#define LPUART_CTRL_WUSEL ((uint16_t)0x3000) /*!< Wakeup Event Selection */
+#define LPUART_CTRL_SMPCNT ((uint16_t)0x4000) /*!< Specify the Sampling Method */
+
+/****************** Bit definition for LPUART_BRCFG1 register ******************/
+#define LPUART_BRCFG1_INTEGER ((uint16_t)0xFFFF) /*!< Baud Rate Parameter Configeration Register1: Fraction */
+
+/****************** Bit definition for LPUART_DAT register ******************/
+#define LPUART_DAT_DAT ((uint8_t)0xFF) /*!< Data Register */
+
+/****************** Bit definition for LPUART_BRCFG2 register ******************/
+#define LPUART_BRCFG2_DECIMAL ((uint8_t)0xFF) /*!< Baud Rate Parameter Configeration Register2: Mantissa */
+
+/****************** Bit definition for LPUART_WUDAT register ******************/
+#define LPUART_WUDAT_WUDAT ((uint32_t)0xFFFFFFFF) /*!< Data Register */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBG_ID register *****************/
+#define DBG_ID_DEV ((uint32_t)0x00000FFF) /*!< Device Identifier */
+
+#define DBG_ID_REV ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBG_ID_REV_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define DBG_ID_REV_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define DBG_ID_REV_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define DBG_ID_REV_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define DBG_ID_REV_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define DBG_ID_REV_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define DBG_ID_REV_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define DBG_ID_REV_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+#define DBG_ID_REV_8 ((uint32_t)0x01000000) /*!< Bit 8 */
+#define DBG_ID_REV_9 ((uint32_t)0x02000000) /*!< Bit 9 */
+#define DBG_ID_REV_10 ((uint32_t)0x04000000) /*!< Bit 10 */
+#define DBG_ID_REV_11 ((uint32_t)0x08000000) /*!< Bit 11 */
+#define DBG_ID_REV_12 ((uint32_t)0x10000000) /*!< Bit 12 */
+#define DBG_ID_REV_13 ((uint32_t)0x20000000) /*!< Bit 13 */
+#define DBG_ID_REV_14 ((uint32_t)0x40000000) /*!< Bit 14 */
+#define DBG_ID_REV_15 ((uint32_t)0x80000000) /*!< Bit 15 */
+
+/****************** Bit definition for DBG_CTRL register *******************/
+#define DBG_CTRL_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
+#define DBG_CTRL_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
+#define DBG_CTRL_STDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
+
+#define DBG_CTRL_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBG_CTRL_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBG_CTRL_TIM1_STOP ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */
+#define DBG_CTRL_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */
+#define DBG_CTRL_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */
+#define DBG_CTRL_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */
+#define DBG_CTRL_CAN_STOP ((uint32_t)0x00004000) /*!< Debug CAN stopped when Core is halted */
+#define DBG_CTRL_I2C1SMBUS_TO ((uint32_t)0x00008000) /*!< SMBUS I2C1 timeout mode stopped when Core is halted */
+#define DBG_CTRL_I2C2SMBUS_TO ((uint32_t)0x00010000) /*!< SMBUS I2C2 timeout mode stopped when Core is halted */
+#define DBG_CTRL_TIM8_STOP ((uint32_t)0x00020000) /*!< TIM8 counter stopped when core is halted */
+#define DBG_CTRL_TIM5_STOP ((uint32_t)0x00040000) /*!< TIM5 counter stopped when core is halted */
+#define DBG_CTRL_TIM6_STOP ((uint32_t)0x00080000) /*!< TIM6 counter stopped when core is halted */
+#define DBG_CTRL_TIM7_STOP ((uint32_t)0x00100000) /*!< TIM7 counter stopped when core is halted */
+#define DBG_CTRL_TIM9_STOP ((uint32_t)0x00200000) /*!< TIM9 counter stopped when core is halted*/
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_AC register ******************/
+#define FLASH_AC_LATENCY ((uint32_t)0x00000003) /*!< LATENCY[2:0] bits (Latency) */
+#define FLASH_AC_LATENCY_0 ((uint32_t)0x00000000) /*!< Bit 0 = 0 */
+#define FLASH_AC_LATENCY_1 ((uint32_t)0x00000001) /*!< Bit 0 = 1 */
+#define FLASH_AC_LATENCY_2 ((uint32_t)0x00000002) /*!< Bit 0 = 0; Bit 1 = 1 */
+#define FLASH_AC_LATENCY_3 ((uint32_t)0x00000003) /*!< Bit 0 = 1; Bit 1 = 1 */
+
+#define FLASH_AC_PRFTBFEN ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
+#define FLASH_AC_PRFTBFSTS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
+#define FLASH_AC_ICAHRST ((uint32_t)0x00000040) /*!< Icache Reset */
+#define FLASH_AC_ICAHEN ((uint32_t)0x00000080) /*!< Icache Enable */
+#define FLASH_AC_LVMF ((uint32_t)0x00000100) /*!< Flash low power work mode status */
+#define FLASH_AC_LVMEN ((uint32_t)0x00000200) /*!< Flash low power work mode Enable */
+#define FLASH_AC_SLMF ((uint32_t)0x00000400) /*!< Flash sleep mode status */
+#define FLASH_AC_SLMEN ((uint32_t)0x00000800) /*!< Flash sleep mode Enable */
+
+/****************** Bit definition for FLASH_KEY register ******************/
+#define FLASH_KEY_FKEY ((uint32_t)0xFFFFFFFF) /*!< FLASH Key */
+
+/***************** Bit definition for FLASH_OPTKEY register ****************/
+#define FLASH_OPTKEY_OPTKEY ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
+
+/****************** Bit definition for FLASH_STS register *******************/
+#define FLASH_STS_BUSY ((uint8_t)0x01) /*!< Busy */
+#define FLASH_STS_PGERR ((uint8_t)0x04) /*!< Programming Error */
+#define FLASH_STS_PVERR ((uint8_t)0x08) /*!< Programming Verify ERROR after program */
+#define FLASH_STS_WRPERR ((uint8_t)0x10) /*!< Write Protection Error */
+#define FLASH_STS_EOP ((uint8_t)0x20) /*!< End of operation */
+#define FLASH_STS_EVERR ((uint8_t)0x40) /*!< Erase Verify ERROR after page erase */
+
+/******************* Bit definition for FLASH_CTRL register *******************/
+#define FLASH_CTRL_PG ((uint16_t)0x0001) /*!< Programming */
+#define FLASH_CTRL_PER ((uint16_t)0x0002) /*!< Page Erase */
+#define FLASH_CTRL_MER ((uint16_t)0x0004) /*!< Mass Erase */
+#define FLASH_CTRL_OPTPG ((uint16_t)0x0010) /*!< Option Byte Programming */
+#define FLASH_CTRL_OPTER ((uint16_t)0x0020) /*!< Option Byte Erase */
+#define FLASH_CTRL_START ((uint16_t)0x0040) /*!< Start */
+#define FLASH_CTRL_LOCK ((uint16_t)0x0080) /*!< Lock */
+#define FLASH_CTRL_SMPSEL ((uint16_t)0x0100) /*!< Flash Program Option Select */
+#define FLASH_CTRL_OPTWE ((uint16_t)0x0200) /*!< Option Bytes Write Enable */
+#define FLASH_CTRL_ERRITE ((uint16_t)0x0400) /*!< Error Interrupt Enable */
+#define FLASH_CTRL_FERRITE ((uint16_t)0x0800) /*!< EVERR PVERR Error Interrupt Enable */
+#define FLASH_CTRL_EOPITE ((uint16_t)0x1000) /*!< End of operation Interrupt Enable */
+
+/******************* Bit definition for FLASH_ADD register *******************/
+#define FLASH_ADD_FADD ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OB2 register *******************/
+#define FLASH_OB2_BOR_LEV ((uint32_t)0x00000700) /*!< BOR_LEV[2:0] */
+#define FLASH_OB2_nBOOT1 ((uint32_t)0x00800000) /*!< nBOOT1 */
+#define FLASH_OB2_nSWBOOT0 ((uint32_t)0x04000000) /*!< nSWBOOT0 */
+#define FLASH_OB2_nBOOT0 ((uint32_t)0x08000000) /*!< nBOOT1 */
+
+/****************** Bit definition for FLASH_OB register *******************/
+#define FLASH_OB_OBERR ((uint16_t)0x0001) /*!< Option Byte Error */
+#define FLASH_OB_RDPRT1 ((uint16_t)0x0002) /*!< Read Protection */
+
+#define FLASH_OB_USER ((uint16_t)0x03FC) /*!< User Option Bytes */
+#define FLASH_OB_WDG_SW ((uint16_t)0x0004) /*!< WDG_SW */
+#define FLASH_OB_NRST_STOP2 ((uint16_t)0x0008) /*!< nRST_STOP2 */
+#define FLASH_OB_NRST_STDBY ((uint16_t)0x0010) /*!< nRST_STDBY */
+#define FLASH_OB_NRST_PD ((uint16_t)0x0020) /*!< nRST_PD */
+
+#define FLASH_OB_DATA0_MSK ((uint32_t)0x0003FC00) /*!< Data0 Mask */
+#define FLASH_OB_DATA1_MSK ((uint32_t)0x03FC0000) /*!< Data1 Mask */
+#define FLASH_OB_RDPRT2 ((uint32_t)0x80000000) /*!< Read Protection Level 2 */
+
+/****************** Bit definition for FLASH_WRP register ******************/
+#define FLASH_WRP_WRPT ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
+
+/****************** Bit definition for FLASH_CAHR register ******************/
+#define FLASH_CAHR_LOCKSTRT_MSK ((uint32_t)0x000F) /*!< LOCKSTRT Mask */
+#define FLASH_CAHR_LOCKSTOP_MSK ((uint32_t)0x00F0) /*!< LOCKSTOP Mask */
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for OptionByte USER ******************/
+#define FLASH_RDP_RDP1 ((uint32_t)0x000000FF) /*!< Read protection option byte */
+#define FLASH_RDP_NRDP1 ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
+
+/****************** Bit definition for OptionByte USER ******************/
+#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
+#define FLASH_USER_NUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
+
+/****************** Bit definition for OptionByte Data0 *****************/
+#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!< User data storage option byte */
+#define FLASH_Data0_NData0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */
+
+/****************** Bit definition for OptionByte Data1 *****************/
+#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */
+#define FLASH_Data1_NData1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */
+
+/****************** Bit definition for OptionByte WRP0 ******************/
+#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP0_NWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for OptionByte WRP1 ******************/
+#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP1_NWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for OptionByte WRP2 ******************/
+#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP2_NWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for OptionByte WRP3 ******************/
+#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP3_NWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for OptionByte RDP2 *******************/
+#define FLASH_RDP_RDP2 ((uint32_t)0x000000FF) /*!< Read protection level 2 option byte */
+#define FLASH_RDP_NRDP2 ((uint32_t)0x0000FF00) /*!< Read protection level 2 complemented option byte */
+
+/****************** Bit definition for OptionByte USER2 ******************/
+#define FLASH_USER_USER2 ((uint32_t)0x00FF0000) /*!< User option byte */
+#define FLASH_USER_NUSER2 ((uint32_t)0xFF000000) /*!< User complemented option byte */
+
+/******************************************************************************/
+/* */
+/* General Purpose and Alternate Function I/O */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for GPIO_PMODE register *******************/
+
+
+#define GPIO_PMODE0_Pos (0)
+#define GPIO_PMODE0_Msk (0x3 << GPIO_PMODE0_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE0 GPIO_PMODE0_Msk
+#define GPIO_PMODE0_0 (0x0 << GPIO_PMODE0_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE0_1 (0x1 << GPIO_PMODE0_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE0_2 (0x2 << GPIO_PMODE0_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE0_3 (0x3 << GPIO_PMODE0_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE1_Pos (2)
+#define GPIO_PMODE1_Msk (0x3 << GPIO_PMODE1_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE1 GPIO_PMODE1_Msk
+#define GPIO_PMODE1_0 (0x0 << GPIO_PMODE1_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE1_1 (0x1 << GPIO_PMODE1_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE1_2 (0x2 << GPIO_PMODE1_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE1_3 (0x3 << GPIO_PMODE1_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE2_Pos (4)
+#define GPIO_PMODE2_Msk (0x3 << GPIO_PMODE2_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE2 GPIO_PMODE2_Msk
+#define GPIO_PMODE2_0 (0x0 << GPIO_PMODE2_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE2_1 (0x1 << GPIO_PMODE2_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE2_2 (0x2 << GPIO_PMODE2_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE2_3 (0x3 << GPIO_PMODE2_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE3_Pos (6)
+#define GPIO_PMODE3_Msk (0x3 << GPIO_PMODE3_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE3 GPIO_PMODE3_Msk
+#define GPIO_PMODE3_0 (0x0 << GPIO_PMODE3_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE3_1 (0x1 << GPIO_PMODE3_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE3_2 (0x2 << GPIO_PMODE3_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE3_3 (0x3 << GPIO_PMODE3_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE4_Pos (8)
+#define GPIO_PMODE4_Msk (0x3 << GPIO_PMODE4_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE4 GPIO_PMODE4_Msk
+#define GPIO_PMODE4_0 (0x0 << GPIO_PMODE4_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE4_1 (0x1 << GPIO_PMODE4_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE4_2 (0x2 << GPIO_PMODE4_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE4_3 (0x3 << GPIO_PMODE4_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE5_Pos (10)
+#define GPIO_PMODE5_Msk (0x3 << GPIO_PMODE5_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE5 GPIO_PMODE5_Msk
+#define GPIO_PMODE5_0 (0x0 << GPIO_PMODE5_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE5_1 (0x1 << GPIO_PMODE5_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE5_2 (0x2 << GPIO_PMODE5_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE5_3 (0x3 << GPIO_PMODE5_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE6_Pos (12)
+#define GPIO_PMODE6_Msk (0x3 << GPIO_PMODE6_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE6 GPIO_PMODE6_Msk
+#define GPIO_PMODE6_0 (0x0 << GPIO_PMODE6_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE6_1 (0x1 << GPIO_PMODE6_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE6_2 (0x2 << GPIO_PMODE6_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE6_3 (0x3 << GPIO_PMODE6_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE7_Pos (14)
+#define GPIO_PMODE7_Msk (0x3 << GPIO_PMODE7_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE7 GPIO_PMODE7_Msk
+#define GPIO_PMODE7_0 (0x0 << GPIO_PMODE7_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE7_1 (0x1 << GPIO_PMODE7_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE7_2 (0x2 << GPIO_PMODE7_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE7_3 (0x3 << GPIO_PMODE7_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE8_Pos (16)
+#define GPIO_PMODE8_Msk (0x3 << GPIO_PMODE8_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE8 GPIO_PMODE8_Msk
+#define GPIO_PMODE8_0 (0x0 << GPIO_PMODE8_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE8_1 (0x1 << GPIO_PMODE8_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE8_2 (0x2 << GPIO_PMODE8_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE8_3 (0x3 << GPIO_PMODE8_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE9_Pos (18)
+#define GPIO_PMODE9_Msk (0x3 << GPIO_PMODE9_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE9 GPIO_PMODE9_Msk
+#define GPIO_PMODE9_0 (0x0 << GPIO_PMODE9_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE9_1 (0x1 << GPIO_PMODE9_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE9_2 (0x2 << GPIO_PMODE9_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE9_3 (0x3 << GPIO_PMODE9_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE10_Pos (20)
+#define GPIO_PMODE10_Msk (0x3 << GPIO_PMODE10_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE10 GPIO_PMODE10_Msk
+#define GPIO_PMODE10_0 (0x0 << GPIO_PMODE10_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE10_1 (0x1 << GPIO_PMODE10_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE10_2 (0x2 << GPIO_PMODE10_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE10_3 (0x3 << GPIO_PMODE10_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE11_Pos (22)
+#define GPIO_PMODE11_Msk (0x3 << GPIO_PMODE11_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE11 GPIO_PMODE11_Msk
+#define GPIO_PMODE11_0 (0x0 << GPIO_PMODE11_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE11_1 (0x1 << GPIO_PMODE11_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE11_2 (0x2 << GPIO_PMODE11_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE11_3 (0x3 << GPIO_PMODE11_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE12_Pos (24)
+#define GPIO_PMODE12_Msk (0x3 << GPIO_PMODE12_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE12 GPIO_PMODE12_Msk
+#define GPIO_PMODE12_0 (0x0 << GPIO_PMODE12_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE12_1 (0x1 << GPIO_PMODE12_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE12_2 (0x2 << GPIO_PMODE12_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE12_3 (0x3 << GPIO_PMODE12_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE13_Pos (26)
+#define GPIO_PMODE13_Msk (0x3 << GPIO_PMODE13_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE13 GPIO_PMODE13_Msk
+#define GPIO_PMODE13_0 (0x0 << GPIO_PMODE13_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE13_1 (0x1 << GPIO_PMODE13_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE13_2 (0x2 << GPIO_PMODE13_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE13_3 (0x3 << GPIO_PMODE13_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE14_Pos (28)
+#define GPIO_PMODE14_Msk (0x3 << GPIO_PMODE14_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE14 GPIO_PMODE14_Msk
+#define GPIO_PMODE14_0 (0x0 << GPIO_PMODE14_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE14_1 (0x1 << GPIO_PMODE14_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE14_2 (0x2 << GPIO_PMODE14_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE14_3 (0x3 << GPIO_PMODE14_Pos) /*!< 0x00000003 */
+
+#define GPIO_PMODE15_Pos (30)
+#define GPIO_PMODE15_Msk (0x3 << GPIO_PMODE15_Pos) /*!< 0x00000003 */
+#define GPIO_PMODE15 GPIO_PMODE15_Msk
+#define GPIO_PMODE15_0 (0x0 << GPIO_PMODE15_Pos) /*!< 0x00000000 */
+#define GPIO_PMODE15_1 (0x1 << GPIO_PMODE15_Pos) /*!< 0x00000001 */
+#define GPIO_PMODE15_2 (0x2 << GPIO_PMODE15_Pos) /*!< 0x00000002 */
+#define GPIO_PMODE15_3 (0x3 << GPIO_PMODE15_Pos) /*!< 0x00000003 */
+
+
+
+
+/****************** Bit definition for GPIO_POTYPER register *****************/
+#define GPIO_POTYPE_POT_0 (0x00000001)
+#define GPIO_POTYPE_POT_1 (0x00000002)
+#define GPIO_POTYPE_POT_2 (0x00000004)
+#define GPIO_POTYPE_POT_3 (0x00000008)
+#define GPIO_POTYPE_POT_4 (0x00000010)
+#define GPIO_POTYPE_POT_5 (0x00000020)
+#define GPIO_POTYPE_POT_6 (0x00000040)
+#define GPIO_POTYPE_POT_7 (0x00000080)
+#define GPIO_POTYPE_POT_8 (0x00000100)
+#define GPIO_POTYPE_POT_9 (0x00000200)
+#define GPIO_POTYPE_POT_10 (0x00000400)
+#define GPIO_POTYPE_POT_11 (0x00000800)
+#define GPIO_POTYPE_POT_12 (0x00001000)
+#define GPIO_POTYPE_POT_13 (0x00002000)
+#define GPIO_POTYPE_POT_14 (0x00004000)
+#define GPIO_POTYPE_POT_15 (0x00008000)
+
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPD0_Pos (0)
+#define GPIO_PUPD0_Msk (0x3 << GPIO_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD0 GPIO_PUPD0_Msk
+#define GPIO_PUPD0_0 (0x0 << GPIO_PUPD0_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD0_1 (0x1 << GPIO_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD0_2 (0x2 << GPIO_PUPD0_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD1_Pos (2)
+#define GPIO_PUPD1_Msk (0x3 << GPIO_PUPD1_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD1 GPIO_PUPD1_Msk
+#define GPIO_PUPD1_0 (0x0 << GPIO_PUPD1_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD1_1 (0x1 << GPIO_PUPD1_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD1_2 (0x2 << GPIO_PUPD1_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD2_Pos (4)
+#define GPIO_PUPD2_Msk (0x3 << GPIO_PUPD2_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD2 GPIO_PUPD2_Msk
+#define GPIO_PUPD2_0 (0x0 << GPIO_PUPD2_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD2_1 (0x1 << GPIO_PUPD2_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD2_2 (0x2 << GPIO_PUPD2_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD3_Pos (6)
+#define GPIO_PUPD3_Msk (0x3 << GPIO_PUPD3_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD3 GPIO_PUPD3_Msk
+#define GPIO_PUPD3_0 (0x0 << GPIO_PUPD3_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD3_1 (0x1 << GPIO_PUPD3_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD3_2 (0x2 << GPIO_PUPD3_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD4_Pos (8)
+#define GPIO_PUPD4_Msk (0x3 << GPIO_PUPD4_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD4 GPIO_PUPD4_Msk
+#define GPIO_PUPD4_0 (0x0 << GPIO_PUPD4_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD4_1 (0x1 << GPIO_PUPD4_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD4_2 (0x2 << GPIO_PUPD4_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD5_Pos (10)
+#define GPIO_PUPD5_Msk (0x3 << GPIO_PUPD5_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD5 GPIO_PUPD5_Msk
+#define GPIO_PUPD5_0 (0x0 << GPIO_PUPD5_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD5_1 (0x1 << GPIO_PUPD5_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD5_2 (0x2 << GPIO_PUPD5_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD6_Pos (12)
+#define GPIO_PUPD6_Msk (0x3 << GPIO_PUPD6_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD6 GPIO_PUPD6_Msk
+#define GPIO_PUPD6_0 (0x0 << GPIO_PUPD6_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD6_1 (0x1 << GPIO_PUPD6_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD6_2 (0x2 << GPIO_PUPD6_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD7_Pos (14)
+#define GPIO_PUPD7_Msk (0x3 << GPIO_PUPD7_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD7 GPIO_PUPD7_Msk
+#define GPIO_PUPD7_0 (0x0 << GPIO_PUPD7_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD7_1 (0x1 << GPIO_PUPD7_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD7_2 (0x2 << GPIO_PUPD7_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD8_Pos (16)
+#define GPIO_PUPD8_Msk (0x3 << GPIO_PUPD8_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD8 GPIO_PUPD8_Msk
+#define GPIO_PUPD8_0 (0x0 << GPIO_PUPD8_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD8_1 (0x1 << GPIO_PUPD8_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD8_2 (0x2 << GPIO_PUPD8_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD9_Pos (18)
+#define GPIO_PUPD9_Msk (0x3 << GPIO_PUPD9_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD9 GPIO_PUPD9_Msk
+#define GPIO_PUPD9_0 (0x0 << GPIO_PUPD9_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD9_1 (0x1 << GPIO_PUPD9_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD9_2 (0x2 << GPIO_PUPD9_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD10_Pos (20)
+#define GPIO_PUPD10_Msk (0x3 << GPIO_PUPD10_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD10 GPIO_PUPD10_Msk
+#define GPIO_PUPD10_0 (0x0 << GPIO_PUPD10_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD10_1 (0x1 << GPIO_PUPD10_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD10_2 (0x2 << GPIO_PUPD10_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD11_Pos (22)
+#define GPIO_PUPD11_Msk (0x3 << GPIO_PUPD11_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD11 GPIO_PUPD11_Msk
+#define GPIO_PUPD11_0 (0x0 << GPIO_PUPD11_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD11_1 (0x1 << GPIO_PUPD11_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD11_2 (0x2 << GPIO_PUPD11_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD12_Pos (24)
+#define GPIO_PUPD12_Msk (0x3 << GPIO_PUPD12_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD12 GPIO_PUPD12_Msk
+#define GPIO_PUPD12_0 (0x0 << GPIO_PUPD12_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD12_1 (0x1 << GPIO_PUPD12_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD12_2 (0x2 << GPIO_PUPD12_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD13_Pos (26)
+#define GPIO_PUPD13_Msk (0x3 << GPIO_PUPD13_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD13 GPIO_PUPD13_Msk
+#define GPIO_PUPD13_0 (0x0 << GPIO_PUPD13_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD13_1 (0x1 << GPIO_PUPD13_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD13_2 (0x2 << GPIO_PUPD13_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD14_Pos (28)
+#define GPIO_PUPD14_Msk (0x3 << GPIO_PUPD14_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD14 GPIO_PUPD14_Msk
+#define GPIO_PUPD14_0 (0x0 << GPIO_PUPD14_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD14_1 (0x1 << GPIO_PUPD14_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD14_2 (0x2 << GPIO_PUPD14_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPD15_Pos (30)
+#define GPIO_PUPD15_Msk (0x3 << GPIO_PUPD15_Pos) /*!< 0x00000003 */
+#define GPIO_PUPD15 GPIO_PUPD15_Msk
+#define GPIO_PUPD15_0 (0x0 << GPIO_PUPD15_Pos) /*!< 0x00000000 */
+#define GPIO_PUPD15_1 (0x1 << GPIO_PUPD15_Pos) /*!< 0x00000001 */
+#define GPIO_PUPD15_2 (0x2 << GPIO_PUPD15_Pos) /*!< 0x00000002 */
+
+
+/*!<****************** Bit definition for GPIO_IDR register *******************/
+#define GPIO_PID_PID0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */
+#define GPIO_PID_PID1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */
+#define GPIO_PID_PID2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */
+#define GPIO_PID_PID3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */
+#define GPIO_PID_PID4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */
+#define GPIO_PID_PID5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */
+#define GPIO_PID_PID6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */
+#define GPIO_PID_PID7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */
+#define GPIO_PID_PID8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */
+#define GPIO_PID_PID9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */
+#define GPIO_PID_PID10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */
+#define GPIO_PID_PID11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */
+#define GPIO_PID_PID12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */
+#define GPIO_PID_PID13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */
+#define GPIO_PID_PID14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */
+#define GPIO_PID_PID15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */
+
+/******************* Bit definition for GPIO_POD register *******************/
+#define GPIO_POD_POD0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */
+#define GPIO_POD_POD1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */
+#define GPIO_POD_POD2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */
+#define GPIO_POD_POD3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */
+#define GPIO_POD_POD4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */
+#define GPIO_POD_POD5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */
+#define GPIO_POD_POD6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */
+#define GPIO_POD_POD7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */
+#define GPIO_POD_POD8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */
+#define GPIO_POD_POD9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */
+#define GPIO_POD_POD10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */
+#define GPIO_POD_POD11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */
+#define GPIO_POD_POD12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */
+#define GPIO_POD_POD13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */
+#define GPIO_POD_POD14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */
+#define GPIO_POD_POD15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */
+
+/****************** Bit definition for GPIO_BSRR register *******************/
+#define GPIO_PBSC_PBS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */
+#define GPIO_PBSC_PBS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */
+#define GPIO_PBSC_PBS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */
+#define GPIO_PBSC_PBS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */
+#define GPIO_PBSC_PBS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */
+#define GPIO_PBSC_PBS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */
+#define GPIO_PBSC_PBS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */
+#define GPIO_PBSC_PBS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */
+#define GPIO_PBSC_PBS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */
+#define GPIO_PBSC_PBS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */
+#define GPIO_PBSC_PBS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */
+#define GPIO_PBSC_PBS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */
+#define GPIO_PBSC_PBS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */
+#define GPIO_PBSC_PBS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */
+#define GPIO_PBSC_PBS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */
+#define GPIO_PBSC_PBS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */
+
+#define GPIO_PBSC_PBC0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */
+#define GPIO_PBSC_PBC1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */
+#define GPIO_PBSC_PBC2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */
+#define GPIO_PBSC_PBC3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */
+#define GPIO_PBSC_PBC4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */
+#define GPIO_PBSC_PBC5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */
+#define GPIO_PBSC_PBC6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */
+#define GPIO_PBSC_PBC7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */
+#define GPIO_PBSC_PBC8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */
+#define GPIO_PBSC_PBC9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */
+#define GPIO_PBSC_PBC10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */
+#define GPIO_PBSC_PBC11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */
+#define GPIO_PBSC_PBC12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */
+#define GPIO_PBSC_PBC13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */
+#define GPIO_PBSC_PBC14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */
+#define GPIO_PBSC_PBC15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */
+
+/******************* Bit definition for GPIO_BRR register *******************/
+#define GPIO_PBC_PBC0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */
+#define GPIO_PBC_PBC1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */
+#define GPIO_PBC_PBC2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */
+#define GPIO_PBC_PBC3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */
+#define GPIO_PBC_PBC4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */
+#define GPIO_PBC_PBC5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */
+#define GPIO_PBC_PBC6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */
+#define GPIO_PBC_PBC7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */
+#define GPIO_PBC_PBC8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */
+#define GPIO_PBC_PBC9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */
+#define GPIO_PBC_PBC10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */
+#define GPIO_PBC_PBC11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */
+#define GPIO_PBC_PBC12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */
+#define GPIO_PBC_PBC13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */
+#define GPIO_PBC_PBC14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */
+#define GPIO_PBC_PBC15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */
+
+/****************** Bit definition for GPIO_LCKR register *******************/
+#define GPIO_PLOCK_PLOCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */
+#define GPIO_PLOCK_PLOCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */
+#define GPIO_PLOCK_PLOCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */
+#define GPIO_PLOCK_PLOCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */
+#define GPIO_PLOCK_PLOCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */
+#define GPIO_PLOCK_PLOCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */
+#define GPIO_PLOCK_PLOCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */
+#define GPIO_PLOCK_PLOCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */
+#define GPIO_PLOCK_PLOCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */
+#define GPIO_PLOCK_PLOCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */
+#define GPIO_PLOCK_PLOCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */
+#define GPIO_PLOCK_PLOCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */
+#define GPIO_PLOCK_PLOCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */
+#define GPIO_PLOCK_PLOCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */
+#define GPIO_PLOCK_PLOCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */
+#define GPIO_PLOCK_PLOCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */
+#define GPIO_PLOCK_PLOCKK ((uint32_t)0x00010000) /*!< Lock key */
+
+/****************** Bit definition for GPIO_AFL register *******************/
+#define GPIO_AFL_AFSEL0 ((uint32_t)0x0000000F) /*!< Port x AFL bit (0..3) */
+#define GPIO_AFL_AFSEL1 ((uint32_t)0x000000F0) /*!< Port x AFL bit (4..7) */
+#define GPIO_AFL_AFSEL2 ((uint32_t)0x00000F00) /*!< Port x AFL bit (8..11) */
+#define GPIO_AFL_AFSEL3 ((uint32_t)0x0000F000) /*!< Port x AFL bit (12..15) */
+#define GPIO_AFL_AFSEL4 ((uint32_t)0x000F0000) /*!< Port x AFL bit (16..19) */
+#define GPIO_AFL_AFSEL5 ((uint32_t)0x00F00000) /*!< Port x AFL bit (20..23) */
+#define GPIO_AFL_AFSEL6 ((uint32_t)0x0F000000) /*!< Port x AFL bit (24..27) */
+#define GPIO_AFL_AFSEL7 ((uint32_t)0xF0000000) /*!< Port x AFL bit (27..31) */
+
+/****************** Bit definition for GPIO_AFH register *******************/
+#define GPIO_AFH_AFSEL8 ((uint32_t)0x0000000F) /*!< Port x AFH bit (0..3) */
+#define GPIO_AFH_AFSEL9 ((uint32_t)0x000000F0) /*!< Port x AFH bit (4..7) */
+#define GPIO_AFH_AFSEL10 ((uint32_t)0x00000F00) /*!< Port x AFH bit (8..11) */
+#define GPIO_AFH_AFSEL11 ((uint32_t)0x0000F000) /*!< Port x AFH bit (12..15) */
+#define GPIO_AFH_AFSEL12 ((uint32_t)0x000F0000) /*!< Port x AFH bit (16..19) */
+#define GPIO_AFH_AFSEL13 ((uint32_t)0x00F00000) /*!< Port x AFH bit (20..23) */
+#define GPIO_AFH_AFSEL14 ((uint32_t)0x0F000000) /*!< Port x AFH bit (24..27) */
+#define GPIO_AFH_AFSEL15 ((uint32_t)0xF0000000) /*!< Port x AFH bit (27..31) */
+
+
+/******************* Bit definition for GPIO_DS register ******************/
+#define GPIO_DS0_Pos (0)
+#define GPIO_DS0_Msk (0x3 << GPIO_DS0_Pos) /*!< 0x00000003 */
+#define GPIO_DS0 GPIO_DS0_Msk
+#define GPIO_DS0_0 (0x0 << GPIO_DS0_Pos) /*!< 0x00000000 */
+#define GPIO_DS0_1 (0x1 << GPIO_DS0_Pos) /*!< 0x00000001 */
+#define GPIO_DS0_2 (0x2 << GPIO_DS0_Pos) /*!< 0x00000002 */
+#define GPIO_DS0_3 (0x3 << GPIO_DS0_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS1_Pos (2)
+#define GPIO_DS1_Msk (0x3 << GPIO_DS1_Pos) /*!< 0x00000003 */
+#define GPIO_DS1 GPIO_DS1_Msk
+#define GPIO_DS1_0 (0x0 << GPIO_DS1_Pos) /*!< 0x00000000 */
+#define GPIO_DS1_1 (0x1 << GPIO_DS1_Pos) /*!< 0x00000001 */
+#define GPIO_DS1_2 (0x2 << GPIO_DS1_Pos) /*!< 0x00000002 */
+#define GPIO_DS1_3 (0x3 << GPIO_DS1_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS2_Pos (4)
+#define GPIO_DS2_Msk (0x3 << GPIO_DS2_Pos) /*!< 0x00000003 */
+#define GPIO_DS2 GPIO_DS2_Msk
+#define GPIO_DS2_0 (0x0 << GPIO_DS2_Pos) /*!< 0x00000000 */
+#define GPIO_DS2_1 (0x1 << GPIO_DS2_Pos) /*!< 0x00000001 */
+#define GPIO_DS2_2 (0x2 << GPIO_DS2_Pos) /*!< 0x00000002 */
+#define GPIO_DS2_3 (0x3 << GPIO_DS2_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS3_Pos (6)
+#define GPIO_DS3_Msk (0x3 << GPIO_DS3_Pos) /*!< 0x00000003 */
+#define GPIO_DS3 GPIO_DS3_Msk
+#define GPIO_DS3_0 (0x0 << GPIO_DS3_Pos) /*!< 0x00000000 */
+#define GPIO_DS3_1 (0x1 << GPIO_DS3_Pos) /*!< 0x00000001 */
+#define GPIO_DS3_2 (0x2 << GPIO_DS3_Pos) /*!< 0x00000002 */
+#define GPIO_DS3_3 (0x3 << GPIO_DS3_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS4_Pos (8)
+#define GPIO_DS4_Msk (0x3 << GPIO_DS4_Pos) /*!< 0x00000003 */
+#define GPIO_DS4 GPIO_DS4_Msk
+#define GPIO_DS4_0 (0x0 << GPIO_DS4_Pos) /*!< 0x00000000 */
+#define GPIO_DS4_1 (0x1 << GPIO_DS4_Pos) /*!< 0x00000001 */
+#define GPIO_DS4_2 (0x2 << GPIO_DS4_Pos) /*!< 0x00000002 */
+#define GPIO_DS4_3 (0x3 << GPIO_DS4_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS5_Pos (10)
+#define GPIO_DS5_Msk (0x3 << GPIO_DS5_Pos) /*!< 0x00000003 */
+#define GPIO_DS5 GPIO_DS5_Msk
+#define GPIO_DS5_0 (0x0 << GPIO_DS5_Pos) /*!< 0x00000000 */
+#define GPIO_DS5_1 (0x1 << GPIO_DS5_Pos) /*!< 0x00000001 */
+#define GPIO_DS5_2 (0x2 << GPIO_DS5_Pos) /*!< 0x00000002 */
+#define GPIO_DS5_3 (0x3 << GPIO_DS5_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS6_Pos (12)
+#define GPIO_DS6_Msk (0x3 << GPIO_DS6_Pos) /*!< 0x00000003 */
+#define GPIO_DS6 GPIO_DS6_Msk
+#define GPIO_DS6_0 (0x0 << GPIO_DS6_Pos) /*!< 0x00000000 */
+#define GPIO_DS6_1 (0x1 << GPIO_DS6_Pos) /*!< 0x00000001 */
+#define GPIO_DS6_2 (0x2 << GPIO_DS6_Pos) /*!< 0x00000002 */
+#define GPIO_DS6_3 (0x3 << GPIO_DS6_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS7_Pos (14)
+#define GPIO_DS7_Msk (0x3 << GPIO_DS7_Pos) /*!< 0x00000003 */
+#define GPIO_DS7 GPIO_DS7_Msk
+#define GPIO_DS7_0 (0x0 << GPIO_DS7_Pos) /*!< 0x00000000 */
+#define GPIO_DS7_1 (0x1 << GPIO_DS7_Pos) /*!< 0x00000001 */
+#define GPIO_DS7_2 (0x2 << GPIO_DS7_Pos) /*!< 0x00000002 */
+#define GPIO_DS7_3 (0x3 << GPIO_DS7_Pos) /*!< 0x00000003 */
+
+
+#define GPIO_DS8_Pos (16)
+#define GPIO_DS8_Msk (0x3 << GPIO_DS8_Pos) /*!< 0x00000003 */
+#define GPIO_DS8 GPIO_DS8_Msk
+#define GPIO_DS8_0 (0x0 << GPIO_DS8_Pos) /*!< 0x00000000 */
+#define GPIO_DS8_1 (0x1 << GPIO_DS8_Pos) /*!< 0x00000001 */
+#define GPIO_DS8_2 (0x2 << GPIO_DS8_Pos) /*!< 0x00000002 */
+#define GPIO_DS8_3 (0x3 << GPIO_DS8_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS9_Pos (18)
+#define GPIO_DS9_Msk (0x3 << GPIO_DS9_Pos) /*!< 0x00000003 */
+#define GPIO_DS9 GPIO_DS9_Msk
+#define GPIO_DS9_0 (0x0 << GPIO_DS9_Pos) /*!< 0x00000000 */
+#define GPIO_DS9_1 (0x1 << GPIO_DS9_Pos) /*!< 0x00000001 */
+#define GPIO_DS9_2 (0x2 << GPIO_DS9_Pos) /*!< 0x00000002 */
+#define GPIO_DS9_3 (0x3 << GPIO_DS9_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS10_Pos (20)
+#define GPIO_DS10_Msk (0x3 << GPIO_DS10_Pos) /*!< 0x00000003 */
+#define GPIO_DS10 GPIO_DS10_Msk
+#define GPIO_DS10_0 (0x0 << GPIO_DS10_Pos) /*!< 0x00000000 */
+#define GPIO_DS10_1 (0x1 << GPIO_DS10_Pos) /*!< 0x00000001 */
+#define GPIO_DS10_2 (0x2 << GPIO_DS10_Pos) /*!< 0x00000002 */
+#define GPIO_DS10_3 (0x3 << GPIO_DS10_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS11_Pos (22)
+#define GPIO_DS11_Msk (0x3 << GPIO_DS11_Pos) /*!< 0x00000003 */
+#define GPIO_DS11 GPIO_DS11_Msk
+#define GPIO_DS11_0 (0x0 << GPIO_DS11_Pos) /*!< 0x00000000 */
+#define GPIO_DS11_1 (0x1 << GPIO_DS11_Pos) /*!< 0x00000001 */
+#define GPIO_DS11_2 (0x2 << GPIO_DS11_Pos) /*!< 0x00000002 */
+#define GPIO_DS11_3 (0x3 << GPIO_DS11_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS12_Pos (24)
+#define GPIO_DS12_Msk (0x3 << GPIO_DS12_Pos) /*!< 0x00000003 */
+#define GPIO_DS12 GPIO_DS12_Msk
+#define GPIO_DS12_0 (0x0 << GPIO_DS12_Pos) /*!< 0x00000000 */
+#define GPIO_DS12_1 (0x1 << GPIO_DS12_Pos) /*!< 0x00000001 */
+#define GPIO_DS12_2 (0x2 << GPIO_DS12_Pos) /*!< 0x00000002 */
+#define GPIO_DS12_3 (0x3 << GPIO_DS12_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS13_Pos (26)
+#define GPIO_DS13_Msk (0x3 << GPIO_DS13_Pos) /*!< 0x00000003 */
+#define GPIO_DS13 GPIO_DS13_Msk
+#define GPIO_DS13_0 (0x0 << GPIO_DS13_Pos) /*!< 0x00000000 */
+#define GPIO_DS13_1 (0x1 << GPIO_DS13_Pos) /*!< 0x00000001 */
+#define GPIO_DS13_2 (0x2 << GPIO_DS13_Pos) /*!< 0x00000002 */
+#define GPIO_DS13_3 (0x3 << GPIO_DS13_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS14_Pos (28)
+#define GPIO_DS14_Msk (0x3 << GPIO_DS14_Pos) /*!< 0x00000003 */
+#define GPIO_DS14 GPIO_DS14_Msk
+#define GPIO_DS14_0 (0x0 << GPIO_DS14_Pos) /*!< 0x00000000 */
+#define GPIO_DS14_1 (0x1 << GPIO_DS14_Pos) /*!< 0x00000001 */
+#define GPIO_DS14_2 (0x2 << GPIO_DS14_Pos) /*!< 0x00000002 */
+#define GPIO_DS14_3 (0x3 << GPIO_DS14_Pos) /*!< 0x00000003 */
+
+#define GPIO_DS15_Pos (30)
+#define GPIO_DS15_Msk (0x3 << GPIO_DS15_Pos) /*!< 0x00000003 */
+#define GPIO_DS15 GPIO_DS15_Msk
+#define GPIO_DS15_0 (0x0 << GPIO_DS15_Pos) /*!< 0x00000000 */
+#define GPIO_DS15_1 (0x1 << GPIO_DS15_Pos) /*!< 0x00000001 */
+#define GPIO_DS15_2 (0x2 << GPIO_DS15_Pos) /*!< 0x00000002 */
+#define GPIO_DS15_3 (0x3 << GPIO_DS15_Pos) /*!< 0x00000003 */
+
+/******************* Bit definition for GPIO_SR register *******************/
+#define GPIO_SR_SR0 ((uint16_t)0x0001) /*!< Slew rate bit 0 */
+#define GPIO_SR_SR1 ((uint16_t)0x0002) /*!< Slew rate bit 1 */
+#define GPIO_SR_SR2 ((uint16_t)0x0004) /*!< Slew rate bit 2 */
+#define GPIO_SR_SR3 ((uint16_t)0x0008) /*!< Slew rate bit 3 */
+#define GPIO_SR_SR4 ((uint16_t)0x0010) /*!< Slew rate bit 4 */
+#define GPIO_SR_SR5 ((uint16_t)0x0020) /*!< Slew rate bit 5 */
+#define GPIO_SR_SR6 ((uint16_t)0x0040) /*!< Slew rate bit 6 */
+#define GPIO_SR_SR7 ((uint16_t)0x0080) /*!< Slew rate bit 7 */
+#define GPIO_SR_SR8 ((uint16_t)0x0100) /*!< Slew rate bit 8 */
+#define GPIO_SR_SR9 ((uint16_t)0x0200) /*!< Slew rate bit 9 */
+#define GPIO_SR_SR10 ((uint16_t)0x0400) /*!< Slew rate bit 10 */
+#define GPIO_SR_SR11 ((uint16_t)0x0800) /*!< Slew rate bit 11 */
+#define GPIO_SR_SR12 ((uint16_t)0x1000) /*!< Slew rate bit 12 */
+#define GPIO_SR_SR13 ((uint16_t)0x2000) /*!< Slew rate bit 13 */
+#define GPIO_SR_SR14 ((uint16_t)0x4000) /*!< Slew rate bit 14 */
+#define GPIO_SR_SR15 ((uint16_t)0x8000) /*!< Slew rate bit 15 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for AFIO_RMP_CFG register *****************/
+#define AFIO_RMP_CFG_SPI1_NSS ((uint16_t)0x0800) /*!< AFIO_RMP_CFG bit 11 */
+#define AFIO_RMP_CFG_SPI2_NSS ((uint16_t)0x0400) /*!< AFIO_RMP_CFG bit 10 */
+#define AFIO_RMP_CFG_ADC_ETRI ((uint16_t)0x0200) /*!< AFIO_RMP_CFG bit 9 */
+#define AFIO_RMP_CFG_ADC_ETRR ((uint16_t)0x0100) /*!< AFIO_RMP_CFG bit 8 */
+#define AFIO_RMP_CFG_EXTI_ETRI ((uint16_t)0x00F0) /*!< AFIO_RMP_CFG bit (4..7) */
+#define AFIO_RMP_CFG_EXTI_ETRR ((uint16_t)0x000F) /*!< AFIO_RMP_CFG bit (0..3) */
+
+/***************** Bit definition for AFIO_EXTICR1 register *****************/
+#define AFIO_EXTI_CFG1_EXTI0 ((uint16_t)0x0003) /*!< EXTI 0 configuration */
+#define AFIO_EXTI_CFG1_EXTI1 ((uint16_t)0x0030) /*!< EXTI 1 configuration */
+#define AFIO_EXTI_CFG1_EXTI2 ((uint16_t)0x0300) /*!< EXTI 2 configuration */
+#define AFIO_EXTI_CFG1_EXTI3 ((uint16_t)0x3000) /*!< EXTI 3 configuration */
+
+/*!< EXTI0 configuration */
+#define AFIO_EXTI_CFG1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
+#define AFIO_EXTI_CFG1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
+#define AFIO_EXTI_CFG1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
+#define AFIO_EXTI_CFG1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
+
+/*!< EXTI1 configuration */
+#define AFIO_EXTI_CFG1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
+#define AFIO_EXTI_CFG1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
+#define AFIO_EXTI_CFG1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
+#define AFIO_EXTI_CFG1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
+
+/*!< EXTI2 configuration */
+#define AFIO_EXTI_CFG1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
+#define AFIO_EXTI_CFG1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
+#define AFIO_EXTI_CFG1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
+#define AFIO_EXTI_CFG1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
+
+/*!< EXTI3 configuration */
+#define AFIO_EXTI_CFG1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
+#define AFIO_EXTI_CFG1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
+#define AFIO_EXTI_CFG1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
+#define AFIO_EXTI_CFG1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
+
+/***************** Bit definition for AFIO_EXTICR2 register *****************/
+#define AFIO_EXTI_CFG2_EXTI4 ((uint16_t)0x0003) /*!< EXTI 4 configuration */
+#define AFIO_EXTI_CFG2_EXTI5 ((uint16_t)0x0030) /*!< EXTI 5 configuration */
+#define AFIO_EXTI_CFG2_EXTI6 ((uint16_t)0x0300) /*!< EXTI 6 configuration */
+#define AFIO_EXTI_CFG2_EXTI7 ((uint16_t)0x3000) /*!< EXTI 7 configuration */
+
+/*!< EXTI4 configuration */
+#define AFIO_EXTI_CFG2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
+#define AFIO_EXTI_CFG2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
+#define AFIO_EXTI_CFG2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
+#define AFIO_EXTI_CFG2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
+
+/*!< EXTI5 configuration */
+#define AFIO_EXTI_CFG2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
+#define AFIO_EXTI_CFG2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
+#define AFIO_EXTI_CFG2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
+#define AFIO_EXTI_CFG2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
+
+/*!< EXTI6 configuration */
+#define AFIO_EXTI_CFG2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
+#define AFIO_EXTI_CFG2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
+#define AFIO_EXTI_CFG2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
+#define AFIO_EXTI_CFG2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
+
+/*!< EXTI7 configuration */
+#define AFIO_EXTI_CFG2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
+#define AFIO_EXTI_CFG2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
+#define AFIO_EXTI_CFG2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
+#define AFIO_EXTI_CFG2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
+
+/***************** Bit definition for AFIO_EXTICR3 register *****************/
+#define AFIO_EXTI_CFG3_EXTI8 ((uint16_t)0x0003) /*!< EXTI 8 configuration */
+#define AFIO_EXTI_CFG3_EXTI9 ((uint16_t)0x0030) /*!< EXTI 9 configuration */
+#define AFIO_EXTI_CFG3_EXTI10 ((uint16_t)0x0300) /*!< EXTI 10 configuration */
+#define AFIO_EXTI_CFG3_EXTI11 ((uint16_t)0x3000) /*!< EXTI 11 configuration */
+
+/*!< EXTI8 configuration */
+#define AFIO_EXTI_CFG3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
+#define AFIO_EXTI_CFG3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
+#define AFIO_EXTI_CFG3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
+#define AFIO_EXTI_CFG3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
+
+/*!< EXTI9 configuration */
+#define AFIO_EXTI_CFG3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
+#define AFIO_EXTI_CFG3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
+#define AFIO_EXTI_CFG3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
+#define AFIO_EXTI_CFG3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
+
+/*!< EXTI10 configuration */
+#define AFIO_EXTI_CFG3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
+#define AFIO_EXTI_CFG3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
+#define AFIO_EXTI_CFG3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
+#define AFIO_EXTI_CFG3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
+
+/*!< EXTI11 configuration */
+#define AFIO_EXTI_CFG3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
+#define AFIO_EXTI_CFG3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
+#define AFIO_EXTI_CFG3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
+#define AFIO_EXTI_CFG3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
+
+/***************** Bit definition for AFIO_EXTICR4 register *****************/
+#define AFIO_EXTI_CFG4_EXTI12 ((uint16_t)0x0003) /*!< EXTI 12 configuration */
+#define AFIO_EXTI_CFG4_EXTI13 ((uint16_t)0x0030) /*!< EXTI 13 configuration */
+#define AFIO_EXTI_CFG4_EXTI14 ((uint16_t)0x0300) /*!< EXTI 14 configuration */
+#define AFIO_EXTI_CFG4_EXTI15 ((uint16_t)0x3000) /*!< EXTI 15 configuration */
+
+/*!< EXTI12 configuration */
+#define AFIO_EXTI_CFG4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
+#define AFIO_EXTI_CFG4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
+#define AFIO_EXTI_CFG4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
+#define AFIO_EXTI_CFG4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
+
+/*!< EXTI13 configuration */
+#define AFIO_EXTI_CFG4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
+#define AFIO_EXTI_CFG4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
+#define AFIO_EXTI_CFG4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
+#define AFIO_EXTI_CFG4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
+
+/*!< EXTI14 configuration */
+#define AFIO_EXTI_CFG4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
+#define AFIO_EXTI_CFG4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
+#define AFIO_EXTI_CFG4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
+#define AFIO_EXTI_CFG4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
+
+/*!< EXTI15 configuration */
+#define AFIO_EXTI_CFG4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
+#define AFIO_EXTI_CFG4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
+#define AFIO_EXTI_CFG4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
+#define AFIO_EXTI_CFG4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMASK_IMASK0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMASK_IMASK1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMASK_IMASK2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMASK_IMASK3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMASK_IMASK4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMASK_IMASK5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMASK_IMASK6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMASK_IMASK7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMASK_IMASK8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMASK_IMASK9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMASK_IMASK10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMASK_IMASK11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMASK_IMASK12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMASK_IMASK13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMASK_IMASK14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMASK_IMASK15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMASK_IMASK16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMASK_IMASK17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMASK_IMASK18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMASK_IMASK19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMASK_IMASK20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMASK_IMASK21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMASK_IMASK22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
+#define EXTI_IMASK_IMASK23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
+#define EXTI_IMASK_IMASK24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */
+#define EXTI_IMASK_IMASK25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
+#define EXTI_IMASK_IMASK26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
+#define EXTI_IMASK_IMASK27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMASK_EMASK0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMASK_EMASK1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMASK_EMASK2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMASK_EMASK3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMASK_EMASK4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMASK_EMASK5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMASK_EMASK6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMASK_EMASK7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMASK_EMASK8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMASK_EMASK9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMASK_EMASK10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMASK_EMASK11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMASK_EMASK12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMASK_EMASK13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMASK_EMASK14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMASK_EMASK15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMASK_EMASK16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMASK_EMASK17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMASK_EMASK18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+#define EXTI_EMASK_EMASK19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMASK_EMASK20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMASK_EMASK21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMASK_EMASK22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
+#define EXTI_EMASK_EMASK23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
+#define EXTI_EMASK_EMASK24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */
+#define EXTI_EMASK_EMASK25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
+#define EXTI_EMASK_EMASK26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
+#define EXTI_EMASK_EMASK27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
+
+
+/****************** Bit definition for EXTI_RT_CFG register *******************/
+#define EXTI_EMASK_RT_CFG_RT_CFG0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_EMASK_RT_CFG_RT_CFG1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_EMASK_RT_CFG_RT_CFG2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_EMASK_RT_CFG_RT_CFG3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_EMASK_RT_CFG_RT_CFG4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_EMASK_RT_CFG_RT_CFG5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_EMASK_RT_CFG_RT_CFG6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_EMASK_RT_CFG_RT_CFG7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_EMASK_RT_CFG_RT_CFG8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_EMASK_RT_CFG_RT_CFG9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_EMASK_RT_CFG_RT_CFG10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_EMASK_RT_CFG_RT_CFG11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_EMASK_RT_CFG_RT_CFG12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_EMASK_RT_CFG_RT_CFG13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_EMASK_RT_CFG_RT_CFG14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_EMASK_RT_CFG_RT_CFG15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_EMASK_RT_CFG_RT_CFG16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_EMASK_RT_CFG_RT_CFG17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_EMASK_RT_CFG_RT_CFG18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_EMASK_RT_CFG_RT_CFG19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_EMASK_RT_CFG_RT_CFG20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_EMASK_RT_CFG_RT_CFG21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_EMASK_RT_CFG_RT_CFG22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
+#define EXTI_EMASK_RT_CFG_RT_CFG23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
+#define EXTI_EMASK_RT_CFG_RT_CFG24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
+#define EXTI_EMASK_RT_CFG_RT_CFG25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
+#define EXTI_EMASK_RT_CFG_RT_CFG26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
+#define EXTI_EMASK_RT_CFG_RT_CFG27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
+
+
+
+/****************** Bit definition for EXTI_FT_CFG register *******************/
+#define EXTI_EMASK_FT_CFG_FT_CFG0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_EMASK_FT_CFG_FT_CFG1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_EMASK_FT_CFG_FT_CFG2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_EMASK_FT_CFG_FT_CFG3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_EMASK_FT_CFG_FT_CFG4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_EMASK_FT_CFG_FT_CFG5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_EMASK_FT_CFG_FT_CFG6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_EMASK_FT_CFG_FT_CFG7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_EMASK_FT_CFG_FT_CFG8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_EMASK_FT_CFG_FT_CFG9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_EMASK_FT_CFG_FT_CFG10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_EMASK_FT_CFG_FT_CFG11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_EMASK_FT_CFG_FT_CFG12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_EMASK_FT_CFG_FT_CFG13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_EMASK_FT_CFG_FT_CFG14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_EMASK_FT_CFG_FT_CFG15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_EMASK_FT_CFG_FT_CFG16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_EMASK_FT_CFG_FT_CFG17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_EMASK_FT_CFG_FT_CFG18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_EMASK_FT_CFG_FT_CFG19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_EMASK_FT_CFG_FT_CFG20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_EMASK_FT_CFG_FT_CFG21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_EMASK_FT_CFG_FT_CFG22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
+#define EXTI_EMASK_FT_CFG_FT_CFG23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
+#define EXTI_EMASK_FT_CFG_FT_CFG24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
+#define EXTI_EMASK_FT_CFG_FT_CFG25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
+#define EXTI_EMASK_FT_CFG_FT_CFG26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
+#define EXTI_EMASK_FT_CFG_FT_CFG27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
+
+/****************** Bit definition for EXTI_SWIE register ******************/
+#define EXTI_SWIE_SWIE0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIE_SWIE1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIE_SWIE2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIE_SWIE3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIE_SWIE4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIE_SWIE5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIE_SWIE6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIE_SWIE7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIE_SWIE8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIE_SWIE9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIE_SWIE10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIE_SWIE11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIE_SWIE12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIE_SWIE13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIE_SWIE14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIE_SWIE15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIE_SWIE16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIE_SWIE17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIE_SWIE18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
+#define EXTI_SWIE_SWIE19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIE_SWIE20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIE_SWIE21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIE_SWIE22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
+#define EXTI_SWIE_SWIE23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
+#define EXTI_SWIE_SWIE24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
+#define EXTI_SWIE_SWIE25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
+#define EXTI_SWIE_SWIE26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
+#define EXTI_SWIE_SWIE27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
+
+/******************* Bit definition for EXTI_PEND register ********************/
+#define EXTI_PEND_PEND0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
+#define EXTI_PEND_PEND1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
+#define EXTI_PEND_PEND2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
+#define EXTI_PEND_PEND3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
+#define EXTI_PEND_PEND4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
+#define EXTI_PEND_PEND5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
+#define EXTI_PEND_PEND6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
+#define EXTI_PEND_PEND7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
+#define EXTI_PEND_PEND8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
+#define EXTI_PEND_PEND9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
+#define EXTI_PEND_PEND10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
+#define EXTI_PEND_PEND11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
+#define EXTI_PEND_PEND12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
+#define EXTI_PEND_PEND13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
+#define EXTI_PEND_PEND14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
+#define EXTI_PEND_PEND15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
+#define EXTI_PEND_PEND16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
+#define EXTI_PEND_PEND17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
+#define EXTI_PEND_PEND18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
+#define EXTI_PEND_PEND19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PEND_PEND20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PEND_PEND21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PEND_PEND22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
+#define EXTI_PEND_PEND23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
+#define EXTI_PEND_PEND24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
+#define EXTI_PEND_PEND25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
+#define EXTI_PEND_PEND26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
+#define EXTI_PEND_PEND27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
+
+
+/******************************************************************************/
+/* */
+/* LCD Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for LCD_CTRL register *******************/
+#define LCD_CTRL_BUFEN_Msk ((uint32_t)0x00000100)
+#define LCD_CTRL_BUFEN_Pos (8U)
+#define LCD_CTRL_BUFEN (LCD_CTRL_BUFEN_Msk) /*!< High driving capacity buffer enable bit*/
+
+#define LCD_CTRL_MUXSEG_Msk ((uint32_t)0x00000080)
+#define LCD_CTRL_MUXSEG_Pos (7U)
+#define LCD_CTRL_MUXSEG (LCD_CTRL_MUXSEG_Msk) /*!< Mux segment enable bit*/
+
+#define LCD_CTRL_BIAS_Msk ((uint32_t)0x00000060)
+#define LCD_CTRL_BIAS_Pos (5U)
+#define LCD_CTRL_BIAS (LCD_CTRL_BIAS_Msk)
+#define LCD_CTRL_BIAS_0 (0x1UL << LCD_CTRL_BIAS_Pos) /*!< Bias selector bit*/
+#define LCD_CTRL_BIAS_1 (0x2UL << LCD_CTRL_BIAS_Pos)
+
+#define LCD_CTRL_DUTY_Msk ((uint32_t)0x0000001C)
+#define LCD_CTRL_DUTY_Pos (2U)
+#define LCD_CTRL_DUTY (LCD_CTRL_DUTY_Msk) /*!< Duty selection bit*/
+#define LCD_CTRL_DUTY_0 (0x1UL << LCD_CTRL_DUTY_Pos)
+#define LCD_CTRL_DUTY_1 (0x2UL << LCD_CTRL_DUTY_Pos)
+#define LCD_CTRL_DUTY_2 (0x4UL << LCD_CTRL_DUTY_Pos)
+
+#define LCD_CTRL_VSEL_Msk ((uint32_t)0x00000002)
+#define LCD_CTRL_VSEL_Pos (1U)
+#define LCD_CTRL_VSEL (LCD_CTRL_VSEL_Msk) /*!< Voltage source selection bit*/
+
+#define LCD_CTRL_LCDEN_Msk ((uint32_t)0x00000001)
+#define LCD_CTRL_LCDEN_Pos (0U)
+#define LCD_CTRL_LCDEN (LCD_CTRL_LCDEN_Msk) /*!< LCD controller enable bit*/
+
+/******************* Bit definition for LCD_FCTRL register *******************/
+#define LCD_FCTRL_PRES_Msk ((uint32_t)0x03C00000)
+#define LCD_FCTRL_PRES_Pos (22U)
+#define LCD_FCTRL_PRES (LCD_FCTRL_PRES_Msk) /*!< 16-bit prescaler bit*/
+#define LCD_FCTRL_PRES_0 (0x1UL << LCD_FCTRL_PRES_Pos)
+#define LCD_FCTRL_PRES_1 (0x2UL << LCD_FCTRL_PRES_Pos)
+#define LCD_FCTRL_PRES_2 (0x4UL << LCD_FCTRL_PRES_Pos)
+#define LCD_FCTRL_PRES_3 (0x8UL << LCD_FCTRL_PRES_Pos)
+
+#define LCD_FCTRL_DIV_Msk ((uint32_t)0x003C0000)
+#define LCD_FCTRL_DIV_Pos (18U)
+#define LCD_FCTRL_DIV (LCD_FCTRL_DIV_Msk) /*!< DIV clock divider bit*/
+#define LCD_FCTRL_DIV_0 (0x1UL << LCD_FCTRL_DIV_Pos)
+#define LCD_FCTRL_DIV_1 (0x2UL << LCD_FCTRL_DIV_Pos)
+#define LCD_FCTRL_DIV_2 (0x4UL << LCD_FCTRL_DIV_Pos)
+#define LCD_FCTRL_DIV_3 (0x8UL << LCD_FCTRL_DIV_Pos)
+
+#define LCD_FCTRL_BLINK_Msk ((uint32_t)0x00030000)
+#define LCD_FCTRL_BLINK_Pos (16U)
+#define LCD_FCTRL_BLINK (LCD_FCTRL_BLINK_Msk) /*!< Blink mode selection bit*/
+#define LCD_FCTRL_BLINK_0 (0x1UL << LCD_FCTRL_BLINK_Pos)
+#define LCD_FCTRL_BLINK_1 (0x2UL << LCD_FCTRL_BLINK_Pos)
+
+#define LCD_FCTRL_BLINKF_Msk ((uint32_t)0x0000E000)
+#define LCD_FCTRL_BLINKF_Pos (13U)
+#define LCD_FCTRL_BLINKF (LCD_FCTRL_BLINKF_Msk) /*!< Blink frequency selection bit*/
+#define LCD_FCTRL_BLINKF_0 (0x1UL << LCD_FCTRL_BLINKF_Pos)
+#define LCD_FCTRL_BLINKF_1 (0x2UL << LCD_FCTRL_BLINKF_Pos)
+#define LCD_FCTRL_BLINKF_2 (0x4UL << LCD_FCTRL_BLINKF_Pos)
+
+#define LCD_FCTRL_CONTRAST_Msk ((uint32_t)0x00001C00)
+#define LCD_FCTRL_CONTRAST_Pos (10U)
+#define LCD_FCTRL_CONTRAST (LCD_FCTRL_CONTRAST_Msk) /*!< Contrast Control bit*/
+#define LCD_FCTRL_CONTRAST_0 (0x1UL << LCD_FCTRL_CONTRAST_Pos)
+#define LCD_FCTRL_CONTRAST_1 (0x2UL << LCD_FCTRL_CONTRAST_Pos)
+#define LCD_FCTRL_CONTRAST_2 (0x4UL << LCD_FCTRL_CONTRAST_Pos)
+
+#define LCD_FCTRL_DEAD_Msk ((uint32_t)0x00000380)
+#define LCD_FCTRL_DEAD_Pos (7U)
+#define LCD_FCTRL_DEAD (LCD_FCTRL_DEAD_Msk) /*!< Dead time duration bit*/
+#define LCD_FCTRL_DEAD_0 (0x1UL << LCD_FCTRL_DEAD_Pos)
+#define LCD_FCTRL_DEAD_1 (0x2UL << LCD_FCTRL_DEAD_Pos)
+#define LCD_FCTRL_DEAD_2 (0x4UL << LCD_FCTRL_DEAD_Pos)
+
+#define LCD_FCTRL_PULSEON_Msk ((uint32_t)0x00000070)
+#define LCD_FCTRL_PULSEON_Pos (4U)
+#define LCD_FCTRL_PULSEON (LCD_FCTRL_PULSEON_Msk) /*!< Pulse on duration bit*/
+#define LCD_FCTRL_PULSEON_0 (0x1UL << LCD_FCTRL_PULSEON_Pos)
+#define LCD_FCTRL_PULSEON_1 (0x2UL << LCD_FCTRL_PULSEON_Pos)
+#define LCD_FCTRL_PULSEON_2 (0x4UL << LCD_FCTRL_PULSEON_Pos)
+
+#define LCD_FCTRL_UDDIE_Msk ((uint32_t)0x00000008)
+#define LCD_FCTRL_UDDIE_Pos (3U)
+#define LCD_FCTRL_UDDIE (LCD_FCTRL_UDDIE_Msk) /*!< Update display done interrupt enable bit*/
+
+#define LCD_FCTRL_SOFIE_Msk ((uint32_t)0x00000002)
+#define LCD_FCTRL_SOFIE_Pos (1U)
+#define LCD_FCTRL_SOFIE (LCD_FCTRL_SOFIE_Msk) /*!< Start of frame interrupt enable bit*/
+
+#define LCD_FCTRL_HDEN_Msk ((uint32_t)0x00000001)
+#define LCD_FCTRL_HDEN_Pos (0U)
+#define LCD_FCTRL_HDEN (LCD_FCTRL_HDEN_Msk) /*!< High drive enable bit*/
+
+/******************* Bit definition for LCD_STS register *******************/
+#define LCD_STS_FCRSF_Msk ((uint32_t)0x00000020)
+#define LCD_STS_FCRSF_Pos (5U)
+#define LCD_STS_FCRSF (LCD_STS_FCRSF_Msk) /*!< LCD Frame Control Register Synchronization flag bit*/
+
+#define LCD_STS_RDY_Msk ((uint32_t)0x00000010)
+#define LCD_STS_RDY_Pos (4U)
+#define LCD_STS_RDY (LCD_STS_RDY_Msk) /*!< VLCD Ready Flag bit*/
+
+#define LCD_STS_UDD_Msk ((uint32_t)0x00000008)
+#define LCD_STS_UDD_Pos (3U)
+#define LCD_STS_UDD (LCD_STS_UDD_Msk) /*!< Update Display Done bit*/
+
+#define LCD_STS_UDR_Msk ((uint32_t)0x00000004)
+#define LCD_STS_UDR_Pos (2U)
+#define LCD_STS_UDR (LCD_STS_UDR_Msk) /*!< Update Display Request bit*/
+
+#define LCD_STS_SOF_Msk ((uint32_t)0x00000002)
+#define LCD_STS_SOF_Pos (1U)
+#define LCD_STS_SOF (LCD_STS_SOF_Msk) /*!< Start of Frame flag*/
+
+#define LCD_STS_ENSTS_Msk ((uint32_t)0x00000001)
+#define LCD_STS_ENSTS_Pos (0U)
+#define LCD_STS_ENSTS (LCD_STS_ENSTS_Msk) /*!< LCD state bit*/
+
+/******************* Bit definition for LCD_CLR register *******************/
+#define LCD_CLR_UDDCLR_Msk ((uint32_t)0x00000008) /*!< Update display done clear bit*/
+#define LCD_CLR_UDDCLR_Pos (3U)
+#define LCD_CLR_UDDCLR (LCD_CLR_UDDCLR_Msk)
+
+#define LCD_CLR_SOFCLR_Msk ((uint32_t)0x00000002) /*!FLASH
+
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ /* section information for finsh shell */
+ . = ALIGN(4);
+ __fsymtab_start = .;
+ KEEP(*(FSymTab))
+ __fsymtab_end = .;
+
+ . = ALIGN(4);
+ __vsymtab_start = .;
+ KEEP(*(VSymTab))
+ __vsymtab_end = .;
+
+ /* section information for initial. */
+ . = ALIGN(4);
+ __rt_init_start = .;
+ KEEP(*(SORT(.rti_fn*)))
+ __rt_init_end = .;
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data goes into FLASH */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >FLASH
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH
+
+ /* used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(4);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(4);
+ } >RAM
+
+
+
+ /* Remove information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/startup/startup_n32l43x.s b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/startup/startup_n32l43x.s
new file mode 100644
index 0000000000..cee6fb09b2
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/startup/startup_n32l43x.s
@@ -0,0 +1,373 @@
+; ****************************************************************************
+; Copyright (c) 2019, Nations Technologies Inc.
+;
+; All rights reserved.
+; ****************************************************************************
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; - Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the disclaimer below.
+;
+; Nations' name may not be used to endorse or promote products derived from
+; this software without specific prior written permission.
+;
+; DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+; DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+; OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; ****************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00001500
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000300
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; RTC Tamper interrupt or Timestamp through EXTI line 19 interrupt
+ DCD RTC_WKUP_IRQHandler ; RTC_WKUP
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA_Channel1_IRQHandler ; DMA Channel 1
+ DCD DMA_Channel2_IRQHandler ; DMA Channel 2
+ DCD DMA_Channel3_IRQHandler ; DMA Channel 3
+ DCD DMA_Channel4_IRQHandler ; DMA Channel 4
+ DCD DMA_Channel5_IRQHandler ; DMA Channel 5
+ DCD DMA_Channel6_IRQHandler ; DMA Channel 6
+ DCD DMA_Channel7_IRQHandler ; DMA Channel 7
+ DCD DMA_Channel8_IRQHandler ; DMA Channel 8
+ DCD ADC_IRQHandler ; ADC
+ DCD USB_HP_IRQHandler ; USB High Priority
+ DCD USB_LP_IRQHandler ; USB Low Priority
+ DCD COMP_1_2_IRQHandler ; COMP1 & COMP2 through EXTI line 21/22
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
+ DCD TIM8_BRK_IRQHandler ; TIM8 Break
+ DCD TIM8_UP_IRQHandler ; TIM8 Update
+ DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD LPUART_IRQHandler ; LPUART
+ DCD TIM5_IRQHandler ; TIM5
+ DCD TIM6_IRQHandler ; TIM6
+ DCD TIM7_IRQHandler ; TIM7
+ DCD CAN_TX_IRQHandler ; CAN TX
+ DCD CAN_RX0_IRQHandler ; CAN RX0
+ DCD CAN_RX1_IRQHandler ; CAN RX1
+ DCD CAN_SCE_IRQHandler ; CAN SCE
+ DCD LPUART_WKUP_IRQHandler ; LPUART_WKUP
+ DCD LPTIM_WKUP_IRQHandler ; LPTIM_WKUP
+ DCD LCD_IRQHandler ; LCD
+ DCD SAC_IRQHandler ; SAC
+ DCD MMU_IRQHandler ; MMU
+ DCD TSC_IRQHandler ; TSC
+ DCD RAMC_PERR_IRQHandler ; RAMC ERR
+ DCD TIM9_IRQHandler ; TIM9
+ DCD UCDR_IRQHandler ; UCDR ERR
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ IMPORT SystemInit
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_IRQHandler [WEAK]
+ EXPORT TAMPER_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA_Channel1_IRQHandler [WEAK]
+ EXPORT DMA_Channel2_IRQHandler [WEAK]
+ EXPORT DMA_Channel3_IRQHandler [WEAK]
+ EXPORT DMA_Channel4_IRQHandler [WEAK]
+ EXPORT DMA_Channel5_IRQHandler [WEAK]
+ EXPORT DMA_Channel6_IRQHandler [WEAK]
+ EXPORT DMA_Channel7_IRQHandler [WEAK]
+ EXPORT DMA_Channel8_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT USB_HP_IRQHandler [WEAK]
+ EXPORT USB_LP_IRQHandler [WEAK]
+ EXPORT COMP_1_2_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTCAlarm_IRQHandler [WEAK]
+ EXPORT USBWakeUp_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_IRQHandler [WEAK]
+ EXPORT TIM8_UP_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT LPUART_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT TIM6_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT CAN_TX_IRQHandler [WEAK]
+ EXPORT CAN_RX0_IRQHandler [WEAK]
+ EXPORT CAN_RX1_IRQHandler [WEAK]
+ EXPORT CAN_SCE_IRQHandler [WEAK]
+ EXPORT LPUART_WKUP_IRQHandler [WEAK]
+ EXPORT LPTIM_WKUP_IRQHandler [WEAK]
+ EXPORT LCD_IRQHandler [WEAK]
+ EXPORT SAC_IRQHandler [WEAK]
+ EXPORT MMU_IRQHandler [WEAK]
+ EXPORT TSC_IRQHandler [WEAK]
+ EXPORT RAMC_PERR_IRQHandler [WEAK]
+ EXPORT TIM9_IRQHandler [WEAK]
+ EXPORT UCDR_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA_Channel1_IRQHandler
+DMA_Channel2_IRQHandler
+DMA_Channel3_IRQHandler
+DMA_Channel4_IRQHandler
+DMA_Channel5_IRQHandler
+DMA_Channel6_IRQHandler
+DMA_Channel7_IRQHandler
+DMA_Channel8_IRQHandler
+ADC_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+COMP_1_2_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+USBWakeUp_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+LPUART_IRQHandler
+TIM5_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+CAN_TX_IRQHandler
+CAN_RX0_IRQHandler
+CAN_RX1_IRQHandler
+CAN_SCE_IRQHandler
+LPUART_WKUP_IRQHandler
+LPTIM_WKUP_IRQHandler
+LCD_IRQHandler
+SAC_IRQHandler
+MMU_IRQHandler
+TSC_IRQHandler
+RAMC_PERR_IRQHandler
+TIM9_IRQHandler
+UCDR_IRQHandler
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/startup/startup_n32l43x_EWARM.s b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/startup/startup_n32l43x_EWARM.s
new file mode 100644
index 0000000000..e9a39bed20
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/startup/startup_n32l43x_EWARM.s
@@ -0,0 +1,523 @@
+; ****************************************************************************
+; Copyright (c) 2019, Nations Technologies Inc.
+;
+; All rights reserved.
+; ****************************************************************************
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; - Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the disclaimer below.
+;
+; Nations name may not be used to endorse or promote products derived from
+; this software without specific prior written permission.
+;
+; DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+; DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+; OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; ****************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; RTC Tamper interrupt or Timestamp through EXTI line 19 interrupt
+ DCD RTC_WKUP_IRQHandler ; RTC_WKUP
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD DMA_Channel8_IRQHandler ; DMA Channel 8
+ DCD ADC_IRQHandler ; ADC
+ DCD USB_HP_IRQHandler ; USB High Priority
+ DCD USB_LP_IRQHandler ; USB Low Priority
+ DCD COMP_1_2_IRQHandler ; COMP1 & COMP2 through EXTI line 21/22
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
+ DCD TIM8_BRK_IRQHandler ; TIM8 Break
+ DCD TIM8_UP_IRQHandler ; TIM8 Update
+ DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD LPUART_IRQHandler ; LPUART
+ DCD TIM5_IRQHandler ; TIM5
+ DCD TIM6_IRQHandler ; TIM6
+ DCD TIM7_IRQHandler ; TIM7
+ DCD CAN_TX_IRQHandler ; CAN TX
+ DCD CAN_RX0_IRQHandler ; CAN RX0
+ DCD CAN_RX1_IRQHandler ; CAN RX1
+ DCD CAN_SCE_IRQHandler ; CAN SCE
+ DCD LPUART_WKUP_IRQHandler ; LPUART_WKUP
+ DCD LPTIM_WKUP_IRQHandler ; LPTIM_WKUP
+ DCD LCD_IRQHandler ; LCD
+ DCD SAC_IRQHandler ; SAC
+ DCD MMU_IRQHandler ; MMU
+ DCD TSC_IRQHandler ; TSC
+ DCD RAMC_PERR_IRQHandler ; RAMC ERR
+ DCD TIM9_IRQHandler ; TIM9
+ DCD UCDR_IRQHandler ; UCDR ERR
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+ PUBWEAK TAMPER_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TAMPER_IRQHandler
+ B TAMPER_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel1_IRQHandler
+ B DMA_Channel1_IRQHandler
+
+ PUBWEAK DMA_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel2_IRQHandler
+ B DMA_Channel2_IRQHandler
+
+ PUBWEAK DMA_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel3_IRQHandler
+ B DMA_Channel3_IRQHandler
+
+ PUBWEAK DMA_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel4_IRQHandler
+ B DMA_Channel4_IRQHandler
+
+ PUBWEAK DMA_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel5_IRQHandler
+ B DMA_Channel5_IRQHandler
+
+ PUBWEAK DMA_Channel6_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel6_IRQHandler
+ B DMA_Channel6_IRQHandler
+
+ PUBWEAK DMA_Channel7_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel7_IRQHandler
+ B DMA_Channel7_IRQHandler
+
+ PUBWEAK DMA_Channel8_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel8_IRQHandler
+ B DMA_Channel8_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK USB_HP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USB_HP_IRQHandler
+ B USB_HP_IRQHandler
+
+ PUBWEAK USB_LP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USB_LP_IRQHandler
+ B USB_LP_IRQHandler
+
+ PUBWEAK COMP_1_2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+COMP_1_2_IRQHandler
+ B COMP_1_2_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTCAlarm_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTCAlarm_IRQHandler
+ B RTCAlarm_IRQHandler
+
+ PUBWEAK USBWakeUp_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USBWakeUp_IRQHandler
+ B USBWakeUp_IRQHandler
+
+ PUBWEAK TIM8_BRK_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_BRK_IRQHandler
+ B TIM8_BRK_IRQHandler
+
+ PUBWEAK TIM8_UP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_UP_IRQHandler
+ B TIM8_UP_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_TRG_COM_IRQHandler
+ B TIM8_TRG_COM_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK LPUART_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+LPUART_IRQHandler
+ B LPUART_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK TIM6_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM6_IRQHandler
+ B TIM6_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK CAN_TX_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN_TX_IRQHandler
+ B CAN_TX_IRQHandler
+
+ PUBWEAK CAN_RX0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN_RX0_IRQHandler
+ B CAN_RX0_IRQHandler
+
+ PUBWEAK CAN_RX1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN_RX1_IRQHandler
+ B CAN_RX1_IRQHandler
+
+ PUBWEAK CAN_SCE_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN_SCE_IRQHandler
+ B CAN_SCE_IRQHandler
+
+ PUBWEAK LPUART_WKUP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+LPUART_WKUP_IRQHandler
+ B LPUART_WKUP_IRQHandler
+
+ PUBWEAK LPTIM_WKUP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+LPTIM_WKUP_IRQHandler
+ B LPTIM_WKUP_IRQHandler
+
+ PUBWEAK LCD_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+LCD_IRQHandler
+ B LCD_IRQHandler
+
+ PUBWEAK SAC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SAC_IRQHandler
+ B SAC_IRQHandler
+
+ PUBWEAK MMU_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MMU_IRQHandler
+ B MMU_IRQHandler
+
+ PUBWEAK TSC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TSC_IRQHandler
+ B TSC_IRQHandler
+
+ PUBWEAK RAMC_PERR_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RAMC_PERR_IRQHandler
+ B RAMC_PERR_IRQHandler
+
+ PUBWEAK TIM9_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM9_IRQHandler
+ B TIM9_IRQHandler
+
+ PUBWEAK UCDR_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UCDR_IRQHandler
+ B UCDR_IRQHandler
+
+
+ END
+
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/startup/startup_n32l43x_gcc.s b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/startup/startup_n32l43x_gcc.s
new file mode 100644
index 0000000000..5eb4eef139
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/startup/startup_n32l43x_gcc.s
@@ -0,0 +1,450 @@
+/**
+ ****************************************************************************
+ Copyright (c) 2019, Nations Technologies Inc.
+
+ All rights reserved.
+ ****************************************************************************
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ - Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the disclaimer below.
+
+ Nations' name may not be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+ DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************
+ **/
+
+/**
+******************************************************************************
+* @file startup_n32l43x_gcc.s
+******************************************************************************
+*/
+
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl entry
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_IRQHandler /* PVD through EXTI Line detection */
+ .word TAMPER_IRQHandler /* Tamper */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA_Channel1_IRQHandler /* DMA1 Channel 1 */
+ .word DMA_Channel2_IRQHandler /* DMA1 Channel 2 */
+ .word DMA_Channel3_IRQHandler /* DMA1 Channel 3 */
+ .word DMA_Channel4_IRQHandler /* DMA1 Channel 4 */
+ .word DMA_Channel5_IRQHandler /* DMA1 Channel 5 */
+ .word DMA_Channel6_IRQHandler /* DMA1 Channel 6 */
+ .word DMA_Channel7_IRQHandler /* DMA1 Channel 7 */
+ .word DMA_Channel8_IRQHandler /* DMA1 Channel 8 */
+ .word ADC_IRQHandler /* ADC */
+ .word USB_HP_IRQHandler /* USB High Priority */
+ .word USB_LP_IRQHandler /* USB Low Priority */
+ .word COMP_1_2_IRQHandler /* COMP1 & COMP2 through EXTI line 21/22 */
+ .word EXTI9_5_IRQHandler /* EXTI Line 9..5 */
+ .word TIM1_BRK_IRQHandler /* TIM1 Break */
+ .word TIM1_UP_IRQHandler /* TIM1 Update */
+ .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */
+ .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
+ .word USBWakeUp_IRQHandler /* USB Wakeup from suspend */
+ .word TIM8_BRK_IRQHandler /* TIM8 Break */
+ .word TIM8_UP_IRQHandler /* TIM8 Update */
+ .word TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word LPUART_IRQHandler /* LPUART */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word TIM6_IRQHandler /* TIM6 */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word CAN_TX_IRQHandler /* CAN TX */
+ .word CAN_RX0_IRQHandler /* CAN RX0 */
+ .word CAN_RX1_IRQHandler /* CAN RX1 */
+ .word CAN_SCE_IRQHandler /* CAN SCE */
+ .word LPUART_WKUP_IRQHandler /* LPUART_WKUP */
+ .word LPTIM_WKUP_IRQHandler /* LPTIM_WKUP */
+ .word LCD_IRQHandler /* LCD */
+ .word SAC_IRQHandler /* SAC */
+ .word MMU_IRQHandler /* MMU */
+ .word TSC_IRQHandler /* TSC */
+ .word RAMC_PERR_IRQHandler /* RAMC ERR */
+ .word TIM9_IRQHandler /* TIM9 */
+ .word UCDR_IRQHandler /* UCDR ERR */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA_Channel1_IRQHandler
+ .thumb_set DMA_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA_Channel2_IRQHandler
+ .thumb_set DMA_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA_Channel3_IRQHandler
+ .thumb_set DMA_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA_Channel4_IRQHandler
+ .thumb_set DMA_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA_Channel5_IRQHandler
+ .thumb_set DMA_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA_Channel6_IRQHandler
+ .thumb_set DMA_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA_Channel7_IRQHandler
+ .thumb_set DMA_Channel7_IRQHandler,Default_Handler
+
+ .weak DMA_Channel8_IRQHandler
+ .thumb_set DMA_Channel8_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak USB_HP_IRQHandler
+ .thumb_set USB_HP_IRQHandler,Default_Handler
+
+ .weak USB_LP_IRQHandler
+ .thumb_set USB_LP_IRQHandler,Default_Handler
+
+ .weak COMP_1_2_IRQHandler
+ .thumb_set COMP_1_2_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTCAlarm_IRQHandler
+ .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_IRQHandler
+ .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_IRQHandler
+ .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_IRQHandler
+ .thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_IRQHandler
+ .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak LPUART_IRQHandler
+ .thumb_set LPUART_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak TIM6_IRQHandler
+ .thumb_set TIM6_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak CAN_TX_IRQHandler
+ .thumb_set CAN_TX_IRQHandler,Default_Handler
+
+ .weak CAN_RX0_IRQHandler
+ .thumb_set CAN_RX0_IRQHandler,Default_Handler
+
+ .weak CAN_RX1_IRQHandler
+ .thumb_set CAN_RX1_IRQHandler,Default_Handler
+
+ .weak CAN_SCE_IRQHandler
+ .thumb_set CAN_SCE_IRQHandler,Default_Handler
+
+ .weak LPUART_WKUP_IRQHandler
+ .thumb_set LPUART_WKUP_IRQHandler,Default_Handler
+
+ .weak LPTIM_WKUP_IRQHandler
+ .thumb_set LPTIM_WKUP_IRQHandler,Default_Handler
+
+ .weak LCD_IRQHandler
+ .thumb_set LCD_IRQHandler,Default_Handler
+
+ .weak SAC_IRQHandler
+ .thumb_set SAC_IRQHandler,Default_Handler
+
+ .weak MMU_IRQHandler
+ .thumb_set MMU_IRQHandler,Default_Handler
+
+ .weak TSC_IRQHandler
+ .thumb_set TSC_IRQHandler,Default_Handler
+
+ .weak RAMC_PERR_IRQHandler
+ .thumb_set RAMC_PERR_IRQHandler,Default_Handler
+
+ .weak TIM9_IRQHandler
+ .thumb_set TIM9_IRQHandler,Default_Handler
+
+ .weak UCDR_IRQHandler
+ .thumb_set UCDR_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/system_n32l43x.c b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/system_n32l43x.c
new file mode 100644
index 0000000000..04376bf7d9
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/system_n32l43x.c
@@ -0,0 +1,615 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file system_n32l43x.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l43x.h"
+
+/* Uncomment the line corresponding to the desired System clock (SYSCLK)
+ frequency (after reset the HSI is used as SYSCLK source)
+
+ IMPORTANT NOTE:
+ ==============
+ 1. After each device reset the HSI is used as System clock source.
+
+ 2. Please make sure that the selected System clock doesn't exceed your
+ device's maximum frequency.
+
+ 3. If none of the define below is enabled, the HSI is used as System clock
+ source.
+
+ 4. The System clock configuration functions provided within this file assume
+ that:
+ - For Low, Medium and High density Value line devices an external 8MHz
+ crystal is used to drive the System clock.
+ - For Low, Medium and High density devices an external 8MHz crystal is
+ used to drive the System clock.
+ - For Connectivity line devices an external 25MHz crystal is used to
+ drive the System clock. If you are using different crystal you have to adapt
+ those functions accordingly.
+ */
+
+#define SYSCLK_USE_MSI 0
+#define SYSCLK_USE_HSI 1
+#define SYSCLK_USE_HSE 2
+#define SYSCLK_USE_HSI_PLL 3
+#define SYSCLK_USE_HSE_PLL 4
+
+#ifndef SYSCLK_FREQ
+#define SYSCLK_FREQ 108000000
+#endif
+
+/*
+* SYSCLK_SRC *
+** SYSCLK_USE_MSI **
+** SYSCLK_USE_HSI **
+** SYSCLK_USE_HSE **
+** SYSCLK_USE_HSI_PLL **
+** SYSCLK_USE_HSE_PLL **
+*/
+#ifndef SYSCLK_SRC
+#define SYSCLK_SRC SYSCLK_USE_HSE_PLL
+#endif
+
+#define PLL_DIV2_DISABLE 0x00000000
+#define PLL_DIV2_ENABLE 0x00000002
+
+#if SYSCLK_SRC == SYSCLK_USE_MSI
+
+ #if (SYSCLK_FREQ == MSI_VALUE_L0)
+ #define MSI_CLK 0
+ #elif (SYSCLK_FREQ == MSI_VALUE_L1)
+ #define MSI_CLK 1
+ #elif (SYSCLK_FREQ == MSI_VALUE_L2)
+ #define MSI_CLK 2
+ #elif (SYSCLK_FREQ == MSI_VALUE_L3)
+ #define MSI_CLK 3
+ #elif (SYSCLK_FREQ == MSI_VALUE_L4)
+ #define MSI_CLK 4
+ #elif (SYSCLK_FREQ == MSI_VALUE_L5)
+ #define MSI_CLK 5
+ #elif (SYSCLK_FREQ == MSI_VALUE_L6)
+ #define MSI_CLK 6
+ #else
+ #error SYSCL_FREQ must be set to MSI_VALUE_Lx(x=0~6)
+ #endif
+
+#elif SYSCLK_SRC == SYSCLK_USE_HSI
+
+ #if SYSCLK_FREQ != HSI_VALUE
+ #error SYSCL_FREQ must be set to HSI_VALUE
+ #endif
+
+#elif SYSCLK_SRC == SYSCLK_USE_HSE
+
+ #ifndef HSE_VALUE
+ #error HSE_VALUE must be defined!
+ #endif
+
+ #if SYSCLK_FREQ != HSE_VALUE
+ #error SYSCL_FREQ must be set to HSE_VALUE
+ #endif
+
+#elif SYSCLK_SRC == SYSCLK_USE_HSI_PLL
+
+ #ifndef HSI_VALUE
+ #error HSI_VALUE must be defined!
+ #endif
+
+ #if ((SYSCLK_FREQ % (HSI_VALUE / 2)) == 0) && (SYSCLK_FREQ / (HSI_VALUE / 2) >= 2) \
+ && (SYSCLK_FREQ / (HSI_VALUE / 2) <= 32)
+
+ #define PLLSRC_DIV 2
+ #define PLL_DIV PLL_DIV2_DISABLE
+ #define PLL_MUL (SYSCLK_FREQ / (HSI_VALUE / 2))
+
+ #elif (SYSCLK_FREQ % HSI_VALUE == 0) && (SYSCLK_FREQ / HSI_VALUE >= 2) && (SYSCLK_FREQ / HSI_VALUE <= 32)
+
+ #define PLLSRC_DIV 1
+ #define PLL_DIV PLL_DIV2_DISABLE
+ #define PLL_MUL (SYSCLK_FREQ / HSI_VALUE)
+
+ #elif ((SYSCLK_FREQ % (HSI_VALUE / 4)) == 0) && (SYSCLK_FREQ / (HSI_VALUE / 4) >= 2) \
+ && (SYSCLK_FREQ / (HSI_VALUE / 4) <= 32)
+
+ #define PLLSRC_DIV 2
+ #define PLL_DIV PLL_DIV2_ENABLE
+ #define PLL_MUL (SYSCLK_FREQ / (HSI_VALUE / 4))
+
+ #else
+ #error Cannot make a PLL multiply factor to SYSCLK_FREQ.
+ #endif
+
+#elif SYSCLK_SRC == SYSCLK_USE_HSE_PLL
+
+ #ifndef HSE_VALUE
+ #error HSE_VALUE must be defined!
+ #endif
+
+ #if ((SYSCLK_FREQ % (HSE_VALUE / 2)) == 0) && (SYSCLK_FREQ / (HSE_VALUE / 2) >= 2) \
+ && (SYSCLK_FREQ / (HSE_VALUE / 2) <= 32)
+
+ #define PLLSRC_DIV 2
+ #define PLL_DIV PLL_DIV2_DISABLE
+ #define PLL_MUL (SYSCLK_FREQ / (HSE_VALUE / 2))
+
+ #elif (SYSCLK_FREQ % HSE_VALUE == 0) && (SYSCLK_FREQ / HSE_VALUE >= 2) && (SYSCLK_FREQ / HSE_VALUE <= 32)
+
+ #define PLLSRC_DIV 1
+ #define PLL_DIV PLL_DIV2_DISABLE
+ #define PLL_MUL (SYSCLK_FREQ / HSE_VALUE)
+
+ #elif ((SYSCLK_FREQ % (HSE_VALUE / 4)) == 0) && (SYSCLK_FREQ / (HSE_VALUE / 4) >= 2) \
+ && (SYSCLK_FREQ / (HSE_VALUE / 4) <= 32)
+
+ #define PLLSRC_DIV 2
+ #define PLL_DIV PLL_DIV2_ENABLE
+ #define PLL_MUL (SYSCLK_FREQ / (HSE_VALUE / 4))
+
+ #else
+ #error Cannot make a PLL multiply factor to SYSCLK_FREQ.
+ #endif
+
+#else
+#error wrong value for SYSCLK_SRC
+#endif
+
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */
+
+/*******************************************************************************
+ * Clock Definitions
+ *******************************************************************************/
+uint32_t SystemCoreClock = SYSCLK_FREQ; /*!< System Clock Frequency (Core Clock) */
+
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint32_t MSIClockTable[7] = {MSI_VALUE_L0, MSI_VALUE_L1, MSI_VALUE_L2, MSI_VALUE_L3,
+ MSI_VALUE_L4, MSI_VALUE_L5, MSI_VALUE_L6};
+
+static void SetSysClock(void);
+
+#ifdef DATA_IN_ExtSRAM
+static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the Embedded Flash Interface, the PLL and update the
+ * SystemCoreClock variable.
+ * @note This function should be used only after reset.
+ */
+void SystemInit(void)
+{
+ /* FPU settings
+ * ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
+
+ /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+ /* Set MSIEN bit */
+ RCC->CTRLSTS |= (uint32_t)0x00000004;
+
+ /* Reset SW, HPRE, PPRE1, PPRE2 and MCO bits */
+ RCC->CFG &= (uint32_t)0xF8FFC000;
+
+ /* Reset HSEON, CLKSSEN and PLLEN bits */
+ RCC->CTRL &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CTRL &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL, MCOPRES and USBPRES bits */
+ RCC->CFG &= (uint32_t)0x0700FFFF;
+
+ /* Reset CFG2 register */
+ RCC->CFG2 = 0x00007000;
+
+ /* Reset CFG3 register */
+ RCC->CFG3 = 0x00003800;
+
+ /* Reset RDCTRL register */
+ RCC->RDCTRL = 0x00000000;
+
+ /* Reset PLLHSIPRE register */
+ RCC->PLLHSIPRE = 0x00000000;
+
+ /* Disable all interrupts and clear pending bits */
+ RCC->CLKINT = 0x04BF8000;
+
+ /* Enable ex mode */
+ RCC->APB1PCLKEN |= RCC_APB1PCLKEN_PWREN;
+ RCC->APB1PCLKEN &= (uint32_t)(~RCC_APB1PCLKEN_PWREN);
+
+ /* Enable ICACHE and Prefetch Buffer */
+ FLASH->AC |= (uint32_t)(FLASH_AC_ICAHEN | FLASH_AC_PRFTBFEN);
+
+ /* Checks whether the Low Voltage Mode status is SET or RESET */
+ if ((FLASH->AC & FLASH_AC_LVMF) != RESET)
+ {
+ /* FLASH Low Voltage Mode Disable */
+ FLASH->AC &= (uint32_t)(~FLASH_AC_LVMEN);
+ }
+
+#ifdef DATA_IN_ExtSRAM
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM */
+
+ /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+ /* Configure the Flash Latency cycles and enable prefetch buffer */
+ SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or
+ * configure other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any
+ * configuration based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is MSI, SystemCoreClock will contain the
+ * MSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the
+ * HSI_VALUE(**)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the
+ * HSE_VALUE(***)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the
+ * HSE_VALUE(***) or HSI_VALUE(**) multiplied by the PLL factors.
+ *
+ * (*) MSI_VALUE is a constant defined in n32l43x.h file (default value
+ * 4 MHz, 100KHz/200KHz/400KHz/800KHz/1MHz/2MHz/4MHz ) but the real
+ * value may vary depending on the variations in voltage and temperature.
+ *
+ * (**) HSI_VALUE is a constant defined in n32l43x.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (***) HSE_VALUE is a constant defined in n32l43x.h file (default value
+ * 8 MHz or 25 MHz, depedning on the product used), user has to
+ * ensure that HSE_VALUE is same as the real frequency of the crystal used.
+ * Otherwise, this function may have wrong result.
+ *
+ * - The result of this function could be not correct when using
+ * fractional value for HSE crystal.
+ */
+void SystemCoreClockUpdate(void)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0, plldiv2 = 0;
+ uint8_t msi_clk = 0;
+
+ /* Get SYSCLK source
+ * -------------------------------------------------------*/
+ tmp = RCC->CFG & RCC_CFG_SCLKSTS;
+
+ /* Get MSI clock
+ * -------------------------------------------------------*/
+ msi_clk = (uint8_t) ((RCC->CTRLSTS & RCC_CTRLSTS_MSIRANGE)>>4);
+
+ switch (tmp)
+ {
+ case 0x00: /* MSI used as system clock */
+ SystemCoreClock = MSIClockTable[msi_clk];
+ break;
+ case 0x04: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x08: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x0C: /* PLL used as system clock */
+
+ /* Get PLL clock source and multiplication factor
+ * ----------------------*/
+ pllmull = RCC->CFG & RCC_CFG_PLLMULFCT;
+ pllsource = RCC->CFG & RCC_CFG_PLLSRC;
+ plldiv2 = RCC->PLLHSIPRE & RCC_PLLHSIPRE_PLLSRCDIV;
+
+ if ((pllmull & RCC_CFG_PLLMULFCT_4) == 0)
+ {
+ pllmull = (pllmull >> 18) + 2; // PLLMUL[4]=0
+ }
+ else
+ {
+ pllmull = ((pllmull >> 18) - 496) + 1; // PLLMUL[4]=1
+ }
+
+ if (pllsource == 0x00)
+ {
+ /* HSI selected as PLL clock entry */
+ if ((RCC->PLLHSIPRE & RCC_PLLHSIPRE_PLLSRCDIV) != (uint32_t)RESET)
+ { /* HSI oscillator clock divided by 2 */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ SystemCoreClock = HSI_VALUE * pllmull;
+ }
+ }
+ else
+ {
+ /* HSE selected as PLL clock entry */
+ if ((RCC->CFG & RCC_CFG_PLLHSEPRES) != (uint32_t)RESET)
+ { /* HSE oscillator clock divided by 2 */
+ SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ SystemCoreClock = HSE_VALUE * pllmull;
+ }
+ }
+
+ if (plldiv2 == 0x02)
+ {
+ /* PLL source clock divided by 2 selected as PLL clock entry */
+ SystemCoreClock >>= 1;
+ }
+
+ break;
+
+ default:
+ SystemCoreClock = MSIClockTable[msi_clk];
+ break;
+ }
+
+ /* Compute HCLK clock frequency ----------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFG & RCC_CFG_AHBPRES) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/**
+ * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1
+ * prescalers.
+ */
+static void SetSysClock(void)
+{
+ uint32_t rcc_cfg = 0;
+ uint32_t rcc_pllhsipre = 0;
+ uint32_t StartUpCounter = 0;
+
+#if (SYSCLK_SRC == SYSCLK_USE_MSI)
+ uint8_t i=0;
+ bool MSIStatus = 0;
+ /* Config MSI */
+ RCC->CTRLSTS &= 0xFFFFFF8F;
+ /*Delay for while*/
+ for(i=0;i<0x30;i++);
+ RCC->CTRLSTS |= (((uint32_t)MSI_CLK) << 4);
+ /*Delay for while*/
+ for(i=0;i<0x30;i++);
+ /* Enable MSI */
+ RCC->CTRLSTS |= ((uint32_t)RCC_CTRLSTS_MSIEN);
+
+ /* Wait till MSI is ready and if Time out is reached exit */
+ do
+ {
+ MSIStatus = RCC->CTRLSTS & RCC_CTRLSTS_MSIRD;
+ StartUpCounter++;
+ } while ((MSIStatus == 0) && (StartUpCounter != MSI_STARTUP_TIMEOUT));
+
+ MSIStatus = ((RCC->CTRLSTS & RCC_CTRLSTS_MSIRD) != RESET);
+ if (!MSIStatus)
+ {
+ /* If MSI fails to start-up, the application will have wrong clock
+ * configuration. User can add here some code to deal with this error */
+ SystemCoreClock = MSI_VALUE_L6;
+ return;
+ }
+
+#elif ((SYSCLK_SRC == SYSCLK_USE_HSI) || (SYSCLK_SRC == SYSCLK_USE_HSI_PLL))
+
+ bool HSIStatus = 0;
+ /* Enable HSI */
+ RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
+
+ /* Wait till HSI is ready and if Time out is reached exit */
+ do
+ {
+ HSIStatus = RCC->CTRL & RCC_CTRL_HSIRDF;
+ StartUpCounter++;
+ } while ((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));
+
+ HSIStatus = ((RCC->CTRL & RCC_CTRL_HSIRDF) != RESET);
+ if (!HSIStatus)
+ {
+ /* If HSI fails to start-up, the application will have wrong clock
+ * configuration. User can add here some code to deal with this error */
+ SystemCoreClock = MSI_VALUE_L6;
+ return;
+ }
+
+#elif ((SYSCLK_SRC == SYSCLK_USE_HSE) || (SYSCLK_SRC == SYSCLK_USE_HSE_PLL))
+
+ bool HSEStatus = 0;
+ /* Enable HSE */
+ RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CTRL & RCC_CTRL_HSERDF;
+ StartUpCounter++;
+ } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ HSEStatus = ((RCC->CTRL & RCC_CTRL_HSERDF) != RESET);
+ if (!HSEStatus)
+ {
+ /* If HSE fails to start-up, the application will have wrong clock
+ * configuration. User can add here some code to deal with this error */
+ SystemCoreClock = MSI_VALUE_L6;
+ return;
+ }
+#endif
+
+ /* If the system clock is greater than 64MHz, the voltage range of the main voltage regulator
+ must be configured as 1.1V */
+ if (SYSCLK_FREQ >= 64000000)
+ {
+ /* Enables PWR peripheral clock */
+ RCC->APB1PCLKEN |= RCC_APB1_PERIPH_PWR;
+ /* Check PWR->CTRL1.MRSEL configuration */
+ if ((PWR->CTRL1 & ((uint32_t)PWR_CTRL1_MRSEL)) == ((uint32_t)PWR_CTRL1_MRSEL2))
+ {
+ /* Config 1.1V */
+ PWR->CTRL1 |= PWR_CTRL1_MRSEL1;
+ }
+ }
+
+ /* Flash wait state
+ 0: HCLK <= 32M
+ 1: HCLK <= 64M
+ 2: HCLK <= 96M
+ 3: HCLK <= 128M
+ */
+ FLASH->AC &= (uint32_t)((uint32_t)~FLASH_AC_LATENCY);
+ FLASH->AC |= (uint32_t)((SYSCLK_FREQ - 1) / 32000000);
+
+ /* HCLK = SYSCLK */
+ RCC->CFG |= (uint32_t)RCC_CFG_AHBPRES_DIV1;
+
+ /* PCLK2 max 54M */
+ if (SYSCLK_FREQ > 54000000)
+ {
+ RCC->CFG |= (uint32_t)RCC_CFG_APB2PRES_DIV2;
+ }
+ else
+ {
+ RCC->CFG |= (uint32_t)RCC_CFG_APB2PRES_DIV1;
+ }
+
+ /* PCLK1 max 27M */
+ if (SYSCLK_FREQ > 54000000)
+ {
+ RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV4;
+ }
+ else if (SYSCLK_FREQ > 27000000)
+ {
+ RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV2;
+ }
+ else
+ {
+ RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV1;
+ }
+
+#if SYSCLK_SRC == SYSCLK_USE_MSI
+ /* Select MSI as system clock source */
+ RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW));
+ RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_MSI;
+
+ /* Wait till MSI is used as system clock source */
+ while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x00)
+ {
+ }
+#elif SYSCLK_SRC == SYSCLK_USE_HSI
+ /* Select HSI as system clock source */
+ RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW));
+ RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_HSI;
+
+ /* Wait till HSI is used as system clock source */
+ while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x04)
+ {
+ }
+#elif SYSCLK_SRC == SYSCLK_USE_HSE
+ /* Select HSE as system clock source */
+ RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW));
+ RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_HSE;
+
+ /* Wait till HSE is used as system clock source */
+ while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x08)
+ {
+ }
+#elif SYSCLK_SRC == SYSCLK_USE_HSI_PLL || SYSCLK_SRC == SYSCLK_USE_HSE_PLL
+
+ /* clear bits */
+ RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_PLLSRC | RCC_CFG_PLLHSEPRES | RCC_CFG_PLLMULFCT));
+ RCC->PLLHSIPRE &= (uint32_t)((uint32_t) ~(RCC_PLLHSIPRE_PLLHSIPRE | RCC_PLLHSIPRE_PLLSRCDIV));
+
+ /* set PLL source */
+ rcc_cfg = RCC->CFG;
+ rcc_cfg |= (SYSCLK_SRC == SYSCLK_USE_HSI_PLL ? RCC_CFG_PLLSRC_HSI : RCC_CFG_PLLSRC_HSE);
+ /* PLL DIV */
+ rcc_pllhsipre = RCC->PLLHSIPRE;
+
+ #if SYSCLK_SRC == SYSCLK_USE_HSI_PLL
+ rcc_pllhsipre |= (PLLSRC_DIV == 1 ? RCC_PLLHSIPRE_PLLHSIPRE_HSI : RCC_PLLHSIPRE_PLLHSIPRE_HSI_DIV2);
+ #elif SYSCLK_SRC == SYSCLK_USE_HSE_PLL
+ rcc_cfg |= (PLLSRC_DIV == 1 ? RCC_CFG_PLLHSEPRES_HSE : RCC_CFG_PLLHSEPRES_HSE_DIV2);
+ #endif
+
+ /* set PLL DIV */
+ rcc_pllhsipre |= (PLL_DIV == PLL_DIV2_DISABLE ? RCC_PLLHSIPRE_PLLSRCDIV_DISABLE : RCC_PLLHSIPRE_PLLSRCDIV_ENABLE);
+
+ /* set PLL multiply factor */
+ #if PLL_MUL <= 16
+ rcc_cfg |= (PLL_MUL - 2) << 18;
+ #else
+ rcc_cfg |= ((PLL_MUL - 17) << 18) | (1 << 27);
+ #endif
+
+ RCC->CFG = rcc_cfg;
+ RCC->PLLHSIPRE = rcc_pllhsipre;
+
+ /* Enable PLL */
+ RCC->CTRL |= RCC_CTRL_PLLEN;
+
+ /* Wait till PLL is ready */
+ while ((RCC->CTRL & RCC_CTRL_PLLRDF) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW));
+ RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x0C)
+ {
+ }
+#endif
+}
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/system_n32l43x.h b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/system_n32l43x.h
new file mode 100644
index 0000000000..073f9c75d5
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/system_n32l43x.h
@@ -0,0 +1,59 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file system_n32l43x.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __SYSTEM_N32L43X_H__
+#define __SYSTEM_N32L43X_H__
+
+#include
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup N32L43X_System
+ * @{
+ */
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_N32L43X_H__ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/SConscript b/bsp/n32/libraries/N32L43x_Firmware_Library/SConscript
new file mode 100644
index 0000000000..93fb32cc45
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/SConscript
@@ -0,0 +1,63 @@
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+
+src = Split('''
+CMSIS/device/system_n32l43x.c
+n32l43x_std_periph_driver/src/n32l43x_gpio.c
+n32l43x_std_periph_driver/src/n32l43x_rcc.c
+n32l43x_std_periph_driver/src/n32l43x_exti.c
+n32l43x_std_periph_driver/src/misc.c
+''')
+
+if GetDepend(['RT_USING_SERIAL']):
+ src += ['n32l43x_std_periph_driver/src/n32l43x_usart.c']
+
+if GetDepend(['RT_USING_I2C']):
+ src += ['n32l43x_std_periph_driver/src/n32l43x_i2c.c']
+
+if GetDepend(['RT_USING_SPI']):
+ src += ['n32l43x_std_periph_driver/src/n32l43x_spi.c']
+
+if GetDepend(['RT_USING_CAN']):
+ src += ['n32l43x_std_periph_driver/src/n32l43x_can.c']
+
+if GetDepend(['RT_USING_ADC']):
+ src += ['n32l43x_std_periph_driver/src/n32l43x_adc.c']
+
+if GetDepend(['RT_USING_DAC']):
+ src += ['n32l43x_std_periph_driver/src/n32l43x_dac.c']
+
+if GetDepend(['RT_USING_HWTIMER']):
+ src += ['n32l43x_std_periph_driver/src/n32l43x_tim.c']
+
+if GetDepend(['RT_USING_RTC']):
+ src += ['n32l43x_std_periph_driver/src/n32l43x_rtc.c']
+ src += ['n32l43x_std_periph_driver/src/n32l43x_pwr.c']
+ src += ['n32l43x_std_periph_driver/src/n32l43x_flash.c']
+
+if GetDepend(['RT_USING_WDT']):
+ src += ['n32l43x_std_periph_driver/src/n32l43x_iwdg.c']
+ src += ['n32l43x_std_periph_driver/src/n32l43x_wwdg.c']
+
+if GetDepend(['RT_USING_BSP_USB']):
+ path += [cwd + '/n32l43x_usbfs_driver/inc']
+ src += [cwd + '/n32l43x_usbfs_driver/src']
+
+path = [
+ cwd + '/CMSIS/device',
+ cwd + '/CMSIS/core',
+ cwd + '/n32l43x_std_periph_driver/inc',]
+
+CPPDEFINES = ['USE_STDPERIPH_DRIVER']
+
+
+
+group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_aes.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_aes.h
new file mode 100644
index 0000000000..f6bea0f3ec
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_aes.h
@@ -0,0 +1,119 @@
+/*****************************************************************************
+* NationS Microcontroller Software Support
+* ----------------------------------------------------------------------------
+* Copyright (c) 2020, NationS Corporation
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* - Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the disclaimer below.
+*
+* NationS's name may not be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ****************************************************************************/
+/*****************************************************************************
+* File Name: n32l43x_aes.h
+* Function: Declaring AES algorithm library API
+* version: V1.2.0
+* Author: zhang.zhenshan
+* date: 2020-4-8
+* ****************************************************************************/
+
+#ifndef __N32L43X_AES_H__
+#define __N32L43X_AES_H__
+
+#include
+
+#define AES_ECB (0x11111111)
+#define AES_CBC (0x22222222)
+#define AES_CTR (0x33333333)
+
+#define AES_ENC (0x44444444)
+#define AES_DEC (0x55555555)
+
+enum
+{
+ AES_Crypto_OK = 0x0, //AES opreation success
+ AES_Init_OK = 0x0, //AES Init opreation success
+ AES_Crypto_ModeError = 0x5a5a5a5a, //Working mode error(Neither ECB nor CBC nor CTR)
+ AES_Crypto_EnOrDeError, //En&De error(Neither encryption nor decryption)
+ AES_Crypto_ParaNull, // the part of input(output/iv) Null
+ AES_Crypto_LengthError, // if Working mode is ECB or CBC,the length of input message must be 4 times and cannot be zero;
+ //if Working mode is CTR,the length of input message cannot be zero; othets: return AES_Crypto_LengthError
+
+ AES_Crypto_KeyLengthError, //the keyWordLen must be 4 or 6 or 8; othets:return AES_Crypto_KeyLengthError
+ AES_Crypto_UnInitError, //AES uninitialized
+};
+
+typedef struct
+{
+ uint32_t *in; // the part of input to be encrypted or decrypted
+ uint32_t *iv; // the part of initial vector
+ uint32_t *out; // the part of out
+ uint32_t *key; // the part of key
+ uint32_t keyWordLen; // the length(by word) of key
+ uint32_t inWordLen; // the length(by word) of plaintext or cipher
+ uint32_t En_De; // 0x44444444- encrypt, 0x55555555 - decrypt
+ uint32_t Mode; // 0x11111111 - ECB, 0x22222222 - CBC, 0x33333333 - CTR
+}AES_PARM;
+
+ /**
+ * @brief AES_Init
+ * @return AES_Init_OK, AES Init success; othets: AES Init fail
+ * @note
+ */
+
+uint32_t AES_Init(AES_PARM *parm);
+
+/**
+ * @brief AES crypto
+ * @param[in] parm pointer to AES context and the detail please refer to struct AES_PARM in AES.h
+ * @return AES_Crypto_OK, AES crypto success; othets: AES crypto fail(reference to the definition by enum variation)
+ * @note 1.Please refer to the demo in user guidance before using this function
+ * 2.Input and output can be the same buffer
+ * 3. IV can be NULL when ECB mode
+ * 4. If Working mode is ECB or CBC,the length of input message must be 4 times and cannot be zero;
+ * if Working mode is CTR,the length of input message cannot be zero;
+ * 5. If the input is in byte, make sure align by word.
+ */
+uint32_t AES_Crypto(AES_PARM *parm);
+
+/**
+ * @brief AES close
+ * @return none
+ * @note if you want to close AES algorithm, this function can be recalled.
+ */
+void AES_Close(void);
+
+/**
+ * @brief Get AES lib version
+ * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
+ * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
+ * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
+ * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
+ * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
+ * @return none
+ * @1.You can recall this function to get AES lib information
+ */
+void AES_Version(uint8_t *type, uint8_t *customer, uint8_t date[3], uint8_t *version);
+
+
+
+
+#endif
+
+
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_algo_common.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_algo_common.h
new file mode 100644
index 0000000000..22d3b74614
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_algo_common.h
@@ -0,0 +1,154 @@
+/*****************************************************************************
+* NationS Microcontroller Software Support
+* ----------------------------------------------------------------------------
+* Copyright (c) 2020, NationS Corporation
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* - Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the disclaimer below.
+*
+* NationS's name may not be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+* DISCLAIMED. IN NO EVENT SHALL NATIONZ BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ****************************************************************************/
+/*****************************************************************************
+* File Name: Common.h
+* Function: Defining the public functions used by other algorithm lib
+* version: V1.2.0
+* Author: huang.jinshang
+* date: 2020-01-06
+* ****************************************************************************/
+
+#ifndef _N32L43X_ALGO_COMMON_H_
+#define _N32L43X_ALGO_COMMON_H_
+
+#include
+
+
+enum{
+ Cpy_OK=0,//copy success
+ SetZero_OK = 0,//set zero success
+ XOR_OK = 0, //XOR success
+ Reverse_OK = 0, //Reverse success
+ Cmp_EQUAL = 0, //Two big number are equal
+ Cmp_UNEQUAL = 1, //Two big number are not equal
+
+};
+
+/**
+ * @brief disturb the sequence order
+ * @param[in] order pointer to the sequence to be disturbed
+ * @param[in] rand pointer to random number
+ * @param[in] the length of order
+ * @return RandomSort_OK: disturb order success; Others: disturb order fail;
+ * @note
+ */
+uint32_t RandomSort(uint8_t *order, const uint8_t *rand, uint32_t len);
+
+/**
+ * @brief Copy data by byte
+ * @param[in] dst pointer to destination data
+ * @param[in] src pointer to source data
+ * @param[in] byte length
+ * @return Cpy_OK: success; others: fail.
+ * @note 1. dst and src cannot be same
+ */
+uint32_t Cpy_U8( uint8_t *dst, uint8_t *src, uint32_t byteLen);
+
+/**
+ * @brief Copy data by word
+ * @param[in] dst pointer to destination data
+ * @param[in] src pointer to source data
+ * @param[in] word length
+ * @return Cpy_OK: success; others: fail.
+ * @note 1. dst and src must be aligned by word
+ */
+uint32_t Cpy_U32( uint32_t *dst, const uint32_t *src, uint32_t wordLen);
+
+ /**
+ * @brief XOR
+ * @param[in] a pointer to one data to be XORed
+ * @param[in] b pointer to another data to be XORed
+ * @param[in] the length of order
+ * @return XOR_OK: operation success; Others: operation fail;
+ * @note
+ */
+uint32_t XOR_U8(uint8_t *a, uint8_t *b, uint8_t *c, uint32_t byteLen);
+
+ /**
+ * @brief XORed two u32 arrays
+ * @param[in] a pointer to one data to be XORed
+ * @param[in] b pointer to another data to be XORed
+ * @param[in] the length of order
+ * @return XOR_OK: operation success; Others: operation fail;
+ * @note
+ */
+uint32_t XOR_U32(uint32_t *a,uint32_t *b,uint32_t *c,uint32_t wordLen);
+
+/**
+ * @brief set zero by byte
+ * @param[in] dst pointer to the address to be set zero
+ * @param[in] byte length
+ * @return SetZero_OK: success; others: fail.
+ * @note
+ */
+uint32_t SetZero_U8(uint8_t *dst, uint32_t byteLen);
+
+/**
+ * @brief set zero by word
+ * @param[in] dst pointer to the address to be set zero
+ * @param[in] word length
+ * @return SetZero_OK: success; others: fail.
+ * @note
+ */
+uint32_t SetZero_U32(uint32_t *dst, uint32_t wordLen);
+
+/**
+ * @brief reverse byte order of every word, the words stay the same
+ * @param[in] dst pointer to the destination address
+ * @param[in] src pointer to the source address
+ * @param[in] word length
+ * @return Reverse_OK: success; others: fail.
+ * @note 1.dst and src can be same
+ */
+uint32_t ReverseBytesInWord_U32(uint32_t *dst, const uint32_t *src, uint32_t wordLen);
+
+/**
+ * @brief compare two big number
+ * @param[in] a pointer to one big number
+ * @param[in] word length of a
+ * @param[in] b pointer to another big number
+ * @param[in] word length of b
+ * @return Cmp_UNEQUAL:a!=b;Cmp_EQUAL: a==b.
+ *
+ */
+int32_t Cmp_U32(const uint32_t *a, uint32_t aWordLen, const uint32_t *b, uint32_t bWordLen);
+
+/**
+ * @brief compare two big number
+ * @param[in] a pointer to one big number
+ * @param[in] word length of a
+ * @param[in] b pointer to another big number
+ * @param[in] word length of b
+ * @return Cmp_UNEQUAL:a!=b;Cmp_EQUAL: a==b.
+ *
+ */
+int32_t Cmp_U8(const uint8_t *a, uint32_t aByteLen, const uint8_t *b, uint32_t bByteLen);
+
+
+#endif
+
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_des.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_des.h
new file mode 100644
index 0000000000..12ffddc5bf
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_des.h
@@ -0,0 +1,115 @@
+/*****************************************************************************
+* Nations Microcontroller Software Support
+* ----------------------------------------------------------------------------
+* Copyright (c) 2020, Nations Corporation
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* - Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the disclaimer below.
+*
+* Nations's name may not be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY Nations "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+* DISCLAIMED. IN NO EVENT SHALL Nations BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ****************************************************************************/
+/*****************************************************************************
+* File Name: Dn32l43x_des.h
+* Function: Declaring DES algorithm library API
+* version: V1.2.0
+* Author: zhang.zhenshan
+* date: 2020-4-8
+* ****************************************************************************/
+
+
+#ifndef _N32L43X_DES_H_
+#define _N32L43X_DES_H_
+
+#include
+
+#define DES_ECB (0x11111111)
+#define DES_CBC (0x22222222)
+
+
+#define DES_ENC (0x33333333)
+#define DES_DEC (0x44444444)
+
+#define DES_KEY (0x55555555)
+#define TDES_2KEY (0x66666666)
+#define TDES_3KEY (0x77777777)
+
+enum DES
+{
+ DES_Crypto_OK = 0x0, //DES/TDES opreation success
+ DES_Init_OK = 0x0, //DES/TDES Init opreation success
+ DES_Crypto_ModeError = 0x5a5a5a5a, //Working mode error(Neither ECB nor CBC)
+ DES_Crypto_EnOrDeError, //En&De error(Neither encryption nor decryption)
+ DES_Crypto_ParaNull, // the part of input(output/iv) Null
+ DES_Crypto_LengthError, //the length of input message must be 2 times and cannot be zero
+ DES_Crypto_KeyError, //keyMode error(Neither DES_KEY nor TDES_2KEY nor TDES_3KEY)
+ DES_Crypto_UnInitError, //DES/TDES uninitialized
+};
+
+typedef struct
+{
+ uint32_t *in; // the part of input to be encrypted or decrypted
+ uint32_t *iv; // the part of initial vector
+ uint32_t *out; // the part of out
+ uint32_t *key; // the part of key
+ uint32_t inWordLen; // the length(by word) of plaintext or cipher
+ uint32_t En_De; // 0x33333333- encrypt, 0x44444444 - decrypt
+ uint32_t Mode; // 0x11111111 - ECB, 0x22222222 - CBC
+ uint32_t keyMode; //TDES key mode: 0x55555555-key,0x66666666-2key, 0x77777777-3key
+}DES_PARM;
+
+ /**
+ * @brief DES_Init
+ * @return DES_Init_OK, DES/TDES Init success; othets: DES/TDES Init fail
+ * @note
+ */
+uint32_t DES_Init(DES_PARM *parm);
+
+/**
+ * @brief DES crypto
+ * @param[in] parm pointer to DES/TDES context and the detail please refer to struct DES_PARM in DES.h
+ * @return DES_Crypto_OK, DES/TDES crypto success; othets: DES/TDES crypto fail(reference to the definition by enum variation)
+ * @note 1.Please refer to the demo in user guidance before using this function
+ * 2.Input and output can be the same buffer
+ * 3. IV can be NULL when ECB mode
+ * 4. The word lengrh of message must be as times as 2.
+ * 5. If the input is in byte, make sure align by word.
+ */
+uint32_t DES_Crypto(DES_PARM *parm);
+
+/**
+ * @brief DES close
+ * @return none
+ * @note if you want to close DES algorithm, this function can be recalled.
+ */
+void DES_Close(void);
+
+/**
+ * @brief Get DES/TDES lib version
+ * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
+ * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
+ * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
+ * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
+ * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
+ * @return none
+ * @1.You can recall this function to get DES/TDES lib information
+ */
+void DES_Version(uint8_t *type, uint8_t *customer, uint8_t date[3], uint8_t *version);
+
+#endif
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_hash.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_hash.h
new file mode 100644
index 0000000000..1fc829721d
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_hash.h
@@ -0,0 +1,212 @@
+/*****************************************************************************
+* Nationz Microcontroller Software Support
+* ----------------------------------------------------------------------------
+* Copyright (c) 2020, Nationz Corporation
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* - Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the disclaimer below.
+*
+* Nationz's name may not be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+* DISCLAIMED. IN NO EVENT SHALL NATIONZ BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ****************************************************************************/
+/*****************************************************************************
+* File Name: HASH.h
+* Function: Declaring HASH algorithm library API
+* version: V1.2.0
+* Author: zhang.zhenshan
+* date: 2020-4-8
+* ****************************************************************************/
+
+#ifndef _N32L43X_HASH_H_
+#define _N32L43X_HASH_H_
+
+#include
+
+#define ALG_SHA1 (uint16_t)(0x0004)
+#define ALG_SHA224 (uint16_t)(0x000A)
+#define ALG_SHA256 (uint16_t)(0x000B)
+//#define ALG_MD5 (u16)(0x000C)
+#define ALG_SM3 (uint16_t)(0x0012)
+
+enum
+{
+ HASH_SEQUENCE_TRUE = 0x0105A5A5,//save IV
+ HASH_SEQUENCE_FALSE = 0x010A5A5A, //not save IV
+ HASH_Init_OK = 0,//hash init success
+ HASH_Start_OK = 0,//hash update success
+ HASH_Update_OK = 0,//hash update success
+ HASH_Complete_OK = 0,//hash complete success
+ HASH_Close_OK = 0,//hash close success
+ HASH_ByteLenPlus_OK = 0,//byte length plus success
+ HASH_PadMsg_OK = 0,//message padding success
+ HASH_ProcMsgBuf_OK = 0, //message processing success
+ SHA1_Hash_OK = 0,//sha1 operation success
+ SM3_Hash_OK = 0,//sm3 operation success
+ SHA224_Hash_OK = 0,//sha224 operation success
+ SHA256_Hash_OK = 0,//sha256 operation success
+ //MD5_Hash_OK = 0,//MD5 operation success
+
+ HASH_Init_ERROR = 0x01044400,//hash init error
+ HASH_Start_ERROR, //hash start error
+ HASH_Update_ERROR, //hash update error
+ HASH_ByteLenPlus_ERROR,//hash byte plus error
+};
+
+struct _HASH_CTX_;
+
+typedef struct
+{
+ const uint16_t HashAlgID;//choice hash algorithm
+ const uint32_t * const K, KLen;//K and word length of K
+ const uint32_t * const IV, IVLen;//IV and word length of IV
+ const uint32_t HASH_SACCR, HASH_HASHCTRL;//relate registers
+ const uint32_t BlockByteLen, BlockWordLen; //byte length of block, word length of block
+ const uint32_t DigestByteLen, DigestWordLen; //byte length of digest,word length of digest
+ const uint32_t Cycle; //interation times
+ uint32_t (* const ByteLenPlus)(uint32_t *, uint32_t); //function pointer
+ uint32_t (* const PadMsg)(struct _HASH_CTX_ *); //function pointer
+}HASH_ALG;
+
+typedef struct _HASH_CTX_
+{
+ const HASH_ALG *hashAlg;//pointer to HASH_ALG
+ uint32_t sequence; // TRUE if the IV should be saved
+ uint32_t IV[16];
+ uint32_t msgByteLen[4];
+ uint8_t msgBuf[128+4];
+ uint32_t msgIdx;
+}HASH_CTX;
+
+extern const HASH_ALG HASH_ALG_SHA1[1];
+extern const HASH_ALG HASH_ALG_SHA224[1];
+extern const HASH_ALG HASH_ALG_SHA256[1];
+//extern const HASH_ALG HASH_ALG_MD5[1];
+extern const HASH_ALG HASH_ALG_SM3[1];
+
+/**
+ * @brief Hash init
+ * @param[in] ctx pointer to HASH_CTX struct
+ * @return HASH_Init_OK, Hash init success; othets: Hash init fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ */
+uint32_t HASH_Init(HASH_CTX *ctx);
+
+/**
+ * @brief Hash start
+ * @param[in] ctx pointer to HASH_CTX struct
+ * @return HASH_Start_OK, Hash start success; othets: Hash start fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ * 2.HASH_Init() should be recalled before use this function
+ */
+uint32_t HASH_Start(HASH_CTX *ctx);
+
+/**
+ * @brief Hash update
+ * @param[in] ctx pointer to HASH_CTX struct
+ * @param[in] in pointer to message
+ * @param[out] out pointer tohash result,digest
+ * @return HASH_Update_OK, Hash update success; othets: Hash update fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ * 2.HASH_Init() and HASH_Start() should be recalled before use this function
+ */
+uint32_t HASH_Update(HASH_CTX *ctx, uint8_t *in, uint32_t byteLen);
+
+/**
+ * @brief Hash complete
+ * @param[in] ctx pointer to HASH_CTX struct
+ * @param[out] out pointer tohash result,digest
+ * @return HASH_Complete_OK, Hash complete success; othets: Hash complete fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ * 2.HASH_Init(), HASH_Start() and HASH_Update() should be recalled before use this function
+ */
+uint32_t HASH_Complete(HASH_CTX *ctx, uint8_t *out);
+
+/**
+ * @brief Hash close
+ * @return HASH_Close_OK, Hash close success; othets: Hash close fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ */
+uint32_t HASH_Close(void);
+
+/**
+ * @brief SM3 Hash for 256bits digest
+ * @param[in] in pointer to message
+ * @param[in] byte length of in
+ * @param[out] out pointer tohash result,digest
+ * @return SM3_Hash_OK, SM3 hash success; othets: SM3 hash fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ */
+uint32_t SM3_Hash(uint8_t *in,uint32_t byteLen, uint8_t* out);
+
+
+/**
+ * @brief SHA1 Hash
+ * @param[in] in pointer to message
+ * @param[in] byte length of in
+ * @param[out] out pointer tohash result,digest
+ * @return SHA1_Hash_OK, SHA1 hash success; othets: SHA1 hash fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ */
+uint32_t SHA1_Hash(uint8_t*in, uint32_t byteLen, uint8_t*out);
+
+/**
+ * @brief SHA224 Hash
+ * @param[in] in pointer to message
+ * @param[in] byte length of in
+ * @param[out] out pointer tohash result,digest
+ * @return SHA224_Hash_OK, SHA224 hash success; othets: SHA224 hash fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ */
+uint32_t SHA224_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
+
+
+/**
+ * @brief SHA256 Hash
+ * @param[in] in pointer to message
+ * @param[in] byte length of in
+ * @param[out] out pointer tohash result,digest
+ * @return SHA256_Hash_OK, SHA256 hash success; othets: SHA256 hash fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ */
+uint32_t SHA256_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
+
+/**
+ * @brief MD5 Hash
+ * @param[in] in pointer to message
+ * @param[in] byte length of in
+ * @param[in] out pointer tohash result,digest
+ * @return MD5_Hash_OK, MD5 hash success; othets: MD5 hash fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ */
+//u32 MD5_Hash(u8* in,u32 byteLen, u8* out);
+
+/**
+ * @brief Get HASH lib version
+ * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
+ * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
+ * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
+ * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
+ * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
+ * @return none
+ * @1.You can recall this function to get RSA lib information
+ */
+void HASH_Version(uint8_t*type, uint8_t*customer, uint8_t date[3], uint8_t *version);
+
+
+#endif
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_rng.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_rng.h
new file mode 100644
index 0000000000..82c542ee8e
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_rng.h
@@ -0,0 +1,83 @@
+/*****************************************************************************
+* NationS Microcontroller Software Support
+* ----------------------------------------------------------------------------
+* Copyright (c) 2020, NationS Corporation
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* - Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the disclaimer below.
+*
+* NationS's name may not be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+* DISCLAIMED. IN NO EVENT SHALL NATIONZ BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ****************************************************************************/
+/*****************************************************************************
+* File Name: n32l43x_rng.h
+* Function: Declaring RNG algorithm library API
+* version: V1.2.0
+* Author: zhang.zhenshan
+* date: 2020-4-8
+* ****************************************************************************/
+
+#ifndef _N32L43X_RNG_H_
+#define _N32L43X_RNG_H_
+
+#include
+
+enum{
+ RNG_OK = 0x5a5a5a5a,
+ LENError = 0x311ECF50, //RNG generation of key length error
+ ADDRNULL = 0x7A9DB86C, // This address is empty
+};
+
+
+//u32 RNG_init(void);
+/**
+ * @brief Get pseudo random number
+ * @param[out] rand pointer to random number
+ * @param[in] the wordlen of random number
+ * @param[in] the seed, can be NULL
+ * @return RNG_OK:get random number success; othets: get random number fail
+ * @note
+ */
+uint32_t GetPseudoRand_U32(uint32_t *rand, uint32_t wordLen,uint32_t seed[2]);
+
+
+/**
+ * @brief Get true random number
+ * @param[out] rand pointer to random number
+ * @param[in] the wordlen of random number
+ * @return RNG_OK:get random number success; othets: get random number fail
+ * @note
+ */
+uint32_t GetTrueRand_U32(uint32_t *rand, uint32_t wordLen);
+
+/**
+ * @brief Get RNG lib version
+ * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
+ * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
+ * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
+ * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
+ * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
+ * @return none
+ * @1.You can recall this function to get RSA lib information
+ */
+void RNG_Version(uint8_t *type, uint8_t *customer, uint8_t date[3], uint8_t *version);
+
+#endif
+
+
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/misc.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/misc.h
new file mode 100644
index 0000000000..444e096314
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/misc.h
@@ -0,0 +1,229 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file misc.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __MISC_H__
+#define __MISC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l43x.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup MISC
+ * @{
+ */
+
+/** @addtogroup MISC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief NVIC Init Structure definition
+ */
+
+typedef struct
+{
+ uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
+ This parameter can be a value of @ref IRQn_Type
+ (For the complete n32l43x Devices IRQ Channels list, please
+ refer to n32l43x.h file) */
+
+ uint8_t
+ NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
+ specified in NVIC_IRQChannel. This parameter can be a value
+ between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+ uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
+ in NVIC_IRQChannel. This parameter can be a value
+ between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+ FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
+ will be enabled or disabled.
+ This parameter can be set either to ENABLE or DISABLE */
+} NVIC_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup NVIC_Priority_Table
+ * @{
+ */
+
+/**
+@code
+ The table below gives the allowed values of the pre-emption priority and subpriority according
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
+ ============================================================================================================================
+ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
+ ============================================================================================================================
+ NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption
+priority | | | 4 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption
+priority | | | 3 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption
+priority | | | 2 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption
+priority | | | 1 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption
+priority | | | 0 bits for subpriority
+ ============================================================================================================================
+@endcode
+*/
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup Vector_Table_Base
+ * @{
+ */
+
+#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
+#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || ((VECTTAB) == NVIC_VectTab_FLASH))
+/**
+ * @}
+ */
+
+/** @addtogroup System_Low_Power
+ * @{
+ */
+
+#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || ((LP) == NVIC_LP_SLEEPDEEP) || ((LP) == NVIC_LP_SLEEPONEXIT))
+/**
+ * @}
+ */
+
+/** @addtogroup Preemption_Priority_Group
+ * @{
+ */
+
+#define NVIC_PriorityGroup_0 \
+ ((uint32_t)0x700) /*!< 0 bits for pre-emption priority \
+ 4 bits for subpriority */
+#define NVIC_PriorityGroup_1 \
+ ((uint32_t)0x600) /*!< 1 bits for pre-emption priority \
+ 3 bits for subpriority */
+#define NVIC_PriorityGroup_2 \
+ ((uint32_t)0x500) /*!< 2 bits for pre-emption priority \
+ 2 bits for subpriority */
+#define NVIC_PriorityGroup_3 \
+ ((uint32_t)0x400) /*!< 3 bits for pre-emption priority \
+ 1 bits for subpriority */
+#define NVIC_PriorityGroup_4 \
+ ((uint32_t)0x300) /*!< 4 bits for pre-emption priority \
+ 0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP) \
+ (((GROUP) == NVIC_PriorityGroup_0) || ((GROUP) == NVIC_PriorityGroup_1) || ((GROUP) == NVIC_PriorityGroup_2) \
+ || ((GROUP) == NVIC_PriorityGroup_3) || ((GROUP) == NVIC_PriorityGroup_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup SysTick_clock_source
+ * @{
+ */
+
+#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) \
+ (((SOURCE) == SysTick_CLKSource_HCLK) || ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Exported_Functions
+ * @{
+ */
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitType* NVIC_InitStruct);
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState Cmd);
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MISC_H__ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_adc.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_adc.h
new file mode 100644
index 0000000000..cf6cae4448
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_adc.h
@@ -0,0 +1,548 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_adc.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L43X_ADC_H__
+#define __N32L43X_ADC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l43x.h"
+#include
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+#define VREF1P2_CTRL (*(uint32_t*)(0x40001800+0x24))
+#define _EnVref1p2() do{VREF1P2_CTRL|=(0x1<<13);}while (0);
+#define _DisVref1p2() do{VREF1P2_CTRL&=~(0x1<<13);}while (0);
+
+#define VREF2P0_CTRL (*(uint32_t*)(0x40001800+0x24))
+#define _EnVref2p0() do{VREF2P0_CTRL|=(0x1<<20);}while (0);
+#define _DisVref2p0() do{VREF2P0_CTRL&=~(0x1<<20);}while (0);
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/** @addtogroup ADC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief ADC Init structure definition
+ */
+typedef struct
+{
+
+ FunctionalState MultiChEn; /*!< Specifies whether the conversion is performed in
+ Scan (multichannels) or Single (one channel) mode.
+ This parameter can be set to ENABLE or DISABLE */
+
+ FunctionalState ContinueConvEn; /*!< Specifies whether the conversion is performed in
+ Continuous or Single mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t ExtTrigSelect; /*!< Defines the external trigger used to start the analog
+ to digital conversion of regular channels. This parameter
+ can be a value of @ref
+ ADC_external_trigger_sources_for_regular_channels_conversion */
+
+ uint32_t DatAlign; /*!< Specifies whether the ADC data alignment is left or right.
+ This parameter can be a value of @ref ADC_data_align */
+
+ uint8_t ChsNumber; /*!< Specifies the number of ADC channels that will be converted
+ using the sequencer for regular channel group.
+ This parameter must range from 1 to 16. */
+} ADC_InitType;
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Exported_Constants
+ * @{
+ */
+
+#define IsAdcModule(PERIPH) (((PERIPH) == ADC))
+
+#define IsAdcDmaModule(PERIPH) (((PERIPH) == ADC))
+
+
+
+/** @addtogroup ADC_external_trigger_sources_for_regular_channels_conversion
+ * @{
+ */
+
+#define ADC_EXT_TRIGCONV_T1_CC1 ((uint32_t)0x00000000)
+#define ADC_EXT_TRIGCONV_T1_CC2 ((uint32_t)0x00020000)
+#define ADC_EXT_TRIGCONV_T1_CC3 ((uint32_t)0x00040000)
+#define ADC_EXT_TRIGCONV_T2_CC2 ((uint32_t)0x00060000)
+#define ADC_EXT_TRIGCONV_T3_TRGO ((uint32_t)0x00080000)
+#define ADC_EXT_TRIGCONV_T4_CC4 ((uint32_t)0x000A0000)
+#define ADC_EXT_TRIGCONV_EXT_INT11_TIM8_TRGO ((uint32_t)0x000C0000)
+#define ADC_EXT_TRIGCONV_NONE ((uint32_t)0x000E0000)
+
+
+#define IsAdcExtTrig(REGTRIG) \
+ (((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC2) \
+ || ((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC3) || ((REGTRIG) == ADC_EXT_TRIGCONV_T2_CC2) \
+ || ((REGTRIG) == ADC_EXT_TRIGCONV_T3_TRGO) || ((REGTRIG) == ADC_EXT_TRIGCONV_T4_CC4) \
+ || ((REGTRIG) == ADC_EXT_TRIGCONV_EXT_INT11_TIM8_TRGO) || ((REGTRIG) == ADC_EXT_TRIGCONV_NONE))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_data_align
+ * @{
+ */
+
+#define ADC_DAT_ALIGN_R ((uint32_t)0x00000000)
+#define ADC_DAT_ALIGN_L ((uint32_t)0x00000800)
+#define IsAdcDatAlign(ALIGN) (((ALIGN) == ADC_DAT_ALIGN_R) || ((ALIGN) == ADC_DAT_ALIGN_L))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_channels
+ * @{
+ */
+
+#define ADC_CH_0 ((uint8_t)0x00)
+#define ADC_CH_1 ((uint8_t)0x01)
+#define ADC_CH_2 ((uint8_t)0x02)
+#define ADC_CH_3 ((uint8_t)0x03)
+#define ADC_CH_4 ((uint8_t)0x04)
+#define ADC_CH_5 ((uint8_t)0x05)
+#define ADC_CH_6 ((uint8_t)0x06)
+#define ADC_CH_7 ((uint8_t)0x07)
+#define ADC_CH_8 ((uint8_t)0x08)
+#define ADC_CH_9 ((uint8_t)0x09)
+#define ADC_CH_10 ((uint8_t)0x0A)
+#define ADC_CH_11 ((uint8_t)0x0B)
+#define ADC_CH_12 ((uint8_t)0x0C)
+#define ADC_CH_13 ((uint8_t)0x0D)
+#define ADC_CH_14 ((uint8_t)0x0E)
+#define ADC_CH_15 ((uint8_t)0x0F)
+#define ADC_CH_16 ((uint8_t)0x10)
+#define ADC_CH_17 ((uint8_t)0x11)
+#define ADC_CH_18 ((uint8_t)0x12)
+
+#define ADC_CH_VREFINT ((uint8_t)ADC_CH_0)
+#define ADC_CH_TEMP_SENSOR ((uint8_t)ADC_CH_17)
+#define ADC_CH_VREFBUF ((uint8_t)ADC_CH_18)
+
+#define IsAdcChannel(CHANNEL) \
+ (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) \
+ || ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) \
+ || ((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9) || ((CHANNEL) == ADC_CH_10) || ((CHANNEL) == ADC_CH_11) \
+ || ((CHANNEL) == ADC_CH_12) || ((CHANNEL) == ADC_CH_13) || ((CHANNEL) == ADC_CH_14) || ((CHANNEL) == ADC_CH_15) \
+ || ((CHANNEL) == ADC_CH_16) || ((CHANNEL) == ADC_CH_17) || ((CHANNEL) == ADC_CH_18))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_sampling_time
+ * @{
+ */
+
+#define ADC_SAMP_TIME_1CYCLES5 ((uint8_t)0x00)
+#define ADC_SAMP_TIME_7CYCLES5 ((uint8_t)0x01)
+#define ADC_SAMP_TIME_13CYCLES5 ((uint8_t)0x02)
+#define ADC_SAMP_TIME_28CYCLES5 ((uint8_t)0x03)
+#define ADC_SAMP_TIME_41CYCLES5 ((uint8_t)0x04)
+#define ADC_SAMP_TIME_55CYCLES5 ((uint8_t)0x05)
+#define ADC_SAMP_TIME_71CYCLES5 ((uint8_t)0x06)
+#define ADC_SAMP_TIME_239CYCLES5 ((uint8_t)0x07)
+#define IsAdcSampleTime(TIME) \
+ (((TIME) == ADC_SAMP_TIME_1CYCLES5) || ((TIME) == ADC_SAMP_TIME_7CYCLES5) || ((TIME) == ADC_SAMP_TIME_13CYCLES5) \
+ || ((TIME) == ADC_SAMP_TIME_28CYCLES5) || ((TIME) == ADC_SAMP_TIME_41CYCLES5) \
+ || ((TIME) == ADC_SAMP_TIME_55CYCLES5) || ((TIME) == ADC_SAMP_TIME_71CYCLES5) \
+ || ((TIME) == ADC_SAMP_TIME_239CYCLES5))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_external_trigger_sources_for_injected_channels_conversion
+ * @{
+ */
+
+#define ADC_EXT_TRIG_INJ_CONV_T1_TRGO ((uint32_t)0x00000000)
+#define ADC_EXT_TRIG_INJ_CONV_T1_CC4 ((uint32_t)0x00001000)
+#define ADC_EXT_TRIG_INJ_CONV_T2_TRGO ((uint32_t)0x00002000)
+#define ADC_EXT_TRIG_INJ_CONV_T2_CC1 ((uint32_t)0x00003000)
+#define ADC_EXT_TRIG_INJ_CONV_T3_CC4 ((uint32_t)0x00004000)
+#define ADC_EXT_TRIG_INJ_CONV_T4_TRGO ((uint32_t)0x00005000)
+#define ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4 ((uint32_t)0x00006000)
+#define ADC_EXT_TRIG_INJ_CONV_NONE ((uint32_t)0x00007000)
+
+
+#define IsAdcExtInjTrig(INJTRIG) \
+ (((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T1_TRGO) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T1_CC4) \
+ || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T2_TRGO) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T2_CC1) \
+ || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T3_CC4) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T4_TRGO) \
+ || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_NONE))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_injected_channel_selection
+ * @{
+ */
+
+#define ADC_INJ_CH_1 ((uint8_t)0x14)
+#define ADC_INJ_CH_2 ((uint8_t)0x18)
+#define ADC_INJ_CH_3 ((uint8_t)0x1C)
+#define ADC_INJ_CH_4 ((uint8_t)0x20)
+#define IsAdcInjCh(CHANNEL) \
+ (((CHANNEL) == ADC_INJ_CH_1) || ((CHANNEL) == ADC_INJ_CH_2) || ((CHANNEL) == ADC_INJ_CH_3) \
+ || ((CHANNEL) == ADC_INJ_CH_4))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_analog_watchdog_selection
+ * @{
+ */
+
+#define ADC_ANALOG_WTDG_SINGLEREG_ENABLE ((uint32_t)0x00800200)
+#define ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE ((uint32_t)0x00400200)
+#define ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE ((uint32_t)0x00C00200)
+#define ADC_ANALOG_WTDG_ALLREG_ENABLE ((uint32_t)0x00800000)
+#define ADC_ANALOG_WTDG_ALLINJEC_ENABLE ((uint32_t)0x00400000)
+#define ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE ((uint32_t)0x00C00000)
+#define ADC_ANALOG_WTDG_NONE ((uint32_t)0x00000000)
+
+#define IsAdcAnalogWatchdog(WATCHDOG) \
+ (((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEREG_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE) \
+ || ((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLREG_ENABLE) \
+ || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLINJEC_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE) \
+ || ((WATCHDOG) == ADC_ANALOG_WTDG_NONE))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_interrupts_definition
+ * @{
+ */
+
+#define ADC_INT_ENDC ((uint16_t)0x0220)
+#define ADC_INT_AWD ((uint16_t)0x0140)
+#define ADC_INT_JENDC ((uint16_t)0x0480)
+
+#define IsAdcInt(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))
+
+#define IsAdcGetInt(IT) (((IT) == ADC_INT_ENDC) || ((IT) == ADC_INT_AWD) || ((IT) == ADC_INT_JENDC))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_flags_definition
+ * @{
+ */
+
+#define ADC_FLAG_AWDG ((uint8_t)0x01)
+#define ADC_FLAG_ENDC ((uint8_t)0x02)
+#define ADC_FLAG_JENDC ((uint8_t)0x04)
+#define ADC_FLAG_JSTR ((uint8_t)0x08)
+#define ADC_FLAG_STR ((uint8_t)0x10)
+#define ADC_FLAG_EOC_ANY ((uint8_t)0x20)
+#define ADC_FLAG_JEOC_ANY ((uint8_t)0x40)
+#define IsAdcClrFlag(FLAG) ((((FLAG) & (uint8_t)0x80) == 0x00) && ((FLAG) != 0x00))
+#define IsAdcGetFlag(FLAG) \
+ (((FLAG) == ADC_FLAG_AWDG) || ((FLAG) == ADC_FLAG_ENDC) || ((FLAG) == ADC_FLAG_JENDC) || ((FLAG) == ADC_FLAG_JSTR) \
+ || ((FLAG) == ADC_FLAG_STR) || ((FLAG) == ADC_FLAG_EOC_ANY) || ((FLAG) == ADC_FLAG_JEOC_ANY))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_thresholds
+ * @{
+ */
+#define IsAdcValid(THRESHOLD) ((THRESHOLD) <= 0xFFF)
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_injected_offset
+ * @{
+ */
+
+#define IsAdcOffsetValid(OFFSET) ((OFFSET) <= 0xFFF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_injected_length
+ * @{
+ */
+
+#define IsAdcInjLenValid(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_injected_rank
+ * @{
+ */
+
+#define IsAdcInjRankValid(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_regular_length
+ * @{
+ */
+
+#define IsAdcSeqLenValid(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_regular_rank
+ * @{
+ */
+
+#define IsAdcReqRankValid(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_regular_discontinuous_mode_number
+ * @{
+ */
+
+#define IsAdcSeqDiscNumberValid(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
+
+/**
+ * @}
+ */
+
+/************************** fllowing bit seg in ex register **********************/
+/**@addtogroup ADC_channels_ex_style
+ * @{
+ */
+
+
+#define ADC_CH_0 ((uint8_t)0x00)
+#define ADC_CH_1_PA0 ((uint8_t)0x01)
+#define ADC_CH_2_PA1 ((uint8_t)0x02)
+#define ADC_CH_3_PA2 ((uint8_t)0x03)
+#define ADC_CH_4_PA3 ((uint8_t)0x04)
+#define ADC_CH_5_PA4 ((uint8_t)0x05)
+#define ADC_CH_6_PA5 ((uint8_t)0x06)
+#define ADC_CH_7_PA6 ((uint8_t)0x07)
+#define ADC_CH_8_PA7 ((uint8_t)0x08)
+#define ADC_CH_9_PB0 ((uint8_t)0x09)
+#define ADC_CH_10_PB1 ((uint8_t)0x0A)
+#define ADC_CH_11_PC0 ((uint8_t)0x0B)
+#define ADC_CH_12_PC1 ((uint8_t)0x0C)
+#define ADC_CH_13_PC2 ((uint8_t)0x0D)
+#define ADC_CH_14_PC3 ((uint8_t)0x0E)
+#define ADC_CH_15_PC4 ((uint8_t)0x0F)
+#define ADC_CH_16_PC5 ((uint8_t)0x10)
+#define ADC_CH_17 ((uint8_t)0x11)
+#define ADC_CH_18 ((uint8_t)0x12)
+/**
+ * @}
+ */
+
+/**@addtogroup ADC_dif_sel_ch_definition
+ * @{
+ */
+#define aDC_DIFSEL_CHS_MASK ((uint32_t)0x0007FFFF)
+#define ADC_DIFSEL_CHS_0 ((uint32_t)0x00000001)
+#define ADC_DIFSEL_CHS_1 ((uint32_t)0x00000002)
+#define ADC_DIFSEL_CHS_2 ((uint32_t)0x00000004)
+#define ADC_DIFSEL_CHS_3 ((uint32_t)0x00000008)
+#define ADC_DIFSEL_CHS_4 ((uint32_t)0x00000010)
+#define ADC_DIFSEL_CHS_5 ((uint32_t)0x00000020)
+#define ADC_DIFSEL_CHS_6 ((uint32_t)0x00000040)
+#define ADC_DIFSEL_CHS_7 ((uint32_t)0x00000080)
+#define ADC_DIFSEL_CHS_8 ((uint32_t)0x00000100)
+#define ADC_DIFSEL_CHS_9 ((uint32_t)0x00000200)
+#define ADC_DIFSEL_CHS_10 ((uint32_t)0x00000400)
+#define ADC_DIFSEL_CHS_11 ((uint32_t)0x00000800)
+#define ADC_DIFSEL_CHS_12 ((uint32_t)0x00001000)
+#define ADC_DIFSEL_CHS_13 ((uint32_t)0x00002000)
+#define ADC_DIFSEL_CHS_14 ((uint32_t)0x00004000)
+#define ADC_DIFSEL_CHS_15 ((uint32_t)0x00008000)
+#define ADC_DIFSEL_CHS_16 ((uint32_t)0x00010000)
+#define ADC_DIFSEL_CHS_17 ((uint32_t)0x00020000)
+#define ADC_DIFSEL_CHS_18 ((uint32_t)0x00040000)
+/**
+ * @}
+ */
+
+/**@addtogroup ADC_calfact_definition
+ * @{
+ */
+#define ADC_CALFACT_CALFACTD_MSK ((uint32_t)0x3FL << 16)
+#define ADC_CALFACT_CALFACTS_MSK ((uint32_t)0x3FL << 0)
+/**
+ * @}
+ */
+
+/**@addtogroup ADC_ctrl3_definition
+ * @{
+ */
+#define ADC_CTRL3_DPWMOD_MSK ((uint32_t)0x01L << 10)
+#define ADC_CTRL3_JENDCAIEN_MSK ((uint32_t)0x01L << 9)
+#define ADC_CTRL3_ENDCAIEN_MSK ((uint32_t)0x01L << 8)
+#define ADC_CTRL3_BPCAL_MSK ((uint32_t)0x01L << 7)
+#define ADC_CTRL3_CKMOD_MSK ((uint32_t)0x01L << 4)
+#define ADC_CTRL3_CALALD_MSK ((uint32_t)0x01L << 3)
+#define ADC_CTRL3_CALDIF_MSK ((uint32_t)0x01L << 2)
+#define ADC_CTRL3_RES_MSK ((uint32_t)0x03L << 0)
+#define ADC_SAMPT3_SAMPSEL_MSK ((uint32_t)0x01L << 3)
+
+#define ADC_CLOCK_PLL ((uint32_t)ADC_CTRL3_CKMOD_MSK)
+#define ADC_CLOCK_AHB ((uint32_t)(~ADC_CTRL3_CKMOD_MSK))
+typedef enum
+{
+ ADC_CTRL3_CKMOD_AHB = 0,
+ ADC_CTRL3_CKMOD_PLL = 1,
+} ADC_CTRL3_CKMOD;
+typedef enum
+{
+ ADC_CTRL3_RES_12BIT = 3,
+ ADC_CTRL3_RES_10BIT = 2,
+ ADC_CTRL3_RES_8BIT = 1,
+ ADC_CTRL3_RES_6BIT = 0,
+} ADC_CTRL3_RES;
+typedef struct
+{
+ FunctionalState DeepPowerModEn;
+ FunctionalState JendcIntEn;
+ FunctionalState EndcIntEn;
+ ADC_CTRL3_CKMOD ClkMode;
+ FunctionalState CalAtuoLoadEn;
+ bool DifModCal;
+ ADC_CTRL3_RES ResBit;
+ bool Samp303Style;
+} ADC_InitTypeEx;
+/**
+ * @}
+ */
+
+/**@addtogroup ADC_bit_num_definition
+ * @{
+ */
+#define ADC_RST_BIT_12 ((uint32_t)0x03)
+#define ADC_RST_BIT_10 ((uint32_t)0x02)
+#define ADC_RST_BIT_8 ((uint32_t)0x01)
+#define ADC_RESULT_BIT_6 ((uint32_t)0x00)
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_flags_ex_definition
+ * @{
+ */
+#define ADC_FLAG_RDY ((uint8_t)0x20)
+#define ADC_FLAG_PD_RDY ((uint8_t)0x40)
+#define IS_ADC_GET_READY(FLAG) (((FLAG) == ADC_FLAG_RDY) || ((FLAG) == ADC_FLAG_PD_RDY))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Exported_Functions
+ * @{
+ */
+
+void ADC_DeInit(ADC_Module* ADCx);
+void ADC_Init(ADC_Module* ADCx, ADC_InitType* ADC_InitStruct);
+void ADC_InitStruct(ADC_InitType* ADC_InitStruct);
+void ADC_Enable(ADC_Module* ADCx, FunctionalState Cmd);
+void ADC_EnableDMA(ADC_Module* ADCx, FunctionalState Cmd);
+void ADC_ConfigInt(ADC_Module* ADCx, uint16_t ADC_IT, FunctionalState Cmd);
+void ADC_StartCalibration(ADC_Module* ADCx);
+FlagStatus ADC_GetCalibrationStatus(ADC_Module* ADCx);
+void ADC_EnableSoftwareStartConv(ADC_Module* ADCx, FunctionalState Cmd);
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_Module* ADCx);
+void ADC_ConfigDiscModeChannelCount(ADC_Module* ADCx, uint8_t Number);
+void ADC_EnableDiscMode(ADC_Module* ADCx, FunctionalState Cmd);
+void ADC_ConfigRegularChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_EnableExternalTrigConv(ADC_Module* ADCx, FunctionalState Cmd);
+uint16_t ADC_GetDat(ADC_Module* ADCx);
+void ADC_EnableAutoInjectedConv(ADC_Module* ADCx, FunctionalState Cmd);
+void ADC_EnableInjectedDiscMode(ADC_Module* ADCx, FunctionalState Cmd);
+void ADC_ConfigExternalTrigInjectedConv(ADC_Module* ADCx, uint32_t ADC_ExternalTrigInjecConv);
+void ADC_EnableExternalTrigInjectedConv(ADC_Module* ADCx, FunctionalState Cmd);
+void ADC_EnableSoftwareStartInjectedConv(ADC_Module* ADCx, FunctionalState Cmd);
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_Module* ADCx);
+void ADC_ConfigInjectedChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_ConfigInjectedSequencerLength(ADC_Module* ADCx, uint8_t Length);
+void ADC_SetInjectedOffsetDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
+uint16_t ADC_GetInjectedConversionDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel);
+void ADC_ConfigAnalogWatchdogWorkChannelType(ADC_Module* ADCx, uint32_t ADC_AnalogWatchdog);
+void ADC_ConfigAnalogWatchdogThresholds(ADC_Module* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
+void ADC_ConfigAnalogWatchdogSingleChannel(ADC_Module* ADCx, uint8_t ADC_Channel);
+void ADC_EnableTempSensorVrefint(FunctionalState Cmd);
+FlagStatus ADC_GetFlagStatus(ADC_Module* ADCx, uint8_t ADC_FLAG);
+void ADC_ClearFlag(ADC_Module* ADCx, uint8_t ADC_FLAG);
+INTStatus ADC_GetIntStatus(ADC_Module* ADCx, uint16_t ADC_IT);
+void ADC_ClearIntPendingBit(ADC_Module* ADCx, uint16_t ADC_IT);
+
+void ADC_InitEx(ADC_Module* ADCx, ADC_InitTypeEx* ADC_InitStructEx);
+FlagStatus ADC_GetFlagStatusNew(ADC_Module* ADCx, uint8_t ADC_FLAG_NEW);
+void ADC_SetBypassCalibration(ADC_Module* ADCx, FunctionalState en);
+void ADC_SetConvResultBitNum(ADC_Module* ADCx, uint32_t ResultBitNum);
+
+void ADC_ConfigClk(ADC_CTRL3_CKMOD ADC_ClkMode, uint32_t RCC_ADCHCLKPrescaler);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32L43X_ADC_H__ */
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_can.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_can.h
new file mode 100644
index 0000000000..4c255decfe
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_can.h
@@ -0,0 +1,670 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_can.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L43X_CAN_H__
+#define __N32L43X_CAN_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l43x.h"
+
+/** @addtogroup N32L43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CAN
+ * @{
+ */
+
+/** @addtogroup CAN_Exported_Types
+ * @{
+ */
+
+#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN))
+
+/**
+ * @brief CAN init structure definition
+ */
+
+typedef struct
+{
+ uint16_t BaudRatePrescaler; /*!< Specifies the length of a time quantum.
+ It ranges from 1 to 1024. */
+
+ uint8_t OperatingMode; /*!< Specifies the CAN operating mode.
+ This parameter can be a value of
+ @ref CAN_operating_mode */
+
+ uint8_t RSJW; /*!< Specifies the maximum number of time quanta
+ the CAN hardware is allowed to lengthen or
+ shorten a bit to perform resynchronization.
+ This parameter can be a value of
+ @ref CAN_synchronisation_jump_width */
+
+ uint8_t TBS1; /*!< Specifies the number of time quanta in Bit
+ Segment 1. This parameter can be a value of
+ @ref CAN_time_quantum_in_bit_segment_1 */
+
+ uint8_t TBS2; /*!< Specifies the number of time quanta in Bit
+ Segment 2.
+ This parameter can be a value of
+ @ref CAN_time_quantum_in_bit_segment_2 */
+
+ FunctionalState TTCM; /*!< Enable or disable the time triggered
+ communication mode. This parameter can be set
+ either to ENABLE or DISABLE. */
+
+ FunctionalState ABOM; /*!< Enable or disable the automatic bus-off
+ management. This parameter can be set either
+ to ENABLE or DISABLE. */
+
+ FunctionalState AWKUM; /*!< Enable or disable the automatic wake-up mode.
+ This parameter can be set either to ENABLE or
+ DISABLE. */
+
+ FunctionalState NART; /*!< Enable or disable the no-automatic
+ retransmission mode. This parameter can be
+ set either to ENABLE or DISABLE. */
+
+ FunctionalState RFLM; /*!< Enable or disable the Receive DATFIFO Locked mode.
+ This parameter can be set either to ENABLE
+ or DISABLE. */
+
+ FunctionalState TXFP; /*!< Enable or disable the transmit DATFIFO priority.
+ This parameter can be set either to ENABLE
+ or DISABLE. */
+} CAN_InitType;
+
+/**
+ * @brief CAN filter init structure definition
+ */
+
+typedef struct
+{
+ uint16_t Filter_HighId; /*!< Specifies the filter identification number (MSBs for a 32-bit
+ configuration, first one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t Filter_LowId; /*!< Specifies the filter identification number (LSBs for a 32-bit
+ configuration, second one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t FilterMask_HighId; /*!< Specifies the filter mask number or identification number,
+ according to the mode (MSBs for a 32-bit configuration,
+ first one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t FilterMask_LowId; /*!< Specifies the filter mask number or identification number,
+ according to the mode (LSBs for a 32-bit configuration,
+ second one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t Filter_FIFOAssignment; /*!< Specifies the DATFIFO (0 or 1) which will be assigned to the filter.
+ This parameter can be a value of @ref CAN_filter_FIFO */
+
+ uint8_t Filter_Num; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
+
+ uint8_t Filter_Mode; /*!< Specifies the filter mode to be initialized.
+ This parameter can be a value of @ref CAN_filter_mode */
+
+ uint8_t Filter_Scale; /*!< Specifies the filter scale.
+ This parameter can be a value of @ref CAN_filter_scale */
+
+ FunctionalState Filter_Act; /*!< Enable or disable the filter.
+ This parameter can be set either to ENABLE or DISABLE. */
+} CAN_FilterInitType;
+
+/**
+ * @brief CAN Tx message structure definition
+ */
+
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter can be a value between 0 to 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+ uint8_t IDE; /*!< Specifies the type of identifier for the message that
+ will be transmitted. This parameter can be a value
+ of @ref CAN_identifier_type */
+
+ uint8_t RTR; /*!< Specifies the type of frame for the message that will
+ be transmitted. This parameter can be a value of
+ @ref CAN_remote_transmission_request */
+
+ uint8_t DLC; /*!< Specifies the length of the frame that will be
+ transmitted. This parameter can be a value between
+ 0 to 8 */
+
+ uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
+ to 0xFF. */
+} CanTxMessage;
+
+/**
+ * @brief CAN Rx message structure definition
+ */
+
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter can be a value between 0 to 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+ uint8_t IDE; /*!< Specifies the type of identifier for the message that
+ will be received. This parameter can be a value of
+ @ref CAN_identifier_type */
+
+ uint8_t RTR; /*!< Specifies the type of frame for the received message.
+ This parameter can be a value of
+ @ref CAN_remote_transmission_request */
+
+ uint8_t DLC; /*!< Specifies the length of the frame that will be received.
+ This parameter can be a value between 0 to 8 */
+
+ uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
+ 0xFF. */
+
+ uint8_t FMI; /*!< Specifies the index of the filter the message stored in
+ the mailbox passes through. This parameter can be a
+ value between 0 to 0xFF */
+} CanRxMessage;
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup CAN_sleep_constants
+ * @{
+ */
+
+#define CAN_InitSTS_Failed ((uint8_t)0x00) /*!< CAN initialization failed */
+#define CAN_InitSTS_Success ((uint8_t)0x01) /*!< CAN initialization OK */
+
+/**
+ * @}
+ */
+
+/** @addtogroup OperatingMode
+ * @{
+ */
+
+#define CAN_Normal_Mode ((uint8_t)0x00) /*!< normal mode */
+#define CAN_LoopBack_Mode ((uint8_t)0x01) /*!< loopback mode */
+#define CAN_Silent_Mode ((uint8_t)0x02) /*!< silent mode */
+#define CAN_Silent_LoopBack_Mode ((uint8_t)0x03) /*!< loopback combined with silent mode */
+
+#define IS_CAN_MODE(MODE) \
+ (((MODE) == CAN_Normal_Mode) || ((MODE) == CAN_LoopBack_Mode) || ((MODE) == CAN_Silent_Mode) \
+ || ((MODE) == CAN_Silent_LoopBack_Mode))
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup CAN_operating_mode
+ * @{
+ */
+#define CAN_Operating_InitMode ((uint8_t)0x00) /*!< Initialization mode */
+#define CAN_Operating_NormalMode ((uint8_t)0x01) /*!< Normal mode */
+#define CAN_Operating_SleepMode ((uint8_t)0x02) /*!< sleep mode */
+
+#define IS_CAN_OPERATING_MODE(MODE) \
+ (((MODE) == CAN_Operating_InitMode) || ((MODE) == CAN_Operating_NormalMode) || ((MODE) == CAN_Operating_SleepMode))
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup CAN_Mode_Status
+ * @{
+ */
+
+#define CAN_ModeSTS_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */
+#define CAN_ModeSTS_Success ((uint8_t)!CAN_ModeSTS_Failed) /*!< CAN entering the specific mode Succeed */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_synchronisation_jump_width
+ * @{
+ */
+
+#define CAN_RSJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_RSJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_RSJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_RSJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+
+#define IS_CAN_RSJW(SJW) \
+ (((SJW) == CAN_RSJW_1tq) || ((SJW) == CAN_RSJW_2tq) || ((SJW) == CAN_RSJW_3tq) || ((SJW) == CAN_RSJW_4tq))
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_time_quantum_in_bit_segment_1
+ * @{
+ */
+
+#define CAN_TBS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_TBS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_TBS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_TBS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+#define CAN_TBS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */
+#define CAN_TBS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */
+#define CAN_TBS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */
+#define CAN_TBS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */
+#define CAN_TBS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */
+#define CAN_TBS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */
+#define CAN_TBS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */
+#define CAN_TBS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */
+#define CAN_TBS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */
+#define CAN_TBS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */
+#define CAN_TBS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */
+#define CAN_TBS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */
+
+#define IS_CAN_TBS1(BS1) ((BS1) <= CAN_TBS1_16tq)
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_time_quantum_in_bit_segment_2
+ * @{
+ */
+
+#define CAN_TBS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_TBS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_TBS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_TBS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+#define CAN_TBS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */
+#define CAN_TBS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */
+#define CAN_TBS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */
+#define CAN_TBS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */
+
+#define IS_CAN_TBS2(BS2) ((BS2) <= CAN_TBS2_8tq)
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_clock_prescaler
+ * @{
+ */
+
+#define IS_CAN_BAUDRATEPRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_filter_number
+ * @{
+ */
+#define IS_CAN_FILTER_NUM(NUMBER) ((NUMBER) <= 13)
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_filter_mode
+ * @{
+ */
+
+#define CAN_Filter_IdMaskMode ((uint8_t)0x00) /*!< identifier/mask mode */
+#define CAN_Filter_IdListMode ((uint8_t)0x01) /*!< identifier list mode */
+
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_Filter_IdMaskMode) || ((MODE) == CAN_Filter_IdListMode))
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_filter_scale
+ * @{
+ */
+
+#define CAN_Filter_16bitScale ((uint8_t)0x00) /*!< Two 16-bit filters */
+#define CAN_Filter_32bitScale ((uint8_t)0x01) /*!< One 32-bit filter */
+
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_Filter_16bitScale) || ((SCALE) == CAN_Filter_32bitScale))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_filter_FIFO
+ * @{
+ */
+
+#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter DATFIFO 0 assignment for filter x */
+#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter DATFIFO 1 assignment for filter x */
+#define IS_CAN_FILTER_FIFO(DATFIFO) (((DATFIFO) == CAN_FilterFIFO0) || ((DATFIFO) == CAN_FilterFIFO1))
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Tx
+ * @{
+ */
+
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_identifier_type
+ * @{
+ */
+
+#define CAN_Standard_Id ((uint32_t)0x00000000) /*!< Standard Id */
+#define CAN_Extended_Id ((uint32_t)0x00000004) /*!< Extended Id */
+#define IS_CAN_ID(IDTYPE) (((IDTYPE) == CAN_Standard_Id) || ((IDTYPE) == CAN_Extended_Id))
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_remote_transmission_request
+ * @{
+ */
+
+#define CAN_RTRQ_Data ((uint32_t)0x00000000) /*!< Data frame */
+#define CAN_RTRQ_Remote ((uint32_t)0x00000002) /*!< Remote frame */
+#define IS_CAN_RTRQ(RTR) (((RTR) == CAN_RTRQ_Data) || ((RTR) == CAN_RTRQ_Remote))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_transmit_constants
+ * @{
+ */
+
+#define CAN_TxSTS_Failed ((uint8_t)0x00) /*!< CAN transmission failed */
+#define CAN_TxSTS_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */
+#define CAN_TxSTS_Pending ((uint8_t)0x02) /*!< CAN transmission pending */
+#define CAN_TxSTS_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_receive_FIFO_number_constants
+ * @{
+ */
+
+#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN DATFIFO 0 used to receive */
+#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN DATFIFO 1 used to receive */
+
+#define IS_CAN_FIFO(DATFIFO) (((DATFIFO) == CAN_FIFO0) || ((DATFIFO) == CAN_FIFO1))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_sleep_constants
+ * @{
+ */
+
+#define CAN_SLEEP_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
+#define CAN_SLEEP_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_wake_up_constants
+ * @{
+ */
+
+#define CAN_WKU_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
+#define CAN_WKU_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
+
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup CAN_Error_Code_constants
+ * @{
+ */
+
+#define CAN_ERRCode_NoErr ((uint8_t)0x00) /*!< No Error */
+#define CAN_ERRCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */
+#define CAN_ERRCode_FormErr ((uint8_t)0x20) /*!< Form Error */
+#define CAN_ERRCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */
+#define CAN_ERRCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */
+#define CAN_ERRCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */
+#define CAN_ERRCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */
+#define CAN_ERRCode_SWSetErr ((uint8_t)0x70) /*!< Software Set Error */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_flags
+ * @{
+ */
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagSTS()
+ and CAN_ClearFlag() functions. */
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagSTS() function. */
+
+/* Transmit Flags */
+#define CAN_FLAG_RQCPM0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
+#define CAN_FLAG_RQCPM1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
+#define CAN_FLAG_RQCPM2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
+
+/* Receive Flags */
+#define CAN_FLAG_FFMP0 ((uint32_t)0x12000003) /*!< DATFIFO 0 Message Pending Flag */
+#define CAN_FLAG_FFULL0 ((uint32_t)0x32000008) /*!< DATFIFO 0 Full Flag */
+#define CAN_FLAG_FFOVR0 ((uint32_t)0x32000010) /*!< DATFIFO 0 Overrun Flag */
+#define CAN_FLAG_FFMP1 ((uint32_t)0x14000003) /*!< DATFIFO 1 Message Pending Flag */
+#define CAN_FLAG_FFULL1 ((uint32_t)0x34000008) /*!< DATFIFO 1 Full Flag */
+#define CAN_FLAG_FFOVR1 ((uint32_t)0x34000010) /*!< DATFIFO 1 Overrun Flag */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */
+#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
+/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible.
+ In this case the SLAK bit can be polled.*/
+
+/* Error Flags */
+#define CAN_FLAG_EWGFL ((uint32_t)0x10F00001) /*!< Error Warning Flag */
+#define CAN_FLAG_EPVFL ((uint32_t)0x10F00002) /*!< Error Passive Flag */
+#define CAN_FLAG_BOFFL ((uint32_t)0x10F00004) /*!< Bus-Off Flag */
+#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */
+
+#define IS_CAN_GET_FLAG(FLAG) \
+ (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOFFL) || ((FLAG) == CAN_FLAG_EPVFL) \
+ || ((FLAG) == CAN_FLAG_EWGFL) || ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FFOVR0) \
+ || ((FLAG) == CAN_FLAG_FFULL0) || ((FLAG) == CAN_FLAG_FFMP0) || ((FLAG) == CAN_FLAG_FFOVR1) \
+ || ((FLAG) == CAN_FLAG_FFULL1) || ((FLAG) == CAN_FLAG_FFMP1) || ((FLAG) == CAN_FLAG_RQCPM2) \
+ || ((FLAG) == CAN_FLAG_RQCPM1) || ((FLAG) == CAN_FLAG_RQCPM0) || ((FLAG) == CAN_FLAG_SLAK))
+
+#define IS_CAN_CLEAR_FLAG(FLAG) \
+ (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCPM2) || ((FLAG) == CAN_FLAG_RQCPM1) \
+ || ((FLAG) == CAN_FLAG_RQCPM0) || ((FLAG) == CAN_FLAG_FFULL0) || ((FLAG) == CAN_FLAG_FFOVR0) \
+ || ((FLAG) == CAN_FLAG_FFULL1) || ((FLAG) == CAN_FLAG_FFOVR1) || ((FLAG) == CAN_FLAG_WKU) \
+ || ((FLAG) == CAN_FLAG_SLAK))
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_interrupts
+ * @{
+ */
+
+#define CAN_INT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
+
+/* Receive Interrupts */
+#define CAN_INT_FMP0 ((uint32_t)0x00000002) /*!< DATFIFO 0 message pending Interrupt*/
+#define CAN_INT_FF0 ((uint32_t)0x00000004) /*!< DATFIFO 0 full Interrupt*/
+#define CAN_INT_FOV0 ((uint32_t)0x00000008) /*!< DATFIFO 0 overrun Interrupt*/
+#define CAN_INT_FMP1 ((uint32_t)0x00000010) /*!< DATFIFO 1 message pending Interrupt*/
+#define CAN_INT_FF1 ((uint32_t)0x00000020) /*!< DATFIFO 1 full Interrupt*/
+#define CAN_INT_FOV1 ((uint32_t)0x00000040) /*!< DATFIFO 1 overrun Interrupt*/
+
+/* Operating Mode Interrupts */
+#define CAN_INT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
+#define CAN_INT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
+
+/* Error Interrupts */
+#define CAN_INT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
+#define CAN_INT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
+#define CAN_INT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
+#define CAN_INT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
+#define CAN_INT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/
+
+/* Flags named as Interrupts : kept only for FW compatibility */
+#define CAN_INT_RQCPM0 CAN_INT_TME
+#define CAN_INT_RQCPM1 CAN_INT_TME
+#define CAN_INT_RQCPM2 CAN_INT_TME
+
+#define IS_CAN_INT(IT) \
+ (((IT) == CAN_INT_TME) || ((IT) == CAN_INT_FMP0) || ((IT) == CAN_INT_FF0) || ((IT) == CAN_INT_FOV0) \
+ || ((IT) == CAN_INT_FMP1) || ((IT) == CAN_INT_FF1) || ((IT) == CAN_INT_FOV1) || ((IT) == CAN_INT_EWG) \
+ || ((IT) == CAN_INT_EPV) || ((IT) == CAN_INT_BOF) || ((IT) == CAN_INT_LEC) || ((IT) == CAN_INT_ERR) \
+ || ((IT) == CAN_INT_WKU) || ((IT) == CAN_INT_SLK))
+
+#define IS_CAN_CLEAR_INT(IT) \
+ (((IT) == CAN_INT_TME) || ((IT) == CAN_INT_FF0) || ((IT) == CAN_INT_FOV0) || ((IT) == CAN_INT_FF1) \
+ || ((IT) == CAN_INT_FOV1) || ((IT) == CAN_INT_EWG) || ((IT) == CAN_INT_EPV) || ((IT) == CAN_INT_BOF) \
+ || ((IT) == CAN_INT_LEC) || ((IT) == CAN_INT_ERR) || ((IT) == CAN_INT_WKU) || ((IT) == CAN_INT_SLK))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Legacy
+ * @{
+ */
+#define CANINITSTSFAILED CAN_InitSTS_Failed
+#define CANINITSTSOK CAN_InitSTS_Success
+#define CAN_FilterFIFO0 CAN_Filter_FIFO0
+#define CAN_FilterFIFO1 CAN_Filter_FIFO1
+#define CAN_ID_STD CAN_Standard_Id
+#define CAN_ID_EXT CAN_Extended_Id
+#define CAN_RTRQ_DATA CAN_RTRQ_Data
+#define CAN_RTRQ_REMOTE CAN_RTRQ_Remote
+#define CANTXSTSFAILE CAN_TxSTS_Failed
+#define CANTXSTSOK CAN_TxSTS_Ok
+#define CANTXSTSPENDING CAN_TxSTS_Pending
+#define CAN_STS_NO_MB CAN_TxSTS_NoMailBox
+#define CANSLEEPFAILED CAN_SLEEP_Failed
+#define CANSLEEPOK CAN_SLEEP_Ok
+#define CANWKUFAILED CAN_WKU_Failed
+#define CANWKUOK CAN_WKU_Ok
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions
+ * @{
+ */
+/* Function used to set the CAN configuration to the default reset state *****/
+void CAN_DeInit(CAN_Module* CANx);
+
+/* Initialization and Configuration functions *********************************/
+uint8_t CAN_Init(CAN_Module* CANx, CAN_InitType* CAN_InitParam);
+void CAN_InitFilter(CAN_FilterInitType* CAN_InitFilterStruct);
+void CAN_InitStruct(CAN_InitType* CAN_InitParam);
+void CAN_DebugFreeze(CAN_Module* CANx, FunctionalState Cmd);
+void CAN_EnTTComMode(CAN_Module* CANx, FunctionalState Cmd);
+
+/* Transmit functions *********************************************************/
+uint8_t CAN_TransmitMessage(CAN_Module* CANx, CanTxMessage* TxMessage);
+uint8_t CAN_TransmitSTS(CAN_Module* CANx, uint8_t TransmitMailbox);
+void CAN_CancelTransmitMessage(CAN_Module* CANx, uint8_t Mailbox);
+
+/* Receive functions **********************************************************/
+void CAN_ReceiveMessage(CAN_Module* CANx, uint8_t FIFONum, CanRxMessage* RxMessage);
+void CAN_ReleaseFIFO(CAN_Module* CANx, uint8_t FIFONum);
+uint8_t CAN_PendingMessage(CAN_Module* CANx, uint8_t FIFONum);
+
+/* Operation modes functions **************************************************/
+uint8_t CAN_OperatingModeReq(CAN_Module* CANx, uint8_t CAN_OperatingMode);
+uint8_t CAN_EnterSleep(CAN_Module* CANx);
+uint8_t CAN_WakeUp(CAN_Module* CANx);
+
+/* Error management functions *************************************************/
+uint8_t CAN_GetLastErrCode(CAN_Module* CANx);
+uint8_t CAN_GetReceiveErrCounter(CAN_Module* CANx);
+uint8_t CAN_GetLSBTransmitErrCounter(CAN_Module* CANx);
+
+/* Interrupts and flags management functions **********************************/
+void CAN_INTConfig(CAN_Module* CANx, uint32_t CAN_INT, FunctionalState Cmd);
+FlagStatus CAN_GetFlagSTS(CAN_Module* CANx, uint32_t CAN_FLAG);
+void CAN_ClearFlag(CAN_Module* CANx, uint32_t CAN_FLAG);
+INTStatus CAN_GetIntStatus(CAN_Module* CANx, uint32_t CAN_INT);
+void CAN_ClearINTPendingBit(CAN_Module* CANx, uint32_t CAN_INT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32L43X_CAN_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_comp.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_comp.h
new file mode 100644
index 0000000000..b0d5578ff0
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_comp.h
@@ -0,0 +1,282 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_comp.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L43X_COMP_H__
+#define __N32L43X_COMP_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l43x.h"
+#include
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup COMP
+ * @{
+ */
+
+/** @addtogroup COMP_Exported_Constants
+ * @{
+ */
+typedef enum
+{
+ COMP1 = 0,
+ COMP2 = 1,
+} COMPX;
+
+// COMPx_CTRL
+#define COMP1_CTRL_PWRMODE_MASK (0x01L << 21)
+#define COMP1_CTRL_INPDAC_MASK (0x01L << 20)
+#define COMP_CTRL_OUT_MASK (0x01L << 19)
+#define COMP_CTRL_BLKING_MASK (0x03L << 16)
+typedef enum
+{
+ COMP_CTRL_BLKING_NO = (0x0L << 16),
+ COMP_CTRL_BLKING_TIM1_OC5 = (0x1L << 16),
+ COMP_CTRL_BLKING_TIM8_OC5 = (0x2L << 16),
+} COMP_CTRL_BLKING;
+#define COMPx_CTRL_HYST_MASK (0x03L << 14)
+typedef enum
+{
+ COMP_CTRL_HYST_NO = (0x0L << 14),
+ COMP_CTRL_HYST_LOW = (0x1L << 14),
+ COMP_CTRL_HYST_MID = (0x2L << 14),
+ COMP_CTRL_HYST_HIGH = (0x3L << 14),
+} COMP_CTRL_HYST;
+
+#define COMP_POL_MASK (0x01L << 13)
+#define COMP_CTRL_OUTSEL_MASK (0x0FL << 9)
+typedef enum
+{
+ // comp1 out trig
+ COMP1_CTRL_OUTSEL_NC = (0x0L << 9),
+ COMP1_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 9),
+ COMP1_CTRL_OUTSEL_TIM1_OCrefclear = (0x2L << 9),
+ COMP1_CTRL_OUTSEL_TIM1_IC1 = (0x3L << 9),
+ COMP1_CTRL_OUTSEL_TIM2_IC1 = (0x4L << 9),
+ COMP1_CTRL_OUTSEL_TIM2_OCrefclear = (0x5L << 9),
+ COMP1_CTRL_OUTSEL_TIM3_IC1 = (0x6L << 9),
+ COMP1_CTRL_OUTSEL_TIM3_OCrefclear = (0x7L << 9),
+ COMP1_CTRL_OUTSEL_TIM4_OCrefclear = (0x8L << 9),
+ COMP1_CTRL_OUTSEL_TIM5_IC1 = (0x9L << 9),
+ COMP1_CTRL_OUTSEL_TIM8_IC1 = (0xAL << 9),
+ COMP1_CTRL_OUTSEL_TIM8_OCrefclear = (0xBL << 9),
+ COMP1_CTRL_OUTSEL_TIM9_OCrefclear = (0xCL << 9),
+ COMP1_CTRL_OUTSEL_TIM8_BKIN = (0xDL << 9),
+ COMP1_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xEL << 9),
+ COMP1_CTRL_OUTSEL_LPTIM_ETR = (0xFL << 9),
+ // comp2 out trig
+ COMP2_CTRL_OUTSEL_NC = (0x0L << 9),
+ COMP2_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 9),
+ COMP2_CTRL_OUTSEL_TIM1_OCrefclear = (0x2L << 9),
+ COMP2_CTRL_OUTSEL_TIM1_IC1 = (0x3L << 9),
+ COMP2_CTRL_OUTSEL_TIM2_OCrefclear = (0x4L << 9),
+ COMP2_CTRL_OUTSEL_TIM3_OCrefclear = (0x5L << 9),
+ COMP2_CTRL_OUTSEL_TIM4_IC1 = (0x6L << 9),
+ COMP2_CTRL_OUTSEL_TIM4_OCrefclear = (0x7L << 9),
+ COMP2_CTRL_OUTSEL_TIM5_IC1 = (0x8L << 9),
+ COMP2_CTRL_OUTSEL_TIM8_IC1 = (0x9L << 9),
+ COMP2_CTRL_OUTSEL_TIM8_OCrefclear = (0xAL << 9),
+ COMP2_CTRL_OUTSEL_TIM9_IC1 = (0xBL << 9),
+ COMP2_CTRL_OUTSEL_TIM9_OCrefclear = (0xCL << 9),
+ COMP2_CTRL_OUTSEL_TIM8_BKIN = (0xDL << 9),
+ COMP2_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xEL << 9),
+ COMP2_CTRL_OUTSEL_LPTIM_ETR = (0xFL << 9),
+} COMP_CTRL_OUTTRIG;
+
+#define COMP_CTRL_INPSEL_MASK (0x0FL<<5)
+typedef enum {
+ //comp1 inp sel
+ COMP1_CTRL_INPSEL_FLOAT = ((uint32_t)0x00000000),
+ COMP1_CTRL_INPSEL_PA0 = ((uint32_t)0x00000100),
+ COMP1_CTRL_INPSEL_PA2 = ((uint32_t)0x00000140),
+ COMP1_CTRL_INPSEL_PA12 = ((uint32_t)0x00000160),
+ COMP1_CTRL_INPSEL_PB3 = ((uint32_t)0x00000180),
+ COMP1_CTRL_INPSEL_PB4 = ((uint32_t)0x000001A0),
+ COMP1_CTRL_INPSEL_PB10 = ((uint32_t)0x000001C0),
+ COMP1_CTRL_INPSEL_PD5 = ((uint32_t)0x000001E0),
+ COMP1_CTRL_INPSEL_PA1_DAC1 = ((uint32_t)0x00000120),
+ //comp2 inp sel
+ COMP2_CTRL_INPSEL_FLOAT = ((uint32_t)0x00000000),
+ COMP2_CTRL_INPSEL_PA1_DAC1_PA4= ((uint32_t)0x00000100),
+ COMP2_CTRL_INPSEL_PA3 = ((uint32_t)0x00000120),
+ COMP2_CTRL_INPSEL_PA6 = ((uint32_t)0x00000140),
+ COMP2_CTRL_INPSEL_PA7 = ((uint32_t)0x00000160),
+ COMP2_CTRL_INPSEL_PA11 = ((uint32_t)0x00000180),
+ COMP2_CTRL_INPSEL_PA15 = ((uint32_t)0x000001A0),
+ COMP2_CTRL_INPSEL_PB7 = ((uint32_t)0x000001C0),
+ COMP2_CTRL_INPSEL_PD7 = ((uint32_t)0x000001E0),
+}COMP_CTRL_INPSEL;
+
+
+#define COMP_CTRL_INMSEL_MASK (0x07L<<1)
+typedef enum {
+ //comp1 inm sel
+ COMP1_CTRL_INMSEL_DAC1_PA4 = ((uint32_t)0x00000002),
+ COMP1_CTRL_INMSEL_PA0 = ((uint32_t)0x00000004),
+ COMP1_CTRL_INMSEL_PA5 = ((uint32_t)0x00000006),
+ COMP1_CTRL_INMSEL_PB5 = ((uint32_t)0x00000008),
+ COMP1_CTRL_INMSEL_PD4 = ((uint32_t)0x0000000A),
+ COMP1_CTRL_INMSEL_VREF_VC1 = ((uint32_t)0x0000000C),
+ COMP1_CTRL_INMSEL_VREF_VC2 = ((uint32_t)0x0000000E),
+ COMP1_CTRL_INMSEL_NC = ((uint32_t)0x00000000),
+ //comp2 inm sel
+ COMP2_CTRL_INMSEL_PA2 = ((uint32_t)0x00000002),
+ COMP2_CTRL_INMSEL_PA5 = ((uint32_t)0x00000004),
+ COMP2_CTRL_INMSEL_PA6 = ((uint32_t)0x00000006),
+ COMP2_CTRL_INMSEL_PB3 = ((uint32_t)0x00000008),
+ COMP2_CTRL_INMSEL_PD6 = ((uint32_t)0x0000000A),
+ COMP2_CTRL_INMSEL_DAC1_PA4 = ((uint32_t)0x0000000C),
+ COMP2_CTRL_INMSEL_VREF_VC2 = ((uint32_t)0x0000000E),
+ COMP2_CTRL_INMSEL_NC = ((uint32_t)0x00000000),
+}COMP_CTRL_INMSEL;
+
+#define COMP_CTRL_EN_MASK (0x01L << 0)
+
+//COMPx_FILC
+#define COMP_FILC_SAMPW_MASK (0x1FL<<6)//Low filter sample window size. Number of samples to monitor is SAMPWIN+1.
+#define COMP_FILC_THRESH_MASK (0x1FL<<1)//For proper operation, the value of THRESH must be greater than SAMPWIN / 2.
+#define COMP_FILC_FILEN_MASK (0x01L<<0)//Filter enable.
+
+//COMPx_FILP
+#define COMP_FILP_CLKPSC_MASK (0xFFFFL)//Prescale number .
+
+//COMP_WINMODE @addtogroup COMP_WINMODE_CMPMD
+#define COMP_WINMODE_CMP12MD (0x01L <<0)//1: Comparators 1 and 2 can be used in window mode.
+
+//COMP_INTEN @addtogroup COMP_INTEN_CMPIEN
+#define COMP_INTEN_CMPIEN_MSK (0x3L << 0) // This bit control Interrput enable of COMP.
+#define COMP_INTEN_CMP2IEN (0x01L << 1)
+#define COMP_INTEN_CMP1IEN (0x01L << 0)
+
+//COMP_INTSTS @addtogroup COMP_INTSTS_CMPIS
+#define COMP_INTSTS_INTSTS_MSK (0x3L << 0) // This bit control Interrput enable of COMP.
+#define COMP_INTSTS_CMP2IS (0x01L << 1)
+#define COMP_INTSTS_CMP1IS (0x01L << 0)
+
+//COMP_VREFSCL @addtogroup COMP_VREFSCL
+#define COMP_VREFSCL_VV2TRM_MSK (0x3FL << 8) // Vref2 Voltage scaler triming value.
+#define COMP_VREFSCL_VV2EN_MSK (0x01L << 7)
+#define COMP_VREFSCL_VV1TRM_MSK (0x3FL << 1) // Vref1 Voltage scaler triming value.
+#define COMP_VREFSCL_VV1EN_MSK (0x01L << 0)
+
+//COMP_LOCK @addtogroup COMP_LOCK
+#define COMP_LOCK_CMP2LK (0x1L << 1) // Vref1 Voltage scaler triming value.
+#define COMP_LOCK_CMP1LK (0x1L << 0)
+
+//COMP_LPCKSEL @addtogroup COMP_LPCKSEL
+#define COMP_LKCKSEL_LPCLKSEL (0x1L << 0)
+
+//COMP_OSEL @addtogroup COMP_OSEL
+#define COMP_OSEL_CMP2XO (0x1L << 0)
+
+/**
+ * @}
+ */
+
+/**
+ * @brief COMP Init structure definition
+ */
+
+typedef struct
+{
+ // ctrl
+ bool LowPoweMode; // only COMP1 have this bit
+ bool InpDacConnect; // only COMP1 have this bit
+
+ COMP_CTRL_BLKING Blking; /*see @ref COMP_CTRL_BLKING */
+
+ COMP_CTRL_HYST Hyst;
+
+ bool PolRev; // out polarity reverse
+
+ COMP_CTRL_OUTTRIG OutTrig;
+ COMP_CTRL_INPSEL InpSel;
+ COMP_CTRL_INMSEL InmSel;
+
+ bool En;
+
+ // filter
+ uint8_t SampWindow; // 5bit
+ uint8_t Thresh; // 5bit ,need > SampWindow/2
+ bool FilterEn;
+
+ // filter psc
+ uint16_t ClkPsc;
+} COMP_InitType;
+
+/** @addtogroup COMP_Exported_Functions
+ * @{
+ */
+
+void COMP_DeInit(void);
+void COMP_StructInit(COMP_InitType* COMP_InitStruct);
+void COMP_Init(COMPX COMPx, COMP_InitType* COMP_InitStruct);
+void COMP_Enable(COMPX COMPx, FunctionalState en);
+void COMP_SetInpSel(COMPX COMPx, COMP_CTRL_INPSEL VpSel);
+void COMP_SetInmSel(COMPX COMPx, COMP_CTRL_INMSEL VmSel);
+void COMP_SetOutTrig(COMPX COMPx, COMP_CTRL_OUTTRIG OutTrig);
+uint32_t COMP_GetIntSts(void); // return see @COMP_INTSTS_CMPIS
+void COMP_SetRefScl(uint8_t Vv2Trim, bool Vv2En, uint8_t Vv1Trim, bool Vv1En); // parma range see @COMP_VREFSCL
+FlagStatus COMP_GetOutStatus(COMPX COMPx);
+FlagStatus COMP_GetIntStsOneComp(COMPX COMPx);
+void COMP_SetLock(uint32_t Lock); // see @COMP_LOCK_CMPLK
+void COMP_SetIntEn(uint32_t IntEn); // see @COMP_INTEN_CMPIEN
+void COMP_CMP2XorOut(bool En);
+void COMP_StopOrLowpower32KClkSel(bool En);
+void COMP_WindowModeEn(bool En);
+void COMP_SetFilterPrescaler(COMPX COMPx , uint16_t FilPreVal);
+void COMP_SetFilterControl(COMPX COMPx , uint8_t FilEn, uint8_t TheresNum , uint8_t SampPW);
+void COMP_SetHyst(COMPX COMPx , COMP_CTRL_HYST HYST);
+void COMP_SetBlanking(COMPX COMPx , COMP_CTRL_BLKING BLK);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32L43X_ADC_H */
+/**
+ * @}
+ */
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_crc.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_crc.h
new file mode 100644
index 0000000000..a941691cbe
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_crc.h
@@ -0,0 +1,105 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_crc.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L43X_CRC_H__
+#define __N32L43X_CRC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l43x.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CRC
+ * @{
+ */
+
+/** @addtogroup CRC_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Exported_Functions
+ * @{
+ */
+
+void CRC32_ResetCrc(void);
+uint32_t CRC32_CalcCrc(uint32_t Data);
+uint32_t CRC32_CalcBufCrc(uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t CRC32_GetCrc(void);
+void CRC32_SetIDat(uint8_t IDValue);
+uint8_t CRC32_GetIDat(void);
+
+uint16_t CRC16_CalcBufCrc(uint8_t pBuffer[], uint32_t BufferLength);
+uint16_t CRC16_CalcCRC(uint8_t Data);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32L43X_CRC_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_dac.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_dac.h
new file mode 100644
index 0000000000..d5c6538cf8
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_dac.h
@@ -0,0 +1,293 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_dac.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L43X_DAC_H__
+#define __N32L43X_DAC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l43x.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DAC
+ * @{
+ */
+
+/** @addtogroup DAC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief DAC Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t Trigger; /*!< Specifies the external trigger for the selected DAC channel.
+ This parameter can be a value of @ref DAC_trigger_selection */
+
+ uint32_t WaveGen; /*!< Specifies whether DAC channel noise waves or triangle waves
+ are generated, or whether no wave is generated.
+ This parameter can be a value of @ref DAC_wave_generation */
+
+ uint32_t
+ LfsrUnMaskTriAmp; /*!< Specifies the LFSR mask for noise wave generation or
+ the maximum amplitude triangle generation for the DAC channel.
+ This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
+
+ uint32_t BufferOutput; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+ This parameter can be a value of @ref DAC_output_buffer */
+} DAC_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup DAC_trigger_selection
+ * @{
+ */
+
+#define DAC_TRG_NONE \
+ ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register \
+ has been loaded, and not by external trigger */
+#define DAC_TRG_T6_TRGO \
+ ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel \
+ */
+#define DAC_TRG_T8_TRGO \
+ ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel \
+ only in High-density devices*/
+#define DAC_TRG_T7_TRGO \
+ ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel \
+ */
+#define DAC_TRG_T5_TRGO \
+ ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel \
+ */
+#define DAC_TRG_T2_TRGO \
+ ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel \
+ */
+#define DAC_TRG_T4_TRGO \
+ ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel \
+ */
+#define DAC_TRG_EXT_IT9 \
+ ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRG_SOFTWARE ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER) \
+ (((TRIGGER) == DAC_TRG_NONE) || ((TRIGGER) == DAC_TRG_T6_TRGO) || ((TRIGGER) == DAC_TRG_T8_TRGO) \
+ || ((TRIGGER) == DAC_TRG_T7_TRGO) || ((TRIGGER) == DAC_TRG_T5_TRGO) || ((TRIGGER) == DAC_TRG_T2_TRGO) \
+ || ((TRIGGER) == DAC_TRG_T4_TRGO) || ((TRIGGER) == DAC_TRG_EXT_IT9) || ((TRIGGER) == DAC_TRG_SOFTWARE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_wave_generation
+ * @{
+ */
+
+#define DAC_WAVEGEN_NONE ((uint32_t)0x00000000)
+#define DAC_WAVEGEN_NOISE ((uint32_t)0x00000040)
+#define DAC_WAVEGEN_TRIANGLE ((uint32_t)0x00000080)
+#define IS_DAC_GENERATE_WAVE(WAVE) \
+ (((WAVE) == DAC_WAVEGEN_NONE) || ((WAVE) == DAC_WAVEGEN_NOISE) || ((WAVE) == DAC_WAVEGEN_TRIANGLE))
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_lfsrunmask_triangleamplitude
+ * @{
+ */
+
+#define DAC_UNMASK_LFSRBIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_UNMASK_LFSRBITS1_0 \
+ ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS2_0 \
+ ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS3_0 \
+ ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS4_0 \
+ ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS5_0 \
+ ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS6_0 \
+ ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS7_0 \
+ ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS8_0 \
+ ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS9_0 \
+ ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS10_0 \
+ ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_UNMASK_LFSRBITS11_0 \
+ ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TRIAMP_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TRIAMP_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
+#define DAC_TRIAMP_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
+#define DAC_TRIAMP_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
+#define DAC_TRIAMP_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
+#define DAC_TRIAMP_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
+#define DAC_TRIAMP_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
+#define DAC_TRIAMP_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
+#define DAC_TRIAMP_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
+#define DAC_TRIAMP_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TRIAMP_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TRIAMP_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) \
+ (((VALUE) == DAC_UNMASK_LFSRBIT0) || ((VALUE) == DAC_UNMASK_LFSRBITS1_0) || ((VALUE) == DAC_UNMASK_LFSRBITS2_0) \
+ || ((VALUE) == DAC_UNMASK_LFSRBITS3_0) || ((VALUE) == DAC_UNMASK_LFSRBITS4_0) \
+ || ((VALUE) == DAC_UNMASK_LFSRBITS5_0) || ((VALUE) == DAC_UNMASK_LFSRBITS6_0) \
+ || ((VALUE) == DAC_UNMASK_LFSRBITS7_0) || ((VALUE) == DAC_UNMASK_LFSRBITS8_0) \
+ || ((VALUE) == DAC_UNMASK_LFSRBITS9_0) || ((VALUE) == DAC_UNMASK_LFSRBITS10_0) \
+ || ((VALUE) == DAC_UNMASK_LFSRBITS11_0) || ((VALUE) == DAC_TRIAMP_1) || ((VALUE) == DAC_TRIAMP_3) \
+ || ((VALUE) == DAC_TRIAMP_7) || ((VALUE) == DAC_TRIAMP_15) || ((VALUE) == DAC_TRIAMP_31) \
+ || ((VALUE) == DAC_TRIAMP_63) || ((VALUE) == DAC_TRIAMP_127) || ((VALUE) == DAC_TRIAMP_255) \
+ || ((VALUE) == DAC_TRIAMP_511) || ((VALUE) == DAC_TRIAMP_1023) || ((VALUE) == DAC_TRIAMP_2047) \
+ || ((VALUE) == DAC_TRIAMP_4095))
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_output_buffer
+ * @{
+ */
+
+#define DAC_BUFFOUTPUT_ENABLE ((uint32_t)0x00000002)
+#define DAC_BUFFOUTPUT_DISABLE ((uint32_t)0x00000000)
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_BUFFOUTPUT_ENABLE) || ((STATE) == DAC_BUFFOUTPUT_DISABLE))
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_data_alignment
+ * @{
+ */
+
+#define DAC_ALIGN_R_12BIT ((uint32_t)0x00000000)
+#define DAC_ALIGN_L_12BIT ((uint32_t)0x00000004)
+#define DAC_ALIGN_R_8BIT ((uint32_t)0x00000008)
+#define IS_DAC_ALIGN(ALIGN) \
+ (((ALIGN) == DAC_ALIGN_R_12BIT) || ((ALIGN) == DAC_ALIGN_L_12BIT) || ((ALIGN) == DAC_ALIGN_R_8BIT))
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_wave_generation
+ * @{
+ */
+
+#define DAC_WAVE_NOISE ((uint32_t)0x00000040)
+#define DAC_WAVE_TRIANGLE ((uint32_t)0x00000080)
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NOISE) || ((WAVE) == DAC_WAVE_TRIANGLE))
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_data
+ * @{
+ */
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Functions
+ * @{
+ */
+
+void DAC_DeInit(void);
+void DAC_Init(DAC_InitType* DAC_InitStruct);
+void DAC_ClearStruct(DAC_InitType* DAC_InitStruct);
+void DAC_Enable(FunctionalState Cmd);
+
+void DAC_DmaEnable(FunctionalState Cmd);
+void DAC_SoftTrgEnable(FunctionalState Cmd);
+void DAC_SoftwareTrgEnable(FunctionalState Cmd);
+void DAC_WaveGenerationEnable(uint32_t DAC_Wave, FunctionalState Cmd);
+void DAC_SetChData(uint32_t DAC_Align, uint16_t Data);
+uint16_t DAC_GetOutputDataVal(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32L43X_DAC_H__ */
+ /**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_dbg.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_dbg.h
new file mode 100644
index 0000000000..917893b262
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_dbg.h
@@ -0,0 +1,124 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_dbg.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L43X_DBG_H__
+#define __N32L43X_DBG_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l43x.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DBG
+ * @{
+ */
+
+/** @addtogroup DBGMCU_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Exported_Constants
+ * @{
+ */
+
+#define DBG_SLEEP ((uint32_t)0x00000001)
+#define DBG_STOP ((uint32_t)0x00000002)
+#define DBG_STDBY ((uint32_t)0x00000004)
+#define DBG_IWDG_STOP ((uint32_t)0x00000100)
+#define DBG_WWDG_STOP ((uint32_t)0x00000200)
+#define DBG_TIM1_STOP ((uint32_t)0x00000400)
+#define DBG_TIM2_STOP ((uint32_t)0x00000800)
+#define DBG_TIM3_STOP ((uint32_t)0x00001000)
+#define DBG_TIM4_STOP ((uint32_t)0x00002000)
+#define DBG_CAN_STOP ((uint32_t)0x00004000)
+#define DBG_I2C1SMBUS_TIMEOUT ((uint32_t)0x00008000)
+#define DBG_I2C2SMBUS_TIMEOUT ((uint32_t)0x00010000)
+#define DBG_TIM8_STOP ((uint32_t)0x00020000)
+#define DBG_TIM5_STOP ((uint32_t)0x00040000)
+#define DBG_TIM6_STOP ((uint32_t)0x00080000)
+#define DBG_TIM7_STOP ((uint32_t)0x00100000)
+#define DBG_TIM9_STOP ((uint32_t)0x00200000)
+
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH)&0xFFC000F8) == 0x00) && ((PERIPH) != 0x00))
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Exported_Functions
+ * @{
+ */
+
+void GetUCID(uint8_t *UCIDbuf);
+void GetUID(uint8_t *UIDbuf);
+void GetDBGMCU_ID(uint8_t *DBGMCU_IDbuf);
+uint32_t DBG_GetRevNum(void);
+uint32_t DBG_GetDevNum(void);
+void DBG_ConfigPeriph(uint32_t DBG_Periph, FunctionalState Cmd);
+
+uint32_t DBG_GetFlashSize(void);
+uint32_t DBG_GetSramSize(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32L43X_DBG_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_dma.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_dma.h
new file mode 100644
index 0000000000..ef15e5f995
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_dma.h
@@ -0,0 +1,469 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_dma.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L43X_DMA_H__
+#define __N32L43X_DMA_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l43x.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @{
+ */
+
+/** @addtogroup DMA_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief DMA Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t PeriphAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
+
+ uint32_t MemAddr; /*!< Specifies the memory base address for DMAy Channelx. */
+
+ uint32_t Direction; /*!< Specifies if the peripheral is the source or destination.
+ This parameter can be a value of @ref DMA_data_transfer_direction */
+
+ uint32_t BufSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
+ The data unit is equal to the configuration set in PeriphDataSize
+ or MemDataSize members depending in the transfer direction. */
+
+ uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register is incremented or not.
+ This parameter can be a value of @ref DMA_peripheral_incremented_mode */
+
+ uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
+ This parameter can be a value of @ref DMA_memory_incremented_mode */
+
+ uint32_t PeriphDataSize; /*!< Specifies the Peripheral data width.
+ This parameter can be a value of @ref DMA_peripheral_data_size */
+
+ uint32_t MemDataSize; /*!< Specifies the Memory data width.
+ This parameter can be a value of @ref DMA_memory_data_size */
+
+ uint32_t CircularMode; /*!< Specifies the operation mode of the DMAy Channelx.
+ This parameter can be a value of @ref DMA_circular_normal_mode.
+ @note: The circular buffer mode cannot be used if the memory-to-memory
+ data transfer is configured on the selected Channel */
+
+ uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
+ This parameter can be a value of @ref DMA_priority_level */
+
+ uint32_t Mem2Mem; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
+ This parameter can be a value of @ref DMA_memory_to_memory */
+} DMA_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Constants
+ * @{
+ */
+
+#define IS_DMA_ALL_PERIPH(PERIPH) \
+ (((PERIPH) == DMA_CH1) || ((PERIPH) == DMA_CH2) || ((PERIPH) == DMA_CH3) || ((PERIPH) == DMA_CH4) \
+ || ((PERIPH) == DMA_CH5) || ((PERIPH) == DMA_CH6) || ((PERIPH) == DMA_CH7) || ((PERIPH) == DMA_CH8))
+
+/** @addtogroup DMA_data_transfer_direction
+ * @{
+ */
+
+#define DMA_DIR_PERIPH_DST ((uint32_t)0x00000010)
+#define DMA_DIR_PERIPH_SRC ((uint32_t)0x00000000)
+#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PERIPH_DST) || ((DIR) == DMA_DIR_PERIPH_SRC))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_peripheral_incremented_mode
+ * @{
+ */
+
+#define DMA_PERIPH_INC_ENABLE ((uint32_t)0x00000040)
+#define DMA_PERIPH_INC_DISABLE ((uint32_t)0x00000000)
+#define IS_DMA_PERIPH_INC_STATE(STATE) (((STATE) == DMA_PERIPH_INC_ENABLE) || ((STATE) == DMA_PERIPH_INC_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_memory_incremented_mode
+ * @{
+ */
+
+#define DMA_MEM_INC_ENABLE ((uint32_t)0x00000080)
+#define DMA_MEM_INC_DISABLE ((uint32_t)0x00000000)
+#define IS_DMA_MEM_INC_STATE(STATE) (((STATE) == DMA_MEM_INC_ENABLE) || ((STATE) == DMA_MEM_INC_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_peripheral_data_size
+ * @{
+ */
+
+#define DMA_PERIPH_DATA_SIZE_BYTE ((uint32_t)0x00000000)
+#define DMA_PERIPH_DATA_SIZE_HALFWORD ((uint32_t)0x00000100)
+#define DMA_PERIPH_DATA_SIZE_WORD ((uint32_t)0x00000200)
+#define IS_DMA_PERIPH_DATA_SIZE(SIZE) \
+ (((SIZE) == DMA_PERIPH_DATA_SIZE_BYTE) || ((SIZE) == DMA_PERIPH_DATA_SIZE_HALFWORD) \
+ || ((SIZE) == DMA_PERIPH_DATA_SIZE_WORD))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_memory_data_size
+ * @{
+ */
+
+#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
+#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
+#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) \
+ (((SIZE) == DMA_MemoryDataSize_Byte) || ((SIZE) == DMA_MemoryDataSize_HalfWord) \
+ || ((SIZE) == DMA_MemoryDataSize_Word))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_circular_normal_mode
+ * @{
+ */
+
+#define DMA_MODE_CIRCULAR ((uint32_t)0x00000020)
+#define DMA_MODE_NORMAL ((uint32_t)0x00000000)
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_MODE_CIRCULAR) || ((MODE) == DMA_MODE_NORMAL))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_priority_level
+ * @{
+ */
+
+#define DMA_PRIORITY_VERY_HIGH ((uint32_t)0x00003000)
+#define DMA_PRIORITY_HIGH ((uint32_t)0x00002000)
+#define DMA_PRIORITY_MEDIUM ((uint32_t)0x00001000)
+#define DMA_PRIORITY_LOW ((uint32_t)0x00000000)
+#define IS_DMA_PRIORITY(PRIORITY) \
+ (((PRIORITY) == DMA_PRIORITY_VERY_HIGH) || ((PRIORITY) == DMA_PRIORITY_HIGH) \
+ || ((PRIORITY) == DMA_PRIORITY_MEDIUM) || ((PRIORITY) == DMA_PRIORITY_LOW))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_memory_to_memory
+ * @{
+ */
+
+#define DMA_M2M_ENABLE ((uint32_t)0x00004000)
+#define DMA_M2M_DISABLE ((uint32_t)0x00000000)
+#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_ENABLE) || ((STATE) == DMA_M2M_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_interrupts_definition
+ * @{
+ */
+
+#define DMA_INT_TXC ((uint32_t)0x00000002)
+#define DMA_INT_HTX ((uint32_t)0x00000004)
+#define DMA_INT_ERR ((uint32_t)0x00000008)
+#define IS_DMA_CONFIG_INT(IT) ((((IT)&0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
+
+#define DMA_INT_GLB1 ((uint32_t)0x00000001)
+#define DMA_INT_TXC1 ((uint32_t)0x00000002)
+#define DMA_INT_HTX1 ((uint32_t)0x00000004)
+#define DMA_INT_ERR1 ((uint32_t)0x00000008)
+#define DMA_INT_GLB2 ((uint32_t)0x00000010)
+#define DMA_INT_TXC2 ((uint32_t)0x00000020)
+#define DMA_INT_HTX2 ((uint32_t)0x00000040)
+#define DMA_INT_ERR2 ((uint32_t)0x00000080)
+#define DMA_INT_GLB3 ((uint32_t)0x00000100)
+#define DMA_INT_TXC3 ((uint32_t)0x00000200)
+#define DMA_INT_HTX3 ((uint32_t)0x00000400)
+#define DMA_INT_ERR3 ((uint32_t)0x00000800)
+#define DMA_INT_GLB4 ((uint32_t)0x00001000)
+#define DMA_INT_TXC4 ((uint32_t)0x00002000)
+#define DMA_INT_HTX4 ((uint32_t)0x00004000)
+#define DMA_INT_ERR4 ((uint32_t)0x00008000)
+#define DMA_INT_GLB5 ((uint32_t)0x00010000)
+#define DMA_INT_TXC5 ((uint32_t)0x00020000)
+#define DMA_INT_HTX5 ((uint32_t)0x00040000)
+#define DMA_INT_ERR5 ((uint32_t)0x00080000)
+#define DMA_INT_GLB6 ((uint32_t)0x00100000)
+#define DMA_INT_TXC6 ((uint32_t)0x00200000)
+#define DMA_INT_HTX6 ((uint32_t)0x00400000)
+#define DMA_INT_ERR6 ((uint32_t)0x00800000)
+#define DMA_INT_GLB7 ((uint32_t)0x01000000)
+#define DMA_INT_TXC7 ((uint32_t)0x02000000)
+#define DMA_INT_HTX7 ((uint32_t)0x04000000)
+#define DMA_INT_ERR7 ((uint32_t)0x08000000)
+#define DMA_INT_GLB8 ((uint32_t)0x10000000)
+#define DMA_INT_TXC8 ((uint32_t)0x20000000)
+#define DMA_INT_HTX8 ((uint32_t)0x40000000)
+#define DMA_INT_ERR8 ((uint32_t)0x80000000)
+
+
+#define IS_DMA_CLR_INT(IT) ((IT) != 0x00)
+
+#define IS_DMA_GET_IT(IT) \
+ (((IT) == DMA_INT_GLB1) || ((IT) == DMA_INT_TXC1) || ((IT) == DMA_INT_HTX1) || ((IT) == DMA_INT_ERR1) \
+ || ((IT) == DMA_INT_GLB2) || ((IT) == DMA_INT_TXC2) || ((IT) == DMA_INT_HTX2) || ((IT) == DMA_INT_ERR2) \
+ || ((IT) == DMA_INT_GLB3) || ((IT) == DMA_INT_TXC3) || ((IT) == DMA_INT_HTX3) || ((IT) == DMA_INT_ERR3) \
+ || ((IT) == DMA_INT_GLB4) || ((IT) == DMA_INT_TXC4) || ((IT) == DMA_INT_HTX4) || ((IT) == DMA_INT_ERR4) \
+ || ((IT) == DMA_INT_GLB5) || ((IT) == DMA_INT_TXC5) || ((IT) == DMA_INT_HTX5) || ((IT) == DMA_INT_ERR5) \
+ || ((IT) == DMA_INT_GLB6) || ((IT) == DMA_INT_TXC6) || ((IT) == DMA_INT_HTX6) || ((IT) == DMA_INT_ERR6) \
+ || ((IT) == DMA_INT_GLB7) || ((IT) == DMA_INT_TXC7) || ((IT) == DMA_INT_HTX7) || ((IT) == DMA_INT_ERR7) \
+ || ((IT) == DMA_INT_GLB8) || ((IT) == DMA_INT_TXC8) || ((IT) == DMA_INT_HTX8) || ((IT) == DMA_INT_ERR8))
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_flags_definition
+ * @{
+ */
+#define DMA_FLAG_GL1 ((uint32_t)0x00000001)
+#define DMA_FLAG_TC1 ((uint32_t)0x00000002)
+#define DMA_FLAG_HT1 ((uint32_t)0x00000004)
+#define DMA_FLAG_TE1 ((uint32_t)0x00000008)
+#define DMA_FLAG_GL2 ((uint32_t)0x00000010)
+#define DMA_FLAG_TC2 ((uint32_t)0x00000020)
+#define DMA_FLAG_HT2 ((uint32_t)0x00000040)
+#define DMA_FLAG_TE2 ((uint32_t)0x00000080)
+#define DMA_FLAG_GL3 ((uint32_t)0x00000100)
+#define DMA_FLAG_TC3 ((uint32_t)0x00000200)
+#define DMA_FLAG_HT3 ((uint32_t)0x00000400)
+#define DMA_FLAG_TE3 ((uint32_t)0x00000800)
+#define DMA_FLAG_GL4 ((uint32_t)0x00001000)
+#define DMA_FLAG_TC4 ((uint32_t)0x00002000)
+#define DMA_FLAG_HT4 ((uint32_t)0x00004000)
+#define DMA_FLAG_TE4 ((uint32_t)0x00008000)
+#define DMA_FLAG_GL5 ((uint32_t)0x00010000)
+#define DMA_FLAG_TC5 ((uint32_t)0x00020000)
+#define DMA_FLAG_HT5 ((uint32_t)0x00040000)
+#define DMA_FLAG_TE5 ((uint32_t)0x00080000)
+#define DMA_FLAG_GL6 ((uint32_t)0x00100000)
+#define DMA_FLAG_TC6 ((uint32_t)0x00200000)
+#define DMA_FLAG_HT6 ((uint32_t)0x00400000)
+#define DMA_FLAG_TE6 ((uint32_t)0x00800000)
+#define DMA_FLAG_GL7 ((uint32_t)0x01000000)
+#define DMA_FLAG_TC7 ((uint32_t)0x02000000)
+#define DMA_FLAG_HT7 ((uint32_t)0x04000000)
+#define DMA_FLAG_TE7 ((uint32_t)0x08000000)
+#define DMA_FLAG_GL8 ((uint32_t)0x10000000)
+#define DMA_FLAG_TC8 ((uint32_t)0x20000000)
+#define DMA_FLAG_HT8 ((uint32_t)0x40000000)
+#define DMA_FLAG_TE8 ((uint32_t)0x80000000)
+
+#define IS_DMA_CLEAR_FLAG(FLAG) ((FLAG) != 0x00)
+
+#define IS_DMA_GET_FLAG(FLAG) \
+ (((FLAG) == DMA_FLAG_GL1) || ((FLAG) == DMA_FLAG_TC1) || ((FLAG) == DMA_FLAG_HT1) || ((FLAG) == DMA_FLAG_TE1) \
+ || ((FLAG) == DMA_FLAG_GL2) || ((FLAG) == DMA_FLAG_TC2) || ((FLAG) == DMA_FLAG_HT2) \
+ || ((FLAG) == DMA_FLAG_TE2) || ((FLAG) == DMA_FLAG_GL3) || ((FLAG) == DMA_FLAG_TC3) \
+ || ((FLAG) == DMA_FLAG_HT3) || ((FLAG) == DMA_FLAG_TE3) || ((FLAG) == DMA_FLAG_GL4) \
+ || ((FLAG) == DMA_FLAG_TC4) || ((FLAG) == DMA_FLAG_HT4) || ((FLAG) == DMA_FLAG_TE4) \
+ || ((FLAG) == DMA_FLAG_GL5) || ((FLAG) == DMA_FLAG_TC5) || ((FLAG) == DMA_FLAG_HT5) \
+ || ((FLAG) == DMA_FLAG_TE5) || ((FLAG) == DMA_FLAG_GL6) || ((FLAG) == DMA_FLAG_TC6) \
+ || ((FLAG) == DMA_FLAG_HT6) || ((FLAG) == DMA_FLAG_TE6) || ((FLAG) == DMA_FLAG_GL7) \
+ || ((FLAG) == DMA_FLAG_TC7) || ((FLAG) == DMA_FLAG_HT7) || ((FLAG) == DMA_FLAG_TE7) \
+ || ((FLAG) == DMA_FLAG_GL8) || ((FLAG) == DMA_FLAG_TC8) || ((FLAG) == DMA_FLAG_HT8) \
+ || ((FLAG) == DMA_FLAG_TE8))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Buffer_Size
+ * @{
+ */
+
+#define IS_DMA_BUF_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_remap_request_definition
+ * @{
+ */
+#define DMA_REMAP_ADC1 ((uint32_t)0x00000000)
+#define DMA_REMAP_USART1_TX ((uint32_t)0x00000001)
+#define DMA_REMAP_USART1_RX ((uint32_t)0x00000002)
+#define DMA_REMAP_USART2_TX ((uint32_t)0x00000003)
+#define DMA_REMAP_USART2_RX ((uint32_t)0x00000004)
+#define DMA_REMAP_USART3_TX ((uint32_t)0x00000005)
+#define DMA_REMAP_USART3_RX ((uint32_t)0x00000006)
+#define DMA_REMAP_UART4_TX ((uint32_t)0x00000007)
+#define DMA_REMAP_UART4_RX ((uint32_t)0x00000008)
+#define DMA_REMAP_UART5_TX ((uint32_t)0x00000009)
+#define DMA_REMAP_UART5_RX ((uint32_t)0x0000000A)
+#define DMA_REMAP_LPUART_TX ((uint32_t)0x0000000B)
+#define DMA_REMAP_LPUART_RX ((uint32_t)0x0000000C)
+#define DMA_REMAP_SPI1_TX ((uint32_t)0x0000000D)
+#define DMA_REMAP_SPI1_RX ((uint32_t)0x0000000E)
+#define DMA_REMAP_SPI2_TX ((uint32_t)0x0000000F)
+#define DMA_REMAP_SPI2_RX ((uint32_t)0x00000010)
+#define DMA_REMAP_I2C1_TX ((uint32_t)0x00000011)
+#define DMA_REMAP_I2C1_RX ((uint32_t)0x00000012)
+#define DMA_REMAP_I2C2_TX ((uint32_t)0x00000013)
+#define DMA_REMAP_I2C2_RX ((uint32_t)0x00000014)
+#define DMA_REMAP_DAC1 ((uint32_t)0x00000015)
+#define DMA_REMAP_TIM1_CH1 ((uint32_t)0x00000016)
+#define DMA_REMAP_TIM1_CH2 ((uint32_t)0x00000017)
+#define DMA_REMAP_TIM1_CH3 ((uint32_t)0x00000018)
+#define DMA_REMAP_TIM1_CH4 ((uint32_t)0x00000019)
+#define DMA_REMAP_TIM1_COM ((uint32_t)0x0000001A)
+#define DMA_REMAP_TIM1_UP ((uint32_t)0x0000001B)
+#define DMA_REMAP_TIM1_TRIG ((uint32_t)0x0000001C)
+#define DMA_REMAP_TIM2_CH1 ((uint32_t)0x0000001D)
+#define DMA_REMAP_TIM2_CH2 ((uint32_t)0x0000001E)
+#define DMA_REMAP_TIM2_CH3 ((uint32_t)0x0000001F)
+#define DMA_REMAP_TIM2_CH4 ((uint32_t)0x00000020)
+#define DMA_REMAP_TIM2_UP ((uint32_t)0x00000021)
+#define DMA_REMAP_TIM3_CH1 ((uint32_t)0x00000022)
+#define DMA_REMAP_TIM3_CH3 ((uint32_t)0x00000023)
+#define DMA_REMAP_TIM3_CH4 ((uint32_t)0x00000024)
+#define DMA_REMAP_TIM3_UP ((uint32_t)0x00000025)
+#define DMA_REMAP_TIM3_TRIG ((uint32_t)0x00000026)
+#define DMA_REMAP_TIM4_CH1 ((uint32_t)0x00000027)
+#define DMA_REMAP_TIM4_CH2 ((uint32_t)0x00000028)
+#define DMA_REMAP_TIM4_CH3 ((uint32_t)0x00000029)
+#define DMA_REMAP_TIM4_UP ((uint32_t)0x0000002A)
+#define DMA_REMAP_TIM5_CH1 ((uint32_t)0x0000002B)
+#define DMA_REMAP_TIM5_CH2 ((uint32_t)0x0000002C)
+#define DMA_REMAP_TIM5_CH3 ((uint32_t)0x0000002D)
+#define DMA_REMAP_TIM5_CH4 ((uint32_t)0x0000002E)
+#define DMA_REMAP_TIM5_UP ((uint32_t)0x0000002F)
+#define DMA_REMAP_TIM5_TRIG ((uint32_t)0x00000030)
+#define DMA_REMAP_TIM6_UP ((uint32_t)0x00000031)
+#define DMA_REMAP_TIM7_UP ((uint32_t)0x00000032)
+#define DMA_REMAP_TIM8_CH1 ((uint32_t)0x00000033)
+#define DMA_REMAP_TIM8_CH2 ((uint32_t)0x00000034)
+#define DMA_REMAP_TIM8_CH3 ((uint32_t)0x00000035)
+#define DMA_REMAP_TIM8_CH4 ((uint32_t)0x00000036)
+#define DMA_REMAP_TIM8_COM ((uint32_t)0x00000037)
+#define DMA_REMAP_TIM8_UP ((uint32_t)0x00000038)
+#define DMA_REMAP_TIM8_TRIG ((uint32_t)0x00000039)
+#define DMA_REMAP_TIM9_CH1 ((uint32_t)0x0000003A)
+#define DMA_REMAP_TIM9_TRIG ((uint32_t)0x0000003B)
+#define DMA_REMAP_TIM9_CH3 ((uint32_t)0x0000003C)
+#define DMA_REMAP_TIM9_CH4 ((uint32_t)0x0000003D)
+#define DMA_REMAP_TIM9_UP ((uint32_t)0x0000003E)
+
+
+#define IS_DMA_REMAP(FLAG) \
+ (((FLAG) == DMA_REMAP_ADC1) || ((FLAG) == DMA_REMAP_USART1_TX) || ((FLAG) == DMA_REMAP_USART1_RX) \
+ || ((FLAG) == DMA_REMAP_USART2_TX) || ((FLAG) == DMA_REMAP_USART2_RX) || ((FLAG) == DMA_REMAP_USART3_TX) \
+ || ((FLAG) == DMA_REMAP_USART3_RX) || ((FLAG) == DMA_REMAP_UART4_TX) || ((FLAG) == DMA_REMAP_UART4_RX) \
+ || ((FLAG) == DMA_REMAP_UART5_TX) || ((FLAG) == DMA_REMAP_UART5_RX) || ((FLAG) == DMA_REMAP_LPUART_TX) \
+ || ((FLAG) == DMA_REMAP_LPUART_RX) || ((FLAG) == DMA_REMAP_SPI1_TX) || ((FLAG) == DMA_REMAP_SPI1_RX) \
+ || ((FLAG) == DMA_REMAP_SPI2_TX) || ((FLAG) == DMA_REMAP_SPI2_RX) || ((FLAG) == DMA_REMAP_I2C1_TX) \
+ || ((FLAG) == DMA_REMAP_I2C1_RX) || ((FLAG) == DMA_REMAP_I2C2_TX) || ((FLAG) == DMA_REMAP_I2C2_RX) \
+ || ((FLAG) == DMA_REMAP_DAC1) || ((FLAG) == DMA_REMAP_TIM1_CH1) || ((FLAG) == DMA_REMAP_TIM1_CH2) \
+ || ((FLAG) == DMA_REMAP_TIM1_CH3) || ((FLAG) == DMA_REMAP_TIM1_CH4) || ((FLAG) == DMA_REMAP_TIM1_COM) \
+ || ((FLAG) == DMA_REMAP_TIM1_UP) || ((FLAG) == DMA_REMAP_TIM1_TRIG)|| ((FLAG) == DMA_REMAP_TIM2_CH1) \
+ || ((FLAG) == DMA_REMAP_TIM2_CH2) || ((FLAG) == DMA_REMAP_TIM2_CH3) || ((FLAG) == DMA_REMAP_TIM2_CH4) \
+ || ((FLAG) == DMA_REMAP_TIM2_UP) || ((FLAG) == DMA_REMAP_TIM3_CH1) || ((FLAG) == DMA_REMAP_TIM3_CH3) \
+ || ((FLAG) == DMA_REMAP_TIM3_CH4) || ((FLAG) == DMA_REMAP_TIM3_UP) || ((FLAG) == DMA_REMAP_TIM3_TRIG) \
+ || ((FLAG) == DMA_REMAP_TIM4_CH1) || ((FLAG) == DMA_REMAP_TIM4_CH2) || ((FLAG) == DMA_REMAP_TIM4_CH3) \
+ || ((FLAG) == DMA_REMAP_TIM4_UP) || ((FLAG) == DMA_REMAP_TIM5_CH1) || ((FLAG) == DMA_REMAP_TIM5_CH2) \
+ || ((FLAG) == DMA_REMAP_TIM5_CH3) || ((FLAG) == DMA_REMAP_TIM5_CH4) || ((FLAG) == DMA_REMAP_TIM5_UP) \
+ || ((FLAG) == DMA_REMAP_TIM5_TRIG)|| ((FLAG) == DMA_REMAP_TIM6_UP) || ((FLAG) == DMA_REMAP_TIM7_UP) \
+ || ((FLAG) == DMA_REMAP_TIM8_CH1) || ((FLAG) == DMA_REMAP_TIM8_CH2) || ((FLAG) == DMA_REMAP_TIM8_CH3) \
+ || ((FLAG) == DMA_REMAP_TIM8_CH4) || ((FLAG) == DMA_REMAP_TIM8_COM) || ((FLAG) == DMA_REMAP_TIM8_UP) \
+ || ((FLAG) == DMA_REMAP_TIM8_TRIG)|| ((FLAG) == DMA_REMAP_TIM9_CH1) || ((FLAG) == DMA_REMAP_TIM9_TRIG) \
+ || ((FLAG) == DMA_REMAP_TIM9_CH3) || ((FLAG) == DMA_REMAP_TIM9_CH4) || ((FLAG) == DMA_REMAP_TIM9_UP))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Functions
+ * @{
+ */
+
+void DMA_DeInit(DMA_ChannelType* DMAChx);
+void DMA_Init(DMA_ChannelType* DMAChx, DMA_InitType* DMA_InitParam);
+void DMA_StructInit(DMA_InitType* DMA_InitParam);
+void DMA_EnableChannel(DMA_ChannelType* DMAChx, FunctionalState Cmd);
+void DMA_ConfigInt(DMA_ChannelType* DMAChx, uint32_t DMAInt, FunctionalState Cmd);
+void DMA_SetCurrDataCounter(DMA_ChannelType* DMAChx, uint16_t DataNumber);
+uint16_t DMA_GetCurrDataCounter(DMA_ChannelType* DMAChx);
+FlagStatus DMA_GetFlagStatus(uint32_t DMAFlag, DMA_Module* DMAy);
+void DMA_ClearFlag(uint32_t DMAFlag, DMA_Module* DMAy);
+INTStatus DMA_GetIntStatus(uint32_t DMA_IT, DMA_Module* DMAy);
+void DMA_ClrIntPendingBit(uint32_t DMA_IT, DMA_Module* DMAy);
+void DMA_RequestRemap(uint32_t DMA_REMAP, DMA_Module* DMAy, DMA_ChannelType* DMAChx, FunctionalState Cmd);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32L43X_DMA_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_exti.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_exti.h
new file mode 100644
index 0000000000..f46a632225
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_exti.h
@@ -0,0 +1,234 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_exti.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L43X_EXTI_H__
+#define __N32L43X_EXTI_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l43x.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup EXTI
+ * @{
+ */
+
+/** @addtogroup EXTI_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief EXTI mode enumeration
+ */
+
+typedef enum
+{
+ EXTI_Mode_Interrupt = 0x00,
+ EXTI_Mode_Event = 0x04
+} EXTI_ModeType;
+
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
+
+/**
+ * @brief EXTI Trigger enumeration
+ */
+
+typedef enum
+{
+ EXTI_Trigger_Rising = 0x08,
+ EXTI_Trigger_Falling = 0x0C,
+ EXTI_Trigger_Rising_Falling = 0x10
+} EXTI_TriggerType;
+
+#define IS_EXTI_TRIGGER(TRIGGER) \
+ (((TRIGGER) == EXTI_Trigger_Rising) || ((TRIGGER) == EXTI_Trigger_Falling) \
+ || ((TRIGGER) == EXTI_Trigger_Rising_Falling))
+/**
+ * @brief EXTI Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
+ This parameter can be any combination of @ref EXTI_Lines */
+
+ EXTI_ModeType EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
+ This parameter can be a value of @ref EXTI_ModeType */
+
+ EXTI_TriggerType EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+ This parameter can be a value of @ref EXTI_ModeType */
+
+ FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
+ This parameter can be set either to ENABLE or DISABLE */
+} EXTI_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup EXTI_Lines
+ * @{
+ */
+
+#define EXTI_LINE0 ((uint32_t)0x00001) /*!< External interrupt line 0 */
+#define EXTI_LINE1 ((uint32_t)0x00002) /*!< External interrupt line 1 */
+#define EXTI_LINE2 ((uint32_t)0x00004) /*!< External interrupt line 2 */
+#define EXTI_LINE3 ((uint32_t)0x00008) /*!< External interrupt line 3 */
+#define EXTI_LINE4 ((uint32_t)0x00010) /*!< External interrupt line 4 */
+#define EXTI_LINE5 ((uint32_t)0x00020) /*!< External interrupt line 5 */
+#define EXTI_LINE6 ((uint32_t)0x00040) /*!< External interrupt line 6 */
+#define EXTI_LINE7 ((uint32_t)0x00080) /*!< External interrupt line 7 */
+#define EXTI_LINE8 ((uint32_t)0x00100) /*!< External interrupt line 8 */
+#define EXTI_LINE9 ((uint32_t)0x00200) /*!< External interrupt line 9 */
+#define EXTI_LINE10 ((uint32_t)0x00400) /*!< External interrupt line 10 */
+#define EXTI_LINE11 ((uint32_t)0x00800) /*!< External interrupt line 11 */
+#define EXTI_LINE12 ((uint32_t)0x01000) /*!< External interrupt line 12 */
+#define EXTI_LINE13 ((uint32_t)0x02000) /*!< External interrupt line 13 */
+#define EXTI_LINE14 ((uint32_t)0x04000) /*!< External interrupt line 14 */
+#define EXTI_LINE15 ((uint32_t)0x08000) /*!< External interrupt line 15 */
+#define EXTI_LINE16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */
+#define EXTI_LINE17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the USB Device/USB OTG FS Wakeup from suspend event */
+#define EXTI_LINE18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the RTC Alarm event */
+#define EXTI_LINE19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the RTC Time stamp event */
+#define EXTI_LINE20 ((uint32_t)0x100000) /*!< External interrupt line 20 Connected to the RTC Wakeup event */
+#define EXTI_LINE21 ((uint32_t)0x200000) /*!< External interrupt line 21 Connected to the COMP1 Global interrupt */
+#define EXTI_LINE22 ((uint32_t)0x400000) /*!< External interrupt line 22 Connected to the COMP2 Global interrupt */
+#define EXTI_LINE23 ((uint32_t)0x800000) /*!< External interrupt line 23 Connected to the LPUART Global interrupt */
+#define EXTI_LINE24 ((uint32_t)0x1000000) /*!< External interrupt line 24 Connected to the LPTIM Global interrupt */
+#define EXTI_LINE25 ((uint32_t)0x2000000) /*!< External interrupt line 25 Connected to the TSC Global interrupt */
+#define EXTI_LINE26 ((uint32_t)0x4000000) /*!< External interrupt line 26 Connected to the LCD Global interrupt */
+#define EXTI_LINE27 ((uint32_t)0x8000000) /*!< External interrupt line 27 Connected to the LPRCNT Global interrupt */
+
+
+
+
+
+
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xF0000000) == 0x00) && ((LINE) != (uint16_t)0x00))
+#define IS_GET_EXTI_LINE(LINE) \
+ (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) \
+ || ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) \
+ || ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) \
+ || ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) \
+ || ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) \
+ || ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) \
+ || ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27))
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_TSSEL_Line
+ * @{
+ */
+#define EXTI_TSSEL_LINE_MASK ((uint32_t)0x00000)
+#define EXTI_TSSEL_LINE0 ((uint32_t)0x00000) /*!< External interrupt line 0 */
+#define EXTI_TSSEL_LINE1 ((uint32_t)0x00001) /*!< External interrupt line 1 */
+#define EXTI_TSSEL_LINE2 ((uint32_t)0x00002) /*!< External interrupt line 2 */
+#define EXTI_TSSEL_LINE3 ((uint32_t)0x00003) /*!< External interrupt line 3 */
+#define EXTI_TSSEL_LINE4 ((uint32_t)0x00004) /*!< External interrupt line 4 */
+#define EXTI_TSSEL_LINE5 ((uint32_t)0x00005) /*!< External interrupt line 5 */
+#define EXTI_TSSEL_LINE6 ((uint32_t)0x00006) /*!< External interrupt line 6 */
+#define EXTI_TSSEL_LINE7 ((uint32_t)0x00007) /*!< External interrupt line 7 */
+#define EXTI_TSSEL_LINE8 ((uint32_t)0x00008) /*!< External interrupt line 8 */
+#define EXTI_TSSEL_LINE9 ((uint32_t)0x00009) /*!< External interrupt line 9 */
+#define EXTI_TSSEL_LINE10 ((uint32_t)0x0000A) /*!< External interrupt line 10 */
+#define EXTI_TSSEL_LINE11 ((uint32_t)0x0000B) /*!< External interrupt line 11 */
+#define EXTI_TSSEL_LINE12 ((uint32_t)0x0000C) /*!< External interrupt line 12 */
+#define EXTI_TSSEL_LINE13 ((uint32_t)0x0000D) /*!< External interrupt line 13 */
+#define EXTI_TSSEL_LINE14 ((uint32_t)0x0000E) /*!< External interrupt line 14 */
+#define EXTI_TSSEL_LINE15 ((uint32_t)0x0000F) /*!< External interrupt line 15 */
+
+#define IS_EXTI_TSSEL_LINE(LINE) \
+ (((LINE) == EXTI_TSSEL_LINE0) || ((LINE) == EXTI_TSSEL_LINE1) || ((LINE) == EXTI_TSSEL_LINE2) \
+ || ((LINE) == EXTI_TSSEL_LINE3) || ((LINE) == EXTI_TSSEL_LINE4) || ((LINE) == EXTI_TSSEL_LINE5) \
+ || ((LINE) == EXTI_TSSEL_LINE6) || ((LINE) == EXTI_TSSEL_LINE7) || ((LINE) == EXTI_TSSEL_LINE8) \
+ || ((LINE) == EXTI_TSSEL_LINE9) || ((LINE) == EXTI_TSSEL_LINE10) || ((LINE) == EXTI_TSSEL_LINE11) \
+ || ((LINE) == EXTI_TSSEL_LINE12) || ((LINE) == EXTI_TSSEL_LINE13) || ((LINE) == EXTI_TSSEL_LINE14) \
+ || ((LINE) == EXTI_TSSEL_LINE15))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Exported_Functions
+ * @{
+ */
+
+void EXTI_DeInit(void);
+void EXTI_InitPeripheral(EXTI_InitType* EXTI_InitStruct);
+void EXTI_InitStruct(EXTI_InitType* EXTI_InitStruct);
+void EXTI_TriggerSWInt(uint32_t EXTI_Line);
+FlagStatus EXTI_GetStatusFlag(uint32_t EXTI_Line);
+void EXTI_ClrStatusFlag(uint32_t EXTI_Line);
+INTStatus EXTI_GetITStatus(uint32_t EXTI_Line);
+void EXTI_ClrITPendBit(uint32_t EXTI_Line);
+void EXTI_RTCTimeStampSel(uint32_t EXTI_TSSEL_Line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32L43X_EXTI_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_flash.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_flash.h
new file mode 100644
index 0000000000..cb64933c7e
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_flash.h
@@ -0,0 +1,513 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_flash.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L43X_FLASH_H__
+#define __N32L43X_FLASH_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l43x.h"
+
+/** @addtogroup N32L43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @{
+ */
+
+/** @addtogroup FLASH_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief FLASH Status
+ */
+
+typedef enum
+{
+ FLASH_BUSY = 1,
+ FLASH_RESERVED,
+ FLASH_ERR_PG,
+ FLASH_ERR_PV,
+ FLASH_ERR_WRP,
+ FLASH_COMPL,
+ FLASH_ERR_EV,
+ FLASH_ERR_RDP2,
+ FLASH_ERR_ADD,
+ FLASH_TIMEOUT
+} FLASH_STS;
+
+/**
+ * @brief FLASH_SMPSEL
+ */
+
+typedef enum
+{
+ FLASH_SMP1 = 0,
+ FLASH_SMP2
+} FLASH_SMPSEL;
+
+/**
+ * @brief FLASH_HSICLOCK
+ */
+
+typedef enum
+{
+ FLASH_HSICLOCK_ENABLE = 0,
+ FLASH_HSICLOCK_DISABLE
+} FLASH_HSICLOCK;
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup Flash_Latency
+ * @{
+ */
+
+#define FLASH_LATENCY_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
+#define FLASH_LATENCY_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */
+#define FLASH_LATENCY_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */
+#define FLASH_LATENCY_3 ((uint32_t)0x00000003) /*!< FLASH Three Latency cycles */
+#define IS_FLASH_LATENCY(LATENCY) \
+ (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || ((LATENCY) == FLASH_LATENCY_2) \
+ || ((LATENCY) == FLASH_LATENCY_3))
+/**
+ * @}
+ */
+
+/** @addtogroup Prefetch_Buffer_Enable_Disable
+ * @{
+ */
+
+#define FLASH_PrefetchBuf_EN ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */
+#define FLASH_PrefetchBuf_DIS ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */
+#define IS_FLASH_PREFETCHBUF_STATE(STATE) (((STATE) == FLASH_PrefetchBuf_EN) || ((STATE) == FLASH_PrefetchBuf_DIS))
+/**
+ * @}
+ */
+
+/** @addtogroup iCache_Enable_Disable
+ * @{
+ */
+
+#define FLASH_iCache_EN ((uint32_t)0x00000080) /*!< FLASH iCache Enable */
+#define FLASH_iCache_DIS ((uint32_t)0x00000000) /*!< FLASH iCache Disable */
+#define IS_FLASH_ICACHE_STATE(STATE) (((STATE) == FLASH_iCache_EN) || ((STATE) == FLASH_iCache_DIS))
+/**
+ * @}
+ */
+
+/** @addtogroup Low Voltage Mode
+ * @{
+ */
+
+#define FLASH_LVM_EN ((uint32_t)0x00000200) /*!< FLASH Low Voltage Mode Enable */
+#define FLASH_LVM_DIS ((uint32_t)0x00000000) /*!< FLASH Low Voltage Mode Disable */
+#define IS_FLASH_LVM(STATE) (((STATE) == FLASH_LVM_EN) || ((STATE) == FLASH_LVM_DIS))
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH Sleep Mode
+ * @{
+ */
+
+#define FLASH_SLM_EN ((uint32_t)0x00000800) /*!< FLASH Sleep Mode Enable */
+#define FLASH_SLM_DIS ((uint32_t)0x00000000) /*!< FLASH Sleep Mode Disable */
+#define IS_FLASH_SLM(STATE) (((STATE) == FLASH_SLM_EN) || ((STATE) == FLASH_SLM_DIS))
+/**
+ * @}
+ */
+
+/** @addtogroup SMPSEL_SMP1_SMP2
+ * @{
+ */
+
+#define FLASH_SMPSEL_SMP1 ((uint32_t)0x00000000) /*!< FLASH SMPSEL SMP1 */
+#define FLASH_SMPSEL_SMP2 ((uint32_t)0x00000100) /*!< FLASH SMPSEL SMP2 */
+#define IS_FLASH_SMPSEL_STATE(STATE) (((STATE) == FLASH_SMPSEL_SMP1) || ((STATE) == FLASH_SMPSEL_SMP2))
+/**
+ * @}
+ */
+
+/* Values to be used with N32L43x devices */
+#define FLASH_WRP_Pages0to1 \
+ ((uint32_t)0x00000001) /*!< N32L43x devices: \
+ Write protection of page 0 to 1 */
+#define FLASH_WRP_Pages2to3 \
+ ((uint32_t)0x00000002) /*!< N32L43x devices: \
+ Write protection of page 2 to 3 */
+#define FLASH_WRP_Pages4to5 \
+ ((uint32_t)0x00000004) /*!< N32L43x devices: \
+ Write protection of page 4 to 5 */
+#define FLASH_WRP_Pages6to7 \
+ ((uint32_t)0x00000008) /*!< N32L43x devices: \
+ Write protection of page 6 to 7 */
+#define FLASH_WRP_Pages8to9 \
+ ((uint32_t)0x00000010) /*!< N32L43x devices: \
+ Write protection of page 8 to 9 */
+#define FLASH_WRP_Pages10to11 \
+ ((uint32_t)0x00000020) /*!< N32L43x devices: \
+ Write protection of page 10 to 11 */
+#define FLASH_WRP_Pages12to13 \
+ ((uint32_t)0x00000040) /*!< N32L43x devices: \
+ Write protection of page 12 to 13 */
+#define FLASH_WRP_Pages14to15 \
+ ((uint32_t)0x00000080) /*!< N32L43x devices: \
+ Write protection of page 14 to 15 */
+#define FLASH_WRP_Pages16to17 \
+ ((uint32_t)0x00000100) /*!< N32L43x devices: \
+ Write protection of page 16 to 17 */
+#define FLASH_WRP_Pages18to19 \
+ ((uint32_t)0x00000200) /*!< N32L43x devices: \
+ Write protection of page 18 to 19 */
+#define FLASH_WRP_Pages20to21 \
+ ((uint32_t)0x00000400) /*!< N32L43x devices: \
+ Write protection of page 20 to 21 */
+#define FLASH_WRP_Pages22to23 \
+ ((uint32_t)0x00000800) /*!< N32L43x devices: \
+ Write protection of page 22 to 23 */
+#define FLASH_WRP_Pages24to25 \
+ ((uint32_t)0x00001000) /*!< N32L43x devices: \
+ Write protection of page 24 to 25 */
+#define FLASH_WRP_Pages26to27 \
+ ((uint32_t)0x00002000) /*!< N32L43x devices: \
+ Write protection of page 26 to 27 */
+#define FLASH_WRP_Pages28to29 \
+ ((uint32_t)0x00004000) /*!< N32L43x devices: \
+ Write protection of page 28 to 29 */
+#define FLASH_WRP_Pages30to31 \
+ ((uint32_t)0x00008000) /*!< N32L43x devices: \
+ Write protection of page 30 to 31 */
+#define FLASH_WRP_Pages32to33 \
+ ((uint32_t)0x00010000) /*!< N32L43x devices: \
+ Write protection of page 32 to 33 */
+#define FLASH_WRP_Pages34to35 \
+ ((uint32_t)0x00020000) /*!< N32L43x devices: \
+ Write protection of page 34 to 35 */
+#define FLASH_WRP_Pages36to37 \
+ ((uint32_t)0x00040000) /*!< N32L43x devices: \
+ Write protection of page 36 to 37 */
+#define FLASH_WRP_Pages38to39 \
+ ((uint32_t)0x00080000) /*!< N32L43x devices: \
+ Write protection of page 38 to 39 */
+#define FLASH_WRP_Pages40to41 \
+ ((uint32_t)0x00100000) /*!< N32L43x devices: \
+ Write protection of page 40 to 41 */
+#define FLASH_WRP_Pages42to43 \
+ ((uint32_t)0x00200000) /*!< N32L43x devices: \
+ Write protection of page 42 to 43 */
+#define FLASH_WRP_Pages44to45 \
+ ((uint32_t)0x00400000) /*!< N32L43x devices: \
+ Write protection of page 44 to 45 */
+#define FLASH_WRP_Pages46to47 \
+ ((uint32_t)0x00800000) /*!< N32L43x devices: \
+ Write protection of page 46 to 47 */
+#define FLASH_WRP_Pages48to49 \
+ ((uint32_t)0x01000000) /*!< N32L43x devices: \
+ Write protection of page 48 to 49 */
+#define FLASH_WRP_Pages50to51 \
+ ((uint32_t)0x02000000) /*!< N32L43x devices: \
+ Write protection of page 50 to 51 */
+#define FLASH_WRP_Pages52to53 \
+ ((uint32_t)0x04000000) /*!< N32L43x devices: \
+ Write protection of page 52 to 53 */
+#define FLASH_WRP_Pages54to55 \
+ ((uint32_t)0x08000000) /*!< N32L43x devices: \
+ Write protection of page 54 to 55 */
+#define FLASH_WRP_Pages56to57 \
+ ((uint32_t)0x10000000) /*!< N32L43x devices: \
+ Write protection of page 56 to 57 */
+#define FLASH_WRP_Pages58to59 \
+ ((uint32_t)0x20000000) /*!< N32L43x devices: \
+ Write protection of page 58 to 59 */
+#define FLASH_WRP_Pages60to61 \
+ ((uint32_t)0x40000000) /*!< N32L43x devices: \
+ Write protection of page 60 to 61 */
+#define FLASH_WRP_Pages62to63 \
+ ((uint32_t)0x80000000) /*!< N32L43x devices:
+ Write protection of page 62 to 63 */
+
+#define FLASH_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
+
+#define IS_FLASH_WRP_PAGE(PAGE) (1) //(((PAGE) <= FLASH_WRP_AllPages))
+
+#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0801FFFF))
+
+#define IS_OB_DATA_ADDRESS(ADDRESS) ((ADDRESS) == 0x1FFFF804)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_RDP1
+ * @{
+ */
+
+#define OB_RDP1_ENABLE ((uint8_t)0x00) /*!< Enable RDP1 */
+#define OB_RDP1_DISABLE ((uint8_t)0xA5) /*!< DISABLE RDP1 */
+#define IS_OB_RDP1_SOURCE(SOURCE) (((SOURCE) == OB_RDP1_ENABLE) || ((SOURCE) == OB_RDP1_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_IWatchdog
+ * @{
+ */
+
+#define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */
+#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_nRST_STOP
+ * @{
+ */
+
+#define OB_STOP2_NORST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */
+#define OB_STOP2_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
+#define IS_OB_STOP2_SOURCE(SOURCE) (((SOURCE) == OB_STOP2_NORST) || ((SOURCE) == OB_STOP2_RST))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_nRST_STDBY
+ * @{
+ */
+
+#define OB_STDBY_NORST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NORST) || ((SOURCE) == OB_STDBY_RST))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_nRST_PD
+ * @{
+ */
+
+#define OB_PD_NORST ((uint8_t)0x08) /*!< No reset generated when entering in PowerDown */
+#define OB_PD_RST ((uint8_t)0x00) /*!< Reset generated when entering in PowerDown */
+#define IS_OB_PD_SOURCE(SOURCE) (((SOURCE) == OB_PD_NORST) || ((SOURCE) == OB_PD_RST))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_RDP2
+ * @{
+ */
+
+#define OB_RDP2_ENABLE ((uint8_t)0x33) /*!< Enable RDP2 */
+#define OB_RDP2_DISABLE ((uint8_t)0x00) /*!< Disable RDP2 */
+#define IS_OB_RDP2_SOURCE(SOURCE) (((SOURCE) == OB_RDP2_ENABLE) || ((SOURCE) == OB_RDP2_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_nBOOT0
+ * @{
+ */
+
+#define OB2_NBOOT0_SET ((uint8_t)0x01) /*!< Set nBOOT0 */
+#define OB2_NBOOT0_CLR ((uint8_t)0x00) /*!< Clear nBOOT0 */
+#define IS_OB2_NBOOT0_SOURCE(SOURCE) (((SOURCE) == OB2_NBOOT0_SET) || ((SOURCE) == OB2_NBOOT0_CLR))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_nBOOT1
+ * @{
+ */
+
+#define OB2_NBOOT1_SET ((uint8_t)0x02) /*!< Set nBOOT1 */
+#define OB2_NBOOT1_CLR ((uint8_t)0x00) /*!< Clear nBOOT1 */
+#define IS_OB2_NBOOT1_SOURCE(SOURCE) (((SOURCE) == OB2_NBOOT1_SET) || ((SOURCE) == OB2_NBOOT1_CLR))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_nSWBOOT0
+ * @{
+ */
+
+#define OB2_NSWBOOT0_SET ((uint8_t)0x04) /*!< Set nSWBOOT0 */
+#define OB2_NSWBOOT0_CLR ((uint8_t)0x00) /*!< Clear nSWBOOT0 */
+#define IS_OB2_NSWBOOT0_SOURCE(SOURCE) (((SOURCE) == OB2_NSWBOOT0_SET) || ((SOURCE) == OB2_NSWBOOT0_CLR))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_BOR_LEV
+ * @{
+ */
+
+#define OB2_BOR_LEV0 ((uint8_t)0x00) /*!< BOR_LEV[2:0] L0 */
+#define OB2_BOR_LEV1 ((uint8_t)0x10) /*!< BOR_LEV[2:0] L1 */
+#define OB2_BOR_LEV2 ((uint8_t)0x20) /*!< BOR_LEV[2:0] L2 */
+#define OB2_BOR_LEV3 ((uint8_t)0x30) /*!< BOR_LEV[2:0] L3 */
+#define OB2_BOR_LEV4 ((uint8_t)0x40) /*!< BOR_LEV[2:0] L4 */
+#define OB2_BOR_LEV5 ((uint8_t)0x50) /*!< BOR_LEV[2:0] L5 */
+#define OB2_BOR_LEV6 ((uint8_t)0x60) /*!< BOR_LEV[2:0] L6 */
+#define OB2_BOR_LEV7 ((uint8_t)0x70) /*!< BOR_LEV[2:0] L7 */
+#define IS_OB2_BOR_LEV_SOURCE(SOURCE) (((SOURCE) == OB2_BOR_LEV0) || ((SOURCE) == OB2_BOR_LEV1) \
+ || ((SOURCE) == OB2_BOR_LEV2) || ((SOURCE) == OB2_BOR_LEV3) \
+ || ((SOURCE) == OB2_BOR_LEV4) || ((SOURCE) == OB2_BOR_LEV5) \
+ || ((SOURCE) == OB2_BOR_LEV6) || ((SOURCE) == OB2_BOR_LEV7))
+
+
+/**
+ * @}
+ */
+/** @addtogroup FLASH_Interrupts
+ * @{
+ */
+#define FLASH_INT_ERRIE ((uint32_t)0x00000400) /*!< PGERR WRPERR ERROR error interrupt source */
+#define FLASH_INT_FERR ((uint32_t)0x00000800) /*!< EVERR PVERR interrupt source */
+#define FLASH_INT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */
+
+#define IS_FLASH_INT(IT) ((((IT) & (uint32_t)0xFFFFE3FF) == 0x00000000) && (((IT) != 0x00000000)))
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Flags
+ * @{
+ */
+#define FLASH_FLAG_BUSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */
+#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */
+#define FLASH_FLAG_PVERR ((uint32_t)0x00000008) /*!< FLASH Program Verify ERROR flag after program */
+#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */
+#define FLASH_FLAG_EVERR ((uint32_t)0x00000040) /*!< FLASH Erase Verify ERROR flag after page erase */
+#define FLASH_FLAG_OBERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */
+
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF83) == 0x00000000) && ((FLAG) != 0x00000000))
+#define IS_FLASH_GET_FLAG(FLAG) \
+ (((FLAG) == FLASH_FLAG_BUSY) || ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_PVERR) \
+ || ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_EVERR) \
+ || ((FLAG) == FLASH_FLAG_OBERR))
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_STS_CLRFLAG
+ * @{
+ */
+#define FLASH_STS_CLRFLAG (FLASH_FLAG_PGERR | FLASH_FLAG_PVERR | FLASH_FLAG_WRPERR | FLASH_FLAG_EOP |FLASH_FLAG_EVERR)
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Exported_Functions
+ * @{
+ */
+
+/*------------ Functions used for N32L43x devices -----*/
+void FLASH_SetLatency(uint32_t FLASH_Latency);
+void FLASH_PrefetchBufSet(uint32_t FLASH_PrefetchBuf);
+void FLASH_iCacheRST(void);
+void FLASH_iCacheCmd(uint32_t FLASH_iCache);
+void FLASH_LowVoltageModeCmd(uint32_t FLASH_LVM);
+FlagStatus FLASH_GetLowVoltageModeSTS(void);
+void FLASH_FLASHSleepModeCmd(uint32_t FLASH_SLM);
+FlagStatus FLASH_GetFLASHSleepModeSTS(void);
+FLASH_HSICLOCK FLASH_ClockInit(void);
+void FLASH_Unlock(void);
+void FLASH_Lock(void);
+FLASH_STS FLASH_EraseOnePage(uint32_t Page_Address);
+FLASH_STS FLASH_MassErase(void);
+FLASH_STS FLASH_EraseOB(void);
+FLASH_STS FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+FLASH_STS FLASH_ProgramOBData(uint32_t Address, uint32_t Data);
+FLASH_STS FLASH_EnWriteProtection(uint32_t FLASH_Pages);
+FLASH_STS FLASH_ReadOutProtectionL1(FunctionalState Cmd);
+FLASH_STS FLASH_ReadOutProtectionL2_ENABLE(void);
+FLASH_STS FLASH_ConfigALLOptionByte(uint8_t OB_RDP1, uint8_t OB_IWDG, uint8_t OB_STOP2,
+ uint8_t OB_STDBY, uint8_t OB_PD, uint8_t OB_Data0,
+ uint8_t OB_Data1, uint32_t WRP_Pages, uint8_t OB_RDP2,
+ uint8_t OB2_nBOOT0, uint8_t OB2_nBOOT1, uint8_t OB2_nSWBOOT0,
+ uint8_t OB2_BOR_LEV);
+FLASH_STS FLASH_ConfigUserOB(uint8_t OB_IWDG, uint8_t OB_STOP2, uint8_t OB_STDBY, uint8_t OB_PD);
+FLASH_STS FLASH_ConfigUserOB2(uint8_t OB2_nBOOT0, uint8_t OB2_nBOOT1, uint8_t OB2_nSWBOOT0, uint8_t OB2_BOR_LEV);
+uint32_t FLASH_GetUserOB(void);
+uint32_t FLASH_GetWriteProtectionOB(void);
+FlagStatus FLASH_GetReadOutProtectionSTS(void);
+FlagStatus FLASH_GetReadOutProtectionL2STS(void);
+FlagStatus FLASH_GetPrefetchBufSTS(void);
+void FLASH_SetSMPSELStatus(uint32_t FLASH_smpsel);
+FLASH_SMPSEL FLASH_GetSMPSELStatus(void);
+void FLASH_INTConfig(uint32_t FLASH_INT, FunctionalState Cmd);
+FlagStatus FLASH_GetFlagSTS(uint32_t FLASH_FLAG);
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);
+FLASH_STS FLASH_GetSTS(void);
+FLASH_STS FLASH_WaitForLastOpt(uint32_t Timeout);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32L43X_FLASH_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_gpio.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_gpio.h
new file mode 100644
index 0000000000..10e7641da9
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_gpio.h
@@ -0,0 +1,676 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_gpio.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L43X_GPIO_H__
+#define __N32L43X_GPIO_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l43x.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/** @addtogroup GPIO_Exported_Types
+ * @{
+ */
+
+#define IS_GPIO_ALL_PERIPH(PERIPH) \
+ (((PERIPH) == GPIOA) || ((PERIPH) == GPIOB) || ((PERIPH) == GPIOC) || ((PERIPH) == GPIOD))
+
+
+#define GPIO_GET_INDEX(PERIPH) (((PERIPH) == (GPIOA))? 0 :\
+ ((PERIPH) == (GPIOB))? 1 :\
+ ((PERIPH) == (GPIOC))? 2 :3)
+#define GPIO_GET_PERIPH(INDEX) (((INDEX)==((uint8_t)0x00))? GPIOA :\
+ ((INDEX)==((uint8_t)0x01))? GPIOB :\
+ ((INDEX)==((uint8_t)0x02))? GPIOC : GPIOD )
+
+
+/**
+ * @brief Output Maximum frequency selection
+ */
+
+typedef enum
+{
+ GPIO_Slew_Rate_High = 0,
+ GPIO_Slew_Rate_Low
+} GPIO_SpeedType;
+#define IS_GPIO_SLEW_RATE(_RATE_) \
+ (((_RATE_) == GPIO_Slew_Rate_High) || ((_RATE_) == GPIO_Slew_Rate_Low))
+
+/**
+ * @brief driver strength config
+ */
+
+typedef enum
+{
+ GPIO_DC_2mA = 0x00,
+ GPIO_DC_4mA = 0x10,
+ GPIO_DC_8mA = 0x01,
+ GPIO_DC_12mA= 0x11
+}GPIO_CurrentType;
+
+#define IS_GPIO_CURRENT(CURRENT) \
+ (((CURRENT) == GPIO_DC_2mA) ||((CURRENT) == GPIO_DC_4mA) \
+ || ((CURRENT) == GPIO_DC_8mA)||((CURRENT) == GPIO_DC_12mA))
+/**
+ * @brief Configuration Mode enumeration
+ */
+
+
+/** @brief GPIO_mode_define Mode definition
+ * @brief GPIO Configuration Mode
+ * Values convention: 0xW0yz00YZ
+ * - W : GPIO mode or EXTI Mode
+ * - y : External IT or Event trigger detection
+ * - z : IO configuration on External IT or Event
+ * - Y : Output type (Push Pull or Open Drain)
+ * - Z : IO Direction mode (Input, Output, Alternate or Analog)
+ * @{
+ */
+
+typedef enum
+{
+ GPIO_Mode_Input = 0x00000000, /*!< Input Floating Mode */
+ GPIO_Mode_Out_PP = 0x00000001, /*!< Output Push Pull Mode */
+ GPIO_Mode_Out_OD = 0x00000011, /*!< Output Open Drain Mode */
+ GPIO_Mode_AF_PP = 0x00000002, /*!< Alternate Function Push Pull Mode */
+ GPIO_Mode_AF_OD = 0x00000012, /*!< Alternate Function Open Drain Mode */
+
+ GPIO_Mode_Analog = 0x00000003, /*!< Analog Mode */
+
+ GPIO_Mode_IT_Rising = 0x10110000, /*!< External Interrupt Mode with Rising edge trigger detection */
+ GPIO_Mode_IT_Falling = 0x10210000, /*!< External Interrupt Mode with Falling edge trigger detection */
+ GPIO_Mode_IT_Rising_Falling = 0x10310000, /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+
+ GPIO_Mode_EVT_Rising = 0x10120000, /*!< External Event Mode with Rising edge trigger detection */
+ GPIO_Mode_EVT_Falling = 0x10220000, /*!< External Event Mode with Falling edge trigger detection */
+ GPIO_Mode_EVT_Rising_Falling = 0x10320000
+}GPIO_ModeType;
+
+
+
+/**
+ * @}
+ */
+#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_Mode_Input) ||\
+ ((__MODE__) == GPIO_Mode_Out_PP) ||\
+ ((__MODE__) == GPIO_Mode_Out_OD) ||\
+ ((__MODE__) == GPIO_Mode_AF_PP) ||\
+ ((__MODE__) == GPIO_Mode_AF_OD) ||\
+ ((__MODE__) == GPIO_Mode_IT_Rising) ||\
+ ((__MODE__) == GPIO_Mode_IT_Falling) ||\
+ ((__MODE__) == GPIO_Mode_IT_Rising_Falling) ||\
+ ((__MODE__) == GPIO_Mode_EVT_Rising) ||\
+ ((__MODE__) == GPIO_Mode_EVT_Falling) ||\
+ ((__MODE__) == GPIO_Mode_EVT_Rising_Falling) ||\
+ ((__MODE__) == GPIO_Mode_Analog))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @brief GPIO_pull_define Pull definition
+ * @brief GPIO Pull-Up or Pull-Down Activation
+ * @{
+ */
+
+typedef enum
+{
+ GPIO_No_Pull = 0x00000000, /*!< No Pull-up or Pull-down activation */
+ GPIO_Pull_Up = 0x00000001, /*!< Pull-up activation */
+ GPIO_Pull_Down = 0x00000002 /*!< Pull-down activation */
+}GPIO_PuPdType;
+/**
+ * @}
+ */
+
+#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_No_Pull) || ((__PULL__) == GPIO_Pull_Up) || \
+ ((__PULL__) == GPIO_Pull_Down))
+/**
+ * @}
+ */
+
+/**
+ * @brief GPIO Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_pins_define */
+
+ GPIO_CurrentType GPIO_Current; /*!.
+ This paramter can be a value of @ref GPIO_CurrentType*/
+
+ GPIO_SpeedType GPIO_Slew_Rate; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIO_SpeedType */
+
+ GPIO_PuPdType GPIO_Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+ This parameter can be a value of @ref GPIO_pull_define */
+
+ GPIO_ModeType GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIO_ModeType */
+
+ uint32_t GPIO_Alternate; /*!< Peripheral to be connected to the selected pins
+ This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
+} GPIO_InitType;
+
+/**
+ * @brief Bit_SET and Bit_RESET enumeration
+ */
+
+typedef enum
+{
+ Bit_RESET = 0,
+ Bit_SET
+} Bit_OperateType;
+
+#define IS_GPIO_BIT_OPERATE(OPERATE) (((OPERATE) == Bit_RESET) || ((OPERATE) == Bit_SET))
+
+/**
+ * @}
+ */
+
+
+
+
+/** @addtogroup GPIO_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup GPIO_pins_define
+ * @{
+ */
+
+#define GPIO_PIN_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
+#define GPIO_PIN_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
+#define GPIO_PIN_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
+#define GPIO_PIN_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
+#define GPIO_PIN_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
+#define GPIO_PIN_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
+#define GPIO_PIN_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
+#define GPIO_PIN_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
+#define GPIO_PIN_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
+#define GPIO_PIN_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
+#define GPIO_PIN_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
+#define GPIO_PIN_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
+#define GPIO_PIN_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
+#define GPIO_PIN_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
+#define GPIO_PIN_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
+#define GPIO_PIN_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
+#define GPIO_PIN_ALL ((uint16_t)0xFFFF) /*!< All pins selected */
+
+#define GPIOA_PIN_AVAILABLE ((uint16_t)0xFFFF)
+#define GPIOB_PIN_AVAILABLE ((uint16_t)0xFFFF)
+#define GPIOC_PIN_AVAILABLE ((uint16_t)0xFFFF)
+#define GPIOD_PIN_AVAILABLE ((uint16_t)0xFFFF)
+
+#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
+
+#define IS_GET_GPIO_PIN(PIN) \
+ (((PIN) == GPIO_PIN_0) || ((PIN) == GPIO_PIN_1) || ((PIN) == GPIO_PIN_2) || ((PIN) == GPIO_PIN_3) \
+ || ((PIN) == GPIO_PIN_4) || ((PIN) == GPIO_PIN_5) || ((PIN) == GPIO_PIN_6) || ((PIN) == GPIO_PIN_7) \
+ || ((PIN) == GPIO_PIN_8) || ((PIN) == GPIO_PIN_9) || ((PIN) == GPIO_PIN_10) || ((PIN) == GPIO_PIN_11) \
+ || ((PIN) == GPIO_PIN_12) || ((PIN) == GPIO_PIN_13) || ((PIN) == GPIO_PIN_14) || ((PIN) == GPIO_PIN_15))
+
+
+#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) \
+ ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \
+ (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \
+ (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \
+ (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))))
+
+
+
+
+
+/**
+ * @}
+ */
+
+
+
+
+/** @addtogroup GPIO_Port_Sources
+ * @{
+ */
+
+#define GPIOA_PORT_SOURCE ((uint8_t)0x00)
+#define GPIOB_PORT_SOURCE ((uint8_t)0x01)
+#define GPIOC_PORT_SOURCE ((uint8_t)0x02)
+#define GPIOD_PORT_SOURCE ((uint8_t)0x03)
+
+#define IS_GPIO_REMAP_PORT_SOURCE(PORTSOURCE) \
+ (((PORTSOURCE) == GPIOA_PORT_SOURCE) || ((PORTSOURCE) == GPIOB_PORT_SOURCE) || ((PORTSOURCE) == GPIOC_PORT_SOURCE) \
+ || ((PORTSOURCE) == GPIOD_PORT_SOURCE))
+
+
+#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) \
+ (((PORTSOURCE) == GPIOA_PORT_SOURCE) || ((PORTSOURCE) == GPIOB_PORT_SOURCE) || ((PORTSOURCE) == GPIOC_PORT_SOURCE) \
+ || ((PORTSOURCE) == GPIOD_PORT_SOURCE))
+
+#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) \
+ (((PORTSOURCE) == GPIOA_PORT_SOURCE) || ((PORTSOURCE) == GPIOB_PORT_SOURCE) || ((PORTSOURCE) == GPIOC_PORT_SOURCE) \
+ || ((PORTSOURCE) == GPIOD_PORT_SOURCE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Pin_sources
+ * @{
+ */
+
+#define GPIO_PIN_SOURCE0 ((uint8_t)0x00)
+#define GPIO_PIN_SOURCE1 ((uint8_t)0x01)
+#define GPIO_PIN_SOURCE2 ((uint8_t)0x02)
+#define GPIO_PIN_SOURCE3 ((uint8_t)0x03)
+#define GPIO_PIN_SOURCE4 ((uint8_t)0x04)
+#define GPIO_PIN_SOURCE5 ((uint8_t)0x05)
+#define GPIO_PIN_SOURCE6 ((uint8_t)0x06)
+#define GPIO_PIN_SOURCE7 ((uint8_t)0x07)
+#define GPIO_PIN_SOURCE8 ((uint8_t)0x08)
+#define GPIO_PIN_SOURCE9 ((uint8_t)0x09)
+#define GPIO_PIN_SOURCE10 ((uint8_t)0x0A)
+#define GPIO_PIN_SOURCE11 ((uint8_t)0x0B)
+#define GPIO_PIN_SOURCE12 ((uint8_t)0x0C)
+#define GPIO_PIN_SOURCE13 ((uint8_t)0x0D)
+#define GPIO_PIN_SOURCE14 ((uint8_t)0x0E)
+#define GPIO_PIN_SOURCE15 ((uint8_t)0x0F)
+
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) \
+ (((PINSOURCE) == GPIO_PIN_SOURCE0) || ((PINSOURCE) == GPIO_PIN_SOURCE1) || ((PINSOURCE) == GPIO_PIN_SOURCE2) \
+ || ((PINSOURCE) == GPIO_PIN_SOURCE3) || ((PINSOURCE) == GPIO_PIN_SOURCE4) || ((PINSOURCE) == GPIO_PIN_SOURCE5) \
+ || ((PINSOURCE) == GPIO_PIN_SOURCE6) || ((PINSOURCE) == GPIO_PIN_SOURCE7) || ((PINSOURCE) == GPIO_PIN_SOURCE8) \
+ || ((PINSOURCE) == GPIO_PIN_SOURCE9) || ((PINSOURCE) == GPIO_PIN_SOURCE10) || ((PINSOURCE) == GPIO_PIN_SOURCE11) \
+ || ((PINSOURCE) == GPIO_PIN_SOURCE12) || ((PINSOURCE) == GPIO_PIN_SOURCE13) || ((PINSOURCE) == GPIO_PIN_SOURCE14) \
+ || ((PINSOURCE) == GPIO_PIN_SOURCE15))
+
+/**
+ * @}
+ */
+
+
+
+/** @defgroup GPIOx_Alternate_function_selection Alternate function selection
+ * @{
+ */
+
+/*
+ * Alternate function AF0
+ */
+#define GPIO_AF0_SW_JTAG ((uint8_t)0x00) /* SPI1 Alternate Function mapping */
+#define GPIO_AF0_SPI1 ((uint8_t)0x00) /* SPI1 Alternate Function mapping */
+#define GPIO_AF0_LPTIM ((uint8_t)0x00) /* LPTIM Alternate Function mapping */
+#define GPIO_AF0_SPI2 ((uint8_t)0x00) /* SPI2 Alternate Function mapping */
+#define GPIO_AF0_TIM8 ((uint8_t)0x00) /* TIM8 Alternate Function mapping */
+#define GPIO_AF0_USART1 ((uint8_t)0x00) /* USART1 Alternate Function mapping */
+#define GPIO_AF0_USART3 ((uint8_t)0x00) /* USART3 Alternate Function mapping */
+#define GPIO_AF0_LPUART ((uint8_t)0x00) /* LPUART Alternate Function mapping */
+#define GPIO_AF0_USART2 ((uint8_t)0x00) /* USART2 Alternate Function mapping */
+
+/**
+ *
+ */
+
+/*
+ * Alternate function AF1
+ */
+#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */
+#define GPIO_AF1_USART1 ((uint8_t)0x01) /* USART1 Alternate Function mapping */
+#define GPIO_AF1_I2C2 ((uint8_t)0x01) /* I2C2 Alternate Function mapping */
+#define GPIO_AF1_CAN ((uint8_t)0x01) /* CAN Alternate Function mapping */
+#define GPIO_AF1_SPI2 ((uint8_t)0x01) /* SPI2 Alternate Function mapping */
+#define GPIO_AF1_TIM9 ((uint8_t)0x01) /* TIM9 Alternate Function mapping */
+#define GPIO_AF1_SPI1 ((uint8_t)0x01) /* SPI1 Alternate Function mapping */
+#define GPIO_AF1_I2C1 ((uint8_t)0x01) /* I2C1 Alternate Function mapping */
+#define GPIO_AF1 ((uint8_t)0x01) /* test Alternate Function mapping */
+/**
+ *
+ */
+
+/*
+ * Alternate function AF2
+ */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_LPTIM ((uint8_t)0x02) /* LPTIM Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_LPUART ((uint8_t)0x02) /* LPUART Alternate Function mapping */
+/**
+ *
+ */
+
+/*
+ * Alternate function AF3
+ */
+#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /* EVENTOUT Alternate Function mapping */
+
+/**
+ *
+ */
+
+/*
+ * Alternate function AF4
+ */
+#define GPIO_AF4_USART2 ((uint8_t)0x04) /* USART2 Alternate Function mapping */
+#define GPIO_AF4_LPUART ((uint8_t)0x04) /* LPUART Alternate Function mapping */
+#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */
+#define GPIO_AF4_TIM3 ((uint8_t)0x04) /* TIM3 Alternate Function mapping*/
+#define GPIO_AF4_SPI1 ((uint8_t)0x04) /* SPI1 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_USART3 ((uint8_t)0x04) /* USART3 Alternate Function mapping */
+/**
+ *
+ */
+
+/*
+ * Alternate function AF5
+ */
+#define GPIO_AF5_TIM2 ((uint8_t)0x05) /* TIM2 Alternate Function mapping */
+#define GPIO_AF5_TIM1 ((uint8_t)0x05) /* TIM1 Alternate Function mapping */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
+#define GPIO_AF5_I2C2 ((uint8_t)0x05) /* I2C2 Alternate Function mapping */
+#define GPIO_AF5_LPTIM ((uint8_t)0x05) /* LPTIM Alternate Function mapping */
+#define GPIO_AF5_CAN ((uint8_t)0x05) /* CAN Alternate Function mapping */
+#define GPIO_AF5_USART3 ((uint8_t)0x05) /* USART3 Alternate Function mapping */
+
+/**
+ *
+ */
+
+/*
+ * Alternate function AF6
+ */
+
+#define GPIO_AF6_USART2 ((uint8_t)0x06) /* USART2 Alternate Function mapping */
+#define GPIO_AF6_LPUART ((uint8_t)0x06) /* LPUART Alternate Function mapping */
+#define GPIO_AF6_TIM5 ((uint8_t)0x06) /* TIM5 Alternate Function mapping */
+#define GPIO_AF6_TIM8 ((uint8_t)0x06) /* TIM8 Alternate Function mapping */
+#define GPIO_AF6_I2C2 ((uint8_t)0x06) /* I2C2 Alternate Function mapping */
+#define GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */
+#define GPIO_AF6_UART5 ((uint8_t)0x06) /* UART5 Alternate Function mapping */
+#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1 Alternate Function mapping */
+/**
+ *
+ */
+
+/*
+ * Alternate function AF7
+ */
+#define GPIO_AF7_COMP1 ((uint8_t)0x07) /* COMP1 Alternate Function mapping */
+#define GPIO_AF7_COMP2 ((uint8_t)0x07) /* COMP2 Alternate Function mapping */
+#define GPIO_AF7_I2C1 ((uint8_t)0x07) /* I2C1 Alternate Function mapping */
+#define GPIO_AF7_TIM8 ((uint8_t)0x07) /* TIM8 Alternate Function mapping */
+#define GPIO_AF7_TIM5 ((uint8_t)0x07) /* TIM5 Alternate Function mapping */
+#define GPIO_AF7_LPUART ((uint8_t)0x07) /* LPUART Alternate Function mapping */
+#define GPIO_AF7_UART5 ((uint8_t)0x07) /* UART5 Alternate Function mapping */
+#define GPIO_AF7_TIM1 ((uint8_t)0x07) /* TIM1 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+
+/**
+ *
+ */
+
+ /*
+ * Alternate function AF8
+ */
+#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
+#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
+#define GPIO_AF8_LPTIM ((uint8_t)0x08) /* LPTIM Alternate Function mapping */
+#define GPIO_AF8_MCO ((uint8_t)0x08) /* MCO Alternate Function mapping */
+
+/**
+ *
+ */
+
+ /*
+ * Alternate function AF9
+ */
+#define GPIO_AF9_RTC ((uint8_t)0x09) /* RTC Alternate Function mapping */
+#define GPIO_AF9_COMP1 ((uint8_t)0x09) /* COMP1 Alternate Function mapping */
+#define GPIO_AF9_TSC ((uint8_t)0x09) /* COMP1 Alternate Function mapping */
+
+/**
+ *
+ */
+
+ /*
+ * Alternate function AF10
+ */
+#define GPIO_AF10_LCD ((uint8_t)0x0A) /* LCD Alternate Function mapping */
+
+/**
+ *
+ */
+
+ /*
+ * Alternate function AF11
+ */
+#define GPIO_AF11_LCD ((uint8_t)0x0B) /* LCD Alternate Function mapping */
+
+
+ /*
+ * Alternate function AF15
+ */
+#define GPIO_AF15 ((uint8_t)0x0F) /* NON Alternate Function mapping */
+
+#define GPIO_NO_AF (GPIO_AF15)
+/**
+ * @}
+ */
+
+
+/**
+ * IS_GPIO_AF macro definition
+ */
+
+#define IS_GPIO_AF(__AF__) (((__AF__) == GPIO_AF0_SPI1) || ((__AF__) == GPIO_AF1_TIM5) || \
+ ((__AF__) == GPIO_AF0_LPTIM) || ((__AF__) == GPIO_AF1_USART1) || \
+ ((__AF__) == GPIO_AF0_SPI2) || ((__AF__) == GPIO_AF1_I2C2) || \
+ ((__AF__) == GPIO_AF0_TIM8) || ((__AF__) == GPIO_AF1_CAN) || \
+ ((__AF__) == GPIO_AF0_USART1) || ((__AF__) == GPIO_AF1_SPI2) || \
+ ((__AF__) == GPIO_AF0_USART3) || ((__AF__) == GPIO_AF1_TIM9) || \
+ ((__AF__) == GPIO_AF0_LPUART) || ((__AF__) == GPIO_AF1_SPI1) || \
+ ((__AF__) == GPIO_AF0_USART2) || ((__AF__) == GPIO_AF1_I2C1) || \
+ ((__AF__) == GPIO_AF3_EVENTOUT) || ((__AF__) == GPIO_AF2_TIM2) || \
+ ((__AF__) == GPIO_AF5_TIM2) || ((__AF__) == GPIO_AF2_TIM3) || \
+ ((__AF__) == GPIO_AF5_TIM1) || ((__AF__) == GPIO_AF2_TIM1) || \
+ ((__AF__) == GPIO_AF5_SPI1) || ((__AF__) == GPIO_AF2_LPTIM) || \
+ ((__AF__) == GPIO_AF5_SPI2) || ((__AF__) == GPIO_AF2_TIM4) || \
+ ((__AF__) == GPIO_AF5_I2C2) || ((__AF__) == GPIO_AF2_LPUART) || \
+ ((__AF__) == GPIO_AF5_LPTIM) || ((__AF__) == GPIO_AF4_USART2) || \
+ ((__AF__) == GPIO_AF5_CAN) || ((__AF__) == GPIO_AF4_LPUART) || \
+ ((__AF__) == GPIO_AF5_USART3) || ((__AF__) == GPIO_AF4_USART1) || \
+ ((__AF__) == GPIO_AF6_USART2) || ((__AF__) == GPIO_AF4_TIM3) || \
+ ((__AF__) == GPIO_AF6_LPUART) || ((__AF__) == GPIO_AF4_SPI1) || \
+ ((__AF__) == GPIO_AF6_TIM5) || ((__AF__) == GPIO_AF4_I2C1) || \
+ ((__AF__) == GPIO_AF6_TIM8) || ((__AF__) == GPIO_AF4_USART3) || \
+ ((__AF__) == GPIO_AF6_I2C2) || ((__AF__) == GPIO_AF7_COMP1) || \
+ ((__AF__) == GPIO_AF6_UART4) || ((__AF__) == GPIO_AF7_COMP2) || \
+ ((__AF__) == GPIO_AF6_UART5) || ((__AF__) == GPIO_AF7_I2C1) || \
+ ((__AF__) == GPIO_AF6_SPI1) || ((__AF__) == GPIO_AF7_TIM8) || \
+ ((__AF__) == GPIO_AF8_COMP1) || ((__AF__) == GPIO_AF7_TIM5) || \
+ ((__AF__) == GPIO_AF8_COMP2) || ((__AF__) == GPIO_AF7_LPUART) || \
+ ((__AF__) == GPIO_AF8_LPTIM) || ((__AF__) == GPIO_AF7_UART5) || \
+ ((__AF__) == GPIO_AF9_RTC) || ((__AF__) == GPIO_AF7_TIM1) || \
+ ((__AF__) == GPIO_AF9_COMP1) || ((__AF__) == GPIO_AF7_USART3) || \
+ ((__AF__) == GPIO_AF10_LCD) || ((__AF__) == GPIO_AF11_LCD) || \
+ ((__AF__) == GPIO_AF15) || ((__AF__) == GPIO_NO_AF))
+
+
+
+
+
+/**
+ * @}
+ */
+/** @defgroup GPIO Alternate function remaping
+ * @{
+ */
+#define AFIO_SPI1_NSS (11U)
+#define AFIO_SPI2_NSS (10U)
+
+#define IS_AFIO_SPIX(_PARAMETER_) \
+ (((_PARAMETER_) == AFIO_SPI1_NSS) ||((_PARAMETER_) == AFIO_SPI2_NSS))
+typedef enum
+{
+ AFIO_SPI_NSS_High_IMPEDANCE = 0U,
+ AFIO_SPI_NSS_High_LEVEL = 1U
+}AFIO_SPI_NSSType;
+
+#define IS_AFIO_SPI_NSS(_PARAMETER_) \
+ (((_PARAMETER_) == AFIO_SPI_NSS_High_IMPEDANCE) ||((_PARAMETER_) == AFIO_SPI_NSS_High_LEVEL))
+
+
+typedef enum
+{
+ AFIO_ADC_ETRI= 9U,
+ AFIO_ADC_ETRR = 8U
+}AFIO_ADC_ETRType;
+
+typedef enum
+{
+ AFIO_ADC_TRIG_EXTI_0 = 0x0U,
+ AFIO_ADC_TRIG_EXTI_1 = 0x01U,
+ AFIO_ADC_TRIG_EXTI_2,
+ AFIO_ADC_TRIG_EXTI_3,
+ AFIO_ADC_TRIG_EXTI_4,
+ AFIO_ADC_TRIG_EXTI_5,
+ AFIO_ADC_TRIG_EXTI_6,
+ AFIO_ADC_TRIG_EXTI_7,
+ AFIO_ADC_TRIG_EXTI_8,
+ AFIO_ADC_TRIG_EXTI_9,
+ AFIO_ADC_TRIG_EXTI_10,
+ AFIO_ADC_TRIG_EXTI_11,
+ AFIO_ADC_TRIG_EXTI_12,
+ AFIO_ADC_TRIG_EXTI_13,
+ AFIO_ADC_TRIG_EXTI_14,
+ AFIO_ADC_TRIG_EXTI_15,
+ AFIO_ADC_TRIG_TIM8_CH3,
+ AFIO_ADC_TRIG_TIM8_CH4
+}AFIO_ADC_Trig_RemapType;
+
+#define IS_AFIO_ADC_ETR(_PARAMETER_) \
+ (((_PARAMETER_) == AFIO_ADC_ETRI) ||((_PARAMETER_) == AFIO_ADC_ETRR))
+#define IS_AFIO_ADC_ETRI(_PARAMETER_) \
+ (((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_0) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_1)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_2) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_3)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_4) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_5)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_6) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_7)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_8) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_9)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_10) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_11)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_12) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_13)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_14) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_15)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_TIM8_CH4))
+
+#define IS_AFIO_ADC_ETRR(_PARAMETER_) \
+ (((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_0) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_1)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_2) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_3)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_4) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_5)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_6) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_7)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_8) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_9)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_10) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_11)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_12) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_13) ||\
+ ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_14) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_15)|| \
+ ((_PARAMETER_) == AFIO_ADC_TRIG_TIM8_CH3))
+
+ /**
+ * @}
+ */
+
+/** @addtogroup GPIO_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Exported_Functions
+ * @{
+ */
+
+void GPIO_DeInit(GPIO_Module* GPIOx);
+void GPIO_AFIOInitDefault(void);
+void GPIO_InitPeripheral(GPIO_Module* GPIOx, GPIO_InitType* GPIO_InitStruct);
+void GPIO_InitStruct(GPIO_InitType* GPIO_InitStruct);
+uint8_t GPIO_ReadInputDataBit(GPIO_Module* GPIOx, uint16_t Pin);
+uint16_t GPIO_ReadInputData(GPIO_Module* GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_Module* GPIOx, uint16_t Pin);
+uint16_t GPIO_ReadOutputData(GPIO_Module* GPIOx);
+void GPIO_SetBits(GPIO_Module* GPIOx, uint16_t Pin);
+void GPIO_ResetBits(GPIO_Module* GPIOx, uint16_t Pin);
+void GPIO_WriteBit(GPIO_Module* GPIOx, uint16_t Pin, Bit_OperateType BitCmd);
+void GPIO_Write(GPIO_Module* GPIOx, uint16_t PortVal);
+void GPIO_ConfigPinLock(GPIO_Module* GPIOx, uint16_t Pin);
+void GPIO_ConfigEventOutput(uint8_t PortSource, uint8_t PinSource);
+void GPIO_CtrlEventOutput(FunctionalState Cmd);
+void GPIO_ConfigPinRemap(uint8_t PortSource, uint8_t PinSource, uint32_t AlternateFunction);
+void GPIO_ConfigEXTILine(uint8_t PortSource, uint8_t PinSource);
+
+void AFIO_ConfigSPINSSMode(uint32_t AFIO_SPIx_NSS,AFIO_SPI_NSSType SpiNssType);
+void AFIO_ConfigADCExternalTrigRemap(AFIO_ADC_ETRType ADCETRType,AFIO_ADC_Trig_RemapType ADCTrigRemap);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32L43X_GPIO_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_i2c.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_i2c.h
new file mode 100644
index 0000000000..921f6d8936
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_i2c.h
@@ -0,0 +1,671 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_i2c.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L43X_I2C_H__
+#define __N32L43X_I2C_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l43x.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @{
+ */
+
+/** @addtogroup I2C_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief I2C Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t ClkSpeed; /*!< Specifies the clock frequency.
+ This parameter must be set to a value lower than 400kHz */
+
+ uint16_t BusMode; /*!< Specifies the I2C mode.
+ This parameter can be a value of @ref I2C_BusMode */
+
+ uint16_t FmDutyCycle; /*!< Specifies the I2C fast mode duty cycle.
+ This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+ uint16_t OwnAddr1; /*!< Specifies the first device own address.
+ This parameter can be a 7-bit or 10-bit address. */
+
+ uint16_t AckEnable; /*!< Enables or disables the acknowledgement.
+ This parameter can be a value of @ref I2C_acknowledgement */
+
+ uint16_t AddrMode; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
+ This parameter can be a value of @ref I2C_acknowledged_address */
+} I2C_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Exported_Constants
+ * @{
+ */
+
+#define IS_I2C_PERIPH(PERIPH) (((PERIPH) == I2C1) || ((PERIPH) == I2C2))
+/** @addtogroup I2C_BusMode
+ * @{
+ */
+
+#define I2C_BUSMODE_I2C ((uint16_t)0x0000)
+#define I2C_BUSMODE_SMBDEVICE ((uint16_t)0x0002)
+#define I2C_BUSMODE_SMBHOST ((uint16_t)0x000A)
+#define IS_I2C_BUS_MODE(MODE) \
+ (((MODE) == I2C_BUSMODE_I2C) || ((MODE) == I2C_BUSMODE_SMBDEVICE) || ((MODE) == I2C_BUSMODE_SMBHOST))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_duty_cycle_in_fast_mode
+ * @{
+ */
+
+#define I2C_FMDUTYCYCLE_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
+#define I2C_FMDUTYCYCLE_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
+#define IS_I2C_FM_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_FMDUTYCYCLE_16_9) || ((CYCLE) == I2C_FMDUTYCYCLE_2))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_acknowledgement
+ * @{
+ */
+
+#define I2C_ACKEN ((uint16_t)0x0400)
+#define I2C_ACKDIS ((uint16_t)0x0000)
+#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_ACKEN) || ((STATE) == I2C_ACKDIS))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_transfer_direction
+ * @{
+ */
+
+#define I2C_DIRECTION_SEND ((uint8_t)0x00)
+#define I2C_DIRECTION_RECV ((uint8_t)0x01)
+#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_DIRECTION_SEND) || ((DIRECTION) == I2C_DIRECTION_RECV))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_acknowledged_address
+ * @{
+ */
+
+#define I2C_ADDR_MODE_7BIT ((uint16_t)0x4000)
+#define I2C_ADDR_MODE_10BIT ((uint16_t)0xC000)
+#define IS_I2C_ADDR_MODE(ADDRESS) (((ADDRESS) == I2C_ADDR_MODE_7BIT) || ((ADDRESS) == I2C_ADDR_MODE_10BIT))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_registers
+ * @{
+ */
+
+#define I2C_REG_CTRL1 ((uint8_t)0x00)
+#define I2C_REG_CTRL2 ((uint8_t)0x04)
+#define I2C_REG_OADDR1 ((uint8_t)0x08)
+#define I2C_REG_OADDR2 ((uint8_t)0x0C)
+#define I2C_REG_DAT ((uint8_t)0x10)
+#define I2C_REG_STS1 ((uint8_t)0x14)
+#define I2C_REG_STS2 ((uint8_t)0x18)
+#define I2C_REG_CLKCTRL ((uint8_t)0x1C)
+#define I2C_REG_TMRISE ((uint8_t)0x20)
+#define IS_I2C_REG(REGISTER) \
+ (((REGISTER) == I2C_REG_CTRL1) || ((REGISTER) == I2C_REG_CTRL2) || ((REGISTER) == I2C_REG_OADDR1) \
+ || ((REGISTER) == I2C_REG_OADDR2) || ((REGISTER) == I2C_REG_DAT) || ((REGISTER) == I2C_REG_STS1) \
+ || ((REGISTER) == I2C_REG_STS2) || ((REGISTER) == I2C_REG_CLKCTRL) || ((REGISTER) == I2C_REG_TMRISE))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_SMBus_alert_pin_level
+ * @{
+ */
+
+#define I2C_SMBALERT_LOW ((uint16_t)0x2000)
+#define I2C_SMBALERT_HIGH ((uint16_t)0xDFFF)
+#define IS_I2C_SMB_ALERT(ALERT) (((ALERT) == I2C_SMBALERT_LOW) || ((ALERT) == I2C_SMBALERT_HIGH))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_PEC_position
+ * @{
+ */
+
+#define I2C_PEC_POS_NEXT ((uint16_t)0x0800)
+#define I2C_PEC_POS_CURRENT ((uint16_t)0xF7FF)
+#define IS_I2C_PEC_POS(POSITION) (((POSITION) == I2C_PEC_POS_NEXT) || ((POSITION) == I2C_PEC_POS_CURRENT))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_NCAK_position
+ * @{
+ */
+
+#define I2C_NACK_POS_NEXT ((uint16_t)0x0800)
+#define I2C_NACK_POS_CURRENT ((uint16_t)0xF7FF)
+#define IS_I2C_NACK_POS(POSITION) (((POSITION) == I2C_NACK_POS_NEXT) || ((POSITION) == I2C_NACK_POS_CURRENT))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_interrupts_definition
+ * @{
+ */
+
+#define I2C_INT_BUF ((uint16_t)0x0400)
+#define I2C_INT_EVENT ((uint16_t)0x0200)
+#define I2C_INT_ERR ((uint16_t)0x0100)
+#define IS_I2C_CFG_INT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_interrupts_definition
+ * @{
+ */
+
+#define I2C_INT_SMBALERT ((uint32_t)0x01008000)
+#define I2C_INT_TIMOUT ((uint32_t)0x01004000)
+#define I2C_INT_PECERR ((uint32_t)0x01001000)
+#define I2C_INT_OVERRUN ((uint32_t)0x01000800)
+#define I2C_INT_ACKFAIL ((uint32_t)0x01000400)
+#define I2C_INT_ARLOST ((uint32_t)0x01000200)
+#define I2C_INT_BUSERR ((uint32_t)0x01000100)
+#define I2C_INT_TXDATE ((uint32_t)0x06000080)
+#define I2C_INT_RXDATNE ((uint32_t)0x06000040)
+#define I2C_INT_STOPF ((uint32_t)0x02000010)
+#define I2C_INT_ADDR10F ((uint32_t)0x02000008)
+#define I2C_INT_BYTEF ((uint32_t)0x02000004)
+#define I2C_INT_ADDRF ((uint32_t)0x02000002)
+#define I2C_INT_STARTBF ((uint32_t)0x02000001)
+
+#define IS_I2C_CLR_INT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
+
+#define IS_I2C_GET_INT(IT) \
+ (((IT) == I2C_INT_SMBALERT) || ((IT) == I2C_INT_TIMOUT) || ((IT) == I2C_INT_PECERR) || ((IT) == I2C_INT_OVERRUN) \
+ || ((IT) == I2C_INT_ACKFAIL) || ((IT) == I2C_INT_ARLOST) || ((IT) == I2C_INT_BUSERR) || ((IT) == I2C_INT_TXDATE) \
+ || ((IT) == I2C_INT_RXDATNE) || ((IT) == I2C_INT_STOPF) || ((IT) == I2C_INT_ADDR10F) || ((IT) == I2C_INT_BYTEF) \
+ || ((IT) == I2C_INT_ADDRF) || ((IT) == I2C_INT_STARTBF))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_flags_definition
+ * @{
+ */
+
+/**
+ * @brief STS2 register flags
+ */
+
+#define I2C_FLAG_DUALFLAG ((uint32_t)0x00800000)
+#define I2C_FLAG_SMBHADDR ((uint32_t)0x00400000)
+#define I2C_FLAG_SMBDADDR ((uint32_t)0x00200000)
+#define I2C_FLAG_GCALLADDR ((uint32_t)0x00100000)
+#define I2C_FLAG_TRF ((uint32_t)0x00040000)
+#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
+#define I2C_FLAG_MSMODE ((uint32_t)0x00010000)
+
+/**
+ * @brief STS1 register flags
+ */
+
+#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
+#define I2C_FLAG_TIMOUT ((uint32_t)0x10004000)
+#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
+#define I2C_FLAG_OVERRUN ((uint32_t)0x10000800)
+#define I2C_FLAG_ACKFAIL ((uint32_t)0x10000400)
+#define I2C_FLAG_ARLOST ((uint32_t)0x10000200)
+#define I2C_FLAG_BUSERR ((uint32_t)0x10000100)
+#define I2C_FLAG_TXDATE ((uint32_t)0x10000080)
+#define I2C_FLAG_RXDATNE ((uint32_t)0x10000040)
+#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
+#define I2C_FLAG_ADDR10F ((uint32_t)0x10000008)
+#define I2C_FLAG_BYTEF ((uint32_t)0x10000004)
+#define I2C_FLAG_ADDRF ((uint32_t)0x10000002)
+#define I2C_FLAG_STARTBF ((uint32_t)0x10000001)
+
+#define IS_I2C_CLR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
+
+#define IS_I2C_GET_FLAG(FLAG) \
+ (((FLAG) == I2C_FLAG_DUALFLAG) || ((FLAG) == I2C_FLAG_SMBHADDR) || ((FLAG) == I2C_FLAG_SMBDADDR) \
+ || ((FLAG) == I2C_FLAG_GCALLADDR) || ((FLAG) == I2C_FLAG_TRF) || ((FLAG) == I2C_FLAG_BUSY) \
+ || ((FLAG) == I2C_FLAG_MSMODE) || ((FLAG) == I2C_FLAG_SMBALERT) || ((FLAG) == I2C_FLAG_TIMOUT) \
+ || ((FLAG) == I2C_FLAG_PECERR) || ((FLAG) == I2C_FLAG_OVERRUN) || ((FLAG) == I2C_FLAG_ACKFAIL) \
+ || ((FLAG) == I2C_FLAG_ARLOST) || ((FLAG) == I2C_FLAG_BUSERR) || ((FLAG) == I2C_FLAG_TXDATE) \
+ || ((FLAG) == I2C_FLAG_RXDATNE) || ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADDR10F) \
+ || ((FLAG) == I2C_FLAG_BYTEF) || ((FLAG) == I2C_FLAG_ADDRF) || ((FLAG) == I2C_FLAG_STARTBF))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Events
+ * @{
+ */
+
+/*========================================
+
+ I2C Master Events (Events grouped in order of communication)
+ ==========================================*/
+/**
+ * @brief Communication start
+ *
+ * After sending the START condition (I2C_GenerateStart() function) the master
+ * has to wait for this event. It means that the Start condition has been correctly
+ * released on the I2C bus (the bus is free, no other devices is communicating).
+ *
+ */
+/* Master mode */
+#define I2C_ROLE_MASTER ((uint32_t)0x00010000) /* MSMODE */
+/* --EV5 */
+#define I2C_EVT_MASTER_MODE_FLAG ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
+
+/**
+ * @brief Address Acknowledge
+ *
+ * After checking on EV5 (start condition correctly released on the bus), the
+ * master sends the address of the slave(s) with which it will communicate
+ * (I2C_SendAddr7bit() function, it also determines the direction of the communication:
+ * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
+ * his address. If an acknowledge is sent on the bus, one of the following events will
+ * be set:
+ *
+ * 1) In case of Master Receiver (7-bit addressing): the I2C_EVT_MASTER_RXMODE_FLAG
+ * event is set.
+ *
+ * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVT_MASTER_TXMODE_FLAG
+ * is set
+ *
+ * 3) In case of 10-Bit addressing mode, the master (just after generating the START
+ * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
+ * function). Then master should wait on EV9. It means that the 10-bit addressing
+ * header has been correctly sent on the bus. Then master should send the second part of
+ * the 10-bit address (LSB) using the function I2C_SendAddr7bit(). Then master
+ * should wait for event EV6.
+ *
+ */
+
+/* --EV6 */
+#define I2C_EVT_MASTER_TXMODE_FLAG ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
+#define I2C_EVT_MASTER_RXMODE_FLAG ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
+/* --EV9 */
+#define I2C_EVT_MASTER_MODE_ADDRESS10_FLAG ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
+
+/**
+ * @brief Communication events
+ *
+ * If a communication is established (START condition generated and slave address
+ * acknowledged) then the master has to check on one of the following events for
+ * communication procedures:
+ *
+ * 1) Master Receiver mode: The master has to wait on the event EV7 then to read
+ * the data received from the slave (I2C_RecvData() function).
+ *
+ * 2) Master Transmitter mode: The master has to send data (I2C_SendData()
+ * function) then to wait on event EV8 or EV8_2.
+ * These two events are similar:
+ * - EV8 means that the data has been written in the data register and is
+ * being shifted out.
+ * - EV8_2 means that the data has been physically shifted out and output
+ * on the bus.
+ * In most cases, using EV8 is sufficient for the application.
+ * Using EV8_2 leads to a slower communication but ensure more reliable test.
+ * EV8_2 is also more suitable than EV8 for testing on the last data transmission
+ * (before Stop condition generation).
+ *
+ * @note In case the user software does not guarantee that this event EV7 is
+ * managed before the current byte end of transfer, then user may check on EV7
+ * and BTF flag at the same time (ie. (I2C_EVT_MASTER_DATA_RECVD_FLAG | I2C_FLAG_BYTEF)).
+ * In this case the communication may be slower.
+ *
+ */
+
+/* Master RECEIVER mode -----------------------------*/
+/* --EV7 */
+#define I2C_EVT_MASTER_DATA_RECVD_FLAG ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
+/* EV7x shifter register full */
+#define I2C_EVT_MASTER_SFT_DATA_RECVD_FLAG ((uint32_t)0x00030044) /* BUSY, MSMODE, BSF and RXDATNE flags */
+
+/* Master TRANSMITTER mode --------------------------*/
+/* --EV8 */
+#define I2C_EVT_MASTER_DATA_SENDING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
+/* --EV8_2 */
+#define I2C_EVT_MASTER_DATA_SENDED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
+
+/*========================================
+
+ I2C Slave Events (Events grouped in order of communication)
+ ==========================================*/
+
+/**
+ * @brief Communication start events
+ *
+ * Wait on one of these events at the start of the communication. It means that
+ * the I2C peripheral detected a Start condition on the bus (generated by master
+ * device) followed by the peripheral address. The peripheral generates an ACK
+ * condition on the bus (if the acknowledge feature is enabled through function
+ * I2C_ConfigAck()) and the events listed above are set :
+ *
+ * 1) In normal case (only one address managed by the slave), when the address
+ * sent by the master matches the own address of the peripheral (configured by
+ * OwnAddr1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
+ * (where XXX could be TRANSMITTER or RECEIVER).
+ *
+ * 2) In case the address sent by the master matches the second address of the
+ * peripheral (configured by the function I2C_ConfigOwnAddr2() and enabled
+ * by the function I2C_EnableDualAddr()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
+ * (where XXX could be TRANSMITTER or RECEIVER) are set.
+ *
+ * 3) In case the address sent by the master is General Call (address 0x00) and
+ * if the General Call is enabled for the peripheral (using function I2C_EnableGeneralCall())
+ * the following event is set I2C_EVT_SLAVE_GCALLADDR_MATCHED.
+ *
+ */
+
+/* --EV1 (all the events below are variants of EV1) */
+/* 1) Case of One Single Address managed by the slave */
+#define I2C_EVT_SLAVE_RECV_ADDR_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
+#define I2C_EVT_SLAVE_SEND_ADDR_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
+
+/* 2) Case of Dual address managed by the slave */
+#define I2C_EVT_SLAVE_RECV_ADDR2_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
+#define I2C_EVT_SLAVE_SEND_ADDR2_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
+
+/* 3) Case of General Call enabled for the slave */
+#define I2C_EVT_SLAVE_GCALLADDR_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
+
+/**
+ * @brief Communication events
+ *
+ * Wait on one of these events when EV1 has already been checked and:
+ *
+ * - Slave RECEIVER mode:
+ * - EV2: When the application is expecting a data byte to be received.
+ * - EV4: When the application is expecting the end of the communication: master
+ * sends a stop condition and data transmission is stopped.
+ *
+ * - Slave Transmitter mode:
+ * - EV3: When a byte has been transmitted by the slave and the application is expecting
+ * the end of the byte transmission. The two events I2C_EVT_SLAVE_DATA_SENDED and
+ * I2C_EVT_SLAVE_DATA_SENDING are similar. The second one can optionally be
+ * used when the user software doesn't guarantee the EV3 is managed before the
+ * current byte end of transfer.
+ * - EV3_2: When the master sends a NACK in order to tell slave that data transmission
+ * shall end (before sending the STOP condition). In this case slave has to stop sending
+ * data bytes and expect a Stop condition on the bus.
+ *
+ * @note In case the user software does not guarantee that the event EV2 is
+ * managed before the current byte end of transfer, then user may check on EV2
+ * and BTF flag at the same time (ie. (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_BYTEF)).
+ * In this case the communication may be slower.
+ *
+ */
+
+/* Slave RECEIVER mode --------------------------*/
+/* --EV2 */
+#define I2C_EVT_SLAVE_DATA_RECVD ((uint32_t)0x00020040) /* BUSY and RXNE flags */
+/* --EV2x */
+#define I2C_EVT_SLAVE_DATA_RECVD_NOBUSY ((uint32_t)0x00000040) /* no BUSY and RXDATNE flags */
+/* --EV4 */
+#define I2C_EVT_SLAVE_STOP_RECVD ((uint32_t)0x00000010) /* STOPF flag */
+
+/* Slave TRANSMITTER mode -----------------------*/
+/* --EV3 */
+#define I2C_EVT_SLAVE_DATA_SENDED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
+#define I2C_EVT_SLAVE_DATA_SENDING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
+/* --EV3_2 */
+#define I2C_EVT_SLAVE_ACK_MISS ((uint32_t)0x00000400) /* AF flag */
+
+/*=========================== End of Events Description ==========================================*/
+
+#define IS_I2C_EVT(EVENT) \
+ (((EVENT) == I2C_EVT_SLAVE_SEND_ADDR_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_RECV_ADDR_MATCHED) \
+ || ((EVENT) == I2C_EVT_SLAVE_SEND_ADDR2_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_RECV_ADDR2_MATCHED) \
+ || ((EVENT) == I2C_EVT_SLAVE_GCALLADDR_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_DATA_RECVD) \
+ || ((EVENT) == (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_DUALFLAG)) \
+ || ((EVENT) == (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_GCALLADDR)) || ((EVENT) == I2C_EVT_SLAVE_DATA_SENDED) \
+ || ((EVENT) == (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_DUALFLAG)) \
+ || ((EVENT) == (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_GCALLADDR)) || ((EVENT) == I2C_EVT_SLAVE_STOP_RECVD) \
+ || ((EVENT) == I2C_EVT_MASTER_MODE_FLAG) || ((EVENT) == I2C_EVT_MASTER_TXMODE_FLAG) \
+ || ((EVENT) == I2C_EVT_MASTER_RXMODE_FLAG) || ((EVENT) == I2C_EVT_MASTER_DATA_RECVD_FLAG) \
+ || ((EVENT) == I2C_EVT_MASTER_DATA_SENDED) || ((EVENT) == I2C_EVT_MASTER_DATA_SENDING) \
+ || ((EVENT) == I2C_EVT_MASTER_MODE_ADDRESS10_FLAG) || ((EVENT) == I2C_EVT_SLAVE_ACK_MISS))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_own_address1
+ * @{
+ */
+
+#define IS_I2C_OWN_ADDR1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_clock_speed
+ * @{
+ */
+
+//#define IS_I2C_CLK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
+#define IS_I2C_CLK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 1000000))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Exported_Functions
+ * @{
+ */
+
+void I2C_DeInit(I2C_Module* I2Cx);
+void I2C_Init(I2C_Module* I2Cx, I2C_InitType* I2C_InitStruct);
+void I2C_InitStruct(I2C_InitType* I2C_InitStruct);
+void I2C_Enable(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_EnableDMA(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_EnableDmaLastSend(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_GenerateStart(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_GenerateStop(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_ConfigAck(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_ConfigOwnAddr2(I2C_Module* I2Cx, uint8_t Address);
+void I2C_EnableDualAddr(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_EnableGeneralCall(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_ConfigInt(I2C_Module* I2Cx, uint16_t I2C_IT, FunctionalState Cmd);
+void I2C_SendData(I2C_Module* I2Cx, uint8_t Data);
+uint8_t I2C_RecvData(I2C_Module* I2Cx);
+void I2C_SendAddr7bit(I2C_Module* I2Cx, uint8_t Address, uint8_t I2C_Direction);
+uint16_t I2C_GetRegister(I2C_Module* I2Cx, uint8_t I2C_Register);
+void I2C_EnableSoftwareReset(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_ConfigNackLocation(I2C_Module* I2Cx, uint16_t I2C_NACKPosition);
+void I2C_ConfigSmbusAlert(I2C_Module* I2Cx, uint16_t I2C_SMBusAlert);
+void I2C_SendPEC(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_ConfigPecLocation(I2C_Module* I2Cx, uint16_t I2C_PECPosition);
+void I2C_ComputePec(I2C_Module* I2Cx, FunctionalState Cmd);
+uint8_t I2C_GetPec(I2C_Module* I2Cx);
+void I2C_EnableArp(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_EnableExtendClk(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_ConfigFastModeDutyCycle(I2C_Module* I2Cx, uint16_t FmDutyCycle);
+
+/**
+ * @brief
+ ****************************************************************************************
+ *
+ * I2C State Monitoring Functions
+ *
+ ****************************************************************************************
+ * This I2C driver provides three different ways for I2C state monitoring
+ * depending on the application requirements and constraints:
+ *
+ *
+ * 1) Basic state monitoring:
+ * Using I2C_CheckEvent() function:
+ * It compares the status registers (STS1 and STS2) content to a given event
+ * (can be the combination of one or more flags).
+ * It returns SUCCESS if the current status includes the given flags
+ * and returns ERROR if one or more flags are missing in the current status.
+ * - When to use:
+ * - This function is suitable for most applications as well as for startup
+ * activity since the events are fully described in the product reference manual
+ * (RM0008).
+ * - It is also suitable for users who need to define their own events.
+ * - Limitations:
+ * - If an error occurs (ie. error flags are set besides to the monitored flags),
+ * the I2C_CheckEvent() function may return SUCCESS despite the communication
+ * hold or corrupted real state.
+ * In this case, it is advised to use error interrupts to monitor the error
+ * events and handle them in the interrupt IRQ handler.
+ *
+ * @note
+ * For error management, it is advised to use the following functions:
+ * - I2C_ConfigInt() to configure and enable the error interrupts (I2C_INT_ERR).
+ * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
+ * Where x is the peripheral instance (I2C1, I2C2 ...)
+ * - I2C_GetFlag() or I2C_GetIntStatus() to be called into I2Cx_ER_IRQHandler()
+ * in order to determine which error occurred.
+ * - I2C_ClrFlag() or I2C_ClrIntPendingBit() and/or I2C_EnableSoftwareReset()
+ * and/or I2C_GenerateStop() in order to clear the error flag and source,
+ * and return to correct communication status.
+ *
+ *
+ * 2) Advanced state monitoring:
+ * Using the function I2C_GetLastEvent() which returns the image of both status
+ * registers in a single word (uint32_t) (Status Register 2 value is shifted left
+ * by 16 bits and concatenated to Status Register 1).
+ * - When to use:
+ * - This function is suitable for the same applications above but it allows to
+ * overcome the limitations of I2C_GetFlag() function (see below).
+ * The returned value could be compared to events already defined in the
+ * library (n32l43x_i2c.h) or to custom values defined by user.
+ * - This function is suitable when multiple flags are monitored at the same time.
+ * - At the opposite of I2C_CheckEvent() function, this function allows user to
+ * choose when an event is accepted (when all events flags are set and no
+ * other flags are set or just when the needed flags are set like
+ * I2C_CheckEvent() function).
+ * - Limitations:
+ * - User may need to define his own events.
+ * - Same remark concerning the error management is applicable for this
+ * function if user decides to check only regular communication flags (and
+ * ignores error flags).
+ *
+ *
+ * 3) Flag-based state monitoring:
+ * Using the function I2C_GetFlag() which simply returns the status of
+ * one single flag (ie. I2C_FLAG_RXDATNE ...).
+ * - When to use:
+ * - This function could be used for specific applications or in debug phase.
+ * - It is suitable when only one flag checking is needed (most I2C events
+ * are monitored through multiple flags).
+ * - Limitations:
+ * - When calling this function, the Status register is accessed. Some flags are
+ * cleared when the status register is accessed. So checking the status
+ * of one Flag, may clear other ones.
+ * - Function may need to be called twice or more in order to monitor one
+ * single event.
+ *
+ */
+
+/**
+ *
+ * 1) Basic state monitoring
+ *******************************************************************************
+ */
+ErrorStatus I2C_CheckEvent(I2C_Module* I2Cx, uint32_t I2C_EVENT);
+/**
+ *
+ * 2) Advanced state monitoring
+ *******************************************************************************
+ */
+uint32_t I2C_GetLastEvent(I2C_Module* I2Cx);
+/**
+ *
+ * 3) Flag-based state monitoring
+ *******************************************************************************
+ */
+FlagStatus I2C_GetFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG);
+/**
+ *
+ *******************************************************************************
+ */
+
+void I2C_ClrFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG);
+INTStatus I2C_GetIntStatus(I2C_Module* I2Cx, uint32_t I2C_IT);
+void I2C_ClrIntPendingBit(I2C_Module* I2Cx, uint32_t I2C_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32L43X_I2C_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_iwdg.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_iwdg.h
new file mode 100644
index 0000000000..dfd7618224
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_iwdg.h
@@ -0,0 +1,145 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_iwdg.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L43X_IWDG_H__
+#define __N32L43X_IWDG_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l43x.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup IWDG
+ * @{
+ */
+
+/** @addtogroup IWDG_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup IWDG_WriteAccess
+ * @{
+ */
+
+#define IWDG_WRITE_ENABLE ((uint16_t)0x5555)
+#define IWDG_WRITE_DISABLE ((uint16_t)0x0000)
+#define IS_IWDG_WRITE(ACCESS) (((ACCESS) == IWDG_WRITE_ENABLE) || ((ACCESS) == IWDG_WRITE_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_prescaler
+ * @{
+ */
+
+#define IWDG_PRESCALER_DIV4 ((uint8_t)0x00)
+#define IWDG_PRESCALER_DIV8 ((uint8_t)0x01)
+#define IWDG_PRESCALER_DIV16 ((uint8_t)0x02)
+#define IWDG_PRESCALER_DIV32 ((uint8_t)0x03)
+#define IWDG_PRESCALER_DIV64 ((uint8_t)0x04)
+#define IWDG_PRESCALER_DIV128 ((uint8_t)0x05)
+#define IWDG_PRESCALER_DIV256 ((uint8_t)0x06)
+#define IS_IWDG_PRESCALER_DIV(PRESCALER) \
+ (((PRESCALER) == IWDG_PRESCALER_DIV4) || ((PRESCALER) == IWDG_PRESCALER_DIV8) \
+ || ((PRESCALER) == IWDG_PRESCALER_DIV16) || ((PRESCALER) == IWDG_PRESCALER_DIV32) \
+ || ((PRESCALER) == IWDG_PRESCALER_DIV64) || ((PRESCALER) == IWDG_PRESCALER_DIV128) \
+ || ((PRESCALER) == IWDG_PRESCALER_DIV256))
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Flag
+ * @{
+ */
+
+#define IWDG_PVU_FLAG ((uint16_t)0x0001)
+#define IWDG_CRVU_FLAG ((uint16_t)0x0002)
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_PVU_FLAG) || ((FLAG) == IWDG_CRVU_FLAG))
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Exported_Functions
+ * @{
+ */
+
+void IWDG_WriteConfig(uint16_t IWDG_WriteAccess);
+void IWDG_SetPrescalerDiv(uint8_t IWDG_Prescaler);
+void IWDG_CntReload(uint16_t Reload);
+void IWDG_ReloadKey(void);
+void IWDG_Enable(void);
+FlagStatus IWDG_GetStatus(uint16_t IWDG_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32L43X_IWDG_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lcd.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lcd.h
new file mode 100644
index 0000000000..fc6992f273
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lcd.h
@@ -0,0 +1,735 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_lcd.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+
+#ifndef __N32L43X_LCD_H__
+#define __N32L43X_LCD_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "n32l43x.h"
+/** @addtogroup N32L43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup LCD
+ * @{
+ */
+
+/* LCD Exported constants --------------------------------------------------------*/
+/** @addtogroup LCD_Exported_Constants LCD Exported Constants
+ * @{
+ */
+
+/**
+ * @brief LCD error code
+ */
+typedef enum {
+ LCD_ERROR_OK = 0x00, /*!< No error */
+ LCD_ERROR_FCRSF = 0x01, /*!< Synchro flag error */
+ LCD_ERROR_UDR = 0x02, /*!< Update display request flag error */
+ LCD_ERROR_UDD = 0x03, /*!< Update display done flag error */
+ LCD_ERROR_ENSTS = 0x04, /*!< LCD enabled status flag error */
+ LCD_ERROR_RDY = 0x05, /*!< LCD VLCD ready flag error */
+ LCD_ERROR_PARAM = 0x06, /*!< LCD function parameter error */
+ LCD_ERROR_CLK = 0x07, /*!< LCD clock source fail error */
+}LCD_ErrorTypeDef;
+
+/**
+* @brief LCD normal timeout
+*/
+#define LCD_TIME_OUT (0x01000000)
+
+/**
+ * @defgroup LCD_Clock_Source
+ */
+#define LCD_CLK_SRC_LSI (RCC_RTCCLK_SRC_LSI) /*!< LSI*/
+#define LCD_CLK_SRC_LSE (RCC_LSE_ENABLE|RCC_RTCCLK_SRC_LSE) /*!< LSE */
+#define LCD_CLK_SRC_LSE_BYPASS (RCC_LSE_BYPASS|RCC_RTCCLK_SRC_LSE) /*!< LSE bypass */
+#define LCD_CLK_SRC_HSE_DIV32 (RCC_HSE_ENABLE|RCC_RTCCLK_SRC_HSE_DIV32) /*!< HSE */
+#define LCD_CLK_SRC_HSE_BYPASS_DIV32 (RCC_HSE_BYPASS|RCC_RTCCLK_SRC_HSE_DIV32) /*!< HSE bypass */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_RAMRegister
+ */
+#define LCD_RAM1_COM0 (0x00000000U)
+#define LCD_RAM2_COM0 (0x00000001U)
+#define LCD_RAM1_COM1 (0x00000002U)
+#define LCD_RAM2_COM1 (0x00000003U)
+#define LCD_RAM1_COM2 (0x00000004U)
+#define LCD_RAM2_COM2 (0x00000005U)
+#define LCD_RAM1_COM3 (0x00000006U)
+#define LCD_RAM2_COM3 (0x00000007U)
+#define LCD_RAM1_COM4 (0x00000008U)
+#define LCD_RAM2_COM4 (0x00000009U)
+#define LCD_RAM1_COM5 (0x0000000AU)
+#define LCD_RAM2_COM5 (0x0000000BU)
+#define LCD_RAM1_COM6 (0x0000000CU)
+#define LCD_RAM2_COM6 (0x0000000DU)
+#define LCD_RAM1_COM7 (0x0000000EU)
+#define LCD_RAM2_COM7 (0x0000000FU)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_Prescaler
+ */
+#define LCD_PRESCALER_1 (0x00000000U) /*!< CLKPS = LCDCLK */
+#define LCD_PRESCALER_2 (0x1UL << LCD_FCTRL_PRES_Pos) /*!< 0x00400000U CLKPS = LCDCLK/2 */
+#define LCD_PRESCALER_4 (0x2UL << LCD_FCTRL_PRES_Pos) /*!< 0x00800000U CLKPS = LCDCLK/4 */
+#define LCD_PRESCALER_8 (0x3UL << LCD_FCTRL_PRES_Pos) /*!< 0x00C00000U CLKPS = LCDCLK/8 */
+#define LCD_PRESCALER_16 (0x4UL << LCD_FCTRL_PRES_Pos) /*!< 0x01000000U CLKPS = LCDCLK/16 */
+#define LCD_PRESCALER_32 (0x5UL << LCD_FCTRL_PRES_Pos) /*!< 0x01400000U CLKPS = LCDCLK/32 */
+#define LCD_PRESCALER_64 (0x6UL << LCD_FCTRL_PRES_Pos) /*!< 0x01800000U CLKPS = LCDCLK/64 */
+#define LCD_PRESCALER_128 (0x7UL << LCD_FCTRL_PRES_Pos) /*!< 0x01C00000U CLKPS = LCDCLK/128 */
+#define LCD_PRESCALER_256 (0x8UL << LCD_FCTRL_PRES_Pos) /*!< 0x02000000U CLKPS = LCDCLK/256 */
+#define LCD_PRESCALER_512 (0x9UL << LCD_FCTRL_PRES_Pos) /*!< 0x02400000U CLKPS = LCDCLK/512 */
+#define LCD_PRESCALER_1024 (0xAUL << LCD_FCTRL_PRES_Pos) /*!< 0x02800000U CLKPS = LCDCLK/1024 */
+#define LCD_PRESCALER_2048 (0xBUL << LCD_FCTRL_PRES_Pos) /*!< 0x02C00000U CLKPS = LCDCLK/2048 */
+#define LCD_PRESCALER_4096 (0xCUL << LCD_FCTRL_PRES_Pos) /*!< 0x03000000U CLKPS = LCDCLK/4096 */
+#define LCD_PRESCALER_8192 (0xDUL << LCD_FCTRL_PRES_Pos) /*!< 0x03400000U CLKPS = LCDCLK/8192 */
+#define LCD_PRESCALER_16384 (0xEUL << LCD_FCTRL_PRES_Pos) /*!< 0x03800000U CLKPS = LCDCLK/16384 */
+#define LCD_PRESCALER_32768 (0xFUL << LCD_FCTRL_PRES_Pos) /*!< 0x03C00000U CLKPS = LCDCLK/32768 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_Divider
+ */
+#define LCD_DIV_16 (0x00000000U) /*!< CLKDIV = CLKPS/(16) */
+#define LCD_DIV_17 (0x1UL << LCD_FCTRL_DIV_Pos) /*!< 0x00040000U CLKDIV = CLKPS/(17) */
+#define LCD_DIV_18 (0x2UL << LCD_FCTRL_DIV_Pos) /*!< 0x00080000U CLKDIV = CLKPS/(18) */
+#define LCD_DIV_19 (0x3UL << LCD_FCTRL_DIV_Pos) /*!< 0x000C0000U CLKDIV = CLKPS/(19) */
+#define LCD_DIV_20 (0x4UL << LCD_FCTRL_DIV_Pos) /*!< 0x00100000U CLKDIV = CLKPS/(20) */
+#define LCD_DIV_21 (0x5UL << LCD_FCTRL_DIV_Pos) /*!< 0x00140000U CLKDIV = CLKPS/(21) */
+#define LCD_DIV_22 (0x6UL << LCD_FCTRL_DIV_Pos) /*!< 0x00180000U CLKDIV = CLKPS/(22) */
+#define LCD_DIV_23 (0x7UL << LCD_FCTRL_DIV_Pos) /*!< 0x001C0000U CLKDIV = CLKPS/(23) */
+#define LCD_DIV_24 (0x8UL << LCD_FCTRL_DIV_Pos) /*!< 0x00200000U CLKDIV = CLKPS/(24) */
+#define LCD_DIV_25 (0x9UL << LCD_FCTRL_DIV_Pos) /*!< 0x00240000U CLKDIV = CLKPS/(25) */
+#define LCD_DIV_26 (0xAUL << LCD_FCTRL_DIV_Pos) /*!< 0x00280000U CLKDIV = CLKPS/(26) */
+#define LCD_DIV_27 (0xBUL << LCD_FCTRL_DIV_Pos) /*!< 0x002C0000U CLKDIV = CLKPS/(27) */
+#define LCD_DIV_28 (0xCUL << LCD_FCTRL_DIV_Pos) /*!< 0x00300000U CLKDIV = CLKPS/(28) */
+#define LCD_DIV_29 (0xDUL << LCD_FCTRL_DIV_Pos) /*!< 0x00340000U CLKDIV = CLKPS/(29) */
+#define LCD_DIV_30 (0xEUL << LCD_FCTRL_DIV_Pos) /*!< 0x00380000U CLKDIV = CLKPS/(30) */
+#define LCD_DIV_31 (0xFUL << LCD_FCTRL_DIV_Pos) /*!< 0x003C0000U CLKDIV = CLKPS/(31) */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_Duty
+ */
+#define LCD_DUTY_STATIC (0x00000000U) /*!< Static duty */
+#define LCD_DUTY_1_2 (0x1UL << LCD_CTRL_DUTY_Pos) /*!< 0x00000004U 1/2 duty */
+#define LCD_DUTY_1_3 (0x2UL << LCD_CTRL_DUTY_Pos) /*!< 0x00000004U 1/3 duty */
+#define LCD_DUTY_1_4 (0x3UL << LCD_CTRL_DUTY_Pos) /*!< 0x00000004U 1/4 duty */
+#define LCD_DUTY_1_8 (0x4UL << LCD_CTRL_DUTY_Pos) /*!< 0x00000004U 1/8 duty */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_Bias
+ */
+#define LCD_BIAS_1_2 (0x00000000U) /*!< 1/2 Bias */
+#define LCD_BIAS_1_3 (0x1UL << LCD_CTRL_BIAS_Pos) /*!< 0x00000020U 1/3 Bias */
+#define LCD_BIAS_1_4 (0x2UL << LCD_CTRL_BIAS_Pos) /*!< 0x00000040U 1/4 Bias */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_Voltage_source
+ */
+#define LCD_VOLTAGESOURCE_INTERNAL (0x00000000U) /*!< Internal voltage source for the LCD */
+#define LCD_VOLTAGESOURCE_EXTERNAL (LCD_CTRL_VSEL) /*!< External voltage source for the LCD */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_Contrast
+ */
+#define LCD_CONTRASTLEVEL_0 (0x00000000U) /*!< Maximum Voltage = 2.60V */
+#define LCD_CONTRASTLEVEL_1 (0x1UL << LCD_FCTRL_CONTRAST_Pos) /*!< 0x00000400U Maximum Voltage = 2.73V */
+#define LCD_CONTRASTLEVEL_2 (0x2UL << LCD_FCTRL_CONTRAST_Pos) /*!< 0x00000800U Maximum Voltage = 2.86V */
+#define LCD_CONTRASTLEVEL_3 (0x3UL << LCD_FCTRL_CONTRAST_Pos) /*!< 0x00000C00U Maximum Voltage = 2.99V */
+#define LCD_CONTRASTLEVEL_4 (0x4UL << LCD_FCTRL_CONTRAST_Pos) /*!< 0x00001000U Maximum Voltage = 3.12V */
+#define LCD_CONTRASTLEVEL_5 (0x5UL << LCD_FCTRL_CONTRAST_Pos) /*!< 0x00001400U Maximum Voltage = 3.26V */
+#define LCD_CONTRASTLEVEL_6 (0x6UL << LCD_FCTRL_CONTRAST_Pos) /*!< 0x00001800U Maximum Voltage = 3.40V */
+#define LCD_CONTRASTLEVEL_7 (0x7UL << LCD_FCTRL_CONTRAST_Pos) /*!< 0x00001C00U Maximum Voltage = 3.55V */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_DeadTime
+ */
+#define LCD_DEADTIME_0 (0x00000000U) /*!< No dead Time */
+#define LCD_DEADTIME_1 (0x1UL << LCD_FCTRL_DEAD_Pos) /*!< 0x00000080U One Phase between different couple of Frame */
+#define LCD_DEADTIME_2 (0x2UL << LCD_FCTRL_DEAD_Pos) /*!< 0x00000100U Two Phase between different couple of Frame */
+#define LCD_DEADTIME_3 (0x3UL << LCD_FCTRL_DEAD_Pos) /*!< 0x00000180UThree Phase between different couple of Frame */
+#define LCD_DEADTIME_4 (0x4UL << LCD_FCTRL_DEAD_Pos) /*!< 0x00000200UFour Phase between different couple of Frame */
+#define LCD_DEADTIME_5 (0x5UL << LCD_FCTRL_DEAD_Pos) /*!< 0x00000280UFive Phase between different couple of Frame */
+#define LCD_DEADTIME_6 (0x6UL << LCD_FCTRL_DEAD_Pos) /*!< 0x00000300USix Phase between different couple of Frame */
+#define LCD_DEADTIME_7 (0x7UL << LCD_FCTRL_DEAD_Pos) /*!< 0x00000380USeven Phase between different couple of Frame */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_PulseOnDuration
+ */
+#define LCD_PULSEONDURATION_0 (0x00000000U) /*!< Pulse ON duration = 0 pulse */
+#define LCD_PULSEONDURATION_1 (0x1U << LCD_FCTRL_PULSEON_Pos) /*!< 0x00000010U Pulse ON duration = 1/CK_PS */
+#define LCD_PULSEONDURATION_2 (0x2U << LCD_FCTRL_PULSEON_Pos) /*!< 0x00000020U Pulse ON duration = 2/CK_PS */
+#define LCD_PULSEONDURATION_3 (0x3U << LCD_FCTRL_PULSEON_Pos) /*!< 0x00000030U Pulse ON duration = 3/CK_PS */
+#define LCD_PULSEONDURATION_4 (0x4U << LCD_FCTRL_PULSEON_Pos) /*!< 0x00000040U Pulse ON duration = 4/CK_PS */
+#define LCD_PULSEONDURATION_5 (0x5U << LCD_FCTRL_PULSEON_Pos) /*!< 0x00000050U Pulse ON duration = 5/CK_PS */
+#define LCD_PULSEONDURATION_6 (0x6U << LCD_FCTRL_PULSEON_Pos) /*!< 0x00000060U Pulse ON duration = 6/CK_PS */
+#define LCD_PULSEONDURATION_7 (0x7U << LCD_FCTRL_PULSEON_Pos) /*!< 0x00000070U Pulse ON duration = 7/CK_PS */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_HighDrive
+ */
+#define LCD_HIGHDRIVE_DISABLE (0x00000000U) /*!< High drive disabled */
+#define LCD_HIGHDRIVE_ENABLE (LCD_FCTRL_HDEN) /*!< High drive enabled */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_HighDrive_Buffer
+ */
+#define LCD_HIGHDRIVEBUFFER_DISABLE (0x00000000U) /*!< High drive buffer disabled */
+#define LCD_HIGHDRIVEBUFFER_ENABLE (LCD_CTRL_BUFEN) /*!< High drive buffer enabled */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_Blink_Mode
+ */
+#define LCD_BLINKMODE_OFF (0x00000000U) /*!< Blink disable */
+#define LCD_BLINKMODE_SEG0_COM0 (0x1UL << LCD_FCTRL_BLINK_Pos) /*!< 0x00010000U Blink enabled on SEG[0], COM[0] (1 pixel) */
+#define LCD_BLINKMODE_SEG0_ALLCOM (0x2UL << LCD_FCTRL_BLINK_Pos) /*!< 0x00020000U Blink enabled on SEG[0], all COM (up to 8 pixels according to the programmed duty) */
+#define LCD_BLINKMODE_ALLSEG_ALLCOM (0x3UL << LCD_FCTRL_BLINK_Pos) /*!< 0x00030000U Blink enabled on all SEG and all COM (all pixels) */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_Blink_Frequency
+ */
+#define LCD_BLINKFREQ_DIV_8 (0x00000000U) /*!< The Blink frequency = fck_div/8 */
+#define LCD_BLINKFREQ_DIV_16 (0x1UL << LCD_FCTRL_BLINKF_Pos) /*!< 0x00002000U The Blink frequency = fck_div/16 */
+#define LCD_BLINKFREQ_DIV_32 (0x2UL << LCD_FCTRL_BLINKF_Pos) /*!< 0x00004000U The Blink frequency = fck_div/32 */
+#define LCD_BLINKFREQ_DIV_64 (0x3UL << LCD_FCTRL_BLINKF_Pos) /*!< 0x00006000U The Blink frequency = fck_div/64 */
+#define LCD_BLINKFREQ_DIV_128 (0x4UL << LCD_FCTRL_BLINKF_Pos) /*!< 0x00008000U The Blink frequency = fck_div/128 */
+#define LCD_BLINKFREQ_DIV_256 (0x5UL << LCD_FCTRL_BLINKF_Pos) /*!< 0x0000A000U The Blink frequency = fck_div/256 */
+#define LCD_BLINKFREQ_DIV_512 (0x6UL << LCD_FCTRL_BLINKF_Pos) /*!< 0x0000C000U The Blink frequency = fck_div/512 */
+#define LCD_BLINKFREQ_DIV_1024 (0x7UL << LCD_FCTRL_BLINKF_Pos) /*!< 0x0000E000U The Blink frequency = fck_div/1024 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_MuxSegment
+ */
+#define LCD_MUXSEGMENT_DISABLE (0x00000000U) /*!< Mux segment disabled */
+#define LCD_MUXSEGMENT_ENABLE (LCD_CTRL_MUXSEG) /*!< Mux segment enabled */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_Interrupt
+ */
+#define LCD_IT_UDD (LCD_FCTRL_UDDIE) /*!< Update display done interrupt */
+#define LCD_IT_SOF (LCD_FCTRL_SOFIE) /*!< Start of frame interrupt */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_Flag
+ */
+#define LCD_FLAG_ENSTS (LCD_STS_ENSTS) /*!< LCD enable flag*/
+#define LCD_FLAG_SOF (LCD_STS_SOF) /*!< LCD start of frame event flag*/
+#define LCD_FLAG_UDR (LCD_STS_UDR) /*!< Update display request Flag*/
+#define LCD_FLAG_UDD (LCD_STS_UDD) /*!< Update display done event flag */
+#define LCD_FLAG_RDY (LCD_STS_RDY) /*!< Ready flag */
+#define LCD_FLAG_FCRSF (LCD_STS_FCRSF) /*!< LCD frame control register synchronization flag */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_Flag_Clear
+ */
+#define LCD_FLAG_SOF_CLEAR (LCD_CLR_SOFCLR) /*!< Clear LCD start of frame event flag*/
+#define LCD_FLAG_UDD_CLEAR (LCD_CLR_UDDCLR) /*!< Clear Update display done event flag */
+/**
+ * @}
+ */
+
+
+/* LCD Exported macros -----------------------------------------------------------*/
+/** @defgroup LCD_Exported_Macros LCD Exported Macros
+ * @{
+ */
+
+/** @brief Enable the LCD peripheral.
+ * @param None
+ * @retval None
+ */
+#define __LCD_ENABLE() SET_BIT(LCD->CTRL, LCD_CTRL_LCDEN)
+
+/** @brief Disable the LCD peripheral.
+ * @param None
+ * @retval None
+ */
+#define __LCD_DISABLE() CLEAR_BIT(LCD->CTRL, LCD_CTRL_LCDEN)
+
+/** @brief Enable the LCD voltage output buffer.
+ * @param None
+ * @retval None
+ */
+#define __LCD_HIGHDRIVE_BUF_ENABLE() SET_BIT(LCD->CTRL, LCD_CTRL_BUFEN)
+
+/** @brief Disable the LCD voltage output buffer.
+ * @param None
+ * @retval None
+ */
+#define __LCD_HIGHDRIVE_BUF_DISABLE() CLEAR_BIT(LCD->CTRL, LCD_CTRL_BUFEN)
+
+/** @brief Enable the LCD mux segment.
+ * @param None
+ * @retval None
+ */
+#define __LCD_MUXSEG_ENABLE() SET_BIT(LCD->CTRL, LCD_CTRL_MUXSEG)
+
+/** @brief Disable the LCD mux segment.
+ * @param None
+ * @retval None
+ */
+#define __LCD_MUXSEG_DISABLE() CLEAR_BIT(LCD->CTRL, LCD_CTRL_MUXSEG)
+
+/** @brief Select internal VLCD as LCD voltage source
+ * @param None
+ * @retval None
+ */
+#define __LCD_SELECT_INTERNAL_VLCD() CLEAR_BIT(LCD->CTRL, LCD_CTRL_VSEL)
+
+/** @brief Select external VLCD as LCD voltage source
+ * @param None
+ * @retval None
+ */
+#define __LCD_SELECT_EXTERNAL_VLCD() SET_BIT(LCD->CTRL, LCD_CTRL_VSEL)
+
+/** @brief Enable the LCD high driver mode.
+ * @param None
+ * @retval None
+ */
+#define __LCD_HIGHDRIVE_ENABLE() SET_BIT(LCD->FCTRL, LCD_FCTRL_HDEN)
+
+/** @brief Disable the LCD high driver mode.
+ * @param None
+ * @retval None
+ */
+#define __LCD_HIGHDRIVE_DISABLE() CLEAR_BIT(LCD->FCTRL, LCD_FCTRL_HDEN)
+
+/** @brief Config the prescaler factor
+ * @param __PRES__ specifies the LCD prescaler
+ * This parameter can be one of the following values:
+ * @arg LCD_PRESCALER_1: CLKPS = LCDCLK
+ * @arg LCD_PRESCALER_2: CLKPS = LCDCLK/2
+ * @arg LCD_PRESCALER_4: CLKPS = LCDCLK/4
+ * @arg LCD_PRESCALER_8: CLKPS = LCDCLK/8
+ * @arg LCD_PRESCALER_16: CLKPS = LCDCLK/16
+ * @arg LCD_PRESCALER_32: CLKPS = LCDCLK/32
+ * @arg LCD_PRESCALER_64: CLKPS = LCDCLK/64
+ * @arg LCD_PRESCALER_128: CLKPS = LCDCLK/128
+ * @arg LCD_PRESCALER_256: CLKPS = LCDCLK/256
+ * @arg LCD_PRESCALER_512: CLKPS = LCDCLK/512
+ * @arg LCD_PRESCALER_1024: CLKPS = LCDCLK/1024
+ * @arg LCD_PRESCALER_2048: CLKPS = LCDCLK/2048
+ * @arg LCD_PRESCALER_4096: CLKPS = LCDCLK/4096
+ * @arg LCD_PRESCALER_8192: CLKPS = LCDCLK/8192
+ * @arg LCD_PRESCALER_16384: CLKPS = LCDCLK/16384
+ * @arg LCD_PRESCALER_32768: CLKPS = LCDCLK/32768
+ * @retval None
+ */
+#define __LCD_PRESCALER_CONFIG(__PRES__) MODIFY_REG(LCD->FCTRL, LCD_FCTRL_PRES,__PRES__)
+
+/** @brief Config the divider factor
+ * @param __DIV__ specifies the LCD divider
+ * This parameter can be one of the following values:
+ * @arg LCD_DIV_16: CLKDIV = CLKPS/(16)
+ * @arg LCD_DIV_17: CLKDIV = CLKPS/(17)
+ * @arg LCD_DIV_18: CLKDIV = CLKPS/(18)
+ * @arg LCD_DIV_19: CLKDIV = CLKPS/(19)
+ * @arg LCD_DIV_20: CLKDIV = CLKPS/(20)
+ * @arg LCD_DIV_21: CLKDIV = CLKPS/(21)
+ * @arg LCD_DIV_22: CLKDIV = CLKPS/(22)
+ * @arg LCD_DIV_23: CLKDIV = CLKPS/(23)
+ * @arg LCD_DIV_24: CLKDIV = CLKPS/(24)
+ * @arg LCD_DIV_25: CLKDIV = CLKPS/(25)
+ * @arg LCD_DIV_26: CLKDIV = CLKPS/(26)
+ * @arg LCD_DIV_27: CLKDIV = CLKPS/(27)
+ * @arg LCD_DIV_28: CLKDIV = CLKPS/(28)
+ * @arg LCD_DIV_29: CLKDIV = CLKPS/(29)
+ * @arg LCD_DIV_30: CLKDIV = CLKPS/(30)
+ * @arg LCD_DIV_31: CLKDIV = CLKPS/(31)
+ * @retval None
+ */
+#define __LCD_DIVIDER_CONFIG(__DIV__) MODIFY_REG(LCD->FCTRL, LCD_FCTRL_DIV,__DIV__)
+
+/** @brief Config the blink mode and frequency
+ * @param __BLINKMODE__ specifies the LCD blink mode
+ * This parameter can be one of the following values:
+ * @arg LCD_DIV_16: CLKDIV = CLKPS/(16)
+ * @arg LCD_BLINKMODE_OFF: Blink disable
+ * @arg LCD_BLINKMODE_SEG0_COM0: Blink enabled on SEG[0], COM[0] (1 pixel)
+ * @arg LCD_BLINKMODE_SEG0_ALLCOM: Blink enabled on SEG[0], all COM (up to 8 pixels according to the programmed duty)
+ * @arg LCD_BLINKMODE_ALLSEG_ALLCOM: Blink enabled on all SEG and all COM (all pixels)
+ * @param __BLINKFREQUENCY__ specifies the LCD blink frequency
+ * This parameter can be one of the following values:
+ * @arg LCD_BLINKFREQ_DIV_8: The Blink frequency = fck_div/8
+ * @arg LCD_BLINKFREQ_DIV_16: The Blink frequency = fck_div/16
+ * @arg LCD_BLINKFREQ_DIV_32: The Blink frequency = fck_div/32
+ * @arg LCD_BLINKFREQ_DIV_64: The Blink frequency = fck_div/64
+ * @arg LCD_BLINKFREQ_DIV_128: The Blink frequency = fck_div/128
+ * @arg LCD_BLINKFREQ_DIV_256: The Blink frequency = fck_div/256
+ * @arg LCD_BLINKFREQ_DIV_512: The Blink frequency = fck_div/512
+ * @arg LCD_BLINKFREQ_DIV_1024: The Blink frequency = fck_div/1024
+ * @retval None
+ */
+#define __LCD_BLINK_CONFIG(__BLINKMODE__,__BLINKFREQUENCY__) MODIFY_REG(LCD->FCTRL, (LCD_FCTRL_BLINK|LCD_FCTRL_BLINKF),(__BLINKMODE__|__BLINKFREQUENCY__))
+
+
+/** @brief Config the contrast
+ * @param __CONTRAST__ specifies the LCD contrast
+ * This parameter can be one of the following values:
+ * @arg LCD_CONTRASTLEVEL_0: Maximum Voltage = 2.60V
+ * @arg LCD_CONTRASTLEVEL_1: Maximum Voltage = 2.73V
+ * @arg LCD_CONTRASTLEVEL_2: Maximum Voltage = 2.86V
+ * @arg LCD_CONTRASTLEVEL_3: Maximum Voltage = 2.99V
+ * @arg LCD_CONTRASTLEVEL_4: Maximum Voltage = 3.12V
+ * @arg LCD_CONTRASTLEVEL_5: Maximum Voltage = 3.26V
+ * @arg LCD_CONTRASTLEVEL_6: Maximum Voltage = 3.40V
+ * @arg LCD_CONTRASTLEVEL_7: Maximum Voltage = 3.55V
+ * @retval None
+ */
+#define __LCD_CONTRAST_CONFIG(__CONTRAST__) MODIFY_REG(LCD->FCTRL, LCD_FCTRL_CONTRAST,__CONTRAST__)
+
+/** @brief Config the dead time
+ * @param __CONTRAST__ specifies the LCD dead time
+ * This parameter can be one of the following values:
+ * @arg LCD_DEADTIME_0: No dead Time
+ * @arg LCD_DEADTIME_1: One Phase between different couple of Frame
+ * @arg LCD_DEADTIME_2: Two Phase between different couple of Frame
+ * @arg LCD_DEADTIME_3: Three Phase between different couple of Frame
+ * @arg LCD_DEADTIME_4: Four Phase between different couple of Frame
+ * @arg LCD_DEADTIME_5: Five Phase between different couple of Frame
+ * @arg LCD_DEADTIME_6: Six Phase between different couple of Frame
+ * @arg LCD_DEADTIME_7: Seven Phase between different couple of Frame
+ * @retval None
+ */
+#define __LCD_DEADTIME_CONFIG(__DEADTIME__) MODIFY_REG(LCD->FCTRL, LCD_FCTRL_DEAD,__DEADTIME__)
+
+/** @brief Config the pulse on duration
+ * @param __PULSEON__ specifies the LCD pulse on duration in terms of
+ * CK_PS (prescaled LCD clock period) pulses.
+ * This parameter can be one of the following values:
+ * @arg LCD_PULSEONDURATION_0: 0 pulse
+ * @arg LCD_PULSEONDURATION_1: Pulse ON duration = 1/CK_PS
+ * @arg LCD_PULSEONDURATION_2: Pulse ON duration = 2/CK_PS
+ * @arg LCD_PULSEONDURATION_3: Pulse ON duration = 3/CK_PS
+ * @arg LCD_PULSEONDURATION_4: Pulse ON duration = 4/CK_PS
+ * @arg LCD_PULSEONDURATION_5: Pulse ON duration = 5/CK_PS
+ * @arg LCD_PULSEONDURATION_6: Pulse ON duration = 6/CK_PS
+ * @arg LCD_PULSEONDURATION_7: Pulse ON duration = 7/CK_PS
+ * @retval None
+ */
+#define __LCD_PULSEONDURATION_CONFIG(__PULSEON__) MODIFY_REG(LCD->FCTRL, LCD_FCTRL_PULSEON,__PULSEON__)
+
+/** @brief Enable the specified LCD interrupt.
+ * @param __INTERRUPT__ specifies the LCD interrupt source to be enabled.
+ * This parameter can be one of the following values:
+ * @arg LCD_IT_SOF: Start of Frame Interrupt
+ * @arg LCD_IT_UDD: Update Display Done Interrupt
+ * @retval None
+ */
+#define __LCD_ENABLE_IT(__INTERRUPT__) SET_BIT(LCD->FCTRL, __INTERRUPT__)
+
+/** @brief Disable the specified LCD interrupt.
+ * @param __INTERRUPT__ specifies the LCD interrupt source to be disabled.
+ * This parameter can be one of the following values:
+ * @arg LCD_IT_SOF: Start of Frame Interrupt
+ * @arg LCD_IT_UDD: Update Display Done Interrupt
+ * @retval None
+ */
+#define __LCD_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(LCD->FCTRL, __INTERRUPT__)
+
+/** @brief Check whether the specified LCD interrupt source is enabled or not.
+ * @param __INTERRUPT__ specifies the LCD interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg LCD_IT_SOF: Start of Frame Interrupt
+ * @arg LCD_IT_UDD: Update Display Done Interrupt.
+ * @retval The state of __INTERRUPT__
+ */
+#define __LCD_GET_IT_SOURCE(__INTERRUPT__) ((LCD->FCTRL) & (__INTERRUPT__))
+
+/** @brief Set LCD UDR flag for update dispaly request
+ * @param None
+ * @retval None
+ */
+#define __LCD_UPDATE_REQUEST() SET_BIT(LCD->STS, LCD_FLAG_UDR)
+
+/** @brief Check whether the specified LCD flag is set or not.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status.
+ * @note The ENS bit is set immediately when the LCDEN bit in the LCD_CR
+ * goes from 0 to 1. On deactivation it reflects the real status of
+ * LCD so it becomes 0 at the end of the last displayed frame.
+ * @arg LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at
+ * the beginning of a new frame, at the same time as the display data is
+ * updated.
+ * @arg LCD_FLAG_UDR: Update Display Request flag.
+ * @arg LCD_FLAG_UDD: Update Display Done flag.
+ * @arg LCD_FLAG_RDY: Step_up converter Ready flag. It indicates the status
+ * of the step-up converter.
+ * @arg LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag.
+ * This flag is set by hardware each time the LCD_FCR register is updated
+ * in the LCDCLK domain.
+ * @retval The new state of __FLAG__
+ */
+#define __LCD_GET_FLAG(__FLAG__) (((LCD->STS) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the specified LCD pending flag.
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg LCD_FLAG_SOF_CLEAR: Start of Frame Interrupt
+ * @arg LCD_FLAG_UDD_CLEAR: Update Display Done Interrupt
+ * @retval None
+ */
+#define __LCD_CLEAR_FLAG(__FLAG__) \
+ do { \
+ SET_BIT((LCD->CLR), (__FLAG__)); \
+ CLEAR_BIT((LCD->CLR), (__FLAG__)); \
+ }while (0)
+
+/** @brief Config LCD to keep display in STOP2 mode.
+ * @param None
+ * @retval None
+ */
+#define __LCD_DISPLAY_IN_STOP2() \
+ do { \
+ SET_BIT(*(__IO uint32_t *)(PWR_BASE+0x08), (0x1UL << 21)); \
+ CLEAR_BIT(*(__IO uint32_t *)(PWR_BASE+0x1c), (0x1UL << 7)); \
+ }while (0)
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup LCD_Private_Macros LCD Private Macros
+ * @{
+ */
+#define IS_LCD_RAM_REGISTER_INDEX(__RAMRegIndex__) ((__RAMRegIndex__)<=LCD_RAM2_COM7)
+
+#define IS_LCD_PRESCALER(_PRESCALER_) \
+ (((_PRESCALER_)==LCD_PRESCALER_1) ||((_PRESCALER_)==LCD_PRESCALER_2) \
+ ||((_PRESCALER_)==LCD_PRESCALER_4) ||((_PRESCALER_)==LCD_PRESCALER_8) \
+ ||((_PRESCALER_)==LCD_PRESCALER_16) ||((_PRESCALER_)==LCD_PRESCALER_32) \
+ ||((_PRESCALER_)==LCD_PRESCALER_64) ||((_PRESCALER_)==LCD_PRESCALER_128) \
+ ||((_PRESCALER_)==LCD_PRESCALER_256) ||((_PRESCALER_)==LCD_PRESCALER_512) \
+ ||((_PRESCALER_)==LCD_PRESCALER_1024)||((_PRESCALER_)==LCD_PRESCALER_2048) \
+ ||((_PRESCALER_)==LCD_PRESCALER_4096)||((_PRESCALER_)==LCD_PRESCALER_8192) \
+ ||((_PRESCALER_)==LCD_PRESCALER_16384)||((_PRESCALER_)==LCD_PRESCALER_32768))
+
+#define IS_LCD_DIVIDER(__DIVIDER__) \
+ (((__DIVIDER__)==LCD_DIV_16)||((__DIVIDER__)==LCD_DIV_17)||((__DIVIDER__)==LCD_DIV_18) \
+ ||((__DIVIDER__)==LCD_DIV_19)||((__DIVIDER__)==LCD_DIV_20)||((__DIVIDER__)==LCD_DIV_21) \
+ ||((__DIVIDER__)==LCD_DIV_22)||((__DIVIDER__)==LCD_DIV_23)||((__DIVIDER__)==LCD_DIV_24) \
+ ||((__DIVIDER__)==LCD_DIV_25)||((__DIVIDER__)==LCD_DIV_26)||((__DIVIDER__)==LCD_DIV_27) \
+ ||((__DIVIDER__)==LCD_DIV_28)||((__DIVIDER__)==LCD_DIV_29)||((__DIVIDER__)==LCD_DIV_30) \
+ ||((__DIVIDER__)==LCD_DIV_31))
+
+#define IS_LCD_DUTY(__DUTY__) \
+ (((__DUTY__)==LCD_DUTY_STATIC)||((__DUTY__)==LCD_DUTY_1_2) \
+ ||((__DUTY__)==LCD_DUTY_1_3) ||((__DUTY__)==LCD_DUTY_1_4) \
+ ||((__DUTY__)==LCD_DUTY_1_8) )
+
+#define IS_LCD_BIAS(__BIAS__) \
+ (((__BIAS__)==LCD_BIAS_1_2)||((__BIAS__)==LCD_BIAS_1_3)||((__BIAS__)==LCD_BIAS_1_4))
+
+#define IS_LCD_VOLTAGESOURCE(__SOURCE__) \
+ (((__SOURCE__)==LCD_VOLTAGESOURCE_INTERNAL)||((__SOURCE__)==LCD_VOLTAGESOURCE_EXTERNAL))
+
+#define IS_LCD_CONTRASTLEVEL(__CONTRAST__) \
+ (((__CONTRAST__)==LCD_CONTRASTLEVEL_0) ||((__CONTRAST__)==LCD_CONTRASTLEVEL_1) \
+ ||((__CONTRAST__)==LCD_CONTRASTLEVEL_2) ||((__CONTRAST__)==LCD_CONTRASTLEVEL_3) \
+ ||((__CONTRAST__)==LCD_CONTRASTLEVEL_4) ||((__CONTRAST__)==LCD_CONTRASTLEVEL_5) \
+ ||((__CONTRAST__)==LCD_CONTRASTLEVEL_6) ||((__CONTRAST__)==LCD_CONTRASTLEVEL_7))
+
+#define IS_LCD_DEADTIME(__DEADTIME__) \
+ (((__DEADTIME__)==LCD_DEADTIME_0) ||((__DEADTIME__)==LCD_DEADTIME_1) \
+ ||((__DEADTIME__)==LCD_DEADTIME_2) ||((__DEADTIME__)==LCD_DEADTIME_3) \
+ ||((__DEADTIME__)==LCD_DEADTIME_4) ||((__DEADTIME__)==LCD_DEADTIME_5) \
+ ||((__DEADTIME__)==LCD_DEADTIME_6) ||((__DEADTIME__)==LCD_DEADTIME_7))
+
+#define IS_LCD_PULSEONDURATION(__PULSE__) \
+ (((__PULSE__)==LCD_PULSEONDURATION_0) ||((__PULSE__)==LCD_PULSEONDURATION_1) \
+ ||((__PULSE__)==LCD_PULSEONDURATION_2) ||((__PULSE__)==LCD_PULSEONDURATION_3) \
+ ||((__PULSE__)==LCD_PULSEONDURATION_4) ||((__PULSE__)==LCD_PULSEONDURATION_5) \
+ ||((__PULSE__)==LCD_PULSEONDURATION_6) ||((__PULSE__)==LCD_PULSEONDURATION_7))
+
+#define IS_LCD_HIGHDRIVE(__HIGHDRIVE__) \
+ ((((__HIGHDRIVE__))==LCD_HIGHDRIVE_DISABLE)||(((__HIGHDRIVE__))==LCD_HIGHDRIVE_ENABLE))
+
+#define IS_LCD_HIGHDRIVEBUFFER(__HIGHDRIVEBUF__) \
+ (((__HIGHDRIVEBUF__)==LCD_HIGHDRIVEBUFFER_DISABLE)||((__HIGHDRIVEBUF__)==LCD_HIGHDRIVEBUFFER_ENABLE))
+
+#define IS_LCD_BLINKMODE(__BLINKMODE__) \
+ (((__BLINKMODE__)==LCD_BLINKMODE_OFF) ||((__BLINKMODE__)==LCD_BLINKMODE_SEG0_COM0) \
+ ||((__BLINKMODE__)==LCD_BLINKMODE_SEG0_ALLCOM) ||((__BLINKMODE__)==LCD_BLINKMODE_ALLSEG_ALLCOM))
+
+#define IS_LCD_BLINKFREQ(__BLINKFREQ__) \
+ (((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_8) ||((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_16) \
+ ||((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_32) ||((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_64) \
+ ||((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_128) ||((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_256) \
+ ||((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_512) ||((__BLINKFREQ__)==LCD_BLINKFREQ_DIV_1024))
+
+#define IS_LCD_MUXSEGMENT(__MUXSEG__) \
+ (((__MUXSEG__)==LCD_MUXSEGMENT_DISABLE)||((__MUXSEG__)==LCD_MUXSEGMENT_ENABLE))
+
+#define IS_LCD_FLAG(__FLAG__) \
+ (((__FLAG__)==LCD_FLAG_ENSTS)||((__FLAG__)==LCD_FLAG_SOF) \
+ ||((__FLAG__)==LCD_FLAG_UDR)||((__FLAG__)==LCD_FLAG_UDD) \
+ ||((__FLAG__)==LCD_FLAG_RDY)||((__FLAG__)==LCD_FLAG_FCRSF))
+
+#define IS_LCD_CLR_FLAG(__CLEARFLAG__) (((__CLEARFLAG__)==LCD_FLAG_SOF_CLEAR)||((__CLEARFLAG__)==LCD_FLAG_UDD_CLEAR)
+
+
+/**
+ * @brief LCD Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t Prescaler; /*!< Configures the LCD Prescaler.
+ This parameter can be one value of @ref LCD_Prescaler */
+ uint32_t Divider; /*!< Configures the LCD Divider.
+ This parameter can be one value of @ref LCD_Divider */
+ uint32_t Duty; /*!< Configures the LCD Duty.
+ This parameter can be one value of @ref LCD_Duty */
+ uint32_t Bias; /*!< Configures the LCD Bias.
+ This parameter can be one value of @ref LCD_Bias */
+ uint32_t VoltageSource; /*!< Selects the LCD Voltage source.
+ This parameter can be one value of @ref LCD_Voltage_source */
+ uint32_t Contrast; /*!< Configures the LCD Contrast.
+ This parameter can be one value of @ref LCD_Contrast */
+ uint32_t DeadTime; /*!< Configures the LCD Dead Time.
+ This parameter can be one value of @ref LCD_DeadTime */
+ uint32_t PulseOnDuration; /*!< Configures the LCD Pulse On Duration.
+ This parameter can be one value of @ref LCD_PulseOnDuration */
+ uint32_t HighDrive; /*!< Enable or disable the permanent high driver.
+ This parameter can be one value of @ref LCD_HighDrive */
+ uint32_t HighDriveBuffer; /*!< Enable or disable the high driver buffer.
+ This parameter can be one value of @ref LCD_HighDrive_Buffer */
+ uint32_t BlinkMode; /*!< Configures the LCD Blink Mode.
+ This parameter can be one value of @ref LCD_Blink_Mode */
+ uint32_t BlinkFreq; /*!< Configures the LCD Blink frequency.
+ This parameter can be one value of @ref LCD_Blink_Frequency */
+ uint32_t MuxSegment; /*!< Enable or disable mux segment.
+ This parameter can be one value of @ref LCD_MuxSegment */
+}LCD_InitType;
+
+
+/** @addtogroup LCD_Exported_Functions
+ * @{
+ */
+LCD_ErrorTypeDef LCD_Init(LCD_InitType *LCD_InitStructure );
+void LCD_DeInit(void);
+
+LCD_ErrorTypeDef LCD_ClockConfig(uint32_t LCD_ClkSource);
+
+void LCD_RamClear(void);
+
+LCD_ErrorTypeDef LCD_UpdateDisplayRequest(void);
+
+LCD_ErrorTypeDef LCD_Write(uint32_t RAMRegisterIndex,uint32_t RAMRegisterMask,uint32_t RAMData);
+
+
+LCD_ErrorTypeDef LCD_SetBit(uint32_t RAMRegisterIndex,uint32_t RAMData);
+
+LCD_ErrorTypeDef LCD_ClearBit(uint32_t RAMRegisterIndex,uint32_t RAMData);
+
+LCD_ErrorTypeDef LCD_WaitForSynchro(void);
+
+/**
+ * @}
+ */
+
+
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* __N32L43X_LCD_H__ */
+ /**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lprcnt.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lprcnt.h
new file mode 100644
index 0000000000..6507c12e66
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lprcnt.h
@@ -0,0 +1,240 @@
+#ifndef __N32L43X_LPRCNT_H__
+#define __N32L43X_LPRCNT_H__
+#include "n32l43x.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* LPRCNT CH_TH mask */
+#define DACREF_default ((uint32_t)0xFFC0FFFF) //比较器内部å‚考电压设置
+
+/* LPRCNT Chanal define */
+typedef enum
+{
+ CHANNEL_0 = 0,
+ CHANNEL_1 = 1,
+ CHANNEL_2 = 2,
+} CHANNELX;
+
+#define CHANNEL_ERROR 0xff
+/* LPRCNT VibrationPowerSelect mask */
+#define POWERSELECT1V5 0 //1.5V
+#define POWERSELECT1V65 1 //1.65V
+#define POWERSELECT1V8 2 //1.8V
+#define POWERSELECT2V0 3 //2.0V
+
+
+/* LPRCNT the alarm sensor scan frequence mask */
+#define FRETIME4 0
+#define FRETIME8 1
+#define FRETIME16 2
+#define FRETIME32 3
+/* LPRCNT MSI division factor mask */
+#define LPRCNT_PRESCALER_DIV1 0x00000000U
+#define LPRCNT_PRESCALER_DIV2 0x00010000U
+#define LPRCNT_PRESCALER_DIV4 0x00020000U
+#define LPRCNT_PRESCALER_DIV8 0x00030000U
+
+#define LPRCNT_ALMFRE_DIV4 0x00000000U
+#define LPRCNT_ALMFRE_DIV8 0x04000000U
+#define LPRCNT_ALMFRE_DIV16 0x08000000U
+#define LPRCNT_ALMFRE_DIV32 0x0c000000U
+/* LPRCNT interrupt mask */
+#define CALIBRATION_INT LPRCNT_CTRL_CALIE
+#define REPORT_INT LPRCNT_CTRL_RPTIE
+#define ALARM_INT LPRCNT_CTRL_ALMIE
+/* LPRCNT interrupt flag mask */
+#define CALIBRATION_INT_FLAG LPRCNT_INTSTS_CALIF
+#define REPORT_INT_FLAG LPRCNT_INTSTS_RPTIF
+#define ALARM_INT_FLAG LPRCNT_INTSTS_ALMIF
+//CMD register
+#define START 1
+#define STOP 2
+#define CLEAR 4
+#define CMD_REG_CLR 0x03
+//work mode
+#define LPRCNT_MODE 1
+#define CAL_MODE 0
+
+
+//Time register
+#define CLEAR_TIME_VALE 0xFF00C0C0
+//TH register
+#define CLEAR_TH_VALE 0xFFFF0000
+
+/**
+ * @brief LPRCNT COMP definition
+ */
+//COMP bits Clear mask
+//#define CMP_HYSEL_CLEAR ((uint32_t)0xFFD8F300)
+//#define CMP_INMSEL_CLEAR ((uint32_t)0xFFD88F00)
+//#define CMP_FILTH_CLEAR ((uint32_t)0xFD68FF00)
+ //Filter threshold control
+#define CMP_FILTH_MODE0 ((uint32_t)0x00000000)
+#define CMP_FILTH_MODE1 ((uint32_t)0x00800000)
+#define CMP_FILTH_MODE2 ((uint32_t)0x01000000)
+
+/**
+ * @brief define LPRCNT some funtion
+ */
+
+//#define STARTSTS(void) ((bool)(LPRCNT->CMD & 0x01) //read start status
+#define LPRCNTModeEnable(mode) do{LPRCNT->CMD &= (~CMD_REG_CLR); LPRCNT->CMD |= (uint32_t)mode;}while (0)//set LPRCNT module CMD .
+#define SetLPRCNTWorkMode(mode) do{LPRCNT->CTRL &= (~LPRCNT_CTRL_RCNTM); LPRCNT->CTRL |= (uint32_t)(mode << 24);}while (0)//calibration mode or LPRCNT mode
+/**
+ * @brief define Auto detection
+ */
+#define AUTODETPERIOD4 0 //count overflow 4*pulse period
+#define AUTODETPERIOD8 1 //count overflow 8*pulse period
+/**************************************************************************************************************************************/
+/* function structure variable */
+/**************************************************************************************************************************************/
+typedef enum
+{
+ HYST_NO = (0x0L << 10),
+ HYST_LOW = (0x1L << 10),
+ HYST_MID = (0x2L << 10),
+ HYST_HIGH = (0x3L << 10),
+} LPRCNT_COMP_CTRL_HYST;
+
+typedef enum {
+ //comp1 inm sel
+ INMSEL_NC = ((uint32_t)0x00000000),
+ INMSEL_DAC1 = ((uint32_t)0x00001000),
+ INMSEL_PA0 = ((uint32_t)0x00002000),
+ INMSEL_PA5 = ((uint32_t)0x00003000),
+ INMSEL_PB5 = ((uint32_t)0x00004000),
+ INMSEL_PD4 = ((uint32_t)0x00005000),
+ INMSEL_VREF_VC1 = ((uint32_t)0x00006000),
+ INMSEL_VREF_VC2 = ((uint32_t)0x00007000),
+}LPRCNT_COMP_CTRL_INMSEL;
+/**
+ * @brief LPRCNT Init structure definition
+ */
+typedef struct
+{
+ uint8_t vibrationtime;
+ uint8_t dischargetime;
+ uint8_t chargetime;
+} LPRCNT_InitTime;
+typedef struct
+{
+ uint8_t dacreference;
+ uint8_t undampedTh;
+ uint8_t dampedTh;
+} LPRCNT_InitThreshold;
+typedef struct
+{
+ uint16_t low_speed;
+ uint8_t hight_speed;
+ uint8_t swtich_time;
+} LPRCNT_Initfrequence;
+typedef struct
+{
+ uint8_t Channel[3];
+ uint8_t ChargeVol;
+ uint8_t WorkMode;
+ LPRCNT_InitTime ChTime[3];
+ LPRCNT_InitThreshold ChTH[3];
+ LPRCNT_Initfrequence NormalFreq;
+ uint8_t AlarmFreq;
+ uint32_t PrescaleDiv;
+ uint16_t Circle;
+ FunctionalState AutoDetEn;
+ bool AutoWaitPer;
+ FunctionalState IntEn;
+ uint32_t Int;
+
+} LPRCNT_InitType;
+
+/**
+ * @brief COMP Init structure definition
+ */
+
+typedef struct
+{
+ bool LowPoweMode; //low power mode
+ LPRCNT_COMP_CTRL_HYST Hyst; //COMP hysteresis
+ LPRCNT_COMP_CTRL_INMSEL InmSel; //COMP input minus selection
+ uint16_t ClkPsc;
+} LPRCNT_COMP_InitType;
+
+
+/**************************************************************************************************************************************/
+/* specail registers */
+/**************************************************************************************************************************************/
+//LPRCNT module setup time
+#define DacSetupTime(time) do{LPRCNT->CAL2 &= (~LPRCNT_CAL2_DACSET); LPRCNT->CAL2 |= (uint32_t)(time);}while (0)//time < 64 ,6bit
+#define CompSetupTime(time) do{LPRCNT->CAL2 &= (~LPRCNT_CAL2_CMPSET); LPRCNT->CAL2 |= (uint32_t)(time << 8);}while (0)//time < 64 ,6bit
+
+#define DacSetupTimeConfig() DacSetupTime(20)
+#define CompSetupTimeConfig() CompSetupTime(31)
+
+#define RcntAdjustCircleNum(time) do{LPRCNT->CAL2 &= (~LPRCNT_CAL2_RCNTADJ); LPRCNT->CAL2 |= (uint32_t)(time << 20);}while (0)//time < 16 ,4bit
+#define ChargeAndDischargeGap(time) do{LPRCNT->CAL2 &= (~LPRCNT_CAL2_GAP); LPRCNT->CAL2 |= (uint32_t)(time << 16);}while (0)//time < 16 ,4bit
+//Analog filter
+#define POPH 0
+#define NEPH 1
+#define ANGFILT_TH (__IO unsigned*)(0x40001800 + 0x1c)
+#define ANGFILT_CTRL (__IO unsigned*)(0x40001800 + 0x28)
+#define CLERR_ANGTH 0xffffff87 //bit3~6
+#define CLERR_ANGPHA 0xffffefff //bit12
+#define SetAnalogFilterTh(vale) do{(*ANGFILT_TH) &= CLERR_ANGTH;(*ANGFILT_TH) |= (uint32_t)(vale <<3);}while (0) //vale only equal to 0,1,3,8,12
+#define CompAnalogFilterPhase(dir) do{(*ANGFILT_CTRL) &= CLERR_ANGPHA;(*ANGFILT_CTRL) |= (uint32_t)(dir << 12);}while (0)//Analog filtering phase selection
+//auto control set funtion
+#define PwrAutoChargeEnable(cmd) do{LPRCNT->CAL3 & = (~LPRCNT_CAL3_PWR_DUR_EN);(LPRCNT->CAL3)|= (uint32_t)(cmd <<7);}while (0)//0 :enable 1:disable
+
+/**************************************************************************************************************************************/
+/* function declaration */
+/**************************************************************************************************************************************/
+void ClearITPendingBit(uint32_t intflag);
+void COMP_1_2_IRQHandler(void);
+void LPRCNT_IE(uint32_t MODE_IE ,FunctionalState NewState);
+void CfgChannelTime(uint8_t Ch,uint8_t VibrationTime ,uint8_t DischargeTime,uint8_t ChargeTime);
+void CfgChannelDacRefVol(uint8_t Ch,uint8_t DacRef);
+void CfgChannelThr(uint8_t Ch, uint8_t UndampedTh, uint8_t DampedTh);
+void SetMsiClkPrescale(uint32_t Div);
+void SetAutoReportCircle(uint16_t Circle);
+void SetScanAverageValue(uint8_t N);
+void SetVibrationPower(uint8_t Value);
+void SetNormalSensorScanfrequence(uint16_t low_speed,uint8_t hight_speed,uint8_t swtich_time);
+void SetAlarmSensorScanfrequence(uint8_t Period);
+void SetAutoDetect(FunctionalState NewState );
+void SetAutoDetectEnale(FunctionalState NewState );
+void SetAutoDetectPeriod(bool per);
+uint8_t GetSampleMode(void);
+uint8_t GetChannelSensorWavesNum(uint8_t Ch);
+uint8_t GetChannelSensorState(uint8_t Ch);
+uint16_t GetRotationCircle(void);
+uint16_t GetSetRcnt(void);
+void ClrRcntCircle(void);
+void SetPwrAutoCharge(bool En);
+bool ReadStartState(void);
+void LPRCNTInit(LPRCNT_InitType* LPRCNT_InitStruct);
+void DAC_CMP_ALWSONCmd(FunctionalState NewState);
+
+void LPRCNT_CompInit(LPRCNT_COMP_InitType* COMP_InitStruct);
+void CompDigitalFilterCfg(bool cmd, uint32_t filterTh);
+void CompAnalogFilterEn(bool cmd);
+void LPRCNTAnalogFilterConfig(void);
+//Interruprt mask
+void LPRCNT_ClrIntBit(uint32_t intflag);
+
+INTStatus LPRCNT_GetIntSts(uint32_t Int);
+void LPRCNT_IntEn(uint32_t Mode ,FunctionalState NewState);
+void CompDigitalFilterPhase(bool dir);
+
+//for prinft some set values
+uint16_t GetNormalSensorLowSpeed(void);
+uint8_t GetNormalSensorHightSpeed(void);
+uint8_t GetNormalSensorSwtichTime(void);
+uint8_t GetDacRefVol(uint8_t Ch);
+uint8_t GetUndampedTh(uint8_t Ch);
+uint8_t GetDampedTh(uint8_t Ch);
+uint8_t GetVibrationTime(uint8_t Ch);
+uint8_t GetDischargeTime(uint8_t Ch);
+uint8_t GetChargeTime(uint8_t Ch);
+#endif /* __LPRCNT_H__ */
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lptim.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lptim.h
new file mode 100644
index 0000000000..a753751a6d
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lptim.h
@@ -0,0 +1,427 @@
+/** ----------------------------------------------------------------------------
+ * Nationz Technology Software Support - NATIONZ -
+ * -----------------------------------------------------------------------------
+ * Copyright (c) 2022, Nationz Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaiimer below.
+ *
+ * - Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the disclaimer below in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * Nationz's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * -----------------------------------------------------------------------------
+ */
+/** ****************************************************************************
+ * @copyright Nationz Co.,Ltd
+ * Copyright (c) 2019 All Rights Reserved
+ *******************************************************************************
+ * @file n32l43x_lptim.h
+ * @author
+ * @date
+ * @version v1.2.0
+ * @brief
+ ******************************************************************************/
+#ifndef __N32L43X_LPTIM_H
+#define __N32L43X_LPTIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "n32l43x.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup LPTIM
+ * @{
+ */
+
+//#if defined (LPTIM)
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup LPTIM_ES_INIT LPTIM Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief LPTIM Init structure definition
+ */
+typedef struct
+{
+ uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
+ This parameter can be a value of @ref LPTIM_EC_CLK_SOURCE.
+
+ This feature can be modified afterwards using unitary function @ref LPTIM_SetClockSource().*/
+
+ uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
+ This parameter can be a value of @ref LPTIM_EC_PRESCALER.
+
+ This feature can be modified afterwards using using unitary function @ref LPTIM_SetPrescaler().*/
+
+ uint32_t Waveform; /*!< Specifies the waveform shape.
+ This parameter can be a value of @ref LPTIM_EC_OUTPUT_WAVEFORM.
+
+ This feature can be modified afterwards using unitary function @ref LPTIM_ConfigOutput().*/
+
+ uint32_t Polarity; /*!< Specifies waveform polarity.
+ This parameter can be a value of @ref LPTIM_EC_OUTPUT_POLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LPTIM_ConfigOutput().*/
+} LPTIM_InitType;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
+ * @{
+ */
+
+/** @defgroup LPTIM_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LPTIM_ReadReg function
+ * @{
+ */
+#define LPTIM_INTSTS_CMPM_FLAG LPTIM_INTSTS_CMPM /*!< Compare match */
+#define LPTIM_INTSTS_ARRM_FLAG LPTIM_INTSTS_ARRM /*!< Autoreload match */
+#define LPTIM_INTSTS_EXTRIG_FLAG LPTIM_INTSTS_EXTRIG /*!< External trigger edge event */
+#define LPTIM_INTSTS_CMPUPD_FLAG LPTIM_INTSTS_CMPUPD /*!< Compare register update OK */
+#define LPTIM_INTSTS_ARRUPD_FLAG LPTIM_INTSTS_ARRUPD /*!< Autoreload register update OK */
+#define LPTIM_INTSTS_UP_FLAG LPTIM_INTSTS_UP /*!< Counter direction change down to up */
+#define LPTIM_INTSTS_DOWN_FLAG LPTIM_INTSTS_DOWN /*!< Counter direction change up to down */
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_EC_IT IT Defines
+ * @brief IT defines which can be used with LPTIM_ReadReg and LPTIM_WriteReg functions
+ * @{
+ */
+#define LPTIM_INTEN_CMPMIE_ENABLE LPTIM_INTEN_CMPMIE /*!< Compare match Interrupt Enable */
+#define LPTIM_INTEN_ARRMIE_ENABLE LPTIM_INTEN_ARRMIE /*!< Autoreload match Interrupt Enable */
+#define LPTIM_INTEN_EXTRIGIE_ENABLE LPTIM_INTEN_EXTRIGIE /*!< External trigger valid edge Interrupt Enable */
+#define LPTIM_INTEN_CMPUPDIE_ENABLE LPTIM_INTEN_CMPUPDIE /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_INTEN_ARRUPDIE_ENABLE LPTIM_INTEN_ARRUPDIE /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_INTEN_UPIE_ENABLE LPTIM_INTEN_UPIE /*!< Direction change to UP Interrupt Enable */
+#define LPTIM_INTEN_DOWNIE_ENABLE LPTIM_INTEN_DOWNIE /*!< Direction change to down Interrupt Enable */
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_EC_OPERATING_MODE Operating Mode
+ * @{
+ */
+#define LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CTRL_TSTCM /*!(__REG__), (__VALUE__))
+
+/**
+ * @brief Read a value in LPTIM register
+ * @param __INSTANCE__ LPTIM Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->(__REG__))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
+ * @{
+ */
+
+/** @defgroup LPTIM_EF_Init Initialisation and deinitialisation functions
+ * @{
+ */
+
+void LPTIM_DeInit(LPTIM_Module *LPTIMx);
+void LPTIM_StructInit(LPTIM_InitType *LPTIM_InitStruct);
+ErrorStatus LPTIM_Init(LPTIM_Module *LPTIMx, LPTIM_InitType *LPTIM_InitStruct);
+void LPTIM_Disable(LPTIM_Module *LPTIMx);
+
+
+
+void LPTIM_Enable(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabled(LPTIM_Module *LPTIMx);
+void LPTIM_StartCounter(LPTIM_Module *LPTIMx, uint32_t OperatingMode);
+void LPTIM_SetUpdateMode(LPTIM_Module *LPTIMx, uint32_t UpdateMode);
+uint32_t LPTIM_GetUpdateMode(LPTIM_Module *LPTIMx);
+void LPTIM_SetAutoReload(LPTIM_Module *LPTIMx, uint32_t AutoReload);
+uint32_t LPTIM_GetAutoReload(LPTIM_Module *LPTIMx);
+void LPTIM_SetCompare(LPTIM_Module *LPTIMx, uint32_t CompareValue);
+uint32_t LPTIM_GetCompare(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_GetCounter(LPTIM_Module *LPTIMx);
+void LPTIM_SetCounterMode(LPTIM_Module *LPTIMx, uint32_t CounterMode);
+uint32_t LPTIM_GetCounterMode(LPTIM_Module *LPTIMx);
+void LPTIM_ConfigOutput(LPTIM_Module *LPTIMx, uint32_t Waveform, uint32_t Polarity);
+void LPTIM_SetWaveform(LPTIM_Module *LPTIMx, uint32_t Waveform);
+uint32_t LPTIM_GetWaveform(LPTIM_Module *LPTIMx);
+void LPTIM_SetPolarity(LPTIM_Module *LPTIMx, uint32_t Polarity);
+uint32_t LPTIM_GetPolarity(LPTIM_Module *LPTIMx);
+void LPTIM_SetPrescaler(LPTIM_Module *LPTIMx, uint32_t Prescaler);
+uint32_t LPTIM_GetPrescaler(LPTIM_Module *LPTIMx);
+void LPTIM_EnableTimeout(LPTIM_Module *LPTIMx);
+void LPTIM_DisableTimeout(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledTimeout(LPTIM_Module *LPTIMx);
+void LPTIM_TrigSw(LPTIM_Module *LPTIMx);
+void LPTIM_ConfigTrigger(LPTIM_Module *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity);
+uint32_t LPTIM_GetTriggerSource(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_GetTriggerFilter(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_GetTriggerPolarity(LPTIM_Module *LPTIMx);
+void LPTIM_SetClockSource(LPTIM_Module *LPTIMx, uint32_t ClockSource);
+uint32_t LPTIM_GetClockSource(LPTIM_Module *LPTIMx);
+void LPTIM_ConfigClock(LPTIM_Module *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity);
+uint32_t LPTIM_GetClockPolarity(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_GetClockFilter(LPTIM_Module *LPTIMx);
+void LPTIM_SetEncoderMode(LPTIM_Module *LPTIMx, uint32_t EncoderMode);
+uint32_t LPTIM_GetEncoderMode(LPTIM_Module *LPTIMx);
+void LPTIM_EnableEncoderMode(LPTIM_Module *LPTIMx);
+void LPTIM_DisableEncoderMode(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledEncoderMode(LPTIM_Module *LPTIMx);
+void LPTIM_ClearFLAG_CMPM(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsActiveFlag_CMPM(LPTIM_Module *LPTIMx);
+void LPTIM_ClearFLAG_ARRM(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsActiveFlag_ARRM(LPTIM_Module *LPTIMx);
+void LPTIM_ClearFlag_EXTTRIG(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsActiveFlag_EXTTRIG(LPTIM_Module *LPTIMx);
+void LPTIM_ClearFlag_CMPOK(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsActiveFlag_CMPOK(LPTIM_Module *LPTIMx);
+void LPTIM_ClearFlag_ARROK(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsActiveFlag_ARROK(LPTIM_Module *LPTIMx);
+void LPTIM_ClearFlag_UP(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsActiveFlag_UP(LPTIM_Module *LPTIMx);
+void LPTIM_ClearFlag_DOWN(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsActiveFlag_DOWN(LPTIM_Module *LPTIMx);
+void LPTIM_EnableIT_CMPM(LPTIM_Module *LPTIMx);
+void LPTIM_DisableIT_CMPM(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledIT_CMPM(LPTIM_Module *LPTIMx);
+void LPTIM_EnableIT_ARRM(LPTIM_Module *LPTIMx);
+void LPTIM_DisableIT_ARRM(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledIT_ARRM(LPTIM_Module *LPTIMx);
+void LPTIM_EnableIT_EXTTRIG(LPTIM_Module *LPTIMx);
+void LPTIM_DisableIT_EXTTRIG(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledIT_EXTTRIG(LPTIM_Module *LPTIMx);
+void LPTIM_EnableIT_CMPOK(LPTIM_Module *LPTIMx);
+void LPTIM_DisableIT_CMPOK(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledIT_CMPOK(LPTIM_Module *LPTIMx);
+void LPTIM_EnableIT_ARROK(LPTIM_Module *LPTIMx);
+void LPTIM_DisableIT_ARROK(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledIT_ARROK(LPTIM_Module *LPTIMx);
+void LPTIM_EnableIT_UP(LPTIM_Module *LPTIMx);
+void LPTIM_DisableIT_UP(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledIT_UP(LPTIM_Module *LPTIMx);
+void LPTIM_EnableIT_DOWN(LPTIM_Module *LPTIMx);
+void LPTIM_DisableIT_DOWN(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledIT_DOWN(LPTIM_Module *LPTIMx);
+void LPTIM_EnableNoEncoderMode(LPTIM_Module *LPTIMx);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+//#endif /* LPTIM */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32L43X_LPTIM_H */
+
+/******************* (C) COPYRIGHT 2019 NATIONZ *****END OF FILE****/
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lpuart.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lpuart.h
new file mode 100644
index 0000000000..48091b85fa
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lpuart.h
@@ -0,0 +1,280 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_lpuart.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L43X_LPUART_H__
+#define __N32L43X_LPUART_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l43x.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup LPUART
+ * @{
+ */
+
+/** @addtogroup LPUART_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief LPUART Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the LPUART communication baud rate.
+ The baud rate is computed using the following formula:
+ - IntegerDivider = ((CLK) / (LPUART_InitStruct->BaudRate)))
+ - FractionalDivider */
+
+ uint16_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (only support
+ 8 data bits). */
+
+ uint16_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref Mode */
+
+ uint16_t RtsThreshold; /* Specifies RTS Threshold.
+ This parameter can be a value of @ref RtsThreshold */
+
+ uint16_t HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
+ or disabled.
+ This parameter can be a value of @ref LPUART_Hardware_Flow_Control */
+} LPUART_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup Parity
+ * @{
+ */
+
+#define LPUART_PE_NO ((uint16_t)0x0008)
+#define LPUART_PE_EVEN ((uint16_t)0x0000)
+#define LPUART_PE_ODD ((uint16_t)0x0001)
+#define IS_LPUART_PARITY(PARITY) (((PARITY) == LPUART_PE_NO) || ((PARITY) == LPUART_PE_EVEN) || ((PARITY) == LPUART_PE_ODD))
+/**
+ * @}
+ */
+
+/** @addtogroup Mode
+ * @{
+ */
+
+#define LPUART_MODE_RX ((uint16_t)0x0000)
+#define LPUART_MODE_TX ((uint16_t)0x0002)
+#define IS_LPUART_MODE(MODE) (((MODE) == LPUART_MODE_RX) || ((MODE) == LPUART_MODE_TX))
+/**
+ * @}
+ */
+
+/** @addtogroup RtsThreshold
+ * @{
+ */
+
+#define LPUART_RTSTH_FIFOHF ((uint16_t)0x0000)
+#define LPUART_RTSTH_FIFO3QF ((uint16_t)0x0100)
+#define LPUART_RTSTH_FIFOFU ((uint16_t)0x0200)
+#define IS_LPUART_RTSTHRESHOLD(RTSTHRESHOLD) \
+ (((RTSTHRESHOLD) == LPUART_RTSTH_FIFOHF) || ((RTSTHRESHOLD) == LPUART_RTSTH_FIFO3QF) || ((RTSTHRESHOLD) == LPUART_RTSTH_FIFOFU))
+/**
+ * @}
+ */
+
+/** @addtogroup Hardware_Flow_Control
+ * @{
+ */
+#define LPUART_HFCTRL_NONE ((uint16_t)0x0000)
+#define LPUART_HFCTRL_CTS ((uint16_t)0x0400)
+#define LPUART_HFCTRL_RTS ((uint16_t)0x0800)
+#define LPUART_HFCTRL_RTS_CTS ((uint16_t)0x0C00)
+#define IS_LPUART_HARDWARE_FLOW_CONTROL(CONTROL) \
+ (((CONTROL) == LPUART_HFCTRL_NONE) || ((CONTROL) == LPUART_HFCTRL_RTS) || ((CONTROL) == LPUART_HFCTRL_CTS) \
+ || ((CONTROL) == LPUART_HFCTRL_RTS_CTS))
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Interrupt_definition
+ * @{
+ */
+
+#define LPUART_INT_PE ((uint16_t)0x0001)
+#define LPUART_INT_TXC ((uint16_t)0x0102)
+#define LPUART_INT_FIFO_OV ((uint16_t)0x0204)
+#define LPUART_INT_FIFO_FU ((uint16_t)0x0308)
+#define LPUART_INT_FIFO_HF ((uint16_t)0x0410)
+#define LPUART_INT_FIFO_NE ((uint16_t)0x0520)
+#define LPUART_INT_WUF ((uint16_t)0x0640)
+#define IS_LPUART_CFG_INT(IT) \
+ (((IT) == LPUART_INT_PE) || ((IT) == LPUART_INT_TXC) || ((IT) == LPUART_INT_FIFO_OV) || ((IT) == LPUART_INT_FIFO_FU) \
+ || ((IT) == LPUART_INT_FIFO_HF) || ((IT) == LPUART_INT_FIFO_NE) || ((IT) == LPUART_INT_WUF))
+#define IS_LPUART_GET_INT(IT) \
+ (((IT) == LPUART_INT_PE) || ((IT) == LPUART_INT_TXC) || ((IT) == LPUART_INT_FIFO_OV) || ((IT) == LPUART_INT_FIFO_FU) \
+ || ((IT) == LPUART_INT_FIFO_HF) || ((IT) == LPUART_INT_FIFO_NE) || ((IT) == LPUART_INT_WUF))
+#define IS_LPUART_CLR_INT(IT) \
+ (((IT) == LPUART_INT_PE) || ((IT) == LPUART_INT_TXC) || ((IT) == LPUART_INT_FIFO_OV) || ((IT) == LPUART_INT_FIFO_FU) \
+ || ((IT) == LPUART_INT_FIFO_HF) || ((IT) == LPUART_INT_FIFO_NE) || ((IT) == LPUART_INT_WUF))
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_DMA_Requests
+ * @{
+ */
+
+#define LPUART_DMAREQ_TX ((uint16_t)0x0020)
+#define LPUART_DMAREQ_RX ((uint16_t)0x0040)
+#define IS_LPUART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF9F) == (uint16_t)0x00) && ((DMAREQ) != (uint16_t)0x00))
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_WakeUp_methods
+ * @{
+ */
+
+#define LPUART_WUSTP_STARTBIT ((uint16_t)0x0000)
+#define LPUART_WUSTP_RXNE ((uint16_t)0x1000)
+#define LPUART_WUSTP_BYTE ((uint16_t)0x2000)
+#define LPUART_WUSTP_FRAME ((uint16_t)0x3000)
+#define IS_LPUART_WAKEUP(WAKEUP) \
+ (((WAKEUP) == LPUART_WUSTP_STARTBIT) || ((WAKEUP) == LPUART_WUSTP_RXNE) || ((WAKEUP) == LPUART_WUSTP_BYTE) || ((WAKEUP) == LPUART_WUSTP_FRAME))
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Sampling_methods
+ * @{
+ */
+
+#define LPUART_SMPCNT_3B ((uint16_t)0x0000)
+#define LPUART_SMPCNT_1B ((uint16_t)0x4000)
+#define IS_LPUART_SAMPLING(SAMPLING) (((SAMPLING) == LPUART_SMPCNT_1B) || ((SAMPLING) == LPUART_SMPCNT_3B))
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Flags
+ * @{
+ */
+
+#define LPUART_FLAG_PEF ((uint16_t)0x0001)
+#define LPUART_FLAG_TXC ((uint16_t)0x0002)
+#define LPUART_FLAG_FIFO_OV ((uint16_t)0x0004)
+#define LPUART_FLAG_FIFO_FU ((uint16_t)0x0008)
+#define LPUART_FLAG_FIFO_HF ((uint16_t)0x0010)
+#define LPUART_FLAG_FIFO_NE ((uint16_t)0x0020)
+#define LPUART_FLAG_CTS ((uint16_t)0x0040)
+#define LPUART_FLAG_WUF ((uint16_t)0x0080)
+#define LPUART_FLAG_NF ((uint16_t)0x0100)
+#define IS_LPUART_FLAG(FLAG) \
+ (((FLAG) == LPUART_FLAG_PEF) || ((FLAG) == LPUART_FLAG_TXC) || ((FLAG) == LPUART_FLAG_FIFO_OV) \
+ || ((FLAG) == LPUART_FLAG_FIFO_FU) || ((FLAG) == LPUART_FLAG_FIFO_HF) || ((FLAG) == LPUART_FLAG_FIFO_NE) \
+ || ((FLAG) == LPUART_FLAG_CTS) || ((FLAG) == LPUART_FLAG_WUF) || ((FLAG) == LPUART_FLAG_NF))
+
+#define IS_LPUART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFE40) == 0x00) && ((FLAG) != (uint16_t)0x00))
+
+#define IS_LPUART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x010000))
+
+#define IS_LPUART_DATA(DATA) ((DATA) <= 0xFF)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Exported_Functions
+ * @{
+ */
+
+void LPUART_DeInit(void);
+void LPUART_Init(LPUART_InitType* LPUART_InitStruct);
+void LPUART_StructInit(LPUART_InitType* LPUART_InitStruct);
+void LPUART_FlushRxFifo(void);
+void LPUART_ConfigInt(uint16_t LPUART_INT, FunctionalState Cmd);
+void LPUART_EnableDMA(uint16_t LPUART_DMAReq, FunctionalState Cmd);
+void LPUART_ConfigWakeUpMethod(uint16_t LPUART_WakeUpMethod);
+void LPUART_EnableWakeUpStop(FunctionalState Cmd);
+void LPUART_ConfigSamplingMethod(uint16_t LPUART_SamplingMethod);
+void LPUART_EnableLoopBack(FunctionalState Cmd);
+void LPUART_SendData(uint8_t Data);
+uint8_t LPUART_ReceiveData(void);
+void LPUART_ConfigWakeUpData(uint32_t LPUART_WakeUpData);
+FlagStatus LPUART_GetFlagStatus(uint16_t LPUART_FLAG);
+void LPUART_ClrFlag(uint16_t LPUART_FLAG);
+INTStatus LPUART_GetIntStatus(uint16_t LPUART_INT);
+void LPUART_ClrIntPendingBit(uint16_t LPART_INT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32L43X_LPUART_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_opamp.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_opamp.h
new file mode 100644
index 0000000000..21204224f4
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_opamp.h
@@ -0,0 +1,209 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_opamp.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L43X_OPAMPMP_H__
+#define __N32L43X_OPAMPMP_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l43x.h"
+#include
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup OPAMP
+ * @{
+ */
+
+/** @addtogroup OPAMP_Exported_Constants
+ * @{
+ */
+typedef enum
+{
+ OPAMP1 = 0,
+ OPAMP2 = 4,
+} OPAMPX;
+
+// OPAMP_CS
+typedef enum
+{
+ OPAMP2_CS_TIMSRCSEL_TIM1CC6 = (0x0L << 24),
+ OPAMP2_CS_TIMSRCSEL_TIM8CC6 = (0x1L << 24),
+}OPAMP2_CS_TIMSRCSEL;
+typedef enum
+{
+ OPAMP1_CS_VPSSEL_PA1 = (0x00L << 19),
+ OPAMP1_CS_VPSSEL_PA5 = (0x01L << 19),
+ OPAMP1_CS_VPSSEL_PA4 = (0x02L << 19),
+ OPAMP1_CS_VPSSEL_PA7 = (0x03L << 19),
+ OPAMP1_CS_VPSSEL_NC = (0x04L << 19),
+
+ OPAMP2_CS_VPSSEL_PA7 = (0x00L << 19),
+ OPAMP2_CS_VPSSEL_PA4 = (0x01L << 19),
+ OPAMP2_CS_VPSSEL_PB14 = (0x02L << 19),
+ OPAMP2_CS_VPSSEL_PD13 = (0x03L << 19),
+ OPAMP2_CS_VPSSEL_NC = (0x04L << 19),
+} OPAMP_CS_VPSSEL;
+typedef enum
+{
+ OPAMP1_CS_VMSSEL_PA3 = (0x00L << 17),
+ OPAMP1_CS_VMSSEL_PC5 = (0x01L << 17),
+ OPAMP1_CS_VMSSEL_NC = (0x02L << 17),
+ OPAMP1_CS_VMSSEL_FLOAT = (0x03L << 17),
+
+ OPAMP2_CS_VMSSEL_PC5 = (0x00L << 17),
+ OPAMP2_CS_VMSSEL_PB0 = (0x01L << 17),
+ OPAMP2_CS_VMSSEL_PA5 = (0x02L << 17),
+ OPAMP2_CS_VMSSEL_FLOAT = (0x03L << 17),
+} OPAMP_CS_VMSSEL;
+
+typedef enum
+{
+ OPAMP1_CS_VPSEL_PA1 = (0x00L << 8),
+ OPAMP1_CS_VPSEL_PA5 = (0x01L << 8),
+ OPAMP1_CS_VPSEL_PA4 = (0x02L << 8),
+ OPAMP1_CS_VPSEL_PA7 = (0x03L << 8),
+ OPAMP1_CS_VPSEL_NC = (0x04L << 8),
+
+ OPAMP2_CS_VPSEL_PA7 = (0x00L << 8),
+ OPAMP2_CS_VPSEL_PA4 = (0x01L << 8),
+ OPAMP2_CS_VPSEL_PB14 = (0x02L << 8),
+ OPAMP2_CS_VPSEL_PD13 = (0x03L << 8),
+ OPAMP2_CS_VPSEL_NC = (0x04L << 8),
+} OPAMP_CS_VPSEL;
+typedef enum
+{
+ OPAMP1_CS_VMSEL_PA3 = (0x00L << 6),
+ OPAMP1_CS_VMSEL_PC5 = (0x01L << 6),
+ OPAMPx_CS_VMSEL_NC = (0x02L << 6),
+ OPAMPx_CS_VMSEL_FLOAT = (0x03L << 6),
+
+ OPAMP2_CS_VMSEL_PC5 = (0x00L << 6),
+ OPAMP2_CS_VMSEL_PB0 = (0x01L << 6),
+ OPAMP2_CS_VMSEL_PA5 = (0x02L << 6),
+ OPAMP2_CS_VMSEL_FLOAT = (0x03L << 6),
+} OPAMP_CS_VMSEL;
+typedef enum
+{
+ OPAMP_CS_PGA_GAIN_2 = (0x00 << 3),
+ OPAMP_CS_PGA_GAIN_4 = (0x01 << 3),
+ OPAMP_CS_PGA_GAIN_8 = (0x02 << 3),
+ OPAMP_CS_PGA_GAIN_16 = (0x03 << 3),
+ OPAMP_CS_PGA_GAIN_32 = (0x04 << 3),
+} OPAMP_CS_PGA_GAIN;
+typedef enum
+{
+ OPAMP_CS_EXT_OPAMP = (0x00 << 1),
+ OPAMP_CS_PGA_EN = (0x02 << 1),
+ OPAMP_CS_FOLLOW = (0x03 << 1),
+} OPAMP_CS_MOD;
+
+// bit mask
+#define OPAMP_CS_EN_MASK (0x01L << 0)
+#define OPAMP_CS_MOD_MASK (0x03L << 1)
+#define OPAMP_CS_PGA_GAIN_MASK (0x07L << 3)
+#define OPAMP_CS_VMSEL_MASK (0x03L << 6)
+#define OPAMP_CS_VPSEL_MASK (0x07L << 8)
+#define OPAMP_CS_CALON_MASK (0x01L << 11)
+#define OPAMP_CS_TSTREF_MASK (0x01L << 13)
+#define OPAMP_CS_CALOUT_MASK (0x01L << 14)
+#define OPAMP_CS_RANGE_MASK (0x01L << 15)
+#define OPAMP_CS_TCMEN_MASK (0x01L << 16)
+#define OPAMP_CS_VMSEL_SECOND_MASK (0x03L << 17)
+#define OPAMP_CS_VPSEL_SECOND_MASK (0x07L << 19)
+#define OPAMP_CS_OPAMP2_TIMSRCSEL (0x01L << 24)
+/** @addtogroup OPAMP_LOCK
+ * @{
+ */
+#define OPAMP_LOCK_1 0x01L
+#define OPAMP_LOCK_2 0x02L
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/**
+ * @brief OPAMP Init structure definition
+ */
+
+typedef struct
+{
+ OPAMP2_CS_TIMSRCSEL Opa2SrcSel; /*only for opa2 can sel,opa1 always TIM1_CC6*/
+
+ FunctionalState TimeAutoMuxEn; /*call ENABLE or DISABLE */
+
+ FunctionalState HighVolRangeEn; /*call ENABLE or DISABLE ,low range VDDA < 2.4V,high range VDDA >= 2.4V*/
+
+ OPAMP_CS_PGA_GAIN Gain; /*see @EM_PGA_GAIN */
+
+ OPAMP_CS_MOD Mod; /*see @EM_OPAMP_MOD*/
+} OPAMP_InitType;
+
+/** @addtogroup OPAMP_Exported_Functions
+ * @{
+ */
+
+void OPAMP_DeInit(void);
+void OPAMP_StructInit(OPAMP_InitType* OPAMP_InitStruct);
+void OPAMP_Init(OPAMPX OPAMPx, OPAMP_InitType* OPAMP_InitStruct);
+void OPAMP_Enable(OPAMPX OPAMPx, FunctionalState en);
+void OPAMP_SetPgaGain(OPAMPX OPAMPx, OPAMP_CS_PGA_GAIN Gain);
+void OPAMP_SetVpSecondSel(OPAMPX OPAMPx, OPAMP_CS_VPSSEL VpSSel);
+void OPAMP_SetVmSecondSel(OPAMPX OPAMPx, OPAMP_CS_VMSSEL VmSSel);
+void OPAMP_SetVpSel(OPAMPX OPAMPx, OPAMP_CS_VPSEL VpSel);
+void OPAMP_SetVmSel(OPAMPX OPAMPx, OPAMP_CS_VMSEL VmSel);
+bool OPAMP_IsCalOutHigh(OPAMPX OPAMPx);
+void OPAMP_CalibrationEnable(OPAMPX OPAMPx, FunctionalState en);
+void OPAMP_SetLock(uint32_t Lock); // see @OPAMP_LOCK
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32L43X_ADC_H */
+ /**
+ * @}
+ */
+ /**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_pwr.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_pwr.h
new file mode 100644
index 0000000000..6e7199ad3f
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_pwr.h
@@ -0,0 +1,222 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_pwr.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L43X_PWR_H__
+#define __N32L43X_PWR_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l43x.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup PWR
+ * @{
+ */
+
+/** @addtogroup PWR_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup PVD_detection_level
+ * @{
+ */
+
+#define PWR_PVDLEVEL_2V1 ((uint32_t)0x00000000)
+#define PWR_PVDLEVEL_2V25 ((uint32_t)0x0000002)
+#define PWR_PVDLEVEL_2V4 ((uint32_t)0x0000004)
+#define PWR_PVDLEVEL_2V55 ((uint32_t)0x0000006)
+#define PWR_PVDLEVEL_2V7 ((uint32_t)0x0000008)
+#define PWR_PVDLEVEL_2V85 ((uint32_t)0x000000A)
+#define PWR_PVDLEVEL_2V95 ((uint32_t)0x000000C)
+#define PWR_PVDLEVEL_IN ((uint32_t)0x000000E)
+
+
+#define IS_PWR_PVD_LEVEL(LEVEL) \
+ (((LEVEL) == PWR_PVDLEVEL_2V1) || ((LEVEL) == PWR_PVDLEVEL_2V25) || ((LEVEL) == PWR_PVDLEVEL_2V4) \
+ || ((LEVEL) == PWR_PVDLEVEL_2V55) || ((LEVEL) == PWR_PVDLEVEL_2V7) || ((LEVEL) == PWR_PVDLEVEL_2V85) \
+ || ((LEVEL) == PWR_PVDLEVEL_2V95) || ((LEVEL) == PWR_PVDLEVEL_IN) )
+
+/**
+ * @}
+ */
+
+/** @addtogroup Regulator_state_is_STOP_mode
+ * @{
+ */
+
+#define PWR_REGULATOR_ON ((uint32_t)0x00000000)
+#define PWR_REGULATOR_LOWPOWER ((uint32_t)0x00000001)
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_REGULATOR_ON) || ((REGULATOR) == PWR_REGULATOR_LOWPOWER))
+/**
+ * @}
+ */
+
+/** @defgroup SLEEP_mode_entry
+ * @{
+ */
+#define SLEEP_ON_EXIT (1)
+#define SLEEP_OFF_EXIT (0)
+#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
+#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
+
+
+/**
+ * @}
+ */
+
+
+/** @defgroup STOP_mode_entry
+ * @{
+ */
+
+#define PWR_STOPENTRY_WFI ((uint8_t)0x01)
+#define PWR_STOPENTRY_WFE ((uint8_t)0x02)
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Flag
+ * @{
+ */
+//STS1
+#define PWR_WKUP0_FLAG ((uint32_t)0x00000001)
+#define PWR_WKUP1_FLAG ((uint32_t)0x00000002)
+#define PWR_WKUP2_FLAG ((uint32_t)0x00000004)
+#define PWR_STBY_FLAG ((uint32_t)0x00000100)
+//STS2
+#define PWR_LPRUN_FLAG ((uint32_t)0x00000001)
+#define PWR_MR_FLAG ((uint32_t)0x00000002)
+#define PWR_PVDO_FLAG ((uint32_t)0x00000004)
+
+#define IS_PWR_GET_FLAG(FLAG) \
+ (((FLAG) == PWR_WKUP0_FLAG) || ((FLAG) == PWR_WKUP1_FLAG) || ((FLAG) == PWR_WKUP2_FLAG) || ((FLAG) == PWR_STBY_FLAG)\
+ || ((FLAG) == PWR_LPRUN_FLAG) || ((FLAG) == PWR_MR_FLAG) || ((FLAG) == PWR_PVDO_FLAG))
+
+#define IS_PWR_CLEAR_FLAG(FLAG) \
+ (((FLAG) == PWR_WKUP0_FLAG) || ((FLAG) == PWR_WKUP1_FLAG) || ((FLAG) == PWR_WKUP2_FLAG) || ((FLAG) == PWR_STBY_FLAG)\
+ || ((FLAG) == PWR_LPRUN_FLAG) || ((FLAG) == PWR_MR_FLAG) || ((FLAG) == PWR_PVDO_FLAG))
+
+
+
+/** @addtogroup SRAM1 SRAM2 retention set
+ * @{
+ */
+//#define SRAM1DIS_SRAM2DIS 0
+//#define SRAM1EN_SRAM2DIS 1
+
+//#define SRAM1DIS_SRAM2EN 2
+//#define SRAM1EN_SRAM2EN 3
+/** @addtogroup MR VOLTAGE
+ * @{
+ */
+#define MR_1V0 2
+#define MR_1V1 3
+
+
+/**
+ * @}
+ */
+typedef enum
+{
+ WAKEUP_PIN0 = 0x0001,
+ WAKEUP_PIN1 = 0x0002,
+ WAKEUP_PIN2 = 0x0004,
+} WAKEUP_PINX;
+/** @addtogroup PWR_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+#define LPRUN_SRAM_ADDR (__IO unsigned*)(0x40001800 + 0x20)
+#define CLERR_BIT25 0xfdffffff //bit25
+#define _SetLprunSramVoltage(vale) do{(*LPRUN_SRAM_ADDR) &= CLERR_BIT25;(*LPRUN_SRAM_ADDR) |= (uint32_t)(vale <<25);}while (0) //0:0.9V 1:1.1V
+#define _SetBandGapMode(vale) do{PWR->CTRL3 &= (~PWR_CTRL3_BGDTLPR);PWR->CTRL3 |= (uint32_t)(vale <<8);}while (0) //0:always on 1:duty on
+#define _SetPvdBorMode(vale) do{PWR->CTRL3 &= (~PWR_CTRL3_PBDTLPR);PWR->CTRL3 |= (uint32_t)(vale <<16);}while (0) //0:normal mode 1:standby mode
+/** @addtogroup PWR_Exported_Functions
+ * @{
+ */
+
+void PWR_DeInit(void);
+void PWR_BackupAccessEnable(FunctionalState Cmd);
+void PWR_PvdEnable(FunctionalState Cmd);
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
+void PWR_WakeUpPinEnable(WAKEUP_PINX WKUP_Pin,FunctionalState Cmd);
+void PWR_EnterStopState(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+void PWR_EnterSLEEPMode(uint8_t SLEEPONEXIT, uint8_t PWR_STOPEntry);
+void PWR_EnterSTOP2Mode(uint8_t PWR_STOPEntry,uint32_t RetentionMode);
+void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry,uint32_t Sam2Ret);
+void PWR_EnterLowPowerRunMode(void);
+void PWR_ExitLowPowerRunMode(void);
+void PWR_EnterLowPowerSleepMode(uint8_t SLEEPONEXIT, uint8_t PWR_SLEEPEntry);
+
+FlagStatus PWR_GetFlagStatus(uint8_t STS, uint32_t PWR_FLAG);
+void PWR_ClearFlag(uint32_t PWR_FLAG);
+void PWR_WakeUpPinConfig(void);
+void SetSysClock_MSI(void);
+uint8_t GetMrVoltage(void);
+void PWR_MRconfig(uint8_t voltage);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32L43X_PWR_H__ */
+ /**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_rcc.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_rcc.h
new file mode 100644
index 0000000000..c80d02ea44
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_rcc.h
@@ -0,0 +1,913 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_rcc.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L43X_RCC_H__
+#define __N32L43X_RCC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l43x.h"
+
+/** @addtogroup N32L43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RCC
+ * @{
+ */
+
+/** @addtogroup RCC_Exported_Types
+ * @{
+ */
+
+typedef struct
+{
+ uint32_t SysclkFreq; /*!< returns SYSCLK clock frequency expressed in Hz */
+ uint32_t HclkFreq; /*!< returns HCLK clock frequency expressed in Hz */
+ uint32_t Pclk1Freq; /*!< returns PCLK1 clock frequency expressed in Hz */
+ uint32_t Pclk2Freq; /*!< returns PCLK2 clock frequency expressed in Hz */
+ uint32_t AdcPllClkFreq; /*!< returns ADCPLLCLK clock frequency expressed in Hz */
+ uint32_t AdcHclkFreq; /*!< returns ADCHCLK clock frequency expressed in Hz */
+} RCC_ClocksType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup HSE_configuration
+ * @{
+ */
+
+#define RCC_HSE_DISABLE ((uint32_t)0x00000000)
+#define RCC_HSE_ENABLE ((uint32_t)0x00010000)
+#define RCC_HSE_BYPASS ((uint32_t)0x00040000)
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_DISABLE) || ((HSE) == RCC_HSE_ENABLE) || ((HSE) == RCC_HSE_BYPASS))
+
+/**
+ * @}
+ */
+
+/** @addtogroup HSI_configuration
+ * @{
+ */
+
+#define RCC_HSI_DISABLE ((uint32_t)0x00000000)
+#define RCC_HSI_ENABLE ((uint32_t)0x00000001)
+#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_DISABLE) || ((HSI) == RCC_HSI_ENABLE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup MSI_configuration
+ * @{
+ */
+
+#define RCC_MSI_DISABLE ((uint32_t)0x00000000)
+#define RCC_MSI_ENABLE ((uint32_t)0x00000004)
+#define IS_RCC_MSI(MSI) (((MSI) == RCC_MSI_DISABLE) || ((MSI) == RCC_MSI_ENABLE))
+
+#define RCC_MSI_RANGE_100K ((uint32_t)0x00000000)
+#define RCC_MSI_RANGE_200K ((uint32_t)0x00000010)
+#define RCC_MSI_RANGE_400K ((uint32_t)0x00000020)
+#define RCC_MSI_RANGE_800K ((uint32_t)0x00000030)
+#define RCC_MSI_RANGE_1M ((uint32_t)0x00000040)
+#define RCC_MSI_RANGE_2M ((uint32_t)0x00000050)
+#define RCC_MSI_RANGE_4M ((uint32_t)0x00000060)
+#define IS_RCC_MSI_RANGE(MSI_RANGE) (((MSI_RANGE) == RCC_MSI_RANGE_100K) || ((MSI_RANGE) == RCC_MSI_RANGE_200K) \
+ || ((MSI_RANGE) == RCC_MSI_RANGE_400K) || ((MSI_RANGE) == RCC_MSI_RANGE_800K) \
+ || ((MSI_RANGE) == RCC_MSI_RANGE_1M) || ((MSI_RANGE) == RCC_MSI_RANGE_2M) \
+ || ((MSI_RANGE) == RCC_MSI_RANGE_4M) \
+ )
+
+/**
+ * @}
+ */
+
+/** @addtogroup PLL_entry_clock_source
+ * @{
+ */
+#define RCC_PLL_HSI_PRE_DIV1 ((uint32_t)0x00000000)
+#define RCC_PLL_HSI_PRE_DIV2 ((uint32_t)0x00000001)
+
+#define RCC_PLL_SRC_HSE_DIV1 ((uint32_t)0x00010000)
+#define RCC_PLL_SRC_HSE_DIV2 ((uint32_t)0x00030000)
+#define IS_RCC_PLL_SRC(SOURCE) \
+ (((SOURCE) == RCC_PLL_HSI_PRE_DIV1) || ((SOURCE) == RCC_PLL_HSI_PRE_DIV2) \
+ || ((SOURCE) == RCC_PLL_SRC_HSE_DIV1) || ((SOURCE) == RCC_PLL_SRC_HSE_DIV2))
+
+#define RCC_PLLDIVCLK_DISABLE ((uint32_t)0x00000000)
+#define RCC_PLLDIVCLK_ENABLE ((uint32_t)0x00000002)
+#define IS_RCC_PLL_DIVCLK(DIVCLK) \
+ (((DIVCLK) == RCC_PLLDIVCLK_DISABLE) || ((DIVCLK) == RCC_PLLDIVCLK_ENABLE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup PLL_multiplication_factor
+ * @{
+ */
+#define RCC_PLL_MUL_2 ((uint32_t)0x00000000)
+#define RCC_PLL_MUL_3 ((uint32_t)0x00040000)
+#define RCC_PLL_MUL_4 ((uint32_t)0x00080000)
+#define RCC_PLL_MUL_5 ((uint32_t)0x000C0000)
+#define RCC_PLL_MUL_6 ((uint32_t)0x00100000)
+#define RCC_PLL_MUL_7 ((uint32_t)0x00140000)
+#define RCC_PLL_MUL_8 ((uint32_t)0x00180000)
+#define RCC_PLL_MUL_9 ((uint32_t)0x001C0000)
+#define RCC_PLL_MUL_10 ((uint32_t)0x00200000)
+#define RCC_PLL_MUL_11 ((uint32_t)0x00240000)
+#define RCC_PLL_MUL_12 ((uint32_t)0x00280000)
+#define RCC_PLL_MUL_13 ((uint32_t)0x002C0000)
+#define RCC_PLL_MUL_14 ((uint32_t)0x00300000)
+#define RCC_PLL_MUL_15 ((uint32_t)0x00340000)
+#define RCC_PLL_MUL_16 ((uint32_t)0x00380000)
+#define RCC_PLL_MUL_17 ((uint32_t)0x08000000)
+#define RCC_PLL_MUL_18 ((uint32_t)0x08040000)
+#define RCC_PLL_MUL_19 ((uint32_t)0x08080000)
+#define RCC_PLL_MUL_20 ((uint32_t)0x080C0000)
+#define RCC_PLL_MUL_21 ((uint32_t)0x08100000)
+#define RCC_PLL_MUL_22 ((uint32_t)0x08140000)
+#define RCC_PLL_MUL_23 ((uint32_t)0x08180000)
+#define RCC_PLL_MUL_24 ((uint32_t)0x081C0000)
+#define RCC_PLL_MUL_25 ((uint32_t)0x08200000)
+#define RCC_PLL_MUL_26 ((uint32_t)0x08240000)
+#define RCC_PLL_MUL_27 ((uint32_t)0x08280000)
+#define RCC_PLL_MUL_28 ((uint32_t)0x082C0000)
+#define RCC_PLL_MUL_29 ((uint32_t)0x08300000)
+#define RCC_PLL_MUL_30 ((uint32_t)0x08340000)
+#define RCC_PLL_MUL_31 ((uint32_t)0x08380000)
+#define RCC_PLL_MUL_32 ((uint32_t)0x083C0000)
+#define IS_RCC_PLL_MUL(MUL) \
+ (((MUL) == RCC_PLL_MUL_2) || ((MUL) == RCC_PLL_MUL_3) || ((MUL) == RCC_PLL_MUL_4) || ((MUL) == RCC_PLL_MUL_5) \
+ || ((MUL) == RCC_PLL_MUL_6) || ((MUL) == RCC_PLL_MUL_7) || ((MUL) == RCC_PLL_MUL_8) || ((MUL) == RCC_PLL_MUL_9) \
+ || ((MUL) == RCC_PLL_MUL_10) || ((MUL) == RCC_PLL_MUL_11) || ((MUL) == RCC_PLL_MUL_12) \
+ || ((MUL) == RCC_PLL_MUL_13) || ((MUL) == RCC_PLL_MUL_14) || ((MUL) == RCC_PLL_MUL_15) \
+ || ((MUL) == RCC_PLL_MUL_16) || ((MUL) == RCC_PLL_MUL_17) || ((MUL) == RCC_PLL_MUL_18) \
+ || ((MUL) == RCC_PLL_MUL_19) || ((MUL) == RCC_PLL_MUL_20) || ((MUL) == RCC_PLL_MUL_21) \
+ || ((MUL) == RCC_PLL_MUL_22) || ((MUL) == RCC_PLL_MUL_23) || ((MUL) == RCC_PLL_MUL_24) \
+ || ((MUL) == RCC_PLL_MUL_25) || ((MUL) == RCC_PLL_MUL_26) || ((MUL) == RCC_PLL_MUL_27) \
+ || ((MUL) == RCC_PLL_MUL_28) || ((MUL) == RCC_PLL_MUL_29) || ((MUL) == RCC_PLL_MUL_30) \
+ || ((MUL) == RCC_PLL_MUL_31) || ((MUL) == RCC_PLL_MUL_32))
+
+/**
+ * @}
+ */
+
+/** @addtogroup System_clock_source
+ * @{
+ */
+
+#define RCC_SYSCLK_SRC_MSI ((uint32_t)0x00000000)
+#define RCC_SYSCLK_SRC_HSI ((uint32_t)0x00000001)
+#define RCC_SYSCLK_SRC_HSE ((uint32_t)0x00000002)
+#define RCC_SYSCLK_SRC_PLLCLK ((uint32_t)0x00000003)
+#define IS_RCC_SYSCLK_SRC(SOURCE) \
+ (((SOURCE) == RCC_SYSCLK_SRC_MSI) || ((SOURCE) == RCC_SYSCLK_SRC_HSI) \
+ || ((SOURCE) == RCC_SYSCLK_SRC_HSE) || ((SOURCE) == RCC_SYSCLK_SRC_PLLCLK))
+/**
+ * @}
+ */
+
+/** @addtogroup AHB_clock_source
+ * @{
+ */
+
+#define RCC_SYSCLK_DIV1 ((uint32_t)0x00000000)
+#define RCC_SYSCLK_DIV2 ((uint32_t)0x00000080)
+#define RCC_SYSCLK_DIV4 ((uint32_t)0x00000090)
+#define RCC_SYSCLK_DIV8 ((uint32_t)0x000000A0)
+#define RCC_SYSCLK_DIV16 ((uint32_t)0x000000B0)
+#define RCC_SYSCLK_DIV64 ((uint32_t)0x000000C0)
+#define RCC_SYSCLK_DIV128 ((uint32_t)0x000000D0)
+#define RCC_SYSCLK_DIV256 ((uint32_t)0x000000E0)
+#define RCC_SYSCLK_DIV512 ((uint32_t)0x000000F0)
+#define IS_RCC_SYSCLK_DIV(HCLK) \
+ (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || ((HCLK) == RCC_SYSCLK_DIV4) \
+ || ((HCLK) == RCC_SYSCLK_DIV8) || ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) \
+ || ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || ((HCLK) == RCC_SYSCLK_DIV512))
+/**
+ * @}
+ */
+
+/** @addtogroup APB1_APB2_clock_source
+ * @{
+ */
+
+#define RCC_HCLK_DIV1 ((uint32_t)0x00000000)
+#define RCC_HCLK_DIV2 ((uint32_t)0x00000400)
+#define RCC_HCLK_DIV4 ((uint32_t)0x00000500)
+#define RCC_HCLK_DIV8 ((uint32_t)0x00000600)
+#define RCC_HCLK_DIV16 ((uint32_t)0x00000700)
+#define IS_RCC_HCLK_DIV(PCLK) \
+ (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) \
+ || ((PCLK) == RCC_HCLK_DIV16))
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Interrupt_source
+ * @{
+ */
+
+#define RCC_INT_LSIRDIF ((uint8_t)0x01)
+#define RCC_INT_LSERDIF ((uint8_t)0x02)
+#define RCC_INT_HSIRDIF ((uint8_t)0x04)
+#define RCC_INT_HSERDIF ((uint8_t)0x08)
+#define RCC_INT_PLLRDIF ((uint8_t)0x10)
+#define RCC_INT_BORIF ((uint8_t)0x20)
+#define RCC_INT_MSIRDIF ((uint8_t)0x40)
+#define RCC_INT_CLKSSIF ((uint8_t)0x80)
+
+#define IS_RCC_INT(IT) \
+ (((IT) == RCC_INT_LSIRDIF) || ((IT) == RCC_INT_LSERDIF) || ((IT) == RCC_INT_HSIRDIF) || ((IT) == RCC_INT_HSERDIF) \
+ || ((IT) == RCC_INT_PLLRDIF) || ((IT) == RCC_INT_BORIF) || ((IT) == RCC_INT_MSIRDIF))
+
+#define IS_RCC_GET_INT(IT) \
+ (((IT) == RCC_INT_LSIRDIF) || ((IT) == RCC_INT_LSERDIF) || ((IT) == RCC_INT_HSIRDIF) || ((IT) == RCC_INT_HSERDIF) \
+ || ((IT) == RCC_INT_PLLRDIF) || ((IT) == RCC_INT_BORIF) || ((IT) == RCC_INT_MSIRDIF) || ((IT) == RCC_INT_CLKSSIF))
+
+#define RCC_CLR_MSIRDIF ((uint32_t)0x00008000)
+#define RCC_CLR_LSIRDIF ((uint32_t)0x00010000)
+#define RCC_CLR_LSERDIF ((uint32_t)0x00020000)
+#define RCC_CLR_HSIRDIF ((uint32_t)0x00040000)
+#define RCC_CLR_HSERDIF ((uint32_t)0x00080000)
+#define RCC_CLR_PLLRDIF ((uint32_t)0x00100000)
+#define RCC_CLR_BORIF ((uint32_t)0x00200000)
+#define RCC_CLR_CLKSSIF ((uint32_t)0x00800000)
+
+#define IS_RCC_CLR_INTF(IT) \
+ (((IT) == RCC_CLR_LSIRDIF) || ((IT) == RCC_CLR_LSERDIF) || ((IT) == RCC_CLR_HSIRDIF) || ((IT) == RCC_CLR_HSERDIF) \
+ || ((IT) == RCC_CLR_PLLRDIF) || ((IT) == RCC_CLR_BORIF) || ((IT) == RCC_CLR_MSIRDIF) || ((IT) == RCC_CLR_CLKSSIF))
+
+/**
+ * @}
+ */
+
+/** @addtogroup USB_Device_clock_source
+ * @{
+ */
+
+#define RCC_USBCLK_SRC_PLLCLK_DIV1_5 ((uint8_t)0x00)
+#define RCC_USBCLK_SRC_PLLCLK_DIV1 ((uint8_t)0x01)
+#define RCC_USBCLK_SRC_PLLCLK_DIV2 ((uint8_t)0x02)
+#define RCC_USBCLK_SRC_PLLCLK_DIV3 ((uint8_t)0x03)
+
+#define IS_RCC_USBCLK_SRC(SOURCE) \
+ (((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV1_5) || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV1) \
+ || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV2) || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV3))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_clock_source
+ * @{
+ */
+
+#define RCC_PCLK2_DIV2 ((uint32_t)0x00000000)
+#define RCC_PCLK2_DIV4 ((uint32_t)0x00004000)
+#define RCC_PCLK2_DIV6 ((uint32_t)0x00008000)
+#define RCC_PCLK2_DIV8 ((uint32_t)0x0000C000)
+#define IS_RCC_PCLK2_DIV(ADCCLK) \
+ (((ADCCLK) == RCC_PCLK2_DIV2) || ((ADCCLK) == RCC_PCLK2_DIV4) || ((ADCCLK) == RCC_PCLK2_DIV6) \
+ || ((ADCCLK) == RCC_PCLK2_DIV8))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_CFGR2_Config
+ * @{
+ */
+#define RCC_TIM18CLK_SRC_TIM18CLK ((uint32_t)0x00000000)
+#define RCC_TIM18CLK_SRC_SYSCLK ((uint32_t)0x20000000)
+#define IS_RCC_TIM18CLKSRC(TIM18CLK) \
+ (((TIM18CLK) == RCC_TIM18CLK_SRC_TIM18CLK) || ((TIM18CLK) == RCC_TIM18CLK_SRC_SYSCLK))
+
+#define RCC_RNGCCLK_SYSCLK_DIV1 ((uint32_t)0x00000000)
+#define RCC_RNGCCLK_SYSCLK_DIV2 ((uint32_t)0x01000000)
+#define RCC_RNGCCLK_SYSCLK_DIV3 ((uint32_t)0x02000000)
+#define RCC_RNGCCLK_SYSCLK_DIV4 ((uint32_t)0x03000000)
+#define RCC_RNGCCLK_SYSCLK_DIV5 ((uint32_t)0x04000000)
+#define RCC_RNGCCLK_SYSCLK_DIV6 ((uint32_t)0x05000000)
+#define RCC_RNGCCLK_SYSCLK_DIV7 ((uint32_t)0x06000000)
+#define RCC_RNGCCLK_SYSCLK_DIV8 ((uint32_t)0x07000000)
+#define RCC_RNGCCLK_SYSCLK_DIV9 ((uint32_t)0x08000000)
+#define RCC_RNGCCLK_SYSCLK_DIV10 ((uint32_t)0x09000000)
+#define RCC_RNGCCLK_SYSCLK_DIV11 ((uint32_t)0x0A000000)
+#define RCC_RNGCCLK_SYSCLK_DIV12 ((uint32_t)0x0B000000)
+#define RCC_RNGCCLK_SYSCLK_DIV13 ((uint32_t)0x0C000000)
+#define RCC_RNGCCLK_SYSCLK_DIV14 ((uint32_t)0x0D000000)
+#define RCC_RNGCCLK_SYSCLK_DIV15 ((uint32_t)0x0E000000)
+#define RCC_RNGCCLK_SYSCLK_DIV16 ((uint32_t)0x0F000000)
+#define RCC_RNGCCLK_SYSCLK_DIV17 ((uint32_t)0x10000000)
+#define RCC_RNGCCLK_SYSCLK_DIV18 ((uint32_t)0x11000000)
+#define RCC_RNGCCLK_SYSCLK_DIV19 ((uint32_t)0x12000000)
+#define RCC_RNGCCLK_SYSCLK_DIV20 ((uint32_t)0x13000000)
+#define RCC_RNGCCLK_SYSCLK_DIV21 ((uint32_t)0x14000000)
+#define RCC_RNGCCLK_SYSCLK_DIV22 ((uint32_t)0x15000000)
+#define RCC_RNGCCLK_SYSCLK_DIV23 ((uint32_t)0x16000000)
+#define RCC_RNGCCLK_SYSCLK_DIV24 ((uint32_t)0x17000000)
+#define RCC_RNGCCLK_SYSCLK_DIV25 ((uint32_t)0x18000000)
+#define RCC_RNGCCLK_SYSCLK_DIV26 ((uint32_t)0x19000000)
+#define RCC_RNGCCLK_SYSCLK_DIV27 ((uint32_t)0x1A000000)
+#define RCC_RNGCCLK_SYSCLK_DIV28 ((uint32_t)0x1B000000)
+#define RCC_RNGCCLK_SYSCLK_DIV29 ((uint32_t)0x1C000000)
+#define RCC_RNGCCLK_SYSCLK_DIV30 ((uint32_t)0x1D000000)
+#define RCC_RNGCCLK_SYSCLK_DIV31 ((uint32_t)0x1E000000)
+#define RCC_RNGCCLK_SYSCLK_DIV32 ((uint32_t)0x1F000000)
+#define IS_RCC_RNGCCLKPRE(DIV) \
+ (((DIV) == RCC_RNGCCLK_SYSCLK_DIV1) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV2) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV3) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV4) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV5) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV6) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV7) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV8) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV9) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV10) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV11) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV12) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV13) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV14) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV15) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV16) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV17) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV18) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV19) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV20) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV21) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV22) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV23) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV24) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV25) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV26) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV27) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV28) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV29) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV30) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV31) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV32))
+
+#define RCC_ADC1MCLK_SRC_HSI ((uint32_t)0x00000000)
+#define RCC_ADC1MCLK_SRC_HSE ((uint32_t)0x00020000)
+#define IS_RCC_ADC1MCLKSRC(ADC1MCLK) (((ADC1MCLK) == RCC_ADC1MCLK_SRC_HSI) || ((ADC1MCLK) == RCC_ADC1MCLK_SRC_HSE))
+
+#define RCC_ADC1MCLK_DIV1 ((uint32_t)0x00000000)
+#define RCC_ADC1MCLK_DIV2 ((uint32_t)0x00001000)
+#define RCC_ADC1MCLK_DIV3 ((uint32_t)0x00002000)
+#define RCC_ADC1MCLK_DIV4 ((uint32_t)0x00003000)
+#define RCC_ADC1MCLK_DIV5 ((uint32_t)0x00004000)
+#define RCC_ADC1MCLK_DIV6 ((uint32_t)0x00005000)
+#define RCC_ADC1MCLK_DIV7 ((uint32_t)0x00006000)
+#define RCC_ADC1MCLK_DIV8 ((uint32_t)0x00007000)
+#define RCC_ADC1MCLK_DIV9 ((uint32_t)0x00008000)
+#define RCC_ADC1MCLK_DIV10 ((uint32_t)0x00009000)
+#define RCC_ADC1MCLK_DIV11 ((uint32_t)0x0000A000)
+#define RCC_ADC1MCLK_DIV12 ((uint32_t)0x0000B000)
+#define RCC_ADC1MCLK_DIV13 ((uint32_t)0x0000C000)
+#define RCC_ADC1MCLK_DIV14 ((uint32_t)0x0000D000)
+#define RCC_ADC1MCLK_DIV15 ((uint32_t)0x0000E000)
+#define RCC_ADC1MCLK_DIV16 ((uint32_t)0x0000F000)
+#define RCC_ADC1MCLK_DIV17 ((uint32_t)0x00010000)
+#define RCC_ADC1MCLK_DIV18 ((uint32_t)0x00011000)
+#define RCC_ADC1MCLK_DIV19 ((uint32_t)0x00012000)
+#define RCC_ADC1MCLK_DIV20 ((uint32_t)0x00013000)
+#define RCC_ADC1MCLK_DIV21 ((uint32_t)0x00014000)
+#define RCC_ADC1MCLK_DIV22 ((uint32_t)0x00015000)
+#define RCC_ADC1MCLK_DIV23 ((uint32_t)0x00016000)
+#define RCC_ADC1MCLK_DIV24 ((uint32_t)0x00017000)
+#define RCC_ADC1MCLK_DIV25 ((uint32_t)0x00018000)
+#define RCC_ADC1MCLK_DIV26 ((uint32_t)0x00019000)
+#define RCC_ADC1MCLK_DIV27 ((uint32_t)0x0001A000)
+#define RCC_ADC1MCLK_DIV28 ((uint32_t)0x0001B000)
+#define RCC_ADC1MCLK_DIV29 ((uint32_t)0x0001C000)
+#define RCC_ADC1MCLK_DIV30 ((uint32_t)0x0001D000)
+#define RCC_ADC1MCLK_DIV31 ((uint32_t)0x0001E000)
+#define RCC_ADC1MCLK_DIV32 ((uint32_t)0x0001F000)
+#define IS_RCC_ADC1MCLKPRE(DIV) \
+ (((DIV) == RCC_ADC1MCLK_DIV1) || ((DIV) == RCC_ADC1MCLK_DIV2) || ((DIV) == RCC_ADC1MCLK_DIV3) \
+ || ((DIV) == RCC_ADC1MCLK_DIV4) || ((DIV) == RCC_ADC1MCLK_DIV5) || ((DIV) == RCC_ADC1MCLK_DIV6) \
+ || ((DIV) == RCC_ADC1MCLK_DIV7) || ((DIV) == RCC_ADC1MCLK_DIV8) || ((DIV) == RCC_ADC1MCLK_DIV9) \
+ || ((DIV) == RCC_ADC1MCLK_DIV10) || ((DIV) == RCC_ADC1MCLK_DIV11) || ((DIV) == RCC_ADC1MCLK_DIV12) \
+ || ((DIV) == RCC_ADC1MCLK_DIV13) || ((DIV) == RCC_ADC1MCLK_DIV14) || ((DIV) == RCC_ADC1MCLK_DIV15) \
+ || ((DIV) == RCC_ADC1MCLK_DIV16) || ((DIV) == RCC_ADC1MCLK_DIV17) || ((DIV) == RCC_ADC1MCLK_DIV18) \
+ || ((DIV) == RCC_ADC1MCLK_DIV19) || ((DIV) == RCC_ADC1MCLK_DIV20) || ((DIV) == RCC_ADC1MCLK_DIV21) \
+ || ((DIV) == RCC_ADC1MCLK_DIV22) || ((DIV) == RCC_ADC1MCLK_DIV23) || ((DIV) == RCC_ADC1MCLK_DIV24) \
+ || ((DIV) == RCC_ADC1MCLK_DIV25) || ((DIV) == RCC_ADC1MCLK_DIV26) || ((DIV) == RCC_ADC1MCLK_DIV27) \
+ || ((DIV) == RCC_ADC1MCLK_DIV28) || ((DIV) == RCC_ADC1MCLK_DIV29) || ((DIV) == RCC_ADC1MCLK_DIV30) \
+ || ((DIV) == RCC_ADC1MCLK_DIV31) || ((DIV) == RCC_ADC1MCLK_DIV32))
+
+#define RCC_ADCPLLCLK_DISABLE ((uint32_t)0xFFFFFEFF)
+#define RCC_ADCPLLCLK_DIV1 ((uint32_t)0x00000100)
+#define RCC_ADCPLLCLK_DIV2 ((uint32_t)0x00000110)
+#define RCC_ADCPLLCLK_DIV4 ((uint32_t)0x00000120)
+#define RCC_ADCPLLCLK_DIV6 ((uint32_t)0x00000130)
+#define RCC_ADCPLLCLK_DIV8 ((uint32_t)0x00000140)
+#define RCC_ADCPLLCLK_DIV10 ((uint32_t)0x00000150)
+#define RCC_ADCPLLCLK_DIV12 ((uint32_t)0x00000160)
+#define RCC_ADCPLLCLK_DIV16 ((uint32_t)0x00000170)
+#define RCC_ADCPLLCLK_DIV32 ((uint32_t)0x00000180)
+#define RCC_ADCPLLCLK_DIV64 ((uint32_t)0x00000190)
+#define RCC_ADCPLLCLK_DIV128 ((uint32_t)0x000001A0)
+#define RCC_ADCPLLCLK_DIV256 ((uint32_t)0x000001B0)
+#define RCC_ADCPLLCLK_DIV_OTHERS ((uint32_t)0x000001C0)
+#define IS_RCC_ADCPLLCLKPRE(DIV) \
+ (((DIV) == RCC_ADCPLLCLK_DIV1) || ((DIV) == RCC_ADCPLLCLK_DIV2) || ((DIV) == RCC_ADCPLLCLK_DIV4) \
+ || ((DIV) == RCC_ADCPLLCLK_DIV6) || ((DIV) == RCC_ADCPLLCLK_DIV8) || ((DIV) == RCC_ADCPLLCLK_DIV10) \
+ || ((DIV) == RCC_ADCPLLCLK_DIV12) || ((DIV) == RCC_ADCPLLCLK_DIV16) || ((DIV) == RCC_ADCPLLCLK_DIV32) \
+ || ((DIV) == RCC_ADCPLLCLK_DIV64) || ((DIV) == RCC_ADCPLLCLK_DIV128) || ((DIV) == RCC_ADCPLLCLK_DIV256) \
+ || (((DIV)&RCC_ADCPLLCLK_DIV_OTHERS) == 0x000001C0))
+
+#define RCC_ADCHCLK_DIV1 ((uint32_t)0x00000000)
+#define RCC_ADCHCLK_DIV2 ((uint32_t)0x00000001)
+#define RCC_ADCHCLK_DIV4 ((uint32_t)0x00000002)
+#define RCC_ADCHCLK_DIV6 ((uint32_t)0x00000003)
+#define RCC_ADCHCLK_DIV8 ((uint32_t)0x00000004)
+#define RCC_ADCHCLK_DIV10 ((uint32_t)0x00000005)
+#define RCC_ADCHCLK_DIV12 ((uint32_t)0x00000006)
+#define RCC_ADCHCLK_DIV16 ((uint32_t)0x00000007)
+#define RCC_ADCHCLK_DIV32 ((uint32_t)0x00000008)
+#define RCC_ADCHCLK_DIV_OTHERS ((uint32_t)0x00000008)
+#define IS_RCC_ADCHCLKPRE(DIV) \
+ (((DIV) == RCC_ADCHCLK_DIV1) || ((DIV) == RCC_ADCHCLK_DIV2) || ((DIV) == RCC_ADCHCLK_DIV4) \
+ || ((DIV) == RCC_ADCHCLK_DIV6) || ((DIV) == RCC_ADCHCLK_DIV8) || ((DIV) == RCC_ADCHCLK_DIV10) \
+ || ((DIV) == RCC_ADCHCLK_DIV12) || ((DIV) == RCC_ADCHCLK_DIV16) || ((DIV) == RCC_ADCHCLK_DIV32) \
+ || (((DIV)&RCC_ADCHCLK_DIV_OTHERS) != 0x00))
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_CFGR3_Config
+ * @{
+ */
+
+#define RCC_TRNG1MCLK_ENABLE ((uint32_t)0x00040000)
+#define RCC_TRNG1MCLK_DISABLE ((uint32_t)0xFFFBFFFF)
+
+#define RCC_TRNG1MCLK_SRC_HSI ((uint32_t)0x00000000)
+#define RCC_TRNG1MCLK_SRC_HSE ((uint32_t)0x00020000)
+#define IS_RCC_TRNG1MCLK_SRC(TRNG1MCLK) \
+ (((TRNG1MCLK) == RCC_TRNG1MCLK_SRC_HSI) || ((TRNG1MCLK) == RCC_TRNG1MCLK_SRC_HSE))
+
+#define RCC_TRNG1MCLK_DIV2 ((uint32_t)0x00000800)
+#define RCC_TRNG1MCLK_DIV4 ((uint32_t)0x00001000)
+#define RCC_TRNG1MCLK_DIV6 ((uint32_t)0x00001800)
+#define RCC_TRNG1MCLK_DIV8 ((uint32_t)0x00002000)
+#define RCC_TRNG1MCLK_DIV10 ((uint32_t)0x00002800)
+#define RCC_TRNG1MCLK_DIV12 ((uint32_t)0x00003000)
+#define RCC_TRNG1MCLK_DIV14 ((uint32_t)0x00003800)
+#define RCC_TRNG1MCLK_DIV16 ((uint32_t)0x00004000)
+#define RCC_TRNG1MCLK_DIV18 ((uint32_t)0x00004800)
+#define RCC_TRNG1MCLK_DIV20 ((uint32_t)0x00005000)
+#define RCC_TRNG1MCLK_DIV22 ((uint32_t)0x00005800)
+#define RCC_TRNG1MCLK_DIV24 ((uint32_t)0x00006000)
+#define RCC_TRNG1MCLK_DIV26 ((uint32_t)0x00006800)
+#define RCC_TRNG1MCLK_DIV28 ((uint32_t)0x00007000)
+#define RCC_TRNG1MCLK_DIV30 ((uint32_t)0x00007800)
+#define RCC_TRNG1MCLK_DIV32 ((uint32_t)0x00008000)
+#define RCC_TRNG1MCLK_DIV34 ((uint32_t)0x00008800)
+#define RCC_TRNG1MCLK_DIV36 ((uint32_t)0x00009000)
+#define RCC_TRNG1MCLK_DIV38 ((uint32_t)0x00009800)
+#define RCC_TRNG1MCLK_DIV40 ((uint32_t)0x0000A000)
+#define RCC_TRNG1MCLK_DIV42 ((uint32_t)0x0000A800)
+#define RCC_TRNG1MCLK_DIV44 ((uint32_t)0x0000B000)
+#define RCC_TRNG1MCLK_DIV46 ((uint32_t)0x0000B800)
+#define RCC_TRNG1MCLK_DIV48 ((uint32_t)0x0000C000)
+#define RCC_TRNG1MCLK_DIV50 ((uint32_t)0x0000C800)
+#define RCC_TRNG1MCLK_DIV52 ((uint32_t)0x0000D000)
+#define RCC_TRNG1MCLK_DIV54 ((uint32_t)0x0000D800)
+#define RCC_TRNG1MCLK_DIV56 ((uint32_t)0x0000E000)
+#define RCC_TRNG1MCLK_DIV58 ((uint32_t)0x0000E800)
+#define RCC_TRNG1MCLK_DIV60 ((uint32_t)0x0000F000)
+#define RCC_TRNG1MCLK_DIV62 ((uint32_t)0x0000F800)
+#define IS_RCC_TRNG1MCLKPRE(VAL) \
+ (((VAL) == RCC_TRNG1MCLK_DIV2) || ((VAL) == RCC_TRNG1MCLK_DIV4) || ((VAL) == RCC_TRNG1MCLK_DIV6) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV8) || ((VAL) == RCC_TRNG1MCLK_DIV10) || ((VAL) == RCC_TRNG1MCLK_DIV12) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV14) || ((VAL) == RCC_TRNG1MCLK_DIV16) || ((VAL) == RCC_TRNG1MCLK_DIV18) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV20) || ((VAL) == RCC_TRNG1MCLK_DIV22) || ((VAL) == RCC_TRNG1MCLK_DIV24) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV26) || ((VAL) == RCC_TRNG1MCLK_DIV28) || ((VAL) == RCC_TRNG1MCLK_DIV30) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV32) || ((VAL) == RCC_TRNG1MCLK_DIV34) || ((VAL) == RCC_TRNG1MCLK_DIV36) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV38) || ((VAL) == RCC_TRNG1MCLK_DIV40) || ((VAL) == RCC_TRNG1MCLK_DIV42) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV44) || ((VAL) == RCC_TRNG1MCLK_DIV46) || ((VAL) == RCC_TRNG1MCLK_DIV48) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV50) || ((VAL) == RCC_TRNG1MCLK_DIV52) || ((VAL) == RCC_TRNG1MCLK_DIV54) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV56) || ((VAL) == RCC_TRNG1MCLK_DIV58) || ((VAL) == RCC_TRNG1MCLK_DIV60) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV62))
+
+#define RCC_UCDR_ENABLE ((uint32_t)0x00000080)
+#define RCC_UCDR_DISABLE ((uint32_t)0xFFFFFF7F)
+
+#define RCC_UCDR300MSource_MASK ((uint32_t)0xFFFFFDFF)
+#define RCC_UCDR300M_SRC_OSC300M ((uint32_t)0x00000000)
+#define RCC_UCDR300M_SRC_PLLVCO ((uint32_t)0x00000200)
+#define IS_RCC_UCDR300M_SRC(UCDR300MCLK) \
+ (((UCDR300MCLK) == RCC_UCDR300M_SRC_OSC300M) || ((UCDR300MCLK) == RCC_UCDR300M_SRC_PLLVCO))
+
+#define RCC_USBXTALESSMode_MASK ((uint32_t)0xFFFFFEFF)
+#define RCC_USBXTALESS_MODE ((uint32_t)0x00000000)
+#define RCC_USBXTALESS_LESSMODE ((uint32_t)0x00000100)
+#define IS_RCC_USBXTALESS_MODE(USBXTALESS) \
+ (((USBXTALESS) == RCC_USBXTALESS_MODE) || ((USBXTALESS) == RCC_USBXTALESS_LESSMODE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup LSE_configuration
+ * @{
+ */
+
+#define RCC_LSE_DISABLE ((uint32_t)0x00000000)
+#define RCC_LSE_ENABLE ((uint32_t)0x00000001)
+#define RCC_LSE_BYPASS ((uint32_t)0x00000004)
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_DISABLE) || ((LSE) == RCC_LSE_ENABLE) || ((LSE) == RCC_LSE_BYPASS))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_clock_source
+ * @{
+ */
+
+#define RCC_RTCCLK_SRC_NONE ((uint32_t)0x00000000)
+#define RCC_RTCCLK_SRC_LSE ((uint32_t)0x00000100)
+#define RCC_RTCCLK_SRC_LSI ((uint32_t)0x00000200)
+#define RCC_RTCCLK_SRC_HSE_DIV32 ((uint32_t)0x00000300)
+#define IS_RCC_RTCCLK_SRC(SOURCE) \
+ (((SOURCE) == RCC_RTCCLK_SRC_NONE) || ((SOURCE) == RCC_RTCCLK_SRC_LSE) || ((SOURCE) == RCC_RTCCLK_SRC_LSI) \
+ || ((SOURCE) == RCC_RTCCLK_SRC_HSE_DIV32))
+/**
+ * @}
+ */
+
+/** @addtogroup LSX_clock_source
+ * @{
+ */
+
+#define RCC_LSXCLK_SRC_LSI ((uint32_t)0x00000000)
+#define RCC_LSXCLK_SRC_LSE ((uint32_t)0x00000020)
+#define IS_RCC_LSXCLK_SRC(SOURCE) \
+ (((SOURCE) == RCC_LSXCLK_SRC_LSI) || ((SOURCE) == RCC_LSXCLK_SRC_LSE))
+/**
+ * @}
+ */
+
+/** @addtogroup AHB_peripheral
+ * @{
+ */
+
+#define RCC_AHB_PERIPH_DMA ((uint32_t)0x00000001)
+#define RCC_AHB_PERIPH_SRAM ((uint32_t)0x00000004)
+#define RCC_AHB_PERIPH_FLITF ((uint32_t)0x00000010)
+#define RCC_AHB_PERIPH_CRC ((uint32_t)0x00000040)
+#define RCC_AHB_PERIPH_RNGC ((uint32_t)0x00000200)
+#define RCC_AHB_PERIPH_SAC ((uint32_t)0x00000800)
+#define RCC_AHB_PERIPH_ADC ((uint32_t)0x00001000)
+
+#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH)&0xFFFFE5AA) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @addtogroup APB2_peripheral
+ * @{
+ */
+
+#define RCC_APB2_PERIPH_AFIO ((uint32_t)0x00000001)
+#define RCC_APB2_PERIPH_GPIOA ((uint32_t)0x00000004)
+#define RCC_APB2_PERIPH_GPIOB ((uint32_t)0x00000008)
+#define RCC_APB2_PERIPH_GPIOC ((uint32_t)0x00000010)
+#define RCC_APB2_PERIPH_GPIOD ((uint32_t)0x00000020)
+#define RCC_APB2_PERIPH_TIM1 ((uint32_t)0x00000800)
+#define RCC_APB2_PERIPH_SPI1 ((uint32_t)0x00001000)
+#define RCC_APB2_PERIPH_TIM8 ((uint32_t)0x00002000)
+#define RCC_APB2_PERIPH_USART1 ((uint32_t)0x00004000)
+#define RCC_APB2_PERIPH_UART4 ((uint32_t)0x00020000)
+#define RCC_APB2_PERIPH_UART5 ((uint32_t)0x00040000)
+#define RCC_APB2_PERIPH_SPI2 ((uint32_t)0x00080000)
+
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH)&0xFFF187C2) == 0x00) && ((PERIPH) != 0x00))
+/**
+ * @}
+ */
+
+/** @addtogroup APB1_peripheral
+ * @{
+ */
+
+#define RCC_APB1_PERIPH_TIM2 ((uint32_t)0x00000001)
+#define RCC_APB1_PERIPH_TIM3 ((uint32_t)0x00000002)
+#define RCC_APB1_PERIPH_TIM4 ((uint32_t)0x00000004)
+#define RCC_APB1_PERIPH_TIM5 ((uint32_t)0x00000008)
+#define RCC_APB1_PERIPH_TIM6 ((uint32_t)0x00000010)
+#define RCC_APB1_PERIPH_TIM7 ((uint32_t)0x00000020)
+#define RCC_APB1_PERIPH_COMP ((uint32_t)0x00000040)
+#define RCC_APB1_PERIPH_COMP_FILT ((uint32_t)0x00000080)
+#define RCC_APB1_PERIPH_AFEC ((uint32_t)0x00000100)
+#define RCC_APB1_PERIPH_TIM9 ((uint32_t)0x00000200)
+#define RCC_APB1_PERIPH_TSC ((uint32_t)0x00000400)
+#define RCC_APB1_PERIPH_WWDG ((uint32_t)0x00000800)
+#define RCC_APB1_PERIPH_USART2 ((uint32_t)0x00020000)
+#define RCC_APB1_PERIPH_USART3 ((uint32_t)0x00040000)
+#define RCC_APB1_PERIPH_I2C1 ((uint32_t)0x00200000)
+#define RCC_APB1_PERIPH_I2C2 ((uint32_t)0x00400000)
+#define RCC_APB1_PERIPH_USB ((uint32_t)0x00800000)
+#define RCC_APB1_PERIPH_CAN ((uint32_t)0x02000000)
+#define RCC_APB1_PERIPH_PWR ((uint32_t)0x10000000)
+#define RCC_APB1_PERIPH_DAC ((uint32_t)0x20000000)
+#define RCC_APB1_PERIPH_OPAMP ((uint32_t)0x80000000)
+
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH)&0x4D19F000) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RET_peripheral
+ * @{
+ */
+
+#define RCC_RET_PERIPH_LPTIM ((uint32_t)0x00000040)
+#define RCC_RET_PERIPH_LPUART ((uint32_t)0x00000080)
+#define RCC_RET_PERIPH_LCD ((uint32_t)0x00000100)
+#define RCC_RET_PERIPH_LPRCNT ((uint32_t)0x00000200)
+
+#define IS_RCC_RET_PERIPH(PERIPH) ((((PERIPH)&0xFFFFFC3F) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPTIM
+ * @{
+ */
+#define RCC_LPTIMCLK_SRC_MASK ((uint32_t)0xFFFFFFF8)
+
+#define RCC_LPTIMCLK_SRC_APB1 ((uint32_t)0x00000000)
+#define RCC_LPTIMCLK_SRC_LSI ((uint32_t)0x00000001)
+#define RCC_LPTIMCLK_SRC_HSI ((uint32_t)0x00000002)
+#define RCC_LPTIMCLK_SRC_LSE ((uint32_t)0x00000003)
+#define RCC_LPTIMCLK_SRC_COMP1 ((uint32_t)0x00000004)
+#define RCC_LPTIMCLK_SRC_COMP2 ((uint32_t)0x00000005)
+
+#define IS_RCC_LPTIM_CLK(LPTIMCLK) (((LPTIMCLK) == RCC_LPTIMCLK_SRC_APB1) \
+ || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_LSI) \
+ || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_HSI) \
+ || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_LSE) \
+ || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_COMP1) \
+ || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_COMP2))
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART
+ * @{
+ */
+#define RCC_LPUARTCLK_SRC_MASK ((uint32_t)0xFFFFFFE7)
+
+#define RCC_LPUARTCLK_SRC_APB1 ((uint32_t)0x00000000)
+#define RCC_LPUARTCLK_SRC_SYSCLK ((uint32_t)0x00000008)
+#define RCC_LPUARTCLK_SRC_HSI ((uint32_t)0x00000010)
+#define RCC_LPUARTCLK_SRC_LSE ((uint32_t)0x00000018)
+
+#define IS_RCC_LPUART_CLK(LPUARTCLK) (((LPUARTCLK)&0xFFFFFFE7) == 0x00)
+
+/**
+ * @}
+ */
+
+/** @addtogroup SRAM_CTRLSTS
+ * @{
+ */
+
+#define SRAM1_PARITYERROR_INT ((uint32_t)0x00000001)
+#define SRAM2_PARITYERROR_INT ((uint32_t)0x00000008)
+#define IS_RCC_SRAMERRORINT(PARITYERROR_INT) (((PARITYERROR_INT) == SRAM1_PARITYERROR_INT) \
+ || ((PARITYERROR_INT) == SRAM2_PARITYERROR_INT))
+
+#define SRAM1_PARITYERROR_RESET ((uint32_t)0x00000002)
+#define SRAM2_PARITYERROR_RESET ((uint32_t)0x00000010)
+#define IS_RCC_SRAMERRORRESET(PARITYERROR_RESET) (((PARITYERROR_RESET) == SRAM1_PARITYERROR_RESET) \
+ || ((PARITYERROR_RESET) == SRAM2_PARITYERROR_RESET))
+
+#define SRAM1_PARITYERROR_FLAG ((uint32_t)0x00000004)
+#define SRAM2_PARITYERROR_FLAG ((uint32_t)0x00000020)
+#define IS_RCC_SRAMERRORFLAG(PARITYERROR_FLAG) (((PARITYERROR_FLAG) == SRAM1_PARITYERROR_FLAG) \
+ || ((PARITYERROR_FLAG) == SRAM2_PARITYERROR_FLAG))
+
+/**
+ * @}
+ */
+
+#define RCC_MCO_CLK_NUM0 ((uint32_t)0x00000000)
+#define RCC_MCO_CLK_NUM1 ((uint32_t)0x10000000)
+#define RCC_MCO_CLK_NUM2 ((uint32_t)0x20000000)
+#define RCC_MCO_CLK_NUM3 ((uint32_t)0x30000000)
+#define RCC_MCO_CLK_NUM4 ((uint32_t)0x40000000)
+#define RCC_MCO_CLK_NUM5 ((uint32_t)0x50000000)
+#define RCC_MCO_CLK_NUM6 ((uint32_t)0x60000000)
+#define RCC_MCO_CLK_NUM7 ((uint32_t)0x70000000)
+#define RCC_MCO_CLK_NUM8 ((uint32_t)0x80000000)
+#define RCC_MCO_CLK_NUM9 ((uint32_t)0x90000000)
+#define RCC_MCO_CLK_NUM10 ((uint32_t)0xA0000000)
+#define RCC_MCO_CLK_NUM11 ((uint32_t)0xB0000000)
+#define RCC_MCO_CLK_NUM12 ((uint32_t)0xC0000000)
+#define RCC_MCO_CLK_NUM13 ((uint32_t)0xD0000000)
+#define RCC_MCO_CLK_NUM14 ((uint32_t)0xE0000000)
+#define RCC_MCO_CLK_NUM15 ((uint32_t)0xF0000000)
+#define IS_RCC_MCOCLKPRE(NUM) \
+ (((NUM) == RCC_MCO_CLK_NUM0) || ((NUM) == RCC_MCO_CLK_NUM1) || ((NUM) == RCC_MCO_CLK_NUM2) \
+ || ((NUM) == RCC_MCO_CLK_NUM3) || ((NUM) == RCC_MCO_CLK_NUM4) || ((NUM) == RCC_MCO_CLK_NUM5) \
+ || ((NUM) == RCC_MCO_CLK_NUM6) || ((NUM) == RCC_MCO_CLK_NUM7) || ((NUM) == RCC_MCO_CLK_NUM8) \
+ || ((NUM) == RCC_MCO_CLK_NUM9) || ((NUM) == RCC_MCO_CLK_NUM10) || ((NUM) == RCC_MCO_CLK_NUM11) \
+ || ((NUM) == RCC_MCO_CLK_NUM12) || ((NUM) == RCC_MCO_CLK_NUM13) || ((NUM) == RCC_MCO_CLK_NUM14) \
+ || ((NUM) == RCC_MCO_CLK_NUM15))
+
+/** @addtogroup Clock_source_to_output_on_MCO_pin
+ * @{
+ */
+
+#define RCC_MCO_NOCLK ((uint8_t)0x00)
+#define RCC_MCO_LSI ((uint8_t)0x01)
+#define RCC_MCO_LSE ((uint8_t)0x02)
+#define RCC_MCO_MSI ((uint8_t)0x03)
+#define RCC_MCO_SYSCLK ((uint8_t)0x04)
+#define RCC_MCO_HSI ((uint8_t)0x05)
+#define RCC_MCO_HSE ((uint8_t)0x06)
+#define RCC_MCO_PLLCLK ((uint8_t)0x07)
+
+#define IS_RCC_MCO(MCO) \
+ (((MCO) == RCC_MCO_NOCLK) || ((MCO) == RCC_MCO_LSI) || ((MCO) == RCC_MCO_LSE) || ((MCO) == RCC_MCO_MSI) \
+ || ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSI) || ((MCO) == RCC_MCO_HSE) || ((MCO) == RCC_MCO_PLLCLK))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Flag
+ * @{
+ */
+#define RCC_CTRL_FLAG_HSIRDF ((uint8_t)0x21)
+#define RCC_CTRL_FLAG_HSERDF ((uint8_t)0x31)
+#define RCC_CTRL_FLAG_PLLRDF ((uint8_t)0x39)
+#define RCC_LDCTRL_FLAG_LSERD ((uint8_t)0x41)
+#define RCC_LDCTRL_FLAG_LSECLKSSF ((uint8_t)0x44)
+#define RCC_LDCTRL_FLAG_BORRSTF ((uint8_t)0x5C)
+#define RCC_LDCTRL_FLAG_LDEMCRSTF ((uint8_t)0x5E)
+#define RCC_CTRLSTS_FLAG_LSIRD ((uint8_t)0x61)
+#define RCC_CTRLSTS_FLAG_MSIRD ((uint8_t)0x63)
+#define RCC_CTRLSTS_FLAG_RAMRSTF ((uint8_t)0x77)
+#define RCC_CTRLSTS_FLAG_MMURSTF ((uint8_t)0x79)
+#define RCC_CTRLSTS_FLAG_PINRSTF ((uint8_t)0x7A)
+#define RCC_CTRLSTS_FLAG_PORRSTF ((uint8_t)0x7B)
+#define RCC_CTRLSTS_FLAG_SFTRSTF ((uint8_t)0x7C)
+#define RCC_CTRLSTS_FLAG_IWDGRSTF ((uint8_t)0x7D)
+#define RCC_CTRLSTS_FLAG_WWDGRSTF ((uint8_t)0x7E)
+#define RCC_CTRLSTS_FLAG_LPWRRSTF ((uint8_t)0x7F)
+
+#define IS_RCC_FLAG(FLAG) \
+ (((FLAG) == RCC_CTRL_FLAG_HSIRDF) || ((FLAG) == RCC_CTRL_FLAG_HSERDF) || ((FLAG) == RCC_CTRL_FLAG_PLLRDF) \
+ || ((FLAG) == RCC_LDCTRL_FLAG_LSERD) || ((FLAG) == RCC_LDCTRL_FLAG_LSECLKSSF) || ((FLAG) == RCC_LDCTRL_FLAG_BORRSTF) \
+ || ((FLAG) == RCC_LDCTRL_FLAG_LDEMCRSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_LSIRD) || ((FLAG) == RCC_CTRLSTS_FLAG_MSIRD) \
+ || ((FLAG) == RCC_CTRLSTS_FLAG_RAMRSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_MMURSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_PINRSTF) \
+ || ((FLAG) == RCC_CTRLSTS_FLAG_PORRSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_SFTRSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_IWDGRSTF) \
+ || ((FLAG) == RCC_CTRLSTS_FLAG_WWDGRSTF) || ((FLAG) == RCC_CTRLSTS_FLAG_LPWRRSTF))
+
+#define IS_RCC_CALIB_VALUE(VALUE) ((VALUE) <= 0x1F)
+#define IS_RCC_MSICALIB_VALUE(VALUE) ((VALUE) <= 0xFF)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Exported_Functions
+ * @{
+ */
+
+void RCC_DeInit(void);
+void RCC_ConfigHse(uint32_t RCC_HSE);
+ErrorStatus RCC_WaitHseStable(void);
+void RCC_ConfigHsi(uint32_t RCC_HSI);
+ErrorStatus RCC_WaitHsiStable(void);
+void RCC_SetHsiCalibValue(uint8_t HSICalibrationValue);
+void RCC_EnableHsi(FunctionalState Cmd);
+void RCC_ConfigMsi(uint32_t RCC_MSI, uint32_t RCC_MSI_Range);
+ErrorStatus RCC_WaitMsiStable(void);
+void RCC_SetMsiCalibValue(uint8_t MSICalibrationValue);
+void RCC_EnableMsi(FunctionalState Cmd);
+void RCC_ConfigPll(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul, uint32_t RCC_PLLDIVCLK);
+void RCC_EnablePll(FunctionalState Cmd);
+
+void RCC_ConfigSysclk(uint32_t RCC_SYSCLKSource);
+uint8_t RCC_GetSysclkSrc(void);
+void RCC_ConfigHclk(uint32_t RCC_SYSCLK);
+void RCC_ConfigPclk1(uint32_t RCC_HCLK);
+void RCC_ConfigPclk2(uint32_t RCC_HCLK);
+void RCC_ConfigInt(uint8_t RccInt, FunctionalState Cmd);
+
+void RCC_ConfigUsbClk(uint32_t RCC_USBCLKSource);
+
+void RCC_ConfigTim18Clk(uint32_t RCC_TIM18CLKSource);
+void RCC_ConfigRngcClk(uint32_t RCC_RNGCCLKPrescaler);
+
+void RCC_ConfigAdc1mClk(uint32_t RCC_ADC1MCLKSource, uint32_t RCC_ADC1MPrescaler);
+void RCC_ConfigAdcPllClk(uint32_t RCC_ADCPLLCLKPrescaler, FunctionalState Cmd);
+void RCC_ConfigAdcHclk(uint32_t RCC_ADCHCLKPrescaler);
+
+void RCC_ConfigTrng1mClk(uint32_t RCC_TRNG1MCLKSource, uint32_t RCC_TRNG1MPrescaler);
+void RCC_EnableTrng1mClk(FunctionalState Cmd);
+
+void RCC_ConfigUCDRClk(uint32_t RCC_UCDR300MSource, FunctionalState Cmd);
+
+void RCC_ConfigUSBXTALESSMode(uint32_t RCC_USBXTALESSMode);
+
+void RCC_EnableRETPeriphClk(uint32_t RCC_RETPeriph, FunctionalState Cmd);
+void RCC_EnableRETPeriphReset(uint32_t RCC_RETPeriph, FunctionalState Cmd);
+
+void RCC_ConfigLSXClk(uint32_t RCC_LSXCLKSource);
+uint32_t RCC_GetLSXClkSrc(void);
+
+void RCC_ConfigLPTIMClk(uint32_t RCC_LPTIMCLKSource);
+uint32_t RCC_GetLPTIMClkSrc(void);
+void RCC_ConfigLPUARTClk(uint32_t RCC_LPUARTCLKSource);
+uint32_t RCC_GetLPUARTClkSrc(void);
+
+void RCC_ConfigSRAMParityErrorInt(uint32_t SramInt, FunctionalState Cmd);
+void RCC_ConfigSRAMParityErrorRESET(uint32_t SramReset, FunctionalState Cmd);
+void RCC_ClrSRAMParityErrorFlag(uint32_t SramErrorflag);
+
+void RCC_ConfigLse(uint8_t RCC_LSE,uint16_t LSE_Trim);
+void RCC_EnableLsi(FunctionalState Cmd);
+void RCC_ConfigRtcClk(uint32_t RCC_RTCCLKSource);
+void RCC_EnableRtcClk(FunctionalState Cmd);
+uint32_t RCC_GetRTCClkSrc(void);
+void RCC_GetClocksFreqValue(RCC_ClocksType* RCC_Clocks);
+void RCC_EnableAHBPeriphClk(uint32_t RCC_AHBPeriph, FunctionalState Cmd);
+void RCC_EnableAPB2PeriphClk(uint32_t RCC_APB2Periph, FunctionalState Cmd);
+void RCC_EnableAPB1PeriphClk(uint32_t RCC_APB1Periph, FunctionalState Cmd);
+
+void RCC_EnableAHBPeriphReset(uint32_t RCC_AHBPeriph, FunctionalState Cmd);
+void RCC_EnableAPB2PeriphReset(uint32_t RCC_APB2Periph, FunctionalState Cmd);
+void RCC_EnableAPB1PeriphReset(uint32_t RCC_APB1Periph, FunctionalState Cmd);
+void RCC_EnableLowPowerReset(FunctionalState Cmd);
+void RCC_EnableClockSecuritySystem(FunctionalState Cmd);
+void RCC_EnableLSEClockSecuritySystem(FunctionalState Cmd);
+FlagStatus RCC_GetLSEClockSecuritySystemStatus(void);
+void RCC_ConfigMcoClkPre(uint32_t RCC_MCOCLKPrescaler);
+void RCC_ConfigMco(uint8_t RCC_MCO);
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
+void RCC_ClrFlag(void);
+INTStatus RCC_GetIntStatus(uint8_t RccInt);
+void RCC_ClrIntPendingBit(uint32_t RccClrInt);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32L43X_RCC_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_rtc.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_rtc.h
new file mode 100644
index 0000000000..4f0f79fe1c
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_rtc.h
@@ -0,0 +1,789 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_rtc.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L43X_RTC_H__
+#define __N32L43X_RTC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l43x.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RTC
+ * @{
+ */
+
+/**
+ * @brief RTC Init structures definition
+ */
+typedef struct
+{
+ uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format.
+ This parameter can be a value of @ref RTC_Hour_Formats */
+
+ uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
+ This parameter must be set to a value lower than 0x7F */
+
+ uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
+ This parameter must be set to a value lower than 0x7FFF */
+} RTC_InitType;
+
+/**
+ * @brief RTC Time structure definition
+ */
+typedef struct
+{
+ uint8_t Hours; /*!< Specifies the RTC Time Hour.
+ This parameter must be set to a value in the 0-12 range
+ if the RTC_12HOUR_FORMAT is selected or 0-23 range if
+ the RTC_24HOUR_FORMAT is selected. */
+
+ uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
+ This parameter must be set to a value in the 0-59 range. */
+
+ uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
+ This parameter must be set to a value in the 0-59 range. */
+
+ uint8_t H12; /*!< Specifies the RTC AM/PM Time.
+ This parameter can be a value of @ref RTC_AM_PM_Definitions */
+} RTC_TimeType;
+
+/**
+ * @brief RTC Date structure definition
+ */
+typedef struct
+{
+ uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
+ This parameter can be a value of @ref RTC_WeekDay_Definitions */
+
+ uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
+ This parameter can be a value of @ref RTC_Month_Date_Definitions */
+
+ uint8_t Date; /*!< Specifies the RTC Date.
+ This parameter must be set to a value in the 1-31 range. */
+
+ uint8_t Year; /*!< Specifies the RTC Date Year.
+ This parameter must be set to a value in the 0-99 range. */
+} RTC_DateType;
+
+/**
+ * @brief RTC Alarm structure definition
+ */
+typedef struct
+{
+ RTC_TimeType AlarmTime; /*!< Specifies the RTC Alarm Time members. */
+
+ uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
+ This parameter can be a value of @ref RTC_AlarmMask_Definitions */
+
+ uint32_t DateWeekMode; /*!< Specifies the RTC Alarm is on Date or WeekDay.
+ This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
+
+ uint8_t DateWeekValue; /*!< Specifies the RTC Alarm Date/WeekDay.
+ If the Alarm Date is selected, this parameter
+ must be set to a value in the 1-31 range.
+ If the Alarm WeekDay is selected, this
+ parameter can be a value of @ref RTC_WeekDay_Definitions */
+} RTC_AlarmType;
+
+/** @addtogroup RTC_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup RTC_Hour_Formats
+ * @{
+ */
+#define RTC_24HOUR_FORMAT ((uint32_t)0x00000000)
+#define RTC_12HOUR_FORMAT ((uint32_t)0x00000040)
+#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_12HOUR_FORMAT) || ((FORMAT) == RTC_24HOUR_FORMAT))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Asynchronous_Predivider
+ * @{
+ */
+#define IS_RTC_PREDIV_ASYNCH(PREDIV) ((PREDIV) <= 0x7F)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Synchronous_Predivider
+ * @{
+ */
+#define IS_RTC_PREDIV_SYNCH(PREDIV) ((PREDIV) <= 0x7FFF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Time_Definitions
+ * @{
+ */
+#define IS_RTC_12HOUR(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))
+#define IS_RTC_24HOUR(HOUR) ((HOUR) <= 23)
+#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)
+#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_AM_PM_Definitions
+ * @{
+ */
+#define RTC_AM_H12 ((uint8_t)0x00)
+#define RTC_PM_H12 ((uint8_t)0x40)
+#define IS_RTC_H12(PM) (((PM) == RTC_AM_H12) || ((PM) == RTC_PM_H12))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Year_Date_Definitions
+ * @{
+ */
+#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Month_Date_Definitions
+ * @{
+ */
+
+/* Coded in BCD format */
+#define RTC_MONTH_JANUARY ((uint8_t)0x01)
+#define RTC_MONTH_FEBRURY ((uint8_t)0x02)
+#define RTC_MONTH_MARCH ((uint8_t)0x03)
+#define RTC_MONTH_APRIL ((uint8_t)0x04)
+#define RTC_MONTH_MAY ((uint8_t)0x05)
+#define RTC_MONTH_JUNE ((uint8_t)0x06)
+#define RTC_MONTH_JULY ((uint8_t)0x07)
+#define RTC_MONTH_AUGUST ((uint8_t)0x08)
+#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
+#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
+#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
+#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
+#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))
+#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_WeekDay_Definitions
+ * @{
+ */
+
+#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
+#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
+#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
+#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
+#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
+#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
+#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
+#define IS_RTC_WEEKDAY(WEEKDAY) \
+ (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) \
+ || ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) \
+ || ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Alarm_Definitions
+ * @{
+ */
+#define IS_RTC_ALARM_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
+#define IS_RTC_ALARM_WEEKDAY_WEEKDAY(WEEKDAY) \
+ (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) \
+ || ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) \
+ || ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_AlarmDateWeekDay_Definitions
+ * @{
+ */
+#define RTC_ALARM_SEL_WEEKDAY_DATE ((uint32_t)0x00000000)
+#define RTC_ALARM_SEL_WEEKDAY_WEEKDAY ((uint32_t)0x40000000)
+
+#define IS_RTC_ALARM_WEEKDAY_SEL(SEL) \
+ (((SEL) == RTC_ALARM_SEL_WEEKDAY_DATE) || ((SEL) == RTC_ALARM_SEL_WEEKDAY_WEEKDAY))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_AlarmMask_Definitions
+ * @{
+ */
+#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000)
+#define RTC_ALARMMASK_WEEKDAY ((uint32_t)0x80000000)
+#define RTC_ALARMMASK_HOURS ((uint32_t)0x00800000)
+#define RTC_ALARMMASK_MINUTES ((uint32_t)0x00008000)
+#define RTC_ALARMMASK_SECONDS ((uint32_t)0x00000080)
+#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080)
+#define IS_ALARM_MASK(INTEN) (((INTEN)&0x7F7F7F7F) == (uint32_t)RESET)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Alarms_Definitions
+ * @{
+ */
+#define RTC_A_ALARM ((uint32_t)0x00000100)
+#define RTC_B_ALARM ((uint32_t)0x00000200)
+#define IS_RTC_ALARM_SEL(ALARM) (((ALARM) == RTC_A_ALARM) || ((ALARM) == RTC_B_ALARM))
+#define IS_RTC_ALARM_ENABLE(ALARM) (((ALARM) & (RTC_A_ALARM | RTC_B_ALARM)) != (uint32_t)RESET)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Alarm_Sub_Seconds_Masks_Definitions
+ * @{
+ */
+#define RTC_SUBS_MASK_ALL \
+ ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. \
+ There is no comparison on sub seconds \
+ for Alarm */
+#define RTC_SUBS_MASK_SS14_1 \
+ ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm \
+ comparison. Only SS[0] is compared. */
+#define RTC_SUBS_MASK_SS14_2 \
+ ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm \
+ comparison. Only SS[1:0] are compared */
+#define RTC_SUBS_MASK_SS14_3 \
+ ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm \
+ comparison. Only SS[2:0] are compared */
+#define RTC_SUBS_MASK_SS14_4 \
+ ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm \
+ comparison. Only SS[3:0] are compared */
+#define RTC_SUBS_MASK_SS14_5 \
+ ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm \
+ comparison. Only SS[4:0] are compared */
+#define RTC_SUBS_MASK_SS14_6 \
+ ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm \
+ comparison. Only SS[5:0] are compared */
+#define RTC_SUBS_MASK_SS14_7 \
+ ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm \
+ comparison. Only SS[6:0] are compared */
+#define RTC_SUBS_MASK_SS14_8 \
+ ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm \
+ comparison. Only SS[7:0] are compared */
+#define RTC_SUBS_MASK_SS14_9 \
+ ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm \
+ comparison. Only SS[8:0] are compared */
+#define RTC_SUBS_MASK_SS14_10 \
+ ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm \
+ comparison. Only SS[9:0] are compared */
+#define RTC_SUBS_MASK_SS14_11 \
+ ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm \
+ comparison. Only SS[10:0] are compared */
+#define RTC_SUBS_MASK_SS14_12 \
+ ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm \
+ comparison.Only SS[11:0] are compared */
+#define RTC_SUBS_MASK_SS14_13 \
+ ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm \
+ comparison. Only SS[12:0] are compared */
+#define RTC_SUBS_MASK_SS14_14 \
+ ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm \
+ comparison.Only SS[13:0] are compared */
+#define RTC_SUBS_MASK_NONE \
+ ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match \
+ to activate alarm. */
+#define IS_RTC_ALARM_SUB_SECOND_MASK_MODE(INTEN) \
+ (((INTEN) == RTC_SUBS_MASK_ALL) || ((INTEN) == RTC_SUBS_MASK_SS14_1) || ((INTEN) == RTC_SUBS_MASK_SS14_2) \
+ || ((INTEN) == RTC_SUBS_MASK_SS14_3) || ((INTEN) == RTC_SUBS_MASK_SS14_4) || ((INTEN) == RTC_SUBS_MASK_SS14_5) \
+ || ((INTEN) == RTC_SUBS_MASK_SS14_6) || ((INTEN) == RTC_SUBS_MASK_SS14_7) || ((INTEN) == RTC_SUBS_MASK_SS14_8) \
+ || ((INTEN) == RTC_SUBS_MASK_SS14_9) || ((INTEN) == RTC_SUBS_MASK_SS14_10) || ((INTEN) == RTC_SUBS_MASK_SS14_11) \
+ || ((INTEN) == RTC_SUBS_MASK_SS14_12) || ((INTEN) == RTC_SUBS_MASK_SS14_13) || ((INTEN) == RTC_SUBS_MASK_SS14_14) \
+ || ((INTEN) == RTC_SUBS_MASK_NONE))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Alarm_Sub_Seconds_Value
+ * @{
+ */
+
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Wakeup_Timer_Definitions
+ * @{
+ */
+#define RTC_WKUPCLK_RTCCLK_DIV16 ((uint32_t)0x00000000)
+#define RTC_WKUPCLK_RTCCLK_DIV8 ((uint32_t)0x00000001)
+#define RTC_WKUPCLK_RTCCLK_DIV4 ((uint32_t)0x00000002)
+#define RTC_WKUPCLK_RTCCLK_DIV2 ((uint32_t)0x00000003)
+#define RTC_WKUPCLK_CK_SPRE_16BITS ((uint32_t)0x00000004)
+#define RTC_WKUPCLK_CK_SPRE_17BITS ((uint32_t)0x00000006)
+#define IS_RTC_WKUP_CLOCK(CLOCK) \
+ (((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV16) || ((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV8) \
+ || ((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV4) || ((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV2) \
+ || ((CLOCK) == RTC_WKUPCLK_CK_SPRE_16BITS) || ((CLOCK) == RTC_WKUPCLK_CK_SPRE_17BITS))
+#define IS_RTC_WKUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Time_Stamp_Edges_definitions
+ * @{
+ */
+#define RTC_TIMESTAMP_EDGE_RISING ((uint32_t)0x00000000)
+#define RTC_TIMESTAMP_EDGE_FALLING ((uint32_t)0x00000008)
+#define IS_RTC_TIMESTAMP_EDGE_MODE(EDGE) \
+ (((EDGE) == RTC_TIMESTAMP_EDGE_RISING) || ((EDGE) == RTC_TIMESTAMP_EDGE_FALLING))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Output_selection_Definitions
+ * @{
+ */
+#define RTC_OUTPUT_DIS ((uint32_t)0x00000000)
+#define RTC_OUTPUT_ALA ((uint32_t)0x00200000)
+#define RTC_OUTPUT_ALB ((uint32_t)0x00400000)
+#define RTC_OUTPUT_WKUP ((uint32_t)0x00600000)
+
+#define IS_RTC_OUTPUT_MODE(OUTPUT) \
+ (((OUTPUT) == RTC_OUTPUT_DIS) || ((OUTPUT) == RTC_OUTPUT_ALA) || ((OUTPUT) == RTC_OUTPUT_ALB) \
+ || ((OUTPUT) == RTC_OUTPUT_WKUP))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Output_Polarity_Definitions
+ * @{
+ */
+#define RTC_OUTPOL_HIGH ((uint32_t)0x00000000)
+#define RTC_OUTPOL_LOW ((uint32_t)0x00100000)
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPOL_HIGH) || ((POL) == RTC_OUTPOL_LOW))
+/**
+ * @}
+ */
+
+
+/** @addtogroup RTC_Calib_Output_selection_Definitions
+ * @{
+ */
+#define RTC_CALIB_OUTPUT_256HZ ((uint32_t)0x00000000)
+#define RTC_CALIB_OUTPUT_1HZ ((uint32_t)0x00080000)
+#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIB_OUTPUT_256HZ) || ((OUTPUT) == RTC_CALIB_OUTPUT_1HZ))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Smooth_calib_period_Definitions
+ * @{
+ */
+#define SMOOTH_CALIB_32SEC \
+ ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \
+ period is 32s, else 2exp20 RTCCLK seconds */
+#define SMOOTH_CALIB_16SEC \
+ ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \
+ period is 16s, else 2exp19 RTCCLK seconds */
+#define SMOOTH_CALIB_8SEC \
+ ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \
+ period is 8s, else 2exp18 RTCCLK seconds */
+#define IS_RTC_SMOOTH_CALIB_PERIOD_SEL(PERIOD) \
+ (((PERIOD) == SMOOTH_CALIB_32SEC) || ((PERIOD) == SMOOTH_CALIB_16SEC) || ((PERIOD) == SMOOTH_CALIB_8SEC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Smooth_calib_Plus_pulses_Definitions
+ * @{
+ */
+#define RTC_SMOOTH_CALIB_PLUS_PULSES_SET \
+ ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added \
+ during a X -second window = Y - CALM[8:0]. \
+ with Y = 512, 256, 128 when X = 32, 16, 8 */
+#define RTC_SMOOTH_CALIB_PLUS_PULSES__RESET \
+ ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited \
+ during a 32-second window = CALM[8:0]. */
+#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) \
+ (((PLUS) == RTC_SMOOTH_CALIB_PLUS_PULSES_SET) || ((PLUS) == RTC_SMOOTH_CALIB_PLUS_PULSES__RESET))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Smooth_calib_Minus_pulses_Definitions
+ * @{
+ */
+#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_DayLightSaving_Definitions
+ * @{
+ */
+#define RTC_DAYLIGHT_SAVING_SUB1H ((uint32_t)0x00020000)
+#define RTC_DAYLIGHT_SAVING_ADD1H ((uint32_t)0x00010000)
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHT_SAVING_SUB1H) || ((SAVE) == RTC_DAYLIGHT_SAVING_ADD1H))
+
+#define RTC_STORE_OPERATION_RESET ((uint32_t)0x00000000)
+#define RTC_STORE_OPERATION_SET ((uint32_t)0x00040000)
+#define IS_RTC_STORE_OPERATION(OPERATION) \
+ (((OPERATION) == RTC_STORE_OPERATION_RESET) || ((OPERATION) == RTC_STORE_OPERATION_SET))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Output_Type_ALARM_OUT
+ * @{
+ */
+#define RTC_OUTPUT_OPENDRAIN ((uint32_t)0x00000000)
+#define RTC_OUTPUT_PUSHPULL ((uint32_t)0x00000001)
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_OPENDRAIN) || ((TYPE) == RTC_OUTPUT_PUSHPULL))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Add_1_Second_Parameter_Definitions
+ * @{
+ */
+#define RTC_SHIFT_ADD1S_DISABLE ((uint32_t)0x00000000)
+#define RTC_SHIFT_ADD1S_ENABLE ((uint32_t)0x80000000)
+#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFT_ADD1S_DISABLE) || ((SEL) == RTC_SHIFT_ADD1S_ENABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Substract_Fraction_Of_Second_Value
+ * @{
+ */
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Input_parameter_format_definitions
+ * @{
+ */
+#define RTC_FORMAT_BIN ((uint32_t)0x000000000)
+#define RTC_FORMAT_BCD ((uint32_t)0x000000001)
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Flags_Definitions
+ * @{
+ */
+#define RTC_FLAG_RECPF ((uint32_t)0x00010000)
+#define RTC_FLAG_TAMP3F ((uint32_t)0x00008000)
+#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000)
+#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)
+#define RTC_FLAG_TISOVF ((uint32_t)0x00001000)
+#define RTC_FLAG_TISF ((uint32_t)0x00000800)
+#define RTC_FLAG_WTF ((uint32_t)0x00000400)
+#define RTC_FLAG_ALBF ((uint32_t)0x00000200)
+#define RTC_FLAG_ALAF ((uint32_t)0x00000100)
+#define RTC_FLAG_INITF ((uint32_t)0x00000040)
+#define RTC_FLAG_RSYF ((uint32_t)0x00000020)
+#define RTC_FLAG_INITSF ((uint32_t)0x00000010)
+#define RTC_FLAG_SHOPF ((uint32_t)0x00000008)
+#define RTC_FLAG_WTWF ((uint32_t)0x00000004)
+#define RTC_FLAG_ALBWF ((uint32_t)0x00000002)
+#define RTC_FLAG_ALAWF ((uint32_t)0x00000001)
+#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RECPF) || ((FLAG) == RTC_FLAG_TAMP3F) || \
+ ((FLAG) == RTC_FLAG_TAMP2F) || ((FLAG) == RTC_FLAG_TAMP1F) || \
+ ((FLAG) == RTC_FLAG_TISOVF) || ((FLAG) == RTC_FLAG_TISF) || \
+ ((FLAG) == RTC_FLAG_WTF) || ((FLAG) == RTC_FLAG_ALBF) || \
+ ((FLAG) == RTC_FLAG_ALAF) || ((FLAG) == RTC_FLAG_INITF) || \
+ ((FLAG) == RTC_FLAG_RSYF) || ((FLAG) == RTC_FLAG_INITSF) || \
+ ((FLAG) == RTC_FLAG_SHOPF) || ((FLAG) == RTC_FLAG_WTWF) || \
+ ((FLAG) == RTC_FLAG_ALBWF)|| ((FLAG) == RTC_FLAG_ALAWF))
+#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Interrupts_Definitions
+ * @{
+ */
+#define RTC_INT_TAMP3 ((uint32_t)0x00080000)
+#define RTC_INT_TAMP2 ((uint32_t)0x00040000)
+#define RTC_INT_TAMP1 ((uint32_t)0x00020000)
+#define RTC_INT_TS ((uint32_t)0x00008000)
+#define RTC_INT_WUT ((uint32_t)0x00004000)
+#define RTC_INT_ALRB ((uint32_t)0x00002000)
+#define RTC_INT_ALRA ((uint32_t)0x00001000)
+
+#define IS_RTC_CONFIG_INT(IT) (((IT) != (uint32_t)RESET) && (((IT)&0xFFFF0FFB) == (uint32_t)RESET))
+#define IS_RTC_GET_INT(IT) \
+ (((IT) == RTC_INT_TAMP3) ||((IT) == RTC_INT_TAMP2) ||((IT) == RTC_INT_TAMP1) ||((IT) == RTC_INT_TS) || ((IT) == RTC_INT_WUT) || ((IT) == RTC_INT_ALRB) || ((IT) == RTC_INT_ALRA))
+#define IS_RTC_CLEAR_INT(IT) (((IT) != (uint32_t)RESET) && (((IT)&0xFFF10FFF) == (uint32_t)RESET))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Legacy
+ * @{
+ */
+#define RTC_DigitalCalibConfig RTC_CoarseCalibConfig
+#define RTC_DigitalCalibCmd RTC_CoarseCalibCmd
+/** @defgroup RTC_Tamper_Trigger_Definitions
+ * @{
+ */
+#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000)
+#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000002)
+#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000)
+#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000002)
+#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
+ ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
+ ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
+ ((TRIGGER) == RTC_TamperTrigger_HighLevel))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Tamper_Filter_Definitions
+ * @{
+ */
+#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
+
+#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2
+ consecutive samples at the active level */
+#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4
+ consecutive samples at the active level */
+#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8
+ consecutive samples at the active leve. */
+
+#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \
+ ((FILTER) == RTC_TamperFilter_2Sample) || \
+ ((FILTER) == RTC_TamperFilter_4Sample) || \
+ ((FILTER) == RTC_TamperFilter_8Sample))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions
+ * @{
+ */
+#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 32768 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 16384 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 8192 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 4096 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 2048 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 1024 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 512 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 256 */
+#define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700) /* Clear TAMPFREQ[2:0] bits in the RTC_TAMPCR register */
+
+#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
+
+/**
+ * @}
+ */
+
+ /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions
+ * @{
+ */
+#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before
+ sampling during 1 RTCCLK cycle */
+#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before
+ sampling during 2 RTCCLK cycles */
+#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before
+ sampling during 4 RTCCLK cycles */
+#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before
+ sampling during 8 RTCCLK cycles */
+#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
+ ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
+ ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
+ ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Tamper_Pins_Definitions
+ * @{
+ */
+#define RTC_TAMPER_1 RTC_TMPCFG_TP1EN /*!< Tamper detection enable for
+ input tamper 1 */
+#define RTC_TAMPER_2 RTC_TMPCFG_TP2EN /*!< Tamper detection enable for
+ input tamper 2 */
+#define RTC_TAMPER_3 RTC_TMPCFG_TP3EN /*!< Tamper detection enable for
+ input tamper 3 */
+#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
+
+
+#define RTC_TAMPER1_INT RTC_TMPCFG_TP1INTEN /*!< Tamper detection interruput enable */
+#define RTC_TAMPER2_INT RTC_TMPCFG_TP2INTEN /*!< Tamper detection interruput enable */
+#define RTC_TAMPER3_INT RTC_TMPCFG_TP3INTEN /*!< Tamper detection interruput enable */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Function used to set the RTC configuration to the default reset state *****/
+ErrorStatus RTC_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+ErrorStatus RTC_Init(RTC_InitType* RTC_InitStruct);
+void RTC_StructInit(RTC_InitType* RTC_InitStruct);
+void RTC_EnableWriteProtection(FunctionalState Cmd);
+ErrorStatus RTC_EnterInitMode(void);
+void RTC_ExitInitMode(void);
+ErrorStatus RTC_WaitForSynchro(void);
+ErrorStatus RTC_EnableRefClock(FunctionalState Cmd);
+void RTC_EnableBypassShadow(FunctionalState Cmd);
+
+/* Time and Date configuration functions **************************************/
+ErrorStatus RTC_ConfigTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct);
+void RTC_TimeStructInit(RTC_TimeType* RTC_TimeStruct);
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct);
+uint32_t RTC_GetSubSecond(void);
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct);
+void RTC_DateStructInit(RTC_DateType* RTC_DateStruct);
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct);
+
+/* Alarms (Alarm A and Alarm B) configuration functions **********************/
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct);
+void RTC_AlarmStructInit(RTC_AlarmType* RTC_AlarmStruct);
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct);
+ErrorStatus RTC_EnableAlarm(uint32_t RTC_Alarm, FunctionalState Cmd);
+void RTC_ConfigAlarmSubSecond(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask);
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
+
+/* WakeUp Timer configuration functions ***************************************/
+void RTC_ConfigWakeUpClock(uint32_t RTC_WakeUpClock);
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);
+uint32_t RTC_GetWakeUpCounter(void);
+ErrorStatus RTC_EnableWakeUp(FunctionalState Cmd);
+
+/* Daylight Saving configuration functions ************************************/
+void RTC_ConfigDayLightSaving(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
+uint32_t RTC_GetStoreOperation(void);
+
+/* Output pin Configuration function ******************************************/
+void RTC_ConfigOutput(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
+
+/* Coarse and Smooth Calibration configuration functions **********************/
+void RTC_EnableCalibOutput(FunctionalState Cmd);
+void RTC_ConfigCalibOutput(uint32_t RTC_CalibOutput);
+ErrorStatus RTC_ConfigSmoothCalib(uint32_t RTC_SmoothCalibPeriod,
+ uint32_t RTC_SmoothCalibPlusPulses,
+ uint32_t RTC_SmouthCalibMinusPulsesValue);
+
+/* TimeStamp configuration functions ******************************************/
+void RTC_EnableTimeStamp(uint32_t RTC_TimeStampEdge, FunctionalState Cmd);
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeType* RTC_StampTimeStruct, RTC_DateType* RTC_StampDateStruct);
+uint32_t RTC_GetTimeStampSubSecond(void);
+
+/* Output Type Config configuration functions *********************************/
+void RTC_ConfigOutputType(uint32_t RTC_OutputType);
+
+/* RTC_Shift_control_synchonisation_functions *********************************/
+ErrorStatus RTC_ConfigSynchroShift(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);
+
+/* Interrupts and flags management functions **********************************/
+void RTC_ConfigInt(uint32_t RTC_INT, FunctionalState Cmd);
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
+void RTC_ClrFlag(uint32_t RTC_FLAG);
+INTStatus RTC_GetITStatus(uint32_t RTC_INT);
+void RTC_ClrIntPendingBit(uint32_t RTC_INT);
+
+/* WakeUp TSC function **********************************/
+void RTC_EnableWakeUpTsc(uint32_t count);
+
+/* Tampers configuration functions ********************************************/
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);
+void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);
+void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);
+void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);
+void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
+void RTC_TamperPullUpCmd(FunctionalState NewState);
+void RTC_TamperIECmd(uint32_t TAMPxIE, FunctionalState NewState);
+void RTC_TamperTAMPTSCmd(FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32L43X_RTC_H__ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_spi.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_spi.h
new file mode 100644
index 0000000000..78fe70eb5d
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_spi.h
@@ -0,0 +1,470 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_spi.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L43X_SPI_H__
+#define __N32L43X_SPI_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l43x.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @{
+ */
+
+/** @addtogroup SPI_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief SPI Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t DataDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
+ This parameter can be a value of @ref SPI_data_direction */
+
+ uint16_t SpiMode; /*!< Specifies the SPI operating mode.
+ This parameter can be a value of @ref SPI_mode */
+
+ uint16_t DataLen; /*!< Specifies the SPI data size.
+ This parameter can be a value of @ref SPI_data_size */
+
+ uint16_t CLKPOL; /*!< Specifies the serial clock steady state.
+ This parameter can be a value of @ref SPI_Clock_Polarity */
+
+ uint16_t CLKPHA; /*!< Specifies the clock active edge for the bit capture.
+ This parameter can be a value of @ref SPI_Clock_Phase */
+
+ uint16_t NSS; /*!< Specifies whether the NSS signal is managed by
+ hardware (NSS pin) or by software using the SSI bit.
+ This parameter can be a value of @ref SPI_Slave_Select_management */
+
+ uint16_t BaudRatePres; /*!< Specifies the Baud Rate prescaler value which will be
+ used to configure the transmit and receive SCK clock.
+ This parameter can be a value of @ref SPI_BaudRate_Prescaler.
+ @note The communication clock is derived from the master
+ clock. The slave clock does not need to be set. */
+
+ uint16_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+ uint16_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. */
+} SPI_InitType;
+
+/**
+ * @brief I2S Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t I2sMode; /*!< Specifies the I2S operating mode.
+ This parameter can be a value of @ref I2sMode */
+
+ uint16_t Standard; /*!< Specifies the standard used for the I2S communication.
+ This parameter can be a value of @ref Standard */
+
+ uint16_t DataFormat; /*!< Specifies the data format for the I2S communication.
+ This parameter can be a value of @ref I2S_Data_Format */
+
+ uint16_t MCLKEnable; /*!< Specifies whether the I2S MCLK output is enabled or not.
+ This parameter can be a value of @ref I2S_MCLK_Output */
+
+ uint32_t AudioFrequency; /*!< Specifies the frequency selected for the I2S communication.
+ This parameter can be a value of @ref I2S_Audio_Frequency */
+
+ uint16_t CLKPOL; /*!< Specifies the idle state of the I2S clock.
+ This parameter can be a value of @ref I2S_Clock_Polarity */
+} I2S_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Exported_Constants
+ * @{
+ */
+
+#define IS_SPI_PERIPH(PERIPH) (((PERIPH) == SPI1) || ((PERIPH) == SPI2))
+
+
+/** @addtogroup SPI_data_direction
+ * @{
+ */
+
+#define SPI_DIR_DOUBLELINE_FULLDUPLEX ((uint16_t)0x0000)
+#define SPI_DIR_DOUBLELINE_RONLY ((uint16_t)0x0400)
+#define SPI_DIR_SINGLELINE_RX ((uint16_t)0x8000)
+#define SPI_DIR_SINGLELINE_TX ((uint16_t)0xC000)
+#define IS_SPI_DIR_MODE(MODE) \
+ (((MODE) == SPI_DIR_DOUBLELINE_FULLDUPLEX) || ((MODE) == SPI_DIR_DOUBLELINE_RONLY) \
+ || ((MODE) == SPI_DIR_SINGLELINE_RX) || ((MODE) == SPI_DIR_SINGLELINE_TX))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_mode
+ * @{
+ */
+
+#define SPI_MODE_MASTER ((uint16_t)0x0104)
+#define SPI_MODE_SLAVE ((uint16_t)0x0000)
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_MASTER) || ((MODE) == SPI_MODE_SLAVE))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_data_size
+ * @{
+ */
+
+#define SPI_DATA_SIZE_16BITS ((uint16_t)0x0800)
+#define SPI_DATA_SIZE_8BITS ((uint16_t)0x0000)
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATA_SIZE_16BITS) || ((DATASIZE) == SPI_DATA_SIZE_8BITS))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Clock_Polarity
+ * @{
+ */
+
+#define SPI_CLKPOL_LOW ((uint16_t)0x0000)
+#define SPI_CLKPOL_HIGH ((uint16_t)0x0002)
+#define IS_SPI_CLKPOL(CPOL) (((CPOL) == SPI_CLKPOL_LOW) || ((CPOL) == SPI_CLKPOL_HIGH))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Clock_Phase
+ * @{
+ */
+
+#define SPI_CLKPHA_FIRST_EDGE ((uint16_t)0x0000)
+#define SPI_CLKPHA_SECOND_EDGE ((uint16_t)0x0001)
+#define IS_SPI_CLKPHA(CPHA) (((CPHA) == SPI_CLKPHA_FIRST_EDGE) || ((CPHA) == SPI_CLKPHA_SECOND_EDGE))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Slave_Select_management
+ * @{
+ */
+
+#define SPI_NSS_SOFT ((uint16_t)0x0200)
+#define SPI_NSS_HARD ((uint16_t)0x0000)
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || ((NSS) == SPI_NSS_HARD))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_BaudRate_Prescaler
+ * @{
+ */
+
+#define SPI_BR_PRESCALER_2 ((uint16_t)0x0000)
+#define SPI_BR_PRESCALER_4 ((uint16_t)0x0008)
+#define SPI_BR_PRESCALER_8 ((uint16_t)0x0010)
+#define SPI_BR_PRESCALER_16 ((uint16_t)0x0018)
+#define SPI_BR_PRESCALER_32 ((uint16_t)0x0020)
+#define SPI_BR_PRESCALER_64 ((uint16_t)0x0028)
+#define SPI_BR_PRESCALER_128 ((uint16_t)0x0030)
+#define SPI_BR_PRESCALER_256 ((uint16_t)0x0038)
+#define IS_SPI_BR_PRESCALER(PRESCALER) \
+ (((PRESCALER) == SPI_BR_PRESCALER_2) || ((PRESCALER) == SPI_BR_PRESCALER_4) || ((PRESCALER) == SPI_BR_PRESCALER_8) \
+ || ((PRESCALER) == SPI_BR_PRESCALER_16) || ((PRESCALER) == SPI_BR_PRESCALER_32) \
+ || ((PRESCALER) == SPI_BR_PRESCALER_64) || ((PRESCALER) == SPI_BR_PRESCALER_128) \
+ || ((PRESCALER) == SPI_BR_PRESCALER_256))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_MSB_LSB_transmission
+ * @{
+ */
+
+#define SPI_FB_MSB ((uint16_t)0x0000)
+#define SPI_FB_LSB ((uint16_t)0x0080)
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FB_MSB) || ((BIT) == SPI_FB_LSB))
+/**
+ * @}
+ */
+
+/** @addtogroup I2sMode
+ * @{
+ */
+
+#define I2S_MODE_SlAVE_TX ((uint16_t)0x0000)
+#define I2S_MODE_SlAVE_RX ((uint16_t)0x0100)
+#define I2S_MODE_MASTER_TX ((uint16_t)0x0200)
+#define I2S_MODE_MASTER_RX ((uint16_t)0x0300)
+#define IS_I2S_MODE(MODE) \
+ (((MODE) == I2S_MODE_SlAVE_TX) || ((MODE) == I2S_MODE_SlAVE_RX) || ((MODE) == I2S_MODE_MASTER_TX) \
+ || ((MODE) == I2S_MODE_MASTER_RX))
+/**
+ * @}
+ */
+
+/** @addtogroup Standard
+ * @{
+ */
+
+#define I2S_STD_PHILLIPS ((uint16_t)0x0000)
+#define I2S_STD_MSB_ALIGN ((uint16_t)0x0010)
+#define I2S_STD_LSB_ALIGN ((uint16_t)0x0020)
+#define I2S_STD_PCM_SHORTFRAME ((uint16_t)0x0030)
+#define I2S_STD_PCM_LONGFRAME ((uint16_t)0x00B0)
+#define IS_I2S_STANDARD(STANDARD) \
+ (((STANDARD) == I2S_STD_PHILLIPS) || ((STANDARD) == I2S_STD_MSB_ALIGN) || ((STANDARD) == I2S_STD_LSB_ALIGN) \
+ || ((STANDARD) == I2S_STD_PCM_SHORTFRAME) || ((STANDARD) == I2S_STD_PCM_LONGFRAME))
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Data_Format
+ * @{
+ */
+
+#define I2S_DATA_FMT_16BITS ((uint16_t)0x0000)
+#define I2S_DATA_FMT_16BITS_EXTENDED ((uint16_t)0x0001)
+#define I2S_DATA_FMT_24BITS ((uint16_t)0x0003)
+#define I2S_DATA_FMT_32BITS ((uint16_t)0x0005)
+#define IS_I2S_DATA_FMT(FORMAT) \
+ (((FORMAT) == I2S_DATA_FMT_16BITS) || ((FORMAT) == I2S_DATA_FMT_16BITS_EXTENDED) \
+ || ((FORMAT) == I2S_DATA_FMT_24BITS) || ((FORMAT) == I2S_DATA_FMT_32BITS))
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_MCLK_Output
+ * @{
+ */
+
+#define I2S_MCLK_ENABLE ((uint16_t)0x0200)
+#define I2S_MCLK_DISABLE ((uint16_t)0x0000)
+#define IS_I2S_MCLK_ENABLE(OUTPUT) (((OUTPUT) == I2S_MCLK_ENABLE) || ((OUTPUT) == I2S_MCLK_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Audio_Frequency
+ * @{
+ */
+
+#define I2S_AUDIO_FREQ_192K ((uint32_t)192000)
+#define I2S_AUDIO_FREQ_96K ((uint32_t)96000)
+#define I2S_AUDIO_FREQ_48K ((uint32_t)48000)
+#define I2S_AUDIO_FREQ_44K ((uint32_t)44100)
+#define I2S_AUDIO_FREQ_32K ((uint32_t)32000)
+#define I2S_AUDIO_FREQ_22K ((uint32_t)22050)
+#define I2S_AUDIO_FREQ_16K ((uint32_t)16000)
+#define I2S_AUDIO_FREQ_11K ((uint32_t)11025)
+#define I2S_AUDIO_FREQ_8K ((uint32_t)8000)
+#define I2S_AUDIO_FREQ_DEFAULT ((uint32_t)2)
+
+#define IS_I2S_AUDIO_FREQ(FREQ) \
+ ((((FREQ) >= I2S_AUDIO_FREQ_8K) && ((FREQ) <= I2S_AUDIO_FREQ_192K)) || ((FREQ) == I2S_AUDIO_FREQ_DEFAULT))
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Clock_Polarity
+ * @{
+ */
+
+#define I2S_CLKPOL_LOW ((uint16_t)0x0000)
+#define I2S_CLKPOL_HIGH ((uint16_t)0x0008)
+#define IS_I2S_CLKPOL(CPOL) (((CPOL) == I2S_CLKPOL_LOW) || ((CPOL) == I2S_CLKPOL_HIGH))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_I2S_DMA_transfer_requests
+ * @{
+ */
+
+#define SPI_I2S_DMA_TX ((uint16_t)0x0002)
+#define SPI_I2S_DMA_RX ((uint16_t)0x0001)
+#define IS_SPI_I2S_DMA(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_NSS_internal_software_management
+ * @{
+ */
+
+#define SPI_NSS_HIGH ((uint16_t)0x0100)
+#define SPI_NSS_LOW ((uint16_t)0xFEFF)
+#define IS_SPI_NSS_LEVEL(INTERNAL) (((INTERNAL) == SPI_NSS_HIGH) || ((INTERNAL) == SPI_NSS_LOW))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_CRC_Transmit_Receive
+ * @{
+ */
+
+#define SPI_CRC_TX ((uint8_t)0x00)
+#define SPI_CRC_RX ((uint8_t)0x01)
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_TX) || ((CRC) == SPI_CRC_RX))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_direction_transmit_receive
+ * @{
+ */
+
+#define SPI_BIDIRECTION_RX ((uint16_t)0xBFFF)
+#define SPI_BIDIRECTION_TX ((uint16_t)0x4000)
+#define IS_SPI_BIDIRECTION(DIRECTION) (((DIRECTION) == SPI_BIDIRECTION_RX) || ((DIRECTION) == SPI_BIDIRECTION_TX))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_I2S_interrupts_definition
+ * @{
+ */
+
+#define SPI_I2S_INT_TE ((uint8_t)0x71)
+#define SPI_I2S_INT_RNE ((uint8_t)0x60)
+#define SPI_I2S_INT_ERR ((uint8_t)0x50)
+#define IS_SPI_I2S_CONFIG_INT(IT) (((IT) == SPI_I2S_INT_TE) || ((IT) == SPI_I2S_INT_RNE) || ((IT) == SPI_I2S_INT_ERR))
+#define SPI_I2S_INT_OVER ((uint8_t)0x56)
+#define SPI_INT_MODERR ((uint8_t)0x55)
+#define SPI_INT_CRCERR ((uint8_t)0x54)
+#define I2S_INT_UNDER ((uint8_t)0x53)
+#define IS_SPI_I2S_CLR_INT(IT) (((IT) == SPI_INT_CRCERR))
+#define IS_SPI_I2S_GET_INT(IT) \
+ (((IT) == SPI_I2S_INT_RNE) || ((IT) == SPI_I2S_INT_TE) || ((IT) == I2S_INT_UNDER) || ((IT) == SPI_INT_CRCERR) \
+ || ((IT) == SPI_INT_MODERR) || ((IT) == SPI_I2S_INT_OVER))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_I2S_flags_definition
+ * @{
+ */
+
+#define SPI_I2S_RNE_FLAG ((uint16_t)0x0001)
+#define SPI_I2S_TE_FLAG ((uint16_t)0x0002)
+#define I2S_CHSIDE_FLAG ((uint16_t)0x0004)
+#define I2S_UNDER_FLAG ((uint16_t)0x0008)
+#define SPI_CRCERR_FLAG ((uint16_t)0x0010)
+#define SPI_MODERR_FLAG ((uint16_t)0x0020)
+#define SPI_I2S_OVER_FLAG ((uint16_t)0x0040)
+#define SPI_I2S_BUSY_FLAG ((uint16_t)0x0080)
+#define IS_SPI_I2S_CLR_FLAG(FLAG) (((FLAG) == SPI_CRCERR_FLAG))
+#define IS_SPI_I2S_GET_FLAG(FLAG) \
+ (((FLAG) == SPI_I2S_BUSY_FLAG) || ((FLAG) == SPI_I2S_OVER_FLAG) || ((FLAG) == SPI_MODERR_FLAG) \
+ || ((FLAG) == SPI_CRCERR_FLAG) || ((FLAG) == I2S_UNDER_FLAG) || ((FLAG) == I2S_CHSIDE_FLAG) \
+ || ((FLAG) == SPI_I2S_TE_FLAG) || ((FLAG) == SPI_I2S_RNE_FLAG))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_CRC_polynomial
+ * @{
+ */
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Exported_Functions
+ * @{
+ */
+
+void SPI_I2S_DeInit(SPI_Module* SPIx);
+void SPI_Init(SPI_Module* SPIx, SPI_InitType* SPI_InitStruct);
+void I2S_Init(SPI_Module* SPIx, I2S_InitType* I2S_InitStruct);
+void SPI_InitStruct(SPI_InitType* SPI_InitStruct);
+void I2S_InitStruct(I2S_InitType* I2S_InitStruct);
+void SPI_Enable(SPI_Module* SPIx, FunctionalState Cmd);
+void I2S_Enable(SPI_Module* SPIx, FunctionalState Cmd);
+void SPI_I2S_EnableInt(SPI_Module* SPIx, uint8_t SPI_I2S_IT, FunctionalState Cmd);
+void SPI_I2S_EnableDma(SPI_Module* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState Cmd);
+void SPI_I2S_TransmitData(SPI_Module* SPIx, uint16_t Data);
+uint16_t SPI_I2S_ReceiveData(SPI_Module* SPIx);
+void SPI_SetNssLevel(SPI_Module* SPIx, uint16_t SPI_NSSInternalSoft);
+void SPI_SSOutputEnable(SPI_Module* SPIx, FunctionalState Cmd);
+void SPI_ConfigDataLen(SPI_Module* SPIx, uint16_t DataLen);
+void SPI_TransmitCrcNext(SPI_Module* SPIx);
+void SPI_EnableCalculateCrc(SPI_Module* SPIx, FunctionalState Cmd);
+uint16_t SPI_GetCRCDat(SPI_Module* SPIx, uint8_t SPI_CRC);
+uint16_t SPI_GetCRCPoly(SPI_Module* SPIx);
+void SPI_ConfigBidirectionalMode(SPI_Module* SPIx, uint16_t DataDirection);
+FlagStatus SPI_I2S_GetStatus(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG);
+void SPI_I2S_ClrCRCErrFlag(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG);
+INTStatus SPI_I2S_GetIntStatus(SPI_Module* SPIx, uint8_t SPI_I2S_IT);
+void SPI_I2S_ClrITPendingBit(SPI_Module* SPIx, uint8_t SPI_I2S_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32L43X_SPI_H__ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_tim.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_tim.h
new file mode 100644
index 0000000000..6d5efba13f
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_tim.h
@@ -0,0 +1,1101 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_tim.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L43X_TIM_H__
+#define __N32L43X_TIM_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l43x.h"
+#include "stdbool.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup TIM
+ * @{
+ */
+
+/** @addtogroup TIM_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief TIM Time Base Init structure definition
+ * @note This structure is used with all TIMx except for TIM6 and TIM7.
+ */
+
+typedef struct
+{
+ uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
+ This parameter can be a number between 0x0000 and 0xFFFF */
+
+ uint16_t CntMode; /*!< Specifies the counter mode.
+ This parameter can be a value of @ref TIM_Counter_Mode */
+
+ uint16_t Period; /*!< Specifies the period value to be loaded into the active
+ Auto-Reload Register at the next update event.
+ This parameter must be a number between 0x0000 and 0xFFFF. */
+
+ uint16_t ClkDiv; /*!< Specifies the clock division.
+ This parameter can be a value of @ref TIM_Clock_Division_CKD */
+
+ uint8_t RepetCnt; /*!< Specifies the repetition counter value. Each time the REPCNT downcounter
+ reaches zero, an update event is generated and counting restarts
+ from the REPCNT value (N).
+ This means in PWM mode that (N+1) corresponds to:
+ - the number of PWM periods in edge-aligned mode
+ - the number of half PWM period in center-aligned mode
+ This parameter must be a number between 0x00 and 0xFF.
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ bool CapCh1FromCompEn; /*!< channel 1 select capture in from comp if 1, from IOM if 0
+ Tim1,Tim8,Tim2,Tim3,Tim4,Tim5 valid*/
+ bool CapCh2FromCompEn; /*!< channel 2 select capture in from comp if 1, from IOM if 0
+ Tim2,Tim3,Tim4,Tim5 valid*/
+ bool CapCh3FromCompEn; /*!< channel 3 select capture in from comp if 1, from IOM if 0
+ Tim2,Tim3,Tim4,Tim5 valid*/
+ bool CapCh4FromCompEn; /*!< channel 4 select capture in from comp if 1, from IOM if 0
+ Tim2,Tim3,Tim4 valid*/
+ bool CapEtrClrFromCompEn; /*!< etr clearref select from comp if 1, from ETR IOM if 0
+ Tim2,Tim3,Tim4 valid*/
+ bool CapEtrSelFromTscEn; /*!< etr select from TSC if 1, from IOM if 0
+ Tim2,Tim4 valid*/
+} TIM_TimeBaseInitType;
+
+/**
+ * @brief TIM Output Compare Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t OcMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+ uint16_t OutputState; /*!< Specifies the TIM Output Compare state.
+ This parameter can be a value of @ref TIM_Output_Compare_state */
+
+ uint16_t OutputNState; /*!< Specifies the TIM complementary Output Compare state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_state
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint16_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between 0x0000 and 0xFFFF */
+
+ uint16_t OcPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+ uint16_t OcNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint16_t OcIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint16_t OcNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+} OCInitType;
+
+/**
+ * @brief TIM Input Capture Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t Channel; /*!< Specifies the TIM channel.
+ This parameter can be a value of @ref Channel */
+
+ uint16_t IcPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint16_t IcSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint16_t IcPrescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint16_t IcFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between 0x0 and 0xF */
+} TIM_ICInitType;
+
+/**
+ * @brief BKDT structure definition
+ * @note This structure is used only with TIM1 and TIM8.
+ */
+
+typedef struct
+{
+ uint16_t OssrState; /*!< Specifies the Off-State selection used in Run mode.
+ This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
+
+ uint16_t OssiState; /*!< Specifies the Off-State used in Idle state.
+ This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
+
+ uint16_t LockLevel; /*!< Specifies the LOCK level parameters.
+ This parameter can be a value of @ref Lock_level */
+
+ uint16_t DeadTime; /*!< Specifies the delay time between the switching-off and the
+ switching-on of the outputs.
+ This parameter can be a number between 0x00 and 0xFF */
+
+ uint16_t Break; /*!< Specifies whether the TIM Break input is enabled or not.
+ This parameter can be a value of @ref Break_Input_enable_disable */
+
+ uint16_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
+ This parameter can be a value of @ref Break_Polarity */
+
+ uint16_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+ bool IomBreakEn; /*!< EXTENDMODE valid, open iom as break in*/
+ bool LockUpBreakEn; /*!< EXTENDMODE valid, open lockup(haldfault) as break in*/
+ bool PvdBreakEn; /*!< EXTENDMODE valid, open pvd(sys voltage too high or too low) as break in*/
+} TIM_BDTRInitType;
+
+/** @addtogroup TIM_Exported_constants
+ * @{
+ */
+
+#define IsTimAllModule(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \
+ || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8))
+
+/* LIST1: TIM 1 and 8 */
+#define IsTimList1Module(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM8))
+
+/* LIST2: TIM 1, 8 */
+#define IsTimList2Module(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM8))
+
+/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */
+#define IsTimList3Module(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \
+ || ((PERIPH) == TIM8))
+
+/* LIST4: TIM 1, 2, 3, 4, 5, 8 */
+#define IsTimList4Module(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \
+ || ((PERIPH) == TIM8))
+
+/* LIST5: TIM 1, 2, 3, 4, 5, 8 */
+#define IsTimList5Module(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \
+ || ((PERIPH) == TIM8))
+
+/* LIST6: TIM 1, 2, 3, 4, 5, 8 */
+#define IsTimList6Module(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \
+ || ((PERIPH) == TIM8))
+
+/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8 */
+#define IsTimList7Module(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \
+ || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8))
+
+/* LIST8: TIM 1, 2, 3, 4, 5, 8 */
+#define IsTimList8Module(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \
+ || ((PERIPH) == TIM8))
+
+/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8 */
+#define IsTimList9Module(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9) \
+ || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8))
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_and_PWM_modes
+ * @{
+ */
+
+#define TIM_OCMODE_TIMING ((uint16_t)0x0000)
+#define TIM_OCMODE_ACTIVE ((uint16_t)0x0010)
+#define TIM_OCMODE_INACTIVE ((uint16_t)0x0020)
+#define TIM_OCMODE_TOGGLE ((uint16_t)0x0030)
+#define TIM_OCMODE_PWM1 ((uint16_t)0x0060)
+#define TIM_OCMODE_PWM2 ((uint16_t)0x0070)
+#define IsTimOcMode(MODE) \
+ (((MODE) == TIM_OCMODE_TIMING) || ((MODE) == TIM_OCMODE_ACTIVE) || ((MODE) == TIM_OCMODE_INACTIVE) \
+ || ((MODE) == TIM_OCMODE_TOGGLE) || ((MODE) == TIM_OCMODE_PWM1) || ((MODE) == TIM_OCMODE_PWM2))
+#define IsTimOc(MODE) \
+ (((MODE) == TIM_OCMODE_TIMING) || ((MODE) == TIM_OCMODE_ACTIVE) || ((MODE) == TIM_OCMODE_INACTIVE) \
+ || ((MODE) == TIM_OCMODE_TOGGLE) || ((MODE) == TIM_OCMODE_PWM1) || ((MODE) == TIM_OCMODE_PWM2) \
+ || ((MODE) == TIM_FORCED_ACTION_ACTIVE) || ((MODE) == TIM_FORCED_ACTION_INACTIVE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_One_Pulse_Mode
+ * @{
+ */
+
+#define TIM_OPMODE_SINGLE ((uint16_t)0x0008)
+#define TIM_OPMODE_REPET ((uint16_t)0x0000)
+#define IsTimOpMOde(MODE) (((MODE) == TIM_OPMODE_SINGLE) || ((MODE) == TIM_OPMODE_REPET))
+/**
+ * @}
+ */
+
+/** @addtogroup Channel
+ * @{
+ */
+
+#define TIM_CH_1 ((uint16_t)0x0000)
+#define TIM_CH_2 ((uint16_t)0x0004)
+#define TIM_CH_3 ((uint16_t)0x0008)
+#define TIM_CH_4 ((uint16_t)0x000C)
+#define IsTimCh(CHANNEL) \
+ (((CHANNEL) == TIM_CH_1) || ((CHANNEL) == TIM_CH_2) || ((CHANNEL) == TIM_CH_3) || ((CHANNEL) == TIM_CH_4))
+#define IsTimPwmInCh(CHANNEL) (((CHANNEL) == TIM_CH_1) || ((CHANNEL) == TIM_CH_2))
+#define IsTimComplementaryCh(CHANNEL) (((CHANNEL) == TIM_CH_1) || ((CHANNEL) == TIM_CH_2) || ((CHANNEL) == TIM_CH_3))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Clock_Division_CKD
+ * @{
+ */
+
+#define TIM_CLK_DIV1 ((uint16_t)0x0000)
+#define TIM_CLK_DIV2 ((uint16_t)0x0100)
+#define TIM_CLK_DIV4 ((uint16_t)0x0200)
+#define IsTimClkDiv(DIV) (((DIV) == TIM_CLK_DIV1) || ((DIV) == TIM_CLK_DIV2) || ((DIV) == TIM_CLK_DIV4))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Counter_Mode
+ * @{
+ */
+
+#define TIM_CNT_MODE_UP ((uint16_t)0x0000)
+#define TIM_CNT_MODE_DOWN ((uint16_t)0x0010)
+#define TIM_CNT_MODE_CENTER_ALIGN1 ((uint16_t)0x0020)
+#define TIM_CNT_MODE_CENTER_ALIGN2 ((uint16_t)0x0040)
+#define TIM_CNT_MODE_CENTER_ALIGN3 ((uint16_t)0x0060)
+#define IsTimCntMode(MODE) \
+ (((MODE) == TIM_CNT_MODE_UP) || ((MODE) == TIM_CNT_MODE_DOWN) || ((MODE) == TIM_CNT_MODE_CENTER_ALIGN1) \
+ || ((MODE) == TIM_CNT_MODE_CENTER_ALIGN2) || ((MODE) == TIM_CNT_MODE_CENTER_ALIGN3))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_Polarity
+ * @{
+ */
+
+#define TIM_OC_POLARITY_HIGH ((uint16_t)0x0000)
+#define TIM_OC_POLARITY_LOW ((uint16_t)0x0002)
+#define IsTimOcPolarity(POLARITY) (((POLARITY) == TIM_OC_POLARITY_HIGH) || ((POLARITY) == TIM_OC_POLARITY_LOW))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_N_Polarity
+ * @{
+ */
+
+#define TIM_OCN_POLARITY_HIGH ((uint16_t)0x0000)
+#define TIM_OCN_POLARITY_LOW ((uint16_t)0x0008)
+#define IsTimOcnPolarity(POLARITY) (((POLARITY) == TIM_OCN_POLARITY_HIGH) || ((POLARITY) == TIM_OCN_POLARITY_LOW))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_state
+ * @{
+ */
+
+#define TIM_OUTPUT_STATE_DISABLE ((uint16_t)0x0000)
+#define TIM_OUTPUT_STATE_ENABLE ((uint16_t)0x0001)
+#define IsTimOutputState(STATE) (((STATE) == TIM_OUTPUT_STATE_DISABLE) || ((STATE) == TIM_OUTPUT_STATE_ENABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_N_state
+ * @{
+ */
+
+#define TIM_OUTPUT_NSTATE_DISABLE ((uint16_t)0x0000)
+#define TIM_OUTPUT_NSTATE_ENABLE ((uint16_t)0x0004)
+#define IsTimOutputNState(STATE) (((STATE) == TIM_OUTPUT_NSTATE_DISABLE) || ((STATE) == TIM_OUTPUT_NSTATE_ENABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Capture_Compare_state
+ * @{
+ */
+
+#define TIM_CAP_CMP_ENABLE ((uint16_t)0x0001)
+#define TIM_CAP_CMP_DISABLE ((uint16_t)0x0000)
+#define IsTimCapCmpState(CCX) (((CCX) == TIM_CAP_CMP_ENABLE) || ((CCX) == TIM_CAP_CMP_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Capture_Compare_N_state
+ * @{
+ */
+
+#define TIM_CAP_CMP_N_ENABLE ((uint16_t)0x0004)
+#define TIM_CAP_CMP_N_DISABLE ((uint16_t)0x0000)
+#define IsTimCapCmpNState(CCXN) (((CCXN) == TIM_CAP_CMP_N_ENABLE) || ((CCXN) == TIM_CAP_CMP_N_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup Break_Input_enable_disable
+ * @{
+ */
+
+#define TIM_BREAK_IN_ENABLE ((uint16_t)0x1000)
+#define TIM_BREAK_IN_DISABLE ((uint16_t)0x0000)
+#define IsTimBreakInState(STATE) (((STATE) == TIM_BREAK_IN_ENABLE) || ((STATE) == TIM_BREAK_IN_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup Break_Polarity
+ * @{
+ */
+
+#define TIM_BREAK_POLARITY_LOW ((uint16_t)0x0000)
+#define TIM_BREAK_POLARITY_HIGH ((uint16_t)0x2000)
+#define IsTimBreakPalarity(POLARITY) (((POLARITY) == TIM_BREAK_POLARITY_LOW) || ((POLARITY) == TIM_BREAK_POLARITY_HIGH))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_AOE_Bit_Set_Reset
+ * @{
+ */
+
+#define TIM_AUTO_OUTPUT_ENABLE ((uint16_t)0x4000)
+#define TIM_AUTO_OUTPUT_DISABLE ((uint16_t)0x0000)
+#define IsTimAutoOutputState(STATE) (((STATE) == TIM_AUTO_OUTPUT_ENABLE) || ((STATE) == TIM_AUTO_OUTPUT_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup Lock_level
+ * @{
+ */
+
+#define TIM_LOCK_LEVEL_OFF ((uint16_t)0x0000)
+#define TIM_LOCK_LEVEL_1 ((uint16_t)0x0100)
+#define TIM_LOCK_LEVEL_2 ((uint16_t)0x0200)
+#define TIM_LOCK_LEVEL_3 ((uint16_t)0x0300)
+#define IsTimLockLevel(LEVEL) \
+ (((LEVEL) == TIM_LOCK_LEVEL_OFF) || ((LEVEL) == TIM_LOCK_LEVEL_1) || ((LEVEL) == TIM_LOCK_LEVEL_2) \
+ || ((LEVEL) == TIM_LOCK_LEVEL_3))
+/**
+ * @}
+ */
+
+/** @addtogroup OSSI_Off_State_Selection_for_Idle_mode_state
+ * @{
+ */
+
+#define TIM_OSSI_STATE_ENABLE ((uint16_t)0x0400)
+#define TIM_OSSI_STATE_DISABLE ((uint16_t)0x0000)
+#define IsTimOssiState(STATE) (((STATE) == TIM_OSSI_STATE_ENABLE) || ((STATE) == TIM_OSSI_STATE_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup OSSR_Off_State_Selection_for_Run_mode_state
+ * @{
+ */
+
+#define TIM_OSSR_STATE_ENABLE ((uint16_t)0x0800)
+#define TIM_OSSR_STATE_DISABLE ((uint16_t)0x0000)
+#define IsTimOssrState(STATE) (((STATE) == TIM_OSSR_STATE_ENABLE) || ((STATE) == TIM_OSSR_STATE_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_Idle_State
+ * @{
+ */
+
+#define TIM_OC_IDLE_STATE_SET ((uint16_t)0x0100)
+#define TIM_OC_IDLE_STATE_RESET ((uint16_t)0x0000)
+#define IsTimOcIdleState(STATE) (((STATE) == TIM_OC_IDLE_STATE_SET) || ((STATE) == TIM_OC_IDLE_STATE_RESET))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_N_Idle_State
+ * @{
+ */
+
+#define TIM_OCN_IDLE_STATE_SET ((uint16_t)0x0200)
+#define TIM_OCN_IDLE_STATE_RESET ((uint16_t)0x0000)
+#define IsTimOcnIdleState(STATE) (((STATE) == TIM_OCN_IDLE_STATE_SET) || ((STATE) == TIM_OCN_IDLE_STATE_RESET))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Input_Capture_Polarity
+ * @{
+ */
+
+#define TIM_IC_POLARITY_RISING ((uint16_t)0x0000)
+#define TIM_IC_POLARITY_FALLING ((uint16_t)0x0002)
+#define TIM_IC_POLARITY_BOTHEDGE ((uint16_t)0x000A)
+#define IsTimIcPalaritySingleEdge(POLARITY) \
+ (((POLARITY) == TIM_IC_POLARITY_RISING) || ((POLARITY) == TIM_IC_POLARITY_FALLING))
+#define IsTimIcPolarityAnyEdge(POLARITY) \
+ (((POLARITY) == TIM_IC_POLARITY_RISING) || ((POLARITY) == TIM_IC_POLARITY_FALLING) \
+ || ((POLARITY) == TIM_IC_POLARITY_BOTHEDGE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Input_Capture_Selection
+ * @{
+ */
+
+#define TIM_IC_SELECTION_DIRECTTI \
+ ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be \
+ connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_IC_SELECTION_INDIRECTTI \
+ ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be \
+ connected to IC2, IC1, IC4 or IC3, respectively. */
+#define TIM_IC_SELECTION_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
+#define IsTimIcSelection(SELECTION) \
+ (((SELECTION) == TIM_IC_SELECTION_DIRECTTI) || ((SELECTION) == TIM_IC_SELECTION_INDIRECTTI) \
+ || ((SELECTION) == TIM_IC_SELECTION_TRC))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Input_Capture_Prescaler
+ * @{
+ */
+
+#define TIM_IC_PSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. \
+ */
+#define TIM_IC_PSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
+#define TIM_IC_PSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
+#define TIM_IC_PSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
+#define IsTimIcPrescaler(PRESCALER) \
+ (((PRESCALER) == TIM_IC_PSC_DIV1) || ((PRESCALER) == TIM_IC_PSC_DIV2) || ((PRESCALER) == TIM_IC_PSC_DIV4) \
+ || ((PRESCALER) == TIM_IC_PSC_DIV8))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_interrupt_sources
+ * @{
+ */
+
+#define TIM_INT_UPDATE ((uint16_t)0x0001)
+#define TIM_INT_CC1 ((uint16_t)0x0002)
+#define TIM_INT_CC2 ((uint16_t)0x0004)
+#define TIM_INT_CC3 ((uint16_t)0x0008)
+#define TIM_INT_CC4 ((uint16_t)0x0010)
+#define TIM_INT_COM ((uint16_t)0x0020)
+#define TIM_INT_TRIG ((uint16_t)0x0040)
+#define TIM_INT_BREAK ((uint16_t)0x0080)
+#define IsTimInt(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
+
+#define IsTimGetInt(IT) \
+ (((IT) == TIM_INT_UPDATE) || ((IT) == TIM_INT_CC1) || ((IT) == TIM_INT_CC2) || ((IT) == TIM_INT_CC3) \
+ || ((IT) == TIM_INT_CC4) || ((IT) == TIM_INT_COM) || ((IT) == TIM_INT_TRIG) || ((IT) == TIM_INT_BREAK))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_DMA_Base_address
+ * @{
+ */
+
+#define TIM_DMABASE_CTRL1 ((uint16_t)0x0000)
+#define TIM_DMABASE_CTRL2 ((uint16_t)0x0001)
+#define TIM_DMABASE_SMCTRL ((uint16_t)0x0002)
+#define TIM_DMABASE_DMAINTEN ((uint16_t)0x0003)
+#define TIM_DMABASE_STS ((uint16_t)0x0004)
+#define TIM_DMABASE_EVTGEN ((uint16_t)0x0005)
+#define TIM_DMABASE_CAPCMPMOD1 ((uint16_t)0x0006)
+#define TIM_DMABASE_CAPCMPMOD2 ((uint16_t)0x0007)
+#define TIM_DMABASE_CAPCMPEN ((uint16_t)0x0008)
+#define TIM_DMABASE_CNT ((uint16_t)0x0009)
+#define TIM_DMABASE_PSC ((uint16_t)0x000A)
+#define TIM_DMABASE_AR ((uint16_t)0x000B)
+#define TIM_DMABASE_REPCNT ((uint16_t)0x000C)
+#define TIM_DMABASE_CAPCMPDAT1 ((uint16_t)0x000D)
+#define TIM_DMABASE_CAPCMPDAT2 ((uint16_t)0x000E)
+#define TIM_DMABASE_CAPCMPDAT3 ((uint16_t)0x000F)
+#define TIM_DMABASE_CAPCMPDAT4 ((uint16_t)0x0010)
+#define TIM_DMABASE_BKDT ((uint16_t)0x0011)
+#define TIM_DMABASE_DMACTRL ((uint16_t)0x0012)
+
+
+#define IsTimDmaBase(BASE) \
+ (((BASE) == TIM_DMABASE_CTRL1) || ((BASE) == TIM_DMABASE_CTRL2) || ((BASE) == TIM_DMABASE_SMCTRL) \
+ || ((BASE) == TIM_DMABASE_DMAINTEN) || ((BASE) == TIM_DMABASE_STS) || ((BASE) == TIM_DMABASE_EVTGEN) \
+ || ((BASE) == TIM_DMABASE_CAPCMPMOD1) || ((BASE) == TIM_DMABASE_CAPCMPMOD2) \
+ || ((BASE) == TIM_DMABASE_CAPCMPEN) || ((BASE) == TIM_DMABASE_CNT) || ((BASE) == TIM_DMABASE_PSC) \
+ || ((BASE) == TIM_DMABASE_AR) || ((BASE) == TIM_DMABASE_REPCNT) || ((BASE) == TIM_DMABASE_CAPCMPDAT1) \
+ || ((BASE) == TIM_DMABASE_CAPCMPDAT2) || ((BASE) == TIM_DMABASE_CAPCMPDAT3) || ((BASE) == TIM_DMABASE_CAPCMPDAT4) \
+ || ((BASE) == TIM_DMABASE_BKDT)|| ((BASE) == TIM_DMABASE_DMACTRL))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_DMA_Burst_Length
+ * @{
+ */
+
+#define TIM_DMABURST_LENGTH_1TRANSFER ((uint16_t)0x0000)
+#define TIM_DMABURST_LENGTH_2TRANSFERS ((uint16_t)0x0100)
+#define TIM_DMABURST_LENGTH_3TRANSFERS ((uint16_t)0x0200)
+#define TIM_DMABURST_LENGTH_4TRANSFERS ((uint16_t)0x0300)
+#define TIM_DMABURST_LENGTH_5TRANSFERS ((uint16_t)0x0400)
+#define TIM_DMABURST_LENGTH_6TRANSFERS ((uint16_t)0x0500)
+#define TIM_DMABURST_LENGTH_7TRANSFERS ((uint16_t)0x0600)
+#define TIM_DMABURST_LENGTH_8TRANSFERS ((uint16_t)0x0700)
+#define TIM_DMABURST_LENGTH_9TRANSFERS ((uint16_t)0x0800)
+#define TIM_DMABURST_LENGTH_10TRANSFERS ((uint16_t)0x0900)
+#define TIM_DMABURST_LENGTH_11TRANSFERS ((uint16_t)0x0A00)
+#define TIM_DMABURST_LENGTH_12TRANSFERS ((uint16_t)0x0B00)
+#define TIM_DMABURST_LENGTH_13TRANSFERS ((uint16_t)0x0C00)
+#define TIM_DMABURST_LENGTH_14TRANSFERS ((uint16_t)0x0D00)
+#define TIM_DMABURST_LENGTH_15TRANSFERS ((uint16_t)0x0E00)
+#define TIM_DMABURST_LENGTH_16TRANSFERS ((uint16_t)0x0F00)
+#define TIM_DMABURST_LENGTH_17TRANSFERS ((uint16_t)0x1000)
+#define TIM_DMABURST_LENGTH_18TRANSFERS ((uint16_t)0x1100)
+#define TIM_DMABURST_LENGTH_19TRANSFERS ((uint16_t)0x1200)
+#define TIM_DMABURST_LENGTH_20TRANSFERS ((uint16_t)0x1300)
+#define TIM_DMABURST_LENGTH_21TRANSFERS ((uint16_t)0x1400)
+#define IsTimDmaLength(LENGTH) \
+ (((LENGTH) == TIM_DMABURST_LENGTH_1TRANSFER) || ((LENGTH) == TIM_DMABURST_LENGTH_2TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_3TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_4TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_5TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_6TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_7TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_8TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_9TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_10TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_11TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_12TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_13TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_14TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_15TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_16TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_17TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_18TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_19TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_20TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_21TRANSFERS))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_DMA_sources
+ * @{
+ */
+
+#define TIM_DMA_UPDATE ((uint16_t)0x0100)
+#define TIM_DMA_CC1 ((uint16_t)0x0200)
+#define TIM_DMA_CC2 ((uint16_t)0x0400)
+#define TIM_DMA_CC3 ((uint16_t)0x0800)
+#define TIM_DMA_CC4 ((uint16_t)0x1000)
+#define TIM_DMA_COM ((uint16_t)0x2000)
+#define TIM_DMA_TRIG ((uint16_t)0x4000)
+#define IsTimDmaSrc(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_External_Trigger_Prescaler
+ * @{
+ */
+
+#define TIM_EXT_TRG_PSC_OFF ((uint16_t)0x0000)
+#define TIM_EXT_TRG_PSC_DIV2 ((uint16_t)0x1000)
+#define TIM_EXT_TRG_PSC_DIV4 ((uint16_t)0x2000)
+#define TIM_EXT_TRG_PSC_DIV8 ((uint16_t)0x3000)
+#define IsTimExtPreDiv(PRESCALER) \
+ (((PRESCALER) == TIM_EXT_TRG_PSC_OFF) || ((PRESCALER) == TIM_EXT_TRG_PSC_DIV2) \
+ || ((PRESCALER) == TIM_EXT_TRG_PSC_DIV4) || ((PRESCALER) == TIM_EXT_TRG_PSC_DIV8))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Internal_Trigger_Selection
+ * @{
+ */
+
+#define TIM_TRIG_SEL_IN_TR0 ((uint16_t)0x0000)
+#define TIM_TRIG_SEL_IN_TR1 ((uint16_t)0x0010)
+#define TIM_TRIG_SEL_IN_TR2 ((uint16_t)0x0020)
+#define TIM_TRIG_SEL_IN_TR3 ((uint16_t)0x0030)
+#define TIM_TRIG_SEL_TI1F_ED ((uint16_t)0x0040)
+#define TIM_TRIG_SEL_TI1FP1 ((uint16_t)0x0050)
+#define TIM_TRIG_SEL_TI2FP2 ((uint16_t)0x0060)
+#define TIM_TRIG_SEL_ETRF ((uint16_t)0x0070)
+#define IsTimTrigSel(SELECTION) \
+ (((SELECTION) == TIM_TRIG_SEL_IN_TR0) || ((SELECTION) == TIM_TRIG_SEL_IN_TR1) \
+ || ((SELECTION) == TIM_TRIG_SEL_IN_TR2) || ((SELECTION) == TIM_TRIG_SEL_IN_TR3) \
+ || ((SELECTION) == TIM_TRIG_SEL_TI1F_ED) || ((SELECTION) == TIM_TRIG_SEL_TI1FP1) \
+ || ((SELECTION) == TIM_TRIG_SEL_TI2FP2) || ((SELECTION) == TIM_TRIG_SEL_ETRF))
+#define IsTimInterTrigSel(SELECTION) \
+ (((SELECTION) == TIM_TRIG_SEL_IN_TR0) || ((SELECTION) == TIM_TRIG_SEL_IN_TR1) \
+ || ((SELECTION) == TIM_TRIG_SEL_IN_TR2) || ((SELECTION) == TIM_TRIG_SEL_IN_TR3))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_TIx_External_Clock_Source
+ * @{
+ */
+
+#define TIM_EXT_CLK_SRC_TI1 ((uint16_t)0x0050)
+#define TIM_EXT_CLK_SRC_TI2 ((uint16_t)0x0060)
+#define TIM_EXT_CLK_SRC_TI1ED ((uint16_t)0x0040)
+#define IsTimExtClkSrc(SOURCE) \
+ (((SOURCE) == TIM_EXT_CLK_SRC_TI1) || ((SOURCE) == TIM_EXT_CLK_SRC_TI2) || ((SOURCE) == TIM_EXT_CLK_SRC_TI1ED))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_External_Trigger_Polarity
+ * @{
+ */
+#define TIM_EXT_TRIG_POLARITY_INVERTED ((uint16_t)0x8000)
+#define TIM_EXT_TRIG_POLARITY_NONINVERTED ((uint16_t)0x0000)
+#define IsTimExtTrigPolarity(POLARITY) \
+ (((POLARITY) == TIM_EXT_TRIG_POLARITY_INVERTED) || ((POLARITY) == TIM_EXT_TRIG_POLARITY_NONINVERTED))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Prescaler_Reload_Mode
+ * @{
+ */
+
+#define TIM_PSC_RELOAD_MODE_UPDATE ((uint16_t)0x0000)
+#define TIM_PSC_RELOAD_MODE_IMMEDIATE ((uint16_t)0x0001)
+#define IsTimPscReloadMode(RELOAD) \
+ (((RELOAD) == TIM_PSC_RELOAD_MODE_UPDATE) || ((RELOAD) == TIM_PSC_RELOAD_MODE_IMMEDIATE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Forced_Action
+ * @{
+ */
+
+#define TIM_FORCED_ACTION_ACTIVE ((uint16_t)0x0050)
+#define TIM_FORCED_ACTION_INACTIVE ((uint16_t)0x0040)
+#define IsTimForceActive(OPERATE) (((OPERATE) == TIM_FORCED_ACTION_ACTIVE) || ((OPERATE) == TIM_FORCED_ACTION_INACTIVE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Encoder_Mode
+ * @{
+ */
+
+#define TIM_ENCODE_MODE_TI1 ((uint16_t)0x0001)
+#define TIM_ENCODE_MODE_TI2 ((uint16_t)0x0002)
+#define TIM_ENCODE_MODE_TI12 ((uint16_t)0x0003)
+#define IsTimEncodeMode(MODE) \
+ (((MODE) == TIM_ENCODE_MODE_TI1) || ((MODE) == TIM_ENCODE_MODE_TI2) || ((MODE) == TIM_ENCODE_MODE_TI12))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Event_Source
+ * @{
+ */
+
+#define TIM_EVT_SRC_UPDATE ((uint16_t)0x0001)
+#define TIM_EVT_SRC_CC1 ((uint16_t)0x0002)
+#define TIM_EVT_SRC_CC2 ((uint16_t)0x0004)
+#define TIM_EVT_SRC_CC3 ((uint16_t)0x0008)
+#define TIM_EVT_SRC_CC4 ((uint16_t)0x0010)
+#define TIM_EVT_SRC_COM ((uint16_t)0x0020)
+#define TIM_EVT_SRC_TRIG ((uint16_t)0x0040)
+#define TIM_EVT_SRC_BREAK ((uint16_t)0x0080)
+#define IsTimEvtSrc(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Update_Source
+ * @{
+ */
+
+#define TIM_UPDATE_SRC_GLOBAL \
+ ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow \
+ or the setting of UG bit, or an update generation \
+ through the slave mode controller. */
+#define TIM_UPDATE_SRC_REGULAr ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
+#define IsTimUpdateSrc(SOURCE) (((SOURCE) == TIM_UPDATE_SRC_GLOBAL) || ((SOURCE) == TIM_UPDATE_SRC_REGULAr))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_Preload_State
+ * @{
+ */
+
+#define TIM_OC_PRE_LOAD_ENABLE ((uint16_t)0x0008)
+#define TIM_OC_PRE_LOAD_DISABLE ((uint16_t)0x0000)
+#define IsTimOcPreLoadState(STATE) (((STATE) == TIM_OC_PRE_LOAD_ENABLE) || ((STATE) == TIM_OC_PRE_LOAD_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_Fast_State
+ * @{
+ */
+
+#define TIM_OC_FAST_ENABLE ((uint16_t)0x0004)
+#define TIM_OC_FAST_DISABLE ((uint16_t)0x0000)
+#define IsTimOcFastState(STATE) (((STATE) == TIM_OC_FAST_ENABLE) || ((STATE) == TIM_OC_FAST_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_Clear_State
+ * @{
+ */
+
+#define TIM_OC_CLR_ENABLE ((uint16_t)0x0080)
+#define TIM_OC_CLR_DISABLE ((uint16_t)0x0000)
+#define IsTimOcClrState(STATE) (((STATE) == TIM_OC_CLR_ENABLE) || ((STATE) == TIM_OC_CLR_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Trigger_Output_Source
+ * @{
+ */
+
+#define TIM_TRGO_SRC_RESET ((uint16_t)0x0000)
+#define TIM_TRGO_SRC_ENABLE ((uint16_t)0x0010)
+#define TIM_TRGO_SRC_UPDATE ((uint16_t)0x0020)
+#define TIM_TRGO_SRC_OC1 ((uint16_t)0x0030)
+#define TIM_TRGO_SRC_OC1REF ((uint16_t)0x0040)
+#define TIM_TRGO_SRC_OC2REF ((uint16_t)0x0050)
+#define TIM_TRGO_SRC_OC3REF ((uint16_t)0x0060)
+#define TIM_TRGO_SRC_OC4REF ((uint16_t)0x0070)
+#define IsTimTrgoSrc(SOURCE) \
+ (((SOURCE) == TIM_TRGO_SRC_RESET) || ((SOURCE) == TIM_TRGO_SRC_ENABLE) || ((SOURCE) == TIM_TRGO_SRC_UPDATE) \
+ || ((SOURCE) == TIM_TRGO_SRC_OC1) || ((SOURCE) == TIM_TRGO_SRC_OC1REF) || ((SOURCE) == TIM_TRGO_SRC_OC2REF) \
+ || ((SOURCE) == TIM_TRGO_SRC_OC3REF) || ((SOURCE) == TIM_TRGO_SRC_OC4REF))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Slave_Mode
+ * @{
+ */
+
+#define TIM_SLAVE_MODE_RESET ((uint16_t)0x0004)
+#define TIM_SLAVE_MODE_GATED ((uint16_t)0x0005)
+#define TIM_SLAVE_MODE_TRIG ((uint16_t)0x0006)
+#define TIM_SLAVE_MODE_EXT1 ((uint16_t)0x0007)
+#define IsTimSlaveMode(MODE) \
+ (((MODE) == TIM_SLAVE_MODE_RESET) || ((MODE) == TIM_SLAVE_MODE_GATED) || ((MODE) == TIM_SLAVE_MODE_TRIG) \
+ || ((MODE) == TIM_SLAVE_MODE_EXT1))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Master_Slave_Mode
+ * @{
+ */
+
+#define TIM_MASTER_SLAVE_MODE_ENABLE ((uint16_t)0x0080)
+#define TIM_MASTER_SLAVE_MODE_DISABLE ((uint16_t)0x0000)
+#define IsTimMasterSlaveMode(STATE) \
+ (((STATE) == TIM_MASTER_SLAVE_MODE_ENABLE) || ((STATE) == TIM_MASTER_SLAVE_MODE_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Flags
+ * @{
+ */
+
+#define TIM_FLAG_UPDATE ((uint32_t)0x0001)
+#define TIM_FLAG_CC1 ((uint32_t)0x0002)
+#define TIM_FLAG_CC2 ((uint32_t)0x0004)
+#define TIM_FLAG_CC3 ((uint32_t)0x0008)
+#define TIM_FLAG_CC4 ((uint32_t)0x0010)
+#define TIM_FLAG_COM ((uint32_t)0x0020)
+#define TIM_FLAG_TRIG ((uint32_t)0x0040)
+#define TIM_FLAG_BREAK ((uint32_t)0x0080)
+#define TIM_FLAG_CC1OF ((uint32_t)0x0200)
+#define TIM_FLAG_CC2OF ((uint32_t)0x0400)
+#define TIM_FLAG_CC3OF ((uint32_t)0x0800)
+#define TIM_FLAG_CC4OF ((uint32_t)0x1000)
+#define TIM_FLAG_CC5 ((uint32_t)0x010000)
+#define TIM_FLAG_CC6 ((uint32_t)0x020000)
+
+#define IsTimGetFlag(FLAG) \
+ (((FLAG) == TIM_FLAG_UPDATE) || ((FLAG) == TIM_FLAG_CC1) || ((FLAG) == TIM_FLAG_CC2) || ((FLAG) == TIM_FLAG_CC3) \
+ || ((FLAG) == TIM_FLAG_CC4) || ((FLAG) == TIM_FLAG_COM) || ((FLAG) == TIM_FLAG_TRIG) \
+ || ((FLAG) == TIM_FLAG_BREAK) || ((FLAG) == TIM_FLAG_CC1OF) || ((FLAG) == TIM_FLAG_CC2OF) \
+ || ((FLAG) == TIM_FLAG_CC3OF) || ((FLAG) == TIM_FLAG_CC4OF) || ((FLAG) == TIM_FLAG_CC5) \
+ || ((FLAG) == TIM_FLAG_CC6))
+
+#define IsTimClrFlag(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Input_Capture_Filer_Value
+ * @{
+ */
+
+#define IsTimInCapFilter(ICFILTER) ((ICFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_External_Trigger_Filter
+ * @{
+ */
+
+#define IsTimExtTrigFilter(EXTFILTER) ((EXTFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+#define TIM_CC1EN ((uint32_t)1<<0)
+#define TIM_CC1NEN ((uint32_t)1<<2)
+#define TIM_CC2EN ((uint32_t)1<<4)
+#define TIM_CC2NEN ((uint32_t)1<<6)
+#define TIM_CC3EN ((uint32_t)1<<8)
+#define TIM_CC3NEN ((uint32_t)1<<10)
+#define TIM_CC4EN ((uint32_t)1<<12)
+#define TIM_CC5EN ((uint32_t)1<<16)
+#define TIM_CC6EN ((uint32_t)1<<20)
+
+#define IsAdvancedTimCCENFlag(FLAG) \
+ (((FLAG) == TIM_CC1EN) || ((FLAG) == TIM_CC1NEN) || ((FLAG) == TIM_CC2EN) || ((FLAG) == TIM_CC2NEN) \
+ || ((FLAG) == TIM_CC3EN) || ((FLAG) == TIM_CC3NEN) \
+ || ((FLAG) == TIM_CC4EN) || ((FLAG) == TIM_CC5EN) || ((FLAG) == TIM_CC6EN) )
+#define IsGeneralTimCCENFlag(FLAG) \
+ (((FLAG) == TIM_CC1EN) || ((FLAG) == TIM_CC2EN) \
+ || ((FLAG) == TIM_CC3EN) \
+ || ((FLAG) == TIM_CC4EN) )
+
+/** @addtogroup TIM_Legacy
+ * @{
+ */
+
+#define TIM_DMA_BURST_LEN_1BYTE TIM_DMABURST_LENGTH_1TRANSFER
+#define TIM_DMA_BURST_LEN_2BYTES TIM_DMABURST_LENGTH_2TRANSFERS
+#define TIM_DMA_BURST_LEN_3BYTES TIM_DMABURST_LENGTH_3TRANSFERS
+#define TIM_DMA_BURST_LEN_4BYTES TIM_DMABURST_LENGTH_4TRANSFERS
+#define TIM_DMA_BURST_LEN_5BYTES TIM_DMABURST_LENGTH_5TRANSFERS
+#define TIM_DMA_BURST_LEN_6BYTES TIM_DMABURST_LENGTH_6TRANSFERS
+#define TIM_DMA_BURST_LEN_7BYTES TIM_DMABURST_LENGTH_7TRANSFERS
+#define TIM_DMA_BURST_LEN_8BYTES TIM_DMABURST_LENGTH_8TRANSFERS
+#define TIM_DMA_BURST_LEN_9BYTES TIM_DMABURST_LENGTH_9TRANSFERS
+#define TIM_DMA_BURST_LEN_10BYTES TIM_DMABURST_LENGTH_10TRANSFERS
+#define TIM_DMA_BURST_LEN_11BYTES TIM_DMABURST_LENGTH_11TRANSFERS
+#define TIM_DMA_BURST_LEN_12BYTES TIM_DMABURST_LENGTH_12TRANSFERS
+#define TIM_DMA_BURST_LEN_13BYTES TIM_DMABURST_LENGTH_13TRANSFERS
+#define TIM_DMA_BURST_LEN_14BYTES TIM_DMABURST_LENGTH_14TRANSFERS
+#define TIM_DMA_BURST_LEN_15BYTES TIM_DMABURST_LENGTH_15TRANSFERS
+#define TIM_DMA_BURST_LEN_16BYTES TIM_DMABURST_LENGTH_16TRANSFERS
+#define TIM_DMA_BURST_LEN_17BYTES TIM_DMABURST_LENGTH_17TRANSFERS
+#define TIM_DMA_BURST_LEN_18BYTES TIM_DMABURST_LENGTH_18TRANSFERS
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions
+ * @{
+ */
+
+void TIM_DeInit(TIM_Module* TIMx);
+void TIM_InitTimeBase(TIM_Module* TIMx, TIM_TimeBaseInitType* TIM_TimeBaseInitStruct);
+void TIM_InitOc1(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
+void TIM_InitOc2(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
+void TIM_InitOc3(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
+void TIM_InitOc4(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
+void TIM_InitOc5(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
+void TIM_InitOc6(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
+void TIM_ICInit(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct);
+void TIM_ConfigPwmIc(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct);
+void TIM_ConfigBkdt(TIM_Module* TIMx, TIM_BDTRInitType* TIM_BDTRInitStruct);
+void TIM_InitTimBaseStruct(TIM_TimeBaseInitType* TIM_TimeBaseInitStruct);
+void TIM_InitOcStruct(OCInitType* TIM_OCInitStruct);
+void TIM_InitIcStruct(TIM_ICInitType* TIM_ICInitStruct);
+void TIM_InitBkdtStruct(TIM_BDTRInitType* TIM_BDTRInitStruct);
+void TIM_Enable(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_EnableCtrlPwmOutputs(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_ConfigInt(TIM_Module* TIMx, uint16_t TIM_IT, FunctionalState Cmd);
+void TIM_GenerateEvent(TIM_Module* TIMx, uint16_t TIM_EventSource);
+void TIM_ConfigDma(TIM_Module* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
+void TIM_EnableDma(TIM_Module* TIMx, uint16_t TIM_DMASource, FunctionalState Cmd);
+void TIM_ConfigInternalClk(TIM_Module* TIMx);
+void TIM_ConfigInternalTrigToExt(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_ConfigExtTrigAsClk(TIM_Module* TIMx,
+ uint16_t TIM_TIxExternalCLKSource,
+ uint16_t IcPolarity,
+ uint16_t ICFilter);
+void TIM_ConfigExtClkMode1(TIM_Module* TIMx,
+ uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter);
+void TIM_ConfigExtClkMode2(TIM_Module* TIMx,
+ uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter);
+void TIM_ConfigExtTrig(TIM_Module* TIMx,
+ uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter);
+void TIM_ConfigPrescaler(TIM_Module* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
+void TIM_ConfigCntMode(TIM_Module* TIMx, uint16_t CntMode);
+void TIM_SelectInputTrig(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_ConfigEncoderInterface(TIM_Module* TIMx,
+ uint16_t TIM_EncoderMode,
+ uint16_t TIM_IC1Polarity,
+ uint16_t TIM_IC2Polarity);
+void TIM_ConfigForcedOc1(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ConfigForcedOc2(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ConfigForcedOc3(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ConfigForcedOc4(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ConfigForcedOc5(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ConfigForcedOc6(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ConfigArPreload(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_SelectComEvt(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_SelectCapCmpDmaSrc(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_EnableCapCmpPreloadControl(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_ConfigOc1Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload);
+void TIM_ConfigOc2Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload);
+void TIM_ConfigOc3Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload);
+void TIM_ConfigOc4Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload);
+void TIM_ConfigOc5Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload);
+void TIM_ConfigOc6Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload);
+void TIM_ConfigOc1Fast(TIM_Module* TIMx, uint16_t TIM_OCFast);
+void TIM_ConfigOc2Fast(TIM_Module* TIMx, uint16_t TIM_OCFast);
+void TIM_ConfigOc3Fast(TIM_Module* TIMx, uint16_t TIM_OCFast);
+void TIM_ConfigOc4Fast(TIM_Module* TIMx, uint16_t TIM_OCFast);
+void TIM_ConfigOc5Fast(TIM_Module* TIMx, uint16_t TIM_OCFast);
+void TIM_ConfigOc6Fast(TIM_Module* TIMx, uint16_t TIM_OCFast);
+void TIM_ClrOc1Ref(TIM_Module* TIMx, uint16_t TIM_OCClear);
+void TIM_ClrOc2Ref(TIM_Module* TIMx, uint16_t TIM_OCClear);
+void TIM_ClrOc3Ref(TIM_Module* TIMx, uint16_t TIM_OCClear);
+void TIM_ClrOc4Ref(TIM_Module* TIMx, uint16_t TIM_OCClear);
+void TIM_ClrOc5Ref(TIM_Module* TIMx, uint16_t TIM_OCClear);
+void TIM_ClrOc6Ref(TIM_Module* TIMx, uint16_t TIM_OCClear);
+void TIM_ConfigOc1Polarity(TIM_Module* TIMx, uint16_t OcPolarity);
+void TIM_ConfigOc1NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity);
+void TIM_ConfigOc2Polarity(TIM_Module* TIMx, uint16_t OcPolarity);
+void TIM_ConfigOc2NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity);
+void TIM_ConfigOc3Polarity(TIM_Module* TIMx, uint16_t OcPolarity);
+void TIM_ConfigOc3NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity);
+void TIM_ConfigOc4Polarity(TIM_Module* TIMx, uint16_t OcPolarity);
+void TIM_ConfigOc5Polarity(TIM_Module* TIMx, uint16_t OcPolarity);
+void TIM_ConfigOc6Polarity(TIM_Module* TIMx, uint16_t OcPolarity);
+void TIM_EnableCapCmpCh(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCx);
+void TIM_EnableCapCmpChN(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCxN);
+void TIM_SelectOcMode(TIM_Module* TIMx, uint16_t Channel, uint16_t OcMode);
+void TIM_EnableUpdateEvt(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_ConfigUpdateRequestIntSrc(TIM_Module* TIMx, uint16_t TIM_UpdateSource);
+void TIM_SelectHallSensor(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_SelectOnePulseMode(TIM_Module* TIMx, uint16_t TIM_OPMode);
+void TIM_SelectOutputTrig(TIM_Module* TIMx, uint16_t TIM_TRGOSource);
+void TIM_SelectSlaveMode(TIM_Module* TIMx, uint16_t TIM_SlaveMode);
+void TIM_SelectMasterSlaveMode(TIM_Module* TIMx, uint16_t TIM_MasterSlaveMode);
+void TIM_SetCnt(TIM_Module* TIMx, uint16_t Counter);
+void TIM_SetAutoReload(TIM_Module* TIMx, uint16_t Autoreload);
+void TIM_SetCmp1(TIM_Module* TIMx, uint16_t Compare1);
+void TIM_SetCmp2(TIM_Module* TIMx, uint16_t Compare2);
+void TIM_SetCmp3(TIM_Module* TIMx, uint16_t Compare3);
+void TIM_SetCmp4(TIM_Module* TIMx, uint16_t Compare4);
+void TIM_SetCmp5(TIM_Module* TIMx, uint16_t Compare5);
+void TIM_SetCmp6(TIM_Module* TIMx, uint16_t Compare6);
+void TIM_SetInCap1Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetInCap2Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetInCap3Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetInCap4Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetClkDiv(TIM_Module* TIMx, uint16_t TIM_CKD);
+uint16_t TIM_GetCap1(TIM_Module* TIMx);
+uint16_t TIM_GetCap2(TIM_Module* TIMx);
+uint16_t TIM_GetCap3(TIM_Module* TIMx);
+uint16_t TIM_GetCap4(TIM_Module* TIMx);
+uint16_t TIM_GetCap5(TIM_Module* TIMx);
+uint16_t TIM_GetCap6(TIM_Module* TIMx);
+uint16_t TIM_GetCnt(TIM_Module* TIMx);
+uint16_t TIM_GetPrescaler(TIM_Module* TIMx);
+uint16_t TIM_GetAutoReload(TIM_Module* TIMx);
+FlagStatus TIM_GetCCENStatus(TIM_Module* TIMx, uint32_t TIM_CCEN);
+FlagStatus TIM_GetFlagStatus(TIM_Module* TIMx, uint32_t TIM_FLAG);
+void TIM_ClearFlag(TIM_Module* TIMx, uint32_t TIM_FLAG);
+INTStatus TIM_GetIntStatus(TIM_Module* TIMx, uint32_t TIM_IT);
+void TIM_ClrIntPendingBit(TIM_Module* TIMx, uint32_t TIM_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32L43X_TIM_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_tsc.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_tsc.h
new file mode 100644
index 0000000000..69880935f4
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_tsc.h
@@ -0,0 +1,483 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_tsc.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L43X_TSC_H__
+#define __N32L43X_TSC_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "n32l43x.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup TSC
+ * @{
+ */
+
+/**
+ * @brief TSC error code
+ */
+ typedef enum {
+ TSC_ERROR_OK = 0x00U, /*!< No error */
+ TSC_ERROR_CLOCK = 0x01U, /*!< clock config error */
+ TSC_ERROR_PARAMETER = 0x02U, /*!< parameter error */
+ TSC_ERROR_HW_MODE = 0x03U, /*!< Exit hw mode timeout */
+
+ }TSC_ErrorTypeDef;
+ /**
+ * @
+ */
+
+/**
+ * @brief TSC clock source
+ */
+#define TSC_CLK_SRC_LSI (RCC_LSXCLK_SRC_LSI) /*!< LSI*/
+#define TSC_CLK_SRC_LSE (RCC_LSE_ENABLE|RCC_LSXCLK_SRC_LSE) /*!< LSE */
+#define TSC_CLK_SRC_LSE_BYPASS (RCC_LSE_BYPASS|RCC_LSXCLK_SRC_LSE) /*!< LSE bypass */
+/**
+ * @
+ */
+
+
+/**
+ * @defgroup Detect_Period
+ */
+#define TSC_DET_PERIOD_8 (0x00000000U) /*!< DET_PERIOD[3:0] = 8/TSC_CLOCK */
+#define TSC_DET_PERIOD_16 (0x01UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000001U DET_PERIOD[3:0] = 16/TSC_CLOCK */
+#define TSC_DET_PERIOD_24 (0x02UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000002U DET_PERIOD[3:0] = 24/TSC_CLOCK */
+#define TSC_DET_PERIOD_32 (0x03UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000003U DET_PERIOD[3:0] = 32/TSC_CLOCK(default) */
+#define TSC_DET_PERIOD_40 (0x04UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000004U DET_PERIOD[3:0] = 40/TSC_CLOCK */
+#define TSC_DET_PERIOD_48 (0x05UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000005U DET_PERIOD[3:0] = 48/TSC_CLOCK */
+#define TSC_DET_PERIOD_56 (0x06UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000006U DET_PERIOD[3:0] = 56/TSC_CLOCK */
+#define TSC_DET_PERIOD_64 (0x07UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000007U DET_PERIOD[3:0] = 64/TSC_CLOCK */
+#define TSC_DET_PERIOD_72 (0x08UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000008U DET_PERIOD[3:0] = 72/TSC_CLOCK */
+#define TSC_DET_PERIOD_80 (0x09UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000009U DET_PERIOD[3:0] = 80/TSC_CLOCK */
+#define TSC_DET_PERIOD_88 (0x0AUL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x0000000AU DET_PERIOD[3:0] = 88/TSC_CLOCK */
+#define TSC_DET_PERIOD_96 (0x0BUL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x0000000BU DET_PERIOD[3:0] = 96/TSC_CLOCK */
+#define TSC_DET_PERIOD_104 (0x0CUL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x0000000CU DET_PERIOD[3:0] = 104/TSC_CLOCK */
+/**
+ * @
+ */
+
+/**
+ * @defgroup Detect_Filter
+ */
+#define TSC_DET_FILTER_1 (0x00000000U) /*!< DET_FILTER[3:0] = 1 sample */
+#define TSC_DET_FILTER_2 (0x01UL << TSC_CTRL_DET_FILTER_Pos) /*!< 0x00000010U DET_FILTER[3:0] = 2 samples */
+#define TSC_DET_FILTER_3 (0x02UL << TSC_CTRL_DET_FILTER_Pos) /*!< 0x00000020U DET_FILTER[3:0] = 3 samples */
+#define TSC_DET_FILTER_4 (0x03UL << TSC_CTRL_DET_FILTER_Pos) /*!< 0x00000030U DET_FILTER[3:0] = 4 samples */
+/**
+ * @
+ */
+
+/**
+ * @defgroup HW_Detect_Mode
+ */
+#define TSC_HW_DET_MODE_DISABLE (0x00000000U) /*!< Hardware detect mode disable */
+#define TSC_HW_DET_MODE_ENABLE (0x01UL << TSC_CTRL_HW_DET_MODE_Pos) /*!< 0x00000040U Hardware detect mode enable */
+/**
+ * @
+ */
+
+/**
+ * @defgroup Detect_Type
+ */
+#define TSC_DET_TYPE_Msk (TSC_CTRL_LESS_DET_SEL_Msk|TSC_CTRL_GREAT_DET_SEL_Msk)
+#define TSC_DET_TYPE_Pos (TSC_CTRL_LESS_DET_SEL_Pos)
+
+#define TSC_DET_TYPE_NONE (0UL) /*!< 0x00000000U Disable detect */
+#define TSC_DET_TYPE_LESS (0x01UL << TSC_DET_TYPE_Pos) /*!< 0x00000100U Less detect enable */
+#define TSC_DET_TYPE_GREAT (0x02UL << TSC_DET_TYPE_Pos) /*!< 0x00000200U Great detect enable */
+#define TSC_DET_TYPE_PERIOD (0x03UL << TSC_DET_TYPE_Pos) /*!< 0x00000300U Both great and less detct enable */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_Interrupt
+ */
+#define TSC_IT_DET_ENABLE (TSC_CTRL_DET_INTEN) /*!< Enable TSC detect interrupt */
+#define TSC_IT_DET_DISABLE (0UL) /*!< Disable TSC detect interrupt */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_Out
+ */
+#define TSC_OUT_PIN (0x00000000U) /*!< TSC output to TSC_OUT pin */
+#define TSC_OUT_TIM4_ETR (0x1UL << TSC_CTRL_TM4_ETR_Pos) /*!< TSC output to TIM4 ETR */
+#define TSC_OUT_TIM2_ETR (0x2UL << TSC_CTRL_TM4_ETR_Pos) /*!< TSC output to TIM2 ETR and TIM2 CH1*/
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_Flag
+ */
+#define TSC_FLAG_HW (0x1UL << TSC_CTRL_HW_DET_ST_Pos) /*!< Flag of hardware detect mode */
+
+#define TSC_FLAG_GREAT_DET (0x1UL << TSC_STS_GREAT_DET_Pos) /*!< Flag of great detect type */
+#define TSC_FLAG_LESS_DET (0x1UL << TSC_STS_LESS_DET_Pos) /*!< Flag of less detect type */
+#define TSC_FLAG_PERIOD_DET (TSC_FLAG_GREAT_DET|TSC_FLAG_LESS_DET) /*!< Flag of period detect type */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_SW_Detect
+ */
+#define TSC_SW_MODE_DISABLE (0x00000000U) /*!< Disable software detect mode */
+#define TSC_SW_MODE_ENABLE (0x1UL << TSC_ANA_CTRL_SW_TSC_EN_Pos) /*!< Enable software detect mode */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_PadOption
+ */
+#define TSC_PAD_INTERNAL_RES (0x00000000U) /*!< Use internal resistor */
+#define TSC_PAD_EXTERNAL_RES (0x1UL << TSC_ANA_SEL_PAD_OPT_Pos) /*!< Use external resistor */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_PadSpeed
+ */
+#define TSC_PAD_SPEED_0 (0x00000000U) /*!< Low speed,about 100K */
+#define TSC_PAD_SPEED_1 (0x1UL << TSC_ANA_SEL_SP_OPT_Pos) /*!< Middle spped */
+#define TSC_PAD_SPEED_2 (0x2UL << TSC_ANA_SEL_SP_OPT_Pos) /*!< Middle spped */
+#define TSC_PAD_SPEED_3 (0x3UL << TSC_ANA_SEL_SP_OPT_Pos) /*!< Middle spped */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_Constant
+ */
+#define TSC_CHN_SEL_ALL (TSC_CHNEN_CHN_SELx_Msk)
+#define MAX_TSC_HW_CHN (24) /*Maximum number of tsc pin*/
+#define MAX_TSC_THRESHOLD_BASE (2047) /*Maximum detect base value of threshold*/
+#define MAX_TSC_THRESHOLD_DELTA (255) /*Maximum detect delta value of threshold*/
+#define TSC_TIMEOUT (0x01000000) /*TSC normal timeout */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_DetectMode
+ */
+#define TSC_HW_DETECT_MODE (0x00000001U) /*TSC hardware detect mode*/
+#define TSC_SW_DETECT_MODE (0x00000000U) /*TSC software detect mode*/
+/**
+ * @
+ */
+
+/* TSC Exported macros -----------------------------------------------------------*/
+/** @defgroup TSC_Exported_Macros
+ * @{
+ */
+
+/** @brief Enable the TSC HW detect mode
+ * @param None
+ * @retval None
+ */
+#define __TSC_HW_ENABLE() SET_BIT(TSC->CTRL, TSC_HW_DET_MODE_ENABLE)
+
+/** @brief Disable the TSC HW detect mode
+ * @param None
+ * @retval None
+ */
+#define __TSC_HW_DISABLE() CLEAR_BIT(TSC->CTRL, TSC_HW_DET_MODE_ENABLE)
+
+/** @brief Config TSC detect period for HW detect mode
+ * @param __PERIOD__ specifies the TSC detect period during HW detect mode
+ * @arg TSC_DET_PERIOD_8: Detect period = 8/TSC_CLK
+ * @arg TSC_DET_PERIOD_16: Detect Period = 1/TSC_CLK
+ * @arg TSC_DET_PERIOD_24: Detect Period = 2/TSC_CLK
+ * @arg TSC_DET_PERIOD_32: Detect Period = 3/TSC_CLK
+ * @arg TSC_DET_PERIOD_40: Detect Period = 4/TSC_CLK
+ * @arg TSC_DET_PERIOD_48: Detect Period = 5/TSC_CLK
+ * @arg TSC_DET_PERIOD_56: Detect Period = 6/TSC_CLK
+ * @arg TSC_DET_PERIOD_64: Detect Period = 7/TSC_CLK
+ * @arg TSC_DET_PERIOD_72: Detect Period = 7/TSC_CLK
+ * @arg TSC_DET_PERIOD_80: Detect Period = 7/TSC_CLK
+ * @arg TSC_DET_PERIOD_88: Detect Period = 7/TSC_CLK
+ * @arg TSC_DET_PERIOD_96: Detect Period = 7/TSC_CLK
+ * @arg TSC_DET_PERIOD_104:Detect Period = 7/TSC_CLK
+ * @retval None
+ */
+#define __TSC_PERIOD_CONFIG(__PERIOD__) MODIFY_REG(TSC->CTRL, TSC_CTRL_DET_PERIOD_Msk,__PERIOD__)
+
+/** @brief Config TSC detect filter for HW detect mode
+ * @param __FILTER__ specifies the least usefull continuous samples during HW detect mode
+ * @arg TSC_DET_FILTER_1: Detect filter = 1 pulse
+ * @arg TSC_DET_FILTER_2: Detect filter = 2 pulse
+ * @arg TSC_DET_FILTER_3: Detect filter = 3 pulse
+ * @arg TSC_DET_FILTER_4: Detect filter = 4 pulse
+ * @retval None
+ */
+#define __TSC_FILTER_CONFIG(__FILTER__) MODIFY_REG(TSC->CTRL, TSC_CTRL_DET_FILTER_Msk,__FILTER__)
+
+/** @brief Config TSC detect type for HW detect mode,less great or both
+ * @param __TYPE__ specifies the detect type of a sample during HW detect mode
+ * @arg TSC_DET_TYPE_NONE: Detect disable
+ * @arg TSC_DET_TYPE_LESS: Pulse number must be greater than the threshold(basee-delta) during a sample time
+ * @arg TSC_DET_TYPE_GREAT: Pulse number must be less than the threshold(basee+delta) during a sample time
+ * @arg TSC_DET_TYPE_PERIOD:Pulse number must be greater than (basee-delta)
+ and also be less than (basee+delta) during a sample time
+ * @retval None
+ */
+#define __TSC_LESS_GREAT_CONFIG(__TYPE__) MODIFY_REG(TSC->CTRL, \
+ (TSC_CTRL_LESS_DET_SEL_Msk|TSC_CTRL_GREAT_DET_SEL_Msk), \
+ __TYPE__)
+
+/** @brief Enable TSC interrupt
+ * @param None
+ * @retval None
+ */
+#define __TSC_INT_ENABLE() SET_BIT(TSC->CTRL, TSC_IT_DET_ENABLE)
+
+/** @brief Disable TSC interrupt
+ * @param None
+ * @retval None
+ */
+#define __TSC_INT_DISABLE() CLEAR_BIT(TSC->CTRL, TSC_IT_DET_ENABLE)
+
+/** @brief Config the TSC output
+ * @param __OUT__ specifies where the TSC output should go
+ * @arg TSC_OUT_PIN: TSC output to the TSC_OUT pin
+ * @arg TSC_OUT_TIM4_ETR: TSC output to TIM4 as ETR
+ * @arg TSC_OUT_TIM2_ETR: TSC output to TIM2 as ETR
+ * @retval None
+ */
+#define __TSC_OUT_CONFIG(__OUT__) MODIFY_REG( TSC->CTRL, \
+ (TSC_CTRL_TM4_ETR_Msk|TSC_CTRL_TM2_ETR_CH1_Msk),\
+ __OUT__)
+
+/** @brief Config the TSC channel
+ * @param __CHN__ specifies the pin of channels used for detect
+ * This parameter:bit[0:23] used,bit[24:31] must be 0
+ * bitx: TSC channel x
+ * @retval None
+ */
+#define __TSC_CHN_CONFIG(__CHN__) WRITE_REG(TSC->CHNEN, __CHN__)
+
+/** @brief Enable the TSC SW detect mode
+ * @param None
+ * @retval None
+ */
+#define __TSC_SW_ENABLE() SET_BIT(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_TSC_EN)
+
+/** @brief Disable the TSC SW detect mode
+ * @param None
+ * @retval None
+ */
+#define __TSC_SW_DISABLE() CLEAR_BIT(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_TSC_EN)
+
+/** @brief Config the detect channel number during SW detect mode
+ * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN
+ * @retval None
+ */
+#define __TSC_SW_CHN_NUM_CONFIG(__NUM__) MODIFY_REG(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_PAD_MUX_Msk,__NUM__)
+
+/** @brief Config the pad charge type
+ * @param __OPT__ specifies which resistor is used for charge
+ * @arg TSC_PAD_INTERNAL_RES: Internal resistor is used
+ * @arg TSC_PAD_EXTERNAL_RES: External resistor is used
+ * @retval None
+ */
+#define __TSC_PAD_OPT_CONFIG(__OPT__) MODIFY_REG(TSC->ANA_SEL, TSC_ANA_SEL_PAD_OPT_Msk,__OPT__)
+
+/** @brief Config TSC speed
+ * @param __SPEED__ specifies the TSC speed range
+ * @arg TSC_PAD_SPEED_0: Low speed
+ * @arg TSC_PAD_SPEED_1: Middle speed
+ * @arg TSC_PAD_SPEED_2: Middle speed
+ * @arg TSC_PAD_SPEED_3: High speed
+ * @retval None
+ */
+#define __TSC_PAD_SPEED_CONFIG(__SPEED__) MODIFY_REG(TSC->ANA_SEL, TSC_ANA_SEL_SP_OPT_Msk,__SPEED__)
+
+
+/** @brief Check if the HW detect mode is enable
+ * @param None
+ * @retval Current state of HW detect mode
+ */
+#define __TSC_GET_HW_MODE() (((TSC->CTRL) & TSC_FLAG_HW) == (TSC_FLAG_HW))
+
+/** @brief Check the detect type during HW detect mode
+ * @param __FLAG__ specifies the flag of detect type
+ * @arg TSC_FLAG_LESS_DET: Flag of less detect type
+ * @arg TSC_FLAG_GREAT_DET: Flag of great detect type
+ * @arg TSC_FLAG_PERIOD_DET: Flag of priod detect type
+ * @retval Current state of flag
+ */
+#define __TSC_GET_HW_DET_TYPE(__FLAG__) (((TSC->STS) & (__FLAG__))==(__FLAG__))
+
+/** @brief Get the number of channel which is detected now
+ * @param None
+ * @retval Current channel number
+ */
+#define __TSC_GET_CHN_NUMBER() (((TSC->STS) & TSC_STS_CHN_NUM_Msk) >> TSC_STS_CHN_NUM_Pos )
+
+/** @brief Get the count value of pulse
+ * @param None
+ * @retval Pulse count of current channel
+ */
+#define __TSC_GET_CHN_CNT() (((TSC->STS) & TSC_STS_CNT_VAL_Msk ) >> TSC_STS_CNT_VAL_Pos )
+
+/** @brief Get the base value of one channel
+ * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN
+ * @retval base value of the channel
+ */
+#define __TSC_GET_CHN_BASE(__NUM__) ((TSC->THRHD[(__NUM__)] & TSC_THRHDx_BASE_Msk ) >> TSC_THRHDx_BASE_Pos)
+
+/** @brief Get the delta value of one channel
+ * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN
+ * @retval delta value of the channel
+ */
+#define __TSC_GET_CHN_DELTA(__NUM__) ((TSC->THRHD[(__NUM__)] & TSC_THRHDx_DELTA_Msk ) >> TSC_THRHDx_DELTA_Pos )
+
+/** @brief Get the internal resist value of one channel
+ * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN
+ * @retval resist value of the channel
+ */
+#define __TSC_GET_CHN_RESIST(__NUM__) ((TSC->RESR[(__NUM__)>>3] >>(((__NUM__) & 0x7UL)*4)) & TSC_RESRx_CHN_RESIST_Msk)
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TSC_Private_Macros
+ * @{
+ */
+#define IS_TSC_DET_PERIOD(_PERIOD_) \
+ (((_PERIOD_)==TSC_DET_PERIOD_8) ||((_PERIOD_)==TSC_DET_PERIOD_16)||((_PERIOD_)==TSC_DET_PERIOD_24) \
+ ||((_PERIOD_)==TSC_DET_PERIOD_32)||((_PERIOD_)==TSC_DET_PERIOD_40)||((_PERIOD_)==TSC_DET_PERIOD_48) \
+ ||((_PERIOD_)==TSC_DET_PERIOD_56)||((_PERIOD_)==TSC_DET_PERIOD_64)||((_PERIOD_)==TSC_DET_PERIOD_72) \
+ ||((_PERIOD_)==TSC_DET_PERIOD_80)||((_PERIOD_)==TSC_DET_PERIOD_88)||((_PERIOD_)==TSC_DET_PERIOD_96) \
+ ||((_PERIOD_)==TSC_DET_PERIOD_104) )
+
+#define IS_TSC_FILTER(_FILTER_) \
+ ( ((_FILTER_)==TSC_DET_FILTER_1) ||((_FILTER_)==TSC_DET_FILTER_2)\
+ ||((_FILTER_)==TSC_DET_FILTER_3) ||((_FILTER_)==TSC_DET_FILTER_4) )
+
+#define IS_TSC_DET_MODE(_MODE_) \
+ ( ((_MODE_)==TSC_HW_DETECT_MODE) ||((_MODE_)==TSC_SW_DETECT_MODE) )
+
+#define IS_TSC_DET_TYPE(_TYPE_) \
+ ( ((_TYPE_)==TSC_DET_TYPE_GREAT) ||((_TYPE_)==TSC_DET_TYPE_LESS) \
+ ||((_TYPE_)==TSC_DET_TYPE_PERIOD)|| ((_TYPE_)==TSC_DET_TYPE_NONE) )
+
+#define IS_TSC_INT(_INT_) (((_INT_)==TSC_IT_DET_ENABLE)||((_INT_)==TSC_IT_DET_DISABLE))
+
+#define IS_TSC_OUT(_ETR_) (((_ETR_)==TSC_OUT_PIN)||((_ETR_)==TSC_OUT_TIM2_ETR)||((_ETR_)==TSC_OUT_TIM4_ETR))
+
+#define IS_TSC_CHN(_CHN_) (0==((_CHN_)&(~TSC_CHNEN_CHN_SELx_Msk)))
+
+#define IS_TSC_CHN_NUMBER(_NUM_) ((uint32_t)(_NUM_)BaudRate)))
+ - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
+
+ uint16_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref USART_Word_Length */
+
+ uint16_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref USART_Stop_Bits */
+
+ uint16_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint16_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref Mode */
+
+ uint16_t HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
+ or disabled.
+ This parameter can be a value of @ref USART_Hardware_Flow_Control */
+} USART_InitType;
+
+/**
+ * @brief USART Clock Init Structure definition
+ */
+
+typedef struct
+{
+ uint16_t Clock; /*!< Specifies whether the USART clock is enabled or disabled.
+ This parameter can be a value of @ref Clock */
+
+ uint16_t Polarity; /*!< Specifies the steady state value of the serial clock.
+ This parameter can be a value of @ref USART_Clock_Polarity */
+
+ uint16_t Phase; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref USART_Clock_Phase */
+
+ uint16_t LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref USART_Last_Bit */
+} USART_ClockInitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Exported_Constants
+ * @{
+ */
+
+#define IS_USART_ALL_PERIPH(PERIPH) \
+ (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3) || ((PERIPH) == UART4) || ((PERIPH) == UART5))
+
+#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3))
+
+#define IS_USART_1234_PERIPH(PERIPH) \
+ (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3) || ((PERIPH) == UART4))
+/** @addtogroup USART_Word_Length
+ * @{
+ */
+
+#define USART_WL_8B ((uint16_t)0x0000)
+#define USART_WL_9B ((uint16_t)0x1000)
+
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WL_8B) || ((LENGTH) == USART_WL_9B))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Stop_Bits
+ * @{
+ */
+
+#define USART_STPB_1 ((uint16_t)0x0000)
+#define USART_STPB_0_5 ((uint16_t)0x1000)
+#define USART_STPB_2 ((uint16_t)0x2000)
+#define USART_STPB_1_5 ((uint16_t)0x3000)
+#define IS_USART_STOPBITS(STOPBITS) \
+ (((STOPBITS) == USART_STPB_1) || ((STOPBITS) == USART_STPB_0_5) || ((STOPBITS) == USART_STPB_2) \
+ || ((STOPBITS) == USART_STPB_1_5))
+/**
+ * @}
+ */
+
+/** @addtogroup Parity
+ * @{
+ */
+
+#define USART_PE_NO ((uint16_t)0x0000)
+#define USART_PE_EVEN ((uint16_t)0x0400)
+#define USART_PE_ODD ((uint16_t)0x0600)
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PE_NO) || ((PARITY) == USART_PE_EVEN) || ((PARITY) == USART_PE_ODD))
+/**
+ * @}
+ */
+
+/** @addtogroup Mode
+ * @{
+ */
+
+#define USART_MODE_RX ((uint16_t)0x0004)
+#define USART_MODE_TX ((uint16_t)0x0008)
+#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Hardware_Flow_Control
+ * @{
+ */
+#define USART_HFCTRL_NONE ((uint16_t)0x0000)
+#define USART_HFCTRL_RTS ((uint16_t)0x0100)
+#define USART_HFCTRL_CTS ((uint16_t)0x0200)
+#define USART_HFCTRL_RTS_CTS ((uint16_t)0x0300)
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL) \
+ (((CONTROL) == USART_HFCTRL_NONE) || ((CONTROL) == USART_HFCTRL_RTS) || ((CONTROL) == USART_HFCTRL_CTS) \
+ || ((CONTROL) == USART_HFCTRL_RTS_CTS))
+/**
+ * @}
+ */
+
+/** @addtogroup Clock
+ * @{
+ */
+#define USART_CLK_DISABLE ((uint16_t)0x0000)
+#define USART_CLK_ENABLE ((uint16_t)0x0800)
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLK_DISABLE) || ((CLOCK) == USART_CLK_ENABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Clock_Polarity
+ * @{
+ */
+
+#define USART_CLKPOL_LOW ((uint16_t)0x0000)
+#define USART_CLKPOL_HIGH ((uint16_t)0x0400)
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CLKPOL_LOW) || ((CPOL) == USART_CLKPOL_HIGH))
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Clock_Phase
+ * @{
+ */
+
+#define USART_CLKPHA_1EDGE ((uint16_t)0x0000)
+#define USART_CLKPHA_2EDGE ((uint16_t)0x0200)
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CLKPHA_1EDGE) || ((CPHA) == USART_CLKPHA_2EDGE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Last_Bit
+ * @{
+ */
+
+#define USART_CLKLB_DISABLE ((uint16_t)0x0000)
+#define USART_CLKLB_ENABLE ((uint16_t)0x0100)
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_CLKLB_DISABLE) || ((LASTBIT) == USART_CLKLB_ENABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Interrupt_definition
+ * @{
+ */
+
+#define USART_INT_PEF ((uint16_t)0x0028)
+#define USART_INT_TXDE ((uint16_t)0x0727)
+#define USART_INT_TXC ((uint16_t)0x0626)
+#define USART_INT_RXDNE ((uint16_t)0x0525)
+#define USART_INT_IDLEF ((uint16_t)0x0424)
+#define USART_INT_LINBD ((uint16_t)0x0846)
+#define USART_INT_CTSF ((uint16_t)0x096A)
+#define USART_INT_ERRF ((uint16_t)0x0060)
+#define USART_INT_OREF ((uint16_t)0x0360)
+#define USART_INT_NEF ((uint16_t)0x0260)
+#define USART_INT_FEF ((uint16_t)0x0160)
+#define IS_USART_CFG_INT(IT) \
+ (((IT) == USART_INT_PEF) || ((IT) == USART_INT_TXDE) || ((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE) \
+ || ((IT) == USART_INT_IDLEF) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF) \
+ || ((IT) == USART_INT_ERRF))
+#define IS_USART_GET_INT(IT) \
+ (((IT) == USART_INT_PEF) || ((IT) == USART_INT_TXDE) || ((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE) \
+ || ((IT) == USART_INT_IDLEF) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF) || ((IT) == USART_INT_OREF) \
+ || ((IT) == USART_INT_NEF) || ((IT) == USART_INT_FEF))
+#define IS_USART_CLR_INT(IT) \
+ (((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_DMA_Requests
+ * @{
+ */
+
+#define USART_DMAREQ_TX ((uint16_t)0x0080)
+#define USART_DMAREQ_RX ((uint16_t)0x0040)
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_WakeUp_methods
+ * @{
+ */
+
+#define USART_WUM_IDLELINE ((uint16_t)0x0000)
+#define USART_WUM_ADDRMASK ((uint16_t)0x0800)
+#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WUM_IDLELINE) || ((WAKEUP) == USART_WUM_ADDRMASK))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_LIN_Break_Detection_Length
+ * @{
+ */
+
+#define USART_LINBDL_10B ((uint16_t)0x0000)
+#define USART_LINBDL_11B ((uint16_t)0x0020)
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == USART_LINBDL_10B) || ((LENGTH) == USART_LINBDL_11B))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_IrDA_Low_Power
+ * @{
+ */
+
+#define USART_IRDAMODE_LOWPPWER ((uint16_t)0x0004)
+#define USART_IRDAMODE_NORMAL ((uint16_t)0x0000)
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IRDAMODE_LOWPPWER) || ((MODE) == USART_IRDAMODE_NORMAL))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Flags
+ * @{
+ */
+
+#define USART_FLAG_CTSF ((uint16_t)0x0200)
+#define USART_FLAG_LINBD ((uint16_t)0x0100)
+#define USART_FLAG_TXDE ((uint16_t)0x0080)
+#define USART_FLAG_TXC ((uint16_t)0x0040)
+#define USART_FLAG_RXDNE ((uint16_t)0x0020)
+#define USART_FLAG_IDLEF ((uint16_t)0x0010)
+#define USART_FLAG_OREF ((uint16_t)0x0008)
+#define USART_FLAG_NEF ((uint16_t)0x0004)
+#define USART_FLAG_FEF ((uint16_t)0x0002)
+#define USART_FLAG_PEF ((uint16_t)0x0001)
+#define IS_USART_FLAG(FLAG) \
+ (((FLAG) == USART_FLAG_PEF) || ((FLAG) == USART_FLAG_TXDE) || ((FLAG) == USART_FLAG_TXC) \
+ || ((FLAG) == USART_FLAG_RXDNE) || ((FLAG) == USART_FLAG_IDLEF) || ((FLAG) == USART_FLAG_LINBD) \
+ || ((FLAG) == USART_FLAG_CTSF) || ((FLAG) == USART_FLAG_OREF) || ((FLAG) == USART_FLAG_NEF) \
+ || ((FLAG) == USART_FLAG_FEF))
+
+#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
+#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) \
+ ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) && ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \
+ || ((USART_FLAG) != USART_FLAG_CTSF))
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x00337F99))
+#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
+#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Exported_Functions
+ * @{
+ */
+
+void USART_DeInit(USART_Module* USARTx);
+void USART_Init(USART_Module* USARTx, USART_InitType* USART_InitStruct);
+void USART_StructInit(USART_InitType* USART_InitStruct);
+void USART_ClockInit(USART_Module* USARTx, USART_ClockInitType* USART_ClockInitStruct);
+void USART_ClockStructInit(USART_ClockInitType* USART_ClockInitStruct);
+void USART_Enable(USART_Module* USARTx, FunctionalState Cmd);
+void USART_ConfigInt(USART_Module* USARTx, uint16_t USART_INT, FunctionalState Cmd);
+void USART_EnableDMA(USART_Module* USARTx, uint16_t USART_DMAReq, FunctionalState Cmd);
+void USART_SetAddr(USART_Module* USARTx, uint8_t USART_Addr);
+void USART_ConfigWakeUpMode(USART_Module* USARTx, uint16_t USART_WakeUpMode);
+void USART_EnableRcvWakeUp(USART_Module* USARTx, FunctionalState Cmd);
+void USART_ConfigLINBreakDetectLength(USART_Module* USARTx, uint16_t USART_LINBreakDetectLength);
+void USART_EnableLIN(USART_Module* USARTx, FunctionalState Cmd);
+void USART_SendData(USART_Module* USARTx, uint16_t Data);
+uint16_t USART_ReceiveData(USART_Module* USARTx);
+void USART_SendBreak(USART_Module* USARTx);
+void USART_SetGuardTime(USART_Module* USARTx, uint8_t USART_GuardTime);
+void USART_SetPrescaler(USART_Module* USARTx, uint8_t USART_Prescaler);
+void USART_EnableSmartCard(USART_Module* USARTx, FunctionalState Cmd);
+void USART_SetSmartCardNACK(USART_Module* USARTx, FunctionalState Cmd);
+void USART_EnableHalfDuplex(USART_Module* USARTx, FunctionalState Cmd);
+void USART_ConfigIrDAMode(USART_Module* USARTx, uint16_t USART_IrDAMode);
+void USART_EnableIrDA(USART_Module* USARTx, FunctionalState Cmd);
+FlagStatus USART_GetFlagStatus(USART_Module* USARTx, uint16_t USART_FLAG);
+void USART_ClrFlag(USART_Module* USARTx, uint16_t USART_FLAG);
+INTStatus USART_GetIntStatus(USART_Module* USARTx, uint16_t USART_INT);
+void USART_ClrIntPendingBit(USART_Module* USARTx, uint16_t USART_INT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32L43X_USART_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_wwdg.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_wwdg.h
new file mode 100644
index 0000000000..17971e3b52
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_wwdg.h
@@ -0,0 +1,122 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_wwdg.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32L43X_WWDG_H__
+#define __N32L43X_WWDG_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32l43x.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup WWDG
+ * @{
+ */
+
+/** @addtogroup WWDG_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup WWDG_Prescaler
+ * @{
+ */
+
+#define WWDG_PRESCALER_DIV1 ((uint32_t)0x00000000)
+#define WWDG_PRESCALER_DIV2 ((uint32_t)0x00000080)
+#define WWDG_PRESCALER_DIV4 ((uint32_t)0x00000100)
+#define WWDG_PRESCALER_DIV8 ((uint32_t)0x00000180)
+#define IS_WWDG_PRESCALER_DIV(PRESCALER) \
+ (((PRESCALER) == WWDG_PRESCALER_DIV1) || ((PRESCALER) == WWDG_PRESCALER_DIV2) \
+ || ((PRESCALER) == WWDG_PRESCALER_DIV4) || ((PRESCALER) == WWDG_PRESCALER_DIV8))
+#define IS_WWDG_WVALUE(VALUE) ((VALUE) <= 0x7F)
+#define IS_WWDG_CNT(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Exported_Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Exported_Functions
+ * @{
+ */
+
+void WWDG_DeInit(void);
+void WWDG_SetPrescalerDiv(uint32_t WWDG_Prescaler);
+void WWDG_SetWValue(uint8_t WindowValue);
+void WWDG_EnableInt(void);
+void WWDG_SetCnt(uint8_t Counter);
+void WWDG_Enable(uint8_t Counter);
+FlagStatus WWDG_GetEWINTF(void);
+void WWDG_ClrEWINTF(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32L43X__WWDG_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/misc.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/misc.c
new file mode 100644
index 0000000000..fd866ca36a
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/misc.c
@@ -0,0 +1,229 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file misc.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "misc.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup MISC
+ * @brief MISC driver modules
+ * @{
+ */
+
+/** @addtogroup MISC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Private_Defines
+ * @{
+ */
+
+#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Configures the priority grouping: pre-emption priority and subpriority.
+ * @param NVIC_PriorityGroup specifies the priority grouping bits length.
+ * This parameter can be one of the following values:
+ * @arg NVIC_PriorityGroup_0 0 bits for pre-emption priority
+ * 4 bits for subpriority
+ * @arg NVIC_PriorityGroup_1 1 bits for pre-emption priority
+ * 3 bits for subpriority
+ * @arg NVIC_PriorityGroup_2 2 bits for pre-emption priority
+ * 2 bits for subpriority
+ * @arg NVIC_PriorityGroup_3 3 bits for pre-emption priority
+ * 1 bits for subpriority
+ * @arg NVIC_PriorityGroup_4 4 bits for pre-emption priority
+ * 0 bits for subpriority
+ */
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
+
+ /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
+ SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
+}
+
+/**
+ * @brief Initializes the NVIC peripheral according to the specified
+ * parameters in the NVIC_InitStruct.
+ * @param NVIC_InitStruct pointer to a NVIC_InitType structure that contains
+ * the configuration information for the specified NVIC peripheral.
+ */
+void NVIC_Init(NVIC_InitType* NVIC_InitStruct)
+{
+ uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
+
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
+ assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
+
+ if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+ {
+ /* Compute the Corresponding IRQ Priority --------------------------------*/
+ tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700)) >> 0x08;
+ tmppre = (0x4 - tmppriority);
+ tmpsub = tmpsub >> tmppriority;
+
+ tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
+ tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
+ tmppriority = tmppriority << 0x04;
+
+ NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
+
+ /* Enable the Selected IRQ Channels --------------------------------------*/
+ NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = (uint32_t)0x01
+ << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+ }
+ else
+ {
+ /* Disable the Selected IRQ Channels -------------------------------------*/
+ NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = (uint32_t)0x01
+ << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+ }
+}
+
+/**
+ * @brief Sets the vector table location and Offset.
+ * @param NVIC_VectTab specifies if the vector table is in RAM or FLASH memory.
+ * This parameter can be one of the following values:
+ * @arg NVIC_VectTab_RAM
+ * @arg NVIC_VectTab_FLASH
+ * @param Offset Vector Table base offset field. This value must be a multiple
+ * of 0x200.
+ */
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
+ assert_param(IS_NVIC_OFFSET(Offset));
+
+ SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
+}
+
+/**
+ * @brief Selects the condition for the system to enter low power mode.
+ * @param LowPowerMode Specifies the new mode for the system to enter low power mode.
+ * This parameter can be one of the following values:
+ * @arg NVIC_LP_SEVONPEND
+ * @arg NVIC_LP_SLEEPDEEP
+ * @arg NVIC_LP_SLEEPONEXIT
+ * @param Cmd new state of LP condition. This parameter can be: ENABLE or DISABLE.
+ */
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_LP(LowPowerMode));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ SCB->SCR |= LowPowerMode;
+ }
+ else
+ {
+ SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
+ }
+}
+
+/**
+ * @brief Configures the SysTick clock source.
+ * @param SysTick_CLKSource specifies the SysTick clock source.
+ * This parameter can be one of the following values:
+ * @arg SysTick_CLKSource_HCLK_Div8 AHB clock divided by 8 selected as SysTick clock source.
+ * @arg SysTick_CLKSource_HCLK AHB clock selected as SysTick clock source.
+ */
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
+ if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
+ {
+ SysTick->CTRL |= SysTick_CLKSource_HCLK;
+ }
+ else
+ {
+ SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_adc.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_adc.c
new file mode 100644
index 0000000000..1de5c13e58
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_adc.c
@@ -0,0 +1,1429 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_adc.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l43x_adc.h"
+#include "n32l43x_rcc.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @brief ADC driver modules
+ * @{
+ */
+
+/** @addtogroup ADC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Private_Defines
+ * @{
+ */
+
+/* ADC DISC_NUM mask */
+#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF)
+
+/* ADC DISC_EN mask */
+#define CTRL1_DISC_EN_SET ((uint32_t)0x00000800)
+#define CTRL1_DISC_EN_RESET ((uint32_t)0xFFFFF7FF)
+
+/* ADC INJ_AUTO mask */
+#define CR1_JAUTO_Set ((uint32_t)0x00000400)
+#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF)
+
+/* ADC INJ_DISC_EN mask */
+#define CTRL1_INJ_DISC_EN_SET ((uint32_t)0x00001000)
+#define CTRL1_INJ_DISC_EN_RESET ((uint32_t)0xFFFFEFFF)
+
+/* ADC AWDG_CH mask */
+#define CTRL1_AWDG_CH_RESET ((uint32_t)0xFFFFFFE0)
+
+/* ADC Analog watchdog enable mode mask */
+#define CTRL1_AWDG_MODE_RESET ((uint32_t)0xFF3FFDFF)
+
+/* CTRL1 register Mask */
+#define CTRL1_CLR_MASK ((uint32_t)0xFFF0FEFF)
+
+/* ADC AD_ON mask */
+#define CTRL2_AD_ON_SET ((uint32_t)0x00000001)
+#define CTRL2_AD_ON_RESET ((uint32_t)0xFFFFFFFE)
+
+/* ADC DMA mask */
+#define CTRL2_DMA_SET ((uint32_t)0x00000100)
+#define CTRL2_DMA_RESET ((uint32_t)0xFFFFFEFF)
+
+/* ADC RST_CALI mask */
+#define CTRL2_RST_CALI_SET ((uint32_t)0x00000008)
+
+/* ADC CAL mask */
+#define CTRL2_CAL_SET ((uint32_t)0x00000004)
+
+/* ADC SOFT_START mask */
+#define CTRL2_SOFT_START_SET ((uint32_t)0x00400000)
+
+/* ADC EXT_TRIG mask */
+#define CTRL2_EXT_TRIG_SET ((uint32_t)0x00100000)
+#define CTRL2_EXT_TRIG_RESET ((uint32_t)0xFFEFFFFF)
+
+/* ADC Software start mask */
+#define CTRL2_EXT_TRIG_SWSTART_SET ((uint32_t)0x00500000)
+#define CTRL2_EXT_TRIG_SWSTART_RESET ((uint32_t)0xFFAFFFFF)
+
+/* ADC INJ_EXT_SEL mask */
+#define CTRL2_INJ_EXT_SEL_RESET ((uint32_t)0xFFFF8FFF)
+
+/* ADC INJ_EXT_TRIG mask */
+#define CTRL2_INJ_EXT_TRIG_SET ((uint32_t)0x00008000)
+#define CTRL2_INJ_EXT_TRIG_RESET ((uint32_t)0xFFFF7FFF)
+
+/* ADC INJ_SWSTART mask */
+#define CTRL2_INJ_SWSTART_SET ((uint32_t)0x00200000)
+
+/* ADC injected software start mask */
+#define CTRL2_INJ_EXT_TRIG_JSWSTART_SET ((uint32_t)0x00208000)
+#define CTRL2_INJ_EXT_TRIG_JSWSTART_RESET ((uint32_t)0xFFDF7FFF)
+
+/* ADC TSPD mask */
+#define CTRL2_TSVREFE_SET ((uint32_t)0x00800000)
+#define CTRL2_TSVREFE_RESET ((uint32_t)0xFF7FFFFF)
+
+/* CTRL2 register Mask */
+#define CTRL2_CLR_MASK ((uint32_t)0xFFF1F7FD)
+
+/* ADC SQx mask */
+#define SQR4_SEQ_SET ((uint32_t)0x0000001F)
+#define SQR3_SEQ_SET ((uint32_t)0x0000001F)
+#define SQR2_SEQ_SET ((uint32_t)0x0000001F)
+#define SQR1_SEQ_SET ((uint32_t)0x0000001F)
+
+/* RSEQ1 register Mask */
+#define RSEQ1_CLR_MASK ((uint32_t)0xFF0FFFFF)
+
+/* ADC JSQx mask */
+#define JSEQ_JSQ_SET ((uint32_t)0x0000001F)
+
+/* ADC INJ_LEN mask */
+#define JSEQ_INJ_LEN_SET ((uint32_t)0x00300000)
+#define JSEQ_INJ_LEN_RESET ((uint32_t)0xFFCFFFFF)
+
+/* ADC SAMPTx mask */
+#define SAMPT1_SMP_SET ((uint32_t)0x00000007)
+#define SAMPT2_SMP_SET ((uint32_t)0x00000007)
+
+/* ADC JDATx registers offset */
+#define JDAT_OFFSET ((uint8_t)0x28)
+
+/* ADC1 DAT register base address */
+#define DAT_ADDR ((uint32_t)0x4001244C)
+
+/* ADC STS register mask */
+#define ADC_STS_RESERVE_MASK ((uint32_t)0x0000007F)
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the ADCx peripheral registers to their default reset values.
+ * @param ADCx where x can be 1, 2 ,3 or 4 to select the ADC peripheral.
+ */
+void ADC_DeInit(ADC_Module* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+
+ if (ADCx == ADC)
+ {
+ /* Enable ADC1 reset state */
+ RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_ADC, ENABLE);
+ /* Release ADC1 from reset state */
+ RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_ADC, DISABLE);
+ }
+}
+
+/**
+ * @brief Initializes the ADCx peripheral according to the specified parameters
+ * in the ADC_InitStruct.
+ * @param ADCx where x can be 1, 2 ,3 or 4 to select the ADC peripheral.
+ * @param ADC_InitStruct pointer to an ADC_InitType structure that contains
+ * the configuration information for the specified ADC peripheral.
+ */
+void ADC_Init(ADC_Module* ADCx, ADC_InitType* ADC_InitStruct)
+{
+ uint32_t tmpreg1 = 0;
+ uint8_t tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->MultiChEn));
+ assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ContinueConvEn));
+ assert_param(IsAdcExtTrig(ADC_InitStruct->ExtTrigSelect));
+ assert_param(IsAdcDatAlign(ADC_InitStruct->DatAlign));
+ assert_param(IsAdcSeqLenValid(ADC_InitStruct->ChsNumber));
+
+ /*---------------------------- ADCx CTRL1 Configuration -----------------*/
+ /* Get the ADCx CTRL1 value */
+ tmpreg1 = ADCx->CTRL1;
+ /* Clear DUALMOD and SCAN bits */
+ tmpreg1 &= CTRL1_CLR_MASK;
+ /* Configure ADCx: Dual mode and scan conversion mode */
+ /* Set DUALMOD bits according to WorkMode value */
+ /* Set SCAN bit according to MultiChEn value */
+ tmpreg1 |= (uint32_t)( ((uint32_t)ADC_InitStruct->MultiChEn << 8));
+ /* Write to ADCx CTRL1 */
+ ADCx->CTRL1 = tmpreg1;
+
+ /*---------------------------- ADCx CTRL2 Configuration -----------------*/
+ /* Get the ADCx CTRL2 value */
+ tmpreg1 = ADCx->CTRL2;
+ /* Clear CONT, ALIGN and EXTSEL bits */
+ tmpreg1 &= CTRL2_CLR_MASK;
+ /* Configure ADCx: external trigger event and continuous conversion mode */
+ /* Set ALIGN bit according to DatAlign value */
+ /* Set EXTSEL bits according to ExtTrigSelect value */
+ /* Set CONT bit according to ContinueConvEn value */
+ tmpreg1 |= (uint32_t)(ADC_InitStruct->DatAlign | ADC_InitStruct->ExtTrigSelect
+ | ((uint32_t)ADC_InitStruct->ContinueConvEn << 1));
+ /* Write to ADCx CTRL2 */
+ ADCx->CTRL2 = tmpreg1;
+
+ /*---------------------------- ADCx RSEQ1 Configuration -----------------*/
+ /* Get the ADCx RSEQ1 value */
+ tmpreg1 = ADCx->RSEQ1;
+ /* Clear L bits */
+ tmpreg1 &= RSEQ1_CLR_MASK;
+ /* Configure ADCx: regular channel sequence length */
+ /* Set L bits according to ChsNumber value */
+ tmpreg2 |= (uint8_t)(ADC_InitStruct->ChsNumber - (uint8_t)1);
+ tmpreg1 |= (uint32_t)tmpreg2 << 20;
+ /* Write to ADCx RSEQ1 */
+ ADCx->RSEQ1 = tmpreg1;
+}
+
+/**
+ * @brief Fills each ADC_InitStruct member with its default value.
+ * @param ADC_InitStruct pointer to an ADC_InitType structure which will be initialized.
+ */
+void ADC_InitStruct(ADC_InitType* ADC_InitStruct)
+{
+ /* Reset ADC init structure parameters values */
+ /* initialize the MultiChEn member */
+ ADC_InitStruct->MultiChEn = DISABLE;
+ /* Initialize the ContinueConvEn member */
+ ADC_InitStruct->ContinueConvEn = DISABLE;
+ /* Initialize the ExtTrigSelect member */
+ ADC_InitStruct->ExtTrigSelect = ADC_EXT_TRIGCONV_T1_CC1;
+ /* Initialize the DatAlign member */
+ ADC_InitStruct->DatAlign = ADC_DAT_ALIGN_R;
+ /* Initialize the ChsNumber member */
+ ADC_InitStruct->ChsNumber = 1;
+}
+
+/**
+ * @brief Enables or disables the specified ADC peripheral.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the ADCx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_Enable(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set the AD_ON bit to wake up the ADC from power down mode */
+ ADCx->CTRL2 |= CTRL2_AD_ON_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC peripheral */
+ ADCx->CTRL2 &= CTRL2_AD_ON_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified ADC DMA request.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC DMA transfer.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableDMA(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcDmaModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC DMA request */
+ ADCx->CTRL2 |= CTRL2_DMA_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC DMA request */
+ ADCx->CTRL2 &= CTRL2_DMA_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified ADC interrupts.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_IT specifies the ADC interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg ADC_INT_ENDC End of conversion interrupt mask
+ * @arg ADC_INT_AWD Analog watchdog interrupt mask
+ * @arg ADC_INT_JENDC End of injected conversion interrupt mask
+ * @param Cmd new state of the specified ADC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_ConfigInt(ADC_Module* ADCx, uint16_t ADC_IT, FunctionalState Cmd)
+{
+ uint8_t itmask = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ assert_param(IsAdcInt(ADC_IT));
+ /* Get the ADC IT index */
+ itmask = (uint8_t)ADC_IT;
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC interrupts */
+ ADCx->CTRL1 |= itmask;
+ }
+ else
+ {
+ /* Disable the selected ADC interrupts */
+ ADCx->CTRL1 &= (~(uint32_t)itmask);
+ }
+}
+
+
+/**
+ * @brief Starts the selected ADC calibration process.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ */
+void ADC_StartCalibration(ADC_Module* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ /* Enable the selected ADC calibration process */
+ if (ADCx->CALFACT==0)
+ ADCx->CTRL2 |= CTRL2_CAL_SET;
+}
+
+/**
+ * @brief Gets the selected ADC calibration status.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @return The new state of ADC calibration (SET or RESET).
+ */
+FlagStatus ADC_GetCalibrationStatus(ADC_Module* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ /* Check the status of CAL bit */
+ if ((ADCx->CTRL2 & CTRL2_CAL_SET) != (uint32_t)RESET)
+ {
+ /* CAL bit is set: calibration on going */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAL bit is reset: end of calibration */
+ bitstatus = RESET;
+ }
+ if (ADCx->CALFACT!=0)
+ bitstatus = RESET;
+ /* Return the CAL bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Enables or disables the selected ADC software start conversion .
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC software start conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableSoftwareStartConv(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC conversion on external event and start the selected
+ ADC conversion */
+ ADCx->CTRL2 |= CTRL2_EXT_TRIG_SWSTART_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC conversion on external event and stop the selected
+ ADC conversion */
+ ADCx->CTRL2 &= CTRL2_EXT_TRIG_SWSTART_RESET;
+ }
+}
+
+/**
+ * @brief Gets the selected ADC Software start conversion Status.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @return The new state of ADC software start conversion (SET or RESET).
+ */
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_Module* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ /* Check the status of SOFT_START bit */
+ if ((ADCx->CTRL2 & CTRL2_SOFT_START_SET) != (uint32_t)RESET)
+ {
+ /* SOFT_START bit is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* SOFT_START bit is reset */
+ bitstatus = RESET;
+ }
+ /* Return the SOFT_START bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Configures the discontinuous mode for the selected ADC regular
+ * group channel.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Number specifies the discontinuous mode regular channel
+ * count value. This number must be between 1 and 8.
+ */
+void ADC_ConfigDiscModeChannelCount(ADC_Module* ADCx, uint8_t Number)
+{
+ uint32_t tmpreg1 = 0;
+ uint32_t tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcSeqDiscNumberValid(Number));
+ /* Get the old register value */
+ tmpreg1 = ADCx->CTRL1;
+ /* Clear the old discontinuous mode channel count */
+ tmpreg1 &= CR1_DISCNUM_Reset;
+ /* Set the discontinuous mode channel count */
+ tmpreg2 = Number - 1;
+ tmpreg1 |= tmpreg2 << 13;
+ /* Store the new register value */
+ ADCx->CTRL1 = tmpreg1;
+}
+
+/**
+ * @brief Enables or disables the discontinuous mode on regular group
+ * channel for the specified ADC
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC discontinuous mode
+ * on regular group channel.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableDiscMode(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC regular discontinuous mode */
+ ADCx->CTRL1 |= CTRL1_DISC_EN_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC regular discontinuous mode */
+ ADCx->CTRL1 &= CTRL1_DISC_EN_RESET;
+ }
+}
+
+/**
+ * @brief Configures for the selected ADC regular channel its corresponding
+ * rank in the sequencer and its sample time.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_Channel the ADC channel to configure.
+ * This parameter can be one of the following values:
+ * @arg ADC_CH_0 ADC Channel0 selected
+ * @arg ADC_CH_1 ADC Channel1 selected
+ * @arg ADC_CH_2 ADC Channel2 selected
+ * @arg ADC_CH_3 ADC Channel3 selected
+ * @arg ADC_CH_4 ADC Channel4 selected
+ * @arg ADC_CH_5 ADC Channel5 selected
+ * @arg ADC_CH_6 ADC Channel6 selected
+ * @arg ADC_CH_7 ADC Channel7 selected
+ * @arg ADC_CH_8 ADC Channel8 selected
+ * @arg ADC_CH_9 ADC Channel9 selected
+ * @arg ADC_CH_10 ADC Channel10 selected
+ * @arg ADC_CH_11 ADC Channel11 selected
+ * @arg ADC_CH_12 ADC Channel12 selected
+ * @arg ADC_CH_13 ADC Channel13 selected
+ * @arg ADC_CH_14 ADC Channel14 selected
+ * @arg ADC_CH_15 ADC Channel15 selected
+ * @arg ADC_CH_16 ADC Channel16 selected
+ * @arg ADC_CH_17 ADC Channel17 selected
+ * @arg ADC_CH_18 ADC Channel18 selected
+ * @param Rank The rank in the regular group sequencer. This parameter must be between 1 to 16.
+ * @param ADC_SampleTime The sample time value to be set for the selected channel.
+ * This parameter can be one of the following values:
+ * @arg ADC_SAMP_TIME_1CYCLES5 Sample time equal to 1.5 cycles
+ * @arg ADC_SAMP_TIME_7CYCLES5 Sample time equal to 7.5 cycles
+ * @arg ADC_SAMP_TIME_13CYCLES5 Sample time equal to 13.5 cycles
+ * @arg ADC_SAMP_TIME_28CYCLES5 Sample time equal to 28.5 cycles
+ * @arg ADC_SAMP_TIME_41CYCLES5 Sample time equal to 41.5 cycles
+ * @arg ADC_SAMP_TIME_55CYCLES5 Sample time equal to 55.5 cycles
+ * @arg ADC_SAMP_TIME_71CYCLES5 Sample time equal to 71.5 cycles
+ * @arg ADC_SAMP_TIME_239CYCLES5 Sample time equal to 239.5 cycles
+ */
+void ADC_ConfigRegularChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcChannel(ADC_Channel));
+ assert_param(IsAdcReqRankValid(Rank));
+ assert_param(IsAdcSampleTime(ADC_SampleTime));
+
+ if (ADC_Channel == ADC_CH_18)
+ {
+ tmpreg1 = ADCx->SAMPT3;
+ tmpreg1 &= (~0x00000007);
+ tmpreg1 |= ADC_SampleTime;
+ ADCx->SAMPT3 = tmpreg1;
+ }
+ if (ADC_Channel > ADC_CH_9) /* if ADC_CH_10 ... ADC_CH_17 is selected */
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SAMPT1;
+ /* Calculate the mask to clear */
+ tmpreg2 = SAMPT1_SMP_SET << (3 * (ADC_Channel - 10));
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SAMPT1 = tmpreg1;
+ }
+ else /* ADC_Channel include in ADC_Channel_[0..9] */
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SAMPT2;
+ /* Calculate the mask to clear */
+ tmpreg2 = SAMPT2_SMP_SET << (3 * ADC_Channel);
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SAMPT2 = tmpreg1;
+ }
+ /* For Rank 1 to 6 */
+ if (Rank < 7)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->RSEQ3;
+ /* Calculate the mask to clear */
+ tmpreg2 = SQR3_SEQ_SET << (5 * (Rank - 1));
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->RSEQ3 = tmpreg1;
+ }
+ /* For Rank 7 to 12 */
+ else if (Rank < 13)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->RSEQ2;
+ /* Calculate the mask to clear */
+ tmpreg2 = SQR2_SEQ_SET << (5 * (Rank - 7));
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->RSEQ2 = tmpreg1;
+ }
+ /* For Rank 13 to 16 */
+ else
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->RSEQ1;
+ /* Calculate the mask to clear */
+ tmpreg2 = SQR1_SEQ_SET << (5 * (Rank - 13));
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->RSEQ1 = tmpreg1;
+ }
+}
+
+/**
+ * @brief Enables or disables the ADCx conversion through external trigger.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC external trigger start of conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableExternalTrigConv(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC conversion on external event */
+ ADCx->CTRL2 |= CTRL2_EXT_TRIG_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC conversion on external event */
+ ADCx->CTRL2 &= CTRL2_EXT_TRIG_RESET;
+ }
+}
+
+/**
+ * @brief Returns the last ADCx conversion result data for regular channel.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @return The Data conversion value.
+ */
+uint16_t ADC_GetDat(ADC_Module* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ /* Return the selected ADC conversion value */
+ return (uint16_t)ADCx->DAT;
+}
+
+/**
+ * @brief Enables or disables the selected ADC automatic injected group
+ * conversion after regular one.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC auto injected conversion
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableAutoInjectedConv(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC automatic injected group conversion */
+ ADCx->CTRL1 |= CR1_JAUTO_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC automatic injected group conversion */
+ ADCx->CTRL1 &= CR1_JAUTO_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the discontinuous mode for injected group
+ * channel for the specified ADC
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC discontinuous mode
+ * on injected group channel.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableInjectedDiscMode(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC injected discontinuous mode */
+ ADCx->CTRL1 |= CTRL1_INJ_DISC_EN_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC injected discontinuous mode */
+ ADCx->CTRL1 &= CTRL1_INJ_DISC_EN_RESET;
+ }
+}
+
+/**
+ * @brief Configures the ADCx external trigger for injected channels conversion.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_ExternalTrigInjecConv specifies the ADC trigger to start injected conversion.
+ * This parameter can be one of the following values:
+ * @arg ADC_EXT_TRIG_INJ_CONV_T1_TRGO Timer1 TRGO event selected (for ADC1, ADC2 and ADC3)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T1_CC4 Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T2_TRGO Timer2 TRGO event selected (for ADC1 and ADC2)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T2_CC1 Timer2 capture compare1 selected (for ADC1 and ADC2)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T3_CC4 Timer3 capture compare4 selected (for ADC1 and ADC2)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T4_TRGO Timer4 TRGO event selected (for ADC1 and ADC2)
+ * @arg ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4 External interrupt line 15 or Timer8
+ * capture compare4 event selected (for ADC1 and ADC2)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T4_CC3 Timer4 capture compare3 selected (for ADC3 only)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T8_CC2 Timer8 capture compare2 selected (for ADC3 only)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T8_CC4 Timer8 capture compare4 selected (for ADC3 only)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T5_TRGO Timer5 TRGO event selected (for ADC3 only)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T5_CC4 Timer5 capture compare4 selected (for ADC3 only)
+ * @arg ADC_EXT_TRIG_INJ_CONV_NONE Injected conversion started by software and not
+ * by external trigger (for ADC1, ADC2 and ADC3)
+ */
+void ADC_ConfigExternalTrigInjectedConv(ADC_Module* ADCx, uint32_t ADC_ExternalTrigInjecConv)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcExtInjTrig(ADC_ExternalTrigInjecConv));
+ /* Get the old register value */
+ tmpregister = ADCx->CTRL2;
+ /* Clear the old external event selection for injected group */
+ tmpregister &= CTRL2_INJ_EXT_SEL_RESET;
+ /* Set the external event selection for injected group */
+ tmpregister |= ADC_ExternalTrigInjecConv;
+ /* Store the new register value */
+ ADCx->CTRL2 = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the ADCx injected channels conversion through
+ * external trigger
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC external trigger start of
+ * injected conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableExternalTrigInjectedConv(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC external event selection for injected group */
+ ADCx->CTRL2 |= CTRL2_INJ_EXT_TRIG_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC external event selection for injected group */
+ ADCx->CTRL2 &= CTRL2_INJ_EXT_TRIG_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the selected ADC start of the injected
+ * channels conversion.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC software start injected conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableSoftwareStartInjectedConv(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC conversion for injected group on external event and start the selected
+ ADC injected conversion */
+ ADCx->CTRL2 |= CTRL2_INJ_EXT_TRIG_JSWSTART_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC conversion on external event for injected group and stop the selected
+ ADC injected conversion */
+ ADCx->CTRL2 &= CTRL2_INJ_EXT_TRIG_JSWSTART_RESET;
+ }
+}
+
+/**
+ * @brief Gets the selected ADC Software start injected conversion Status.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @return The new state of ADC software start injected conversion (SET or RESET).
+ */
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_Module* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ /* Check the status of INJ_SWSTART bit */
+ if ((ADCx->CTRL2 & CTRL2_INJ_SWSTART_SET) != (uint32_t)RESET)
+ {
+ /* INJ_SWSTART bit is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* INJ_SWSTART bit is reset */
+ bitstatus = RESET;
+ }
+ /* Return the INJ_SWSTART bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Configures for the selected ADC injected channel its corresponding
+ * rank in the sequencer and its sample time.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_Channel the ADC channel to configure.
+ * This parameter can be one of the following values:
+ * @arg ADC_CH_0 ADC Channel0 selected
+ * @arg ADC_CH_1 ADC Channel1 selected
+ * @arg ADC_CH_2 ADC Channel2 selected
+ * @arg ADC_CH_3 ADC Channel3 selected
+ * @arg ADC_CH_4 ADC Channel4 selected
+ * @arg ADC_CH_5 ADC Channel5 selected
+ * @arg ADC_CH_6 ADC Channel6 selected
+ * @arg ADC_CH_7 ADC Channel7 selected
+ * @arg ADC_CH_8 ADC Channel8 selected
+ * @arg ADC_CH_9 ADC Channel9 selected
+ * @arg ADC_CH_10 ADC Channel10 selected
+ * @arg ADC_CH_11 ADC Channel11 selected
+ * @arg ADC_CH_12 ADC Channel12 selected
+ * @arg ADC_CH_13 ADC Channel13 selected
+ * @arg ADC_CH_14 ADC Channel14 selected
+ * @arg ADC_CH_15 ADC Channel15 selected
+ * @arg ADC_CH_16 ADC Channel16 selected
+ * @arg ADC_CH_17 ADC Channel17 selected
+ * @arg ADC_CH_18 ADC Channel18 selected
+ * @param Rank The rank in the injected group sequencer. This parameter must be between 1 and 4.
+ * @param ADC_SampleTime The sample time value to be set for the selected channel.
+ * This parameter can be one of the following values:
+ * @arg ADC_SAMP_TIME_1CYCLES5 Sample time equal to 1.5 cycles
+ * @arg ADC_SAMP_TIME_7CYCLES5 Sample time equal to 7.5 cycles
+ * @arg ADC_SAMP_TIME_13CYCLES5 Sample time equal to 13.5 cycles
+ * @arg ADC_SAMP_TIME_28CYCLES5 Sample time equal to 28.5 cycles
+ * @arg ADC_SAMP_TIME_41CYCLES5 Sample time equal to 41.5 cycles
+ * @arg ADC_SAMP_TIME_55CYCLES5 Sample time equal to 55.5 cycles
+ * @arg ADC_SAMP_TIME_71CYCLES5 Sample time equal to 71.5 cycles
+ * @arg ADC_SAMP_TIME_239CYCLES5 Sample time equal to 239.5 cycles
+ */
+void ADC_ConfigInjectedChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcChannel(ADC_Channel));
+ assert_param(IsAdcInjRankValid(Rank));
+ assert_param(IsAdcSampleTime(ADC_SampleTime));
+
+ if (ADC_Channel == ADC_CH_18)
+ {
+ tmpreg1 = ADCx->SAMPT3;
+ tmpreg1 &= (~0x00000007);
+ tmpreg1 |= ADC_SampleTime;
+ ADCx->SAMPT3 = tmpreg1;
+ }
+ else if (ADC_Channel > ADC_CH_9) /* if ADC_CH_10 ... ADC_CH_17 is selected */
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SAMPT1;
+ /* Calculate the mask to clear */
+ tmpreg2 = SAMPT1_SMP_SET << (3 * (ADC_Channel - 10));
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SAMPT1 = tmpreg1;
+ }
+ else /* ADC_Channel include in ADC_Channel_[0..9] */
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SAMPT2;
+ /* Calculate the mask to clear */
+ tmpreg2 = SAMPT2_SMP_SET << (3 * ADC_Channel);
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SAMPT2 = tmpreg1;
+ }
+ /* Rank configuration */
+ /* Get the old register value */
+ tmpreg1 = ADCx->JSEQ;
+ /* Get INJ_LEN value: Number = INJ_LEN+1 */
+ tmpreg3 = (tmpreg1 & JSEQ_INJ_LEN_SET) >> 20;
+ /* Calculate the mask to clear: ((Rank-1)+(4-INJ_LEN-1)) */
+ tmpreg2 = JSEQ_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+ /* Clear the old JSQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set: ((Rank-1)+(4-INJ_LEN-1)) */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+ /* Set the JSQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->JSEQ = tmpreg1;
+}
+
+/**
+ * @brief Configures the sequencer length for injected channels
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Length The sequencer length.
+ * This parameter must be a number between 1 to 4.
+ */
+void ADC_ConfigInjectedSequencerLength(ADC_Module* ADCx, uint8_t Length)
+{
+ uint32_t tmpreg1 = 0;
+ uint32_t tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcInjLenValid(Length));
+
+ /* Get the old register value */
+ tmpreg1 = ADCx->JSEQ;
+ /* Clear the old injected sequnence lenght INJ_LEN bits */
+ tmpreg1 &= JSEQ_INJ_LEN_RESET;
+ /* Set the injected sequnence lenght INJ_LEN bits */
+ tmpreg2 = Length - 1;
+ tmpreg1 |= tmpreg2 << 20;
+ /* Store the new register value */
+ ADCx->JSEQ = tmpreg1;
+}
+
+/**
+ * @brief Set the injected channels conversion value offset
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_InjectedChannel the ADC injected channel to set its offset.
+ * This parameter can be one of the following values:
+ * @arg ADC_INJ_CH_1 Injected Channel1 selected
+ * @arg ADC_INJ_CH_2 Injected Channel2 selected
+ * @arg ADC_INJ_CH_3 Injected Channel3 selected
+ * @arg ADC_INJ_CH_4 Injected Channel4 selected
+ * @param Offset the offset value for the selected ADC injected channel
+ * This parameter must be a 12bit value.
+ */
+void ADC_SetInjectedOffsetDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcInjCh(ADC_InjectedChannel));
+ assert_param(IsAdcOffsetValid(Offset));
+
+ tmp = (uint32_t)ADCx;
+ tmp += ADC_InjectedChannel;
+
+ /* Set the selected injected channel data offset */
+ *(__IO uint32_t*)tmp = (uint32_t)Offset;
+}
+
+/**
+ * @brief Returns the ADC injected channel conversion result
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_InjectedChannel the converted ADC injected channel.
+ * This parameter can be one of the following values:
+ * @arg ADC_INJ_CH_1 Injected Channel1 selected
+ * @arg ADC_INJ_CH_2 Injected Channel2 selected
+ * @arg ADC_INJ_CH_3 Injected Channel3 selected
+ * @arg ADC_INJ_CH_4 Injected Channel4 selected
+ * @return The Data conversion value.
+ */
+uint16_t ADC_GetInjectedConversionDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcInjCh(ADC_InjectedChannel));
+
+ tmp = (uint32_t)ADCx;
+ tmp += ADC_InjectedChannel + JDAT_OFFSET;
+
+ /* Returns the selected injected channel conversion data value */
+ return (uint16_t)(*(__IO uint32_t*)tmp);
+}
+
+/**
+ * @brief Enables or disables the analog watchdog on single/all regular
+ * or injected channels
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_AnalogWatchdog the ADC analog watchdog configuration.
+ * This parameter can be one of the following values:
+ * @arg ADC_ANALOG_WTDG_SINGLEREG_ENABLE Analog watchdog on a single regular channel
+ * @arg ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE Analog watchdog on a single injected channel
+ * @arg ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE Analog watchdog on a single regular or injected channel
+ * @arg ADC_ANALOG_WTDG_ALLREG_ENABLE Analog watchdog on all regular channel
+ * @arg ADC_ANALOG_WTDG_ALLINJEC_ENABLE Analog watchdog on all injected channel
+ * @arg ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE Analog watchdog on all regular and injected channels
+ * @arg ADC_ANALOG_WTDG_NONE No channel guarded by the analog watchdog
+ */
+void ADC_ConfigAnalogWatchdogWorkChannelType(ADC_Module* ADCx, uint32_t ADC_AnalogWatchdog)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcAnalogWatchdog(ADC_AnalogWatchdog));
+ /* Get the old register value */
+ tmpregister = ADCx->CTRL1;
+ /* Clear AWDEN, AWDENJ and AWDSGL bits */
+ tmpregister &= CTRL1_AWDG_MODE_RESET;
+ /* Set the analog watchdog enable mode */
+ tmpregister |= ADC_AnalogWatchdog;
+ /* Store the new register value */
+ ADCx->CTRL1 = tmpregister;
+}
+
+/**
+ * @brief Configures the high and low thresholds of the analog watchdog.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param HighThreshold the ADC analog watchdog High threshold value.
+ * This parameter must be a 12bit value.
+ * @param LowThreshold the ADC analog watchdog Low threshold value.
+ * This parameter must be a 12bit value.
+ */
+void ADC_ConfigAnalogWatchdogThresholds(ADC_Module* ADCx, uint16_t HighThreshold, uint16_t LowThreshold)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcValid(HighThreshold));
+ assert_param(IsAdcValid(LowThreshold));
+ /* Set the ADCx high threshold */
+ ADCx->WDGHIGH = HighThreshold;
+ /* Set the ADCx low threshold */
+ ADCx->WDGLOW = LowThreshold;
+}
+
+/**
+ * @brief Configures the analog watchdog guarded single channel
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_Channel the ADC channel to configure for the analog watchdog.
+ * This parameter can be one of the following values:
+ * @arg ADC_CH_0 ADC Channel0 selected
+ * @arg ADC_CH_1 ADC Channel1 selected
+ * @arg ADC_CH_2 ADC Channel2 selected
+ * @arg ADC_CH_3 ADC Channel3 selected
+ * @arg ADC_CH_4 ADC Channel4 selected
+ * @arg ADC_CH_5 ADC Channel5 selected
+ * @arg ADC_CH_6 ADC Channel6 selected
+ * @arg ADC_CH_7 ADC Channel7 selected
+ * @arg ADC_CH_8 ADC Channel8 selected
+ * @arg ADC_CH_9 ADC Channel9 selected
+ * @arg ADC_CH_10 ADC Channel10 selected
+ * @arg ADC_CH_11 ADC Channel11 selected
+ * @arg ADC_CH_12 ADC Channel12 selected
+ * @arg ADC_CH_13 ADC Channel13 selected
+ * @arg ADC_CH_14 ADC Channel14 selected
+ * @arg ADC_CH_15 ADC Channel15 selected
+ * @arg ADC_CH_16 ADC Channel16 selected
+ * @arg ADC_CH_17 ADC Channel17 selected
+ * @arg ADC_CH_18 ADC Channel18 selected
+ */
+void ADC_ConfigAnalogWatchdogSingleChannel(ADC_Module* ADCx, uint8_t ADC_Channel)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcChannel(ADC_Channel));
+ /* Get the old register value */
+ tmpregister = ADCx->CTRL1;
+ /* Clear the Analog watchdog channel select bits */
+ tmpregister &= CTRL1_AWDG_CH_RESET;
+ /* Set the Analog watchdog channel */
+ tmpregister |= ADC_Channel;
+ /* Store the new register value */
+ ADCx->CTRL1 = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the temperature sensor and Vrefint channel.
+ * @param Cmd new state of the temperature sensor.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableTempSensorVrefint(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the temperature sensor and Vrefint channel*/
+ ADC->CTRL2 |= CTRL2_TSVREFE_SET;
+ _EnVref1p2()
+ _EnVref2p0()
+ }
+ else
+ {
+ /* Disable the temperature sensor and Vrefint channel*/
+ ADC->CTRL2 &= CTRL2_TSVREFE_RESET;
+ _DisVref1p2()
+ _DisVref2p0()
+ }
+}
+
+/**
+ * @brief Checks whether the specified ADC flag is set or not.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_FLAG specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg ADC_FLAG_AWDG Analog watchdog flag
+ * @arg ADC_FLAG_ENDC End of conversion flag
+ * @arg ADC_FLAG_JENDC End of injected group conversion flag
+ * @arg ADC_FLAG_JSTR Start of injected group conversion flag
+ * @arg ADC_FLAG_STR Start of regular group conversion flag
+ * @return The new state of ADC_FLAG (SET or RESET).
+ */
+FlagStatus ADC_GetFlagStatus(ADC_Module* ADCx, uint8_t ADC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcGetFlag(ADC_FLAG));
+ /* Check the status of the specified ADC flag */
+ if ((ADCx->STS & ADC_FLAG) != (uint8_t)RESET)
+ {
+ /* ADC_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* ADC_FLAG is reset */
+ bitstatus = RESET;
+ }
+ /* Return the ADC_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the ADCx's pending flags.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_FLAG specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg ADC_FLAG_AWDG Analog watchdog flag
+ * @arg ADC_FLAG_ENDC End of conversion flag
+ * @arg ADC_FLAG_JENDC End of injected group conversion flag
+ * @arg ADC_FLAG_JSTR Start of injected group conversion flag
+ * @arg ADC_FLAG_STR Start of regular group conversion flag
+ */
+void ADC_ClearFlag(ADC_Module* ADCx, uint8_t ADC_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcClrFlag(ADC_FLAG));
+ /* Clear the selected ADC flags */
+ ADCx->STS = (~(uint32_t)ADC_FLAG & ADC_STS_RESERVE_MASK);
+}
+
+/**
+ * @brief Checks whether the specified ADC interrupt has occurred or not.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_IT specifies the ADC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg ADC_INT_ENDC End of conversion interrupt mask
+ * @arg ADC_INT_AWD Analog watchdog interrupt mask
+ * @arg ADC_INT_JENDC End of injected conversion interrupt mask
+ * @return The new state of ADC_IT (SET or RESET).
+ */
+INTStatus ADC_GetIntStatus(ADC_Module* ADCx, uint16_t ADC_IT)
+{
+ INTStatus bitstatus = RESET;
+ uint32_t itmask = 0, enablestatus = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcGetInt(ADC_IT));
+ /* Get the ADC IT index */
+ itmask = ADC_IT >> 8;
+ /* Get the ADC_IT enable bit status */
+ enablestatus = (ADCx->CTRL1 & (uint8_t)ADC_IT);
+ /* Check the status of the specified ADC interrupt */
+ if (((ADCx->STS & itmask) != (uint32_t)RESET) && enablestatus)
+ {
+ /* ADC_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* ADC_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the ADC_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the ADCx's interrupt pending bits.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_IT specifies the ADC interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg ADC_INT_ENDC End of conversion interrupt mask
+ * @arg ADC_INT_AWD Analog watchdog interrupt mask
+ * @arg ADC_INT_JENDC End of injected conversion interrupt mask
+ */
+void ADC_ClearIntPendingBit(ADC_Module* ADCx, uint16_t ADC_IT)
+{
+ uint8_t itmask = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcInt(ADC_IT));
+ /* Get the ADC IT index */
+ itmask = (uint8_t)(ADC_IT >> 8);
+ /* Clear the selected ADC interrupt pending bits */
+ ADCx->STS = (~(uint32_t)itmask & ADC_STS_RESERVE_MASK);
+}
+
+/**
+ * @brief Initializes the ADCx peripheral according to the specified parameters
+ * in the ADC_InitStructEx.
+ * @param ADCx where x can be 1, 2 ,3 or 4 to select the ADC peripheral.
+ * @param ADC_InitStructEx pointer to an ADC_InitTypeEx structure that contains
+ * the configuration information for the specified ADC peripheral.
+ */
+void ADC_InitEx(ADC_Module* ADCx, ADC_InitTypeEx* ADC_InitStructEx)
+{
+ uint32_t tmpregister = 0;
+ /*ADC_SAMPT3 samp time sele ,as sam 103 or 303 style*/
+ if (ADC_InitStructEx->Samp303Style)
+ ADCx->SAMPT3 |= ADC_SAMPT3_SAMPSEL_MSK;
+ else
+ ADCx->SAMPT3 &= (~ADC_SAMPT3_SAMPSEL_MSK);
+
+ /*intial ADC_CTRL3 once initiall config*/
+ tmpregister = ADCx->CTRL3;
+ if (ADC_InitStructEx->DeepPowerModEn)
+ tmpregister |= ADC_CTRL3_DPWMOD_MSK;
+ else
+ tmpregister &= (~ADC_CTRL3_DPWMOD_MSK);
+
+ if (ADC_InitStructEx->JendcIntEn)
+ tmpregister |= ADC_CTRL3_JENDCAIEN_MSK;
+ else
+ tmpregister &= (~ADC_CTRL3_JENDCAIEN_MSK);
+
+ if (ADC_InitStructEx->EndcIntEn)
+ tmpregister |= ADC_CTRL3_ENDCAIEN_MSK;
+ else
+ tmpregister &= (~ADC_CTRL3_ENDCAIEN_MSK);
+
+ if (ADC_InitStructEx->CalAtuoLoadEn)
+ tmpregister |= ADC_CTRL3_CALALD_MSK;
+ else
+ tmpregister &= (~ADC_CTRL3_CALALD_MSK);
+
+ if (ADC_InitStructEx->DifModCal)
+ tmpregister |= ADC_CTRL3_CALDIF_MSK;
+ else
+ tmpregister &= (~ADC_CTRL3_CALDIF_MSK);
+
+ tmpregister &= (~ADC_CTRL3_RES_MSK);
+ tmpregister |= ADC_InitStructEx->ResBit;
+
+ tmpregister &= (~ADC_CTRL3_CKMOD_MSK);
+ if (ADC_InitStructEx->ClkMode==ADC_CTRL3_CKMOD_PLL)
+ tmpregister |= ADC_CTRL3_CKMOD_MSK;
+
+ ADCx->CTRL3 = tmpregister;
+}
+/**
+ * @brief Checks whether the specified ADC flag is set or not.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_FLAG_NEW specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg ADC_FLAG_RDY ADC ready flag
+ * @arg ADC_FLAG_PD_RDY ADC powerdown ready flag
+ * @return The new state of ADC_FLAG_NEW (SET or RESET).
+ */
+FlagStatus ADC_GetFlagStatusNew(ADC_Module* ADCx, uint8_t ADC_FLAG_NEW)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcGetFlag(ADC_FLAG_NEW));
+ /* Check the status of the specified ADC flag */
+ if ((ADCx->CTRL3 & ADC_FLAG_NEW) != (uint8_t)RESET)
+ {
+ /* ADC_FLAG_NEW is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* ADC_FLAG_NEW is reset */
+ bitstatus = RESET;
+ }
+ /* Return the ADC_FLAG_NEW status */
+ return bitstatus;
+}
+/**
+ * @brief Set Adc calibration bypass or enable.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param en enable bypass calibration.
+ * This parameter can be one of the following values:
+ * @arg true bypass calibration
+ * @arg false not bypass calibration
+ */
+void ADC_SetBypassCalibration(ADC_Module* ADCx, FunctionalState en)
+{
+ uint32_t tmpregister = 0;
+
+ tmpregister = ADCx->CTRL3;
+ if (en)
+ tmpregister |= ADC_CTRL3_BPCAL_MSK;
+ else
+ tmpregister &= (~ADC_CTRL3_BPCAL_MSK);
+ ADCx->CTRL3 = tmpregister;
+}
+/**
+ * @brief Set Adc trans bits width.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ResultBitNum specifies num with adc trans width.
+ * This parameter can be one of the following values:
+ * @arg ADC_RST_BIT_12 12 bit trans
+ * @arg ADC_RST_BIT_10 10 bit trans
+ * @arg ADC_RST_BIT_8 8 bit trans
+ * @arg ADC_RESULT_BIT_6 6 bit trans
+ */
+void ADC_SetConvResultBitNum(ADC_Module* ADCx, uint32_t ResultBitNum)
+{
+ uint32_t tmpregister = 0;
+
+ tmpregister = ADCx->CTRL3;
+ tmpregister &= 0xFFFFFFFC;
+ tmpregister |= ResultBitNum;
+ ADCx->CTRL3 = tmpregister;
+ return;
+}
+/**
+ * @brief Set Adc Clock bits for AHB .
+ * @param ADCx where x can be 1 to select the ADC peripheral.
+ */
+void ADC_AHB_Clock_Mode_Config(ADC_Module* ADCx)
+{
+ ADCx->CTRL3 &= ADC_CLOCK_AHB;
+}
+
+/**
+ * @brief Set Adc Clock bits for PLL .
+ * @param ADCx where x can be 1 to select the ADC peripheral.
+ */
+void ADC_PLL_Clock_Mode_Config(ADC_Module* ADCx)
+{
+ ADCx->CTRL3 |= ADC_CLOCK_PLL;
+}
+
+/**
+ * @brief Configures the ADCHCLK prescaler.
+ * @param RCC_ADCHCLKPrescaler specifies the ADCHCLK prescaler.
+ * This parameter can be on of the following values:
+ * @arg RCC_ADCHCLK_DIV1 ADCHCLKPRE[3:0] = 0000, HCLK Clock Divided By 1
+ * @arg RCC_ADCHCLK_DIV2 ADCHCLKPRE[3:0] = 0001, HCLK Clock Divided By 2
+ * @arg RCC_ADCHCLK_DIV4 ADCHCLKPRE[3:0] = 0010, HCLK Clock Divided By 4
+ * @arg RCC_ADCHCLK_DIV6 ADCHCLKPRE[3:0] = 0011, HCLK Clock Divided By 6
+ * @arg RCC_ADCHCLK_DIV8 ADCHCLKPRE[3:0] = 0100, HCLK Clock Divided By 8
+ * @arg RCC_ADCHCLK_DIV10 ADCHCLKPRE[3:0] = 0101, HCLK Clock Divided By 10
+ * @arg RCC_ADCHCLK_DIV12 ADCHCLKPRE[3:0] = 0110, HCLK Clock Divided By 12
+ * @arg RCC_ADCHCLK_DIV16 ADCHCLKPRE[3:0] = 0111, HCLK Clock Divided By 16
+ * @arg RCC_ADCHCLK_DIV32 ADCHCLKPRE[3:0] = 1000, HCLK Clock Divided By 32
+ * @arg RCC_ADCHCLK_DIV32 ADCHCLKPRE[3:0] = others, HCLK Clock Divided By 32
+
+ * @arg RCC_ADCPLLCLK_DISABLE ADCPLLCLKPRES[4:0] = 0xxxx, ADC Pll Clock Disable
+ * @arg RCC_ADCPLLCLK_DIV1 ADCPLLCLKPRES[4:0] = 10000, Pll Clock Divided By 1
+ * @arg RCC_ADCPLLCLK_DIV2 ADCPLLCLKPRES[4:0] = 10001, Pll Clock Divided By 2
+ * @arg RCC_ADCPLLCLK_DIV4 ADCPLLCLKPRES[4:0] = 10010, Pll Clock Divided By 4
+ * @arg RCC_ADCPLLCLK_DIV6 ADCPLLCLKPRES[4:0] = 10011, Pll Clock Divided By 6
+ * @arg RCC_ADCPLLCLK_DIV8 ADCPLLCLKPRES[4:0] = 10100, Pll Clock Divided By 8
+ * @arg RCC_ADCPLLCLK_DIV10 ADCPLLCLKPRES[4:0] = 10101, Pll Clock Divided By 10
+ * @arg RCC_ADCPLLCLK_DIV12 ADCPLLCLKPRES[4:0] = 10110, Pll Clock Divided By 12
+ * @arg RCC_ADCPLLCLK_DIV16 ADCPLLCLKPRES[4:0] = 10111, Pll Clock Divided By 16
+ * @arg RCC_ADCPLLCLK_DIV32 ADCPLLCLKPRES[4:0] = 11000, Pll Clock Divided By 32
+ * @arg RCC_ADCPLLCLK_DIV64 ADCPLLCLKPRES[4:0] = 11001, Pll Clock Divided By 64
+ * @arg RCC_ADCPLLCLK_DIV128 ADCPLLCLKPRES[4:0] = 11010, Pll Clock Divided By 128
+ * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = 11011, Pll Clock Divided By 256
+ * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = others, Pll Clock Divided By 256
+ */
+void ADC_ConfigClk(ADC_CTRL3_CKMOD ADC_ClkMode, uint32_t RCC_ADCHCLKPrescaler)
+{
+ if (ADC_ClkMode==ADC_CTRL3_CKMOD_AHB){
+ RCC_ConfigAdcPllClk(RCC_ADCPLLCLK_DIV1, DISABLE);
+ RCC_ConfigAdcHclk(RCC_ADCHCLKPrescaler);
+ ADC_AHB_Clock_Mode_Config(ADC);
+ }else{
+ RCC_ConfigAdcPllClk(RCC_ADCHCLKPrescaler, ENABLE);
+ RCC_ConfigAdcHclk(RCC_ADCHCLK_DIV1);
+ ADC_PLL_Clock_Mode_Config(ADC);
+ }
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_can.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_can.c
new file mode 100644
index 0000000000..4386e0bc7d
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_can.c
@@ -0,0 +1,1372 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_can.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l43x_can.h"
+#include "n32l43x_rcc.h"
+
+/** @addtogroup N32L43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CAN
+ * @brief CAN driver modules
+ * @{
+ */
+
+/** @addtogroup CAN_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Private_Defines
+ * @{
+ */
+
+/* CAN Master Control Register bits */
+#define MCTRL_DBGF ((uint32_t)0x00010000) /* Debug freeze */
+#define MCTRL_MRST ((uint32_t)0x00010000) /* software master reset */
+
+/* CAN Mailbox Transmit Request */
+#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */
+
+/* CAN Filter Master Register bits */
+#define FMC_FINITM ((uint32_t)0x00000001) /* Filter init mode */
+
+/* Time out for INAK bit */
+#define INIAK_TIMEOUT ((uint32_t)0x0000FFFF)
+/* Time out for SLAK bit */
+#define SLPAK_TIMEOUT ((uint32_t)0x0000FFFF)
+
+/* Flags in TSTS register */
+#define CAN_FLAGS_TSTS ((uint32_t)0x08000000)
+/* Flags in RFF1 register */
+#define CAN_FLAGS_RFF1 ((uint32_t)0x04000000)
+/* Flags in RFF0 register */
+#define CAN_FLAGS_RFF0 ((uint32_t)0x02000000)
+/* Flags in MSTS register */
+#define CAN_FLAGS_MSTS ((uint32_t)0x01000000)
+/* Flags in ESTS register */
+#define CAN_FLAGS_ESTS ((uint32_t)0x00F00000)
+
+/* Mailboxes definition */
+#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
+#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
+#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
+
+#define CAN_MODE_MASK ((uint32_t)0x00000003)
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Private_FunctionPrototypes
+ * @{
+ */
+
+static INTStatus CheckINTStatus(uint32_t CAN_Reg, uint32_t Int_Bit);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the CAN peripheral registers to their default reset values.
+ * @param CANx.
+ */
+void CAN_DeInit(CAN_Module* CANx)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Enable CAN reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_CAN, ENABLE);
+ /* Release CAN from reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_CAN, DISABLE);
+}
+
+/**
+ * @brief Initializes the CAN peripheral according to the specified
+ * parameters in the CAN_InitParam.
+ * @param CAN to select the CAN peripheral.
+ * @param CAN_InitParam pointer to a CAN_InitType structure that
+ * contains the configuration information for the
+ * CAN peripheral.
+ * @return Constant indicates initialization succeed which will be
+ * CAN_InitSTS_Failed or CAN_InitSTS_Success.
+ */
+uint8_t CAN_Init(CAN_Module* CANx, CAN_InitType* CAN_InitParam)
+{
+ uint8_t InitStatus = CAN_InitSTS_Failed;
+ uint32_t wait_ack = 0x00000000;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->TTCM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->ABOM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->AWKUM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->NART));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->RFLM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->TXFP));
+ assert_param(IS_CAN_MODE(CAN_InitParam->OperatingMode));
+ assert_param(IS_CAN_RSJW(CAN_InitParam->RSJW));
+ assert_param(IS_CAN_TBS1(CAN_InitParam->TBS1));
+ assert_param(IS_CAN_TBS2(CAN_InitParam->TBS2));
+ assert_param(IS_CAN_BAUDRATEPRESCALER(CAN_InitParam->BaudRatePrescaler));
+
+ /* Exit from sleep mode */
+ CANx->MCTRL &= (~(uint32_t)CAN_MCTRL_SLPRQ);
+
+ /* Request initialisation */
+ CANx->MCTRL |= CAN_MCTRL_INIRQ;
+
+ /* Wait the acknowledge */
+ while (((CANx->MSTS & CAN_MSTS_INIAK) != CAN_MSTS_INIAK) && (wait_ack != INIAK_TIMEOUT))
+ {
+ wait_ack++;
+ }
+
+ /* Check acknowledge */
+ if ((CANx->MSTS & CAN_MSTS_INIAK) != CAN_MSTS_INIAK)
+ {
+ InitStatus = CAN_InitSTS_Failed;
+ }
+ else
+ {
+ /* Set the time triggered communication mode */
+ if (CAN_InitParam->TTCM == ENABLE)
+ {
+ CANx->MCTRL |= CAN_MCTRL_TTCM;
+ }
+ else
+ {
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_TTCM;
+ }
+
+ /* Set the automatic bus-off management */
+ if (CAN_InitParam->ABOM == ENABLE)
+ {
+ CANx->MCTRL |= CAN_MCTRL_ABOM;
+ }
+ else
+ {
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_ABOM;
+ }
+
+ /* Set the automatic wake-up mode */
+ if (CAN_InitParam->AWKUM == ENABLE)
+ {
+ CANx->MCTRL |= CAN_MCTRL_AWKUM;
+ }
+ else
+ {
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_AWKUM;
+ }
+
+ /* Set the no automatic retransmission */
+ if (CAN_InitParam->NART == ENABLE)
+ {
+ CANx->MCTRL |= CAN_MCTRL_NART;
+ }
+ else
+ {
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_NART;
+ }
+
+ /* Set the receive DATFIFO locked mode */
+ if (CAN_InitParam->RFLM == ENABLE)
+ {
+ CANx->MCTRL |= CAN_MCTRL_RFLM;
+ }
+ else
+ {
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_RFLM;
+ }
+
+ /* Set the transmit DATFIFO priority */
+ if (CAN_InitParam->TXFP == ENABLE)
+ {
+ CANx->MCTRL |= CAN_MCTRL_TXFP;
+ }
+ else
+ {
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_TXFP;
+ }
+
+ /* Set the bit timing register */
+ CANx->BTIM = (uint32_t)((uint32_t)CAN_InitParam->OperatingMode << 30) | ((uint32_t)CAN_InitParam->RSJW << 24)
+ | ((uint32_t)CAN_InitParam->TBS1 << 16) | ((uint32_t)CAN_InitParam->TBS2 << 20)
+ | ((uint32_t)CAN_InitParam->BaudRatePrescaler - 1);
+
+ /* Request leave initialisation */
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_INIRQ;
+
+ /* Wait the acknowledge */
+ wait_ack = 0;
+
+ while (((CANx->MSTS & CAN_MSTS_INIAK) == CAN_MSTS_INIAK) && (wait_ack != INIAK_TIMEOUT))
+ {
+ wait_ack++;
+ }
+
+ /* ...and check acknowledged */
+ if ((CANx->MSTS & CAN_MSTS_INIAK) == CAN_MSTS_INIAK)
+ {
+ InitStatus = CAN_InitSTS_Failed;
+ }
+ else
+ {
+ InitStatus = CAN_InitSTS_Success;
+ }
+ }
+
+ /* At this step, return the status of initialization */
+ return InitStatus;
+}
+
+/**
+ * @brief Initializes the CAN peripheral according to the specified
+ * parameters in the CAN_InitFilterStruct.
+ * @param CAN_InitFilterStruct pointer to a CAN_FilterInitType
+ * structure that contains the configuration
+ * information.
+ */
+void CAN_InitFilter(CAN_FilterInitType* CAN_InitFilterStruct)
+{
+ uint32_t filter_number_bit_pos = 0;
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_NUM(CAN_InitFilterStruct->Filter_Num));
+ assert_param(IS_CAN_FILTER_MODE(CAN_InitFilterStruct->Filter_Mode));
+ assert_param(IS_CAN_FILTER_SCALE(CAN_InitFilterStruct->Filter_Scale));
+ assert_param(IS_CAN_FILTER_FIFO(CAN_InitFilterStruct->Filter_FIFOAssignment));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitFilterStruct->Filter_Act));
+
+ filter_number_bit_pos = ((uint32_t)1) << CAN_InitFilterStruct->Filter_Num;
+
+ /* Initialisation mode for the filter */
+ CAN->FMC |= FMC_FINITM;
+
+ /* Filter Deactivation */
+ CAN->FA1 &= ~(uint32_t)filter_number_bit_pos;
+
+ /* Filter Scale */
+ if (CAN_InitFilterStruct->Filter_Scale == CAN_Filter_16bitScale)
+ {
+ /* 16-bit scale for the filter */
+ CAN->FS1 &= ~(uint32_t)filter_number_bit_pos;
+
+ /* First 16-bit identifier and First 16-bit mask */
+ /* Or First 16-bit identifier and Second 16-bit identifier */
+ CAN->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR1 =
+ ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_LowId) << 16)
+ | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_LowId);
+
+ /* Second 16-bit identifier and Second 16-bit mask */
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+ CAN->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR2 =
+ ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_HighId) << 16)
+ | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_HighId);
+ }
+
+ if (CAN_InitFilterStruct->Filter_Scale == CAN_Filter_32bitScale)
+ {
+ /* 32-bit scale for the filter */
+ CAN->FS1 |= filter_number_bit_pos;
+ /* 32-bit identifier or First 32-bit identifier */
+ CAN->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR1 =
+ ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_HighId) << 16)
+ | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_LowId);
+ /* 32-bit mask or Second 32-bit identifier */
+ CAN->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR2 =
+ ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_HighId) << 16)
+ | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_LowId);
+ }
+
+ /* Filter Mode */
+ if (CAN_InitFilterStruct->Filter_Mode == CAN_Filter_IdMaskMode)
+ {
+ /*Id/Mask mode for the filter*/
+ CAN->FM1 &= ~(uint32_t)filter_number_bit_pos;
+ }
+ else /* CAN_InitFilterStruct->Filter_Mode == CAN_Filter_IdListMode */
+ {
+ /*Identifier list mode for the filter*/
+ CAN->FM1 |= (uint32_t)filter_number_bit_pos;
+ }
+
+ /* Filter DATFIFO assignment */
+ if (CAN_InitFilterStruct->Filter_FIFOAssignment == CAN_Filter_FIFO0)
+ {
+ /* DATFIFO 0 assignation for the filter */
+ CAN->FFA1 &= ~(uint32_t)filter_number_bit_pos;
+ }
+
+ if (CAN_InitFilterStruct->Filter_FIFOAssignment == CAN_Filter_FIFO1)
+ {
+ /* DATFIFO 1 assignation for the filter */
+ CAN->FFA1 |= (uint32_t)filter_number_bit_pos;
+ }
+
+ /* Filter activation */
+ if (CAN_InitFilterStruct->Filter_Act == ENABLE)
+ {
+ CAN->FA1 |= filter_number_bit_pos;
+ }
+
+ /* Leave the initialisation mode for the filter */
+ CAN->FMC &= ~FMC_FINITM;
+}
+/**
+ * @brief Fills each CAN_InitParam member with its default value.
+ * @param CAN_InitParam pointer to a CAN_InitType structure which
+ * will be initialized.
+ */
+void CAN_InitStruct(CAN_InitType* CAN_InitParam)
+{
+ /* Reset CAN init structure parameters values */
+
+ /* Initialize the time triggered communication mode */
+ CAN_InitParam->TTCM = DISABLE;
+
+ /* Initialize the automatic bus-off management */
+ CAN_InitParam->ABOM = DISABLE;
+
+ /* Initialize the automatic wake-up mode */
+ CAN_InitParam->AWKUM = DISABLE;
+
+ /* Initialize the no automatic retransmission */
+ CAN_InitParam->NART = DISABLE;
+
+ /* Initialize the receive DATFIFO locked mode */
+ CAN_InitParam->RFLM = DISABLE;
+
+ /* Initialize the transmit DATFIFO priority */
+ CAN_InitParam->TXFP = DISABLE;
+
+ /* Initialize the OperatingMode member */
+ CAN_InitParam->OperatingMode = CAN_Normal_Mode;
+
+ /* Initialize the RSJW member */
+ CAN_InitParam->RSJW = CAN_RSJW_1tq;
+
+ /* Initialize the TBS1 member */
+ CAN_InitParam->TBS1 = CAN_TBS1_4tq;
+
+ /* Initialize the TBS2 member */
+ CAN_InitParam->TBS2 = CAN_TBS2_3tq;
+
+ /* Initialize the BaudRatePrescaler member */
+ CAN_InitParam->BaudRatePrescaler = 1;
+}
+
+/**
+ * @brief Enables or disables the DBG Freeze for CAN.
+ * @param CAN to select the CAN peripheral.
+ * @param Cmd new state of the CAN peripheral. This parameter can
+ * be: ENABLE or DISABLE.
+ */
+void CAN_DebugFreeze(CAN_Module* CANx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable Debug Freeze */
+ CANx->MCTRL |= MCTRL_DBGF;
+ }
+ else
+ {
+ /* Disable Debug Freeze */
+ CANx->MCTRL &= ~MCTRL_DBGF;
+ }
+}
+
+/**
+ * @brief Enables or disabes the CAN Time TriggerOperation communication mode.
+ * @param CAN to select the CAN peripheral.
+ * @param Cmd Mode new state , can be one of @ref FunctionalState.
+ * @note when enabled, Time stamp (TIME[15:0]) value is sent in the last
+ * two data bytes of the 8-byte message: TIME[7:0] in data byte 6
+ * and TIME[15:8] in data byte 7
+ * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be
+ * sent over the CAN bus.
+ */
+void CAN_EnTTComMode(CAN_Module* CANx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the TTCM mode */
+ CANx->MCTRL |= CAN_MCTRL_TTCM;
+
+ /* Set TGT bits */
+ CANx->sTxMailBox[0].TMDT |= ((uint32_t)CAN_TMDT0_TGT);
+ CANx->sTxMailBox[1].TMDT |= ((uint32_t)CAN_TMDT1_TGT);
+ CANx->sTxMailBox[2].TMDT |= ((uint32_t)CAN_TMDT2_TGT);
+ }
+ else
+ {
+ /* Disable the TTCM mode */
+ CANx->MCTRL &= (uint32_t)(~(uint32_t)CAN_MCTRL_TTCM);
+
+ /* Reset TGT bits */
+ CANx->sTxMailBox[0].TMDT &= ((uint32_t)~CAN_TMDT0_TGT);
+ CANx->sTxMailBox[1].TMDT &= ((uint32_t)~CAN_TMDT1_TGT);
+ CANx->sTxMailBox[2].TMDT &= ((uint32_t)~CAN_TMDT2_TGT);
+ }
+}
+/**
+ * @brief Initiates the transmission of a message.
+ * @param CAN to select the CAN peripheral.
+ * @param TxMessage pointer to a structure which contains CAN Id, CAN
+ * DLC and CAN data.
+ * @return The number of the mailbox that is used for transmission
+ * or CAN_TxSTS_NoMailBox if there is no empty mailbox.
+ */
+uint8_t CAN_TransmitMessage(CAN_Module* CANx, CanTxMessage* TxMessage)
+{
+ uint8_t transmit_mailbox = 0;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_ID(TxMessage->IDE));
+ assert_param(IS_CAN_RTRQ(TxMessage->RTR));
+ assert_param(IS_CAN_DLC(TxMessage->DLC));
+
+ /* Select one empty transmit mailbox */
+ if ((CANx->TSTS & CAN_TSTS_TMEM0) == CAN_TSTS_TMEM0)
+ {
+ transmit_mailbox = 0;
+ }
+ else if ((CANx->TSTS & CAN_TSTS_TMEM1) == CAN_TSTS_TMEM1)
+ {
+ transmit_mailbox = 1;
+ }
+ else if ((CANx->TSTS & CAN_TSTS_TMEM2) == CAN_TSTS_TMEM2)
+ {
+ transmit_mailbox = 2;
+ }
+ else
+ {
+ transmit_mailbox = CAN_TxSTS_NoMailBox;
+ }
+
+ if (transmit_mailbox != CAN_TxSTS_NoMailBox)
+ {
+ /* Set up the Id */
+ CANx->sTxMailBox[transmit_mailbox].TMI &= TMIDxR_TXRQ;
+ if (TxMessage->IDE == CAN_Standard_Id)
+ {
+ assert_param(IS_CAN_STDID(TxMessage->StdId));
+ CANx->sTxMailBox[transmit_mailbox].TMI |= ((TxMessage->StdId << 21) | TxMessage->RTR);
+ }
+ else
+ {
+ assert_param(IS_CAN_EXTID(TxMessage->ExtId));
+ CANx->sTxMailBox[transmit_mailbox].TMI |= ((TxMessage->ExtId << 3) | TxMessage->IDE | TxMessage->RTR);
+ }
+
+ /* Set up the DLC */
+ TxMessage->DLC &= (uint8_t)0x0000000F;
+ CANx->sTxMailBox[transmit_mailbox].TMDT &= (uint32_t)0xFFFFFFF0;
+ CANx->sTxMailBox[transmit_mailbox].TMDT |= TxMessage->DLC;
+
+ /* Set up the data field */
+ CANx->sTxMailBox[transmit_mailbox].TMDL =
+ (((uint32_t)TxMessage->Data[3] << 24) | ((uint32_t)TxMessage->Data[2] << 16)
+ | ((uint32_t)TxMessage->Data[1] << 8) | ((uint32_t)TxMessage->Data[0]));
+ CANx->sTxMailBox[transmit_mailbox].TMDH =
+ (((uint32_t)TxMessage->Data[7] << 24) | ((uint32_t)TxMessage->Data[6] << 16)
+ | ((uint32_t)TxMessage->Data[5] << 8) | ((uint32_t)TxMessage->Data[4]));
+ /* Request transmission */
+ CANx->sTxMailBox[transmit_mailbox].TMI |= TMIDxR_TXRQ;
+ }
+ return transmit_mailbox;
+}
+
+/**
+ * @brief Checks the transmission of a message.
+ * @param CANx to select the CAN peripheral.
+ * @param TransmitMailbox the number of the mailbox that is used for
+ * transmission.
+ * @return CAN_TxSTS_Ok if the CAN driver transmits the message, CAN_TxSTS_Failed
+ * in an other case.
+ */
+uint8_t CAN_TransmitSTS(CAN_Module* CANx, uint8_t TransmitMailbox)
+{
+ uint32_t state = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
+
+ switch (TransmitMailbox)
+ {
+ case (CAN_TXMAILBOX_0):
+ state = CANx->TSTS & (CAN_TSTS_RQCPM0 | CAN_TSTS_TXOKM0 | CAN_TSTS_TMEM0);
+ break;
+ case (CAN_TXMAILBOX_1):
+ state = CANx->TSTS & (CAN_TSTS_RQCPM1 | CAN_TSTS_TXOKM1 | CAN_TSTS_TMEM1);
+ break;
+ case (CAN_TXMAILBOX_2):
+ state = CANx->TSTS & (CAN_TSTS_RQCPM2 | CAN_TSTS_TXOKM2 | CAN_TSTS_TMEM2);
+ break;
+ default:
+ state = CAN_TxSTS_Failed;
+ break;
+ }
+ switch (state)
+ {
+ /* transmit pending */
+ case (0x0):
+ state = CAN_TxSTS_Pending;
+ break;
+ /* transmit failed */
+ case (CAN_TSTS_RQCPM0 | CAN_TSTS_TMEM0):
+ state = CAN_TxSTS_Failed;
+ break;
+ case (CAN_TSTS_RQCPM1 | CAN_TSTS_TMEM1):
+ state = CAN_TxSTS_Failed;
+ break;
+ case (CAN_TSTS_RQCPM2 | CAN_TSTS_TMEM2):
+ state = CAN_TxSTS_Failed;
+ break;
+ /* transmit succeeded */
+ case (CAN_TSTS_RQCPM0 | CAN_TSTS_TXOKM0 | CAN_TSTS_TMEM0):
+ state = CAN_TxSTS_Ok;
+ break;
+ case (CAN_TSTS_RQCPM1 | CAN_TSTS_TXOKM1 | CAN_TSTS_TMEM1):
+ state = CAN_TxSTS_Ok;
+ break;
+ case (CAN_TSTS_RQCPM2 | CAN_TSTS_TXOKM2 | CAN_TSTS_TMEM2):
+ state = CAN_TxSTS_Ok;
+ break;
+ default:
+ state = CAN_TxSTS_Failed;
+ break;
+ }
+ return (uint8_t)state;
+}
+
+/**
+ * @brief Cancels a transmit request.
+ * @param CAN to select the CAN peripheral.
+ * @param Mailbox Mailbox number.
+ */
+void CAN_CancelTransmitMessage(CAN_Module* CANx, uint8_t Mailbox)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));
+ /* abort transmission */
+ switch (Mailbox)
+ {
+ case (CAN_TXMAILBOX_0):
+ CANx->TSTS = CAN_TSTS_ABRQM0;
+ break;
+ case (CAN_TXMAILBOX_1):
+ CANx->TSTS = CAN_TSTS_ABRQM1;
+ break;
+ case (CAN_TXMAILBOX_2):
+ CANx->TSTS = CAN_TSTS_ABRQM2;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Receives a message.
+ * @param CAN to select the CAN peripheral.
+ * @param FIFONum Receive DATFIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @param RxMessage pointer to a structure receive message which contains
+ * CAN Id, CAN DLC, CAN datas and FMI number.
+ */
+void CAN_ReceiveMessage(CAN_Module* CANx, uint8_t FIFONum, CanRxMessage* RxMessage)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FIFO(FIFONum));
+ /* Get the Id */
+ RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONum].RMI;
+ if (RxMessage->IDE == CAN_Standard_Id)
+ {
+ RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONum].RMI >> 21);
+ }
+ else
+ {
+ RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONum].RMI >> 3);
+ }
+
+ RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONum].RMI;
+ /* Get the DLC */
+ RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONum].RMDT;
+ /* Get the FMI */
+ RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDT >> 8);
+ /* Get the data field */
+ RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONum].RMDL;
+ RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDL >> 8);
+ RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDL >> 16);
+ RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDL >> 24);
+ RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONum].RMDH;
+ RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDH >> 8);
+ RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDH >> 16);
+ RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDH >> 24);
+ /* Release the DATFIFO */
+ /* Release FIFO0 */
+ if (FIFONum == CAN_FIFO0)
+ {
+ CANx->RFF0 |= CAN_RFF0_RFFOM0;
+ }
+ /* Release FIFO1 */
+ else /* FIFONum == CAN_FIFO1 */
+ {
+ CANx->RFF1 |= CAN_RFF1_RFFOM1;
+ }
+}
+
+/**
+ * @brief Releases the specified DATFIFO.
+ * @param CAN to select the CAN peripheral.
+ * @param FIFONum DATFIFO to release, CAN_FIFO0 or CAN_FIFO1.
+ */
+void CAN_ReleaseFIFO(CAN_Module* CANx, uint8_t FIFONum)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FIFO(FIFONum));
+ /* Release FIFO0 */
+ if (FIFONum == CAN_FIFO0)
+ {
+ CANx->RFF0 |= CAN_RFF0_RFFOM0;
+ }
+ /* Release FIFO1 */
+ else /* FIFONum == CAN_FIFO1 */
+ {
+ CANx->RFF1 |= CAN_RFF1_RFFOM1;
+ }
+}
+
+/**
+ * @brief Returns the number of pending messages.
+ * @param CAN to select the CAN peripheral.
+ * @param FIFONum Receive DATFIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @return NbMessage : which is the number of pending message.
+ */
+uint8_t CAN_PendingMessage(CAN_Module* CANx, uint8_t FIFONum)
+{
+ uint8_t message_pending = 0;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FIFO(FIFONum));
+ if (FIFONum == CAN_FIFO0)
+ {
+ message_pending = (uint8_t)(CANx->RFF0 & (uint32_t)0x03);
+ }
+ else if (FIFONum == CAN_FIFO1)
+ {
+ message_pending = (uint8_t)(CANx->RFF1 & (uint32_t)0x03);
+ }
+ else
+ {
+ message_pending = 0;
+ }
+ return message_pending;
+}
+
+/**
+ * @brief Select the CAN Operation mode.
+ * @param CAN to select the CAN peripheral.
+ * @param CAN_OperatingMode CAN Operating Mode. This parameter can be one
+ * of @ref CAN_operating_mode enumeration.
+ * @return status of the requested mode which can be
+ * - CAN_ModeSTS_Failed CAN failed entering the specific mode
+ * - CAN_ModeSTS_Success CAN Succeed entering the specific mode
+
+ */
+uint8_t CAN_OperatingModeReq(CAN_Module* CANx, uint8_t CAN_OperatingMode)
+{
+ uint8_t status = CAN_ModeSTS_Failed;
+
+ /* Timeout for INAK or also for SLAK bits*/
+ uint32_t timeout = INIAK_TIMEOUT;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode));
+
+ if (CAN_OperatingMode == CAN_Operating_InitMode)
+ {
+ /* Request initialisation */
+ CANx->MCTRL = (uint32_t)((CANx->MCTRL & (uint32_t)(~(uint32_t)CAN_MCTRL_SLPRQ)) | CAN_MCTRL_INIRQ);
+
+ /* Wait the acknowledge */
+ while (((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_INIAK) && (timeout != 0))
+ {
+ timeout--;
+ }
+ if ((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_INIAK)
+ {
+ status = CAN_ModeSTS_Failed;
+ }
+ else
+ {
+ status = CAN_ModeSTS_Success;
+ }
+ }
+ else if (CAN_OperatingMode == CAN_Operating_NormalMode)
+ {
+ /* Request leave initialisation and sleep mode and enter Normal mode */
+ CANx->MCTRL &= (uint32_t)(~(CAN_MCTRL_SLPRQ | CAN_MCTRL_INIRQ));
+
+ /* Wait the acknowledge */
+ while (((CANx->MSTS & CAN_MODE_MASK) != 0) && (timeout != 0))
+ {
+ timeout--;
+ }
+ if ((CANx->MSTS & CAN_MODE_MASK) != 0)
+ {
+ status = CAN_ModeSTS_Failed;
+ }
+ else
+ {
+ status = CAN_ModeSTS_Success;
+ }
+ }
+ else if (CAN_OperatingMode == CAN_Operating_SleepMode)
+ {
+ /* Request Sleep mode */
+ CANx->MCTRL = (uint32_t)((CANx->MCTRL & (uint32_t)(~(uint32_t)CAN_MCTRL_INIRQ)) | CAN_MCTRL_SLPRQ);
+
+ /* Wait the acknowledge */
+ while (((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_SLPAK) && (timeout != 0))
+ {
+ timeout--;
+ }
+ if ((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_SLPAK)
+ {
+ status = CAN_ModeSTS_Failed;
+ }
+ else
+ {
+ status = CAN_ModeSTS_Success;
+ }
+ }
+ else
+ {
+ status = CAN_ModeSTS_Failed;
+ }
+
+ return (uint8_t)status;
+}
+
+/**
+ * @brief Enters the low power mode.
+ * @param CAN to select the CAN peripheral.
+ * @return status: CAN_SLEEP_Ok if sleep entered, CAN_SLEEP_Failed in an
+ * other case.
+ */
+uint8_t CAN_EnterSleep(CAN_Module* CANx)
+{
+ uint8_t sleepstatus = CAN_SLEEP_Failed;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Request Sleep mode */
+ CANx->MCTRL = (((CANx->MCTRL) & (uint32_t)(~(uint32_t)CAN_MCTRL_INIRQ)) | CAN_MCTRL_SLPRQ);
+
+ /* Sleep mode status */
+ if ((CANx->MSTS & (CAN_MSTS_SLPAK | CAN_MSTS_INIAK)) == CAN_MSTS_SLPAK)
+ {
+ /* Sleep mode not entered */
+ sleepstatus = CAN_SLEEP_Ok;
+ }
+ /* return sleep mode status */
+ return (uint8_t)sleepstatus;
+}
+
+/**
+ * @brief Wakes the CAN up.
+ * @param CAN to select the CAN peripheral.
+ * @return status: CAN_WKU_Ok if sleep mode left, CAN_WKU_Failed in an
+ * other case.
+ */
+uint8_t CAN_WakeUp(CAN_Module* CANx)
+{
+ uint32_t wait_slak = SLPAK_TIMEOUT;
+ uint8_t wakeupstatus = CAN_WKU_Failed;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Wake up request */
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_SLPRQ;
+
+ /* Sleep mode status */
+ while (((CANx->MSTS & CAN_MSTS_SLPAK) == CAN_MSTS_SLPAK) && (wait_slak != 0x00))
+ {
+ wait_slak--;
+ }
+ if ((CANx->MSTS & CAN_MSTS_SLPAK) != CAN_MSTS_SLPAK)
+ {
+ /* wake up done : Sleep mode exited */
+ wakeupstatus = CAN_WKU_Ok;
+ }
+ /* return wakeup status */
+ return (uint8_t)wakeupstatus;
+}
+
+/**
+ * @brief Returns the CANx's last error code (LEC).
+ * @param CAN to select the CAN peripheral.
+ * @return CAN_ErrorCode: specifies the Error code :
+ * - CAN_ERRORCODE_NoErr No Error
+ * - CAN_ERRORCODE_StuffErr Stuff Error
+ * - CAN_ERRORCODE_FormErr Form Error
+ * - CAN_ERRORCODE_ACKErr Acknowledgment Error
+ * - CAN_ERRORCODE_BitRecessiveErr Bit Recessive Error
+ * - CAN_ERRORCODE_BitDominantErr Bit Dominant Error
+ * - CAN_ERRORCODE_CRCErr CRC Error
+ * - CAN_ERRORCODE_SoftwareSetErr Software Set Error
+ */
+
+uint8_t CAN_GetLastErrCode(CAN_Module* CANx)
+{
+ uint8_t errorcode = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Get the error code*/
+ errorcode = (((uint8_t)CANx->ESTS) & (uint8_t)CAN_ESTS_LEC);
+
+ /* Return the error code*/
+ return errorcode;
+}
+/**
+ * @brief Returns the CANx Receive Error Counter (REC).
+ * @note In case of an error during reception, this counter is incremented
+ * by 1 or by 8 depending on the error condition as defined by the CAN
+ * standard. After every successful reception, the counter is
+ * decremented by 1 or reset to 120 if its value was higher than 128.
+ * When the counter value exceeds 127, the CAN controller enters the
+ * error passive state.
+ * @param CANx to to select the CAN peripheral.
+ * @return CAN Receive Error Counter.
+ */
+uint8_t CAN_GetReceiveErrCounter(CAN_Module* CANx)
+{
+ uint8_t counter = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Get the Receive Error Counter*/
+ counter = (uint8_t)((CANx->ESTS & CAN_ESTS_RXEC) >> 24);
+
+ /* Return the Receive Error Counter*/
+ return counter;
+}
+
+/**
+ * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
+ * @param CAN to to select the CAN peripheral.
+ * @return LSB of the 9-bit CAN Transmit Error Counter.
+ */
+uint8_t CAN_GetLSBTransmitErrCounter(CAN_Module* CANx)
+{
+ uint8_t counter = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
+ counter = (uint8_t)((CANx->ESTS & CAN_ESTS_TXEC) >> 16);
+
+ /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
+ return counter;
+}
+
+/**
+ * @brief Enables or disables the specified CANx interrupts.
+ * @param CAN to select the CAN peripheral.
+ * @param CAN_INT specifies the CAN interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * - CAN_INT_TME,
+ * - CAN_INT_FMP0,
+ * - CAN_INT_FF0,
+ * - CAN_INT_FOV0,
+ * - CAN_INT_FMP1,
+ * - CAN_INT_FF1,
+ * - CAN_INT_FOV1,
+ * - CAN_INT_EWG,
+ * - CAN_INT_EPV,
+ * - CAN_INT_LEC,
+ * - CAN_INT_ERR,
+ * - CAN_INT_WKU or
+ * - CAN_INT_SLK.
+ * @param Cmd new state of the CAN interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void CAN_INTConfig(CAN_Module* CANx, uint32_t CAN_INT, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_INT(CAN_INT));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected CANx interrupt */
+ CANx->INTE |= CAN_INT;
+ }
+ else
+ {
+ /* Disable the selected CANx interrupt */
+ CANx->INTE &= ~CAN_INT;
+ }
+}
+/**
+ * @brief Checks whether the specified CAN flag is set or not.
+ * @param CAN to select the CAN peripheral.
+ * @param CAN_FLAG specifies the flag to check.
+ * This parameter can be one of the following flags:
+ * - CAN_FLAG_EWGFL
+ * - CAN_FLAG_EPVFL
+ * - CAN_FLAG_BOFFL
+ * - CAN_FLAG_RQCPM0
+ * - CAN_FLAG_RQCPM1
+ * - CAN_FLAG_RQCPM2
+ * - CAN_FLAG_FFMP1
+ * - CAN_FLAG_FFULL1
+ * - CAN_FLAG_FFOVR1
+ * - CAN_FLAG_FFMP0
+ * - CAN_FLAG_FFULL0
+ * - CAN_FLAG_FFOVR0
+ * - CAN_FLAG_WKU
+ * - CAN_FLAG_SLAK
+ * - CAN_FLAG_LEC
+ * @return The new state of CAN_FLAG (SET or RESET).
+ */
+FlagStatus CAN_GetFlagSTS(CAN_Module* CANx, uint32_t CAN_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_GET_FLAG(CAN_FLAG));
+
+ if ((CAN_FLAG & CAN_FLAGS_ESTS) != (uint32_t)RESET)
+ {
+ /* Check the status of the specified CAN flag */
+ if ((CANx->ESTS & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ else if ((CAN_FLAG & CAN_FLAGS_MSTS) != (uint32_t)RESET)
+ {
+ /* Check the status of the specified CAN flag */
+ if ((CANx->MSTS & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ else if ((CAN_FLAG & CAN_FLAGS_TSTS) != (uint32_t)RESET)
+ {
+ /* Check the status of the specified CAN flag */
+ if ((CANx->TSTS & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ else if ((CAN_FLAG & CAN_FLAGS_RFF0) != (uint32_t)RESET)
+ {
+ /* Check the status of the specified CAN flag */
+ if ((CANx->RFF0 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ else /* if (CAN_FLAG & CAN_FLAGS_RFF1 != (uint32_t)RESET) */
+ {
+ /* Check the status of the specified CAN flag */
+ if ((uint32_t)(CANx->RFF1 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ /* Return the CAN_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the CAN's pending flags.
+ * @param CAN to select the CAN peripheral.
+ * @param CAN_FLAG specifies the flag to clear.
+ * This parameter can be one of the following flags:
+ * - CAN_FLAG_RQCPM0
+ * - CAN_FLAG_RQCPM1
+ * - CAN_FLAG_RQCPM2
+ * - CAN_FLAG_FFULL1
+ * - CAN_FLAG_FFOVR1
+ * - CAN_FLAG_FFULL0
+ * - CAN_FLAG_FFOVR0
+ * - CAN_FLAG_WKU
+ * - CAN_FLAG_SLAK
+ * - CAN_FLAG_LEC
+ */
+void CAN_ClearFlag(CAN_Module* CANx, uint32_t CAN_FLAG)
+{
+ uint32_t flagtmp = 0;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));
+
+ if (CAN_FLAG == CAN_FLAG_LEC) /* ESTS register */
+ {
+ /* Clear the selected CAN flags */
+ CANx->ESTS = (uint32_t)RESET;
+ }
+ else /* MSTS or TSTS or RFF0 or RFF1 */
+ {
+ flagtmp = CAN_FLAG & 0x000FFFFF;
+
+ if ((CAN_FLAG & CAN_FLAGS_RFF0) != (uint32_t)RESET)
+ {
+ /* Receive Flags */
+ CANx->RFF0 = (uint32_t)(flagtmp);
+ }
+ else if ((CAN_FLAG & CAN_FLAGS_RFF1) != (uint32_t)RESET)
+ {
+ /* Receive Flags */
+ CANx->RFF1 = (uint32_t)(flagtmp);
+ }
+ else if ((CAN_FLAG & CAN_FLAGS_TSTS) != (uint32_t)RESET)
+ {
+ /* Transmit Flags */
+ CANx->TSTS = (uint32_t)(flagtmp);
+ }
+ else /* if ((CAN_FLAG & CAN_FLAGS_MSTS)!=(uint32_t)RESET) */
+ {
+ /* Operating mode Flags */
+ CANx->MSTS = (uint32_t)(flagtmp);
+ }
+ }
+}
+
+/**
+ * @brief Checks whether the specified CANx interrupt has occurred or not.
+ * @param CAN to select the CAN peripheral.
+ * @param CAN_INT specifies the CAN interrupt source to check.
+ * This parameter can be one of the following flags:
+ * - CAN_INT_TME
+ * - CAN_INT_FMP0
+ * - CAN_INT_FF0
+ * - CAN_INT_FOV0
+ * - CAN_INT_FMP1
+ * - CAN_INT_FF1
+ * - CAN_INT_FOV1
+ * - CAN_INT_WKU
+ * - CAN_INT_SLK
+ * - CAN_INT_EWG
+ * - CAN_INT_EPV
+ * - CAN_INT_BOF
+ * - CAN_INT_LEC
+ * - CAN_INT_ERR
+ * @return The current state of CAN_INT (SET or RESET).
+ */
+INTStatus CAN_GetIntStatus(CAN_Module* CANx, uint32_t CAN_INT)
+{
+ INTStatus itstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_INT(CAN_INT));
+
+ /* check the enable interrupt bit */
+ if ((CANx->INTE & CAN_INT) != RESET)
+ {
+ /* in case the Interrupt is enabled, .... */
+ switch (CAN_INT)
+ {
+ case CAN_INT_TME:
+ /* Check CAN_TSTS_RQCPx bits */
+ itstatus = CheckINTStatus(CANx->TSTS, CAN_TSTS_RQCPM0 | CAN_TSTS_RQCPM1 | CAN_TSTS_RQCPM2);
+ break;
+ case CAN_INT_FMP0:
+ /* Check CAN_RFF0_FFMP0 bit */
+ itstatus = CheckINTStatus(CANx->RFF0, CAN_RFF0_FFMP0);
+ break;
+ case CAN_INT_FF0:
+ /* Check CAN_RFF0_FFULL0 bit */
+ itstatus = CheckINTStatus(CANx->RFF0, CAN_RFF0_FFULL0);
+ break;
+ case CAN_INT_FOV0:
+ /* Check CAN_RFF0_FFOVR0 bit */
+ itstatus = CheckINTStatus(CANx->RFF0, CAN_RFF0_FFOVR0);
+ break;
+ case CAN_INT_FMP1:
+ /* Check CAN_RFF1_FFMP1 bit */
+ itstatus = CheckINTStatus(CANx->RFF1, CAN_RFF1_FFMP1);
+ break;
+ case CAN_INT_FF1:
+ /* Check CAN_RFF1_FFULL1 bit */
+ itstatus = CheckINTStatus(CANx->RFF1, CAN_RFF1_FFULL1);
+ break;
+ case CAN_INT_FOV1:
+ /* Check CAN_RFF1_FFOVR1 bit */
+ itstatus = CheckINTStatus(CANx->RFF1, CAN_RFF1_FFOVR1);
+ break;
+ case CAN_INT_WKU:
+ /* Check CAN_MSTS_WKUINT bit */
+ itstatus = CheckINTStatus(CANx->MSTS, CAN_MSTS_WKUINT);
+ break;
+ case CAN_INT_SLK:
+ /* Check CAN_MSTS_SLAKINT bit */
+ itstatus = CheckINTStatus(CANx->MSTS, CAN_MSTS_SLAKINT);
+ break;
+ case CAN_INT_EWG:
+ /* Check CAN_ESTS_EWGFL bit */
+ itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_EWGFL);
+ break;
+ case CAN_INT_EPV:
+ /* Check CAN_ESTS_EPVFL bit */
+ itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_EPVFL);
+ break;
+ case CAN_INT_BOF:
+ /* Check CAN_ESTS_BOFFL bit */
+ itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_BOFFL);
+ break;
+ case CAN_INT_LEC:
+ /* Check CAN_ESTS_LEC bit */
+ itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_LEC);
+ break;
+ case CAN_INT_ERR:
+ /* Check CAN_MSTS_ERRINT bit */
+ itstatus = CheckINTStatus(CANx->MSTS, CAN_MSTS_ERRINT);
+ break;
+ default:
+ /* in case of error, return RESET */
+ itstatus = RESET;
+ break;
+ }
+ }
+ else
+ {
+ /* in case the Interrupt is not enabled, return RESET */
+ itstatus = RESET;
+ }
+
+ /* Return the CAN_INT status */
+ return itstatus;
+}
+
+/**
+ * @brief Clears the CANx's interrupt pending bits.
+ * @param CAN to select the CAN peripheral.
+ * @param CAN_INT specifies the interrupt pending bit to clear.
+ * - CAN_INT_TME
+ * - CAN_INT_FF0
+ * - CAN_INT_FOV0
+ * - CAN_INT_FF1
+ * - CAN_INT_FOV1
+ * - CAN_INT_WKU
+ * - CAN_INT_SLK
+ * - CAN_INT_EWG
+ * - CAN_INT_EPV
+ * - CAN_INT_BOF
+ * - CAN_INT_LEC
+ * - CAN_INT_ERR
+ */
+void CAN_ClearINTPendingBit(CAN_Module* CANx, uint32_t CAN_INT)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_CLEAR_INT(CAN_INT));
+
+ switch (CAN_INT)
+ {
+ case CAN_INT_TME:
+ /* Clear CAN_TSTS_RQCPx (rc_w1)*/
+ CANx->TSTS = CAN_TSTS_RQCPM0 | CAN_TSTS_RQCPM1 | CAN_TSTS_RQCPM2;
+ break;
+ case CAN_INT_FF0:
+ /* Clear CAN_RFF0_FFULL0 (rc_w1)*/
+ CANx->RFF0 = CAN_RFF0_FFULL0;
+ break;
+ case CAN_INT_FOV0:
+ /* Clear CAN_RFF0_FFOVR0 (rc_w1)*/
+ CANx->RFF0 = CAN_RFF0_FFOVR0;
+ break;
+ case CAN_INT_FF1:
+ /* Clear CAN_RFF1_FFULL1 (rc_w1)*/
+ CANx->RFF1 = CAN_RFF1_FFULL1;
+ break;
+ case CAN_INT_FOV1:
+ /* Clear CAN_RFF1_FFOVR1 (rc_w1)*/
+ CANx->RFF1 = CAN_RFF1_FFOVR1;
+ break;
+ case CAN_INT_WKU:
+ /* Clear CAN_MSTS_WKUINT (rc_w1)*/
+ CANx->MSTS = CAN_MSTS_WKUINT;
+ break;
+ case CAN_INT_SLK:
+ /* Clear CAN_MSTS_SLAKINT (rc_w1)*/
+ CANx->MSTS = CAN_MSTS_SLAKINT;
+ break;
+ case CAN_INT_EWG:
+ /* Clear CAN_MSTS_ERRINT (rc_w1) */
+ CANx->MSTS = CAN_MSTS_ERRINT;
+ /* Note : the corresponding Flag is cleared by hardware depending
+ of the CAN Bus status*/
+ break;
+ case CAN_INT_EPV:
+ /* Clear CAN_MSTS_ERRINT (rc_w1) */
+ CANx->MSTS = CAN_MSTS_ERRINT;
+ /* Note : the corresponding Flag is cleared by hardware depending
+ of the CAN Bus status*/
+ break;
+ case CAN_INT_BOF:
+ /* Clear CAN_MSTS_ERRINT (rc_w1) */
+ CANx->MSTS = CAN_MSTS_ERRINT;
+ /* Note : the corresponding Flag is cleared by hardware depending
+ of the CAN Bus status*/
+ break;
+ case CAN_INT_LEC:
+ /* Clear LEC bits */
+ CANx->ESTS = RESET;
+ /* Clear CAN_MSTS_ERRINT (rc_w1) */
+ CANx->MSTS = CAN_MSTS_ERRINT;
+ break;
+ case CAN_INT_ERR:
+ /*Clear LEC bits */
+ CANx->ESTS = RESET;
+ /* Clear CAN_MSTS_ERRINT (rc_w1) */
+ CANx->MSTS = CAN_MSTS_ERRINT;
+ /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending
+ of the CAN Bus status*/
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Checks whether the CAN interrupt has occurred or not.
+ * @param CAN_Reg specifies the CAN interrupt register to check.
+ * @param Int_Bit specifies the interrupt source bit to check.
+ * @return The new state of the CAN Interrupt (SET or RESET).
+ */
+static INTStatus CheckINTStatus(uint32_t CAN_Reg, uint32_t Int_Bit)
+{
+ INTStatus pendingbitstatus = RESET;
+
+ if ((CAN_Reg & Int_Bit) != (uint32_t)RESET)
+ {
+ /* CAN_INT is set */
+ pendingbitstatus = SET;
+ }
+ else
+ {
+ /* CAN_INT is reset */
+ pendingbitstatus = RESET;
+ }
+ return pendingbitstatus;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_comp.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_comp.c
new file mode 100644
index 0000000000..9bd15092f1
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_comp.c
@@ -0,0 +1,385 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_comp.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l43x_comp.h"
+#include "n32l43x_rcc.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup COMP
+ * @brief COMP driver modules
+ * @{
+ */
+
+/** @addtogroup COMP_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup COMP_Private_Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup COMP_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup COMP_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup COMP_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup COMP_Private_Functions
+ * @{
+ */
+#define SetBitMsk(reg, bit, msk) ((reg) = (((reg) & ~(msk)) | (bit)))
+#define ClrBit(reg, bit) ((reg) &= ~(bit))
+#define SetBit(reg, bit) ((reg) |= (bit))
+#define GetBit(reg, bit) ((reg) & (bit))
+/**
+ * @brief Deinitializes the COMP peripheral registers to their default reset values.
+ */
+void COMP_DeInit(void)
+{
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP, DISABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP_FILT, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP_FILT, DISABLE);
+}
+void COMP_StructInit(COMP_InitType* COMP_InitStruct)
+{
+ COMP_InitStruct->LowPoweMode = false; // only COMP1 have this bit
+ COMP_InitStruct->InpDacConnect = false; // only COMP1 have this bit
+
+ COMP_InitStruct->Blking = COMP_CTRL_BLKING_NO; /*see @ref COMP_CTRL_BLKING */
+
+ COMP_InitStruct->Hyst = COMP_CTRL_HYST_NO; // see @COMPx_CTRL_HYST_MASK
+
+ COMP_InitStruct->PolRev = false; // out polarity reverse
+
+ COMP_InitStruct->OutTrig = COMP1_CTRL_OUTSEL_NC;
+ COMP_InitStruct->InpSel = COMP1_CTRL_INPSEL_FLOAT; //Float as same with comp1 and comp2
+ COMP_InitStruct->InmSel = COMP2_CTRL_INMSEL_NC; //NC as same with comp1 and comp2s
+ COMP_InitStruct->FilterEn= false;
+ COMP_InitStruct->ClkPsc= 0;
+ COMP_InitStruct->SampWindow= 0;
+ COMP_InitStruct->Thresh= 0;
+ COMP_InitStruct->En = false;
+}
+void COMP_Init(COMPX COMPx, COMP_InitType* COMP_InitStruct)
+{
+ COMP_SingleType* pCS;
+ __IO uint32_t tmp;
+ if (COMPx == COMP1)
+ pCS = &COMP->Cmp1;
+ else
+ pCS = &COMP->Cmp2;
+
+ // filter
+ tmp = pCS->FILC;
+ SetBitMsk(tmp, COMP_InitStruct->SampWindow << 6, COMP_FILC_SAMPW_MASK);
+ SetBitMsk(tmp, COMP_InitStruct->Thresh << 1, COMP_FILC_THRESH_MASK);
+ SetBitMsk(tmp, COMP_InitStruct->FilterEn << 0, COMP_FILC_FILEN_MASK);
+ pCS->FILC = tmp;
+ // filter psc
+ pCS->FILP = COMP_InitStruct->ClkPsc;
+
+ // ctrl
+ tmp = pCS->CTRL;
+ if (COMPx == COMP1)
+ {
+ if (COMP_InitStruct->InpDacConnect)
+ SetBit(tmp, COMP1_CTRL_INPDAC_MASK);
+ else
+ ClrBit(tmp, COMP1_CTRL_INPDAC_MASK);
+ if (COMP_InitStruct->LowPoweMode)
+ SetBit(tmp, COMP1_CTRL_PWRMODE_MASK);
+ else
+ ClrBit(tmp, COMP1_CTRL_PWRMODE_MASK);
+ }
+ SetBitMsk(tmp, COMP_InitStruct->Blking, COMP_CTRL_BLKING_MASK);
+ SetBitMsk(tmp, COMP_InitStruct->Hyst, COMPx_CTRL_HYST_MASK);
+ if (COMP_InitStruct->PolRev)
+ SetBit(tmp, COMP_POL_MASK);
+ else
+ ClrBit(tmp, COMP_POL_MASK);
+ SetBitMsk(tmp, COMP_InitStruct->OutTrig, COMP_CTRL_OUTSEL_MASK);
+ SetBitMsk(tmp, COMP_InitStruct->InpSel, COMP_CTRL_INPSEL_MASK);
+ SetBitMsk(tmp, COMP_InitStruct->InmSel, COMP_CTRL_INMSEL_MASK);
+ if (COMP_InitStruct->En)
+ SetBit(tmp, COMP_CTRL_EN_MASK);
+ else
+ ClrBit(tmp, COMP_CTRL_EN_MASK);
+ pCS->CTRL = tmp;
+}
+void COMP_Enable(COMPX COMPx, FunctionalState en)
+{
+ if (COMPx == COMP1)
+ {
+ if (en)
+ SetBit(COMP->Cmp1.CTRL, COMP_CTRL_EN_MASK);
+ else
+ ClrBit(COMP->Cmp1.CTRL, COMP_CTRL_EN_MASK);
+ }
+ else
+ {
+ if (en)
+ SetBit(COMP->Cmp2.CTRL, COMP_CTRL_EN_MASK);
+ else
+ ClrBit(COMP->Cmp2.CTRL, COMP_CTRL_EN_MASK);
+ }
+}
+
+void COMP_SetInpSel(COMPX COMPx, COMP_CTRL_INPSEL VpSel)
+{
+ __IO uint32_t tmp;
+ if (COMPx == COMP1)
+ tmp = COMP->Cmp1.CTRL;
+ else
+ tmp = COMP->Cmp2.CTRL;
+
+ SetBitMsk(tmp, VpSel, COMP_CTRL_INPSEL_MASK);
+
+ if (COMPx == COMP1)
+ COMP->Cmp1.CTRL = tmp;
+ else
+ COMP->Cmp2.CTRL = tmp;
+}
+void COMP_SetInmSel(COMPX COMPx, COMP_CTRL_INMSEL VmSel)
+{
+ __IO uint32_t tmp;
+ if (COMPx == COMP1)
+ tmp = COMP->Cmp1.CTRL;
+ else
+ tmp = COMP->Cmp2.CTRL;
+
+ SetBitMsk(tmp, VmSel, COMP_CTRL_INMSEL_MASK);
+
+ if (COMPx == COMP1)
+ COMP->Cmp1.CTRL = tmp;
+ else
+ COMP->Cmp2.CTRL = tmp;
+
+}
+void COMP_SetOutTrig(COMPX COMPx, COMP_CTRL_OUTTRIG OutTrig)
+{
+ __IO uint32_t tmp;
+ if (COMPx == COMP1)
+ tmp = COMP->Cmp1.CTRL;
+ else
+ tmp = COMP->Cmp2.CTRL;
+
+ SetBitMsk(tmp, OutTrig, COMP_CTRL_OUTSEL_MASK);
+
+ if (COMPx == COMP1)
+ COMP->Cmp1.CTRL = tmp;
+ else
+ COMP->Cmp2.CTRL = tmp;
+}
+
+// return see @COMP_INTSTS_CMPIS
+uint32_t COMP_GetIntSts(void)
+{
+ return COMP->INTSTS;
+}
+// parma range see @COMP_VREFSCL
+// Vv2Trim,Vv1Trim max 63
+void COMP_SetRefScl(uint8_t Vv2Trim, bool Vv2En, uint8_t Vv1Trim, bool Vv1En)
+{
+ __IO uint32_t tmp = 0;
+
+ SetBitMsk(tmp, Vv2Trim << 8, COMP_VREFSCL_VV2TRM_MSK);
+ SetBitMsk(tmp, Vv2En << 7, COMP_VREFSCL_VV2EN_MSK);
+ SetBitMsk(tmp, Vv1Trim << 1, COMP_VREFSCL_VV1TRM_MSK);
+ SetBitMsk(tmp, Vv1En << 0, COMP_VREFSCL_VV1EN_MSK);
+
+ COMP->VREFSCL = tmp;
+}
+// SET when comp out 1
+// RESET when comp out 0
+FlagStatus COMP_GetOutStatus(COMPX COMPx)
+{
+ if (COMPx == COMP1)
+ return (COMP->Cmp1.CTRL & COMP_CTRL_OUT_MASK) ? SET : RESET;
+ else
+ return (COMP->Cmp2.CTRL & COMP_CTRL_OUT_MASK) ? SET : RESET;
+}
+// get one comp interrupt flags
+FlagStatus COMP_GetIntStsOneComp(COMPX COMPx)
+{
+ return (COMP_GetIntSts() & (0x01 << COMPx)) ? SET : RESET;
+}
+
+// Lock see @COMP_LOCK
+void COMP_SetLock(uint32_t Lock)
+{
+ COMP->LOCK = Lock;
+}
+// IntEn see @COMP_INTEN_CMPIEN
+void COMP_SetIntEn(uint32_t IntEn)
+{
+ COMP->INTEN = IntEn;
+}
+// set comp2 xor output with comp1
+void COMP_CMP2XorOut(bool En)
+{
+ COMP->CMP2OSEL = (En==true)?0x1L:0x0L;
+}
+// set stop or lowpower mode that sel 32k clk
+void COMP_StopOrLowpower32KClkSel(bool En)
+{
+ COMP->LPCKSEL = (En==true)?0x1L:0x0L;
+}
+// set comp1 and comp2 component window compare mode
+void COMP_WindowModeEn(bool En)
+{
+ COMP->WINMODE = (En==true)?0x1L:0x0L;
+}
+
+
+/**
+ * @brief Set the COMP filter clock Prescaler value.
+ * @param COMPx where x can be 1 to 2 to select the COMP peripheral.
+ * @param FilPreVal Prescaler Value,Div clock = FilPreVal+1.
+ * @return void
+ */
+void COMP_SetFilterPrescaler(COMPX COMPx , uint16_t FilPreVal)
+{
+ if (COMPx == COMP1)
+ COMP->Cmp1.FILP=FilPreVal;
+ else
+ COMP->Cmp2.FILP=FilPreVal;
+}
+
+/**
+ * @brief Set the COMP filter control value.
+ * @param COMPx where x can be 1 to 2 to select the COMP peripheral.
+ * @param FilEn 1 for enable ,0 or disable
+ * @param TheresNum num under this value is noise
+ * @param SampPW total sample number in a window
+ * @return void
+ */
+void COMP_SetFilterControl(COMPX COMPx , uint8_t FilEn, uint8_t TheresNum , uint8_t SampPW)
+{
+ if (COMPx == COMP1)
+ COMP->Cmp1.FILC=(FilEn&COMP_FILC_FILEN_MASK)+((TheresNum<<1)&COMP_FILC_THRESH_MASK)+((SampPW<<6)&COMP_FILC_SAMPW_MASK);
+ else
+ COMP->Cmp2.FILC=(FilEn&COMP_FILC_FILEN_MASK)+((TheresNum<<1)&COMP_FILC_THRESH_MASK)+((SampPW<<6)&COMP_FILC_SAMPW_MASK);
+}
+
+/**
+ * @brief Set the COMP Hyst value.
+ * @param COMPx where x can be 1 to 2 to select the COMP peripheral.
+ * @param HYST specifies the HYST level.
+ * This parameter can be one of the following values:
+* @arg COMP_CTRL_HYST_NO Hyst disable
+* @arg COMP_CTRL_HYST_LOW Hyst level 5.1mV
+* @arg COMP_CTRL_HYST_MID Hyst level 15mV
+* @arg COMP_CTRL_HYST_HIGH Hyst level 25mV
+ * @return void
+ */
+void COMP_SetHyst(COMPX COMPx , COMP_CTRL_HYST HYST)
+{
+ uint32_t tmp;
+ if (COMPx == COMP1)
+ tmp=COMP->Cmp1.CTRL;
+ else
+ tmp=COMP->Cmp2.CTRL;
+
+ tmp&=~COMP_CTRL_HYST_HIGH;
+ tmp|=HYST;
+ if (COMPx == COMP1)
+ COMP->Cmp1.CTRL=tmp;
+ else
+ COMP->Cmp2.CTRL=tmp;
+}
+
+/**
+ * @brief Set the COMP Blanking source .
+ * @param COMPx where x can be 1 to 2 to select the COMP peripheral.
+ * @param BLK specifies the blanking source .
+ * This parameter can be one of the following values:
+* @arg COMP_CTRL_BLKING_NO Blanking disable
+* @arg COMP_CTRL_BLKING_TIM1_OC5 Blanking source TIM1_OC5
+* @arg COMP_CTRL_BLKING_TIM8_OC5 Blanking source TIM8_OC5
+ * @return void
+ */
+void COMP_SetBlanking(COMPX COMPx , COMP_CTRL_BLKING BLK)
+{
+ uint32_t tmp;
+ if (COMPx == COMP1)
+ tmp=COMP->Cmp1.CTRL;
+ else
+ tmp=COMP->Cmp2.CTRL;
+ tmp&=~(7<<16);
+ tmp|=BLK;
+ if (COMPx == COMP1)
+ COMP->Cmp1.CTRL=tmp;
+ else
+ COMP->Cmp2.CTRL=tmp;
+}
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_crc.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_crc.c
new file mode 100644
index 0000000000..955eae83ae
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_crc.c
@@ -0,0 +1,227 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_crc.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l43x_crc.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CRC
+ * @brief CRC driver modules
+ * @{
+ */
+
+/** @addtogroup CRC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Private_Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Resets the CRC Data register (DAT).
+ */
+void CRC32_ResetCrc(void)
+{
+ /* Reset CRC generator */
+ CRC->CRC32CTRL = CRC32_CTRL_RESET;
+}
+
+/**
+ * @brief Computes the 32-bit CRC of a given data word(32-bit).
+ * @param Data data word(32-bit) to compute its CRC
+ * @return 32-bit CRC
+ */
+uint32_t CRC32_CalcCrc(uint32_t Data)
+{
+ CRC->CRC32DAT = Data;
+
+ return (CRC->CRC32DAT);
+}
+
+/**
+ * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
+ * @param pBuffer pointer to the buffer containing the data to be computed
+ * @param BufferLength length of the buffer to be computed
+ * @return 32-bit CRC
+ */
+uint32_t CRC32_CalcBufCrc(uint32_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t index = 0;
+
+ for (index = 0; index < BufferLength; index++)
+ {
+ CRC->CRC32DAT = pBuffer[index];
+ }
+ return (CRC->CRC32DAT);
+}
+
+/**
+ * @brief Returns the current CRC value.
+ * @return 32-bit CRC
+ */
+uint32_t CRC32_GetCrc(void)
+{
+ return (CRC->CRC32DAT);
+}
+
+/**
+ * @brief Stores a 8-bit data in the Independent Data(ID) register.
+ * @param IDValue 8-bit value to be stored in the ID register
+ */
+void CRC32_SetIDat(uint8_t IDValue)
+{
+ CRC->CRC32IDAT = IDValue;
+}
+
+/**
+ * @brief Returns the 8-bit data stored in the Independent Data(ID) register
+ * @return 8-bit value of the ID register
+ */
+uint8_t CRC32_GetIDat(void)
+{
+ return (CRC->CRC32IDAT);
+}
+
+// CRC16 add
+void __CRC16_SetLittleEndianFmt(void)
+{
+ CRC->CRC16CTRL = CRC16_CTRL_LITTLE | CRC->CRC16CTRL;
+}
+void __CRC16_SetBigEndianFmt(void)
+{
+ CRC->CRC16CTRL = CRC16_CTRL_BIG & CRC->CRC16CTRL;
+}
+void __CRC16_SetCleanEnable(void)
+{
+ CRC->CRC16CTRL = CRC16_CTRL_RESET | CRC->CRC16CTRL;
+}
+void __CRC16_SetCleanDisable(void)
+{
+ CRC->CRC16CTRL = CRC16_CTRL_NO_RESET & CRC->CRC16CTRL;
+}
+
+uint16_t __CRC16_CalcCrc(uint8_t Data)
+{
+ CRC->CRC16DAT = Data;
+ return (CRC->CRC16D);
+}
+
+void __CRC16_SetCrc(uint8_t Data)
+{
+ CRC->CRC16DAT = Data;
+}
+
+uint16_t __CRC16_GetCrc(void)
+{
+ return (CRC->CRC16D);
+}
+
+void __CRC16_SetLRC(uint8_t Data)
+{
+ CRC->LRC = Data;
+}
+
+uint8_t __CRC16_GetLRC(void)
+{
+ return (CRC->LRC);
+}
+
+uint16_t CRC16_CalcBufCrc(uint8_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t index = 0;
+
+ CRC->CRC16D = 0x00;
+ for (index = 0; index < BufferLength; index++)
+ {
+ CRC->CRC16DAT = pBuffer[index];
+ }
+ return (CRC->CRC16D);
+}
+
+uint16_t CRC16_CalcCRC(uint8_t Data)
+{
+ CRC->CRC16DAT = Data;
+
+ return (CRC->CRC16D);
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_dac.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_dac.c
new file mode 100644
index 0000000000..953728cbe3
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_dac.c
@@ -0,0 +1,357 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_dac.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l43x_dac.h"
+#include "n32l43x_rcc.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DAC
+ * @brief DAC driver modules
+ * @{
+ */
+
+/** @addtogroup DAC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Private_Defines
+ * @{
+ */
+
+/* CTRL register Mask */
+#define CTRL_CLEAR_MASK ((uint32_t)0x00000FFE)
+
+/* DAC Dual Channels SWTRIG masks */
+#define DUAL_SWTRIG_SET ((uint32_t)0x00000001)
+#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFE)
+
+/* DCH registers offsets */
+#define DR12CH_OFFSET ((uint32_t)0x00000008)
+
+/* DATO register offset */
+#define DATO_OFFSET ((uint32_t)0x0000002C)
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the DAC peripheral registers to their default reset values.
+ */
+void DAC_DeInit(void)
+{
+ /* Enable DAC reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_DAC, ENABLE);
+ /* Release DAC from reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_DAC, DISABLE);
+}
+
+/**
+ * @brief Initializes the DAC peripheral according to the specified
+ * parameters in the DAC_InitStruct.
+ * @param DAC_Channel the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1 DAC Channel1 selected
+ * @arg DAC_CHANNEL_2 DAC Channel2 selected
+ * @param DAC_InitStruct pointer to a DAC_InitType structure that
+ * contains the configuration information for the specified DAC channel.
+ */
+void DAC_Init(DAC_InitType* DAC_InitStruct)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;
+ /* Check the DAC parameters */
+ assert_param(IS_DAC_TRIGGER(DAC_InitStruct->Trigger));
+ assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->WaveGen));
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->LfsrUnMaskTriAmp));
+ assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->BufferOutput));
+ /*---------------------------- DAC CTRL Configuration --------------------------*/
+ /* Get the DAC CTRL value */
+ tmpreg1 = DAC->CTRL;
+ /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
+ tmpreg1 &= ~(CTRL_CLEAR_MASK );
+ /* Configure for the selected DAC channel: buffer output, trigger, wave generation,
+ mask/amplitude for wave generation */
+ /* Set TSELx and TENx bits according to Trigger value */
+ /* Set WAVEx bits according to WaveGen value */
+ /* Set MAMPx bits according to LfsrUnMaskTriAmp value */
+ /* Set BOFFx bit according to BufferOutput value */
+ tmpreg2 = (DAC_InitStruct->Trigger | DAC_InitStruct->WaveGen | DAC_InitStruct->LfsrUnMaskTriAmp
+ | DAC_InitStruct->BufferOutput);
+ /* Calculate CTRL register value depending on DAC_Channel */
+ tmpreg1 |= tmpreg2 ;
+ /* Write to DAC CTRL */
+ DAC->CTRL = tmpreg1;
+}
+
+/**
+ * @brief Fills each DAC_InitStruct member with its default value.
+ * @param DAC_InitStruct pointer to a DAC_InitType structure which will
+ * be initialized.
+ */
+void DAC_ClearStruct(DAC_InitType* DAC_InitStruct)
+{
+ /*--------------- Reset DAC init structure parameters values -----------------*/
+ /* Initialize the Trigger member */
+ DAC_InitStruct->Trigger = DAC_TRG_NONE;
+ /* Initialize the WaveGen member */
+ DAC_InitStruct->WaveGen = DAC_WAVEGEN_NONE;
+ /* Initialize the LfsrUnMaskTriAmp member */
+ DAC_InitStruct->LfsrUnMaskTriAmp = DAC_UNMASK_LFSRBIT0;
+ /* Initialize the BufferOutput member */
+ DAC_InitStruct->BufferOutput = DAC_BUFFOUTPUT_ENABLE;
+}
+
+/**
+ * @brief Enables or disables the specified DAC channel.
+ * @param DAC_Channel the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1 DAC Channel1 selected
+ * @arg DAC_CHANNEL_2 DAC Channel2 selected
+ * @param Cmd new state of the DAC channel.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DAC_Enable(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected DAC channel */
+ DAC->CTRL |= DAC_CTRL_CHEN ;
+ }
+ else
+ {
+ /* Disable the selected DAC channel */
+ DAC->CTRL &= ~DAC_CTRL_CHEN ;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified DAC channel DMA request.
+ * @param DAC_Channel the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1 DAC Channel1 selected
+ * @arg DAC_CHANNEL_2 DAC Channel2 selected
+ * @param Cmd new state of the selected DAC channel DMA request.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DAC_DmaEnable(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected DAC channel DMA request */
+ DAC->CTRL |= DAC_CTRL_DMAEN;
+ }
+ else
+ {
+ /* Disable the selected DAC channel DMA request */
+ DAC->CTRL &= ~DAC_CTRL_DMAEN;
+ }
+}
+
+/**
+ * @brief Enables or disables the selected DAC channel software trigger.
+ * @param DAC_Channel the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1 DAC Channel1 selected
+ * @arg DAC_CHANNEL_2 DAC Channel2 selected
+ * @param Cmd new state of the selected DAC channel software trigger.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DAC_SoftTrgEnable(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable software trigger for the selected DAC channel */
+ DAC->SOTTR |= DAC_SOTTR_TREN ;
+ }
+ else
+ {
+ /* Disable software trigger for the selected DAC channel */
+ DAC->SOTTR &= ~(DAC_SOTTR_TREN);
+ }
+}
+
+/**
+ * @brief Enables or disables simultaneously the two DAC channels software
+ * triggers.
+ * @param Cmd new state of the DAC channels software triggers.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DAC_SoftwareTrgEnable(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable software trigger for both DAC channels */
+ DAC->SOTTR |= DUAL_SWTRIG_SET;
+ }
+ else
+ {
+ /* Disable software trigger for both DAC channels */
+ DAC->SOTTR &= DUAL_SWTRIG_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the selected DAC channel wave generation.
+ * @param DAC_Channel the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1 DAC Channel1 selected
+ * @arg DAC_CHANNEL_2 DAC Channel2 selected
+ * @param DAC_Wave Specifies the wave type to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg DAC_WAVE_NOISE noise wave generation
+ * @arg DAC_WAVE_TRIANGLE triangle wave generation
+ * @param Cmd new state of the selected DAC channel wave generation.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DAC_WaveGenerationEnable(uint32_t DAC_Wave, FunctionalState Cmd)
+{
+ __IO uint32_t tmp = 0;
+ /* Check the parameters */
+ assert_param(IS_DAC_WAVE(DAC_Wave));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ tmp=DAC->CTRL;
+ tmp&=~(3<<6);
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected wave generation for the selected DAC channel */
+ tmp |= DAC_Wave;
+ }
+ else
+ {
+ /* Disable the selected wave generation for the selected DAC channel */
+ tmp&=~(3<<6);
+ }
+ DAC->CTRL =tmp;
+}
+
+/**
+ * @brief Set the specified data holding register value for DAC channel1.
+ * @param DAC_Align Specifies the data alignment for DAC channel1.
+ * This parameter can be one of the following values:
+ * @arg DAC_ALIGN_R_8BIT 8bit right data alignment selected
+ * @arg DAC_ALIGN_L_12BIT 12bit left data alignment selected
+ * @arg DAC_ALIGN_R_12BIT 12bit right data alignment selected
+ * @param Data Data to be loaded in the selected data holding register.
+ */
+void DAC_SetChData(uint32_t DAC_Align, uint16_t Data)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALIGN(DAC_Align));
+ assert_param(IS_DAC_DATA(Data));
+
+ tmp = (uint32_t)DAC_BASE;
+ tmp += DR12CH_OFFSET + DAC_Align;
+
+ /* Set the DAC channel1 selected data holding register */
+ *(__IO uint32_t*)tmp = Data;
+}
+
+
+
+
+
+/**
+ * @brief Returns the last data output value of the selected DAC channel.
+ * @param DAC_Channel the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1 DAC Channel1 selected
+ * @arg DAC_CHANNEL_2 DAC Channel2 selected
+ * @return The selected DAC channel data output value.
+ */
+uint16_t DAC_GetOutputDataVal(void)
+{
+ __IO uint32_t tmp = 0;
+
+ tmp = (uint32_t)DAC_BASE;
+ tmp += DATO_OFFSET;
+
+ /* Returns the DAC channel data output register value */
+ return (uint16_t)(*(__IO uint32_t*)tmp);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_dbg.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_dbg.c
new file mode 100644
index 0000000000..ac09c9731b
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_dbg.c
@@ -0,0 +1,246 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_dbg.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l43x_dbg.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DBG
+ * @brief DBG driver modules
+ * @{
+ */
+
+/** @addtogroup DBGMCU_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Private_Defines
+ * @{
+ */
+
+#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Private_Functions
+ * @{
+ */
+
+
+void GetUCID(uint8_t *UCIDbuf)
+{
+ uint8_t num = 0;
+ uint32_t* ucid_addr = (void*)0;
+ uint32_t temp = 0;
+
+ ucid_addr = (uint32_t*)UCID_BASE;
+
+ for (num = 0; num < UCID_LENGTH;)
+ {
+ temp = *(__IO uint32_t*)(ucid_addr++);
+ UCIDbuf[num++] = (temp & 0xFF);
+ UCIDbuf[num++] = (temp & 0xFF00) >> 8;
+ UCIDbuf[num++] = (temp & 0xFF0000) >> 16;
+ UCIDbuf[num++] = (temp & 0xFF000000) >> 24;
+ }
+}
+
+/**
+ * @brief Returns the UID.
+ * @return UID
+ */
+
+void GetUID(uint8_t *UIDbuf)
+{
+ uint8_t num = 0;
+ uint32_t* uid_addr = (void*)0;
+ uint32_t temp = 0;
+
+ uid_addr = (uint32_t*)UID_BASE;
+
+ for (num = 0; num < UID_LENGTH;)
+ {
+ temp = *(__IO uint32_t*)(uid_addr++);
+ UIDbuf[num++] = (temp & 0xFF);
+ UIDbuf[num++] = (temp & 0xFF00) >> 8;
+ UIDbuf[num++] = (temp & 0xFF0000) >> 16;
+ UIDbuf[num++] = (temp & 0xFF000000) >> 24;
+ }
+}
+
+/**
+ * @brief Returns the DBGMCU_ID.
+ * @return DBGMCU_ID
+ */
+
+void GetDBGMCU_ID(uint8_t *DBGMCU_IDbuf)
+{
+ uint8_t num = 0;
+ uint32_t* dbgid_addr = (void*)0;
+ uint32_t temp = 0;
+
+ dbgid_addr = (uint32_t*)DBGMCU_ID_BASE;
+ for (num = 0; num < DBGMCU_ID_LENGTH;)
+ {
+ temp = *(__IO uint32_t*)(dbgid_addr++);
+ DBGMCU_IDbuf[num++] = (temp & 0xFF);
+ DBGMCU_IDbuf[num++] = (temp & 0xFF00) >> 8;
+ DBGMCU_IDbuf[num++] = (temp & 0xFF0000) >> 16;
+ DBGMCU_IDbuf[num++] = (temp & 0xFF000000) >> 24;
+ }
+}
+
+/**
+ * @brief Returns the device revision number.
+ * @return Device revision identifier
+ */
+uint32_t DBG_GetRevNum(void)
+{
+ return (DBG->ID & 0x00FF);
+}
+
+/**
+ * @brief Returns the device identifier.
+ * @return Device identifier
+ */
+uint32_t DBG_GetDevNum(void)
+{
+ uint32_t id = DBG->ID;
+ return ((id & 0x00F00000) >> 20) | ((id & 0xFF00) >> 4);
+}
+
+/**
+ * @brief Configures the specified peripheral and low power mode behavior
+ * when the MCU under Debug mode.
+ * @param DBG_Periph specifies the peripheral and low power mode.
+ * This parameter can be any combination of the following values:
+ * @arg DBG_SLEEP Keep debugger connection during SLEEP mode
+ * @arg DBG_STOP Keep debugger connection during STOP mode
+ * @arg DBG_STDBY Keep debugger connection during STANDBY mode
+ * @arg DBG_IWDG_STOP Debug IWDG stopped when Core is halted
+ * @arg DBG_WWDG_STOP Debug WWDG stopped when Core is halted
+ * @arg DBG_TIM1_STOP TIM1 counter stopped when Core is halted
+ * @arg DBG_TIM2_STOP TIM2 counter stopped when Core is halted
+ * @arg DBG_TIM3_STOP TIM3 counter stopped when Core is halted
+ * @arg DBG_TIM4_STOP TIM4 counter stopped when Core is halted
+ * @arg DBG_CAN_STOP Debug CAN stopped when Core is halted
+ * @arg DBG_I2C1SMBUS_TIMEOUT I2C1 SMBUS timeout mode stopped when Core is halted
+ * @arg DBG_I2C2SMBUS_TIMEOUT I2C2 SMBUS timeout mode stopped when Core is halted
+ * @arg DBG_TIM8_STOP TIM8 counter stopped when Core is halted
+ * @arg DBG_TIM5_STOP TIM5 counter stopped when Core is halted
+ * @arg DBG_TIM6_STOP TIM6 counter stopped when Core is halted
+ * @arg DBG_TIM7_STOP TIM7 counter stopped when Core is halted
+ * @arg DBG_TIM9_STOP TIM9 counter stopped when Core is halted
+
+ * @param Cmd new state of the specified peripheral in Debug mode.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DBG_ConfigPeriph(uint32_t DBG_Periph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_DBGMCU_PERIPH(DBG_Periph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ DBG->CTRL |= DBG_Periph;
+ }
+ else
+ {
+ DBG->CTRL &= ~DBG_Periph;
+ }
+}
+
+/**
+ * @brief Get FLASH size of this chip.
+ *
+ * @return FLASH size in bytes.
+ */
+uint32_t DBG_GetFlashSize(void)
+{
+ return (DBG->ID & 0x000F0000);
+}
+
+/**
+ * @brief Get SRAM size of this chip.
+ *
+ * @return SRAM size in bytes.
+ */
+uint32_t DBG_GetSramSize(void)
+{
+ return (((DBG->ID & 0xF0000000) >> 28) + 1) << 14;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_dma.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_dma.c
new file mode 100644
index 0000000000..ba84cdb3bc
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_dma.c
@@ -0,0 +1,686 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_dma.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l43x_dma.h"
+#include "n32l43x_rcc.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @brief DMA driver modules
+ * @{
+ */
+
+/** @addtogroup DMA_Private_TypesDefinitions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Defines
+ * @{
+ */
+
+/* DMA Channelx interrupt pending bit masks */
+#define DMA_CH1_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF1 | DMA_INTSTS_TXCF1 | DMA_INTSTS_HTXF1 | DMA_INTSTS_ERRF1))
+#define DMA_CH2_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF2 | DMA_INTSTS_TXCF2 | DMA_INTSTS_HTXF2 | DMA_INTSTS_ERRF2))
+#define DMA_CH3_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF3 | DMA_INTSTS_TXCF3 | DMA_INTSTS_HTXF3 | DMA_INTSTS_ERRF3))
+#define DMA_CH4_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF4 | DMA_INTSTS_TXCF4 | DMA_INTSTS_HTXF4 | DMA_INTSTS_ERRF4))
+#define DMA_CH5_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF5 | DMA_INTSTS_TXCF5 | DMA_INTSTS_HTXF5 | DMA_INTSTS_ERRF5))
+#define DMA_CH6_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF6 | DMA_INTSTS_TXCF6 | DMA_INTSTS_HTXF6 | DMA_INTSTS_ERRF6))
+#define DMA_CH7_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF7 | DMA_INTSTS_TXCF7 | DMA_INTSTS_HTXF7 | DMA_INTSTS_ERRF7))
+#define DMA_CH8_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF8 | DMA_INTSTS_TXCF8 | DMA_INTSTS_HTXF8 | DMA_INTSTS_ERRF8))
+
+
+/* DMA CHCFGx registers Masks, MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
+#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the DMAy Channelx registers to their default reset
+ * values.
+ * @param DMAyChx where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 8 for DMA1 and 1 to 8 for DMA2 to select the DMA Channel.
+ */
+void DMA_DeInit(DMA_ChannelType* DMAChx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAChx));
+
+ /* Disable the selected DMAy Channelx */
+ DMAChx->CHCFG &= (uint16_t)(~DMA_CHCFG1_CHEN);
+
+ /* Reset DMAy Channelx control register */
+ DMAChx->CHCFG = 0;
+
+ /* Reset DMAy Channelx remaining bytes register */
+ DMAChx->TXNUM = 0;
+
+ /* Reset DMAy Channelx peripheral address register */
+ DMAChx->PADDR = 0;
+
+ /* Reset DMAy Channelx memory address register */
+ DMAChx->MADDR = 0;
+
+ if (DMAChx == DMA_CH1)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel1 */
+ DMA->INTCLR |= DMA_CH1_INT_MASK;
+ }
+ else if (DMAChx == DMA_CH2)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel2 */
+ DMA->INTCLR |= DMA_CH2_INT_MASK;
+ }
+ else if (DMAChx == DMA_CH3)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel3 */
+ DMA->INTCLR |= DMA_CH3_INT_MASK;
+ }
+ else if (DMAChx == DMA_CH4)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel4 */
+ DMA->INTCLR |= DMA_CH4_INT_MASK;
+ }
+ else if (DMAChx == DMA_CH5)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel5 */
+ DMA->INTCLR |= DMA_CH5_INT_MASK;
+ }
+ else if (DMAChx == DMA_CH6)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel6 */
+ DMA->INTCLR |= DMA_CH6_INT_MASK;
+ }
+ else if (DMAChx == DMA_CH7)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel7 */
+ DMA->INTCLR |= DMA_CH7_INT_MASK;
+ }
+ else if (DMAChx == DMA_CH8)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel8 */
+ DMA->INTCLR |= DMA_CH8_INT_MASK;
+ }
+}
+
+/**
+ * @brief Initializes the DMAy Channelx according to the specified
+ * parameters in the DMA_InitParam.
+ * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel.
+ * @param DMA_InitParam pointer to a DMA_InitType structure that
+ * contains the configuration information for the specified DMA Channel.
+ */
+void DMA_Init(DMA_ChannelType* DMAChx, DMA_InitType* DMA_InitParam)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAChx));
+ assert_param(IS_DMA_DIR(DMA_InitParam->Direction));
+ assert_param(IS_DMA_BUF_SIZE(DMA_InitParam->BufSize));
+ assert_param(IS_DMA_PERIPH_INC_STATE(DMA_InitParam->PeriphInc));
+ assert_param(IS_DMA_MEM_INC_STATE(DMA_InitParam->DMA_MemoryInc));
+ assert_param(IS_DMA_PERIPH_DATA_SIZE(DMA_InitParam->PeriphDataSize));
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitParam->MemDataSize));
+ assert_param(IS_DMA_MODE(DMA_InitParam->CircularMode));
+ assert_param(IS_DMA_PRIORITY(DMA_InitParam->Priority));
+ assert_param(IS_DMA_M2M_STATE(DMA_InitParam->Mem2Mem));
+
+ /*--------------------------- DMAy Channelx CHCFG Configuration -----------------*/
+ /* Get the DMAyChx CHCFG value */
+ tmpregister = DMAChx->CHCFG;
+ /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
+ tmpregister &= CCR_CLEAR_Mask;
+ /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
+ /* Set DIR bit according to Direction value */
+ /* Set CIRC bit according to CircularMode value */
+ /* Set PINC bit according to PeriphInc value */
+ /* Set MINC bit according to DMA_MemoryInc value */
+ /* Set PSIZE bits according to PeriphDataSize value */
+ /* Set MSIZE bits according to MemDataSize value */
+ /* Set PL bits according to Priority value */
+ /* Set the MEM2MEM bit according to Mem2Mem value */
+ tmpregister |= DMA_InitParam->Direction | DMA_InitParam->CircularMode | DMA_InitParam->PeriphInc
+ | DMA_InitParam->DMA_MemoryInc | DMA_InitParam->PeriphDataSize | DMA_InitParam->MemDataSize
+ | DMA_InitParam->Priority | DMA_InitParam->Mem2Mem;
+
+ /* Write to DMAy Channelx CHCFG */
+ DMAChx->CHCFG = tmpregister;
+
+ /*--------------------------- DMAy Channelx TXNUM Configuration ---------------*/
+ /* Write to DMAy Channelx TXNUM */
+ DMAChx->TXNUM = DMA_InitParam->BufSize;
+
+ /*--------------------------- DMAy Channelx PADDR Configuration ----------------*/
+ /* Write to DMAy Channelx PADDR */
+ DMAChx->PADDR = DMA_InitParam->PeriphAddr;
+
+ /*--------------------------- DMAy Channelx MADDR Configuration ----------------*/
+ /* Write to DMAy Channelx MADDR */
+ DMAChx->MADDR = DMA_InitParam->MemAddr;
+}
+
+/**
+ * @brief Fills each DMA_InitParam member with its default value.
+ * @param DMA_InitParam pointer to a DMA_InitType structure which will
+ * be initialized.
+ */
+void DMA_StructInit(DMA_InitType* DMA_InitParam)
+{
+ /*-------------- Reset DMA init structure parameters values ------------------*/
+ /* Initialize the PeriphAddr member */
+ DMA_InitParam->PeriphAddr = 0;
+ /* Initialize the MemAddr member */
+ DMA_InitParam->MemAddr = 0;
+ /* Initialize the Direction member */
+ DMA_InitParam->Direction = DMA_DIR_PERIPH_SRC;
+ /* Initialize the BufSize member */
+ DMA_InitParam->BufSize = 0;
+ /* Initialize the PeriphInc member */
+ DMA_InitParam->PeriphInc = DMA_PERIPH_INC_DISABLE;
+ /* Initialize the DMA_MemoryInc member */
+ DMA_InitParam->DMA_MemoryInc = DMA_MEM_INC_DISABLE;
+ /* Initialize the PeriphDataSize member */
+ DMA_InitParam->PeriphDataSize = DMA_PERIPH_DATA_SIZE_BYTE;
+ /* Initialize the MemDataSize member */
+ DMA_InitParam->MemDataSize = DMA_MemoryDataSize_Byte;
+ /* Initialize the CircularMode member */
+ DMA_InitParam->CircularMode = DMA_MODE_NORMAL;
+ /* Initialize the Priority member */
+ DMA_InitParam->Priority = DMA_PRIORITY_LOW;
+ /* Initialize the Mem2Mem member */
+ DMA_InitParam->Mem2Mem = DMA_M2M_DISABLE;
+}
+
+/**
+ * @brief Enables or disables the specified DMAy Channelx.
+ * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel.
+ * @param Cmd new state of the DMA Channelx.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DMA_EnableChannel(DMA_ChannelType* DMAChx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAChx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected DMAy Channelx */
+ DMAChx->CHCFG |= DMA_CHCFG1_CHEN;
+ }
+ else
+ {
+ /* Disable the selected DMAy Channelx */
+ DMAChx->CHCFG &= (uint16_t)(~DMA_CHCFG1_CHEN);
+ }
+}
+
+/**
+ * @brief Enables or disables the specified DMAy Channelx interrupts.
+ * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel.
+ * @param DMAInt specifies the DMA interrupts sources to be enabled
+ * or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_INT_TXC Transfer complete interrupt mask
+ * @arg DMA_INT_HTX Half transfer interrupt mask
+ * @arg DMA_INT_ERR Transfer error interrupt mask
+ * @param Cmd new state of the specified DMA interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DMA_ConfigInt(DMA_ChannelType* DMAChx, uint32_t DMAInt, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAChx));
+ assert_param(IS_DMA_CONFIG_INT(DMAInt));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected DMA interrupts */
+ DMAChx->CHCFG |= DMAInt;
+ }
+ else
+ {
+ /* Disable the selected DMA interrupts */
+ DMAChx->CHCFG &= ~DMAInt;
+ }
+}
+
+/**
+ * @brief Sets the number of data units in the current DMAy Channelx transfer.
+ * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel.
+ * @param DataNumber The number of data units in the current DMAy Channelx
+ * transfer.
+ * @note This function can only be used when the DMAyChx is disabled.
+ */
+void DMA_SetCurrDataCounter(DMA_ChannelType* DMAChx, uint16_t DataNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAChx));
+
+ /*--------------------------- DMAy Channelx TXNUM Configuration ---------------*/
+ /* Write to DMA Channelx TXNUM */
+ DMAChx->TXNUM = DataNumber;
+}
+
+/**
+ * @brief Returns the number of remaining data units in the current
+ * DMA Channelx transfer.
+ * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel.
+ * @return The number of remaining data units in the current DMA Channelx
+ * transfer.
+ */
+uint16_t DMA_GetCurrDataCounter(DMA_ChannelType* DMAChx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAChx));
+ /* Return the number of remaining data units for DMAy Channelx */
+ return ((uint16_t)(DMAChx->TXNUM));
+}
+
+/**
+ * @brief Checks whether the specified DMA Channelx flag is set or not.
+ * @param DMAFlag specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg DMA_FLAG_GL1 DMA Channel1 global flag.
+ * @arg DMA_FLAG_TC1 DMA Channel1 transfer complete flag.
+ * @arg DMA_FLAG_HT1 DMA Channel1 half transfer flag.
+ * @arg DMA_FLAG_TE1 DMA Channel1 transfer error flag.
+ * @arg DMA_FLAG_GL2 DMA Channel2 global flag.
+ * @arg DMA_FLAG_TC2 DMA Channel2 transfer complete flag.
+ * @arg DMA_FLAG_HT2 DMA Channel2 half transfer flag.
+ * @arg DMA_FLAG_TE2 DMA Channel2 transfer error flag.
+ * @arg DMA_FLAG_GL3 DMA Channel3 global flag.
+ * @arg DMA_FLAG_TC3 DMA Channel3 transfer complete flag.
+ * @arg DMA_FLAG_HT3 DMA Channel3 half transfer flag.
+ * @arg DMA_FLAG_TE3 DMA Channel3 transfer error flag.
+ * @arg DMA_FLAG_GL4 DMA Channel4 global flag.
+ * @arg DMA_FLAG_TC4 DMA Channel4 transfer complete flag.
+ * @arg DMA_FLAG_HT4 DMA Channel4 half transfer flag.
+ * @arg DMA_FLAG_TE4 DMA Channel4 transfer error flag.
+ * @arg DMA_FLAG_GL5 DMA Channel5 global flag.
+ * @arg DMA_FLAG_TC5 DMA Channel5 transfer complete flag.
+ * @arg DMA_FLAG_HT5 DMA Channel5 half transfer flag.
+ * @arg DMA_FLAG_TE5 DMA Channel5 transfer error flag.
+ * @arg DMA_FLAG_GL6 DMA Channel6 global flag.
+ * @arg DMA_FLAG_TC6 DMA Channel6 transfer complete flag.
+ * @arg DMA_FLAG_HT6 DMA Channel6 half transfer flag.
+ * @arg DMA_FLAG_TE6 DMA Channel6 transfer error flag.
+ * @arg DMA_FLAG_GL7 DMA Channel7 global flag.
+ * @arg DMA_FLAG_TC7 DMA Channel7 transfer complete flag.
+ * @arg DMA_FLAG_HT7 DMA Channel7 half transfer flag.
+ * @arg DMA_FLAG_TE7 DMA Channel7 transfer error flag.
+ * @arg DMA_FLAG_GL8 DMA Channel7 global flag.
+ * @arg DMA_FLAG_TC8 DMA Channel7 transfer complete flag.
+ * @arg DMA_FLAG_HT8 DMA Channel7 half transfer flag.
+ * @arg DMA_FLAG_TE8 DMA Channel7 transfer error flag.
+ * @param DMAy DMA
+ * This parameter can be one of the following values:
+ * @arg DMA .
+ * @return The new state of DMAFlag (SET or RESET).
+ */
+FlagStatus DMA_GetFlagStatus(uint32_t DMAFlag, DMA_Module* DMAy)
+{
+ FlagStatus bitstatus = RESET;
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_GET_FLAG(DMAFlag));
+
+ /* Calculate the used DMAy */
+ /* Get DMAy INTSTS register value */
+ tmpregister = DMAy->INTSTS;
+
+ /* Check the status of the specified DMAy flag */
+ if ((tmpregister & DMAFlag) != (uint32_t)RESET)
+ {
+ /* DMAyFlag is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DMAyFlag is reset */
+ bitstatus = RESET;
+ }
+
+ /* Return the DMAyFlag status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the DMA Channelx's pending flags.
+ * @param DMAFlag specifies the flag to clear.
+ * This parameter can be any combination (for the same DMA) of the following values:
+ * @arg DMA_FLAG_GL1 DMA Channel1 global flag.
+ * @arg DMA_FLAG_TC1 DMA Channel1 transfer complete flag.
+ * @arg DMA_FLAG_HT1 DMA Channel1 half transfer flag.
+ * @arg DMA_FLAG_TE1 DMA Channel1 transfer error flag.
+ * @arg DMA_FLAG_GL2 DMA Channel2 global flag.
+ * @arg DMA_FLAG_TC2 DMA Channel2 transfer complete flag.
+ * @arg DMA_FLAG_HT2 DMA Channel2 half transfer flag.
+ * @arg DMA_FLAG_TE2 DMA Channel2 transfer error flag.
+ * @arg DMA_FLAG_GL3 DMA Channel3 global flag.
+ * @arg DMA_FLAG_TC3 DMA Channel3 transfer complete flag.
+ * @arg DMA_FLAG_HT3 DMA Channel3 half transfer flag.
+ * @arg DMA_FLAG_TE3 DMA Channel3 transfer error flag.
+ * @arg DMA_FLAG_GL4 DMA Channel4 global flag.
+ * @arg DMA_FLAG_TC4 DMA Channel4 transfer complete flag.
+ * @arg DMA_FLAG_HT4 DMA Channel4 half transfer flag.
+ * @arg DMA_FLAG_TE4 DMA Channel4 transfer error flag.
+ * @arg DMA_FLAG_GL5 DMA Channel5 global flag.
+ * @arg DMA_FLAG_TC5 DMA Channel5 transfer complete flag.
+ * @arg DMA_FLAG_HT5 DMA Channel5 half transfer flag.
+ * @arg DMA_FLAG_TE5 DMA Channel5 transfer error flag.
+ * @arg DMA_FLAG_GL6 DMA Channel6 global flag.
+ * @arg DMA_FLAG_TC6 DMA Channel6 transfer complete flag.
+ * @arg DMA_FLAG_HT6 DMA Channel6 half transfer flag.
+ * @arg DMA_FLAG_TE6 DMA Channel6 transfer error flag.
+ * @arg DMA_FLAG_GL7 DMA Channel7 global flag.
+ * @arg DMA_FLAG_TC7 DMA Channel7 transfer complete flag.
+ * @arg DMA_FLAG_HT7 DMA Channel7 half transfer flag.
+ * @arg DMA_FLAG_TE7 DMA Channel7 transfer error flag.
+ * @arg DMA_FLAG_GL8 DMA Channel8 global flag.
+ * @arg DMA_FLAG_TC8 DMA Channel8 transfer complete flag.
+ * @arg DMA_FLAG_HT8 DMA Channel8 half transfer flag.
+ * @arg DMA_FLAG_TE8 DMA Channel8 transfer error flag.
+ * @param DMA DMA
+ * This parameter can be one of the following values:
+ * @arg DMA .
+ */
+void DMA_ClearFlag(uint32_t DMAFlag, DMA_Module* DMAy)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_CLEAR_FLAG(DMAFlag));
+
+ /* Calculate the used DMAy */
+ /* Clear the selected DMAy flags */
+ DMAy->INTCLR = DMAFlag;
+}
+
+/**
+ * @brief Checks whether the specified DMA Channelx interrupt has occurred or not.
+ * @param DMA_IT specifies the DMAy interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DMA_INT_GLB1 DMA Channel1 global interrupt.
+ * @arg DMA_INT_TXC1 DMA Channel1 transfer complete interrupt.
+ * @arg DMA_INT_HTX1 DMA Channel1 half transfer interrupt.
+ * @arg DMA_INT_ERR1 DMA Channel1 transfer error interrupt.
+ * @arg DMA_INT_GLB2 DMA Channel2 global interrupt.
+ * @arg DMA_INT_TXC2 DMA Channel2 transfer complete interrupt.
+ * @arg DMA_INT_HTX2 DMA Channel2 half transfer interrupt.
+ * @arg DMA_INT_ERR2 DMA Channel2 transfer error interrupt.
+ * @arg DMA_INT_GLB3 DMA Channel3 global interrupt.
+ * @arg DMA_INT_TXC3 DMA Channel3 transfer complete interrupt.
+ * @arg DMA_INT_HTX3 DMA Channel3 half transfer interrupt.
+ * @arg DMA_INT_ERR3 DMA Channel3 transfer error interrupt.
+ * @arg DMA_INT_GLB4 DMA Channel4 global interrupt.
+ * @arg DMA_INT_TXC4 DMA Channel4 transfer complete interrupt.
+ * @arg DMA_INT_HTX4 DMA Channel4 half transfer interrupt.
+ * @arg DMA_INT_ERR4 DMA Channel4 transfer error interrupt.
+ * @arg DMA_INT_GLB5 DMA Channel5 global interrupt.
+ * @arg DMA_INT_TXC5 DMA Channel5 transfer complete interrupt.
+ * @arg DMA_INT_HTX5 DMA Channel5 half transfer interrupt.
+ * @arg DMA_INT_ERR5 DMA Channel5 transfer error interrupt.
+ * @arg DMA_INT_GLB6 DMA Channel6 global interrupt.
+ * @arg DMA_INT_TXC6 DMA Channel6 transfer complete interrupt.
+ * @arg DMA_INT_HTX6 DMA Channel6 half transfer interrupt.
+ * @arg DMA_INT_ERR6 DMA Channel6 transfer error interrupt.
+ * @arg DMA_INT_GLB7 DMA Channel7 global interrupt.
+ * @arg DMA_INT_TXC7 DMA Channel7 transfer complete interrupt.
+ * @arg DMA_INT_HTX7 DMA Channel7 half transfer interrupt.
+ * @arg DMA_INT_ERR7 DMA Channel7 transfer error interrupt.
+ * @arg DMA_INT_GLB8 DMA Channel8 global interrupt.
+ * @arg DMA_INT_TXC8 DMA Channel8 transfer complete interrupt.
+ * @arg DMA_INT_HTX8 DMA Channel8 half transfer interrupt.
+ * @arg DMA_INT_ERR8 DMA Channel8 transfer error interrupt.
+ * @param DMA DMA
+ * This parameter can be one of the following values:
+ * @arg DMA .
+ * @return The new state of DMA_IT (SET or RESET).
+ */
+INTStatus DMA_GetIntStatus(uint32_t DMA_IT, DMA_Module* DMAy)
+{
+ INTStatus bitstatus = RESET;
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_GET_IT(DMA_IT));
+
+ /* Calculate the used DMA */
+ /* Get DMAy INTSTS register value */
+ tmpregister = DMAy->INTSTS;
+
+ /* Check the status of the specified DMAy interrupt */
+ if ((tmpregister & DMA_IT) != (uint32_t)RESET)
+ {
+ /* DMAy_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DMAy_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the DMAInt status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the DMA Channelx's interrupt pending bits.
+ * @param DMA_IT specifies the DMA interrupt pending bit to clear.
+ * This parameter can be any combination (for the same DMA) of the following values:
+ * @arg DMA_INT_GLB1 DMA Channel1 global interrupt.
+ * @arg DMA_INT_TXC1 DMA Channel1 transfer complete interrupt.
+ * @arg DMA_INT_HTX1 DMA Channel1 half transfer interrupt.
+ * @arg DMA_INT_ERR1 DMA Channel1 transfer error interrupt.
+ * @arg DMA_INT_GLB2 DMA Channel2 global interrupt.
+ * @arg DMA_INT_TXC2 DMA Channel2 transfer complete interrupt.
+ * @arg DMA_INT_HTX2 DMA Channel2 half transfer interrupt.
+ * @arg DMA_INT_ERR2 DMA Channel2 transfer error interrupt.
+ * @arg DMA_INT_GLB3 DMA Channel3 global interrupt.
+ * @arg DMA_INT_TXC3 DMA Channel3 transfer complete interrupt.
+ * @arg DMA_INT_HTX3 DMA Channel3 half transfer interrupt.
+ * @arg DMA_INT_ERR3 DMA Channel3 transfer error interrupt.
+ * @arg DMA_INT_GLB4 DMA Channel4 global interrupt.
+ * @arg DMA_INT_TXC4 DMA Channel4 transfer complete interrupt.
+ * @arg DMA_INT_HTX4 DMA Channel4 half transfer interrupt.
+ * @arg DMA_INT_ERR4 DMA Channel4 transfer error interrupt.
+ * @arg DMA_INT_GLB5 DMA Channel5 global interrupt.
+ * @arg DMA_INT_TXC5 DMA Channel5 transfer complete interrupt.
+ * @arg DMA_INT_HTX5 DMA Channel5 half transfer interrupt.
+ * @arg DMA_INT_ERR5 DMA Channel5 transfer error interrupt.
+ * @arg DMA_INT_GLB6 DMA Channel6 global interrupt.
+ * @arg DMA_INT_TXC6 DMA Channel6 transfer complete interrupt.
+ * @arg DMA_INT_HTX6 DMA Channel6 half transfer interrupt.
+ * @arg DMA_INT_ERR6 DMA Channel6 transfer error interrupt.
+ * @arg DMA_INT_GLB7 DMA Channel7 global interrupt.
+ * @arg DMA_INT_TXC7 DMA Channel7 transfer complete interrupt.
+ * @arg DMA_INT_HTX7 DMA Channel7 half transfer interrupt.
+ * @arg DMA_INT_ERR7 DMA Channel7 transfer error interrupt.
+ * @arg DMA_INT_GLB8 DMA Channel8 global interrupt.
+ * @arg DMA_INT_TXC8 DMA Channel8 transfer complete interrupt.
+ * @arg DMA_INT_HTX8 DMA Channel8 half transfer interrupt.
+ * @arg DMA_INT_ERR8 DMA Channel8 transfer error interrupt.
+ * @param DMAy DMA
+ * This parameter can be one of the following values:
+ * @arg DMA .
+ */
+void DMA_ClrIntPendingBit(uint32_t DMA_IT, DMA_Module* DMAy)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_CLR_INT(DMA_IT));
+
+ /* Calculate the used DMA */
+ /* Clear the selected DMA interrupt pending bits */
+ DMAy->INTCLR = DMA_IT;
+}
+
+/**
+ * @brief Set the DMA Channelx's remap request.
+ * @param DMA_REMAP specifies the DMA request.
+ * This parameter can be set by the following values:
+ * @arg DMA_REMAP_ADC1 DMA Request For ADC1.
+ * @arg DMA_REMAP_USART1_TX DMA Request For USART1_TX.
+ * @arg DMA_REMAP_USART1_RX DMA Request For USART1_RX.
+ * @arg DMA_REMAP_USART2_TX DMA Request For USART2_TX.
+ * @arg DMA_REMAP_USART2_RX DMA Request For USART2_RX.
+ * @arg DMA_REMAP_USART3_TX DMA Request For USART3_TX.
+ * @arg DMA_REMAP_USART3_RX DMA Request For USART3_RX.
+ * @arg DMA_REMAP_UART4_TX DMA Request For UART4_TX.
+ * @arg DMA_REMAP_UART4_RX DMA Request For UART4_RX.
+ * @arg DMA_REMAP_UART5_TX DMA Request For UART5_TX.
+ * @arg DMA_REMAP_UART5_RX DMA Request For UART5_RX.
+ * @arg DMA_REMAP_LPUART_TX DMA Request For LPUART_TX.
+ * @arg DMA_REMAP_LPUART_RX DMA Request For LPUART_RX.
+ * @arg DMA_REMAP_SPI1_TX DMA Request For SPI1_TX.
+ * @arg DMA_REMAP_SPI1_RX DMA Request For SPI1_RX.
+ * @arg DMA_REMAP_SPI2_TX DMA Request For SPI2_TX.
+ * @arg DMA_REMAP_SPI2_RX DMA Request For SPI2_RX.
+ * @arg DMA_REMAP_I2C1_TX DMA Request For I2C1_TX.
+ * @arg DMA_REMAP_I2C1_RX DMA Request For I2C1_RX.
+ * @arg DMA_REMAP_I2C2_TX DMA Request For I2C2_TX.
+ * @arg DMA_REMAP_I2C2_RX DMA Request For I2C2_RX.
+ * @arg DMA_REMAP_DAC1 DMA Request For DAC1.
+ * @arg DMA_REMAP_TIM1_CH1 DMA Request For TIM1_CH1.
+ * @arg DMA_REMAP_TIM1_CH2 DMA Request For TIM1_CH2.
+ * @arg DMA_REMAP_TIM1_CH3 DMA Request For TIM1_CH3.
+ * @arg DMA_REMAP_TIM1_CH4 DMA Request For TIM1_CH4.
+ * @arg DMA_REMAP_TIM1_COM DMA Request For TIM1_COM.
+ * @arg DMA_REMAP_TIM1_UP DMA Request For TIM1_UP.
+ * @arg DMA_REMAP_TIM1_TRIG DMA Request For TIM1_TRIG.
+ * @arg DMA_REMAP_TIM2_CH1 DMA Request For TIM2_CH1.
+ * @arg DMA_REMAP_TIM2_CH2 DMA Request For TIM2_CH2.
+ * @arg DMA_REMAP_TIM2_CH3 DMA Request For TIM2_CH3.
+ * @arg DMA_REMAP_TIM2_CH4 DMA Request For TIM3_TRIG.
+ * @arg DMA_REMAP_TIM2_UP DMA Request For TIM2_UP.
+ * @arg DMA_REMAP_TIM3_CH1 DMA Request For TIM3_CH1.
+ * @arg DMA_REMAP_TIM3_CH3 DMA Request For TIM3_CH3.
+ * @arg DMA_REMAP_TIM3_CH4 DMA Request For TIM3_CH4.
+ * @arg DMA_REMAP_TIM3_UP DMA Request For TIM3_UP.
+ * @arg DMA_REMAP_TIM3_TRIG DMA Request For TIM3_TRIG.
+ * @arg DMA_REMAP_TIM4_CH1 DMA Request For TIM4_CH1.
+ * @arg DMA_REMAP_TIM4_CH2 DMA Request For TIM4_CH2.
+ * @arg DMA_REMAP_TIM4_CH3 DMA Request For TIM4_CH3.
+ * @arg DMA_REMAP_TIM4_UP DMA Request For TIM4_UP.
+ * @arg DMA_REMAP_TIM5_CH1 DMA Request For TIM5_CH1.
+ * @arg DMA_REMAP_TIM5_CH2 DMA Request For TIM5_CH2.
+ * @arg DMA_REMAP_TIM5_CH3 DMA Request For TIM5_CH3.
+ * @arg DMA_REMAP_TIM5_CH4 DMA Request For TIM5_CH4.
+ * @arg DMA_REMAP_TIM5_UP DMA Request For TIM5_UP.
+ * @arg DMA_REMAP_TIM5_TRIG DMA Request For TIM5_TRIG.
+ * @arg DMA_REMAP_TIM6_UP DMA Request For TIM6_UP.
+ * @arg DMA_REMAP_TIM7_UP DMA Request For TIM7_UP.
+ * @arg DMA_REMAP_TIM8_CH1 DMA Request For TIM8_CH1.
+ * @arg DMA_REMAP_TIM8_CH2 DMA Request For TIM8_CH2.
+ * @arg DMA_REMAP_TIM8_CH3 DMA Request For TIM8_CH3.
+ * @arg DMA_REMAP_TIM8_CH4 DMA Request For TIM8_CH4.
+ * @arg DMA_REMAP_TIM8_COM DMA Request For TIM8_COM.
+ * @arg DMA_REMAP_TIM8_UP DMA Request For TIM8_UP.
+ * @arg DMA_REMAP_TIM8_TRIG DMA Request For TIM8_TRIG.
+ * @arg DMA_REMAP_TIM9_CH1 DMA Request For TIM9_CH1.
+ * @arg DMA_REMAP_TIM9_TRIG DMA Request For TIM9_TRIG.
+ * @arg DMA_REMAP_TIM9_CH3 DMA Request For TIM9_CH3.
+ * @arg DMA_REMAP_TIM9_CH4 DMA Request For TIM9_CH4.
+ * @arg DMA_REMAP_TIM9_UP DMA Request For TIM9_UP.
+ * @param DMAy DMA
+ * This parameter can be one of the following values:
+ * @arg DMA .
+ * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel.
+ * @param Cmd new state of the DMA Channelx.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DMA_RequestRemap(uint32_t DMA_REMAP, DMA_Module* DMAy, DMA_ChannelType* DMAChx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_REMAP(DMA_REMAP));
+
+ if (Cmd != DISABLE)
+ {
+ /* Calculate the used DMAy */
+ /* Set the selected DMAy remap request */
+ DMAChx->CHSEL = DMA_REMAP;
+ }
+ else
+ {
+ /* Clear DMAy remap */
+ DMAChx->CHSEL = 0;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_exti.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_exti.c
new file mode 100644
index 0000000000..0b79154553
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_exti.c
@@ -0,0 +1,286 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_exti.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l43x_exti.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup EXTI
+ * @brief EXTI driver modules
+ * @{
+ */
+
+/** @addtogroup EXTI_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Private_Defines
+ * @{
+ */
+
+#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the EXTI peripheral registers to their default reset values.
+ */
+void EXTI_DeInit(void)
+{
+ EXTI->IMASK = 0x00000000;
+ EXTI->EMASK = 0x00000000;
+ EXTI->RT_CFG = 0x00000000;
+ EXTI->FT_CFG = 0x00000000;
+ EXTI->PEND = 0x0FFFFFFF;
+}
+
+/**
+ * @brief Initializes the EXTI peripheral according to the specified
+ * parameters in the EXTI_InitStruct.
+ * @param EXTI_InitStruct pointer to a EXTI_InitType structure
+ * that contains the configuration information for the EXTI peripheral.
+ */
+void EXTI_InitPeripheral(EXTI_InitType* EXTI_InitStruct)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
+ assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
+ assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
+ assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
+
+ tmp = (uint32_t)EXTI_BASE;
+
+ if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
+ {
+ /* Clear EXTI line configuration */
+ EXTI->IMASK &= ~EXTI_InitStruct->EXTI_Line;
+ EXTI->EMASK &= ~EXTI_InitStruct->EXTI_Line;
+
+ tmp += EXTI_InitStruct->EXTI_Mode;
+
+ *(__IO uint32_t*)tmp |= EXTI_InitStruct->EXTI_Line;
+
+ /* Clear Rising Falling edge configuration */
+ EXTI->RT_CFG &= ~EXTI_InitStruct->EXTI_Line;
+ EXTI->FT_CFG &= ~EXTI_InitStruct->EXTI_Line;
+
+ /* Select the trigger for the selected external interrupts */
+ if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
+ {
+ /* Rising Falling edge */
+ EXTI->RT_CFG |= EXTI_InitStruct->EXTI_Line;
+ EXTI->FT_CFG |= EXTI_InitStruct->EXTI_Line;
+ }
+ else
+ {
+ tmp = (uint32_t)EXTI_BASE;
+ tmp += EXTI_InitStruct->EXTI_Trigger;
+
+ *(__IO uint32_t*)tmp |= EXTI_InitStruct->EXTI_Line;
+ }
+ }
+ else
+ {
+ tmp += EXTI_InitStruct->EXTI_Mode;
+
+ /* Disable the selected external lines */
+ *(__IO uint32_t*)tmp &= ~EXTI_InitStruct->EXTI_Line;
+ }
+}
+
+/**
+ * @brief Fills each EXTI_InitStruct member with its reset value.
+ * @param EXTI_InitStruct pointer to a EXTI_InitType structure which will
+ * be initialized.
+ */
+void EXTI_InitStruct(EXTI_InitType* EXTI_InitStruct)
+{
+ EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
+ EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
+ EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
+ EXTI_InitStruct->EXTI_LineCmd = DISABLE;
+}
+
+/**
+ * @brief Generates a Software interrupt.
+ * @param EXTI_Line specifies the EXTI lines to be enabled or disabled.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..27).
+ */
+void EXTI_TriggerSWInt(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(EXTI_Line));
+
+ EXTI->SWIE |= EXTI_Line;
+}
+
+/**
+ * @brief Checks whether the specified EXTI line flag is set or not.
+ * @param EXTI_Line specifies the EXTI line flag to check.
+ * This parameter can be:
+ * @arg EXTI_Linex External interrupt line x where x(0..27)
+ * @return The new state of EXTI_Line (SET or RESET).
+ */
+FlagStatus EXTI_GetStatusFlag(uint32_t EXTI_Line)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+ if ((EXTI->PEND & EXTI_Line) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the EXTI's line pending flags.
+ * @param EXTI_Line specifies the EXTI lines flags to clear.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..27).
+ */
+void EXTI_ClrStatusFlag(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(EXTI_Line));
+
+ EXTI->PEND = EXTI_Line;
+}
+
+/**
+ * @brief Checks whether the specified EXTI line is asserted or not.
+ * @param EXTI_Line specifies the EXTI line to check.
+ * This parameter can be:
+ * @arg EXTI_Linex External interrupt line x where x(0..27)
+ * @return The new state of EXTI_Line (SET or RESET).
+ */
+INTStatus EXTI_GetITStatus(uint32_t EXTI_Line)
+{
+ INTStatus bitstatus = RESET;
+ uint32_t enablestatus = 0;
+ /* Check the parameters */
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+ enablestatus = EXTI->IMASK & EXTI_Line;
+ if (((EXTI->PEND & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the EXTI's line pending bits.
+ * @param EXTI_Line specifies the EXTI lines to clear.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..27).
+ */
+void EXTI_ClrITPendBit(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(EXTI_Line));
+
+ EXTI->PEND = EXTI_Line;
+}
+
+/**
+ * @brief Select one of EXTI inputs to the RTC TimeStamp event.
+ * @param EXTI_TSSEL_Line specifies the EXTI lines to select.
+ * This parameter can be any combination of EXTI_TSSEL_Line where x can be (0..15).
+ */
+void EXTI_RTCTimeStampSel(uint32_t EXTI_TSSEL_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_TSSEL_LINE(EXTI_TSSEL_Line));
+
+ EXTI->TS_SEL &= EXTI_TSSEL_LINE_MASK;
+ EXTI->TS_SEL |= EXTI_TSSEL_Line;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_flash.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_flash.c
new file mode 100644
index 0000000000..1b33ad1d58
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_flash.c
@@ -0,0 +1,1565 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_flash.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l43x_flash.h"
+
+/** @addtogroup N32L43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @brief FLASH driver modules
+ * @{
+ */
+
+/** @addtogroup FLASH_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Defines
+ * @{
+ */
+
+/* Flash Access Control Register bits */
+#define AC_LATENCY_MSK ((uint32_t)0x000000F8)
+#define AC_PRFTBE_MSK ((uint32_t)0xFFFFFFEF)
+#define AC_ICAHEN_MSK ((uint32_t)0xFFFFFF7F)
+#define AC_LVMEN_MSK ((uint32_t)0xFFFFFDFF)
+#define AC_SLMEN_MSK ((uint32_t)0xFFFFF7FF)
+
+/* Flash Access Control Register bits */
+#define AC_PRFTBS_MSK ((uint32_t)0x00000020)
+#define AC_ICAHRST_MSK ((uint32_t)0x00000040)
+#define AC_LVMF_MSK ((uint32_t)0x00000100)
+#define AC_SLMF_MSK ((uint32_t)0x00000400)
+
+/* Flash Control Register bits */
+#define CTRL_Set_PG ((uint32_t)0x00000001)
+#define CTRL_Reset_PG ((uint32_t)0x00003FFE)
+#define CTRL_Set_PER ((uint32_t)0x00000002)
+#define CTRL_Reset_PER ((uint32_t)0x00003FFD)
+#define CTRL_Set_MER ((uint32_t)0x00000004)
+#define CTRL_Reset_MER ((uint32_t)0x00003FFB)
+#define CTRL_Set_OPTPG ((uint32_t)0x00000010)
+#define CTRL_Reset_OPTPG ((uint32_t)0x00003FEF)
+#define CTRL_Set_OPTER ((uint32_t)0x00000020)
+#define CTRL_Reset_OPTER ((uint32_t)0x00003FDF)
+#define CTRL_Set_START ((uint32_t)0x00000040)
+#define CTRL_Set_LOCK ((uint32_t)0x00000080)
+#define CTRL_Reset_SMPSEL ((uint32_t)0x00003EFF)
+#define CTRL_SMPSEL_SMP1 ((uint32_t)0x00000000)
+#define CTRL_SMPSEL_SMP2 ((uint32_t)0x00000100)
+
+/* FLASH Mask */
+#define RDPRTL1_MSK ((uint32_t)0x00000002)
+#define RDPRTL2_MSK ((uint32_t)0x80000000)
+#define OBR_USER_MSK ((uint32_t)0x0000001C)
+#define WRP0_MSK ((uint32_t)0x000000FF)
+#define WRP1_MSK ((uint32_t)0x0000FF00)
+#define WRP2_MSK ((uint32_t)0x00FF0000)
+#define WRP3_MSK ((uint32_t)0xFF000000)
+
+/* FLASH Keys */
+#define L1_RDP_Key ((uint32_t)0xFFFF00A5)
+#define RDP_USER_Key ((uint32_t)0xFFF000A5)
+#define L2_RDP_Key ((uint32_t)0xFFFF33CC)
+#define FLASH_KEY1 ((uint32_t)0x45670123)
+#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
+
+/* Delay definition */
+#define EraseTimeout ((uint32_t)0x000B0000)
+#define ProgramTimeout ((uint32_t)0x00002000)
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Sets the code latency value.
+ * @note This function can be used for N32L43x devices.
+ * @param FLASH_Latency specifies the FLASH Latency value.
+ * This parameter can be one of the following values:
+ * @arg FLASH_LATENCY_0 FLASH Zero Latency cycle
+ * @arg FLASH_LATENCY_1 FLASH One Latency cycle
+ * @arg FLASH_LATENCY_2 FLASH Two Latency cycles
+ * @arg FLASH_LATENCY_3 FLASH Three Latency cycles
+ */
+void FLASH_SetLatency(uint32_t FLASH_Latency)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_LATENCY(FLASH_Latency));
+
+ /* Read the ACR register */
+ tmpregister = FLASH->AC;
+
+ /* Sets the Latency value */
+ tmpregister &= AC_LATENCY_MSK;
+ tmpregister |= FLASH_Latency;
+
+ /* Write the ACR register */
+ FLASH->AC = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the Prefetch Buffer.
+ * @note This function can be used for N32L43x devices.
+ * @param FLASH_PrefetchBuf specifies the Prefetch buffer status.
+ * This parameter can be one of the following values:
+ * @arg FLASH_PrefetchBuf_EN FLASH Prefetch Buffer Enable
+ * @arg FLASH_PrefetchBuf_DIS FLASH Prefetch Buffer Disable
+ */
+void FLASH_PrefetchBufSet(uint32_t FLASH_PrefetchBuf)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_PREFETCHBUF_STATE(FLASH_PrefetchBuf));
+
+ /* Enable or disable the Prefetch Buffer */
+ FLASH->AC &= AC_PRFTBE_MSK;
+ FLASH->AC |= FLASH_PrefetchBuf;
+}
+
+/**
+ * @brief ICache Reset.
+ * @note This function can be used for N32L43x devices.
+ */
+void FLASH_iCacheRST(void)
+{
+ /* ICache Reset */
+ FLASH->AC |= FLASH_AC_ICAHRST;
+}
+
+/**
+ * @brief Enables or disables the iCache.
+ * @note This function can be used for N32L43x devices.
+ * @param FLASH_iCache specifies the iCache status.
+ * This parameter can be one of the following values:
+ * @arg FLASH_iCache_EN FLASH iCache Enable
+ * @arg FLASH_iCache_DIS FLASH iCache Disable
+ */
+void FLASH_iCacheCmd(uint32_t FLASH_iCache)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_ICACHE_STATE(FLASH_iCache));
+
+ /* Enable or disable the iCache */
+ FLASH->AC &= AC_ICAHEN_MSK;
+ FLASH->AC |= FLASH_iCache;
+}
+
+/**
+ * @brief Enables or disables the Low Voltage Mode.
+ * @note This function can be used for N32L43x devices.
+ * @param FLASH_LVM specifies the Low Voltage Mode status.
+ * This parameter can be one of the following values:
+ * @arg FLASH_LVM_EN FLASH Low Voltage Mode Enable
+ * @arg FLASH_LVM_DIS FLASH Low Voltage Mode Disable
+ */
+void FLASH_LowVoltageModeCmd(uint32_t FLASH_LVM)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_LVM(FLASH_LVM));
+
+ /* Enable or disable LVM */
+ FLASH->AC &= AC_LVMEN_MSK;
+ FLASH->AC |= FLASH_LVM;
+}
+
+/**
+ * @brief Checks whether the Low Voltage Mode status is SET or RESET.
+ * @note This function can be used for N32L43x devices.
+ * @return Low Voltage Mode Status (SET or RESET).
+ */
+FlagStatus FLASH_GetLowVoltageModeSTS(void)
+{
+ FlagStatus bitstatus = RESET;
+
+ if ((FLASH->AC & AC_LVMF_MSK) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the new state of FLASH Low Voltage Mode Status (SET or RESET) */
+ return bitstatus;
+}
+
+/**
+ * @brief Enables or disables the FLASH Sleep Mode.
+ * @note This function can be used for N32L43x devices.
+ * @param FLASH_SLM specifies the FLASH Sleep Mode status.
+ * This parameter can be one of the following values:
+ * @arg FLASH_SLM_EN FLASH iCache Enable
+ * @arg FLASH_SLM_DIS FLASH iCache Disable
+ */
+void FLASH_FLASHSleepModeCmd(uint32_t FLASH_SLM)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_SLM(FLASH_SLM));
+
+ /* Enable or disable SLM */
+ FLASH->AC &= AC_SLMEN_MSK;
+ FLASH->AC |= FLASH_SLM;
+}
+
+/**
+ * @brief Checks whether the FLASH Sleep Mode status is SET or RESET.
+ * @note This function can be used for N32L43x devices.
+ * @return FLASH Sleep Mode Status (SET or RESET).
+ */
+FlagStatus FLASH_GetFLASHSleepModeSTS(void)
+{
+ FlagStatus bitstatus = RESET;
+
+ if ((FLASH->AC & AC_SLMF_MSK) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the new state of FLASH Sleep Mode Status (SET or RESET) */
+ return bitstatus;
+}
+
+/**
+ * @brief Checks whether the FLASH SMPSEL is SMP1 or SMP2.
+ * @note This function can be used for N32L43x devices.
+ * @param FLASH_smpsel FLASH_SMPSEL_SMP1 or FLASH_SMPSEL_SMP2
+ */
+void FLASH_SetSMPSELStatus(uint32_t FLASH_smpsel)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_SMPSEL_STATE(FLASH_smpsel));
+
+ /* SMP1 or SMP2 */
+ FLASH->CTRL &= CTRL_Reset_SMPSEL;
+ FLASH->CTRL |= FLASH_smpsel;
+}
+
+/**
+ * @brief Configures the Internal High Speed oscillator
+ * to program/erase FLASH.
+ * @note This function can be used for N32L43x devices.
+ * - For N32L43x devices this function enable HSI.
+ * @return FLASH_HSICLOCK (FLASH_HSICLOCK_ENABLE or FLASH_HSICLOCK_DISABLE).
+ */
+FLASH_HSICLOCK FLASH_ClockInit(void)
+{
+ bool HSIStatus = 0;
+ __IO uint32_t StartUpCounter = 0;
+ FLASH_HSICLOCK hsiclock_status = FLASH_HSICLOCK_ENABLE;
+
+ if ((RCC->CTRL & RCC_CTRL_HSIRDF) == RESET)
+ {
+ /* Enable HSI */
+ RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
+
+ /* Wait till HSI is ready and if Time out is reached exit */
+ do
+ {
+ HSIStatus = RCC->CTRL & RCC_CTRL_HSIRDF;
+ StartUpCounter++;
+ } while ((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));
+
+ HSIStatus = ((RCC->CTRL & RCC_CTRL_HSIRDF) != RESET);
+ if (!HSIStatus)
+ {
+ hsiclock_status = FLASH_HSICLOCK_DISABLE;
+ }
+ }
+ return hsiclock_status;
+}
+
+/**
+ * @brief Unlocks the FLASH Program Erase Controller.
+ * @note This function can be used for N32L43x devices.
+ * - For N32L43x devices this function unlocks Bank.
+ * to FLASH_Unlock function..
+ */
+void FLASH_Unlock(void)
+{
+ /* Unlocks the FLASH Program Erase Controller */
+ FLASH->KEYR = FLASH_KEY1;
+ FLASH->KEYR = FLASH_KEY2;
+}
+
+/**
+ * @brief Locks the FLASH Program Erase Controller.
+ * @note This function can be used for N32L43x devices.
+ * - For N32L43x devices this function Locks Bank.
+ * to FLASH_Lock function.
+ */
+void FLASH_Lock(void)
+{
+ /* Set the Lock Bit to lock the FLASH Program Erase Controller */
+ FLASH->CTRL |= CTRL_Set_LOCK;
+}
+
+/**
+ * @brief Erases a specified FLASH page.
+ * @note This function can be used for N32L43x devices.
+ * @param Page_Address The page address to be erased.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_EraseOnePage(uint32_t Page_Address)
+{
+ FLASH_STS status = FLASH_COMPL;
+ /* Check the parameters */
+ assert_param(IS_FLASH_ADDRESS(Page_Address));
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* if the previous operation is completed, proceed to erase the page */
+ FLASH->CTRL |= CTRL_Set_PER;
+ FLASH->ADD = Page_Address;
+ FLASH->CTRL |= CTRL_Set_START;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ /* Disable the PER Bit */
+ FLASH->CTRL &= CTRL_Reset_PER;
+ }
+
+ /* Return the Erase Status */
+ return status;
+}
+
+/**
+ * @brief Erases all FLASH pages.
+ * @note This function can be used for all N32L43x devices.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_MassErase(void)
+{
+ FLASH_STS status = FLASH_COMPL;
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+ if (status == FLASH_COMPL)
+ {
+ /* if the previous operation is completed, proceed to erase all pages */
+ FLASH->CTRL |= CTRL_Set_MER;
+ FLASH->CTRL |= CTRL_Set_START;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ /* Disable the MER Bit */
+ FLASH->CTRL &= CTRL_Reset_MER;
+ }
+
+ /* Return the Erase Status */
+ return status;
+}
+
+/**
+ * @brief Erases the FLASH option bytes.
+ * @note This functions erases all option bytes except the Read protection (RDP).
+ * @note This function can be used for N32L43x devices.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_EraseOB(void)
+{
+ uint32_t rdptmp = L1_RDP_Key;
+
+ FLASH_STS status = FLASH_COMPL;
+
+ /* Get the actual read protection L2 Option Byte value */
+ if (FLASH_GetReadOutProtectionL2STS() != RESET)
+ {
+ status = FLASH_ERR_RDP2;
+ return status;
+ }
+
+ /* Get the actual read protection Option Byte value */
+ if (FLASH_GetReadOutProtectionSTS() != RESET)
+ {
+ rdptmp = FLASH_USER_USER;
+ }
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Authorize the small information block programming */
+ FLASH->OPTKEY = FLASH_KEY1;
+ FLASH->OPTKEY = FLASH_KEY2;
+
+ /* if the previous operation is completed, proceed to erase the option bytes */
+ FLASH->CTRL |= CTRL_Set_OPTER;
+ FLASH->CTRL |= CTRL_Set_START;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* if the erase operation is completed, disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CTRL |= CTRL_Set_OPTPG;
+ /* Restore the last read protection Option Byte value */
+ OBT->USER_RDP = (uint32_t)rdptmp;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTPG;
+ }
+ }
+ else
+ {
+ if (status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+ }
+ }
+ }
+ /* Return the erase status */
+ return status;
+}
+
+
+/**
+ * @brief Programs the FLASH User Option Byte:
+ * RDP1 / IWDG_SW / RST_STOP2 / RST_STDBY / RST_PD / OB_Data0 / OB_Data1
+ * WRP_Pages / RDP2 / nBOOT0 / nBOOT1 / nSWBOOT0 / BOR_LEV[2:0].
+ * @note This function can be used for N32L43x devices.
+ * @param OB_RDP1
+ * This parameter can be one of the following values:
+ * @arg OB_RDP1_ENABLE
+ * @arg OB_RDP1_DISABLE
+ * @param OB_IWDG Selects the IWDG mode
+ * This parameter can be one of the following values:
+ * @arg OB_IWDG_SW Software IWDG selected
+ * @arg OB_IWDG_HW Hardware IWDG selected
+ * @param OB_STOP2 Reset event when entering STOP2 mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STOP2_NORST No reset generated when entering in STOP2
+ * @arg OB_STOP2_RST Reset generated when entering in STOP2
+ * @param OB_STDBY Reset event when entering Standby mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STDBY_NORST No reset generated when entering in STANDBY
+ * @arg OB_STDBY_RST Reset generated when entering in STANDBY
+ * @param OB_PD Reset event when entering PowerDown mode.
+ * This parameter can be one of the following values:
+ * @arg OB_PD_NORST No reset generated when entering in PowerDown
+ * @arg OB_PD_RST Reset generated when entering in PowerDown
+ * @param OB_Data0
+ * This parameter can be one of the following values:
+ * @arg 0x00 ~ 0xFF
+ * @param OB_Data1
+ * This parameter can be one of the following values:
+ * @arg 0x00 ~ 0xFF
+ * @param WRP_Pages specifies the address of the pages to be write protected.
+ * This parameter can be:
+ * @arg For @b N32L43x_devices: value between FLASH_WRP_Pages0to1 and
+ * FLASH_WRP_Pages62to63 or FLASH_WRP_AllPages or (~FLASH_WRP_AllPages)
+ * @param OB_RDP2
+ * This parameter can be one of the following values:
+ * @arg OB_RDP2_ENABLE
+ * @arg OB_RDP2_DISABLE
+ * @param OB2_nBOOT0
+ * This parameter can be one of the following values:
+ * @arg OB2_NBOOT0_SET Set nBOOT0
+ * @arg OB2_NBOOT0_CLR Clear nBOOT0
+ * @param OB2_nBOOT1
+ * This parameter can be one of the following values:
+ * @arg OB2_NBOOT1_SET Set nBOOT1
+ * @arg OB2_NBOOT1_CLR Clear nBOOT1
+ * @param OB2_nSWBOOT0
+ * This parameter can be one of the following values:
+ * @arg OB2_NSWBOOT0_SET Set nSWBOOT0
+ * @arg OB2_NSWBOOT0_CLR Clear nSWBOOT0
+* @param OB2_BOR_LEV[2:0]
+ * This parameter can be one of the following values:
+ * @arg OB2_BOR_LEV0
+ * @arg OB2_BOR_LEV1
+ * @arg OB2_BOR_LEV2
+ * @arg OB2_BOR_LEV3
+ * @arg OB2_BOR_LEV4
+ * @arg OB2_BOR_LEV5
+ * @arg OB2_BOR_LEV6
+ * @arg OB2_BOR_LEV7
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ConfigALLOptionByte(uint8_t OB_RDP1, uint8_t OB_IWDG, uint8_t OB_STOP2,
+ uint8_t OB_STDBY, uint8_t OB_PD, uint8_t OB_Data0,
+ uint8_t OB_Data1, uint32_t WRP_Pages, uint8_t OB_RDP2,
+ uint8_t OB2_nBOOT0, uint8_t OB2_nBOOT1, uint8_t OB2_nSWBOOT0,
+ uint8_t OB2_BOR_LEV)
+{
+ uint32_t rdpuser_tmp, data0data1_tmp, wrp0wrp1_tmp, wrp2wrp3_tmp, rdp2user2_tmp;
+
+ FLASH_STS status = FLASH_COMPL;
+
+ /* Check the parameters */
+ assert_param(IS_OB_RDP1_SOURCE(OB_RDP1));
+ assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
+ assert_param(IS_OB_STOP2_SOURCE(OB_STOP2));
+ assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
+ assert_param(IS_OB_PD_SOURCE(OB_PD));
+ assert_param(IS_FLASH_WRP_PAGE(WRP_Pages));
+ assert_param(IS_OB_RDP2_SOURCE(OB_RDP2));
+ assert_param(IS_OB2_NBOOT0_SOURCE(OB2_nBOOT0));
+ assert_param(IS_OB2_NBOOT1_SOURCE(OB2_nBOOT1));
+ assert_param(IS_OB2_NSWBOOT0_SOURCE(OB2_nSWBOOT0));
+ assert_param(IS_OB2_BOR_LEV_SOURCE(OB2_BOR_LEV));
+
+ /* Get the actual read protection L2 Option Byte value */
+ if (FLASH_GetReadOutProtectionL2STS() != RESET)
+ {
+ status = FLASH_ERR_RDP2;
+ return status;
+ }
+
+ WRP_Pages = (uint32_t)(~WRP_Pages);
+ rdpuser_tmp = (((uint32_t)OB_RDP1) | (((uint32_t)(OB_IWDG | OB_STOP2 | OB_STDBY | OB_PD)) << 16));
+ data0data1_tmp = (((uint32_t)OB_Data0) | (((uint32_t)OB_Data0) << 16));
+ wrp0wrp1_tmp = ((WRP_Pages & FLASH_WRP0_WRP0) | ((WRP_Pages << 8) & FLASH_WRP1_WRP1));
+ wrp2wrp3_tmp = (((WRP_Pages >> 16) & FLASH_WRP2_WRP2) | ((WRP_Pages >> 8) & FLASH_WRP3_WRP3));
+ rdp2user2_tmp = (((uint32_t)OB_RDP2) | (((uint32_t)(OB2_nBOOT0 | OB2_nBOOT1 | OB2_nSWBOOT0 | OB2_BOR_LEV)) << 16));
+
+ /* Authorize the small information block programming */
+ FLASH->OPTKEY = FLASH_KEY1;
+ FLASH->OPTKEY = FLASH_KEY2;
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+ if (status == FLASH_COMPL)
+ {
+ /* if the previous operation is completed, proceed to erase the option bytes */
+ FLASH->CTRL |= CTRL_Set_OPTER;
+ FLASH->CTRL |= CTRL_Set_START;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* if the erase operation is completed, disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CTRL |= CTRL_Set_OPTPG;
+
+ /* Program USER_RDP Option Byte value */
+ OBT->USER_RDP = (uint32_t)rdpuser_tmp;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* Program Data1_Data0 Option Byte value */
+ OBT->Data1_Data0 = (uint32_t)data0data1_tmp;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* Program WRP1_WRP0 Option Byte value */
+ OBT->WRP1_WRP0 = (uint32_t)wrp0wrp1_tmp;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* Program WRP3_WRP2 Option Byte value */
+ OBT->WRP3_WRP2 = (uint32_t)wrp2wrp3_tmp;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* Program USER2_RDP2 Option Byte value */
+ OBT->USER2_RDP2 = (uint32_t)rdp2user2_tmp;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+ }
+ }
+ }
+ }
+
+ if (status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTPG;
+ }
+ }
+ else
+ {
+ if (status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+ }
+ }
+ }
+
+ /* Return the Option Byte program Status */
+ return status;
+}
+
+/**
+ * @brief Programs a word at a specified address.
+ * @note This function can be used for N32L43x devices.
+ * @param Address specifies the address to be programmed.
+ * @param Data specifies the data to be programmed.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_ADD or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ProgramWord(uint32_t Address, uint32_t Data)
+{
+ FLASH_STS status = FLASH_COMPL;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_ADDRESS(Address));
+
+ if ((Address & (uint32_t)0x3) != 0)
+ {
+ /* The programming address is not a multiple of 4 */
+ status = FLASH_ERR_ADD;
+ return status;
+ }
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* if the previous operation is completed, proceed to program the new word */
+ FLASH->CTRL |= CTRL_Set_PG;
+
+ *(__IO uint32_t*)Address = (uint32_t)Data;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ /* Disable the PG Bit */
+ FLASH->CTRL &= CTRL_Reset_PG;
+ }
+
+ /* Return the Program Status */
+ return status;
+}
+
+/**
+ * @brief Programs a half word at a specified Option Byte Data address.
+ * @note This function can be used for N32L43x devices.
+ * @param Address specifies the address to be programmed.
+ * This parameter can be 0x1FFFF804.
+ * @param Data specifies the data to be programmed(Data0 and Data1).
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ProgramOBData(uint32_t Address, uint32_t Data)
+{
+ FLASH_STS status = FLASH_COMPL;
+ /* Check the parameters */
+ assert_param(IS_OB_DATA_ADDRESS(Address));
+
+ /* Get the actual read protection L2 Option Byte value */
+ if (FLASH_GetReadOutProtectionL2STS() != RESET)
+ {
+ status = FLASH_ERR_RDP2;
+ return status;
+ }
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Authorize the small information block programming */
+ FLASH->OPTKEY = FLASH_KEY1;
+ FLASH->OPTKEY = FLASH_KEY2;
+ /* Enables the Option Bytes Programming operation */
+ FLASH->CTRL |= CTRL_Set_OPTPG;
+ *(__IO uint32_t*)Address = (uint32_t)Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+ if (status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTPG;
+ }
+ }
+ /* Return the Option Byte Data Program Status */
+ return status;
+}
+
+/**
+ * @brief Write protects the desired pages
+ * @note This function can be used for N32L43x devices.
+ * @param FLASH_Pages specifies the address of the pages to be write protected.
+ * This parameter can be:
+ * @arg For @b N32L43x_devices: value between FLASH_WRP_Pages0to1 and
+ * FLASH_WRP_Pages60to61 or FLASH_WRP_Pages62to63
+ * @arg FLASH_WRP_AllPages
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_EnWriteProtection(uint32_t FLASH_Pages)
+{
+ uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
+
+ FLASH_STS status = FLASH_COMPL;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_WRP_PAGE(FLASH_Pages));
+
+ /* Get the actual read protection L2 Option Byte value */
+ if (FLASH_GetReadOutProtectionL2STS() != RESET)
+ {
+ status = FLASH_ERR_RDP2;
+ return status;
+ }
+
+ FLASH_Pages = (uint32_t)(~FLASH_Pages);
+ WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_MSK);
+ WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_MSK) >> 8);
+ WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_MSK) >> 16);
+ WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_MSK) >> 24);
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Authorizes the small information block programming */
+ FLASH->OPTKEY = FLASH_KEY1;
+ FLASH->OPTKEY = FLASH_KEY2;
+ FLASH->CTRL |= CTRL_Set_OPTPG;
+
+ if ((WRP0_Data != 0xFF) || (WRP1_Data != 0xFF))
+ {
+ OBT->WRP1_WRP0 = (((uint32_t)WRP0_Data) | (((uint32_t)WRP1_Data) << 16));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+ }
+
+ if (((WRP2_Data != 0xFF) || (WRP3_Data != 0xFF)) && (status == FLASH_COMPL))
+ {
+ OBT->WRP3_WRP2 = (((uint32_t)WRP2_Data) | (((uint32_t)WRP3_Data) << 16));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+ }
+
+ if (status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTPG;
+ }
+ }
+ /* Return the write protection operation Status */
+ return status;
+}
+
+/**
+ * @brief Enables or disables the read out protection.
+ * @note If the user has already programmed the other option bytes before calling
+ * this function, he must re-program them since this function erases all option bytes.
+ * @note This function can be used for N32L43x devices.
+ * @param Cmd new state of the ReadOut Protection.
+ * This parameter can be: ENABLE or DISABLE.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ReadOutProtectionL1(FunctionalState Cmd)
+{
+ uint32_t usertmp;
+ FLASH_STS status = FLASH_COMPL;
+
+ usertmp = ((OBR_USER_MSK & FLASH->OB) << 0x0E);
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ /* Get the actual read protection L2 Option Byte value */
+ if (FLASH_GetReadOutProtectionL2STS() != RESET)
+ {
+ status = FLASH_ERR_RDP2;
+ return status;
+ }
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Authorizes the small information block programming */
+ FLASH->OPTKEY = FLASH_KEY1;
+ FLASH->OPTKEY = FLASH_KEY2;
+ FLASH->CTRL |= CTRL_Set_OPTER;
+ FLASH->CTRL |= CTRL_Set_START;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* if the erase operation is completed, disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CTRL |= CTRL_Set_OPTPG;
+ if (Cmd != DISABLE)
+ {
+ OBT->USER_RDP = (FLASH_USER_USER & usertmp);
+ }
+ else
+ {
+ OBT->USER_RDP = ((L1_RDP_Key & FLASH_RDP_RDP1) | usertmp);
+ }
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTPG;
+ }
+ }
+ else
+ {
+ if (status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+ }
+ }
+ }
+ /* Return the protection operation Status */
+ return status;
+}
+
+/**
+ * @brief Enables or disables the read out protection L2.
+ * @note If the user has already programmed the other option bytes before calling
+ * this function, he must re-program them since this function erases all option bytes.
+ * @note This function can be used for N32L43x devices.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ReadOutProtectionL2_ENABLE(void)
+{
+ uint32_t usertmp;
+ FLASH_STS status = FLASH_COMPL;
+
+ usertmp = ((OBR_USER_MSK & FLASH->OB) << 0x0E);
+
+ /* Get the actual read protection L1 Option Byte value */
+ if (FLASH_GetReadOutProtectionSTS() == RESET)
+ {
+ usertmp |= (L1_RDP_Key & FLASH_RDP_RDP1);
+ }
+ /* Get the actual read protection L2 Option Byte value */
+ if (FLASH_GetReadOutProtectionL2STS() != RESET)
+ {
+ status = FLASH_ERR_RDP2;
+ return status;
+ }
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Authorizes the small information block programming */
+ FLASH->OPTKEY = FLASH_KEY1;
+ FLASH->OPTKEY = FLASH_KEY2;
+ FLASH->CTRL |= CTRL_Set_OPTER;
+ FLASH->CTRL |= CTRL_Set_START;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* if the erase operation is completed, disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CTRL |= CTRL_Set_OPTPG;
+
+ OBT->USER_RDP = usertmp;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* Enables the read out protection L2 */
+ OBT->USER2_RDP2 = L2_RDP_Key;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+ }
+
+ if (status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTPG;
+ }
+ }
+ else
+ {
+ if (status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+ }
+ }
+ }
+ /* Return the protection operation Status */
+ return status;
+}
+
+/**
+ * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
+ * @note This function can be used for N32L43x devices.
+ * @param OB_IWDG Selects the IWDG mode
+ * This parameter can be one of the following values:
+ * @arg OB_IWDG_SW Software IWDG selected
+ * @arg OB_IWDG_HW Hardware IWDG selected
+ * @param OB_STOP2 Reset event when entering STOP2 mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STOP2_NORST No reset generated when entering in STOP2
+ * @arg OB_STOP2_RST Reset generated when entering in STOP2
+ * @param OB_STDBY Reset event when entering Standby mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STDBY_NORST No reset generated when entering in STANDBY
+ * @arg OB_STDBY_RST Reset generated when entering in STANDBY
+ * @param OB_PD Reset event when entering PowerDown mode.
+ * This parameter can be one of the following values:
+ * @arg OB_PD_NORST No reset generated when entering in PowerDown
+ * @arg OB_PD_RST Reset generated when entering in PowerDown
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ConfigUserOB(uint8_t OB_IWDG, uint8_t OB_STOP2, uint8_t OB_STDBY, uint8_t OB_PD)
+{
+ uint32_t rdpuser_tmp = RDP_USER_Key;
+
+ FLASH_STS status = FLASH_COMPL;
+
+ /* Check the parameters */
+ assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
+ assert_param(IS_OB_STOP2_SOURCE(OB_STOP2));
+ assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
+ assert_param(IS_OB_PD_SOURCE(OB_PD));
+
+ /* Get the actual read protection L2 Option Byte value */
+ if (FLASH_GetReadOutProtectionL2STS() != RESET)
+ {
+ status = FLASH_ERR_RDP2;
+ return status;
+ }
+
+ /* Get the actual read protection Option Byte value */
+ if (FLASH_GetReadOutProtectionSTS() != RESET)
+ {
+ rdpuser_tmp = 0xFFF00000;
+ }
+
+ /* Authorize the small information block programming */
+ FLASH->OPTKEY = FLASH_KEY1;
+ FLASH->OPTKEY = FLASH_KEY2;
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* if the previous operation is completed, proceed to erase the option bytes */
+ FLASH->CTRL |= CTRL_Set_OPTER;
+ FLASH->CTRL |= CTRL_Set_START;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* if the erase operation is completed, disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CTRL |= CTRL_Set_OPTPG;
+ /* Restore the last read protection Option Byte value */
+ OBT->USER_RDP =
+ (uint32_t)rdpuser_tmp
+ | (((uint32_t)(OB_IWDG | OB_STOP2 | OB_STDBY | OB_PD)) << 16);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTPG;
+ }
+ }
+ else
+ {
+ if (status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+ }
+ }
+ }
+
+ /* Return the Option Byte program Status */
+ return status;
+}
+
+/**
+ * @brief Programs the FLASH User Option Byte: nBOOT0 / nBOOT1 / nSWBOOT0 / BOR_LEV[2:0].
+ * @note This function can be used for N32L43x devices.
+ * @param OB2_nBOOT0
+ * This parameter can be one of the following values:
+ * @arg OB2_NBOOT0_SET Set nBOOT0
+ * @arg OB2_NBOOT0_CLR Clear nBOOT0
+ * @param OB2_nBOOT1
+ * This parameter can be one of the following values:
+ * @arg OB2_NBOOT1_SET Set nBOOT1
+ * @arg OB2_NBOOT1_CLR Clear nBOOT1
+ * @param OB2_nSWBOOT0
+ * This parameter can be one of the following values:
+ * @arg OB2_NSWBOOT0_SET Set nSWBOOT0
+ * @arg OB2_NSWBOOT0_CLR Clear nSWBOOT0
+* @param OB2_BOR_LEV[2:0]
+ * This parameter can be one of the following values:
+ * @arg OB2_BOR_LEV0
+ * @arg OB2_BOR_LEV1
+ * @arg OB2_BOR_LEV2
+ * @arg OB2_BOR_LEV3
+ * @arg OB2_BOR_LEV4
+ * @arg OB2_BOR_LEV5
+ * @arg OB2_BOR_LEV6
+ * @arg OB2_BOR_LEV7
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ConfigUserOB2(uint8_t OB2_nBOOT0, uint8_t OB2_nBOOT1,
+ uint8_t OB2_nSWBOOT0, uint8_t OB2_BOR_LEV)
+{
+ uint32_t rdpuser_tmp = (RDP_USER_Key | FLASH_USER_USER);
+ uint32_t rdp2user2_tmp = 0xFF00FFFF;
+
+ FLASH_STS status = FLASH_COMPL;
+
+ /* Check the parameters */
+ assert_param(IS_OB2_NBOOT0_SOURCE(OB2_nBOOT0));
+ assert_param(IS_OB2_NBOOT1_SOURCE(OB2_nBOOT1));
+ assert_param(IS_OB2_NSWBOOT0_SOURCE(OB2_nSWBOOT0));
+ assert_param(IS_OB2_BOR_LEV_SOURCE(OB2_BOR_LEV));
+
+ /* Get the actual read protection L2 Option Byte value */
+ if (FLASH_GetReadOutProtectionL2STS() != RESET)
+ {
+ status = FLASH_ERR_RDP2;
+ return status;
+ }
+
+ /* Get the actual read protection Option Byte value */
+ if (FLASH_GetReadOutProtectionSTS() != RESET)
+ {
+ rdpuser_tmp = 0xFFFF0000;
+ }
+
+ /* Authorize the small information block programming */
+ FLASH->OPTKEY = FLASH_KEY1;
+ FLASH->OPTKEY = FLASH_KEY2;
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* if the previous operation is completed, proceed to erase the option bytes */
+ FLASH->CTRL |= CTRL_Set_OPTER;
+ FLASH->CTRL |= CTRL_Set_START;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* if the erase operation is completed, disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CTRL |= CTRL_Set_OPTPG;
+
+ /* Restore the last RDP1 Option Byte value */
+ OBT->USER_RDP = (uint32_t)rdpuser_tmp;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* Restore the last RDP2 Option Byte value */
+ OBT->USER2_RDP2 = (uint32_t)rdp2user2_tmp | (((uint32_t)(OB2_nBOOT0) | (uint32_t)(OB2_nBOOT1) \
+ | (uint32_t)(OB2_nSWBOOT0) | (uint32_t)(OB2_BOR_LEV)) << 16);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+ }
+
+ if (status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTPG;
+ }
+ }
+ else
+ {
+ if (status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+ }
+ }
+ }
+
+ /* Return the Option Byte program Status */
+ return status;
+}
+
+/**
+ * @brief Returns the FLASH User Option Bytes values.
+ * @note This function can be used for N32L43x devices.
+ * @return The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
+ * and RST_STDBY(Bit2).
+ */
+uint32_t FLASH_GetUserOB(void)
+{
+ /* Return the User Option Byte */
+ return (uint32_t)(FLASH->OB >> 2);
+}
+
+/**
+ * @brief Returns the FLASH Write Protection Option Bytes Register value.
+ * @note This function can be used for N32L43x devices.
+ * @return The FLASH Write Protection Option Bytes Register value
+ */
+uint32_t FLASH_GetWriteProtectionOB(void)
+{
+ /* Return the Flash write protection Register value */
+ return (uint32_t)(FLASH->WRP);
+}
+
+/**
+ * @brief Checks whether the FLASH Read Out Protection Status is set or not.
+ * @note This function can be used for N32L43x devices.
+ * @return FLASH ReadOut Protection Status(SET or RESET)
+ */
+FlagStatus FLASH_GetReadOutProtectionSTS(void)
+{
+ FlagStatus readoutstatus = RESET;
+ if ((FLASH->OB & RDPRTL1_MSK) != (uint32_t)RESET)
+ {
+ readoutstatus = SET;
+ }
+ else
+ {
+ readoutstatus = RESET;
+ }
+ return readoutstatus;
+}
+
+/**
+ * @brief Checks whether the FLASH Read Out Protection L2 Status is set or not.
+ * @note This function can be used for N32L43x devices.
+ * @return FLASH ReadOut Protection L2 Status(SET or RESET)
+ */
+FlagStatus FLASH_GetReadOutProtectionL2STS(void)
+{
+ FlagStatus readoutstatus = RESET;
+ if ((FLASH->OB & RDPRTL2_MSK) != (uint32_t)RESET)
+ {
+ readoutstatus = SET;
+ }
+ else
+ {
+ readoutstatus = RESET;
+ }
+ return readoutstatus;
+}
+
+/**
+ * @brief Checks whether the FLASH Prefetch Buffer status is set or not.
+ * @note This function can be used for N32L43x devices.
+ * @return FLASH Prefetch Buffer Status (SET or RESET).
+ */
+FlagStatus FLASH_GetPrefetchBufSTS(void)
+{
+ FlagStatus bitstatus = RESET;
+
+ if ((FLASH->AC & AC_PRFTBS_MSK) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */
+ return bitstatus;
+}
+
+/**
+ * @brief Checks whether the FLASH SMPSEL is SMP1 or SMP2.
+ * @note This function can be used for N32L43x devices.
+ * @return FLASH SMPSEL (FLASH_SMP1 or FLASH_SMP2).
+ */
+FLASH_SMPSEL FLASH_GetSMPSELStatus(void)
+{
+ FLASH_SMPSEL bitstatus = FLASH_SMP1;
+
+ if ((FLASH->CTRL & CTRL_Reset_SMPSEL) != (uint32_t)FLASH_SMP1)
+ {
+ bitstatus = FLASH_SMP2;
+ }
+ else
+ {
+ bitstatus = FLASH_SMP1;
+ }
+ /* Return the new state of FLASH SMPSEL (FLASH_SMP1 or FLASH_SMP2) */
+ return bitstatus;
+}
+
+/**
+ * @brief Enables or disables the specified FLASH interrupts.
+ * @note This function can be used for N32L43x devices.
+ * @param FLASH_INT specifies the FLASH interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_ERROR FLASH Error Interrupt
+ * @arg FLASH_INT_FERR EVERR PVERR Interrupt
+ * @arg FLASH_INT_EOP FLASH end of operation Interrupt
+ * @param Cmd new state of the specified Flash interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void FLASH_INTConfig(uint32_t FLASH_INT, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_INT(FLASH_INT));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the interrupt sources */
+ FLASH->CTRL |= FLASH_INT;
+ }
+ else
+ {
+ /* Disable the interrupt sources */
+ FLASH->CTRL &= ~(uint32_t)FLASH_INT;
+ }
+}
+
+/**
+ * @brief Checks whether the specified FLASH flag is set or not.
+ * @note This function can be used for N32L43x devices.
+ * @param FLASH_FLAG specifies the FLASH flag to check.
+ * This parameter can be one of the following values:
+ * @arg FLASH_FLAG_BUSY FLASH Busy flag
+ * @arg FLASH_FLAG_PGERR FLASH Program error flag
+ * @arg FLASH_FLAG_PVERR FLASH Program Verify ERROR flag
+ * @arg FLASH_FLAG_WRPERR FLASH Write protected error flag
+ * @arg FLASH_FLAG_EOP FLASH End of Operation flag
+ * @arg FLASH_FLAG_EVERR FLASH Erase Verify ERROR flag
+ * @arg FLASH_FLAG_OBERR FLASH Option Byte error flag
+ * @return The new state of FLASH_FLAG (SET or RESET).
+ */
+FlagStatus FLASH_GetFlagSTS(uint32_t FLASH_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));
+ if (FLASH_FLAG == FLASH_FLAG_OBERR)
+ {
+ if ((FLASH->OB & FLASH_FLAG_OBERR) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+ else
+ {
+ if ((FLASH->STS & FLASH_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+
+ /* Return the new state of FLASH_FLAG (SET or RESET) */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the FLASH's pending flags.
+ * @note This function can be used for N32L43x devices.
+ * @param FLASH_FLAG specifies the FLASH flags to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_FLAG_PGERR FLASH Program error flag
+ * @arg FLASH_FLAG_PVERR FLASH Program Verify ERROR flag
+ * @arg FLASH_FLAG_WRPERR FLASH Write protected error flag
+ * @arg FLASH_FLAG_EOP FLASH End of Operation flag
+ * @arg FLASH_FLAG_EVERR FLASH Erase Verify ERROR flag
+ */
+void FLASH_ClearFlag(uint32_t FLASH_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));
+
+ /* Clear the flags */
+ FLASH->STS |= FLASH_FLAG;
+}
+
+/**
+ * @brief Returns the FLASH Status.
+ * @note This function can be used for N32L43x devices, it is equivalent
+ * to FLASH_GetBank1Status function.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_GetSTS(void)
+{
+ FLASH_STS flashstatus = FLASH_COMPL;
+
+ if ((FLASH->STS & FLASH_FLAG_BUSY) == FLASH_FLAG_BUSY)
+ {
+ flashstatus = FLASH_BUSY;
+ }
+ else
+ {
+ if ((FLASH->STS & FLASH_FLAG_PGERR) != 0)
+ {
+ flashstatus = FLASH_ERR_PG;
+ }
+ else
+ {
+ if ((FLASH->STS & FLASH_FLAG_PVERR) != 0)
+ {
+ flashstatus = FLASH_ERR_PV;
+ }
+ else
+ {
+ if ((FLASH->STS & FLASH_FLAG_WRPERR) != 0)
+ {
+ flashstatus = FLASH_ERR_WRP;
+ }
+ else
+ {
+ if ((FLASH->STS & FLASH_FLAG_EVERR) != 0)
+ {
+ flashstatus = FLASH_ERR_EV;
+ }
+ else
+ {
+ flashstatus = FLASH_COMPL;
+ }
+ }
+ }
+ }
+ }
+
+ /* Return the Flash Status */
+ return flashstatus;
+}
+
+/**
+ * @brief Waits for a Flash operation to complete or a TIMEOUT to occur.
+ * @note This function can be used for N32L43x devices,
+ * it is equivalent to FLASH_WaitForLastBank1Operation..
+ * @param Timeout FLASH programming Timeout
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_WaitForLastOpt(uint32_t Timeout)
+{
+ FLASH_STS status = FLASH_COMPL;
+
+ /* Check for the Flash Status */
+ status = FLASH_GetSTS();
+ /* Wait for a Flash operation to complete or a TIMEOUT to occur */
+ while ((status == FLASH_BUSY) && (Timeout != 0x00))
+ {
+ status = FLASH_GetSTS();
+ Timeout--;
+ }
+ if (Timeout == 0x00)
+ {
+ status = FLASH_TIMEOUT;
+ }
+ /* Return the operation status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_gpio.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_gpio.c
new file mode 100644
index 0000000000..684a646bfc
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_gpio.c
@@ -0,0 +1,768 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_gpio.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l43x_gpio.h"
+#include "n32l43x_rcc.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @brief GPIO driver modules
+ * @{
+ */
+
+/** @addtogroup GPIO_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Private_Defines
+ * @{
+ */
+
+/* ------------ RCC registers bit address in the alias region ----------------*/
+#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)
+
+/* --- Event control register -----*/
+
+/* Alias word address of EVOE bit */
+#define EVCR_OFFSET (AFIO_OFFSET + 0x00)
+#define EVOE_BitNumber ((uint8_t)0x07)
+#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
+
+
+#define GPIO_MODE ((uint32_t)0x00000003)
+#define EXTI_MODE ((uint32_t)0x10000000)
+#define GPIO_MODE_IT ((uint32_t)0x00010000)
+#define GPIO_MODE_EVT ((uint32_t)0x00020000)
+#define RISING_EDGE ((uint32_t)0x00100000)
+#define FALLING_EDGE ((uint32_t)0x00200000)
+#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
+#define GPIO_PULLUP_PULLDOWN ((uint32_t)0x00000300)
+#define GPIO_NUMBER ((uint32_t)16)
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the GPIOx peripheral registers to their default reset values.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ */
+void GPIO_DeInit(GPIO_Module* GPIOx)
+{
+
+ uint32_t position = 0x00U;
+ uint32_t iocurrent = 0x00U;
+ uint32_t tmp = 0x00U;
+ uint32_t GPIO_Pin = GPIO_PIN_ALL;
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin));
+
+ if (GPIOx == GPIOA)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOA, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOA, DISABLE);
+ }
+ else if (GPIOx == GPIOB)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOB, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOB, DISABLE);
+ }
+ else if (GPIOx == GPIOC)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOC, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOC, DISABLE);
+ }
+ else if (GPIOx == GPIOD)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOD, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOD, DISABLE);
+ }
+ else
+ {
+ return;
+ }
+
+ /* Configure the port pins */
+ while ((GPIO_Pin >> position) != 0)
+ {
+ /* Get the IO position */
+ iocurrent = (GPIO_Pin) & ((uint32_t)0x01 << position);
+
+ if (iocurrent)
+ {
+ /*------------------------- EXTI Mode Configuration --------------------*/
+ /* Clear the External Interrupt or Event for the current IO */
+ tmp = AFIO->EXTI_CFG[position>>2];
+ tmp &= (0x0FuL << (4u*(position & 0x03u)));
+ if (tmp == (GPIO_GET_INDEX(GPIOx)<<(4u * (position & 0x03u))))
+ {
+ /* Clear EXTI line configuration */
+ EXTI->IMASK &= ~(iocurrent);
+ EXTI->EMASK &= ~(iocurrent);
+
+ /* Clear Rising Falling edge configuration */
+ EXTI->RT_CFG &= ~(iocurrent);
+ EXTI->FT_CFG &= ~(iocurrent);
+ tmp = 0x0FuL << (4u * (position & 0x03u));
+ AFIO->EXTI_CFG[position >> 2u] &= ~tmp;
+ }
+
+
+ /*------------------------- GPIO Mode Configuration --------------------*/
+ /* Configure IO Direction in Input Floting Mode */
+ GPIOx->PMODE &= ~(GPIO_PMODE0_Msk << (position * 2U));
+
+ /* Configure the default Alternate Function in current IO */
+ if (position & 0x08)
+ GPIOx->AFH |= ((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4U));
+ else
+ GPIOx->AFL |= ((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4U));
+
+ /* Configure the default value IO Output Type */
+ GPIOx->POTYPE &= ~(GPIO_POTYPE_POT_0 << position) ;
+
+ /* Deactivate the Pull-up oand Pull-down resistor for the current IO */
+ GPIOx->PUPD &= ~(GPIO_PUPD0_Msk << (position * 2U));
+
+ }
+ position++;
+ }
+}
+
+
+/**
+ * @brief Deinitializes the Alternate Functions (remap, event control
+ * and EXTI configuration) registers to their default reset values.
+ */
+void GPIO_AFIOInitDefault(void)
+{
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_AFIO, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_AFIO, DISABLE);
+}
+
+/**
+ * @brief Initializes the GPIOx peripheral according to the specified
+ * parameters in the GPIO_InitStruct.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param GPIO_InitStruct pointer to a GPIO_InitType structure that
+ * contains the configuration information for the specified GPIO peripheral.
+ */
+
+void GPIO_InitPeripheral(GPIO_Module* GPIOx, GPIO_InitType * GPIO_InitStruct)
+{
+ uint32_t pinpos = 0x00U;
+ uint32_t tmp = 0x00U,tmpregister=0x00U;
+ uint32_t position = 0x00U;
+ uint32_t iocurrent = 0x00U;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
+ assert_param(IS_GPIO_PIN(GPIO_InitStruct->Pin));
+ assert_param(IS_GPIO_PULL(GPIO_InitStruct->GPIO_Pull));
+ assert_param(IS_GPIO_SLEW_RATE(GPIO_InitStruct->GPIO_Slew_Rate));
+
+ /*---------------------------- GPIO Mode Configuration -----------------------*/
+
+ /*---------------------------- GPIO PL_CFG Configuration ------------------------*/
+
+ while (((GPIO_InitStruct->Pin)>>position) != 0)
+ {
+ iocurrent = (GPIO_InitStruct->Pin)&(1U<GPIO_Mode == GPIO_Mode_AF_PP) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF_OD) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_Input) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_Analog))
+ {
+ /* Check if the Alternate function is compliant with the GPIO in use */
+ assert_param(IS_GPIO_AF(GPIO_InitStruct->GPIO_Alternate));
+ /* Configure Alternate function mapped with the current IO */
+ if (position & 0x08)
+ {
+ tmp = GPIOx->AFH;
+ tmp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4U));
+ tmp |= ((uint32_t)(GPIO_InitStruct->GPIO_Alternate) << ((uint32_t)(position & (uint32_t)0x07) * 4U)) ;
+ GPIOx->AFH = tmp;
+ }
+ else
+ {
+ tmp = GPIOx->AFL;
+ tmp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4U)) ;
+ tmp |= ((uint32_t)(GPIO_InitStruct->GPIO_Alternate) << ((uint32_t)(position & (uint32_t)0x07) * 4U)) ;
+ GPIOx->AFL = tmp;
+ }
+ }
+ /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+ tmpregister = GPIOx->PMODE;
+ tmp = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
+ tmpregister &= ~(((uint32_t)0x03) << pinpos);
+ tmpregister |=( tmp << pinpos);
+ GPIOx->PMODE = tmpregister;
+
+ /* Configure pull-down mode */
+ tmpregister = GPIOx->PUPD;
+ tmp = (GPIO_InitStruct->GPIO_Pull & (uint32_t)0x03);
+ tmpregister &=~(((uint32_t)0x03) << pinpos);
+ tmpregister |= (tmp <PUPD = tmpregister;
+
+
+ /* Configure driver current*/
+ if ((GPIO_InitStruct->GPIO_Mode & GPIO_MODE) && (GPIO_InitStruct->GPIO_Mode != GPIO_Mode_Analog))
+ {
+ assert_param(IS_GPIO_CURRENT(GPIO_InitStruct->GPIO_Current));
+ tmpregister = GPIOx->DS;
+ tmp = (GPIO_InitStruct->GPIO_Current &((uint32_t)0x03));
+ tmpregister &= ~(((uint32_t)0x03) << pinpos);
+ tmpregister |= (tmp<DS = tmpregister;
+ }
+ /* Configure slew rate*/
+ tmp = GPIOx->SR;
+ tmp &=((uint32_t)(~((uint16_t)0x01 << position)));
+ tmp |= (GPIO_InitStruct->GPIO_Slew_Rate &((uint32_t)0x01))<SR = tmp;
+ /*Configure Set/Reset register*/
+ if (GPIO_InitStruct->GPIO_Pull == GPIO_Pull_Down)
+ {
+ GPIOx->PBC |= (((uint32_t)0x01) << position);
+ }
+ else
+ {
+ /* Set the corresponding POD bit */
+ if (GPIO_InitStruct->GPIO_Pull == GPIO_Pull_Up)
+ {
+ GPIOx->PBSC |= (((uint32_t)0x01) << position);
+ }
+ }
+
+ /* In case of Output or Alternate function mode selection */
+ if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_Out_PP) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF_PP) ||
+ (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_Out_OD) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF_OD))
+ {
+ /* Configure the IO Output Type */
+
+ tmp= GPIOx->POTYPE;
+ tmp &= ~(((uint32_t)0x01U) << position) ;
+ tmp |= (((GPIO_InitStruct->GPIO_Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
+ GPIOx->POTYPE = tmp;
+ }
+ /*--------------------- EXTI Mode Configuration ------------------------*/
+ /* Configure the External Interrupt or event for the current IO */
+ if (GPIO_InitStruct->GPIO_Mode & EXTI_MODE)
+ {
+ /* Clear EXTI line configuration */
+ tmp = EXTI->IMASK;
+ tmp &= ~((uint32_t)0x01<GPIO_Mode & GPIO_MODE_IT)== GPIO_MODE_IT)
+ {
+ tmp |= ((uint32_t)0x01 << position);
+ }
+ EXTI->IMASK = tmp;
+
+ tmp = EXTI->EMASK;
+ tmp &= ~((uint32_t)0x01<GPIO_Mode & GPIO_MODE_EVT)== GPIO_MODE_EVT)
+ {
+ tmp |= ((uint32_t)0x01 << position);
+ }
+ EXTI->EMASK = tmp;
+
+ /* Clear Rising Falling edge configuration */
+
+ tmp = EXTI->RT_CFG;
+ tmp &= ~((uint32_t)0x01<GPIO_Mode & RISING_EDGE)== RISING_EDGE)
+ {
+ tmp |= ((uint32_t)0x01 << position);
+ }
+ EXTI->RT_CFG = tmp;
+
+ tmp = EXTI->FT_CFG;
+ tmp &= ~((uint32_t)0x01<GPIO_Mode & FALLING_EDGE)== FALLING_EDGE)
+ {
+ tmp |= ((uint32_t)0x01 << position);
+ }
+ EXTI->FT_CFG = tmp;
+ }
+ }
+ position++;
+ }
+}
+
+/**
+ * @brief Fills each GPIO_InitStruct member with its default value.
+ * @param GPIO_InitStruct pointer to a GPIO_InitType structure which will
+ * be initialized.
+ */
+void GPIO_InitStruct(GPIO_InitType* GPIO_InitStruct)
+{
+ /* Reset GPIO init structure parameters values */
+ GPIO_InitStruct->Pin = GPIO_PIN_ALL;
+ GPIO_InitStruct->GPIO_Slew_Rate = GPIO_Slew_Rate_High;
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_Input;
+ GPIO_InitStruct->GPIO_Alternate = GPIO_NO_AF;
+ GPIO_InitStruct->GPIO_Pull = GPIO_No_Pull;
+ GPIO_InitStruct->GPIO_Current = GPIO_DC_2mA;
+}
+
+/**
+ * @brief Reads the specified input port pin.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param Pin specifies the port bit to read.
+ * This parameter can be GPIO_Pin_x where x can be (0..15).
+ * @return The input port pin value.
+ */
+uint8_t GPIO_ReadInputDataBit(GPIO_Module* GPIOx, uint16_t Pin)
+{
+ uint8_t bitstatus = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(Pin));
+
+ if ((GPIOx->PID & Pin) != (uint32_t)Bit_RESET)
+ {
+ bitstatus = (uint8_t)Bit_SET;
+ }
+ else
+ {
+ bitstatus = (uint8_t)Bit_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Reads the specified GPIO input data port.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @return GPIO input data port value.
+ */
+uint16_t GPIO_ReadInputData(GPIO_Module* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ return ((uint16_t)GPIOx->PID);
+}
+
+/**
+ * @brief Reads the specified output data port bit.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param Pin specifies the port bit to read.
+ * This parameter can be GPIO_Pin_x where x can be (0..15).
+ * @return The output port pin value.
+ */
+uint8_t GPIO_ReadOutputDataBit(GPIO_Module* GPIOx, uint16_t Pin)
+{
+ uint8_t bitstatus = 0x00;
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(Pin));
+
+ if ((GPIOx->POD & Pin) != (uint32_t)Bit_RESET)
+ {
+ bitstatus = (uint8_t)Bit_SET;
+ }
+ else
+ {
+ bitstatus = (uint8_t)Bit_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Reads the specified GPIO output data port.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @return GPIO output data port value.
+ */
+uint16_t GPIO_ReadOutputData(GPIO_Module* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ return ((uint16_t)GPIOx->POD);
+}
+
+/**
+ * @brief Sets the selected data port bits.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param Pin specifies the port bits to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ */
+void GPIO_SetBits(GPIO_Module* GPIOx, uint16_t Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(Pin));
+
+ GPIOx->PBSC = Pin;
+}
+void GPIO_SetBitsHigh16(GPIO_Module* GPIOx, uint32_t Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ // assert_param(IS_GPIO_PIN(Pin));
+
+ GPIOx->PBSC = Pin;
+}
+
+/**
+ * @brief Clears the selected data port bits.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param Pin specifies the port bits to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ */
+void GPIO_ResetBits(GPIO_Module* GPIOx, uint16_t Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(Pin));
+
+ GPIOx->PBC = Pin;
+}
+
+/**
+ * @brief Sets or clears the selected data port bit.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param Pin specifies the port bit to be written.
+ * This parameter can be one of GPIO_Pin_x where x can be (0..15).
+ * @param BitCmd specifies the value to be written to the selected bit.
+ * This parameter can be one of the Bit_OperateType enum values:
+ * @arg Bit_RESET to clear the port pin
+ * @arg Bit_SET to set the port pin
+ */
+void GPIO_WriteBit(GPIO_Module* GPIOx, uint16_t Pin, Bit_OperateType BitCmd)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(Pin));
+ assert_param(IS_GPIO_BIT_OPERATE(BitCmd));
+
+ if (BitCmd != Bit_RESET)
+ {
+ GPIOx->PBSC = Pin;
+ }
+ else
+ {
+ GPIOx->PBC = Pin;
+ }
+}
+
+/**
+ * @brief Writes data to the specified GPIO data port.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param PortVal specifies the value to be written to the port output data register.
+ */
+void GPIO_Write(GPIO_Module* GPIOx, uint16_t PortVal)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ GPIOx->POD = PortVal;
+}
+
+/**
+ * @brief Locks GPIO Pins configuration registers.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param Pin specifies the port bit to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ */
+void GPIO_ConfigPinLock(GPIO_Module* GPIOx, uint16_t Pin)
+{
+ uint32_t tmp = 0x00010000;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(Pin));
+
+ tmp |= Pin;
+ /* Set LCKK bit */
+ GPIOx->PLOCK = tmp;
+ /* Reset LCKK bit */
+ GPIOx->PLOCK = Pin;
+ /* Set LCKK bit */
+ GPIOx->PLOCK = tmp;
+ /* Read LCKK bit*/
+ tmp = GPIOx->PLOCK;
+ /* Read LCKK bit*/
+ tmp = GPIOx->PLOCK;
+}
+
+
+
+/**
+ * @brief Changes the mapping of the specified pin.
+ * @param PortSource selects the GPIO port to be used.
+ * @param PinSource specifies the pin for the remaping.
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).
+ * @param AlternateFunction specifies the alternate function for the remaping.
+ */
+void GPIO_ConfigPinRemap(uint8_t PortSource, uint8_t PinSource, uint32_t AlternateFunction)
+{
+ uint32_t tmp = 0x00, tmpregister = 0x00;
+ GPIO_Module *GPIOx;
+ /* Check the parameters */
+ assert_param(IS_GPIO_REMAP_PORT_SOURCE(PortSource));
+ assert_param(IS_GPIO_PIN_SOURCE(PinSource));
+ assert_param(IS_GPIO_AF(AlternateFunction));
+ /*Get Peripheral point*/
+ GPIOx = GPIO_GET_PERIPH(PortSource);
+ /**/
+ if (PinSource & (uint8_t)0x08)
+ {
+ tmp = (uint32_t)(PinSource & (uint8_t)0x07);
+ /*Read GPIO_AFH register*/
+ tmpregister = GPIOx->AFH;
+ /*Reset corresponding bits*/
+ tmpregister &=~((uint32_t)0x0F <<(tmp*4U));
+ /*Set corresponding bits*/
+ tmpregister |= AlternateFunction << (tmp*4U);
+ /*Write to the GPIO_AFH register*/
+ GPIOx->AFH = tmpregister;
+ }
+ else
+ {
+ tmp = (uint32_t)(PinSource & (uint8_t)0x07);
+ /*Read GPIO_AFL register*/
+ tmpregister = GPIOx->AFL;
+ /*Reset corresponding bits*/
+ tmpregister &=~((uint32_t)0x0F <<(tmp*4U));
+ /*Set corresponding bits*/
+ tmpregister |= AlternateFunction << (tmp*4U);
+ /*Write to the GPIO_AFL register*/
+ GPIOx->AFL = tmpregister;
+ }
+}
+
+/**
+ * @brief Selects the GPIO pin used as Event output.
+ * @param PortSource selects the GPIO port to be used as source
+ * for Event output.
+ * This parameter can be GPIO_PortSourceGPIOx where x can be (A..D).
+ * @param PinSource specifies the pin for the Event output.
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).
+ */
+void GPIO_ConfigEventOutput(uint8_t PortSource, uint8_t PinSource)
+{
+ uint32_t tmpregister = 0x00,tmp = 0x00;
+ GPIO_Module *GPIOx;
+ /* Check the parameters */
+ assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(PortSource));
+ assert_param(IS_GPIO_PIN_SOURCE(PinSource));
+
+ /*Get Peripheral structure point*/
+ GPIOx = GPIO_GET_PERIPH(PortSource);
+ if (PinSource & (uint8_t)0x08)
+ {
+ tmp = (uint32_t)(PinSource & (uint8_t)0x07);
+ /*Read GPIO_AFH register*/
+ tmpregister = GPIOx->AFH;
+ /*Reset corresponding bits*/
+ tmpregister &=~((uint32_t)0x0F <<(tmp*4U));
+ /*Set corresponding bits*/
+ tmpregister |= GPIO_AF3_EVENTOUT;
+ /*Write to the GPIO_AFH register*/
+ GPIOx->AFH = tmpregister;
+ }
+ else
+ {
+ tmp = (uint32_t)(PinSource & (uint8_t)0x07);
+ /*Read GPIO_AFL register*/
+ tmpregister = GPIOx->AFL;
+ /*Reset corresponding bits*/
+ tmpregister &=~((uint32_t)0x0F <<(tmp*4U));
+ /*Set corresponding bits*/
+ tmpregister |= GPIO_AF3_EVENTOUT;
+ /*Write to the GPIO_AFL register*/
+ GPIOx->AFL = tmpregister;
+ }
+}
+
+/**
+ * @brief Enables or disables the Event Output.
+ * @param Cmd new state of the Event output.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void GPIO_CtrlEventOutput(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ *(__IO uint32_t*)EVCR_EVOE_BB = (uint32_t)Cmd;
+}
+
+
+/**
+ * @brief Selects the GPIO pin used as EXTI Line.
+ * @param PortSource selects the GPIO port to be used as source for EXTI lines.
+ * This parameter can be GPIO_PortSourceGPIOx where x can be (A..D).
+ * @param PinSource specifies the EXTI line to be configured.
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).
+ */
+void GPIO_ConfigEXTILine(uint8_t PortSource, uint8_t PinSource)
+{
+ uint32_t port = (uint32_t)PortSource;
+ /* Check the parameters */
+ assert_param(IS_GPIO_EXTI_PORT_SOURCE(PortSource));
+ assert_param(IS_GPIO_PIN_SOURCE(PinSource));
+
+ AFIO->EXTI_CFG[(PinSource >> 0x02)] &= ~(((uint32_t)0x03) << ((PinSource & (uint8_t)0x03)*4u));
+ AFIO->EXTI_CFG[(PinSource >> 0x02)] |= (port << ((PinSource & (uint8_t)0x03) *4u));
+}
+
+/**
+ * @brief Selects the alternate function SPIx NSS mode.
+ * @param AFIO_SPIx_NSS choose which SPI configuration.
+ * This parameter can be AFIO_SPI1_NSS and AFIO_SPI2_NSS.
+ * @param SpiNssType specifies the SPI_NSS mode to be configured.
+ * This parameter can be AFIO_SPI1_NSS_High_IMPEDANCE and AFIO_SPI1_NSS_High_LEVEL.
+ */
+void AFIO_ConfigSPINSSMode(uint32_t AFIO_SPIx_NSS,AFIO_SPI_NSSType SpiNssType)
+{
+ uint32_t tmp = 0x00;
+ /* Check the parameters */
+ assert_param(IS_AFIO_SPIX(AFIO_SPIx_NSS));
+ assert_param(IS_AFIO_SPI_NSS(SpiNssType));
+ tmp = AFIO->RMP_CFG;
+ tmp &=(~(0x01U << AFIO_SPIx_NSS));
+ tmp |=(SpiNssType << AFIO_SPIx_NSS);
+ AFIO->RMP_CFG = tmp;
+}
+
+/**
+ * @brief Configur ADC external trigger.
+ * @param ADCETRType choose whether to configure rule conversion or injection conversion .
+ * This parameter can be AFIO_ADC_ETRI and AFIO_ADC_ETRR.
+ * @param ADCTrigRemap specifies the external trigger line be configured.
+ * This parameter can be AFIO_ADC_TRIG_EXTI_x where x can be (0..15) or AFIO_ADC_TRIG_TIM8_CHy where y can be(3..4).
+ */
+void AFIO_ConfigADCExternalTrigRemap(AFIO_ADC_ETRType ADCETRType,AFIO_ADC_Trig_RemapType ADCTrigRemap)
+{
+ uint32_t tmp = 0x00;
+ /* Check the parameters */
+ assert_param(IS_AFIO_ADC_ETR(ADCETRType));
+ if (ADCETRType == AFIO_ADC_ETRI)
+ {
+ /* Check the parameters */
+ assert_param(IS_AFIO_ADC_ETRI(ADCTrigRemap));
+ tmp = AFIO->RMP_CFG;
+ /* clear AFIO_RMP_CFG register ETRI bit*/
+ tmp &= (~(0x01U << AFIO_ADC_ETRI));
+ /* if ADCETRType is AFIO_ADC_ETRI then ADCTrigRemap cannot be AFIO_ADC_TRIG_TIM8_CH3*/
+ if (ADCTrigRemap == AFIO_ADC_TRIG_TIM8_CH4)
+ {
+ /* select TIM8_CH4 line to connect*/
+ tmp |= (0x01U << AFIO_ADC_ETRI);
+ }
+ else
+ {
+ /* select which external line is connected*/
+ tmp &=(~(0x0FU<<4U));
+ tmp |= (ADCTrigRemap<<4U);
+ }
+ AFIO->RMP_CFG = tmp;
+ }
+ else
+ {
+ if (ADCETRType == AFIO_ADC_ETRR)
+ {
+ /* Check the parameters */
+ assert_param(IS_AFIO_ADC_ETRR(ADCTrigRemap));
+ tmp = AFIO->RMP_CFG;
+ /* clear AFIO_RMP_CFG register ETRR bit*/
+ tmp &= (~(0x01U << AFIO_ADC_ETRR));
+ /* if ADCETRType is AFIO_ADC_ETRR then ADCTrigRemap cannot be AFIO_ADC_TRIG_TIM8_CH4*/
+ if (ADCTrigRemap == AFIO_ADC_TRIG_TIM8_CH3)
+ {
+ /* select TIM8_CH3 line to connect*/
+ tmp |= (0x01U << AFIO_ADC_ETRR);
+ }
+ else
+ {
+ /* select which external line is connected*/
+ tmp &=(~(0x0FU<<0));
+ tmp |= ADCTrigRemap;
+ }
+ AFIO->RMP_CFG = tmp;
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_i2c.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_i2c.c
new file mode 100644
index 0000000000..a9642c191b
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_i2c.c
@@ -0,0 +1,1301 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_i2c.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l43x_i2c.h"
+#include "n32l43x_rcc.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @brief I2C driver modules
+ * @{
+ */
+
+/** @addtogroup I2C_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_Defines
+ * @{
+ */
+
+/* I2C SPE mask */
+#define CTRL1_SPEN_SET ((uint16_t)0x0001)
+#define CTRL1_SPEN_RESET ((uint16_t)0xFFFE)
+
+/* I2C START mask */
+#define CTRL1_START_SET ((uint16_t)0x0100)
+#define CTRL1_START_RESET ((uint16_t)0xFEFF)
+
+/* I2C STOP mask */
+#define CTRL1_STOP_SET ((uint16_t)0x0200)
+#define CTRL1_STOP_RESET ((uint16_t)0xFDFF)
+
+/* I2C ACK mask */
+#define CTRL1_ACK_SET ((uint16_t)0x0400)
+#define CTRL1_ACK_RESET ((uint16_t)0xFBFF)
+
+/* I2C ENGC mask */
+#define CTRL1_GCEN_SET ((uint16_t)0x0040)
+#define CTRL1_GCEN_RESET ((uint16_t)0xFFBF)
+
+/* I2C SWRST mask */
+#define CTRL1_SWRESET_SET ((uint16_t)0x8000)
+#define CTRL1_SWRESET_RESET ((uint16_t)0x7FFF)
+
+/* I2C PEC mask */
+#define CTRL1_PEC_SET ((uint16_t)0x1000)
+#define CTRL1_PEC_RESET ((uint16_t)0xEFFF)
+
+/* I2C ENPEC mask */
+#define CTRL1_PECEN_SET ((uint16_t)0x0020)
+#define CTRL1_PECEN_RESET ((uint16_t)0xFFDF)
+
+/* I2C ENARP mask */
+#define CTRL1_ARPEN_SET ((uint16_t)0x0010)
+#define CTRL1_ARPEN_RESET ((uint16_t)0xFFEF)
+
+/* I2C NOSTRETCH mask */
+#define CTRL1_NOEXTEND_SET ((uint16_t)0x0080)
+#define CTRL1_NOEXTEND_RESET ((uint16_t)0xFF7F)
+
+/* I2C registers Masks */
+#define CTRL1_CLR_MASK ((uint16_t)0xFBF5)
+
+/* I2C DMAEN mask */
+#define CTRL2_DMAEN_SET ((uint16_t)0x0800)
+#define CTRL2_DMAEN_RESET ((uint16_t)0xF7FF)
+
+/* I2C LAST mask */
+#define CTRL2_DMALAST_SET ((uint16_t)0x1000)
+#define CTRL2_DMALAST_RESET ((uint16_t)0xEFFF)
+
+/* I2C FREQ mask */
+#define CTRL2_CLKFREQ_RESET ((uint16_t)0xFFC0)
+
+/* I2C ADD0 mask */
+#define OADDR1_ADDR0_SET ((uint16_t)0x0001)
+#define OADDR1_ADDR0_RESET ((uint16_t)0xFFFE)
+
+/* I2C ENDUAL mask */
+#define OADDR2_DUALEN_SET ((uint16_t)0x0001)
+#define OADDR2_DUALEN_RESET ((uint16_t)0xFFFE)
+
+/* I2C ADD2 mask */
+#define OADDR2_ADDR2_RESET ((uint16_t)0xFF01)
+
+/* I2C F/S mask */
+#define CLKCTRL_FSMODE_SET ((uint16_t)0x8000)
+
+/* I2C CHCFG mask */
+#define CLKCTRL_CLKCTRL_SET ((uint16_t)0x0FFF)
+
+/* I2C FLAG mask */
+#define FLAG_MASK ((uint32_t)0x00FFFFFF)
+
+/* I2C Interrupt Enable mask */
+#define INTEN_MASK ((uint32_t)0x07000000)
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the I2Cx peripheral registers to their default reset values.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ */
+void I2C_DeInit(I2C_Module* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+
+ if (I2Cx == I2C1)
+ {
+ /* Enable I2C1 reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C1, ENABLE);
+ /* Release I2C1 from reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C1, DISABLE);
+ }
+ else
+ {
+ /* Enable I2C2 reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C2, ENABLE);
+ /* Release I2C2 from reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C2, DISABLE);
+ }
+}
+
+/**
+ * @brief Initializes the I2Cx peripheral according to the specified
+ * parameters in the I2C_InitStruct.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_InitStruct pointer to a I2C_InitType structure that
+ * contains the configuration information for the specified I2C peripheral.
+ */
+void I2C_Init(I2C_Module* I2Cx, I2C_InitType* I2C_InitStruct)
+{
+ uint16_t tmpregister = 0, freqrange = 0;
+ uint16_t result = 0x04;
+ uint32_t pclk1 = 8000000;
+ RCC_ClocksType rcc_clocks;
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_CLK_SPEED(I2C_InitStruct->ClkSpeed));
+ assert_param(IS_I2C_BUS_MODE(I2C_InitStruct->BusMode));
+ assert_param(IS_I2C_FM_DUTY_CYCLE(I2C_InitStruct->FmDutyCycle));
+ assert_param(IS_I2C_OWN_ADDR1(I2C_InitStruct->OwnAddr1));
+ assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->AckEnable));
+ assert_param(IS_I2C_ADDR_MODE(I2C_InitStruct->AddrMode));
+
+ /*---------------------------- I2Cx CTRL2 Configuration ------------------------*/
+ /* Get the I2Cx CTRL2 value */
+ tmpregister = I2Cx->CTRL2;
+ /* Clear frequency FREQ[5:0] bits */
+ tmpregister &= CTRL2_CLKFREQ_RESET;
+ /* Get pclk1 frequency value */
+ RCC_GetClocksFreqValue(&rcc_clocks);
+ pclk1 = rcc_clocks.Pclk1Freq;
+ /* Set frequency bits depending on pclk1 value */
+ freqrange = (uint16_t)(pclk1 / 1000000);
+ tmpregister |= freqrange;
+ /* Write to I2Cx CTRL2 */
+ I2Cx->CTRL2 = tmpregister;
+
+ /*---------------------------- I2Cx CHCFG Configuration ------------------------*/
+ /* Disable the selected I2C peripheral to configure TMRISE */
+ I2Cx->CTRL1 &= CTRL1_SPEN_RESET;
+ /* Reset tmpregister value */
+ /* Clear F/S, DUTY and CHCFG[11:0] bits */
+ tmpregister = 0;
+
+ /* Configure speed in standard mode */
+ if (I2C_InitStruct->ClkSpeed <= 100000)
+ {
+ /* Standard mode speed calculate */
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->ClkSpeed << 1));
+ /* Test if CHCFG value is under 0x4*/
+ if (result < 0x04)
+ {
+ /* Set minimum allowed value */
+ result = 0x04;
+ }
+ /* Set speed value for standard mode */
+ tmpregister |= result;
+ /* Set Maximum Rise Time for standard mode */
+ I2Cx->TMRISE = freqrange + 1;
+ }
+ /* Configure speed in fast mode */
+ // else if ((I2C_InitStruct->ClkSpeed > 100000)&&(I2C_InitStruct->ClkSpeed <= 400000))/*(I2C_InitStruct->ClkSpeed <=
+ // 400000)*/
+ else
+ {
+ if (I2C_InitStruct->FmDutyCycle == I2C_FMDUTYCYCLE_2)
+ {
+ /* Fast mode speed calculate: Tlow/Thigh = 2 */
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->ClkSpeed * 3));
+ }
+ else /*I2C_InitStruct->FmDutyCycle == I2C_FMDUTYCYCLE_16_9*/
+ {
+ /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->ClkSpeed * 25));
+ /* Set DUTY bit */
+ result |= I2C_FMDUTYCYCLE_16_9;
+ }
+
+ /* Test if CHCFG value is under 0x1*/
+ if ((result & CLKCTRL_CLKCTRL_SET) == 0)
+ {
+ /* Set minimum allowed value */
+ result |= (uint16_t)0x0001;
+ }
+ /* Set speed value and set F/S bit for fast mode */
+ tmpregister |= (uint16_t)(result | CLKCTRL_FSMODE_SET);
+ /* Set Maximum Rise Time for fast mode */
+ // if (I2C_InitStruct->ClkSpeed <= 400000)
+ {
+ I2Cx->TMRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
+ }
+ // else//add test
+ //{
+ // I2Cx->TMRISE = (uint16_t)(((freqrange * (uint16_t)100) / (uint16_t)1000) + (uint16_t)1);
+ //}
+ }
+ /* Write to I2Cx CHCFG */
+ I2Cx->CLKCTRL = tmpregister;
+ /* Enable the selected I2C peripheral */
+ I2Cx->CTRL1 |= CTRL1_SPEN_SET;
+
+ /*---------------------------- I2Cx CTRL1 Configuration ------------------------*/
+ /* Get the I2Cx CTRL1 value */
+ tmpregister = I2Cx->CTRL1;
+ /* Clear ACK, SMBTYPE and SMBUS bits */
+ tmpregister &= CTRL1_CLR_MASK;
+ /* Configure I2Cx: mode and acknowledgement */
+ /* Set SMBTYPE and SMBUS bits according to BusMode value */
+ /* Set ACK bit according to AckEnable value */
+ tmpregister |= (uint16_t)((uint32_t)I2C_InitStruct->BusMode | I2C_InitStruct->AckEnable);
+ /* Write to I2Cx CTRL1 */
+ I2Cx->CTRL1 = tmpregister;
+
+ /*---------------------------- I2Cx OADDR1 Configuration -----------------------*/
+ /* Set I2Cx Own Address1 and acknowledged address */
+ I2Cx->OADDR1 = (I2C_InitStruct->AddrMode | I2C_InitStruct->OwnAddr1);
+}
+
+/**
+ * @brief Fills each I2C_InitStruct member with its default value.
+ * @param I2C_InitStruct pointer to an I2C_InitType structure which will be initialized.
+ */
+void I2C_InitStruct(I2C_InitType* I2C_InitStruct)
+{
+ /*---------------- Reset I2C init structure parameters values ----------------*/
+ /* initialize the ClkSpeed member */
+ I2C_InitStruct->ClkSpeed = 5000;
+ /* Initialize the BusMode member */
+ I2C_InitStruct->BusMode = I2C_BUSMODE_I2C;
+ /* Initialize the FmDutyCycle member */
+ I2C_InitStruct->FmDutyCycle = I2C_FMDUTYCYCLE_2;
+ /* Initialize the OwnAddr1 member */
+ I2C_InitStruct->OwnAddr1 = 0;
+ /* Initialize the AckEnable member */
+ I2C_InitStruct->AckEnable = I2C_ACKDIS;
+ /* Initialize the AddrMode member */
+ I2C_InitStruct->AddrMode = I2C_ADDR_MODE_7BIT;
+}
+
+/**
+ * @brief Enables or disables the specified I2C peripheral.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2Cx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_Enable(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected I2C peripheral */
+ I2Cx->CTRL1 |= CTRL1_SPEN_SET;
+ }
+ else
+ {
+ /* Disable the selected I2C peripheral */
+ I2Cx->CTRL1 &= CTRL1_SPEN_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C DMA requests.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C DMA transfer.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableDMA(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected I2C DMA requests */
+ I2Cx->CTRL2 |= CTRL2_DMAEN_SET;
+ }
+ else
+ {
+ /* Disable the selected I2C DMA requests */
+ I2Cx->CTRL2 &= CTRL2_DMAEN_RESET;
+ }
+}
+
+/**
+ * @brief Specifies if the next DMA transfer will be the last one.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C DMA last transfer.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableDmaLastSend(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Next DMA transfer is the last transfer */
+ I2Cx->CTRL2 |= CTRL2_DMALAST_SET;
+ }
+ else
+ {
+ /* Next DMA transfer is not the last transfer */
+ I2Cx->CTRL2 &= CTRL2_DMALAST_RESET;
+ }
+}
+
+/**
+ * @brief Generates I2Cx communication START condition.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C START condition generation.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_GenerateStart(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Generate a START condition */
+ I2Cx->CTRL1 |= CTRL1_START_SET;
+ }
+ else
+ {
+ /* Disable the START condition generation */
+ I2Cx->CTRL1 &= CTRL1_START_RESET;
+ }
+}
+
+/**
+ * @brief Generates I2Cx communication STOP condition.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C STOP condition generation.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_GenerateStop(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Generate a STOP condition */
+ I2Cx->CTRL1 |= CTRL1_STOP_SET;
+ }
+ else
+ {
+ /* Disable the STOP condition generation */
+ I2Cx->CTRL1 &= CTRL1_STOP_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C acknowledge feature.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C Acknowledgement.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_ConfigAck(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the acknowledgement */
+ I2Cx->CTRL1 |= CTRL1_ACK_SET;
+ }
+ else
+ {
+ /* Disable the acknowledgement */
+ I2Cx->CTRL1 &= CTRL1_ACK_RESET;
+ }
+}
+
+/**
+ * @brief Configures the specified I2C own address2.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Address specifies the 7bit I2C own address2.
+ */
+void I2C_ConfigOwnAddr2(I2C_Module* I2Cx, uint8_t Address)
+{
+ uint16_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+
+ /* Get the old register value */
+ tmpregister = I2Cx->OADDR2;
+
+ /* Reset I2Cx Own address2 bit [7:1] */
+ tmpregister &= OADDR2_ADDR2_RESET;
+
+ /* Set I2Cx Own address2 */
+ tmpregister |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
+
+ /* Store the new register value */
+ I2Cx->OADDR2 = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the specified I2C dual addressing mode.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C dual addressing mode.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableDualAddr(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable dual addressing mode */
+ I2Cx->OADDR2 |= OADDR2_DUALEN_SET;
+ }
+ else
+ {
+ /* Disable dual addressing mode */
+ I2Cx->OADDR2 &= OADDR2_DUALEN_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C general call feature.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C General call.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableGeneralCall(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable generall call */
+ I2Cx->CTRL1 |= CTRL1_GCEN_SET;
+ }
+ else
+ {
+ /* Disable generall call */
+ I2Cx->CTRL1 &= CTRL1_GCEN_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C interrupts.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT specifies the I2C interrupts sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_INT_BUF Buffer interrupt mask
+ * @arg I2C_INT_EVENT Event interrupt mask
+ * @arg I2C_INT_ERR Error interrupt mask
+ * @param Cmd new state of the specified I2C interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_ConfigInt(I2C_Module* I2Cx, uint16_t I2C_IT, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ assert_param(IS_I2C_CFG_INT(I2C_IT));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected I2C interrupts */
+ I2Cx->CTRL2 |= I2C_IT;
+ }
+ else
+ {
+ /* Disable the selected I2C interrupts */
+ I2Cx->CTRL2 &= (uint16_t)~I2C_IT;
+ }
+}
+
+/**
+ * @brief Sends a data byte through the I2Cx peripheral.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Data Byte to be transmitted..
+ */
+void I2C_SendData(I2C_Module* I2Cx, uint8_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ /* Write in the DAT register the data to be sent */
+ I2Cx->DAT = Data;
+}
+
+/**
+ * @brief Returns the most recent received data by the I2Cx peripheral.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @return The value of the received data.
+ */
+uint8_t I2C_RecvData(I2C_Module* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ /* Return the data in the DAT register */
+ return (uint8_t)I2Cx->DAT;
+}
+
+/**
+ * @brief Transmits the address byte to select the slave device.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Address specifies the slave address which will be transmitted
+ * @param I2C_Direction specifies whether the I2C device will be a
+ * Transmitter or a Receiver. This parameter can be one of the following values
+ * @arg I2C_DIRECTION_SEND Transmitter mode
+ * @arg I2C_DIRECTION_RECV Receiver mode
+ */
+void I2C_SendAddr7bit(I2C_Module* I2Cx, uint8_t Address, uint8_t I2C_Direction)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_DIRECTION(I2C_Direction));
+ /* Test on the direction to set/reset the read/write bit */
+ if (I2C_Direction != I2C_DIRECTION_SEND)
+ {
+ /* Set the address bit0 for read */
+ Address |= OADDR1_ADDR0_SET;
+ }
+ else
+ {
+ /* Reset the address bit0 for write */
+ Address &= OADDR1_ADDR0_RESET;
+ }
+ /* Send the address */
+ I2Cx->DAT = Address;
+}
+
+/**
+ * @brief Reads the specified I2C register and returns its value.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_Register specifies the register to read.
+ * This parameter can be one of the following values:
+ * @arg I2C_REG_CTRL1 CTRL1 register.
+ * @arg I2C_REG_CTRL2 CTRL2 register.
+ * @arg I2C_REG_OADDR1 OADDR1 register.
+ * @arg I2C_REG_OADDR2 OADDR2 register.
+ * @arg I2C_REG_DAT DAT register.
+ * @arg I2C_REG_STS1 STS1 register.
+ * @arg I2C_REG_STS2 STS2 register.
+ * @arg I2C_REG_CLKCTRL CHCFG register.
+ * @arg I2C_REG_TMRISE TMRISE register.
+ * @return The value of the read register.
+ */
+uint16_t I2C_GetRegister(I2C_Module* I2Cx, uint8_t I2C_Register)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_REG(I2C_Register));
+
+ tmp = (uint32_t)I2Cx;
+ tmp += I2C_Register;
+
+ /* Return the selected register value */
+ return (*(__IO uint16_t*)tmp);
+}
+
+/**
+ * @brief Enables or disables the specified I2C software reset.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C software reset.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableSoftwareReset(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Peripheral under reset */
+ I2Cx->CTRL1 |= CTRL1_SWRESET_SET;
+ }
+ else
+ {
+ /* Peripheral not under reset */
+ I2Cx->CTRL1 &= CTRL1_SWRESET_RESET;
+ }
+}
+
+/**
+ * @brief Selects the specified I2C NACK position in master receiver mode.
+ * This function is useful in I2C Master Receiver mode when the number
+ * of data to be received is equal to 2. In this case, this function
+ * should be called (with parameter I2C_NACK_POS_NEXT) before data
+ * reception starts,as described in the 2-byte reception procedure
+ * recommended in Reference Manual in Section: Master receiver.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_NACKPosition specifies the NACK position.
+ * This parameter can be one of the following values:
+ * @arg I2C_NACK_POS_NEXT indicates that the next byte will be the last
+ * received byte.
+ * @arg I2C_NACK_POS_CURRENT indicates that current byte is the last
+ * received byte.
+ *
+ * @note This function configures the same bit (POS) as I2C_ConfigPecLocation()
+ * but is intended to be used in I2C mode while I2C_ConfigPecLocation()
+ * is intended to used in SMBUS mode.
+ *
+ */
+void I2C_ConfigNackLocation(I2C_Module* I2Cx, uint16_t I2C_NACKPosition)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_NACK_POS(I2C_NACKPosition));
+
+ /* Check the input parameter */
+ if (I2C_NACKPosition == I2C_NACK_POS_NEXT)
+ {
+ /* Next byte in shift register is the last received byte */
+ I2Cx->CTRL1 |= I2C_NACK_POS_NEXT;
+ }
+ else
+ {
+ /* Current byte in shift register is the last received byte */
+ I2Cx->CTRL1 &= I2C_NACK_POS_CURRENT;
+ }
+}
+
+/**
+ * @brief Drives the SMBusAlert pin high or low for the specified I2C.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_SMBusAlert specifies SMBAlert pin level.
+ * This parameter can be one of the following values:
+ * @arg I2C_SMBALERT_LOW SMBAlert pin driven low
+ * @arg I2C_SMBALERT_HIGH SMBAlert pin driven high
+ */
+void I2C_ConfigSmbusAlert(I2C_Module* I2Cx, uint16_t I2C_SMBusAlert)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_SMB_ALERT(I2C_SMBusAlert));
+ if (I2C_SMBusAlert == I2C_SMBALERT_LOW)
+ {
+ /* Drive the SMBusAlert pin Low */
+ I2Cx->CTRL1 |= I2C_SMBALERT_LOW;
+ }
+ else
+ {
+ /* Drive the SMBusAlert pin High */
+ I2Cx->CTRL1 &= I2C_SMBALERT_HIGH;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C PEC transfer.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C PEC transmission.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_SendPEC(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected I2C PEC transmission */
+ I2Cx->CTRL1 |= CTRL1_PEC_SET;
+ }
+ else
+ {
+ /* Disable the selected I2C PEC transmission */
+ I2Cx->CTRL1 &= CTRL1_PEC_RESET;
+ }
+}
+
+/**
+ * @brief Selects the specified I2C PEC position.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_PECPosition specifies the PEC position.
+ * This parameter can be one of the following values:
+ * @arg I2C_PEC_POS_NEXT indicates that the next byte is PEC
+ * @arg I2C_PEC_POS_CURRENT indicates that current byte is PEC
+ *
+ * @note This function configures the same bit (POS) as I2C_ConfigNackLocation()
+ * but is intended to be used in SMBUS mode while I2C_ConfigNackLocation()
+ * is intended to used in I2C mode.
+ *
+ */
+void I2C_ConfigPecLocation(I2C_Module* I2Cx, uint16_t I2C_PECPosition)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_PEC_POS(I2C_PECPosition));
+ if (I2C_PECPosition == I2C_PEC_POS_NEXT)
+ {
+ /* Next byte in shift register is PEC */
+ I2Cx->CTRL1 |= I2C_PEC_POS_NEXT;
+ }
+ else
+ {
+ /* Current byte in shift register is PEC */
+ I2Cx->CTRL1 &= I2C_PEC_POS_CURRENT;
+ }
+}
+
+/**
+ * @brief Enables or disables the PEC value calculation of the transferred bytes.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2Cx PEC value calculation.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_ComputePec(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected I2C PEC calculation */
+ I2Cx->CTRL1 |= CTRL1_PECEN_SET;
+ }
+ else
+ {
+ /* Disable the selected I2C PEC calculation */
+ I2Cx->CTRL1 &= CTRL1_PECEN_RESET;
+ }
+}
+
+/**
+ * @brief Returns the PEC value for the specified I2C.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @return The PEC value.
+ */
+uint8_t I2C_GetPec(I2C_Module* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ /* Return the selected I2C PEC value */
+ return ((I2Cx->STS2) >> 8);
+}
+
+/**
+ * @brief Enables or disables the specified I2C ARP.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2Cx ARP.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableArp(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected I2C ARP */
+ I2Cx->CTRL1 |= CTRL1_ARPEN_SET;
+ }
+ else
+ {
+ /* Disable the selected I2C ARP */
+ I2Cx->CTRL1 &= CTRL1_ARPEN_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C Clock stretching.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2Cx Clock stretching.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableExtendClk(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd == DISABLE)
+ {
+ /* Enable the selected I2C Clock stretching */
+ I2Cx->CTRL1 |= CTRL1_NOEXTEND_SET;
+ }
+ else
+ {
+ /* Disable the selected I2C Clock stretching */
+ I2Cx->CTRL1 &= CTRL1_NOEXTEND_RESET;
+ }
+}
+
+/**
+ * @brief Selects the specified I2C fast mode duty cycle.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param FmDutyCycle specifies the fast mode duty cycle.
+ * This parameter can be one of the following values:
+ * @arg I2C_FMDUTYCYCLE_2 I2C fast mode Tlow/Thigh = 2
+ * @arg I2C_FMDUTYCYCLE_16_9 I2C fast mode Tlow/Thigh = 16/9
+ */
+void I2C_ConfigFastModeDutyCycle(I2C_Module* I2Cx, uint16_t FmDutyCycle)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_FM_DUTY_CYCLE(FmDutyCycle));
+ if (FmDutyCycle != I2C_FMDUTYCYCLE_16_9)
+ {
+ /* I2C fast mode Tlow/Thigh=2 */
+ I2Cx->CLKCTRL &= I2C_FMDUTYCYCLE_2;
+ }
+ else
+ {
+ /* I2C fast mode Tlow/Thigh=16/9 */
+ I2Cx->CLKCTRL |= I2C_FMDUTYCYCLE_16_9;
+ }
+}
+
+/**
+ * @brief
+ ****************************************************************************************
+ *
+ * I2C State Monitoring Functions
+ *
+ ****************************************************************************************
+ * This I2C driver provides three different ways for I2C state monitoring
+ * depending on the application requirements and constraints:
+ *
+ *
+ * 1) Basic state monitoring:
+ * Using I2C_CheckEvent() function:
+ * It compares the status registers (STS1 and STS2) content to a given event
+ * (can be the combination of one or more flags).
+ * It returns SUCCESS if the current status includes the given flags
+ * and returns ERROR if one or more flags are missing in the current status.
+ * - When to use:
+ * - This function is suitable for most applications as well as for startup
+ * activity since the events are fully described in the product reference manual
+ * (RM0008).
+ * - It is also suitable for users who need to define their own events.
+ * - Limitations:
+ * - If an error occurs (ie. error flags are set besides to the monitored flags),
+ * the I2C_CheckEvent() function may return SUCCESS despite the communication
+ * hold or corrupted real state.
+ * In this case, it is advised to use error interrupts to monitor the error
+ * events and handle them in the interrupt IRQ handler.
+ *
+ * @note
+ * For error management, it is advised to use the following functions:
+ * - I2C_ConfigInt() to configure and enable the error interrupts (I2C_INT_ERR).
+ * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
+ * Where x is the peripheral instance (I2C1, I2C2 ...)
+ * - I2C_GetFlag() or I2C_GetIntStatus() to be called into I2Cx_ER_IRQHandler()
+ * in order to determine which error occured.
+ * - I2C_ClrFlag() or I2C_ClrIntPendingBit() and/or I2C_EnableSoftwareReset()
+ * and/or I2C_GenerateStop() in order to clear the error flag and source,
+ * and return to correct communication status.
+ *
+ *
+ * 2) Advanced state monitoring:
+ * Using the function I2C_GetLastEvent() which returns the image of both status
+ * registers in a single word (uint32_t) (Status Register 2 value is shifted left
+ * by 16 bits and concatenated to Status Register 1).
+ * - When to use:
+ * - This function is suitable for the same applications above but it allows to
+ * overcome the mentioned limitation of I2C_GetFlag() function.
+ * The returned value could be compared to events already defined in the
+ * library (n32l43x_i2c.h) or to custom values defined by user.
+ * - This function is suitable when multiple flags are monitored at the same time.
+ * - At the opposite of I2C_CheckEvent() function, this function allows user to
+ * choose when an event is accepted (when all events flags are set and no
+ * other flags are set or just when the needed flags are set like
+ * I2C_CheckEvent() function).
+ * - Limitations:
+ * - User may need to define his own events.
+ * - Same remark concerning the error management is applicable for this
+ * function if user decides to check only regular communication flags (and
+ * ignores error flags).
+ *
+ *
+ * 3) Flag-based state monitoring:
+ * Using the function I2C_GetFlag() which simply returns the status of
+ * one single flag (ie. I2C_FLAG_RXDATNE ...).
+ * - When to use:
+ * - This function could be used for specific applications or in debug phase.
+ * - It is suitable when only one flag checking is needed (most I2C events
+ * are monitored through multiple flags).
+ * - Limitations:
+ * - When calling this function, the Status register is accessed. Some flags are
+ * cleared when the status register is accessed. So checking the status
+ * of one Flag, may clear other ones.
+ * - Function may need to be called twice or more in order to monitor one
+ * single event.
+ *
+ * For detailed description of Events, please refer to section I2C_Events in
+ * n32l43x_i2c.h file.
+ *
+ */
+
+/**
+ * @brief Checks whether the last I2Cx Event is equal to the one passed
+ * as parameter.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_EVENT specifies the event to be checked.
+ * This parameter can be one of the following values:
+ * @arg I2C_EVT_SLAVE_SEND_ADDR_MATCHED EV1
+ * @arg I2C_EVT_SLAVE_RECV_ADDR_MATCHED EV1
+ * @arg I2C_EVT_SLAVE_SEND_ADDR2_MATCHED EV1
+ * @arg I2C_EVT_SLAVE_RECV_ADDR2_MATCHED EV1
+ * @arg I2C_EVT_SLAVE_GCALLADDR_MATCHED EV1
+ * @arg I2C_EVT_SLAVE_DATA_RECVD EV2
+ * @arg (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_DUALFLAG) EV2
+ * @arg (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_GCALLADDR) EV2
+ * @arg I2C_EVT_SLAVE_DATA_SENDED EV3
+ * @arg (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_DUALFLAG) EV3
+ * @arg (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_GCALLADDR) EV3
+ * @arg I2C_EVT_SLAVE_ACK_MISS EV3_2
+ * @arg I2C_EVT_SLAVE_STOP_RECVD EV4
+ * @arg I2C_EVT_MASTER_MODE_FLAG EV5
+ * @arg I2C_EVT_MASTER_TXMODE_FLAG EV6
+ * @arg I2C_EVT_MASTER_RXMODE_FLAG EV6
+ * @arg I2C_EVT_MASTER_DATA_RECVD_FLAG EV7
+ * @arg I2C_EVT_MASTER_DATA_SENDING EV8
+ * @arg I2C_EVT_MASTER_DATA_SENDED EV8_2
+ * @arg I2C_EVT_MASTER_MODE_ADDRESS10_FLAG EV9
+ *
+ * @note: For detailed description of Events, please refer to section
+ * I2C_Events in n32l43x_i2c.h file.
+ *
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: Last event is equal to the I2C_EVENT
+ * - ERROR: Last event is different from the I2C_EVENT
+ */
+ErrorStatus I2C_CheckEvent(I2C_Module* I2Cx, uint32_t I2C_EVENT)
+{
+ uint32_t lastevent = 0;
+ uint32_t flag1 = 0, flag2 = 0;
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_EVT(I2C_EVENT));
+
+ /* Read the I2Cx status register */
+ flag1 = I2Cx->STS1;
+ flag2 = I2Cx->STS2;
+ flag2 = flag2 << 16;
+
+ /* Get the last event value from I2C status register */
+ lastevent = (flag1 | flag2) & FLAG_MASK;
+
+ /* Check whether the last event contains the I2C_EVENT */
+ if ((lastevent & I2C_EVENT) == I2C_EVENT)
+ {
+ /* SUCCESS: last event is equal to I2C_EVENT */
+ status = SUCCESS;
+ }
+ else
+ {
+ /* ERROR: last event is different from I2C_EVENT */
+ status = ERROR;
+ }
+ /* Return status */
+ return status;
+}
+
+/**
+ * @brief Returns the last I2Cx Event.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ *
+ * @note: For detailed description of Events, please refer to section
+ * I2C_Events in n32l43x_i2c.h file.
+ *
+ * @return The last event
+ */
+uint32_t I2C_GetLastEvent(I2C_Module* I2Cx)
+{
+ uint32_t lastevent = 0;
+ uint32_t flag1 = 0, flag2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+
+ /* Read the I2Cx status register */
+ flag1 = I2Cx->STS1;
+ flag2 = I2Cx->STS2;
+ flag2 = flag2 << 16;
+
+ /* Get the last event value from I2C status register */
+ lastevent = (flag1 | flag2) & FLAG_MASK;
+
+ /* Return status */
+ return lastevent;
+}
+
+/**
+ * @brief Checks whether the specified I2C flag is set or not.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_FLAG specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg I2C_FLAG_DUALFLAG Dual flag (Slave mode)
+ * @arg I2C_FLAG_SMBHADDR SMBus host header (Slave mode)
+ * @arg I2C_FLAG_SMBDADDR SMBus default header (Slave mode)
+ * @arg I2C_FLAG_GCALLADDR General call header flag (Slave mode)
+ * @arg I2C_FLAG_TRF Transmitter/Receiver flag
+ * @arg I2C_FLAG_BUSY Bus busy flag
+ * @arg I2C_FLAG_MSMODE Master/Slave flag
+ * @arg I2C_FLAG_SMBALERT SMBus Alert flag
+ * @arg I2C_FLAG_TIMOUT Timeout or Tlow error flag
+ * @arg I2C_FLAG_PECERR PEC error in reception flag
+ * @arg I2C_FLAG_OVERRUN Overrun/Underrun flag (Slave mode)
+ * @arg I2C_FLAG_ACKFAIL Acknowledge failure flag
+ * @arg I2C_FLAG_ARLOST Arbitration lost flag (Master mode)
+ * @arg I2C_FLAG_BUSERR Bus error flag
+ * @arg I2C_FLAG_TXDATE Data register empty flag (Transmitter)
+ * @arg I2C_FLAG_RXDATNE Data register not empty (Receiver) flag
+ * @arg I2C_FLAG_STOPF Stop detection flag (Slave mode)
+ * @arg I2C_FLAG_ADDR10F 10-bit header sent flag (Master mode)
+ * @arg I2C_FLAG_BYTEF Byte transfer finished flag
+ * @arg I2C_FLAG_ADDRF Address sent flag (Master mode) "ADSL"
+ * Address matched flag (Slave mode)"ENDA"
+ * @arg I2C_FLAG_STARTBF Start bit flag (Master mode)
+ * @return The new state of I2C_FLAG (SET or RESET).
+ */
+FlagStatus I2C_GetFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ __IO uint32_t i2creg = 0, i2cxbase = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
+
+ /* Get the I2Cx peripheral base address */
+ i2cxbase = (uint32_t)I2Cx;
+
+ /* Read flag register index */
+ i2creg = I2C_FLAG >> 28;
+
+ /* Get bit[23:0] of the flag */
+ I2C_FLAG &= FLAG_MASK;
+
+ if (i2creg != 0)
+ {
+ /* Get the I2Cx STS1 register address */
+ i2cxbase += 0x14;
+ }
+ else
+ {
+ /* Flag in I2Cx STS2 Register */
+ I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
+ /* Get the I2Cx STS2 register address */
+ i2cxbase += 0x18;
+ }
+
+ if (((*(__IO uint32_t*)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
+ {
+ /* I2C_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* I2C_FLAG is reset */
+ bitstatus = RESET;
+ }
+
+ /* Return the I2C_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the I2Cx's pending flags.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_FLAG specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_FLAG_SMBALERT SMBus Alert flag
+ * @arg I2C_FLAG_TIMOUT Timeout or Tlow error flag
+ * @arg I2C_FLAG_PECERR PEC error in reception flag
+ * @arg I2C_FLAG_OVERRUN Overrun/Underrun flag (Slave mode)
+ * @arg I2C_FLAG_ACKFAIL Acknowledge failure flag
+ * @arg I2C_FLAG_ARLOST Arbitration lost flag (Master mode)
+ * @arg I2C_FLAG_BUSERR Bus error flag
+ *
+ * @note
+ * - STOPF (STOP detection) is cleared by software sequence: a read operation
+ * to I2C_STS1 register (I2C_GetFlag()) followed by a write operation
+ * to I2C_CTRL1 register (I2C_Enable() to re-enable the I2C peripheral).
+ * - ADD10 (10-bit header sent) is cleared by software sequence: a read
+ * operation to I2C_STS1 (I2C_GetFlag()) followed by writing the
+ * second byte of the address in DAT register.
+ * - BTF (Byte Transfer Finished) is cleared by software sequence: a read
+ * operation to I2C_STS1 register (I2C_GetFlag()) followed by a
+ * read/write to I2C_DAT register (I2C_SendData()).
+ * - ADDR (Address sent) is cleared by software sequence: a read operation to
+ * I2C_STS1 register (I2C_GetFlag()) followed by a read operation to
+ * I2C_STS2 register ((void)(I2Cx->STS2)).
+ * - SB (Start Bit) is cleared software sequence: a read operation to I2C_STS1
+ * register (I2C_GetFlag()) followed by a write operation to I2C_DAT
+ * register (I2C_SendData()).
+ */
+void I2C_ClrFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG)
+{
+ uint32_t flagpos = 0;
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_CLR_FLAG(I2C_FLAG));
+ /* Get the I2C flag position */
+ flagpos = I2C_FLAG & FLAG_MASK;
+ /* Clear the selected I2C flag */
+ I2Cx->STS1 = (uint16_t)~flagpos;
+}
+
+/**
+ * @brief Checks whether the specified I2C interrupt has occurred or not.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT specifies the interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg I2C_INT_SMBALERT SMBus Alert flag
+ * @arg I2C_INT_TIMOUT Timeout or Tlow error flag
+ * @arg I2C_INT_PECERR PEC error in reception flag
+ * @arg I2C_INT_OVERRUN Overrun/Underrun flag (Slave mode)
+ * @arg I2C_INT_ACKFAIL Acknowledge failure flag
+ * @arg I2C_INT_ARLOST Arbitration lost flag (Master mode)
+ * @arg I2C_INT_BUSERR Bus error flag
+ * @arg I2C_INT_TXDATE Data register empty flag (Transmitter)
+ * @arg I2C_INT_RXDATNE Data register not empty (Receiver) flag
+ * @arg I2C_INT_STOPF Stop detection flag (Slave mode)
+ * @arg I2C_INT_ADDR10F 10-bit header sent flag (Master mode)
+ * @arg I2C_INT_BYTEF Byte transfer finished flag
+ * @arg I2C_INT_ADDRF Address sent flag (Master mode) "ADSL"
+ * Address matched flag (Slave mode)"ENDAD"
+ * @arg I2C_INT_STARTBF Start bit flag (Master mode)
+ * @return The new state of I2C_IT (SET or RESET).
+ */
+INTStatus I2C_GetIntStatus(I2C_Module* I2Cx, uint32_t I2C_IT)
+{
+ INTStatus bitstatus = RESET;
+ uint32_t enablestatus = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_GET_INT(I2C_IT));
+
+ /* Check if the interrupt source is enabled or not */
+ enablestatus = (uint32_t)(((I2C_IT & INTEN_MASK) >> 16) & (I2Cx->CTRL2));
+
+ /* Get bit[23:0] of the flag */
+ I2C_IT &= FLAG_MASK;
+
+ /* Check the status of the specified I2C flag */
+ if (((I2Cx->STS1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
+ {
+ /* I2C_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* I2C_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the I2C_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the I2Cx's interrupt pending bits.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_INT_SMBALERT SMBus Alert interrupt
+ * @arg I2C_INT_TIMOUT Timeout or Tlow error interrupt
+ * @arg I2C_INT_PECERR PEC error in reception interrupt
+ * @arg I2C_INT_OVERRUN Overrun/Underrun interrupt (Slave mode)
+ * @arg I2C_INT_ACKFAIL Acknowledge failure interrupt
+ * @arg I2C_INT_ARLOST Arbitration lost interrupt (Master mode)
+ * @arg I2C_INT_BUSERR Bus error interrupt
+ *
+ * @note
+ * - STOPF (STOP detection) is cleared by software sequence: a read operation
+ * to I2C_STS1 register (I2C_GetIntStatus()) followed by a write operation to
+ * I2C_CTRL1 register (I2C_Enable() to re-enable the I2C peripheral).
+ * - ADD10 (10-bit header sent) is cleared by software sequence: a read
+ * operation to I2C_STS1 (I2C_GetIntStatus()) followed by writing the second
+ * byte of the address in I2C_DAT register.
+ * - BTF (Byte Transfer Finished) is cleared by software sequence: a read
+ * operation to I2C_STS1 register (I2C_GetIntStatus()) followed by a
+ * read/write to I2C_DAT register (I2C_SendData()).
+ * - ADDR (Address sent) is cleared by software sequence: a read operation to
+ * I2C_STS1 register (I2C_GetIntStatus()) followed by a read operation to
+ * I2C_STS2 register ((void)(I2Cx->STS2)).
+ * - SB (Start Bit) is cleared by software sequence: a read operation to
+ * I2C_STS1 register (I2C_GetIntStatus()) followed by a write operation to
+ * I2C_DAT register (I2C_SendData()).
+ */
+void I2C_ClrIntPendingBit(I2C_Module* I2Cx, uint32_t I2C_IT)
+{
+ uint32_t flagpos = 0;
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_CLR_INT(I2C_IT));
+ /* Get the I2C flag position */
+ flagpos = I2C_IT & FLAG_MASK;
+ /* Clear the selected I2C flag */
+ I2Cx->STS1 = (uint16_t)~flagpos;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_iwdg.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_iwdg.c
new file mode 100644
index 0000000000..5e54c02cf1
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_iwdg.c
@@ -0,0 +1,193 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_iwdg.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l43x_iwdg.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup IWDG
+ * @brief IWDG driver modules
+ * @{
+ */
+
+/** @addtogroup IWDG_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Private_Defines
+ * @{
+ */
+
+/* ---------------------- IWDG registers bit mask ----------------------------*/
+
+/* KEY register bit mask */
+#define KEY_ReloadKey ((uint16_t)0xAAAA)
+#define KEY_EnableKey ((uint16_t)0xCCCC)
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
+ * @param IWDG_WriteAccess new state of write access to IWDG_PR and IWDG_RLR registers.
+ * This parameter can be one of the following values:
+ * @arg IWDG_WRITE_ENABLE Enable write access to IWDG_PR and IWDG_RLR registers
+ * @arg IWDG_WRITE_DISABLE Disable write access to IWDG_PR and IWDG_RLR registers
+ */
+void IWDG_WriteConfig(uint16_t IWDG_WriteAccess)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_WRITE(IWDG_WriteAccess));
+ IWDG->KEY = IWDG_WriteAccess;
+}
+
+/**
+ * @brief Sets IWDG Prescaler value.
+ * @param IWDG_Prescaler specifies the IWDG Prescaler value.
+ * This parameter can be one of the following values:
+ * @arg IWDG_PRESCALER_DIV4 IWDG prescaler set to 4
+ * @arg IWDG_PRESCALER_DIV8 IWDG prescaler set to 8
+ * @arg IWDG_PRESCALER_DIV16 IWDG prescaler set to 16
+ * @arg IWDG_PRESCALER_DIV32 IWDG prescaler set to 32
+ * @arg IWDG_PRESCALER_DIV64 IWDG prescaler set to 64
+ * @arg IWDG_PRESCALER_DIV128 IWDG prescaler set to 128
+ * @arg IWDG_PRESCALER_DIV256 IWDG prescaler set to 256
+ */
+void IWDG_SetPrescalerDiv(uint8_t IWDG_Prescaler)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_PRESCALER_DIV(IWDG_Prescaler));
+ IWDG->PREDIV = IWDG_Prescaler;
+}
+
+/**
+ * @brief Sets IWDG Reload value.
+ * @param Reload specifies the IWDG Reload value.
+ * This parameter must be a number between 0 and 0x0FFF.
+ */
+void IWDG_CntReload(uint16_t Reload)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_RELOAD(Reload));
+ IWDG->RELV = Reload;
+}
+
+/**
+ * @brief Reloads IWDG counter with value defined in the reload register
+ * (write access to IWDG_PR and IWDG_RLR registers disabled).
+ */
+void IWDG_ReloadKey(void)
+{
+ IWDG->KEY = KEY_ReloadKey;
+}
+
+/**
+ * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
+ */
+void IWDG_Enable(void)
+{
+ IWDG->KEY = KEY_EnableKey;
+}
+
+/**
+ * @brief Checks whether the specified IWDG flag is set or not.
+ * @param IWDG_FLAG specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg IWDG_PVU_FLAG Prescaler Value Update on going
+ * @arg IWDG_CRVU_FLAG Reload Value Update on going
+ * @return The new state of IWDG_FLAG (SET or RESET).
+ */
+FlagStatus IWDG_GetStatus(uint16_t IWDG_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_IWDG_FLAG(IWDG_FLAG));
+ if ((IWDG->STS & IWDG_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lcd.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lcd.c
new file mode 100644
index 0000000000..b1c3461acd
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lcd.c
@@ -0,0 +1,406 @@
+/*****************************************************************************
+* Copyright (c) 2022, Nations Technologies Inc.
+*
+* All rights reserved.
+* ****************************************************************************
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* - Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the disclaimer below.
+*
+* Nations' name may not be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ****************************************************************************/
+
+/**
+ * @file n32l43x_lcd.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+
+#include "n32l43x_lcd.h"
+
+/** @addtogroup N32L43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup LCD
+ * @brief LCD driver modules
+ * @{
+ */
+
+/** @addtogroup LCD_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup LCD_Private_Defines
+ * @{
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @brief Initialize the LCD peripheral according to the specified parameters
+ * in the LCD_InitStruct.
+ * @param LCD_InitStructure LCD initialize structure parameters
+ * @retval LCD error code
+ */
+LCD_ErrorTypeDef LCD_Init(LCD_InitType *LCD_InitStructure )
+{
+ uint32_t tmp, timeout;
+
+ /* Check function parameters */
+ assert_param(IS_LCD_BIAS(LCD_InitStructure->Bias));
+ assert_param(IS_LCD_BLINKFREQ(LCD_InitStructure->BlinkFreq));
+ assert_param(IS_LCD_BLINKMODE(LCD_InitStructure->BlinkMode));
+ assert_param(IS_LCD_CONTRASTLEVEL(LCD_InitStructure->Contrast));
+ assert_param(IS_LCD_DEADTIME(LCD_InitStructure->DeadTime));
+ assert_param(IS_LCD_DIVIDER(LCD_InitStructure->Divider));
+ assert_param(IS_LCD_DUTY(LCD_InitStructure->Duty));
+ assert_param(IS_LCD_HIGHDRIVE(LCD_InitStructure->HighDrive));
+ assert_param(IS_LCD_HIGHDRIVEBUFFER(LCD_InitStructure->HighDriveBuffer));
+ assert_param(IS_LCD_MUXSEGMENT(LCD_InitStructure->MuxSegment));
+ assert_param(IS_LCD_PRESCALER(LCD_InitStructure->Prescaler));
+ assert_param(IS_LCD_PULSEONDURATION(LCD_InitStructure->PulseOnDuration));
+ assert_param(IS_LCD_VOLTAGESOURCE(LCD_InitStructure->VoltageSource));
+
+ /*Disable LCD controller*/
+ __LCD_DISABLE();
+
+ /*During 1/8 duty mode, 1/4 bias is not supported,use 1/3 bias instead*/
+ if (LCD_DUTY_1_8 == LCD_InitStructure->Duty)
+ {
+ if (LCD_BIAS_1_4 == LCD_InitStructure->Bias)
+ LCD_InitStructure->Bias = LCD_BIAS_1_3;
+ }
+
+ /* set the bits of LCD_CTRL register with corresonding parameters */
+ tmp = 0;
+ tmp |= LCD_InitStructure->HighDriveBuffer;
+ tmp |= LCD_InitStructure->MuxSegment;
+ tmp |= LCD_InitStructure->Bias;
+ tmp |= LCD_InitStructure->Duty;
+ tmp |= LCD_InitStructure->VoltageSource;
+ LCD->CTRL = tmp;
+
+ /*If High driver enable, PulseOnDuration must be LCD_PulseOnDuration_1*/
+ if (LCD_InitStructure->HighDrive == LCD_HIGHDRIVE_ENABLE)
+ {
+ LCD_InitStructure->PulseOnDuration = LCD_PULSEONDURATION_1;
+ }
+
+ /* set the bits of LCD_FCTRL register with corresonding parameters */
+ tmp = 0;
+ tmp |= LCD_InitStructure->Prescaler;
+ tmp |= LCD_InitStructure->Divider;
+ tmp |= LCD_InitStructure->BlinkMode;
+ tmp |= LCD_InitStructure->BlinkFreq;
+ tmp |= LCD_InitStructure->Contrast;
+ tmp |= LCD_InitStructure->DeadTime;
+ tmp |= LCD_InitStructure->HighDrive;
+ tmp |= LCD_InitStructure->PulseOnDuration;
+ LCD->FCTRL = tmp;
+
+ /*Clear LCD display ram, and set the update request flag*/
+ LCD_RamClear();
+ __LCD_UPDATE_REQUEST();
+
+ /*Enable LCD controller*/
+ __LCD_ENABLE();
+
+ /*Check the LCD ENSTS status*/
+ timeout = 0;
+ while (RESET == (__LCD_GET_FLAG(LCD_FLAG_ENSTS)))
+ {
+ if (++timeout >= LCD_TIME_OUT)
+ return LCD_ERROR_ENSTS;
+ }
+
+ /*Wait VLCD stable*/
+ timeout = 0;
+ while (RESET == (__LCD_GET_FLAG(LCD_FLAG_RDY)))
+ {
+ if (++timeout >= LCD_TIME_OUT)
+ return LCD_ERROR_RDY;
+ }
+
+ return (LCD_WaitForSynchro());
+}
+
+/**
+ * @brief DeInitialize the LCD peripheral
+ * @param None
+ * @retval None
+ */
+void LCD_DeInit(void)
+{
+ RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LCD,ENABLE);
+ RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LCD,DISABLE);
+}
+
+/**
+ * @brief Config the clock source of LCD
+ * @param LCD_ClkSource specifies the clock source of LCD
+ * This parameter can be one of the following values:
+ * @arg LCD_CLK_SRC_LSI: LCD clock source is LSI
+ * @arg LCD_CLK_SRC_LSE: LCD clock source is LSE,and LSE is oscillator
+ * @arg LCD_CLK_SRC_LSE_BYPASS: LCD clock source is LSE,and LSE is extennal clock
+ * @arg LCD_CLK_SRC_HSE_DIV32: LCD clock source is HSE/32,and HSE is oscillator
+ * @arg LCD_CLK_SRC_HSE_BYPASS_DIV32: LCD clock source is HSE/32,and HSE is extennal clock
+ * @retval LCD error code
+ * note: LCD clock is the same with RTC
+ */
+LCD_ErrorTypeDef LCD_ClockConfig(uint32_t LCD_ClkSource)
+{
+ uint32_t timeout;
+
+ /*Enable PWR peripheral Clock*/
+ RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR,ENABLE);
+
+ if (LCD_CLK_SRC_LSI == LCD_ClkSource)
+ {
+ /*enable LSI clock*/
+ RCC_EnableLsi(ENABLE);
+
+ /*Wait LSI stable*/
+ timeout = 0;
+ while (RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_LSIRD) == RESET)
+ {
+ if (++timeout >LCD_TIME_OUT)
+ return LCD_ERROR_CLK;
+ }
+ }
+ else if ((LCD_CLK_SRC_LSE==LCD_ClkSource)||(LCD_CLK_SRC_LSE_BYPASS==LCD_ClkSource))
+ {
+ if (RCC_GetFlagStatus(RCC_LDCTRL_FLAG_LSERD)==RESET)
+ {
+ RCC_ConfigLse((LCD_ClkSource & (~RCC_LDCTRL_RTCSEL)),0x28);
+ timeout = 0;
+ while (RCC_GetFlagStatus(RCC_LDCTRL_FLAG_LSERD) == RESET)
+ {
+ if (++timeout >LCD_TIME_OUT)
+ return LCD_ERROR_CLK;
+ }
+ }
+ }
+ else if ((LCD_CLK_SRC_HSE_DIV32==LCD_ClkSource)||(LCD_CLK_SRC_HSE_BYPASS_DIV32==LCD_ClkSource))
+ {
+ if (RCC_GetFlagStatus(RCC_CTRL_FLAG_HSERDF)==RESET)
+ {
+ RCC_ConfigHse(LCD_ClkSource & (~RCC_LDCTRL_RTCSEL));
+ if (RCC_WaitHseStable()!=SUCCESS)
+ return LCD_ERROR_CLK;
+ }
+ }
+ else
+ return LCD_ERROR_PARAM;
+
+ // Set bit 8 of PWR_CTRL1.Open PWR DBP.
+ PWR_BackupAccessEnable(ENABLE); //PWR->CTRL1 |= 0x100;
+
+ /*set LSI as RTC clock source*/
+ RCC_ConfigRtcClk(LCD_ClkSource & RCC_LDCTRL_RTCSEL);
+
+ /*Enable RTC clk*/
+ RCC_EnableRtcClk(ENABLE);
+
+ /*Enable LCD clk*/
+ RCC_EnableRETPeriphClk(RCC_RET_PERIPH_LCD,ENABLE);
+
+ return LCD_ERROR_OK;
+}
+
+/**
+ * @brief Clear LCD ram register.
+ * @param None
+ * @retval None
+ */
+void LCD_RamClear(void)
+{
+ uint32_t counter;
+
+ /*Clear lcd ram*/
+ for(counter = LCD_RAM1_COM0; counter <= LCD_RAM2_COM7; counter++)
+ {
+ LCD->RAM_COM[counter] = 0x0U;
+ }
+}
+
+/**
+ * @brief Update Display request.
+ * @param None
+ * @retval LCD error code
+ */
+LCD_ErrorTypeDef LCD_UpdateDisplayRequest(void)
+{
+ uint32_t timeout;
+
+ /*Clear UDD flag*/
+ __LCD_CLEAR_FLAG(LCD_FLAG_UDD_CLEAR);
+
+ /* set update display request bit*/
+ __LCD_UPDATE_REQUEST();
+
+ /* Wait update complete */
+ timeout = 0;
+ while (RESET == (__LCD_GET_FLAG(LCD_FLAG_UDD)))
+ {
+ if (++timeout >= LCD_TIME_OUT)
+ return LCD_ERROR_UDD;
+ }
+
+ return LCD_ERROR_OK;
+}
+
+/**
+ * @brief write to the lcd ram register.
+ * @param RAMRegisterIndex RAM register index,
+ * this parameter can be LCD_RAM_COMx_y where x can be (0..7) and y can be (1..2).
+ * @param RAMRegisterMask specifies the LCD RAM Register Data Mask.
+ * @param RAMData value written to RAM.
+ * @retval LCD error code
+ */
+LCD_ErrorTypeDef LCD_Write(uint32_t RAMRegisterIndex,uint32_t RAMRegisterMask,uint32_t RAMData)
+{
+ uint32_t timeout;
+
+ /* Check function parameters */
+ assert_param(IS_LCD_RAM_REGISTER_INDEX(RAMRegisterIndex));
+
+ if (RAMRegisterIndex > LCD_RAM2_COM7)
+ return LCD_ERROR_PARAM;
+
+ /* Wait VLCD request flag clear */
+ timeout = 0;
+ while (__LCD_GET_FLAG(LCD_FLAG_UDR))
+ {
+ if (++timeout >= LCD_TIME_OUT)
+ {
+ return LCD_ERROR_UDR;
+ }
+ }
+
+ /* Write lcd RAMData */
+ MODIFY_REG(LCD->RAM_COM[RAMRegisterIndex], ~(RAMRegisterMask), RAMData &(~(RAMRegisterMask)));
+
+ return LCD_ERROR_OK;
+
+}
+
+/**
+ * @brief set some bits of lcd ram register.
+ * @param RAMRegisterIndex: RAM register index,
+ * this parameter can be LCD_RAM_COMx_y where x can be (0..7) and y can be (1..2).
+ * @param RAMData: value to be set
+ * @retval LCD error code
+ */
+LCD_ErrorTypeDef LCD_SetBit(uint32_t RAMRegisterIndex,uint32_t RAMData)
+{
+ uint32_t timeout;
+ /* Check function parameters */
+ assert_param(IS_LCD_RAM_REGISTER_INDEX(RAMRegisterIndex));
+
+ if (RAMRegisterIndex > LCD_RAM2_COM7)
+ return LCD_ERROR_PARAM;
+
+ /* Wait VLCD request flag clear */
+ timeout = 0;
+ while (__LCD_GET_FLAG(LCD_FLAG_UDR))
+ {
+ if (++timeout >= LCD_TIME_OUT)
+ {
+ return LCD_ERROR_UDR;
+ }
+ }
+
+ /* Write lcd RAMData */
+ SET_BIT(LCD->RAM_COM[RAMRegisterIndex], RAMData);
+ return LCD_ERROR_OK;
+}
+
+/**
+ * @brief clear some bits of lcd ram register.
+ * @param RAMRegisterIndex: RAM register index,
+ * this parameter can be LCD_RAM_COMx_y where x can be (0..7) and y can be (1..2).
+ * @param RAMData: value to be clear
+ * @retval LCD error code
+ */
+LCD_ErrorTypeDef LCD_ClearBit(uint32_t RAMRegisterIndex,uint32_t RAMData)
+{
+ uint32_t timeout;
+ /* Check function parameters */
+ assert_param(IS_LCD_RAM_REGISTER_INDEX(RAMRegisterIndex));
+
+ if (RAMRegisterIndex > LCD_RAM2_COM7)
+ return LCD_ERROR_PARAM;
+
+ /* Wait VLCD request flag clear */
+ timeout = 0;
+ while (__LCD_GET_FLAG(LCD_FLAG_UDR))
+ {
+ if (++timeout >= LCD_TIME_OUT)
+ {
+ return LCD_ERROR_UDR;
+ }
+ }
+
+ /* Write lcd RAMData */
+ CLEAR_BIT(LCD->RAM_COM[RAMRegisterIndex], RAMData);
+ return LCD_ERROR_OK;
+}
+
+
+/**
+ * @brief Wait until the LCD FCTRL register is synchronized in the LCDCLK domain.
+ * This function must be called after any write operation to LCD_FCTRL register.
+ * @param RAMData: None
+ * @retval LCD error code
+ */
+LCD_ErrorTypeDef LCD_WaitForSynchro(void)
+{
+ uint32_t timeout;
+
+ /* Loop until FCRSF flag is set */
+ timeout = 0;
+ while (RESET == (__LCD_GET_FLAG(LCD_FLAG_FCRSF)))
+ {
+ if (++timeout >= LCD_TIME_OUT)
+ {
+ return LCD_ERROR_FCRSF;
+ }
+ }
+
+ return LCD_ERROR_OK;
+}
+
+/**
+* @}
+*/
+/**
+* @}
+*/
+
+
+
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lprcnt.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lprcnt.c
new file mode 100644
index 0000000000..18d337d6ef
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lprcnt.c
@@ -0,0 +1,891 @@
+/** ----------------------------------------------------------------------------
+ * Nationz Technology Software Support - NATIONZ -
+ * -----------------------------------------------------------------------------
+ * Copyright (c) 2022, Nationz Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaiimer below.
+ *
+ * - Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the disclaimer below in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * Nationz's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+ * -----------------------------------------------------------------------------
+ */
+
+/** ****************************************************************************
+ * @copyright Nationz Co.,Ltd
+ * Copyright (c) 2019 All Rights Reserved
+ *******************************************************************************
+ * @file n32l43x_LPRCNT.c
+ * @author
+ * @date
+ * @version v1.2.0
+ * @brief
+ ******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "n32l43x_LPRCNT.h"
+//nclude "n32l43x_rcc.h"
+//#include "n32l43x.h"
+#include "n32l43x_exti.h"
+#include "misc.h"
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup LPRCNT
+ * @brief LPRCNT driver modules
+ * @{
+ */
+
+/** @defgroup LPRCNT_Private_TypesDefinitions
+ * @{
+ */
+/**
+ * @}
+ */
+
+
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/**
+ * @brief clear LPRCNT interrupt flag funtion.
+ * @param intflag: include LPRCNT interrupt flag
+ * This parameter can be one of the following values:
+ * @arg CALIBRATION_INT_FLAG
+ * @arg REPORT_INT_FLAG
+ * @arg ALARM_INT_FLAG
+ * @retval None
+ */
+void LPRCNT_ClrIntBit(uint32_t IntFlag)
+{
+ LPRCNT->INTSTS |= IntFlag;
+}
+
+/**
+ * @brief Checks whether the specified LPRCNT interrupt has occurred or not.
+ * @param LPRCNT_INT specifies the LPRCNT interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg CALIBRATION_INT_FLAG Calibration mode damped oscillation interrupt.
+ * @arg REPORT_INT_FLAG Report interrupt.
+ * @arg ALARM_INT_FLAG Alarm interrupt .
+ * @return The new state of LPRCNT_INT (SET or RESET).
+ */
+INTStatus LPRCNT_GetIntSts(uint32_t Int)
+{
+ INTStatus bitstatus = RESET;
+ uint32_t Temp = 0;
+
+ Temp = LPRCNT->INTSTS ;
+ Temp &= 0x00070000;
+ if (Temp == Int)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+
+}
+/**
+ * @brief LPRCNT interrupt funtion.
+ * @param MODE_IE: include LPRCNT interrupt
+ * This parameter can be one of the following values:
+ * @arg CALIBRATION_INT
+ * @arg REPORT_INT
+ * @arg ALARM_INT
+ * @param NewState: open or disable
+ * @arg DISABLE
+ * @arg ENABLE
+ * @retval None
+ */
+void LPRCNT_IntEn(uint32_t Mode ,FunctionalState NewState)
+{
+ if (NewState == ENABLE)
+ {
+ LPRCNT->CTRL |= Mode;
+ }
+ else
+ {
+ LPRCNT->CTRL &= ~Mode;
+ }
+}
+/**
+ * @brief configure per channel sensor detection time.
+ * @param ch: sensor channel .
+ * @param vibrationtime: comparator processing duration time.
+ * @param dischargetime: discharge duration time.
+ * @param chargetime: power charge duration time.
+ * @retval None
+ */
+void CfgChannelTime(uint8_t Ch,uint8_t VibrationTime ,uint8_t DischargeTime,uint8_t ChargeTime )
+{
+ uint32_t Temp = 0;
+ switch (Ch)
+ {
+ case CHANNEL_0 :
+ Temp = LPRCNT->CH0CFG1;
+ Temp &= CLEAR_TIME_VALE;
+ Temp |= (uint32_t)((VibrationTime << 16) | (DischargeTime << 8) | (ChargeTime));
+ LPRCNT->CH0CFG1 = Temp;
+ break;
+ case CHANNEL_1 :
+ Temp = LPRCNT->CH1CFG1;
+ Temp &= CLEAR_TIME_VALE;
+ Temp |= (uint32_t)((VibrationTime << 16) | (DischargeTime << 8) | (ChargeTime));
+ LPRCNT->CH1CFG1 = Temp;
+ break;
+ case CHANNEL_2 :
+ Temp = LPRCNT->CH2CFG1;
+ Temp &= CLEAR_TIME_VALE;
+ Temp |= (uint32_t)((VibrationTime << 16) | (DischargeTime << 8) | (ChargeTime));
+ LPRCNT->CH2CFG1 = Temp;
+ break;
+ default: break ;
+ }
+}
+
+/**
+ * @brief get the comparator processing duration time.
+ * @param ch: sensor channel .
+ * @retval duration time
+ */
+uint8_t GetVibrationTime(uint8_t Ch)
+{
+ uint8_t Temp = 0;
+ switch (Ch)
+ {
+ case CHANNEL_0 :
+ Temp = (LPRCNT->CH0CFG1 >> 16);
+ break;
+ case CHANNEL_1 :
+ Temp = (LPRCNT->CH1CFG1 >> 16);
+ break;
+ case CHANNEL_2 :
+ Temp = (LPRCNT->CH2CFG1 >> 16);
+ break;
+ }
+ return Temp;
+}
+/**
+ * @brief get discharge duration time.
+ * @param ch: sensor channel .
+ * @retval discharge duration time
+ */
+uint8_t GetDischargeTime(uint8_t Ch)
+{
+ uint8_t Temp = 0;
+ switch (Ch)
+ {
+ case CHANNEL_0 :
+ Temp = ((LPRCNT->CH0CFG1 >> 8) & 0x3f);
+ break;
+ case CHANNEL_1 :
+ Temp = ((LPRCNT->CH1CFG1 >> 8) & 0x3f);
+ break;
+ case CHANNEL_2 :
+ Temp = ((LPRCNT->CH2CFG1 >> 8) & 0x3f);
+ break;
+ }
+ return Temp;
+}
+/**
+ * @brief get charge duration time.
+ * @param ch: sensor channel .
+ * @retval charge duration time
+ */
+uint8_t GetChargeTime(uint8_t Ch)
+{
+ uint8_t Temp = 0;
+ switch (Ch)
+ {
+ case CHANNEL_0 :
+ Temp = (LPRCNT->CH0CFG1 & 0x3f);
+ break;
+ case CHANNEL_1 :
+ Temp = (LPRCNT->CH1CFG1 & 0x3f);
+ break;
+ case CHANNEL_2 :
+ Temp = (LPRCNT->CH2CFG1 & 0x3f);
+ break;
+ }
+ return Temp;
+}
+/**
+ * @brief configure per channel sensor detection threshold.
+ * @param ch: sensor channel .
+ * @param dacreference: DAC reference value for comparator.
+ * @retval None
+ */
+void CfgChannelDacRefVol(uint8_t Ch,uint8_t DacRef)
+{
+ uint32_t Temp = 0;
+ switch (Ch)
+ {
+ case CHANNEL_0 :
+ Temp = LPRCNT->CH0CFG0;
+ Temp &= (~LPRCNT_CH0CFG0_DACREF);
+ Temp |= (uint32_t)(DacRef <<16);
+ LPRCNT->CH0CFG0 = Temp;
+ break;
+ case CHANNEL_1 :
+ Temp = LPRCNT->CH1CFG0;
+ Temp &= (~LPRCNT_CH1CFG0_DACREF);
+ Temp |= (uint32_t)(DacRef <<16);
+ LPRCNT->CH1CFG0 = Temp;
+ break;
+ case CHANNEL_2 :
+ Temp = LPRCNT->CH2CFG0;
+ Temp &= (~LPRCNT_CH2CFG0_DACREF);
+ Temp |= (uint32_t)(DacRef <<16);
+ LPRCNT->CH2CFG0 = Temp;
+ break;
+ default:
+ break ;
+ }
+
+}
+/**
+ * @brief get the DAC reference voltage.
+ * @param ch: sensor channel .
+ * @retval DAC reference voltage values,Temp <= 64
+ */
+uint8_t GetDacRefVol(uint8_t Ch)
+{
+ uint8_t Temp = 0;
+ switch (Ch)
+ {
+ case CHANNEL_0 :
+ Temp = ((LPRCNT->CH0CFG0 >> 16) & 0x3f);
+ break;
+ case CHANNEL_1 :
+ Temp = ((LPRCNT->CH1CFG0 >> 16) & 0x3f);
+ break;
+ case CHANNEL_2 :
+ Temp = ((LPRCNT->CH2CFG0 >> 16) & 0x3f);
+ break;
+ }
+ return Temp;
+}
+
+/**
+ * @brief configure per channel sensor detection threshold.
+ * @param ch: sensor channel .
+ * @param undampedTh: undamped threshold.
+ * @param dampedTh: damped threshold.
+ * @retval None
+ */
+void CfgChannelThr(uint8_t Ch, uint8_t UndampedTh, uint8_t DampedTh)
+{
+ uint32_t Temp = 0;
+ switch (Ch)
+ {
+ case CHANNEL_0 :
+ Temp = LPRCNT->CH0CFG0;
+ Temp &= CLEAR_TH_VALE;
+ Temp |= (uint32_t)((UndampedTh <<8) | DampedTh);
+ LPRCNT->CH0CFG0 = Temp;
+ break;
+ case CHANNEL_1 :
+ Temp = LPRCNT->CH1CFG0;
+ Temp &= CLEAR_TH_VALE;
+ Temp |= (uint32_t)((UndampedTh <<8) | DampedTh);
+ LPRCNT->CH1CFG0 = Temp;
+ break;
+ case CHANNEL_2 :
+ Temp = LPRCNT->CH2CFG0;
+ Temp &= CLEAR_TH_VALE;
+ Temp |= (uint32_t)((UndampedTh <<8) | DampedTh);
+ LPRCNT->CH2CFG0 = Temp;
+ break;
+ default: break ;
+ }
+}
+
+/**
+ * @brief get undamped threshold.
+ * @param ch: sensor channel .
+ * @retval undamped threshold.
+ */
+uint8_t GetUndampedTh(uint8_t Ch)
+{
+ uint8_t Temp = 0;
+ switch (Ch)
+ {
+ case CHANNEL_0 :
+ Temp = (LPRCNT->CH0CFG0 >> 8);
+ break;
+ case CHANNEL_1 :
+ Temp = (LPRCNT->CH1CFG0 >> 8);
+ break;
+ case CHANNEL_2 :
+ Temp = (LPRCNT->CH2CFG0 >> 8);
+ break;
+ }
+ return Temp;
+}
+/**
+ * @brief get damped threshold.
+ * @param ch: sensor channel .
+ * @retval damped threshold.
+ */
+uint8_t GetDampedTh(uint8_t Ch)
+{
+ uint8_t Temp = 0;
+ switch (Ch)
+ {
+ case CHANNEL_0 :
+ Temp = (LPRCNT->CH0CFG0);
+ break;
+ case CHANNEL_1 :
+ Temp = (LPRCNT->CH1CFG0);
+ break;
+ case CHANNEL_2 :
+ Temp = (LPRCNT->CH2CFG0);
+ break;
+ }
+ return Temp;
+}
+/**
+ * @brief MSI clock prescale.
+ * @param div: division factor
+ * This parameter can be one of the following values:
+ * @arg LPRCNT_PRESCALER_DIV1
+ * @arg LPRCNT_PRESCALER_DIV2
+ * @arg LPRCNT_PRESCALER_DIV4
+ * @arg LPRCNT_PRESCALER_DIV8
+ * @retval None
+ */
+void SetMsiClkPrescale(uint32_t Div)
+{
+ uint32_t Temp = 0;
+ Temp = LPRCNT->CTRL;
+ //clear the bit that need add new vale
+ Temp &= (~LPRCNT_CTRL_CLKDIV);
+ Temp |= Div;
+ LPRCNT->CTRL = Temp;
+}
+
+/**
+ * @brief get the Circle value .
+ * @param ch: there are three state mode
+ * This parameter can be one of the following values:
+ * @retval the ratation Circle value
+ */
+
+uint16_t GetRotationCircle(void)
+{
+ uint16_t Temp;
+ Temp = (uint16_t)LPRCNT->INTSTS;
+ return Temp ;
+
+}
+/**
+ * @brief get the user set circle value .
+ * This parameter can be one of the following values:
+ * @retval the set ratation Circle value
+ */
+
+uint16_t GetSetRcnt(void)
+{
+ uint16_t Temp;
+ Temp = (uint16_t)LPRCNT->CTRL;
+ return Temp ;
+}
+/**
+ * @brief clear the RCNT circle.
+ * @param None
+ * @retval None
+ */
+void ClrRcntCircle(void)
+{
+ uint32_t Temp;
+ Temp = LPRCNT->CMD;
+ //clear the bit that need add new vale
+ Temp &= (~LPRCNT_CMD_CLRCNT);
+ Temp |= LPRCNT_CMD_CLRCNT;
+ LPRCNT->CMD = Temp;
+}
+/**
+ * @brief when the setting number is reach ,it is will creat a overflow interrupt.
+ * @param Circle: the rotating Circle number
+ * @retval None
+ */
+void SetAutoReportCircle(uint16_t Circle)
+{
+ uint32_t Temp = 0;
+ uint16_t Cnt = 0;
+ //when set the circle numbers,need add the lase numbers
+ Cnt = GetRotationCircle();
+ Temp = LPRCNT->CTRL;
+ //clear the bit that need add new vale
+ Temp &= (~LPRCNT_CTRL_RPTTH);
+ Temp |= (uint32_t)(Circle + Cnt);
+ LPRCNT->CTRL = Temp;
+
+}
+#if 0
+/**
+ * @brief when the setting number is reach ,it is will creat a overflow interrupt.
+ * @param Circle: the rotating Circle number
+ * @retval None
+ */
+void SetAutoReportCircle(uint16_t Circle)
+{
+ uint32_t Temp = 0;
+ Temp = LPRCNT->CTRL;
+ //clear the bit that need add new vale
+ Temp &= (~LPRCNT_CTRL_RPTTH);
+ Temp |= (uint32_t)Circle;
+ LPRCNT->CTRL = Temp;
+}
+#endif
+/**
+ * @brief enable to auto detect comparator stop.
+ * @param CMD: ENABLE or DISABLE
+ * @retval None
+ */
+void SetAutoDetectEnale(FunctionalState NewState )
+{
+ uint32_t Temp = 0;
+ Temp = LPRCNT->CTRL;
+ //clear the bit that need add new vale
+ Temp &= (~LPRCNT_CTRL_CMPAUT);
+ Temp |= (uint32_t)(NewState <<23);
+ LPRCNT->CTRL = Temp;
+}
+/**
+ * @brief set auto detect comparator stop need wait period.
+ * @param per: AUTODETPERIOD4 or AUTODETPERIOD8
+ * @retval None
+ */
+void SetAutoDetectPeriod(bool per)
+{
+ uint32_t Temp = 0;
+ Temp = LPRCNT->CAL3;
+ //clear the bit that need add new vale
+ Temp &= (~LPRCNT_CAL3_CMP_AUTO_MODE);
+ Temp |= (uint32_t)(per <<6);
+ LPRCNT->CAL3 = Temp;
+}
+/**
+ * @brief set auto to charge by DAC.
+ * @param En: ENABLE or DISABLE
+ * @retval None
+ */
+void SetPwrAutoCharge(bool En)
+{
+ uint32_t Temp = 0;
+ Temp = LPRCNT->CAL3;
+ //clear the bit that need add new vale
+ Temp &= (~LPRCNT_CAL3_PWR_DUR_EN);
+ Temp |= (uint32_t)(En <<7);
+ LPRCNT->CAL3 = Temp;
+}
+/**
+ * @brief After seveval rounds of scanning , it is necessary to take the average .
+ * @param n: the scanning times , times = 2^n
+ * @retval None
+ */
+void SetScanAverageValue(uint8_t N)
+{
+ uint32_t Temp = 0;
+ if (N <= 3)
+ {
+ Temp = LPRCNT->CTRL;
+ //clear the bit that need add new vale
+ Temp &= (~LPRCNT_CTRL_AVGSEL);
+ Temp |= (uint32_t)(N << 18);
+ LPRCNT->CTRL = Temp;
+ }
+}
+/**
+ * @brief SetVibrationPower.
+ * @param value: the damped vibration power select.
+ * This parameter can be one of the following values:
+ * @arg POWERSELECT1V5
+ * @arg POWERSELECT1V65
+ * @arg POWERSELECT1V8
+ * @arg POWERSELECT2V0
+ * @retval None
+ */
+void SetVibrationPower(uint8_t Value)
+{
+ uint32_t Temp = 0;
+ Temp = LPRCNT->CTRL;
+ //clear the bit that need add new vale
+ Temp &= (~LPRCNT_CTRL_PWRLVL);
+ Temp |= (uint32_t)(Value << 21);
+ LPRCNT->CTRL = Temp;
+}
+
+/**
+ * @brief configure normal sensor scan frequence.
+ * @param low_speed: if the rotating object does not move for a long time ,it will enter into low speed .
+ * @param hight_speed: In other cases, MCU keep in hight speed to detect rotation.
+ * @param swtich_time: the time interval about hight speed swtich to low speed.
+ * @retval None
+ */
+void SetNormalSensorScanfrequence(uint16_t Low_speed,uint8_t Hight_speed,uint8_t Swtich_time)
+{
+ uint32_t Temp = 0;
+ Temp = LPRCNT->SCTRL;
+ //clear the bit that need add new vale
+ Temp &= 0xfc000000;
+ Temp |= (uint32_t)((Low_speed <<16) | (Swtich_time <<8) | (Hight_speed));
+ LPRCNT->SCTRL = Temp;
+}
+/**
+ * @brief get normal sensor low speed values.
+ * @retval low speed values
+ */
+uint16_t GetNormalSensorLowSpeed(void)
+{
+ uint16_t Temp = 0;
+ Temp = (uint16_t)((LPRCNT->SCTRL >> 16) & 0x03ff);
+ return Temp;
+}
+/**
+ * @brief get normal sensor hight speed values.
+ * @retval hight speed values
+ */
+uint8_t GetNormalSensorHightSpeed(void)
+{
+ uint8_t Temp = 0;
+ Temp = (uint8_t)(LPRCNT->SCTRL);
+ return Temp;
+}
+/**
+ * @brief get normal sensor swtich time.
+ * @retval swtich time values
+ */
+uint8_t GetNormalSensorSwtichTime(void)
+{
+ uint8_t Temp = 0;
+ Temp = (uint8_t)(LPRCNT->SCTRL >> 8);
+ return Temp;
+}
+/**
+ * @brief SetAlarmSensorScanfrequence.
+ * @param the frequence is several times than the normal sensor .
+ * This parameter can be one of the following values:
+ * @arg FRETIME4
+ * @arg FRETIME8
+ * @arg FRETIME16
+ * @arg FRETIME32
+ * @retval None
+ */
+void SetAlarmSensorScanfrequence(uint8_t Period)
+{
+ uint32_t Temp = 0;
+ Temp = LPRCNT->CTRL;
+ //clear the bit that need add new vale
+ Temp &= (~LPRCNT_CTRL_ALMPRD);
+ Temp |= (uint32_t)(Period <<26);
+ LPRCNT->CTRL = Temp;
+}
+/**
+ * @brief set LPRCNT module CMD .
+ * @param command .
+ * This parameter can be one of the following values:
+ * @retval None
+ */
+//void LPRCNTModeEnable(uint8_t Cmd)
+//{
+// LPRCNT->CMD |= (uint32_t)Cmd;
+//
+//}
+/**
+ * @brief Read lprcnt Start state .
+ * @param void .
+ * @retval 0 or 1
+ */
+bool ReadStartState(void)
+{
+ bool temp;
+ temp = LPRCNT->CMD;
+ return temp ;
+}
+
+/**
+ * @brief After the comparator , the square waves can be got for each channel .
+ * @param ch: there are in total three sensor.The frequence of the three sensors is staggered,
+ * so the number of square waves will be different.
+ * @retval the waves number
+ */
+uint8_t GetChannelSensorWavesNum(uint8_t Ch)
+{
+ uint8_t Temp =0;
+ if (Ch == CHANNEL_0)
+ {
+ Temp = (LPRCNT->CAL0 & 0x000000ff);
+ return Temp;
+ }
+ else if (Ch == CHANNEL_1)
+ {
+ Temp =((LPRCNT->CAL0 & 0x00ff0000)>> 16);
+ return Temp;
+ }
+ else
+ {
+ Temp = (LPRCNT->CAL1 & 0x000000ff);
+ return Temp;
+ }
+}
+
+/**
+ * @brief Through the threshold value judgment,per channel can redefine as the state mode .
+ * @param ch: there are three state mode
+ * This parameter can be one of the following values:
+ * @arg 0: undamped
+ * @arg 1: middle state
+ * @arg 2: damped
+ * @retval the state value
+ */
+uint8_t GetChannelSensorState(uint8_t Ch)
+{
+ if (Ch == CHANNEL_0)
+ {
+ return ((uint8_t)((LPRCNT->CAL0 >> 8) & 0x3));
+ }
+ else if (Ch == CHANNEL_1)
+ {
+ return ((uint8_t)((LPRCNT->CAL0 >> 24) & 0x3));
+ }
+ else if (Ch == CHANNEL_2)
+ {
+ return ((uint8_t)((LPRCNT->CAL1 >> 8) & 0x3));
+ }
+ else
+ {
+ return CHANNEL_ERROR;//channel error
+ }
+}
+
+/**
+ * @brief get the sample mode .
+ * @param ch: there are three state mode
+ * This parameter can be one of the following values:
+ * @retval the ratation Circle value
+ */
+uint8_t GetSampleMode(void)
+{
+ uint8_t Temp;
+ Temp = (uint8_t)((LPRCNT->CAL2 >> 25) & 0x01);
+ return Temp ;
+}
+/**
+ * @brief LPRCNT module can work in two mode.this is LPRCNT mode and calibration mode .
+ * @param mode: working mode .
+ * This parameter can be one of the following values:
+ * @arg 0: calibration mode , for calibration rotation object parameters
+ * @arg 1: LPRCNT mode, the mode can detect the Circle of rotation
+ * @retval None
+ */
+//void SetLPRCNTWorkMode(uint8_t mode)//å°è£…æˆä¸€ä¸ªå®
+//{
+// LPRCNT->CTRL |= (uint32_t)(mode << 24);
+//}
+
+/**
+ * @brief LPRCNT COMP Init.
+ * @param COMP_InitStruct.
+ * This parameter can be one of the following values:
+ * LPRCNT_COMP_InitType
+ * @retval None
+ */
+void LPRCNT_CompInit(LPRCNT_COMP_InitType* COMP_InitStruct)
+{
+ uint32_t Temp ;
+ Temp = LPRCNT->CAL3;
+ //clear the bits about COMP hysteresis
+ Temp &= (~LPRCNT_CAL3_CMP_HYSEL);
+ Temp |= COMP_InitStruct->Hyst;
+ //clear input minus selection bits
+ Temp &= (~LPRCNT_CAL3_CMP_INMSEL);
+ Temp |= COMP_InitStruct->InmSel;
+ //COMP low power enable
+ Temp |= COMP_InitStruct->LowPoweMode;
+ LPRCNT->CAL3 = Temp;
+}
+
+/**
+ * @brief DigitalfilterConfig.
+* @param cmd:enable or disable.
+* @param filterTh:Filter threshold control.
+ * This parameter can be one of the following values:
+ * CMP_FILTH_MODE0 : T/2~T
+ * CMP_FILTH_MODE1 : T~3T/2
+ * CMP_FILTH_MODE2 : 3T/2~2T
+ * @retval None
+ */
+void CompDigitalFilterCfg(bool Cmd, uint32_t FilterThr)
+{
+ uint32_t Temp ;
+ Temp = LPRCNT->CAL3;
+ //clear FILTH bit
+ Temp &= (~LPRCNT_CAL3_FILTH);
+ Temp |= FilterThr;
+ LPRCNT->CAL3 = Temp;
+ if (Cmd == ENABLE)
+ {
+ LPRCNT->CAL3 |= LPRCNT_CAL3_DIGFILEN;
+ }
+ else
+ {
+ LPRCNT->CAL3 &= (~LPRCNT_CAL3_DIGFILEN);
+ }
+}
+/**
+ * @brief COMPDigitalfilterEnable.
+ * @param cmd:ENABLE or DISABLE.
+ * @retval None
+ */
+void CompAnalogFilterEn(bool Cmd)
+{
+ if (Cmd == ENABLE)
+ {
+ LPRCNT->CAL3 |= LPRCNT_CAL3_ANGFILEN;
+ }
+ else
+ {
+ LPRCNT->CAL3 &= (~LPRCNT_CAL3_ANGFILEN);
+ }
+}
+
+/**
+ * @brief Digital filter phase control.
+ * @param direction:P or N.
+ * @retval None
+ */
+void CompDigitalFilterPhase(bool dir)
+{
+ uint32_t Temp ;
+ Temp = LPRCNT->CAL3;
+ Temp &= (~LPRCNT_CAL3_DIGFILPH);
+ if (dir == POPH)
+ {
+ Temp |= LPRCNT_CAL3_DIGFILPH_P;
+ LPRCNT->CAL3 = Temp;
+ }
+ else
+ {
+ Temp |= LPRCNT_CAL3_DIGFILPH_N;
+ LPRCNT->CAL3 = Temp;
+ }
+}
+
+
+/**
+ * @brief DAC & CMP always on enable while 1 round sampling.
+ * @param NewState:ENABLE or DISABLE.
+ * @retval None
+ */
+void DAC_CMP_ALWSONCmd(FunctionalState NewState)
+{
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected LPRCNT AlwaysON，hardware auto turn on MSI clock */
+ LPRCNT->CAL3 |= LPRCNT_CAL3_DAC_CMP_ALWSON;
+ RCC_EnableMsi(DISABLE);
+ }
+ else
+ {
+ /* Disable the selected LPRCNT stop */
+ LPRCNT->CAL3 &= ~LPRCNT_CAL3_DAC_CMP_ALWSON;
+ }
+}
+/**
+ * @brief LPRCNT analog filter,include gated values and phases.
+ * @param None
+ * @retval None
+ */
+void LPRCNTAnalogFilterConfig(void)
+{
+ SetAnalogFilterTh(1);
+ CompAnalogFilterPhase(POPH);
+ CompAnalogFilterEn(ENABLE);
+}
+/**
+ * @brief LPRCNT module Init.
+ * @param LPRCNT are ready to run .
+ * This parameter can be one of the following values:
+ * @arg 0: LPRCNT_InitStruct , for init rotation object parameters
+ * @retval None
+ */
+void LPRCNTInit(LPRCNT_InitType* LPRCNT_InitStruct)
+{
+ //clock and charge voltage
+ SetMsiClkPrescale(LPRCNT_InitStruct->PrescaleDiv);
+ SetVibrationPower(LPRCNT_InitStruct->ChargeVol);
+ //SetPwrAutoCharge(ENABLE);
+ //DAC_CMP_ALWSONCmd(ENABLE);
+ //sensor time paragram
+ CfgChannelTime(CHANNEL_0,LPRCNT_InitStruct->ChTime[0].vibrationtime,LPRCNT_InitStruct->ChTime[0].dischargetime,LPRCNT_InitStruct->ChTime[0].chargetime);
+ CfgChannelTime(CHANNEL_1,LPRCNT_InitStruct->ChTime[1].vibrationtime,LPRCNT_InitStruct->ChTime[1].dischargetime,LPRCNT_InitStruct->ChTime[1].chargetime);
+ CfgChannelTime(CHANNEL_2,LPRCNT_InitStruct->ChTime[2].vibrationtime,LPRCNT_InitStruct->ChTime[2].dischargetime,LPRCNT_InitStruct->ChTime[2].chargetime);
+ //sensor state paragram
+ CfgChannelThr(CHANNEL_0,LPRCNT_InitStruct->ChTH[0].undampedTh,LPRCNT_InitStruct->ChTH[0].dampedTh);
+ CfgChannelDacRefVol(CHANNEL_0,LPRCNT_InitStruct->ChTH[0].dacreference);
+ CfgChannelThr(CHANNEL_1,LPRCNT_InitStruct->ChTH[1].undampedTh,LPRCNT_InitStruct->ChTH[1].dampedTh);
+ CfgChannelDacRefVol(CHANNEL_1,LPRCNT_InitStruct->ChTH[1].dacreference);
+ CfgChannelThr(CHANNEL_2,LPRCNT_InitStruct->ChTH[2].undampedTh,LPRCNT_InitStruct->ChTH[2].dampedTh);
+ CfgChannelDacRefVol(CHANNEL_2,LPRCNT_InitStruct->ChTH[2].dacreference);
+ SetNormalSensorScanfrequence(LPRCNT_InitStruct->NormalFreq.low_speed,LPRCNT_InitStruct->NormalFreq.hight_speed,LPRCNT_InitStruct->NormalFreq.swtich_time);
+ SetScanAverageValue(0);//default 0
+ //scan period
+ SetNormalSensorScanfrequence(LPRCNT_InitStruct->NormalFreq.low_speed,LPRCNT_InitStruct->NormalFreq.hight_speed,LPRCNT_InitStruct->NormalFreq.swtich_time);
+ SetAlarmSensorScanfrequence(LPRCNT_InitStruct->AlarmFreq);
+ SetAutoDetectPeriod(LPRCNT_InitStruct->AutoWaitPer);
+ SetAutoDetectEnale(LPRCNT_InitStruct->AutoDetEn);
+ //setup time funtion
+ DacSetupTimeConfig();
+ CompSetupTimeConfig();
+ //ChargeAndDischargeGap(5);
+ ClrRcntCircle();
+ SetAutoReportCircle(LPRCNT_InitStruct->Circle);
+ LPRCNTAnalogFilterConfig();//default to select the analog filter
+ SetLPRCNTWorkMode(LPRCNT_InitStruct->WorkMode);
+ //interruput
+ LPRCNT_ClrIntBit(LPRCNT_INTSTS_RPTIF);
+ LPRCNT_IntEn(LPRCNT_InitStruct->Int,LPRCNT_InitStruct->IntEn);
+}
+
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/******************* (C) COPYRIGHT 2019 NATIONZ *****END OF FILE****/
+
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lptim.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lptim.c
new file mode 100644
index 0000000000..8099d65647
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lptim.c
@@ -0,0 +1,1258 @@
+/** ----------------------------------------------------------------------------
+ * Nationz Technology Software Support - NATIONZ -
+ * -----------------------------------------------------------------------------
+ * Copyright (c) 2022, Nationz Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaiimer below.
+ *
+ * - Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the disclaimer below in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * Nationz's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+ * -----------------------------------------------------------------------------
+ */
+
+/** ****************************************************************************
+ * @copyright Nationz Co.,Ltd
+ * Copyright (c) 2019 All Rights Reserved
+ *******************************************************************************
+ * @file n32l43x_lptim.c
+ * @author
+ * @date
+ * @version v1.2.0
+ * @brief
+ ******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "n32l43x_lptim.h"
+#include "n32l43x_rcc.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup LPTIM
+ * @brief LPTIM driver modules
+ * @{
+ */
+
+/** @defgroup LPTIM_Private_TypesDefinitions
+ * @{
+ */
+/**
+ * @}
+ */
+//#define LPTIM
+//#if defined (LPTIM)//LPTIM
+
+/** @defgroup RCC_EC_LPTIM1 Peripheral LPTIM get clock source
+ * @{
+ */
+#define RCC_LPTIM_CLKSOURCE ((uint32_t)0x00000007)/*!< LPTIM1 clock source selection bits */
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup LPTIM_Private_Macros
+ * @{
+ */
+#define IS_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LPTIM_CLK_SOURCE_INTERNAL) \
+ || ((__VALUE__) == LPTIM_CLK_SOURCE_EXTERNAL))
+
+#define IS_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LPTIM_PRESCALER_DIV1) \
+ || ((__VALUE__) == LPTIM_PRESCALER_DIV2) \
+ || ((__VALUE__) == LPTIM_PRESCALER_DIV4) \
+ || ((__VALUE__) == LPTIM_PRESCALER_DIV8) \
+ || ((__VALUE__) == LPTIM_PRESCALER_DIV16) \
+ || ((__VALUE__) == LPTIM_PRESCALER_DIV32) \
+ || ((__VALUE__) == LPTIM_PRESCALER_DIV64) \
+ || ((__VALUE__) == LPTIM_PRESCALER_DIV128))
+
+#define IS_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LPTIM_OUTPUT_WAVEFORM_PWM) \
+ || ((__VALUE__) == LPTIM_OUTPUT_WAVEFORM_SETONCE))
+
+#define IS_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LPTIM_OUTPUT_POLARITY_REGULAR) \
+ || ((__VALUE__) == LPTIM_OUTPUT_POLARITY_INVERSE))
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
+ * @{
+ */
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup LPTIM_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup LPTIM_EF_Init
+ * @{
+ */
+
+/**
+ * @brief Set LPTIMx registers to their reset values.
+ * @param LPTIMx LP Timer instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: LPTIMx registers are de-initialized
+ * - ERROR: invalid LPTIMx instance
+ */
+void LPTIM_DeInit(LPTIM_Module* LPTIMx)
+{
+ if (LPTIMx == LPTIM)
+ {
+ RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LPTIM,ENABLE);
+ RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LPTIM,DISABLE);
+ }
+}
+
+/**
+ * @brief Set each fields of the LPTIM_InitStruct structure to its default
+ * value.
+ * @param LPTIM_InitStruct pointer to a @ref LPTIM_InitType structure
+ * @retval None
+ */
+void LPTIM_StructInit(LPTIM_InitType* LPTIM_InitStruct)
+{
+ /* Set the default configuration */
+ LPTIM_InitStruct->ClockSource = LPTIM_CLK_SOURCE_INTERNAL;
+ LPTIM_InitStruct->Prescaler = LPTIM_PRESCALER_DIV1;
+ LPTIM_InitStruct->Waveform = LPTIM_OUTPUT_WAVEFORM_PWM;
+ LPTIM_InitStruct->Polarity = LPTIM_OUTPUT_POLARITY_REGULAR;
+}
+
+/**
+ * @brief Configure the LPTIMx peripheral according to the specified parameters.
+ * @note LPTIM_Init can only be called when the LPTIM instance is disabled.
+ * @note LPTIMx can be disabled using unitary function @ref LPTIM_Disable().
+ * @param LPTIMx LP Timer Instance
+ * @param LPTIM_InitStruct pointer to a @ref LPTIM_InitType structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: LPTIMx instance has been initialized
+ * - ERROR: LPTIMx instance hasn't been initialized
+ */
+ErrorStatus LPTIM_Init(LPTIM_Module * LPTIMx, LPTIM_InitType* LPTIM_InitStruct)
+{
+ ErrorStatus result = SUCCESS;
+ /* Check the parameters */
+ assert_param(IS_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource));
+ assert_param(IS_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler));
+ assert_param(IS_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform));
+ assert_param(IS_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity));
+
+ /* The LPTIMx_CFG register must only be modified when the LPTIM is disabled
+ (ENABLE bit is reset to 0).
+ */
+ if (LPTIM_IsEnabled(LPTIMx) == 1UL)
+ {
+ result = ERROR;
+ }
+ else
+ {
+ /* Set CKSEL bitfield according to ClockSource value */
+ /* Set PRESC bitfield according to Prescaler value */
+ /* Set WAVE bitfield according to Waveform value */
+ /* Set WAVEPOL bitfield according to Polarity value */
+ MODIFY_REG(LPTIMx->CFG,
+ (LPTIM_CFG_CLKSEL | LPTIM_CFG_CLKPOL | LPTIM_CFG_WAVE| LPTIM_CFG_WAVEPOL),
+ LPTIM_InitStruct->ClockSource | \
+ LPTIM_InitStruct->Prescaler | \
+ LPTIM_InitStruct->Waveform | \
+ LPTIM_InitStruct->Polarity);
+ }
+
+ return result;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @brief Disable the LPTIM instance
+ * @rmtoll CR ENABLE LPTIM_Disable
+ * @param LPTIMx Low-Power Timer instance
+ * @note
+ * @retval None
+ */
+void LPTIM_Disable(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->CTRL, LPTIM_CTRL_LPTIMEN);
+}
+
+/** @defgroup LPTIM_EF_LPTIM_Configuration LPTIM Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable the LPTIM instance
+ * @note After setting the ENABLE bit, a delay of two counter clock is needed
+ * before the LPTIM instance is actually enabled.
+ * @rmtoll CR ENABLE LPTIM_Enable
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_Enable(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->CTRL, LPTIM_CTRL_LPTIMEN);
+}
+
+/**
+ * @brief Indicates whether the LPTIM instance is enabled.
+ * @rmtoll CR ENABLE LPTIM_IsEnabled
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsEnabled(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->CTRL, LPTIM_CTRL_LPTIMEN) == LPTIM_CTRL_LPTIMEN)? 1UL : 0UL));
+}
+
+/**
+ * @brief Starts the LPTIM counter in the desired mode.
+ * @note LPTIM instance must be enabled before starting the counter.
+ * @note It is possible to change on the fly from One Shot mode to
+ * Continuous mode.
+ * @rmtoll CR CNTSTRT LPTIM_StartCounter\n
+ * CR SNGSTRT LPTIM_StartCounter
+ * @param LPTIMx Low-Power Timer instance
+ * @param OperatingMode This parameter can be one of the following values:
+ * @arg @ref LPTIM_OPERATING_MODE_CONTINUOUS
+ * @arg @ref LPTIM_OPERATING_MODE_ONESHOT
+ * @retval None
+ */
+void LPTIM_StartCounter(LPTIM_Module *LPTIMx, uint32_t OperatingMode)
+{
+ MODIFY_REG(LPTIMx->CTRL, LPTIM_CTRL_TSTCM | LPTIM_CTRL_SNGMST, OperatingMode);
+}
+
+/**
+ * @brief Set the LPTIM registers update mode (enable/disable register preload)
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @rmtoll CFG PRELOAD LPTIM_SetUpdateMode
+ * @param LPTIMx Low-Power Timer instance
+ * @param UpdateMode This parameter can be one of the following values:
+ * @arg @ref LPTIM_UPDATE_MODE_IMMEDIATE
+ * @arg @ref LPTIM_UPDATE_MODE_ENDOFPERIOD
+ * @retval None
+ */
+void LPTIM_SetUpdateMode(LPTIM_Module *LPTIMx, uint32_t UpdateMode)
+{
+ MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_RELOAD, UpdateMode);
+}
+
+/**
+ * @brief Get the LPTIM registers update mode
+ * @rmtoll CFG PRELOAD LPTIM_GetUpdateMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_UPDATE_MODE_IMMEDIATE
+ * @arg @ref LPTIM_UPDATE_MODE_ENDOFPERIOD
+ */
+uint32_t LPTIM_GetUpdateMode(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_RELOAD));
+}
+
+/**
+ * @brief Set the auto reload value
+ * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
+ * @note After a write to the LPTIMx_ARR register a new write operation to the
+ * same register can only be performed when the previous write operation
+ * is completed. Any successive write before the ARROK flag be set, will
+ * lead to unpredictable results.
+ * @note autoreload value be strictly greater than the compare value.
+ * @rmtoll ARR ARR LPTIM_SetAutoReload
+ * @param LPTIMx Low-Power Timer instance
+ * @param AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
+ * @retval None
+ */
+void LPTIM_SetAutoReload(LPTIM_Module *LPTIMx, uint32_t AutoReload)
+{
+ MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARRVAL, AutoReload);
+}
+
+/**
+ * @brief Get actual auto reload value
+ * @rmtoll ARR ARR LPTIM_GetAutoReload
+ * @param LPTIMx Low-Power Timer instance
+ * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+uint32_t LPTIM_GetAutoReload(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARRVAL));
+}
+
+/**
+ * @brief Set the compare value
+ * @note After a write to the LPTIMx_CMP register a new write operation to the
+ * same register can only be performed when the previous write operation
+ * is completed. Any successive write before the CMPOK flag be set, will
+ * lead to unpredictable results.
+ * @rmtoll CMP CMP LPTIM_SetCompare
+ * @param LPTIMx Low-Power Timer instance
+ * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
+ * @retval None
+ */
+void LPTIM_SetCompare(LPTIM_Module *LPTIMx, uint32_t CompareValue)
+{
+ MODIFY_REG(LPTIMx->COMPx, LPTIM_COMP_CMPVAL, CompareValue);
+}
+
+/**
+ * @brief Get actual compare value
+ * @rmtoll CMP CMP LPTIM_GetCompare
+ * @param LPTIMx Low-Power Timer instance
+ * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+uint32_t LPTIM_GetCompare(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->COMPx, LPTIM_COMP_CMPVAL));
+}
+
+/**
+ * @brief Get actual counter value
+ * @note When the LPTIM instance is running with an asynchronous clock, reading
+ * the LPTIMx_CNT register may return unreliable values. So in this case
+ * it is necessary to perform two consecutive read accesses and verify
+ * that the two returned values are identical.
+ * @rmtoll CNT CNT LPTIM_GetCounter
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Counter value
+ */
+uint32_t LPTIM_GetCounter(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNTVAL));
+}
+
+/**
+ * @brief Set the counter mode (selection of the LPTIM counter clock source).
+ * @note The counter mode can be set only when the LPTIM instance is disabled.
+ * @rmtoll CFG COUNTMODE LPTIM_SetCounterMode
+ * @param LPTIMx Low-Power Timer instance
+ * @param CounterMode This parameter can be one of the following values:
+ * @arg @ref LPTIM_COUNTER_MODE_INTERNAL
+ * @arg @ref LPTIM_COUNTER_MODE_EXTERNAL
+ * @retval None
+ */
+void LPTIM_SetCounterMode(LPTIM_Module *LPTIMx, uint32_t CounterMode)
+{
+ MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CNTMEN, CounterMode);
+}
+
+/**
+ * @brief Get the counter mode
+ * @rmtoll CFG COUNTMODE LPTIM_GetCounterMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_COUNTER_MODE_INTERNAL
+ * @arg @ref LPTIM_COUNTER_MODE_EXTERNAL
+ */
+uint32_t LPTIM_GetCounterMode(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CNTMEN));
+}
+
+/**
+ * @brief Configure the LPTIM instance output (LPTIMx_OUT)
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note Regarding the LPTIM output polarity the change takes effect
+ * immediately, so the output default value will change immediately after
+ * the polarity is re-configured, even before the timer is enabled.
+ * @rmtoll CFG WAVE LPTIM_ConfigOutput\n
+ * CFG WAVPOL LPTIM_ConfigOutput
+ * @param LPTIMx Low-Power Timer instance
+ * @param Waveform This parameter can be one of the following values:
+ * @arg @ref LPTIM_OUTPUT_WAVEFORM_PWM
+ * @arg @ref LPTIM_OUTPUT_WAVEFORM_SETONCE
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LPTIM_OUTPUT_POLARITY_REGULAR
+ * @arg @ref LPTIM_OUTPUT_POLARITY_INVERSE
+ * @retval None
+ */
+void LPTIM_ConfigOutput(LPTIM_Module *LPTIMx, uint32_t Waveform, uint32_t Polarity)
+{
+ MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_WAVE | LPTIM_CFG_WAVEPOL, Waveform | Polarity);
+}
+
+/**
+ * @brief Set waveform shape
+ * @rmtoll CFG WAVE LPTIM_SetWaveform
+ * @param LPTIMx Low-Power Timer instance
+ * @param Waveform This parameter can be one of the following values:
+ * @arg @ref LPTIM_OUTPUT_WAVEFORM_PWM
+ * @arg @ref LPTIM_OUTPUT_WAVEFORM_SETONCE
+ * @retval None
+ */
+void LPTIM_SetWaveform(LPTIM_Module *LPTIMx, uint32_t Waveform)
+{
+ MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_WAVE, Waveform);
+}
+
+/**
+ * @brief Get actual waveform shape
+ * @rmtoll CFG WAVE LPTIM_GetWaveform
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_OUTPUT_WAVEFORM_PWM
+ * @arg @ref LPTIM_OUTPUT_WAVEFORM_SETONCE
+ */
+uint32_t LPTIM_GetWaveform(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_WAVE));
+}
+
+/**
+ * @brief Set output polarity
+ * @rmtoll CFG WAVPOL LPTIM_SetPolarity
+ * @param LPTIMx Low-Power Timer instance
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LPTIM_OUTPUT_POLARITY_REGULAR
+ * @arg @ref LPTIM_OUTPUT_POLARITY_INVERSE
+ * @retval None
+ */
+void LPTIM_SetPolarity(LPTIM_Module *LPTIMx, uint32_t Polarity)
+{
+ MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_WAVEPOL, Polarity);
+}
+
+/**
+ * @brief Get actual output polarity
+ * @rmtoll CFG WAVPOL LPTIM_GetPolarity
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_OUTPUT_POLARITY_REGULAR
+ * @arg @ref LPTIM_OUTPUT_POLARITY_INVERSE
+ */
+uint32_t LPTIM_GetPolarity(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_WAVEPOL));
+}
+
+/**
+ * @brief Set actual prescaler division ratio.
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note When the LPTIM is configured to be clocked by an internal clock source
+ * and the LPTIM counter is configured to be updated by active edges
+ * detected on the LPTIM external Input1, the internal clock provided to
+ * the LPTIM must be not be prescaled.
+ * @rmtoll CFG PRESC LPTIM_SetPrescaler
+ * @param LPTIMx Low-Power Timer instance
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LPTIM_PRESCALER_DIV1
+ * @arg @ref LPTIM_PRESCALER_DIV2
+ * @arg @ref LPTIM_PRESCALER_DIV4
+ * @arg @ref LPTIM_PRESCALER_DIV8
+ * @arg @ref LPTIM_PRESCALER_DIV16
+ * @arg @ref LPTIM_PRESCALER_DIV32
+ * @arg @ref LPTIM_PRESCALER_DIV64
+ * @arg @ref LPTIM_PRESCALER_DIV128
+ * @retval None
+ */
+void LPTIM_SetPrescaler(LPTIM_Module *LPTIMx, uint32_t Prescaler)
+{
+ MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKPRE, Prescaler);
+}
+
+/**
+ * @brief Get actual prescaler division ratio.
+ * @rmtoll CFG PRESC LPTIM_GetPrescaler
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_PRESCALER_DIV1
+ * @arg @ref LPTIM_PRESCALER_DIV2
+ * @arg @ref LPTIM_PRESCALER_DIV4
+ * @arg @ref LPTIM_PRESCALER_DIV8
+ * @arg @ref LPTIM_PRESCALER_DIV16
+ * @arg @ref LPTIM_PRESCALER_DIV32
+ * @arg @ref LPTIM_PRESCALER_DIV64
+ * @arg @ref LPTIM_PRESCALER_DIV128
+ */
+uint32_t LPTIM_GetPrescaler(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKPRE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_EF_Trigger_Configuration Trigger Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable the timeout function
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note The first trigger event will start the timer, any successive trigger
+ * event will reset the counter and the timer will restart.
+ * @note The timeout value corresponds to the compare value; if no trigger
+ * occurs within the expected time frame, the MCU is waked-up by the
+ * compare match event.
+ * @rmtoll CFG TIMOUT LPTIM_EnableTimeout
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_EnableTimeout(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->CFG, LPTIM_CFG_TIMOUTEN);
+}
+
+/**
+ * @brief Disable the timeout function
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note A trigger event arriving when the timer is already started will be
+ * ignored.
+ * @rmtoll CFG TIMOUT LPTIM_DisableTimeout
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_DisableTimeout(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->CFG, LPTIM_CFG_TIMOUTEN);
+}
+
+/**
+ * @brief Indicate whether the timeout function is enabled.
+ * @rmtoll CFG TIMOUT LPTIM_IsEnabledTimeout
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsEnabledTimeout(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->CFG, LPTIM_CFG_TIMOUTEN) == LPTIM_CFG_TIMOUTEN)? 1UL : 0UL));
+}
+
+/**
+ * @brief Start the LPTIM counter
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @rmtoll CFG TRIGEN LPTIM_TrigSw
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_TrigSw(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->CFG, LPTIM_CFG_TRGEN);
+}
+
+/**
+ * @brief Configure the external trigger used as a trigger event for the LPTIM.
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note An internal clock source must be present when a digital filter is
+ * required for the trigger.
+ * @rmtoll CFG TRIGSEL LPTIM_ConfigTrigger\n
+ * CFG TRGFLT LPTIM_ConfigTrigger\n
+ * CFG TRIGEN LPTIM_ConfigTrigger
+ * @param LPTIMx Low-Power Timer instance
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LPTIM_TRIG_SOURCE_GPIO
+ * @arg @ref LPTIM_TRIG_SOURCE_RTCALARMA
+ * @arg @ref LPTIM_TRIG_SOURCE_RTCALARMB
+ * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP1 (*)
+ * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP2
+ * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP3 (*)
+ * @arg @ref LPTIM_TRIG_SOURCE_COMP1
+ * @arg @ref LPTIM_TRIG_SOURCE_COMP2
+ *
+ * (*) Value not defined in all devices. \n
+ *
+ * @param Filter This parameter can be one of the following values:
+ * @arg @ref LPTIM_TRIG_FILTER_NONE
+ * @arg @ref LPTIM_TRIG_FILTER_2
+ * @arg @ref LPTIM_TRIG_FILTER_4
+ * @arg @ref LPTIM_TRIG_FILTER_8
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LPTIM_TRIG_POLARITY_RISING
+ * @arg @ref LPTIM_TRIG_POLARITY_FALLING
+ * @arg @ref LPTIM_TRIG_POLARITY_RISING_FALLING
+ * @retval None
+ */
+void LPTIM_ConfigTrigger(LPTIM_Module *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
+{
+ MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_TRGSEL | LPTIM_CFG_TRIGFLT | LPTIM_CFG_TRGEN, Source | Filter | Polarity);
+}
+
+/**
+ * @brief Get actual external trigger source.
+ * @rmtoll CFG TRIGSEL LPTIM_GetTriggerSource
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_TRIG_SOURCE_GPIO
+ * @arg @ref LPTIM_TRIG_SOURCE_RTCALARMA
+ * @arg @ref LPTIM_TRIG_SOURCE_RTCALARMB
+ * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP1 (*)
+ * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP2
+ * @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP3 (*)
+ * @arg @ref LPTIM_TRIG_SOURCE_COMP1
+ * @arg @ref LPTIM_TRIG_SOURCE_COMP2
+ *
+ * (*) Value not defined in all devices. \n
+ *
+ */
+uint32_t LPTIM_GetTriggerSource(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_TRGSEL));
+}
+
+/**
+ * @brief Get actual external trigger filter.
+ * @rmtoll CFG TRGFLT LPTIM_GetTriggerFilter
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_TRIG_FILTER_NONE
+ * @arg @ref LPTIM_TRIG_FILTER_2
+ * @arg @ref LPTIM_TRIG_FILTER_4
+ * @arg @ref LPTIM_TRIG_FILTER_8
+ */
+uint32_t LPTIM_GetTriggerFilter(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_TRIGFLT));
+}
+
+/**
+ * @brief Get actual external trigger polarity.
+ * @rmtoll CFG TRIGEN LPTIM_GetTriggerPolarity
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_TRIG_POLARITY_RISING
+ * @arg @ref LPTIM_TRIG_POLARITY_FALLING
+ * @arg @ref LPTIM_TRIG_POLARITY_RISING_FALLING
+ */
+uint32_t LPTIM_GetTriggerPolarity(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_TRGEN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_EF_Clock_Configuration Clock Configuration
+ * @{
+ */
+
+/**
+ * @brief Set the source of the clock used by the LPTIM instance.
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @rmtoll CFG CKSEL LPTIM_SetClockSource
+ * @param LPTIMx Low-Power Timer instance
+ * @param ClockSource This parameter can be one of the following values:
+ * @arg @ref LPTIM_CLK_SOURCE_INTERNAL
+ * @arg @ref LPTIM_CLK_SOURCE_EXTERNAL
+ * @retval None
+ */
+void LPTIM_SetClockSource(LPTIM_Module *LPTIMx, uint32_t ClockSource)
+{
+ MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKSEL, ClockSource);
+}
+
+/**
+ * @brief Get actual LPTIM instance clock source.
+ * @rmtoll CFG CKSEL LPTIM_GetClockSource
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_CLK_SOURCE_INTERNAL
+ * @arg @ref LPTIM_CLK_SOURCE_EXTERNAL
+ */
+uint32_t LPTIM_GetClockSource(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKSEL));
+}
+
+/**
+ * @brief Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note When both external clock signal edges are considered active ones,
+ * the LPTIM must also be clocked by an internal clock source with a
+ * frequency equal to at least four times the external clock frequency.
+ * @note An internal clock source must be present when a digital filter is
+ * required for external clock.
+ * @rmtoll CFG CKFLT LPTIM_ConfigClock\n
+ * CFG CKPOL LPTIM_ConfigClock
+ * @param LPTIMx Low-Power Timer instance
+ * @param ClockFilter This parameter can be one of the following values:
+ * @arg @ref LPTIM_CLK_FILTER_NONE
+ * @arg @ref LPTIM_CLK_FILTER_2
+ * @arg @ref LPTIM_CLK_FILTER_4
+ * @arg @ref LPTIM_CLK_FILTER_8
+ * @param ClockPolarity This parameter can be one of the following values:
+ * @arg @ref LPTIM_CLK_POLARITY_RISING
+ * @arg @ref LPTIM_CLK_POLARITY_FALLING
+ * @arg @ref LPTIM_CLK_POLARITY_RISING_FALLING
+ * @retval None
+ */
+void LPTIM_ConfigClock(LPTIM_Module *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
+{
+ MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKFLT | LPTIM_CFG_CLKPOL, ClockFilter | ClockPolarity);
+}
+
+/**
+ * @brief Get actual clock polarity
+ * @rmtoll CFG CKPOL LPTIM_GetClockPolarity
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_CLK_POLARITY_RISING
+ * @arg @ref LPTIM_CLK_POLARITY_FALLING
+ * @arg @ref LPTIM_CLK_POLARITY_RISING_FALLING
+ */
+uint32_t LPTIM_GetClockPolarity(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKPOL));
+}
+
+/**
+ * @brief Get actual clock digital filter
+ * @rmtoll CFG CKFLT LPTIM_GetClockFilter
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_CLK_FILTER_NONE
+ * @arg @ref LPTIM_CLK_FILTER_2
+ * @arg @ref LPTIM_CLK_FILTER_4
+ * @arg @ref LPTIM_CLK_FILTER_8
+ */
+uint32_t LPTIM_GetClockFilter(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKFLT));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_EF_Encoder_Mode Encoder Mode
+ * @{
+ */
+
+/**
+ * @brief Configure the encoder mode.
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @rmtoll CFG CKPOL LPTIM_SetEncoderMode
+ * @param LPTIMx Low-Power Timer instance
+ * @param EncoderMode This parameter can be one of the following values:
+ * @arg @ref LPTIM_ENCODER_MODE_RISING
+ * @arg @ref LPTIM_ENCODER_MODE_FALLING
+ * @arg @ref LPTIM_ENCODER_MODE_RISING_FALLING
+ * @retval None
+ */
+void LPTIM_SetEncoderMode(LPTIM_Module *LPTIMx, uint32_t EncoderMode)
+{
+ MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKPOL, EncoderMode);
+}
+
+/**
+ * @brief Get actual encoder mode.
+ * @rmtoll CFG CKPOL LPTIM_GetEncoderMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LPTIM_ENCODER_MODE_RISING
+ * @arg @ref LPTIM_ENCODER_MODE_FALLING
+ * @arg @ref LPTIM_ENCODER_MODE_RISING_FALLING
+ */
+uint32_t LPTIM_GetEncoderMode(LPTIM_Module *LPTIMx)
+{
+ return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKPOL));
+}
+
+/**
+ * @brief Enable the encoder mode
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note In this mode the LPTIM instance must be clocked by an internal clock
+ * source. Also, the prescaler division ratio must be equal to 1.
+ * @note LPTIM instance must be configured in continuous mode prior enabling
+ * the encoder mode.
+ * @rmtoll CFG ENC LPTIM_EnableEncoderMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_EnableEncoderMode(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->CFG, LPTIM_CFG_ENC);
+}
+/**
+ * @brief Enable the encoder mode
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @note In this mode the LPTIM instance must be clocked by an internal clock
+ * source. Also, the prescaler division ratio must be equal to 1.
+ * @note LPTIM instance must be configured in continuous mode prior enabling
+ * the encoder mode.
+ * @rmtoll CFG ENC LPTIM_EnableEncoderMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_EnableNoEncoderMode(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->CFG, LPTIM_CFG_NENC);
+}
+/**
+ * @brief Disable the encoder mode
+ * @note This function must be called when the LPTIM instance is disabled.
+ * @rmtoll CFG ENC LPTIM_DisableEncoderMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_DisableEncoderMode(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->CFG, LPTIM_CFG_ENC);
+}
+
+/**
+ * @brief Indicates whether the LPTIM operates in encoder mode.
+ * @rmtoll CFG ENC LPTIM_IsEnabledEncoderMode
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsEnabledEncoderMode(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->CFG, LPTIM_CFG_ENC) == LPTIM_CFG_ENC)? 1UL : 0UL));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_EF_FLAG_Management FLAG Management
+ * @{
+ */
+
+/**
+ * @brief Clear the compare match flag (CMPMCF)
+ * @rmtoll ICR CMPMCF LPTIM_ClearFLAG_CMPM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_ClearFLAG_CMPM(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_CMPMCF);
+}
+
+/**
+ * @brief Inform application whether a compare match interrupt has occurred.
+ * @rmtoll ISR CMPM LPTIM_IsActiveFlag_CMPM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsActiveFlag_CMPM(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_CMPM) ==LPTIM_INTSTS_CMPM)? 1UL : 0UL));
+}
+
+/**
+ * @brief Clear the autoreload match flag (ARRMCF)
+ * @rmtoll ICR ARRMCF LPTIM_ClearFLAG_ARRM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_ClearFLAG_ARRM(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_ARRMCF);
+}
+
+/**
+ * @brief Inform application whether a autoreload match interrupt has occured.
+ * @rmtoll ISR ARRM LPTIM_IsActiveFlag_ARRM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsActiveFlag_ARRM(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_ARRM) ==LPTIM_INTSTS_ARRM)? 1UL : 0UL));
+}
+
+/**
+ * @brief Clear the external trigger valid edge flag(EXTTRIGCF).
+ * @rmtoll ICR EXTTRIGCF LPTIM_ClearFlag_EXTTRIG
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_ClearFlag_EXTTRIG(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_EXTRIGCF);
+}
+
+/**
+ * @brief Inform application whether a valid edge on the selected external trigger input has occurred.
+ * @rmtoll ISR EXTTRIG LPTIM_IsActiveFlag_EXTTRIG
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsActiveFlag_EXTTRIG(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_EXTRIG) ==LPTIM_INTSTS_EXTRIG)? 1UL : 0UL));
+}
+
+/**
+ * @brief Clear the compare register update interrupt flag (CMPOKCF).
+ * @rmtoll ICR CMPOKCF LPTIM_ClearFlag_CMPOK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_ClearFlag_CMPOK(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_CMPUPDCF);
+}
+
+/**
+ * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed. If so, a new one can be initiated.
+ * @rmtoll ISR CMPOK LPTIM_IsActiveFlag_CMPOK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsActiveFlag_CMPOK(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_CMPUPD) ==LPTIM_INTSTS_CMPUPD)? 1UL : 0UL));
+}
+
+/**
+ * @brief Clear the autoreload register update interrupt flag (ARROKCF).
+ * @rmtoll ICR ARROKCF LPTIM_ClearFlag_ARROK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_ClearFlag_ARROK(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_ARRUPDCF);
+}
+
+/**
+ * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed. If so, a new one can be initiated.
+ * @rmtoll ISR ARROK LPTIM_IsActiveFlag_ARROK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsActiveFlag_ARROK(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_ARRUPD) ==LPTIM_INTSTS_ARRUPD)? 1UL : 0UL));
+}
+
+/**
+ * @brief Clear the counter direction change to up interrupt flag (UPCF).
+ * @rmtoll ICR UPCF LPTIM_ClearFlag_UP
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_ClearFlag_UP(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_UPCF);
+}
+
+/**
+ * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).
+ * @rmtoll ISR UP LPTIM_IsActiveFlag_UP
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsActiveFlag_UP(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTSTS, LPTIM_INTSTS_UP) == LPTIM_INTSTS_UP)? 1UL : 0UL));
+}
+
+/**
+ * @brief Clear the counter direction change to down interrupt flag (DOWNCF).
+ * @rmtoll ICR DOWNCF LPTIM_ClearFlag_DOWN
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_ClearFlag_DOWN(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_DOWNCF);
+}
+
+/**
+ * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).
+ * @rmtoll ISR DOWN LPTIM_IsActiveFlag_DOWN
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsActiveFlag_DOWN(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_DOWN) ==LPTIM_INTSTS_DOWN)? 1UL : 0UL));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup LPTIM_EF_IT_Management Interrupt Management
+ * @{
+ */
+
+/**
+ * @brief Enable compare match interrupt (CMPMIE).
+ * @rmtoll IER CMPMIE LPTIM_EnableIT_CMPM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_EnableIT_CMPM(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPMIE);
+}
+
+/**
+ * @brief Disable compare match interrupt (CMPMIE).
+ * @rmtoll IER CMPMIE LPTIM_DisableIT_CMPM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_DisableIT_CMPM(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPMIE);
+}
+
+/**
+ * @brief Indicates whether the compare match interrupt (CMPMIE) is enabled.
+ * @rmtoll IER CMPMIE LPTIM_IsEnabledIT_CMPM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsEnabledIT_CMPM(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPMIE) == LPTIM_INTEN_CMPMIE)? 1UL : 0UL));
+}
+
+/**
+ * @brief Enable autoreload match interrupt (ARRMIE).
+ * @rmtoll IER ARRMIE LPTIM_EnableIT_ARRM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_EnableIT_ARRM(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRMIE);
+}
+
+/**
+ * @brief Disable autoreload match interrupt (ARRMIE).
+ * @rmtoll IER ARRMIE LPTIM_DisableIT_ARRM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_DisableIT_ARRM(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRMIE);
+}
+
+/**
+ * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
+ * @rmtoll IER ARRMIE LPTIM_IsEnabledIT_ARRM
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsEnabledIT_ARRM(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRMIE) == LPTIM_INTEN_ARRMIE)? 1UL : 0UL));
+}
+
+/**
+ * @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
+ * @rmtoll IER EXTTRIGIE LPTIM_EnableIT_EXTTRIG
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_EnableIT_EXTTRIG(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_EXTRIGIE);
+}
+
+/**
+ * @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
+ * @rmtoll IER EXTTRIGIE LPTIM_DisableIT_EXTTRIG
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_DisableIT_EXTTRIG(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_EXTRIGIE);
+}
+
+/**
+ * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
+ * @rmtoll IER EXTTRIGIE LPTIM_IsEnabledIT_EXTTRIG
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsEnabledIT_EXTTRIG(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_EXTRIGIE) == LPTIM_INTEN_EXTRIGIE)? 1UL : 0UL));
+}
+
+/**
+ * @brief Enable compare register write completed interrupt (CMPOKIE).
+ * @rmtoll IER CMPOKIE LPTIM_EnableIT_CMPOK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_EnableIT_CMPOK(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPUPDIE);
+}
+
+/**
+ * @brief Disable compare register write completed interrupt (CMPOKIE).
+ * @rmtoll IER CMPOKIE LPTIM_DisableIT_CMPOK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_DisableIT_CMPOK(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPUPDIE);
+}
+
+/**
+ * @brief Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
+ * @rmtoll IER CMPOKIE LPTIM_IsEnabledIT_CMPOK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsEnabledIT_CMPOK(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPUPDIE) == LPTIM_INTEN_CMPUPDIE)? 1UL : 0UL));
+}
+
+/**
+ * @brief Enable autoreload register write completed interrupt (ARROKIE).
+ * @rmtoll IER ARROKIE LPTIM_EnableIT_ARROK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_EnableIT_ARROK(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRUPDIE);
+}
+
+/**
+ * @brief Disable autoreload register write completed interrupt (ARROKIE).
+ * @rmtoll IER ARROKIE LPTIM_DisableIT_ARROK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_DisableIT_ARROK(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRUPDIE);
+}
+
+/**
+ * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
+ * @rmtoll IER ARROKIE LPTIM_IsEnabledIT_ARROK
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsEnabledIT_ARROK(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRUPDIE) == LPTIM_INTEN_ARRUPDIE)? 1UL : 0UL));
+}
+
+/**
+ * @brief Enable direction change to up interrupt (UPIE).
+ * @rmtoll IER UPIE LPTIM_EnableIT_UP
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_EnableIT_UP(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_UPIE);
+}
+
+/**
+ * @brief Disable direction change to up interrupt (UPIE).
+ * @rmtoll IER UPIE LPTIM_DisableIT_UP
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_DisableIT_UP(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_UPIE);
+}
+
+/**
+ * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
+ * @rmtoll IER UPIE LPTIM_IsEnabledIT_UP
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsEnabledIT_UP(LPTIM_Module *LPTIMx)
+{
+ return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_UPIE) == LPTIM_INTEN_UPIE)? 1UL : 0UL));
+}
+
+/**
+ * @brief Enable direction change to down interrupt (DOWNIE).
+ * @rmtoll IER DOWNIE LPTIM_EnableIT_DOWN
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_EnableIT_DOWN(LPTIM_Module *LPTIMx)
+{
+ SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_DOWNIE);
+}
+
+/**
+ * @brief Disable direction change to down interrupt (DOWNIE).
+ * @rmtoll IER DOWNIE LPTIM_DisableIT_DOWN
+ * @param LPTIMx Low-Power Timer instance
+ * @retval None
+ */
+void LPTIM_DisableIT_DOWN(LPTIM_Module *LPTIMx)
+{
+ CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_DOWNIE);
+}
+
+/**
+ * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
+ * @rmtoll IER DOWNIE LPTIM_IsEnabledIT_DOWN
+ * @param LPTIMx Low-Power Timer instance
+ * @retval State of bit (1 or 0).
+ */
+uint32_t LPTIM_IsEnabledIT_DOWN(LPTIM_Module *LPTIMx)
+{
+ return ((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_DOWNIE) == LPTIM_INTEN_DOWNIE)? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+
+//#endif /* LPTIM */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/******************* (C) COPYRIGHT 2019 NATIONZ *****END OF FILE****/
+
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lpuart.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lpuart.c
new file mode 100644
index 0000000000..d99dc7b97a
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lpuart.c
@@ -0,0 +1,532 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_lpuart.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l43x_lpuart.h"
+#include "n32l43x_rcc.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup LPUART
+ * @brief LPUART driver modules
+ * @{
+ */
+
+/** @addtogroup LPUART_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Private_Defines
+ * @{
+ */
+
+#define STS_CLR_MASK ((uint16_t)0x01BF) /*!< LPUART STS Mask */
+
+#define INTEN_CLR_MASK ((uint16_t)0x0000) /*!< LPUART INTEN Mask */
+#define INT_MASK ((uint16_t)0x007F) /*!< LPUART Interrupt Mask */
+
+#define CTRL_CLR_MASK ((uint16_t)0x70F4) /*!< LPUART CTRL Mask */
+#define CTRL_SMPCNT_MASK ((uint16_t)0x3FFF) /*!< LPUART Sampling Method Mask */
+#define CTRL_WUSTP_MASK ((uint16_t)0x4FFF) /*!< LPUART WakeUp Method Mask */
+#define CTRL_WUSTP_SET ((uint16_t)0x0080) /*!< LPUART stop mode Enable Mask */
+#define CTRL_WUSTP_RESET ((uint16_t)0x7F7F) /*!< LPUART stop mode Disable Mask */
+#define CTRL_LOOPBACK_SET ((uint16_t)0x0010) /*!< LPUART Loopback Test Enable Mask */
+#define CTRL_LOOPBACK_RESET ((uint16_t)0xFFEF) /*!< LPUART Loopback Test Disable Mask */
+#define CTRL_FLUSH_SET ((uint16_t)0x0004) /*!< LPUART Flush Receiver FIFO Enable Mask */
+#define CTRL_FLUSH_RESET ((uint16_t)0x7FFB) /*!< LPUART Flush Receiver FIFO Disable Mask */
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the LPUART peripheral registers to their default reset values.
+ */
+void LPUART_DeInit(void)
+{
+ RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LPUART, ENABLE);
+ RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LPUART, DISABLE);
+}
+
+/**
+ * @brief Initializes the LPUART peripheral according to the specified
+ * parameters in the LPUART_InitStruct.
+ * @param LPUART_InitStruct pointer to a LPUART_InitType structure
+ * that contains the configuration information for the specified LPUART
+ * peripheral.
+ */
+void LPUART_Init(LPUART_InitType* LPUART_InitStruct)
+{
+ uint32_t tmpregister = 0x00, clocksrc = 0x00, apbclock = 0x00;
+ uint32_t integerdivider = 0x00;
+ uint32_t fractionaldivider = 0x00;
+ uint32_t tmpdivider = 0x00, lastdivider = 0x00, i = 0x00;
+ RCC_ClocksType RCC_ClocksStatus;
+
+ /* Check the parameters */
+ // assert_param(IS_LPUART_BAUDRATE(LPUART_InitStruct->BaudRate));
+ assert_param(IS_LPUART_PARITY(LPUART_InitStruct->Parity));
+ assert_param(IS_LPUART_MODE(LPUART_InitStruct->Mode));
+ assert_param(IS_LPUART_RTSTHRESHOLD(LPUART_InitStruct->RtsThreshold));
+ assert_param(IS_LPUART_HARDWARE_FLOW_CONTROL(LPUART_InitStruct->HardwareFlowControl));
+
+ // 时钟æºåˆ¤æ–，波特率范围
+
+ /*---------------------------- LPUART CTRL Configuration -----------------------*/
+ tmpregister = LPUART->CTRL;
+ /* Clear FC_RXEN, FC_TXEN, RTS_THSEL[1:0], PCDIS, TRS and PSEL bits */
+ tmpregister &= CTRL_CLR_MASK;
+ /* Configure the LPUART Parity, Mode, RtsThrehold and HardwareFlowControl ----------------------- */
+ /* Set PCDIS and PSEL bits according to Parity value */
+ /* Set the TRS bit according to Mode */
+ /* Set RTS_THSEL[1:0] bits according to RtsThrehold */
+ /* Set FC_RXEN and FC_TXEN bits according to HardwareFlowControl */
+ tmpregister |= (uint32_t)LPUART_InitStruct->Parity | LPUART_InitStruct->Mode | LPUART_InitStruct->RtsThreshold | LPUART_InitStruct->HardwareFlowControl;
+ /* Write to LPUART CTRL */
+ LPUART->CTRL = (uint16_t)tmpregister;
+
+ /*---------------------------- LPUART BRCFG1 & 2 Configuration -----------------------*/
+ /* Configure the LPUART Baud Rate -------------------------------------------*/
+ clocksrc = RCC_GetLPUARTClkSrc();
+ if (clocksrc == RCC_LPUARTCLK_SRC_LSE)
+ {
+ apbclock = 0x8000; // 32.768kHz
+ }
+ else if (clocksrc == RCC_LPUARTCLK_SRC_HSI)
+ {
+ apbclock = 0xF42400; // 16MHz
+ }
+ else if (clocksrc == RCC_LPUARTCLK_SRC_SYSCLK)
+ {
+ RCC_GetClocksFreqValue(&RCC_ClocksStatus);
+ apbclock = RCC_ClocksStatus.SysclkFreq;
+ }
+ else //(clocksrc ==RCC_LPUARTCLK_SRC_APB1)
+ {
+ RCC_GetClocksFreqValue(&RCC_ClocksStatus);
+ apbclock = RCC_ClocksStatus.Pclk1Freq;
+ }
+
+ /* Determine the integer part */
+ integerdivider = apbclock / (LPUART_InitStruct->BaudRate);
+
+ /* Configure sampling method */
+ if (integerdivider <= 10)
+ {
+ LPUART_ConfigSamplingMethod(LPUART_SMPCNT_1B);
+ }
+ else
+ {
+ LPUART_ConfigSamplingMethod(LPUART_SMPCNT_3B);
+ }
+
+ /* Check baudrate */
+ assert_param(IS_LPUART_BAUDRATE(integerdivider));
+ /* Write to LPUART BRCFG1 */
+ LPUART->BRCFG1 = (uint16_t)integerdivider;
+
+ /* Determine the fractional part */
+ fractionaldivider = ((apbclock % (LPUART_InitStruct->BaudRate)) * 10000) / (LPUART_InitStruct->BaudRate);
+
+ tmpregister = 0x00;
+ tmpdivider = fractionaldivider;
+ /* Implement the fractional part in the register */
+ for( i = 0; i < 8; i++)
+ {
+ lastdivider = tmpdivider;
+ tmpdivider = lastdivider + fractionaldivider;
+ if ((tmpdivider / 10000) ^ (lastdivider / 10000))
+ {
+ tmpregister |= (0x01 << i);
+ }
+ }
+ /* Write to LPUART BRCFG2 */
+ LPUART->BRCFG2 = (uint8_t)tmpregister;
+}
+
+/**
+ * @brief Fills each LPUART_InitStruct member with its default value.
+ * @param LPUART_InitStruct pointer to a LPUART_InitType structure
+ * which will be initialized.
+ */
+void LPUART_StructInit(LPUART_InitType* LPUART_InitStruct)
+{
+ /* LPUART_InitStruct members default value */
+ LPUART_InitStruct->BaudRate = 9600;
+ LPUART_InitStruct->Parity = LPUART_PE_NO;
+ LPUART_InitStruct->Mode = LPUART_MODE_RX | LPUART_MODE_TX;
+ LPUART_InitStruct->RtsThreshold = LPUART_RTSTH_FIFOFU;
+ LPUART_InitStruct->HardwareFlowControl = LPUART_HFCTRL_NONE;
+}
+
+/**
+ * @brief Flushes Receiver FIFO.
+ */
+void LPUART_FlushRxFifo(void)
+{
+ /* Clear LPUART Flush Receiver FIFO */
+ LPUART->CTRL |= CTRL_FLUSH_SET;
+ while (LPUART_GetFlagStatus(LPUART_FLAG_FIFO_NE) != RESET)
+ {
+ }
+ LPUART->CTRL &= CTRL_FLUSH_RESET;
+}
+
+/**
+ * @brief Enables or disables the specified LPUART interrupts.
+ * @param LPUART_INT specifies the LPUART interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg LPUART_INT_WUF Wake-Up Interrupt
+ * @arg LPUART_INT_FIFO_NE FIFO Non-Empty Interrupt
+ * @arg LPUART_INT_FIFO_HF FIFO Half Full Interrupt
+ * @arg LPUART_INT_FIFO_FU FIFO Full Interrupt Enable
+ * @arg LPUART_INT_FIFO_OV FIFO Overflow Interrupt
+ * @arg LPUART_INT_TXC TX Complete Interrupt
+ * @arg LPUART_INT_PE Parity Check Error Interrupt
+ * @param Cmd new state of the specified LPUART interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void LPUART_ConfigInt(uint16_t LPUART_INT, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_LPUART_CFG_INT(LPUART_INT));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ LPUART->INTEN |= (uint8_t)LPUART_INT;
+ }
+ else
+ {
+ LPUART->INTEN &= (uint8_t)(~LPUART_INT);
+ }
+}
+
+/**
+ * @brief Enables or disables the LPUART's DMA interface.
+ * @param LPUART_DMAReq specifies the DMA request.
+ * This parameter can be any combination of the following values:
+ * @arg LPUART_DMAREQ_TX LPUART DMA transmit request
+ * @arg LPUART_DMAREQ_RX LPUART DMA receive request
+ * @param Cmd new state of the DMA Request sources.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void LPUART_EnableDMA(uint16_t LPUART_DMAReq, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_LPUART_DMAREQ(LPUART_DMAReq));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the DMA transfer by setting the DMA_RXEN and/or DMA_TXEN bits in the LPUART_CTRL register */
+ LPUART->CTRL |= LPUART_DMAReq;
+ }
+ else
+ {
+ /* Disable the DMA transfer by clearing the DMA_RXEN and/or DMA_TXEN bits in the LPUART_CTRL register */
+ LPUART->CTRL &= (uint16_t)(~LPUART_DMAReq);
+ }
+}
+
+/**
+ * @brief Selects the LPUART WakeUp method.
+ * @param LPUART_WakeUpMethod specifies the LPUART wakeup method.
+ * This parameter can be one of the following values:
+ * @arg LPUART_WUSTP_STARTBIT WakeUp by Start Bit Detection
+ * @arg LPUART_WUSTP_RXNE WakeUp by RXNE Detection
+ * @arg LPUART_WUSTP_BYTE WakeUp by A Configurable Received Byte
+ * @arg LPUART_WUSTP_FRAME WakeUp by A Programmed 4-Byte Frame
+ */
+void LPUART_ConfigWakeUpMethod(uint16_t LPUART_WakeUpMethod)
+{
+ /* Check the parameters */
+ assert_param(IS_LPUART_WAKEUP(LPUART_WakeUpMethod));
+
+ LPUART->CTRL &= CTRL_WUSTP_MASK;
+ LPUART->CTRL |= LPUART_WakeUpMethod;
+}
+
+/**
+ * @brief Enables or disables LPUART Wakeup in STOP2 mode.
+ * @param Cmd new state of the LPUART Wakeup in STOP2 mode.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void LPUART_EnableWakeUpStop(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable Wakeup in STOP2 mode by setting the WUSTP bit in the CTRL register */
+ LPUART->CTRL |= CTRL_WUSTP_SET;
+ }
+ else
+ {
+ /* Disable Wakeup in STOP2 mode by clearing the WUSTP bit in the CTRL register */
+ LPUART->CTRL &= CTRL_WUSTP_RESET;
+ }
+}
+
+/**
+ * @brief Selects the LPUART Sampling method.
+ * @param LPUART_SamplingMethod specifies the LPAURT sampling method.
+ * This parameter can be one of the following values:
+ * @arg LPUART_SMPCNT_3B 3 Sample bit
+ * @arg LPUART_SMPCNT_1B 1 Sample bit
+ */
+void LPUART_ConfigSamplingMethod(uint16_t LPUART_SamplingMethod)
+{
+ /* Check the parameters */
+ assert_param(IS_LPUART_SAMPLING(LPUART_SamplingMethod));
+
+ LPUART->CTRL &= CTRL_SMPCNT_MASK;
+ LPUART->CTRL |= LPUART_SamplingMethod;
+}
+
+/**
+ * @brief Enables or disables LPUART Loop Back Self-Test.
+ * @param Cmd new state of the LPUART Loop Back Self-Test.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void LPUART_EnableLoopBack(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable LPUART Loop Back Self-Test by setting the LOOKBACK bit in the CTRL register */
+ LPUART->CTRL |= CTRL_LOOPBACK_SET;
+ }
+ else
+ {
+ /* Disable LPUART Loop Back Self-Test by clearing the LOOKBACK bit in the CTRL register */
+ LPUART->CTRL &= CTRL_LOOPBACK_RESET;
+ }
+}
+
+/**
+ * @brief Transmits single data through the LPUART peripheral.
+ * @param Data the data to transmit.
+ */
+void LPUART_SendData(uint8_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_LPUART_DATA(Data));
+
+ /* Transmit Data */
+ LPUART->DAT = (Data & (uint8_t)0xFF);
+}
+
+/**
+ * @brief Returns the most recent received data by the LPUART peripheral.
+ * @return The received data.
+ */
+uint8_t LPUART_ReceiveData(void)
+{
+ /* Receive Data */
+ return (uint8_t)(LPUART->DAT & (uint8_t)0xFF);
+}
+
+/**
+ * @brief SConfigures LPUART detected byte or frame match for wakeup CPU from STOPS mode.
+ * @param LPUART_WakeUpData specifies the LPUART detected byte or frame match for wakeup CPU from STOP2 mode.
+ */
+void LPUART_ConfigWakeUpData(uint32_t LPUART_WakeUpData)
+{
+ LPUART->WUDAT = LPUART_WakeUpData;
+}
+
+/**
+ * @brief Checks whether the specified LPUART flag is set or not.
+ * @param LPUART_FLAG specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg LPUART_FLAG_PEF Parity Check Error Flag.
+ * @arg LPUART_FLAG_TXC TX Complete Flag.
+ * @arg LPUART_FLAG_FIFO_OV FIFO Overflow Flag.
+ * @arg LPUART_FLAG_FIFO_FU FIFO Full Flag.
+ * @arg LPUART_FLAG_FIFO_HF FIFO Half Full Flag.
+ * @arg LPUART_FLAG_FIFO_NE FIFO Non-Empty Flag.
+ * @arg LPUART_FLAG_CTS CTS Change(Hardware Flow Control) Flag.
+ * @arg LPUART_FLAG_WUFWakeup from STOP2 mode Flag.
+ * @arg LPUART_FLAG_NF Noise Detection Flag.
+ * @return The new state of LPUART_FLAG (SET or RESET).
+ */
+FlagStatus LPUART_GetFlagStatus(uint16_t LPUART_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_LPUART_FLAG(LPUART_FLAG));
+
+ if ((LPUART->STS & LPUART_FLAG) != (uint16_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the LPUART's pending flags.
+ * @param LPUART_FLAG specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg LPUART_FLAG_PEF Parity Check Error Flag.
+ * @arg LPUART_FLAG_TXC TX Complete Flag.
+ * @arg LPUART_FLAG_FIFO_OV FIFO Overflow Flag.
+ * @arg LPUART_FLAG_FIFO_FU FIFO Full Flag.
+ * @arg LPUART_FLAG_FIFO_HF FIFO Half Full Flag.
+ * @arg LPUART_FLAG_FIFO_NE FIFO Non-Empty Flag.
+ * @arg LPUART_FLAG_CTS CTS Change(Hardware Flow Control) Flag.
+ * @arg LPUART_FLAG_WUFWakeup from STOP2 mode Flag.
+ * @arg LPUART_FLAG_NF Noise Detection Flag.
+ */
+void LPUART_ClrFlag(uint16_t LPUART_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_LPUART_CLEAR_FLAG(LPUART_FLAG));
+
+ LPUART->STS = (uint16_t)LPUART_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified LPUART interrupt has occurred or not.
+ * @param LPUART_INT specifies the LPUART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg LPUART_INT_WUF Wake-Up Interrupt
+ * @arg LPUART_INT_FIFO_NE FIFO Non-Empty Interrupt
+ * @arg LPUART_INT_FIFO_HF FIFO Half Full Interrupt
+ * @arg LPUART_INT_FIFO_FU FIFO Full Interrupt Enable
+ * @arg LPUART_INT_FIFO_OV FIFO Overflow Interrupt
+ * @arg LPUART_INT_TXC TX Complete Interrupt
+ * @arg LPUART_INT_PE Parity Check Error Interrupt
+ * @return The new state of LPUART_INT (SET or RESET).
+ */
+INTStatus LPUART_GetIntStatus(uint16_t LPUART_INT)
+{
+ uint32_t bitpos = 0x00, itmask = 0x00;
+ INTStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_LPUART_GET_INT(LPUART_INT));
+
+ /* Get the interrupt position */
+ itmask = (uint8_t)(LPUART_INT >> 0x08) & INT_MASK;
+ itmask = (uint32_t)0x01 << itmask;
+ itmask &= LPUART->INTEN;
+
+ bitpos = ((uint8_t)LPUART_INT) & 0xFF;
+ if (LPUART_INT_WUF == LPUART_INT){
+ bitpos = (bitpos << 0x01);
+ }
+ bitpos &= LPUART->STS;
+ if ((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the LPUART's interrupt pending bits.
+ * @param LPUART_INT specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg LPUART_INT_WUF Wake-Up Interrupt
+ * @arg LPUART_INT_FIFO_NE FIFO Non-Empty Interrupt
+ * @arg LPUART_INT_FIFO_HF FIFO Half Full Interrupt
+ * @arg LPUART_INT_FIFO_FU FIFO Full Interrupt Enable
+ * @arg LPUART_INT_FIFO_OV FIFO Overflow Interrupt
+ * @arg LPUART_INT_TXC TX Complete Interrupt
+ * @arg LPUART_INT_PE Parity Check Error Interrupt
+ */
+void LPUART_ClrIntPendingBit(uint16_t LPUART_INT)
+{
+ uint16_t itmask = 0x00;
+ /* Check the parameters */
+ assert_param(IS_LPUART_CLR_INT(LPUART_INT));
+
+ itmask = ((uint8_t)LPUART_INT) & 0xFF;
+ LPUART->STS = (uint16_t)itmask;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_opamp.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_opamp.c
new file mode 100644
index 0000000000..a6599534f5
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_opamp.c
@@ -0,0 +1,198 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_opamp.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l43x_opamp.h"
+#include "n32l43x_rcc.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup OPAMP
+ * @brief OPAMP driver modules
+ * @{
+ */
+
+/** @addtogroup OPAMP_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup OPAMP_Private_Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup OPAMP_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup OPAMP_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup OPAMP_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup OPAMP_Private_Functions
+ * @{
+ */
+#define SetBitMsk(reg, bit, msk) ((reg) = (((reg) & ~(msk)) | (bit)))
+#define ClrBit(reg, bit) ((reg) &= ~(bit))
+#define SetBit(reg, bit) ((reg) |= (bit))
+#define GetBit(reg, bit) ((reg) & (bit))
+/**
+ * @brief Deinitializes the OPAMP peripheral registers to their default reset values.
+ */
+void OPAMP_DeInit(void)
+{
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_OPAMP, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_OPAMP, DISABLE);
+}
+void OPAMP_StructInit(OPAMP_InitType* OPAMP_InitStruct)
+{
+ OPAMP_InitStruct->Opa2SrcSel = OPAMP2_CS_TIMSRCSEL_TIM1CC6;
+ OPAMP_InitStruct->Gain = OPAMP_CS_PGA_GAIN_2;
+ OPAMP_InitStruct->HighVolRangeEn = ENABLE;
+ OPAMP_InitStruct->TimeAutoMuxEn = DISABLE;
+ OPAMP_InitStruct->Mod = OPAMP_CS_PGA_EN;
+}
+void OPAMP_Init(OPAMPX OPAMPx, OPAMP_InitType* OPAMP_InitStruct)
+{
+ __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+ __IO uint32_t tmp = *pCs;
+ if (OPAMPx == OPAMP2)
+ SetBitMsk(tmp, OPAMP_InitStruct->Opa2SrcSel, OPAMP_CS_OPAMP2_TIMSRCSEL);
+ SetBitMsk(tmp, OPAMP_InitStruct->Gain, OPAMP_CS_PGA_GAIN_MASK);
+ if (OPAMP_InitStruct->HighVolRangeEn==ENABLE)
+ SetBitMsk(tmp, OPAMP_CS_RANGE_MASK, OPAMP_CS_RANGE_MASK);
+ else
+ ClrBit(tmp,OPAMP_CS_RANGE_MASK);
+ if (OPAMP_InitStruct->TimeAutoMuxEn==ENABLE)
+ SetBitMsk(tmp,OPAMP_CS_TCMEN_MASK, OPAMP_CS_TCMEN_MASK);
+ else
+ ClrBit(tmp,OPAMP_CS_TCMEN_MASK);
+ SetBitMsk(tmp, OPAMP_InitStruct->Mod, OPAMP_CS_MOD_MASK);
+ *pCs = tmp;
+}
+void OPAMP_Enable(OPAMPX OPAMPx, FunctionalState en)
+{
+ __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+ if (en)
+ SetBit(*pCs, OPAMP_CS_EN_MASK);
+ else
+ ClrBit(*pCs, OPAMP_CS_EN_MASK);
+}
+
+void OPAMP_SetPgaGain(OPAMPX OPAMPx, OPAMP_CS_PGA_GAIN Gain)
+{
+ __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+ __IO uint32_t tmp = *pCs;
+ SetBitMsk(tmp, Gain, OPAMP_CS_PGA_GAIN_MASK);
+ *pCs = tmp;
+}
+void OPAMP_SetVpSecondSel(OPAMPX OPAMPx, OPAMP_CS_VPSSEL VpSSel)
+{
+ __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+ __IO uint32_t tmp = *pCs;
+ SetBitMsk(tmp, VpSSel, OPAMP_CS_VPSEL_SECOND_MASK);
+ *pCs = tmp;
+}
+void OPAMP_SetVmSecondSel(OPAMPX OPAMPx, OPAMP_CS_VMSSEL VmSSel)
+{
+ __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+ __IO uint32_t tmp = *pCs;
+ SetBitMsk(tmp, VmSSel, OPAMP_CS_VMSEL_SECOND_MASK);
+ *pCs = tmp;
+}
+void OPAMP_SetVpSel(OPAMPX OPAMPx, OPAMP_CS_VPSEL VpSel)
+{
+ __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+ __IO uint32_t tmp = *pCs;
+ SetBitMsk(tmp, VpSel, OPAMP_CS_VPSEL_MASK);
+ *pCs = tmp;
+}
+void OPAMP_SetVmSel(OPAMPX OPAMPx, OPAMP_CS_VMSEL VmSel)
+{
+ __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+ __IO uint32_t tmp = *pCs;
+ SetBitMsk(tmp, VmSel, OPAMP_CS_VMSEL_MASK);
+ *pCs = tmp;
+}
+bool OPAMP_IsCalOutHigh(OPAMPX OPAMPx)
+{
+ __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+ return (GetBit(*pCs, OPAMP_CS_CALOUT_MASK)) ? true : false;
+}
+void OPAMP_CalibrationEnable(OPAMPX OPAMPx, FunctionalState en)
+{
+ __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+ if (en)
+ SetBit(*pCs, OPAMP_CS_CALON_MASK);
+ else
+ ClrBit(*pCs, OPAMP_CS_CALON_MASK);
+}
+// Lock see @OPAMP_LOCK
+void OPAMP_SetLock(uint32_t Lock)
+{
+ OPAMP->LOCK = Lock;
+}
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_pwr.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_pwr.c
new file mode 100644
index 0000000000..a5d7cdc5b9
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_pwr.c
@@ -0,0 +1,542 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_pwr.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l43x_pwr.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup PWR
+ * @brief PWR driver modules
+ * @{
+ */
+
+/** @addtogroup PWR_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Private_Defines
+ * @{
+ */
+
+/* --------- PWR registers bit address in the alias region ---------- */
+#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
+
+/* --- CTRL Register ---*/
+
+/* Alias word address of DBKP bit */
+#define CTRL_OFFSET (PWR_OFFSET + 0x00)
+#define DBKP_BITN 0x08
+#define CTRL_DBKP_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (DBKP_BITN * 4))
+
+/* Alias word address of PVDEN bit */
+#define PVDEN_BITN 0x04
+#define CTRL_PVDEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (PVDEN_BITN * 4))
+
+/* --- CTRLSTS Register ---*/
+
+/* Alias word address of WKUPEN bit */
+#define CTRLSTS_OFFSET (PWR_OFFSET + 0x04)
+#define WKUPEN_BITN 0x08
+#define CTRLSTS_WKUPEN_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (WKUPEN_BITN * 4))
+
+/* ------------------ PWR registers bit mask ------------------------ */
+
+
+void SetSysClock_MSI(void);
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the PWR peripheral registers to their default reset values.
+ */
+void PWR_DeInit(void)
+{
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_PWR, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_PWR, DISABLE);
+}
+
+/**
+ * @brief Enables or disables access to the RTC and backup registers.
+ * @param Cmd new state of the access to the RTC and backup registers.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void PWR_BackupAccessEnable(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)CTRL_DBKP_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief MR voltage selection.
+ * @param voltage value: 1.0V and 1.1V.
+ * This parameter can be: MR_1V0 or MR_1V1.
+ */
+void PWR_MRconfig(uint8_t voltage)
+{
+ uint32_t tmpreg = 0;
+ tmpreg = PWR->CTRL1;
+ /* Clear MRSEL bits */
+ tmpreg &= (~PWR_CTRL1_MRSELMASK);
+ /* Set voltage*/
+ tmpreg |= (uint32_t)(voltage << 9);
+ PWR->CTRL1 = tmpreg;
+}
+
+/**
+ * @brief Get MR voltage value.
+ * @param voltage value: 1.0V and 1.1V.
+ * @return The value of voltage.
+ */
+uint8_t GetMrVoltage(void)
+{
+ uint8_t tmp = 0;
+ /* 2bits */
+ tmp = (uint8_t)((PWR->CTRL1 >> 9) & 0x03);
+ return tmp ;
+}
+
+/**
+ * @brief Enables or disables the Power Voltage Detector(PVD).
+ * @param Cmd new state of the PVD.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void PWR_PvdEnable(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ /* Can not enable the PVD bit */
+ //*(__IO uint32_t*)CTRL_PVDEN_BB = (uint32_t)Cmd;
+ PWR->CTRL2 |= Cmd;
+}
+
+/**
+ * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+ * @param PWR_PVDLevel: specifies the PVD detection level
+ * This parameter can be one of the following values:
+ * @arg PWR_CTRL2_PLS1: PVD detection level set to 2.1V
+ * @arg PWR_CTRL2_PLS2: PVD detection level set to 2.25V
+ * @arg PWR_CTRL2_PLS3: PVD detection level set to 2.4V
+ * @arg PWR_CTRL2_PLS4: PVD detection level set to 2.55V
+ * @arg PWR_CTRL2_PLS5: PVD detection level set to 2.7V
+ * @arg PWR_CTRL2_PLS6: PVD detection level set to 2.85V
+ * @arg PWR_CTRL2_PLS7: PVD detection level set to 2.95V
+ * @arg PWR_CTRL2_PLS8: external input analog voltage PVD_IN (compared internally to VREFINT)
+ * @retval None
+ */
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
+ tmpregister = PWR->CTRL2;
+ /* Clear PLS[7:5] bits */
+ tmpregister &= (~PWR_CTRL2_PLSMASK);
+ /* Set PRS[7:5] bits according to PWR_PVDLevel value */
+ tmpregister |= PWR_PVDLevel;
+ /* Store the new value */
+ PWR->CTRL2 = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the WakeUp Pin functionality.
+ * @param Pin: which PIN select to wakeup.
+ * This parameter can be one of the following values:
+ * @arg WAKEUP_PIN0
+ * @arg WAKEUP_PIN1
+ * @arg WAKEUP_PIN2
+ * @param Cmd new state of the WakeUp Pin functionality.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void PWR_WakeUpPinEnable(WAKEUP_PINX WKUP_Pin,FunctionalState Cmd)
+{
+ uint32_t Temp = 0;
+ Temp = PWR->CTRL3;
+ if (ENABLE==Cmd)
+ {
+ Temp &= (~(PWR_CTRL3_WKUP0EN|PWR_CTRL3_WKUP1EN|PWR_CTRL3_WKUP2EN));
+ Temp |= (WKUP_Pin);
+ PWR->CTRL3 = Temp;
+ }
+ else
+ {
+ Temp &= (~(WKUP_Pin));
+ PWR->CTRL3 = Temp;
+ }
+}
+
+/**
+ * @brief Enters SLEEP mode.
+ * @param SLEEPONEXIT: specifies the SLEEPONEXIT state in SLEEP mode.
+ * This parameter can be one of the following values:
+ * @arg 0: SLEEP mode with SLEEPONEXIT disable
+ * @arg 1: SLEEP mode with SLEEPONEXIT enable
+ * @param PWR_STOPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.
+ * This parameter can be one of the following values:
+ * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction
+ * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction
+ * @retval None
+ */
+void PWR_EnterSLEEPMode(uint8_t SLEEPONEXIT, uint8_t PWR_SLEEPEntry)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));
+ /* CLEAR SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
+ /* Select SLEEPONEXIT mode entry --------------------------------------------------*/
+ if (SLEEPONEXIT == 1)
+ {
+ /* the MCU enters Sleep mode as soon as it exits the lowest priority ISR */
+ SCB->SCR |= SCB_SCR_SLEEPONEXIT;
+ }
+ else if (SLEEPONEXIT == 0)
+ {
+ /* Sleep-now */
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPONEXIT);
+ }
+ /* Select SLEEP mode entry --------------------------------------------------*/
+ if (PWR_SLEEPEntry == PWR_SLEEPENTRY_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+}
+
+/**
+ * @brief Enters STOP2 mode.
+ * @param PWR_STOPEntry specifies if STOP2 mode in entered with WFI or WFE instruction.
+ * This parameter can be one of the following values:
+ * @arg PWR_STOPENTRY_WFI enter STOP2 mode with WFI instruction
+ * @arg PWR_STOPENTRY_WFE enter STOP2 mode with WFE instruction
+ * @param RetentionMode: PWR_CTRL3_RAM1RET or PWR_CTRL3_RAM2RET
+ */
+void PWR_EnterSTOP2Mode(uint8_t PWR_STOPEntry,uint32_t RetentionMode)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
+ /* Wait MR Voltage Adjust Complete */
+ while ((PWR->STS2 &0X2) != 2);
+ tmpreg = PWR->CTRL3;
+ /* Clear SRAMRET bits */
+ tmpreg &= (~PWR_CTRL3_RAMRETMASK);
+ /* Set SRAM1/2 select */
+ tmpreg |= RetentionMode;
+ PWR->CTRL3 = tmpreg;
+ /* Select the regulator state in STOP2 mode ---------------------------------*/
+ tmpreg = PWR->CTRL1;
+ /* Clear LPMS bits */
+ tmpreg &= (~PWR_CTRL1_LPMSELMASK);
+ /* Set stop2 mode select */
+ tmpreg |= PWR_CTRL1_STOP2;
+ /* Store the new value */
+ PWR->CTRL1 = tmpreg;
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP;
+ /* Select STOP mode entry --------------------------------------------------*/
+ if (PWR_STOPEntry == PWR_STOPENTRY_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
+}
+
+/**
+ * @brief Enters Low power run mode.
+ * @param
+ * @arg
+ * @arg
+ * @retval None
+ */
+void PWR_EnterLowPowerRunMode(void)
+{
+ uint32_t tmpreg = 0;
+ SetSysClock_MSI();
+ FLASH_SetLatency(FLASH_LATENCY_2); //Configure the Flash read latency to be grater than 2, so LVE/SE timing requirement is guaranteed
+ /* config FLASH enter the low power voltage mode */
+ FLASH->AC |= FLASH_AC_LVMEN;
+ while ((FLASH->AC & FLASH_AC_LVMF) != FLASH_AC_LVMF);
+ FLASH_SetLatency(FLASH_LATENCY_0); //Configure the latency of Flash read cycle to proper value which depends on the Flash read access time.
+ _SetLprunSramVoltage(0);
+ _SetBandGapMode(0);
+ _SetPvdBorMode(0);
+ /* Select the regulator state in LPRUN mode */
+ tmpreg = PWR->CTRL1;
+ /* Clear LPMS bits */
+ tmpreg &= (~PWR_CTRL1_LPMSELMASK);
+ /* Set lpr to run the main power domain */
+ tmpreg |= PWR_CTRL1_LPREN;
+ /* Store the new value */
+ PWR->CTRL1 = tmpreg;
+ /* LPRCNT flag ready */
+ while ((PWR->STS2 &PWR_STS2_LPRUNF) != 0);
+}
+
+/**
+ * @brief Exit Low power run mode.
+ * @param
+ * @arg
+ * @arg
+ * @retval None
+ */
+void PWR_ExitLowPowerRunMode(void)
+{
+ PWR->CTRL1 &= ~PWR_CTRL1_LPREN;
+ while ((PWR->STS2 &PWR_STS2_LPRUNF) != PWR_STS2_LPRUNF);
+ /* Configure the Flash read latency to be grater than 2, so LVE/SE timing requirement is guaranteed */
+ FLASH_SetLatency(FLASH_LATENCY_2);
+ /* clear LVMREQ */
+ FLASH->AC &= ~FLASH_AC_LVMEN;
+ /* wait LVE is deasserted by polling the LVMVLD bit */
+ while ((FLASH->AC &FLASH_AC_LVMF) != 0);
+ /* Configure the latency of Flash read cycle to proper value which depends on the Flash read access time */
+ FLASH_SetLatency(FLASH_LATENCY_0);
+}
+
+/**
+ * @brief Enters LP_SLEEP mode.
+ * @param SLEEPONEXIT: specifies the SLEEPONEXIT state in SLEEP mode.
+ * This parameter can be one of the following values:
+ * @arg 0: SLEEP mode with SLEEPONEXIT disable
+ * @arg 1: SLEEP mode with SLEEPONEXIT enable
+ * @param PWR_STOPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.
+ * This parameter can be one of the following values:
+ * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction
+ * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction
+ * @retval None
+ */
+void PWR_EnterLowPowerSleepMode(uint8_t SLEEPONEXIT, uint8_t PWR_SLEEPEntry)
+{
+ PWR_EnterLowPowerRunMode();
+ PWR_EnterSLEEPMode(SLEEPONEXIT, PWR_SLEEPEntry);
+}
+
+ /**
+ * @brief Enters STANDBY mode.
+ * @param PWR_STANDBYEntry: specifies if STANDBY mode in entered with WFI or WFE instruction.
+ * This parameter can be one of the following values:
+ * @arg PWR_STANDBYEntry_WFI: enter STANDBY mode with WFI instruction
+ * @arg PWR_CTRL3_RAM2RET: SRAM2 whether to retention
+ * @retval None
+ */
+void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry,uint32_t Sam2Ret)
+{
+ uint32_t tmpreg;
+ /* Clear Wake-up flag */
+ PWR->STSCLR |= PWR_STSCLR_CLRWKUP0;
+ PWR->STSCLR |= PWR_STSCLR_CLRWKUP1;
+ PWR->STSCLR |= PWR_STSCLR_CLRWKUP2;
+ tmpreg = PWR->CTRL3;
+ /* Clear SRAMRET bits */
+ tmpreg &= (~PWR_CTRL3_RAMRETMASK);
+ /* Set SRAM1/2 select */
+ tmpreg |= Sam2Ret;
+ PWR->CTRL3 = tmpreg;
+ tmpreg = PWR->CTRL1;
+ /* Clear LPMS bits */
+ tmpreg &= (~PWR_CTRL1_LPMSELMASK);
+ /* Select STANDBY mode */
+ tmpreg |= PWR_CTRL1_STANDBY;
+ PWR->CTRL1 = tmpreg;
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP;
+ /* This option is used to ensure that store operations are completed */
+ #if defined (__CC_ARM)
+ __force_stores();
+ #endif
+ /* Select STANDBY mode entry */
+ if (PWR_STANDBYEntry == PWR_STOPENTRY_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+}
+
+/**
+ * @brief Checks whether the specified PWR flag is set or not.
+ * @param PWR_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg PWR_WKUP1_FLAG/PWR_WKUP2_FLAG/PWR_WKUP3_FLAG: Wake Up flag
+ * @arg PWR_STBY_FLAG: StandBy flag
+ * @arg PWR_LPRUN_FLAG: low power work flag
+ * @arg PWR_MR_FLAG: MR work statue flag
+ * @arg PWR_PVDO_FLAG: PVD output flag
+ * @retval The new state of PWR_FLAG (SET or RESET).
+ */
+FlagStatus PWR_GetFlagStatus(uint8_t STS,uint32_t PWR_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
+ if (STS == 1)
+ {
+ if ((PWR->STS1 & PWR_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+ else
+ {
+ if ((PWR->STS2 & PWR_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the PWR's pending flags.
+ * @param PWR_FLAG specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg PWR_WKUP1_FLAG/PWR_WKUP2_FLAG/PWR_WKUP3_FLAG: Wake Up flag
+ * @arg PWR_STBY_FLAG: StandBy flag
+ */
+void PWR_ClearFlag(uint32_t PWR_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
+ PWR->STSCLR |= PWR_FLAG ;
+}
+
+/**
+ * @brief set system clock with MSI.
+ * @param void.
+ */
+void SetSysClock_MSI(void)
+{
+ RCC_DeInit();
+ if (RESET == RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_MSIRD))
+ {
+ /* Enable MSI and Config Clock */
+ RCC_ConfigMsi(RCC_MSI_ENABLE, RCC_MSI_RANGE_4M);
+ /* Waits for MSI start-up */
+ while (SUCCESS != RCC_WaitMsiStable());
+ }
+ /* Enable Prefetch Buffer */
+ FLASH_PrefetchBufSet(FLASH_PrefetchBuf_EN);
+ /* Select MSI as system clock source */
+ RCC_ConfigSysclk(RCC_SYSCLK_SRC_MSI);
+ /* Wait till MSI is used as system clock source */
+ while (RCC_GetSysclkSrc() != 0x00)
+ {
+ }
+ /* Flash 0 wait state */
+ //FLASH_SetLatency(FLASH_LATENCY_0);
+ /* HCLK = SYSCLK */
+ RCC_ConfigHclk(RCC_SYSCLK_DIV1);
+ /* PCLK2 = HCLK */
+ RCC_ConfigPclk2(RCC_HCLK_DIV1);
+ /* PCLK1 = HCLK */
+ RCC_ConfigPclk1(RCC_HCLK_DIV1);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_rcc.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_rcc.c
new file mode 100644
index 0000000000..2d13afd21b
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_rcc.c
@@ -0,0 +1,1876 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_rcc.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l43x_rcc.h"
+
+/** @addtogroup N32L43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RCC
+ * @brief RCC driver modules
+ * @{
+ */
+
+/** @addtogroup RCC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_Defines
+ * @{
+ */
+
+/* ------------ RCC registers bit address in the alias region ----------- */
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
+
+/* --- CTRL Register ---*/
+
+/* Alias word address of HSIEN bit */
+#define CTRL_OFFSET (RCC_OFFSET + 0x00)
+#define HSIEN_BITN 0x00
+#define CTRL_HSIEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (HSIEN_BITN * 4))
+
+/* Alias word address of PLLEN bit */
+#define PLLEN_BITN 0x18
+#define CTRL_PLLEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (PLLEN_BITN * 4))
+
+/* Alias word address of CLKSSEN bit */
+#define CLKSSEN_BITN 0x13
+#define CTRL_CLKSSEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (CLKSSEN_BITN * 4))
+
+/* --- CFG Register ---*/
+
+/* Alias word address of USBPRES bit */
+#define CFG_OFFSET (RCC_OFFSET + 0x04)
+
+#define USBPRES_BITN 0x16
+#define CFG_USBPRES_BB (PERIPH_BB_BASE + (CFG_OFFSET * 32) + (USBPRES_BITN * 4))
+
+#define USBPRE_Bit1Number 0x17
+#define CFGR_USBPRE_BB_BIT1 (PERIPH_BB_BASE + (CFG_OFFSET * 32) + (USBPRE_Bit1Number * 4))
+
+/* --- CLKINT Register ---*/
+
+#define CLKINT_OFFSET (RCC_OFFSET + 0x08)
+
+/* Alias word address of LSIRDIF bit */
+#define LSIRDIF_BITN 0x00
+#define CLKINT_LSIRDIF_BB (PERIPH_BB_BASE + (CLKINT_OFFSET * 32) + (LSIRDIF_BITN * 4))
+
+/* --- LDCTRL Register ---*/
+
+/* Alias word address of LSECLKSSEN bit */
+#define LSECLKSSEN_BITN 0x03
+#define LDCTRL_LSECLKSSEN_BB (PERIPH_BB_BASE + (LDCTRL_OFFSET * 32) + (LSECLKSSEN_BITN * 4))
+
+/* Alias word address of RTCEN bit */
+#define LDCTRL_OFFSET (RCC_OFFSET + 0x20)
+#define RTCEN_BITN 0x0F
+#define LDCTRL_RTCEN_BB (PERIPH_BB_BASE + (LDCTRL_OFFSET * 32) + (RTCEN_BITN * 4))
+
+/* Alias word address of LDSFTRST bit */
+#define LDSFTRST_BITN 0x10
+#define LDCTRL_LDSFTRST_BB (PERIPH_BB_BASE + (LDCTRL_OFFSET * 32) + (LDSFTRST_BITN * 4))
+
+/* --- CTRLSTS Register ---*/
+
+/* Alias word address of LSIEN bit */
+#define CTRLSTS_OFFSET (RCC_OFFSET + 0x24)
+#define LSIEN_BITNUMBER 0x00
+#define CTRLSTS_LSIEN_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (LSIEN_BITNUMBER * 4))
+
+/* Alias word address of MSIEN bit */
+#define MSIEN_BITNUMBER 0x02
+#define CTRLSTS_MSIEN_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (MSIEN_BITNUMBER * 4))
+
+/* ---------------------- RCC registers bit mask ------------------------ */
+
+/* CTRL register bit mask */
+#define CTRL_HSEBP_RESET ((uint32_t)0xFFFBFFFF)
+#define CTRL_HSEBP_SET ((uint32_t)0x00040000)
+#define CTRL_HSEEN_RESET ((uint32_t)0xFFFEFFFF)
+#define CTRL_HSEEN_SET ((uint32_t)0x00010000)
+#define CTRL_HSITRIM_MASK ((uint32_t)0xFFFFFF83)
+#define CTRL_HSIEN_RESET ((uint32_t)0xFFFFFFFE)
+#define CTRL_HSIEN_SET ((uint32_t)0x00000001)
+
+/* CTRLSTS register bit mask */
+#define CTRLSTS_MSITRIM_MASK ((uint32_t)0xFF807FFF)
+#define CTRLSTS_MSIEN_RESET ((uint32_t)0xFFFFFFFB)
+#define CTRLSTS_MSIEN_SET ((uint32_t)0x00000004)
+
+#define CTRLSTS_MSIRANGE_MASK ((uint32_t)0xFFFFFF8F)
+#define CTRLSTS_MSIRANGE_RESET ((uint32_t)0x00000060) /* 4MHz */
+
+/* CFG register bit mask */
+#define CFG_PLL_MASK ((uint32_t)0xF7C0FFFF)
+
+#define CFG_PLLMULFCT_MASK ((uint32_t)0x083C0000)
+#define CFG_PLLSRC_MASK ((uint32_t)0x00010000)
+#define CFG_PLLHSEPRES_MASK ((uint32_t)0x00020000)
+#define CFG_SCLKSTS_MASK ((uint32_t)0x0000000C)
+#define CFG_SCLKSW_MASK ((uint32_t)0xFFFFFFFC)
+#define CFG_AHBPRES_RESET_MASK ((uint32_t)0xFFFFFF0F)
+#define CFG_AHBPRES_SET_MASK ((uint32_t)0x000000F0)
+#define CFG_APB1PRES_RESET_MASK ((uint32_t)0xFFFFF8FF)
+#define CFG_APB1PRES_SET_MASK ((uint32_t)0x00000700)
+#define CFG_APB2PRES_RESET_MASK ((uint32_t)0xFFFFC7FF)
+#define CFG_APB2PRES_SET_MASK ((uint32_t)0x00003800)
+
+/* CFG2 register bit mask */
+#define CFG2_TIM18CLKSEL_SET_MASK ((uint32_t)0x20000000)
+#define CFG2_TIM18CLKSEL_RESET_MASK ((uint32_t)0xDFFFFFFF)
+#define CFG2_RNGCPRES_SET_MASK ((uint32_t)0x1F000000)
+#define CFG2_RNGCPRES_RESET_MASK ((uint32_t)0xE0FFFFFF)
+#define CFG2_ETHCLKSEL_SET_MASK ((uint32_t)0x00100000)
+#define CFG2_ETHCLKSEL_RESET_MASK ((uint32_t)0xFFEFFFFF)
+#define CFG2_ADC1MSEL_SET_MASK ((uint32_t)0x00020000)
+#define CFG2_ADC1MSEL_RESET_MASK ((uint32_t)0xFFFDFFFF)
+#define CFG2_ADC1MPRES_SET_MASK ((uint32_t)0x0001F000)
+#define CFG2_ADC1MPRES_RESET_MASK ((uint32_t)0xFFFE0FFF)
+#define CFG2_ADCPLLPRES_SET_MASK ((uint32_t)0x000001F0)
+#define CFG2_ADCPLLPRES_RESET_MASK ((uint32_t)0xFFFFFE0F)
+#define CFG2_ADCHPRES_SET_MASK ((uint32_t)0x0000000F)
+#define CFG2_ADCHPRES_RESET_MASK ((uint32_t)0xFFFFFFF0)
+
+/* CFG3 register bit mask */
+#define CFGR3_TRNG1MSEL_SET_MASK ((uint32_t)0x00020000)
+#define CFGR3_TRNG1MSEL_RESET_MASK ((uint32_t)0xFFFDFFFF)
+#define CFGR3_TRNG1MPRES_SET_MASK ((uint32_t)0x0000F800)
+#define CFGR3_TRNG1MPRES_RESET_MASK ((uint32_t)0xFFFF07FF)
+
+/* CTRLSTS register bit mask */
+#define CSR_RMRSTF_SET ((uint32_t)0x01000000)
+#define CSR_RMVF_Reset ((uint32_t)0xfeffffff)
+
+/* RCC Flag Mask */
+#define FLAG_MASK ((uint8_t)0x1F)
+
+/* CLKINT register(Bits[31:0]) base address */
+#define CLKINT_ADDR ((uint32_t)0x40021008)
+
+/* LDCTRL register base address */
+#define LDCTRL_ADDR (PERIPH_BASE + LDCTRL_OFFSET)
+
+/* RDCTRL register bit mask */
+#define RDCTRL_LPTIMCLKSEL_MASK ((uint32_t)0x00000007)
+#define RDCTRL_LPUARTCLKSEL_MASK ((uint32_t)0x00000018)
+
+/* PLLHSIPRE register bit mask */
+#define PLLHSIPRE_PLLHSI_PRE_MASK ((uint32_t)0x00000001)
+#define PLLHSIPRE_PLLSRCDIV_MASK ((uint32_t)0x00000002)
+
+#define LSE_TRIMR_ADDR ((uint32_t)0x40001808)
+
+#define LSE_GM_MASK_VALUE (0x1FF)
+#define LSE_GM_MAX_VALUE (0x1FF)
+#define LSE_GM_DEFAULT_VALUE (0x1FF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_Variables
+ * @{
+ */
+
+static const uint8_t s_ApbAhbPresTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+static const uint8_t s_AdcHclkPresTable[16] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 32, 32, 32, 32, 32, 32, 32};
+static const uint16_t s_AdcPllClkPresTable[16] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256, 256, 256, 256, 256};
+static const uint32_t s_msiClockTable[7] = {MSI_VALUE_L0, MSI_VALUE_L1, MSI_VALUE_L2, MSI_VALUE_L3,
+ MSI_VALUE_L4, MSI_VALUE_L5, MSI_VALUE_L6};
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Resets the RCC clock configuration to the default reset state.
+ */
+void RCC_DeInit(void)
+{
+ /* Set MSIEN bit */
+ RCC->CTRLSTS |= (uint32_t)0x00000004;
+ /* Reset SW, HPRE, PPRE1, PPRE2 and MCO bits */
+ RCC->CFG &= (uint32_t)0xF8FFC000;
+ /* Reset HSIEN, HSEEN, CLKSSEN and PLLEN bits */
+ RCC->CTRL &= (uint32_t)0xFEF6FFFE;
+ /* Reset HSEBYP bit */
+ RCC->CTRL &= (uint32_t)0xFFFBFFFF;
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRES bits */
+ RCC->CFG &= (uint32_t)0xF700FFFF;
+ /* Reset CFG2 register */
+ RCC->CFG2 = 0x00007000;
+ /* Reset CFG3 register */
+ RCC->CFG3 = 0x00003800;
+ /* Reset RDCTRL register */
+ RCC->RDCTRL = 0x00000000;
+ /* Reset PLLHSIPRE register */
+ RCC->PLLHSIPRE = 0x00000000;
+ /* Disable all interrupts and clear pending bits */
+ RCC->CLKINT = 0x04BF8000;
+}
+
+/**
+ * @brief Configures the External High Speed oscillator (HSE).
+ * @note HSE can not be stopped if it is used directly or through the PLL as system clock.
+ * @param RCC_HSE specifies the new state of the HSE.
+ * This parameter can be one of the following values:
+ * @arg RCC_HSE_DISABLE HSE oscillator OFF
+ * @arg RCC_HSE_ENABLE HSE oscillator ON
+ * @arg RCC_HSE_BYPASS HSE oscillator bypassed with external clock
+ */
+void RCC_ConfigHse(uint32_t RCC_HSE)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_HSE(RCC_HSE));
+ /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
+ /* Reset HSEON bit */
+ RCC->CTRL &= CTRL_HSEEN_RESET;
+ /* Reset HSEBYP bit */
+ RCC->CTRL &= CTRL_HSEBP_RESET;
+ /* Configure HSE (RCC_HSE_DISABLE is already covered by the code section above) */
+ switch (RCC_HSE)
+ {
+ case RCC_HSE_ENABLE:
+ /* Set HSEEN bit */
+ RCC->CTRL |= CTRL_HSEEN_SET;
+ break;
+ case RCC_HSE_BYPASS:
+ /* Set HSEBYP and HSEEN bits */
+ RCC->CTRL |= CTRL_HSEBP_SET | CTRL_HSEEN_SET;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Waits for HSE start-up.
+ * @return An ErrorStatus enumuration value:
+ * - SUCCESS: HSE oscillator is stable and ready to use
+ * - ERROR: HSE oscillator not yet ready
+ */
+ErrorStatus RCC_WaitHseStable(void)
+{
+ __IO uint32_t StartUpCounter = 0;
+ ErrorStatus status = ERROR;
+ FlagStatus HSEStatus = RESET;
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC_GetFlagStatus(RCC_CTRL_FLAG_HSERDF);
+ StartUpCounter++;
+ } while ((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
+ if (RCC_GetFlagStatus(RCC_CTRL_FLAG_HSERDF) != RESET)
+ {
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+ return (status);
+}
+
+/**
+ * @brief Configures the Internal High Speed oscillator (HSI).
+ * @note HSI can not be stopped if it is used directly or through the PLL as system clock.
+ * @param RCC_HSI specifies the new state of the HSI.
+ * This parameter can be one of the following values:
+ * @arg RCC_HSI_DISABLE HSI oscillator OFF
+ * @arg RCC_HSI_ENABLE HSI oscillator ON
+ */
+void RCC_ConfigHsi(uint32_t RCC_HSI)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_HSI(RCC_HSI));
+ /* Reset HSIEN bit */
+ RCC->CTRL &= CTRL_HSIEN_RESET;
+ /* Configure HSI */
+ switch (RCC_HSI)
+ {
+ case RCC_HSI_ENABLE:
+ /* Set HSIEN bit */
+ RCC->CTRL |= CTRL_HSIEN_SET;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Waits for HSI start-up.
+ * @return An ErrorStatus enumuration value:
+ * - SUCCESS: HSI oscillator is stable and ready to use
+ * - ERROR: HSI oscillator not yet ready
+ */
+ErrorStatus RCC_WaitHsiStable(void)
+{
+ __IO uint32_t StartUpCounter = 0;
+ ErrorStatus status = ERROR;
+ FlagStatus HSIStatus = RESET;
+ /* Wait till HSI is ready and if Time out is reached exit */
+ do
+ {
+ HSIStatus = RCC_GetFlagStatus(RCC_CTRL_FLAG_HSIRDF);
+ StartUpCounter++;
+ } while ((StartUpCounter != HSI_STARTUP_TIMEOUT) && (HSIStatus == RESET));
+ if (RCC_GetFlagStatus(RCC_CTRL_FLAG_HSIRDF) != RESET)
+ {
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+ return (status);
+}
+
+/**
+ * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
+ * @param HSICalibrationValue specifies the calibration trimming value.
+ * This parameter must be a number between 0 and 0x1F.
+ */
+void RCC_SetHsiCalibValue(uint8_t HSICalibrationValue)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_CALIB_VALUE(HSICalibrationValue));
+ tmpregister = RCC->CTRL;
+ /* Clear HSITRIM[4:0] bits */
+ tmpregister &= CTRL_HSITRIM_MASK;
+ /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
+ tmpregister |= (uint32_t)HSICalibrationValue << 2;
+ /* Store the new value */
+ RCC->CTRL = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the Internal High Speed oscillator (HSI).
+ * @note HSI can not be stopped if it is used directly or through the PLL as system clock.
+ * @param Cmd new state of the HSI. This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableHsi(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)CTRL_HSIEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Configures the Multi Speed oscillator (MSI).
+ * @param RCC_MSI specifies the new state of the MSI.
+ * This parameter can be one of the following values:
+ * @arg RCC_MSI_DISABLE MSI oscillator OFF
+ * @arg RCC_MSI_ENABLE MSI oscillator ON
+ * @param RCC_MSI_Range specifies the clock of the MSI.
+ * This parameter can be one of the following values:
+ * @arg RCC_MSI_RANGE_100K 100KHz
+ * @arg RCC_MSI_RANGE_200K 200KHz
+ * @arg RCC_MSI_RANGE_400K 400KHz
+ * @arg RCC_MSI_RANGE_800K 800KHz
+ * @arg RCC_MSI_RANGE_1M 1MHz
+ * @arg RCC_MSI_RANGE_2M 2MHz
+ * @arg RCC_MSI_RANGE_4M 4MHz
+ */
+void RCC_ConfigMsi(uint32_t RCC_MSI, uint32_t RCC_MSI_Range)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_MSI(RCC_MSI));
+ assert_param(IS_RCC_MSI_RANGE(RCC_MSI_Range));
+ /* Set MSIRANGE[2:0] bit */
+ RCC->CTRLSTS &= CTRLSTS_MSIRANGE_MASK;
+ RCC->CTRLSTS |= RCC_MSI_Range;
+ /* Configure MSI */
+ switch (RCC_MSI)
+ {
+ case RCC_MSI_ENABLE:
+ /* Set MSIEN bit */
+ RCC->CTRLSTS |= CTRLSTS_MSIEN_SET;
+ break;
+ case RCC_MSI_DISABLE:
+ /* Reset MSIEN bit */
+ RCC->CTRLSTS &= CTRLSTS_MSIEN_RESET;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Waits for MSI start-up.
+ * @return An ErrorStatus enumuration value:
+ * - SUCCESS: MSI oscillator is stable and ready to use
+ * - ERROR: MSI oscillator not yet ready
+ */
+ErrorStatus RCC_WaitMsiStable(void)
+{
+ __IO uint32_t StartUpCounter = 0;
+ ErrorStatus status = ERROR;
+ FlagStatus MSIStatus = RESET;
+ /* Wait till MSI is ready and if Time out is reached exit */
+ do
+ {
+ MSIStatus = RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_MSIRD);
+ StartUpCounter++;
+ } while ((StartUpCounter != MSI_STARTUP_TIMEOUT) && (MSIStatus == RESET));
+ if (RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_MSIRD) != RESET)
+ {
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+ return (status);
+}
+
+/**
+ * @brief Adjusts the Multi Speed oscillator (MSI) calibration value.
+ * @param MSICalibrationValue specifies the calibration trimming value.
+ * This parameter must be a number between 0 and 0xFF.
+ */
+void RCC_SetMsiCalibValue(uint8_t MSICalibrationValue)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ //assert_param(IS_RCC_MSICALIB_VALUE(MSICalibrationValue));
+ tmpregister = RCC->CTRLSTS;
+ /* Clear MSITRIM[7:0] bits */
+ tmpregister &= CTRLSTS_MSITRIM_MASK;
+ /* Set the MSITRIM[7:0] bits according to MSICalibrationValue value */
+ tmpregister |= (uint32_t)MSICalibrationValue << 15;
+ /* Store the new value */
+ RCC->CTRLSTS = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the Multi Speed oscillator (MSI).
+ * @param Cmd new state of the MSI. This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableMsi(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)CTRLSTS_MSIEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Configures the PLL clock source and multiplication factor.
+ * @note This function must be used only when the PLL is disabled.
+ * @param RCC_PLLSource specifies the PLL entry clock source.
+ * this parameter can be one of the following values:
+ * @arg RCC_PLL_HSI_PRE_DIV1 HSI oscillator clock selected as PLL clock entry
+ * @arg RCC_PLL_HSI_PRE_DIV2 HSI oscillator clock divided by 2 selected as PLL clock entry
+ * @arg RCC_PLL_SRC_HSE_DIV1 HSE oscillator clock selected as PLL clock entry
+ * @arg RCC_PLL_SRC_HSE_DIV2 HSE oscillator clock divided by 2 selected as PLL clock entry
+ * @param RCC_PLLMul specifies the PLL multiplication factor.
+ * this parameter can be RCC_PLLMul_x where x:[2,32]
+ * @param RCC_PLLDIVCLK specifies the PLL divider feedback clock source.
+ * this parameter can be one of the following values:
+ * @arg RCC_PLLDIVCLK_DISABLE PLLSource clock selected as PLL clock entry
+ * @arg RCC_PLLDIVCLK_ENABLE PLLSource clock divided by 2 selected as PLL clock entry
+ */
+void RCC_ConfigPll(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul, uint32_t RCC_PLLDIVCLK)
+{
+ uint32_t tmpregister = 0;
+ uint32_t pllhsipreregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL_SRC(RCC_PLLSource));
+ assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
+ assert_param(IS_RCC_PLL_DIVCLK(RCC_PLLDIVCLK));
+ tmpregister = RCC->CFG;
+ pllhsipreregister = RCC->PLLHSIPRE;
+ /* Clear PLLSRC, PLLXTPRE and PLLMUL[4:0] bits */
+ tmpregister &= CFG_PLL_MASK;
+ /* Clear PLLHSIPRE, PLLSRCDIV bits */
+ pllhsipreregister &= (~(PLLHSIPRE_PLLHSI_PRE_MASK | PLLHSIPRE_PLLSRCDIV_MASK));
+ /* Set the PLL configuration bits */
+ if ((RCC_PLLSource == RCC_PLL_HSI_PRE_DIV1) || (RCC_PLLSource == RCC_PLL_HSI_PRE_DIV2))
+ {
+ tmpregister |= RCC_PLLMul;
+ pllhsipreregister |= RCC_PLLSource | RCC_PLLDIVCLK;
+ }
+ /* (RCC_PLLSource == RCC_PLL_SRC_HSE_DIV1) || (RCC_PLLSource == RCC_PLL_SRC_HSE_DIV2) */
+ else
+ {
+ tmpregister |= RCC_PLLSource | RCC_PLLMul;
+ pllhsipreregister |= RCC_PLLDIVCLK;
+ }
+ /* Store the new value */
+ RCC->CFG = tmpregister;
+ RCC->PLLHSIPRE = pllhsipreregister;
+}
+
+/**
+ * @brief Enables or disables the PLL.
+ * @note The PLL can not be disabled if it is used as system clock.
+ * @param Cmd new state of the PLL. This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnablePll(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)CTRL_PLLEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Configures the system clock (SYSCLK).
+ * @param RCC_SYSCLKSource specifies the clock source used as system clock.
+ * This parameter can be one of the following values:
+ * @arg RCC_SYSCLK_SRC_MSI HSI selected as system clock
+ * @arg RCC_SYSCLK_SRC_HSI HSI selected as system clock
+ * @arg RCC_SYSCLK_SRC_HSE HSE selected as system clock
+ * @arg RCC_SYSCLK_SRC_PLLCLK PLL selected as system clock
+ */
+void RCC_ConfigSysclk(uint32_t RCC_SYSCLKSource)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_SYSCLK_SRC(RCC_SYSCLKSource));
+ tmpregister = RCC->CFG;
+ /* Clear SW[1:0] bits */
+ tmpregister &= CFG_SCLKSW_MASK;
+ /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
+ tmpregister |= RCC_SYSCLKSource;
+ /* Store the new value */
+ RCC->CFG = tmpregister;
+}
+
+/**
+ * @brief Returns the clock source used as system clock.
+ * @return The clock source used as system clock. The returned value can
+ * be one of the following:
+ * - 0x00: MSI used as system clock
+ * - 0x04: HSI used as system clock
+ * - 0x08: HSE used as system clock
+ * - 0x0C: PLL used as system clock
+ */
+uint8_t RCC_GetSysclkSrc(void)
+{
+ return ((uint8_t)(RCC->CFG & CFG_SCLKSTS_MASK));
+}
+
+/**
+ * @brief Configures the AHB clock (HCLK).
+ * @param RCC_SYSCLK defines the AHB clock divider. This clock is derived from
+ * the system clock (SYSCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_SYSCLK_DIV1 AHB clock = SYSCLK
+ * @arg RCC_SYSCLK_DIV2 AHB clock = SYSCLK/2
+ * @arg RCC_SYSCLK_DIV4 AHB clock = SYSCLK/4
+ * @arg RCC_SYSCLK_DIV8 AHB clock = SYSCLK/8
+ * @arg RCC_SYSCLK_DIV16 AHB clock = SYSCLK/16
+ * @arg RCC_SYSCLK_DIV64 AHB clock = SYSCLK/64
+ * @arg RCC_SYSCLK_DIV128 AHB clock = SYSCLK/128
+ * @arg RCC_SYSCLK_DIV256 AHB clock = SYSCLK/256
+ * @arg RCC_SYSCLK_DIV512 AHB clock = SYSCLK/512
+ */
+void RCC_ConfigHclk(uint32_t RCC_SYSCLK)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_SYSCLK_DIV(RCC_SYSCLK));
+ tmpregister = RCC->CFG;
+ /* Clear HPRE[3:0] bits */
+ tmpregister &= CFG_AHBPRES_RESET_MASK;
+ /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
+ tmpregister |= RCC_SYSCLK;
+ /* Store the new value */
+ RCC->CFG = tmpregister;
+}
+
+/**
+ * @brief Configures the Low Speed APB clock (PCLK1).
+ * @param RCC_HCLK defines the APB1 clock divider. This clock is derived from
+ * the AHB clock (HCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_HCLK_DIV1 APB1 clock = HCLK
+ * @arg RCC_HCLK_DIV2 APB1 clock = HCLK/2
+ * @arg RCC_HCLK_DIV4 APB1 clock = HCLK/4
+ * @arg RCC_HCLK_DIV8 APB1 clock = HCLK/8
+ * @arg RCC_HCLK_DIV16 APB1 clock = HCLK/16
+ */
+void RCC_ConfigPclk1(uint32_t RCC_HCLK)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_HCLK_DIV(RCC_HCLK));
+ tmpregister = RCC->CFG;
+ /* Clear PPRE1[2:0] bits */
+ tmpregister &= CFG_APB1PRES_RESET_MASK;
+ /* Set PPRE1[2:0] bits according to RCC_HCLK value */
+ tmpregister |= RCC_HCLK;
+ /* Store the new value */
+ RCC->CFG = tmpregister;
+}
+
+/**
+ * @brief Configures the High Speed APB clock (PCLK2).
+ * @param RCC_HCLK defines the APB2 clock divider. This clock is derived from
+ * the AHB clock (HCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_HCLK_DIV1 APB2 clock = HCLK
+ * @arg RCC_HCLK_DIV2 APB2 clock = HCLK/2
+ * @arg RCC_HCLK_DIV4 APB2 clock = HCLK/4
+ * @arg RCC_HCLK_DIV8 APB2 clock = HCLK/8
+ * @arg RCC_HCLK_DIV16 APB2 clock = HCLK/16
+ */
+void RCC_ConfigPclk2(uint32_t RCC_HCLK)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_HCLK_DIV(RCC_HCLK));
+ tmpregister = RCC->CFG;
+ /* Clear PPRE2[2:0] bits */
+ tmpregister &= CFG_APB2PRES_RESET_MASK;
+ /* Set PPRE2[2:0] bits according to RCC_HCLK value */
+ tmpregister |= RCC_HCLK << 3;
+ /* Store the new value */
+ RCC->CFG = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the specified RCC interrupts.
+ * @param RccInt specifies the RCC interrupt sources to be enabled or disabled.
+ *
+ * this parameter can be any combination of the following values
+ * @arg RCC_INT_LSIRDIF LSI ready interrupt
+ * @arg RCC_INT_LSERDIF LSE ready interrupt
+ * @arg RCC_INT_HSIRDIF HSI ready interrupt
+ * @arg RCC_INT_HSERDIF HSE ready interrupt
+ * @arg RCC_INT_PLLRDIF PLL ready interrupt
+ * @arg RCC_INT_BORIF BOR interrupt
+ * @arg RCC_INT_MSIRDIF MSI ready interrupt
+ *
+ * @param Cmd new state of the specified RCC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_ConfigInt(uint8_t RccInt, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_INT(RccInt));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Perform Byte access to RCC_CLKINT bits to enable the selected interrupts */
+ *(__IO uint32_t*)CLKINT_ADDR |= (((uint32_t)RccInt) << 8);
+ }
+ else
+ {
+ /* Perform Byte access to RCC_CLKINT bits to disable the selected interrupts */
+ *(__IO uint32_t*)CLKINT_ADDR &= (~(((uint32_t)RccInt) << 8));
+ }
+}
+
+/**
+ * @brief Configures the USB clock (USBCLK).
+ * @param RCC_USBCLKSource specifies the USB clock source. This clock is
+ * derived from the PLL output.
+ * This parameter can be one of the following values:
+ * @arg RCC_USBCLK_SRC_PLLCLK_DIV1_5 PLL clock divided by 1,5 selected as USB clock source
+ * @arg RCC_USBCLK_SRC_PLLCLK_DIV1 PLL clock divided by 1 selected as USB clock source
+ * @arg RCC_USBCLK_SRC_PLLCLK_DIV2 PLL clock divided by 2 selected as USB clock source
+ * @arg RCC_USBCLK_SRC_PLLCLK_DIV3 PLL clock divided by 3 selected as USB clock source
+ */
+void RCC_ConfigUsbClk(uint32_t RCC_USBCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_USBCLK_SRC(RCC_USBCLKSource));
+ *(__IO uint32_t*)CFG_USBPRES_BB = RCC_USBCLKSource;
+ *(__IO uint32_t*)CFGR_USBPRE_BB_BIT1 = RCC_USBCLKSource >> 1;
+}
+
+/**
+ * @brief Configures the TIM1/8 clock (TIM1/8CLK).
+ * @param RCC_TIM18CLKSource specifies the TIM1/8 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_TIM18CLK_SRC_TIM18CLK
+ * @arg RCC_TIM18CLK_SRC_SYSCLK
+ */
+void RCC_ConfigTim18Clk(uint32_t RCC_TIM18CLKSource)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_TIM18CLKSRC(RCC_TIM18CLKSource));
+ tmpregister = RCC->CFG2;
+ /* Clear TIMCLK_SEL bits */
+ tmpregister &= CFG2_TIM18CLKSEL_RESET_MASK;
+ /* Set TIMCLK_SEL bits according to RCC_TIM18CLKSource value */
+ tmpregister |= RCC_TIM18CLKSource;
+ /* Store the new value */
+ RCC->CFG2 = tmpregister;
+}
+
+/**
+ * @brief Configures the RNGCCLK prescaler.
+ * @param RCC_RNGCCLKPrescaler specifies the RNGCCLK prescaler.
+ * This parameter can be one of the following values:
+ * @arg RCC_RNGCCLK_SYSCLK_DIV1 RNGCPRE[24:28] = 00000, SYSCLK Divided By 1
+ * @arg RCC_RNGCCLK_SYSCLK_DIV2 RNGCPRE[24:28] = 00001, SYSCLK Divided By 2
+ * @arg RCC_RNGCCLK_SYSCLK_DIV3 RNGCPRE[24:28] = 00002, SYSCLK Divided By 3
+ * ...
+ * @arg RCC_RNGCCLK_SYSCLK_DIV31 RNGCPRE[24:28] = 11110, SYSCLK Divided By 31
+ * @arg RCC_RNGCCLK_SYSCLK_DIV32 RNGCPRE[24:28] = 11111, SYSCLK Divided By 32
+ */
+void RCC_ConfigRngcClk(uint32_t RCC_RNGCCLKPrescaler)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_RNGCCLKPRE(RCC_RNGCCLKPrescaler));
+ tmpregister = RCC->CFG2;
+ /* Clear RNGCPRE[3:0] bits */
+ tmpregister &= CFG2_RNGCPRES_RESET_MASK;
+ /* Set RNGCPRE[3:0] bits according to RCC_RNGCCLKPrescaler value */
+ tmpregister |= RCC_RNGCCLKPrescaler;
+ /* Store the new value */
+ RCC->CFG2 = tmpregister;
+}
+
+/**
+ * @brief Configures the ADCx 1M clock (ADC1MCLK).
+ * @param RCC_ADC1MCLKSource specifies the ADC1M clock source.
+ * This parameter can be on of the following values:
+ * @arg RCC_ADC1MCLK_SRC_HSI
+ * @arg RCC_ADC1MCLK_SRC_HSE
+ *
+ * @param RCC_ADC1MPrescaler specifies the ADC1M clock prescaler.
+ * This parameter can be on of the following values:
+ * @arg RCC_ADC1MCLK_DIV1 ADC1M clock = RCC_ADC1MCLKSource_xxx/1
+ * @arg RCC_ADC1MCLK_DIV2 ADC1M clock = RCC_ADC1MCLKSource_xxx/2
+ * @arg RCC_ADC1MCLK_DIV3 ADC1M clock = RCC_ADC1MCLKSource_xxx/3
+ * ...
+ * @arg RCC_ADC1MCLK_DIV31 ADC1M clock = RCC_ADC1MCLKSource_xxx/31
+ * @arg RCC_ADC1MCLK_DIV32 ADC1M clock = RCC_ADC1MCLKSource_xxx/32
+ */
+void RCC_ConfigAdc1mClk(uint32_t RCC_ADC1MCLKSource, uint32_t RCC_ADC1MPrescaler)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_ADC1MCLKSRC(RCC_ADC1MCLKSource));
+ assert_param(IS_RCC_ADC1MCLKPRE(RCC_ADC1MPrescaler));
+ tmpregister = RCC->CFG2;
+ /* Clear ADC1MSEL and ADC1MPRE[4:0] bits */
+ tmpregister &= CFG2_ADC1MSEL_RESET_MASK;
+ tmpregister &= CFG2_ADC1MPRES_RESET_MASK;
+ /* Set ADC1MSEL bits according to RCC_ADC1MCLKSource value */
+ tmpregister |= RCC_ADC1MCLKSource;
+ /* Set ADC1MPRE[4:0] bits according to RCC_ADC1MPrescaler value */
+ tmpregister |= RCC_ADC1MPrescaler;
+ /* Store the new value */
+ RCC->CFG2 = tmpregister;
+}
+
+/**
+ * @brief Configures the ADCPLLCLK prescaler, and enable/disable ADCPLLCLK.
+ * @param RCC_ADCPLLCLKPrescaler specifies the ADCPLLCLK prescaler.
+ * This parameter can be on of the following values:
+ * @arg RCC_ADCPLLCLK_DIV1 ADCPLLCLKPRES[4:0] = 10000, Pll Clock Divided By 1
+ * @arg RCC_ADCPLLCLK_DIV2 ADCPLLCLKPRES[4:0] = 10001, Pll Clock Divided By 2
+ * @arg RCC_ADCPLLCLK_DIV4 ADCPLLCLKPRES[4:0] = 10010, Pll Clock Divided By 4
+ * @arg RCC_ADCPLLCLK_DIV6 ADCPLLCLKPRES[4:0] = 10011, Pll Clock Divided By 6
+ * @arg RCC_ADCPLLCLK_DIV8 ADCPLLCLKPRES[4:0] = 10100, Pll Clock Divided By 8
+ * @arg RCC_ADCPLLCLK_DIV10 ADCPLLCLKPRES[4:0] = 10101, Pll Clock Divided By 10
+ * @arg RCC_ADCPLLCLK_DIV12 ADCPLLCLKPRES[4:0] = 10110, Pll Clock Divided By 12
+ * @arg RCC_ADCPLLCLK_DIV16 ADCPLLCLKPRES[4:0] = 10111, Pll Clock Divided By 16
+ * @arg RCC_ADCPLLCLK_DIV32 ADCPLLCLKPRES[4:0] = 11000, Pll Clock Divided By 32
+ * @arg RCC_ADCPLLCLK_DIV64 ADCPLLCLKPRES[4:0] = 11001, Pll Clock Divided By 64
+ * @arg RCC_ADCPLLCLK_DIV128 ADCPLLCLKPRES[4:0] = 11010, Pll Clock Divided By 128
+ * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = 11011, Pll Clock Divided By 256
+ * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = others, Pll Clock Divided By 256
+ *
+ * @param Cmd specifies the ADCPLLCLK enable/disable selection.
+ * This parameter can be on of the following values:
+ * @arg ENABLE enable ADCPLLCLK
+ * @arg DISABLE disable ADCPLLCLK ADCPLLCLKPRES[4:0] = 0xxxx, ADC Pll Clock Disable
+ */
+void RCC_ConfigAdcPllClk(uint32_t RCC_ADCPLLCLKPrescaler, FunctionalState Cmd)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_ADCPLLCLKPRE(RCC_ADCPLLCLKPrescaler));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ tmpregister = RCC->CFG2;
+ /* Clear ADCPLLPRES[4:0] bits */
+ tmpregister &= CFG2_ADCPLLPRES_RESET_MASK;
+ if (Cmd != DISABLE)
+ {
+ tmpregister |= RCC_ADCPLLCLKPrescaler;
+ }
+ else
+ {
+ tmpregister |= RCC_ADCPLLCLKPrescaler;
+ tmpregister &= RCC_ADCPLLCLK_DISABLE;
+ }
+ /* Store the new value */
+ RCC->CFG2 = tmpregister;
+}
+
+/**
+ * @brief Configures the ADCHCLK prescaler.
+ * @param RCC_ADCHCLKPrescaler specifies the ADCHCLK prescaler.
+ * This parameter can be on of the following values:
+ * @arg RCC_ADCHCLK_DIV1 ADCHCLKPRE[3:0] = 0000, HCLK Clock Divided By 1
+ * @arg RCC_ADCHCLK_DIV2 ADCHCLKPRE[3:0] = 0001, HCLK Clock Divided By 2
+ * @arg RCC_ADCHCLK_DIV4 ADCHCLKPRE[3:0] = 0010, HCLK Clock Divided By 4
+ * @arg RCC_ADCHCLK_DIV6 ADCHCLKPRE[3:0] = 0011, HCLK Clock Divided By 6
+ * @arg RCC_ADCHCLK_DIV8 ADCHCLKPRE[3:0] = 0100, HCLK Clock Divided By 8
+ * @arg RCC_ADCHCLK_DIV10 ADCHCLKPRE[3:0] = 0101, HCLK Clock Divided By 10
+ * @arg RCC_ADCHCLK_DIV12 ADCHCLKPRE[3:0] = 0110, HCLK Clock Divided By 12
+ * @arg RCC_ADCHCLK_DIV16 ADCHCLKPRE[3:0] = 0111, HCLK Clock Divided By 16
+ * @arg RCC_ADCHCLK_DIV32 ADCHCLKPRE[3:0] = 1000, HCLK Clock Divided By 32
+ * @arg RCC_ADCHCLK_DIV_OTHERS ADCHCLKPRE[3:0] = others, HCLK Clock Divided By 32
+ */
+void RCC_ConfigAdcHclk(uint32_t RCC_ADCHCLKPrescaler)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_ADCHCLKPRE(RCC_ADCHCLKPrescaler));
+ tmpregister = RCC->CFG2;
+ /* Clear ADCHPRE[3:0] bits */
+ tmpregister &= CFG2_ADCHPRES_RESET_MASK;
+ /* Set ADCHPRE[3:0] bits according to RCC_ADCHCLKPrescaler value */
+ tmpregister |= RCC_ADCHCLKPrescaler;
+ /* Store the new value */
+ RCC->CFG2 = tmpregister;
+}
+
+/**
+ * @brief Configures the TRNG 1M clock (TRNG1MCLK).
+ * @param RCC_TRNG1MCLKSource specifies the TRNG1M clock source.
+ * This parameter can be on of the following values:
+ * @arg RCC_TRNG1MCLK_SRC_HSI
+ * @arg RCC_TRNG1MCLK_SRC_HSE
+ *
+ * @param RCC_TRNG1MPrescaler specifies the TRNG1M prescaler.
+ * This parameter can be on of the following values:
+ * @arg RCC_TRNG1MCLK_DIV2 TRNG1M clock = RCC_TRNG1MCLK_SRC_HSE/2
+ * @arg RCC_TRNG1MCLK_DIV4 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/4
+ * @arg RCC_TRNG1MCLK_DIV6 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/6
+ * ...
+ * @arg RCC_TRNG1MCLK_DIV60 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/60
+ * @arg RCC_TRNG1MCLK_DIV62 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/62
+ */
+void RCC_ConfigTrng1mClk(uint32_t RCC_TRNG1MCLKSource, uint32_t RCC_TRNG1MPrescaler)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_TRNG1MCLK_SRC(RCC_TRNG1MCLKSource));
+ assert_param(IS_RCC_TRNG1MCLKPRE(RCC_TRNG1MPrescaler));
+ tmpregister = RCC->CFG3;
+ /* Clear TRNG1MSEL and TRNG1MPRE[4:0] bits */
+ tmpregister &= CFGR3_TRNG1MSEL_RESET_MASK;
+ tmpregister &= CFGR3_TRNG1MPRES_RESET_MASK;
+ /* Set TRNG1MSEL bits according to RCC_TRNG1MCLKSource value */
+ tmpregister |= RCC_TRNG1MCLKSource;
+ /* Set TRNG1MPRE[4:0] bits according to RCC_TRNG1MPrescaler value */
+ tmpregister |= RCC_TRNG1MPrescaler;
+ /* Store the new value */
+ RCC->CFG3 = tmpregister;
+}
+
+/**
+ * @brief Enable/disable TRNG clock (TRNGCLK).
+ * @param Cmd specifies the TRNGCLK enable/disable selection.
+ * This parameter can be on of the following values:
+ * @arg ENABLE enable TRNGCLK
+ * @arg DISABLE disable TRNGCLK
+ */
+void RCC_EnableTrng1mClk(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ RCC->CFG3 |= RCC_TRNG1MCLK_ENABLE;
+ }
+ else
+ {
+ RCC->CFG3 &= RCC_TRNG1MCLK_DISABLE;
+ }
+}
+
+/**
+ * @brief Configures the UCDR clock.
+ * @param RCC_UCDR300MSource specifies the UCDR clock source.
+ * This parameter can be on of the following values:
+ * @arg RCC_UCDR300M_SRC_OSC300M
+ * @arg RCC_UCDR300M_SRC_PLLVCO
+ *
+ * @param Cmd enable/disable selection.
+ * This parameter can be on of the following values:
+ * @arg ENABLE enable UCDR
+ * @arg DISABLE disable UCDR
+ */
+void RCC_ConfigUCDRClk(uint32_t RCC_UCDR300MSource, FunctionalState Cmd)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_UCDR300M_SRC(RCC_UCDR300MSource));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ tmpregister = RCC->CFG3;
+ /* Clear UCDR300MSEL bits */
+ tmpregister &= RCC_UCDR300MSource_MASK;
+ /* Set UCDR300MSEL bits */
+ tmpregister |= RCC_UCDR300MSource;
+ /* Store the new value */
+ RCC->CFG3 = tmpregister;
+ if (Cmd != DISABLE)
+ {
+ RCC->CFG3 |= RCC_UCDR_ENABLE;
+ }
+ else
+ {
+ RCC->CFG3 &= RCC_UCDR_DISABLE;
+ }
+}
+
+/**
+ * @brief Configures the USB Crystal Mode.
+ * @param RCC_USBXTALESSMode specifies the USB Crystal Mode.
+ * This parameter can be one of the following values:
+ * @arg RCC_USBXTALESS_MODE USB work in crystal mode
+ * @arg RCC_USBXTALESS_LESSMODE USB work in crystalless mode
+ */
+void RCC_ConfigUSBXTALESSMode(uint32_t RCC_USBXTALESSMode)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_USBXTALESS_MODE(RCC_USBXTALESSMode));
+ /* Clear the USB Crystal Mode bit */
+ RCC->CFG3 &= RCC_USBXTALESSMode_MASK;
+ /* Select the USB Crystal Mode */
+ RCC->CFG3 |= RCC_USBXTALESSMode;
+}
+
+/**
+ * @brief Enables or disables the RET peripheral clock.
+ * @param RCC_RETPeriph specifies the RET peripheral to gates its clock.
+ *
+ * this parameter can be any combination of the following values:
+ * @arg RCC_RET_PERIPH_LPTIM
+ * @arg RCC_RET_PERIPH_LPUART
+ * @arg RCC_RET_PERIPH_LCD
+ * @arg RCC_RET_PERIPH_LPRCNT
+ *
+ * @param Cmd new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableRETPeriphClk(uint32_t RCC_RETPeriph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_RET_PERIPH(RCC_RETPeriph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ RCC->RDCTRL |= RCC_RETPeriph;
+ }
+ else
+ {
+ RCC->RDCTRL &= ~RCC_RETPeriph;
+ }
+}
+
+/**
+ * @brief Forces or releases RET peripheral reset.
+ * @param RCC_RETPeriph specifies the RET peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_RET_PERIPH_LPTIM.
+ * RCC_RET_PERIPH_LPUART.
+ * RCC_RET_PERIPH_LCD.
+ * RCC_RET_PERIPH_LPRCNT.
+ * @param Cmd new state of the specified peripheral reset. This parameter can be ENABLE or DISABLE.
+ */
+void RCC_EnableRETPeriphReset(uint32_t RCC_RETPeriph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_RET_PERIPH(RCC_RETPeriph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ RCC->RDCTRL |= (RCC_RETPeriph << 4);
+ }
+ else
+ {
+ RCC->RDCTRL &= ~(RCC_RETPeriph << 4);
+ }
+}
+
+/**
+ * @brief Configures the LPTIM clock (LPTIMCLK).
+ * @param RCC_LPTIMCLKSource specifies the LPTIM clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_LPTIMCLK_SRC_APB1 APB1 clock selected as LPTIM clock
+ * @arg RCC_LPTIMCLK_SRC_LSI LSI selected as LPTIM clock
+ * @arg RCC_LPTIMCLK_SRC_HSI HSI selected as LPTIM clock
+ * @arg RCC_LPTIMCLK_SRC_LSE LSE selected as LPTIM clock
+ * @arg RCC_LPTIMCLK_SRC_COMP1 COMP1 output selected as LPTIM clock
+ * @arg RCC_LPTIMCLK_SRC_COMP2 COMP2 output selected as LPTIM clock
+ * @note When switching from comparator1/2 to other clock sources,
+ * it is suggested to disable comparators first.
+ */
+void RCC_ConfigLPTIMClk(uint32_t RCC_LPTIMCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_LPTIM_CLK(RCC_LPTIMCLKSource));
+ //PWR DBP set 1
+ RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR, ENABLE);
+ PWR->CTRL1 |= 0x100;
+ /* Clear the LPTIM clock source */
+ RCC->RDCTRL &= RCC_LPTIMCLK_SRC_MASK;
+ /* Select the LPTIM clock source */
+ RCC->RDCTRL |= RCC_LPTIMCLKSource;
+}
+
+/**
+ * @brief Returns the clock source used as LPTIM clock (LPTIMCLK).
+ * @return The clock source used as system clock. The returned value can
+ * be one of the following:
+ * - RCC_LPTIMCLK_SRC_APB1 APB1 clock selected as LPTIM clock
+ * - RCC_LPTIMCLK_SRC_LSI LSI selected as LPTIM clock
+ * - RCC_LPTIMCLK_SRC_HSI HSI selected as LPTIM clock
+ * - RCC_LPTIMCLK_SRC_LSE LSE selected as LPTIM clock
+ * - RCC_LPTIMCLK_SRC_COMP1 COMP1 output selected as LPTIM clock
+ * - RCC_LPTIMCLK_SRC_COMP2 COMP2 output selected as LPTIM clock
+ */
+uint32_t RCC_GetLPTIMClkSrc(void)
+{
+ return ((uint32_t)(RCC->RDCTRL & RDCTRL_LPTIMCLKSEL_MASK));
+}
+
+/**
+ * @brief Configures the LPUART clock (LPUARTCLK).
+ * @param RCC_LPUARTCLKSource specifies the LPUART clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_LPUARTCLK_SRC_APB1 APB1 clock selected as LPTIM clock
+ * @arg RCC_LPUARTCLK_SRC_SYSCLK SYSCLK selected as LPTIM clock
+ * @arg RCC_LPUARTCLK_SRC_HSI HSI selected as LPTIM clock
+ * @arg RCC_LPUARTCLK_SRC_LSE LSE selected as LPTIM clock
+ */
+void RCC_ConfigLPUARTClk(uint32_t RCC_LPUARTCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_LPUART_CLK(RCC_LPUARTCLKSource));
+ /* Clear the LPUART clock source */
+ RCC->RDCTRL &= RCC_LPUARTCLK_SRC_MASK;
+ /* Select the LPTIM clock source */
+ RCC->RDCTRL |= RCC_LPUARTCLKSource;
+}
+
+/**
+ * @brief Returns the clock source used as LPUART clock.
+ * @return The clock source used as system clock. The returned value can
+ * be one of the following:
+ * - RCC_RDCTRL_LPUARTSEL_APB1: APB1 used as LPUART clock
+ * - RCC_RDCTRL_LPUARTSEL_SYSCLK: SYSCLK used as LPUART clock
+ * - RCC_RDCTRL_LPUARTSEL_HSI: HSI used as LPUART clock
+ * - RCC_RDCTRL_LPUARTSEL_LSE: LSE used as LPUART clock
+ */
+uint32_t RCC_GetLPUARTClkSrc(void)
+{
+ return ((uint32_t)(RCC->RDCTRL & RDCTRL_LPUARTCLKSEL_MASK));
+}
+
+/**
+ * @brief Enables or disables the specified SRAM1/2 parity error interrupts.
+ * @param SramErrorInt specifies the SRAM1/2 interrupt sources to be enabled or disabled.
+ *
+ * this parameter can be any combination of the following values
+ * @arg SRAM1_PARITYERROR_INT SRAM1 parity interrupt
+ * @arg SRAM2_PARITYERROR_INT SRAM2 parity interrupt
+ *
+ * @param Cmd new state of the specified SRAM1/2 parity error interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_ConfigSRAMParityErrorInt(uint32_t SramErrorInt, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_SRAMERRORINT(SramErrorInt));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set ERR1EN/ERR2EN bit to enable the selected parity error interrupts */
+ RCC->SRAM_CTRLSTS |= SramErrorInt;
+ }
+ else
+ {
+ /* Clear ERR1EN/ERR2EN bit to disable the selected parity error interrupts */
+ RCC->SRAM_CTRLSTS &= (~SramErrorInt);
+ }
+}
+
+/**
+ * @brief Enables or disables the specified SRAM1/2 parity error reset.
+ * @param SramErrorReset specifies the SRAM1/2 parity error reset to be enabled or disabled.
+ *
+ * this parameter can be any combination of the following values
+ * @arg SRAM1_PARITYERROR_RESET SRAM1 parity error reset
+ * @arg SRAM2_PARITYERROR_RESET SRAM2 parity error reset
+ *
+ * @param Cmd new state of the specified SRAM1/2 parity error reset.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_ConfigSRAMParityErrorRESET(uint32_t SramErrorReset, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_SRAMERRORRESET(SramErrorReset));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set ERR1EN/ERR2EN bit to enable SRAM1/2 parity error reset */
+ RCC->SRAM_CTRLSTS |= SramErrorReset;
+ }
+ else
+ {
+ /* Clear ERR1EN/ERR2EN bit to disable SRAM1/2 parity error reset */
+ RCC->SRAM_CTRLSTS &= (~SramErrorReset);
+ }
+}
+
+/**
+ * @brief Clears the specified SRAM1/2 parity error flag.
+ * @param SramErrorReset specifies the SRAM1/2 parity error flag.
+ *
+ * this parameter can be any combination of the following values
+ * @arg SRAM1_PARITYERROR_FLAG SRAM1 parity error flag
+ * @arg SRAM2_PARITYERROR_FLAG SRAM2 parity error flag
+ */
+void RCC_ClrSRAMParityErrorFlag(uint32_t SramErrorflag)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_SRAMERRORFLAG(SramErrorflag));
+ RCC->SRAM_CTRLSTS |= SramErrorflag;
+}
+
+/**
+ * @brief Configures the External Low Speed oscillator (LSE) Xtal bias.
+ * @param LSE_Trim specifies LSE Driver Trim Level.
+ * Trim value rang 0x0~0x1FF
+ */
+void LSE_XtalConfig(uint16_t LSE_Trim)
+{
+ uint32_t tmpregister = 0;
+ tmpregister = *(__IO uint32_t*)LSE_TRIMR_ADDR;
+ //clear lse trim[8:0]
+ tmpregister &= (~(LSE_GM_MASK_VALUE));
+ (LSE_Trim>LSE_GM_MAX_VALUE) ? (LSE_Trim=LSE_GM_DEFAULT_VALUE):(LSE_Trim&=LSE_GM_MASK_VALUE);
+ tmpregister |= LSE_Trim;
+ *(__IO uint32_t*)LSE_TRIMR_ADDR = tmpregister;
+}
+
+/**
+ * @brief Configures the External Low Speed oscillator (LSE).
+ * @param RCC_LSE specifies the new state of the LSE.
+ * This parameter can be one of the following values:
+ * @arg RCC_LSE_DISABLE LSE oscillator OFF
+ * @arg RCC_LSE_ENABLE LSE oscillator ON
+ * @arg RCC_LSE_BYPASS LSE oscillator bypassed with external clock
+ * @param LSE_Trim specifies LSE Driver Trim Level.
+ * Trim value rang 0x00~0x1FF
+ */
+void RCC_ConfigLse(uint8_t RCC_LSE,uint16_t LSE_Trim)
+{
+ //PWR DBP set 1
+ /* Enable PWR Clock */
+ RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR, ENABLE);
+ PWR->CTRL1 |= 0x100;
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE(RCC_LSE));
+ /* Reset LSEEN LSEBYP and LSECLKSSEN bits before configuring the LSE ------------------*/
+ *(__IO uint32_t*)LDCTRL_ADDR &= (~(RCC_LDCTRL_LSEEN | RCC_LDCTRL_LSEBP | RCC_LDCTRL_LSECLKSSEN));
+ /* Configure LSE (RCC_LSE_DISABLE is already covered by the code section above) */
+ switch (RCC_LSE)
+ {
+ case RCC_LSE_ENABLE:
+ /* Set LSEON bit */
+ *(__IO uint32_t*)LDCTRL_ADDR |= RCC_LSE_ENABLE;
+ LSE_XtalConfig(LSE_Trim);
+ break;
+ case RCC_LSE_BYPASS:
+ /* Set LSEBYP and LSEON bits */
+ *(__IO uint32_t*)LDCTRL_ADDR |= (RCC_LSE_BYPASS | RCC_LSE_ENABLE);
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Enables or disables the Internal Low Speed oscillator (LSI).
+ * @note LSI can not be disabled if the IWDG is running.
+ * @param Cmd new state of the LSI. This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableLsi(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)CTRLSTS_LSIEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Configures the RTC clock (RTCCLK).
+ * @note Once the RTC clock is selected it can't be changed unless the LowPower domain is reset.
+ * @param RCC_RTCCLKSource specifies the RTC clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_RTCCLK_SRC_NONE: No clock selected as RTC clock
+ * @arg RCC_RTCCLK_SRC_LSE: LSE selected as RTC clock
+ * @arg RCC_RTCCLK_SRC_LSI: LSI selected as RTC clock
+ * @arg RCC_RTCCLK_SRC_HSE_DIV32: HSE clock divided by 32 selected as RTC clock
+ */
+void RCC_ConfigRtcClk(uint32_t RCC_RTCCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_RTCCLK_SRC(RCC_RTCCLKSource));
+ /* Clear the RTC clock source */
+ RCC->LDCTRL &= (~RCC_LDCTRL_RTCSEL);
+ /* Select the RTC clock source */
+ RCC->LDCTRL |= RCC_RTCCLKSource;
+}
+
+/**
+ * @brief Returns the clock source used as RTC clock (RTCCLK).
+ * @return The clock source used as system clock. The returned value can
+ * be one of the following:
+ * - RCC_RTCCLK_SRC_NONE: No clock used as RTC clock (RTCCLK)
+ * - RCC_RTCCLK_SRC_LSE: LSE used as RTC clock (RTCCLK)
+ * - RCC_RTCCLK_SRC_LSI: LSI used as RTC clock (RTCCLK)
+ * - RCC_RTCCLK_SRC_HSE_DIV32: HSE clock divided by 32 used as RTC clock (RTCCLK)
+ */
+uint32_t RCC_GetRTCClkSrc(void)
+{
+ return ((uint32_t)(RCC->LDCTRL & RCC_LDCTRL_RTCSEL));
+}
+
+/**
+ * @brief Enables or disables the RTC clock.
+ * @note This function must be used only after the RTC clock was selected using the RCC_ConfigRtcClk function.
+ * @param Cmd new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableRtcClk(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)LDCTRL_RTCEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Configures the LSX clock (for TSC/LPRCNT).
+ * @note Once the LSX clock is selected it can't be changed unless the LowPower domain is reset.
+ * @param RCC_RTCCLKSource specifies the RTC clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_LSXCLK_SRC_LSI LSI selected as RTC clock
+ * @arg RCC_LSXCLK_SRC_LSE LSE selected as RTC clock
+ */
+void RCC_ConfigLSXClk(uint32_t RCC_LSXCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_LSXCLK_SRC(RCC_LSXCLKSource));
+ /* Clear the LSX clock source */
+ RCC->LDCTRL &= (~RCC_LDCTRL_LSXSEL);
+ /* Select the LSX clock source */
+ RCC->LDCTRL |= RCC_LSXCLKSource;
+}
+
+/**
+ * @brief Returns the clock source used as LSX clock (for TSC/LPRCNT).
+ * @return The clock source used as system clock. The returned value can
+ * be one of the following:
+ * - RCC_LSXCLK_SRC_LSI: LSI used as LSX clock (for TSC/LPRCNT)
+ * - RCC_LSXCLK_SRC_LSE: LSE used as LSX clock (for TSC/LPRCNT)
+ */
+uint32_t RCC_GetLSXClkSrc(void)
+{
+ return ((uint32_t)(RCC->LDCTRL & RCC_LDCTRL_LSXSEL));
+}
+
+/**
+ * @brief Returns the frequencies of different on chip clocks.
+ * @param RCC_Clocks pointer to a RCC_ClocksType structure which will hold
+ * the clocks frequencies.
+ * @note The result of this function could be not correct when using
+ * fractional value for HSE crystal.
+ */
+void RCC_GetClocksFreqValue(RCC_ClocksType* RCC_Clocks)
+{
+ uint32_t tmp = 0, pllclk = 0, pllmull = 0, pllsource = 0, presc = 0;
+ uint8_t msi_clk = 0;
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFG & CFG_PLLMULFCT_MASK;
+ pllsource = RCC->CFG & CFG_PLLSRC_MASK;
+ /* Get MSI clock --------------------------------------------------------*/
+ msi_clk = (uint8_t) ((RCC->CTRLSTS & RCC_CTRLSTS_MSIRANGE)>>4);
+ if ((pllmull & RCC_CFG_PLLMULFCT_4) == 0)
+ {
+ pllmull = (pllmull >> 18) + 2; // PLLMUL[4]=0
+ }
+ else
+ {
+ pllmull = ((pllmull >> 18) - 496) + 1; // PLLMUL[4]=1
+ }
+ if (pllsource == 0x00)
+ {
+ /* HSI selected as PLL clock entry */
+ if ((RCC->PLLHSIPRE & PLLHSIPRE_PLLHSI_PRE_MASK) != (uint32_t)RESET)
+ { /* HSI oscillator clock divided by 2 */
+ pllclk = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ pllclk = HSI_VALUE * pllmull;
+ }
+
+ }
+ else
+ {
+ /* HSE selected as PLL clock entry */
+ if ((RCC->CFG & CFG_PLLHSEPRES_MASK) != (uint32_t)RESET)
+ { /* HSE oscillator clock divided by 2 */
+ pllclk = (HSE_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ pllclk = HSE_VALUE * pllmull;
+ }
+ }
+ /* PLL Div clock */
+ if ((RCC->PLLHSIPRE & PLLHSIPRE_PLLSRCDIV_MASK) != (uint32_t)RESET)
+ { /* PLL clock divided by 2 */
+ pllclk = (pllclk >> 1);
+ }
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFG & CFG_SCLKSTS_MASK;
+ switch (tmp)
+ {
+ case 0x00: /* MSI used as system clock */
+ RCC_Clocks->SysclkFreq = s_msiClockTable[msi_clk];
+ break;
+ case 0x04: /* HSI used as system clock */
+ RCC_Clocks->SysclkFreq = HSI_VALUE;
+ break;
+ case 0x08: /* HSE used as system clock */
+ RCC_Clocks->SysclkFreq = HSE_VALUE;
+ break;
+ case 0x0C: /* PLL used as system clock */
+ RCC_Clocks->SysclkFreq = pllclk;
+ break;
+ default:
+ RCC_Clocks->SysclkFreq = s_msiClockTable[msi_clk];
+ break;
+ }
+ /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
+ /* Get HCLK prescaler */
+ tmp = RCC->CFG & CFG_AHBPRES_SET_MASK;
+ tmp = tmp >> 4;
+ presc = s_ApbAhbPresTable[tmp];
+ /* HCLK clock frequency */
+ RCC_Clocks->HclkFreq = RCC_Clocks->SysclkFreq >> presc;
+ /* Get PCLK1 prescaler */
+ tmp = RCC->CFG & CFG_APB1PRES_SET_MASK;
+ tmp = tmp >> 8;
+ presc = s_ApbAhbPresTable[tmp];
+ /* PCLK1 clock frequency */
+ RCC_Clocks->Pclk1Freq = RCC_Clocks->HclkFreq >> presc;
+ /* Get PCLK2 prescaler */
+ tmp = RCC->CFG & CFG_APB2PRES_SET_MASK;
+ tmp = tmp >> 11;
+ presc = s_ApbAhbPresTable[tmp];
+ /* PCLK2 clock frequency */
+ RCC_Clocks->Pclk2Freq = RCC_Clocks->HclkFreq >> presc;
+ /* Get ADCHCLK prescaler */
+ tmp = RCC->CFG2 & CFG2_ADCHPRES_SET_MASK;
+ presc = s_AdcHclkPresTable[tmp];
+ /* ADCHCLK clock frequency */
+ RCC_Clocks->AdcHclkFreq = RCC_Clocks->HclkFreq / presc;
+ /* Get ADCPLLCLK prescaler */
+ tmp = RCC->CFG2 & CFG2_ADCPLLPRES_SET_MASK;
+ tmp = tmp >> 4;
+ presc = s_AdcPllClkPresTable[(tmp & 0xF)]; // ignore BIT5
+ /* ADCPLLCLK clock frequency */
+ RCC_Clocks->AdcPllClkFreq = pllclk / presc;
+}
+
+/**
+ * @brief Enables or disables the AHB peripheral clock.
+ * @param RCC_AHBPeriph specifies the AHB peripheral to gates its clock.
+ *
+ * this parameter can be any combination of the following values:
+ * @arg RCC_AHB_PERIPH_DMA
+ * @arg RCC_AHB_PERIPH_SRAM
+ * @arg RCC_AHB_PERIPH_FLITF
+ * @arg RCC_AHB_PERIPH_CRC
+ * @arg RCC_AHB_PERIPH_RNGC
+ * @arg RCC_AHB_PERIPH_SAC
+ * @arg RCC_AHB_PERIPH_ADC
+ *
+ * @note SRAM and FLITF clock can be disabled only during sleep mode.
+ * @param Cmd new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableAHBPeriphClk(uint32_t RCC_AHBPeriph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ RCC->AHBPCLKEN |= RCC_AHBPeriph;
+ }
+ else
+ {
+ RCC->AHBPCLKEN &= ~RCC_AHBPeriph;
+ }
+}
+
+/**
+ * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
+ * @param RCC_APB2Periph specifies the APB2 peripheral to gates its clock.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB2_PERIPH_AFIO, RCC_APB2_PERIPH_GPIOA, RCC_APB2_PERIPH_GPIOB,
+ * RCC_APB2_PERIPH_GPIOC, RCC_APB2_PERIPH_GPIOD, RCC_APB2_PERIPH_TIM1,
+ * RCC_APB2_PERIPH_SPI1, RCC_APB2_PERIPH_TIM8, RCC_APB2_PERIPH_USART1,
+ * RCC_APB2_PERIPH_UART4, RCC_APB2_PERIPH_UART5, RCC_APB2_PERIPH_SPI2
+ * @param Cmd new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableAPB2PeriphClk(uint32_t RCC_APB2Periph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ RCC->APB2PCLKEN |= RCC_APB2Periph;
+ }
+ else
+ {
+ RCC->APB2PCLKEN &= ~RCC_APB2Periph;
+ }
+}
+
+/**
+ * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
+ * @param RCC_APB1Periph specifies the APB1 peripheral to gates its clock.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB1_PERIPH_TIM2, RCC_APB1_PERIPH_TIM3, RCC_APB1_PERIPH_TIM4,
+ * RCC_APB1_PERIPH_TIM5, RCC_APB1_PERIPH_TIM6, RCC_APB1_PERIPH_TIM7,
+ * RCC_APB1_PERIPH_COMP, RCC_APB1_PERIPH_COMP_FILT, RCC_APB1_PERIPH_AFEC,
+ * RCC_APB1_PERIPH_TIM9, RCC_APB1_PERIPH_TSC, RCC_APB1_PERIPH_WWDG,
+ * RCC_APB1_PERIPH_USART2, RCC_APB1_PERIPH_USART3, RCC_APB1_PERIPH_I2C1,
+ * RCC_APB1_PERIPH_I2C2, RCC_APB1_PERIPH_USB, RCC_APB1_PERIPH_CAN,
+ * RCC_APB1_PERIPH_PWR, RCC_APB1_PERIPH_DAC, RCC_APB1_PERIPH_OPAMP
+ *
+ * @param Cmd new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableAPB1PeriphClk(uint32_t RCC_APB1Periph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ RCC->APB1PCLKEN |= RCC_APB1Periph;
+ }
+ else
+ {
+ RCC->APB1PCLKEN &= ~RCC_APB1Periph;
+ }
+}
+
+/**
+ * @brief Forces or releases AHB peripheral reset.
+ * @param RCC_AHBPeriph specifies the AHB peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_AHB_PERIPH_ADC.
+ * RCC_AHB_PERIPH_SAC.
+ * RCC_AHB_PERIPH_RNGC.
+ * @param Cmd new state of the specified peripheral reset. This parameter can be ENABLE or DISABLE.
+ */
+void RCC_EnableAHBPeriphReset(uint32_t RCC_AHBPeriph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ RCC->AHBPRST |= RCC_AHBPeriph;
+ }
+ else
+ {
+ RCC->AHBPRST &= ~RCC_AHBPeriph;
+ }
+}
+
+/**
+ * @brief Forces or releases High Speed APB (APB2) peripheral reset.
+ * @param RCC_APB2Periph specifies the APB2 peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB2_PERIPH_AFIO, RCC_APB2_PERIPH_GPIOA, RCC_APB2_PERIPH_GPIOB,
+ * RCC_APB2_PERIPH_GPIOC, RCC_APB2_PERIPH_GPIOD, RCC_APB2_PERIPH_TIM1,
+ * RCC_APB2_PERIPH_SPI1, RCC_APB2_PERIPH_TIM8, RCC_APB2_PERIPH_USART1,
+ * RCC_APB2_PERIPH_UART4, RCC_APB2_PERIPH_UART5, RCC_APB2_PERIPH_SPI2
+ * @param Cmd new state of the specified peripheral reset.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableAPB2PeriphReset(uint32_t RCC_APB2Periph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ RCC->APB2PRST |= RCC_APB2Periph;
+ }
+ else
+ {
+ RCC->APB2PRST &= ~RCC_APB2Periph;
+ }
+}
+
+/**
+ * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
+ * @param RCC_APB1Periph specifies the APB1 peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB1_PERIPH_TIM2, RCC_APB1_PERIPH_TIM3, RCC_APB1_PERIPH_TIM4,
+ * RCC_APB1_PERIPH_TIM5, RCC_APB1_PERIPH_TIM6, RCC_APB1_PERIPH_TIM7,
+ * RCC_APB1_PERIPH_COMP, RCC_APB1_PERIPH_COMP_FILT, RCC_APB1_PERIPH_AFEC,
+ * RCC_APB1_PERIPH_TIM9, RCC_APB1_PERIPH_TSC, RCC_APB1_PERIPH_WWDG,
+ * RCC_APB1_PERIPH_USART2, RCC_APB1_PERIPH_USART3, RCC_APB1_PERIPH_I2C1,
+ * RCC_APB1_PERIPH_I2C2, RCC_APB1_PERIPH_USB, RCC_APB1_PERIPH_CAN,
+ * RCC_APB1_PERIPH_PWR, RCC_APB1_PERIPH_DAC, RCC_APB1_PERIPH_OPAMP
+ * @param Cmd new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableAPB1PeriphReset(uint32_t RCC_APB1Periph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ RCC->APB1PRST |= RCC_APB1Periph;
+ }
+ else
+ {
+ RCC->APB1PRST &= ~RCC_APB1Periph;
+ }
+}
+
+/**
+ * @brief Forces or releases the LowPower domain reset.
+ * @param Cmd new state of the Backup domain reset.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableLowPowerReset(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)LDCTRL_LDSFTRST_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Enables or disables the Clock Security System.
+ * @param Cmd new state of the Clock Security System..
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableClockSecuritySystem(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)CTRL_CLKSSEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Enables or disables the LSE Clock Security System.
+ * @param Cmd new state of the LSE Clock Security System..
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableLSEClockSecuritySystem(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)LDCTRL_LSECLKSSEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Get LSE Clock Security System failure status.
+ * @return LSE Clock Security System failure status (SET or RESET).
+ */
+FlagStatus RCC_GetLSEClockSecuritySystemStatus(void)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the status of LSE Clock Security System */
+ if ((RCC->LDCTRL & RCC_LDCTRL_LSECLKSSF) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return LSE Clock Security System status */
+ return bitstatus;
+}
+
+/**
+ * @brief Configures the MCO PLL clock prescaler.
+ * @param RCC_MCOPLLCLKPrescaler specifies the MCO PLL clock prescaler.
+ * This parameter can be on of the following values:
+ * @arg RCC_MCO_CLK_NUM0 MCOPRE[3:0] = 0000, PLL Clock Divided By 1, Duty cycle = clock source
+ * @arg RCC_MCO_CLK_NUM1 MCOPRE[3:0] = 0001, PLL Clock Divided By 2, Duty cycle = 1/((MCOPRE[3:0]+1)*2)
+ * @arg RCC_MCO_CLK_NUM2 MCOPRE[3:0] = 0010, PLL Clock Divided By 3, Duty cycle = 1/((MCOPRE[3:0]+1)*2)
+ * @arg RCC_MCO_CLK_NUM3 MCOPRE[3:0] = 0011, PLL Clock Divided By 4, Duty cycle = 1/((MCOPRE[3:0]+1)*2)
+ * @arg RCC_MCO_CLK_NUM4 MCOPRE[3:0] = 0100, PLL Clock Divided By 5, Duty cycle = 1/((MCOPRE[3:0]+1)*2)
+ * @arg RCC_MCO_CLK_NUM5 MCOPRE[3:0] = 0101, PLL Clock Divided By 6, Duty cycle = 1/((MCOPRE[3:0]+1)*2)
+ * @arg RCC_MCO_CLK_NUM6 MCOPRE[3:0] = 0110, PLL Clock Divided By 7, Duty cycle = 1/((MCOPRE[3:0]+1)*2)
+ * @arg RCC_MCO_CLK_NUM7 MCOPRE[3:0] = 0111, PLL Clock Divided By 8, Duty cycle = 1/((MCOPRE[3:0]+1)*2)
+ * @arg RCC_MCO_CLK_NUM8 MCOPRE[3:0] = 1000, PLL Clock Divided By 2, Duty cycle = 50%
+ * @arg RCC_MCO_CLK_NUM9 MCOPRE[3:0] = 1001, PLL Clock Divided By 4, Duty cycle = 50%
+ * @arg RCC_MCO_CLK_NUM10 MCOPRE[3:0] = 1010, PLL Clock Divided By 6, Duty cycle = 50%
+ * @arg RCC_MCO_CLK_NUM11 MCOPRE[3:0] = 1011, PLL Clock Divided By 8, Duty cycle = 50%
+ * @arg RCC_MCO_CLK_NUM12 MCOPRE[3:0] = 1100, PLL Clock Divided By 10, Duty cycle = 50%
+ * @arg RCC_MCO_CLK_NUM13 MCOPRE[3:0] = 1101, PLL Clock Divided By 12, Duty cycle = 50%
+ * @arg RCC_MCO_CLK_NUM14 MCOPRE[3:0] = 1110, PLL Clock Divided By 14, Duty cycle = 50%
+ * @arg RCC_MCO_CLK_NUM15 MCOPRE[3:0] = 1111, PLL Clock Divided By 16, Duty cycle = 50%
+ */
+void RCC_ConfigMcoClkPre(uint32_t RCC_MCOCLKPrescaler)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_MCOCLKPRE(RCC_MCOCLKPrescaler));
+ tmpregister = RCC->CFG;
+ /* Clear MCOPRE[3:0] bits */
+ tmpregister &= ((uint32_t)0x0FFFFFFF);
+ /* Set MCOPRE[3:0] bits according to RCC_ADCHCLKPrescaler value */
+ tmpregister |= RCC_MCOCLKPrescaler;
+ /* Store the new value */
+ RCC->CFG = tmpregister;
+}
+
+/**
+ * @brief Selects the clock source to output on MCO pin.
+ * @param RCC_MCO specifies the clock source to output.
+ *
+ * this parameter can be one of the following values:
+ * @arg RCC_MCO_NOCLK No clock selected
+ * @arg RCC_MCO_LSI LSI oscillator clock selected
+ * @arg RCC_MCO_LSE LSE oscillator clock selected
+ * @arg RCC_MCO_MSI MSI oscillator clock selected
+ * @arg RCC_MCO_SYSCLK System clock selected
+ * @arg RCC_MCO_HSI HSI oscillator clock selected
+ * @arg RCC_MCO_HSE HSE oscillator clock selected
+ * @arg RCC_MCO_PLLCLK PLL clock selected
+ *
+ */
+void RCC_ConfigMco(uint8_t RCC_MCO)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_MCO(RCC_MCO));
+ tmpregister = RCC->CFG;
+ /* Clear MCO[2:0] bits */
+ tmpregister &= ((uint32_t)0xF8FFFFFF);
+ /* Set MCO[2:0] bits according to RCC_MCO value */
+ tmpregister |= ((uint32_t)(RCC_MCO << 24));
+ /* Store the new value */
+ RCC->CFG = tmpregister;
+}
+
+/**
+ * @brief Checks whether the specified RCC flag is set or not.
+ * @param RCC_FLAG specifies the flag to check.
+ *
+ * this parameter can be one of the following values:
+ * @arg RCC_CTRL_FLAG_HSIRDF HSI oscillator clock ready
+ * @arg RCC_CTRL_FLAG_HSERDF HSE oscillator clock ready
+ * @arg RCC_CTRL_FLAG_PLLRDF PLL clock ready
+ * @arg RCC_LDCTRL_FLAG_LSERD LSE oscillator clock ready
+ * @arg RCC_LDCTRL_FLAG_LSECLKSSF LSE Clock Security System failure status
+ * @arg RCC_LDCTRL_FLAG_BORRSTF BOR reset flag
+ * @arg RCC_LDCTRL_FLAG_LDEMCRSTF LowPower EMC reset flag
+ * @arg RCC_CTRLSTS_FLAG_LSIRD LSI oscillator clock ready
+ * @arg RCC_CTRLSTS_FLAG_MSIRD MSI oscillator clock ready
+ * @arg RCC_CTRLSTS_FLAG_RAMRSTF RAM reset flag
+ * @arg RCC_CTRLSTS_FLAG_MMURSTF MMU reset flag
+ * @arg RCC_CTRLSTS_FLAG_PINRSTF Pin reset
+ * @arg RCC_CTRLSTS_FLAG_PORRSTF POR reset
+ * @arg RCC_CTRLSTS_FLAG_SFTRSTF Software reset
+ * @arg RCC_CTRLSTS_FLAG_IWDGRSTF Independent Watchdog reset
+ * @arg RCC_CTRLSTS_FLAG_WWDGRSTF Window Watchdog reset
+ * @arg RCC_CTRLSTS_FLAG_LPWRRSTF Low Power reset
+ *
+ * @return The new state of RCC_FLAG (SET or RESET).
+ */
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
+{
+ uint32_t tmp = 0;
+ uint32_t statusreg = 0;
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_RCC_FLAG(RCC_FLAG));
+
+ /* Get the RCC register index */
+ tmp = RCC_FLAG >> 5;
+ if (tmp == 1) /* The flag to check is in CTRL register */
+ {
+ statusreg = RCC->CTRL;
+ }
+ else if (tmp == 2) /* The flag to check is in BDCTRL register */
+ {
+ statusreg = RCC->LDCTRL;
+ }
+ else /* The flag to check is in CTRLSTS register */
+ {
+ statusreg = RCC->CTRLSTS;
+ }
+ /* Get the flag position */
+ tmp = RCC_FLAG & FLAG_MASK;
+ if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RCC reset flags.
+ * @note The reset flags are: RCC_FLAG_LPEMCRST, RCC_FLAG_BORRST, RCC_FLAG_RAMRST, RCC_FLAG_MMURST,
+ * RCC_FLAG_PINRST, RCC_FLAG_PORRST,RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST,
+ * RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
+ */
+void RCC_ClrFlag(void)
+{
+ /* Set RMVF bit to clear the reset flags */
+ RCC->CTRLSTS |= CSR_RMRSTF_SET;
+ /* RMVF bit should be reset */
+ RCC->CTRLSTS &= CSR_RMVF_Reset;
+}
+
+/**
+ * @brief Checks whether the specified RCC interrupt has occurred or not.
+ * @param RccInt specifies the RCC interrupt source to check.
+ *
+ * this parameter can be one of the following values:
+ * @arg RCC_INT_LSIRDIF LSI ready interrupt
+ * @arg RCC_INT_LSERDIF LSE ready interrupt
+ * @arg RCC_INT_HSIRDIF HSI ready interrupt
+ * @arg RCC_INT_HSERDIF HSE ready interrupt
+ * @arg RCC_INT_PLLRDIF PLL ready interrupt
+ * @arg RCC_INT_BORIF interrupt
+ * @arg RCC_INT_MSIRDIF MSI ready interrupt
+ * @arg RCC_INT_CLKSSIF Clock Security System interrupt
+ *
+ * @return The new state of RccInt (SET or RESET).
+ */
+INTStatus RCC_GetIntStatus(uint8_t RccInt)
+{
+ INTStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_RCC_GET_INT(RccInt));
+ /* Check the status of the specified RCC interrupt */
+ if ((RCC->CLKINT & RccInt) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the RccInt status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RCC's interrupt pending bits.
+ * @param RccInt specifies the interrupt pending bit to clear.
+ *
+ * this parameter can be any combination of the
+ * following values:
+ * @arg RCC_CLR_MSIRDIF Clear MSI ready interrupt flag
+ * @arg RCC_CLR_LSIRDIF Clear LSI ready interrupt flag
+ * @arg RCC_CLR_LSERDIF Clear LSE ready interrupt flag
+ * @arg RCC_CLR_HSIRDIF Clear HSI ready interrupt flag
+ * @arg RCC_CLR_HSERDIF Clear HSE ready interrupt flag
+ * @arg RCC_CLR_PLLRDIF Clear PLL ready interrupt flag
+ * @arg RCC_CLR_BORIF Clear BOR interrupt flag
+ * @arg RCC_CLR_CLKSSIF Clear Clock Security System interrupt flag
+ */
+void RCC_ClrIntPendingBit(uint32_t RccClrInt)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_CLR_INTF(RccClrInt));
+ /* Software set this bit to clear INT flag. */
+ RCC->CLKINT |= RccClrInt;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_rtc.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_rtc.c
new file mode 100644
index 0000000000..9849b14270
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_rtc.c
@@ -0,0 +1,2152 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_rtc.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l43x_rtc.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RTC
+ * @brief RTC driver modules
+ * @{
+ */
+
+/* Masks Definition */
+#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
+#define RTC_DATE_RESERVED_MASK ((uint32_t)0x00FFFF3F)
+
+#define RTC_RSF_MASK ((uint32_t)0xFFFFFFDF)
+#define RTC_FLAGS_MASK \
+ ((uint32_t)(RTC_FLAG_TISOVF | RTC_FLAG_TISF | RTC_FLAG_WTF | RTC_FLAG_ALBF | RTC_FLAG_ALAF | RTC_FLAG_INITF \
+ | RTC_FLAG_RSYF | RTC_FLAG_INITSF | RTC_FLAG_WTWF | RTC_FLAG_ALBWF | RTC_FLAG_ALAWF | RTC_FLAG_RECPF \
+ | RTC_FLAG_SHOPF))
+
+#define INITMODE_TIMEOUT ((uint32_t)0x00002000)
+#define SYNCHRO_TIMEOUT ((uint32_t)0x00008000)
+#define RECALPF_TIMEOUT ((uint32_t)0x00001000)
+#define SHPF_TIMEOUT ((uint32_t)0x00002000)
+
+static uint8_t RTC_ByteToBcd2(uint8_t Value);
+static uint8_t RTC_Bcd2ToByte(uint8_t Value);
+
+/** @addtogroup RTC_Private_Functions
+ * @{
+ */
+
+/** @addtogroup RTC_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This section provide functions allowing to initialize and configure the
+ RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
+ RTC registers Write protection, enter and exit the RTC initialization mode,
+ RTC registers synchronization check and reference clock detection enable.
+ (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
+ It is split into 2 programmable prescalers to minimize power consumption.
+ (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler.
+ (++) When both prescalers are used, it is recommended to configure the
+ asynchronous prescaler to a high value to minimize consumption.
+ (#) All RTC registers are Write protected. Writing to the RTC registers
+ is enabled by writing a key into the Write Protection register, RTC_WRP.
+ (#) To Configure the RTC Calendar, user application should enter
+ initialization mode. In this mode, the calendar counter is stopped
+ and its value can be updated. When the initialization sequence is
+ complete, the calendar restarts counting after 4 RTCCLK cycles.
+ (#) To read the calendar through the shadow registers after Calendar
+ initialization, calendar update or after wakeup from low power modes
+ the software must first clear the RSYF flag. The software must then
+ wait until it is set again before reading the calendar, which means
+ that the calendar registers have been correctly copied into the
+ RTC_TSH and RTC_DATE shadow registers.The RTC_WaitForSynchro() function
+ implements the above software sequence (RSYF clear and RSYF check).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the RTC registers to their default reset values.
+ * @note This function doesn't reset the RTC Clock source and RTC Backup Data
+ * registers.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are deinitialized
+ * - ERROR: RTC registers are not deinitialized
+ */
+ErrorStatus RTC_DeInit(void)
+{
+ __IO uint32_t wutcounter = 0x00;
+ uint32_t wutwfstatus = 0x00;
+ ErrorStatus status = ERROR;
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+ /* Set Initialization mode */
+ if (RTC_EnterInitMode() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ /* Reset TSH, DAT and CTRL registers */
+ RTC->TSH = (uint32_t)0x00000000;
+ RTC->DATE = (uint32_t)0x00002101;
+ /* Reset All CTRL bits except CTRL[2:0] */
+ RTC->CTRL &= (uint32_t)0x00000007;
+ /* Wait till RTC WTWF flag is set and if Time out is reached exit */
+ do
+ {
+ wutwfstatus = RTC->INITSTS & RTC_INITSTS_WTWF;
+ wutcounter++;
+ } while ((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
+ if ((RTC->INITSTS & RTC_INITSTS_WTWF) == RESET)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ /* Reset all RTC CTRL register bits */
+ RTC->CTRL &= (uint32_t)0x00000000;
+ RTC->WKUPT = (uint32_t)0x0000FFFF;
+ RTC->PRE = (uint32_t)0x007F00FF;
+ RTC->ALARMA = (uint32_t)0x00000000;
+ RTC->ALARMB = (uint32_t)0x00000000;
+ RTC->SCTRL = (uint32_t)0x00000000;
+ RTC->CALIB = (uint32_t)0x00000000;
+ RTC->ALRMASS = (uint32_t)0x00000000;
+ RTC->ALRMBSS = (uint32_t)0x00000000;
+ /* Reset INTSTS register and exit initialization mode */
+ RTC->INITSTS = (uint32_t)0x00000000;
+ RTC->OPT = (uint32_t)0x00000000;
+ RTC->TSCWKUPCTRL = (uint32_t)0x00000008;
+ RTC->TSCWKUPCNT = (uint32_t)0x000002FE;
+ /* Wait till the RTC RSYF flag is set */
+ if (RTC_WaitForSynchro() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ }
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+ return status;
+}
+
+/**
+ * @brief Initializes the RTC registers according to the specified parameters
+ * in RTC_InitStruct.
+ * @param RTC_InitStruct pointer to a RTC_InitType structure that contains
+ * the configuration information for the RTC peripheral.
+ * @note The RTC Prescaler register is write protected and can be written in
+ * initialization mode only.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are initialized
+ * - ERROR: RTC registers are not initialized
+ */
+ErrorStatus RTC_Init(RTC_InitType* RTC_InitStruct)
+{
+ ErrorStatus status = ERROR;
+ uint32_t i =0;
+ /* Check the parameters */
+ assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat));
+ assert_param(IS_RTC_PREDIV_ASYNCH(RTC_InitStruct->RTC_AsynchPrediv));
+ assert_param(IS_RTC_PREDIV_SYNCH(RTC_InitStruct->RTC_SynchPrediv));
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+ /* Set Initialization mode */
+ if (RTC_EnterInitMode() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ /* Clear RTC CTRL HFMT Bit */
+ RTC->CTRL &= ((uint32_t) ~(RTC_CTRL_HFMT));
+ /* Set RTC_CTRL register */
+ RTC->CTRL |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat));
+ /* Configure the RTC PRE */
+ RTC->PRE = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv);
+ RTC->PRE |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16);
+ /* Exit Initialization mode */
+ RTC_ExitInitMode();
+ status = SUCCESS;
+ }
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+ /* Delay for the RTC prescale effect */
+ for(i=0;i<0x2FF;i++);
+ return status;
+}
+
+/**
+ * @brief Fills each RTC_InitStruct member with its default value.
+ * @param RTC_InitStruct pointer to a RTC_InitType structure which will be
+ * initialized.
+ */
+void RTC_StructInit(RTC_InitType* RTC_InitStruct)
+{
+ /* Initialize the RTC_HourFormat member */
+ RTC_InitStruct->RTC_HourFormat = RTC_24HOUR_FORMAT;
+ /* Initialize the RTC_AsynchPrediv member */
+ RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F;
+ /* Initialize the RTC_SynchPrediv member */
+ RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF;
+}
+
+/**
+ * @brief Enables or disables the RTC registers write protection.
+ * @note All the RTC registers are write protected except for RTC_INITSTS[13:8].
+ * @note Writing a wrong key reactivates the write protection.
+ * @note The protection mechanism is not affected by system reset.
+ * @param Cmd new state of the write protection.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RTC_EnableWriteProtection(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+ }
+ else
+ {
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+ }
+}
+
+/**
+ * @brief Enters the RTC Initialization mode.
+ * @note The RTC Initialization mode is write protected, use the
+ * RTC_EnableWriteProtection(DISABLE) before calling this function.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC is in Init mode
+ * - ERROR: RTC is not in Init mode
+ */
+ErrorStatus RTC_EnterInitMode(void)
+{
+ __IO uint32_t initcounter = 0x00;
+ ErrorStatus status = ERROR;
+ uint32_t initstatus = 0x00;
+ /* Check if the Initialization mode is set */
+ if ((RTC->INITSTS & RTC_INITSTS_INITF) == (uint32_t)RESET)
+ {
+ /* Set the Initialization mode */
+ RTC->INITSTS = (uint32_t)RTC_INITSTS_INITM;
+ /* Wait till RTC is in INIT state and if Time out is reached exit */
+ do
+ {
+ initstatus = RTC->INITSTS & RTC_INITSTS_INITF;
+ initcounter++;
+ } while ((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));
+ if ((RTC->INITSTS & RTC_INITSTS_INITF) != RESET)
+ {
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ return (status);
+}
+
+/**
+ * @brief Exits the RTC Initialization mode.
+ * @note When the initialization sequence is complete, the calendar restarts
+ * counting after 4 RTCCLK cycles.
+ * @note The RTC Initialization mode is write protected, use the
+ * RTC_EnableWriteProtection(DISABLE) before calling this function.
+ */
+void RTC_ExitInitMode(void)
+{
+ /* Exit Initialization mode */
+ RTC->INITSTS &= (uint32_t)~RTC_INITSTS_INITM;
+}
+
+/**
+ * @brief Waits until the RTC Time and Date registers (RTC_TSH and RTC_DATE) are
+ * synchronized with RTC APB clock.
+ * @note The RTC Resynchronization mode is write protected, use the
+ * RTC_EnableWriteProtection(DISABLE) before calling this function.
+ * @note To read the calendar through the shadow registers after Calendar
+ * initialization, calendar update or after wakeup from low power modes
+ * the software must first clear the RSYF flag.
+ * The software must then wait until it is set again before reading
+ * the calendar, which means that the calendar registers have been
+ * correctly copied into the RTC_TSH and RTC_DATE shadow registers.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are synchronised
+ * - ERROR: RTC registers are not synchronised
+ */
+ErrorStatus RTC_WaitForSynchro(void)
+{
+ __IO uint32_t synchrocounter = 0;
+ ErrorStatus status = ERROR;
+ uint32_t synchrostatus = 0x00;
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+ /* Clear RSYF flag */
+ RTC->INITSTS &= (uint32_t)RTC_RSF_MASK;
+ /* Wait the registers to be synchronised */
+ do
+ {
+ synchrostatus = RTC->INITSTS & RTC_INITSTS_RSYF;
+ synchrocounter++;
+ } while ((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));
+ if ((RTC->INITSTS & RTC_INITSTS_RSYF) != RESET)
+ {
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+ return (status);
+}
+
+/**
+ * @brief Enables or disables the RTC reference clock detection.
+ * @param Cmd new state of the RTC reference clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC reference clock detection is enabled
+ * - ERROR: RTC reference clock detection is disabled
+ */
+ErrorStatus RTC_EnableRefClock(FunctionalState Cmd)
+{
+ ErrorStatus status = ERROR;
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+ /* Set Initialization mode */
+ if (RTC_EnterInitMode() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ if (Cmd != DISABLE)
+ {
+ /* Enable the RTC reference clock detection */
+ RTC->CTRL |= RTC_CTRL_REFCLKEN;
+ }
+ else
+ {
+ /* Disable the RTC reference clock detection */
+ RTC->CTRL &= ~RTC_CTRL_REFCLKEN;
+ }
+ /* Exit Initialization mode */
+ RTC_ExitInitMode();
+ status = SUCCESS;
+ }
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+ return status;
+}
+
+/**
+ * @brief Enables or Disables the Bypass Shadow feature.
+ * @note When the Bypass Shadow is enabled the calendar value are taken
+ * directly from the Calendar counter.
+ * @param Cmd new state of the Bypass Shadow feature.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RTC_EnableBypassShadow(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+ if (Cmd != DISABLE)
+ {
+ /* Set the BYPS bit */
+ RTC->CTRL |= (uint8_t)RTC_CTRL_BYPS;
+ }
+ else
+ {
+ /* Reset the BYPS bit */
+ RTC->CTRL &= (uint8_t)~RTC_CTRL_BYPS;
+ }
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group2 Time and Date configuration functions
+ * @brief Time and Date configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Time and Date configuration functions #####
+ ===============================================================================
+ [..] This section provide functions allowing to program and read the RTC
+ Calendar (Time and Date).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set the RTC current time.
+ * @param RTC_Format specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN Binary data format.
+ * @arg RTC_FORMAT_BCD BCD data format.
+ * @param RTC_TimeStruct pointer to a RTC_TimeType structure that contains
+ * the time configuration information for the RTC.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Time register is configured
+ * - ERROR: RTC Time register is not configured
+ */
+ErrorStatus RTC_ConfigTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct)
+{
+ uint32_t tmpregister = 0;
+ ErrorStatus status = ERROR;
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+ if (RTC_Format == RTC_FORMAT_BIN)
+ {
+ if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET)
+ {
+ assert_param(IS_RTC_12HOUR(RTC_TimeStruct->Hours));
+ assert_param(IS_RTC_H12(RTC_TimeStruct->H12));
+ }
+ else
+ {
+ RTC_TimeStruct->H12 = 0x00;
+ assert_param(IS_RTC_24HOUR(RTC_TimeStruct->Hours));
+ }
+ assert_param(IS_RTC_MINUTES(RTC_TimeStruct->Minutes));
+ assert_param(IS_RTC_SECONDS(RTC_TimeStruct->Seconds));
+ }
+ else
+ {
+ if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET)
+ {
+ tmpregister = RTC_Bcd2ToByte(RTC_TimeStruct->Hours);
+ assert_param(IS_RTC_12HOUR(tmpregister));
+ assert_param(IS_RTC_H12(RTC_TimeStruct->H12));
+ }
+ else
+ {
+ RTC_TimeStruct->H12 = 0x00;
+ assert_param(IS_RTC_24HOUR(RTC_Bcd2ToByte(RTC_TimeStruct->Hours)));
+ }
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->Seconds)));
+ }
+ /* Check the input parameters format */
+ if (RTC_Format != RTC_FORMAT_BIN)
+ {
+ tmpregister = (((uint32_t)(RTC_TimeStruct->Hours) << 16) | ((uint32_t)(RTC_TimeStruct->Minutes) << 8)
+ | ((uint32_t)RTC_TimeStruct->Seconds) | ((uint32_t)(RTC_TimeStruct->H12) << 16));
+ }
+ else
+ {
+ tmpregister =(uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->Hours) << 16)
+ | ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->Minutes) << 8)
+ | ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->Seconds)) | (((uint32_t)RTC_TimeStruct->H12) << 16));
+ }
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+ /* Set Initialization mode */
+ if (RTC_EnterInitMode() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ /* Set the RTC_TSH register */
+ RTC->TSH = (uint32_t)(tmpregister & RTC_TR_RESERVED_MASK);
+ /* Exit Initialization mode */
+ RTC_ExitInitMode();
+ /* If RTC_CTRL_BYPS bit = 0, wait for synchro else this check is not needed */
+ if ((RTC->CTRL & RTC_CTRL_BYPS) == RESET)
+ {
+ if (RTC_WaitForSynchro() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+ /* Waits until the RTC Time and Date registers
+ (RTC_TSH and RTC_DATE) are synchronized with RTC APB clock. */
+ status=RTC_WaitForSynchro();
+ return status;
+}
+
+/**
+ * @brief Fills each RTC_TimeStruct member with its default value
+ * (Time = 00h:00min:00sec).
+ * @param RTC_TimeStruct pointer to a RTC_TimeType structure which will be
+ * initialized.
+ */
+void RTC_TimeStructInit(RTC_TimeType* RTC_TimeStruct)
+{
+ /* Time = 00h:00min:00sec */
+ RTC_TimeStruct->H12 = RTC_AM_H12;
+ RTC_TimeStruct->Hours = 0;
+ RTC_TimeStruct->Minutes = 0;
+ RTC_TimeStruct->Seconds = 0;
+}
+
+/**
+ * @brief Get the RTC current Time.
+ * @param RTC_Format specifies the format of the returned parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN Binary data format.
+ * @arg RTC_FORMAT_BCD BCD data format.
+ * @param RTC_TimeStruct pointer to a RTC_TimeType structure that will
+ * contain the returned current time configuration.
+ */
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+ /* Get the RTC_TSH register */
+ tmpregister = (uint32_t)(RTC->TSH & RTC_TR_RESERVED_MASK);
+ /* Fill the structure fields with the read parameters */
+ RTC_TimeStruct->Hours = (uint8_t)((tmpregister & (RTC_TSH_HOT | RTC_TSH_HOU)) >> 16);
+ RTC_TimeStruct->Minutes = (uint8_t)((tmpregister & (RTC_TSH_MIT | RTC_TSH_MIU)) >> 8);
+ RTC_TimeStruct->Seconds = (uint8_t)(tmpregister & (RTC_TSH_SCT | RTC_TSH_SCU));
+ RTC_TimeStruct->H12 = (uint8_t)((tmpregister & (RTC_TSH_APM)) >> 16);
+ /* Check the input parameters format */
+ if (RTC_Format == RTC_FORMAT_BIN)
+ {
+ /* Convert the structure parameters to Binary format */
+ RTC_TimeStruct->Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->Hours);
+ RTC_TimeStruct->Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->Minutes);
+ RTC_TimeStruct->Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->Seconds);
+ }
+}
+
+/**
+ * @brief Gets the RTC current Calendar Subseconds value.
+ * @return RTC current Calendar Subseconds value.
+ */
+uint32_t RTC_GetSubSecond(void)
+{
+ uint32_t tmpregister = 0;
+ /* Get subseconds values from the correspondent registers*/
+ tmpregister = (uint32_t)(RTC->SUBS);
+ return (tmpregister);
+}
+
+/**
+ * @brief Set the RTC current date.
+ * @param RTC_Format specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN Binary data format.
+ * @arg RTC_FORMAT_BCD BCD data format.
+ * @param RTC_DateStruct pointer to a RTC_DateType structure that contains
+ * the date configuration information for the RTC.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Date register is configured
+ * - ERROR: RTC Date register is not configured
+ */
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct)
+{
+ uint32_t tmpregister = 0;
+ ErrorStatus status = ERROR;
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+ if ((RTC_Format == RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10) == 0x10))
+ {
+ RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint32_t) ~(0x10)) + 0x0A;
+ }
+ if (RTC_Format == RTC_FORMAT_BIN)
+ {
+ assert_param(IS_RTC_YEAR(RTC_DateStruct->Year));
+ assert_param(IS_RTC_MONTH(RTC_DateStruct->Month));
+ assert_param(IS_RTC_DATE(RTC_DateStruct->Date));
+ }
+ else
+ {
+ assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->Year)));
+ tmpregister = RTC_Bcd2ToByte(RTC_DateStruct->Month);
+ assert_param(IS_RTC_MONTH(tmpregister));
+ tmpregister = RTC_Bcd2ToByte(RTC_DateStruct->Date);
+ assert_param(IS_RTC_DATE(tmpregister));
+ }
+ assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->WeekDay));
+ /* Check the input parameters format */
+ if (RTC_Format != RTC_FORMAT_BIN)
+ {
+ tmpregister = ((((uint32_t)RTC_DateStruct->Year) << 16) | (((uint32_t)RTC_DateStruct->Month) << 8)
+ | ((uint32_t)RTC_DateStruct->Date) | (((uint32_t)RTC_DateStruct->WeekDay) << 13));
+ }
+ else
+ {
+ tmpregister = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->Year) << 16)
+ | ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->Month) << 8)
+ | ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->Date)) | ((uint32_t)RTC_DateStruct->WeekDay << 13));
+ }
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+ /* Set Initialization mode */
+ if (RTC_EnterInitMode() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ /* Set the RTC_DATE register */
+ RTC->DATE = (uint32_t)(tmpregister & RTC_DATE_RESERVED_MASK);
+ /* Exit Initialization mode */
+ RTC_ExitInitMode();
+ /* If RTC_CTRL_BYPS bit = 0, wait for synchro else this check is not needed */
+ if ((RTC->CTRL & RTC_CTRL_BYPS) == RESET)
+ {
+ if (RTC_WaitForSynchro() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+ /* Waits until the RTC Time and Date registers
+ (RTC_TSH and RTC_DATE) are synchronized with RTC APB clock. */
+ status=RTC_WaitForSynchro();
+ return status;
+}
+
+/**
+ * @brief Fills each RTC_DateStruct member with its default value
+ * (Monday, January 01 xx00).
+ * @param RTC_DateStruct pointer to a RTC_DateType structure which will be
+ * initialized.
+ */
+void RTC_DateStructInit(RTC_DateType* RTC_DateStruct)
+{
+ /* Monday, January 01 xx00 */
+ RTC_DateStruct->WeekDay = RTC_WEEKDAY_MONDAY;
+ RTC_DateStruct->Date = 1;
+ RTC_DateStruct->Month = RTC_MONTH_JANUARY;
+ RTC_DateStruct->Year = 0;
+}
+
+/**
+ * @brief Get the RTC current date.
+ * @param RTC_Format specifies the format of the returned parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN Binary data format.
+ * @arg RTC_FORMAT_BCD BCD data format.
+ * @param RTC_DateStruct pointer to a RTC_DateType structure that will
+ * contain the returned current date configuration.
+ */
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+ /* Get the RTC_TSH register */
+ tmpregister = (uint32_t)(RTC->DATE & RTC_DATE_RESERVED_MASK);
+ /* Fill the structure fields with the read parameters */
+ RTC_DateStruct->Year = (uint8_t)((tmpregister & (RTC_DATE_YRT | RTC_DATE_YRU)) >> 16);
+ RTC_DateStruct->Month = (uint8_t)((tmpregister & (RTC_DATE_MOT | RTC_DATE_MOU)) >> 8);
+ RTC_DateStruct->Date = (uint8_t)(tmpregister & (RTC_DATE_DAT | RTC_DATE_DAU));
+ RTC_DateStruct->WeekDay = (uint8_t)((tmpregister & (RTC_DATE_WDU)) >> 13);
+ /* Check the input parameters format */
+ if (RTC_Format == RTC_FORMAT_BIN)
+ {
+ /* Convert the structure parameters to Binary format */
+ RTC_DateStruct->Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->Year);
+ RTC_DateStruct->Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->Month);
+ RTC_DateStruct->Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->Date);
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group3 Alarms configuration functions
+ * @brief Alarms (Alarm A and Alarm B) configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Alarms (Alarm A and Alarm B) configuration functions #####
+ ===============================================================================
+ [..] This section provide functions allowing to program and read the RTC
+ Alarms.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set the specified RTC Alarm.
+ * @note The Alarm register can only be written when the corresponding Alarm
+ * is disabled (Use the RTC_EnableAlarm(DISABLE)).
+ * @param RTC_Format specifies the format of the returned parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN Binary data format.
+ * @arg RTC_FORMAT_BCD BCD data format.
+ * @param RTC_Alarm specifies the alarm to be configured.
+ * This parameter can be one of the following values:
+ * @arg RTC_A_ALARM to select Alarm A.
+ * @arg RTC_B_ALARM to select Alarm B.
+ * @param RTC_AlarmStruct pointer to a RTC_AlarmType structure that
+ * contains the alarm configuration parameters.
+ */
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+ assert_param(IS_RTC_ALARM_SEL(RTC_Alarm));
+ assert_param(IS_ALARM_MASK(RTC_AlarmStruct->AlarmMask));
+ assert_param(IS_RTC_ALARM_WEEKDAY_SEL(RTC_AlarmStruct->DateWeekMode));
+ if (RTC_Format == RTC_FORMAT_BIN)
+ {
+ if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET)
+ {
+ assert_param(IS_RTC_12HOUR(RTC_AlarmStruct->AlarmTime.Hours));
+ assert_param(IS_RTC_H12(RTC_AlarmStruct->AlarmTime.H12));
+ }
+ else
+ {
+ RTC_AlarmStruct->AlarmTime.H12 = 0x00;
+ assert_param(IS_RTC_24HOUR(RTC_AlarmStruct->AlarmTime.Hours));
+ }
+ assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
+ assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
+ if (RTC_AlarmStruct->DateWeekMode == RTC_ALARM_SEL_WEEKDAY_DATE)
+ {
+ assert_param(IS_RTC_ALARM_WEEKDAY_DATE(RTC_AlarmStruct->DateWeekValue));
+ }
+ else
+ {
+ assert_param(IS_RTC_ALARM_WEEKDAY_WEEKDAY(RTC_AlarmStruct->DateWeekValue));
+ }
+ }
+ else
+ {
+ if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET)
+ {
+ tmpregister = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Hours);
+ assert_param(IS_RTC_12HOUR(tmpregister));
+ assert_param(IS_RTC_H12(RTC_AlarmStruct->AlarmTime.H12));
+ }
+ else
+ {
+ RTC_AlarmStruct->AlarmTime.H12 = 0x00;
+ assert_param(IS_RTC_24HOUR(RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Hours)));
+ }
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Seconds)));
+ if (RTC_AlarmStruct->DateWeekMode == RTC_ALARM_SEL_WEEKDAY_DATE)
+ {
+ tmpregister = RTC_Bcd2ToByte(RTC_AlarmStruct->DateWeekValue);
+ assert_param(IS_RTC_ALARM_WEEKDAY_DATE(tmpregister));
+ }
+ else
+ {
+ tmpregister = RTC_Bcd2ToByte(RTC_AlarmStruct->DateWeekValue);
+ assert_param(IS_RTC_ALARM_WEEKDAY_WEEKDAY(tmpregister));
+ }
+ }
+ /* Check the input parameters format */
+ if (RTC_Format != RTC_FORMAT_BIN)
+ {
+ tmpregister = (((uint32_t)(RTC_AlarmStruct->AlarmTime.Hours) << 16)
+ | ((uint32_t)(RTC_AlarmStruct->AlarmTime.Minutes) << 8) | ((uint32_t)RTC_AlarmStruct->AlarmTime.Seconds)
+ | ((uint32_t)(RTC_AlarmStruct->AlarmTime.H12) << 16) | ((uint32_t)(RTC_AlarmStruct->DateWeekValue) << 24)
+ | ((uint32_t)RTC_AlarmStruct->DateWeekMode) | ((uint32_t)RTC_AlarmStruct->AlarmMask));
+ }
+ else
+ {
+ tmpregister = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->AlarmTime.Hours) << 16)
+ | ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->AlarmTime.Minutes) << 8)
+ | ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->AlarmTime.Seconds))
+ | ((uint32_t)(RTC_AlarmStruct->AlarmTime.H12) << 16)
+ | ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->DateWeekValue) << 24)
+ | ((uint32_t)RTC_AlarmStruct->DateWeekMode) | ((uint32_t)RTC_AlarmStruct->AlarmMask));
+ }
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+ /* Configure the Alarm register */
+ if (RTC_Alarm == RTC_A_ALARM)
+ {
+ RTC->ALARMA = (uint32_t)tmpregister;
+ }
+ else
+ {
+ RTC->ALARMB = (uint32_t)tmpregister;
+ }
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Fills each RTC_AlarmStruct member with its default value
+ * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask =
+ * all fields are masked).
+ * @param RTC_AlarmStruct pointer to a @ref RTC_AlarmType structure which
+ * will be initialized.
+ */
+void RTC_AlarmStructInit(RTC_AlarmType* RTC_AlarmStruct)
+{
+ /* Alarm Time Settings : Time = 00h:00mn:00sec */
+ RTC_AlarmStruct->AlarmTime.H12 = RTC_AM_H12;
+ RTC_AlarmStruct->AlarmTime.Hours = 0;
+ RTC_AlarmStruct->AlarmTime.Minutes = 0;
+ RTC_AlarmStruct->AlarmTime.Seconds = 0;
+ /* Alarm Date Settings : Date = 1st day of the month */
+ RTC_AlarmStruct->DateWeekMode = RTC_ALARM_SEL_WEEKDAY_DATE;
+ RTC_AlarmStruct->DateWeekValue = 1;
+ /* Alarm Masks Settings : Mask = all fields are not masked */
+ RTC_AlarmStruct->AlarmMask = RTC_ALARMMASK_NONE;
+}
+
+/**
+ * @brief Get the RTC Alarm value and masks.
+ * @param RTC_Format specifies the format of the output parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN Binary data format.
+ * @arg RTC_FORMAT_BCD BCD data format.
+ * @param RTC_Alarm specifies the alarm to be read.
+ * This parameter can be one of the following values:
+ * @arg RTC_A_ALARM to select Alarm A.
+ * @arg RTC_B_ALARM to select Alarm B.
+ * @param RTC_AlarmStruct pointer to a RTC_AlarmType structure that will
+ * contains the output alarm configuration values.
+ */
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+ assert_param(IS_RTC_ALARM_SEL(RTC_Alarm));
+ /* Get the RTC_ALARMx register */
+ if (RTC_Alarm == RTC_A_ALARM)
+ {
+ tmpregister = (uint32_t)(RTC->ALARMA);
+ }
+ else
+ {
+ tmpregister = (uint32_t)(RTC->ALARMB);
+ }
+ /* Fill the structure with the read parameters */
+ RTC_AlarmStruct->AlarmTime.Hours = (uint32_t)((tmpregister & (RTC_ALARMA_HOT | RTC_ALARMA_HOU)) >> 16);
+ RTC_AlarmStruct->AlarmTime.Minutes = (uint32_t)((tmpregister & (RTC_ALARMA_MIT | RTC_ALARMA_MIU)) >> 8);
+ RTC_AlarmStruct->AlarmTime.Seconds = (uint32_t)(tmpregister & (RTC_ALARMA_SET | RTC_ALARMA_SEU));
+ RTC_AlarmStruct->AlarmTime.H12 = (uint32_t)((tmpregister & RTC_ALARMA_APM) >> 16);
+ RTC_AlarmStruct->DateWeekValue = (uint32_t)((tmpregister & (RTC_ALARMA_DTT | RTC_ALARMA_DTU)) >> 24);
+ RTC_AlarmStruct->DateWeekMode = (uint32_t)(tmpregister & RTC_ALARMA_WKDSEL);
+ RTC_AlarmStruct->AlarmMask = (uint32_t)(tmpregister & RTC_ALARMMASK_ALL);
+ if (RTC_Format == RTC_FORMAT_BIN)
+ {
+ RTC_AlarmStruct->AlarmTime.Hours = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Hours);
+ RTC_AlarmStruct->AlarmTime.Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Minutes);
+ RTC_AlarmStruct->AlarmTime.Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Seconds);
+ RTC_AlarmStruct->DateWeekValue = RTC_Bcd2ToByte(RTC_AlarmStruct->DateWeekValue);
+ }
+}
+
+/**
+ * @brief Enables or disables the specified RTC Alarm.
+ * @param RTC_Alarm specifies the alarm to be configured.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_A_ALARM to select Alarm A.
+ * @arg RTC_B_ALARM to select Alarm B.
+ * @param Cmd new state of the specified alarm.
+ * This parameter can be: ENABLE or DISABLE.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Alarm is enabled/disabled
+ * - ERROR: RTC Alarm is not enabled/disabled
+ */
+ErrorStatus RTC_EnableAlarm(uint32_t RTC_Alarm, FunctionalState Cmd)
+{
+ __IO uint32_t alarmcounter = 0x00;
+ uint32_t alarmstatus = 0x00;
+ ErrorStatus status = ERROR;
+ /* Check the parameters */
+ assert_param(IS_RTC_ALARM_ENABLE(RTC_Alarm));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+ /* Configure the Alarm state */
+ if (Cmd != DISABLE)
+ {
+ RTC->CTRL |= (uint32_t)RTC_Alarm;
+ status = SUCCESS;
+ }
+ else
+ {
+ /* Disable the Alarm in RTC_CTRL register */
+ RTC->CTRL &= (uint32_t)~RTC_Alarm;
+ /* Wait till RTC ALxWF flag is set and if Time out is reached exit */
+ do
+ {
+ alarmstatus = RTC->INITSTS & (RTC_Alarm >> 8);
+ alarmcounter++;
+ } while ((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00));
+ if ((RTC->INITSTS & (RTC_Alarm >> 8)) == RESET)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+ return status;
+}
+
+/**
+ * @brief Configure the RTC AlarmA/B Subseconds value and mask.*
+ * @note This function is performed only when the Alarm is disabled.
+ * @param RTC_Alarm specifies the alarm to be configured.
+ * This parameter can be one of the following values:
+ * @arg RTC_A_ALARM to select Alarm A.
+ * @arg RTC_B_ALARM to select Alarm B.
+ * @param RTC_AlarmSubSecondValue specifies the Subseconds value.
+ * This parameter can be a value from 0 to 0x00007FFF.
+ * @param RTC_AlarmSubSecondMask specifies the Subseconds Mask.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_SUBS_MASK_ALL All Alarm SS fields are masked.
+ * There is no comparison on sub seconds for Alarm.
+ * @arg RTC_SUBS_MASK_SS14_1 SS[14:1] are don't care in Alarm comparison.
+ * Only SS[0] is compared
+ * @arg RTC_SUBS_MASK_SS14_2 SS[14:2] are don't care in Alarm comparison.
+ * Only SS[1:0] are compared
+ * @arg RTC_SUBS_MASK_SS14_3 SS[14:3] are don't care in Alarm comparison.
+ * Only SS[2:0] are compared
+ * @arg RTC_SUBS_MASK_SS14_4 SS[14:4] are don't care in Alarm comparison.
+ * Only SS[3:0] are compared
+ * @arg RTC_SUBS_MASK_SS14_5 SS[14:5] are don't care in Alarm comparison.
+ * Only SS[4:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_6 SS[14:6] are don't care in Alarm comparison.
+ * Only SS[5:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_7 SS[14:7] are don't care in Alarm comparison.
+ * Only SS[6:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_8 SS[14:8] are don't care in Alarm comparison.
+ * Only SS[7:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_9 SS[14:9] are don't care in Alarm comparison.
+ * Only SS[8:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_10 SS[14:10] are don't care in Alarm comparison.
+ * Only SS[9:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_11 SS[14:11] are don't care in Alarm comparison.
+ * Only SS[10:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_12 SS[14:12] are don't care in Alarm comparison.
+ * Only SS[11:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_13 SS[14:13] are don't care in Alarm comparison.
+ * Only SS[12:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_14 SS[14] is don't care in Alarm comparison.
+ * Only SS[13:0] are compared.
+ * @arg RTC_SUBS_MASK_NONE SS[14:0] are compared and must match
+ * to activate alarm.
+ */
+void RTC_ConfigAlarmSubSecond(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RTC_ALARM_SEL(RTC_Alarm));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_MASK_MODE(RTC_AlarmSubSecondMask));
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+ /* Configure the Alarm A or Alarm B SubSecond registers */
+ tmpregister = (uint32_t)(uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask);
+ if (RTC_Alarm == RTC_A_ALARM)
+ {
+ /* Configure the AlarmA SubSecond register */
+ RTC->ALRMASS = tmpregister;
+ }
+ else
+ {
+ /* Configure the Alarm B SubSecond register */
+ RTC->ALRMBSS = tmpregister;
+ }
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Gets the RTC Alarm Subseconds value.
+ * @param RTC_Alarm specifies the alarm to be read.
+ * This parameter can be one of the following values:
+ * @arg RTC_A_ALARM to select Alarm A.
+ * @arg RTC_B_ALARM to select Alarm B.
+ * @return RTC Alarm Subseconds value.
+ */
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm)
+{
+ uint32_t tmpregister = 0;
+ /* Get the RTC_ALARMx register */
+ if (RTC_Alarm == RTC_A_ALARM)
+ {
+ tmpregister = (uint32_t)((RTC->ALRMASS) & RTC_ALRMASS_SSV);
+ }
+ else
+ {
+ tmpregister = (uint32_t)((RTC->ALRMBSS) & RTC_ALRMBSS_SSV);
+ }
+ return (tmpregister);
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group4 WakeUp Timer configuration functions
+ * @brief WakeUp Timer configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### WakeUp Timer configuration functions #####
+ ===============================================================================
+ [..] This section provide functions allowing to program and read the RTC WakeUp.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the RTC Wakeup clock source.
+ * @note The WakeUp Clock source can only be changed when the RTC WakeUp
+ * is disabled (Use the RTC_EnableWakeUp(DISABLE)).
+ * @param RTC_WakeUpClock Wakeup Clock source.
+ * This parameter can be one of the following values:
+ * @arg RTC_WKUPCLK_RTCCLK_DIV16 RTC Wakeup Counter Clock = RTCCLK/16.
+ * @arg RTC_WKUPCLK_RTCCLK_DIV8 RTC Wakeup Counter Clock = RTCCLK/8.
+ * @arg RTC_WKUPCLK_RTCCLK_DIV4 RTC Wakeup Counter Clock = RTCCLK/4.
+ * @arg RTC_WKUPCLK_RTCCLK_DIV2 RTC Wakeup Counter Clock = RTCCLK/2.
+ * @arg RTC_WKUPCLK_CK_SPRE_16BITS RTC Wakeup Counter Clock = CK_SPRE.
+ * @arg RTC_WKUPCLK_CK_SPRE_17BITS RTC Wakeup Counter Clock = CK_SPRE.
+ */
+void RTC_ConfigWakeUpClock(uint32_t RTC_WakeUpClock)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_WKUP_CLOCK(RTC_WakeUpClock));
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+ /* Clear the Wakeup Timer clock source bits in CTRL register */
+ RTC->CTRL &= (uint32_t)~RTC_CTRL_WKUPSEL;
+ /* Configure the clock source */
+ RTC->CTRL |= (uint32_t)RTC_WakeUpClock;
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Configures the RTC Wakeup counter.
+ * @note The RTC WakeUp counter can only be written when the RTC WakeUp.
+ * is disabled (Use the RTC_EnableWakeUp(DISABLE)).
+ * @param RTC_WakeUpCounter specifies the WakeUp counter.
+ * This parameter can be a value from 0x0000 to 0xFFFF.
+ */
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_WKUP_COUNTER(RTC_WakeUpCounter));
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+ /* Configure the Wakeup Timer counter */
+ RTC->WKUPT = (uint32_t)RTC_WakeUpCounter;
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Returns the RTC WakeUp timer counter value.
+ * @return The RTC WakeUp Counter value.
+ */
+uint32_t RTC_GetWakeUpCounter(void)
+{
+ /* Get the counter value */
+ return ((uint32_t)(RTC->WKUPT & RTC_WKUPT_WKUPT));
+}
+
+/**
+ * @brief Enables or Disables the RTC WakeUp timer.
+ * @param Cmd new state of the WakeUp timer.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+ErrorStatus RTC_EnableWakeUp(FunctionalState Cmd)
+{
+ __IO uint32_t wutcounter = 0x00;
+ uint32_t wutwfstatus = 0x00;
+ ErrorStatus status = ERROR;
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+ if (Cmd != DISABLE)
+ {
+ /* Enable the Wakeup Timer */
+ RTC->CTRL |= (uint32_t)RTC_CTRL_WTEN;
+ status = SUCCESS;
+ }
+ else
+ {
+ /* Disable the Wakeup Timer */
+ RTC->CTRL &= (uint32_t)~RTC_CTRL_WTEN;
+ /* Wait till RTC WTWF flag is set and if Time out is reached exit */
+ do
+ {
+ wutwfstatus = RTC->INITSTS & RTC_INITSTS_WTWF;
+ wutcounter++;
+ } while ((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
+ if ((RTC->INITSTS & RTC_INITSTS_WTWF) == RESET)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group5 Daylight Saving configuration functions
+ * @brief Daylight Saving configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Daylight Saving configuration functions #####
+ ===============================================================================
+ [..] This section provide functions allowing to configure the RTC DayLight Saving.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Adds or substract one hour from the current time.
+ * @param RTC_DayLightSaving the value of hour adjustment.
+ * This parameter can be one of the following values:
+ * @arg RTC_DAYLIGHT_SAVING_SUB1H Substract one hour (winter time).
+ * @arg RTC_DAYLIGHT_SAVING_ADD1H Add one hour (summer time).
+ * @param RTC_StoreOperation Specifies the value to be written in the BCK bit
+ * in CTRL register to store the operation.
+ * This parameter can be one of the following values:
+ * @arg RTC_STORE_OPERATION_RESET BCK Bit Reset.
+ * @arg RTC_STORE_OPERATION_SET BCK Bit Set.
+ */
+void RTC_ConfigDayLightSaving(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving));
+ assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation));
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+ /* Clear the bits to be configured */
+ RTC->CTRL &= (uint32_t) ~(RTC_CTRL_BAKP);
+ /* Clear the SU1H and AD1H bits to be configured */
+ RTC->CTRL &= (uint32_t) ~(RTC_CTRL_SU1H & RTC_CTRL_AD1H);
+ /* Configure the RTC_CTRL register */
+ RTC->CTRL |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation);
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Returns the RTC Day Light Saving stored operation.
+ * @return RTC Day Light Saving stored operation.
+ * - RTC_STORE_OPERATION_RESET
+ * - RTC_STORE_OPERATION_SET
+ */
+uint32_t RTC_GetStoreOperation(void)
+{
+ return (RTC->CTRL & RTC_CTRL_BAKP);
+}
+
+/**
+ * @}
+ */
+
+
+
+
+/**
+ * @brief Configures the RTC output source (AFO_ALARM).
+ * @param RTC_Output Specifies which signal will be routed to the RTC output.
+ * This parameter can be one of the following values:
+ * @arg RTC_OUTPUT_DIS No output selected
+ * @arg RTC_OUTPUT_ALA signal of AlarmA mapped to output.
+ * @arg RTC_OUTPUT_ALB signal of AlarmB mapped to output.
+ * @arg RTC_OUTPUT_WKUP signal of WakeUp mapped to output.
+ * @param RTC_OutputPolarity Specifies the polarity of the output signal.
+ * This parameter can be one of the following:
+ * @arg RTC_OUTPOL_HIGH The output pin is high when the
+ * ALRAF/ALRBF/WUTF is high (depending on OSEL).
+ * @arg RTC_OUTPOL_LOW The output pin is low when the
+ * ALRAF/ALRBF/WUTF is high (depending on OSEL).
+ */
+void RTC_ConfigOutput(uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_OUTPUT_MODE(RTC_Output));
+ assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity));
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+ /* Clear the bits to be configured */
+ RTC->CTRL &= (uint32_t) ~(RTC_CTRL_OUTSEL | RTC_CTRL_OPOL);
+ /* Configure the output selection and polarity */
+ RTC->CTRL |= (uint32_t)(RTC_Output | RTC_OutputPolarity);
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group7 Coarse and Smooth Calibrations configuration functions
+ * @brief Coarse and Smooth Calibrations configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Coarse and Smooth Calibrations configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the RTC clock to be output through the relative
+ * pin.
+ * @param Cmd new state of the coarse calibration Output.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RTC_EnableCalibOutput(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+ if (Cmd != DISABLE)
+ {
+ /* Enable the RTC clock output */
+ RTC->CTRL |= (uint32_t)RTC_CTRL_COEN;
+ }
+ else
+ {
+ /* Disable the RTC clock output */
+ RTC->CTRL &= (uint32_t)~RTC_CTRL_COEN;
+ }
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ * @param RTC_CalibOutput Select the Calibration output Selection .
+ * This parameter can be one of the following values:
+ * @arg RTC_CALIB_OUTPUT_256HZ A signal has a regular waveform at 256Hz.
+ * @arg RTC_CALIB_OUTPUT_1HZ A signal has a regular waveform at 1Hz.
+ */
+void RTC_ConfigCalibOutput(uint32_t RTC_CalibOutput)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput));
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+ /*clear flags before config*/
+ RTC->CTRL &= (uint32_t) ~(RTC_CTRL_CALOSEL);
+ /* Configure the RTC_CTRL register */
+ RTC->CTRL |= (uint32_t)RTC_CalibOutput;
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Configures the Smooth Calibration Settings.
+ * @param RTC_SmoothCalibPeriod Select the Smooth Calibration Period.
+ * This parameter can be can be one of the following values:
+ * @arg SMOOTH_CALIB_32SEC The smooth calibration periode is 32s.
+ * @arg SMOOTH_CALIB_16SEC The smooth calibration periode is 16s.
+ * @arg SMOOTH_CALIB_8SEC The smooth calibartion periode is 8s.
+ * @param RTC_SmoothCalibPlusPulses Select to Set or reset the CALP bit.
+ * This parameter can be one of the following values:
+ * @arg RTC_SMOOTH_CALIB_PLUS_PULSES_SET Add one RTCCLK puls every 2**11 pulses.
+ * @arg RTC_SMOOTH_CALIB_PLUS_PULSES__RESET No RTCCLK pulses are added.
+ * @param RTC_SmouthCalibMinusPulsesValue Select the value of CALM[8:0] bits.
+ * This parameter can be one any value from 0 to 0x000001FF.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Calib registers are configured
+ * - ERROR: RTC Calib registers are not configured
+ */
+ErrorStatus RTC_ConfigSmoothCalib(uint32_t RTC_SmoothCalibPeriod,
+ uint32_t RTC_SmoothCalibPlusPulses,
+ uint32_t RTC_SmouthCalibMinusPulsesValue)
+{
+ ErrorStatus status = ERROR;
+ uint32_t recalpfcount = 0;
+ /* Check the parameters */
+ assert_param(IS_RTC_SMOOTH_CALIB_PERIOD_SEL(RTC_SmoothCalibPeriod));
+ assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses));
+ assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue));
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+ /* check if a calibration is pending*/
+ if ((RTC->INITSTS & RTC_INITSTS_RECPF) != RESET)
+ {
+ /* wait until the Calibration is completed*/
+ while (((RTC->INITSTS & RTC_INITSTS_RECPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT))
+ {
+ recalpfcount++;
+ }
+ }
+ /* check if the calibration pending is completed or if there is no calibration operation at all*/
+ if ((RTC->INITSTS & RTC_INITSTS_RECPF) == RESET)
+ {
+ /* Configure the Smooth calibration settings */
+ RTC->CALIB = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses
+ | (uint32_t)RTC_SmouthCalibMinusPulsesValue);
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+ return (ErrorStatus)(status);
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group8 TimeStamp configuration functions
+ * @brief TimeStamp configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### TimeStamp configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or Disables the RTC TimeStamp functionality with the
+ * specified time stamp pin stimulating edge.
+ * @param RTC_TimeStampEdge Specifies the pin edge on which the TimeStamp is
+ * activated.
+ * This parameter can be one of the following:
+ * @arg RTC_TIMESTAMP_EDGE_RISING the Time stamp event occurs on the rising
+ * edge of the related pin.
+ * @arg RTC_TIMESTAMP_EDGE_FALLING the Time stamp event occurs on the
+ * falling edge of the related pin.
+ * @param Cmd new state of the TimeStamp.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RTC_EnableTimeStamp(uint32_t RTC_TimeStampEdge, FunctionalState Cmd)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RTC_TIMESTAMP_EDGE_MODE(RTC_TimeStampEdge));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ /* Get the RTC_CTRL register and clear the bits to be configured */
+ tmpregister = (uint32_t)(RTC->CTRL & (uint32_t) ~(RTC_CTRL_TEDGE | RTC_CTRL_TSEN));
+ /* Get the new configuration */
+ if (Cmd != DISABLE)
+ {
+ tmpregister |= (uint32_t)(RTC_TimeStampEdge | RTC_CTRL_TSEN);
+ }
+ else
+ {
+ tmpregister |= (uint32_t)(RTC_TimeStampEdge);
+ }
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+ /* Configure the Time Stamp TSEDGE and Enable bits */
+ RTC->CTRL = (uint32_t)tmpregister;
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Get the RTC TimeStamp value and masks.
+ * @param RTC_Format specifies the format of the output parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN Binary data format
+ * @arg RTC_FORMAT_BCD BCD data format
+ * @param RTC_StampTimeStruct pointer to a RTC_TimeType structure that will
+ * contains the TimeStamp time values.
+ * @param RTC_StampDateStruct pointer to a RTC_DateType structure that will
+ * contains the TimeStamp date values.
+ */
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeType* RTC_StampTimeStruct, RTC_DateType* RTC_StampDateStruct)
+{
+ uint32_t tmptime = 0, tmpdate = 0;
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+ /* Get the TimeStamp time and date registers values */
+ tmptime = (uint32_t)(RTC->TST & RTC_TR_RESERVED_MASK);
+ tmpdate = (uint32_t)(RTC->TSD & RTC_DATE_RESERVED_MASK);
+ /* Fill the Time structure fields with the read parameters */
+ RTC_StampTimeStruct->Hours = (uint8_t)((tmptime & (RTC_TSH_HOT | RTC_TSH_HOU)) >> 16);
+ RTC_StampTimeStruct->Minutes = (uint8_t)((tmptime & (RTC_TSH_MIT | RTC_TSH_MIU)) >> 8);
+ RTC_StampTimeStruct->Seconds = (uint8_t)(tmptime & (RTC_TSH_SCT | RTC_TSH_SCU));
+ RTC_StampTimeStruct->H12 = (uint8_t)((tmptime & (RTC_TSH_APM)) >> 16);
+ /* Fill the Date structure fields with the read parameters */
+ RTC_StampDateStruct->Year = (uint8_t)((tmpdate & (RTC_DATE_YRT | RTC_DATE_YRU)) >> 16);
+ RTC_StampDateStruct->Month = (uint8_t)((tmpdate & (RTC_DATE_MOT | RTC_DATE_MOU)) >> 8);
+ RTC_StampDateStruct->Date = (uint8_t)(tmpdate & (RTC_DATE_DAT | RTC_DATE_DAU));
+ RTC_StampDateStruct->WeekDay = (uint8_t)((tmpdate & (RTC_DATE_WDU)) >> 13);
+ /* Check the input parameters format */
+ if (RTC_Format == RTC_FORMAT_BIN)
+ {
+ /* Convert the Time structure parameters to Binary format */
+ RTC_StampTimeStruct->Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->Hours);
+ RTC_StampTimeStruct->Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->Minutes);
+ RTC_StampTimeStruct->Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->Seconds);
+ /* Convert the Date structure parameters to Binary format */
+ RTC_StampDateStruct->Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->Month);
+ RTC_StampDateStruct->Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->Date);
+ RTC_StampDateStruct->WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->WeekDay);
+ }
+}
+
+/**
+ * @brief Get the RTC timestamp Subseconds value.
+ * @return RTC current timestamp Subseconds value.
+ */
+uint32_t RTC_GetTimeStampSubSecond(void)
+{
+ /* Get timestamp subseconds values from the correspondent registers */
+ return (uint32_t)(RTC->TSSS);
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group11 Output Type Config configuration functions
+ * @brief Output Type Config configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Output Type Config configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the RTC Output Pin mode.
+ * @param RTC_OutputType specifies the RTC Output (PC13) pin mode.
+ * This parameter can be one of the following values:
+ * @arg RTC_OUTPUT_OPENDRAIN RTC Output (PC13) is configured in
+ * Open Drain mode.
+ * @arg RTC_OUTPUT_PUSHPULL RTC Output (PC13) is configured in
+ * Push Pull mode.
+ */
+void RTC_ConfigOutputType(uint32_t RTC_OutputType)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType));
+ RTC->OPT &= (uint32_t) ~(RTC_OPT_TYPE);
+ RTC->OPT |= (uint32_t)(RTC_OutputType);
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group12 Shift control synchronisation functions
+ * @brief Shift control synchronisation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Shift control synchronisation functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the Synchronization Shift Control Settings.
+ * @note When REFCKON is set, firmware must not write to Shift control register
+ * @param RTC_ShiftAdd1S Select to add or not 1 second to the time Calendar.
+ * This parameter can be one of the following values :
+ * @arg RTC_SHIFT_ADD1S_ENABLE Add one second to the clock calendar.
+ * @arg RTC_SHIFT_ADD1S_DISABLE No effect.
+ * @param RTC_ShiftSubFS Select the number of Second Fractions to Substitute.
+ * This parameter can be one any value from 0 to 0x7FFF.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Shift registers are configured
+ * - ERROR: RTC Shift registers are not configured
+ */
+ErrorStatus RTC_ConfigSynchroShift(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS)
+{
+ ErrorStatus status = ERROR;
+ uint32_t shpfcount = 0;
+ /* Check the parameters */
+ assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S));
+ assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS));
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+ /* Check if a Shift is pending*/
+ if ((RTC->INITSTS & RTC_INITSTS_SHOPF) != RESET)
+ {
+ /* Wait until the shift is completed*/
+ while (((RTC->INITSTS & RTC_INITSTS_SHOPF) != RESET) && (shpfcount != SHPF_TIMEOUT))
+ {
+ shpfcount++;
+ }
+ }
+ /* Check if the Shift pending is completed or if there is no Shift operation at all*/
+ if ((RTC->INITSTS & RTC_INITSTS_SHOPF) == RESET)
+ {
+ /* check if the reference clock detection is disabled */
+ if ((RTC->CTRL & RTC_CTRL_REFCLKEN) == RESET)
+ {
+ /* Configure the Shift settings */
+ RTC->SCTRL = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S);
+ if (RTC_WaitForSynchro() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ else
+ {
+ status = ERROR;
+ }
+ }
+ else
+ {
+ status = ERROR;
+ }
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+ return (ErrorStatus)(status);
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group13 Interrupts and flags management functions
+ * @brief Interrupts and flags management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupts and flags management functions #####
+ ===============================================================================
+ [..] All RTC interrupts are connected to the EXTI controller.
+ (+) To enable the RTC Alarm interrupt, the following sequence is required:
+ (+) Configure and enable the EXTI Line 17 in interrupt mode and select
+ the rising edge sensitivity using the EXTI_InitPeripheral() function.
+ (+) Configure and enable the RTC_Alarm IRQ channel in the NVIC using
+ the NVIC_Init() function.
+ (+) Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B)
+ using the RTC_SetAlarm() and RTC_EnableAlarm() functions.
+
+ (+) To enable the RTC Wakeup interrupt, the following sequence is required:
+ (+) Configure and enable the EXTI Line 20 in interrupt mode and select
+ the rising edge sensitivity using the EXTI_InitPeripheral() function.
+ (+) Configure and enable the RTC_WKUP IRQ channel in the NVIC using the
+ NVIC_Init() function.
+ (+) Configure the RTC to generate the RTC wakeup timer event using the
+ RTC_ConfigWakeUpClock(), RTC_SetWakeUpCounter() and RTC_EnableWakeUp()
+ functions.
+
+ (+) To enable the RTC Tamper interrupt, the following sequence is required:
+ (+) Configure and enable the EXTI Line 19 in interrupt mode and select
+ the rising edge sensitivity using the EXTI_InitPeripheral() function.
+ (+) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using
+ the NVIC_Init() function.
+ (+) Configure the RTC to detect the RTC tamper event using the
+ RTC_TamperTriggerConfig() and RTC_TamperCmd() functions.
+
+ (+) To enable the RTC TimeStamp interrupt, the following sequence is
+ required:
+ (+) Configure and enable the EXTI Line 19 in interrupt mode and select
+ the rising edge sensitivity using the EXTI_InitPeripheral() function.
+ (+) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using
+ the NVIC_Init() function.
+ (+) Configure the RTC to detect the RTC time-stamp event using the
+ RTC_EnableTimeStamp() functions.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the specified RTC interrupts.
+ * @param RTC_INT specifies the RTC interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_INT_TS Time Stamp interrupt mask.
+ * @arg RTC_INT_WUT WakeUp Timer interrupt mask.
+ * @arg RTC_INT_ALRB Alarm B interrupt mask.
+ * @arg RTC_INT_ALRA Alarm A interrupt mask.
+ * @param Cmd new state of the specified RTC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RTC_ConfigInt(uint32_t RTC_INT, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_CONFIG_INT(RTC_INT));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+ if (Cmd != DISABLE)
+ {
+ /* Configure the Interrupts in the RTC_CTRL register */
+ RTC->CTRL |= (uint32_t)(RTC_INT & ~RTC_TMPCFG_TPINTEN);
+ }
+ else
+ {
+ /* Configure the Interrupts in the RTC_CTRL register */
+ RTC->CTRL &= (uint32_t) ~(RTC_INT & (uint32_t)~RTC_TMPCFG_TPINTEN);
+ }
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Checks whether the specified RTC flag is set or not.
+ * @param RTC_FLAG specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg RTC_FLAG_RECPF RECALPF event flag.
+ * @arg RTC_FLAG_TAMP3F: Tamper 3 event flag.
+ * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag.
+ * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag.
+ * @arg RTC_FLAG_TISOVF Time Stamp OverFlow flag.
+ * @arg RTC_FLAG_TISF Time Stamp event flag.
+ * @arg RTC_FLAG_WTF WakeUp Timer flag.
+ * @arg RTC_FLAG_ALBF Alarm B flag.
+ * @arg RTC_FLAG_ALAF Alarm A flag.
+ * @arg RTC_FLAG_INITF Initialization mode flag.
+ * @arg RTC_FLAG_RSYF Registers Synchronized flag.
+ * @arg RTC_FLAG_INITSF Registers Configured flag.
+ * @arg RTC_FLAG_SHOPF Shift operation pending flag.
+ * @arg RTC_FLAG_WTWF WakeUp Timer Write flag.
+ * @arg RTC_FLAG_ALBWF Alarm B Write flag.
+ * @arg RTC_FLAG_ALAWF Alarm A write flag.
+ * @return The new state of RTC_FLAG (SET or RESET).
+ */
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
+ /* Get all the flags */
+ tmpregister = (uint32_t)(RTC->INITSTS & RTC_FLAGS_MASK);
+ /* Return the status of the flag */
+ if ((tmpregister & RTC_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RTC's pending flags.
+ * @param RTC_FLAG specifies the RTC flag to clear.
+ * This parameter can be any combination of the following values:.
+ * @arg RTC_FLAG_TAMP3F: Tamper 3 event flag.
+ * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag.
+ * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag.
+ * @arg RTC_FLAG_TISOVF Time Stamp Overflow flag.
+ * @arg RTC_FLAG_TISF Time Stamp event flag.
+ * @arg RTC_FLAG_WTF WakeUp Timer flag.
+ * @arg RTC_FLAG_ALBF Alarm B flag.
+ * @arg RTC_FLAG_ALAF Alarm A flag.
+ * @arg RTC_FLAG_RSYF Registers Synchronized flag.
+ */
+void RTC_ClrFlag(uint32_t RTC_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
+ /* Clear the Flags in the RTC_INITSTS register */
+ RTC->INITSTS = (uint32_t)(
+ (uint32_t)(~((RTC_FLAG | RTC_INITSTS_INITM) & 0x0001FFFF) | (uint32_t)(RTC->INITSTS & RTC_INITSTS_INITM)));
+}
+
+/**
+ * @brief Checks whether the specified RTC interrupt has occurred or not.
+ * @param RTC_INT specifies the RTC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg RTC_INT_TS Time Stamp interrupt.
+ * @arg RTC_INT_WUT WakeUp Timer interrupt.
+ * @arg RTC_INT_ALRB Alarm B interrupt.
+ * @arg RTC_INT_ALRA Alarm A interrupt.
+ * @return The new state of RTC_INT (SET or RESET).
+ */
+INTStatus RTC_GetITStatus(uint32_t RTC_INT)
+{
+ INTStatus bitstatus = RESET;
+ uint32_t tmpregister = 0, enablestatus = 0;
+ uint8_t tamperEnable = 0;
+ /* Check the parameters */
+ assert_param(IS_RTC_GET_INT(RTC_INT));
+ /* Get the Interrupt enable Status */
+ if ((RTC_INT == RTC_INT_TAMP1) || (RTC_INT == RTC_INT_TAMP2)|| (RTC_INT == RTC_INT_TAMP3))
+ {
+ tamperEnable = ((RTC->TMPCFG & 0x00ff0000)>>16);
+ if (tamperEnable > 0)
+ {
+ enablestatus = SET;
+ }
+ }
+ else
+ {
+ enablestatus = (uint32_t)((RTC->CTRL & RTC_INT));
+ }
+ /* Get the Interrupt pending bit */
+ tmpregister = (uint32_t)((RTC->INITSTS & (uint32_t)(RTC_INT >> 4)));
+ /* Get the status of the Interrupt */
+ if ((enablestatus != (uint32_t)RESET) && ((tmpregister & 0x0000FFFF) != (uint32_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RTC's interrupt pending bits.
+ * @param RTC_INT specifies the RTC interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_INT_TS Time Stamp interrupt
+ * @arg RTC_INT_WUT WakeUp Timer interrupt
+ * @arg RTC_INT_ALRB Alarm B interrupt
+ * @arg RTC_INT_ALRA Alarm A interrupt
+ */
+void RTC_ClrIntPendingBit(uint32_t RTC_INT)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RTC_CLEAR_INT(RTC_INT));
+ /* Get the RTC_INITSTS Interrupt pending bits mask */
+ tmpregister = (uint32_t)(RTC_INT >> 4);
+ /* Clear the interrupt pending bits in the RTC_INITSTS register */
+ RTC->INITSTS = (uint32_t)(
+ (uint32_t)(~((tmpregister | RTC_INITSTS_INITM) & 0x0000FFFF) | (uint32_t)(RTC->INITSTS & RTC_INITSTS_INITM)));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief Converts a 2 digit decimal to BCD format.
+ * @param Value Byte to be converted.
+ * @return Converted byte
+ */
+static uint8_t RTC_ByteToBcd2(uint8_t Value)
+{
+ uint8_t bcdhigh = 0;
+ while (Value >= 10)
+ {
+ bcdhigh++;
+ Value -= 10;
+ }
+ return ((uint8_t)(bcdhigh << 4) | Value);
+}
+
+/**
+ * @brief Convert from 2 digit BCD to Binary.
+ * @param Value BCD value to be converted.
+ * @return Converted word
+ */
+static uint8_t RTC_Bcd2ToByte(uint8_t Value)
+{
+ uint8_t tmp = 0;
+ tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
+ return (tmp + (Value & (uint8_t)0x0F));
+}
+/**
+ * @brief Enable wakeup tsc functionand wakeup by the set time
+ * @param count wakeup time.
+ */
+void RTC_EnableWakeUpTsc(uint32_t count)
+{
+ // Wait until bit RTC_TSCWKUPCTRL_WKUPOFF is 1
+ while (!(RTC->TSCWKUPCTRL & RTC_TSCWKUPCTRL_WKUPOFF))
+ {
+ }
+ // enter config wakeup cnt mode
+ RTC->TSCWKUPCTRL = RTC_TSCWKUPCTRL_WKUPCNF;
+ // config tsc wakeup cnt ,tsc wakeup module counting cycle = WAKUPCNT * LSE/LSI
+ RTC->TSCWKUPCNT = count;
+ // exit config wakeup cnt mode
+ RTC->TSCWKUPCTRL &= ~(RTC_TSCWKUPCTRL_WKUPCNF);
+ while (!(RTC->TSCWKUPCTRL & RTC_TSCWKUPCTRL_WKUPOFF))
+ {
+ }
+ // TSC wakeup enable
+ RTC->TSCWKUPCTRL = RTC_TSCWKUPCTRL_WKUPEN;
+}
+
+/** @defgroup RTC_Group9 Tampers configuration functions
+ * @brief Tampers configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Tampers configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the select Tamper pin edge.
+ * @param RTC_Tamper: Selected tamper pin.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_Tamper_1: Select Tamper 1.
+ * @arg RTC_Tamper_2: Select Tamper 2.
+ * @arg RTC_Tamper_3: Select Tamper 3.
+ * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that
+ * stimulates tamper event.
+ * This parameter can be one of the following values:
+ * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event.
+ * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event.
+ * @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event.
+ * @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event.
+ * @retval None
+ */
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER(RTC_Tamper));
+ assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger));
+ if (RTC_Tamper == RTC_TAMPER_3)
+ {
+ RTC_TamperTrigger <<= 5;
+ }
+ if (RTC_Tamper == RTC_TAMPER_2)
+ {
+ RTC_TamperTrigger <<= 3;
+ }
+ /* Configure the RTC_TAMPCR register */
+ RTC->TMPCFG |= (uint32_t)(RTC_Tamper | RTC_TamperTrigger);
+}
+
+/**
+ * @brief Enables or Disables the Tamper detection.
+ * @param RTC_Tamper: Selected tamper pin.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_TAMPER_1: Select Tamper 1.
+ * @arg RTC_TAMPER_2: Select Tamper 2.
+ * @arg RTC_TAMPER_3: Select Tamper 3.
+ * @param NewState: new state of the tamper pin.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER(RTC_Tamper));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected Tamper pin */
+ RTC->TMPCFG |= (uint32_t)RTC_Tamper;
+ }
+ else
+ {
+ /* Disable the selected Tamper pin */
+ RTC->TMPCFG &= (uint32_t)~RTC_Tamper;
+ }
+}
+
+/**
+ * @brief Configures the Tampers Filter.
+ * @param RTC_TamperFilter: Specifies the tampers filter.
+ * This parameter can be one of the following values:
+ * @arg RTC_TamperFilter_Disable: Tamper filter is disabled.
+ * @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive
+ * samples at the active level.
+ * @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive
+ * samples at the active level.
+ * @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive
+ * samples at the active level.
+ * @retval None
+ */
+void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter));
+ /* Clear TAMPFLT[1:0] bits in the RTC_TAMPCR register */
+ RTC->TMPCFG &= (uint32_t)~(RTC_TMPCFG_TPFLT);
+ /* Configure the RTC_TAMPCR register */
+ RTC->TMPCFG |= (uint32_t)RTC_TamperFilter;
+}
+
+/**
+ * @brief Configures the Tampers Sampling Frequency.
+ * @param RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency.
+ * This parameter can be one of the following values:
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 32768
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 16384
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 8192
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 4096
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 2048
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 1024
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 512
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled
+ * with a frequency = RTCCLK / 256
+ * @retval None
+ */
+void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq));
+ /* Clear TAMPFREQ[2:0] bits in the RTC_TAMPCR register */
+ RTC->TMPCFG &= (uint32_t)~(RTC_TAMPCR_TAMPFREQ);
+ /* Configure the RTC_TAMPCR register */
+ RTC->TMPCFG |= (uint32_t)RTC_TamperSamplingFreq;
+}
+
+/**
+ * @brief Configures the Tampers Pins input Precharge Duration.
+ * @param RTC_TamperPrechargeDuration: Specifies the Tampers Pins input
+ * Precharge Duration.
+ * This parameter can be one of the following values:
+ * @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle.
+ * @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle.
+ * @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle.
+ * @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle.
+ * @retval None
+ */
+void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration));
+ /* Clear TAMPPRCH[1:0] bits in the RTC_TAMPCR register */
+ RTC->TMPCFG &= (uint32_t)~(RTC_TMPCFG_TPPRCH);
+ /* Configure the RTC_TAMPCR register */
+ RTC->TMPCFG |= (uint32_t)RTC_TamperPrechargeDuration;
+}
+
+/**
+ * @brief Enables or Disables the TimeStamp on Tamper Detection Event.
+ * @note The timestamp is valid even the TSEN bit in tamper control register
+ * is reset.
+ * @param NewState: new state of the timestamp on tamper event.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Save timestamp on tamper detection event */
+ RTC->TMPCFG |= (uint32_t)RTC_TMPCFG_TPTS;
+ }
+ else
+ {
+ /* Tamper detection does not cause a timestamp to be saved */
+ RTC->TMPCFG &= (uint32_t)~RTC_TMPCFG_TPTS;
+ }
+}
+
+/**
+ * @brief Enables or Disables the Precharge of Tamper pin.
+ * @param NewState: new state of tamper pull up.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RTC_TamperPullUpCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable precharge of the selected Tamper pin */
+ RTC->TMPCFG &= (uint32_t)~RTC_TMPCFG_TPPUDIS;
+ }
+ else
+ {
+ /* Disable precharge of the selected Tamper pin */
+ RTC->TMPCFG |= (uint32_t)RTC_TMPCFG_TPPUDIS;
+ }
+}
+
+/**
+ * @brief Enables or Disables the TAMPTS.
+ * @param NewState: new state of TAMPTS.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RTC_TamperTAMPTSCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable precharge of the selected Tamper pin */
+ RTC->TMPCFG |= (uint32_t)RTC_TMPCFG_TPTS;
+ }
+ else
+ {
+ /* Disable precharge of the selected Tamper pin */
+ RTC->TMPCFG &= (uint32_t)~RTC_TMPCFG_TPTS;
+ }
+}
+
+/**
+ * @brief Enables or Disables the Tamper detection.
+ * @param RTC_Tamper: Selected tamper pin.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_TAMPER1_INT: Select Tamper 1.
+ * @arg RTC_TAMPER2_INT: Select Tamper 2.
+ * @arg RTC_TAMPER3_INT: Select Tamper 3.
+ * @param NewState: new state of the tamper pin.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RTC_TamperIECmd(uint32_t TAMPxIE, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER(TAMPxIE));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected Tamper pin */
+ RTC->TMPCFG |= (uint32_t)TAMPxIE;
+ }
+ else
+ {
+ /* Disable the selected Tamper pin */
+ RTC->TMPCFG &= (uint32_t)~TAMPxIE;
+ }
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_spi.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_spi.c
new file mode 100644
index 0000000000..195cd6771a
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_spi.c
@@ -0,0 +1,853 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_spi.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l43x_spi.h"
+#include "n32l43x_rcc.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @brief SPI driver modules
+ * @{
+ */
+
+/** @addtogroup SPI_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_Defines
+ * @{
+ */
+
+/* SPI SPIEN mask */
+#define CTRL1_SPIEN_ENABLE ((uint16_t)0x0040)
+#define CTRL1_SPIEN_DISABLE ((uint16_t)0xFFBF)
+
+/* I2S I2SEN mask */
+#define I2SCFG_I2SEN_ENABLE ((uint16_t)0x0400)
+#define I2SCFG_I2SEN_DISABLE ((uint16_t)0xFBFF)
+
+/* SPI CRCNEXT mask */
+#define CTRL1_CRCNEXT_ENABLE ((uint16_t)0x1000)
+
+/* SPI CRCEN mask */
+#define CTRL1_CRCEN_ENABLE ((uint16_t)0x2000)
+#define CTRL1_CRCEN_DISABLE ((uint16_t)0xDFFF)
+
+/* SPI SSOE mask */
+#define CTRL2_SSOEN_ENABLE ((uint16_t)0x0004)
+#define CTRL2_SSOEN_DISABLE ((uint16_t)0xFFFB)
+
+/* SPI registers Masks */
+#define CTRL1_CLR_MASK ((uint16_t)0x3040)
+#define I2SCFG_CLR_MASK ((uint16_t)0xF040)
+
+/* SPI or I2S mode selection masks */
+#define SPI_MODE_ENABLE ((uint16_t)0xF7FF)
+#define I2S_MODE_ENABLE ((uint16_t)0x0800)
+
+/* I2S clock source selection masks */
+#define I2S1_CLKSRC ((uint32_t)(0x00020000))
+#define I2S2_CLKSRC ((uint32_t)(0x00040000))
+#define I2S_MUL_MASK ((uint32_t)(0x0000F000))
+#define I2S_DIV_MASK ((uint32_t)(0x000000F0))
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the SPIx peripheral registers to their default
+ * reset values (Affects also the I2Ss).
+ * @param SPIx where x can be 1, 2 to select the SPI peripheral.
+ */
+void SPI_I2S_DeInit(SPI_Module* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+
+ if (SPIx == SPI1)
+ {
+ /* Enable SPI1 reset state */
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI1, ENABLE);
+ /* Release SPI1 from reset state */
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI1, DISABLE);
+ }
+ else if (SPIx == SPI2)
+ {
+ /* Enable SPI2 reset state */
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI2, ENABLE);
+ /* Release SPI2 from reset state */
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI2, DISABLE);
+ }
+
+}
+
+/**
+ * @brief Initializes the SPIx peripheral according to the specified
+ * parameters in the SPI_InitStruct.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param SPI_InitStruct pointer to a SPI_InitType structure that
+ * contains the configuration information for the specified SPI peripheral.
+ */
+void SPI_Init(SPI_Module* SPIx, SPI_InitType* SPI_InitStruct)
+{
+ uint16_t tmpregister = 0;
+
+ /* check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+
+ /* Check the SPI parameters */
+ assert_param(IS_SPI_DIR_MODE(SPI_InitStruct->DataDirection));
+ assert_param(IS_SPI_MODE(SPI_InitStruct->SpiMode));
+ assert_param(IS_SPI_DATASIZE(SPI_InitStruct->DataLen));
+ assert_param(IS_SPI_CLKPOL(SPI_InitStruct->CLKPOL));
+ assert_param(IS_SPI_CLKPHA(SPI_InitStruct->CLKPHA));
+ assert_param(IS_SPI_NSS(SPI_InitStruct->NSS));
+ assert_param(IS_SPI_BR_PRESCALER(SPI_InitStruct->BaudRatePres));
+ assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->FirstBit));
+ assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
+
+ /*---------------------------- SPIx CTRL1 Configuration ------------------------*/
+ /* Get the SPIx CTRL1 value */
+ tmpregister = SPIx->CTRL1;
+ /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
+ tmpregister &= CTRL1_CLR_MASK;
+ /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
+ master/salve mode, CPOL and CPHA */
+ /* Set BIDImode, BIDIOE and RxONLY bits according to DataDirection value */
+ /* Set SSM, SSI and MSTR bits according to SpiMode and NSS values */
+ /* Set LSBFirst bit according to FirstBit value */
+ /* Set BR bits according to BaudRatePres value */
+ /* Set CPOL bit according to CLKPOL value */
+ /* Set CPHA bit according to CLKPHA value */
+ tmpregister |= (uint16_t)((uint32_t)SPI_InitStruct->DataDirection | SPI_InitStruct->SpiMode
+ | SPI_InitStruct->DataLen | SPI_InitStruct->CLKPOL | SPI_InitStruct->CLKPHA
+ | SPI_InitStruct->NSS | SPI_InitStruct->BaudRatePres | SPI_InitStruct->FirstBit);
+ /* Write to SPIx CTRL1 */
+ SPIx->CTRL1 = tmpregister;
+
+ /* Activate the SPI mode (Reset I2SMOD bit in I2SCFG register) */
+ SPIx->I2SCFG &= SPI_MODE_ENABLE;
+
+ /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
+ /* Write to SPIx CRCPOLY */
+ SPIx->CRCPOLY = SPI_InitStruct->CRCPoly;
+}
+
+/**
+ * @brief Initializes the SPIx peripheral according to the specified
+ * parameters in the I2S_InitStruct.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral
+ * (configured in I2S mode).
+ * @param I2S_InitStruct pointer to an I2S_InitType structure that
+ * contains the configuration information for the specified SPI peripheral
+ * configured in I2S mode.
+ * @note
+ * The function calculates the optimal prescaler needed to obtain the most
+ * accurate audio frequency (depending on the I2S clock source, the PLL values
+ * and the product configuration). But in case the prescaler value is greater
+ * than 511, the default value (0x02) will be configured instead. *
+ */
+void I2S_Init(SPI_Module* SPIx, I2S_InitType* I2S_InitStruct)
+{
+ uint16_t tmpregister = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
+ uint32_t tmp = 0;
+ RCC_ClocksType RCC_Clocks;
+ uint32_t sourceclock = 0;
+
+ /* Check the I2S parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_I2S_MODE(I2S_InitStruct->I2sMode));
+ assert_param(IS_I2S_STANDARD(I2S_InitStruct->Standard));
+ assert_param(IS_I2S_DATA_FMT(I2S_InitStruct->DataFormat));
+ assert_param(IS_I2S_MCLK_ENABLE(I2S_InitStruct->MCLKEnable));
+ assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFrequency));
+ assert_param(IS_I2S_CLKPOL(I2S_InitStruct->CLKPOL));
+
+ /*----------------------- SPIx I2SCFG & I2SPREDIV Configuration -----------------*/
+ /* Clear I2SMOD, I2SE, MODCFG, PCMSYNC, STDSEL, CKPOL, TDATLEN and CHLEN bits */
+ SPIx->I2SCFG &= I2SCFG_CLR_MASK;
+ SPIx->I2SPREDIV = 0x0002;
+
+ /* Get the I2SCFG register value */
+ tmpregister = SPIx->I2SCFG;
+
+ /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
+ if (I2S_InitStruct->AudioFrequency == I2S_AUDIO_FREQ_DEFAULT)
+ {
+ i2sodd = (uint16_t)0;
+ i2sdiv = (uint16_t)2;
+ }
+ /* If the requested audio frequency is not the default, compute the prescaler */
+ else
+ {
+ /* Check the frame length (For the Prescaler computing) */
+ if (I2S_InitStruct->DataFormat == I2S_DATA_FMT_16BITS)
+ {
+ /* Packet length is 16 bits */
+ packetlength = 1;
+ }
+ else
+ {
+ /* Packet length is 32 bits */
+ packetlength = 2;
+ }
+
+ /* Get the I2S clock source mask depending on the peripheral number */
+ if (((uint32_t)SPIx) == SPI2_BASE)
+ {
+ /* The mask is relative to I2S1 */
+ tmp = I2S1_CLKSRC;
+ }
+ else
+ {
+ /* The mask is relative to I2S2 */
+ tmp = I2S2_CLKSRC;
+ }
+
+ /* I2S Clock source is System clock: Get System Clock frequency */
+ RCC_GetClocksFreqValue(&RCC_Clocks);
+
+ /* Get the source clock value: based on System Clock value */
+ sourceclock = RCC_Clocks.SysclkFreq;
+
+ /* Compute the Real divider depending on the MCLK output state with a floating point */
+ if (I2S_InitStruct->MCLKEnable == I2S_MCLK_ENABLE)
+ {
+ /* MCLK output is enabled */
+ tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->AudioFrequency)) + 5);
+ }
+ else
+ {
+ /* MCLK output is disabled */
+ tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) * 10) / I2S_InitStruct->AudioFrequency)) + 5);
+ }
+
+ /* Remove the floating point */
+ tmp = tmp / 10;
+
+ /* Check the parity of the divider */
+ i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
+
+ /* Compute the i2sdiv prescaler */
+ i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
+
+ /* Get the Mask for the Odd bit (SPI_I2SPREDIV[8]) register */
+ i2sodd = (uint16_t)(i2sodd << 8);
+ }
+
+ /* Test if the divider is 1 or 0 or greater than 0xFF */
+ if ((i2sdiv < 2) || (i2sdiv > 0xFF))
+ {
+ /* Set the default values */
+ i2sdiv = 2;
+ i2sodd = 0;
+ }
+
+ /* Write to SPIx I2SPREDIV register the computed value */
+ SPIx->I2SPREDIV = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->MCLKEnable));
+
+ /* Configure the I2S with the SPI_InitStruct values */
+ tmpregister |= (uint16_t)(
+ I2S_MODE_ENABLE
+ | (uint16_t)(I2S_InitStruct->I2sMode
+ | (uint16_t)(I2S_InitStruct->Standard
+ | (uint16_t)(I2S_InitStruct->DataFormat | (uint16_t)I2S_InitStruct->CLKPOL))));
+
+ /* Write to SPIx I2SCFG */
+ SPIx->I2SCFG = tmpregister;
+}
+
+/**
+ * @brief Fills each SPI_InitStruct member with its default value.
+ * @param SPI_InitStruct pointer to a SPI_InitType structure which will be initialized.
+ */
+void SPI_InitStruct(SPI_InitType* SPI_InitStruct)
+{
+ /*--------------- Reset SPI init structure parameters values -----------------*/
+ /* Initialize the DataDirection member */
+ SPI_InitStruct->DataDirection = SPI_DIR_DOUBLELINE_FULLDUPLEX;
+ /* initialize the SpiMode member */
+ SPI_InitStruct->SpiMode = SPI_MODE_SLAVE;
+ /* initialize the DataLen member */
+ SPI_InitStruct->DataLen = SPI_DATA_SIZE_8BITS;
+ /* Initialize the CLKPOL member */
+ SPI_InitStruct->CLKPOL = SPI_CLKPOL_LOW;
+ /* Initialize the CLKPHA member */
+ SPI_InitStruct->CLKPHA = SPI_CLKPHA_FIRST_EDGE;
+ /* Initialize the NSS member */
+ SPI_InitStruct->NSS = SPI_NSS_HARD;
+ /* Initialize the BaudRatePres member */
+ SPI_InitStruct->BaudRatePres = SPI_BR_PRESCALER_2;
+ /* Initialize the FirstBit member */
+ SPI_InitStruct->FirstBit = SPI_FB_MSB;
+ /* Initialize the CRCPoly member */
+ SPI_InitStruct->CRCPoly = 7;
+}
+
+/**
+ * @brief Fills each I2S_InitStruct member with its default value.
+ * @param I2S_InitStruct pointer to a I2S_InitType structure which will be initialized.
+ */
+void I2S_InitStruct(I2S_InitType* I2S_InitStruct)
+{
+ /*--------------- Reset I2S init structure parameters values -----------------*/
+ /* Initialize the I2sMode member */
+ I2S_InitStruct->I2sMode = I2S_MODE_SlAVE_TX;
+
+ /* Initialize the Standard member */
+ I2S_InitStruct->Standard = I2S_STD_PHILLIPS;
+
+ /* Initialize the DataFormat member */
+ I2S_InitStruct->DataFormat = I2S_DATA_FMT_16BITS;
+
+ /* Initialize the MCLKEnable member */
+ I2S_InitStruct->MCLKEnable = I2S_MCLK_DISABLE;
+
+ /* Initialize the AudioFrequency member */
+ I2S_InitStruct->AudioFrequency = I2S_AUDIO_FREQ_DEFAULT;
+
+ /* Initialize the CLKPOL member */
+ I2S_InitStruct->CLKPOL = I2S_CLKPOL_LOW;
+}
+
+/**
+ * @brief Enables or disables the specified SPI peripheral.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param Cmd new state of the SPIx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void SPI_Enable(SPI_Module* SPIx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected SPI peripheral */
+ SPIx->CTRL1 |= CTRL1_SPIEN_ENABLE;
+ }
+ else
+ {
+ /* Disable the selected SPI peripheral */
+ SPIx->CTRL1 &= CTRL1_SPIEN_DISABLE;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified SPI peripheral (in I2S mode).
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param Cmd new state of the SPIx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2S_Enable(SPI_Module* SPIx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected SPI peripheral (in I2S mode) */
+ SPIx->I2SCFG |= I2SCFG_I2SEN_ENABLE;
+ }
+ else
+ {
+ /* Disable the selected SPI peripheral (in I2S mode) */
+ SPIx->I2SCFG &= I2SCFG_I2SEN_DISABLE;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified SPI/I2S interrupts.
+ * @param SPIx where x can be
+ * - 1 or 2 in SPI mode
+ * - 1 or 2 in I2S mode
+ * @param SPI_I2S_IT specifies the SPI/I2S interrupt source to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg SPI_I2S_INT_TE Tx buffer empty interrupt mask
+ * @arg SPI_I2S_INT_RNE Rx buffer not empty interrupt mask
+ * @arg SPI_I2S_INT_ERR Error interrupt mask
+ * @param Cmd new state of the specified SPI/I2S interrupt.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void SPI_I2S_EnableInt(SPI_Module* SPIx, uint8_t SPI_I2S_IT, FunctionalState Cmd)
+{
+ uint16_t itpos = 0, itmask = 0;
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ assert_param(IS_SPI_I2S_CONFIG_INT(SPI_I2S_IT));
+
+ /* Get the SPI/I2S IT index */
+ itpos = SPI_I2S_IT >> 4;
+
+ /* Set the IT mask */
+ itmask = (uint16_t)1 << (uint16_t)itpos;
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected SPI/I2S interrupt */
+ SPIx->CTRL2 |= itmask;
+ }
+ else
+ {
+ /* Disable the selected SPI/I2S interrupt */
+ SPIx->CTRL2 &= (uint16_t)~itmask;
+ }
+}
+
+/**
+ * @brief Enables or disables the SPIx/I2Sx DMA interface.
+ * @param SPIx where x can be
+ * - 1 or 2 in SPI mode
+ * - 1 or 2 in I2S mode
+ * @param SPI_I2S_DMAReq specifies the SPI/I2S DMA transfer request to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg SPI_I2S_DMA_TX Tx buffer DMA transfer request
+ * @arg SPI_I2S_DMA_RX Rx buffer DMA transfer request
+ * @param Cmd new state of the selected SPI/I2S DMA transfer request.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void SPI_I2S_EnableDma(SPI_Module* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ assert_param(IS_SPI_I2S_DMA(SPI_I2S_DMAReq));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected SPI/I2S DMA requests */
+ SPIx->CTRL2 |= SPI_I2S_DMAReq;
+ }
+ else
+ {
+ /* Disable the selected SPI/I2S DMA requests */
+ SPIx->CTRL2 &= (uint16_t)~SPI_I2S_DMAReq;
+ }
+}
+
+/**
+ * @brief Transmits a Data through the SPIx/I2Sx peripheral.
+ * @param SPIx where x can be
+ * - 1 or 2 in SPI mode
+ * - 1 or 2 in I2S mode
+ * @param Data Data to be transmitted.
+ */
+void SPI_I2S_TransmitData(SPI_Module* SPIx, uint16_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+
+ /* Write in the DAT register the data to be sent */
+ SPIx->DAT = Data;
+}
+
+/**
+ * @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
+ * @param SPIx where x can be
+ * - 1 or 2 in SPI mode
+ * - 1 or 2 in I2S mode
+ * @return The value of the received data.
+ */
+uint16_t SPI_I2S_ReceiveData(SPI_Module* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+
+ /* Return the data in the DAT register */
+ return SPIx->DAT;
+}
+
+/**
+ * @brief Configures internally by software the NSS pin for the selected SPI.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param SPI_NSSInternalSoft specifies the SPI NSS internal state.
+ * This parameter can be one of the following values:
+ * @arg SPI_NSS_HIGH Set NSS pin internally
+ * @arg SPI_NSS_LOW Reset NSS pin internally
+ */
+void SPI_SetNssLevel(SPI_Module* SPIx, uint16_t SPI_NSSInternalSoft)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_NSS_LEVEL(SPI_NSSInternalSoft));
+ if (SPI_NSSInternalSoft != SPI_NSS_LOW)
+ {
+ /* Set NSS pin internally by software */
+ SPIx->CTRL1 |= SPI_NSS_HIGH;
+ }
+ else
+ {
+ /* Reset NSS pin internally by software */
+ SPIx->CTRL1 &= SPI_NSS_LOW;
+ }
+}
+
+/**
+ * @brief Enables or disables the SS output for the selected SPI.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param Cmd new state of the SPIx SS output.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void SPI_SSOutputEnable(SPI_Module* SPIx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected SPI SS output */
+ SPIx->CTRL2 |= CTRL2_SSOEN_ENABLE;
+ }
+ else
+ {
+ /* Disable the selected SPI SS output */
+ SPIx->CTRL2 &= CTRL2_SSOEN_DISABLE;
+ }
+}
+
+/**
+ * @brief Configures the data size for the selected SPI.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param DataLen specifies the SPI data size.
+ * This parameter can be one of the following values:
+ * @arg SPI_DATA_SIZE_16BITS Set data frame format to 16bit
+ * @arg SPI_DATA_SIZE_8BITS Set data frame format to 8bit
+ */
+void SPI_ConfigDataLen(SPI_Module* SPIx, uint16_t DataLen)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_DATASIZE(DataLen));
+ /* Clear DFF bit */
+ SPIx->CTRL1 &= (uint16_t)~SPI_DATA_SIZE_16BITS;
+ /* Set new DFF bit value */
+ SPIx->CTRL1 |= DataLen;
+}
+
+/**
+ * @brief Transmit the SPIx CRC value.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ */
+void SPI_TransmitCrcNext(SPI_Module* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+
+ /* Enable the selected SPI CRC transmission */
+ SPIx->CTRL1 |= CTRL1_CRCNEXT_ENABLE;
+}
+
+/**
+ * @brief Enables or disables the CRC value calculation of the transferred bytes.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param Cmd new state of the SPIx CRC value calculation.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void SPI_EnableCalculateCrc(SPI_Module* SPIx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected SPI CRC calculation */
+ SPIx->CTRL1 |= CTRL1_CRCEN_ENABLE;
+ }
+ else
+ {
+ /* Disable the selected SPI CRC calculation */
+ SPIx->CTRL1 &= CTRL1_CRCEN_DISABLE;
+ }
+}
+
+/**
+ * @brief Returns the transmit or the receive CRC register value for the specified SPI.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param SPI_CRC specifies the CRC register to be read.
+ * This parameter can be one of the following values:
+ * @arg SPI_CRC_TX Selects Tx CRC register
+ * @arg SPI_CRC_RX Selects Rx CRC register
+ * @return The selected CRC register value..
+ */
+uint16_t SPI_GetCRCDat(SPI_Module* SPIx, uint8_t SPI_CRC)
+{
+ uint16_t crcreg = 0;
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_CRC(SPI_CRC));
+ if (SPI_CRC != SPI_CRC_RX)
+ {
+ /* Get the Tx CRC register */
+ crcreg = SPIx->CRCTDAT;
+ }
+ else
+ {
+ /* Get the Rx CRC register */
+ crcreg = SPIx->CRCRDAT;
+ }
+ /* Return the selected CRC register */
+ return crcreg;
+}
+
+/**
+ * @brief Returns the CRC Polynomial register value for the specified SPI.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @return The CRC Polynomial register value.
+ */
+uint16_t SPI_GetCRCPoly(SPI_Module* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+
+ /* Return the CRC polynomial register */
+ return SPIx->CRCPOLY;
+}
+
+/**
+ * @brief Selects the data transfer direction in bi-directional mode for the specified SPI.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param DataDirection specifies the data transfer direction in bi-directional mode.
+ * This parameter can be one of the following values:
+ * @arg SPI_BIDIRECTION_TX Selects Tx transmission direction
+ * @arg SPI_BIDIRECTION_RX Selects Rx receive direction
+ */
+void SPI_ConfigBidirectionalMode(SPI_Module* SPIx, uint16_t DataDirection)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_BIDIRECTION(DataDirection));
+ if (DataDirection == SPI_BIDIRECTION_TX)
+ {
+ /* Set the Tx only mode */
+ SPIx->CTRL1 |= SPI_BIDIRECTION_TX;
+ }
+ else
+ {
+ /* Set the Rx only mode */
+ SPIx->CTRL1 &= SPI_BIDIRECTION_RX;
+ }
+}
+
+/**
+ * @brief Checks whether the specified SPI/I2S flag is set or not.
+ * @param SPIx where x can be
+ * - 1 or 2 in SPI mode
+ * - 1 or 2 in I2S mode
+ * @param SPI_I2S_FLAG specifies the SPI/I2S flag to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_I2S_TE_FLAG Transmit buffer empty flag.
+ * @arg SPI_I2S_RNE_FLAG Receive buffer not empty flag.
+ * @arg SPI_I2S_BUSY_FLAG Busy flag.
+ * @arg SPI_I2S_OVER_FLAG Overrun flag.
+ * @arg SPI_MODERR_FLAG Mode Fault flag.
+ * @arg SPI_CRCERR_FLAG CRC Error flag.
+ * @arg I2S_UNDER_FLAG Underrun Error flag.
+ * @arg I2S_CHSIDE_FLAG Channel Side flag.
+ * @return The new state of SPI_I2S_FLAG (SET or RESET).
+ */
+FlagStatus SPI_I2S_GetStatus(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
+ /* Check the status of the specified SPI/I2S flag */
+ if ((SPIx->STS & SPI_I2S_FLAG) != (uint16_t)RESET)
+ {
+ /* SPI_I2S_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* SPI_I2S_FLAG is reset */
+ bitstatus = RESET;
+ }
+ /* Return the SPI_I2S_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the SPIx CRC Error (CRCERR) flag.
+ * @param SPIx where x can be
+ * - 1 or 2 in SPI mode
+ * @param SPI_I2S_FLAG specifies the SPI flag to clear.
+ * This function clears only CRCERR flag.
+ * @note
+ * - OVR (OverRun error) flag is cleared by software sequence: a read
+ * operation to SPI_DAT register (SPI_I2S_ReceiveData()) followed by a read
+ * operation to SPI_STS register (SPI_I2S_GetStatus()).
+ * - UDR (UnderRun error) flag is cleared by a read operation to
+ * SPI_STS register (SPI_I2S_GetStatus()).
+ * - MODF (Mode Fault) flag is cleared by software sequence: a read/write
+ * operation to SPI_STS register (SPI_I2S_GetStatus()) followed by a
+ * write operation to SPI_CTRL1 register (SPI_Enable() to enable the SPI).
+ */
+void SPI_I2S_ClrCRCErrFlag(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_CLR_FLAG(SPI_I2S_FLAG));
+
+ /* Clear the selected SPI CRC Error (CRCERR) flag */
+ SPIx->STS = (uint16_t)~SPI_I2S_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified SPI/I2S interrupt has occurred or not.
+ * @param SPIx where x can be
+ * - 1 or 2 in SPI mode
+ * - 1 or 2 in I2S mode
+ * @param SPI_I2S_IT specifies the SPI/I2S interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_I2S_INT_TE Transmit buffer empty interrupt.
+ * @arg SPI_I2S_INT_RNE Receive buffer not empty interrupt.
+ * @arg SPI_I2S_INT_OVER Overrun interrupt.
+ * @arg SPI_INT_MODERR Mode Fault interrupt.
+ * @arg SPI_INT_CRCERR CRC Error interrupt.
+ * @arg I2S_INT_UNDER Underrun Error interrupt.
+ * @return The new state of SPI_I2S_IT (SET or RESET).
+ */
+INTStatus SPI_I2S_GetIntStatus(SPI_Module* SPIx, uint8_t SPI_I2S_IT)
+{
+ INTStatus bitstatus = RESET;
+ uint16_t itpos = 0, itmask = 0, enablestatus = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_GET_INT(SPI_I2S_IT));
+
+ /* Get the SPI/I2S IT index */
+ itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+
+ /* Get the SPI/I2S IT mask */
+ itmask = SPI_I2S_IT >> 4;
+
+ /* Set the IT mask */
+ itmask = 0x01 << itmask;
+
+ /* Get the SPI_I2S_IT enable bit status */
+ enablestatus = (SPIx->CTRL2 & itmask);
+
+ /* Check the status of the specified SPI/I2S interrupt */
+ if (((SPIx->STS & itpos) != (uint16_t)RESET) && enablestatus)
+ {
+ /* SPI_I2S_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* SPI_I2S_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the SPI_I2S_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
+ * @param SPIx where x can be
+ * - 1 or 2 in SPI mode
+ * @param SPI_I2S_IT specifies the SPI interrupt pending bit to clear.
+ * This function clears only CRCERR interrupt pending bit.
+ * @note
+ * - OVR (OverRun Error) interrupt pending bit is cleared by software
+ * sequence: a read operation to SPI_DAT register (SPI_I2S_ReceiveData())
+ * followed by a read operation to SPI_STS register (SPI_I2S_GetIntStatus()).
+ * - UDR (UnderRun Error) interrupt pending bit is cleared by a read
+ * operation to SPI_STS register (SPI_I2S_GetIntStatus()).
+ * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
+ * a read/write operation to SPI_STS register (SPI_I2S_GetIntStatus())
+ * followed by a write operation to SPI_CTRL1 register (SPI_Enable() to enable
+ * the SPI).
+ */
+void SPI_I2S_ClrITPendingBit(SPI_Module* SPIx, uint8_t SPI_I2S_IT)
+{
+ uint16_t itpos = 0;
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_CLR_INT(SPI_I2S_IT));
+
+ /* Get the SPI IT index */
+ itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+
+ /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
+ SPIx->STS = (uint16_t)~itpos;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_tim.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_tim.c
new file mode 100644
index 0000000000..1482930b07
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_tim.c
@@ -0,0 +1,3290 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_tim.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l43x_tim.h"
+#include "n32l43x_rcc.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup TIM
+ * @brief TIM driver modules
+ * @{
+ */
+
+/** @addtogroup TIM_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Defines
+ * @{
+ */
+
+/* ---------------------- TIM registers bit mask ------------------------ */
+#define SMCTRL_ETR_MASK ((uint16_t)0x00FF)
+#define CAPCMPMOD_OFFSET ((uint16_t)0x0018)
+#define CAPCMPEN_CCE_SET ((uint16_t)0x0001)
+#define CAPCMPEN_CCNE_SET ((uint16_t)0x0004)
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_FunctionPrototypes
+ * @{
+ */
+
+static void ConfigTI1(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter);
+static void ConfigTI2(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter);
+static void ConfigTI3(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter);
+static void ConfigTI4(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the TIMx peripheral registers to their default reset values.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ */
+void TIM_DeInit(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+
+ if (TIMx == TIM1)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM1, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM1, DISABLE);
+ }
+ else if (TIMx == TIM2)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM2, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM2, DISABLE);
+ }
+ else if (TIMx == TIM3)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM3, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM3, DISABLE);
+ }
+ else if (TIMx == TIM4)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM4, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM4, DISABLE);
+ }
+ else if (TIMx == TIM5)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM5, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM5, DISABLE);
+ }
+ else if (TIMx == TIM6)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM6, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM6, DISABLE);
+ }
+ else if (TIMx == TIM7)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM7, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM7, DISABLE);
+ }
+ else if (TIMx == TIM8)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM8, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM8, DISABLE);
+ }
+ else if (TIMx == TIM9)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM9, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM9, DISABLE);
+ }
+}
+
+/**
+ * @brief Initializes the TIMx Time Base Unit peripheral according to
+ * the specified parameters in the TIM_TimeBaseInitStruct.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_TimeBaseInitStruct pointer to a TIM_TimeBaseInitType
+ * structure that contains the configuration information for the
+ * specified TIM peripheral.
+ */
+void TIM_InitTimeBase(TIM_Module* TIMx, TIM_TimeBaseInitType* TIM_TimeBaseInitStruct)
+{
+ uint32_t tmpcr1 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimCntMode(TIM_TimeBaseInitStruct->CntMode));
+ assert_param(IsTimClkDiv(TIM_TimeBaseInitStruct->ClkDiv));
+
+ tmpcr1 = TIMx->CTRL1;
+
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9))
+ {
+ /* Select the Counter Mode */
+ tmpcr1 &= (uint32_t)(~((uint32_t)(TIM_CTRL1_DIR | TIM_CTRL1_CAMSEL)));
+ tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->CntMode;
+ }
+
+ if ((TIMx != TIM6) && (TIMx != TIM7))
+ {
+ /* Set the clock division */
+ tmpcr1 &= (uint32_t)(~((uint32_t)TIM_CTRL1_CLKD));
+ tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->ClkDiv;
+ }
+
+ TIMx->CTRL1 = tmpcr1;
+
+ /* Set the Autoreload value */
+ TIMx->AR = TIM_TimeBaseInitStruct->Period;
+
+ /* Set the Prescaler value */
+ TIMx->PSC = TIM_TimeBaseInitStruct->Prescaler;
+
+ if ((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ /* Set the Repetition Counter value */
+ TIMx->REPCNT = TIM_TimeBaseInitStruct->RepetCnt;
+ }
+
+ /* Generate an update event to reload the Prescaler and the Repetition counter
+ values immediately */
+ TIMx->EVTGEN = TIM_PSC_RELOAD_MODE_IMMEDIATE;
+
+ /*channel input from comp or iom*/
+ tmpcr1 = TIMx->CTRL1;
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9))
+ {
+ if (TIM_TimeBaseInitStruct->CapCh1FromCompEn)
+ tmpcr1 |= (0x01L << 11);
+ else
+ tmpcr1 &= ~(0x01L << 11);
+ }
+ if (TIMx==TIM9)
+ {
+ if (TIM_TimeBaseInitStruct->CapCh2FromCompEn)
+ tmpcr1 |= (0x01L << 12);
+ else
+ tmpcr1 &= ~(0x01L << 12);
+ if (TIM_TimeBaseInitStruct->CapCh3FromCompEn)
+ tmpcr1 |= (0x01L << 13);
+ else
+ tmpcr1 &= ~(0x01L << 13);
+ if (TIM_TimeBaseInitStruct->CapCh4FromCompEn)
+ tmpcr1 |= (0x01L << 14);
+ else
+ tmpcr1 &= ~(0x01L << 14);
+ }
+ /*etr input from comp or iom*/
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM9))
+ {
+ if (TIM_TimeBaseInitStruct->CapEtrClrFromCompEn)
+ tmpcr1 |= (0x01L << 15);
+ else
+ tmpcr1 &= ~(0x01L << 15);
+ }
+ TIMx->CTRL1 = tmpcr1;
+ /*sel etr from iom or tsc*/
+ tmpcr1 = TIMx->CTRL2;
+ if ((TIMx == TIM2) || (TIMx == TIM4))
+ {
+ if (TIM_TimeBaseInitStruct->CapEtrSelFromTscEn)
+ tmpcr1 |= (0x01L << 8);
+ else
+ tmpcr1 &= ~(0x01L << 8);
+ }
+ TIMx->CTRL2 = tmpcr1;
+}
+
+/**
+ * @brief Initializes the TIMx Channel1 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_InitOc1(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0;
+ uint32_t tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode));
+ assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState));
+ assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity));
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCEN &= (uint32_t)(~(uint32_t)TIM_CCEN_CC1EN);
+ /* Get the TIMx CCEN register value */
+ tmpccer = TIMx->CCEN;
+ /* Get the TIMx CTRL2 register value */
+ tmpcr2 = TIMx->CTRL2;
+
+ /* Get the TIMx CCMOD1 register value */
+ tmpccmrx = TIMx->CCMOD1;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_OC1M));
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_CC1SEL));
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= TIM_OCInitStruct->OcMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC1P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= TIM_OCInitStruct->OcPolarity;
+
+ /* Set the Output State */
+ tmpccer |= TIM_OCInitStruct->OutputState;
+
+ if ((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IsTimOutputNState(TIM_OCInitStruct->OutputNState));
+ assert_param(IsTimOcnPolarity(TIM_OCInitStruct->OcNPolarity));
+ assert_param(IsTimOcnIdleState(TIM_OCInitStruct->OcNIdleState));
+ assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC1NP));
+ /* Set the Output N Polarity */
+ tmpccer |= TIM_OCInitStruct->OcNPolarity;
+
+ /* Reset the Output N State */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC1NEN));
+ /* Set the Output N State */
+ tmpccer |= TIM_OCInitStruct->OutputNState;
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI1));
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI1N));
+
+ /* Set the Output Idle state */
+ tmpcr2 |= TIM_OCInitStruct->OcIdleState;
+ /* Set the Output N Idle state */
+ tmpcr2 |= TIM_OCInitStruct->OcNIdleState;
+ }
+ /* Write to TIMx CTRL2 */
+ TIMx->CTRL2 = tmpcr2;
+
+ /* Write to TIMx CCMOD1 */
+ TIMx->CCMOD1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCDAT1 = TIM_OCInitStruct->Pulse;
+
+ /* Write to TIMx CCEN */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel2 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select
+ * the TIM peripheral.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_InitOc2(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0;
+ uint32_t tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode));
+ assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState));
+ assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity));
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC2EN));
+
+ /* Get the TIMx CCEN register value */
+ tmpccer = TIMx->CCEN;
+ /* Get the TIMx CTRL2 register value */
+ tmpcr2 = TIMx->CTRL2;
+
+ /* Get the TIMx CCMOD1 register value */
+ tmpccmrx = TIMx->CCMOD1;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_OC2M));
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_CC2SEL));
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC2P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 4);
+
+ /* Set the Output State */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 4);
+
+ if ((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IsTimOutputNState(TIM_OCInitStruct->OutputNState));
+ assert_param(IsTimOcnPolarity(TIM_OCInitStruct->OcNPolarity));
+ assert_param(IsTimOcnIdleState(TIM_OCInitStruct->OcNIdleState));
+ assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC2NP));
+ /* Set the Output N Polarity */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OcNPolarity << 4);
+
+ /* Reset the Output N State */
+ tmpccer &= (uint32_t)(~((uint16_t)TIM_CCEN_CC2NEN));
+ /* Set the Output N State */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputNState << 4);
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI2));
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI2N));
+
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 2);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcNIdleState << 2);
+ }
+ /* Write to TIMx CTRL2 */
+ TIMx->CTRL2 = tmpcr2;
+
+ /* Write to TIMx CCMOD1 */
+ TIMx->CCMOD1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCDAT2 = TIM_OCInitStruct->Pulse;
+
+ /* Write to TIMx CCEN */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel3 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_InitOc3(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0;
+ uint32_t tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode));
+ assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState));
+ assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity));
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC3EN));
+
+ /* Get the TIMx CCEN register value */
+ tmpccer = TIMx->CCEN;
+ /* Get the TIMx CTRL2 register value */
+ tmpcr2 = TIMx->CTRL2;
+
+ /* Get the TIMx CCMOD2 register value */
+ tmpccmrx = TIMx->CCMOD2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_OC3MD));
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_CC3SEL));
+ /* Select the Output Compare Mode */
+ tmpccmrx |= TIM_OCInitStruct->OcMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)(~((uint16_t)TIM_CCEN_CC3P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 8);
+
+ /* Set the Output State */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 8);
+
+ if ((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IsTimOutputNState(TIM_OCInitStruct->OutputNState));
+ assert_param(IsTimOcnPolarity(TIM_OCInitStruct->OcNPolarity));
+ assert_param(IsTimOcnIdleState(TIM_OCInitStruct->OcNIdleState));
+ assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC3NP));
+ /* Set the Output N Polarity */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OcNPolarity << 8);
+ /* Reset the Output N State */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC3NEN));
+
+ /* Set the Output N State */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputNState << 8);
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI3));
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI3N));
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 4);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcNIdleState << 4);
+ }
+ /* Write to TIMx CTRL2 */
+ TIMx->CTRL2 = tmpcr2;
+
+ /* Write to TIMx CCMOD2 */
+ TIMx->CCMOD2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCDAT3 = TIM_OCInitStruct->Pulse;
+
+ /* Write to TIMx CCEN */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel4 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_InitOc4(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0;
+ uint32_t tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode));
+ assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState));
+ assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity));
+ /* Disable the Channel 2: Reset the CC4E Bit */
+ TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC4EN));
+
+ /* Get the TIMx CCEN register value */
+ tmpccer = TIMx->CCEN;
+ /* Get the TIMx CTRL2 register value */
+ tmpcr2 = TIMx->CTRL2;
+
+ /* Get the TIMx CCMOD2 register value */
+ tmpccmrx = TIMx->CCMOD2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_OC4MD));
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_CC4SEL));
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC4P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 12);
+
+ /* Set the Output State */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 12);
+
+ if ((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState));
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI4));
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 6);
+ }
+ /* Write to TIMx CTRL2 */
+ TIMx->CTRL2 = tmpcr2;
+
+ /* Write to TIMx CCMOD2 */
+ TIMx->CCMOD2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCDAT4 = TIM_OCInitStruct->Pulse;
+
+ /* Write to TIMx CCEN */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel5 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_InitOc5(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0;
+ uint32_t tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode));
+ assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState));
+ assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity));
+ /* Disable the Channel 5: Reset the CC5E Bit */
+ TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC5EN));
+
+ /* Get the TIMx CCEN register value */
+ tmpccer = TIMx->CCEN;
+ /* Get the TIMx CTRL2 register value */
+ tmpcr2 = TIMx->CTRL2;
+
+ /* Get the TIMx CCMOD3 register value */
+ tmpccmrx = TIMx->CCMOD3;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD3_OC5MD));
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC5P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 16);
+
+ /* Set the Output State */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 16);
+
+ if ((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState));
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI5));
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 8);
+ }
+ /* Write to TIMx CTRL2 */
+ TIMx->CTRL2 = tmpcr2;
+
+ /* Write to TIMx CCMOD3 */
+ TIMx->CCMOD3 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCDAT5 = TIM_OCInitStruct->Pulse;
+
+ /* Write to TIMx CCEN */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel6 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_InitOc6(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0;
+ uint32_t tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode));
+ assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState));
+ assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity));
+ /* Disable the Channel 6: Reset the CC6E Bit */
+ TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC6EN));
+
+ /* Get the TIMx CCEN register value */
+ tmpccer = TIMx->CCEN;
+ /* Get the TIMx CTRL2 register value */
+ tmpcr2 = TIMx->CTRL2;
+
+ /* Get the TIMx CCMOD3 register value */
+ tmpccmrx = TIMx->CCMOD3;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD3_OC6MD));
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC6P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 20);
+
+ /* Set the Output State */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 20);
+
+ if ((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState));
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI6));
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 10);
+ }
+ /* Write to TIMx CTRL2 */
+ TIMx->CTRL2 = tmpcr2;
+
+ /* Write to TIMx CCMOD3 */
+ TIMx->CCMOD3 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCDAT6 = TIM_OCInitStruct->Pulse;
+
+ /* Write to TIMx CCEN */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIM peripheral according to the specified
+ * parameters in the TIM_ICInitStruct.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_ICInitStruct pointer to a TIM_ICInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_ICInit(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IsTimCh(TIM_ICInitStruct->Channel));
+ assert_param(IsTimIcSelection(TIM_ICInitStruct->IcSelection));
+ assert_param(IsTimIcPrescaler(TIM_ICInitStruct->IcPrescaler));
+ assert_param(IsTimInCapFilter(TIM_ICInitStruct->IcFilter));
+
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9))
+ {
+ assert_param(IsTimIcPalaritySingleEdge(TIM_ICInitStruct->IcPolarity));
+ }
+ else
+ {
+ assert_param(IsTimIcPolarityAnyEdge(TIM_ICInitStruct->IcPolarity));
+ }
+ if (TIM_ICInitStruct->Channel == TIM_CH_1)
+ {
+ assert_param(IsTimList8Module(TIMx));
+ /* TI1 Configuration */
+ ConfigTI1(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap1Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ }
+ else if (TIM_ICInitStruct->Channel == TIM_CH_2)
+ {
+ assert_param(IsTimList6Module(TIMx));
+ /* TI2 Configuration */
+ ConfigTI2(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap2Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ }
+ else if (TIM_ICInitStruct->Channel == TIM_CH_3)
+ {
+ assert_param(IsTimList3Module(TIMx));
+ /* TI3 Configuration */
+ ConfigTI3(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap3Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ }
+ else
+ {
+ assert_param(IsTimList3Module(TIMx));
+ /* TI4 Configuration */
+ ConfigTI4(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap4Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ }
+}
+
+/**
+ * @brief Configures the TIM peripheral according to the specified
+ * parameters in the TIM_ICInitStruct to measure an external PWM signal.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param TIM_ICInitStruct pointer to a TIM_ICInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_ConfigPwmIc(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct)
+{
+ uint16_t icoppositepolarity = TIM_IC_POLARITY_RISING;
+ uint16_t icoppositeselection = TIM_IC_SELECTION_DIRECTTI;
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ /* Select the Opposite Input Polarity */
+ if (TIM_ICInitStruct->IcPolarity == TIM_IC_POLARITY_RISING)
+ {
+ icoppositepolarity = TIM_IC_POLARITY_FALLING;
+ }
+ else
+ {
+ icoppositepolarity = TIM_IC_POLARITY_RISING;
+ }
+ /* Select the Opposite Input */
+ if (TIM_ICInitStruct->IcSelection == TIM_IC_SELECTION_DIRECTTI)
+ {
+ icoppositeselection = TIM_IC_SELECTION_INDIRECTTI;
+ }
+ else
+ {
+ icoppositeselection = TIM_IC_SELECTION_DIRECTTI;
+ }
+ if (TIM_ICInitStruct->Channel == TIM_CH_1)
+ {
+ /* TI1 Configuration */
+ ConfigTI1(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap1Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ /* TI2 Configuration */
+ ConfigTI2(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap2Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ }
+ else
+ {
+ /* TI2 Configuration */
+ ConfigTI2(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap2Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ /* TI1 Configuration */
+ ConfigTI1(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap1Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ }
+}
+
+/**
+ * @brief Configures the: Break feature, dead time, Lock level, the OSSI,
+ * the OSSR State and the AOE(automatic output enable).
+ * @param TIMx where x can be 1 or 8 to select the TIM
+ * @param TIM_BDTRInitStruct pointer to a TIM_BDTRInitType structure that
+ * contains the BKDT Register configuration information for the TIM peripheral.
+ */
+void TIM_ConfigBkdt(TIM_Module* TIMx, TIM_BDTRInitType* TIM_BDTRInitStruct)
+{
+ uint32_t tmp;
+ /* Check the parameters */
+ assert_param(IsTimList2Module(TIMx));
+ assert_param(IsTimOssrState(TIM_BDTRInitStruct->OssrState));
+ assert_param(IsTimOssiState(TIM_BDTRInitStruct->OssiState));
+ assert_param(IsTimLockLevel(TIM_BDTRInitStruct->LockLevel));
+ assert_param(IsTimBreakInState(TIM_BDTRInitStruct->Break));
+ assert_param(IsTimBreakPalarity(TIM_BDTRInitStruct->BreakPolarity));
+ assert_param(IsTimAutoOutputState(TIM_BDTRInitStruct->AutomaticOutput));
+ /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */
+ TIMx->BKDT = (uint32_t)TIM_BDTRInitStruct->OssrState | TIM_BDTRInitStruct->OssiState | TIM_BDTRInitStruct->LockLevel
+ | TIM_BDTRInitStruct->DeadTime | TIM_BDTRInitStruct->Break | TIM_BDTRInitStruct->BreakPolarity
+ | TIM_BDTRInitStruct->AutomaticOutput;
+
+ /*cofigure other break in*/
+ tmp = TIMx->CTRL1;
+ /*IOMBKPEN 0 meaning iom as break enable*/
+ if (TIM_BDTRInitStruct->IomBreakEn)
+ tmp &= ~(0x01L << 10);
+ else
+ tmp |= (0x01L << 10);
+ if (TIM_BDTRInitStruct->LockUpBreakEn)
+ tmp |= (0x01L << 16);
+ else
+ tmp &= ~(0x01L << 16);
+ if (TIM_BDTRInitStruct->PvdBreakEn)
+ tmp |= (0x01L << 17);
+ else
+ tmp &= ~(0x01L << 17);
+ TIMx->CTRL1 = tmp;
+}
+
+/**
+ * @brief Fills each TIM_TimeBaseInitStruct member with its default value.
+ * @param TIM_TimeBaseInitStruct pointer to a TIM_TimeBaseInitType
+ * structure which will be initialized.
+ */
+void TIM_InitTimBaseStruct(TIM_TimeBaseInitType* TIM_TimeBaseInitStruct)
+{
+ /* Set the default configuration */
+ TIM_TimeBaseInitStruct->Period = 0xFFFF;
+ TIM_TimeBaseInitStruct->Prescaler = 0x0000;
+ TIM_TimeBaseInitStruct->ClkDiv = TIM_CLK_DIV1;
+ TIM_TimeBaseInitStruct->CntMode = TIM_CNT_MODE_UP;
+ TIM_TimeBaseInitStruct->RepetCnt = 0x0000;
+
+ TIM_TimeBaseInitStruct->CapCh1FromCompEn = false;
+ TIM_TimeBaseInitStruct->CapCh2FromCompEn = false;
+ TIM_TimeBaseInitStruct->CapCh3FromCompEn = false;
+ TIM_TimeBaseInitStruct->CapCh4FromCompEn = false;
+ TIM_TimeBaseInitStruct->CapEtrClrFromCompEn = false;
+ TIM_TimeBaseInitStruct->CapEtrSelFromTscEn = false;
+}
+
+/**
+ * @brief Fills each TIM_OCInitStruct member with its default value.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure which will
+ * be initialized.
+ */
+void TIM_InitOcStruct(OCInitType* TIM_OCInitStruct)
+{
+ /* Set the default configuration */
+ TIM_OCInitStruct->OcMode = TIM_OCMODE_TIMING;
+ TIM_OCInitStruct->OutputState = TIM_OUTPUT_STATE_DISABLE;
+ TIM_OCInitStruct->OutputNState = TIM_OUTPUT_NSTATE_DISABLE;
+ TIM_OCInitStruct->Pulse = 0x0000;
+ TIM_OCInitStruct->OcPolarity = TIM_OC_POLARITY_HIGH;
+ TIM_OCInitStruct->OcNPolarity = TIM_OC_POLARITY_HIGH;
+ TIM_OCInitStruct->OcIdleState = TIM_OC_IDLE_STATE_RESET;
+ TIM_OCInitStruct->OcNIdleState = TIM_OCN_IDLE_STATE_RESET;
+}
+
+/**
+ * @brief Fills each TIM_ICInitStruct member with its default value.
+ * @param TIM_ICInitStruct pointer to a TIM_ICInitType structure which will
+ * be initialized.
+ */
+void TIM_InitIcStruct(TIM_ICInitType* TIM_ICInitStruct)
+{
+ /* Set the default configuration */
+ TIM_ICInitStruct->Channel = TIM_CH_1;
+ TIM_ICInitStruct->IcPolarity = TIM_IC_POLARITY_RISING;
+ TIM_ICInitStruct->IcSelection = TIM_IC_SELECTION_DIRECTTI;
+ TIM_ICInitStruct->IcPrescaler = TIM_IC_PSC_DIV1;
+ TIM_ICInitStruct->IcFilter = 0x00;
+}
+
+/**
+ * @brief Fills each TIM_BDTRInitStruct member with its default value.
+ * @param TIM_BDTRInitStruct pointer to a TIM_BDTRInitType structure which
+ * will be initialized.
+ */
+void TIM_InitBkdtStruct(TIM_BDTRInitType* TIM_BDTRInitStruct)
+{
+ /* Set the default configuration */
+ TIM_BDTRInitStruct->OssrState = TIM_OSSR_STATE_DISABLE;
+ TIM_BDTRInitStruct->OssiState = TIM_OSSI_STATE_DISABLE;
+ TIM_BDTRInitStruct->LockLevel = TIM_LOCK_LEVEL_OFF;
+ TIM_BDTRInitStruct->DeadTime = 0x00;
+ TIM_BDTRInitStruct->Break = TIM_BREAK_IN_DISABLE;
+ TIM_BDTRInitStruct->BreakPolarity = TIM_BREAK_POLARITY_LOW;
+ TIM_BDTRInitStruct->AutomaticOutput = TIM_AUTO_OUTPUT_DISABLE;
+}
+
+/**
+ * @brief Enables or disables the specified TIM peripheral.
+ * @param TIMx where x can be 1 to 8 to select the TIMx peripheral.
+ * @param Cmd new state of the TIMx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_Enable(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the TIM Counter */
+ TIMx->CTRL1 |= TIM_CTRL1_CNTEN;
+ }
+ else
+ {
+ /* Disable the TIM Counter */
+ TIMx->CTRL1 &= (uint32_t)(~((uint32_t)TIM_CTRL1_CNTEN));
+ }
+}
+
+/**
+ * @brief Enables or disables the TIM peripheral Main Outputs.
+ * @param TIMx where x can be 1, 8 to select the TIMx peripheral.
+ * @param Cmd new state of the TIM peripheral Main Outputs.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_EnableCtrlPwmOutputs(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimList2Module(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the TIM Main Output */
+ TIMx->BKDT |= TIM_BKDT_MOEN;
+ }
+ else
+ {
+ /* Disable the TIM Main Output */
+ TIMx->BKDT &= (uint16_t)(~((uint16_t)TIM_BKDT_MOEN));
+ }
+}
+
+/**
+ * @brief Enables or disables the specified TIM interrupts.
+ * @param TIMx where x can be 1 to 8 to select the TIMx peripheral.
+ * @param TIM_IT specifies the TIM interrupts sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_INT_UPDATE TIM update Interrupt source
+ * @arg TIM_INT_CC1 TIM Capture Compare 1 Interrupt source
+ * @arg TIM_INT_CC2 TIM Capture Compare 2 Interrupt source
+ * @arg TIM_INT_CC3 TIM Capture Compare 3 Interrupt source
+ * @arg TIM_INT_CC4 TIM Capture Compare 4 Interrupt source
+ * @arg TIM_INT_COM TIM Commutation Interrupt source
+ * @arg TIM_INT_TRIG TIM Trigger Interrupt source
+ * @arg TIM_INT_BREAK TIM Break Interrupt source
+ * @note
+ * - TIM6 and TIM7 can only generate an update interrupt.
+ * - TIM_INT_BREAK is used only with TIM1, TIM8.
+ * - TIM_INT_COM is used only with TIM1, TIM8.
+ * @param Cmd new state of the TIM interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_ConfigInt(TIM_Module* TIMx, uint16_t TIM_IT, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimInt(TIM_IT));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the Interrupt sources */
+ TIMx->DINTEN |= TIM_IT;
+ }
+ else
+ {
+ /* Disable the Interrupt sources */
+ TIMx->DINTEN &= (uint16_t)~TIM_IT;
+ }
+}
+
+/**
+ * @brief Configures the TIMx event to be generate by software.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_EventSource specifies the event source.
+ * This parameter can be one or more of the following values:
+ * @arg TIM_EVT_SRC_UPDATE Timer update Event source
+ * @arg TIM_EVT_SRC_CC1 Timer Capture Compare 1 Event source
+ * @arg TIM_EVT_SRC_CC2 Timer Capture Compare 2 Event source
+ * @arg TIM_EVT_SRC_CC3 Timer Capture Compare 3 Event source
+ * @arg TIM_EVT_SRC_CC4 Timer Capture Compare 4 Event source
+ * @arg TIM_EVT_SRC_COM Timer COM event source
+ * @arg TIM_EVT_SRC_TRIG Timer Trigger Event source
+ * @arg TIM_EVT_SRC_BREAK Timer Break event source
+ * @note
+ * - TIM6 and TIM7 can only generate an update event.
+ * - TIM_EVT_SRC_COM and TIM_EVT_SRC_BREAK are used only with TIM1 and TIM8.
+ */
+void TIM_GenerateEvent(TIM_Module* TIMx, uint16_t TIM_EventSource)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimEvtSrc(TIM_EventSource));
+
+ /* Set the event sources */
+ TIMx->EVTGEN = TIM_EventSource;
+}
+
+/**
+ * @brief Configures the TIMx's DMA interface.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select
+ * the TIM peripheral.
+ * @param TIM_DMABase DMA Base address.
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABase_CR, TIM_DMABASE_CTRL2, TIM_DMABASE_SMCTRL,
+ * TIM_DMABASE_DMAINTEN, TIM1_DMABase_SR, TIM_DMABASE_EVTGEN,
+ * TIM_DMABASE_CAPCMPMOD1, TIM_DMABASE_CAPCMPMOD2, TIM_DMABASE_CAPCMPEN,
+ * TIM_DMABASE_CNT, TIM_DMABASE_PSC, TIM_DMABASE_AR,
+ * TIM_DMABASE_REPCNT, TIM_DMABASE_CAPCMPDAT1, TIM_DMABASE_CAPCMPDAT2,
+ * TIM_DMABASE_CAPCMPDAT3, TIM_DMABASE_CAPCMPDAT4, TIM_DMABASE_BKDT,
+ * TIM_DMABASE_DMACTRL.
+ * @param TIM_DMABurstLength DMA Burst length.
+ * This parameter can be one value between:
+ * TIM_DMABURST_LENGTH_1TRANSFER and TIM_DMABURST_LENGTH_18TRANSFERS.
+ */
+void TIM_ConfigDma(TIM_Module* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
+{
+ /* Check the parameters */
+ assert_param(IsTimList4Module(TIMx));
+ assert_param(IsTimDmaBase(TIM_DMABase));
+ assert_param(IsTimDmaLength(TIM_DMABurstLength));
+ /* Set the DMA Base and the DMA Burst Length */
+ TIMx->DCTRL = TIM_DMABase | TIM_DMABurstLength;
+}
+
+/**
+ * @brief Enables or disables the TIMx's DMA Requests.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 6, 7, 8
+ * to select the TIM peripheral.
+ * @param TIM_DMASource specifies the DMA Request sources.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_DMA_UPDATE TIM update Interrupt source
+ * @arg TIM_DMA_CC1 TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2 TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3 TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4 TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM TIM Commutation DMA source
+ * @arg TIM_DMA_TRIG TIM Trigger DMA source
+ * @param Cmd new state of the DMA Request sources.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_EnableDma(TIM_Module* TIMx, uint16_t TIM_DMASource, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimList9Module(TIMx));
+ assert_param(IsTimDmaSrc(TIM_DMASource));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the DMA sources */
+ TIMx->DINTEN |= TIM_DMASource;
+ }
+ else
+ {
+ /* Disable the DMA sources */
+ TIMx->DINTEN &= (uint16_t)~TIM_DMASource;
+ }
+}
+
+/**
+ * @brief Configures the TIMx internal Clock
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8
+ * to select the TIM peripheral.
+ */
+void TIM_ConfigInternalClk(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ /* Disable slave mode to clock the prescaler directly with the internal clock */
+ TIMx->SMCTRL &= (uint16_t)(~((uint16_t)TIM_SMCTRL_SMSEL));
+}
+
+/**
+ * @brief Configures the TIMx Internal Trigger as External Clock
+ * @param TIMx where x can be 1, 2, 3, 4, 5 to select the TIM peripheral.
+ * @param TIM_InputTriggerSource Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TRIG_SEL_IN_TR0 Internal Trigger 0
+ * @arg TIM_TRIG_SEL_IN_TR1 Internal Trigger 1
+ * @arg TIM_TRIG_SEL_IN_TR2 Internal Trigger 2
+ * @arg TIM_TRIG_SEL_IN_TR3 Internal Trigger 3
+ */
+void TIM_ConfigInternalTrigToExt(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimInterTrigSel(TIM_InputTriggerSource));
+ /* Select the Internal Trigger */
+ TIM_SelectInputTrig(TIMx, TIM_InputTriggerSource);
+ /* Select the External clock mode1 */
+ TIMx->SMCTRL |= TIM_SLAVE_MODE_EXT1;
+}
+
+/**
+ * @brief Configures the TIMx Trigger as External Clock
+ * @param TIMx where x can be 1, 2, 3, 4, 5 to select the TIM peripheral.
+ * @param TIM_TIxExternalCLKSource Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_EXT_CLK_SRC_TI1ED TI1 Edge Detector
+ * @arg TIM_EXT_CLK_SRC_TI1 Filtered Timer Input 1
+ * @arg TIM_EXT_CLK_SRC_TI2 Filtered Timer Input 2
+ * @param IcPolarity specifies the TIx Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_POLARITY_RISING
+ * @arg TIM_IC_POLARITY_FALLING
+ * @param ICFilter specifies the filter value.
+ * This parameter must be a value between 0x0 and 0xF.
+ */
+void TIM_ConfigExtTrigAsClk(TIM_Module* TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t IcPolarity, uint16_t ICFilter)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimExtClkSrc(TIM_TIxExternalCLKSource));
+ assert_param(IsTimIcPalaritySingleEdge(IcPolarity));
+ assert_param(IsTimInCapFilter(ICFilter));
+ /* Configure the Timer Input Clock Source */
+ if (TIM_TIxExternalCLKSource == TIM_EXT_CLK_SRC_TI2)
+ {
+ ConfigTI2(TIMx, IcPolarity, TIM_IC_SELECTION_DIRECTTI, ICFilter);
+ }
+ else
+ {
+ ConfigTI1(TIMx, IcPolarity, TIM_IC_SELECTION_DIRECTTI, ICFilter);
+ }
+ /* Select the Trigger source */
+ TIM_SelectInputTrig(TIMx, TIM_TIxExternalCLKSource);
+ /* Select the External clock mode1 */
+ TIMx->SMCTRL |= TIM_SLAVE_MODE_EXT1;
+}
+
+/**
+ * @brief Configures the External clock Mode1
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_EXT_TRG_PSC_OFF ETRP Prescaler OFF.
+ * @arg TIM_EXT_TRG_PSC_DIV2 ETRP frequency divided by 2.
+ * @arg TIM_EXT_TRG_PSC_DIV4 ETRP frequency divided by 4.
+ * @arg TIM_EXT_TRG_PSC_DIV8 ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_EXT_TRIG_POLARITY_INVERTED active low or falling edge active.
+ * @arg TIM_EXT_TRIG_POLARITY_NONINVERTED active high or rising edge active.
+ * @param ExtTRGFilter External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ */
+void TIM_ConfigExtClkMode1(TIM_Module* TIMx,
+ uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter)
+{
+ uint16_t tmpsmcr = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimExtPreDiv(TIM_ExtTRGPrescaler));
+ assert_param(IsTimExtTrigPolarity(TIM_ExtTRGPolarity));
+ assert_param(IsTimExtTrigFilter(ExtTRGFilter));
+ /* Configure the ETR Clock source */
+ TIM_ConfigExtTrig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+
+ /* Get the TIMx SMCTRL register value */
+ tmpsmcr = TIMx->SMCTRL;
+ /* Reset the SMS Bits */
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_SMSEL));
+ /* Select the External clock mode1 */
+ tmpsmcr |= TIM_SLAVE_MODE_EXT1;
+ /* Select the Trigger selection : ETRF */
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_TSEL));
+ tmpsmcr |= TIM_TRIG_SEL_ETRF;
+ /* Write to TIMx SMCTRL */
+ TIMx->SMCTRL = tmpsmcr;
+}
+
+/**
+ * @brief Configures the External clock Mode2
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_EXT_TRG_PSC_OFF ETRP Prescaler OFF.
+ * @arg TIM_EXT_TRG_PSC_DIV2 ETRP frequency divided by 2.
+ * @arg TIM_EXT_TRG_PSC_DIV4 ETRP frequency divided by 4.
+ * @arg TIM_EXT_TRG_PSC_DIV8 ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_EXT_TRIG_POLARITY_INVERTED active low or falling edge active.
+ * @arg TIM_EXT_TRIG_POLARITY_NONINVERTED active high or rising edge active.
+ * @param ExtTRGFilter External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ */
+void TIM_ConfigExtClkMode2(TIM_Module* TIMx,
+ uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter)
+{
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimExtPreDiv(TIM_ExtTRGPrescaler));
+ assert_param(IsTimExtTrigPolarity(TIM_ExtTRGPolarity));
+ assert_param(IsTimExtTrigFilter(ExtTRGFilter));
+ /* Configure the ETR Clock source */
+ TIM_ConfigExtTrig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+ /* Enable the External clock mode2 */
+ TIMx->SMCTRL |= TIM_SMCTRL_EXCEN;
+}
+
+/**
+ * @brief Configures the TIMx External Trigger (ETR).
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_EXT_TRG_PSC_OFF ETRP Prescaler OFF.
+ * @arg TIM_EXT_TRG_PSC_DIV2 ETRP frequency divided by 2.
+ * @arg TIM_EXT_TRG_PSC_DIV4 ETRP frequency divided by 4.
+ * @arg TIM_EXT_TRG_PSC_DIV8 ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_EXT_TRIG_POLARITY_INVERTED active low or falling edge active.
+ * @arg TIM_EXT_TRIG_POLARITY_NONINVERTED active high or rising edge active.
+ * @param ExtTRGFilter External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ */
+void TIM_ConfigExtTrig(TIM_Module* TIMx,
+ uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter)
+{
+ uint16_t tmpsmcr = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimExtPreDiv(TIM_ExtTRGPrescaler));
+ assert_param(IsTimExtTrigPolarity(TIM_ExtTRGPolarity));
+ assert_param(IsTimExtTrigFilter(ExtTRGFilter));
+ tmpsmcr = TIMx->SMCTRL;
+ /* Reset the ETR Bits */
+ tmpsmcr &= SMCTRL_ETR_MASK;
+ /* Set the Prescaler, the Filter value and the Polarity */
+ tmpsmcr |=
+ (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
+ /* Write to TIMx SMCTRL */
+ TIMx->SMCTRL = tmpsmcr;
+}
+
+/**
+ * @brief Configures the TIMx Prescaler.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param Prescaler specifies the Prescaler Register value
+ * @param TIM_PSCReloadMode specifies the TIM Prescaler Reload mode
+ * This parameter can be one of the following values:
+ * @arg TIM_PSC_RELOAD_MODE_UPDATE The Prescaler is loaded at the update event.
+ * @arg TIM_PSC_RELOAD_MODE_IMMEDIATE The Prescaler is loaded immediately.
+ */
+void TIM_ConfigPrescaler(TIM_Module* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimPscReloadMode(TIM_PSCReloadMode));
+ /* Set the Prescaler value */
+ TIMx->PSC = Prescaler;
+ /* Set or reset the UG Bit */
+ TIMx->EVTGEN = TIM_PSCReloadMode;
+}
+
+/**
+ * @brief Specifies the TIMx Counter Mode to be used.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param CntMode specifies the Counter Mode to be used
+ * This parameter can be one of the following values:
+ * @arg TIM_CNT_MODE_UP TIM Up Counting Mode
+ * @arg TIM_CNT_MODE_DOWN TIM Down Counting Mode
+ * @arg TIM_CNT_MODE_CENTER_ALIGN1 TIM Center Aligned Mode1
+ * @arg TIM_CNT_MODE_CENTER_ALIGN2 TIM Center Aligned Mode2
+ * @arg TIM_CNT_MODE_CENTER_ALIGN3 TIM Center Aligned Mode3
+ */
+void TIM_ConfigCntMode(TIM_Module* TIMx, uint16_t CntMode)
+{
+ uint32_t tmpcr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimCntMode(CntMode));
+ tmpcr1 = TIMx->CTRL1;
+ /* Reset the CMS and DIR Bits */
+ tmpcr1 &= (uint32_t)(~((uint32_t)(TIM_CTRL1_DIR | TIM_CTRL1_CAMSEL)));
+ /* Set the Counter Mode */
+ tmpcr1 |= CntMode;
+ /* Write to TIMx CTRL1 register */
+ TIMx->CTRL1 = tmpcr1;
+}
+
+/**
+ * @brief Selects the Input Trigger source
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param TIM_InputTriggerSource The Input Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TRIG_SEL_IN_TR0 Internal Trigger 0
+ * @arg TIM_TRIG_SEL_IN_TR1 Internal Trigger 1
+ * @arg TIM_TRIG_SEL_IN_TR2 Internal Trigger 2
+ * @arg TIM_TRIG_SEL_IN_TR3 Internal Trigger 3
+ * @arg TIM_TRIG_SEL_TI1F_ED TI1 Edge Detector
+ * @arg TIM_TRIG_SEL_TI1FP1 Filtered Timer Input 1
+ * @arg TIM_TRIG_SEL_TI2FP2 Filtered Timer Input 2
+ * @arg TIM_TRIG_SEL_ETRF External Trigger input
+ */
+void TIM_SelectInputTrig(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource)
+{
+ uint16_t tmpsmcr = 0;
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimTrigSel(TIM_InputTriggerSource));
+ /* Get the TIMx SMCTRL register value */
+ tmpsmcr = TIMx->SMCTRL;
+ /* Reset the TS Bits */
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_TSEL));
+ /* Set the Input Trigger source */
+ tmpsmcr |= TIM_InputTriggerSource;
+ /* Write to TIMx SMCTRL */
+ TIMx->SMCTRL = tmpsmcr;
+}
+
+/**
+ * @brief Configures the TIMx Encoder Interface.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_EncoderMode specifies the TIMx Encoder Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_ENCODE_MODE_TI1 Counter counts on TI1FP1 edge depending on TI2FP2 level.
+ * @arg TIM_ENCODE_MODE_TI2 Counter counts on TI2FP2 edge depending on TI1FP1 level.
+ * @arg TIM_ENCODE_MODE_TI12 Counter counts on both TI1FP1 and TI2FP2 edges depending
+ * on the level of the other input.
+ * @param TIM_IC1Polarity specifies the IC1 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_POLARITY_FALLING IC Falling edge.
+ * @arg TIM_IC_POLARITY_RISING IC Rising edge.
+ * @param TIM_IC2Polarity specifies the IC2 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_POLARITY_FALLING IC Falling edge.
+ * @arg TIM_IC_POLARITY_RISING IC Rising edge.
+ */
+void TIM_ConfigEncoderInterface(TIM_Module* TIMx,
+ uint16_t TIM_EncoderMode,
+ uint16_t TIM_IC1Polarity,
+ uint16_t TIM_IC2Polarity)
+{
+ uint16_t tmpsmcr = 0;
+ uint16_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList5Module(TIMx));
+ assert_param(IsTimEncodeMode(TIM_EncoderMode));
+ assert_param(IsTimIcPalaritySingleEdge(TIM_IC1Polarity));
+ assert_param(IsTimIcPalaritySingleEdge(TIM_IC2Polarity));
+
+ /* Get the TIMx SMCTRL register value */
+ tmpsmcr = TIMx->SMCTRL;
+
+ /* Get the TIMx CCMOD1 register value */
+ tmpccmr1 = TIMx->CCMOD1;
+
+ /* Get the TIMx CCEN register value */
+ tmpccer = TIMx->CCEN;
+
+ /* Set the encoder Mode */
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_SMSEL));
+ tmpsmcr |= TIM_EncoderMode;
+
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+ tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD1_CC1SEL)) & (uint16_t)(~((uint16_t)TIM_CCMOD1_CC2SEL)));
+ tmpccmr1 |= TIM_CCMOD1_CC1SEL_0 | TIM_CCMOD1_CC2SEL_0;
+
+ /* Set the TI1 and the TI2 Polarities */
+ tmpccer &= (uint32_t)(((uint32_t) ~((uint32_t)TIM_CCEN_CC1P)) & ((uint32_t) ~((uint32_t)TIM_CCEN_CC2P)));
+ tmpccer |= (uint32_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
+
+ /* Write to TIMx SMCTRL */
+ TIMx->SMCTRL = tmpsmcr;
+ /* Write to TIMx CCMOD1 */
+ TIMx->CCMOD1 = tmpccmr1;
+ /* Write to TIMx CCEN */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Forces the TIMx output 1 waveform to active or inactive level.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC1REF
+ * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC1REF.
+ */
+void TIM_ConfigForcedOc1(TIM_Module* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimForceActive(TIM_ForcedAction));
+ tmpccmr1 = TIMx->CCMOD1;
+ /* Reset the OC1M Bits */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1M);
+ /* Configure The Forced output Mode */
+ tmpccmr1 |= TIM_ForcedAction;
+ /* Write to TIMx CCMOD1 register */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Forces the TIMx output 2 waveform to active or inactive level.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC2REF
+ * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC2REF.
+ */
+void TIM_ConfigForcedOc2(TIM_Module* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimForceActive(TIM_ForcedAction));
+ tmpccmr1 = TIMx->CCMOD1;
+ /* Reset the OC2M Bits */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2M);
+ /* Configure The Forced output Mode */
+ tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
+ /* Write to TIMx CCMOD1 register */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Forces the TIMx output 3 waveform to active or inactive level.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC3REF
+ * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC3REF.
+ */
+void TIM_ConfigForcedOc3(TIM_Module* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimForceActive(TIM_ForcedAction));
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC1M Bits */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3MD);
+ /* Configure The Forced output Mode */
+ tmpccmr2 |= TIM_ForcedAction;
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Forces the TIMx output 4 waveform to active or inactive level.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC4REF
+ * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC4REF.
+ */
+void TIM_ConfigForcedOc4(TIM_Module* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimForceActive(TIM_ForcedAction));
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC2M Bits */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4MD);
+ /* Configure The Forced output Mode */
+ tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Forces the TIMx output 5 waveform to active or inactive level.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC5REF
+ * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC5REF.
+ */
+void TIM_ConfigForcedOc5(TIM_Module* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimForceActive(TIM_ForcedAction));
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC2M Bits */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5MD);
+ /* Configure The Forced output Mode */
+ tmpccmr3 |= (uint16_t)(TIM_ForcedAction);
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Forces the TIMx output 6 waveform to active or inactive level.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC6REF
+ * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC6REF.
+ */
+void TIM_ConfigForcedOc6(TIM_Module* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimForceActive(TIM_ForcedAction));
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC2M Bits */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6MD);
+ /* Configure The Forced output Mode */
+ tmpccmr3 |= (uint16_t)(TIM_ForcedAction << 8);
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Enables or disables TIMx peripheral Preload register on AR.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param Cmd new state of the TIMx peripheral Preload register
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_ConfigArPreload(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set the AR Preload Bit */
+ TIMx->CTRL1 |= TIM_CTRL1_ARPEN;
+ }
+ else
+ {
+ /* Reset the AR Preload Bit */
+ TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_ARPEN);
+ }
+}
+
+/**
+ * @brief Selects the TIM peripheral Commutation event.
+ * @param TIMx where x can be 1, 8 to select the TIMx peripheral
+ * @param Cmd new state of the Commutation event.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_SelectComEvt(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimList2Module(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set the COM Bit */
+ TIMx->CTRL2 |= TIM_CTRL2_CCUSEL;
+ }
+ else
+ {
+ /* Reset the COM Bit */
+ TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_CCUSEL);
+ }
+}
+
+/**
+ * @brief Selects the TIMx peripheral Capture Compare DMA source.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select
+ * the TIM peripheral.
+ * @param Cmd new state of the Capture Compare DMA source
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_SelectCapCmpDmaSrc(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimList4Module(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set the CCDS Bit */
+ TIMx->CTRL2 |= TIM_CTRL2_CCDSEL;
+ }
+ else
+ {
+ /* Reset the CCDS Bit */
+ TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_CCDSEL);
+ }
+}
+
+/**
+ * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8
+ * to select the TIMx peripheral
+ * @param Cmd new state of the Capture Compare Preload Control bit
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_EnableCapCmpPreloadControl(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimList5Module(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set the CCPC Bit */
+ TIMx->CTRL2 |= TIM_CTRL2_CCPCTL;
+ }
+ else
+ {
+ /* Reset the CCPC Bit */
+ TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_CCPCTL);
+ }
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCDAT1.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_OCPreload new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_PRE_LOAD_ENABLE
+ * @arg TIM_OC_PRE_LOAD_DISABLE
+ */
+void TIM_ConfigOc1Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimOcPreLoadState(TIM_OCPreload));
+ tmpccmr1 = TIMx->CCMOD1;
+ /* Reset the OC1PE Bit */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1PEN);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr1 |= TIM_OCPreload;
+ /* Write to TIMx CCMOD1 register */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCDAT2.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select
+ * the TIM peripheral.
+ * @param TIM_OCPreload new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_PRE_LOAD_ENABLE
+ * @arg TIM_OC_PRE_LOAD_DISABLE
+ */
+void TIM_ConfigOc2Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimOcPreLoadState(TIM_OCPreload));
+ tmpccmr1 = TIMx->CCMOD1;
+ /* Reset the OC2PE Bit */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2PEN);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
+ /* Write to TIMx CCMOD1 register */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCDAT3.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_PRE_LOAD_ENABLE
+ * @arg TIM_OC_PRE_LOAD_DISABLE
+ */
+void TIM_ConfigOc3Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcPreLoadState(TIM_OCPreload));
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC3PE Bit */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3PEN);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr2 |= TIM_OCPreload;
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCDAT4.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_PRE_LOAD_ENABLE
+ * @arg TIM_OC_PRE_LOAD_DISABLE
+ */
+void TIM_ConfigOc4Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcPreLoadState(TIM_OCPreload));
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC4PE Bit */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4PEN);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCDAT5.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_PRE_LOAD_ENABLE
+ * @arg TIM_OC_PRE_LOAD_DISABLE
+ */
+void TIM_ConfigOc5Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcPreLoadState(TIM_OCPreload));
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC5PE Bit */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5PEN);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr3 |= (uint16_t)(TIM_OCPreload);
+ /* Write to TIMx CCMOD3 register */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCDAT6.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_PRE_LOAD_ENABLE
+ * @arg TIM_OC_PRE_LOAD_DISABLE
+ */
+void TIM_ConfigOc6Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcPreLoadState(TIM_OCPreload));
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC6PE Bit */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6PEN);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr3 |= (uint16_t)(TIM_OCPreload << 8);
+ /* Write to TIMx CCMOD3 register */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 1 Fast feature.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_OCFast new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable
+ * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable
+ */
+void TIM_ConfigOc1Fast(TIM_Module* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimOcFastState(TIM_OCFast));
+ /* Get the TIMx CCMOD1 register value */
+ tmpccmr1 = TIMx->CCMOD1;
+ /* Reset the OC1FE Bit */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1FEN);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr1 |= TIM_OCFast;
+ /* Write to TIMx CCMOD1 */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 2 Fast feature.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select
+ * the TIM peripheral.
+ * @param TIM_OCFast new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable
+ * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable
+ */
+void TIM_ConfigOc2Fast(TIM_Module* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimOcFastState(TIM_OCFast));
+ /* Get the TIMx CCMOD1 register value */
+ tmpccmr1 = TIMx->CCMOD1;
+ /* Reset the OC2FE Bit */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2FEN);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
+ /* Write to TIMx CCMOD1 */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 3 Fast feature.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable
+ * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable
+ */
+void TIM_ConfigOc3Fast(TIM_Module* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcFastState(TIM_OCFast));
+ /* Get the TIMx CCMOD2 register value */
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC3FE Bit */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3FEN);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr2 |= TIM_OCFast;
+ /* Write to TIMx CCMOD2 */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 4 Fast feature.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable
+ * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable
+ */
+void TIM_ConfigOc4Fast(TIM_Module* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcFastState(TIM_OCFast));
+ /* Get the TIMx CCMOD2 register value */
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC4FE Bit */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4FEN);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
+ /* Write to TIMx CCMOD2 */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 5 Fast feature.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable
+ * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable
+ */
+void TIM_ConfigOc5Fast(TIM_Module* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcFastState(TIM_OCFast));
+ /* Get the TIMx CCMOD2 register value */
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC4FE Bit */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5FEN);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr3 |= (uint16_t)(TIM_OCFast);
+ /* Write to TIMx CCMOD3 */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 6 Fast feature.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable
+ * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable
+ */
+void TIM_ConfigOc6Fast(TIM_Module* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcFastState(TIM_OCFast));
+ /* Get the TIMx CCMOD2 register value */
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC4FE Bit */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6FEN);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr3 |= (uint16_t)(TIM_OCFast << 8);
+ /* Write to TIMx CCMOD3 */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF1 signal on an external event
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_CLR_ENABLE TIM Output clear enable
+ * @arg TIM_OC_CLR_DISABLE TIM Output clear disable
+ */
+void TIM_ClrOc1Ref(TIM_Module* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcClrState(TIM_OCClear));
+
+ tmpccmr1 = TIMx->CCMOD1;
+
+ /* Reset the OC1CE Bit */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1CEN);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr1 |= TIM_OCClear;
+ /* Write to TIMx CCMOD1 register */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF2 signal on an external event
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_CLR_ENABLE TIM Output clear enable
+ * @arg TIM_OC_CLR_DISABLE TIM Output clear disable
+ */
+void TIM_ClrOc2Ref(TIM_Module* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcClrState(TIM_OCClear));
+ tmpccmr1 = TIMx->CCMOD1;
+ /* Reset the OC2CE Bit */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2CEN);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
+ /* Write to TIMx CCMOD1 register */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF3 signal on an external event
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_CLR_ENABLE TIM Output clear enable
+ * @arg TIM_OC_CLR_DISABLE TIM Output clear disable
+ */
+void TIM_ClrOc3Ref(TIM_Module* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcClrState(TIM_OCClear));
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC3CE Bit */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3CEN);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr2 |= TIM_OCClear;
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF4 signal on an external event
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_CLR_ENABLE TIM Output clear enable
+ * @arg TIM_OC_CLR_DISABLE TIM Output clear disable
+ */
+void TIM_ClrOc4Ref(TIM_Module* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcClrState(TIM_OCClear));
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC4CE Bit */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4CEN);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF5 signal on an external event
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_CLR_ENABLE TIM Output clear enable
+ * @arg TIM_OC_CLR_DISABLE TIM Output clear disable
+ */
+void TIM_ClrOc5Ref(TIM_Module* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcClrState(TIM_OCClear));
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC4CE Bit */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5CEN);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr3 |= (uint16_t)(TIM_OCClear);
+ /* Write to TIMx CCMOD3 register */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF6 signal on an external event
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_CLR_ENABLE TIM Output clear enable
+ * @arg TIM_OC_CLR_DISABLE TIM Output clear disable
+ */
+void TIM_ClrOc6Ref(TIM_Module* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcClrState(TIM_OCClear));
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC4CE Bit */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6CEN);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr3 |= (uint16_t)(TIM_OCClear << 8);
+ /* Write to TIMx CCMOD3 register */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Configures the TIMx channel 1 polarity.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param OcPolarity specifies the OC1 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OC_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc1Polarity(TIM_Module* TIMx, uint16_t OcPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimOcPolarity(OcPolarity));
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC1P Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC1P);
+ tmpccer |= OcPolarity;
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx Channel 1N polarity.
+ * @param TIMx where x can be 1, 8 to select the TIM peripheral.
+ * @param OcNPolarity specifies the OC1N Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCN_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OCN_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc1NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList2Module(TIMx));
+ assert_param(IsTimOcnPolarity(OcNPolarity));
+
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC1NP Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC1NP);
+ tmpccer |= OcNPolarity;
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 2 polarity.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param OcPolarity specifies the OC2 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OC_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc2Polarity(TIM_Module* TIMx, uint16_t OcPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimOcPolarity(OcPolarity));
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC2P Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC2P);
+ tmpccer |= (uint32_t)(OcPolarity << 4);
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx Channel 2N polarity.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param OcNPolarity specifies the OC2N Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCN_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OCN_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc2NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcnPolarity(OcNPolarity));
+
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC2NP Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC2NP);
+ tmpccer |= (uint32_t)(OcNPolarity << 4);
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 3 polarity.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param OcPolarity specifies the OC3 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OC_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc3Polarity(TIM_Module* TIMx, uint16_t OcPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcPolarity(OcPolarity));
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC3P Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC3P);
+ tmpccer |= (uint32_t)(OcPolarity << 8);
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx Channel 3N polarity.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param OcNPolarity specifies the OC3N Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCN_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OCN_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc3NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity)
+{
+ uint32_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcnPolarity(OcNPolarity));
+
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC3NP Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC3NP);
+ tmpccer |= (uint32_t)(OcNPolarity << 8);
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 4 polarity.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param OcPolarity specifies the OC4 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OC_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc4Polarity(TIM_Module* TIMx, uint16_t OcPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcPolarity(OcPolarity));
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC4P Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC4P);
+ tmpccer |= (uint32_t)(OcPolarity << 12);
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 5 polarity.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param OcPolarity specifies the OC5 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OC_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc5Polarity(TIM_Module* TIMx, uint16_t OcPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcPolarity(OcPolarity));
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC5P Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC5P);
+ tmpccer |= (uint32_t)(OcPolarity << 16);
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 6 polarity.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param OcPolarity specifies the OC6 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OC_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc6Polarity(TIM_Module* TIMx, uint16_t OcPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcPolarity(OcPolarity));
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC6P Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC6P);
+ tmpccer |= (uint32_t)(OcPolarity << 20);
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel x.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CH_1 TIM Channel 1
+ * @arg TIM_CH_2 TIM Channel 2
+ * @arg TIM_CH_3 TIM Channel 3
+ * @arg TIM_CH_4 TIM Channel 4
+ * @param TIM_CCx specifies the TIM Channel CCxE bit new state.
+ * This parameter can be: TIM_CAP_CMP_ENABLE or TIM_CAP_CMP_DISABLE.
+ */
+void TIM_EnableCapCmpCh(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCx)
+{
+ uint16_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimCh(Channel));
+ assert_param(IsTimCapCmpState(TIM_CCx));
+
+ tmp = CAPCMPEN_CCE_SET << Channel;
+
+ /* Reset the CCxE Bit */
+ TIMx->CCEN &= (uint32_t)~tmp;
+
+ /* Set or reset the CCxE Bit */
+ TIMx->CCEN |= (uint32_t)(TIM_CCx << Channel);
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel xN.
+ * @param TIMx where x can be 1, 8 to select the TIM peripheral.
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CH_1 TIM Channel 1
+ * @arg TIM_CH_2 TIM Channel 2
+ * @arg TIM_CH_3 TIM Channel 3
+ * @param TIM_CCxN specifies the TIM Channel CCxNE bit new state.
+ * This parameter can be: TIM_CAP_CMP_N_ENABLE or TIM_CAP_CMP_N_DISABLE.
+ */
+void TIM_EnableCapCmpChN(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCxN)
+{
+ uint16_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList2Module(TIMx));
+ assert_param(IsTimComplementaryCh(Channel));
+ assert_param(IsTimCapCmpNState(TIM_CCxN));
+
+ tmp = CAPCMPEN_CCNE_SET << Channel;
+
+ /* Reset the CCxNE Bit */
+ TIMx->CCEN &= (uint32_t)~tmp;
+
+ /* Set or reset the CCxNE Bit */
+ TIMx->CCEN |= (uint32_t)(TIM_CCxN << Channel);
+}
+
+/**
+ * @brief Selects the TIM Output Compare Mode.
+ * @note This function disables the selected channel before changing the Output
+ * Compare Mode.
+ * User has to enable this channel using TIM_EnableCapCmpCh and TIM_EnableCapCmpChN functions.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CH_1 TIM Channel 1
+ * @arg TIM_CH_2 TIM Channel 2
+ * @arg TIM_CH_3 TIM Channel 3
+ * @arg TIM_CH_4 TIM Channel 4
+ * @param OcMode specifies the TIM Output Compare Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCMODE_TIMING
+ * @arg TIM_OCMODE_ACTIVE
+ * @arg TIM_OCMODE_TOGGLE
+ * @arg TIM_OCMODE_PWM1
+ * @arg TIM_OCMODE_PWM2
+ * @arg TIM_FORCED_ACTION_ACTIVE
+ * @arg TIM_FORCED_ACTION_INACTIVE
+ */
+void TIM_SelectOcMode(TIM_Module* TIMx, uint16_t Channel, uint16_t OcMode)
+{
+ uint32_t tmp = 0;
+ uint16_t tmp1 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimCh(Channel));
+ assert_param(IsTimOc(OcMode));
+
+ tmp = (uint32_t)TIMx;
+ tmp += CAPCMPMOD_OFFSET;
+
+ tmp1 = CAPCMPEN_CCE_SET << (uint16_t)Channel;
+
+ /* Disable the Channel: Reset the CCxE Bit */
+ TIMx->CCEN &= (uint16_t)~tmp1;
+
+ if ((Channel == TIM_CH_1) || (Channel == TIM_CH_3))
+ {
+ tmp += (Channel >> 1);
+
+ /* Reset the OCxM bits in the CCMRx register */
+ *(__IO uint32_t*)tmp &= (uint32_t) ~((uint32_t)TIM_CCMOD1_OC1M);
+
+ /* Configure the OCxM bits in the CCMRx register */
+ *(__IO uint32_t*)tmp |= OcMode;
+ }
+ else
+ {
+ tmp += (uint16_t)(Channel - (uint16_t)4) >> (uint16_t)1;
+
+ /* Reset the OCxM bits in the CCMRx register */
+ *(__IO uint32_t*)tmp &= (uint32_t) ~((uint32_t)TIM_CCMOD1_OC2M);
+
+ /* Configure the OCxM bits in the CCMRx register */
+ *(__IO uint32_t*)tmp |= (uint16_t)(OcMode << 8);
+ }
+}
+
+/**
+ * @brief Enables or Disables the TIMx Update event.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param Cmd new state of the TIMx UDIS bit
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_EnableUpdateEvt(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set the Update Disable Bit */
+ TIMx->CTRL1 |= TIM_CTRL1_UPDIS;
+ }
+ else
+ {
+ /* Reset the Update Disable Bit */
+ TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_UPDIS);
+ }
+}
+
+/**
+ * @brief Configures the TIMx Update Request Interrupt source.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_UpdateSource specifies the Update source.
+ * This parameter can be one of the following values:
+ * @arg TIM_UPDATE_SRC_REGULAr Source of update is the counter overflow/underflow
+ or the setting of UG bit, or an update generation
+ through the slave mode controller.
+ * @arg TIM_UPDATE_SRC_GLOBAL Source of update is counter overflow/underflow.
+ */
+void TIM_ConfigUpdateRequestIntSrc(TIM_Module* TIMx, uint16_t TIM_UpdateSource)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimUpdateSrc(TIM_UpdateSource));
+ if (TIM_UpdateSource != TIM_UPDATE_SRC_GLOBAL)
+ {
+ /* Set the URS Bit */
+ TIMx->CTRL1 |= TIM_CTRL1_UPRS;
+ }
+ else
+ {
+ /* Reset the URS Bit */
+ TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_UPRS);
+ }
+}
+
+/**
+ * @brief Enables or disables the TIMx's Hall sensor interface.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param Cmd new state of the TIMx Hall sensor interface.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_SelectHallSensor(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set the TI1S Bit */
+ TIMx->CTRL2 |= TIM_CTRL2_TI1SEL;
+ }
+ else
+ {
+ /* Reset the TI1S Bit */
+ TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_TI1SEL);
+ }
+}
+
+/**
+ * @brief Selects the TIMx's One Pulse Mode.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_OPMode specifies the OPM Mode to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_OPMODE_SINGLE
+ * @arg TIM_OPMODE_REPET
+ */
+void TIM_SelectOnePulseMode(TIM_Module* TIMx, uint16_t TIM_OPMode)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimOpMOde(TIM_OPMode));
+ /* Reset the OPM Bit */
+ TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_ONEPM);
+ /* Configure the OPM Mode */
+ TIMx->CTRL1 |= TIM_OPMode;
+}
+
+/**
+ * @brief Selects the TIMx Trigger Output Mode.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 6, 7, 8 to select the TIM peripheral.
+ * @param TIM_TRGOSource specifies the Trigger Output source.
+ * This paramter can be one of the following values:
+ *
+ * - For all TIMx
+ * @arg TIM_TRGO_SRC_RESET The UG bit in the TIM_EVTGEN register is used as the trigger output (TRGO).
+ * @arg TIM_TRGO_SRC_ENABLE The Counter Enable CEN is used as the trigger output (TRGO).
+ * @arg TIM_TRGO_SRC_UPDATE The update event is selected as the trigger output (TRGO).
+ *
+ * - For all TIMx except TIM6 and TIM7
+ * @arg TIM_TRGO_SRC_OC1 The trigger output sends a positive pulse when the CC1IF flag
+ * is to be set, as soon as a capture or compare match occurs (TRGO).
+ * @arg TIM_TRGO_SRC_OC1REF OC1REF signal is used as the trigger output (TRGO).
+ * @arg TIM_TRGO_SRC_OC2REF OC2REF signal is used as the trigger output (TRGO).
+ * @arg TIM_TRGO_SRC_OC3REF OC3REF signal is used as the trigger output (TRGO).
+ * @arg TIM_TRGO_SRC_OC4REF OC4REF signal is used as the trigger output (TRGO).
+ *
+ */
+void TIM_SelectOutputTrig(TIM_Module* TIMx, uint16_t TIM_TRGOSource)
+{
+ /* Check the parameters */
+ assert_param(IsTimList7Module(TIMx));
+ assert_param(IsTimTrgoSrc(TIM_TRGOSource));
+ /* Reset the MMS Bits */
+ TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_MMSEL);
+ /* Select the TRGO source */
+ TIMx->CTRL2 |= TIM_TRGOSource;
+}
+
+/**
+ * @brief Selects the TIMx Slave Mode.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param TIM_SlaveMode specifies the Timer Slave Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_SLAVE_MODE_RESET Rising edge of the selected trigger signal (TRGI) re-initializes
+ * the counter and triggers an update of the registers.
+ * @arg TIM_SLAVE_MODE_GATED The counter clock is enabled when the trigger signal (TRGI) is high.
+ * @arg TIM_SLAVE_MODE_TRIG The counter starts at a rising edge of the trigger TRGI.
+ * @arg TIM_SLAVE_MODE_EXT1 Rising edges of the selected trigger (TRGI) clock the counter.
+ */
+void TIM_SelectSlaveMode(TIM_Module* TIMx, uint16_t TIM_SlaveMode)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimSlaveMode(TIM_SlaveMode));
+ /* Reset the SMS Bits */
+ TIMx->SMCTRL &= (uint16_t) ~((uint16_t)TIM_SMCTRL_SMSEL);
+ /* Select the Slave Mode */
+ TIMx->SMCTRL |= TIM_SlaveMode;
+}
+
+/**
+ * @brief Sets or Resets the TIMx Master/Slave Mode.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param TIM_MasterSlaveMode specifies the Timer Master Slave Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_MASTER_SLAVE_MODE_ENABLE synchronization between the current timer
+ * and its slaves (through TRGO).
+ * @arg TIM_MASTER_SLAVE_MODE_DISABLE No action
+ */
+void TIM_SelectMasterSlaveMode(TIM_Module* TIMx, uint16_t TIM_MasterSlaveMode)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimMasterSlaveMode(TIM_MasterSlaveMode));
+ /* Reset the MSM Bit */
+ TIMx->SMCTRL &= (uint16_t) ~((uint16_t)TIM_SMCTRL_MSMD);
+
+ /* Set or Reset the MSM Bit */
+ TIMx->SMCTRL |= TIM_MasterSlaveMode;
+}
+
+/**
+ * @brief Sets the TIMx Counter Register value
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param Counter specifies the Counter register new value.
+ */
+void TIM_SetCnt(TIM_Module* TIMx, uint16_t Counter)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ /* Set the Counter Register value */
+ TIMx->CNT = Counter;
+}
+
+/**
+ * @brief Sets the TIMx Autoreload Register value
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param Autoreload specifies the Autoreload register new value.
+ */
+void TIM_SetAutoReload(TIM_Module* TIMx, uint16_t Autoreload)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ /* Set the Autoreload Register value */
+ TIMx->AR = Autoreload;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare1 Register value
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param Compare1 specifies the Capture Compare1 register new value.
+ */
+void TIM_SetCmp1(TIM_Module* TIMx, uint16_t Compare1)
+{
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ /* Set the Capture Compare1 Register value */
+ TIMx->CCDAT1 = Compare1;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare2 Register value
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param Compare2 specifies the Capture Compare2 register new value.
+ */
+void TIM_SetCmp2(TIM_Module* TIMx, uint16_t Compare2)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ /* Set the Capture Compare2 Register value */
+ TIMx->CCDAT2 = Compare2;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare3 Register value
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param Compare3 specifies the Capture Compare3 register new value.
+ */
+void TIM_SetCmp3(TIM_Module* TIMx, uint16_t Compare3)
+{
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ /* Set the Capture Compare3 Register value */
+ TIMx->CCDAT3 = Compare3;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare4 Register value
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param Compare4 specifies the Capture Compare4 register new value.
+ */
+void TIM_SetCmp4(TIM_Module* TIMx, uint16_t Compare4)
+{
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ /* Set the Capture Compare4 Register value */
+ TIMx->CCDAT4 = Compare4;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare5 Register value
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param Compare5 specifies the Capture Compare5 register new value.
+ */
+void TIM_SetCmp5(TIM_Module* TIMx, uint16_t Compare5)
+{
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ /* Set the Capture Compare4 Register value */
+ TIMx->CCDAT5 = Compare5;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare4 Register value
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param Compare6 specifies the Capture Compare6 register new value.
+ */
+void TIM_SetCmp6(TIM_Module* TIMx, uint16_t Compare6)
+{
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ /* Set the Capture Compare4 Register value */
+ TIMx->CCDAT6 = Compare6;
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 1 prescaler.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_ICPSC specifies the Input Capture1 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_PSC_DIV1 no prescaler
+ * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events
+ * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events
+ * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events
+ */
+void TIM_SetInCap1Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimIcPrescaler(TIM_ICPSC));
+ /* Reset the IC1PSC Bits */
+ TIMx->CCMOD1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_IC1PSC);
+ /* Set the IC1PSC value */
+ TIMx->CCMOD1 |= TIM_ICPSC;
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 2 prescaler.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param TIM_ICPSC specifies the Input Capture2 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_PSC_DIV1 no prescaler
+ * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events
+ * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events
+ * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events
+ */
+void TIM_SetInCap2Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimIcPrescaler(TIM_ICPSC));
+ /* Reset the IC2PSC Bits */
+ TIMx->CCMOD1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_IC2PSC);
+ /* Set the IC2PSC value */
+ TIMx->CCMOD1 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 3 prescaler.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPSC specifies the Input Capture3 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_PSC_DIV1 no prescaler
+ * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events
+ * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events
+ * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events
+ */
+void TIM_SetInCap3Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimIcPrescaler(TIM_ICPSC));
+ /* Reset the IC3PSC Bits */
+ TIMx->CCMOD2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_IC3PSC);
+ /* Set the IC3PSC value */
+ TIMx->CCMOD2 |= TIM_ICPSC;
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 4 prescaler.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPSC specifies the Input Capture4 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_PSC_DIV1 no prescaler
+ * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events
+ * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events
+ * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events
+ */
+void TIM_SetInCap4Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimIcPrescaler(TIM_ICPSC));
+ /* Reset the IC4PSC Bits */
+ TIMx->CCMOD2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_IC4PSC);
+ /* Set the IC4PSC value */
+ TIMx->CCMOD2 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/**
+ * @brief Sets the TIMx Clock Division value.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select
+ * the TIM peripheral.
+ * @param TIM_CKD specifies the clock division value.
+ * This parameter can be one of the following value:
+ * @arg TIM_CLK_DIV1 TDTS = Tck_tim
+ * @arg TIM_CLK_DIV2 TDTS = 2*Tck_tim
+ * @arg TIM_CLK_DIV4 TDTS = 4*Tck_tim
+ */
+void TIM_SetClkDiv(TIM_Module* TIMx, uint16_t TIM_CKD)
+{
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimClkDiv(TIM_CKD));
+ /* Reset the CKD Bits */
+ TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_CLKD);
+ /* Set the CKD value */
+ TIMx->CTRL1 |= TIM_CKD;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 1 value.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @return Capture Compare 1 Register value.
+ */
+uint16_t TIM_GetCap1(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ /* Get the Capture 1 Register value */
+ return TIMx->CCDAT1;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 2 value.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @return Capture Compare 2 Register value.
+ */
+uint16_t TIM_GetCap2(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ /* Get the Capture 2 Register value */
+ return TIMx->CCDAT2;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 3 value.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @return Capture Compare 3 Register value.
+ */
+uint16_t TIM_GetCap3(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ /* Get the Capture 3 Register value */
+ return TIMx->CCDAT3;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 4 value.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @return Capture Compare 4 Register value.
+ */
+uint16_t TIM_GetCap4(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ /* Get the Capture 4 Register value */
+ return TIMx->CCDAT4;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 5 value.
+ * @param TIMx where x can be 1 8 to select the TIM peripheral.
+ * @return Capture Compare 5 Register value.
+ */
+uint16_t TIM_GetCap5(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ /* Get the Capture 5 Register value */
+ return TIMx->CCDAT5;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 6 value.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @return Capture Compare 6 Register value.
+ */
+uint16_t TIM_GetCap6(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ /* Get the Capture 6 Register value */
+ return TIMx->CCDAT6;
+}
+
+/**
+ * @brief Gets the TIMx Counter value.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @return Counter Register value.
+ */
+uint16_t TIM_GetCnt(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ /* Get the Counter Register value */
+ return TIMx->CNT;
+}
+
+/**
+ * @brief Gets the TIMx Prescaler value.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @return Prescaler Register value.
+ */
+uint16_t TIM_GetPrescaler(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ /* Get the Prescaler Register value */
+ return TIMx->PSC;
+}
+
+/**
+ * @brief Gets the TIMx Prescaler value.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @return Prescaler Register value.
+ */
+uint16_t TIM_GetAutoReload(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ /* Get the Prescaler Register value */
+ return TIMx->AR;
+}
+
+/**
+ * @brief Checks whether the specified TIM flag is set or not.
+ * @param TIMx where x can be 1 to 5 , 8 ,9 to select the TIM peripheral.
+ * @param TIM_CCEN specifies the Bit to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_CC1EN CC1EN Bit
+ * @arg TIM_CC1NEN CC1NEN Bit
+ * @arg TIM_CC2EN CC2EN Bit
+ * @arg TIM_CC2NEN CC2NEN Bit
+ * @arg TIM_CC3EN CC3EN Bit
+ * @arg TIM_CC3NEN CC3NEN Bit
+ * @arg TIM_CC4EN CC4EN Bit
+ * @arg TIM_CC5EN CC5EN Bit
+ * @arg TIM_CC6EN CC6EN Bit
+ * @note
+ * - TIM_CC1NEN TIM_CC2NEN TIM_CC3NEN is used only with TIM1, TIM8.
+ * @return The new state of TIM_FLAG (SET or RESET).
+ */
+FlagStatus TIM_GetCCENStatus(TIM_Module* TIMx, uint32_t TIM_CCEN)
+{
+ INTStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+
+ if (TIMx==TIM1 || TIMx==TIM8){
+ assert_param(IsAdvancedTimCCENFlag(TIM_CCEN));
+ if ((TIMx->CCEN & TIM_CCEN) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }else if (TIMx==TIM2 || TIMx==TIM3 || TIMx==TIM4 || TIMx==TIM5 || TIMx==TIM9){
+ assert_param(IsGeneralTimCCENFlag(TIM_CCEN));
+ if ((TIMx->CCEN & TIM_CCEN) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+
+ return bitstatus;
+}
+
+/**
+ * @brief Checks whether the specified TIM flag is set or not.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_FLAG specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_FLAG_UPDATE TIM update Flag
+ * @arg TIM_FLAG_CC1 TIM Capture Compare 1 Flag
+ * @arg TIM_FLAG_CC2 TIM Capture Compare 2 Flag
+ * @arg TIM_FLAG_CC3 TIM Capture Compare 3 Flag
+ * @arg TIM_FLAG_CC4 TIM Capture Compare 4 Flag
+ * @arg TIM_FLAG_COM TIM Commutation Flag
+ * @arg TIM_FLAG_TRIG TIM Trigger Flag
+ * @arg TIM_FLAG_BREAK TIM Break Flag
+ * @arg TIM_FLAG_CC1OF TIM Capture Compare 1 overcapture Flag
+ * @arg TIM_FLAG_CC2OF TIM Capture Compare 2 overcapture Flag
+ * @arg TIM_FLAG_CC3OF TIM Capture Compare 3 overcapture Flag
+ * @arg TIM_FLAG_CC4OF TIM Capture Compare 4 overcapture Flag
+ * @arg TIM_FLAG_CC5 TIM Capture Compare 5 Flag
+ * @arg TIM_FLAG_CC6 TIM Capture Compare 6 Flag
+ * @note
+ * - TIM6 and TIM7 can have only one update flag.
+ * - TIM_FLAG_BREAK is used only with TIM1, TIM8.
+ * - TIM_FLAG_COM is used only with TIM1, TIM8.
+ * @return The new state of TIM_FLAG (SET or RESET).
+ */
+FlagStatus TIM_GetFlagStatus(TIM_Module* TIMx, uint32_t TIM_FLAG)
+{
+ INTStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimGetFlag(TIM_FLAG));
+
+ if ((TIMx->STS & TIM_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the TIMx's pending flags.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_FLAG specifies the flag bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_FLAG_UPDATE TIM update Flag
+ * @arg TIM_FLAG_CC1 TIM Capture Compare 1 Flag
+ * @arg TIM_FLAG_CC2 TIM Capture Compare 2 Flag
+ * @arg TIM_FLAG_CC3 TIM Capture Compare 3 Flag
+ * @arg TIM_FLAG_CC4 TIM Capture Compare 4 Flag
+ * @arg TIM_FLAG_COM TIM Commutation Flag
+ * @arg TIM_FLAG_TRIG TIM Trigger Flag
+ * @arg TIM_FLAG_BREAK TIM Break Flag
+ * @arg TIM_FLAG_CC1OF TIM Capture Compare 1 overcapture Flag
+ * @arg TIM_FLAG_CC2OF TIM Capture Compare 2 overcapture Flag
+ * @arg TIM_FLAG_CC3OF TIM Capture Compare 3 overcapture Flag
+ * @arg TIM_FLAG_CC4OF TIM Capture Compare 4 overcapture Flag
+ * @note
+ * - TIM6 and TIM7 can have only one update flag.
+ * - TIM_FLAG_BREAK is used only with TIM1, TIM8.
+ * - TIM_FLAG_COM is used only with TIM1, TIM8.
+ */
+void TIM_ClearFlag(TIM_Module* TIMx, uint32_t TIM_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimClrFlag(TIM_FLAG));
+
+ /* Clear the flags */
+ TIMx->STS = (uint32_t)~TIM_FLAG;
+}
+
+/**
+ * @brief Checks whether the TIM interrupt has occurred or not.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_IT specifies the TIM interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_INT_UPDATE TIM update Interrupt source
+ * @arg TIM_INT_CC1 TIM Capture Compare 1 Interrupt source
+ * @arg TIM_INT_CC2 TIM Capture Compare 2 Interrupt source
+ * @arg TIM_INT_CC3 TIM Capture Compare 3 Interrupt source
+ * @arg TIM_INT_CC4 TIM Capture Compare 4 Interrupt source
+ * @arg TIM_INT_COM TIM Commutation Interrupt source
+ * @arg TIM_INT_TRIG TIM Trigger Interrupt source
+ * @arg TIM_INT_BREAK TIM Break Interrupt source
+ * @note
+ * - TIM6 and TIM7 can generate only an update interrupt.
+ * - TIM_INT_BREAK is used only with TIM1, TIM8.
+ * - TIM_INT_COM is used only with TIM1, TIM8.
+ * @return The new state of the TIM_IT(SET or RESET).
+ */
+INTStatus TIM_GetIntStatus(TIM_Module* TIMx, uint32_t TIM_IT)
+{
+ INTStatus bitstatus = RESET;
+ uint32_t itstatus = 0x0, itenable = 0x0;
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimGetInt(TIM_IT));
+
+ itstatus = TIMx->STS & TIM_IT;
+
+ itenable = TIMx->DINTEN & TIM_IT;
+ if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the TIMx's interrupt pending bits.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_IT specifies the pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_INT_UPDATE TIM1 update Interrupt source
+ * @arg TIM_INT_CC1 TIM Capture Compare 1 Interrupt source
+ * @arg TIM_INT_CC2 TIM Capture Compare 2 Interrupt source
+ * @arg TIM_INT_CC3 TIM Capture Compare 3 Interrupt source
+ * @arg TIM_INT_CC4 TIM Capture Compare 4 Interrupt source
+ * @arg TIM_INT_COM TIM Commutation Interrupt source
+ * @arg TIM_INT_TRIG TIM Trigger Interrupt source
+ * @arg TIM_INT_BREAK TIM Break Interrupt source
+ * @note
+ * - TIM6 and TIM7 can generate only an update interrupt.
+ * - TIM_INT_BREAK is used only with TIM1, TIM8.
+ * - TIM_INT_COM is used only with TIM1, TIM8.
+ */
+void TIM_ClrIntPendingBit(TIM_Module* TIMx, uint32_t TIM_IT)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimInt(TIM_IT));
+ /* Clear the IT pending Bit */
+ TIMx->STS = (uint32_t)~TIM_IT;
+}
+
+/**
+ * @brief Configure the TI1 as Input.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param IcPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_POLARITY_RISING
+ * @arg TIM_IC_POLARITY_FALLING
+ * @param IcSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 1 is selected to be connected to IC1.
+ * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 1 is selected to be connected to IC2.
+ * @arg TIM_IC_SELECTION_TRC TIM Input 1 is selected to be connected to TRC.
+ * @param IcFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ */
+static void ConfigTI1(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter)
+{
+ uint16_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0;
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC1EN);
+ tmpccmr1 = TIMx->CCMOD1;
+ tmpccer = TIMx->CCEN;
+ /* Select the Input and set the filter */
+ tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD1_CC1SEL)) & ((uint16_t) ~((uint16_t)TIM_CCMOD1_IC1F)));
+ tmpccmr1 |= (uint16_t)(IcSelection | (uint16_t)(IcFilter << (uint16_t)4));
+
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9))
+ {
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC1P));
+ tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC1EN);
+ }
+ else
+ {
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC1P | TIM_CCEN_CC1NP));
+ tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC1EN);
+ }
+
+ /* Write to TIMx CCMOD1 and CCEN registers */
+ TIMx->CCMOD1 = tmpccmr1;
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configure the TI2 as Input.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param IcPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_POLARITY_RISING
+ * @arg TIM_IC_POLARITY_FALLING
+ * @param IcSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 2 is selected to be connected to IC2.
+ * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 2 is selected to be connected to IC1.
+ * @arg TIM_IC_SELECTION_TRC TIM Input 2 is selected to be connected to TRC.
+ * @param IcFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ */
+static void ConfigTI2(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter)
+{
+ uint16_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0, tmp = 0;
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC2EN);
+ tmpccmr1 = TIMx->CCMOD1;
+ tmpccer = TIMx->CCEN;
+ tmp = (uint32_t)(IcPolarity << 4);
+ /* Select the Input and set the filter */
+ tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD1_CC2SEL)) & ((uint16_t) ~((uint16_t)TIM_CCMOD1_IC2F)));
+ tmpccmr1 |= (uint16_t)(IcFilter << 12);
+ tmpccmr1 |= (uint16_t)(IcSelection << 8);
+
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9))
+ {
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC2P));
+ tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCEN_CC2EN);
+ }
+ else
+ {
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC2P | TIM_CCEN_CC2NP));
+ tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC2EN);
+ }
+
+ /* Write to TIMx CCMOD1 and CCEN registers */
+ TIMx->CCMOD1 = tmpccmr1;
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configure the TI3 as Input.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param IcPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_POLARITY_RISING
+ * @arg TIM_IC_POLARITY_FALLING
+ * @param IcSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 3 is selected to be connected to IC3.
+ * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 3 is selected to be connected to IC4.
+ * @arg TIM_IC_SELECTION_TRC TIM Input 3 is selected to be connected to TRC.
+ * @param IcFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ */
+static void ConfigTI3(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter)
+{
+ uint16_t tmpccmr2 = 0;
+ uint32_t tmpccer = 0, tmp = 0;
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC3EN);
+ tmpccmr2 = TIMx->CCMOD2;
+ tmpccer = TIMx->CCEN;
+ tmp = (uint32_t)(IcPolarity << 8);
+ /* Select the Input and set the filter */
+ tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD2_CC3SEL)) & ((uint16_t) ~((uint16_t)TIM_CCMOD2_IC3F)));
+ tmpccmr2 |= (uint16_t)(IcSelection | (uint16_t)(IcFilter << (uint16_t)4));
+
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9))
+ {
+ /* Select the Polarity and set the CC3E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC3P));
+ tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCEN_CC3EN);
+ }
+ else
+ {
+ /* Select the Polarity and set the CC3E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC3P | TIM_CCEN_CC3NP));
+ tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC3EN);
+ }
+
+ /* Write to TIMx CCMOD2 and CCEN registers */
+ TIMx->CCMOD2 = tmpccmr2;
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configure the TI4 as Input.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param IcPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_POLARITY_RISING
+ * @arg TIM_IC_POLARITY_FALLING
+ * @param IcSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 4 is selected to be connected to IC4.
+ * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 4 is selected to be connected to IC3.
+ * @arg TIM_IC_SELECTION_TRC TIM Input 4 is selected to be connected to TRC.
+ * @param IcFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ */
+static void ConfigTI4(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter)
+{
+ uint16_t tmpccmr2 = 0;
+ uint32_t tmpccer = 0, tmp = 0;
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC4EN);
+ tmpccmr2 = TIMx->CCMOD2;
+ tmpccer = TIMx->CCEN;
+ tmp = (uint32_t)(IcPolarity << 12);
+ /* Select the Input and set the filter */
+ tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMOD2_CC4SEL) & ((uint16_t) ~((uint16_t)TIM_CCMOD2_IC4F)));
+ tmpccmr2 |= (uint16_t)(IcSelection << 8);
+ tmpccmr2 |= (uint16_t)(IcFilter << 12);
+
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9))
+ {
+ /* Select the Polarity and set the CC4E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC4P));
+ tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCEN_CC4EN);
+ }
+ else
+ {
+ /* Select the Polarity and set the CC4E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC4P));
+ tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC4EN);
+ }
+ /* Write to TIMx CCMOD2 and CCEN registers */
+ TIMx->CCMOD2 = tmpccmr2;
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_tsc.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_tsc.c
new file mode 100644
index 0000000000..1a94933b43
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_tsc.c
@@ -0,0 +1,279 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_tsc.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l43x.h"
+#include "n32l43x_tsc.h"
+
+/**
+* @brief Init TSC config
+* @param InitParam: TSC initialize structure
+* @return : TSC_ErrorTypeDef
+*/
+TSC_ErrorTypeDef TSC_Init(TSC_InitType* InitParam)
+{
+ uint32_t tempreg,timeout;
+
+ assert_param(IS_TSC_DET_MODE(InitParam->Mode));
+ assert_param(IS_TSC_PAD_OPTION(InitParam->PadOpt));
+ assert_param(IS_TSC_PAD_SPEED(InitParam->Speed));
+
+ /* waiting tsc hw for idle status.*/
+ timeout = 0;
+ do
+ {
+ __TSC_HW_DISABLE();
+
+ if (++timeout > TSC_TIMEOUT)
+ return TSC_ERROR_HW_MODE;
+ }while (__TSC_GET_HW_MODE());
+
+ /*TSC_CTRL config*/
+ tempreg = 0;
+ if (InitParam->Mode == TSC_HW_DETECT_MODE)
+ {
+ assert_param(IS_TSC_DET_PERIOD(InitParam->Period));
+ assert_param(IS_TSC_FILTER(InitParam->Filter));
+ assert_param(IS_TSC_DET_TYPE(InitParam->Type));
+ assert_param(IS_TSC_INT(InitParam->Int));
+
+ tempreg |= InitParam->Period;
+ tempreg |= InitParam->Filter;
+ tempreg |= InitParam->Type;
+ tempreg |= InitParam->Int;
+ }
+ else
+ {
+ assert_param(IS_TSC_OUT(InitParam->Out));
+ tempreg |= InitParam->Out;
+ }
+
+ TSC->CTRL = tempreg;
+
+ /*TSC_ANA_SEL config*/
+ TSC->ANA_SEL = InitParam->PadOpt | InitParam->Speed;
+
+ return TSC_ERROR_OK;
+}
+
+/**
+ * @brief Config the clock source of TSC
+ * @param TSC_ClkSource specifies the clock source of TSC
+ * This parameter can be one of the following values:
+ * @arg TSC_CLK_SRC_LSI: TSC clock source is LSI(default)
+ * @arg TSC_CLK_SRC_LSE: TSC clock source is LSE,and LSE is oscillator
+ * @arg TSC_CLK_SRC_LSE_BYPASS: TSC clock source is LSE,and LSE is extennal clock
+ * @retval TSC error code
+ */
+TSC_ErrorTypeDef TSC_ClockConfig(uint32_t TSC_ClkSource)
+{
+ uint32_t timeout;
+
+ /*Enable PWR peripheral Clock*/
+ RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR,ENABLE);
+
+ if (TSC_CLK_SRC_LSI == TSC_ClkSource)
+ {
+ /*enable LSI clock*/
+ RCC_EnableLsi(ENABLE);
+
+ /*Wait LSI stable*/
+ timeout = 0;
+ while (RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_LSIRD) == RESET)
+ {
+ if (++timeout >TSC_TIMEOUT)
+ return TSC_ERROR_CLOCK;
+ }
+ }
+ else if ((TSC_CLK_SRC_LSE_BYPASS==TSC_ClkSource)||(TSC_CLK_SRC_LSE==TSC_ClkSource))
+ {
+ if (RCC_GetFlagStatus(RCC_LDCTRL_FLAG_LSERD)==RESET)
+ {
+ RCC_ConfigLse((TSC_ClkSource & (~RCC_LDCTRL_LSXSEL)),0x28);
+ timeout = 0;
+ while (RCC_GetFlagStatus(RCC_LDCTRL_FLAG_LSERD) == RESET)
+ {
+ if (++timeout >TSC_TIMEOUT)
+ return TSC_ERROR_CLOCK;
+ }
+ }
+ }
+ else
+ return TSC_ERROR_PARAMETER;
+
+ // Set bit 8 of PWR_CTRL1.Open PWR DBP.
+ PWR_BackupAccessEnable(ENABLE); //PWR->CTRL1 |= 0x100;
+
+ /*set LSI as TSC clock source*/
+ RCC_ConfigLSXClk(TSC_ClkSource & RCC_LDCTRL_LSXSEL);
+
+ /*Enable TSC clk*/
+ RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TSC,ENABLE);
+
+ return TSC_ERROR_OK;
+}
+
+/**
+* @brief Configure internal charge resistor for some channels
+* @param res: internal resistor selecte
+* This parameter can be one of the following values:
+* @arg TSC_RESR_CHN_RESIST_0: 1M OHM
+* @arg TSC_RESR_CHN_RESIST_1: 882K OHM
+* @arg TSC_RESR_CHN_RESIST_2: 756K OHM
+* @arg TSC_RESR_CHN_RESIST_3: 630K OHM
+* @arg TSC_RESR_CHN_RESIST_4: 504K OHM
+* @arg TSC_RESR_CHN_RESIST_5: 378K OHM
+* @arg TSC_RESR_CHN_RESIST_6: 252K OHM
+* @arg TSC_RESR_CHN_RESIST_7: 126K OHM
+* @param Channels: channels to be configed, as TSC_CHNEN defined
+* This parameter:bit[0:23] used,bit[24:31] must be 0
+* bitx: TSC channel x
+* @return: none
+*/
+TSC_ErrorTypeDef TSC_ConfigInternalResistor(uint32_t Channels, uint32_t res )
+{
+ uint32_t i,chn,timeout,nReg,nPos;
+
+ assert_param(IS_TSC_CHN(Channels));
+ assert_param(IS_TSC_RESISTOR_VALUE(res));
+
+ /*Check charge resistor value */
+ if (res > TSC_RESRx_CHN_RESIST_7)
+ return TSC_ERROR_PARAMETER;
+
+ /* waiting tsc hw for idle status.*/
+ timeout = 0;
+ do
+ {
+ __TSC_HW_DISABLE();
+
+ if (++timeout > TSC_TIMEOUT)
+ return TSC_ERROR_HW_MODE;
+ }while (__TSC_GET_HW_MODE());
+
+ /* Mask invalie bits*/
+ chn = Channels & TSC_CHNEN_CHN_SELx_Msk;
+
+ /* Set resistance for each channel one by one*/
+ for (i = 0; i> 3;
+ nPos = (i & 0x7UL)*4;
+ MODIFY_REG(TSC->RESR[nReg],TSC_RESRx_CHN_RESIST_Msk<>= 1;
+ }
+
+ return TSC_ERROR_OK;
+}
+
+/**
+* @brief Configure threshold value for some channels
+* @param Channels: channels to be configed, as TSC_CHNEN defined
+* This parameter:bit[0:23] used,bit[24:31] must be 0
+* bitx: TSC channel x
+* @param base: base value of threshold, 0-MAX_TSC_THRESHOLD_BASE
+* @param delta: delta value of threshold,0-MAX_TSC_THRESHOLD_DELRA
+* @return: None
+*/
+TSC_ErrorTypeDef TSC_ConfigThreshold( uint32_t Channels, uint32_t base, uint32_t delta)
+{
+ uint32_t i, chn,timeout;
+ assert_param(IS_TSC_CHN(Channels));
+ assert_param(IS_TSC_THRESHOLD_BASE(base));
+ assert_param(IS_TSC_THRESHOLD_DELTA(delta));
+
+ /*Check the base and delta value*/
+ if ( (base>MAX_TSC_THRESHOLD_BASE)||(delta>MAX_TSC_THRESHOLD_DELTA))
+ return TSC_ERROR_PARAMETER;
+
+ /* waiting tsc hw for idle status.*/
+ timeout = 0;
+ do
+ {
+ __TSC_HW_DISABLE();
+
+ if (++timeout > TSC_TIMEOUT)
+ return TSC_ERROR_HW_MODE;
+ }while (__TSC_GET_HW_MODE());
+
+ /*Mask invalie bits*/
+ chn = Channels & TSC_CHNEN_CHN_SELx_Msk;
+
+ /* Set the base and delta for each channnel one by one*/
+ for (i = 0; iTHRHD[i] = (base<>= 1;
+ }
+
+ return TSC_ERROR_OK;
+}
+
+
+/**
+* @brief Get parameters of one channel.
+* @param ChnCfg: Pointer of TSC_ChnCfg structure.
+* @param ChannelNum: The channel number of which we want to get parameters,must be less then MAX_TSC_HW_CHN
+* @return: None
+*/
+TSC_ErrorTypeDef TSC_GetChannelCfg( TSC_ChnCfg* ChnCfg, uint32_t ChannelNum)
+{
+ uint32_t nReg,nPos;
+
+ assert_param(IS_TSC_CHN_NUMBER(ChannelNum));
+
+ /*Check channel number*/
+ if (!(IS_TSC_CHN_NUMBER(ChannelNum)))
+ return TSC_ERROR_PARAMETER;
+
+ /* Get the base and delta value for a channel*/
+ ChnCfg->TSC_Base = (TSC->THRHD[ChannelNum] & TSC_THRHDx_BASE_Msk) >> TSC_THRHDx_BASE_Pos;
+ ChnCfg->TSC_Delta = (TSC->THRHD[ChannelNum] & TSC_THRHDx_DELTA_Msk)>> TSC_THRHDx_DELTA_Pos;
+
+ /* Get the charge resistor type for a channel*/
+ nReg = ChannelNum>>3;
+ nPos = (ChannelNum & 0x7UL)*4;
+ ChnCfg->TSC_Resistor = (TSC->RESR[nReg] >> nPos) & TSC_RESRx_CHN_RESIST_Msk;
+
+ return TSC_ERROR_OK;
+}
+
+
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_usart.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_usart.c
new file mode 100644
index 0000000000..25333a44f5
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_usart.c
@@ -0,0 +1,956 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_usart.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l43x_usart.h"
+#include "n32l43x_rcc.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup USART
+ * @brief USART driver modules
+ * @{
+ */
+
+/** @addtogroup USART_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Private_Defines
+ * @{
+ */
+
+#define CTRL1_UEN_SET ((uint16_t)0x2000) /*!< USART Enable Mask */
+#define CTRL1_UEN_RESET ((uint16_t)0xDFFF) /*!< USART Disable Mask */
+
+#define CTRL1_WUM_MASK ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */
+
+#define CTRL1_RCVWU_SET ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */
+#define CTRL1_RCVWU_RESET ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */
+#define CTRL1_SDBRK_SET ((uint16_t)0x0001) /*!< USART Break Character send Mask */
+#define CTRL1_CLR_MASK ((uint16_t)0xE9F3) /*!< USART CTRL1 Mask */
+#define CTRL2_ADDR_MASK ((uint16_t)0xFFF0) /*!< USART address Mask */
+
+#define CTRL2_LINMEN_SET ((uint16_t)0x4000) /*!< USART LIN Enable Mask */
+#define CTRL2_LINMEN_RESET ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */
+
+#define CTRL2_LINBDL_MASK ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */
+#define CTRL2_STPB_CLR_MASK ((uint16_t)0xCFFF) /*!< USART CTRL2 STOP Bits Mask */
+#define CTRL2_CLOCK_CLR_MASK ((uint16_t)0xF0FF) /*!< USART CTRL2 Clock Mask */
+
+#define CTRL3_SCMEN_SET ((uint16_t)0x0020) /*!< USART SC Enable Mask */
+#define CTRL3_SCMEN_RESET ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */
+
+#define CTRL3_SCNACK_SET ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */
+#define CTRL3_SCNACK_RESET ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */
+
+#define CTRL3_HDMEN_SET ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */
+#define CTRL3_HDMEN_RESET ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */
+
+#define CTRL3_IRDALP_MASK ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */
+#define CTRL3_CLR_MASK ((uint16_t)0xFCFF) /*!< USART CTRL3 Mask */
+
+#define CTRL3_IRDAMEN_SET ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */
+#define CTRL3_IRDAMEN_RESET ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */
+#define GTP_LSB_MASK ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */
+#define GTP_MSB_MASK ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */
+#define INT_MASK ((uint16_t)0x001F) /*!< USART Interrupt Mask */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the USARTx peripheral registers to their default reset values.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ */
+void USART_DeInit(USART_Module* USARTx)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ if (USARTx == USART1)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_USART1, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_USART1, DISABLE);
+ }
+ else if (USARTx == USART2)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART2, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART2, DISABLE);
+ }
+ else if (USARTx == USART3)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART3, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART3, DISABLE);
+ }
+ else if (USARTx == UART4)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART4, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART4, DISABLE);
+ }
+ else if (USARTx == UART5)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART5, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART5, DISABLE);
+ }
+}
+
+/**
+ * @brief Initializes the USARTx peripheral according to the specified
+ * parameters in the USART_InitStruct .
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_InitStruct pointer to a USART_InitType structure
+ * that contains the configuration information for the specified USART
+ * peripheral.
+ */
+void USART_Init(USART_Module* USARTx, USART_InitType* USART_InitStruct)
+{
+ uint32_t tmpregister = 0x00, apbclock = 0x00;
+ uint32_t integerdivider = 0x00;
+ uint32_t fractionaldivider = 0x00;
+ uint32_t usartxbase = 0;
+ RCC_ClocksType RCC_ClocksStatus;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_BAUDRATE(USART_InitStruct->BaudRate));
+ assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->WordLength));
+ assert_param(IS_USART_STOPBITS(USART_InitStruct->StopBits));
+ assert_param(IS_USART_PARITY(USART_InitStruct->Parity));
+ assert_param(IS_USART_MODE(USART_InitStruct->Mode));
+ assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->HardwareFlowControl));
+ /* The hardware flow control is available only for USART1, USART2 and USART3 */
+ if (USART_InitStruct->HardwareFlowControl != USART_HFCTRL_NONE)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ usartxbase = (uint32_t)USARTx;
+
+ /*---------------------------- USART CTRL2 Configuration -----------------------*/
+ tmpregister = USARTx->CTRL2;
+ /* Clear STOP[13:12] bits */
+ tmpregister &= CTRL2_STPB_CLR_MASK;
+ /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
+ /* Set STOP[13:12] bits according to StopBits value */
+ tmpregister |= (uint32_t)USART_InitStruct->StopBits;
+
+ /* Write to USART CTRL2 */
+ USARTx->CTRL2 = (uint16_t)tmpregister;
+
+ /*---------------------------- USART CTRL1 Configuration -----------------------*/
+ tmpregister = USARTx->CTRL1;
+ /* Clear M, PCE, PS, TE and RE bits */
+ tmpregister &= CTRL1_CLR_MASK;
+ /* Configure the USART Word Length, Parity and mode ----------------------- */
+ /* Set the M bits according to WordLength value */
+ /* Set PCE and PS bits according to Parity value */
+ /* Set TE and RE bits according to Mode value */
+ tmpregister |= (uint32_t)USART_InitStruct->WordLength | USART_InitStruct->Parity | USART_InitStruct->Mode;
+ /* Write to USART CTRL1 */
+ USARTx->CTRL1 = (uint16_t)tmpregister;
+
+ /*---------------------------- USART CTRL3 Configuration -----------------------*/
+ tmpregister = USARTx->CTRL3;
+ /* Clear CTSE and RTSE bits */
+ tmpregister &= CTRL3_CLR_MASK;
+ /* Configure the USART HFC -------------------------------------------------*/
+ /* Set CTSE and RTSE bits according to HardwareFlowControl value */
+ tmpregister |= USART_InitStruct->HardwareFlowControl;
+ /* Write to USART CTRL3 */
+ USARTx->CTRL3 = (uint16_t)tmpregister;
+
+ /*---------------------------- USART PBC Configuration -----------------------*/
+ /* Configure the USART Baud Rate -------------------------------------------*/
+ RCC_GetClocksFreqValue(&RCC_ClocksStatus);
+ if ((usartxbase == USART1_BASE) || (usartxbase == UART4_BASE) || (usartxbase == UART5_BASE))
+ {
+ apbclock = RCC_ClocksStatus.Pclk2Freq;
+ }
+ else
+ {
+ apbclock = RCC_ClocksStatus.Pclk1Freq;
+ }
+
+ /* Determine the integer part */
+ integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->BaudRate)));
+ tmpregister = (integerdivider / 100) << 4;
+
+ /* Determine the fractional part */
+ fractionaldivider = integerdivider - (100 * (tmpregister >> 4));
+
+ /* Implement the fractional part in the register */
+ tmpregister |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
+
+ /* Write to USART PBC */
+ USARTx->BRCF = (uint16_t)tmpregister;
+}
+
+/**
+ * @brief Fills each USART_InitStruct member with its default value.
+ * @param USART_InitStruct pointer to a USART_InitType structure
+ * which will be initialized.
+ */
+void USART_StructInit(USART_InitType* USART_InitStruct)
+{
+ /* USART_InitStruct members default value */
+ USART_InitStruct->BaudRate = 9600;
+ USART_InitStruct->WordLength = USART_WL_8B;
+ USART_InitStruct->StopBits = USART_STPB_1;
+ USART_InitStruct->Parity = USART_PE_NO;
+ USART_InitStruct->Mode = USART_MODE_RX | USART_MODE_TX;
+ USART_InitStruct->HardwareFlowControl = USART_HFCTRL_NONE;
+}
+
+/**
+ * @brief Initializes the USARTx peripheral Clock according to the
+ * specified parameters in the USART_ClockInitStruct .
+ * @param USARTx where x can be 1, 2, 3 to select the USART peripheral.
+ * @param USART_ClockInitStruct pointer to a USART_ClockInitType
+ * structure that contains the configuration information for the specified
+ * USART peripheral.
+ * @note The Smart Card and Synchronous modes are not available for UART4/UART5.
+ */
+void USART_ClockInit(USART_Module* USARTx, USART_ClockInitType* USART_ClockInitStruct)
+{
+ uint32_t tmpregister = 0x00;
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ assert_param(IS_USART_CLOCK(USART_ClockInitStruct->Clock));
+ assert_param(IS_USART_CPOL(USART_ClockInitStruct->Polarity));
+ assert_param(IS_USART_CPHA(USART_ClockInitStruct->Phase));
+ assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->LastBit));
+
+ /*---------------------------- USART CTRL2 Configuration -----------------------*/
+ tmpregister = USARTx->CTRL2;
+ /* Clear CLKEN, CPOL, CPHA and LBCL bits */
+ tmpregister &= CTRL2_CLOCK_CLR_MASK;
+ /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/
+ /* Set CLKEN bit according to Clock value */
+ /* Set CPOL bit according to Polarity value */
+ /* Set CPHA bit according to Phase value */
+ /* Set LBCL bit according to LastBit value */
+ tmpregister |= (uint32_t)USART_ClockInitStruct->Clock | USART_ClockInitStruct->Polarity
+ | USART_ClockInitStruct->Phase | USART_ClockInitStruct->LastBit;
+ /* Write to USART CTRL2 */
+ USARTx->CTRL2 = (uint16_t)tmpregister;
+}
+
+/**
+ * @brief Fills each USART_ClockInitStruct member with its default value.
+ * @param USART_ClockInitStruct pointer to a USART_ClockInitType
+ * structure which will be initialized.
+ */
+void USART_ClockStructInit(USART_ClockInitType* USART_ClockInitStruct)
+{
+ /* USART_ClockInitStruct members default value */
+ USART_ClockInitStruct->Clock = USART_CLK_DISABLE;
+ USART_ClockInitStruct->Polarity = USART_CLKPOL_LOW;
+ USART_ClockInitStruct->Phase = USART_CLKPHA_1EDGE;
+ USART_ClockInitStruct->LastBit = USART_CLKLB_DISABLE;
+}
+
+/**
+ * @brief Enables or disables the specified USART peripheral.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param Cmd new state of the USARTx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void USART_Enable(USART_Module* USARTx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected USART by setting the UE bit in the CTRL1 register */
+ USARTx->CTRL1 |= CTRL1_UEN_SET;
+ }
+ else
+ {
+ /* Disable the selected USART by clearing the UE bit in the CTRL1 register */
+ USARTx->CTRL1 &= CTRL1_UEN_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified USART interrupts.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_INT specifies the USART interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg USART_INT_CTSF CTS change interrupt (not available for UART4 and UART5)
+ * @arg USART_INT_LINBD LIN Break detection interrupt
+ * @arg USART_INT_TXDE Transmit Data Register empty interrupt
+ * @arg USART_INT_TXC Transmission complete interrupt
+ * @arg USART_INT_RXDNE Receive Data register not empty interrupt
+ * @arg USART_INT_IDLEF Idle line detection interrupt
+ * @arg USART_INT_PEF Parity Error interrupt
+ * @arg USART_INT_ERRF Error interrupt(Frame error, noise error, overrun error)
+ * @param Cmd new state of the specified USARTx interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void USART_ConfigInt(USART_Module* USARTx, uint16_t USART_INT, FunctionalState Cmd)
+{
+ uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
+ uint32_t usartxbase = 0x00;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_CFG_INT(USART_INT));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ /* The CTS interrupt is not available for UART4/UART5 */
+ if (USART_INT == USART_INT_CTSF)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ usartxbase = (uint32_t)USARTx;
+
+ /* Get the USART register index */
+ usartreg = (((uint8_t)USART_INT) >> 0x05);
+
+ /* Get the interrupt position */
+ itpos = USART_INT & INT_MASK;
+ itmask = (((uint32_t)0x01) << itpos);
+
+ if (usartreg == 0x01) /* The IT is in CTRL1 register */
+ {
+ usartxbase += 0x0C;
+ }
+ else if (usartreg == 0x02) /* The IT is in CTRL2 register */
+ {
+ usartxbase += 0x10;
+ }
+ else /* The IT is in CTRL3 register */
+ {
+ usartxbase += 0x14;
+ }
+ if (Cmd != DISABLE)
+ {
+ *(__IO uint32_t*)usartxbase |= itmask;
+ }
+ else
+ {
+ *(__IO uint32_t*)usartxbase &= ~itmask;
+ }
+}
+
+/**
+ * @brief Enables or disables the USART's DMA interface.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_DMAReq specifies the DMA request.
+ * This parameter can be any combination of the following values:
+ * @arg USART_DMAREQ_TX USART DMA transmit request
+ * @arg USART_DMAREQ_RX USART DMA receive request
+ * @param Cmd new state of the DMA Request sources.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void USART_EnableDMA(USART_Module* USARTx, uint16_t USART_DMAReq, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_DMAREQ(USART_DMAReq));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the DMA transfer for selected requests by setting the DMAT and/or
+ DADDR bits in the USART CTRL3 register */
+ USARTx->CTRL3 |= USART_DMAReq;
+ }
+ else
+ {
+ /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
+ DADDR bits in the USART CTRL3 register */
+ USARTx->CTRL3 &= (uint16_t)~USART_DMAReq;
+ }
+}
+
+/**
+ * @brief Sets the address of the USART node.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_Addr Indicates the address of the USART node.
+ */
+void USART_SetAddr(USART_Module* USARTx, uint8_t USART_Addr)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_ADDRESS(USART_Addr));
+
+ /* Clear the USART address */
+ USARTx->CTRL2 &= CTRL2_ADDR_MASK;
+ /* Set the USART address node */
+ USARTx->CTRL2 |= USART_Addr;
+}
+
+/**
+ * @brief Selects the USART WakeUp method.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_WakeUpMode specifies the USART wakeup method.
+ * This parameter can be one of the following values:
+ * @arg USART_WUM_IDLELINE WakeUp by an idle line detection
+ * @arg USART_WUM_ADDRMASK WakeUp by an address mark
+ */
+void USART_ConfigWakeUpMode(USART_Module* USARTx, uint16_t USART_WakeUpMode)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_WAKEUP(USART_WakeUpMode));
+
+ USARTx->CTRL1 &= CTRL1_WUM_MASK;
+ USARTx->CTRL1 |= USART_WakeUpMode;
+}
+
+/**
+ * @brief Determines if the USART is in mute mode or not.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param Cmd new state of the USART mute mode.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void USART_EnableRcvWakeUp(USART_Module* USARTx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the USART mute mode by setting the RWU bit in the CTRL1 register */
+ USARTx->CTRL1 |= CTRL1_RCVWU_SET;
+ }
+ else
+ {
+ /* Disable the USART mute mode by clearing the RWU bit in the CTRL1 register */
+ USARTx->CTRL1 &= CTRL1_RCVWU_RESET;
+ }
+}
+
+/**
+ * @brief Sets the USART LIN Break detection length.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_LINBreakDetectLength specifies the LIN break detection length.
+ * This parameter can be one of the following values:
+ * @arg USART_LINBDL_10B 10-bit break detection
+ * @arg USART_LINBDL_11B 11-bit break detection
+ */
+void USART_ConfigLINBreakDetectLength(USART_Module* USARTx, uint16_t USART_LINBreakDetectLength)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
+
+ USARTx->CTRL2 &= CTRL2_LINBDL_MASK;
+ USARTx->CTRL2 |= USART_LINBreakDetectLength;
+}
+
+/**
+ * @brief Enables or disables the USART's LIN mode.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param Cmd new state of the USART LIN mode.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void USART_EnableLIN(USART_Module* USARTx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the LIN mode by setting the LINEN bit in the CTRL2 register */
+ USARTx->CTRL2 |= CTRL2_LINMEN_SET;
+ }
+ else
+ {
+ /* Disable the LIN mode by clearing the LINEN bit in the CTRL2 register */
+ USARTx->CTRL2 &= CTRL2_LINMEN_RESET;
+ }
+}
+
+/**
+ * @brief Transmits single data through the USARTx peripheral.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param Data the data to transmit.
+ */
+void USART_SendData(USART_Module* USARTx, uint16_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_DATA(Data));
+
+ /* Transmit Data */
+ USARTx->DAT = (Data & (uint16_t)0x01FF);
+}
+
+/**
+ * @brief Returns the most recent received data by the USARTx peripheral.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @return The received data.
+ */
+uint16_t USART_ReceiveData(USART_Module* USARTx)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ /* Receive Data */
+ return (uint16_t)(USARTx->DAT & (uint16_t)0x01FF);
+}
+
+/**
+ * @brief Transmits break characters.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ */
+void USART_SendBreak(USART_Module* USARTx)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ /* Send break characters */
+ USARTx->CTRL1 |= CTRL1_SDBRK_SET;
+}
+
+/**
+ * @brief Sets the specified USART guard time.
+ * @param USARTx where x can be 1, 2 or 3 to select the USART peripheral.
+ * @param USART_GuardTime specifies the guard time.
+ * @note The guard time bits are not available for UART4/UART5.
+ */
+void USART_SetGuardTime(USART_Module* USARTx, uint8_t USART_GuardTime)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+
+ /* Clear the USART Guard time */
+ USARTx->GTP &= GTP_LSB_MASK;
+ /* Set the USART guard time */
+ USARTx->GTP |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
+}
+
+/**
+ * @brief Sets the system clock prescaler.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_Prescaler specifies the prescaler clock.
+ * @note The function is used for IrDA mode with UART4 and UART5.
+ */
+void USART_SetPrescaler(USART_Module* USARTx, uint8_t USART_Prescaler)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ /* Clear the USART prescaler */
+ USARTx->GTP &= GTP_MSB_MASK;
+ /* Set the USART prescaler */
+ USARTx->GTP |= USART_Prescaler;
+}
+
+/**
+ * @brief Enables or disables the USART's Smart Card mode.
+ * @param USARTx where x can be 1, 2 or 3 to select the USART peripheral.
+ * @param Cmd new state of the Smart Card mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note The Smart Card mode is not available for UART4/UART5.
+ */
+void USART_EnableSmartCard(USART_Module* USARTx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the SC mode by setting the SCEN bit in the CTRL3 register */
+ USARTx->CTRL3 |= CTRL3_SCMEN_SET;
+ }
+ else
+ {
+ /* Disable the SC mode by clearing the SCEN bit in the CTRL3 register */
+ USARTx->CTRL3 &= CTRL3_SCMEN_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables NACK transmission.
+ * @param USARTx where x can be 1, 2 or 3 to select the USART peripheral.
+ * @param Cmd new state of the NACK transmission.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note The Smart Card mode is not available for UART4/UART5.
+ */
+void USART_SetSmartCardNACK(USART_Module* USARTx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the NACK transmission by setting the NACK bit in the CTRL3 register */
+ USARTx->CTRL3 |= CTRL3_SCNACK_SET;
+ }
+ else
+ {
+ /* Disable the NACK transmission by clearing the NACK bit in the CTRL3 register */
+ USARTx->CTRL3 &= CTRL3_SCNACK_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the USART's Half Duplex communication.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param Cmd new state of the USART Communication.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void USART_EnableHalfDuplex(USART_Module* USARTx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CTRL3 register */
+ USARTx->CTRL3 |= CTRL3_HDMEN_SET;
+ }
+ else
+ {
+ /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CTRL3 register */
+ USARTx->CTRL3 &= CTRL3_HDMEN_RESET;
+ }
+}
+
+/**
+ * @brief Configures the USART's IrDA interface.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_IrDAMode specifies the IrDA mode.
+ * This parameter can be one of the following values:
+ * @arg USART_IRDAMODE_LOWPPWER
+ * @arg USART_IRDAMODE_NORMAL
+ */
+void USART_ConfigIrDAMode(USART_Module* USARTx, uint16_t USART_IrDAMode)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
+
+ USARTx->CTRL3 &= CTRL3_IRDALP_MASK;
+ USARTx->CTRL3 |= USART_IrDAMode;
+}
+
+/**
+ * @brief Enables or disables the USART's IrDA interface.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param Cmd new state of the IrDA mode.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void USART_EnableIrDA(USART_Module* USARTx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the IrDA mode by setting the IREN bit in the CTRL3 register */
+ USARTx->CTRL3 |= CTRL3_IRDAMEN_SET;
+ }
+ else
+ {
+ /* Disable the IrDA mode by clearing the IREN bit in the CTRL3 register */
+ USARTx->CTRL3 &= CTRL3_IRDAMEN_RESET;
+ }
+}
+
+/**
+ * @brief Checks whether the specified USART flag is set or not.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_FLAG specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg USART_FLAG_CTSF CTS Change flag (not available for UART4 and UART5)
+ * @arg USART_FLAG_LINBD LIN Break detection flag
+ * @arg USART_FLAG_TXDE Transmit data register empty flag
+ * @arg USART_FLAG_TXC Transmission Complete flag
+ * @arg USART_FLAG_RXDNE Receive data register not empty flag
+ * @arg USART_FLAG_IDLEF Idle Line detection flag
+ * @arg USART_FLAG_OREF OverRun Error flag
+ * @arg USART_FLAG_NEF Noise Error flag
+ * @arg USART_FLAG_FEF Framing Error flag
+ * @arg USART_FLAG_PEF Parity Error flag
+ * @return The new state of USART_FLAG (SET or RESET).
+ */
+FlagStatus USART_GetFlagStatus(USART_Module* USARTx, uint16_t USART_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_FLAG(USART_FLAG));
+ /* The CTS flag is not available for UART4/UART5 */
+ if (USART_FLAG == USART_FLAG_CTSF)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ if ((USARTx->STS & USART_FLAG) != (uint16_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the USARTx's pending flags.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_FLAG specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg USART_FLAG_CTSF CTS Change flag (not available for UART4 and UART5).
+ * @arg USART_FLAG_LINBD LIN Break detection flag.
+ * @arg USART_FLAG_TXC Transmission Complete flag.
+ * @arg USART_FLAG_RXDNE Receive data register not empty flag.
+ *
+ * @note
+ * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ * error) and IDLE (Idle line detected) flags are cleared by software
+ * sequence: a read operation to USART_SR register (USART_GetFlagStatus())
+ * followed by a read operation to USART_DR register (USART_ReceiveData()).
+ * - RXNE flag can be also cleared by a read to the USART_DR register
+ * (USART_ReceiveData()).
+ * - TC flag can be also cleared by software sequence: a read operation to
+ * USART_SR register (USART_GetFlagStatus()) followed by a write operation
+ * to USART_DR register (USART_SendData()).
+ * - TXE flag is cleared only by a write to the USART_DR register
+ * (USART_SendData()).
+ */
+void USART_ClrFlag(USART_Module* USARTx, uint16_t USART_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
+ /* The CTS flag is not available for UART4/UART5 */
+ if ((USART_FLAG & USART_FLAG_CTSF) == USART_FLAG_CTSF)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ USARTx->STS = (uint16_t)~USART_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified USART interrupt has occurred or not.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_INT specifies the USART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg USART_INT_CTSF CTS change interrupt (not available for UART4 and UART5)
+ * @arg USART_INT_LINBD LIN Break detection interrupt
+ * @arg USART_INT_TXDE Tansmit Data Register empty interrupt
+ * @arg USART_INT_TXC Transmission complete interrupt
+ * @arg USART_INT_RXDNE Receive Data register not empty interrupt
+ * @arg USART_INT_IDLEF Idle line detection interrupt
+ * @arg USART_INT_OREF OverRun Error interrupt
+ * @arg USART_INT_NEF Noise Error interrupt
+ * @arg USART_INT_FEF Framing Error interrupt
+ * @arg USART_INT_PEF Parity Error interrupt
+ * @return The new state of USART_INT (SET or RESET).
+ */
+INTStatus USART_GetIntStatus(USART_Module* USARTx, uint16_t USART_INT)
+{
+ uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
+ INTStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_GET_INT(USART_INT));
+ /* The CTS interrupt is not available for UART4/UART5 */
+ if (USART_INT == USART_INT_CTSF)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ /* Get the USART register index */
+ usartreg = (((uint8_t)USART_INT) >> 0x05);
+ /* Get the interrupt position */
+ itmask = USART_INT & INT_MASK;
+ itmask = (uint32_t)0x01 << itmask;
+
+ if (usartreg == 0x01) /* The IT is in CTRL1 register */
+ {
+ itmask &= USARTx->CTRL1;
+ }
+ else if (usartreg == 0x02) /* The IT is in CTRL2 register */
+ {
+ itmask &= USARTx->CTRL2;
+ }
+ else /* The IT is in CTRL3 register */
+ {
+ itmask &= USARTx->CTRL3;
+ }
+
+ bitpos = USART_INT >> 0x08;
+ bitpos = (uint32_t)0x01 << bitpos;
+ bitpos &= USARTx->STS;
+ if ((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the USARTx's interrupt pending bits.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_INT specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg USART_INT_CTSF CTS change interrupt (not available for UART4 and UART5)
+ * @arg USART_INT_LINBD LIN Break detection interrupt
+ * @arg USART_INT_TXC Transmission complete interrupt.
+ * @arg USART_INT_RXDNE Receive Data register not empty interrupt.
+ *
+ * @note
+ * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ * error) and IDLE (Idle line detected) pending bits are cleared by
+ * software sequence: a read operation to USART_SR register
+ * (USART_GetIntStatus()) followed by a read operation to USART_DR register
+ * (USART_ReceiveData()).
+ * - RXNE pending bit can be also cleared by a read to the USART_DR register
+ * (USART_ReceiveData()).
+ * - TC pending bit can be also cleared by software sequence: a read
+ * operation to USART_SR register (USART_GetIntStatus()) followed by a write
+ * operation to USART_DR register (USART_SendData()).
+ * - TXE pending bit is cleared only by a write to the USART_DR register
+ * (USART_SendData()).
+ */
+void USART_ClrIntPendingBit(USART_Module* USARTx, uint16_t USART_INT)
+{
+ uint16_t bitpos = 0x00, itmask = 0x00;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_CLR_INT(USART_INT));
+ /* The CTS interrupt is not available for UART4/UART5 */
+ if (USART_INT == USART_INT_CTSF)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ bitpos = USART_INT >> 0x08;
+ itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
+ USARTx->STS = (uint16_t)~itmask;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_wwdg.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_wwdg.c
new file mode 100644
index 0000000000..e2ed330967
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_wwdg.c
@@ -0,0 +1,219 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32l43x_wwdg.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32l43x_wwdg.h"
+#include "n32l43x_rcc.h"
+
+/** @addtogroup n32l43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup WWDG
+ * @brief WWDG driver modules
+ * @{
+ */
+
+/** @addtogroup WWDG_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Private_Defines
+ * @{
+ */
+
+/* ----------- WWDG registers bit address in the alias region ----------- */
+#define WWDG_OFFADDR (WWDG_BASE - PERIPH_BASE)
+
+/* Alias word address of EWI bit */
+#define CFG_OFFADDR (WWDG_OFFADDR + 0x04)
+#define EWINT_BIT 0x09
+#define CFG_EWINT_BB (PERIPH_BB_BASE + (CFG_OFFADDR * 32) + (EWINT_BIT * 4))
+
+/* --------------------- WWDG registers bit mask ------------------------ */
+
+/* CTRL register bit mask */
+#define CTRL_ACTB_SET ((uint32_t)0x00000080)
+
+/* CFG register bit mask */
+#define CFG_TIMERB_MASK ((uint32_t)0xFFFFFE7F)
+#define CFG_W_MASK ((uint32_t)0xFFFFFF80)
+#define BIT_MASK ((uint8_t)0x7F)
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the WWDG peripheral registers to their default reset values.
+ */
+void WWDG_DeInit(void)
+{
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_WWDG, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_WWDG, DISABLE);
+}
+
+/**
+ * @brief Sets the WWDG Prescaler.
+ * @param WWDG_Prescaler specifies the WWDG Prescaler.
+ * This parameter can be one of the following values:
+ * @arg WWDG_PRESCALER_DIV1 WWDG counter clock = (PCLK1/4096)/1
+ * @arg WWDG_PRESCALER_DIV2 WWDG counter clock = (PCLK1/4096)/2
+ * @arg WWDG_PRESCALER_DIV4 WWDG counter clock = (PCLK1/4096)/4
+ * @arg WWDG_PRESCALER_DIV8 WWDG counter clock = (PCLK1/4096)/8
+ */
+void WWDG_SetPrescalerDiv(uint32_t WWDG_Prescaler)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_WWDG_PRESCALER_DIV(WWDG_Prescaler));
+ /* Clear WDGTB[1:0] bits */
+ tmpregister = WWDG->CFG & CFG_TIMERB_MASK;
+ /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
+ tmpregister |= WWDG_Prescaler;
+ /* Store the new value */
+ WWDG->CFG = tmpregister;
+}
+
+/**
+ * @brief Sets the WWDG window value.
+ * @param WindowValue specifies the window value to be compared to the downcounter.
+ * This parameter value must be lower than 0x80.
+ */
+void WWDG_SetWValue(uint8_t WindowValue)
+{
+ __IO uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_WWDG_WVALUE(WindowValue));
+ /* Clear W[6:0] bits */
+ tmpregister = WWDG->CFG & CFG_W_MASK;
+ /* Set W[6:0] bits according to WindowValue value */
+ tmpregister |= WindowValue & (uint32_t)BIT_MASK;
+ /* Store the new value */
+ WWDG->CFG = tmpregister;
+}
+
+/**
+ * @brief Enables the WWDG Early Wakeup interrupt(EWI).
+ */
+void WWDG_EnableInt(void)
+{
+ *(__IO uint32_t*)CFG_EWINT_BB = (uint32_t)ENABLE;
+}
+
+/**
+ * @brief Sets the WWDG counter value.
+ * @param Counter specifies the watchdog counter value.
+ * This parameter must be a number between 0x40 and 0x7F.
+ */
+void WWDG_SetCnt(uint8_t Counter)
+{
+ /* Check the parameters */
+ assert_param(IS_WWDG_CNT(Counter));
+ /* Write to T[6:0] bits to configure the counter value, no need to do
+ a read-modify-write; writing a 0 to WDGA bit does nothing */
+ WWDG->CTRL = Counter & BIT_MASK;
+}
+
+/**
+ * @brief Enables WWDG and load the counter value.
+ * @param Counter specifies the watchdog counter value.
+ * This parameter must be a number between 0x40 and 0x7F.
+ */
+void WWDG_Enable(uint8_t Counter)
+{
+ /* Check the parameters */
+ assert_param(IS_WWDG_CNT(Counter));
+ WWDG->CTRL = CTRL_ACTB_SET | Counter;
+}
+
+/**
+ * @brief Checks whether the Early Wakeup interrupt flag is set or not.
+ * @return The new state of the Early Wakeup interrupt flag (SET or RESET)
+ */
+FlagStatus WWDG_GetEWINTF(void)
+{
+ return (FlagStatus)(WWDG->STS);
+}
+
+/**
+ * @brief Clears Early Wakeup interrupt flag.
+ */
+void WWDG_ClrEWINTF(void)
+{
+ WWDG->STS = (uint32_t)RESET;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_core.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_core.h
new file mode 100644
index 0000000000..5b81b4ea2c
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_core.h
@@ -0,0 +1,264 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_core.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_CORE_H__
+#define __USB_CORE_H__
+
+#include "n32l43x.h"
+
+/**
+ * @addtogroup N32L43X_USB_Driver
+ * @brief N32L43x USB low level driver
+ * @{
+ */
+
+typedef enum _CONTROL_STATE
+{
+ WaitSetup, /* 0 */
+ SettingUp, /* 1 */
+ InData, /* 2 */
+ OutData, /* 3 */
+ LastInData, /* 4 */
+ LastOutData, /* 5 */
+ WaitStatusIn, /* 6 */
+ WaitStatusOut, /* 7 */
+ Stalled, /* 8 */
+ Pause /* 9 */
+} USB_ControlState; /* The state machine states of a control pipe */
+
+typedef struct OneDescriptor
+{
+ uint8_t* Descriptor;
+ uint16_t Descriptor_Size;
+} USB_OneDescriptor, *PONE_DESCRIPTOR;
+/* All the request process routines return a value of this type
+ If the return value is not SUCCESS or NOT_READY,
+ the software will STALL the correspond endpoint */
+typedef enum _RESULT
+{
+ Success = 0, /* Process successfully */
+ Error,
+ UnSupport,
+ Not_Ready /* The process has not been finished, endpoint will be
+ NAK to further request */
+} USB_Result;
+
+/*-*-*-*-*-*-*-*-*-*-* Definitions for endpoint level -*-*-*-*-*-*-*-*-*-*-*-*/
+typedef struct _ENDPOINT_INFO
+{
+ /* When send data out of the device,
+ CopyData() is used to get data buffer 'Length' bytes data
+ if Length is 0,
+ CopyData() returns the total length of the data
+ if the request is not supported, returns 0
+ (NEW Feature )
+ if CopyData() returns -1, the calling routine should not proceed
+ further and will resume the SETUP process by the class device
+ if Length is not 0,
+ CopyData() returns a pointer to indicate the data location
+ Usb_wLength is the data remain to be sent,
+ Usb_wOffset is the Offset of original data
+ When receive data from the host,
+ CopyData() is used to get user data buffer which is capable
+ of Length bytes data to copy data from the endpoint buffer.
+ if Length is 0,
+ CopyData() returns the available data length,
+ if Length is not 0,
+ CopyData() returns user buffer address
+ Usb_rLength is the data remain to be received,
+ Usb_rPointer is the Offset of data buffer
+ */
+ uint16_t Usb_wLength;
+ uint16_t Usb_wOffset;
+ uint16_t PacketSize;
+ uint8_t* (*CopyData)(uint16_t Length);
+} USB_EndpointMess;
+
+/*-*-*-*-*-*-*-*-*-*-*-* Definitions for device level -*-*-*-*-*-*-*-*-*-*-*-*/
+
+typedef struct _DEVICE
+{
+ uint8_t TotalEndpoint; /* Number of endpoints that are used */
+ uint8_t TotalConfiguration; /* Number of configuration available */
+} USB_Device;
+
+typedef union
+{
+ uint16_t w;
+ struct BW
+ {
+ uint8_t bb1;
+ uint8_t bb0;
+ } bw;
+} uint16_t_uint8_t;
+
+typedef struct _DEVICE_INFO
+{
+ uint8_t bmRequestType; /* bmRequestType */
+ uint8_t bRequest; /* bRequest */
+ uint16_t_uint8_t wValues; /* wValue */
+ uint16_t_uint8_t wIndexs; /* wIndex */
+ uint16_t_uint8_t wLengths; /* wLength */
+
+ uint8_t CtrlState; /* of type USB_ControlState */
+ uint8_t CurrentFeature;
+ uint8_t CurrentConfiguration; /* Selected configuration */
+ uint8_t CurrentInterface; /* Selected interface of current configuration */
+ uint8_t CurrentAlternateSetting; /* Selected Alternate Setting of current
+ interface*/
+
+ USB_EndpointMess Ctrl_Info;
+} USB_DeviceMess;
+
+typedef struct _DEVICE_PROP
+{
+ void (*Init)(void); /* Initialize the device */
+ void (*Reset)(void); /* Reset routine of this device */
+
+ /* Device dependent process after the status stage */
+ void (*Process_Status_IN)(void);
+ void (*Process_Status_OUT)(void);
+
+ /* Procedure of process on setup stage of a class specified request with data stage */
+ /* All class specified requests with data stage are processed in Class_Data_Setup
+ Class_Data_Setup()
+ responses to check all special requests and fills USB_EndpointMess
+ according to the request
+ If IN tokens are expected, then wLength & wOffset will be filled
+ with the total transferring bytes and the starting position
+ If OUT tokens are expected, then rLength & rOffset will be filled
+ with the total expected bytes and the starting position in the buffer
+
+ If the request is valid, Class_Data_Setup returns SUCCESS, else UNSUPPORT
+
+ CAUTION:
+ Since GET_CONFIGURATION & GET_INTERFACE are highly related to
+ the individual classes, they will be checked and processed here.
+ */
+ USB_Result (*Class_Data_Setup)(uint8_t RequestNo);
+
+ /* Procedure of process on setup stage of a class specified request without data stage */
+ /* All class specified requests without data stage are processed in Class_NoData_Setup
+ Class_NoData_Setup
+ responses to check all special requests and perform the request
+
+ CAUTION:
+ Since SET_CONFIGURATION & SET_INTERFACE are highly related to
+ the individual classes, they will be checked and processed here.
+ */
+ USB_Result (*Class_NoData_Setup)(uint8_t RequestNo);
+
+ /*Class_Get_Interface_Setting
+ This function is used by the file usb_core.c to test if the selected Interface
+ and Alternate Setting (uint8_t Interface, uint8_t AlternateSetting) are supported by
+ the application.
+ This function is writing by user. It should return "SUCCESS" if the Interface
+ and Alternate Setting are supported by the application or "UNSUPPORT" if they
+ are not supported. */
+
+ USB_Result (*Class_Get_Interface_Setting)(uint8_t Interface, uint8_t AlternateSetting);
+
+ uint8_t* (*GetDeviceDescriptor)(uint16_t Length);
+ uint8_t* (*GetConfigDescriptor)(uint16_t Length);
+ uint8_t* (*GetStringDescriptor)(uint16_t Length);
+
+ /* This field is not used in current library version. It is kept only for
+ compatibility with previous versions */
+ void* RxEP_buffer;
+
+ uint8_t MaxPacketSize;
+
+} DEVICE_PROP;
+
+typedef struct _USER_STANDARD_REQUESTS
+{
+ void (*User_GetConfiguration)(void); /* Get Configuration */
+ void (*User_SetConfiguration)(void); /* Set Configuration */
+ void (*User_GetInterface)(void); /* Get Interface */
+ void (*User_SetInterface)(void); /* Set Interface */
+ void (*User_GetStatus)(void); /* Get Status */
+ void (*User_ClearFeature)(void); /* Clear Feature */
+ void (*User_SetEndPointFeature)(void); /* Set Endpoint Feature */
+ void (*User_SetDeviceFeature)(void); /* Set Device Feature */
+ void (*User_SetDeviceAddress)(void); /* Set Device Address */
+} USER_STANDARD_REQUESTS;
+
+#define Type_Recipient (pInformation->bmRequestType & (REQUEST_TYPE | RECIPIENT))
+
+#define Usb_rLength Usb_wLength
+#define Usb_rOffset Usb_wOffset
+
+#define USBwValue wValues.w
+#define USBwValue0 wValues.bw.bb0
+#define USBwValue1 wValues.bw.bb1
+#define USBwIndex wIndexs.w
+#define USBwIndex0 wIndexs.bw.bb0
+#define USBwIndex1 wIndexs.bw.bb1
+#define USBwLength wLengths.w
+#define USBwLength0 wLengths.bw.bb0
+#define USBwLength1 wLengths.bw.bb1
+
+uint8_t USB_ProcessSetup0(void);
+uint8_t USB_ProcessPost0(void);
+uint8_t USB_ProcessOut0(void);
+uint8_t USB_ProcessIn0(void);
+
+USB_Result Standard_SetEndPointFeature(void);
+USB_Result Standard_SetDeviceFeature(void);
+
+uint8_t* Standard_GetConfiguration(uint16_t Length);
+USB_Result Standard_SetConfiguration(void);
+uint8_t* Standard_GetInterface(uint16_t Length);
+USB_Result Standard_SetInterface(void);
+uint8_t* Standard_GetDescriptorData(uint16_t Length, PONE_DESCRIPTOR pDesc);
+
+uint8_t* Standard_GetStatus(uint16_t Length);
+USB_Result Standard_ClearFeature(void);
+void USB_SetDeviceAddress(uint8_t);
+void USB_ProcessNop(void);
+
+extern DEVICE_PROP Device_Property;
+extern USER_STANDARD_REQUESTS User_Standard_Requests;
+extern USB_Device Device_Table;
+extern USB_DeviceMess Device_Info;
+
+/* cells saving status during interrupt servicing */
+extern __IO uint16_t SaveRState;
+extern __IO uint16_t SaveTState;
+
+/**
+ * @}
+ */
+
+#endif /* __USB_CORE_H__ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_def.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_def.h
new file mode 100644
index 0000000000..5a7e2881ee
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_def.h
@@ -0,0 +1,98 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_def.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_DEF_H__
+#define __USB_DEF_H__
+
+/**
+ * @addtogroup N32L43X_USB_Driver
+ * @{
+ */
+
+typedef enum _RECIPIENT_TYPE
+{
+ DEVICE_RECIPIENT, /* Recipient device */
+ INTERFACE_RECIPIENT, /* Recipient interface */
+ ENDPOINT_RECIPIENT, /* Recipient endpoint */
+ OTHER_RECIPIENT
+} RECIPIENT_TYPE;
+
+typedef enum _STANDARD_REQUESTS
+{
+ GET_STATUS = 0,
+ CLR_FEATURE,
+ RESERVED1,
+ SET_FEATURE,
+ RESERVED2,
+ SET_ADDRESS,
+ GET_DESCRIPTOR,
+ SET_DESCRIPTOR,
+ GET_CONFIGURATION,
+ SET_CONFIGURATION,
+ GET_INTERFACE,
+ SET_INTERFACE,
+ TOTAL_SREQUEST, /* Total number of Standard request */
+ SYNCH_FRAME = 12
+} STANDARD_REQUESTS;
+
+/* Definition of "USBwValue" */
+typedef enum _DESCRIPTOR_TYPE
+{
+ DEVICE_DESCRIPTOR = 1,
+ CONFIG_DESCRIPTOR,
+ STRING_DESCRIPTOR,
+ INTERFACE_DESCRIPTOR,
+ ENDPOINT_DESCRIPTOR
+} DESCRIPTOR_TYPE;
+
+/* Feature selector of a SET_FEATURE or CLR_FEATURE */
+typedef enum _FEATURE_SELECTOR
+{
+ ENDPOINT_STALL,
+ DEVICE_REMOTE_WAKEUP
+} FEATURE_SELECTOR;
+
+/* Definition of "bmRequestType" */
+#define REQUEST_TYPE 0x60 /* Mask to get request type */
+#define STANDARD_REQUEST 0x00 /* Standard request */
+#define CLASS_REQUEST 0x20 /* Class request */
+#define VENDOR_REQUEST 0x40 /* Vendor request */
+
+#define RECIPIENT 0x1F /* Mask to get recipient */
+
+/**
+ * @}
+ */
+
+#endif /* __USB_DEF_H__ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_init.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_init.h
new file mode 100644
index 0000000000..90180b0a32
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_init.h
@@ -0,0 +1,71 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_init.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_INIT_H__
+#define __USB_INIT_H__
+
+#include "n32l43x.h"
+#include "usb_core.h"
+
+/**
+ * @addtogroup N32L43X_USB_Driver
+ * @{
+ */
+
+void USB_Init(void);
+
+/* The number of current endpoint, it will be used to specify an endpoint */
+extern uint8_t EPindex;
+/* The number of current device, it is an index to the Device_Table */
+/*extern uint8_t Device_no; */
+/* Points to the USB_DeviceMess structure of current device */
+/* The purpose of this register is to speed up the execution */
+extern USB_DeviceMess* pInformation;
+/* Points to the DEVICE_PROP structure of current device */
+/* The purpose of this register is to speed up the execution */
+extern DEVICE_PROP* pProperty;
+/* Temporary save the state of Rx & Tx status. */
+/* Whenever the Rx or Tx state is changed, its value is saved */
+/* in this variable first and will be set to the EPRB or EPRA */
+/* at the end of interrupt process */
+extern USER_STANDARD_REQUESTS* pUser_Standard_Requests;
+
+extern uint16_t SaveState;
+extern uint16_t wInterrupt_Mask;
+
+/**
+ * @}
+ */
+
+#endif /* __USB_INIT_H__ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_int.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_int.h
new file mode 100644
index 0000000000..b7e2d8f8a7
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_int.h
@@ -0,0 +1,50 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_int.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_INT_H__
+#define __USB_INT_H__
+
+/**
+ * @addtogroup N32L43X_USB_Driver
+ * @{
+ */
+
+void USB_CorrectTransferLp(void);
+void USB_CorrectTransferHp(void);
+
+/**
+ * @}
+ */
+
+#endif /* __USB_INT_H__ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_lib.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_lib.h
new file mode 100644
index 0000000000..0b1a044c89
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_lib.h
@@ -0,0 +1,47 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_lib.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_LIB_H__
+#define __USB_LIB_H__
+
+#include "usb_type.h"
+#include "usb_regs.h"
+#include "usb_def.h"
+#include "usb_core.h"
+#include "usb_init.h"
+#include "usb_sil.h"
+#include "usb_mem.h"
+#include "usb_int.h"
+
+#endif /* __USB_LIB_H__ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_mem.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_mem.h
new file mode 100644
index 0000000000..56c3f48cf8
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_mem.h
@@ -0,0 +1,52 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_mem.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_MEM_H__
+#define __USB_MEM_H__
+
+#include "n32l43x.h"
+
+/**
+ * @addtogroup N32L43X_USB_Driver
+ * @{
+ */
+
+void USB_CopyUserToPMABuf(uint8_t* pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+void USB_CopyPMAToUserBuf(uint8_t* pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+
+/**
+ * @}
+ */
+
+#endif /*__USB_MEM_H__*/
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_regs.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_regs.h
new file mode 100644
index 0000000000..3f07cef87b
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_regs.h
@@ -0,0 +1,716 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_regs.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_REGS_H__
+#define __USB_REGS_H__
+
+#include "n32l43x.h"
+
+/**
+ * @addtogroup N32L43X_USB_Driver
+ * @{
+ */
+
+typedef enum _EP_DBUF_DIR
+{
+ /* double buffered endpoint direction */
+ EP_DBUF_ERR,
+ EP_DBUF_OUT,
+ EP_DBUF_IN
+} EP_DBUF_DIR;
+
+/* endpoint buffer number */
+enum EP_BUF_NUM
+{
+ EP_NOBUF,
+ EP_BUF0,
+ EP_BUF1
+};
+
+#define RegBase (0x40005C00L) /* USB_IP Peripheral Registers base address */
+#define PMAAddr (0x40006000L) /* USB_IP Packet Memory Area base address */
+
+/******************************************************************************/
+/* Special registers */
+/******************************************************************************/
+/* Pull up controller register */
+#define DP_CTRL ((__IO unsigned*)(0x40001824))
+
+#define _ClrDPCtrl() (*DP_CTRL = (*DP_CTRL) & (~0x8000000));
+#define _EnPortPullup() (*DP_CTRL = (*DP_CTRL) | 0x02000000);
+#define _DisPortPullup() (*DP_CTRL = (*DP_CTRL) & 0xFDFFFFFF);
+
+/******************************************************************************/
+/* General registers */
+/******************************************************************************/
+
+/* Control register */
+#define USB_CTRL ((__IO unsigned*)(RegBase + 0x40))
+/* Interrupt status register */
+#define USB_STS ((__IO unsigned*)(RegBase + 0x44))
+/* Frame number register */
+#define USB_FN ((__IO unsigned*)(RegBase + 0x48))
+/* Device address register */
+#define USB_ADDR ((__IO unsigned*)(RegBase + 0x4C))
+/* Buffer Table address register */
+#define USB_BUFTAB ((__IO unsigned*)(RegBase + 0x50))
+/******************************************************************************/
+/* Endpoint registers */
+/******************************************************************************/
+#define EP0REG ((__IO unsigned*)(RegBase)) /* endpoint 0 register address */
+
+/* Endpoint Addresses (w/direction) */
+#define EP0_OUT ((uint8_t)0x00)
+#define EP0_IN ((uint8_t)0x80)
+#define EP1_OUT ((uint8_t)0x01)
+#define EP1_IN ((uint8_t)0x81)
+#define EP2_OUT ((uint8_t)0x02)
+#define EP2_IN ((uint8_t)0x82)
+#define EP3_OUT ((uint8_t)0x03)
+#define EP3_IN ((uint8_t)0x83)
+#define EP4_OUT ((uint8_t)0x04)
+#define EP4_IN ((uint8_t)0x84)
+#define EP5_OUT ((uint8_t)0x05)
+#define EP5_IN ((uint8_t)0x85)
+#define EP6_OUT ((uint8_t)0x06)
+#define EP6_IN ((uint8_t)0x86)
+#define EP7_OUT ((uint8_t)0x07)
+#define EP7_IN ((uint8_t)0x87)
+
+/* endpoints enumeration */
+#define ENDP0 ((uint8_t)0)
+#define ENDP1 ((uint8_t)1)
+#define ENDP2 ((uint8_t)2)
+#define ENDP3 ((uint8_t)3)
+#define ENDP4 ((uint8_t)4)
+#define ENDP5 ((uint8_t)5)
+#define ENDP6 ((uint8_t)6)
+#define ENDP7 ((uint8_t)7)
+
+/******************************************************************************/
+/* USB_STS interrupt events */
+/******************************************************************************/
+#define STS_CTRS (0x8000) /* Correct TRansfer (clear-only bit) */
+#define STS_DOVR (0x4000) /* DMA OVeR/underrun (clear-only bit) */
+#define STS_ERROR (0x2000) /* ERRor (clear-only bit) */
+#define STS_WKUP (0x1000) /* WaKe UP (clear-only bit) */
+#define STS_SUSPD (0x0800) /* SUSPend (clear-only bit) */
+#define STS_RST (0x0400) /* RESET (clear-only bit) */
+#define STS_SOF (0x0200) /* Start Of Frame (clear-only bit) */
+#define STS_ESOF (0x0100) /* Expected Start Of Frame (clear-only bit) */
+
+#define STS_DIR (0x0010) /* DIRection of transaction (read-only bit) */
+#define STS_EP_ID (0x000F) /* EndPoint IDentifier (read-only bit) */
+
+#define CLR_CTRS (~STS_CTRS) /* clear Correct TRansfer bit */
+#define CLR_DOVR (~STS_DOVR) /* clear DMA OVeR/underrun bit*/
+#define CLR_ERROR (~STS_ERROR) /* clear ERRor bit */
+#define CLR_WKUP (~STS_WKUP) /* clear WaKe UP bit */
+#define CLR_SUSPD (~STS_SUSPD) /* clear SUSPend bit */
+#define CLR_RST (~STS_RST) /* clear RESET bit */
+#define CLR_SOF (~STS_SOF) /* clear Start Of Frame bit */
+#define CLR_ESOF (~STS_ESOF) /* clear Expected Start Of Frame bit */
+
+/******************************************************************************/
+/* USB_CTRL control register bits definitions */
+/******************************************************************************/
+#define CTRL_CTRSM (0x8000) /* Correct TRansfer Mask */
+#define CTRL_DOVRM (0x4000) /* DMA OVeR/underrun Mask */
+#define CTRL_ERRORM (0x2000) /* ERRor Mask */
+#define CTRL_WKUPM (0x1000) /* WaKe UP Mask */
+#define CTRL_SUSPDM (0x0800) /* SUSPend Mask */
+#define CTRL_RSTM (0x0400) /* RESET Mask */
+#define CTRL_SOFM (0x0200) /* Start Of Frame Mask */
+#define CTRL_ESOFM (0x0100) /* Expected Start Of Frame Mask */
+
+#define CTRL_RESUM (0x0010) /* RESUME request */
+#define CTRL_FSUSPD (0x0008) /* Force SUSPend */
+#define CTRL_LP_MODE (0x0004) /* Low-power MODE */
+#define CTRL_PD (0x0002) /* Power DoWN */
+#define CTRL_FRST (0x0001) /* Force USB RESet */
+
+/******************************************************************************/
+/* USB_FN Frame Number Register bit definitions */
+/******************************************************************************/
+#define FN_RXDP (0x8000) /* status of D+ data line */
+#define FN_RXDM (0x4000) /* status of D- data line */
+#define FN_LCK (0x2000) /* LoCKed */
+#define FN_LSOF (0x1800) /* Lost SOF */
+#define FN_FNUM (0x07FF) /* Frame Number */
+/******************************************************************************/
+/* USB_ADDR Device ADDRess bit definitions */
+/******************************************************************************/
+#define ADDR_EFUC (0x80)
+#define ADDR_ADDR (0x7F)
+/******************************************************************************/
+/* Endpoint register */
+/******************************************************************************/
+/* bit positions */
+#define EP_CTRS_RX (0x8000) /* EndPoint Correct TRansfer RX */
+#define EP_DATTOG_RX (0x4000) /* EndPoint Data TOGGLE RX */
+#define EPRX_STS (0x3000) /* EndPoint RX STATus bit field */
+#define EP_SETUP (0x0800) /* EndPoint SETUP */
+#define EP_T_FIELD (0x0600) /* EndPoint TYPE */
+#define EP_KIND (0x0100) /* EndPoint KIND */
+#define EP_CTRS_TX (0x0080) /* EndPoint Correct TRansfer TX */
+#define EP_DATTOG_TX (0x0040) /* EndPoint Data TOGGLE TX */
+#define EPTX_STS (0x0030) /* EndPoint TX STATus bit field */
+#define EPADDR_FIELD (0x000F) /* EndPoint ADDRess FIELD */
+
+/* EndPoint REGister INTEN (no toggle fields) */
+#define EPREG_MASK (EP_CTRS_RX | EP_SETUP | EP_T_FIELD | EP_KIND | EP_CTRS_TX | EPADDR_FIELD)
+
+/* EP_TYPE[1:0] EndPoint TYPE */
+#define EP_TYPE_MASK (0x0600) /* EndPoint TYPE Mask */
+#define EP_BULK (0x0000) /* EndPoint BULK */
+#define EP_CONTROL (0x0200) /* EndPoint CONTROL */
+#define EP_ISOCHRONOUS (0x0400) /* EndPoint ISOCHRONOUS */
+#define EP_INTERRUPT (0x0600) /* EndPoint INTERRUPT */
+#define EP_T_MASK (~EP_T_FIELD & EPREG_MASK)
+
+/* EP_KIND EndPoint KIND */
+#define EPKIND_MASK (~EP_KIND & EPREG_MASK)
+
+/* STAT_TX[1:0] STATus for TX transfer */
+#define EP_TX_DIS (0x0000) /* EndPoint TX DISabled */
+#define EP_TX_STALL (0x0010) /* EndPoint TX STALLed */
+#define EP_TX_NAK (0x0020) /* EndPoint TX NAKed */
+#define EP_TX_VALID (0x0030) /* EndPoint TX VALID */
+#define EPTX_DATTOG1 (0x0010) /* EndPoint TX Data TOGgle bit1 */
+#define EPTX_DATTOG2 (0x0020) /* EndPoint TX Data TOGgle bit2 */
+#define EPTX_DATTOGMASK (EPTX_STS | EPREG_MASK)
+
+/* STAT_RX[1:0] STATus for RX transfer */
+#define EP_RX_DIS (0x0000) /* EndPoint RX DISabled */
+#define EP_RX_STALL (0x1000) /* EndPoint RX STALLed */
+#define EP_RX_NAK (0x2000) /* EndPoint RX NAKed */
+#define EP_RX_VALID (0x3000) /* EndPoint RX VALID */
+#define EPRX_DATTOG1 (0x1000) /* EndPoint RX Data TOGgle bit1 */
+#define EPRX_DATTOG2 (0x2000) /* EndPoint RX Data TOGgle bit1 */
+#define EPRX_DATTOGMASK (EPRX_STS | EPREG_MASK)
+
+/* USB_SetCtrl */
+#define _SetCNTR(wRegValue) (*USB_CTRL = (uint16_t)wRegValue)
+
+/* USB_SetSts */
+#define _SetISTR(wRegValue) (*USB_STS = (uint16_t)wRegValue)
+
+/* USB_SetAddr */
+#define _SetDADDR(wRegValue) (*USB_ADDR = (uint16_t)wRegValue)
+
+/* USB_SetBuftab */
+#define _SetBTABLE(wRegValue) (*USB_BUFTAB = (uint16_t)(wRegValue & 0xFFF8))
+
+/* USB_GetCtrl */
+#define _GetCNTR() ((uint16_t)*USB_CTRL)
+
+/* USB_GetSts */
+#define _GetISTR() ((uint16_t)*USB_STS)
+
+/* USB_GetFn */
+#define _GetFNR() ((uint16_t)*USB_FN)
+
+/* USB_GetAddr */
+#define _GetDADDR() ((uint16_t)*USB_ADDR)
+
+/* USB_GetBTABLE */
+#define _GetBTABLE() ((uint16_t)*USB_BUFTAB)
+
+/* USB_SetEndPoint */
+#define _SetENDPOINT(bEpNum, wRegValue) (*(EP0REG + bEpNum) = (uint16_t)wRegValue)
+
+/* USB_GetEndPoint */
+#define _GetENDPOINT(bEpNum) ((uint16_t)(*(EP0REG + bEpNum)))
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpType
+ * Description : sets the type in the endpoint register(bits EP_TYPE[1:0])
+ * Input : bEpNum: Endpoint Number.
+ * wType
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPType(bEpNum, wType) (_SetENDPOINT(bEpNum, ((_GetENDPOINT(bEpNum) & EP_T_MASK) | wType)))
+
+/*******************************************************************************
+ * Macro Name : USB_GetEpType
+ * Description : gets the type in the endpoint register(bits EP_TYPE[1:0])
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : Endpoint Type
+ *******************************************************************************/
+#define _GetEPType(bEpNum) (_GetENDPOINT(bEpNum) & EP_T_FIELD)
+
+/*******************************************************************************
+ * Macro Name : SetEPTxStatus
+ * Description : sets the status for tx transfer (bits STAT_TX[1:0]).
+ * Input : bEpNum: Endpoint Number.
+ * wState: new state
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPTxStatus(bEpNum, wState) \
+ { \
+ register uint16_t _wRegVal; \
+ _wRegVal = _GetENDPOINT(bEpNum) & EPTX_DATTOGMASK; \
+ /* toggle first bit ? */ \
+ if ((EPTX_DATTOG1 & wState) != 0) \
+ _wRegVal ^= EPTX_DATTOG1; \
+ /* toggle second bit ? */ \
+ if ((EPTX_DATTOG2 & wState) != 0) \
+ _wRegVal ^= EPTX_DATTOG2; \
+ _SetENDPOINT(bEpNum, (_wRegVal | EP_CTRS_RX | EP_CTRS_TX)); \
+ } /* _SetEPTxStatus */
+
+/*******************************************************************************
+ * Macro Name : SetEPRxStatus
+ * Description : sets the status for rx transfer (bits STAT_TX[1:0])
+ * Input : bEpNum: Endpoint Number.
+ * wState: new state.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPRxStatus(bEpNum, wState) \
+ { \
+ register uint16_t _wRegVal; \
+ \
+ _wRegVal = _GetENDPOINT(bEpNum) & EPRX_DATTOGMASK; \
+ /* toggle first bit ? */ \
+ if ((EPRX_DATTOG1 & wState) != 0) \
+ _wRegVal ^= EPRX_DATTOG1; \
+ /* toggle second bit ? */ \
+ if ((EPRX_DATTOG2 & wState) != 0) \
+ _wRegVal ^= EPRX_DATTOG2; \
+ _SetENDPOINT(bEpNum, (_wRegVal | EP_CTRS_RX | EP_CTRS_TX)); \
+ } /* _SetEPRxStatus */
+
+/*******************************************************************************
+ * Macro Name : SetEPRxTxStatus
+ * Description : sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
+ * Input : bEpNum: Endpoint Number.
+ * wStaterx: new state.
+ * wStatetx: new state.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPRxTxStatus(bEpNum, wStaterx, wStatetx) \
+ { \
+ register uint32_t _wRegVal; \
+ \
+ _wRegVal = _GetENDPOINT(bEpNum) & (EPRX_DATTOGMASK | EPTX_STS); \
+ /* toggle first bit ? */ \
+ if ((EPRX_DATTOG1 & wStaterx) != 0) \
+ _wRegVal ^= EPRX_DATTOG1; \
+ /* toggle second bit ? */ \
+ if ((EPRX_DATTOG2 & wStaterx) != 0) \
+ _wRegVal ^= EPRX_DATTOG2; \
+ /* toggle first bit ? */ \
+ if ((EPTX_DATTOG1 & wStatetx) != 0) \
+ _wRegVal ^= EPTX_DATTOG1; \
+ /* toggle second bit ? */ \
+ if ((EPTX_DATTOG2 & wStatetx) != 0) \
+ _wRegVal ^= EPTX_DATTOG2; \
+ _SetENDPOINT(bEpNum, _wRegVal | EP_CTRS_RX | EP_CTRS_TX); \
+ } /* _SetEPRxTxStatus */
+/*******************************************************************************
+ * Macro Name : USB_GetEpTxSts / USB_GetEpRxSts
+ * Description : gets the status for tx/rx transfer (bits STAT_TX[1:0]
+ * /STAT_RX[1:0])
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : status .
+ *******************************************************************************/
+#define _GetEPTxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EPTX_STS)
+
+#define _GetEPRxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EPRX_STS)
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpTxValid / USB_SetEpRxValid
+ * Description : sets directly the VALID tx/rx-status into the enpoint register
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPTxValid(bEpNum) (_SetEPTxStatus(bEpNum, EP_TX_VALID))
+
+#define _SetEPRxValid(bEpNum) (_SetEPRxStatus(bEpNum, EP_RX_VALID))
+
+/*******************************************************************************
+ * Macro Name : USB_GetTxStallSts / USB_GetRxStallSts.
+ * Description : checks stall condition in an endpoint.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : TRUE = endpoint in stall condition.
+ *******************************************************************************/
+#define _GetTxStallStatus(bEpNum) (_GetEPTxStatus(bEpNum) == EP_TX_STALL)
+#define _GetRxStallStatus(bEpNum) (_GetEPRxStatus(bEpNum) == EP_RX_STALL)
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpKind / USB_ClrEpKind.
+ * Description : set & clear EP_KIND bit.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEP_KIND(bEpNum) \
+ (_SetENDPOINT(bEpNum, (EP_CTRS_RX | EP_CTRS_TX | ((_GetENDPOINT(bEpNum) | EP_KIND) & EPREG_MASK))))
+#define _ClearEP_KIND(bEpNum) (_SetENDPOINT(bEpNum, (EP_CTRS_RX | EP_CTRS_TX | (_GetENDPOINT(bEpNum) & EPKIND_MASK))))
+
+/*******************************************************************************
+ * Macro Name : USB_SetStsOut / USB_ClrStsOut.
+ * Description : Sets/clears directly STATUS_OUT bit in the endpoint register.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _Set_Status_Out(bEpNum) _SetEP_KIND(bEpNum)
+#define _Clear_Status_Out(bEpNum) _ClearEP_KIND(bEpNum)
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpDoubleBufer / USB_ClrEpDoubleBufer.
+ * Description : Sets/clears directly EP_KIND bit in the endpoint register.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPDoubleBuff(bEpNum) _SetEP_KIND(bEpNum)
+#define _ClearEPDoubleBuff(bEpNum) _ClearEP_KIND(bEpNum)
+
+/*******************************************************************************
+ * Macro Name : USB_ClrEpCtrsRx / USB_ClrEpCtrsTx.
+ * Description : Clears bit CTR_RX / CTR_TX in the endpoint register.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _ClearEP_CTR_RX(bEpNum) (_SetENDPOINT(bEpNum, _GetENDPOINT(bEpNum) & 0x7FFF & EPREG_MASK))
+#define _ClearEP_CTR_TX(bEpNum) (_SetENDPOINT(bEpNum, _GetENDPOINT(bEpNum) & 0xFF7F & EPREG_MASK))
+
+/*******************************************************************************
+ * Macro Name : USB_DattogRx / USB_DattogTx .
+ * Description : Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _ToggleDTOG_RX(bEpNum) \
+ (_SetENDPOINT(bEpNum, EP_CTRS_RX | EP_CTRS_TX | EP_DATTOG_RX | (_GetENDPOINT(bEpNum) & EPREG_MASK)))
+#define _ToggleDTOG_TX(bEpNum) \
+ (_SetENDPOINT(bEpNum, EP_CTRS_RX | EP_CTRS_TX | EP_DATTOG_TX | (_GetENDPOINT(bEpNum) & EPREG_MASK)))
+
+/*******************************************************************************
+ * Macro Name : USB_ClrDattogRx / USB_ClrDattogTx.
+ * Description : Clears DTOG_RX / DTOG_TX bit in the endpoint register.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _ClearDTOG_RX(bEpNum) \
+ if ((_GetENDPOINT(bEpNum) & EP_DATTOG_RX) != 0) \
+ _ToggleDTOG_RX(bEpNum)
+#define _ClearDTOG_TX(bEpNum) \
+ if ((_GetENDPOINT(bEpNum) & EP_DATTOG_TX) != 0) \
+ _ToggleDTOG_TX(bEpNum)
+/*******************************************************************************
+ * Macro Name : USB_SetEpAddress.
+ * Description : Sets address in an endpoint register.
+ * Input : bEpNum: Endpoint Number.
+ * bAddr: Address.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPAddress(bEpNum, bAddr) \
+ _SetENDPOINT(bEpNum, EP_CTRS_RX | EP_CTRS_TX | (_GetENDPOINT(bEpNum) & EPREG_MASK) | bAddr)
+
+/*******************************************************************************
+ * Macro Name : USB_GetEpAddress.
+ * Description : Gets address in an endpoint register.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _GetEPAddress(bEpNum) ((uint8_t)(_GetENDPOINT(bEpNum) & EPADDR_FIELD))
+
+#define _pEPTxAddr(bEpNum) ((uint32_t*)((_GetBTABLE() + bEpNum * 8) * 2 + PMAAddr))
+#define _pEPTxCount(bEpNum) ((uint32_t*)((_GetBTABLE() + bEpNum * 8 + 2) * 2 + PMAAddr))
+#define _pEPRxAddr(bEpNum) ((uint32_t*)((_GetBTABLE() + bEpNum * 8 + 4) * 2 + PMAAddr))
+#define _pEPRxCount(bEpNum) ((uint32_t*)((_GetBTABLE() + bEpNum * 8 + 6) * 2 + PMAAddr))
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpTxAddr / USB_SetEpRxAddr.
+ * Description : sets address of the tx/rx buffer.
+ * Input : bEpNum: Endpoint Number.
+ * wAddr: address to be set (must be word aligned).
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPTxAddr(bEpNum, wAddr) (*_pEPTxAddr(bEpNum) = ((wAddr >> 1) << 1))
+#define _SetEPRxAddr(bEpNum, wAddr) (*_pEPRxAddr(bEpNum) = ((wAddr >> 1) << 1))
+
+/*******************************************************************************
+ * Macro Name : USB_GetEpTxAddr / USB_GetEpRxAddr.
+ * Description : Gets address of the tx/rx buffer.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : address of the buffer.
+ *******************************************************************************/
+#define _GetEPTxAddr(bEpNum) ((uint16_t)*_pEPTxAddr(bEpNum))
+#define _GetEPRxAddr(bEpNum) ((uint16_t)*_pEPRxAddr(bEpNum))
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpCntRxReg.
+ * Description : Sets counter of rx buffer with no. of blocks.
+ * Input : pdwReg: pointer to counter.
+ * wCount: Counter.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _BlocksOf32(dwReg, wCount, wNBlocks) \
+ { \
+ wNBlocks = wCount >> 5; \
+ if ((wCount & 0x1f) == 0) \
+ wNBlocks--; \
+ *pdwReg = (uint32_t)((wNBlocks << 10) | 0x8000); \
+ } /* _BlocksOf32 */
+
+#define _BlocksOf2(dwReg, wCount, wNBlocks) \
+ { \
+ wNBlocks = wCount >> 1; \
+ if ((wCount & 0x1) != 0) \
+ wNBlocks++; \
+ *pdwReg = (uint32_t)(wNBlocks << 10); \
+ } /* _BlocksOf2 */
+
+#define _SetEPCountRxReg(dwReg, wCount) \
+ { \
+ uint16_t wNBlocks; \
+ if (wCount > 62) \
+ { \
+ _BlocksOf32(dwReg, wCount, wNBlocks); \
+ } \
+ else \
+ { \
+ _BlocksOf2(dwReg, wCount, wNBlocks); \
+ } \
+ } /* _SetEPCountRxReg */
+
+#define _SetEPRxDblBuf0Count(bEpNum, wCount) \
+ { \
+ uint32_t* pdwReg = _pEPTxCount(bEpNum); \
+ _SetEPCountRxReg(pdwReg, wCount); \
+ }
+/*******************************************************************************
+ * Macro Name : USB_SetEpTxCnt / USB_SetEpRxCnt.
+ * Description : sets counter for the tx/rx buffer.
+ * Input : bEpNum: endpoint number.
+ * wCount: Counter value.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPTxCount(bEpNum, wCount) (*_pEPTxCount(bEpNum) = wCount)
+#define _SetEPRxCount(bEpNum, wCount) \
+ { \
+ uint32_t* pdwReg = _pEPRxCount(bEpNum); \
+ _SetEPCountRxReg(pdwReg, wCount); \
+ }
+/*******************************************************************************
+ * Macro Name : USB_GetEpTxCnt / USB_GetEpRxCnt.
+ * Description : gets counter of the tx buffer.
+ * Input : bEpNum: endpoint number.
+ * Output : None.
+ * Return : Counter value.
+ *******************************************************************************/
+#define _GetEPTxCount(bEpNum) ((uint16_t)(*_pEPTxCount(bEpNum)) & 0x3ff)
+#define _GetEPRxCount(bEpNum) ((uint16_t)(*_pEPRxCount(bEpNum)) & 0x3ff)
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpDblBuf0Addr / USB_SetEpDblBuf1Addr.
+ * Description : Sets buffer 0/1 address in a double buffer endpoint.
+ * Input : bEpNum: endpoint number.
+ * : wBuf0Addr: buffer 0 address.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPDblBuf0Addr(bEpNum, wBuf0Addr) \
+ { \
+ _SetEPTxAddr(bEpNum, wBuf0Addr); \
+ }
+#define _SetEPDblBuf1Addr(bEpNum, wBuf1Addr) \
+ { \
+ _SetEPRxAddr(bEpNum, wBuf1Addr); \
+ }
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpDblBuferAddr.
+ * Description : Sets addresses in a double buffer endpoint.
+ * Input : bEpNum: endpoint number.
+ * : wBuf0Addr: buffer 0 address.
+ * : wBuf1Addr = buffer 1 address.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPDblBuffAddr(bEpNum, wBuf0Addr, wBuf1Addr) \
+ { \
+ _SetEPDblBuf0Addr(bEpNum, wBuf0Addr); \
+ _SetEPDblBuf1Addr(bEpNum, wBuf1Addr); \
+ } /* _SetEPDblBuffAddr */
+
+/*******************************************************************************
+ * Macro Name : USB_GetEpDblBuf0Addr / USB_GetEpDblBuf1Addr.
+ * Description : Gets buffer 0/1 address of a double buffer endpoint.
+ * Input : bEpNum: endpoint number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _GetEPDblBuf0Addr(bEpNum) (_GetEPTxAddr(bEpNum))
+#define _GetEPDblBuf1Addr(bEpNum) (_GetEPRxAddr(bEpNum))
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpDblBuferCnt / USB_SetEpDblBuf0Cnt / USB_SetEpDblBuf1Cnt.
+ * Description : Gets buffer 0/1 address of a double buffer endpoint.
+ * Input : bEpNum: endpoint number.
+ * : bDir: endpoint dir EP_DBUF_OUT = OUT
+ * EP_DBUF_IN = IN
+ * : wCount: Counter value
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPDblBuf0Count(bEpNum, bDir, wCount) \
+ { \
+ if (bDir == EP_DBUF_OUT) \
+ /* OUT endpoint */ \
+ { \
+ _SetEPRxDblBuf0Count(bEpNum, wCount); \
+ } \
+ else if (bDir == EP_DBUF_IN) \
+ /* IN endpoint */ \
+ *_pEPTxCount(bEpNum) = (uint32_t)wCount; \
+ } /* USB_SetEpDblBuf0Cnt*/
+
+#define _SetEPDblBuf1Count(bEpNum, bDir, wCount) \
+ { \
+ if (bDir == EP_DBUF_OUT) \
+ /* OUT endpoint */ \
+ { \
+ _SetEPRxCount(bEpNum, wCount); \
+ } \
+ else if (bDir == EP_DBUF_IN) \
+ /* IN endpoint */ \
+ *_pEPRxCount(bEpNum) = (uint32_t)wCount; \
+ } /* USB_SetEpDblBuf1Cnt */
+
+#define _SetEPDblBuffCount(bEpNum, bDir, wCount) \
+ { \
+ _SetEPDblBuf0Count(bEpNum, bDir, wCount); \
+ _SetEPDblBuf1Count(bEpNum, bDir, wCount); \
+ } /* _SetEPDblBuffCount */
+
+/*******************************************************************************
+ * Macro Name : USB_GetEpDblBuf0Cnt / USB_GetEpDblBuf1Cnt.
+ * Description : Gets buffer 0/1 rx/tx counter for double buffering.
+ * Input : bEpNum: endpoint number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _GetEPDblBuf0Count(bEpNum) (_GetEPTxCount(bEpNum))
+#define _GetEPDblBuf1Count(bEpNum) (_GetEPRxCount(bEpNum))
+
+extern __IO uint16_t wIstr; /* USB_STS register last read value */
+
+void USB_SetCtrl(uint16_t /*wRegValue*/);
+void USB_SetSts(uint16_t /*wRegValue*/);
+void USB_SetAddr(uint16_t /*wRegValue*/);
+void USB_SetBuftab(uint16_t /*wRegValue*/);
+void USB_SetBuftab(uint16_t /*wRegValue*/);
+uint16_t USB_GetCtrl(void);
+uint16_t USB_GetSts(void);
+uint16_t USB_GetFn(void);
+uint16_t USB_GetAddr(void);
+uint16_t USB_GetBTABLE(void);
+void USB_SetEndPoint(uint8_t /*bEpNum*/, uint16_t /*wRegValue*/);
+uint16_t USB_GetEndPoint(uint8_t /*bEpNum*/);
+void USB_SetEpType(uint8_t /*bEpNum*/, uint16_t /*wType*/);
+uint16_t USB_GetEpType(uint8_t /*bEpNum*/);
+void SetEPTxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/);
+void SetEPRxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/);
+void USB_SetDouBleBuferEpStall(uint8_t /*bEpNum*/, uint8_t bDir);
+uint16_t USB_GetEpTxSts(uint8_t /*bEpNum*/);
+uint16_t USB_GetEpRxSts(uint8_t /*bEpNum*/);
+void USB_SetEpTxValid(uint8_t /*bEpNum*/);
+void USB_SetEpRxValid(uint8_t /*bEpNum*/);
+uint16_t USB_GetTxStallSts(uint8_t /*bEpNum*/);
+uint16_t USB_GetRxStallSts(uint8_t /*bEpNum*/);
+void USB_SetEpKind(uint8_t /*bEpNum*/);
+void USB_ClrEpKind(uint8_t /*bEpNum*/);
+void USB_SetStsOut(uint8_t /*bEpNum*/);
+void USB_ClrStsOut(uint8_t /*bEpNum*/);
+void USB_SetEpDoubleBufer(uint8_t /*bEpNum*/);
+void USB_ClrEpDoubleBufer(uint8_t /*bEpNum*/);
+void USB_ClrEpCtrsRx(uint8_t /*bEpNum*/);
+void USB_ClrEpCtrsTx(uint8_t /*bEpNum*/);
+void USB_DattogRx(uint8_t /*bEpNum*/);
+void USB_DattogTx(uint8_t /*bEpNum*/);
+void USB_ClrDattogRx(uint8_t /*bEpNum*/);
+void USB_ClrDattogTx(uint8_t /*bEpNum*/);
+void USB_SetEpAddress(uint8_t /*bEpNum*/, uint8_t /*bAddr*/);
+uint8_t USB_GetEpAddress(uint8_t /*bEpNum*/);
+void USB_SetEpTxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/);
+void USB_SetEpRxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/);
+uint16_t USB_GetEpTxAddr(uint8_t /*bEpNum*/);
+uint16_t USB_GetEpRxAddr(uint8_t /*bEpNum*/);
+void USB_SetEpCntRxReg(uint32_t* /*pdwReg*/, uint16_t /*wCount*/);
+void USB_SetEpTxCnt(uint8_t /*bEpNum*/, uint16_t /*wCount*/);
+void USB_SetEpRxCnt(uint8_t /*bEpNum*/, uint16_t /*wCount*/);
+uint16_t USB_GetEpTxCnt(uint8_t /*bEpNum*/);
+uint16_t USB_GetEpRxCnt(uint8_t /*bEpNum*/);
+void USB_SetEpDblBuf0Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/);
+void USB_SetEpDblBuf1Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf1Addr*/);
+void USB_SetEpDblBuferAddr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/, uint16_t /*wBuf1Addr*/);
+uint16_t USB_GetEpDblBuf0Addr(uint8_t /*bEpNum*/);
+uint16_t USB_GetEpDblBuf1Addr(uint8_t /*bEpNum*/);
+void USB_SetEpDblBuferCnt(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
+void USB_SetEpDblBuf0Cnt(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
+void USB_SetEpDblBuf1Cnt(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
+uint16_t USB_GetEpDblBuf0Cnt(uint8_t /*bEpNum*/);
+uint16_t USB_GetEpDblBuf1Cnt(uint8_t /*bEpNum*/);
+EP_DBUF_DIR GetEPDblBufDir(uint8_t /*bEpNum*/);
+void USB_FreeUserBuf(uint8_t bEpNum /*bEpNum*/, uint8_t bDir);
+uint16_t USB_ToWord(uint8_t, uint8_t);
+uint16_t USB_ByteSwap(uint16_t);
+
+/**
+ * @}
+ */
+
+#endif /* __USB_REGS_H__ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_sil.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_sil.h
new file mode 100644
index 0000000000..25c4bf8307
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_sil.h
@@ -0,0 +1,53 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_sil.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_SIL_H__
+#define __USB_SIL_H__
+
+#include "n32l43x.h"
+
+/**
+ * @addtogroup N32L43X_USB_Driver
+ * @{
+ */
+
+uint32_t USB_SilInit(void);
+uint32_t USB_SilWrite(uint8_t bEpAddr, uint8_t* pBufferPointer, uint32_t wBufferSize);
+uint32_t USB_SilRead(uint8_t bEpAddr, uint8_t* pBufferPointer);
+
+/**
+ * @}
+ */
+
+#endif /* __USB_SIL_H__ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_type.h b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_type.h
new file mode 100644
index 0000000000..2d5e916d5d
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_type.h
@@ -0,0 +1,54 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_type.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_TYPE_H__
+#define __USB_TYPE_H__
+
+#include "usb_conf.h"
+#include
+
+/**
+ * @addtogroup N32L43X_USB_Driver
+ * @{
+ */
+
+#ifndef NULL
+#define NULL ((void*)0)
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* __USB_TYPE_H__ */
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_core.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_core.c
new file mode 100644
index 0000000000..77ece332a8
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_core.c
@@ -0,0 +1,950 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_core.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "usb_lib.h"
+
+#define ValBit(VAR, Place) (VAR & (1 << Place))
+#define SetBit(VAR, Place) (VAR |= (1 << Place))
+#define ClrBit(VAR, Place) (VAR &= ((1 << Place) ^ 255))
+
+#define Send0LengthData() \
+ { \
+ _SetEPTxCount(ENDP0, 0); \
+ vSetEPTxStatus(EP_TX_VALID); \
+ }
+
+#define vSetEPRxStatus(st) (SaveRState = st)
+#define vSetEPTxStatus(st) (SaveTState = st)
+
+#define USB_StatusIn() Send0LengthData()
+#define USB_StatusOut() vSetEPRxStatus(EP_RX_VALID)
+
+#define StatusInfo0 StatusInfo.bw.bb1 /* Reverse bb0 & bb1 */
+#define StatusInfo1 StatusInfo.bw.bb0
+
+uint16_t_uint8_t StatusInfo;
+
+bool Data_Mul_MaxPacketSize = false;
+
+static void DataStageOut(void);
+static void DataStageIn(void);
+static void NoData_Setup0(void);
+static void Data_Setup0(void);
+
+/**
+ * @brief Return the current configuration variable address.
+ * Input : Length - How many bytes are needed.
+ * @return Return 1 , if the request is invalid when "Length" is 0.
+ * Return "Buffer" if the "Length" is not 0.
+ */
+uint8_t* Standard_GetConfiguration(uint16_t Length)
+{
+ if (Length == 0)
+ {
+ pInformation->Ctrl_Info.Usb_wLength = sizeof(pInformation->CurrentConfiguration);
+ return 0;
+ }
+ pUser_Standard_Requests->User_GetConfiguration();
+ return (uint8_t*)&pInformation->CurrentConfiguration;
+}
+
+/**
+ * @brief This routine is called to set the configuration value
+ * Then each class should configure device itself.
+ * @return
+ * - Success, if the request is performed.
+ * - UnSupport, if the request is invalid.
+ */
+USB_Result Standard_SetConfiguration(void)
+{
+ if ((pInformation->USBwValue0 <= Device_Table.TotalConfiguration) && (pInformation->USBwValue1 == 0)
+ && (pInformation->USBwIndex == 0)) /*call Back usb spec 2.0*/
+ {
+ pInformation->CurrentConfiguration = pInformation->USBwValue0;
+ pUser_Standard_Requests->User_SetConfiguration();
+ return Success;
+ }
+ else
+ {
+ return UnSupport;
+ }
+}
+
+/**
+ * @brief Return the Alternate Setting of the current interface.
+ * Input : Length - How many bytes are needed.
+ * @return
+ * - NULL, if the request is invalid when "Length" is 0.
+ * - "Buffer" if the "Length" is not 0.
+ */
+uint8_t* Standard_GetInterface(uint16_t Length)
+{
+ if (Length == 0)
+ {
+ pInformation->Ctrl_Info.Usb_wLength = sizeof(pInformation->CurrentAlternateSetting);
+ return 0;
+ }
+ pUser_Standard_Requests->User_GetInterface();
+ return (uint8_t*)&pInformation->CurrentAlternateSetting;
+}
+
+/**
+ * @brief This routine is called to set the interface.
+ * Then each class should configure the interface them self.
+ * @return
+ * - Success, if the request is performed.
+ * - UnSupport, if the request is invalid.
+ */
+USB_Result Standard_SetInterface(void)
+{
+ USB_Result Re;
+ /*Test if the specified Interface and Alternate Setting are supported by
+ the application Firmware*/
+ Re = (*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, pInformation->USBwValue0);
+
+ if (pInformation->CurrentConfiguration != 0)
+ {
+ if ((Re != Success) || (pInformation->USBwIndex1 != 0) || (pInformation->USBwValue1 != 0))
+ {
+ return UnSupport;
+ }
+ else if (Re == Success)
+ {
+ pUser_Standard_Requests->User_SetInterface();
+ pInformation->CurrentInterface = pInformation->USBwIndex0;
+ pInformation->CurrentAlternateSetting = pInformation->USBwValue0;
+ return Success;
+ }
+ }
+
+ return UnSupport;
+}
+
+/**
+ * @brief Copy the device request data to "StatusInfo buffer".
+ * Input : - Length - How many bytes are needed.
+ * @return Return 0, if the request is at end of data block,
+ * or is invalid when "Length" is 0.
+ */
+uint8_t* Standard_GetStatus(uint16_t Length)
+{
+ if (Length == 0)
+ {
+ pInformation->Ctrl_Info.Usb_wLength = 2;
+ return 0;
+ }
+
+ /* Reset Status Information */
+ StatusInfo.w = 0;
+
+ if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+ {
+ /*Get Device Status */
+ uint8_t Feature = pInformation->CurrentFeature;
+
+ /* Remote Wakeup enabled */
+ if (ValBit(Feature, 5))
+ {
+ SetBit(StatusInfo0, 1);
+ }
+ else
+ {
+ ClrBit(StatusInfo0, 1);
+ }
+
+ /* Bus-powered */
+ if (ValBit(Feature, 6))
+ {
+ SetBit(StatusInfo0, 0);
+ }
+ else /* Self-powered */
+ {
+ ClrBit(StatusInfo0, 0);
+ }
+ }
+ /*Interface Status*/
+ else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
+ {
+ return (uint8_t*)&StatusInfo;
+ }
+ /*Get EndPoint Status*/
+ else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+ {
+ uint8_t Related_Endpoint;
+ uint8_t wIndex0 = pInformation->USBwIndex0;
+
+ Related_Endpoint = (wIndex0 & 0x0f);
+ if (ValBit(wIndex0, 7))
+ {
+ /* IN endpoint */
+ if (_GetTxStallStatus(Related_Endpoint))
+ {
+ SetBit(StatusInfo0, 0); /* IN Endpoint stalled */
+ }
+ }
+ else
+ {
+ /* OUT endpoint */
+ if (_GetRxStallStatus(Related_Endpoint))
+ {
+ SetBit(StatusInfo0, 0); /* OUT Endpoint stalled */
+ }
+ }
+ }
+ else
+ {
+ return NULL;
+ }
+ pUser_Standard_Requests->User_GetStatus();
+ return (uint8_t*)&StatusInfo;
+}
+
+/**
+ * @brief Clear or disable a specific feature.
+ * @return - Return Success, if the request is performed.
+ * - Return UnSupport, if the request is invalid.
+ */
+USB_Result Standard_ClearFeature(void)
+{
+ uint32_t Type_Rec = Type_Recipient;
+ uint32_t Status;
+
+ if (Type_Rec == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+ { /*Device Clear Feature*/
+ ClrBit(pInformation->CurrentFeature, 5);
+ return Success;
+ }
+ else if (Type_Rec == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+ { /*EndPoint Clear Feature*/
+ USB_Device* pDev;
+ uint32_t Related_Endpoint;
+ uint32_t wIndex0;
+ uint32_t rEP;
+
+ if ((pInformation->USBwValue != ENDPOINT_STALL) || (pInformation->USBwIndex1 != 0))
+ {
+ return UnSupport;
+ }
+
+ pDev = &Device_Table;
+ wIndex0 = pInformation->USBwIndex0;
+ rEP = wIndex0 & ~0x80;
+ Related_Endpoint = ENDP0 + rEP;
+
+ if (ValBit(pInformation->USBwIndex0, 7))
+ {
+ /*Get Status of endpoint & stall the request if the related_ENdpoint
+ is Disabled*/
+ Status = _GetEPTxStatus(Related_Endpoint);
+ }
+ else
+ {
+ Status = _GetEPRxStatus(Related_Endpoint);
+ }
+
+ if ((rEP >= pDev->TotalEndpoint) || (Status == 0) || (pInformation->CurrentConfiguration == 0))
+ {
+ return UnSupport;
+ }
+
+ if (wIndex0 & 0x80)
+ {
+ /* IN endpoint */
+ if (_GetTxStallStatus(Related_Endpoint))
+ {
+ USB_ClrDattogTx(Related_Endpoint);
+ SetEPTxStatus(Related_Endpoint, EP_TX_VALID);
+ }
+ }
+ else
+ {
+ /* OUT endpoint */
+ if (_GetRxStallStatus(Related_Endpoint))
+ {
+ if (Related_Endpoint == ENDP0)
+ {
+ /* After clear the STALL, enable the default endpoint receiver */
+ USB_SetEpRxCnt(Related_Endpoint, Device_Property.MaxPacketSize);
+ _SetEPRxStatus(Related_Endpoint, EP_RX_VALID);
+ }
+ else
+ {
+ USB_ClrDattogRx(Related_Endpoint);
+ _SetEPRxStatus(Related_Endpoint, EP_RX_VALID);
+ }
+ }
+ }
+ pUser_Standard_Requests->User_ClearFeature();
+ return Success;
+ }
+
+ return UnSupport;
+}
+
+/**
+ * @brief Set or enable a specific feature of EndPoint
+ * @return - Return Success, if the request is performed.
+ * - Return UnSupport, if the request is invalid.
+ */
+USB_Result Standard_SetEndPointFeature(void)
+{
+ uint32_t wIndex0;
+ uint32_t Related_Endpoint;
+ uint32_t rEP;
+ uint32_t Status;
+
+ wIndex0 = pInformation->USBwIndex0;
+ rEP = wIndex0 & ~0x80;
+ Related_Endpoint = ENDP0 + rEP;
+
+ if (ValBit(pInformation->USBwIndex0, 7))
+ {
+ /* get Status of endpoint & stall the request if the related_ENdpoint
+ is Disabled*/
+ Status = _GetEPTxStatus(Related_Endpoint);
+ }
+ else
+ {
+ Status = _GetEPRxStatus(Related_Endpoint);
+ }
+
+ if (Related_Endpoint >= Device_Table.TotalEndpoint || pInformation->USBwValue != 0 || Status == 0
+ || pInformation->CurrentConfiguration == 0)
+ {
+ return UnSupport;
+ }
+ else
+ {
+ if (wIndex0 & 0x80)
+ {
+ /* IN endpoint */
+ _SetEPTxStatus(Related_Endpoint, EP_TX_STALL);
+ }
+
+ else
+ {
+ /* OUT endpoint */
+ _SetEPRxStatus(Related_Endpoint, EP_RX_STALL);
+ }
+ }
+ pUser_Standard_Requests->User_SetEndPointFeature();
+ return Success;
+}
+
+/**
+ * @brief Set or enable a specific feature of Device.
+ * @return - Return Success, if the request is performed.
+ * - Return UnSupport, if the request is invalid.
+ */
+USB_Result Standard_SetDeviceFeature(void)
+{
+ SetBit(pInformation->CurrentFeature, 5);
+ pUser_Standard_Requests->User_SetDeviceFeature();
+ return Success;
+}
+
+/**
+ * @brief Standard_GetDescriptorData is used for descriptors transfer.
+ * : This routine is used for the descriptors resident in Flash
+ * or RAM
+ * pDesc can be in either Flash or RAM
+ * The purpose of this routine is to have a versatile way to
+ * response descriptors request. It allows user to generate
+ * certain descriptors with software or read descriptors from
+ * external storage part by part.
+ * Input : - Length - Length of the data in this transfer.
+ * - pDesc - A pointer points to descriptor struct.
+ * The structure gives the initial address of the descriptor and
+ * its original size.
+ * @return Address of a part of the descriptor pointed by the Usb_
+ * wOffset The buffer pointed by this address contains at least
+ * Length bytes.
+ */
+uint8_t* Standard_GetDescriptorData(uint16_t Length, USB_OneDescriptor* pDesc)
+{
+ uint32_t wOffset;
+
+ wOffset = pInformation->Ctrl_Info.Usb_wOffset;
+ if (Length == 0)
+ {
+ pInformation->Ctrl_Info.Usb_wLength = pDesc->Descriptor_Size - wOffset;
+ return 0;
+ }
+
+ return pDesc->Descriptor + wOffset;
+}
+
+/**
+ * @brief Data stage of a Control Write Transfer.
+ */
+void DataStageOut(void)
+{
+ USB_EndpointMess* pEPinfo = &pInformation->Ctrl_Info;
+ uint32_t save_rLength;
+
+ save_rLength = pEPinfo->Usb_rLength;
+
+ if (pEPinfo->CopyData && save_rLength)
+ {
+ uint8_t* Buffer;
+ uint32_t Length;
+
+ Length = pEPinfo->PacketSize;
+ if (Length > save_rLength)
+ {
+ Length = save_rLength;
+ }
+
+ Buffer = (*pEPinfo->CopyData)(Length);
+ pEPinfo->Usb_rLength -= Length;
+ pEPinfo->Usb_rOffset += Length;
+
+ USB_CopyPMAToUserBuf(Buffer, USB_GetEpRxAddr(ENDP0), Length);
+ }
+
+ if (pEPinfo->Usb_rLength != 0)
+ {
+ vSetEPRxStatus(EP_RX_VALID); /* re-enable for next data reception */
+ USB_SetEpTxCnt(ENDP0, 0);
+ vSetEPTxStatus(EP_TX_VALID); /* Expect the host to abort the data OUT stage */
+ }
+ /* Set the next State*/
+ if (pEPinfo->Usb_rLength >= pEPinfo->PacketSize)
+ {
+ pInformation->CtrlState = OutData;
+ }
+ else
+ {
+ if (pEPinfo->Usb_rLength > 0)
+ {
+ pInformation->CtrlState = LastOutData;
+ }
+ else if (pEPinfo->Usb_rLength == 0)
+ {
+ pInformation->CtrlState = WaitStatusIn;
+ USB_StatusIn();
+ }
+ }
+}
+
+/**
+ * @brief Data stage of a Control Read Transfer.
+ */
+void DataStageIn(void)
+{
+ USB_EndpointMess* pEPinfo = &pInformation->Ctrl_Info;
+ uint32_t save_wLength = pEPinfo->Usb_wLength;
+ uint32_t CtrlState = pInformation->CtrlState;
+
+ uint8_t* DataBuffer;
+ uint32_t Length;
+
+ if ((save_wLength == 0) && (CtrlState == LastInData))
+ {
+ if (Data_Mul_MaxPacketSize == true)
+ {
+ /* No more data to send and empty packet */
+ Send0LengthData();
+ CtrlState = LastInData;
+ Data_Mul_MaxPacketSize = false;
+ }
+ else
+ {
+ /* No more data to send so STALL the TX Status*/
+ CtrlState = WaitStatusOut;
+ vSetEPTxStatus(EP_TX_STALL);
+ }
+
+ goto Expect_Status_Out;
+ }
+
+ Length = pEPinfo->PacketSize;
+ CtrlState = (save_wLength <= Length) ? LastInData : InData;
+
+ if (Length > save_wLength)
+ {
+ Length = save_wLength;
+ }
+
+ DataBuffer = (*pEPinfo->CopyData)(Length);
+
+ USB_CopyUserToPMABuf(DataBuffer, USB_GetEpTxAddr(ENDP0), Length);
+
+ USB_SetEpTxCnt(ENDP0, Length);
+
+ pEPinfo->Usb_wLength -= Length;
+ pEPinfo->Usb_wOffset += Length;
+ vSetEPTxStatus(EP_TX_VALID);
+
+ USB_StatusOut(); /* Expect the host to abort the data IN stage */
+
+Expect_Status_Out:
+ pInformation->CtrlState = CtrlState;
+}
+
+/**
+ * @brief Proceed the processing of setup request without data stage.
+ */
+void NoData_Setup0(void)
+{
+ USB_Result Result = UnSupport;
+ uint32_t RequestNo = pInformation->bRequest;
+ uint32_t CtrlState;
+
+ if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+ {
+ /* Device Request*/
+ /* SET_CONFIGURATION*/
+ if (RequestNo == SET_CONFIGURATION)
+ {
+ Result = Standard_SetConfiguration();
+ }
+
+ /*SET ADDRESS*/
+ else if (RequestNo == SET_ADDRESS)
+ {
+ if ((pInformation->USBwValue0 > 127) || (pInformation->USBwValue1 != 0) || (pInformation->USBwIndex != 0)
+ || (pInformation->CurrentConfiguration != 0))
+ /* Device Address should be 127 or less*/
+ {
+ CtrlState = Stalled;
+ goto exit_NoData_Setup0;
+ }
+ else
+ {
+ Result = Success;
+ }
+ }
+ /*SET FEATURE for Device*/
+ else if (RequestNo == SET_FEATURE)
+ {
+ if ((pInformation->USBwValue0 == DEVICE_REMOTE_WAKEUP) && (pInformation->USBwIndex == 0))
+ {
+ Result = Standard_SetDeviceFeature();
+ }
+ else
+ {
+ Result = UnSupport;
+ }
+ }
+ /*Clear FEATURE for Device */
+ else if (RequestNo == CLR_FEATURE)
+ {
+ if (pInformation->USBwValue0 == DEVICE_REMOTE_WAKEUP && pInformation->USBwIndex == 0
+ && ValBit(pInformation->CurrentFeature, 5))
+ {
+ Result = Standard_ClearFeature();
+ }
+ else
+ {
+ Result = UnSupport;
+ }
+ }
+ }
+
+ /* Interface Request*/
+ else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
+ {
+ /*SET INTERFACE*/
+ if (RequestNo == SET_INTERFACE)
+ {
+ Result = Standard_SetInterface();
+ }
+ }
+
+ /* EndPoint Request*/
+ else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+ {
+ /*CLEAR FEATURE for EndPoint*/
+ if (RequestNo == CLR_FEATURE)
+ {
+ Result = Standard_ClearFeature();
+ }
+ /* SET FEATURE for EndPoint*/
+ else if (RequestNo == SET_FEATURE)
+ {
+ Result = Standard_SetEndPointFeature();
+ }
+ }
+ else
+ {
+ Result = UnSupport;
+ }
+
+ if (Result != Success)
+ {
+ Result = (*pProperty->Class_NoData_Setup)(RequestNo);
+ if (Result == Not_Ready)
+ {
+ CtrlState = Pause;
+ goto exit_NoData_Setup0;
+ }
+ }
+
+ if (Result != Success)
+ {
+ CtrlState = Stalled;
+ goto exit_NoData_Setup0;
+ }
+
+ CtrlState = WaitStatusIn; /* After no data stage SETUP */
+
+ USB_StatusIn();
+
+exit_NoData_Setup0:
+ pInformation->CtrlState = CtrlState;
+ return;
+}
+
+/**
+ * @brief Proceed the processing of setup request with data stage.
+ */
+void Data_Setup0(void)
+{
+ uint8_t* (*CopyRoutine)(uint16_t);
+ USB_Result Result;
+ uint32_t Request_No = pInformation->bRequest;
+
+ uint32_t Related_Endpoint, Reserved;
+ uint32_t wOffset, Status;
+
+ CopyRoutine = NULL;
+ wOffset = 0;
+
+ /*GET DESCRIPTOR*/
+ if (Request_No == GET_DESCRIPTOR)
+ {
+ if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+ {
+ uint8_t wValue1 = pInformation->USBwValue1;
+ if (wValue1 == DEVICE_DESCRIPTOR)
+ {
+ CopyRoutine = pProperty->GetDeviceDescriptor;
+ }
+ else if (wValue1 == CONFIG_DESCRIPTOR)
+ {
+ CopyRoutine = pProperty->GetConfigDescriptor;
+ }
+ else if (wValue1 == STRING_DESCRIPTOR)
+ {
+ CopyRoutine = pProperty->GetStringDescriptor;
+ } /* End of GET_DESCRIPTOR */
+ }
+ }
+
+ /*GET STATUS*/
+ else if ((Request_No == GET_STATUS) && (pInformation->USBwValue == 0) && (pInformation->USBwLength == 0x0002)
+ && (pInformation->USBwIndex1 == 0))
+ {
+ /* GET STATUS for Device*/
+ if ((Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)) && (pInformation->USBwIndex == 0))
+ {
+ CopyRoutine = Standard_GetStatus;
+ }
+
+ /* GET STATUS for Interface*/
+ else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
+ {
+ if (((*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, 0) == Success)
+ && (pInformation->CurrentConfiguration != 0))
+ {
+ CopyRoutine = Standard_GetStatus;
+ }
+ }
+
+ /* GET STATUS for EndPoint*/
+ else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+ {
+ Related_Endpoint = (pInformation->USBwIndex0 & 0x0f);
+ Reserved = pInformation->USBwIndex0 & 0x70;
+
+ if (ValBit(pInformation->USBwIndex0, 7))
+ {
+ /*Get Status of endpoint & stall the request if the related_ENdpoint
+ is Disabled*/
+ Status = _GetEPTxStatus(Related_Endpoint);
+ }
+ else
+ {
+ Status = _GetEPRxStatus(Related_Endpoint);
+ }
+
+ if ((Related_Endpoint < Device_Table.TotalEndpoint) && (Reserved == 0) && (Status != 0))
+ {
+ CopyRoutine = Standard_GetStatus;
+ }
+ }
+ }
+
+ /*GET CONFIGURATION*/
+ else if (Request_No == GET_CONFIGURATION)
+ {
+ if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+ {
+ CopyRoutine = Standard_GetConfiguration;
+ }
+ }
+ /*GET INTERFACE*/
+ else if (Request_No == GET_INTERFACE)
+ {
+ if ((Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT)) && (pInformation->CurrentConfiguration != 0)
+ && (pInformation->USBwValue == 0) && (pInformation->USBwIndex1 == 0) && (pInformation->USBwLength == 0x0001)
+ && ((*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, 0) == Success))
+ {
+ CopyRoutine = Standard_GetInterface;
+ }
+ }
+
+ if (CopyRoutine)
+ {
+ pInformation->Ctrl_Info.Usb_wOffset = wOffset;
+ pInformation->Ctrl_Info.CopyData = CopyRoutine;
+ /* sb in the original the cast to word was directly */
+ /* now the cast is made step by step */
+ (*CopyRoutine)(0);
+ Result = Success;
+ }
+ else
+ {
+ Result = (*pProperty->Class_Data_Setup)(pInformation->bRequest);
+ if (Result == Not_Ready)
+ {
+ pInformation->CtrlState = Pause;
+ return;
+ }
+ }
+
+ if (pInformation->Ctrl_Info.Usb_wLength == 0xFFFF)
+ {
+ /* Data is not ready, wait it */
+ pInformation->CtrlState = Pause;
+ return;
+ }
+ if ((Result == UnSupport) || (pInformation->Ctrl_Info.Usb_wLength == 0))
+ {
+ /* Unsupported request */
+ pInformation->CtrlState = Stalled;
+ return;
+ }
+
+ if (ValBit(pInformation->bmRequestType, 7))
+ {
+ /* Device ==> Host */
+ __IO uint32_t wLength = pInformation->USBwLength;
+
+ /* Restrict the data length to be the one host asks for */
+ if (pInformation->Ctrl_Info.Usb_wLength > wLength)
+ {
+ pInformation->Ctrl_Info.Usb_wLength = wLength;
+ }
+
+ else if (pInformation->Ctrl_Info.Usb_wLength < pInformation->USBwLength)
+ {
+ if (pInformation->Ctrl_Info.Usb_wLength < pProperty->MaxPacketSize)
+ {
+ Data_Mul_MaxPacketSize = false;
+ }
+ else if ((pInformation->Ctrl_Info.Usb_wLength % pProperty->MaxPacketSize) == 0)
+ {
+ Data_Mul_MaxPacketSize = true;
+ }
+ }
+
+ pInformation->Ctrl_Info.PacketSize = pProperty->MaxPacketSize;
+ DataStageIn();
+ }
+ else
+ {
+ pInformation->CtrlState = OutData;
+ vSetEPRxStatus(EP_RX_VALID); /* enable for next data reception */
+ }
+
+ return;
+}
+
+/**
+ * @brief Get the device request data and dispatch to individual process.
+ * @return USB_ProcessPost0.
+ */
+uint8_t USB_ProcessSetup0(void)
+{
+ union
+ {
+ uint8_t* b;
+ uint16_t* w;
+ } pBuf;
+
+ uint16_t offset = 1;
+
+ pBuf.b = PMAAddr + (uint8_t*)(_GetEPRxAddr(ENDP0) * 2); /* *2 for 32 bits addr */
+
+ if (pInformation->CtrlState != Pause)
+ {
+ pInformation->bmRequestType = *pBuf.b++; /* bmRequestType */
+ pInformation->bRequest = *pBuf.b++; /* bRequest */
+ pBuf.w += offset; /* word not accessed because of 32 bits addressing */
+ pInformation->USBwValue = USB_ByteSwap(*pBuf.w++); /* wValue */
+ pBuf.w += offset; /* word not accessed because of 32 bits addressing */
+ pInformation->USBwIndex = USB_ByteSwap(*pBuf.w++); /* wIndex */
+ pBuf.w += offset; /* word not accessed because of 32 bits addressing */
+ pInformation->USBwLength = *pBuf.w; /* wLength */
+ }
+
+ pInformation->CtrlState = SettingUp;
+ if (pInformation->USBwLength == 0)
+ {
+ /* Setup with no data stage */
+ NoData_Setup0();
+ }
+ else
+ {
+ /* Setup with data stage */
+ Data_Setup0();
+ }
+ return USB_ProcessPost0();
+}
+
+/**
+ * @brief Process the IN token on all default endpoint.
+ * @return USB_ProcessPost0.
+ */
+uint8_t USB_ProcessIn0(void)
+{
+ uint32_t CtrlState = pInformation->CtrlState;
+
+ if ((CtrlState == InData) || (CtrlState == LastInData))
+ {
+ DataStageIn();
+ /* CtrlState may be changed outside the function */
+ CtrlState = pInformation->CtrlState;
+ }
+
+ else if (CtrlState == WaitStatusIn)
+ {
+ if ((pInformation->bRequest == SET_ADDRESS) && (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)))
+ {
+ USB_SetDeviceAddress(pInformation->USBwValue0);
+ pUser_Standard_Requests->User_SetDeviceAddress();
+ }
+ (*pProperty->Process_Status_IN)();
+ CtrlState = Stalled;
+ }
+
+ else
+ {
+ CtrlState = Stalled;
+ }
+
+ pInformation->CtrlState = CtrlState;
+
+ return USB_ProcessPost0();
+}
+
+/**
+ * @brief Process the OUT token on all default endpoint.
+ * @return USB_ProcessPost0.
+ */
+uint8_t USB_ProcessOut0(void)
+{
+ uint32_t CtrlState = pInformation->CtrlState;
+
+ if ((CtrlState == InData) || (CtrlState == LastInData))
+ {
+ /* host aborts the transfer before finish */
+ CtrlState = Stalled;
+ }
+ else if ((CtrlState == OutData) || (CtrlState == LastOutData))
+ {
+ DataStageOut();
+ CtrlState = pInformation->CtrlState; /* may be changed outside the function */
+ }
+
+ else if (CtrlState == WaitStatusOut)
+ {
+ (*pProperty->Process_Status_OUT)();
+ CtrlState = Stalled;
+ }
+
+ /* Unexpect state, STALL the endpoint */
+ else
+ {
+ CtrlState = Stalled;
+ }
+
+ pInformation->CtrlState = CtrlState;
+
+ return USB_ProcessPost0();
+}
+
+/**
+ * @brief Stall the Endpoint 0 in case of error.
+ * @return
+ * - 0 if the control State is in Pause
+ * - 1 if not.
+ */
+uint8_t USB_ProcessPost0(void)
+{
+ USB_SetEpRxCnt(ENDP0, Device_Property.MaxPacketSize);
+
+ if (pInformation->CtrlState == Stalled)
+ {
+ vSetEPRxStatus(EP_RX_STALL);
+ vSetEPTxStatus(EP_TX_STALL);
+ }
+ return (pInformation->CtrlState == Pause);
+}
+
+/**
+ * @brief Set the device and all the used Endpoints addresses.
+ * @param Val device address.
+ */
+void USB_SetDeviceAddress(uint8_t Val)
+{
+ uint32_t i;
+ uint32_t nEP = Device_Table.TotalEndpoint;
+
+ /* set address in every used endpoint */
+ for (i = 0; i < nEP; i++)
+ {
+ _SetEPAddress((uint8_t)i, (uint8_t)i);
+ } /* for */
+ _SetDADDR(Val | ADDR_EFUC); /* set device address and enable function */
+}
+
+/**
+ * @brief No operation function.
+ */
+void USB_ProcessNop(void)
+{
+}
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_init.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_init.c
new file mode 100644
index 0000000000..a274b60657
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_init.c
@@ -0,0 +1,71 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_init.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "usb_lib.h"
+
+/* The number of current endpoint, it will be used to specify an endpoint */
+uint8_t EPindex;
+/* The number of current device, it is an index to the Device_Table */
+/* uint8_t Device_no; */
+/* Points to the USB_DeviceMess structure of current device */
+/* The purpose of this register is to speed up the execution */
+USB_DeviceMess* pInformation;
+/* Points to the DEVICE_PROP structure of current device */
+/* The purpose of this register is to speed up the execution */
+DEVICE_PROP* pProperty;
+/* Temporary save the state of Rx & Tx status. */
+/* Whenever the Rx or Tx state is changed, its value is saved */
+/* in this variable first and will be set to the EPRB or EPRA */
+/* at the end of interrupt process */
+uint16_t SaveState;
+uint16_t wInterrupt_Mask;
+USB_DeviceMess Device_Info;
+USER_STANDARD_REQUESTS* pUser_Standard_Requests;
+
+/**
+ * @brief USB system initialization
+ */
+void USB_Init(void)
+{
+ pInformation = &Device_Info;
+ pInformation->CtrlState = 2;
+ pProperty = &Device_Property;
+ pUser_Standard_Requests = &User_Standard_Requests;
+ /* Initialize devices one by one */
+ pProperty->Init();
+ /*Pull up DP*/
+// _ClrDPCtrl();
+ _EnPortPullup();
+// printf("DP_CTRL=%x\r\n", (*DP_CTRL));
+}
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_int.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_int.c
new file mode 100644
index 0000000000..933ed45f29
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_int.c
@@ -0,0 +1,179 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_int.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "usb_lib.h"
+
+__IO uint16_t SaveRState;
+__IO uint16_t SaveTState;
+
+extern void (*pEpInt_IN[7])(void); /* Handles IN interrupts */
+extern void (*pEpInt_OUT[7])(void); /* Handles OUT interrupts */
+
+/**
+ * @brief Low priority Endpoint Correct Transfer interrupt's service routine.
+ */
+void USB_CorrectTransferLp(void)
+{
+ __IO uint16_t wEPVal = 0;
+ /* stay in loop while pending interrupts */
+ while (((wIstr = _GetISTR()) & STS_CTRS) != 0)
+ {
+ /* extract highest priority endpoint number */
+ EPindex = (uint8_t)(wIstr & STS_EP_ID);
+ if (EPindex == 0)
+ {
+ /* Decode and service control endpoint interrupt */
+ /* calling related service routine */
+ /* (USB_ProcessSetup0, USB_ProcessIn0, USB_ProcessOut0) */
+
+ /* save RX & TX status */
+ /* and set both to NAK */
+
+ SaveRState = _GetENDPOINT(ENDP0);
+ SaveTState = SaveRState & EPTX_STS;
+ SaveRState &= EPRX_STS;
+ _SetEPRxTxStatus(ENDP0, EP_RX_NAK, EP_TX_NAK);
+
+ /* DIR bit = origin of the interrupt */
+
+ if ((wIstr & STS_DIR) == 0)
+ {
+ /* DIR = 0 */
+
+ /* DIR = 0 => IN int */
+ /* DIR = 0 implies that (EP_CTRS_TX = 1) always */
+
+ _ClearEP_CTR_TX(ENDP0);
+ USB_ProcessIn0();
+
+ /* before terminate set Tx & Rx status */
+
+ _SetEPRxTxStatus(ENDP0, SaveRState, SaveTState);
+ return;
+ }
+ else
+ {
+ /* DIR = 1 */
+
+ /* DIR = 1 & CTR_RX => SETUP or OUT int */
+ /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
+
+ wEPVal = _GetENDPOINT(ENDP0);
+
+ if ((wEPVal & EP_SETUP) != 0)
+ {
+ _ClearEP_CTR_RX(ENDP0); /* SETUP bit kept frozen while CTR_RX = 1 */
+ USB_ProcessSetup0();
+ /* before terminate set Tx & Rx status */
+
+ _SetEPRxTxStatus(ENDP0, SaveRState, SaveTState);
+ return;
+ }
+
+ else if ((wEPVal & EP_CTRS_RX) != 0)
+ {
+ _ClearEP_CTR_RX(ENDP0);
+ USB_ProcessOut0();
+ /* before terminate set Tx & Rx status */
+
+ _SetEPRxTxStatus(ENDP0, SaveRState, SaveTState);
+ return;
+ }
+ }
+ } /* if (EPindex == 0) */
+ else
+ {
+ /* Decode and service non control endpoints interrupt */
+
+ /* process related endpoint register */
+ wEPVal = _GetENDPOINT(EPindex);
+ if ((wEPVal & EP_CTRS_RX) != 0)
+ {
+ /* clear int flag */
+ _ClearEP_CTR_RX(EPindex);
+
+ /* call OUT service function */
+ (*pEpInt_OUT[EPindex - 1])();
+
+ } /* if ((wEPVal & EP_CTRS_RX) */
+
+ if ((wEPVal & EP_CTRS_TX) != 0)
+ {
+ /* clear int flag */
+ _ClearEP_CTR_TX(EPindex);
+
+ /* call IN service function */
+ (*pEpInt_IN[EPindex - 1])();
+ } /* if ((wEPVal & EP_CTRS_TX) != 0) */
+
+ } /* if (EPindex == 0) else */
+
+ } /* while (...) */
+}
+
+/**
+ * @brief High Priority Endpoint Correct Transfer interrupt's service routine.
+ */
+void USB_CorrectTransferHp(void)
+{
+ uint32_t wEPVal = 0;
+
+ while (((wIstr = _GetISTR()) & STS_CTRS) != 0)
+ {
+ _SetISTR((uint16_t)CLR_CTRS); /* clear CTR flag */
+ /* extract highest priority endpoint number */
+ EPindex = (uint8_t)(wIstr & STS_EP_ID);
+ /* process related endpoint register */
+ wEPVal = _GetENDPOINT(EPindex);
+ if ((wEPVal & EP_CTRS_RX) != 0)
+ {
+ /* clear int flag */
+ _ClearEP_CTR_RX(EPindex);
+
+ /* call OUT service function */
+ (*pEpInt_OUT[EPindex - 1])();
+
+ } /* if ((wEPVal & EP_CTRS_RX) */
+ else if ((wEPVal & EP_CTRS_TX) != 0)
+ {
+ /* clear int flag */
+ _ClearEP_CTR_TX(EPindex);
+
+ /* call IN service function */
+ (*pEpInt_IN[EPindex - 1])();
+
+ } /* if ((wEPVal & EP_CTRS_TX) != 0) */
+
+ } /* while (...) */
+}
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_mem.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_mem.c
new file mode 100644
index 0000000000..02768e0307
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_mem.c
@@ -0,0 +1,81 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_mem.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "usb_lib.h"
+u8* EpOutDataPtrTmp;
+u8* EpInDataPtrTmp;
+
+/**
+ * @brief Copy a buffer from user memory area to packet memory area (PMA)
+ * @param pbUsrBuf pointer to user memory area.
+ * @param wPMABufAddr address into PMA.
+ * @param wNBytes no. of bytes to be copied.
+ */
+void USB_CopyUserToPMABuf(uint8_t* pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+ uint32_t n = (wNBytes + 1) >> 1; /* n = (wNBytes + 1) / 2 */
+ uint32_t i, temp1, temp2;
+ uint16_t* pdwVal;
+ pdwVal = (uint16_t*)(wPMABufAddr * 2 + PMAAddr);
+ for (i = n; i != 0; i--)
+ {
+ temp1 = (uint16_t)*pbUsrBuf;
+ pbUsrBuf++;
+ temp2 = temp1 | (uint16_t)*pbUsrBuf << 8;
+ *pdwVal++ = temp2;
+ pdwVal++;
+ pbUsrBuf++;
+ EpInDataPtrTmp = pbUsrBuf;
+ }
+}
+
+/**
+ * @brief Copy a buffer from user memory area to packet memory area (PMA)
+ * @param pbUsrBuf pointer to user memory area.
+ * @param wPMABufAddr address into PMA.
+ * @param wNBytes no. of bytes to be copied.
+ */
+void USB_CopyPMAToUserBuf(uint8_t* pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+ uint32_t n = (wNBytes + 1) >> 1; /* /2*/
+ uint32_t i;
+ uint32_t* pdwVal;
+ pdwVal = (uint32_t*)(wPMABufAddr * 2 + PMAAddr);
+ for (i = n; i != 0; i--)
+ {
+ *(uint16_t*)pbUsrBuf++ = *pdwVal++;
+ pbUsrBuf++;
+ EpOutDataPtrTmp = pbUsrBuf;
+ }
+}
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_regs.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_regs.c
new file mode 100644
index 0000000000..457eef62b1
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_regs.c
@@ -0,0 +1,598 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_regs.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "usb_lib.h"
+
+/**
+ * @brief Set the CTRL register value.
+ * @param wRegValue new register value.
+ */
+void USB_SetCtrl(uint16_t wRegValue)
+{
+ _SetCNTR(wRegValue);
+}
+
+/**
+ * @brief returns the CTRL register value.
+ * @return CTRL register Value.
+ */
+uint16_t USB_GetCtrl(void)
+{
+ return (_GetCNTR());
+}
+
+/**
+ * @brief Set the STS register value.
+ * @param wRegValue new register value.
+ */
+void USB_SetSts(uint16_t wRegValue)
+{
+ _SetISTR(wRegValue);
+}
+
+/**
+ * @brief Returns the STS register value.
+ * @return STS register Value
+ */
+uint16_t USB_GetSts(void)
+{
+ return (_GetISTR());
+}
+
+/**
+ * @brief Returns the FN register value.
+ * @return FN register Value
+ */
+uint16_t USB_GetFn(void)
+{
+ return (_GetFNR());
+}
+
+/**
+ * @brief Set the ADDR register value.
+ * @param wRegValue new register value.
+ */
+void USB_SetAddr(uint16_t wRegValue)
+{
+ _SetDADDR(wRegValue);
+}
+
+/**
+ * @brief Returns the ADDR register value.
+ * @return ADDR register Value
+ */
+uint16_t USB_GetAddr(void)
+{
+ return (_GetDADDR());
+}
+
+/**
+ * @brief Set the BUFTAB.
+ * @param wRegValue New register value.
+ */
+void USB_SetBuftab(uint16_t wRegValue)
+{
+ _SetBTABLE(wRegValue);
+}
+
+/**
+ * @brief Returns the BUFTAB register value.
+ * @return BUFTAB address.
+ */
+uint16_t USB_GetBTABLE(void)
+{
+ return (_GetBTABLE());
+}
+
+/**
+ * @brief Set the Endpoint register value.
+ * @param bEpNum Endpoint Number.
+ * @param wRegValue New register value.
+ */
+void USB_SetEndPoint(uint8_t bEpNum, uint16_t wRegValue)
+{
+ _SetENDPOINT(bEpNum, wRegValue);
+}
+
+/**
+ * @brief Return the Endpoint register value.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint register value.
+ */
+uint16_t USB_GetEndPoint(uint8_t bEpNum)
+{
+ return (_GetENDPOINT(bEpNum));
+}
+
+/**
+ * @brief sets the type in the endpoint register.
+ * @param bEpNum Endpoint Number.
+ * @param wType type definition.
+ */
+void USB_SetEpType(uint8_t bEpNum, uint16_t wType)
+{
+ _SetEPType(bEpNum, wType);
+}
+
+/**
+ * @brief Returns the endpoint type.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint Type
+ */
+uint16_t USB_GetEpType(uint8_t bEpNum)
+{
+ return (_GetEPType(bEpNum));
+}
+
+/**
+ * @brief Set the status of Tx endpoint.
+ * @param bEpNum Endpoint Number.
+ * @param wState new state.
+ */
+void SetEPTxStatus(uint8_t bEpNum, uint16_t wState)
+{
+ _SetEPTxStatus(bEpNum, wState);
+}
+
+/**
+ * @brief Set the status of Rx endpoint.
+ * @param bEpNum Endpoint Number.
+ * @param wState new state.
+ */
+void SetEPRxStatus(uint8_t bEpNum, uint16_t wState)
+{
+ _SetEPRxStatus(bEpNum, wState);
+}
+
+/**
+ * @brief sets the status for Double Buffer Endpoint to STALL
+ * @param bEpNum Endpoint Number.
+ * @param bDir Endpoint direction.
+ */
+void USB_SetDouBleBuferEpStall(uint8_t bEpNum, uint8_t bDir)
+{
+ uint16_t Endpoint_DTOG_Status;
+ Endpoint_DTOG_Status = USB_GetEndPoint(bEpNum);
+ if (bDir == EP_DBUF_OUT)
+ { /* OUT double buffered endpoint */
+ _SetENDPOINT(bEpNum, Endpoint_DTOG_Status & ~EPRX_DATTOG1);
+ }
+ else if (bDir == EP_DBUF_IN)
+ { /* IN double buffered endpoint */
+ _SetENDPOINT(bEpNum, Endpoint_DTOG_Status & ~EPTX_DATTOG1);
+ }
+}
+
+/**
+ * @brief Returns the endpoint Tx status.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint TX Status
+ */
+uint16_t USB_GetEpTxSts(uint8_t bEpNum)
+{
+ return (_GetEPTxStatus(bEpNum));
+}
+
+/**
+ * @brief Returns the endpoint Rx status.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint RX Status
+ */
+uint16_t USB_GetEpRxSts(uint8_t bEpNum)
+{
+ return (_GetEPRxStatus(bEpNum));
+}
+
+/**
+ * @brief Valid the endpoint Tx Status.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_SetEpTxValid(uint8_t bEpNum)
+{
+ _SetEPTxStatus(bEpNum, EP_TX_VALID);
+}
+
+/**
+ * @brief Valid the endpoint Rx Status.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_SetEpRxValid(uint8_t bEpNum)
+{
+ _SetEPRxStatus(bEpNum, EP_RX_VALID);
+}
+
+/**
+ * @brief Clear the EP_KIND bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_SetEpKind(uint8_t bEpNum)
+{
+ _SetEP_KIND(bEpNum);
+}
+
+/**
+ * @brief set the EP_KIND bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrEpKind(uint8_t bEpNum)
+{
+ _ClearEP_KIND(bEpNum);
+}
+/**
+ * @brief Clear the Status Out of the related Endpoint
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrStsOut(uint8_t bEpNum)
+{
+ _ClearEP_KIND(bEpNum);
+}
+/**
+ * @brief Set the Status Out of the related Endpoint
+ * @param bEpNum Endpoint Number.
+ */
+void USB_SetStsOut(uint8_t bEpNum)
+{
+ _SetEP_KIND(bEpNum);
+}
+/**
+ * @brief Enable the double buffer feature for the endpoint.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_SetEpDoubleBufer(uint8_t bEpNum)
+{
+ _SetEP_KIND(bEpNum);
+}
+/**
+ * @brief Disable the double buffer feature for the endpoint.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrEpDoubleBufer(uint8_t bEpNum)
+{
+ _ClearEP_KIND(bEpNum);
+}
+/**
+ * @brief Returns the Stall status of the Tx endpoint.
+ * @param bEpNum Endpoint Number.
+ * @return Tx Stall status.
+ */
+uint16_t USB_GetTxStallSts(uint8_t bEpNum)
+{
+ return (_GetTxStallStatus(bEpNum));
+}
+/**
+ * @brief Returns the Stall status of the Rx endpoint.
+ * @param bEpNum Endpoint Number.
+ * @return Rx Stall status.
+ */
+uint16_t USB_GetRxStallSts(uint8_t bEpNum)
+{
+ return (_GetRxStallStatus(bEpNum));
+}
+/**
+ * @brief Clear the CTR_RX bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrEpCtrsRx(uint8_t bEpNum)
+{
+ _ClearEP_CTR_RX(bEpNum);
+}
+/**
+ * @brief Clear the CTR_TX bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrEpCtrsTx(uint8_t bEpNum)
+{
+ _ClearEP_CTR_TX(bEpNum);
+}
+/**
+ * @brief Toggle the DTOG_RX bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_DattogRx(uint8_t bEpNum)
+{
+ _ToggleDTOG_RX(bEpNum);
+}
+/**
+ * @brief Toggle the DTOG_TX bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_DattogTx(uint8_t bEpNum)
+{
+ _ToggleDTOG_TX(bEpNum);
+}
+/**
+ * @brief Clear the DTOG_RX bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrDattogRx(uint8_t bEpNum)
+{
+ _ClearDTOG_RX(bEpNum);
+}
+/**
+ * @brief Clear the DTOG_TX bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrDattogTx(uint8_t bEpNum)
+{
+ _ClearDTOG_TX(bEpNum);
+}
+/**
+ * @brief Set the endpoint address.
+ * @param bEpNum Endpoint Number.
+ * @param bAddr New endpoint address.
+ */
+void USB_SetEpAddress(uint8_t bEpNum, uint8_t bAddr)
+{
+ _SetEPAddress(bEpNum, bAddr);
+}
+/**
+ * @brief Get the endpoint address.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint address.
+ */
+uint8_t USB_GetEpAddress(uint8_t bEpNum)
+{
+ return (_GetEPAddress(bEpNum));
+}
+/**
+ * @brief Set the endpoint Tx buffer address.
+ * @param bEpNum Endpoint Number.
+ * @param wAddr new address.
+ */
+void USB_SetEpTxAddr(uint8_t bEpNum, uint16_t wAddr)
+{
+ _SetEPTxAddr(bEpNum, wAddr);
+}
+/**
+ * @brief Set the endpoint Rx buffer address.
+ * @param bEpNum Endpoint Number.
+ * @param wAddr new address.
+ */
+void USB_SetEpRxAddr(uint8_t bEpNum, uint16_t wAddr)
+{
+ _SetEPRxAddr(bEpNum, wAddr);
+}
+/**
+ * @brief Returns the endpoint Tx buffer address.
+ * @param bEpNum Endpoint Number.
+ * @return Rx buffer address.
+ */
+uint16_t USB_GetEpTxAddr(uint8_t bEpNum)
+{
+ return (_GetEPTxAddr(bEpNum));
+}
+/**
+ * @brief Returns the endpoint Rx buffer address.
+ * @param bEpNum Endpoint Number.
+ * @return Rx buffer address.
+ */
+uint16_t USB_GetEpRxAddr(uint8_t bEpNum)
+{
+ return (_GetEPRxAddr(bEpNum));
+}
+/**
+ * @brief Set the Tx count.
+ * @param bEpNum Endpoint Number.
+ * @param wCount new count value.
+ */
+void USB_SetEpTxCnt(uint8_t bEpNum, uint16_t wCount)
+{
+ _SetEPTxCount(bEpNum, wCount);
+}
+/**
+ * @brief Set the Count Rx Register value.
+ * @param pdwReg point to the register.
+ * @param wCount the new register value.
+ */
+void USB_SetEpCntRxReg(uint32_t* pdwReg, uint16_t wCount)
+{
+ _SetEPCountRxReg(dwReg, wCount);
+}
+/**
+ * @brief Set the Rx count.
+ * @param bEpNum Endpoint Number.
+ * @param wCount the new count value.
+ */
+void USB_SetEpRxCnt(uint8_t bEpNum, uint16_t wCount)
+{
+ _SetEPRxCount(bEpNum, wCount);
+}
+/**
+ * @brief Get the Tx count.
+ * @param bEpNum Endpoint Number.
+ * @return Tx count value.
+ */
+uint16_t USB_GetEpTxCnt(uint8_t bEpNum)
+{
+ return (_GetEPTxCount(bEpNum));
+}
+/**
+ * @brief Get the Rx count.
+ * @param bEpNum Endpoint Number.
+ * @return Rx count value.
+ */
+uint16_t USB_GetEpRxCnt(uint8_t bEpNum)
+{
+ return (_GetEPRxCount(bEpNum));
+}
+/**
+ * @brief Set the addresses of the buffer 0 and 1.
+ * @param bEpNum Endpoint Number.
+ * @param wBuf0Addr new address of buffer 0.
+ * @param wBuf1Addr new address of buffer 1.
+ */
+void USB_SetEpDblBuferAddr(uint8_t bEpNum, uint16_t wBuf0Addr, uint16_t wBuf1Addr)
+{
+ _SetEPDblBuffAddr(bEpNum, wBuf0Addr, wBuf1Addr);
+}
+/**
+ * @brief Set the Buffer 1 address.
+ * @param bEpNum Endpoint Number
+ * @param wBuf0Addr new address.
+ */
+void USB_SetEpDblBuf0Addr(uint8_t bEpNum, uint16_t wBuf0Addr)
+{
+ _SetEPDblBuf0Addr(bEpNum, wBuf0Addr);
+}
+/**
+ * @brief Set the Buffer 1 address.
+ * @param bEpNum Endpoint Number
+ * @param wBuf1Addr new address.
+ */
+void USB_SetEpDblBuf1Addr(uint8_t bEpNum, uint16_t wBuf1Addr)
+{
+ _SetEPDblBuf1Addr(bEpNum, wBuf1Addr);
+}
+/**
+ * @brief Returns the address of the Buffer 0.
+ * @param bEpNum Endpoint Number.
+ */
+uint16_t USB_GetEpDblBuf0Addr(uint8_t bEpNum)
+{
+ return (_GetEPDblBuf0Addr(bEpNum));
+}
+/**
+ * @brief Returns the address of the Buffer 1.
+ * @param bEpNum Endpoint Number.
+ * @return Address of the Buffer 1.
+ */
+uint16_t USB_GetEpDblBuf1Addr(uint8_t bEpNum)
+{
+ return (_GetEPDblBuf1Addr(bEpNum));
+}
+/**
+ * @brief Set the number of bytes for a double Buffer endpoint.
+ * @param bEpNum
+ * @param bDir
+ * @param wCount
+ */
+void USB_SetEpDblBuferCnt(uint8_t bEpNum, uint8_t bDir, uint16_t wCount)
+{
+ _SetEPDblBuffCount(bEpNum, bDir, wCount);
+}
+/**
+ * @brief Set the number of bytes in the buffer 0 of a double Buffer endpoint.
+ * @param bEpNum
+ * @param bDir
+ * @param wCount
+ */
+void USB_SetEpDblBuf0Cnt(uint8_t bEpNum, uint8_t bDir, uint16_t wCount)
+{
+ _SetEPDblBuf0Count(bEpNum, bDir, wCount);
+}
+/**
+ * @brief Set the number of bytes in the buffer 0 of a double Buffer endpoint.
+ * @param bEpNum
+ * @param bDir
+ * @param wCount
+ */
+void USB_SetEpDblBuf1Cnt(uint8_t bEpNum, uint8_t bDir, uint16_t wCount)
+{
+ _SetEPDblBuf1Count(bEpNum, bDir, wCount);
+}
+/**
+ * @brief Returns the number of byte received in the buffer 0 of a double Buffer endpoint.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint Buffer 0 count
+ */
+uint16_t USB_GetEpDblBuf0Cnt(uint8_t bEpNum)
+{
+ return (_GetEPDblBuf0Count(bEpNum));
+}
+/**
+ * @brief Returns the number of data received in the buffer 1 of a double Buffer endpoint.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint Buffer 1 count.
+ */
+uint16_t USB_GetEpDblBuf1Cnt(uint8_t bEpNum)
+{
+ return (_GetEPDblBuf1Count(bEpNum));
+}
+/**
+ * @brief gets direction of the double buffered endpoint
+ * @param bEpNum Endpoint Number.
+ * @return EP_DBUF_OUT, EP_DBUF_IN, EP_DBUF_ERR if the endpoint counter not yet programmed.
+ */
+EP_DBUF_DIR GetEPDblBufDir(uint8_t bEpNum)
+{
+ if ((uint16_t)(*_pEPRxCount(bEpNum) & 0xFC00) != 0)
+ return (EP_DBUF_OUT);
+ else if (((uint16_t)(*_pEPTxCount(bEpNum)) & 0x03FF) != 0)
+ return (EP_DBUF_IN);
+ else
+ return (EP_DBUF_ERR);
+}
+/**
+ * @brief free buffer used from the application realizing it to the line toggles
+ * bit SW_BUF in the double buffered endpoint register
+ * @param bEpNum
+ * @param bDir
+ */
+void USB_FreeUserBuf(uint8_t bEpNum, uint8_t bDir)
+{
+ if (bDir == EP_DBUF_OUT)
+ { /* OUT double buffered endpoint */
+ _ToggleDTOG_TX(bEpNum);
+ }
+ else if (bDir == EP_DBUF_IN)
+ { /* IN double buffered endpoint */
+ _ToggleDTOG_RX(bEpNum);
+ }
+}
+
+/**
+ * @brief merge two byte in a word.
+ * @param bh byte high
+ * @param bl bytes low.
+ * @return resulted word.
+ */
+uint16_t USB_ToWord(uint8_t bh, uint8_t bl)
+{
+ uint16_t wRet;
+ wRet = (uint16_t)bl | ((uint16_t)bh << 8);
+ return (wRet);
+}
+/**
+ * @brief Swap two byte in a word.
+ * @param wSwW word to Swap.
+ * @return resulted word.
+ */
+uint16_t USB_ByteSwap(uint16_t wSwW)
+{
+ uint8_t bTemp;
+ uint16_t wRet;
+ bTemp = (uint8_t)(wSwW & 0xff);
+ wRet = (wSwW >> 8) | ((uint16_t)bTemp << 8);
+ return (wRet);
+}
diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_sil.c b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_sil.c
new file mode 100644
index 0000000000..0cea2761dd
--- /dev/null
+++ b/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_sil.c
@@ -0,0 +1,83 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_sil.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "usb_lib.h"
+
+/**
+ * @brief Initialize the USB Device IP and the Endpoint 0.
+ * @return Status.
+ */
+uint32_t USB_SilInit(void)
+{
+ /* USB interrupts initialization */
+ /* clear pending interrupts */
+ _SetISTR(0);
+ wInterrupt_Mask = IMR_MSK;
+ /* set interrupts mask */
+ _SetCNTR(wInterrupt_Mask);
+ return 0;
+}
+
+/**
+ * @brief Write a buffer of data to a selected endpoint.
+ * @param bEpAddr The address of the non control endpoint.
+ * @param pBufferPointer The pointer to the buffer of data to be written to the endpoint.
+ * @param wBufferSize Number of data to be written (in bytes).
+ * @return Status.
+ */
+uint32_t USB_SilWrite(uint8_t bEpAddr, uint8_t* pBufferPointer, uint32_t wBufferSize)
+{
+ /* Use the memory interface function to write to the selected endpoint */
+ USB_CopyUserToPMABuf(pBufferPointer, USB_GetEpTxAddr(bEpAddr & 0x7F), wBufferSize);
+ /* Update the data length in the control register */
+ USB_SetEpTxCnt((bEpAddr & 0x7F), wBufferSize);
+ return 0;
+}
+
+/**
+ * @brief Write a buffer of data to a selected endpoint.
+ * @param bEpAddr The address of the non control endpoint.
+ * @param pBufferPointer The pointer to which will be saved the received data buffer.
+ * @return Number of received data (in Bytes).
+ */
+uint32_t USB_SilRead(uint8_t bEpAddr, uint8_t* pBufferPointer)
+{
+ uint32_t DataLength = 0;
+ /* Get the number of received data on the selected Endpoint */
+ DataLength = USB_GetEpRxCnt(bEpAddr & 0x7F);
+ /* Use the memory interface function to write to the selected endpoint */
+ USB_CopyPMAToUserBuf(pBufferPointer, USB_GetEpRxAddr(bEpAddr & 0x7F), DataLength);
+ /* Return the number of received data */
+ return DataLength;
+}
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/arm_common_tables.h b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/arm_common_tables.h
new file mode 100644
index 0000000000..dfea7460e9
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/arm_common_tables.h
@@ -0,0 +1,121 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_common_tables.h
+ * Description: Extern declaration for common tables
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
+#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
+#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
+#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
+#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
+#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
+#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
+#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /* ARM_COMMON_TABLES_H */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/arm_const_structs.h b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/arm_const_structs.h
new file mode 100644
index 0000000000..80a3e8bbe7
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/arm_const_structs.h
@@ -0,0 +1,66 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_const_structs.h
+ * Description: Constant structs that are initialized for user convenience.
+ * For example, some can be given as arguments to the arm_cfft_f32() function.
+ *
+ * $Date: 27. January 2017
+ * $Revision: V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/arm_math.h b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/arm_math.h
new file mode 100644
index 0000000000..d6b5b2b1ce
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/arm_math.h
@@ -0,0 +1,7157 @@
+/******************************************************************************
+ * @file arm_math.h
+ * @brief Public header file for CMSIS DSP LibraryU
+ * @version V1.5.3
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ \mainpage CMSIS DSP Software Library
+ *
+ * Introduction
+ * ------------
+ *
+ * This user manual describes the CMSIS DSP software library,
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.
+ *
+ * The library is divided into a number of functions each covering a specific category:
+ * - Basic math functions
+ * - Fast math functions
+ * - Complex math functions
+ * - Filters
+ * - Matrix functions
+ * - Transforms
+ * - Motor control functions
+ * - Statistical functions
+ * - Support functions
+ * - Interpolation functions
+ *
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+ * 32-bit integer and 32-bit floating-point values.
+ *
+ * Using the Library
+ * ------------
+ *
+ * The library installer contains prebuilt versions of the libraries in the Lib folder.
+ * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)
+ * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)
+ * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)
+ * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)
+ * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)
+ * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)
+ * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)
+ * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)
+ * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)
+ * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)
+ * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)
+ * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)
+ * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)
+ * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)
+ * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian)
+ * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian)
+ * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit)
+ * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions)
+ * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
+ *
+ * The library functions are declared in the public file arm_math.h which is placed in the Include folder.
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+ * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+ * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or
+ * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+ * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
+ * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions.
+ *
+ *
+ * Examples
+ * --------
+ *
+ * The library ships with a number of examples which demonstrate how to use the library functions.
+ *
+ * Toolchain Support
+ * ------------
+ *
+ * The library has been developed and tested with MDK version 5.14.0.0
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+ *
+ * Building the Library
+ * ------------
+ *
+ * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP_Lib\\Source\\ARM folder.
+ * - arm_cortexM_math.uvprojx
+ *
+ *
+ * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above.
+ *
+ * Preprocessor Macros
+ * ------------
+ *
+ * Each library project have different preprocessor macros.
+ *
+ * - UNALIGNED_SUPPORT_DISABLE:
+ *
+ * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+ *
+ * - ARM_MATH_BIG_ENDIAN:
+ *
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+ *
+ * - ARM_MATH_MATRIX_CHECK:
+ *
+ * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+ *
+ * - ARM_MATH_ROUNDING:
+ *
+ * Define macro ARM_MATH_ROUNDING for rounding on support functions
+ *
+ * - ARM_MATH_CMx:
+ *
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+ * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+ * ARM_MATH_CM7 for building the library on cortex-M7.
+ *
+ * - ARM_MATH_ARMV8MxL:
+ *
+ * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library
+ * on Armv8-M Mainline target.
+ *
+ * - __FPU_PRESENT:
+ *
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries.
+ *
+ * - __DSP_PRESENT:
+ *
+ * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions.
+ *
+ *
+ * CMSIS-DSP in ARM::CMSIS Pack
+ * -----------------------------
+ *
+ * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories:
+ * |File/Folder |Content |
+ * |------------------------------|------------------------------------------------------------------------|
+ * |\b CMSIS\\Documentation\\DSP | This documentation |
+ * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) |
+ * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions |
+ * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library |
+ *
+ *
+ * Revision History of CMSIS-DSP
+ * ------------
+ * Please refer to \ref ChangeLog_pg.
+ *
+ * Copyright Notice
+ * ------------
+ *
+ * Copyright (C) 2010-2015 Arm Limited. All rights reserved.
+ */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures. For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ *
+ * typedef struct
+ * {
+ * uint16_t numRows; // number of rows of the matrix.
+ * uint16_t numCols; // number of columns of the matrix.
+ * float32_t *pData; // points to the data of the matrix.
+ * } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data. The array is of size numRows X numCols
+ * and the values are arranged in row order. That is, the
+ * matrix element (i, j) is stored at:
+ *
+ * pData[i*numCols + j]
+ *
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function arm_mat_init_f32(), arm_mat_init_q31()
+ * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure. For example:
+ *
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns
+ * specifies the number of columns, and pData points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices. For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns. If the size check fails the functions return:
+ *
+ * ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return
+ *
+ * ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ *
+ * ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined
+ * and size checking is enabled. By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster. With size checking disabled the functions always
+ * return ARM_MATH_SUCCESS.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+/* Compiler specific diagnostic adjustment */
+#if defined ( __CC_ARM )
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+#elif defined ( __ICCARM__ )
+
+#elif defined ( __TI_ARM__ )
+
+#elif defined ( __CSMC__ )
+
+#elif defined ( __TASKING__ )
+
+#else
+ #error Unknown compiler
+#endif
+
+
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+ #include "core_cm7.h"
+ #define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM4)
+ #include "core_cm4.h"
+ #define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM3)
+ #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+ #include "core_cm0.h"
+ #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+ #include "core_cm0plus.h"
+ #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MBL)
+ #include "core_armv8mbl.h"
+ #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MML)
+ #include "core_armv8mml.h"
+ #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1))
+ #define ARM_MATH_DSP
+ #endif
+#else
+ #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML"
+#endif
+
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+ /**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31 (0x100)
+#define DELTA_Q15 0x5
+#define INDEX_MASK 0x0000003F
+#ifndef PI
+ #define PI 3.14159265358979f
+#endif
+
+ /**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define FAST_MATH_TABLE_SIZE 512
+#define FAST_MATH_Q31_SHIFT (32 - 10)
+#define FAST_MATH_Q15_SHIFT (16 - 10)
+#define CONTROLLER_Q31_SHIFT (32 - 9)
+#define TABLE_SPACING_Q31 0x400000
+#define TABLE_SPACING_Q15 0x80
+
+ /**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+ /* 1.31(q31) Fixed value of 2/360 */
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING 0xB60B61
+
+ /**
+ * @brief Macro for Unaligned Support
+ */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+ #define ALIGN4
+#else
+ #if defined (__GNUC__)
+ #define ALIGN4 __attribute__((aligned(4)))
+ #else
+ #define ALIGN4 __align(4)
+ #endif
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /**
+ * @brief Error status returned by some functions in the library.
+ */
+
+ typedef enum
+ {
+ ARM_MATH_SUCCESS = 0, /**< No error */
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
+ } arm_status;
+
+ /**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+ typedef int8_t q7_t;
+
+ /**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+ typedef int16_t q15_t;
+
+ /**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+ typedef int32_t q31_t;
+
+ /**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+ typedef int64_t q63_t;
+
+ /**
+ * @brief 32-bit floating-point type definition.
+ */
+ typedef float float32_t;
+
+ /**
+ * @brief 64-bit floating-point type definition.
+ */
+ typedef double float64_t;
+
+ /**
+ * @brief definition to read/write two 16 bit values.
+ */
+#if defined ( __CC_ARM )
+ #define __SIMD32_TYPE int32_t __packed
+ #define CMSIS_UNUSED __attribute__((unused))
+ #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED __attribute__((unused))
+ #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __GNUC__ )
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED __attribute__((unused))
+ #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ICCARM__ )
+ #define __SIMD32_TYPE int32_t __packed
+ #define CMSIS_UNUSED
+ #define CMSIS_INLINE
+
+#elif defined ( __TI_ARM__ )
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED __attribute__((unused))
+ #define CMSIS_INLINE
+
+#elif defined ( __CSMC__ )
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED
+ #define CMSIS_INLINE
+
+#elif defined ( __TASKING__ )
+ #define __SIMD32_TYPE __unaligned int32_t
+ #define CMSIS_UNUSED
+ #define CMSIS_INLINE
+
+#else
+ #error Unknown compiler
+#endif
+
+#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))
+#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))
+#define __SIMD64(addr) (*(int64_t **) & (addr))
+
+#if !defined (ARM_MATH_DSP)
+ /**
+ * @brief definition to pack two 16 bit values.
+ */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
+
+#endif /* !defined (ARM_MATH_DSP) */
+
+ /**
+ * @brief definition to pack four 8 bit values.
+ */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
+
+#endif
+
+
+ /**
+ * @brief Clips Q63 to Q31 values.
+ */
+ CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+ }
+
+ /**
+ * @brief Clips Q63 to Q15 values.
+ */
+ CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+ }
+
+ /**
+ * @brief Clips Q31 to Q7 values.
+ */
+ CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+ }
+
+ /**
+ * @brief Clips Q31 to Q15 values.
+ */
+ CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+ }
+
+ /**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+
+ CMSIS_INLINE __STATIC_INLINE q63_t mult32x64(
+ q63_t x,
+ q31_t y)
+ {
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+ (((q63_t) (x >> 32) * y)));
+ }
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+ */
+
+ CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31(
+ q31_t in,
+ q31_t * dst,
+ q31_t * pRecipTable)
+ {
+ q31_t out;
+ uint32_t tempVal;
+ uint32_t index, i;
+ uint32_t signBits;
+
+ if (in > 0)
+ {
+ signBits = ((uint32_t) (__CLZ( in) - 1));
+ }
+ else
+ {
+ signBits = ((uint32_t) (__CLZ(-in) - 1));
+ }
+
+ /* Convert input sample to 1.31 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 24);
+ index = (index & INDEX_MASK);
+
+ /* 1.31 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0U; i < 2U; i++)
+ {
+ tempVal = (uint32_t) (((q63_t) in * out) >> 31);
+ tempVal = 0x7FFFFFFFu - tempVal;
+ /* 1.31 with exp 1 */
+ /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
+ out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1U);
+ }
+
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15(
+ q15_t in,
+ q15_t * dst,
+ q15_t * pRecipTable)
+ {
+ q15_t out = 0;
+ uint32_t tempVal = 0;
+ uint32_t index = 0, i = 0;
+ uint32_t signBits = 0;
+
+ if (in > 0)
+ {
+ signBits = ((uint32_t)(__CLZ( in) - 17));
+ }
+ else
+ {
+ signBits = ((uint32_t)(__CLZ(-in) - 17));
+ }
+
+ /* Convert input sample to 1.15 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 8);
+ index = (index & INDEX_MASK);
+
+ /* 1.15 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0U; i < 2U; i++)
+ {
+ tempVal = (uint32_t) (((q31_t) in * out) >> 15);
+ tempVal = 0x7FFFu - tempVal;
+ /* 1.15 with exp 1 */
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);
+ /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1);
+ }
+
+
+/*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+#if !defined (ARM_MATH_DSP)
+
+ /*
+ * @brief C custom defined QADD8 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB8 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */
+ q31_t r = 0, s = 0;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHADD16 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB16 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSUB16 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QASX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHASX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSAX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSAX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSDX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+ /*
+ * @brief C custom defined SMUADX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined QADD for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE int32_t __QADD(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE int32_t __QSUB(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined SMLAD for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLADX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLSDX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALD for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALDX for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUAD for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSD for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SXTB16 for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16(
+ uint32_t x)
+ {
+ return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
+ ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) ));
+ }
+
+ /*
+ * @brief C custom defined SMMLA for M3 and M0 processors
+ */
+ CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA(
+ int32_t x,
+ int32_t y,
+ int32_t sum)
+ {
+ return (sum + (int32_t) (((int64_t) x * y) >> 32));
+ }
+
+#endif /* !defined (ARM_MATH_DSP) */
+
+
+ /**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q7;
+
+ /**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] S points to an instance of the Q7 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q7(
+ const arm_fir_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 FIR filter.
+ * @param[in,out] S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ */
+ void arm_fir_init_q7(
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] S points to an instance of the Q15 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR filter.
+ * @param[in,out] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+ * numTaps is not a supported value.
+ */
+ arm_status arm_fir_init_q15(
+ arm_fir_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] S points to an instance of the Q31 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR filter.
+ * @param[in,out] S points to an instance of the Q31 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_q31(
+ arm_fir_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] S points to an instance of the floating-point FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_f32(
+ const arm_fir_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_f32(
+ arm_fir_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q15;
+
+ /**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q31;
+
+ /**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_casd_df1_inst_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float32_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f32;
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float64_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f64;
+
+ /**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q15_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q31_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q31;
+
+
+ /**
+ * @brief Floating-point matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Q31, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+
+ /**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+
+ /**
+ * @brief Q31 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix scaling.
+ * @param[in] pSrc points to the input matrix
+ * @param[in] scale scale factor
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_q31(
+ arm_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t * pData);
+
+
+ /**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_q15(
+ arm_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t * pData);
+
+
+ /**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_f32(
+ arm_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t * pData);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+ typedef struct
+ {
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+#if !defined (ARM_MATH_DSP)
+ q15_t A1;
+ q15_t A2;
+#else
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+ q15_t state[3]; /**< The state array of length 3. */
+ q15_t Kp; /**< The proportional gain. */
+ q15_t Ki; /**< The integral gain. */
+ q15_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+ typedef struct
+ {
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ q31_t A2; /**< The derived gain, A2 = Kd . */
+ q31_t state[3]; /**< The state array of length 3. */
+ q31_t Kp; /**< The proportional gain. */
+ q31_t Ki; /**< The integral gain. */
+ q31_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+ typedef struct
+ {
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ float32_t A2; /**< The derived gain, A2 = Kd . */
+ float32_t state[3]; /**< The state array of length 3. */
+ float32_t Kp; /**< The proportional gain. */
+ float32_t Ki; /**< The integral gain. */
+ float32_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_f32;
+
+
+
+ /**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ */
+ void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S);
+
+
+ /**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ */
+
+ void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S);
+
+
+ /**
+ * @brief Initialization function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the q15 PID Control structure
+ */
+ void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S);
+
+
+ /**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+ typedef struct
+ {
+ uint32_t nValues; /**< nValues */
+ float32_t x1; /**< x1 */
+ float32_t xSpacing; /**< xSpacing */
+ float32_t *pYData; /**< pointer to the table of Y values */
+ } arm_linear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ float32_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q31_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q15_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q7_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q7;
+
+
+ /**
+ * @brief Q7 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q15(
+ arm_cfft_radix2_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q31(
+ arm_cfft_radix2_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q31(
+ const arm_cfft_radix2_instance_q31 * S,
+ q31_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+ void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc);
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_f32(
+ const arm_cfft_radix2_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q15_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_q15;
+
+void arm_cfft_q15(
+ const arm_cfft_instance_q15 * S,
+ q15_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_q31;
+
+void arm_cfft_q31(
+ const arm_cfft_instance_q31 * S,
+ q31_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_f32;
+
+ void arm_cfft_f32(
+ const arm_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q15;
+
+ arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst);
+
+ /**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q31;
+
+ arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint16_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_f32;
+
+ arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_f32(
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+typedef struct
+ {
+ arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
+ uint16_t fftLenRFFT; /**< length of the real sequence */
+ float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
+ } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+ arm_rfft_fast_instance_f32 * S,
+ uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+ arm_rfft_fast_instance_f32 * S,
+ float32_t * p, float32_t * pOut,
+ uint8_t ifftFlag);
+
+ /**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ float32_t normalize; /**< normalizing factor. */
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ float32_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.
+ */
+ arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize);
+
+
+ /**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q31_t normalize; /**< normalizing factor. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ q31_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q31;
+
+
+ /**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31 * S,
+ arm_rfft_instance_q31 * S_RFFT,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q31 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q15_t normalize; /**< normalizing factor. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ q15_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15 * S,
+ arm_rfft_instance_q15 * S_RFFT,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q15 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer);
+
+
+ /**
+ * @brief Floating-point vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_f32(
+ float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q7(
+ q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q15(
+ q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q31(
+ q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result);
+
+
+ /**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result);
+
+
+ /**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q7(
+ q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q15(
+ q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q31(
+ q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_f32(
+ float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q7(
+ q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q15(
+ q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q31(
+ q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point FIR decimator.
+ * @param[in] S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR decimator.
+ * @param[in,out] S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+ arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+ arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q31(
+ arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+ arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+ } arm_fir_interpolate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+ arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+ arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+ arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
+ } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+ /**
+ * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f64;
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f32(
+ const arm_biquad_cascade_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_stereo_df2T_f32(
+ const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f64(
+ const arm_biquad_cascade_df2T_instance_f64 * S,
+ float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_stereo_df2T_init_f32(
+ arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f64(
+ arm_biquad_cascade_df2T_instance_f64 * S,
+ uint8_t numStages,
+ float64_t * pCoeffs,
+ float64_t * pState);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pkCoeffs,
+ float32_t * pvCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pkCoeffs,
+ q31_t * pvCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ */
+ void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pkCoeffs,
+ q15_t * pvCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that controls filter coefficient updates. */
+ } arm_lms_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_init_f32(
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q15(
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q15(
+ const arm_lms_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q31(
+ const arm_lms_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q31(
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that control filter coefficient updates. */
+ float32_t energy; /**< saves previous frame energy. */
+ float32_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q31_t *recipTable; /**< points to the reciprocal initial value table. */
+ q31_t energy; /**< saves previous frame energy. */
+ q31_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< Number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q15_t *recipTable; /**< Points to the reciprocal initial value table. */
+ q15_t energy; /**< saves previous frame energy. */
+ q15_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q15;
+
+
+ /**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+ void arm_correlate_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+ void arm_correlate_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+ void arm_correlate_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+ void arm_correlate_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_correlate_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q7;
+
+
+ /**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cos output.
+ */
+ void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCosVal);
+
+
+ /**
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cosine output.
+ */
+ void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal);
+
+
+ /**
+ * @brief Floating-point complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * S points to an instance of the PID control data structure. in
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ *
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ * A0 = Kp + Ki + Kd
+ * A1 = (-Kp ) - (2 * Kd )
+ * A2 = Kd
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ */
+ CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32(
+ arm_pid_instance_f32 * S,
+ float32_t in)
+ {
+ float32_t out;
+
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
+ out = (S->A0 * in) +
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @brief Process function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+ CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31(
+ arm_pid_instance_q31 * S,
+ q31_t in)
+ {
+ q63_t acc;
+ q31_t out;
+
+ /* acc = A0 * x[n] */
+ acc = (q63_t) S->A0 * in;
+
+ /* acc += A1 * x[n-1] */
+ acc += (q63_t) S->A1 * S->state[0];
+
+ /* acc += A2 * x[n-2] */
+ acc += (q63_t) S->A2 * S->state[1];
+
+ /* convert output to 1.31 format to add y[n-1] */
+ out = (q31_t) (acc >> 31U);
+
+ /* out += y[n-1] */
+ out += S->state[2];
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+
+ /**
+ * @brief Process function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+ CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15(
+ arm_pid_instance_q15 * S,
+ q15_t in)
+ {
+ q63_t acc;
+ q15_t out;
+
+#if defined (ARM_MATH_DSP)
+ __SIMD32_TYPE *vstate;
+
+ /* Implementation of PID controller */
+
+ /* acc = A0 * x[n] */
+ acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ vstate = __SIMD32_CONST(S->state);
+ acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);
+#else
+ /* acc = A0 * x[n] */
+ acc = ((q31_t) S->A0) * in;
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc += (q31_t) S->A1 * S->state[0];
+ acc += (q31_t) S->A2 * S->state[1];
+#endif
+
+ /* acc += y[n-1] */
+ acc += (q31_t) S->state[2] << 15;
+
+ /* saturate the output */
+ out = (q15_t) (__SSAT((acc >> 15), 16));
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+ /**
+ * @} end of PID group
+ */
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f32(
+ const arm_matrix_instance_f32 * src,
+ arm_matrix_instance_f32 * dst);
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f64(
+ const arm_matrix_instance_f64 * src,
+ arm_matrix_instance_f64 * dst);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents
+ * in the two-phase orthogonal stator axis Ialpha and Ibeta.
+ * When Ialpha is superposed with Ia as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta
+ * can be calculated using only Ia and Ib.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where Ia and Ib are the instantaneous stator phases and
+ * pIalpha and pIbeta are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup clarke
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point Clarke transform
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32(
+ float32_t Ia,
+ float32_t Ib,
+ float32_t * pIalpha,
+ float32_t * pIbeta)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+ }
+
+
+ /**
+ * @brief Clarke transform for Q31 version
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31(
+ q31_t Ia,
+ q31_t Ib,
+ q31_t * pIalpha,
+ q31_t * pIbeta)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+ /* pIbeta is calculated by adding the intermediate products */
+ *pIbeta = __QADD(product1, product2);
+ }
+
+ /**
+ * @} end of clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q31(
+ q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where pIa and pIb are the instantaneous stator phases and
+ * Ialpha and Ibeta are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Clarke transform
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] pIa points to output three-phase coordinate a
+ * @param[out] pIb points to output three-phase coordinate b
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pIa,
+ float32_t * pIb)
+ {
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+ *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
+ }
+
+
+ /**
+ * @brief Inverse Clarke transform for Q31 version
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] pIa points to output three-phase coordinate a
+ * @param[out] pIb points to output three-phase coordinate b
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pIa,
+ q31_t * pIb)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+ /* pIb is calculated by subtracting the products */
+ *pIb = __QSUB(product2, product1);
+ }
+
+ /**
+ * @} end of inv_clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q15(
+ q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where Ialpha and Ibeta are the stator vector components,
+ * pId and pIq are rotor vector components and cosVal and sinVal are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Park transform
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_park_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pId,
+ float32_t * pIq,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+ *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+ }
+
+
+ /**
+ * @brief Park transform for Q31 version
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_park_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pId,
+ q31_t * pIq,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Ialpha * cosVal) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * sinVal) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Ialpha * sinVal) */
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * cosVal) */
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+ /* Calculate pId by adding the two intermediate products 1 and 2 */
+ *pId = __QADD(product1, product2);
+
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+ *pIq = __QSUB(product4, product3);
+ }
+
+ /**
+ * @} end of park group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q7_to_float(
+ q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where pIalpha and pIbeta are the stator vector components,
+ * Id and Iq are rotor vector components and cosVal and sinVal are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Park transform
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32(
+ float32_t Id,
+ float32_t Iq,
+ float32_t * pIalpha,
+ float32_t * pIbeta,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+ *pIalpha = Id * cosVal - Iq * sinVal;
+
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+ *pIbeta = Id * sinVal + Iq * cosVal;
+ }
+
+
+ /**
+ * @brief Inverse Park transform for Q31 version
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31(
+ q31_t Id,
+ q31_t Iq,
+ q31_t * pIalpha,
+ q31_t * pIbeta,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Id * cosVal) */
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * sinVal) */
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Id * sinVal) */
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * cosVal) */
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+ *pIalpha = __QSUB(product1, product2);
+
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+ *pIbeta = __QADD(product4, product3);
+ }
+
+ /**
+ * @} end of Inverse park group
+ */
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_float(
+ q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ *
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ * where x0, x1 are nearest values of input x
+ * y0, y1 are nearest values to output y
+ *
+ *
+ * \par
+ * This set of functions implements Linear interpolation process
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
+ * sample of data and each call to the function returns a single processed value.
+ * S points to an instance of the Linear Interpolate function data structure.
+ * x is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+ /**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+ CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32(
+ arm_linear_interp_instance_f32 * S,
+ float32_t x)
+ {
+ float32_t y;
+ float32_t x0, x1; /* Nearest input values */
+ float32_t y0, y1; /* Nearest output values */
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */
+ int32_t i; /* Index variable */
+ float32_t *pYData = S->pYData; /* pointer to output table */
+
+ /* Calculation of index */
+ i = (int32_t) ((x - S->x1) / xSpacing);
+
+ if (i < 0)
+ {
+ /* Iniatilize output for below specified range as least output value of table */
+ y = pYData[0];
+ }
+ else if ((uint32_t)i >= S->nValues)
+ {
+ /* Iniatilize output for above specified range as last output value of table */
+ y = pYData[S->nValues - 1];
+ }
+ else
+ {
+ /* Calculation of nearest input values */
+ x0 = S->x1 + i * xSpacing;
+ x1 = S->x1 + (i + 1) * xSpacing;
+
+ /* Read of nearest output values */
+ y0 = pYData[i];
+ y1 = pYData[i + 1];
+
+ /* Calculation of output */
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+ }
+
+ /* returns output value */
+ return (y);
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q31 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q31 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31(
+ q31_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q31_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (q31_t)0xFFF00000) >> 20);
+
+ if (index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if (index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* shift left by 11 to keep fract in 1.31 format */
+ fract = (x & 0x000FFFFF) << 11;
+
+ /* Read two nearest output values from the index in 1.31(q31) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+ /* Convert y to 1.31 format */
+ return (y << 1U);
+ }
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q15 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15(
+ q15_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q63_t y; /* output */
+ q15_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (int32_t)0xFFF00000) >> 20);
+
+ if (index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if (index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+ y = ((q63_t) y0 * (0xFFFFF - fract));
+
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+ y += ((q63_t) y1 * (fract));
+
+ /* convert y to 1.15 format */
+ return (q15_t) (y >> 20);
+ }
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q7 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+ CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7(
+ q7_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q7_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ uint32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ if (x < 0)
+ {
+ return (pYData[0]);
+ }
+ index = (x >> 20) & 0xfff;
+
+ if (index >= (nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index and are in 1.7(q7) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+ y = ((y0 * (0xFFFFF - fract)));
+
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+ y += (y1 * fract);
+
+ /* convert y to 1.7(q7) format */
+ return (q7_t) (y >> 20);
+ }
+ }
+
+ /**
+ * @} end of LinearInterpolate group
+ */
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+ float32_t arm_sin_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q31_t arm_sin_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q15_t arm_sin_q15(
+ q15_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+ float32_t arm_cos_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q31_t arm_cos_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q15_t arm_cos_q15(
+ q15_t x);
+
+
+ /**
+ * @ingroup groupFastMath
+ */
+
+
+ /**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ *
+ * x1 = x0 - f(x0)/f'(x0)
+ *
+ * where x1 is the current estimate,
+ * x0 is the previous estimate, and
+ * f'(x0) is the derivative of f() evaluated at x0.
+ * For the square root function, the algorithm reduces to:
+ *
+ * x0 = in/2 [initial guess]
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]
+ *
+ */
+
+
+ /**
+ * @addtogroup SQRT
+ * @{
+ */
+
+ /**
+ * @brief Floating-point square root function.
+ * @param[in] in input value.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+ CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32(
+ float32_t in,
+ float32_t * pOut)
+ {
+ if (in >= 0.0f)
+ {
+
+#if (__FPU_USED == 1) && defined ( __CC_ARM )
+ *pOut = __sqrtf(in);
+#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+ *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined(__GNUC__)
+ *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
+ __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
+#else
+ *pOut = sqrtf(in);
+#endif
+
+ return (ARM_MATH_SUCCESS);
+ }
+ else
+ {
+ *pOut = 0.0f;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+ }
+
+
+ /**
+ * @brief Q31 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q31(
+ q31_t in,
+ q31_t * pOut);
+
+
+ /**
+ * @brief Q15 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q15(
+ q15_t in,
+ q15_t * pOut);
+
+ /**
+ * @} end of SQRT group
+ */
+
+
+ /**
+ * @brief floating-point Circular write function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const int32_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+
+ /**
+ * @brief floating-point Circular Read function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ int32_t * dst,
+ int32_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == (int32_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular write function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q15_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular Read function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q15_t * dst,
+ q15_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == (q15_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular write function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q7_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular Read function.
+ */
+ CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q7_t * dst,
+ q7_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == (q7_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Floating-point complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult);
+
+
+ /**
+ * @brief Q31 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult);
+
+
+ /**
+ * @brief Floating-point complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult);
+
+
+ /**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q15(
+ q15_t * pSrcCmplx,
+ q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q31(
+ q31_t * pSrcCmplx,
+ q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_f32(
+ float32_t * pSrcCmplx,
+ float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] result is output pointer
+ * @param[in] index is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * result,
+ uint32_t * index);
+
+
+ /**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[in] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q31(
+ float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q15(
+ float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q7(
+ float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q15(
+ q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q7(
+ q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_float(
+ q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q31(
+ q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q7(
+ q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function f(x, y) is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * Algorithm
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ *
+ * typedef struct
+ * {
+ * uint16_t numRows;
+ * uint16_t numCols;
+ * float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ *
+ *
+ * \par
+ * where numRows specifies the number of rows in the table;
+ * numCols specifies the number of columns in the table;
+ * and pData points to an array of size numRows*numCols values.
+ * The data table pTable is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers.
+ *
+ * \par
+ * Let (x, y) specify the desired interpolation point. Then define:
+ *
+ * XF = floor(x)
+ * YF = floor(y)
+ *
+ * \par
+ * The interpolated output point is computed as:
+ *
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ *
+ * Note that the coordinates (x, y) contain integer and fractional components.
+ * The integer components specify which portion of the table to use while the
+ * fractional components control the interpolation processor.
+ *
+ * \par
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+ */
+
+ /**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+
+ /**
+ *
+ * @brief Floating-point bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate.
+ * @param[in] Y interpolation coordinate.
+ * @return out interpolated value.
+ */
+ CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32(
+ const arm_bilinear_interp_instance_f32 * S,
+ float32_t X,
+ float32_t Y)
+ {
+ float32_t out;
+ float32_t f00, f01, f10, f11;
+ float32_t *pData = S->pData;
+ int32_t xIndex, yIndex, index;
+ float32_t xdiff, ydiff;
+ float32_t b1, b2, b3, b4;
+
+ xIndex = (int32_t) X;
+ yIndex = (int32_t) Y;
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* Calculation of index for two nearest points in X-direction */
+ index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+ /* Read two nearest points in X-direction */
+ f00 = pData[index];
+ f01 = pData[index + 1];
+
+ /* Calculation of index for two nearest points in Y-direction */
+ index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+ /* Read two nearest points in Y-direction */
+ f10 = pData[index];
+ f11 = pData[index + 1];
+
+ /* Calculation of intermediate values */
+ b1 = f00;
+ b2 = f01 - f00;
+ b3 = f10 - f00;
+ b4 = f00 - f01 - f10 + f11;
+
+ /* Calculation of fractional part in X */
+ xdiff = X - xIndex;
+
+ /* Calculation of fractional part in Y */
+ ydiff = Y - yIndex;
+
+ /* Calculation of bi-linear interpolated output */
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+ /* return to application */
+ return (out);
+ }
+
+
+ /**
+ *
+ * @brief Q31 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31(
+ arm_bilinear_interp_instance_q31 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q31_t out; /* Temporary output */
+ q31_t acc = 0; /* output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q31_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q31_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* shift left xfract by 11 to keep 1.31 format */
+ xfract = (X & 0x000FFFFF) << 11U;
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + (int32_t)nCols * (cI) ];
+ x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* shift left yfract by 11 to keep 1.31 format */
+ yfract = (Y & 0x000FFFFF) << 11U;
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ];
+ y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* Convert acc to 1.31(q31) format */
+ return ((q31_t)(acc << 2));
+ }
+
+
+ /**
+ * @brief Q15 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15(
+ arm_bilinear_interp_instance_q15 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q15_t x1, x2, y1, y2; /* Nearest output values */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ int32_t rI, cI; /* Row and column indices */
+ q15_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U);
+ acc = ((q63_t) out * (0xFFFFF - yfract));
+
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U);
+ acc += ((q63_t) out * (xfract));
+
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U);
+ acc += ((q63_t) out * (yfract));
+
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U);
+ acc += ((q63_t) out * (yfract));
+
+ /* acc is in 13.51 format and down shift acc by 36 times */
+ /* Convert out to 1.15 format */
+ return ((q15_t)(acc >> 36));
+ }
+
+
+ /**
+ * @brief Q7 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7(
+ arm_bilinear_interp_instance_q7 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q7_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q7_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+ out = ((x1 * (0xFFFFF - xfract)));
+ acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
+ out = ((x2 * (0xFFFFF - yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y1 * (0xFFFFF - xfract)));
+ acc += (((q63_t) out * (yfract)));
+
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y2 * (yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+ return ((q7_t)(acc >> 40));
+ }
+
+ /**
+ * @} end of BilinearInterpolate group
+ */
+
+
+/* SMMLAR */
+#define multAcc_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMLSR */
+#define multSub_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMULR */
+#define mult_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+/* SMMLA */
+#define multAcc_32x32_keep32(a, x, y) \
+ a += (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMLS */
+#define multSub_32x32_keep32(a, x, y) \
+ a -= (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMUL */
+#define mult_32x32_keep32(a, x, y) \
+ a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM )
+ /* Enter low optimization region - place directly above function definition */
+ #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("push") \
+ _Pragma ("O1")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+ #define LOW_OPTIMIZATION_EXIT \
+ _Pragma ("pop")
+ #else
+ #define LOW_OPTIMIZATION_EXIT
+ #endif
+
+ /* Enter low optimization region - place directly above function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __GNUC__ )
+ #define LOW_OPTIMIZATION_ENTER \
+ __attribute__(( optimize("-O1") ))
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __ICCARM__ )
+ /* Enter low optimization region - place directly above function definition */
+ #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define LOW_OPTIMIZATION_EXIT
+
+ /* Enter low optimization region - place directly above function definition */
+ #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TI_ARM__ )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __CSMC__ )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TASKING__ )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/* Compiler specific diagnostic adjustment */
+#if defined ( __CC_ARM )
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+
+#elif defined ( __ICCARM__ )
+
+#elif defined ( __TI_ARM__ )
+
+#elif defined ( __CSMC__ )
+
+#elif defined ( __TASKING__ )
+
+#else
+ #error Unknown compiler
+#endif
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_armcc.h b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_armcc.h
new file mode 100644
index 0000000000..a4c67e0268
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_armcc.h
@@ -0,0 +1,865 @@
+/**************************************************************************//**
+ * @file cmsis_armcc.h
+ * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+ #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
+ (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
+ #define __ARM_ARCH_6M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
+ #define __ARM_ARCH_7M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+ #define __ARM_ARCH_7EM__ 1
+#endif
+
+ /* __ARM_ARCH_8M_BASE__ not applicable */
+ /* __ARM_ARCH_8M_MAIN__ not applicable */
+
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE static __forceinline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __declspec(noreturn)
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT __packed struct
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION __packed union
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); */
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() do {\
+ __schedule_barrier();\
+ __isb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+ __schedule_barrier();\
+ __dsb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+ __schedule_barrier();\
+ __dmb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+ #define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+ return result;
+}
+#endif
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+#else
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+#else
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+#else
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXB(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXH(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXW(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32U) ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_armclang.h b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_armclang.h
new file mode 100644
index 0000000000..a1722f87a8
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_armclang.h
@@ -0,0 +1,1869 @@
+/**************************************************************************//**
+ * @file cmsis_armclang.h
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR() ((uint32_t)0U)
+#endif
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __set_FPSCR __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x) ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF);
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF);
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF);
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV(value) __builtin_bswap32(value)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __builtin_arm_rbit
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_compiler.h b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_compiler.h
new file mode 100644
index 0000000000..94212eb87a
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_compiler.h
@@ -0,0 +1,266 @@
+/**************************************************************************//**
+ * @file cmsis_compiler.h
+ * @brief CMSIS compiler generic header file
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include
+
+/*
+ * Arm Compiler 4/5
+ */
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+ #include
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+ #include
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed))
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed))
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __packed__
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __packed__
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __packed__
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __packed__ T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __align(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+ #include
+
+ #ifndef __ASM
+ #define __ASM _asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ // NO RETURN is automatically detected hence no warning here
+ #define __NO_RETURN
+ #endif
+ #ifndef __USED
+ #warning No compiler specific solution for __USED. __USED is ignored.
+ #define __USED
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __weak
+ #endif
+ #ifndef __PACKED
+ #define __PACKED @packed
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT @packed struct
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION @packed union
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ @packed struct T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+
+#else
+ #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_gcc.h b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_gcc.h
new file mode 100644
index 0000000000..cd374afaef
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_gcc.h
@@ -0,0 +1,2085 @@
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS compiler GCC header file
+ * @version V5.0.4
+ * @date 09. April 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+ #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_get_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ return __builtin_arm_get_fpscr();
+#else
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#endif
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ __builtin_arm_set_fpscr(fpscr);
+#else
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP() __ASM volatile ("nop")
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI() __ASM volatile ("wfi")
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE() __ASM volatile ("wfe")
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV() __ASM volatile ("sev")
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (int16_t)__builtin_bswap16(value);
+#else
+ int16_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return result;
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ __extension__ \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_iccarm.h b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_iccarm.h
new file mode 100644
index 0000000000..b82874d0e4
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_iccarm.h
@@ -0,0 +1,935 @@
+/**************************************************************************//**
+ * @file cmsis_iccarm.h
+ * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version V5.0.7
+ * @date 19. June 2018
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2018 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+ #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+ #define __ICCARM_V8 1
+#else
+ #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+ #if __ICCARM_V8
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #elif (__VER__ >= 7080000)
+ /* Needs IAR language extensions */
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #else
+ #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+ #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+ #if __ARM_ARCH == 6
+ #define __ARM_ARCH_6M__ 1
+ #elif __ARM_ARCH == 7
+ #if __ARM_FEATURE_DSP
+ #define __ARM_ARCH_7EM__ 1
+ #else
+ #define __ARM_ARCH_7M__ 1
+ #endif
+ #endif /* __ARM_ARCH */
+ #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+ !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+ #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+ #define __ARM_ARCH_6M__ 1
+ #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+ #define __ARM_ARCH_7M__ 1
+ #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+ #define __ARM_ARCH_7EM__ 1
+ #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #else
+ #error "Unknown target."
+ #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+ #define __IAR_M0_FAMILY 1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+ #define __IAR_M0_FAMILY 1
+#else
+ #define __IAR_M0_FAMILY 0
+#endif
+
+
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+
+#ifndef __NO_RETURN
+ #if __ICCARM_V8
+ #define __NO_RETURN __attribute__((__noreturn__))
+ #else
+ #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+ #endif
+#endif
+
+#ifndef __PACKED
+ #if __ICCARM_V8
+ #define __PACKED __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED __packed
+ #endif
+#endif
+
+#ifndef __PACKED_STRUCT
+ #if __ICCARM_V8
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_STRUCT __packed struct
+ #endif
+#endif
+
+#ifndef __PACKED_UNION
+ #if __ICCARM_V8
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_UNION __packed union
+ #endif
+#endif
+
+#ifndef __RESTRICT
+ #define __RESTRICT restrict//__restrict
+#endif
+
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+
+#ifndef __FORCEINLINE
+ #define __FORCEINLINE _Pragma("inline=forced")
+#endif
+
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+ return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+ *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+ return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+ *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef __USED
+ #if __ICCARM_V8
+ #define __USED __attribute__((used))
+ #else
+ #define __USED _Pragma("__root")
+ #endif
+#endif
+
+#ifndef __WEAK
+ #if __ICCARM_V8
+ #define __WEAK __attribute__((weak))
+ #else
+ #define __WEAK _Pragma("__weak")
+ #endif
+#endif
+
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+ #define __ICCARM_INTRINSICS_VERSION__ 0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+ #if defined(__CLZ)
+ #undef __CLZ
+ #endif
+ #if defined(__REVSH)
+ #undef __REVSH
+ #endif
+ #if defined(__RBIT)
+ #undef __RBIT
+ #endif
+ #if defined(__SSAT)
+ #undef __SSAT
+ #endif
+ #if defined(__USAT)
+ #undef __USAT
+ #endif
+
+ #include "iccarm_builtin.h"
+
+ #define __disable_fault_irq __iar_builtin_disable_fiq
+ #define __disable_irq __iar_builtin_disable_interrupt
+ #define __enable_fault_irq __iar_builtin_enable_fiq
+ #define __enable_irq __iar_builtin_enable_interrupt
+ #define __arm_rsr __iar_builtin_rsr
+ #define __arm_wsr __iar_builtin_wsr
+
+
+ #define __get_APSR() (__arm_rsr("APSR"))
+ #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
+ #define __get_CONTROL() (__arm_rsr("CONTROL"))
+ #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
+
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ #define __get_FPSCR() (__arm_rsr("FPSCR"))
+ #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
+ #else
+ #define __get_FPSCR() ( 0 )
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #define __get_IPSR() (__arm_rsr("IPSR"))
+ #define __get_MSP() (__arm_rsr("MSP"))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __get_MSPLIM() (0U)
+ #else
+ #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
+ #endif
+ #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
+ #define __get_PSP() (__arm_rsr("PSP"))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __get_PSPLIM() (0U)
+ #else
+ #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
+ #endif
+
+ #define __get_xPSR() (__arm_rsr("xPSR"))
+
+ #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
+ #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
+ #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
+ #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
+ #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __set_MSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
+ #endif
+ #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
+ #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __set_PSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
+ #endif
+
+ #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
+ #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
+ #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
+ #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
+ #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
+ #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
+ #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
+ #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
+ #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
+ #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
+ #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
+ #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
+ #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
+ #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __TZ_get_PSPLIM_NS() (0U)
+ #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+ #else
+ #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
+ #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+ #endif
+
+ #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
+ #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+ #define __NOP __iar_builtin_no_operation
+
+ #define __CLZ __iar_builtin_CLZ
+ #define __CLREX __iar_builtin_CLREX
+
+ #define __DMB __iar_builtin_DMB
+ #define __DSB __iar_builtin_DSB
+ #define __ISB __iar_builtin_ISB
+
+ #define __LDREXB __iar_builtin_LDREXB
+ #define __LDREXH __iar_builtin_LDREXH
+ #define __LDREXW __iar_builtin_LDREX
+
+ #define __RBIT __iar_builtin_RBIT
+ #define __REV __iar_builtin_REV
+ #define __REV16 __iar_builtin_REV16
+
+ __IAR_FT int16_t __REVSH(int16_t val)
+ {
+ return (int16_t) __iar_builtin_REVSH(val);
+ }
+
+ #define __ROR __iar_builtin_ROR
+ #define __RRX __iar_builtin_RRX
+
+ #define __SEV __iar_builtin_SEV
+
+ #if !__IAR_M0_FAMILY
+ #define __SSAT __iar_builtin_SSAT
+ #endif
+
+ #define __STREXB __iar_builtin_STREXB
+ #define __STREXH __iar_builtin_STREXH
+ #define __STREXW __iar_builtin_STREX
+
+ #if !__IAR_M0_FAMILY
+ #define __USAT __iar_builtin_USAT
+ #endif
+
+ #define __WFE __iar_builtin_WFE
+ #define __WFI __iar_builtin_WFI
+
+ #if __ARM_MEDIA__
+ #define __SADD8 __iar_builtin_SADD8
+ #define __QADD8 __iar_builtin_QADD8
+ #define __SHADD8 __iar_builtin_SHADD8
+ #define __UADD8 __iar_builtin_UADD8
+ #define __UQADD8 __iar_builtin_UQADD8
+ #define __UHADD8 __iar_builtin_UHADD8
+ #define __SSUB8 __iar_builtin_SSUB8
+ #define __QSUB8 __iar_builtin_QSUB8
+ #define __SHSUB8 __iar_builtin_SHSUB8
+ #define __USUB8 __iar_builtin_USUB8
+ #define __UQSUB8 __iar_builtin_UQSUB8
+ #define __UHSUB8 __iar_builtin_UHSUB8
+ #define __SADD16 __iar_builtin_SADD16
+ #define __QADD16 __iar_builtin_QADD16
+ #define __SHADD16 __iar_builtin_SHADD16
+ #define __UADD16 __iar_builtin_UADD16
+ #define __UQADD16 __iar_builtin_UQADD16
+ #define __UHADD16 __iar_builtin_UHADD16
+ #define __SSUB16 __iar_builtin_SSUB16
+ #define __QSUB16 __iar_builtin_QSUB16
+ #define __SHSUB16 __iar_builtin_SHSUB16
+ #define __USUB16 __iar_builtin_USUB16
+ #define __UQSUB16 __iar_builtin_UQSUB16
+ #define __UHSUB16 __iar_builtin_UHSUB16
+ #define __SASX __iar_builtin_SASX
+ #define __QASX __iar_builtin_QASX
+ #define __SHASX __iar_builtin_SHASX
+ #define __UASX __iar_builtin_UASX
+ #define __UQASX __iar_builtin_UQASX
+ #define __UHASX __iar_builtin_UHASX
+ #define __SSAX __iar_builtin_SSAX
+ #define __QSAX __iar_builtin_QSAX
+ #define __SHSAX __iar_builtin_SHSAX
+ #define __USAX __iar_builtin_USAX
+ #define __UQSAX __iar_builtin_UQSAX
+ #define __UHSAX __iar_builtin_UHSAX
+ #define __USAD8 __iar_builtin_USAD8
+ #define __USADA8 __iar_builtin_USADA8
+ #define __SSAT16 __iar_builtin_SSAT16
+ #define __USAT16 __iar_builtin_USAT16
+ #define __UXTB16 __iar_builtin_UXTB16
+ #define __UXTAB16 __iar_builtin_UXTAB16
+ #define __SXTB16 __iar_builtin_SXTB16
+ #define __SXTAB16 __iar_builtin_SXTAB16
+ #define __SMUAD __iar_builtin_SMUAD
+ #define __SMUADX __iar_builtin_SMUADX
+ #define __SMMLA __iar_builtin_SMMLA
+ #define __SMLAD __iar_builtin_SMLAD
+ #define __SMLADX __iar_builtin_SMLADX
+ #define __SMLALD __iar_builtin_SMLALD
+ #define __SMLALDX __iar_builtin_SMLALDX
+ #define __SMUSD __iar_builtin_SMUSD
+ #define __SMUSDX __iar_builtin_SMUSDX
+ #define __SMLSD __iar_builtin_SMLSD
+ #define __SMLSDX __iar_builtin_SMLSDX
+ #define __SMLSLD __iar_builtin_SMLSLD
+ #define __SMLSLDX __iar_builtin_SMLSLDX
+ #define __SEL __iar_builtin_SEL
+ #define __QADD __iar_builtin_QADD
+ #define __QSUB __iar_builtin_QSUB
+ #define __PKHBT __iar_builtin_PKHBT
+ #define __PKHTB __iar_builtin_PKHTB
+ #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #define __CLZ __cmsis_iar_clz_not_active
+ #define __SSAT __cmsis_iar_ssat_not_active
+ #define __USAT __cmsis_iar_usat_not_active
+ #define __RBIT __cmsis_iar_rbit_not_active
+ #define __get_APSR __cmsis_iar_get_APSR_not_active
+ #endif
+
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+ #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+ #endif
+
+ #ifdef __INTRINSICS_INCLUDED
+ #error intrinsics.h is already included previously!
+ #endif
+
+ #include
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #undef __CLZ
+ #undef __SSAT
+ #undef __USAT
+ #undef __RBIT
+ #undef __get_APSR
+
+ __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+ {
+ if (data == 0U) { return 32U; }
+
+ uint32_t count = 0U;
+ uint32_t mask = 0x80000000U;
+
+ while ((data & mask) == 0U)
+ {
+ count += 1U;
+ mask = mask >> 1U;
+ }
+ return count;
+ }
+
+ __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+ {
+ uint8_t sc = 31U;
+ uint32_t r = v;
+ for (v >>= 1U; v; v >>= 1U)
+ {
+ r <<= 1U;
+ r |= v & 1U;
+ sc--;
+ }
+ return (r << sc);
+ }
+
+ __STATIC_INLINE uint32_t __get_APSR(void)
+ {
+ uint32_t res;
+ __asm("MRS %0,APSR" : "=r" (res));
+ return res;
+ }
+
+ #endif
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #undef __get_FPSCR
+ #undef __set_FPSCR
+ #define __get_FPSCR() (0)
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #pragma diag_suppress=Pe940
+ #pragma diag_suppress=Pe177
+
+ #define __enable_irq __enable_interrupt
+ #define __disable_irq __disable_interrupt
+ #define __NOP __no_operation
+
+ #define __get_xPSR __get_PSR
+
+ #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+ __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+ {
+ return __LDREX((unsigned long *)ptr);
+ }
+
+ __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+ {
+ return __STREX(value, (unsigned long *)ptr);
+ }
+ #endif
+
+
+ /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+ #if (__CORTEX_M >= 0x03)
+
+ __IAR_FT uint32_t __RRX(uint32_t value)
+ {
+ uint32_t result;
+ __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
+ return(result);
+ }
+
+ __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
+ }
+
+
+ #define __enable_fault_irq __enable_fiq
+ #define __disable_fault_irq __disable_fiq
+
+
+ #endif /* (__CORTEX_M >= 0x03) */
+
+ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+ {
+ return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+ }
+
+ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+ __IAR_FT uint32_t __get_MSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,MSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_MSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR MSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __get_PSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_PSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
+ {
+ __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR PSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_SP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,SP_NS" : "=r" (res));
+ return res;
+ }
+ __IAR_FT void __TZ_set_SP_NS(uint32_t value)
+ {
+ __asm volatile("MSR SP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
+ }
+
+ #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+ __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+ {
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+ }
+
+ __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+ {
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+ }
+#endif
+
+#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+ __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+ {
+ __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+ {
+ __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+ {
+ __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+ }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+
+ __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+ {
+ __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+ {
+ __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+ {
+ __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_version.h b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_version.h
new file mode 100644
index 0000000000..660f612aa3
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_version.h
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file cmsis_version.h
+ * @brief CMSIS Core(M) Version definitions
+ * @version V5.0.2
+ * @date 19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/* CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
+#endif
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/core_cm4.h b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/core_cm4.h
new file mode 100644
index 0000000000..7d56873532
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/core_cm4.h
@@ -0,0 +1,2129 @@
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V5.0.8
+ * @date 04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M4
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (4U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000U
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/mpu_armv7.h b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/mpu_armv7.h
new file mode 100644
index 0000000000..be73de161f
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/mpu_armv7.h
@@ -0,0 +1,270 @@
+/******************************************************************************
+ * @file mpu_armv7.h
+ * @brief CMSIS MPU API for Armv7-M MPU
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+ (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
+ ((Region) & MPU_RBAR_REGION_Msk) | \
+ (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+*
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
+ ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
+ (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
+ (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
+ (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
+ ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
+ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
+ (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+ ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+* - TEX: 000b
+* - Shareable
+* - Non-cacheable
+* - Non-bufferable
+*/
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+* - TEX: 000b (if non-shareable) or 010b (if shareable)
+* - Shareable or non-shareable
+* - Non-cacheable
+* - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+* - TEX: 1BBb (reflecting outer cacheability rules)
+* - Shareable or non-shareable
+* - Cacheable or non-cacheable (reflecting inner cacheability rules)
+* - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+ uint32_t RBAR; //!< The region base address register value (RBAR)
+ uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+ __DSB();
+ __ISB();
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+ __DSB();
+ __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+ MPU->RNR = rnr;
+ MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+ MPU->RNR = rnr;
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+ uint32_t i;
+ for (i = 0U; i < len; ++i)
+ {
+ dst[i] = src[i];
+ }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+ while (cnt > MPU_TYPE_RALIASES) {
+ orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+ table += MPU_TYPE_RALIASES;
+ cnt -= MPU_TYPE_RALIASES;
+ }
+ orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/n32wb452.h b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/n32wb452.h
new file mode 100644
index 0000000000..b9d65f5293
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/n32wb452.h
@@ -0,0 +1,7723 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452.h
+ * @author Nations
+ * @version v1.0.3
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32WB452_H__
+#define __N32WB452_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup N32WB452_Library_Basic
+ * @{
+ */
+
+#if !defined USE_STDPERIPH_DRIVER
+/*
+ * Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+#define USE_STDPERIPH_DRIVER
+#endif
+
+/*
+ * In the following line adjust the value of External High Speed oscillator (HSE)
+ used in your application
+
+ Tip: To avoid modifying this file each time you need to use different HSE, you
+ can define the HSE value in your toolchain compiler preprocessor.
+ */
+#if !defined HSE_VALUE
+#define HSE_VALUE (8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+/*
+ * In the following line adjust the External High Speed oscillator (HSE) Startup
+ Timeout value
+ */
+#define HSE_STARTUP_TIMEOUT ((uint16_t)0x8000) /*!< Time out for HSE start up */
+
+#define HSI_VALUE (8000000) /*!< Value of the Internal oscillator in Hz*/
+
+#define __N32WB452_STDPERIPH_VERSION_MAIN (0x00) /*!< [31:24] main version */
+#define __N32WB452_STDPERIPH_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */
+#define __N32WB452_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __N32WB452_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
+
+/**
+ * @brief N32WB452 Standard Peripheral Library version number
+ */
+#define __N32WB452_STDPERIPH_VERSION \
+ ((__N32WB452_STDPERIPH_VERSION_MAIN << 24) | (__N32WB452_STDPERIPH_VERSION_SUB1 << 16) \
+ | (__N32WB452_STDPERIPH_VERSION_SUB2 << 8) | (__N32WB452_STDPERIPH_VERSION_RC))
+
+/*
+ * Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#ifdef N32WB452
+#define __MPU_PRESENT 1 /*!< N32WB452 devices does not provide an MPU */
+#define __FPU_PRESENT 1 /*!< FPU present */
+#endif /* N32WB452 */
+#define __NVIC_PRIO_BITS 4 /*!< N32WB452 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @brief N32WB452 Interrupt Number Definition
+ */
+typedef enum IRQn
+{
+ /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+
+ /****** N32WB452 specific Interrupt Numbers ********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_IRQn = 2, /*!< Tamper Interrupt */
+ RTC_IRQn = 3, /*!< RTC global Interrupt */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
+
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+ TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
+ TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
+ TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ RESERVE47_IRQn = 47, /*!< RESERVE47 Interrupt */
+ RESERVE48_IRQn = 48, /*!< RESERVE48 Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
+ RESERVE61_IRQn = 61, /*!< RESERVE61 global Interrupt */
+ RESERVE62_IRQn = 62, /*!< RESERVE62 interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ RESERVE67_IRQn = 67, /*!< RESERVE67 Interrupt */
+ DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global Interrupt */
+ DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global Interrupt */
+ I2C3_EV_IRQn = 70, /*!< I2C3 Event Interrupt */
+ I2C3_ER_IRQn = 71, /*!< I2C3 Error Interrupt */
+ I2C4_EV_IRQn = 72, /*!< I2C4 Event Interrupt */
+ I2C4_ER_IRQn = 73, /*!< I2C4 Error Interrupt */
+ UART6_IRQn = 74, /*!< UART6 global Interrupt */
+ UART7_IRQn = 75, /*!< UART7 global Interrupt */
+ DMA1_Channel8_IRQn = 76, /*!< DMA1 Channel 8 global Interrupt */
+ DMA2_Channel8_IRQn = 77, /*!< DMA2 Channel 8 global Interrupt */
+ DVP_IRQn = 78, /*!< DVP global Interrupt */
+ SAC_IRQn = 79, /*!< SAC global Interrupt */
+ MMU_IRQn = 80, /*!< MMU global Interrupt */
+ TSC_IRQn = 81, /*!< TSC global Interrupt */
+ RESERVE82_IRQn = 82, /*!< COMP1 & COMP2 & COMP3 global Interrupt */
+ RESERVE83_IRQn = 83, /*!< COMP4 & COMP5 & COMP6 global Interrupt */
+ RESERVE84_IRQn = 84 /*!< COMP7 global Interrupt */
+
+} IRQn_Type;
+
+#include "core_cm4.h"
+#include "system_n32wb452.h"
+#include
+#include
+
+typedef int32_t s32;
+typedef int16_t s16;
+typedef int8_t s8;
+
+typedef const int32_t sc32; /*!< Read Only */
+typedef const int16_t sc16; /*!< Read Only */
+typedef const int8_t sc8; /*!< Read Only */
+
+typedef __IO int32_t vs32;
+typedef __IO int16_t vs16;
+typedef __IO int8_t vs8;
+
+typedef __I int32_t vsc32; /*!< Read Only */
+typedef __I int16_t vsc16; /*!< Read Only */
+typedef __I int8_t vsc8; /*!< Read Only */
+
+typedef uint32_t u32;
+typedef uint16_t u16;
+typedef uint8_t u8;
+
+typedef const uint32_t uc32; /*!< Read Only */
+typedef const uint16_t uc16; /*!< Read Only */
+typedef const uint8_t uc8; /*!< Read Only */
+
+typedef __IO uint32_t vu32;
+typedef __IO uint16_t vu16;
+typedef __IO uint8_t vu8;
+
+typedef __I uint32_t vuc32; /*!< Read Only */
+typedef __I uint16_t vuc16; /*!< Read Only */
+typedef __I uint8_t vuc8; /*!< Read Only */
+typedef enum
+{
+ RESET = 0,
+ SET = !RESET
+} FlagStatus,
+ INTStatus;
+
+typedef enum
+{
+ DISABLE = 0,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/* N32WB452 Standard Peripheral Library old definitions (maintained for legacy purpose) */
+#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT
+#define HSE_Value HSE_VALUE
+#define HSI_Value HSI_VALUE
+
+/**
+ * @brief Analog to Digital Converter
+ */
+typedef struct
+{
+ __IO uint32_t STS;
+ __IO uint32_t CTRL1;
+ __IO uint32_t CTRL2;
+ __IO uint32_t SAMPT1;
+ __IO uint32_t SAMPT2;
+ __IO uint32_t JOFFSET1;
+ __IO uint32_t JOFFSET2;
+ __IO uint32_t JOFFSET3;
+ __IO uint32_t JOFFSET4;
+ __IO uint32_t WDGHIGH;
+ __IO uint32_t WDGLOW;
+ __IO uint32_t RSEQ1;
+ __IO uint32_t RSEQ2;
+ __IO uint32_t RSEQ3;
+ __IO uint32_t JSEQ;
+ __IO uint32_t JDAT1;
+ __IO uint32_t JDAT2;
+ __IO uint32_t JDAT3;
+ __IO uint32_t JDAT4;
+ __IO uint32_t DAT;
+ __IO uint32_t DIFSEL;
+ __IO uint32_t CALFACT;
+ __IO uint32_t CTRL3;
+ __IO uint32_t SAMPT3;
+} ADC_Module;
+
+/**
+ * @brief AFEC
+ */
+
+typedef struct
+{
+ __IO uint32_t TRIMR0;
+ __IO uint32_t TRIMR1;
+ __IO uint32_t TRIMR2;
+ __IO uint32_t TRIMR3;
+ __IO uint32_t TRIMR4;
+ __IO uint32_t TRIMR5;
+ __IO uint32_t TRIMR6;
+ uint32_t RESERVED0;
+ __IO uint32_t TESTR0;
+ __IO uint32_t TESTR1;
+} AFEC_Module;
+
+/**
+ * @brief Backup Registers
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0;
+ __IO uint16_t DAT1;
+ uint16_t RESERVED1;
+ __IO uint16_t DAT2;
+ uint16_t RESERVED2;
+ __IO uint16_t DAT3;
+ uint16_t RESERVED3;
+ __IO uint16_t DAT4;
+ uint16_t RESERVED4;
+ __IO uint16_t DAT5;
+ uint16_t RESERVED5;
+ __IO uint16_t DAT6;
+ uint16_t RESERVED6;
+ __IO uint16_t DAT7;
+ uint16_t RESERVED7;
+ __IO uint16_t DAT8;
+ uint16_t RESERVED8;
+ __IO uint16_t DAT9;
+ uint16_t RESERVED9;
+ __IO uint16_t DAT10;
+ uint16_t RESERVED10;
+ __IO uint16_t RESERVED;
+ uint16_t RESERVED11;
+ __IO uint16_t CTRL;
+ uint16_t RESERVED12;
+ __IO uint16_t CTRLSTS;
+ uint16_t RESERVED13[5];
+ __IO uint16_t DAT11;
+ uint16_t RESERVED14;
+ __IO uint16_t DAT12;
+ uint16_t RESERVED15;
+ __IO uint16_t DAT13;
+ uint16_t RESERVED16;
+ __IO uint16_t DAT14;
+ uint16_t RESERVED17;
+ __IO uint16_t DAT15;
+ uint16_t RESERVED18;
+ __IO uint16_t DAT16;
+ uint16_t RESERVED19;
+ __IO uint16_t DAT17;
+ uint16_t RESERVED20;
+ __IO uint16_t DAT18;
+ uint16_t RESERVED21;
+ __IO uint16_t DAT19;
+ uint16_t RESERVED22;
+ __IO uint16_t DAT20;
+ uint16_t RESERVED23;
+ __IO uint16_t DAT21;
+ uint16_t RESERVED24;
+ __IO uint16_t DAT22;
+ uint16_t RESERVED25;
+ __IO uint16_t DAT23;
+ uint16_t RESERVED26;
+ __IO uint16_t DAT24;
+ uint16_t RESERVED27;
+ __IO uint16_t DAT25;
+ uint16_t RESERVED28;
+ __IO uint16_t DAT26;
+ uint16_t RESERVED29;
+ __IO uint16_t DAT27;
+ uint16_t RESERVED30;
+ __IO uint16_t DAT28;
+ uint16_t RESERVED31;
+ __IO uint16_t DAT29;
+ uint16_t RESERVED32;
+ __IO uint16_t DAT30;
+ uint16_t RESERVED33;
+ __IO uint16_t DAT31;
+ uint16_t RESERVED34;
+ __IO uint16_t DAT32;
+ uint16_t RESERVED35;
+ __IO uint16_t DAT33;
+ uint16_t RESERVED36;
+ __IO uint16_t DAT34;
+ uint16_t RESERVED37;
+ __IO uint16_t DAT35;
+ uint16_t RESERVED38;
+ __IO uint16_t DAT36;
+ uint16_t RESERVED39;
+ __IO uint16_t DAT37;
+ uint16_t RESERVED40;
+ __IO uint16_t DAT38;
+ uint16_t RESERVED41;
+ __IO uint16_t DAT39;
+ uint16_t RESERVED42;
+ __IO uint16_t DAT40;
+ uint16_t RESERVED43;
+ __IO uint16_t DAT41;
+ uint16_t RESERVED44;
+ __IO uint16_t DAT42;
+ uint16_t RESERVED45;
+} BKP_Module;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TMI;
+ __IO uint32_t TMDT;
+ __IO uint32_t TMDL;
+ __IO uint32_t TMDH;
+} CAN_TxMailBox_Param;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RMI;
+ __IO uint32_t RMDT;
+ __IO uint32_t RMDL;
+ __IO uint32_t RMDH;
+} CAN_FIFOMailBox_Param;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1;
+ __IO uint32_t FR2;
+} CAN_FilterRegister_Param;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCTRL;
+ __IO uint32_t MSTS;
+ __IO uint32_t TSTS;
+ __IO uint32_t RFF0;
+ __IO uint32_t RFF1;
+ __IO uint32_t INTE;
+ __IO uint32_t ESTS;
+ __IO uint32_t BTIM;
+ uint32_t RESERVED0[88];
+ CAN_TxMailBox_Param sTxMailBox[3];
+ CAN_FIFOMailBox_Param sFIFOMailBox[2];
+ uint32_t RESERVED1[12];
+ __IO uint32_t FMC;
+ __IO uint32_t FM1;
+ uint32_t RESERVED2;
+ __IO uint32_t FS1;
+ uint32_t RESERVED3;
+ __IO uint32_t FFA1;
+ uint32_t RESERVED4;
+ __IO uint32_t FA1;
+ uint32_t RESERVED5[8];
+ CAN_FilterRegister_Param sFilterRegister[14];
+} CAN_Module;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t CRC32DAT; /*!< CRC data register */
+ __IO uint8_t CRC32IDAT; /*!< CRC independent data register*/
+ uint8_t RESERVED0;
+ uint16_t RESERVED1;
+ __IO uint32_t CRC32CTRL; /*!< CRC control register */
+ __IO uint32_t CRC16CTRL;
+ __IO uint8_t CRC16DAT;
+ uint8_t RESERVED2;
+ uint16_t RESERVED3;
+ __IO uint16_t CRC16D;
+ uint16_t RESERVED4;
+ __IO uint8_t LRC;
+ uint8_t RESERVED5;
+ uint16_t RESERVED6;
+} CRC_Module;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CTRL;
+ __IO uint32_t SOTTR;
+ __IO uint32_t DR12CH1;
+ __IO uint32_t DL12CH1;
+ __IO uint32_t DR8CH1;
+ __IO uint32_t DR12CH2;
+ __IO uint32_t DL12CH2;
+ __IO uint32_t DR8CH2;
+ __IO uint32_t DR12DCH;
+ __IO uint32_t DL12DCH;
+ __IO uint32_t DR8DCH;
+ __IO uint32_t DATO1;
+ __IO uint32_t DATO2;
+} DAC_Module;
+/**
+ * @brief USB
+ */
+
+typedef struct
+{
+ __IO uint32_t EP0;
+ __IO uint32_t EP1;
+ __IO uint32_t EP2;
+ __IO uint32_t EP3;
+ __IO uint32_t EP4;
+ __IO uint32_t EP5;
+ __IO uint32_t EP6;
+ __IO uint32_t EP7;
+ __IO uint32_t Reserve20h;
+ __IO uint32_t Reserve24h;
+ __IO uint32_t Reserve28h;
+ __IO uint32_t Reserve2Ch;
+ __IO uint32_t Reserve30h;
+ __IO uint32_t Reserve34h;
+ __IO uint32_t Reserve38h;
+ __IO uint32_t Reserve3Ch;
+ __IO uint32_t CTRL;
+ __IO uint32_t STS;
+ __IO uint32_t FN;
+ __IO uint32_t ADDR;
+ __IO uint32_t BUFTAB;
+} USB_Module;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t ID;
+ __IO uint32_t CTRL;
+} DBG_Module;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CHCFG;
+ __IO uint32_t TXNUM;
+ __IO uint32_t PADDR;
+ __IO uint32_t MADDR;
+ __IO uint32_t CHSEL;
+
+} DMA_ChannelType;
+
+typedef struct
+{
+ __IO uint32_t INTSTS;
+ __IO uint32_t INTCLR;
+ __IO DMA_ChannelType DMA_Channel[8];
+ __IO uint32_t CHMAPEN;
+} DMA_Module;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMASK;
+ __IO uint32_t EMASK;
+ __IO uint32_t RT_CFG;
+ __IO uint32_t FT_CFG;
+ __IO uint32_t SWIE;
+ __IO uint32_t PEND;
+ __IO uint32_t TSSEL;
+} EXTI_Module;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t AC;
+ __IO uint32_t KEY;
+ __IO uint32_t OPTKEY;
+ __IO uint32_t STS;
+ __IO uint32_t CTRL;
+ __IO uint32_t ADD;
+ __IO uint32_t RESERVED0;
+ __IO uint32_t OBR;
+ __IO uint32_t WRP;
+ __IO uint32_t RESERVED1;
+ __IO uint32_t RESERVED2;
+ __IO uint32_t RDN;
+ __IO uint32_t CAHR;
+} FLASH_Module;
+
+/**
+ * @brief Option Bytes Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t USER_RDP;
+ __IO uint32_t Data1_Data0;
+ __IO uint32_t WRP1_WRP0;
+ __IO uint32_t WRP3_WRP2;
+ __IO uint32_t RDP2;
+} OB_Module;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t PL_CFG;
+ __IO uint32_t PH_CFG;
+ __IO uint32_t PID;
+ __IO uint32_t POD;
+ __IO uint32_t PBSC;
+ __IO uint32_t PBC;
+ __IO uint32_t PLOCK_CFG;
+ uint32_t RESERVED0;
+ __IO uint32_t DS_CFG;
+ __IO uint32_t SR_CFG;
+} GPIO_Module;
+
+/**
+ * @brief Alternate Function I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t ECTRL;
+ __IO uint32_t RMP_CFG;
+ __IO uint32_t EXTI_CFG[4];
+ uint32_t RESERVED0;
+ uint32_t RESERVED1;
+ __IO uint32_t RMP_CFG3;
+ __IO uint32_t RMP_CFG4;
+ __IO uint32_t RMP_CFG5;
+} AFIO_Module;
+/**
+ * @brief Inter Integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint16_t CTRL1;
+ uint16_t RESERVED0;
+ __IO uint16_t CTRL2;
+ uint16_t RESERVED1;
+ __IO uint16_t OADDR1;
+ uint16_t RESERVED2;
+ __IO uint16_t OADDR2;
+ uint16_t RESERVED3;
+ __IO uint16_t DAT;
+ uint16_t RESERVED4;
+ __IO uint16_t STS1;
+ uint16_t RESERVED5;
+ __IO uint16_t STS2;
+ uint16_t RESERVED6;
+ __IO uint16_t CLKCTRL;
+ uint16_t RESERVED7;
+ __IO uint16_t TMRISE;
+ uint16_t RESERVED8;
+} I2C_Module;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KEY;
+ __IO uint32_t PREDIV; /*!< IWDG PREDIV */
+ __IO uint32_t RELV;
+ __IO uint32_t STS;
+} IWDG_Module;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CTRL;
+ __IO uint32_t CTRLSTS;
+ __IO uint32_t CTRL2;
+ __IO uint32_t CTRL3;
+} PWR_Module;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CTRL;
+ __IO uint32_t CFG;
+ __IO uint32_t CLKINT;
+ __IO uint32_t APB2PRST;
+ __IO uint32_t APB1PRST;
+ __IO uint32_t AHBPCLKEN;
+ __IO uint32_t APB2PCLKEN;
+ __IO uint32_t APB1PCLKEN;
+ __IO uint32_t BDCTRL;
+ __IO uint32_t CTRLSTS;
+
+ __IO uint32_t AHBPRST;
+ __IO uint32_t CFG2;
+ __IO uint32_t CFG3;
+} RCC_Module;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TSH; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DATE; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CTRL; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t INITSTS; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRE; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WKUPT; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t reserved0; /*!< Reserved */
+ __IO uint32_t ALARMA; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALARMB; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WRP; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SUBS; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SCTRL; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TST; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSD; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSS; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALIB; /*!< RTC calibration register, Address offset: 0x3C */
+ uint32_t reserved6; /*!< RTC tamper configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASS; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSS; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ __IO uint32_t OPT; /*!< RTC option register, Address offset: 0x4C */
+ uint32_t reserved1; /*!< Reserved Address offset: 0x50 */
+ uint32_t reserved2; /*!< Reserved Address offset: 0x54 */
+ uint32_t reserved3; /*!< Reserved Address offset: 0x58 */
+ uint32_t reserved4; /*!< Reserved Address offset: 0x5C */
+ uint32_t reserved5; /*!< Reserved Address offset: 0x60 */
+ __IO uint32_t TSCWKUPCTRL; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t TSCWKUPCNT; /*!< RTC backup register 6, Address offset: 0x68 */
+} RTC_Module;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t PWRCTRL;
+ __IO uint32_t CLKCTRL;
+ __IO uint32_t CMDARG;
+ __IO uint32_t CMDCTRL;
+ __I uint32_t CMDRESP;
+ __I uint32_t RESPONSE1;
+ __I uint32_t RESPONSE2;
+ __I uint32_t RESPONSE3;
+ __I uint32_t RESPONSE4;
+ __IO uint32_t DTIMER;
+ __IO uint32_t DATLEN;
+ __IO uint32_t DATCTRL;
+ __I uint32_t DATCOUNT;
+ __I uint32_t STS;
+ __IO uint32_t INTCLR;
+ __IO uint32_t INTEN;
+ uint32_t RESERVED0[2];
+ __I uint32_t FIFOCOUNT;
+ uint32_t RESERVED1[13];
+ __IO uint32_t DATFIFO;
+} SDIO_Module;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint16_t CTRL1;
+ uint16_t RESERVED0;
+ __IO uint16_t CTRL2;
+ uint16_t RESERVED1;
+ __IO uint16_t STS;
+ uint16_t RESERVED2;
+ __IO uint16_t DAT;
+ uint16_t RESERVED3;
+ __IO uint16_t CRCPOLY;
+ uint16_t RESERVED4;
+ __IO uint16_t CRCRDAT;
+ uint16_t RESERVED5;
+ __IO uint16_t CRCTDAT;
+ uint16_t RESERVED6;
+ __IO uint16_t I2SCFG;
+ uint16_t RESERVED7;
+ __IO uint16_t I2SPREDIV;
+ uint16_t RESERVED8;
+} SPI_Module;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CTRL1;
+ __IO uint32_t CTRL2;
+ __IO uint16_t SMCTRL;
+ uint16_t RESERVED1;
+ __IO uint16_t DINTEN;
+ uint16_t RESERVED2;
+ __IO uint32_t STS;
+ __IO uint16_t EVTGEN;
+ uint16_t RESERVED3;
+ __IO uint16_t CCMOD1;
+ uint16_t RESERVED4;
+ __IO uint16_t CCMOD2;
+ uint16_t RESERVED5;
+ __IO uint32_t CCEN;
+ __IO uint16_t CNT;
+ uint16_t RESERVED6;
+ __IO uint16_t PSC;
+ uint16_t RESERVED7;
+ __IO uint16_t AR;
+ uint16_t RESERVED8;
+ __IO uint16_t REPCNT;
+ uint16_t RESERVED9;
+ __IO uint16_t CCDAT1;
+ uint16_t RESERVED10;
+ __IO uint16_t CCDAT2;
+ uint16_t RESERVED11;
+ __IO uint16_t CCDAT3;
+ uint16_t RESERVED12;
+ __IO uint16_t CCDAT4;
+ uint16_t RESERVED13;
+ __IO uint16_t BKDT;
+ uint16_t RESERVED14;
+ __IO uint16_t DCTRL;
+ uint16_t RESERVED15;
+ __IO uint16_t DADDR;
+ uint16_t RESERVED16;
+ uint32_t RESERVED17;
+ __IO uint16_t CCMOD3;
+ uint16_t RESERVED18;
+ __IO uint16_t CCDAT5;
+ uint16_t RESERVED19;
+ __IO uint16_t CCDAT6;
+ uint16_t RESERVED20;
+} TIM_Module;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint16_t STS;
+ uint16_t RESERVED0;
+ __IO uint16_t DAT;
+ uint16_t RESERVED1;
+ __IO uint16_t BRCF;
+ uint16_t RESERVED2;
+ __IO uint16_t CTRL1;
+ uint16_t RESERVED3;
+ __IO uint16_t CTRL2;
+ uint16_t RESERVED4;
+ __IO uint16_t CTRL3;
+ uint16_t RESERVED5;
+ __IO uint16_t GTP;
+ uint16_t RESERVED6;
+} USART_Module;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CTRL;
+ __IO uint32_t CFG;
+ __IO uint32_t STS;
+} WWDG_Module;
+
+/**
+ * @brief Touch Sensor Controller
+ */
+typedef struct
+{
+ __IO uint32_t CTRL;
+ __IO uint32_t CHNEN;
+ __IO uint32_t STS;
+ __IO uint32_t RESERVED;
+ __IO uint32_t ANA_CTRL;
+ __IO uint32_t ANA_SEL;
+ __IO uint32_t RESR0;
+ __IO uint32_t RESR1;
+ __IO uint32_t RESR2;
+ __IO uint32_t THRHD0;
+ __IO uint32_t THRHD1;
+ __IO uint32_t THRHD2;
+ __IO uint32_t THRHD3;
+ __IO uint32_t THRHD4;
+ __IO uint32_t THRHD5;
+ __IO uint32_t THRHD6;
+ __IO uint32_t THRHD7;
+ __IO uint32_t THRHD8;
+ __IO uint32_t THRHD9;
+ __IO uint32_t THRHD10;
+ __IO uint32_t THRHD11;
+ __IO uint32_t THRHD12;
+ __IO uint32_t THRHD13;
+ __IO uint32_t THRHD14;
+ __IO uint32_t THRHD15;
+ __IO uint32_t THRHD16;
+ __IO uint32_t THRHD17;
+ __IO uint32_t THRHD18;
+ __IO uint32_t THRHD19;
+ __IO uint32_t THRHD20;
+ __IO uint32_t THRHD21;
+ __IO uint32_t THRHD22;
+ __IO uint32_t THRHD23;
+} TSC_Module;
+
+/**
+ * @brief DVP
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< DVP control register*/
+ __IO uint32_t STS; /*!< DVP status register*/
+ __IO uint32_t INTSTS; /*!< DVP interrupt status register*/
+ __IO uint32_t INTEN; /*!< DVP interrupt enable register*/
+ __IO uint32_t MINTSTS; /*!< DVP interrupt mask status register */
+ __IO uint32_t WST; /*!< DVP start register */
+ __IO uint32_t WSIZE; /*!< DVP size register */
+ __IO uint32_t FIFO; /*!< DVP FIFO register */
+} DVP_Module;
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+#define UCID_BASE ((uint32_t)0x1FFFF7C0) /*!< UCID Address : 0x1FFF_F7C0 */
+#define UCID_LENGTH ((uint32_t)0x10) /*!< UCID Length : 16Bytes */
+#define UID_BASE ((uint32_t)0x1FFFF7F0) /*!< UID Address : 0x1FFF_F7F0 */
+#define UID_LENGTH ((uint32_t)0x0C) /*!< UID Length : 12Bytes */
+#define DBGMCU_ID_BASE ((uint32_t)0xE0042000) /*!< DBGMCU_ID Address */
+#define DBGMCU_ID_LENGTH ((uint8_t)0x04) /*!< DBGMCU_ID Length : 4 Bytes */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE (PERIPH_BASE)
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x18000)
+
+/* APB1 */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
+#define AFEC_BASE (APB1PERIPH_BASE + 0x1800)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define TSC_BASE (APB1PERIPH_BASE + 0x3400)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define USB_BASE (APB1PERIPH_BASE + 0x5C00)
+#define USB_CAN1_SRAM_BASE (APB1PERIPH_BASE + 0x6000)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
+#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+
+/* APB2 */
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+#define I2C3_BASE (APB2PERIPH_BASE + 0x4400)
+#define I2C4_BASE (APB2PERIPH_BASE + 0x4800)
+#define DVP_BASE (APB2PERIPH_BASE + 0x4C00)
+#define UART6_BASE (APB2PERIPH_BASE + 0x5000)
+#define UART7_BASE (APB2PERIPH_BASE + 0x5400)
+
+/* AHB */
+#define SDIO_BASE (AHBPERIPH_BASE + 0x0000)
+#define DMA1_BASE (AHBPERIPH_BASE + 0x8000)
+#define DMA1_CH1_BASE (AHBPERIPH_BASE + 0x8008)
+#define DMA1_CH2_BASE (AHBPERIPH_BASE + 0x801C)
+#define DMA1_CH3_BASE (AHBPERIPH_BASE + 0x8030)
+#define DMA1_CH4_BASE (AHBPERIPH_BASE + 0x8044)
+#define DMA1_CH5_BASE (AHBPERIPH_BASE + 0x8058)
+#define DMA1_CH6_BASE (AHBPERIPH_BASE + 0x806C)
+#define DMA1_CH7_BASE (AHBPERIPH_BASE + 0x8080)
+#define DMA1_CH8_BASE (AHBPERIPH_BASE + 0x8094)
+#define DMA2_BASE (AHBPERIPH_BASE + 0x8400)
+#define DMA2_CH1_BASE (AHBPERIPH_BASE + 0x8408)
+#define DMA2_CH2_BASE (AHBPERIPH_BASE + 0x841C)
+#define DMA2_CH3_BASE (AHBPERIPH_BASE + 0x8430)
+#define DMA2_CH4_BASE (AHBPERIPH_BASE + 0x8444)
+#define DMA2_CH5_BASE (AHBPERIPH_BASE + 0x8458)
+#define DMA2_CH6_BASE (AHBPERIPH_BASE + 0x846C)
+#define DMA2_CH7_BASE (AHBPERIPH_BASE + 0x8480)
+#define DMA2_CH8_BASE (AHBPERIPH_BASE + 0x8494)
+#define ADC1_BASE (AHBPERIPH_BASE + 0x8800)
+#define ADC2_BASE (AHBPERIPH_BASE + 0x8C00)
+#define RCC_BASE (AHBPERIPH_BASE + 0x9000)
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0xA000) /*!< Flash registers base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+#define CRC_BASE (AHBPERIPH_BASE + 0xB000)
+#define SAC_BASE (AHBPERIPH_BASE + 0xC000)
+#define SAC_SRAM_BASE (AHBPERIPH_BASE + 0xC400)
+#define MMU_BASE (AHBPERIPH_BASE + 0xCC00)
+
+#define DBG_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+#define TIM2 ((TIM_Module*)TIM2_BASE)
+#define TIM3 ((TIM_Module*)TIM3_BASE)
+#define TIM4 ((TIM_Module*)TIM4_BASE)
+#define TIM5 ((TIM_Module*)TIM5_BASE)
+#define TIM6 ((TIM_Module*)TIM6_BASE)
+#define TIM7 ((TIM_Module*)TIM7_BASE)
+#define AFEC ((AFEC_Module*)AFEC_BASE)
+#define RTC ((RTC_Module*)RTC_BASE)
+#define WWDG ((WWDG_Module*)WWDG_BASE)
+#define IWDG ((IWDG_Module*)IWDG_BASE)
+#define TSC ((TSC_Module*)TSC_BASE)
+#define SPI2 ((SPI_Module*)SPI2_BASE)
+#define SPI3 ((SPI_Module*)SPI3_BASE)
+#define USART2 ((USART_Module*)USART2_BASE)
+#define USART3 ((USART_Module*)USART3_BASE)
+#define UART4 ((USART_Module*)UART4_BASE)
+#define UART5 ((USART_Module*)UART5_BASE)
+#define I2C1 ((I2C_Module*)I2C1_BASE)
+#define I2C2 ((I2C_Module*)I2C2_BASE)
+#define USB ((USB_Module*)USB_BASE)
+#define CAN1 ((CAN_Module*)CAN1_BASE)
+#define CAN2 ((CAN_Module*)CAN2_BASE)
+#define BKP ((BKP_Module*)BKP_BASE)
+#define PWR ((PWR_Module*)PWR_BASE)
+#define DAC ((DAC_Module*)DAC_BASE)
+#define AFIO ((AFIO_Module*)AFIO_BASE)
+#define EXTI ((EXTI_Module*)EXTI_BASE)
+#define GPIOA ((GPIO_Module*)GPIOA_BASE)
+#define GPIOB ((GPIO_Module*)GPIOB_BASE)
+#define GPIOC ((GPIO_Module*)GPIOC_BASE)
+#define GPIOD ((GPIO_Module*)GPIOD_BASE)
+#define GPIOE ((GPIO_Module*)GPIOE_BASE)
+#define TIM1 ((TIM_Module*)TIM1_BASE)
+#define SPI1 ((SPI_Module*)SPI1_BASE)
+#define TIM8 ((TIM_Module*)TIM8_BASE)
+#define USART1 ((USART_Module*)USART1_BASE)
+#define I2C3 ((I2C_Module*)I2C3_BASE)
+#define I2C4 ((I2C_Module*)I2C4_BASE)
+#define DVP ((DVP_Module*)DVP_BASE)
+#define UART6 ((USART_Module*)UART6_BASE)
+#define UART7 ((USART_Module*)UART7_BASE)
+#define SDIO ((SDIO_Module*)SDIO_BASE)
+#define DMA1 ((DMA_Module*)DMA1_BASE)
+#define DMA2 ((DMA_Module*)DMA2_BASE)
+#define DMA1_CH1 ((DMA_ChannelType*)DMA1_CH1_BASE)
+#define DMA1_CH2 ((DMA_ChannelType*)DMA1_CH2_BASE)
+#define DMA1_CH3 ((DMA_ChannelType*)DMA1_CH3_BASE)
+#define DMA1_CH4 ((DMA_ChannelType*)DMA1_CH4_BASE)
+#define DMA1_CH5 ((DMA_ChannelType*)DMA1_CH5_BASE)
+#define DMA1_CH6 ((DMA_ChannelType*)DMA1_CH6_BASE)
+#define DMA1_CH7 ((DMA_ChannelType*)DMA1_CH7_BASE)
+#define DMA1_CH8 ((DMA_ChannelType*)DMA1_CH8_BASE)
+#define DMA2_CH1 ((DMA_ChannelType*)DMA2_CH1_BASE)
+#define DMA2_CH2 ((DMA_ChannelType*)DMA2_CH2_BASE)
+#define DMA2_CH3 ((DMA_ChannelType*)DMA2_CH3_BASE)
+#define DMA2_CH4 ((DMA_ChannelType*)DMA2_CH4_BASE)
+#define DMA2_CH5 ((DMA_ChannelType*)DMA2_CH5_BASE)
+#define DMA2_CH6 ((DMA_ChannelType*)DMA2_CH6_BASE)
+#define DMA2_CH7 ((DMA_ChannelType*)DMA2_CH7_BASE)
+#define DMA2_CH8 ((DMA_ChannelType*)DMA2_CH8_BASE)
+#define ADC1 ((ADC_Module*)ADC1_BASE)
+#define ADC2 ((ADC_Module*)ADC2_BASE)
+#define RCC ((RCC_Module*)RCC_BASE)
+#define FLASH ((FLASH_Module*)FLASH_R_BASE)
+#define OB ((OB_Module*)OB_BASE)
+#define CRC ((CRC_Module*)CRC_BASE)
+
+#define DBG ((DBG_Module*)DBG_BASE)
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRC_CRC32DAT register *********************/
+#define CRC32_DAT_DAT ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/******************* Bit definition for CRC_CRC32IDAT register ********************/
+#define CRC32_IDAT_IDAT ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CRC32CTRL register ********************/
+#define CRC32_CTRL_RESET ((uint8_t)0x01) /*!< RESET bit */
+
+/******************** Bit definition for CRC16_CR register ********************/
+#define CRC16_CTRL_LITTLE ((uint8_t)0x02)
+#define CRC16_CTRL_BIG ((uint8_t)0xFD)
+
+#define CRC16_CTRL_RESET ((uint8_t)0x04)
+#define CRC16_CTRL_NO_RESET ((uint8_t)0xFB)
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CTRL register ********************/
+#define PWR_CTRL_LPS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */
+#define PWR_CTRL_PDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */
+#define PWR_CTRL_CWKUP ((uint16_t)0x0004) /*!< Clear Wakeup Flag */
+#define PWR_CTRL_CSBVBAT ((uint16_t)0x0008) /*!< Clear Standby Flag */
+#define PWR_CTRL_PVDEN ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */
+
+#define PWR_CTRL_PRS ((uint16_t)0x00E0) /*!< PRS[2:0] bits (PVD Level Selection) */
+#define PWR_CTRL_PRS_0 ((uint16_t)0x0020) /*!< Bit 0 */
+#define PWR_CTRL_PRS_1 ((uint16_t)0x0040) /*!< Bit 1 */
+#define PWR_CTRL_PRS_2 ((uint16_t)0x0080) /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CTRL_PRS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */
+#define PWR_CTRL_PRS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */
+#define PWR_CTRL_PRS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */
+#define PWR_CTRL_PRS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */
+#define PWR_CTRL_PRS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */
+#define PWR_CTRL_PRS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */
+#define PWR_CTRL_PRS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */
+#define PWR_CTRL_PRS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */
+
+#define PWR_CTRL_DBKP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */
+#define PWR_CTRL_MSB ((uint16_t)0x0200) /*!< Bit 9 */
+
+/******************* Bit definition for PWR_CTRLSTS register ********************/
+#define PWR_CTRLSTS_WKUPF ((uint16_t)0x0001) /*!< Wakeup Flag */
+#define PWR_CTRLSTS_SBF ((uint16_t)0x0002) /*!< Standby Flag */
+#define PWR_CTRLSTS_PVDO ((uint16_t)0x0004) /*!< PVD Output */
+#define PWR_CTRLSTS_VBATF ((uint16_t)0x0008) /*!< VBAT Flag */
+#define PWR_CTRLSTS_WKUPEN ((uint16_t)0x0100) /*!< Enable WKUP pin */
+
+/******************* Bit definition for PWR_CTRL2 register ********************/
+#define PWR_CTRL2_STOP2S ((uint16_t)0x0001) /*!< Enable STOP2 */
+#define PWR_CTRL2_SR2VBRET ((uint16_t)0x0002) /*!< VBAT mode SRAM2 retention */
+#define PWR_CTRL2_SR2STBRET ((uint16_t)0x0004) /*!< Standby mode SRAM2 retention */
+#define PWR_CTRL2_TMPWPEN ((uint16_t)0x0008) /*!< Enable Tamper WakeUp */
+#define PWR_CTRL2_LSITRIM ((uint16_t)0x01F0) /*!< config the LSI trimming value */
+#define PWR_CTRL2_IWDGWPEN ((uint16_t)0x0200) /*!< Enable IWDG WakeUp */
+#define PWR_CTRL2_IWDGRSTEN ((uint16_t)0x0400) /*!< Enable IWDG RST WakeUp */
+
+/******************* Bit definition for PWR_CTRL3 register ********************/
+#define PWR_CTRL3_EXMODE ((uint16_t)0x0001) /*!< BKPM Mode */
+#define PWR_CTRL3_EXMODE_EXTEND ((uint16_t)0x0001) /*!< EXTEND Mode */
+#define PWR_CTRL3_EXMODE_NORMAL ((uint16_t)0x0000) /*!< NORMAL Mode */
+
+
+/******************************************************************************/
+/* */
+/* Backup registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for BKP_DAT1 register ********************/
+#define BKP_DAT1_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT2 register ********************/
+#define BKP_DAT2_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT3 register ********************/
+#define BKP_DAT3_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT4 register ********************/
+#define BKP_DAT4_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT5 register ********************/
+#define BKP_DAT5_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT6 register ********************/
+#define BKP_DAT6_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT7 register ********************/
+#define BKP_DAT7_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT8 register ********************/
+#define BKP_DAT8_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT9 register ********************/
+#define BKP_DAT9_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT10 register *******************/
+#define BKP_DAT10_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT11 register *******************/
+#define BKP_DAT11_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT12 register *******************/
+#define BKP_DAT12_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT13 register *******************/
+#define BKP_DAT13_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT14 register *******************/
+#define BKP_DAT14_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT15 register *******************/
+#define BKP_DAT15_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT16 register *******************/
+#define BKP_DAT16_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT17 register *******************/
+#define BKP_DAT17_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/****************** Bit definition for BKP_DAT18 register ********************/
+#define BKP_DAT18_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT19 register *******************/
+#define BKP_DAT19_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT20 register *******************/
+#define BKP_DAT20_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT21 register *******************/
+#define BKP_DAT21_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT22 register *******************/
+#define BKP_DAT22_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT23 register *******************/
+#define BKP_DAT23_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT24 register *******************/
+#define BKP_DAT24_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT25 register *******************/
+#define BKP_DAT25_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT26 register *******************/
+#define BKP_DAT26_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT27 register *******************/
+#define BKP_DAT27_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT28 register *******************/
+#define BKP_DAT28_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT29 register *******************/
+#define BKP_DAT29_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT30 register *******************/
+#define BKP_DAT30_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT31 register *******************/
+#define BKP_DAT31_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT32 register *******************/
+#define BKP_DAT32_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT33 register *******************/
+#define BKP_DAT33_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT34 register *******************/
+#define BKP_DAT34_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT35 register *******************/
+#define BKP_DAT35_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT36 register *******************/
+#define BKP_DAT36_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT37 register *******************/
+#define BKP_DAT37_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT38 register *******************/
+#define BKP_DAT38_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT39 register *******************/
+#define BKP_DAT39_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT40 register *******************/
+#define BKP_DAT40_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT41 register *******************/
+#define BKP_DAT41_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DAT42 register *******************/
+#define BKP_DAT42_DAT ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************** Bit definition for BKP_CTRL register ********************/
+#define BKP_CTRL_TP_EN ((uint8_t)0x01) /*!< TAMPER pin enable */
+#define BKP_CTRL_TP_ALEV ((uint8_t)0x02) /*!< TAMPER pin active level */
+
+/******************* Bit definition for BKP_CTRLSTS register ********************/
+#define BKP_CTRLSTS_CLRTE ((uint16_t)0x0001) /*!< Clear Tamper event */
+#define BKP_CTRLSTS_CLRTINT ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */
+#define BKP_CTRLSTS_TPINT_EN ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */
+#define BKP_CTRLSTS_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */
+#define BKP_CTRLSTS_TINTF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for RCC_CTRL register ********************/
+#define RCC_CTRL_HSIEN ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
+#define RCC_CTRL_HSIRDF ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
+#define RCC_CTRL_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
+#define RCC_CTRL_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
+#define RCC_CTRL_HSEEN ((uint32_t)0x00010000) /*!< External High Speed clock enable */
+#define RCC_CTRL_HSERDF ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
+#define RCC_CTRL_HSEBP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
+#define RCC_CTRL_CLKSSEN ((uint32_t)0x00080000) /*!< Clock Security System enable */
+#define RCC_CTRL_PLLEN ((uint32_t)0x01000000) /*!< PLL enable */
+#define RCC_CTRL_PLLRDF ((uint32_t)0x02000000) /*!< PLL clock ready flag */
+
+/******************* Bit definition for RCC_CFG register *******************/
+/*!< SW configuration */
+#define RCC_CFG_SCLKSW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFG_SCLKSW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFG_SCLKSW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFG_SCLKSW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFG_SCLKSW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFG_SCLKSW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFG_SCLKSTS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFG_SCLKSTS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFG_SCLKSTS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFG_SCLKSTS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFG_SCLKSTS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFG_SCLKSTS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFG_AHBPRES ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFG_AHBPRES_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFG_AHBPRES_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFG_AHBPRES_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFG_AHBPRES_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFG_AHBPRES_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFG_AHBPRES_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFG_AHBPRES_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFG_AHBPRES_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFG_AHBPRES_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFG_AHBPRES_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFG_AHBPRES_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFG_AHBPRES_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFG_AHBPRES_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFG_APB1PRES ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFG_APB1PRES_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_CFG_APB1PRES_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define RCC_CFG_APB1PRES_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+#define RCC_CFG_APB1PRES_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFG_APB1PRES_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFG_APB1PRES_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFG_APB1PRES_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFG_APB1PRES_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFG_APB2PRES ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFG_APB2PRES_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define RCC_CFG_APB2PRES_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+#define RCC_CFG_APB2PRES_2 ((uint32_t)0x00002000) /*!< Bit 2 */
+
+#define RCC_CFG_APB2PRES_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFG_APB2PRES_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFG_APB2PRES_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFG_APB2PRES_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFG_APB2PRES_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+/*!< PLLSRC configuration */
+#define RCC_CFG_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
+
+/*!< PLLXTPRE configuration */
+#define RCC_CFG_PLLHSEPRES ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFG_PLLMULFCT ((uint32_t)0x083C0000) /*!< PLLMUL[4:0] bits (PLL multiplication factor) */
+#define RCC_CFG_PLLMULFCT_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFG_PLLMULFCT_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define RCC_CFG_PLLMULFCT_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+#define RCC_CFG_PLLMULFCT_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+#define RCC_CFG_PLLMULFCT_4 ((uint32_t)0x08000000) /*!< Bit 4 */
+
+#define RCC_CFG_PLLSRC_HSI_DIV2 \
+ ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source \
+ */
+#define RCC_CFG_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */
+
+#define RCC_CFG_PLLHSEPRES_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
+#define RCC_CFG_PLLHSEPRES_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+#define RCC_CFG_PLLMULFCT2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFG_PLLMULFCT3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
+#define RCC_CFG_PLLMULFCT4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
+#define RCC_CFG_PLLMULFCT5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
+#define RCC_CFG_PLLMULFCT6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
+#define RCC_CFG_PLLMULFCT7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
+#define RCC_CFG_PLLMULFCT8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
+#define RCC_CFG_PLLMULFCT9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
+#define RCC_CFG_PLLMULFCT10 ((uint32_t)0x00200000) /*!< PLL input clock*10 */
+#define RCC_CFG_PLLMULFCT11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
+#define RCC_CFG_PLLMULFCT12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
+#define RCC_CFG_PLLMULFCT13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
+#define RCC_CFG_PLLMULFCT14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
+#define RCC_CFG_PLLMULFCT15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
+#define RCC_CFG_PLLMULFCT16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
+#define RCC_CFG_PLLMULFCT16N ((uint32_t)0x003C0000) /*!< PLL input clock*16 */
+#define RCC_CFG_PLLMULFCT17 ((uint32_t)0x08000000) /*!< PLL input clock*17 */
+#define RCC_CFG_PLLMULFCT18 ((uint32_t)0x08040000) /*!< PLL input clock*18 */
+#define RCC_CFG_PLLMULFCT19 ((uint32_t)0x08080000) /*!< PLL input clock*19 */
+#define RCC_CFG_PLLMULFCT20 ((uint32_t)0x080C0000) /*!< PLL input clock*20 */
+#define RCC_CFG_PLLMULFCT21 ((uint32_t)0x08100000) /*!< PLL input clock*21 */
+#define RCC_CFG_PLLMULFCT22 ((uint32_t)0x08140000) /*!< PLL input clock*22 */
+#define RCC_CFG_PLLMULFCT23 ((uint32_t)0x08180000) /*!< PLL input clock*23 */
+#define RCC_CFG_PLLMULFCT24 ((uint32_t)0x081C0000) /*!< PLL input clock*24 */
+#define RCC_CFG_PLLMULFCT25 ((uint32_t)0x08200000) /*!< PLL input clock*25 */
+#define RCC_CFG_PLLMULFCT26 ((uint32_t)0x08240000) /*!< PLL input clock*26 */
+#define RCC_CFG_PLLMULFCT27 ((uint32_t)0x08280000) /*!< PLL input clock*27 */
+#define RCC_CFG_PLLMULFCT28 ((uint32_t)0x082C0000) /*!< PLL input clock*28 */
+#define RCC_CFG_PLLMULFCT29 ((uint32_t)0x08300000) /*!< PLL input clock*29 */
+#define RCC_CFG_PLLMULFCT30 ((uint32_t)0x08340000) /*!< PLL input clock*30 */
+#define RCC_CFG_PLLMULFCT31 ((uint32_t)0x08380000) /*!< PLL input clock*31 */
+#define RCC_CFG_PLLMULFCT32 ((uint32_t)0x083C0000) /*!< PLL input clock*32 */
+
+/*!< USBPRES configuration */
+#define RCC_CFG_USBPRES ((uint32_t)0x00C00000) /*!< USB Device prescaler */
+#define RCC_CFG_USBPRES_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define RCC_CFG_USBPRES_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define RCC_CFG_USBPRES_PLLDIV1_5 ((uint32_t)0x00000000) /*!< PLL clock is divided by 1.5 */
+#define RCC_CFG_USBPRES_PLLDIV1 ((uint32_t)0x00400000) /*!< PLL clock is not divided */
+#define RCC_CFG_USBPRES_PLLDIV2 ((uint32_t)0x00800000) /*!< PLL clock is divided by 2 */
+#define RCC_CFG_USBPRES_PLLDIV3 ((uint32_t)0x00C00000) /*!< PLL clock is divided by 3 */
+
+/*!< MCO configuration */
+#define RCC_CFG_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define RCC_CFG_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define RCC_CFG_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define RCC_CFG_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define RCC_CFG_MCO_NOCLK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFG_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFG_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFG_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFG_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+
+/*!< MCOPRE configuration */
+#define RCC_CFG_MCOPRES \
+ ((uint32_t)0xF0000000) /*!< MCOPRE[3:0] bits ( PLL prescaler set and cleared by software to generate MCOPRE \
+ clock.) */
+#define RCC_CFG_MCOPRES_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define RCC_CFG_MCOPRES_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+#define RCC_CFG_MCOPRES_2 ((uint32_t)0x40000000) /*!< Bit 2 */
+#define RCC_CFG_MCOPRES_3 ((uint32_t)0x80000000) /*!< Bit 3 */
+
+#define RCC_CFG_MCOPRES_PLLDIV2 ((uint32_t)0x20000000) /*!< PLL clock is divided by 2 */
+#define RCC_CFG_MCOPRES_PLLDIV3 ((uint32_t)0x30000000) /*!< PLL clock is divided by 3 */
+#define RCC_CFG_MCOPRES_PLLDIV4 ((uint32_t)0x40000000) /*!< PLL clock is divided by 4 */
+#define RCC_CFG_MCOPRES_PLLDIV5 ((uint32_t)0x50000000) /*!< PLL clock is divided by 5 */
+#define RCC_CFG_MCOPRES_PLLDIV6 ((uint32_t)0x60000000) /*!< PLL clock is divided by 6 */
+#define RCC_CFG_MCOPRES_PLLDIV7 ((uint32_t)0x70000000) /*!< PLL clock is divided by 7 */
+#define RCC_CFG_MCOPRES_PLLDIV8 ((uint32_t)0x80000000) /*!< PLL clock is divided by 8 */
+#define RCC_CFG_MCOPRES_PLLDIV9 ((uint32_t)0x90000000) /*!< PLL clock is divided by 9 */
+#define RCC_CFG_MCOPRES_PLLDIV10 ((uint32_t)0xA0000000) /*!< PLL clock is divided by 10 */
+#define RCC_CFG_MCOPRES_PLLDIV11 ((uint32_t)0xB0000000) /*!< PLL clock is divided by 11 */
+#define RCC_CFG_MCOPRES_PLLDIV12 ((uint32_t)0xC0000000) /*!< PLL clock is divided by 12 */
+#define RCC_CFG_MCOPRES_PLLDIV13 ((uint32_t)0xD0000000) /*!< PLL clock is divided by 13 */
+#define RCC_CFG_MCOPRES_PLLDIV14 ((uint32_t)0xE0000000) /*!< PLL clock is divided by 14 */
+#define RCC_CFG_MCOPRES_PLLDIV15 ((uint32_t)0xF0000000) /*!< PLL clock is divided by 15 */
+
+/*!<****************** Bit definition for RCC_CLKINT register ********************/
+#define RCC_CLKINT_LSIRDIF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
+#define RCC_CLKINT_LSERDIF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
+#define RCC_CLKINT_HSIRDIF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
+#define RCC_CLKINT_HSERDIF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
+#define RCC_CLKINT_PLLRDIF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
+#define RCC_CLKINT_CLKSSIF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
+#define RCC_CLKINT_LSIRDIEN ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
+#define RCC_CLKINT_LSERDIEN ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
+#define RCC_CLKINT_HSIRDIEN ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
+#define RCC_CLKINT_HSERDIEN ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
+#define RCC_CLKINT_PLLRDIEN ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
+#define RCC_CLKINT_LSIRDICLR ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
+#define RCC_CLKINT_LSERDICLR ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
+#define RCC_CLKINT_HSIRDICLR ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
+#define RCC_CLKINT_HSERDICLR ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
+#define RCC_CLKINT_PLLRDICLR ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
+#define RCC_CLKINT_CLKSSICLR ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
+
+/***************** Bit definition for RCC_APB2PRST register *****************/
+#define RCC_APB2PRST_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */
+#define RCC_APB2PRST_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */
+#define RCC_APB2PRST_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */
+#define RCC_APB2PRST_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */
+#define RCC_APB2PRST_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */
+#define RCC_APB2PRST_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */
+#define RCC_APB2PRST_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */
+#define RCC_APB2PRST_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */
+#define RCC_APB2PRST_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */
+#define RCC_APB2PRST_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */
+#define RCC_APB2PRST_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */
+#define RCC_APB2PRST_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
+#define RCC_APB2PRST_DVPRST ((uint32_t)0x00010000) /*!< DVP reset */
+#define RCC_APB2PRST_UART6RST ((uint32_t)0x00020000) /*!< UART6 reset */
+#define RCC_APB2PRST_UART7RST ((uint32_t)0x00040000) /*!< UART7 reset */
+#define RCC_APB2PRST_I2C3RST ((uint32_t)0x00080000) /*!< I2C3 reset */
+#define RCC_APB2PRST_I2C4RST ((uint32_t)0x00100000) /*!< I2C4 reset */
+
+/***************** Bit definition for RCC_APB1PRST register *****************/
+#define RCC_APB1PRST_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
+#define RCC_APB1PRST_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
+#define RCC_APB1PRST_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
+#define RCC_APB1PRST_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
+#define RCC_APB1PRST_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
+#define RCC_APB1PRST_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
+#define RCC_APB1PRST_TSCRST ((uint32_t)0x00000400) /*!< TSC reset */
+#define RCC_APB1PRST_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
+#define RCC_APB1PRST_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
+#define RCC_APB1PRST_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */
+#define RCC_APB1PRST_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
+#define RCC_APB1PRST_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
+#define RCC_APB1PRST_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
+#define RCC_APB1PRST_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
+#define RCC_APB1PRST_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
+#define RCC_APB1PRST_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
+#define RCC_APB1PRST_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */
+#define RCC_APB1PRST_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */
+#define RCC_APB1PRST_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */
+#define RCC_APB1PRST_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */
+#define RCC_APB1PRST_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
+#define RCC_APB1PRST_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
+
+/****************** Bit definition for RCC_AHBPCLKEN register ******************/
+#define RCC_AHBPCLKEN_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
+#define RCC_AHBPCLKEN_DMA2EN ((uint32_t)0x00000002) /*!< DMA2 clock enable */
+#define RCC_AHBPCLKEN_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
+#define RCC_AHBPCLKEN_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
+#define RCC_AHBPCLKEN_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
+#define RCC_AHBPCLKEN_RNGCEN ((uint32_t)0x00000200) /*!< RNGC clock enable */
+#define RCC_AHBPCLKEN_SDIOEN ((uint32_t)0x00000400) /*!< SDIO clock enable */
+#define RCC_AHBPCLKEN_SACEN ((uint32_t)0x00000800) /*!< SAC clock enable */
+#define RCC_AHBPCLKEN_ADC1EN ((uint32_t)0x00001000) /*!< ADC1 clock enable */
+#define RCC_AHBPCLKEN_ADC2EN ((uint32_t)0x00002000) /*!< ADC2 clock enable */
+
+/****************** Bit definition for RCC_APB2PCLKEN register *****************/
+#define RCC_APB2PCLKEN_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */
+#define RCC_APB2PCLKEN_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */
+#define RCC_APB2PCLKEN_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */
+#define RCC_APB2PCLKEN_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */
+#define RCC_APB2PCLKEN_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */
+#define RCC_APB2PCLKEN_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */
+#define RCC_APB2PCLKEN_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */
+#define RCC_APB2PCLKEN_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */
+#define RCC_APB2PCLKEN_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */
+#define RCC_APB2PCLKEN_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
+#define RCC_APB2PCLKEN_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */
+#define RCC_APB2PCLKEN_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
+#define RCC_APB2PCLKEN_DVPEN ((uint32_t)0x00010000) /*!< DVP clock enable */
+#define RCC_APB2PCLKEN_UART6EN ((uint32_t)0x00020000) /*!< UART6 clock enable */
+#define RCC_APB2PCLKEN_UART7EN ((uint32_t)0x00040000) /*!< UART7 clock enable */
+#define RCC_APB2PCLKEN_I2C3EN ((uint32_t)0x00080000) /*!< I2C3 clock enable */
+#define RCC_APB2PCLKEN_I2C4EN ((uint32_t)0x00100000) /*!< I2C4 clock enable */
+
+/***************** Bit definition for RCC_APB1PCLKEN register ******************/
+#define RCC_APB1PCLKEN_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
+#define RCC_APB1PCLKEN_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
+#define RCC_APB1PCLKEN_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
+#define RCC_APB1PCLKEN_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */
+#define RCC_APB1PCLKEN_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
+#define RCC_APB1PCLKEN_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
+#define RCC_APB1PCLKEN_COMPEN ((uint32_t)0x00000040) /*!< COMP clock enable */
+#define RCC_APB1PCLKEN_COMPFILTEN ((uint32_t)0x00000080) /*!< COMPFILT clock enable */
+#define RCC_APB1PCLKEN_TSCEN ((uint32_t)0x00000400) /*!< TSC clock enable */
+#define RCC_APB1PCLKEN_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
+#define RCC_APB1PCLKEN_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */
+#define RCC_APB1PCLKEN_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */
+#define RCC_APB1PCLKEN_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
+#define RCC_APB1PCLKEN_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
+#define RCC_APB1PCLKEN_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
+#define RCC_APB1PCLKEN_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
+#define RCC_APB1PCLKEN_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
+#define RCC_APB1PCLKEN_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
+#define RCC_APB1PCLKEN_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */
+#define RCC_APB1PCLKEN_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */
+#define RCC_APB1PCLKEN_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */
+#define RCC_APB1PCLKEN_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */
+#define RCC_APB1PCLKEN_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
+#define RCC_APB1PCLKEN_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
+#define RCC_APB1PCLKEN_OPAMPEN ((uint32_t)0x80000000) /*!< OPAMP interface clock enable */
+
+/******************* Bit definition for RCC_BDCTRL register *******************/
+#define RCC_BDCTRL_LSEEN ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
+#define RCC_BDCTRL_LSERD ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
+#define RCC_BDCTRL_LSEBP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCTRL_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCTRL_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_BDCTRL_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< RTC congiguration */
+#define RCC_BDCTRL_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCTRL_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCTRL_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCTRL_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_BDCTRL_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
+#define RCC_BDCTRL_BDSFTRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
+
+/******************* Bit definition for RCC_CTRLSTS register ********************/
+#define RCC_CTRLSTS_LSIEN ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
+#define RCC_CTRLSTS_LSIRD ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
+#define RCC_CTRLSTS_BORRSTF ((uint32_t)0x00080000) /*!< BOR reset flag */
+#define RCC_CTRLSTS_RETEMCF ((uint32_t)0x00100000) /*!< RET_EMC reset flag */
+#define RCC_CTRLSTS_BKPEMCF ((uint32_t)0x00200000) /*!< BKP_EMC reset flag */
+#define RCC_CTRLSTS_RAMRSTF ((uint32_t)0x00800000) /*!< RAM reset flag */
+#define RCC_CTRLSTS_RMRSTF ((uint32_t)0x01000000) /*!< Remove reset flag */
+#define RCC_CTRLSTS_MMURSTF ((uint32_t)0x02000000) /*!< MMU reset flag */
+#define RCC_CTRLSTS_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
+#define RCC_CTRLSTS_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
+#define RCC_CTRLSTS_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
+#define RCC_CTRLSTS_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
+#define RCC_CTRLSTS_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
+#define RCC_CTRLSTS_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
+
+/******************* Bit definition for RCC_AHBPRST register ****************/
+#define RCC_AHBRST_RNGCRST ((uint32_t)0x00000200) /*!< RNGC reset */
+#define RCC_AHBRST_SACRST ((uint32_t)0x00000800) /*!< SAC reset */
+#define RCC_AHBRST_ADC1RST ((uint32_t)0x00001000) /*!< ADC1 reset */
+#define RCC_AHBRST_ADC2RST ((uint32_t)0x00002000) /*!< ADC2 reset */
+
+/******************* Bit definition for RCC_CFG2 register ******************/
+/*!< ADCHPRE configuration */
+#define RCC_CFG2_ADCHPRES ((uint32_t)0x0000000F) /*!< ADCHPRE[3:0] bits */
+#define RCC_CFG2_ADCHPRES_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFG2_ADCHPRES_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RCC_CFG2_ADCHPRES_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RCC_CFG2_ADCHPRES_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define RCC_CFG2_ADCHPRES_DIV1 ((uint32_t)0x00000000) /*!< HCLK clock divided by 1 */
+#define RCC_CFG2_ADCHPRES_DIV2 ((uint32_t)0x00000001) /*!< HCLK clock divided by 2 */
+#define RCC_CFG2_ADCHPRES_DIV4 ((uint32_t)0x00000002) /*!< HCLK clock divided by 4 */
+#define RCC_CFG2_ADCHPRES_DIV6 ((uint32_t)0x00000003) /*!< HCLK clock divided by 6 */
+#define RCC_CFG2_ADCHPRES_DIV8 ((uint32_t)0x00000004) /*!< HCLK clock divided by 8 */
+#define RCC_CFG2_ADCHPRES_DIV10 ((uint32_t)0x00000005) /*!< HCLK clock divided by 10 */
+#define RCC_CFG2_ADCHPRES_DIV12 ((uint32_t)0x00000006) /*!< HCLK clock divided by 12 */
+#define RCC_CFG2_ADCHPRES_DIV16 ((uint32_t)0x00000007) /*!< HCLK clock divided by 16 */
+#define RCC_CFG2_ADCHPRES_DIV32 ((uint32_t)0x00000008) /*!< HCLK clock divided by 32 */
+#define RCC_CFG2_ADCHPRES_OTHERS ((uint32_t)0x00000008) /*!< HCLK clock divided by 32 */
+
+/*!< ADCPLLPRES configuration */
+#define RCC_CFG2_ADCPLLPRES ((uint32_t)0x000001F0) /*!< ADCPLLPRES[4:0] bits */
+#define RCC_CFG2_ADCPLLPRES_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFG2_ADCPLLPRES_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFG2_ADCPLLPRES_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFG2_ADCPLLPRES_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+#define RCC_CFG2_ADCPLLPRES_4 ((uint32_t)0x00000100) /*!< Bit 4 */
+
+#define RCC_CFG2_ADCPLLCLK_DISABLE ((uint32_t)0xFFFFFEFF) /*!< ADC PLL clock Disable */
+#define RCC_CFG2_ADCPLLPRES_DIV1 ((uint32_t)0x00000100) /*!< PLL clock divided by 1 */
+#define RCC_CFG2_ADCPLLPRES_DIV2 ((uint32_t)0x00000110) /*!< PLL clock divided by 2 */
+#define RCC_CFG2_ADCPLLPRES_DIV4 ((uint32_t)0x00000120) /*!< PLL clock divided by 4 */
+#define RCC_CFG2_ADCPLLPRES_DIV6 ((uint32_t)0x00000130) /*!< PLL clock divided by 6 */
+#define RCC_CFG2_ADCPLLPRES_DIV8 ((uint32_t)0x00000140) /*!< PLL clock divided by 8 */
+#define RCC_CFG2_ADCPLLPRES_DIV10 ((uint32_t)0x00000150) /*!< PLL clock divided by 10 */
+#define RCC_CFG2_ADCPLLPRES_DIV12 ((uint32_t)0x00000160) /*!< PLL clock divided by 12 */
+#define RCC_CFG2_ADCPLLPRES_DIV16 ((uint32_t)0x00000170) /*!< PLL clock divided by 16 */
+#define RCC_CFG2_ADCPLLPRES_DIV32 ((uint32_t)0x00000180) /*!< PLL clock divided by 32 */
+#define RCC_CFG2_ADCPLLPRES_DIV64 ((uint32_t)0x00000190) /*!< PLL clock divided by 64 */
+#define RCC_CFG2_ADCPLLPRES_DIV128 ((uint32_t)0x000001A0) /*!< PLL clock divided by 128 */
+#define RCC_CFG2_ADCPLLPRES_DIV256 ((uint32_t)0x000001B0) /*!< PLL clock divided by 256 */
+#define RCC_CFG2_ADCPLLPRES_DIV256N ((uint32_t)0x000001C0) /*!< PLL clock divided by 256 */
+
+/*!< ADC1MSEL configuration */
+#define RCC_CFG2_ADC1MSEL ((uint32_t)0x00000400) /*!< ADC1M clock source select */
+
+#define RCC_CFG2_ADC1MSEL_HSI ((uint32_t)0x00000000) /*!< HSI clock selected as ADC1M input clock */
+#define RCC_CFG2_ADC1MSEL_HSE ((uint32_t)0x00000400) /*!< HSE clock selected as ADC1M input clock */
+
+/*!< ADC1MPRE configuration */
+#define RCC_CFG2_ADC1MPRES ((uint32_t)0x0000F800) /*!< ADC1MPRE[4:0] bits */
+#define RCC_CFG2_ADC1MPRES_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define RCC_CFG2_ADC1MPRES_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+#define RCC_CFG2_ADC1MPRES_2 ((uint32_t)0x00002000) /*!< Bit 2 */
+#define RCC_CFG2_ADC1MPRES_3 ((uint32_t)0x00004000) /*!< Bit 3 */
+#define RCC_CFG2_ADC1MPRES_4 ((uint32_t)0x00008000) /*!< Bit 4 */
+
+#define RCC_CFG2_ADC1MPRES_DIV1 ((uint32_t)0x00000000) /*!< ADC1M source clock is divided by 1 */
+#define RCC_CFG2_ADC1MPRES_DIV2 ((uint32_t)0x00000800) /*!< ADC1M source clock is divided by 2 */
+#define RCC_CFG2_ADC1MPRES_DIV3 ((uint32_t)0x00001000) /*!< ADC1M source clock is divided by 3 */
+#define RCC_CFG2_ADC1MPRES_DIV4 ((uint32_t)0x00001800) /*!< ADC1M source clock is divided by 4 */
+#define RCC_CFG2_ADC1MPRES_DIV5 ((uint32_t)0x00002000) /*!< ADC1M source clock is divided by 5 */
+#define RCC_CFG2_ADC1MPRES_DIV6 ((uint32_t)0x00002800) /*!< ADC1M source clock is divided by 6 */
+#define RCC_CFG2_ADC1MPRES_DIV7 ((uint32_t)0x00003000) /*!< ADC1M source clock is divided by 7 */
+#define RCC_CFG2_ADC1MPRES_DIV8 ((uint32_t)0x00003800) /*!< ADC1M source clock is divided by 8 */
+#define RCC_CFG2_ADC1MPRES_DIV9 ((uint32_t)0x00004000) /*!< ADC1M source clock is divided by 9 */
+#define RCC_CFG2_ADC1MPRES_DIV10 ((uint32_t)0x00004800) /*!< ADC1M source clock is divided by 10 */
+#define RCC_CFG2_ADC1MPRES_DIV11 ((uint32_t)0x00005000) /*!< ADC1M source clock is divided by 11 */
+#define RCC_CFG2_ADC1MPRES_DIV12 ((uint32_t)0x00005800) /*!< ADC1M source clock is divided by 12 */
+#define RCC_CFG2_ADC1MPRES_DIV13 ((uint32_t)0x00006000) /*!< ADC1M source clock is divided by 13 */
+#define RCC_CFG2_ADC1MPRES_DIV14 ((uint32_t)0x00006800) /*!< ADC1M source clock is divided by 14 */
+#define RCC_CFG2_ADC1MPRES_DIV15 ((uint32_t)0x00007000) /*!< ADC1M source clock is divided by 15 */
+#define RCC_CFG2_ADC1MPRES_DIV16 ((uint32_t)0x00007800) /*!< ADC1M source clock is divided by 16 */
+#define RCC_CFG2_ADC1MPRES_DIV17 ((uint32_t)0x00008000) /*!< ADC1M source clock is divided by 17 */
+#define RCC_CFG2_ADC1MPRES_DIV18 ((uint32_t)0x00008800) /*!< ADC1M source clock is divided by 18 */
+#define RCC_CFG2_ADC1MPRES_DIV19 ((uint32_t)0x00009000) /*!< ADC1M source clock is divided by 19 */
+#define RCC_CFG2_ADC1MPRES_DIV20 ((uint32_t)0x00009800) /*!< ADC1M source clock is divided by 20 */
+#define RCC_CFG2_ADC1MPRES_DIV21 ((uint32_t)0x0000A000) /*!< ADC1M source clock is divided by 21 */
+#define RCC_CFG2_ADC1MPRES_DIV22 ((uint32_t)0x0000A800) /*!< ADC1M source clock is divided by 22 */
+#define RCC_CFG2_ADC1MPRES_DIV23 ((uint32_t)0x0000B000) /*!< ADC1M source clock is divided by 23 */
+#define RCC_CFG2_ADC1MPRES_DIV24 ((uint32_t)0x0000B800) /*!< ADC1M source clock is divided by 24 */
+#define RCC_CFG2_ADC1MPRES_DIV25 ((uint32_t)0x0000C000) /*!< ADC1M source clock is divided by 25 */
+#define RCC_CFG2_ADC1MPRES_DIV26 ((uint32_t)0x0000C800) /*!< ADC1M source clock is divided by 26 */
+#define RCC_CFG2_ADC1MPRES_DIV27 ((uint32_t)0x0000D000) /*!< ADC1M source clock is divided by 27 */
+#define RCC_CFG2_ADC1MPRES_DIV28 ((uint32_t)0x0000D800) /*!< ADC1M source clock is divided by 28 */
+#define RCC_CFG2_ADC1MPRES_DIV29 ((uint32_t)0x0000E000) /*!< ADC1M source clock is divided by 29 */
+#define RCC_CFG2_ADC1MPRES_DIV30 ((uint32_t)0x0000E800) /*!< ADC1M source clock is divided by 30 */
+#define RCC_CFG2_ADC1MPRES_DIV31 ((uint32_t)0x0000F000) /*!< ADC1M source clock is divided by 31 */
+#define RCC_CFG2_ADC1MPRES_DIV32 ((uint32_t)0x0000F800) /*!< ADC1M source clock is divided by 32 */
+
+/*!< RNGCPRE configuration */
+#define RCC_CFG2_RNGCPRES ((uint32_t)0x1F000000) /*!< RNGCPRE[4:0] bits */
+#define RCC_CFG2_RNGCPRES_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define RCC_CFG2_RNGCPRES_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define RCC_CFG2_RNGCPRES_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define RCC_CFG2_RNGCPRES_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define RCC_CFG2_RNGCPRES_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+
+#define RCC_CFG2_RNGCPRES_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK source clock is divided by 1 */
+#define RCC_CFG2_RNGCPRES_DIV2 ((uint32_t)0x01000000) /*!< SYSCLK source clock is divided by 2 */
+#define RCC_CFG2_RNGCPRES_DIV3 ((uint32_t)0x02000000) /*!< SYSCLK source clock is divided by 3 */
+#define RCC_CFG2_RNGCPRES_DIV4 ((uint32_t)0x03000000) /*!< SYSCLK source clock is divided by 4 */
+#define RCC_CFG2_RNGCPRES_DIV5 ((uint32_t)0x04000000) /*!< SYSCLK source clock is divided by 5 */
+#define RCC_CFG2_RNGCPRES_DIV6 ((uint32_t)0x05000000) /*!< SYSCLK source clock is divided by 6 */
+#define RCC_CFG2_RNGCPRES_DIV7 ((uint32_t)0x06000000) /*!< SYSCLK source clock is divided by 7 */
+#define RCC_CFG2_RNGCPRES_DIV8 ((uint32_t)0x07000000) /*!< SYSCLK source clock is divided by 8 */
+#define RCC_CFG2_RNGCPRES_DIV9 ((uint32_t)0x08000000) /*!< SYSCLK source clock is divided by 9 */
+#define RCC_CFG2_RNGCPRES_DIV10 ((uint32_t)0x09000000) /*!< SYSCLK source clock is divided by 10 */
+#define RCC_CFG2_RNGCPRES_DIV11 ((uint32_t)0x0A000000) /*!< SYSCLK source clock is divided by 11 */
+#define RCC_CFG2_RNGCPRES_DIV12 ((uint32_t)0x0B000000) /*!< SYSCLK source clock is divided by 12 */
+#define RCC_CFG2_RNGCPRES_DIV13 ((uint32_t)0x0C000000) /*!< SYSCLK source clock is divided by 13 */
+#define RCC_CFG2_RNGCPRES_DIV14 ((uint32_t)0x0D000000) /*!< SYSCLK source clock is divided by 14 */
+#define RCC_CFG2_RNGCPRES_DIV15 ((uint32_t)0x0E000000) /*!< SYSCLK source clock is divided by 15 */
+#define RCC_CFG2_RNGCPRES_DIV16 ((uint32_t)0x0F000000) /*!< SYSCLK source clock is divided by 16 */
+#define RCC_CFG2_RNGCPRES_DIV17 ((uint32_t)0x10000000) /*!< SYSCLK source clock is divided by 17 */
+#define RCC_CFG2_RNGCPRES_DIV18 ((uint32_t)0x11000000) /*!< SYSCLK source clock is divided by 18 */
+#define RCC_CFG2_RNGCPRES_DIV19 ((uint32_t)0x12000000) /*!< SYSCLK source clock is divided by 19 */
+#define RCC_CFG2_RNGCPRES_DIV20 ((uint32_t)0x13000000) /*!< SYSCLK source clock is divided by 20 */
+#define RCC_CFG2_RNGCPRES_DIV21 ((uint32_t)0x14000000) /*!< SYSCLK source clock is divided by 21 */
+#define RCC_CFG2_RNGCPRES_DIV22 ((uint32_t)0x15000000) /*!< SYSCLK source clock is divided by 22 */
+#define RCC_CFG2_RNGCPRES_DIV23 ((uint32_t)0x16000000) /*!< SYSCLK source clock is divided by 23 */
+#define RCC_CFG2_RNGCPRES_DIV24 ((uint32_t)0x17000000) /*!< SYSCLK source clock is divided by 24 */
+#define RCC_CFG2_RNGCPRES_DIV25 ((uint32_t)0x18000000) /*!< SYSCLK source clock is divided by 25 */
+#define RCC_CFG2_RNGCPRES_DIV26 ((uint32_t)0x19000000) /*!< SYSCLK source clock is divided by 26 */
+#define RCC_CFG2_RNGCPRES_DIV27 ((uint32_t)0x1A000000) /*!< SYSCLK source clock is divided by 27 */
+#define RCC_CFG2_RNGCPRES_DIV28 ((uint32_t)0x1B000000) /*!< SYSCLK source clock is divided by 28 */
+#define RCC_CFG2_RNGCPRES_DIV29 ((uint32_t)0x1C000000) /*!< SYSCLK source clock is divided by 29 */
+#define RCC_CFG2_RNGCPRES_DIV30 ((uint32_t)0x1D000000) /*!< SYSCLK source clock is divided by 30 */
+#define RCC_CFG2_RNGCPRES_DIV31 ((uint32_t)0x1E000000) /*!< SYSCLK source clock is divided by 31 */
+#define RCC_CFG2_RNGCPRES_DIV32 ((uint32_t)0x1F000000) /*!< SYSCLK source clock is divided by 32 */
+
+/*!< TIMCLK_SEL configuration */
+#define RCC_CFG2_TIMCLKSEL ((uint32_t)0x20000000) /*!< Timer1/8 clock source select */
+
+#define RCC_CFG2_TIMCLKSEL_TIM18CLK ((uint32_t)0x00000000) /*!< Timer1/8 clock selected as tim1/8_clk input clock */
+#define RCC_CFG2_TIMCLKSEL_SYSCLK ((uint32_t)0x20000000) /*!< Timer1/8 clock selected as sysclk input clock */
+
+/******************* Bit definition for RCC_CFG3 register ******************/
+/*!< BORRSTEN configuration */
+#define RCC_CFG3_BORRSTEN ((uint32_t)0x00000040) /*!< BOR reset enable */
+
+#define RCC_CFG3_BORRSTEN_ENABLE ((uint32_t)0x00000040) /*!< BOR reset enable */
+#define RCC_CFG3_BORRSTEN_DISABLE ((uint32_t)0x00000000) /*!< BOR reset disable */
+
+/*!< TRNG1MPRE configuration */
+#define RCC_CFG3_TRNG1MPRES ((uint32_t)0x0000F800) /*!< TRNG1MPRE[4:0] bits */
+#define RCC_CFG3_TRNG1MPRES_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define RCC_CFG3_TRNG1MPRES_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+#define RCC_CFG3_TRNG1MPRES_2 ((uint32_t)0x00002000) /*!< Bit 2 */
+#define RCC_CFG3_TRNG1MPRES_3 ((uint32_t)0x00004000) /*!< Bit 3 */
+#define RCC_CFG3_TRNG1MPRES_4 ((uint32_t)0x00008000) /*!< Bit 4 */
+
+#define RCC_CFG3_TRNG1MPRES_VAL1 ((uint32_t)0x00000000) /*!< TRNG 1M source clock is divided by 2 */
+#define RCC_CFG3_TRNG1MPRES_VAL2 ((uint32_t)0x00000800) /*!< TRNG 1M source clock is divided by 2 */
+#define RCC_CFG3_TRNG1MPRES_VAL3 ((uint32_t)0x00001000) /*!< TRNG 1M source clock is divided by 4 */
+#define RCC_CFG3_TRNG1MPRES_VAL4 ((uint32_t)0x00001800) /*!< TRNG 1M source clock is divided by 4 */
+#define RCC_CFG3_TRNG1MPRES_VAL5 ((uint32_t)0x00002000) /*!< TRNG 1M source clock is divided by 6 */
+#define RCC_CFG3_TRNG1MPRES_VAL6 ((uint32_t)0x00002800) /*!< TRNG 1M source clock is divided by 6 */
+#define RCC_CFG3_TRNG1MPRES_VAL7 ((uint32_t)0x00003000) /*!< TRNG 1M source clock is divided by 8 */
+#define RCC_CFG3_TRNG1MPRES_VAL8 ((uint32_t)0x00003800) /*!< TRNG 1M source clock is divided by 8 */
+#define RCC_CFG3_TRNG1MPRES_VAL9 ((uint32_t)0x00004000) /*!< TRNG 1M source clock is divided by 10 */
+#define RCC_CFG3_TRNG1MPRES_VAL10 ((uint32_t)0x00004800) /*!< TRNG 1M source clock is divided by 10 */
+#define RCC_CFG3_TRNG1MPRES_VAL11 ((uint32_t)0x00005000) /*!< TRNG 1M source clock is divided by 12 */
+#define RCC_CFG3_TRNG1MPRES_VAL12 ((uint32_t)0x00005800) /*!< TRNG 1M source clock is divided by 12 */
+#define RCC_CFG3_TRNG1MPRES_VAL13 ((uint32_t)0x00006000) /*!< TRNG 1M source clock is divided by 14 */
+#define RCC_CFG3_TRNG1MPRES_VAL14 ((uint32_t)0x00006800) /*!< TRNG 1M source clock is divided by 14 */
+#define RCC_CFG3_TRNG1MPRES_VAL15 ((uint32_t)0x00007000) /*!< TRNG 1M source clock is divided by 16 */
+#define RCC_CFG3_TRNG1MPRES_VAL16 ((uint32_t)0x00007800) /*!< TRNG 1M source clock is divided by 16 */
+#define RCC_CFG3_TRNG1MPRES_VAL17 ((uint32_t)0x00008000) /*!< TRNG 1M source clock is divided by 18 */
+#define RCC_CFG3_TRNG1MPRES_VAL18 ((uint32_t)0x00008800) /*!< TRNG 1M source clock is divided by 18 */
+#define RCC_CFG3_TRNG1MPRES_VAL19 ((uint32_t)0x00009000) /*!< TRNG 1M source clock is divided by 20 */
+#define RCC_CFG3_TRNG1MPRES_VAL20 ((uint32_t)0x00009800) /*!< TRNG 1M source clock is divided by 20 */
+#define RCC_CFG3_TRNG1MPRES_VAL21 ((uint32_t)0x0000A000) /*!< TRNG 1M source clock is divided by 22 */
+#define RCC_CFG3_TRNG1MPRES_VAL22 ((uint32_t)0x0000A800) /*!< TRNG 1M source clock is divided by 22 */
+#define RCC_CFG3_TRNG1MPRES_VAL23 ((uint32_t)0x0000B000) /*!< TRNG 1M source clock is divided by 24 */
+#define RCC_CFG3_TRNG1MPRES_VAL24 ((uint32_t)0x0000B800) /*!< TRNG 1M source clock is divided by 24 */
+#define RCC_CFG3_TRNG1MPRES_VAL25 ((uint32_t)0x0000C000) /*!< TRNG 1M source clock is divided by 26 */
+#define RCC_CFG3_TRNG1MPRES_VAL26 ((uint32_t)0x0000C800) /*!< TRNG 1M source clock is divided by 26 */
+#define RCC_CFG3_TRNG1MPRES_VAL27 ((uint32_t)0x0000D000) /*!< TRNG 1M source clock is divided by 28 */
+#define RCC_CFG3_TRNG1MPRES_VAL28 ((uint32_t)0x0000D800) /*!< TRNG 1M source clock is divided by 28 */
+#define RCC_CFG3_TRNG1MPRES_VAL29 ((uint32_t)0x0000E000) /*!< TRNG 1M source clock is divided by 30 */
+#define RCC_CFG3_TRNG1MPRES_VAL30 ((uint32_t)0x0000E800) /*!< TRNG 1M source clock is divided by 30 */
+#define RCC_CFG3_TRNG1MPRES_VAL31 ((uint32_t)0x0000F000) /*!< TRNG 1M source clock is divided by 32 */
+#define RCC_CFG3_TRNG1MPRES_VAL32 ((uint32_t)0x0000F800) /*!< TRNG 1M source clock is divided by 32 */
+
+/*!< TRNG1MSEL configuration */
+#define RCC_CFG3_TRNG1MSEL ((uint32_t)0x00020000) /*!< TRNG_1M clock source select */
+
+#define RCC_CFG3_TRNG1MSEL_HSI ((uint32_t)0x00000000) /*!< HSI clock selected as TRNG_1M input clock */
+#define RCC_CFG3_TRNG1MSEL_HSE ((uint32_t)0x00020000) /*!< HSE clock selected as TRNG_1M input clock */
+
+/*!< TRNG1MEN configuration */
+#define RCC_CFG3_TRNG1MEN ((uint32_t)0x00040000) /*!< TRNG_1M clock enable */
+
+#define RCC_CFG3_TRNG1MEN_DISABLE ((uint32_t)0x00000000) /*!< TRNG_1M clock disable */
+#define RCC_CFG3_TRNG1MEN_ENABLE ((uint32_t)0x00040000) /*!< TRNG_1M clock enable */
+
+/******************************************************************************/
+/* */
+/* General Purpose and Alternate Function I/O */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for GPIO_PL_CFG register *******************/
+#define GPIO_PL_CFG_PMODE ((uint32_t)0x33333333) /*!< Port x mode bits */
+
+#define GPIO_PL_CFG_PMODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define GPIO_PL_CFG_PMODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define GPIO_PL_CFG_PMODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define GPIO_PL_CFG_PMODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define GPIO_PL_CFG_PMODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define GPIO_PL_CFG_PMODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define GPIO_PL_CFG_PMODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define GPIO_PL_CFG_PMODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define GPIO_PL_CFG_PMODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define GPIO_PL_CFG_PMODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define GPIO_PL_CFG_PMODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define GPIO_PL_CFG_PMODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define GPIO_PL_CFG_PMODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define GPIO_PL_CFG_PMODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define GPIO_PL_CFG_PMODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define GPIO_PL_CFG_PMODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define GPIO_PL_CFG_PMODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define GPIO_PL_CFG_PMODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+#define GPIO_PL_CFG_PMODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define GPIO_PL_CFG_PMODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define GPIO_PL_CFG_PMODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+
+#define GPIO_PL_CFG_PMODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define GPIO_PL_CFG_PMODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define GPIO_PL_CFG_PMODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+#define GPIO_PL_CFG_PCFG ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
+
+#define GPIO_PL_CFG_PCFG0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define GPIO_PL_CFG_PCFG0_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define GPIO_PL_CFG_PCFG0_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define GPIO_PL_CFG_PCFG1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define GPIO_PL_CFG_PCFG1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define GPIO_PL_CFG_PCFG1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define GPIO_PL_CFG_PCFG2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define GPIO_PL_CFG_PCFG2_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define GPIO_PL_CFG_PCFG2_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define GPIO_PL_CFG_PCFG3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define GPIO_PL_CFG_PCFG3_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define GPIO_PL_CFG_PCFG3_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+
+#define GPIO_PL_CFG_PCFG4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define GPIO_PL_CFG_PCFG4_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define GPIO_PL_CFG_PCFG4_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+
+#define GPIO_PL_CFG_PCFG5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define GPIO_PL_CFG_PCFG5_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define GPIO_PL_CFG_PCFG5_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define GPIO_PL_CFG_PCFG6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define GPIO_PL_CFG_PCFG6_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define GPIO_PL_CFG_PCFG6_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+
+#define GPIO_PL_CFG_PCFG7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define GPIO_PL_CFG_PCFG7_0 ((uint32_t)0x40000000) /*!< Bit 0 */
+#define GPIO_PL_CFG_PCFG7_1 ((uint32_t)0x80000000) /*!< Bit 1 */
+
+/******************* Bit definition for GPIO_PH_CFG register *******************/
+#define GPIO_PH_CFG_PMODE ((uint32_t)0x33333333) /*!< Port x mode bits */
+
+#define GPIO_PH_CFG_PMODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define GPIO_PH_CFG_PMODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define GPIO_PH_CFG_PMODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define GPIO_PH_CFG_PMODE1 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define GPIO_PH_CFG_PMODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define GPIO_PH_CFG_PMODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define GPIO_PH_CFG_PMODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define GPIO_PH_CFG_PMODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define GPIO_PH_CFG_PMODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define GPIO_PH_CFG_PMODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define GPIO_PH_CFG_PMODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define GPIO_PH_CFG_PMODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define GPIO_PH_CFG_PMODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define GPIO_PH_CFG_PMODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define GPIO_PH_CFG_PMODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define GPIO_PH_CFG_PMODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define GPIO_PH_CFG_PMODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define GPIO_PH_CFG_PMODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+#define GPIO_PH_CFG_PMODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define GPIO_PH_CFG_PMODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define GPIO_PH_CFG_PMODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+
+#define GPIO_PH_CFG_PMODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define GPIO_PH_CFG_PMODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define GPIO_PH_CFG_PMODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+#define GPIO_PH_CFG_PCFG ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
+
+#define GPIO_PH_CFG_PCFG8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define GPIO_PH_CFG_PCFG8_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define GPIO_PH_CFG_PCFG8_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define GPIO_PH_CFG_PCFG9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define GPIO_PH_CFG_PCFG9_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define GPIO_PH_CFG_PCFG9_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define GPIO_PH_CFG_PCFG10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define GPIO_PH_CFG_PCFG10_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define GPIO_PH_CFG_PCFG10_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define GPIO_PH_CFG_PCFG11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define GPIO_PH_CFG_PCFG11_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define GPIO_PH_CFG_PCFG11_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+
+#define GPIO_PH_CFG_PCFG12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define GPIO_PH_CFG_PCFG12_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define GPIO_PH_CFG_PCFG12_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+
+#define GPIO_PH_CFG_PCFG13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define GPIO_PH_CFG_PCFG13_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define GPIO_PH_CFG_PCFG13_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define GPIO_PH_CFG_PCFG14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define GPIO_PH_CFG_PCFG14_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define GPIO_PH_CFG_PCFG14_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+
+#define GPIO_PH_CFG_PCFG15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define GPIO_PH_CFG_PCFG15_0 ((uint32_t)0x40000000) /*!< Bit 0 */
+#define GPIO_PH_CFG_PCFG15_1 ((uint32_t)0x80000000) /*!< Bit 1 */
+
+/*!<****************** Bit definition for GPIO_PID register *******************/
+#define GPIO_PID_PID0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */
+#define GPIO_PID_PID1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */
+#define GPIO_PID_PID2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */
+#define GPIO_PID_PID3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */
+#define GPIO_PID_PID4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */
+#define GPIO_PID_PID5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */
+#define GPIO_PID_PID6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */
+#define GPIO_PID_PID7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */
+#define GPIO_PID_PID8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */
+#define GPIO_PID_PID9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */
+#define GPIO_PID_PID10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */
+#define GPIO_PID_PID11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */
+#define GPIO_PID_PID12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */
+#define GPIO_PID_PID13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */
+#define GPIO_PID_PID14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */
+#define GPIO_PID_PID15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */
+
+/******************* Bit definition for GPIO_POD register *******************/
+#define GPIO_POD_POD0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */
+#define GPIO_POD_POD1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */
+#define GPIO_POD_POD2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */
+#define GPIO_POD_POD3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */
+#define GPIO_POD_POD4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */
+#define GPIO_POD_POD5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */
+#define GPIO_POD_POD6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */
+#define GPIO_POD_POD7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */
+#define GPIO_POD_POD8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */
+#define GPIO_POD_POD9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */
+#define GPIO_POD_POD10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */
+#define GPIO_POD_POD11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */
+#define GPIO_POD_POD12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */
+#define GPIO_POD_POD13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */
+#define GPIO_POD_POD14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */
+#define GPIO_POD_POD15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */
+
+/****************** Bit definition for GPIO_PBSC register *******************/
+#define GPIO_PBSC_PBS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */
+#define GPIO_PBSC_PBS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */
+#define GPIO_PBSC_PBS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */
+#define GPIO_PBSC_PBS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */
+#define GPIO_PBSC_PBS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */
+#define GPIO_PBSC_PBS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */
+#define GPIO_PBSC_PBS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */
+#define GPIO_PBSC_PBS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */
+#define GPIO_PBSC_PBS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */
+#define GPIO_PBSC_PBS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */
+#define GPIO_PBSC_PBS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */
+#define GPIO_PBSC_PBS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */
+#define GPIO_PBSC_PBS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */
+#define GPIO_PBSC_PBS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */
+#define GPIO_PBSC_PBS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */
+#define GPIO_PBSC_PBS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */
+
+#define GPIO_PBSC_PBC0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */
+#define GPIO_PBSC_PBC1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */
+#define GPIO_PBSC_PBC2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */
+#define GPIO_PBSC_PBC3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */
+#define GPIO_PBSC_PBC4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */
+#define GPIO_PBSC_PBC5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */
+#define GPIO_PBSC_PBC6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */
+#define GPIO_PBSC_PBC7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */
+#define GPIO_PBSC_PBC8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */
+#define GPIO_PBSC_PBC9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */
+#define GPIO_PBSC_PBC10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */
+#define GPIO_PBSC_PBC11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */
+#define GPIO_PBSC_PBC12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */
+#define GPIO_PBSC_PBC13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */
+#define GPIO_PBSC_PBC14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */
+#define GPIO_PBSC_PBC15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */
+
+/******************* Bit definition for GPIO_PBC register *******************/
+#define GPIO_PBC_PBC0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */
+#define GPIO_PBC_PBC1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */
+#define GPIO_PBC_PBC2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */
+#define GPIO_PBC_PBC3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */
+#define GPIO_PBC_PBC4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */
+#define GPIO_PBC_PBC5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */
+#define GPIO_PBC_PBC6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */
+#define GPIO_PBC_PBC7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */
+#define GPIO_PBC_PBC8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */
+#define GPIO_PBC_PBC9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */
+#define GPIO_PBC_PBC10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */
+#define GPIO_PBC_PBC11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */
+#define GPIO_PBC_PBC12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */
+#define GPIO_PBC_PBC13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */
+#define GPIO_PBC_PBC14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */
+#define GPIO_PBC_PBC15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */
+
+/****************** Bit definition for GPIO_PLOCK_CFG register *******************/
+#define GPIO_PLOCK_CFG_PLOCK_CFG0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */
+#define GPIO_PLOCK_CFG_PLOCK_CFG1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */
+#define GPIO_PLOCK_CFG_PLOCK_CFG2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */
+#define GPIO_PLOCK_CFG_PLOCK_CFG3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */
+#define GPIO_PLOCK_CFG_PLOCK_CFG4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */
+#define GPIO_PLOCK_CFG_PLOCK_CFG5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */
+#define GPIO_PLOCK_CFG_PLOCK_CFG6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */
+#define GPIO_PLOCK_CFG_PLOCK_CFG7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */
+#define GPIO_PLOCK_CFG_PLOCK_CFG8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */
+#define GPIO_PLOCK_CFG_PLOCK_CFG9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */
+#define GPIO_PLOCK_CFG_PLOCK_CFG10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */
+#define GPIO_PLOCK_CFG_PLOCK_CFG11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */
+#define GPIO_PLOCK_CFG_PLOCK_CFG12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */
+#define GPIO_PLOCK_CFG_PLOCK_CFG13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */
+#define GPIO_PLOCK_CFG_PLOCK_CFG14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */
+#define GPIO_PLOCK_CFG_PLOCK_CFG15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */
+#define GPIO_PLOCK_CFG_PLOCKK_CFG ((uint32_t)0x00010000) /*!< Lock key */
+
+/******************* Bit definition for GPIO_DS_CFG register *******************/
+#define GPIO_DS_CFG0 ((uint16_t)0x0001) /*!< Port x Drive bit 0 */
+#define GPIO_DS_CFG1 ((uint16_t)0x0002) /*!< Port x Drive bit 1 */
+#define GPIO_DS_CFG2 ((uint16_t)0x0004) /*!< Port x Drive bit 2 */
+#define GPIO_DS_CFG3 ((uint16_t)0x0008) /*!< Port x Drive bit 3 */
+#define GPIO_DS_CFG4 ((uint16_t)0x0010) /*!< Port x Drive bit 4 */
+#define GPIO_DS_CFG5 ((uint16_t)0x0020) /*!< Port x Drive bit 5 */
+#define GPIO_DS_CFG6 ((uint16_t)0x0040) /*!< Port x Drive bit 6 */
+#define GPIO_DS_CFG7 ((uint16_t)0x0080) /*!< Port x Drive bit 7 */
+#define GPIO_DS_CFG8 ((uint16_t)0x0100) /*!< Port x Drive bit 8 */
+#define GPIO_DS_CFG9 ((uint16_t)0x0200) /*!< Port x Drive bit 9 */
+#define GPIO_DS_CFG10 ((uint16_t)0x0400) /*!< Port x Drive bit 10 */
+#define GPIO_DS_CFG11 ((uint16_t)0x0800) /*!< Port x Drive bit 11 */
+#define GPIO_DS_CFG12 ((uint16_t)0x1000) /*!< Port x Drive bit 12 */
+#define GPIO_DS_CFG13 ((uint16_t)0x2000) /*!< Port x Drive bit 13 */
+#define GPIO_DS_CFG14 ((uint16_t)0x4000) /*!< Port x Drive bit 14 */
+#define GPIO_DS_CFG15 ((uint16_t)0x8000) /*!< Port x Drive bit 15 */
+
+/******************* Bit definition for GPIO_SR_CFG register *******************/
+#define GPIO_SR_CFG0 ((uint16_t)0x0001) /*!< Port x Turn bit 0 */
+#define GPIO_SR_CFG1 ((uint16_t)0x0002) /*!< Port x Turn bit 1 */
+#define GPIO_SR_CFG2 ((uint16_t)0x0004) /*!< Port x Turn bit 2 */
+#define GPIO_SR_CFG3 ((uint16_t)0x0008) /*!< Port x Turn bit 3 */
+#define GPIO_SR_CFG4 ((uint16_t)0x0010) /*!< Port x Turn bit 4 */
+#define GPIO_SR_CFG5 ((uint16_t)0x0020) /*!< Port x Turn bit 5 */
+#define GPIO_SR_CFG6 ((uint16_t)0x0040) /*!< Port x Turn bit 6 */
+#define GPIO_SR_CFG7 ((uint16_t)0x0080) /*!< Port x Turn bit 7 */
+#define GPIO_SR_CFG8 ((uint16_t)0x0100) /*!< Port x Turn bit 8 */
+#define GPIO_SR_CFG9 ((uint16_t)0x0200) /*!< Port x Turn bit 9 */
+#define GPIO_SR_CFG10 ((uint16_t)0x0400) /*!< Port x Turn bit 10 */
+#define GPIO_SR_CFG11 ((uint16_t)0x0800) /*!< Port x Turn bit 11 */
+#define GPIO_SR_CFG12 ((uint16_t)0x1000) /*!< Port x Turn bit 12 */
+#define GPIO_SR_CFG13 ((uint16_t)0x2000) /*!< Port x Turn bit 13 */
+#define GPIO_SR_CFG14 ((uint16_t)0x4000) /*!< Port x Turn bit 14 */
+#define GPIO_SR_CFG15 ((uint16_t)0x8000) /*!< Port x Turn bit 15 */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for AFIO_ECTRL register *******************/
+#define AFIO_ECTRL_PIN_SEL ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */
+#define AFIO_ECTRL_PIN_SEL_0 ((uint8_t)0x01) /*!< Bit 0 */
+#define AFIO_ECTRL_PIN_SEL_1 ((uint8_t)0x02) /*!< Bit 1 */
+#define AFIO_ECTRL_PIN_SEL_2 ((uint8_t)0x04) /*!< Bit 2 */
+#define AFIO_ECTRL_PIN_SEL_3 ((uint8_t)0x08) /*!< Bit 3 */
+
+/*!< PIN configuration */
+#define AFIO_ECTRL_PIN_SEL_PIN0 ((uint8_t)0x00) /*!< Pin 0 selected */
+#define AFIO_ECTRL_PIN_SEL_PIN1 ((uint8_t)0x01) /*!< Pin 1 selected */
+#define AFIO_ECTRL_PIN_SEL_PIN2 ((uint8_t)0x02) /*!< Pin 2 selected */
+#define AFIO_ECTRL_PIN_SEL_PIN3 ((uint8_t)0x03) /*!< Pin 3 selected */
+#define AFIO_ECTRL_PIN_SEL_PIN4 ((uint8_t)0x04) /*!< Pin 4 selected */
+#define AFIO_ECTRL_PIN_SEL_PIN5 ((uint8_t)0x05) /*!< Pin 5 selected */
+#define AFIO_ECTRL_PIN_SEL_PIN6 ((uint8_t)0x06) /*!< Pin 6 selected */
+#define AFIO_ECTRL_PIN_SEL_PIN7 ((uint8_t)0x07) /*!< Pin 7 selected */
+#define AFIO_ECTRL_PIN_SEL_PIN8 ((uint8_t)0x08) /*!< Pin 8 selected */
+#define AFIO_ECTRL_PIN_SEL_PIN9 ((uint8_t)0x09) /*!< Pin 9 selected */
+#define AFIO_ECTRL_PIN_SEL_PIN10 ((uint8_t)0x0A) /*!< Pin 10 selected */
+#define AFIO_ECTRL_PIN_SEL_PIN11 ((uint8_t)0x0B) /*!< Pin 11 selected */
+#define AFIO_ECTRL_PIN_SEL_PIN12 ((uint8_t)0x0C) /*!< Pin 12 selected */
+#define AFIO_ECTRL_PIN_SEL_PIN13 ((uint8_t)0x0D) /*!< Pin 13 selected */
+#define AFIO_ECTRL_PIN_SEL_PIN14 ((uint8_t)0x0E) /*!< Pin 14 selected */
+#define AFIO_ECTRL_PIN_SEL_PIN15 ((uint8_t)0x0F) /*!< Pin 15 selected */
+
+#define AFIO_ECTRL_PORT_SEL ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */
+#define AFIO_ECTRL_PORT_SEL_0 ((uint8_t)0x10) /*!< Bit 0 */
+#define AFIO_ECTRL_PORT_SEL_1 ((uint8_t)0x20) /*!< Bit 1 */
+#define AFIO_ECTRL_PORT_SEL_2 ((uint8_t)0x40) /*!< Bit 2 */
+
+/*!< PORT configuration */
+#define AFIO_ECTRL_PORT_SEL_PA ((uint8_t)0x00) /*!< Port A selected */
+#define AFIO_ECTRL_PORT_SEL_PB ((uint8_t)0x10) /*!< Port B selected */
+#define AFIO_ECTRL_PORT_SEL_PC ((uint8_t)0x20) /*!< Port C selected */
+#define AFIO_ECTRL_PORT_SEL_PD ((uint8_t)0x30) /*!< Port D selected */
+#define AFIO_ECTRL_PORT_SEL_PE ((uint8_t)0x40) /*!< Port E selected */
+
+#define AFIO_ECTRL_EOE ((uint8_t)0x80) /*!< Event Output Enable */
+
+/****************** Bit definition for AFIO_RMP_CFG register *******************/
+#define AFIO_RMP_CFG_SPI1_RMP_0 ((uint32_t)0x00000001) /*!< SPI1_RMP_0 remapping */
+#define AFIO_RMP_CFG_I2C1_RMP ((uint32_t)0x00000002) /*!< I2C1 remapping */
+#define AFIO_RMP_CFG_USART1_RMP ((uint32_t)0x00000004) /*!< USART1 remapping */
+#define AFIO_RMP_CFG_USART2_RMP_0 ((uint32_t)0x00000008) /*!< USART2_RMP_0 remapping */
+
+#define AFIO_RMP_CFG_USART3_RMP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
+#define AFIO_RMP_CFG_USART3_RMP_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define AFIO_RMP_CFG_USART3_RMP_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+/* USART3_REMAP configuration */
+#define AFIO_RMP_CFG_USART3_RMP_NONE \
+ ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_RMP_CFG_USART3_RMP_PART \
+ ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+#define AFIO_RMP_CFG_USART3_RMP_ALL \
+ ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
+
+#define AFIO_RMP_CFG_TIM1_RMP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_RMP_CFG_TIM1_RMP_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define AFIO_RMP_CFG_TIM1_RMP_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+/*!< TIM1_REMAP configuration */
+#define AFIO_RMP_CFG_TIM1_RMP_NONE \
+ ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, \
+ CH2N/PB14, CH3N/PB15) */
+#define AFIO_RMP_CFG_TIM1_RMP_PART \
+ ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, \
+ CH2N/PB0, CH3N/PB1) */
+#define AFIO_RMP_CFG_TIM1_RMP_ALL \
+ ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, \
+ CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_RMP_CFG_TIM2_RMP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_RMP_CFG_TIM2_RMP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define AFIO_RMP_CFG_TIM2_RMP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< TIM2_REMAP configuration */
+#define AFIO_RMP_CFG_TIM2_RMP_NONE ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_RMP_CFG_TIM2_RMP_PART1 \
+ ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_RMP_CFG_TIM2_RMP_PART2 \
+ ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_RMP_CFG_TIM2_RMP_ALL \
+ ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) \
+ */
+
+#define AFIO_RMP_CFG_TIM3_RMP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_RMP_CFG_TIM3_RMP_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define AFIO_RMP_CFG_TIM3_RMP_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+/*!< TIM3_REMAP configuration */
+#define AFIO_RMP_CFG_TIM3_RMP_NONE ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_RMP_CFG_TIM3_RMP_PART ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_RMP_CFG_TIM3_RMP_ALL ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+#define AFIO_RMP_CFG_TIM4_RMP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */
+
+#define AFIO_RMP_CFG_CAN1_RMP ((uint32_t)0x00006000) /*!< CAN1_RMP[1:0] bits (CAN1 Alternate function remapping) */
+#define AFIO_RMP_CFG_CAN1_RMP_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define AFIO_RMP_CFG_CAN1_RMP_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+
+/*!< CAN1_REMAP configuration */
+#define AFIO_RMP_CFG_CAN1_RMP_RMP1 ((uint32_t)0x00000000) /*!< CAN1RX mapped to PA11, CAN1TX mapped to PA12 */
+#define AFIO_RMP_CFG_CAN1_RMP_RMP2 ((uint32_t)0x00004000) /*!< CAN1RX mapped to PB8, CAN1TX mapped to PB9 */
+#define AFIO_RMP_CFG_CAN1_RMP_RMP3 ((uint32_t)0x00006000) /*!< CAN1RX mapped to PD0, CAN1TX mapped to PD1 */
+#define AFIO_RMP_CFG_CAN1_RMP_RMP4 ((uint32_t)0x00002000) /*!< CAN1RX mapped to PD12, CAN1TX mapped to PD13 */
+
+#define AFIO_RMP_CFG_PD01_RMP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+#define AFIO_RMP_CFG_TIM5CH4_RMP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */
+#define AFIO_RMP_CFG_ADC1_ETRI_RMP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */
+#define AFIO_RMP_CFG_ADC1_ETRR_RMP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */
+#define AFIO_RMP_CFG_ADC2_ETRI_RMP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */
+#define AFIO_RMP_CFG_ADC2_ETRR_RMP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */
+#define AFIO_RMP_CFG_MII_RMII_SEL ((uint32_t)0x00800000) /*!< ETH MAC MII_RMII_SEL remapping */
+/*!< SWJ_CFG configuration */
+#define AFIO_RMP_CFG_SW_JTAG_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_RMP_CFG_SW_JTAG_CFG0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define AFIO_RMP_CFG_SW_JTAG_CFG1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define AFIO_RMP_CFG_SW_JTAG_CFG2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define AFIO_RMP_CFG_SW_JTAG_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_RMP_CFG_SW_JTAG_CFG_NO_NJTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST \
+ */
+#define AFIO_RMP_CFG_SW_JTAG_CFG_SW_ENABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_RMP_CFG_SW_JTAG_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */
+
+/***************** Bit definition for AFIO_EXTI_CFG1 register *****************/
+#define AFIO_EXTI_CFG1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
+#define AFIO_EXTI_CFG1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
+#define AFIO_EXTI_CFG1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
+#define AFIO_EXTI_CFG1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+
+/*!< EXTI0 configuration */
+#define AFIO_EXTI_CFG1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
+#define AFIO_EXTI_CFG1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
+#define AFIO_EXTI_CFG1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
+#define AFIO_EXTI_CFG1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
+#define AFIO_EXTI_CFG1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
+#define AFIO_EXTI_CFG1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
+#define AFIO_EXTI_CFG1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */
+
+/*!< EXTI1 configuration */
+#define AFIO_EXTI_CFG1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
+#define AFIO_EXTI_CFG1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
+#define AFIO_EXTI_CFG1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
+#define AFIO_EXTI_CFG1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
+#define AFIO_EXTI_CFG1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
+#define AFIO_EXTI_CFG1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
+#define AFIO_EXTI_CFG1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */
+
+/*!< EXTI2 configuration */
+#define AFIO_EXTI_CFG1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
+#define AFIO_EXTI_CFG1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
+#define AFIO_EXTI_CFG1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
+#define AFIO_EXTI_CFG1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
+#define AFIO_EXTI_CFG1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
+#define AFIO_EXTI_CFG1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
+#define AFIO_EXTI_CFG1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */
+
+/*!< EXTI3 configuration */
+#define AFIO_EXTI_CFG1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
+#define AFIO_EXTI_CFG1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
+#define AFIO_EXTI_CFG1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
+#define AFIO_EXTI_CFG1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
+#define AFIO_EXTI_CFG1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
+#define AFIO_EXTI_CFG1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
+#define AFIO_EXTI_CFG1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */
+
+/***************** Bit definition for AFIO_EXTI_CFG2 register *****************/
+#define AFIO_EXTI_CFG2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
+#define AFIO_EXTI_CFG2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
+#define AFIO_EXTI_CFG2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
+#define AFIO_EXTI_CFG2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+
+/*!< EXTI4 configuration */
+#define AFIO_EXTI_CFG2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
+#define AFIO_EXTI_CFG2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
+#define AFIO_EXTI_CFG2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
+#define AFIO_EXTI_CFG2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
+#define AFIO_EXTI_CFG2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
+#define AFIO_EXTI_CFG2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
+#define AFIO_EXTI_CFG2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */
+
+/* EXTI5 configuration */
+#define AFIO_EXTI_CFG2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
+#define AFIO_EXTI_CFG2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
+#define AFIO_EXTI_CFG2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
+#define AFIO_EXTI_CFG2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
+#define AFIO_EXTI_CFG2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
+#define AFIO_EXTI_CFG2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
+#define AFIO_EXTI_CFG2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */
+
+/*!< EXTI6 configuration */
+#define AFIO_EXTI_CFG2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
+#define AFIO_EXTI_CFG2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
+#define AFIO_EXTI_CFG2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
+#define AFIO_EXTI_CFG2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
+#define AFIO_EXTI_CFG2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
+#define AFIO_EXTI_CFG2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
+#define AFIO_EXTI_CFG2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */
+
+/*!< EXTI7 configuration */
+#define AFIO_EXTI_CFG2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
+#define AFIO_EXTI_CFG2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
+#define AFIO_EXTI_CFG2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
+#define AFIO_EXTI_CFG2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
+#define AFIO_EXTI_CFG2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
+#define AFIO_EXTI_CFG2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
+#define AFIO_EXTI_CFG2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */
+
+/***************** Bit definition for AFIO_EXTI_CFG3 register *****************/
+#define AFIO_EXTI_CFG3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
+#define AFIO_EXTI_CFG3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
+#define AFIO_EXTI_CFG3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
+#define AFIO_EXTI_CFG3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+
+/*!< EXTI8 configuration */
+#define AFIO_EXTI_CFG3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
+#define AFIO_EXTI_CFG3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
+#define AFIO_EXTI_CFG3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
+#define AFIO_EXTI_CFG3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
+#define AFIO_EXTI_CFG3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
+#define AFIO_EXTI_CFG3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */
+#define AFIO_EXTI_CFG3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */
+
+/*!< EXTI9 configuration */
+#define AFIO_EXTI_CFG3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
+#define AFIO_EXTI_CFG3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
+#define AFIO_EXTI_CFG3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
+#define AFIO_EXTI_CFG3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
+#define AFIO_EXTI_CFG3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
+#define AFIO_EXTI_CFG3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
+#define AFIO_EXTI_CFG3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */
+
+/*!< EXTI10 configuration */
+#define AFIO_EXTI_CFG3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
+#define AFIO_EXTI_CFG3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
+#define AFIO_EXTI_CFG3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
+#define AFIO_EXTI_CFG3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
+#define AFIO_EXTI_CFG3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */
+#define AFIO_EXTI_CFG3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
+#define AFIO_EXTI_CFG3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */
+
+/*!< EXTI11 configuration */
+#define AFIO_EXTI_CFG3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
+#define AFIO_EXTI_CFG3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
+#define AFIO_EXTI_CFG3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
+#define AFIO_EXTI_CFG3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
+#define AFIO_EXTI_CFG3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
+#define AFIO_EXTI_CFG3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */
+#define AFIO_EXTI_CFG3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */
+
+/***************** Bit definition for AFIO_EXTI_CFG4 register *****************/
+#define AFIO_EXTI_CFG4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
+#define AFIO_EXTI_CFG4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
+#define AFIO_EXTI_CFG4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
+#define AFIO_EXTI_CFG4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+
+/* EXTI12 configuration */
+#define AFIO_EXTI_CFG4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
+#define AFIO_EXTI_CFG4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
+#define AFIO_EXTI_CFG4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
+#define AFIO_EXTI_CFG4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
+#define AFIO_EXTI_CFG4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
+#define AFIO_EXTI_CFG4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */
+#define AFIO_EXTI_CFG4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */
+
+/* EXTI13 configuration */
+#define AFIO_EXTI_CFG4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
+#define AFIO_EXTI_CFG4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
+#define AFIO_EXTI_CFG4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
+#define AFIO_EXTI_CFG4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
+#define AFIO_EXTI_CFG4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
+#define AFIO_EXTI_CFG4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */
+#define AFIO_EXTI_CFG4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */
+
+/*!< EXTI14 configuration */
+#define AFIO_EXTI_CFG4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
+#define AFIO_EXTI_CFG4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
+#define AFIO_EXTI_CFG4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
+#define AFIO_EXTI_CFG4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
+#define AFIO_EXTI_CFG4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
+#define AFIO_EXTI_CFG4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */
+#define AFIO_EXTI_CFG4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */
+
+/*!< EXTI15 configuration */
+#define AFIO_EXTI_CFG4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
+#define AFIO_EXTI_CFG4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
+#define AFIO_EXTI_CFG4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
+#define AFIO_EXTI_CFG4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
+#define AFIO_EXTI_CFG4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
+#define AFIO_EXTI_CFG4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */
+#define AFIO_EXTI_CFG4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */
+
+/****************** Bit definition for AFIO_RMP_CFG3 register *******************/
+#define AFIO_RMP_CFG3_SDIO_RMP ((uint32_t)0x00000001) /*!< SDIO remapping */
+#define AFIO_RMP_CFG3_CAN2_RMP ((uint32_t)0x00000006) /*!FLASH
+
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ /* section information for finsh shell */
+ . = ALIGN(4);
+ __fsymtab_start = .;
+ KEEP(*(FSymTab))
+ __fsymtab_end = .;
+
+ . = ALIGN(4);
+ __vsymtab_start = .;
+ KEEP(*(VSymTab))
+ __vsymtab_end = .;
+
+ /* section information for initial. */
+ . = ALIGN(4);
+ __rt_init_start = .;
+ KEEP(*(SORT(.rti_fn*)))
+ __rt_init_end = .;
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data goes into FLASH */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >FLASH
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH
+
+ /* used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(4);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(4);
+ } >RAM
+
+
+
+ /* Remove information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/startup/startup_n32wb452.s b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/startup/startup_n32wb452.s
new file mode 100644
index 0000000000..808c0b11c6
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/startup/startup_n32wb452.s
@@ -0,0 +1,426 @@
+; ****************************************************************************
+; Copyright (c) 2019, Nations Technologies Inc.
+;
+; All rights reserved.
+; ****************************************************************************
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; - Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the disclaimer below.
+;
+; Nations' name may not be used to endorse or promote products derived from
+; this software without specific prior written permission.
+;
+; DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+; DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+; OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; ****************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00001400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000800
+
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Tamper
+ DCD RTC_WKUP_IRQHandler ; RTC_WKUP
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 & ADC2
+ DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
+ DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
+ DCD TIM8_BRK_IRQHandler ; TIM8 Break
+ DCD TIM8_UP_IRQHandler ; TIM8 Update
+ DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
+ DCD RESERVE47_IRQHandler ; RESERVE47
+ DCD RESERVE48_IRQHandler ; RESERVE48
+ DCD SDIO_IRQHandler ; SDIO
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_IRQHandler ; TIM6
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
+ DCD RESERVE61_IRQHandler ; RESERVE61 global interrupt
+ DCD RESERVE62_IRQHandler ; RESERVE62 interrupt
+ DCD CAN2_TX_IRQHandler ; CAN2 TX
+ DCD CAN2_RX0_IRQHandler ; CAN2 RX0
+ DCD CAN2_RX1_IRQHandler ; CAN2 RX1
+ DCD CAN2_SCE_IRQHandler ; CAN2 SCE
+ DCD RESERVE67_IRQHandler ; RESERVE67
+ DCD DMA2_Channel6_IRQHandler ; DMA2 Channel6
+ DCD DMA2_Channel7_IRQHandler ; DMA2 Channel7
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD I2C4_EV_IRQHandler ; I2C4 event
+ DCD I2C4_ER_IRQHandler ; I2C4 error
+ DCD UART6_IRQHandler ; UART6
+ DCD UART7_IRQHandler ; UART7
+ DCD DMA1_Channel8_IRQHandler ; DMA1 Channel8
+ DCD DMA2_Channel8_IRQHandler ; DMA2 Channel8
+ DCD DVP_IRQHandler ; DVP
+ DCD SAC_IRQHandler ; SAC
+ DCD MMU_IRQHandler ; MMU
+ DCD TSC_IRQHandler ; TSC
+ DCD RESERVE82_IRQHandler ; RESERVE82
+ DCD RESERVE83_IRQHandler ; RESERVE83
+ DCD RESERVE84_IRQHandler ; RESERVE84
+ DCD RSRAM_IRQHandler ; R-SRAM parity error interrupt
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ IMPORT SystemInit
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_IRQHandler [WEAK]
+ EXPORT TAMPER_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC1_2_IRQHandler [WEAK]
+ EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
+ EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
+ EXPORT CAN1_RX1_IRQHandler [WEAK]
+ EXPORT CAN1_SCE_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTCAlarm_IRQHandler [WEAK]
+ EXPORT USBWakeUp_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_IRQHandler [WEAK]
+ EXPORT TIM8_UP_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT SDIO_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Channel1_IRQHandler [WEAK]
+ EXPORT DMA2_Channel2_IRQHandler [WEAK]
+ EXPORT DMA2_Channel3_IRQHandler [WEAK]
+ EXPORT DMA2_Channel4_IRQHandler [WEAK]
+ EXPORT DMA2_Channel5_IRQHandler [WEAK]
+ EXPORT CAN2_TX_IRQHandler [WEAK]
+ EXPORT CAN2_RX0_IRQHandler [WEAK]
+ EXPORT CAN2_RX1_IRQHandler [WEAK]
+ EXPORT CAN2_SCE_IRQHandler [WEAK]
+ EXPORT DMA2_Channel6_IRQHandler [WEAK]
+ EXPORT DMA2_Channel7_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT I2C4_EV_IRQHandler [WEAK]
+ EXPORT I2C4_ER_IRQHandler [WEAK]
+ EXPORT UART6_IRQHandler [WEAK]
+ EXPORT UART7_IRQHandler [WEAK]
+ EXPORT DMA1_Channel8_IRQHandler [WEAK]
+ EXPORT DMA2_Channel8_IRQHandler [WEAK]
+ EXPORT DVP_IRQHandler [WEAK]
+ EXPORT SAC_IRQHandler [WEAK]
+ EXPORT MMU_IRQHandler [WEAK]
+ EXPORT TSC_IRQHandler [WEAK]
+ EXPORT RSRAM_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+USB_HP_CAN1_TX_IRQHandler
+USB_LP_CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+USBWakeUp_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+RESERVE47_IRQHandler
+RESERVE48_IRQHandler
+SDIO_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+RESERVE61_IRQHandler
+RESERVE62_IRQHandler
+CAN2_TX_IRQHandler
+CAN2_RX0_IRQHandler
+CAN2_RX1_IRQHandler
+CAN2_SCE_IRQHandler
+RESERVE67_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+UART6_IRQHandler
+UART7_IRQHandler
+DMA1_Channel8_IRQHandler
+DMA2_Channel8_IRQHandler
+DVP_IRQHandler
+SAC_IRQHandler
+MMU_IRQHandler
+TSC_IRQHandler
+RESERVE82_IRQHandler
+RESERVE83_IRQHandler
+RESERVE84_IRQHandler
+RSRAM_IRQHandler
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/startup/startup_n32wb452_EWARM.s b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/startup/startup_n32wb452_EWARM.s
new file mode 100644
index 0000000000..d213ed8904
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/startup/startup_n32wb452_EWARM.s
@@ -0,0 +1,607 @@
+; ****************************************************************************
+; Copyright (c) 2019, Nations Technologies Inc.
+;
+; All rights reserved.
+; ****************************************************************************
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; - Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the disclaimer below.
+;
+; Nations name may not be used to endorse or promote products derived from
+; this software without specific prior written permission.
+;
+; DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+; DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+; OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; ****************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Tamper
+ DCD RTC_WKUP_IRQHandler ; RTC
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 & ADC2
+ DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
+ DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
+ DCD TIM8_BRK_IRQHandler ; TIM8 Break
+ DCD TIM8_UP_IRQHandler ; TIM8 Update
+ DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
+ DCD DEFAULT_IRQHandler ; RESERVE47
+ DCD DEFAULT_IRQHandler ; RESERVE48
+ DCD SDIO_IRQHandler ; SDIO
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_IRQHandler ; TIM6
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
+ DCD DEFAULT_IRQHandler ; RESERVE61
+ DCD DEFAULT_IRQHandler ; RESERVE62
+ DCD CAN2_TX_IRQHandler ; CAN2 TX
+ DCD CAN2_RX0_IRQHandler ; CAN2 RX0
+ DCD CAN2_RX1_IRQHandler ; CAN2 RX1
+ DCD CAN2_SCE_IRQHandler ; CAN2 SCE
+ DCD DEFAULT_IRQHandler ; RESERVE67
+ DCD DMA2_Channel6_IRQHandler ; DMA2 Channel6
+ DCD DMA2_Channel7_IRQHandler ; DMA2 Channel7
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD I2C4_EV_IRQHandler ; I2C4 event
+ DCD I2C4_ER_IRQHandler ; I2C4 error
+ DCD UART6_IRQHandler ; UART6
+ DCD UART7_IRQHandler ; UART7
+ DCD DMA1_Channel8_IRQHandler ; DMA1 Channel8
+ DCD DMA2_Channel8_IRQHandler ; DMA2 Channel8
+ DCD DVP_IRQHandler ; DVP
+ DCD SAC_IRQHandler ; SAC
+ DCD MMU_IRQHandler ; MMU
+ DCD TSC_IRQHandler ; TSC
+ DCD DEFAULT_IRQHandler ; RESERVE82
+ DCD DEFAULT_IRQHandler ; RESERVE83
+ DCD DEFAULT_IRQHandler ; RESERVE84
+ DCD RSRAM_IRQHandler ; R-SRAM parity error interrupt
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+ PUBWEAK TAMPER_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TAMPER_IRQHandler
+ B TAMPER_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC1_2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ADC1_2_IRQHandler
+ B ADC1_2_IRQHandler
+
+ PUBWEAK USB_HP_CAN1_TX_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USB_HP_CAN1_TX_IRQHandler
+ B USB_HP_CAN1_TX_IRQHandler
+
+ PUBWEAK USB_LP_CAN1_RX0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USB_LP_CAN1_RX0_IRQHandler
+ B USB_LP_CAN1_RX0_IRQHandler
+
+ PUBWEAK CAN1_RX1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN1_RX1_IRQHandler
+ B CAN1_RX1_IRQHandler
+
+ PUBWEAK CAN1_SCE_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN1_SCE_IRQHandler
+ B CAN1_SCE_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTCAlarm_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTCAlarm_IRQHandler
+ B RTCAlarm_IRQHandler
+
+ PUBWEAK USBWakeUp_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USBWakeUp_IRQHandler
+ B USBWakeUp_IRQHandler
+
+ PUBWEAK TIM8_BRK_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_BRK_IRQHandler
+ B TIM8_BRK_IRQHandler
+
+ PUBWEAK TIM8_UP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_UP_IRQHandler
+ B TIM8_UP_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_TRG_COM_IRQHandler
+ B TIM8_TRG_COM_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK SDIO_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SDIO_IRQHandler
+ B SDIO_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM6_IRQHandler
+ B TIM6_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel1_IRQHandler
+ B DMA2_Channel1_IRQHandler
+
+ PUBWEAK DMA2_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel2_IRQHandler
+ B DMA2_Channel2_IRQHandler
+
+ PUBWEAK DMA2_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel3_IRQHandler
+ B DMA2_Channel3_IRQHandler
+
+ PUBWEAK DMA2_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel4_IRQHandler
+ B DMA2_Channel4_IRQHandler
+
+ PUBWEAK DMA2_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel5_IRQHandler
+ B DMA2_Channel5_IRQHandler
+
+ PUBWEAK CAN2_TX_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN2_TX_IRQHandler
+ B CAN2_TX_IRQHandler
+
+ PUBWEAK CAN2_RX0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN2_RX0_IRQHandler
+ B CAN2_RX0_IRQHandler
+
+ PUBWEAK CAN2_RX1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN2_RX1_IRQHandler
+ B CAN2_RX1_IRQHandler
+
+ PUBWEAK CAN2_SCE_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN2_SCE_IRQHandler
+ B CAN2_SCE_IRQHandler
+
+ PUBWEAK DMA2_Channel6_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel6_IRQHandler
+ B DMA2_Channel6_IRQHandler
+
+ PUBWEAK DMA2_Channel7_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel7_IRQHandler
+ B DMA2_Channel7_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK I2C4_EV_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C4_EV_IRQHandler
+ B I2C4_EV_IRQHandler
+
+ PUBWEAK I2C4_ER_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C4_ER_IRQHandler
+ B I2C4_ER_IRQHandler
+
+ PUBWEAK UART6_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART6_IRQHandler
+ B UART6_IRQHandler
+
+ PUBWEAK UART7_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UART7_IRQHandler
+ B UART7_IRQHandler
+
+ PUBWEAK DMA1_Channel8_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel8_IRQHandler
+ B DMA1_Channel8_IRQHandler
+
+ PUBWEAK DMA2_Channel8_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel8_IRQHandler
+ B DMA2_Channel8_IRQHandler
+
+ PUBWEAK DVP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DVP_IRQHandler
+ B DVP_IRQHandler
+
+ PUBWEAK SAC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SAC_IRQHandler
+ B SAC_IRQHandler
+
+ PUBWEAK MMU_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MMU_IRQHandler
+ B MMU_IRQHandler
+
+ PUBWEAK TSC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TSC_IRQHandler
+ B TSC_IRQHandler
+
+ PUBWEAK RSRAM_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RSRAM_IRQHandler
+ B RSRAM_IRQHandler
+
+ PUBWEAK DEFAULT_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DEFAULT_IRQHandler
+ B DEFAULT_IRQHandler
+
+ END
+
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/startup/startup_n32wb452_gcc.s b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/startup/startup_n32wb452_gcc.s
new file mode 100644
index 0000000000..013e739c93
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/startup/startup_n32wb452_gcc.s
@@ -0,0 +1,506 @@
+/**
+ ****************************************************************************
+ Copyright (c) 2019, Nations Technologies Inc.
+
+ All rights reserved.
+ ****************************************************************************
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ - Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the disclaimer below.
+
+ Nations' name may not be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+ DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************
+ **/
+
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl entry
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_IRQHandler /* PVD through EXTI Line detection */
+ .word TAMPER_IRQHandler /* Tamper */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
+ .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
+ .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
+ .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
+ .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
+ .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
+ .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
+ .word ADC1_2_IRQHandler /* ADC1, ADC2 */
+ .word USB_HP_CAN1_TX_IRQHandler /* USB High Priority or CAN1 TX */
+ .word USB_LP_CAN1_RX0_IRQHandler /* USB Low Priority or CAN1 RX0 */
+ .word CAN1_RX1_IRQHandler /* CAN1 RX1 */
+ .word CAN1_SCE_IRQHandler /* CAN1 SCE */
+ .word EXTI9_5_IRQHandler /* EXTI Line 9..5 */
+ .word TIM1_BRK_IRQHandler /* TIM1 Break */
+ .word TIM1_UP_IRQHandler /* TIM1 Update */
+ .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */
+ .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
+ .word USBWakeUp_IRQHandler /* USB Wakeup from suspend */
+ .word TIM8_BRK_IRQHandler /* TIM8 Break */
+ .word TIM8_UP_IRQHandler /* TIM8 Update */
+ .word TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word ADC3_4_IRQHandler /* ADC3 & ADC4 */
+ .word XFMC_IRQHandler /* XFMC */
+ .word SDIO_IRQHandler /* SDIO */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TIM6_IRQHandler /* TIM6 */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word DMA2_Channel1_IRQHandler /* DMA2 Channel1 */
+ .word DMA2_Channel2_IRQHandler /* DMA2 Channel2 */
+ .word DMA2_Channel3_IRQHandler /* DMA2 Channel3 */
+ .word DMA2_Channel4_IRQHandler /* DMA2 Channel4 */
+ .word DMA2_Channel5_IRQHandler /* DMA2 Channel5 */
+ .word ETH_IRQHandler /* Ethernet global interrupt */
+ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line interrupt */
+ .word CAN2_TX_IRQHandler /* CAN2 TX */
+ .word CAN2_RX0_IRQHandler /* CAN2 RX0 */
+ .word CAN2_RX1_IRQHandler /* CAN2 RX1 */
+ .word CAN2_SCE_IRQHandler /* CAN2 SCE */
+ .word QSPI_IRQHandler /* QSPI */
+ .word DMA2_Channel6_IRQHandler /* DMA2 Channel6 */
+ .word DMA2_Channel7_IRQHandler /* DMA2 Channel7 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word I2C4_EV_IRQHandler /* I2C4 event */
+ .word I2C4_ER_IRQHandler /* I2C4 error */
+ .word UART6_IRQHandler /* UART6 */
+ .word UART7_IRQHandler /* UART7 */
+ .word DMA1_Channel8_IRQHandler /* DMA1 Channel8 */
+ .word DMA2_Channel8_IRQHandler /* DMA2 Channel8 */
+ .word DVP_IRQHandler /* DVP */
+ .word SAC_IRQHandler /* SAC */
+ .word MMU_IRQHandler /* MMU */
+ .word TSC_IRQHandler /* TSC */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak USB_HP_CAN1_TX_IRQHandler
+ .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+ .weak USB_LP_CAN1_RX0_IRQHandler
+ .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+ .weak CAN1_RX1_IRQHandler
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+ .weak CAN1_SCE_IRQHandler
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTCAlarm_IRQHandler
+ .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_IRQHandler
+ .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_IRQHandler
+ .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_IRQHandler
+ .thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_IRQHandler
+ .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak ADC3_4_IRQHandler
+ .thumb_set ADC3_4_IRQHandler,Default_Handler
+
+ .weak XFMC_IRQHandler
+ .thumb_set XFMC_IRQHandler,Default_Handler
+
+ .weak SDIO_IRQHandler
+ .thumb_set SDIO_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_IRQHandler
+ .thumb_set TIM6_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak ETH_IRQHandler
+ .thumb_set ETH_IRQHandler,Default_Handler
+
+ .weak ETH_WKUP_IRQHandler
+ .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+ .weak CAN2_TX_IRQHandler
+ .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+ .weak CAN2_RX0_IRQHandler
+ .thumb_set CAN2_RX0_IRQHandler,Default_Handler
+
+ .weak CAN2_RX1_IRQHandler
+ .thumb_set CAN2_RX1_IRQHandler,Default_Handler
+
+ .weak CAN2_SCE_IRQHandler
+ .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+ .weak QSPI_IRQHandler
+ .thumb_set QSPI_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel6_IRQHandler
+ .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel7_IRQHandler
+ .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak I2C4_EV_IRQHandler
+ .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+ .weak I2C4_ER_IRQHandler
+ .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+ .weak UART6_IRQHandler
+ .thumb_set UART6_IRQHandler,Default_Handler
+
+ .weak UART7_IRQHandler
+ .thumb_set UART7_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel8_IRQHandler
+ .thumb_set DMA1_Channel8_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel8_IRQHandler
+ .thumb_set DMA2_Channel8_IRQHandler,Default_Handler
+
+ .weak DVP_IRQHandler
+ .thumb_set DVP_IRQHandler,Default_Handler
+
+ .weak SAC_IRQHandler
+ .thumb_set SAC_IRQHandler,Default_Handler
+
+ .weak MMU_IRQHandler
+ .thumb_set MMU_IRQHandler,Default_Handler
+
+ .weak TSC_IRQHandler
+ .thumb_set TSC_IRQHandler,Default_Handler
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/system_n32wb452.c b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/system_n32wb452.c
new file mode 100644
index 0000000000..126995006d
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/system_n32wb452.c
@@ -0,0 +1,421 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file system_n32wb452.c
+ * @author Nations
+ * @version v1.0.2
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32wb452.h"
+
+/* Uncomment the line corresponding to the desired System clock (SYSCLK)
+ frequency (after reset the HSI is used as SYSCLK source)
+
+ IMPORTANT NOTE:
+ ==============
+ 1. After each device reset the HSI is used as System clock source.
+
+ 2. Please make sure that the selected System clock doesn't exceed your
+ device's maximum frequency.
+
+ 3. If none of the define below is enabled, the HSI is used as System clock
+ source.
+
+ 4. The System clock configuration functions provided within this file assume
+ that:
+ - For Low, Medium and High density Value line devices an external 8MHz
+ crystal is used to drive the System clock.
+ - For Low, Medium and High density devices an external 8MHz crystal is
+ used to drive the System clock.
+ - For Connectivity line devices an external 25MHz crystal is used to
+ drive the System clock. If you are using different crystal you have to adapt
+ those functions accordingly.
+ */
+
+#define SYSCLK_USE_HSI 0
+#define SYSCLK_USE_HSE 1
+#define SYSCLK_USE_HSI_PLL 2
+#define SYSCLK_USE_HSE_PLL 3
+
+#ifndef SYSCLK_FREQ
+#define SYSCLK_FREQ 144000000
+#endif
+
+#ifndef SYSCLK_SRC
+#define SYSCLK_SRC SYSCLK_USE_HSE_PLL
+#endif
+
+#if SYSCLK_SRC == SYSCLK_USE_HSI
+
+#if SYSCLK_FREQ != HSI_VALUE
+#error SYSCL_FREQ must be set to HSI_VALUE
+#endif
+
+#elif SYSCLK_SRC == SYSCLK_USE_HSE
+
+#ifndef HSE_VALUE
+#error HSE_VALUE must be defined!
+#endif
+
+#if SYSCLK_FREQ != HSE_VALUE
+#error SYSCL_FREQ must be set to HSE_VALUE
+#endif
+
+#elif SYSCLK_SRC == SYSCLK_USE_HSI_PLL
+
+#if (SYSCLK_FREQ % (HSI_VALUE / 2) == 0) && (SYSCLK_FREQ / (HSI_VALUE / 2) >= 2) \
+ && (SYSCLK_FREQ / (HSI_VALUE / 2) <= 32)
+
+#define PLLSRC_DIV 2
+#define PLL_MUL (SYSCLK_FREQ / (HSI_VALUE / 2))
+
+#else
+#error Cannot make a PLL multiply factor to SYSCLK_FREQ.
+#endif
+
+#elif SYSCLK_SRC == SYSCLK_USE_HSE_PLL
+
+#ifndef HSE_VALUE
+#error HSE_VALUE must be defined!
+#endif
+
+#if ((SYSCLK_FREQ % (HSE_VALUE / 2)) == 0) && (SYSCLK_FREQ / (HSE_VALUE / 2) >= 2) \
+ && (SYSCLK_FREQ / (HSE_VALUE / 2) <= 32)
+
+#define PLLSRC_DIV 2
+#define PLL_MUL (SYSCLK_FREQ / (HSE_VALUE / 2))
+
+#elif (SYSCLK_FREQ % HSE_VALUE == 0) && (SYSCLK_FREQ / HSE_VALUE >= 2) && (SYSCLK_FREQ / HSE_VALUE <= 32)
+
+#define PLLSRC_DIV 1
+#define PLL_MUL (SYSCLK_FREQ / HSE_VALUE)
+
+#else
+#error Cannot make a PLL multiply factor to SYSCLK_FREQ.
+#endif
+
+#else
+#error wrong value for SYSCLK_SRC
+#endif
+
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */
+
+/*******************************************************************************
+ * Clock Definitions
+ *******************************************************************************/
+uint32_t SystemCoreClock = SYSCLK_FREQ; /*!< System Clock Frequency (Core Clock) */
+
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+static void SetSysClock(void);
+
+#ifdef DATA_IN_ExtSRAM
+static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the Embedded Flash Interface, the PLL and update the
+ * SystemCoreClock variable.
+ * @note This function should be used only after reset.
+ */
+void SystemInit(void)
+{
+ /* FPU settings
+ * ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
+
+ /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+ /* Set HSIEN bit */
+ RCC->CTRL |= (uint32_t)0x00000001;
+
+ /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+ RCC->CFG &= (uint32_t)0xF8FFC000;
+
+ /* Reset HSEON, CLKSSEN and PLLEN bits */
+ RCC->CTRL &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CTRL &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRES/OTGFSPRE bits */
+ RCC->CFG &= (uint32_t)0xF700FFFF;
+
+ /* Reset CFG2 register */
+ RCC->CFG2 = 0x00003800;
+
+ /* Reset CFG3 register */
+ RCC->CFG3 = 0x00003840;
+
+ /* Disable all interrupts and clear pending bits */
+ RCC->CLKINT = 0x009F0000;
+
+ /* Enable ex mode */
+ RCC->APB1PCLKEN |= RCC_APB1PCLKEN_PWREN;
+ PWR->CTRL3 |= 0x00000001;
+ RCC->APB1PCLKEN &= (uint32_t)(~RCC_APB1PCLKEN_PWREN);
+
+ /* Enable ICACHE and Prefetch Buffer */
+ FLASH->AC |= (uint32_t)(FLASH_AC_ICAHEN | FLASH_AC_PRFTBFEN);
+
+#ifdef DATA_IN_ExtSRAM
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM */
+
+ /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+ /* Configure the Flash Latency cycles and enable prefetch buffer */
+ SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or
+ * configure other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any
+ * configuration based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the
+ * HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the
+ * HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the
+ * HSE_VALUE(**) or HSI_VALUE(*) multiplied by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in n32wb452.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in N32WB452.h file (default value
+ * 8 MHz or 25 MHz, depedning on the product used), user has to
+ * ensure that HSE_VALUE is same as the real frequency of the crystal used.
+ * Otherwise, this function may have wrong result.
+ *
+ * - The result of this function could be not correct when using
+ * fractional value for HSE crystal.
+ */
+void SystemCoreClockUpdate(void)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+ /* Get SYSCLK source
+ * -------------------------------------------------------*/
+ tmp = RCC->CFG & RCC_CFG_SCLKSTS;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x04: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x08: /* PLL used as system clock */
+
+ /* Get PLL clock source and multiplication factor
+ * ----------------------*/
+ pllmull = RCC->CFG & RCC_CFG_PLLMULFCT;
+ pllsource = RCC->CFG & RCC_CFG_PLLSRC;
+
+ if ((pllmull & RCC_CFG_PLLMULFCT_4) == 0)
+ {
+ pllmull = (pllmull >> 18) + 2; // PLLMUL[4]=0
+ }
+ else
+ {
+ pllmull = ((pllmull >> 18) - 496) + 1; // PLLMUL[4]=1
+ }
+
+ if (pllsource == 0x00)
+ {
+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ /* HSE selected as PLL clock entry */
+ if ((RCC->CFG & RCC_CFG_PLLHSEPRES) != (uint32_t)RESET)
+ { /* HSE oscillator clock divided by 2 */
+ SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ SystemCoreClock = HSE_VALUE * pllmull;
+ }
+ }
+
+ break;
+
+ default:
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+
+ /* Compute HCLK clock frequency ----------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFG & RCC_CFG_AHBPRES) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/**
+ * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1
+ * prescalers.
+ */
+static void SetSysClock(void)
+{
+ uint32_t rcc_cfgr = 0;
+ bool HSEStatus = 0;
+ uint32_t StartUpCounter = 0;
+
+#if SYSCLK_SRC == SYSCLK_USE_HSE || SYSCLK_SRC == SYSCLK_USE_HSE_PLL
+
+ /* Enable HSE */
+ RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CTRL & RCC_CTRL_HSERDF;
+ StartUpCounter++;
+ } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ HSEStatus = ((RCC->CTRL & RCC_CTRL_HSERDF) != RESET);
+ if (!HSEStatus)
+ {
+ /* If HSE fails to start-up, the application will have wrong clock
+ * configuration. User can add here some code to deal with this error */
+ SystemCoreClock = HSI_VALUE;
+ return;
+ }
+#endif
+
+ /* Flash wait state
+ 0: HCLK <= 32M
+ 1: HCLK <= 64M
+ 2: HCLK <= 96M
+ 3: HCLK <= 128M
+ 4: HCLK <= 144M
+ */
+ FLASH->AC &= (uint32_t)((uint32_t)~FLASH_AC_LATENCY);
+ FLASH->AC |= (uint32_t)((SYSCLK_FREQ - 1) / 32000000);
+
+ /* HCLK = SYSCLK */
+ RCC->CFG |= (uint32_t)RCC_CFG_AHBPRES_DIV1;
+
+ /* PCLK2 max 72M */
+ if (SYSCLK_FREQ > 72000000)
+ {
+ RCC->CFG |= (uint32_t)RCC_CFG_APB2PRES_DIV2;
+ }
+ else
+ {
+ RCC->CFG |= (uint32_t)RCC_CFG_APB2PRES_DIV1;
+ }
+
+ /* PCLK1 max 36M */
+ if (SYSCLK_FREQ > 72000000)
+ {
+ RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV4;
+ }
+ else if (SYSCLK_FREQ > 36000000)
+ {
+ RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV2;
+ }
+ else
+ {
+ RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV1;
+ }
+
+#if SYSCLK_SRC == SYSCLK_USE_HSE
+ /* Select HSE as system clock source */
+ RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW));
+ RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_HSE;
+
+ /* Wait till HSE is used as system clock source */
+ while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x04)
+ {
+ }
+#elif SYSCLK_SRC == SYSCLK_USE_HSI_PLL || SYSCLK_SRC == SYSCLK_USE_HSE_PLL
+
+ /* clear bits */
+ RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_PLLSRC | RCC_CFG_PLLHSEPRES | RCC_CFG_PLLMULFCT));
+
+ /* set PLL source */
+ rcc_cfgr = RCC->CFG;
+ rcc_cfgr |= (SYSCLK_SRC == SYSCLK_USE_HSI_PLL ? RCC_CFG_PLLSRC_HSI_DIV2 : RCC_CFG_PLLSRC_HSE);
+
+#if SYSCLK_SRC == SYSCLK_USE_HSE_PLL
+ rcc_cfgr |= (PLLSRC_DIV == 1 ? RCC_CFG_PLLHSEPRES_HSE : RCC_CFG_PLLHSEPRES_HSE_DIV2);
+#endif
+
+ /* set PLL multiply factor */
+#if PLL_MUL <= 16
+ rcc_cfgr |= (PLL_MUL - 2) << 18;
+#else
+ rcc_cfgr |= ((PLL_MUL - 17) << 18) | (1 << 27);
+#endif
+
+ RCC->CFG = rcc_cfgr;
+
+ /* Enable PLL */
+ RCC->CTRL |= RCC_CTRL_PLLEN;
+
+ /* Wait till PLL is ready */
+ while ((RCC->CTRL & RCC_CTRL_PLLRDF) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW));
+ RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x08)
+ {
+ }
+#endif
+}
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/system_n32wb452.h b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/system_n32wb452.h
new file mode 100644
index 0000000000..2895a681f1
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/system_n32wb452.h
@@ -0,0 +1,59 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file system_n32wb452.h
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __SYSTEM_N32WB452_H__
+#define __SYSTEM_N32WB452_H__
+
+#include
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup N32WB452_System
+ * @{
+ */
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_N32WB452_H__ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/SConscript b/bsp/n32/libraries/N32WB452_Firmware_Library/SConscript
new file mode 100644
index 0000000000..35dab246b3
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/SConscript
@@ -0,0 +1,66 @@
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+
+src = Split('''
+CMSIS/device/system_n32wb452.c
+n32wb452_std_periph_driver/src/n32wb452_gpio.c
+n32wb452_std_periph_driver/src/n32wb452_rcc.c
+n32wb452_std_periph_driver/src/n32wb452_exti.c
+n32wb452_std_periph_driver/src/misc.c
+''')
+
+if GetDepend(['RT_USING_SERIAL']):
+ src += ['n32wb452_std_periph_driver/src/n32wb452_usart.c']
+
+if GetDepend(['RT_USING_I2C']):
+ src += ['n32wb452_std_periph_driver/src/n32wb452_i2c.c']
+
+if GetDepend(['RT_USING_SPI']):
+ src += ['n32wb452_std_periph_driver/src/n32wb452_spi.c']
+
+if GetDepend(['RT_USING_CAN']):
+ src += ['n32wb452_std_periph_driver/src/n32wb452_can.c']
+
+if GetDepend(['RT_USING_ADC']):
+ src += ['n32wb452_std_periph_driver/src/n32wb452_adc.c']
+
+if GetDepend(['RT_USING_DAC']):
+ src += ['n32wb452_std_periph_driver/src/n32wb452_dac.c']
+
+if GetDepend(['RT_USING_HWTIMER']):
+ src += ['n32wb452_std_periph_driver/src/n32wb452_tim.c']
+
+if GetDepend(['RT_USING_RTC']):
+ src += ['n32wb452_std_periph_driver/src/n32wb452_rtc.c']
+ src += ['n32wb452_std_periph_driver/src/n32wb452_pwr.c']
+ src += ['n32wb452_std_periph_driver/src/n32wb452_bkp.c']
+
+if GetDepend(['RT_USING_WDT']):
+ src += ['n32wb452_std_periph_driver/src/n32wb452_wwdg.c']
+ src += ['n32wb452_std_periph_driver/src/n32wb452_iwdg.c']
+
+if GetDepend(['RT_USING_SDIO']):
+ src += ['n32wb452_std_periph_driver/src/n32wb452_sdio.c']
+
+if GetDepend(['RT_USING_BSP_USB']):
+ path += [cwd + '/n32wb452_usbfs_driver/inc']
+ src += [cwd + '/n32wb452_usbfs_driver/src']
+
+path = [
+ cwd + '/CMSIS/device',
+ cwd + '/CMSIS/core',
+ cwd + '/n32wb452_std_periph_driver/inc',]
+
+CPPDEFINES = ['USE_STDPERIPH_DRIVER']
+
+
+
+group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_aes.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_aes.h
new file mode 100644
index 0000000000..d9652dabb5
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_aes.h
@@ -0,0 +1,126 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_aes.h
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32WB452_AES_H__
+#define __N32WB452_AES_H__
+
+#include
+/** @addtogroup N32WB452_Algorithm_Library
+ * @{
+ */
+
+/** @addtogroup AES
+ * @brief AES symmetrical cipher algorithm
+ * @{
+ */
+
+#define AES_ECB (0x11111111)
+#define AES_CBC (0x22222222)
+#define AES_CTR (0x33333333)
+
+#define AES_ENC (0x44444444)
+#define AES_DEC (0x55555555)
+
+enum
+{
+ AES_Crypto_OK = 0x0, //AES opreation success
+ AES_Init_OK = 0x0, //AES Init opreation success
+ AES_Crypto_ModeError = 0x5a5a5a5a, //Working mode error(Neither ECB nor CBC nor CTR)
+ AES_Crypto_EnOrDeError, //En&De error(Neither encryption nor decryption)
+ AES_Crypto_ParaNull, // the part of input(output/iv) Null
+ AES_Crypto_LengthError, // if Working mode is ECB or CBC,the length of input message must be 4 times and cannot be zero;
+ //if Working mode is CTR,the length of input message cannot be zero; othets: return AES_Crypto_LengthError
+
+ AES_Crypto_KeyLengthError, //the keyWordLen must be 4 or 6 or 8; othets:return AES_Crypto_KeyLengthError
+ AES_Crypto_UnInitError, //AES uninitialized
+};
+
+typedef struct
+{
+ uint32_t *in; // the part of input to be encrypted or decrypted
+ uint32_t *iv; // the part of initial vector
+ uint32_t *out; // the part of out
+ uint32_t *key; // the part of key
+ uint32_t keyWordLen; // the length(by word) of key
+ uint32_t inWordLen; // the length(by word) of plaintext or cipher
+ uint32_t En_De; // 0x44444444- encrypt, 0x55555555 - decrypt
+ uint32_t Mode; // 0x11111111 - ECB, 0x22222222 - CBC, 0x33333333 - CTR
+}AES_PARM;
+
+ /**
+ * @brief AES_Init
+ * @return AES_Init_OK, AES Init success; othets: AES Init fail
+ * @note
+ */
+
+uint32_t AES_Init(AES_PARM *parm);
+
+/**
+ * @brief AES crypto
+ * @param[in] parm pointer to AES context and the detail please refer to struct AES_PARM in AES.h
+ * @return AES_Crypto_OK, AES crypto success; othets: AES crypto fail(reference to the definition by enum variation)
+ * @note 1.Please refer to the demo in user guidance before using this function
+ * 2.Input and output can be the same buffer
+ * 3. IV can be NULL when ECB mode
+ * 4. If Working mode is ECB or CBC,the length of input message must be 4 times and cannot be zero;
+ * if Working mode is CTR,the length of input message cannot be zero;
+ * 5. If the input is in byte, make sure align by word.
+ */
+uint32_t AES_Crypto(AES_PARM *parm);
+
+/**
+ * @brief AES close
+ * @return none
+ * @note if you want to close AES algorithm, this function can be recalled.
+ */
+void AES_Close(void);
+
+/**
+ * @brief Get AES lib version
+ * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
+ * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
+ * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
+ * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
+ * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
+ * @return none
+ * @1.You can recall this function to get AES lib information
+ */
+void AES_Version(uint8_t *type, uint8_t *customer, uint8_t date[3], uint8_t *version);
+
+
+
+
+#endif
+
+
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_algo_common.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_algo_common.h
new file mode 100644
index 0000000000..92864c8f36
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_algo_common.h
@@ -0,0 +1,154 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_algo_common.h
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32WB452_ALGO_COMMON_H__
+#define __N32WB452_ALGO_COMMON_H__
+
+#include
+/** @addtogroup N32WB452_Algorithm_Library
+ * @{
+ */
+enum{
+ Cpy_OK=0,//copy success
+ SetZero_OK = 0,//set zero success
+ XOR_OK = 0, //XOR success
+ Reverse_OK = 0, //Reverse success
+ Cmp_EQUAL = 0, //Two big number are equal
+ Cmp_UNEQUAL = 1, //Two big number are not equal
+
+};
+
+/**
+ * @brief disturb the sequence order
+ * @param[in] order pointer to the sequence to be disturbed
+ * @param[in] rand pointer to random number
+ * @param[in] the length of order
+ * @return RandomSort_OK: disturb order success; Others: disturb order fail;
+ * @note
+ */
+uint32_t RandomSort(uint8_t *order, const uint8_t *rand, uint32_t len);
+
+/**
+ * @brief Copy data by byte
+ * @param[in] dst pointer to destination data
+ * @param[in] src pointer to source data
+ * @param[in] byte length
+ * @return Cpy_OK: success; others: fail.
+ * @note 1. dst and src cannot be same
+ */
+uint32_t Cpy_U8(uint8_t *dst, uint8_t *src, uint32_t byteLen);
+
+/**
+ * @brief Copy data by word
+ * @param[in] dst pointer to destination data
+ * @param[in] src pointer to source data
+ * @param[in] word length
+ * @return Cpy_OK: success; others: fail.
+ * @note 1. dst and src must be aligned by word
+ */
+uint32_t Cpy_U32(uint32_t *dst, const uint32_t *src, uint32_t wordLen);
+
+ /**
+ * @brief XOR
+ * @param[in] a pointer to one data to be XORed
+ * @param[in] b pointer to another data to be XORed
+ * @param[in] the length of order
+ * @return XOR_OK: operation success; Others: operation fail;
+ * @note
+ */
+uint32_t XOR_U8(uint8_t *a, uint8_t *b, uint8_t *c, uint32_t byteLen);
+
+ /**
+ * @brief XORed two u32 arrays
+ * @param[in] a pointer to one data to be XORed
+ * @param[in] b pointer to another data to be XORed
+ * @param[in] the length of order
+ * @return XOR_OK: operation success; Others: operation fail;
+ * @note
+ */
+uint32_t XOR_U32(uint32_t *a,uint32_t *b,uint32_t *c,uint32_t wordLen);
+
+/**
+ * @brief set zero by byte
+ * @param[in] dst pointer to the address to be set zero
+ * @param[in] byte length
+ * @return SetZero_OK: success; others: fail.
+ * @note
+ */
+uint32_t SetZero_U8(uint8_t *dst, uint32_t byteLen);
+
+/**
+ * @brief set zero by word
+ * @param[in] dst pointer to the address to be set zero
+ * @param[in] word length
+ * @return SetZero_OK: success; others: fail.
+ * @note
+ */
+uint32_t SetZero_U32(uint32_t *dst, uint32_t wordLen);
+
+/**
+ * @brief reverse byte order of every word, the words stay the same
+ * @param[in] dst pointer to the destination address
+ * @param[in] src pointer to the source address
+ * @param[in] word length
+ * @return Reverse_OK: success; others: fail.
+ * @note 1.dst and src can be same
+ */
+uint32_t ReverseBytesInWord_U32(uint32_t *dst, const uint32_t *src, uint32_t wordLen);
+
+/**
+ * @brief compare two big number
+ * @param[in] a pointer to one big number
+ * @param[in] word length of a
+ * @param[in] b pointer to another big number
+ * @param[in] word length of b
+ * @return Cmp_UNEQUAL:a!=b;Cmp_EQUAL: a==b.
+ *
+ */
+int32_t Cmp_U32(const uint32_t *a, uint32_t aWordLen, const uint32_t *b, uint32_t bWordLen);
+
+/**
+ * @brief compare two big number
+ * @param[in] a pointer to one big number
+ * @param[in] word length of a
+ * @param[in] b pointer to another big number
+ * @param[in] word length of b
+ * @return Cmp_UNEQUAL:a!=b;Cmp_EQUAL: a==b.
+ *
+ */
+int32_t Cmp_U8(const uint8_t *a, uint32_t aByteLen, const uint8_t *b, uint32_t bByteLen);
+
+
+#endif
+
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_des.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_des.h
new file mode 100644
index 0000000000..0e09f5e855
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_des.h
@@ -0,0 +1,119 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_des.h
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32WB452_DES_H__
+#define __N32WB452_DES_H__
+#include
+/** @addtogroup N32WB452_Algorithm_Library
+ * @{
+ */
+
+/** @addtogroup DES
+ * @brief DES symmetrical cipher algorithm
+ * @{
+ */
+#define DES_ECB (0x11111111)
+#define DES_CBC (0x22222222)
+
+
+#define DES_ENC (0x33333333)
+#define DES_DEC (0x44444444)
+
+#define DES_KEY (0x55555555)
+#define TDES_2KEY (0x66666666)
+#define TDES_3KEY (0x77777777)
+
+enum DES
+{
+ DES_Crypto_OK = 0x0, //DES/TDES opreation success
+ DES_Init_OK = 0x0, //DES/TDES Init opreation success
+ DES_Crypto_ModeError = 0x5a5a5a5a, //Working mode error(Neither ECB nor CBC)
+ DES_Crypto_EnOrDeError, //En&De error(Neither encryption nor decryption)
+ DES_Crypto_ParaNull, // the part of input(output/iv) Null
+ DES_Crypto_LengthError, //the length of input message must be 2 times and cannot be zero
+ DES_Crypto_KeyError, //keyMode error(Neither DES_KEY nor TDES_2KEY nor TDES_3KEY)
+ DES_Crypto_UnInitError, //DES/TDES uninitialized
+};
+
+typedef struct
+{
+ uint32_t *in; // the part of input to be encrypted or decrypted
+ uint32_t *iv; // the part of initial vector
+ uint32_t *out; // the part of out
+ uint32_t *key; // the part of key
+ uint32_t inWordLen; // the length(by word) of plaintext or cipher
+ uint32_t En_De; // 0x33333333- encrypt, 0x44444444 - decrypt
+ uint32_t Mode; // 0x11111111 - ECB, 0x22222222 - CBC
+ uint32_t keyMode; //TDES key mode: 0x55555555-key,0x66666666-2key, 0x77777777-3key
+}DES_PARM;
+
+ /**
+ * @brief DES_Init
+ * @return DES_Init_OK, DES/TDES Init success; othets: DES/TDES Init fail
+ * @note
+ */
+uint32_t DES_Init(DES_PARM *parm);
+
+/**
+ * @brief DES crypto
+ * @param[in] parm pointer to DES/TDES context and the detail please refer to struct DES_PARM in DES.h
+ * @return DES_Crypto_OK, DES/TDES crypto success; othets: DES/TDES crypto fail(reference to the definition by enum variation)
+ * @note 1.Please refer to the demo in user guidance before using this function
+ * 2.Input and output can be the same buffer
+ * 3. IV can be NULL when ECB mode
+ * 4. The word lengrh of message must be as times as 2.
+ * 5. If the input is in byte, make sure align by word.
+ */
+uint32_t DES_Crypto(DES_PARM *parm);
+
+/**
+ * @brief DES close
+ * @return none
+ * @note if you want to close DES algorithm, this function can be recalled.
+ */
+void DES_Close(void);
+
+/**
+ * @brief Get DES/TDES lib version
+ * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
+ * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
+ * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
+ * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
+ * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
+ * @return none
+ * @1.You can recall this function to get DES/TDES lib information
+ */
+void DES_Version(uint8_t *type, uint8_t *customer, uint8_t date[3], uint8_t *version);
+
+#endif
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_hash.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_hash.h
new file mode 100644
index 0000000000..98798c51e6
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_hash.h
@@ -0,0 +1,218 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_hash.h
+ * @author Nations
+ * @version v1.0.1
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32WB452_HASH_H__
+#define __N32WB452_HASH_H__
+
+#include
+/** @addtogroup N32WB452_Algorithm_Library
+ * @{
+ */
+
+/** @addtogroup HASH
+ * @brief Message digest algorithms
+ * @{
+ */
+#define ALG_SHA1 (uint16_t)(0x0004)
+#define ALG_SHA224 (uint16_t)(0x000A)
+#define ALG_SHA256 (uint16_t)(0x000B)
+#define ALG_MD5 (uint16_t)(0x000C)
+#define ALG_SM3 (uint16_t)(0x0012)
+
+enum
+{
+ HASH_SEQUENCE_TRUE = 0x0105A5A5,//save IV
+ HASH_SEQUENCE_FALSE = 0x010A5A5A, //not save IV
+ HASH_Init_OK = 0,//hash init success
+ HASH_Start_OK = 0,//hash update success
+ HASH_Update_OK = 0,//hash update success
+ HASH_Complete_OK = 0,//hash complete success
+ HASH_Close_OK = 0,//hash close success
+ HASH_ByteLenPlus_OK = 0,//byte length plus success
+ HASH_PadMsg_OK = 0,//message padding success
+ HASH_ProcMsgBuf_OK = 0, //message processing success
+ SHA1_Hash_OK = 0,//sha1 operation success
+ SM3_Hash_OK = 0,//sm3 operation success
+ SHA224_Hash_OK = 0,//sha224 operation success
+ SHA256_Hash_OK = 0,//sha256 operation success
+ MD5_Hash_OK = 0,//MD5 operation success
+
+ HASH_Init_ERROR = 0x01044400,//hash init error
+ HASH_Start_ERROR, //hash start error
+ HASH_Update_ERROR, //hash update error
+ HASH_ByteLenPlus_ERROR,//hash byte plus error
+};
+
+struct _HASH_CTX_;
+
+typedef struct
+{
+ const uint16_t HashAlgID;//choice hash algorithm
+ const uint32_t * const K, KLen;//K and word length of K
+ const uint32_t * const IV, IVLen;//IV and word length of IV
+ const uint32_t HASH_SACCR, HASH_HASHCTRL;//relate registers
+ const uint32_t BlockByteLen, BlockWordLen; //byte length of block, word length of block
+ const uint32_t DigestByteLen, DigestWordLen; //byte length of digest,word length of digest
+ const uint32_t Cycle; //interation times
+ uint32_t (* const ByteLenPlus)(uint32_t *, uint32_t); //function pointer
+ uint32_t (* const PadMsg)(struct _HASH_CTX_ *); //function pointer
+}HASH_ALG;
+
+typedef struct _HASH_CTX_
+{
+ const HASH_ALG *hashAlg;//pointer to HASH_ALG
+ uint32_t sequence; // TRUE if the IV should be saved
+ uint32_t IV[16];
+ uint32_t msgByteLen[4];
+ uint8_t msgBuf[128+4];
+ uint32_t msgIdx;
+}HASH_CTX;
+
+extern const HASH_ALG HASH_ALG_SHA1[1];
+extern const HASH_ALG HASH_ALG_SHA224[1];
+extern const HASH_ALG HASH_ALG_SHA256[1];
+extern const HASH_ALG HASH_ALG_MD5[1];
+extern const HASH_ALG HASH_ALG_SM3[1];
+
+/**
+ * @brief Hash init
+ * @param[in] ctx pointer to HASH_CTX struct
+ * @return HASH_Init_OK, Hash init success; othets: Hash init fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ */
+uint32_t HASH_Init(HASH_CTX *ctx);
+
+/**
+ * @brief Hash start
+ * @param[in] ctx pointer to HASH_CTX struct
+ * @return HASH_Start_OK, Hash start success; othets: Hash start fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ * 2.HASH_Init() should be recalled before use this function
+ */
+uint32_t HASH_Start(HASH_CTX *ctx);
+
+/**
+ * @brief Hash update
+ * @param[in] ctx pointer to HASH_CTX struct
+ * @param[in] in pointer to message
+ * @param[out] out pointer tohash result,digest
+ * @return HASH_Update_OK, Hash update success; othets: Hash update fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ * 2.HASH_Init() and HASH_Start() should be recalled before use this function
+ */
+uint32_t HASH_Update(HASH_CTX *ctx, uint8_t *in, uint32_t byteLen);
+
+/**
+ * @brief Hash complete
+ * @param[in] ctx pointer to HASH_CTX struct
+ * @param[out] out pointer tohash result,digest
+ * @return HASH_Complete_OK, Hash complete success; othets: Hash complete fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ * 2.HASH_Init(), HASH_Start() and HASH_Update() should be recalled before use this function
+ */
+uint32_t HASH_Complete(HASH_CTX *ctx, uint8_t *out);
+
+/**
+ * @brief Hash close
+ * @return HASH_Close_OK, Hash close success; othets: Hash close fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ */
+uint32_t HASH_Close(void);
+
+/**
+ * @brief SM3 Hash for 256bits digest
+ * @param[in] in pointer to message
+ * @param[in] byte length of in
+ * @param[out] out pointer tohash result,digest
+ * @return SM3_Hash_OK, SM3 hash success; othets: SM3 hash fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ */
+uint32_t SM3_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
+
+
+/**
+ * @brief SHA1 Hash
+ * @param[in] in pointer to message
+ * @param[in] byte length of in
+ * @param[out] out pointer tohash result,digest
+ * @return SHA1_Hash_OK, SHA1 hash success; othets: SHA1 hash fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ */
+uint32_t SHA1_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
+
+/**
+ * @brief SHA224 Hash
+ * @param[in] in pointer to message
+ * @param[in] byte length of in
+ * @param[out] out pointer tohash result,digest
+ * @return SHA224_Hash_OK, SHA224 hash success; othets: SHA224 hash fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ */
+uint32_t SHA224_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
+
+
+/**
+ * @brief SHA256 Hash
+ * @param[in] in pointer to message
+ * @param[in] byte length of in
+ * @param[out] out pointer tohash result,digest
+ * @return SHA256_Hash_OK, SHA256 hash success; othets: SHA256 hash fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ */
+uint32_t SHA256_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
+
+/**
+ * @brief MD5 Hash
+ * @param[in] in pointer to message
+ * @param[in] byte length of in
+ * @param[in] out pointer tohash result,digest
+ * @return MD5_Hash_OK, MD5 hash success; othets: MD5 hash fail
+ * @note 1.Please refer to the demo in user guidance before using this function
+ */
+uint32_t MD5_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
+
+/**
+ * @brief Get HASH lib version
+ * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
+ * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
+ * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
+ * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
+ * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
+ * @return none
+ * @1.You can recall this function to get RSA lib information
+ */
+void HASH_Version(uint8_t *type, uint8_t *customer, uint8_t date[3], uint8_t *version);
+
+
+#endif
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_rng.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_rng.h
new file mode 100644
index 0000000000..66dc0877b1
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_rng.h
@@ -0,0 +1,93 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_rng.h
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32WB452_RNG_H__
+#define __N32WB452_RNG_H__
+
+#include
+
+/** @addtogroup N32WB452_Algorithm_Library
+ * @{
+ */
+
+/** @addtogroup RNG
+ * @brief Random number generator
+ * @{
+ */
+
+
+
+enum{
+ RNG_OK = 0x5a5a5a5a,
+ LENError = 0x311ECF50, //RNG generation of key length error
+ ADDRNULL = 0x7A9DB86C, // This address is empty
+};
+
+
+//u32 RNG_init(void);
+/**
+ * @brief Get pseudo random number
+ * @param[out] rand pointer to random number
+ * @param[in] the wordlen of random number
+ * @param[in] the seed, can be NULL
+ * @return RNG_OK:get random number success; othets: get random number fail
+ * @note
+ */
+uint32_t GetPseudoRand_U32(uint32_t *rand, uint32_t wordLen,uint32_t seed[2]);
+
+
+/**
+ * @brief Get true random number
+ * @param[out] rand pointer to random number
+ * @param[in] the wordlen of random number
+ * @return RNG_OK:get random number success; othets: get random number fail
+ * @note
+ */
+uint32_t GetTrueRand_U32(uint32_t *rand, uint32_t wordLen);
+
+/**
+ * @brief Get RNG lib version
+ * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
+ * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
+ * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
+ * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
+ * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
+ * @return none
+ * @1.You can recall this function to get RSA lib information
+ */
+void RNG_Version(uint8_t *type, uint8_t *customer, uint8_t date[3], uint8_t *version);
+
+#endif
+
+
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/att.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/att.h
new file mode 100644
index 0000000000..d9b0769410
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/att.h
@@ -0,0 +1,1136 @@
+/**
+ ****************************************************************************************
+ *
+ * @file att.h
+ *
+ * @brief Header file - ATT.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef ATT_H_
+#define ATT_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup ATT Attribute Protocol
+ * @ingroup HOST
+ * @brief Attribute Protocol.
+ *
+ * The ATT block contains the procedures for discovering, reading, writing
+ * and indicating attributes to peer device . It also defines a number of items
+ * that caters to the security aspect of the block as access to some information
+ * may require both authorization and an authenticated and encrypted physical
+ * link before an attribute can be read or written
+ *
+ * @{
+ *
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/// Macro used to convert CPU integer define to LSB first 16-bits UUID
+#define ATT_UUID_16(uuid) (uuid)
+
+/// Invalid attribute handle
+#define ATT_INVALID_HDL (0x0000)
+/// Invalid attribute idx (used for profiles)
+#define ATT_INVALID_IDX (0xff)
+
+#define ATT_1ST_REQ_START_HDL 0x0001
+#define ATT_1ST_REQ_END_HDL 0xFFFF
+
+/// Maximum possible attribute handle
+#define ATT_MAX_ATTR_HDL ATT_1ST_REQ_END_HDL
+
+/// Offset of value in signed PDU
+#define ATT_SIGNED_PDU_VAL_OFFSET 0x03
+
+/// Attribute Features
+#define ATT_SERVER_CONFIG 0x0001
+#define ATT_SERVICE_DISC 0x0002
+#define ATT_RELATIONSHIP_DISC 0x0004
+#define ATT_CHAR_DISC 0x0008
+#define ATT_CHAR_DESC_DISC 0x0010
+#define ATT_RD_CHAR_VALUE 0x0020
+#define ATT_WR_CHAR_VALUE 0x0040
+#define ATT_NOTIF_CHAR_VALUE 0x0080
+#define ATT_IND_CHAR_VALUE 0x0100
+#define ATT_RD_CHAR_DESC 0x0200
+#define ATT_WR_CHAR_DESC 0x0400
+
+/// Length, number, offset defines
+#define ATT_SVC_VALUE_MAX_LEN 0x0030
+#define ATT_CHAR_NAME_MAX_LEN 0x0030
+#define ATT_UUID_16_LEN 0x0002
+#define ATT_UUID_32_LEN 0x0004
+#define ATT_UUID_128_LEN 0x0010
+
+/// offset - l2cap header and ATT code
+#define ATT_PDU_DATA_OFFSET 0x05
+
+/// Characteristic Properties Bit
+#define ATT_CHAR_PROP_BCAST 0x01
+#define ATT_CHAR_PROP_RD 0x02
+#define ATT_CHAR_PROP_WR_NO_RESP 0x04
+#define ATT_CHAR_PROP_WR 0x08
+#define ATT_CHAR_PROP_NTF 0x10
+#define ATT_CHAR_PROP_IND 0x20
+#define ATT_CHAR_PROP_AUTH 0x40
+#define ATT_CHAR_PROP_EXT_PROP 0x80
+/// Invalid Attribute Handle
+#define ATT_INVALID_SEARCH_HANDLE 0x0000
+#define ATT_INVALID_HANDLE 0x0000
+/// Read Information Request
+#define ATT_UUID_FILTER_0 0x00
+#define ATT_UUID_FILTER_2 0x02
+#define ATT_UUID_FILTER_16 0x10
+/// Read Information Response
+#define ATT_FORMAT_LEN 0x0001
+#define ATT_FORMAT_16BIT_UUID 0x01
+#define ATT_FORMAT_128BIT_UUID 0x02
+/// For No fix length PDU
+#define ATT_HANDLE_LEN 0x0002
+#define ATT_EACHLEN_LEN 0x0001
+#define ATT_PROP_LEN 0x0001
+#define ATT_CODE_LEN 0x0001
+#define ATT_CODE_AND_DATA_LEN 0x0002
+#define ATT_CODE_AND_HANDLE_LEN 0x0003
+#define ATT_CODE_AND_HANDLE_LEN_AND_OFFSET 0x0005
+#define ATT_SIGNATURE_LEN 0x0C
+
+/// extended characteristics
+#define ATT_EXT_RELIABLE_WRITE 0x0001
+#define ATT_EXT_WRITABLE_AUX 0x0002
+#define ATT_EXT_RFU 0xFFFC
+
+/// PDU size for error response
+#define ATT_ERROR_RESP_LEN 0x05
+
+/// Offset of value in signed PDU
+#define ATT_SIGNED_PDU_VAL_OFFSET 0x03
+
+
+
+#define ATT_BT_UUID_128 {0xFB, 0x34, 0x9B, 0x5F, 0x80, 0x00, 0x00, 0x80, \
+ 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+
+
+
+/* Attribute Specification Defines */
+
+/// Common 16-bit Universal Unique Identifier
+enum {
+ ATT_INVALID_UUID = ATT_UUID_16(0x0000),
+ /*----------------- SERVICES ---------------------*/
+ /// Generic Access Profile
+ ATT_SVC_GENERIC_ACCESS = ATT_UUID_16(0x1800),
+ /// Attribute Profile
+ ATT_SVC_GENERIC_ATTRIBUTE = ATT_UUID_16(0x1801),
+ /// Immediate alert Service
+ ATT_SVC_IMMEDIATE_ALERT = ATT_UUID_16(0x1802),
+ /// Link Loss Service
+ ATT_SVC_LINK_LOSS = ATT_UUID_16(0x1803),
+ /// Tx Power Service
+ ATT_SVC_TX_POWER = ATT_UUID_16(0x1804),
+ /// Current Time Service Service
+ ATT_SVC_CURRENT_TIME = ATT_UUID_16(0x1805),
+ /// Reference Time Update Service
+ ATT_SVC_REF_TIME_UPDATE = ATT_UUID_16(0x1806),
+ /// Next DST Change Service
+ ATT_SVC_NEXT_DST_CHANGE = ATT_UUID_16(0x1807),
+ /// Glucose Service
+ ATT_SVC_GLUCOSE = ATT_UUID_16(0x1808),
+ /// Health Thermometer Service
+ ATT_SVC_HEALTH_THERMOM = ATT_UUID_16(0x1809),
+ /// Device Information Service
+ ATT_SVC_DEVICE_INFO = ATT_UUID_16(0x180A),
+ /// Heart Rate Service
+ ATT_SVC_HEART_RATE = ATT_UUID_16(0x180D),
+ /// Phone Alert Status Service
+ ATT_SVC_PHONE_ALERT_STATUS = ATT_UUID_16(0x180E),
+ /// Battery Service
+ ATT_SVC_BATTERY_SERVICE = ATT_UUID_16(0x180F),
+ /// Blood Pressure Service
+ ATT_SVC_BLOOD_PRESSURE = ATT_UUID_16(0x1810),
+ /// Alert Notification Service
+ ATT_SVC_ALERT_NTF = ATT_UUID_16(0x1811),
+ /// HID Service
+ ATT_SVC_HID = ATT_UUID_16(0x1812),
+ /// Scan Parameters Service
+ ATT_SVC_SCAN_PARAMETERS = ATT_UUID_16(0x1813),
+ /// Running Speed and Cadence Service
+ ATT_SVC_RUNNING_SPEED_CADENCE = ATT_UUID_16(0x1814),
+ /// Cycling Speed and Cadence Service
+ ATT_SVC_CYCLING_SPEED_CADENCE = ATT_UUID_16(0x1816),
+ /// Cycling Power Service
+ ATT_SVC_CYCLING_POWER = ATT_UUID_16(0x1818),
+ /// Location and Navigation Service
+ ATT_SVC_LOCATION_AND_NAVIGATION = ATT_UUID_16(0x1819),
+ /// Environmental Sensing Service
+ ATT_SVC_ENVIRONMENTAL_SENSING = ATT_UUID_16(0x181A),
+ /// Body Composition Service
+ ATT_SVC_BODY_COMPOSITION = ATT_UUID_16(0x181B),
+ /// User Data Service
+ ATT_SVC_USER_DATA = ATT_UUID_16(0x181C),
+ /// Weight Scale Service
+ ATT_SVC_WEIGHT_SCALE = ATT_UUID_16(0x181D),
+ /// Bond Management Service
+ ATT_SVC_BOND_MANAGEMENT = ATT_UUID_16(0x181E),
+ /// Continuous Glucose Monitoring Service
+ ATT_SVC_CONTINUOUS_GLUCOSE_MONITORING = ATT_UUID_16(0x181F),
+ /// Internet Protocol Support Service
+ ATT_SVC_IP_SUPPORT = ATT_UUID_16(0x1820),
+ /// Indoor Positioning Service
+ ATT_SVC_INDOOR_POSITIONING = ATT_UUID_16(0x1821),
+ /// Pulse Oximeter Service
+ ATT_SVC_PULSE_OXIMETER = ATT_UUID_16(0x1822),
+ /// HTTP Proxy Service
+ ATT_SVC_HTTP_PROXY = ATT_UUID_16(0x1823),
+ /// Transport Discovery Service
+ ATT_SVC_TRANSPORT_DISCOVERY = ATT_UUID_16(0x1824),
+ /// Object Transfer Service
+ ATT_SVC_OBJECT_TRANSFER = ATT_UUID_16(0x1825),
+ //USER-DEFINED by wq
+ ATT_SVC_DATA_TRANSFER = ATT_UUID_16(0xFF00),
+
+ /*------------------- UNITS ---------------------*/
+ /// No defined unit
+ ATT_UNIT_UNITLESS = ATT_UUID_16(0x2700),
+ /// Length Unit - Metre
+ ATT_UNIT_METRE = ATT_UUID_16(0x2701),
+ ///Mass unit - Kilogram
+ ATT_UNIT_KG = ATT_UUID_16(0x2702),
+ ///Time unit - second
+ ATT_UNIT_SECOND = ATT_UUID_16(0x2703),
+ ///Electric current unit - Ampere
+ ATT_UNIT_AMPERE = ATT_UUID_16(0x2704),
+ ///Thermodynamic Temperature unit - Kelvin
+ ATT_UNIT_KELVIN = ATT_UUID_16(0x2705),
+ /// Amount of substance unit - mole
+ ATT_UNIT_MOLE = ATT_UUID_16(0x2706),
+ ///Luminous intensity unit - candela
+ ATT_UNIT_CANDELA = ATT_UUID_16(0x2707),
+ ///Area unit - square metres
+ ATT_UNIT_SQ_METRE = ATT_UUID_16(0x2710),
+ ///Colume unit - cubic metres
+ ATT_UNIT_CUBIC_METRE = ATT_UUID_16(0x2710),
+ ///Velocity unit - metres per second
+ ATT_UNIT_METRE_PER_SECOND = ATT_UUID_16(0x2711),
+ ///Acceleration unit - metres per second squared
+ ATT_UNIT_METRES_PER_SEC_SQ = ATT_UUID_16(0x2712),
+ ///Wavenumber unit - reciprocal metre
+ ATT_UNIT_RECIPROCAL_METRE = ATT_UUID_16(0x2713),
+ ///Density unit - kilogram per cubic metre
+ ATT_UNIT_DENS_KG_PER_CUBIC_METRE = ATT_UUID_16(0x2714),
+ ///Surface density unit - kilogram per square metre
+ ATT_UNIT_KG_PER_SQ_METRE = ATT_UUID_16(0x2715),
+ ///Specific volume unit - cubic metre per kilogram
+ ATT_UNIT_CUBIC_METRE_PER_KG = ATT_UUID_16(0x2716),
+ ///Current density unit - ampere per square metre
+ ATT_UNIT_AMPERE_PER_SQ_METRE = ATT_UUID_16(0x2717),
+ ///Magnetic field strength unit - Ampere per metre
+ ATT_UNIT_AMPERE_PER_METRE = ATT_UUID_16(0x2718),
+ ///Amount concentration unit - mole per cubic metre
+ ATT_UNIT_MOLE_PER_CUBIC_METRE = ATT_UUID_16(0x2719),
+ ///Mass Concentration unit - kilogram per cubic metre
+ ATT_UNIT_MASS_KG_PER_CUBIC_METRE = ATT_UUID_16(0x271A),
+ ///Luminance unit - candela per square metre
+ ATT_UNIT_CANDELA_PER_SQ_METRE = ATT_UUID_16(0x271B),
+ ///Refractive index unit
+ ATT_UNIT_REFRACTIVE_INDEX = ATT_UUID_16(0x271C),
+ ///Relative permeability unit
+ ATT_UNIT_RELATIVE_PERMEABILITY = ATT_UUID_16(0x271D),
+ ///Plane angle unit - radian
+ ATT_UNIT_RADIAN = ATT_UUID_16(0x2720),
+ ///Solid angle unit - steradian
+ ATT_UNIT_STERADIAN = ATT_UUID_16(0x2721),
+ ///Frequency unit - Hertz
+ ATT_UNIT_HERTZ = ATT_UUID_16(0x2722),
+ ///Force unit - Newton
+ ATT_UNIT_NEWTON = ATT_UUID_16(0x2723),
+ ///Pressure unit - Pascal
+ ATT_UNIT_PASCAL = ATT_UUID_16(0x2724),
+ ///Energy unit - Joule
+ ATT_UNIT_JOULE = ATT_UUID_16(0x2725),
+ ///Power unit - Watt
+ ATT_UNIT_WATT = ATT_UUID_16(0x2726),
+ ///electric Charge unit - Coulomb
+ ATT_UNIT_COULOMB = ATT_UUID_16(0x2727),
+ ///Electric potential difference - Volt
+ ATT_UNIT_VOLT = ATT_UUID_16(0x2728),
+ ///Capacitance unit - Farad
+ ATT_UNIT_FARAD = ATT_UUID_16(0x2729),
+ ///electric resistance unit - Ohm
+ ATT_UNIT_OHM = ATT_UUID_16(0x272A),
+ ///Electric conductance - Siemens
+ ATT_UNIT_SIEMENS = ATT_UUID_16(0x272B),
+ ///Magnetic flux unit - Weber
+ ATT_UNIT_WEBER = ATT_UUID_16(0x272C),
+ ///Magnetic flux density unit - Tesla
+ ATT_UNIT_TESLA = ATT_UUID_16(0x272D),
+ ///Inductance unit - Henry
+ ATT_UNIT_HENRY = ATT_UUID_16(0x272E),
+ ///Temperature unit - degree Celsius
+ ATT_UNIT_CELSIUS = ATT_UUID_16(0x272F),
+ ///Luminous flux unit - lumen
+ ATT_UNIT_LUMEN = ATT_UUID_16(0x2730),
+ ///Illuminance unit - lux
+ ATT_UNIT_LUX = ATT_UUID_16(0x2731),
+ ///Activity referred to a radionuclide unit - becquerel
+ ATT_UNIT_BECQUEREL = ATT_UUID_16(0x2732),
+ ///Absorbed dose unit - Gray
+ ATT_UNIT_GRAY = ATT_UUID_16(0x2733),
+ ///Dose equivalent unit - Sievert
+ ATT_UNIT_SIEVERT = ATT_UUID_16(0x2734),
+ ///Catalytic activity unit - Katal
+ ATT_UNIT_KATAL = ATT_UUID_16(0x2735),
+ ///Synamic viscosity unit - Pascal second
+ ATT_UNIT_PASCAL_SECOND = ATT_UUID_16(0x2740),
+ ///Moment of force unit - Newton metre
+ ATT_UNIT_NEWTON_METRE = ATT_UUID_16(0x2741),
+ ///surface tension unit - Newton per metre
+ ATT_UNIT_NEWTON_PER_METRE = ATT_UUID_16(0x2742),
+ ///Angular velocity unit - radian per second
+ ATT_UNIT_RADIAN_PER_SECOND = ATT_UUID_16(0x2743),
+ ///Angular acceleration unit - radian per second squared
+ ATT_UNIT_RADIAN_PER_SECOND_SQ = ATT_UUID_16(0x2744),
+ ///Heat flux density unit - Watt per square metre
+ ATT_UNIT_WATT_PER_SQ_METRE = ATT_UUID_16(0x2745),
+ ///HEat capacity unit - Joule per Kelvin
+ ATT_UNIT_JOULE_PER_KELVIN = ATT_UUID_16(0x2746),
+ ///Specific heat capacity unit - Joule per kilogram kelvin
+ ATT_UNIT_JOULE_PER_KG_KELVIN = ATT_UUID_16(0x2747),
+ ///Specific Energy unit - Joule per kilogram
+ ATT_UNIT_JOULE_PER_KG = ATT_UUID_16(0x2748),
+ ///Thermal conductivity - Watt per metre Kelvin
+ ATT_UNIT_WATT_PER_METRE_KELVIN = ATT_UUID_16(0x2749),
+ ///Energy Density unit - joule per cubic metre
+ ATT_UNIT_JOULE_PER_CUBIC_METRE = ATT_UUID_16(0x274A),
+ ///Electric field strength unit - volt per metre
+ ATT_UNIT_VOLT_PER_METRE = ATT_UUID_16(0x274B),
+ ///Electric charge density unit - coulomb per cubic metre
+ ATT_UNIT_COULOMB_PER_CUBIC_METRE = ATT_UUID_16(0x274C),
+ ///Surface charge density unit - coulomb per square metre
+ ATT_UNIT_SURF_COULOMB_PER_SQ_METRE = ATT_UUID_16(0x274D),
+ ///Electric flux density unit - coulomb per square metre
+ ATT_UNIT_FLUX_COULOMB_PER_SQ_METRE = ATT_UUID_16(0x274E),
+ ///Permittivity unit - farad per metre
+ ATT_UNIT_FARAD_PER_METRE = ATT_UUID_16(0x274F),
+ ///Permeability unit - henry per metre
+ ATT_UNIT_HENRY_PER_METRE = ATT_UUID_16(0x2750),
+ ///Molar energy unit - joule per mole
+ ATT_UNIT_JOULE_PER_MOLE = ATT_UUID_16(0x2751),
+ ///Molar entropy unit - joule per mole kelvin
+ ATT_UNIT_JOULE_PER_MOLE_KELVIN = ATT_UUID_16(0x2752),
+ ///Exposure unit - coulomb per kilogram
+ ATT_UNIT_COULOMB_PER_KG = ATT_UUID_16(0x2753),
+ ///Absorbed dose rate unit - gray per second
+ ATT_UNIT_GRAY_PER_SECOND = ATT_UUID_16(0x2754),
+ ///Radiant intensity unit - watt per steradian
+ ATT_UNIT_WATT_PER_STERADIAN = ATT_UUID_16(0x2755),
+ ///Radiance unit - watt per square meter steradian
+ ATT_UNIT_WATT_PER_SQ_METRE_STERADIAN = ATT_UUID_16(0x2756),
+ ///Catalytic activity concentration unit - katal per cubic metre
+ ATT_UNIT_KATAL_PER_CUBIC_METRE = ATT_UUID_16(0x2757),
+ ///Time unit - minute
+ ATT_UNIT_MINUTE = ATT_UUID_16(0x2760),
+ ///Time unit - hour
+ ATT_UNIT_HOUR = ATT_UUID_16(0x2761),
+ ///Time unit - day
+ ATT_UNIT_DAY = ATT_UUID_16(0x2762),
+ ///Plane angle unit - degree
+ ATT_UNIT_ANGLE_DEGREE = ATT_UUID_16(0x2763),
+ ///Plane angle unit - minute
+ ATT_UNIT_ANGLE_MINUTE = ATT_UUID_16(0x2764),
+ ///Plane angle unit - second
+ ATT_UNIT_ANGLE_SECOND = ATT_UUID_16(0x2765),
+ ///Area unit - hectare
+ ATT_UNIT_HECTARE = ATT_UUID_16(0x2766),
+ ///Volume unit - litre
+ ATT_UNIT_LITRE = ATT_UUID_16(0x2767),
+ ///Mass unit - tonne
+ ATT_UNIT_TONNE = ATT_UUID_16(0x2768),
+ ///Pressure unit - bar
+ ATT_UNIT_BAR = ATT_UUID_16(0x2780),
+ ///Pressure unit - millimetre of mercury
+ ATT_UNIT_MM_MERCURY = ATT_UUID_16(0x2781),
+ ///Length unit - angstrom
+ ATT_UNIT_ANGSTROM = ATT_UUID_16(0x2782),
+ ///Length unit - nautical mile
+ ATT_UNIT_NAUTICAL_MILE = ATT_UUID_16(0x2783),
+ ///Area unit - barn
+ ATT_UNIT_BARN = ATT_UUID_16(0x2784),
+ ///Velocity unit - knot
+ ATT_UNIT_KNOT = ATT_UUID_16(0x2785),
+ ///Logarithmic radio quantity unit - neper
+ ATT_UNIT_NEPER = ATT_UUID_16(0x2786),
+ ///Logarithmic radio quantity unit - bel
+ ATT_UNIT_BEL = ATT_UUID_16(0x2787),
+ ///Length unit - yard
+ ATT_UNIT_YARD = ATT_UUID_16(0x27A0),
+ ///Length unit - parsec
+ ATT_UNIT_PARSEC = ATT_UUID_16(0x27A1),
+ ///length unit - inch
+ ATT_UNIT_INCH = ATT_UUID_16(0x27A2),
+ ///length unit - foot
+ ATT_UNIT_FOOT = ATT_UUID_16(0x27A3),
+ ///length unit - mile
+ ATT_UNIT_MILE = ATT_UUID_16(0x27A4),
+ ///pressure unit - pound-force per square inch
+ ATT_UNIT_POUND_FORCE_PER_SQ_INCH = ATT_UUID_16(0x27A5),
+ ///velocity unit - kilometre per hour
+ ATT_UNIT_KM_PER_HOUR = ATT_UUID_16(0x27A6),
+ ///velocity unit - mile per hour
+ ATT_UNIT_MILE_PER_HOUR = ATT_UUID_16(0x27A7),
+ ///angular velocity unit - revolution per minute
+ ATT_UNIT_REVOLUTION_PER_MINUTE = ATT_UUID_16(0x27A8),
+ ///energy unit - gram calorie
+ ATT_UNIT_GRAM_CALORIE = ATT_UUID_16(0x27A9),
+ ///energy unit - kilogram calorie
+ ATT_UNIT_KG_CALORIE = ATT_UUID_16(0x27AA),
+ /// energy unit - kilowatt hour
+ ATT_UNIT_KILOWATT_HOUR = ATT_UUID_16(0x27AB),
+ ///thermodynamic temperature unit - degree Fahrenheit
+ ATT_UNIT_FAHRENHEIT = ATT_UUID_16(0x27AC),
+ ///percentage
+ ATT_UNIT_PERCENTAGE = ATT_UUID_16(0x27AD),
+ ///per mille
+ ATT_UNIT_PER_MILLE = ATT_UUID_16(0x27AE),
+ ///period unit - beats per minute)
+ ATT_UNIT_BEATS_PER_MINUTE = ATT_UUID_16(0x27AF),
+ ///electric charge unit - ampere hours
+ ATT_UNIT_AMPERE_HOURS = ATT_UUID_16(0x27B0),
+ ///mass density unit - milligram per decilitre
+ ATT_UNIT_MILLIGRAM_PER_DECILITRE = ATT_UUID_16(0x27B1),
+ ///mass density unit - millimole per litre
+ ATT_UNIT_MILLIMOLE_PER_LITRE = ATT_UUID_16(0x27B2),
+ ///time unit - year
+ ATT_UNIT_YEAR = ATT_UUID_16(0x27B3),
+ ////time unit - month
+ ATT_UNIT_MONTH = ATT_UUID_16(0x27B4),
+
+
+ /*---------------- DECLARATIONS -----------------*/
+ /// Primary service Declaration
+ ATT_DECL_PRIMARY_SERVICE = ATT_UUID_16(0x2800),
+ /// Secondary service Declaration
+ ATT_DECL_SECONDARY_SERVICE = ATT_UUID_16(0x2801),
+ /// Include Declaration
+ ATT_DECL_INCLUDE = ATT_UUID_16(0x2802),
+ /// Characteristic Declaration
+ ATT_DECL_CHARACTERISTIC = ATT_UUID_16(0x2803),
+
+
+ /*----------------- DESCRIPTORS -----------------*/
+ /// Characteristic extended properties
+ ATT_DESC_CHAR_EXT_PROPERTIES = ATT_UUID_16(0x2900),
+ /// Characteristic user description
+ ATT_DESC_CHAR_USER_DESCRIPTION = ATT_UUID_16(0x2901),
+ /// Client characteristic configuration
+ ATT_DESC_CLIENT_CHAR_CFG = ATT_UUID_16(0x2902),
+ /// Server characteristic configuration
+ ATT_DESC_SERVER_CHAR_CFG = ATT_UUID_16(0x2903),
+ /// Characteristic Presentation Format
+ ATT_DESC_CHAR_PRES_FORMAT = ATT_UUID_16(0x2904),
+ /// Characteristic Aggregate Format
+ ATT_DESC_CHAR_AGGREGATE_FORMAT = ATT_UUID_16(0x2905),
+ /// Valid Range
+ ATT_DESC_VALID_RANGE = ATT_UUID_16(0x2906),
+ /// External Report Reference
+ ATT_DESC_EXT_REPORT_REF = ATT_UUID_16(0x2907),
+ /// Report Reference
+ ATT_DESC_REPORT_REF = ATT_UUID_16(0x2908),
+ /// Environmental Sensing Configuration
+ ATT_DESC_ES_CONFIGURATION = ATT_UUID_16(0x290B),
+ /// Environmental Sensing Measurement
+ ATT_DESC_ES_MEASUREMENT = ATT_UUID_16(0x290C),
+ /// Environmental Sensing Trigger Setting
+ ATT_DESC_ES_TRIGGER_SETTING = ATT_UUID_16(0x290D),
+
+
+ /*--------------- CHARACTERISTICS ---------------*/
+ /// Device name
+ ATT_CHAR_DEVICE_NAME = ATT_UUID_16(0x2A00),
+ /// Appearance
+ ATT_CHAR_APPEARANCE = ATT_UUID_16(0x2A01),
+ /// Privacy flag
+ ATT_CHAR_PRIVACY_FLAG = ATT_UUID_16(0x2A02),
+ /// Reconnection address
+ ATT_CHAR_RECONNECTION_ADDR = ATT_UUID_16(0x2A03),
+ /// Peripheral preferred connection parameters
+ ATT_CHAR_PERIPH_PREF_CON_PARAM = ATT_UUID_16(0x2A04),
+ /// Service handles changed
+ ATT_CHAR_SERVICE_CHANGED = ATT_UUID_16(0x2A05),
+ /// Alert Level characteristic
+ ATT_CHAR_ALERT_LEVEL = ATT_UUID_16(0x2A06),
+ /// Tx Power Level
+ ATT_CHAR_TX_POWER_LEVEL = ATT_UUID_16(0x2A07),
+ /// Date Time
+ ATT_CHAR_DATE_TIME = ATT_UUID_16(0x2A08),
+ /// Day of Week
+ ATT_CHAR_DAY_WEEK = ATT_UUID_16(0x2A09),
+ /// Day Date Time
+ ATT_CHAR_DAY_DATE_TIME = ATT_UUID_16(0x2A0A),
+ /// Exact time 256
+ ATT_CHAR_EXACT_TIME_256 = ATT_UUID_16(0x2A0C),
+ /// DST Offset
+ ATT_CHAR_DST_OFFSET = ATT_UUID_16(0x2A0D),
+ /// Time zone
+ ATT_CHAR_TIME_ZONE = ATT_UUID_16(0x2A0E),
+ /// Local time Information
+ ATT_CHAR_LOCAL_TIME_INFO = ATT_UUID_16(0x2A0F),
+ /// Time with DST
+ ATT_CHAR_TIME_WITH_DST = ATT_UUID_16(0x2A11),
+ /// Time Accuracy
+ ATT_CHAR_TIME_ACCURACY = ATT_UUID_16(0x2A12),
+ ///Time Source
+ ATT_CHAR_TIME_SOURCE = ATT_UUID_16(0x2A13),
+ /// Reference Time Information
+ ATT_CHAR_REFERENCE_TIME_INFO = ATT_UUID_16(0x2A14),
+ /// Time Update Control Point
+ ATT_CHAR_TIME_UPDATE_CNTL_POINT = ATT_UUID_16(0x2A16),
+ /// Time Update State
+ ATT_CHAR_TIME_UPDATE_STATE = ATT_UUID_16(0x2A17),
+ /// Glucose Measurement
+ ATT_CHAR_GLUCOSE_MEAS = ATT_UUID_16(0x2A18),
+ /// Battery Level
+ ATT_CHAR_BATTERY_LEVEL = ATT_UUID_16(0x2A19),
+ /// Temperature Measurement
+ ATT_CHAR_TEMPERATURE_MEAS = ATT_UUID_16(0x2A1C),
+ /// Temperature Type
+ ATT_CHAR_TEMPERATURE_TYPE = ATT_UUID_16(0x2A1D),
+ /// Intermediate Temperature
+ ATT_CHAR_INTERMED_TEMPERATURE = ATT_UUID_16(0x2A1E),
+ /// Measurement Interval
+ ATT_CHAR_MEAS_INTERVAL = ATT_UUID_16(0x2A21),
+ /// Boot Keyboard Input Report
+ ATT_CHAR_BOOT_KB_IN_REPORT = ATT_UUID_16(0x2A22),
+ /// System ID
+ ATT_CHAR_SYS_ID = ATT_UUID_16(0x2A23),
+ /// Model Number String
+ ATT_CHAR_MODEL_NB = ATT_UUID_16(0x2A24),
+ /// Serial Number String
+ ATT_CHAR_SERIAL_NB = ATT_UUID_16(0x2A25),
+ /// Firmware Revision String
+ ATT_CHAR_FW_REV = ATT_UUID_16(0x2A26),
+ /// Hardware revision String
+ ATT_CHAR_HW_REV = ATT_UUID_16(0x2A27),
+ /// Software Revision String
+ ATT_CHAR_SW_REV = ATT_UUID_16(0x2A28),
+ /// Manufacturer Name String
+ ATT_CHAR_MANUF_NAME = ATT_UUID_16(0x2A29),
+ /// IEEE Regulatory Certification Data List
+ ATT_CHAR_IEEE_CERTIF = ATT_UUID_16(0x2A2A),
+ /// CT Time
+ ATT_CHAR_CT_TIME = ATT_UUID_16(0x2A2B),
+ /// Magnetic Declination
+ ATT_CHAR_MAGN_DECLINE = ATT_UUID_16(0x2A2C),
+ /// Scan Refresh
+ ATT_CHAR_SCAN_REFRESH = ATT_UUID_16(0x2A31),
+ /// Boot Keyboard Output Report
+ ATT_CHAR_BOOT_KB_OUT_REPORT = ATT_UUID_16(0x2A32),
+ /// Boot Mouse Input Report
+ ATT_CHAR_BOOT_MOUSE_IN_REPORT = ATT_UUID_16(0x2A33),
+ /// Glucose Measurement Context
+ ATT_CHAR_GLUCOSE_MEAS_CTX = ATT_UUID_16(0x2A34),
+ /// Blood Pressure Measurement
+ ATT_CHAR_BLOOD_PRESSURE_MEAS = ATT_UUID_16(0x2A35),
+ /// Intermediate Cuff Pressure
+ ATT_CHAR_INTERMEDIATE_CUFF_PRESSURE = ATT_UUID_16(0x2A36),
+ /// Heart Rate Measurement
+ ATT_CHAR_HEART_RATE_MEAS = ATT_UUID_16(0x2A37),
+ /// Body Sensor Location
+ ATT_CHAR_BODY_SENSOR_LOCATION = ATT_UUID_16(0x2A38),
+ /// Heart Rate Control Point
+ ATT_CHAR_HEART_RATE_CNTL_POINT = ATT_UUID_16(0x2A39),
+ /// Alert Status
+ ATT_CHAR_ALERT_STATUS = ATT_UUID_16(0x2A3F),
+ /// Ringer Control Point
+ ATT_CHAR_RINGER_CNTL_POINT = ATT_UUID_16(0x2A40),
+ /// Ringer Setting
+ ATT_CHAR_RINGER_SETTING = ATT_UUID_16(0x2A41),
+ /// Alert Category ID Bit Mask
+ ATT_CHAR_ALERT_CAT_ID_BIT_MASK = ATT_UUID_16(0x2A42),
+ /// Alert Category ID
+ ATT_CHAR_ALERT_CAT_ID = ATT_UUID_16(0x2A43),
+ /// Alert Notification Control Point
+ ATT_CHAR_ALERT_NTF_CTNL_PT = ATT_UUID_16(0x2A44),
+ /// Unread Alert Status
+ ATT_CHAR_UNREAD_ALERT_STATUS = ATT_UUID_16(0x2A45),
+ /// New Alert
+ ATT_CHAR_NEW_ALERT = ATT_UUID_16(0x2A46),
+ /// Supported New Alert Category
+ ATT_CHAR_SUP_NEW_ALERT_CAT = ATT_UUID_16(0x2A47),
+ /// Supported Unread Alert Category
+ ATT_CHAR_SUP_UNREAD_ALERT_CAT = ATT_UUID_16(0x2A48),
+ /// Blood Pressure Feature
+ ATT_CHAR_BLOOD_PRESSURE_FEATURE = ATT_UUID_16(0x2A49),
+ /// HID Information
+ ATT_CHAR_HID_INFO = ATT_UUID_16(0x2A4A),
+ /// Report Map
+ ATT_CHAR_REPORT_MAP = ATT_UUID_16(0x2A4B),
+ /// HID Control Point
+ ATT_CHAR_HID_CTNL_PT = ATT_UUID_16(0x2A4C),
+ /// Report
+ ATT_CHAR_REPORT = ATT_UUID_16(0x2A4D),
+ /// Protocol Mode
+ ATT_CHAR_PROTOCOL_MODE = ATT_UUID_16(0x2A4E),
+ /// Scan Interval Window
+ ATT_CHAR_SCAN_INTV_WD = ATT_UUID_16(0x2A4F),
+ /// PnP ID
+ ATT_CHAR_PNP_ID = ATT_UUID_16(0x2A50),
+ /// Glucose Feature
+ ATT_CHAR_GLUCOSE_FEATURE = ATT_UUID_16(0x2A51),
+ /// Record access control point
+ ATT_CHAR_REC_ACCESS_CTRL_PT = ATT_UUID_16(0x2A52),
+ /// RSC Measurement
+ ATT_CHAR_RSC_MEAS = ATT_UUID_16(0x2A53),
+ /// RSC Feature
+ ATT_CHAR_RSC_FEAT = ATT_UUID_16(0x2A54),
+ /// SC Control Point
+ ATT_CHAR_SC_CNTL_PT = ATT_UUID_16(0x2A55),
+ /// CSC Measurement
+ ATT_CHAR_CSC_MEAS = ATT_UUID_16(0x2A5B),
+ /// CSC Feature
+ ATT_CHAR_CSC_FEAT = ATT_UUID_16(0x2A5C),
+ /// Sensor Location
+ ATT_CHAR_SENSOR_LOC = ATT_UUID_16(0x2A5D),
+ /// CP Measurement
+ ATT_CHAR_CP_MEAS = ATT_UUID_16(0x2A63),
+ /// CP Vector
+ ATT_CHAR_CP_VECTOR = ATT_UUID_16(0x2A64),
+ /// CP Feature
+ ATT_CHAR_CP_FEAT = ATT_UUID_16(0x2A65),
+ /// CP Control Point
+ ATT_CHAR_CP_CNTL_PT = ATT_UUID_16(0x2A66),
+ /// Location and Speed
+ ATT_CHAR_LOC_SPEED = ATT_UUID_16(0x2A67),
+ /// Navigation
+ ATT_CHAR_NAVIGATION = ATT_UUID_16(0x2A68),
+ /// Position Quality
+ ATT_CHAR_POS_QUALITY = ATT_UUID_16(0x2A69),
+ /// LN Feature
+ ATT_CHAR_LN_FEAT = ATT_UUID_16(0x2A6A),
+ /// LN Control Point
+ ATT_CHAR_LN_CNTL_PT = ATT_UUID_16(0x2A6B),
+ /// Elevation
+ ATT_CHAR_ELEVATION = ATT_UUID_16(0x2A6C),
+ /// Pressure
+ ATT_CHAR_PRESSURE = ATT_UUID_16(0x2A6D),
+ /// Temperature
+ ATT_CHAR_TEMPERATURE = ATT_UUID_16(0x2A6E),
+ /// Humidity
+ ATT_CHAR_HUMIDITY = ATT_UUID_16(0x2A6F),
+ /// True Wind Speed
+ ATT_CHAR_TRUE_WIND_SPEED = ATT_UUID_16(0x2A70),
+ /// True Wind Direction
+ ATT_CHAR_TRUE_WIND_DIR = ATT_UUID_16(0x2A71),
+ /// Apparent Wind Speed
+ ATT_CHAR_APRNT_WIND_SPEED = ATT_UUID_16(0x2A72),
+ /// Apparent Wind Direction
+ ATT_CHAR_APRNT_WIND_DIRECTION = ATT_UUID_16(0x2A73),
+ /// Gust Factor
+ ATT_CHAR_GUST_FACTOR = ATT_UUID_16(0x2A74),
+ /// Pollen Concentration
+ ATT_CHAR_POLLEN_CONC = ATT_UUID_16(0x2A75),
+ /// UV Index
+ ATT_CHAR_UV_INDEX = ATT_UUID_16(0x2A76),
+ /// Irradiance
+ ATT_CHAR_IRRADIANCE = ATT_UUID_16(0x2A77),
+ /// Rainfall
+ ATT_CHAR_RAINFALL = ATT_UUID_16(0x2A78),
+ /// Wind Chill
+ ATT_CHAR_WIND_CHILL = ATT_UUID_16(0x2A79),
+ /// Heat Index
+ ATT_CHAR_HEAT_INDEX = ATT_UUID_16(0x2A7A),
+ /// Dew Point
+ ATT_CHAR_DEW_POINT = ATT_UUID_16(0x2A7B),
+ /// Descriptor Value Changed
+ ATT_CHAR_DESCRIPTOR_VALUE_CHANGED = ATT_UUID_16(0x2A7D),
+ /// Aerobic Heart Rate Lower Limit
+ ATT_CHAR_AEROBIC_HEART_RATE_LOWER_LIMIT = ATT_UUID_16(0x2A7E),
+ /// Aerobic Threshhold
+ ATT_CHAR_AEROBIC_THRESHHOLD = ATT_UUID_16(0x2A7F),
+ /// Age
+ ATT_CHAR_AGE = ATT_UUID_16(0x2A80),
+ /// Anaerobic Heart Rate Lower Limit
+ ATT_CHAR_ANAEROBIC_HEART_RATE_LOWER_LIMIT = ATT_UUID_16(0x2A81),
+ /// Anaerobic Heart Rate Upper Limit
+ ATT_CHAR_ANAEROBIC_HEART_RATE_UPPER_LIMIT = ATT_UUID_16(0x2A82),
+ /// Anaerobic Threshhold
+ ATT_CHAR_ANAEROBIC_THRESHHOLD = ATT_UUID_16(0x2A83),
+ /// Aerobic Heart Rate Upper Limit
+ ATT_CHAR_AEROBIC_HEART_RATE_UPPER_LIMIT = ATT_UUID_16(0x2A84),
+ /// Date Of Birth
+ ATT_CHAR_DATE_OF_BIRTH = ATT_UUID_16(0x2A85),
+ /// Date Of Threshold Assessment
+ ATT_CHAR_DATE_OF_THRESHOLD_ASSESSMENT = ATT_UUID_16(0x2A86),
+ /// Email Address
+ ATT_CHAR_EMAIL_ADDRESS = ATT_UUID_16(0x2A87),
+ /// Fat Burn Heart Rate Lower Limit
+ ATT_CHAR_FAT_BURN_HEART_RATE_LOWER_LIMIT = ATT_UUID_16(0x2A88),
+ /// Fat Burn Heart Rate Upper Limit
+ ATT_CHAR_FAT_BURN_HEART_RATE_UPPER_LIMIT = ATT_UUID_16(0x2A89),
+ /// First Name
+ ATT_CHAR_FIRST_NAME = ATT_UUID_16(0x2A8A),
+ /// Five Zone Heart Rate Limits
+ ATT_CHAR_FIVE_ZONE_HEART_RATE_LIMITS = ATT_UUID_16(0x2A8B),
+ /// Gender
+ ATT_CHAR_GENDER = ATT_UUID_16(0x2A8C),
+ /// Max Heart Rate
+ ATT_CHAR_MAX_HEART_RATE = ATT_UUID_16(0x2A8D),
+ /// Height
+ ATT_CHAR_HEIGHT = ATT_UUID_16(0x2A8E),
+ /// Hip Circumference
+ ATT_CHAR_HIP_CIRCUMFERENCE = ATT_UUID_16(0x2A8F),
+ /// Last Name
+ ATT_CHAR_LAST_NAME = ATT_UUID_16(0x2A90),
+ /// Maximum Recommended Heart Rate
+ ATT_CHAR_MAXIMUM_RECOMMENDED_HEART_RATE = ATT_UUID_16(0x2A91),
+ /// Resting Heart Rate
+ ATT_CHAR_RESTING_HEART_RATE = ATT_UUID_16(0x2A92),
+ /// Sport Type For Aerobic And Anaerobic Thresholds
+ ATT_CHAR_SPORT_TYPE_FOR_AEROBIC_AND_ANAEROBIC_THRESHOLDS = ATT_UUID_16(0x2A93),
+ /// Three Zone Heart Rate Limits
+ ATT_CHAR_THREE_ZONE_HEART_RATE_LIMITS = ATT_UUID_16(0x2A94),
+ /// Two Zone Heart Rate Limit
+ ATT_CHAR_TWO_ZONE_HEART_RATE_LIMIT = ATT_UUID_16(0x2A95),
+ /// Vo2 Max
+ ATT_CHAR_VO2_MAX = ATT_UUID_16(0x2A96),
+ /// Waist Circumference
+ ATT_CHAR_WAIST_CIRCUMFERENCE = ATT_UUID_16(0x2A97),
+ /// Weight
+ ATT_CHAR_WEIGHT = ATT_UUID_16(0x2A98),
+ /// Database Change Increment
+ ATT_CHAR_DATABASE_CHANGE_INCREMENT = ATT_UUID_16(0x2A99),
+ /// User Index
+ ATT_CHAR_USER_INDEX = ATT_UUID_16(0x2A9A),
+ /// Body Composition Feature
+ ATT_CHAR_BODY_COMPOSITION_FEATURE = ATT_UUID_16(0x2A9B),
+ /// Body Composition Measurement
+ ATT_CHAR_BODY_COMPOSITION_MEASUREMENT = ATT_UUID_16(0x2A9C),
+ /// Weight Measurement
+ ATT_CHAR_WEIGHT_MEASUREMENT = ATT_UUID_16(0x2A9D),
+ /// Weight Scale Feature
+ ATT_CHAR_WEIGHT_SCALE_FEATURE = ATT_UUID_16(0x2A9E),
+ /// User Control Point
+ ATT_CHAR_USER_CONTROL_POINT = ATT_UUID_16(0x2A9F),
+ /// Flux Density - 2D
+ ATT_CHAR_MAGN_FLUX_2D = ATT_UUID_16(0x2AA0),
+ /// Magnetic Flux Density - 3D
+ ATT_CHAR_MAGN_FLUX_3D = ATT_UUID_16(0x2AA1),
+ /// Language string
+ ATT_CHAR_LANGUAGE = ATT_UUID_16(0x2AA2),
+ /// Barometric Pressure Trend
+ ATT_CHAR_BAR_PRES_TREND = ATT_UUID_16(0x2AA3),
+ /// Central Address Resolution Support
+ ATT_CHAR_CTL_ADDR_RESOL_SUPP = ATT_UUID_16(0x2AA6),
+ //by wq
+ ATT_SVC_UKEY_SERVICE = ATT_UUID_16(0xFEE7),
+ ATT_CHAR_WRITE_NOTIFY = ATT_UUID_16(0xFEC1),
+ ATT_CHAR_READ_NOTIFY = ATT_UUID_16(0xFEC2),
+
+// ATT_SVC_USER_DEF1 = ATT_UUID_16(0xFF06),
+// ATT_CHAR_READ_WRITE1 = ATT_UUID_16(0xFF60),
+// ATT_CHAR_DATA_NOTIFY1 = ATT_UUID_16(0xFF61),
+// ATT_CHAR_DATA_WRITE1 = ATT_UUID_16(0xFF62),
+//
+// ATT_SVC_USER_DEF2 = ATT_UUID_16(0xFF07),
+// ATT_CHAR_READ_WRITE2 = ATT_UUID_16(0xFF70),
+// ATT_CHAR_DATA_NOTIFY2 = ATT_UUID_16(0xFF71),
+// ATT_CHAR_DATA_WRITE2 = ATT_UUID_16(0xFF72),
+};
+
+/// Format for Characteristic Presentation
+enum {
+ /// unsigned 1-bit: true or false
+ ATT_FORMAT_BOOL = 0x01,
+ /// unsigned 2-bit integer
+ ATT_FORMAT_2BIT,
+ /// unsigned 4-bit integer
+ ATT_FORMAT_NIBBLE,
+ /// unsigned 8-bit integer
+ ATT_FORMAT_UINT8,
+ /// unsigned 12-bit integer
+ ATT_FORMAT_UINT12,
+ /// unsigned 16-bit integer
+ ATT_FORMAT_UINT16,
+ /// unsigned 24-bit integer
+ ATT_FORMAT_UINT24,
+ /// unsigned 32-bit integer
+ ATT_FORMAT_UINT32,
+ /// unsigned 48-bit integer
+ ATT_FORMAT_UINT48,
+ /// unsigned 64-bit integer
+ ATT_FORMAT_UINT64,
+ /// unsigned 128-bit integer
+ ATT_FORMAT_UINT128,
+ /// signed 8-bit integer
+ ATT_FORMAT_SINT8,
+ /// signed 12-bit integer
+ ATT_FORMAT_SINT12,
+ /// signed 16-bit integer
+ ATT_FORMAT_SINT16,
+ /// signed 24-bit integer
+ ATT_FORMAT_SINT24,
+ /// signed 32-bit integer
+ ATT_FORMAT_SINT32,
+ /// signed 48-bit integer
+ ATT_FORMAT_SINT48,
+ /// signed 64-bit integer
+ ATT_FORMAT_SINT64,
+ /// signed 128-bit integer
+ ATT_FORMAT_SINT128,
+ /// IEEE-754 32-bit floating point
+ ATT_FORMAT_FLOAT32,
+ /// IEEE-754 64-bit floating point
+ ATT_FORMAT_FLOAT64,
+ /// IEEE-11073 16-bit SFLOAT
+ ATT_FORMAT_SFLOAT,
+ /// IEEE-11073 32-bit FLOAT
+ ATT_FORMAT_FLOAT,
+ /// IEEE-20601 format
+ ATT_FORMAT_DUINT16,
+ /// UTF-8 string
+ ATT_FORMAT_UTF8S,
+ /// UTF-16 string
+ ATT_FORMAT_UTF16S,
+ /// Opaque structure
+ ATT_FORMAT_STRUCT,
+ /// Last format
+ ATT_FORMAT_LAST
+};
+
+
+/// Client Characteristic Configuration Codes
+enum att_ccc_val
+{
+ /// Stop notification/indication
+ ATT_CCC_STOP_NTFIND = 0x0000,
+ /// Start notification
+ ATT_CCC_START_NTF,
+ /// Start indication
+ ATT_CCC_START_IND
+};
+
+/*
+ * Type Definition
+ ****************************************************************************************
+ */
+
+/// Attribute length type
+typedef uint16_t att_size_t;
+
+
+/// UUID - 128-bit type
+struct att_uuid_128
+{
+ /// 128-bit UUID
+ uint8_t uuid[ATT_UUID_128_LEN];
+};
+
+/// UUID - 32-bit type
+struct att_uuid_32
+{
+ /// 32-bit UUID
+ uint8_t uuid[ATT_UUID_32_LEN];
+};
+
+
+
+/// Characteristic Value Descriptor
+struct att_char_desc
+{
+ /// properties
+ uint8_t prop;
+ /// attribute handle
+ uint8_t attr_hdl[ATT_HANDLE_LEN];
+ /// attribute type
+ uint8_t attr_type[ATT_UUID_16_LEN];
+};
+
+/// Characteristic Value Descriptor
+struct att_char128_desc
+{
+ /// properties
+ uint8_t prop;
+ /// attribute handle
+ uint8_t attr_hdl[ATT_HANDLE_LEN];
+ /// attribute type
+ uint8_t attr_type[ATT_UUID_128_LEN];
+};
+
+/// Service Value Descriptor - 16-bit
+typedef uint16_t att_svc_desc_t;
+
+/// include service entry element
+struct att_incl_desc
+{
+ /// start handle value of included service
+ uint16_t start_hdl;
+ /// end handle value of included service
+ uint16_t end_hdl;
+ /// attribute value UUID
+ uint16_t uuid;
+};
+
+/// include service entry element
+struct att_incl128_desc
+{
+ /// start handle value of included service
+ uint16_t start_hdl;
+ /// end handle value of included service
+ uint16_t end_hdl;
+};
+
+
+// -------------------------- PDU HANDLER Definition --------------------------
+
+/// used to know if PDU handler has been found
+#define ATT_PDU_HANDLER_NOT_FOUND (0xff)
+
+/// Format of a pdu handler function
+typedef int (*att_func_t)(uint8_t conidx, void *pdu);
+
+/// Element of a pdu handler table.
+struct att_pdu_handler
+{
+ /// PDU identifier of the message
+ uint8_t pdu_id;
+ /// Pointer to the handler function for the pdu above.
+ att_func_t handler;
+};
+
+
+// --------------------------- Database permissions -----------------------------
+
+/// Macro used to retrieve access permission rights
+#define PERM_GET(perm, access)\
+ (((perm) & (PERM_MASK_ ## access)) >> (PERM_POS_ ## access))
+
+/// Macro used to retrieve permission value from access and rights on attribute.
+#define PERM(access, right) \
+ (((PERM_RIGHT_ ## right) << (PERM_POS_ ## access)) & (PERM_MASK_ ## access))
+
+/// Macro used know if permission is set or not.
+#define PERM_IS_SET(perm, access, right) \
+ (((perm) & (((PERM_RIGHT_ ## right) << (PERM_POS_ ## access))) \
+ & (PERM_MASK_ ## access)) == PERM(access, right))
+
+/// Macro used to create permission value
+#define PERM_VAL(access, perm) \
+ ((((perm) << (PERM_POS_ ## access))) & (PERM_MASK_ ## access))
+
+
+
+/// Retrieve attribute security level from attribute right and service right
+#define ATT_GET_SEC_LVL(att_right, svc_right) \
+ co_max(((att_right) & PERM_RIGHT_AUTH), ((svc_right) & PERM_RIGHT_AUTH));
+
+/// Retrieve UUID LEN from UUID Length Permission
+#define ATT_UUID_LEN(uuid_len_perm) ((uuid_len_perm == 0) ? ATT_UUID_16_LEN : \
+ ((uuid_len_perm == 1) ? ATT_UUID_32_LEN : \
+ ((uuid_len_perm == 2) ? ATT_UUID_128_LEN : 0)))
+
+/// Initialization of attribute element
+#define ATT_ELEMT_INIT {{NULL}, false}
+
+/**
+ * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+ * +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
+ * |EXT | WS | I | N | WR | WC | RD | B | NP | IP | WP | RP |
+ * +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
+ *
+ * Bit [0-1] : Read Permission (0 = NO_AUTH, 1 = UNAUTH, 2 = AUTH, 3 = SEC_CON)
+ * Bit [2-3] : Write Permission (0 = NO_AUTH, 1 = UNAUTH, 2 = AUTH, 3 = SEC_CON)
+ * Bit [4-5] : Indication Permission (0 = NO_AUTH, 1 = UNAUTH, 2 = AUTH, 3 = SEC_CON)
+ * Bit [6-7] : Notification Permission (0 = NO_AUTH, 1 = UNAUTH, 2 = AUTH, 3 = SEC_CON)
+ *
+ * Bit [8] : Extended properties present (only relevant for a characteristic value)
+ * Bit [9] : Broadcast permission (only relevant for a characteristic value)
+ * Bit [10] : Write Command accepted
+ * Bit [11] : Write Signed accepted
+ * Bit [12] : Write Request accepted
+ * Bit [13] : Encryption key Size must be 16 bytes
+ */
+enum attm_perm_mask
+{
+ /// retrieve all permission info
+ PERM_MASK_ALL = 0x0000,
+ /// Read Permission Mask
+ PERM_MASK_RP = 0x0003,
+ PERM_POS_RP = 0,
+ /// Write Permission Mask
+ PERM_MASK_WP = 0x000C,
+ PERM_POS_WP = 2,
+ /// Indication Access Mask
+ PERM_MASK_IP = 0x0030,
+ PERM_POS_IP = 4,
+ /// Notification Access Mask
+ PERM_MASK_NP = 0x00C0,
+ PERM_POS_NP = 6,
+ /// Broadcast descriptor present
+ PERM_MASK_BROADCAST = 0x0100,
+ PERM_POS_BROADCAST = 8,
+ /// Read Access Mask
+ PERM_MASK_RD = 0x0200,
+ PERM_POS_RD = 9,
+ /// Write Command Enabled attribute Mask
+ PERM_MASK_WRITE_COMMAND = 0x0400,
+ PERM_POS_WRITE_COMMAND = 10,
+ /// Write Request Enabled attribute Mask
+ PERM_MASK_WRITE_REQ = 0x0800,
+ PERM_POS_WRITE_REQ = 11,
+ /// Notification Access Mask
+ PERM_MASK_NTF = 0x1000,
+ PERM_POS_NTF = 12,
+ /// Indication Access Mask
+ PERM_MASK_IND = 0x2000,
+ PERM_POS_IND = 13,
+ /// Write Signed Enabled attribute Mask
+ PERM_MASK_WRITE_SIGNED = 0x4000,
+ PERM_POS_WRITE_SIGNED = 14,
+ /// Extended properties descriptor present
+ PERM_MASK_EXT = 0x8000,
+ PERM_POS_EXT = 15,
+
+ /// Properties
+ PERM_MASK_PROP = 0xFF00,
+ PERM_POS_PROP = 8,
+};
+
+/**
+ * Value permission bit field
+ *
+ * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+ * +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
+ * | RI |UUID_LEN |EKS | MAX_LEN (RI = 1) / Value Offset (RI = 0) |
+ * +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
+ *
+ * Bit [0-11] : Maximum Attribute Length or Value Offset pointer
+ * Bit [12] : Encryption key Size must be 16 bytes
+ * Bit [14-13]: UUID Length (0 = 16 bits, 1 = 32 bits, 2 = 128 bits, 3 = RFU)
+ * Bit [15] : Trigger Read Indication (0 = Value present in Database, 1 = Value not present in Database)
+ */
+enum attm_value_perm_mask
+{
+ /// Maximum Attribute Length
+ PERM_MASK_MAX_LEN = 0x0FFF,
+ PERM_POS_MAX_LEN = 0,
+ /// Attribute value Offset
+ PERM_MASK_VAL_OFFSET = 0x0FFF,
+ PERM_POS_VAL_OFFSET = 0,
+ /// Check Encryption key size Mask
+ PERM_MASK_EKS = 0x1000,
+ PERM_POS_EKS = 12,
+ /// UUID Length
+ PERM_MASK_UUID_LEN = 0x6000,
+ PERM_POS_UUID_LEN = 13,
+ /// Read trigger Indication
+ PERM_MASK_RI = 0x8000,
+ PERM_POS_RI = 15,
+};
+
+
+/**
+ * Service permissions
+ *
+ * 7 6 5 4 3 2 1 0
+ * +----+----+----+----+----+----+----+----+
+ * |SEC |UUID_LEN |DIS | AUTH |EKS | MI |
+ * +----+----+----+----+----+----+----+----+
+ *
+ * Bit [0] : Task that manage service is multi-instantiated (Connection index is conveyed)
+ * Bit [1] : Encryption key Size must be 16 bytes
+ * Bit [2-3]: Service Permission (0 = NO_AUTH, 1 = UNAUTH, 2 = AUTH, 3 = Secure Connect)
+ * Bit [4] : Disable the service
+ * Bit [5-6]: UUID Length (0 = 16 bits, 1 = 32 bits, 2 = 128 bits, 3 = RFU)
+ * Bit [7] : Secondary Service (0 = Primary Service, 1 = Secondary Service)
+ */
+enum attm_svc_perm_mask
+{
+ /// Task that manage service is multi-instantiated
+ PERM_MASK_SVC_MI = 0x01,
+ PERM_POS_SVC_MI = 0,
+ /// Check Encryption key size for service Access
+ PERM_MASK_SVC_EKS = 0x02,
+ PERM_POS_SVC_EKS = 1,
+ /// Service Permission authentication
+ PERM_MASK_SVC_AUTH = 0x0C,
+ PERM_POS_SVC_AUTH = 2,
+ /// Disable the service
+ PERM_MASK_SVC_DIS = 0x10,
+ PERM_POS_SVC_DIS = 4,
+ /// Service UUID Length
+ PERM_MASK_SVC_UUID_LEN = 0x60,
+ PERM_POS_SVC_UUID_LEN = 5,
+ /// Service type Secondary
+ PERM_MASK_SVC_SECONDARY = 0x80,
+ PERM_POS_SVC_SECONDARY = 7,
+};
+
+/// Attribute & Service access mode
+enum
+{
+ /// Disable access
+ PERM_RIGHT_DISABLE = 0,
+ /// Enable access
+ PERM_RIGHT_ENABLE = 1,
+};
+
+/// Attribute & Service access rights
+enum
+{
+ /// No Authentication
+ PERM_RIGHT_NO_AUTH = 0,
+ /// Access Requires Unauthenticated link
+ PERM_RIGHT_UNAUTH = 1,
+ /// Access Requires Authenticated link
+ PERM_RIGHT_AUTH = 2,
+ /// Access Requires Secure Connection link
+ PERM_RIGHT_SEC_CON = 3,
+};
+
+/// Attribute & Service UUID Length
+enum
+{
+ /// 16 bits UUID
+ PERM_UUID_16 = 0,
+ PERM_RIGHT_UUID_16 = 0,
+ /// 32 bits UUID
+ PERM_UUID_32 = 1,
+ PERM_RIGHT_UUID_32 = 1,
+ /// 128 bits UUID
+ PERM_UUID_128 = 2,
+ PERM_RIGHT_UUID_128 = 2,
+ /// Invalid
+ PERM_UUID_RFU = 3,
+};
+
+/// execute flags
+enum
+{
+ /// Cancel All the Reliable Writes
+ ATT_CANCEL_ALL_PREPARED_WRITES = 0x00,
+ /// Write All the Reliable Writes
+ ATT_EXECUTE_ALL_PREPARED_WRITES
+};
+
+
+
+/// @} ATT
+#endif // ATT_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/attc.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/attc.h
new file mode 100644
index 0000000000..d4524e5973
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/attc.h
@@ -0,0 +1,127 @@
+/**
+ ****************************************************************************************
+ *
+ * @file attc.h
+ *
+ * @brief Header file - ATTC.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef ATTC_H_
+#define ATTC_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup ATTC Attribute Client
+ * @ingroup ATT
+ * @brief Attribute Protocol Client
+ *
+ * The ATTC module is responsible for handling messages intended for the attribute
+ * profile client. It has defined interfaces with @ref ATTM "ATTM".
+ *
+ * @{
+ *
+ ****************************************************************************************
+ */
+#include "rwip_config.h"
+
+#include
+#include "l2cc.h"
+#include "ke_task.h"
+
+#if (BLE_ATTC)
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/// Allocate a Attribute PDU packet for a specific attribute request.
+#define ATTC_ALLOCATE_ATT_REQ(conidx, opcode, pdu_type, value_len)\
+ L2CC_ATT_PDU_ALLOC_DYN(conidx, opcode, KE_BUILD_ID(TASK_GATTC, conidx), pdu_type, value_len)
+
+/*
+ * DATA STRUCTURES
+ ****************************************************************************************
+ */
+
+/// Peer device event registration
+struct attc_register_evt
+{
+ /// list header
+ struct co_list_hdr hdr;
+ /// Attribute start handle
+ uint16_t start_hdl;
+ /// Attribute end handle
+ uint16_t end_hdl;
+ /// Task to be notified
+ ke_task_id_t task;
+};
+
+
+/*
+ * GLOBAL VARIABLE DECLARATIONS
+ ****************************************************************************************
+ */
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+/**
+ ****************************************************************************************
+ * @brief Sends Indication reception confirmation message
+ *
+ * @param[in] conidx connection index
+ *
+ ****************************************************************************************
+ */
+void attc_send_hdl_cfm(uint8_t conidx);
+
+/**
+ ****************************************************************************************
+ * @brief Sends write execute.
+ *
+ * @param[in] conidx connection index
+ * @param[in] flag write execute flag (write or discard)
+ *
+ ****************************************************************************************
+ */
+void attc_send_execute(uint8_t conidx, uint8_t flag);
+
+
+/**
+ ****************************************************************************************
+ * @brief Send a PDU Attribute request packet
+ *
+ * @param[in] conidx Index of the connection with the peer device
+ * @param[in] pdu PDU Packet
+ ****************************************************************************************
+ */
+void attc_send_att_req(uint8_t conidx, void *pdu);
+
+#endif /* (BLE_ATTC) */
+
+#if (BLE_CENTRAL || BLE_PERIPHERAL)
+/**
+ ****************************************************************************************
+ * @brief Handles reception of PDU Packet
+ *
+ * @param[in] conidx Index of the connection with the peer device
+ * @param[in] param Received PDU Packet
+ *
+ * @return If message has been proceed or consumed
+ ****************************************************************************************
+ */
+int attc_l2cc_pdu_recv_handler(uint8_t conidx, struct l2cc_pdu_recv_ind *param);
+#endif /* #if (BLE_CENTRAL || BLE_PERIPHERAL) */
+
+/// @} ATTC
+#endif // ATT_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/attm.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/attm.h
new file mode 100644
index 0000000000..4078c078ea
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/attm.h
@@ -0,0 +1,414 @@
+/**
+ ****************************************************************************************
+ *
+ * @file attm.h
+ *
+ * @brief Header file - ATTM.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef ATTM_H_
+#define ATTM_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup ATTM Attribute Manager
+ * @ingroup ATT
+ * @brief Attribute Manager
+ *
+ * The ATTM is the attribute manager of the Attribute Profile block and
+ * is responsible for managing messages and providing generic attribute
+ * functionalities to @ref ATTC "ATTC" and @ref ATTS "ATTS".
+ *
+ *
+ * @{
+ *
+ ****************************************************************************************
+ */
+
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "rwip_config.h"
+#include
+#include
+
+#include "co_error.h"
+#include "att.h"
+#include "ke_task.h"
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/// update attribute permission on specific handle
+#define ATTMDB_UPDATE_PERM(handle, access, right)\
+ attm_att_update_perm(handle, (PERM_MASK_ ## access), PERM(access, right))
+
+#define ATTMDB_UPDATE_PERM_VAL(handle, access, val)\
+ attm_att_update_perm(handle, (PERM_MASK_ ## access), ((val) << (PERM_POS_ ## access)))
+
+
+
+/*
+ * DATA STRUCTURES
+ ****************************************************************************************
+ */
+
+/// Internal 16bits UUID service description
+struct attm_desc
+{
+ /// 16 bits UUID LSB First
+ uint16_t uuid;
+ /// Attribute Permissions (@see enum attm_perm_mask)
+ uint16_t perm;
+ /// Attribute Extended Permissions (@see enum attm_value_perm_mask)
+ uint16_t ext_perm;
+ /// Attribute Max Size
+ /// note: for characteristic declaration contains handle offset
+ /// note: for included service, contains target service handle
+ uint16_t max_size;
+};
+
+
+/// Internal 128bits UUID service description
+struct attm_desc_128
+{
+ /// 128 bits UUID LSB First
+ uint8_t uuid[ATT_UUID_128_LEN];
+ /// Attribute Permissions (@see enum attm_perm_mask)
+ uint16_t perm;
+ /// Attribute Extended Permissions (@see enum attm_value_perm_mask)
+ uint16_t ext_perm;
+ /// Attribute Max Size
+ /// note: for characteristic declaration contains handle offset
+ /// note: for included service, contains target service handle
+ uint16_t max_size;
+};
+
+
+
+#if (BLE_CENTRAL || BLE_PERIPHERAL)
+/*
+ * GLOBAL VARIABLE DECLARATIONS
+ ****************************************************************************************
+ */
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+
+/**
+ ****************************************************************************************
+ * @brief Compare if two UUIDs matches
+ *
+ * @param[in] uuid_a UUID A value
+ * @param[in] uuid_a_len UUID A length
+ * @param[in] uuid_b UUID B value
+ * @param[in] uuid_b_len UUID B length
+ *
+ * @return true if UUIDs matches, false otherwise
+ ****************************************************************************************
+ */
+bool attm_uuid_comp(const uint8_t *uuid_a, uint8_t uuid_a_len,
+ const uint8_t *uuid_b, uint8_t uuid_b_len);
+
+
+/**
+ ****************************************************************************************
+ * @brief Check if two UUIDs matches (2nd UUID is a 16 bits UUID with LSB First)
+ *
+ * @param[in] uuid_a UUID A value
+ * @param[in] uuid_a_len UUID A length
+ * @param[in] uuid_b UUID B 16 bit value
+ *
+ * @return true if UUIDs matches, false otherwise
+ ****************************************************************************************
+ */
+bool attm_uuid16_comp(uint8_t *uuid_a, uint8_t uuid_a_len, uint16_t uuid_b);
+
+
+/**
+ ****************************************************************************************
+ * @brief Convert UUID value to 128 bit UUID
+ *
+ * @param[out] uuid128 converted 32-bit Bluetooth UUID to 128-bit UUID
+ * @param[in] uuid UUID to convert to 128-bit UUID
+ * @param[in] uuid_len UUID length
+ *
+ ****************************************************************************************
+ */
+void attm_convert_to128(uint8_t *uuid128, const uint8_t *uuid, uint8_t uuid_len);
+
+/**
+ ****************************************************************************************
+ * @brief Check if it's a Bluetooth 16-bits UUID for 128-bit input
+ *
+ * @param[in] uuid 128-bit UUID
+ *
+ * @return true if uuid is a Bluetooth 16-bit UUID, false else.
+ ****************************************************************************************
+ */
+bool attm_is_bt16_uuid(uint8_t *uuid);
+
+/**
+ ****************************************************************************************
+ * @brief Check if it's a Bluetooth 32 bits UUID for 128-bit input
+ *
+ * @param[in] uuid 128-bit UUID
+ *
+ * @return true if uuid is a Bluetooth 32-bits UUID, false else.
+ ****************************************************************************************
+ */
+bool attm_is_bt32_uuid(uint8_t *uuid);
+
+
+#if (BLE_ATTS)
+/**
+ ****************************************************************************************
+ * @brief Function use to ease service database creation.
+ * Use @see attmdb_add_service function of attmdb module to create service database,
+ * then use @see attmdb_add_attribute function of attmdb module to create attributes
+ * according to database description array given in parameter.
+ *
+ * @note: database description array shall be const to reduce memory consumption (only ROM)
+ * @note: It supports only 16 bits UUIDs
+ *
+ * @note: If shdl = 0, it return handle using first available handle (shdl is
+ * modified); else it verifies if start handle given can be used to allocates handle range.
+ *
+ * @param[in|out] shdl Service start handle.
+ * @param[in] uuid Service UUID
+ * @param[in|out] cfg_flag Configuration Flag, each bit matches with an attribute of
+ * att_db (Max: 32 attributes); if the bit is set to 1, the
+ * attribute will be added in the service.
+ * @param[in] max_nb_att Number of attributes in the service
+ * @param[in|out] att_tbl Array which will be fulfilled with the difference between
+ * each characteristic handle and the service start handle.
+ * This array is useful if several characteristics are optional
+ * within the service, can be set to NULL if not needed.
+ * @param[in] dest_id Task ID linked to the service. This task will be notified
+ * each time the service content is modified by a peer device.
+ * @param[in|out] att_db Table containing all attributes information
+ * @param[in] svc_perm Service permission (@see enum attm_svc_perm_mask)
+ *
+ * @return Command status code:
+ * - @ref ATT_ERR_NO_ERROR: If database creation succeeds.
+ * - @ref ATT_ERR_INVALID_HANDLE: If start_hdl given in parameter + nb of attribute override
+ * some existing services handles.
+ * - @ref ATT_ERR_INSUFF_RESOURCE: There is not enough memory to allocate service buffer.
+ * or of new attribute cannot be added because all expected
+ * attributes already added or buffer overflow detected during
+ * allocation
+ ****************************************************************************************
+ */
+uint8_t attm_svc_create_db(uint16_t *shdl, uint16_t uuid, uint8_t *cfg_flag, uint8_t max_nb_att,
+ uint8_t *att_tbl, ke_task_id_t const dest_id,
+ const struct attm_desc *att_db, uint8_t svc_perm);
+
+
+
+/**
+ ****************************************************************************************
+ * @brief Function use to ease service database creation.
+ * Use @see attmdb_add_service function of attmdb module to create service database,
+ * then use @see attmdb_add_attribute function of attmdb module to create attributes
+ * according to database description array given in parameter.
+ *
+ * @note: database description array shall be const to reduce memory consumption (only ROM)
+ * @note: It supports 128, 32 and 16 bits UUIDs
+ *
+ * @note: If shdl = 0, it return handle using first available handle (shdl is
+ * modified); else it verifies if start handle given can be used to allocates handle range.
+ *
+ * @param[in|out] shdl Service start handle.
+ * @param[in] uuid Service UUID
+ * @param[in|out] cfg_flag Configuration Flag, each bit matches with an attribute of
+ * att_db (Max: 32 attributes); if the bit is set to 1, the
+ * attribute will be added in the service.
+ * @param[in] max_nb_att Number of attributes in the service
+ * @param[in|out] att_tbl Array which will be fulfilled with the difference between
+ * each characteristic handle and the service start handle.
+ * This array is useful if several characteristics are optional
+ * within the service, can be set to NULL if not needed.
+ * @param[in] dest_id Task ID linked to the service. This task will be notified
+ * each time the service content is modified by a peer device.
+ * @param[in|out] att_db Table containing all attributes information
+ * @param[in] svc_perm Service permission (@see enum attm_svc_perm_mask)
+ *
+ * @return Command status code:
+ * - @ref ATT_ERR_NO_ERROR: If database creation succeeds.
+ * - @ref ATT_ERR_INVALID_HANDLE: If start_hdl given in parameter + nb of attribute override
+ * some existing services handles.
+ * - @ref ATT_ERR_INSUFF_RESOURCE: There is not enough memory to allocate service buffer.
+ * or of new attribute cannot be added because all expected
+ * attributes already added or buffer overflow detected during
+ * allocation
+ ****************************************************************************************
+ */
+uint8_t attm_svc_create_db_128(uint16_t *shdl, const uint8_t* uuid, uint8_t *cfg_flag, uint8_t max_nb_att,
+ uint8_t *att_tbl, ke_task_id_t const dest_id,
+ const struct attm_desc_128 *att_db, uint8_t svc_perm);
+
+/**
+ ****************************************************************************************
+ * @brief Function use to verify if several services can be allocated on a contiguous
+ * handle range. If this command succeed, it means that service allocation will succeed.
+ *
+ * If start_hdl = 0, it return handle using first available handle (start_hdl is
+ * modified); else it verifies if start handle given can be used to allocates handle range.
+ *
+ * @param[in|out] start_hdl Service start handle.
+ * @param[in] nb_att Number of handle to allocate (containing service handles)
+ *
+ * @return Command status code:
+ * - @ref ATT_ERR_NO_ERROR: If service allocation succeeds.
+ * - @ref ATT_ERR_INVALID_HANDLE: If start_hdl given in parameter or UUIDs value invalid
+ ****************************************************************************************
+ */
+uint8_t attm_reserve_handle_range(uint16_t* start_hdl, uint8_t nb_att);
+
+
+
+/**
+ ****************************************************************************************
+ * @brief Update attribute value
+ *
+ * Updating attribute value do not trigger any notification or indication, this shall be
+ * handled by GATT task.
+ *
+ * @param[in] handle Attribute handle.
+ * @param[in] length Size of new attribute value
+ * @param[in] offset Data offset of in the payload to set
+ * @param[in] value Attribute value payload
+ *
+ * @return Command status code:
+ * - @ref ATT_ERR_NO_ERROR: If attribute value update succeeds
+ * - @ref ATT_ERR_INVALID_HANDLE: If handle doesn't exist in database
+ * - @ref ATT_ERR_REQUEST_NOT_SUPPORTED: If attribute data not present in database or
+ * cannot be modified
+ * - @ref ATT_ERR_INVALID_ATTRIBUTE_VAL_LEN: If new value length exceeds maximum attribute
+ * value length.
+ *
+ ****************************************************************************************
+ */
+uint8_t attm_att_set_value(uint16_t handle, att_size_t length, att_size_t offset, uint8_t* value);
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve attribute value
+
+ *
+ * @param[in] handle Attribute handle.
+ * @param[out] length Size of attribute value
+ * @param[out] value Pointer to attribute value payload
+ *
+ * @return Command status code:
+ * - @ref ATT_ERR_NO_ERROR: If request succeeds
+ * - @ref ATT_ERR_INVALID_HANDLE: If handle doesn't exist in database
+ * - @ref ATT_ERR_REQUEST_NOT_SUPPORTED: If attribute data not present in database
+ ****************************************************************************************
+ */
+uint8_t attm_get_value(uint16_t handle, att_size_t* length, uint8_t** value);
+
+
+/**
+ ****************************************************************************************
+ * @brief Update attribute permission
+ *
+ * @param[in] handle Attribute handle.
+ * - @ref ATT_ERR_REQUEST_NOT_SUPPORTED: If attribute data not present in database
+ * @param[in] perm New attribute permission
+ * @param[in] ext_perm New attribute extended permission
+ *
+ * @return Command status code:
+ * - @ref ATT_ERR_NO_ERROR: If request succeeds
+ * - @ref ATT_ERR_INVALID_HANDLE: If handle doesn't exist in database
+ * - @ref ATT_ERR_REQUEST_NOT_SUPPORTED: If attribute permission is fixed
+ ****************************************************************************************
+ */
+uint8_t attm_att_set_permission(uint16_t handle, uint16_t perm, uint16_t ext_perm);
+
+
+/**
+ ****************************************************************************************
+ * @brief Reset some permissions bit in the Handle passed as parameter.
+ *
+ * @param[in] handle Attribute handle.
+ * @param[in] access_mask Access mask of permission to update
+ * @param[in] perm New value of the permission to update
+ *
+ *
+ * @return Command status code:
+ * - @ref ATT_ERR_NO_ERROR: If request succeeds
+ * - @ref ATT_ERR_INVALID_HANDLE: If handle doesn't exist in database
+ * - @ref ATT_ERR_REQUEST_NOT_SUPPORTED: If attribute permission is fixed
+ ****************************************************************************************
+ */
+uint8_t attm_att_update_perm(uint16_t handle, uint16_t access_mask, uint16_t perm);
+
+/**
+ ****************************************************************************************
+ * @brief Update attribute service permission
+ *
+ * @param[in] handle Attribute handle.
+ * @param[in] perm New attribute permission
+ *
+ * @return Command status code:
+ * - @ref ATT_ERR_NO_ERROR: If request succeeds
+ * - @ref ATT_ERR_INVALID_HANDLE: If handle doesn't exist in database
+ ****************************************************************************************
+ */
+uint8_t attm_svc_set_permission(uint16_t handle, uint8_t perm);
+
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve attribute service permission
+ *
+ * @param[in] handle Attribute handle.
+ * @param[out] perm Permission value to return
+ *
+ * @return Command status code:
+ * - @ref ATT_ERR_NO_ERROR: If request succeeds
+ * - @ref ATT_ERR_INVALID_HANDLE: If handle doesn't exist in database
+ ****************************************************************************************
+ */
+uint8_t attm_svc_get_permission(uint16_t handle, uint8_t* perm);
+
+
+/**
+ ****************************************************************************************
+ * @brief Clear database
+ *
+ * For debug purpose only, this function clear the database and unalloc all services
+ * within database.
+ *
+ * This function shall be used only for qualification and tests in order to manually
+ * change database without modifying software.
+ ****************************************************************************************
+ */
+void attmdb_destroy(void);
+
+/**
+ ****************************************************************************************
+ * @brief Initialize Attribute Database (clear it)
+ *
+ * @param[in] reset true if it's requested by a reset; false if it's boot initialization
+ ****************************************************************************************
+ */
+void attm_init(bool reset);
+#endif // (BLE_ATTS)
+
+#endif // #if (BLE_CENTRAL || BLE_PERIPHERAL)
+/// @} ATTM
+#endif // ATTM_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/attm_db.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/attm_db.h
new file mode 100644
index 0000000000..eb484e804e
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/attm_db.h
@@ -0,0 +1,368 @@
+/**
+ ****************************************************************************************
+ *
+ * @file attm_db.h
+ *
+ * @brief Header file - ATTM.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef ATTM_DB_H_
+#define ATTM_DB_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup ATTDB Database
+ * @ingroup ATTM
+ * @brief Attribute Protocol Database
+ *
+ * The ATTDB module is responsible for providing different sets of attribute databases
+ * for Attribute Profile server.
+ *
+ * This module can be tailored by client, to match the requirement of the desired database.
+ *
+ * @{
+ *
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "rwip_config.h"
+#if (BLE_ATTS)
+#include
+#include "rwip_config.h"
+#include "ke_task.h"
+#include "attm.h"
+#include "gattm_task.h"
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+
+/*
+ * TYPE DEFINITION
+ ****************************************************************************************
+ */
+#if (BLE_ATTS)
+
+/**
+ * Attribute Description
+ */
+struct attm_att_desc
+{
+ /**
+ * 16 bits UUID or data offset used to retrieve 32 or 128 bits UUID in service memory block
+ */
+ uint16_t uuid;
+
+ /**
+ * Attribute Permission (@see attm_perm_mask)
+ */
+ uint16_t perm;
+
+ /**
+ * value information (@see attm_value_perm_mask)
+ */
+ union att_info
+ {
+ /// attribute max length (RI = 1)
+ uint16_t max_length;
+
+ /// attribute value offset pointer (RI = 0)
+ uint16_t offset;
+ } info;
+};
+
+/// attribute value if present in database
+struct attm_att_value
+{
+ /// Maximum attribute length
+ uint16_t max_length;
+ /// currrent attribute length that can be read.
+ uint16_t length;
+ ///value data pointer
+ uint8_t value[__ARRAY_EMPTY];
+};
+
+/// service description
+struct attm_svc_desc
+{
+ /// Service Start Handle
+ uint16_t start_hdl;
+ /// Service End Handle
+ uint16_t end_hdl;
+ /// Task identifier that manages service
+ uint16_t task_id;
+
+ /**
+ * Service Permission (@see attm_svc_perm_mask)
+ */
+ uint8_t perm;
+
+ /// number of attributes present in service (end_hdl - start_hdl - 1)
+ uint8_t nb_att;
+
+ /// Service 16 bits UUID (LSB First) or data offset used to retrieve 32 or 128 bits
+ /// UUID in service memory block
+ uint16_t uuid;
+};
+
+/**
+ * Service description present in attribute database
+ */
+struct attm_svc
+{
+ /// Next Service
+ struct attm_svc* next;
+
+ /// service description
+ struct attm_svc_desc svc;
+
+ /**
+ * List of attribute description present in service.
+ */
+ struct attm_att_desc atts[__ARRAY_EMPTY];
+};
+
+/// Attribute element information
+struct attm_elmt
+{
+ /// element info
+ union elem_info
+ {
+ /// attribute info pointer
+ struct attm_att_desc* att;
+
+ /// service info pointer
+ struct attm_svc_desc* svc;
+ } info;
+
+ /// use to know if current element is a service or an attribute
+ bool service;
+};
+
+/// ATTM General Information Manager
+struct attm_db
+{
+ /**
+ * **************************************************************************************
+ * @brief Attribute database
+ *
+ * The Attribute database is a list of attribute services sorted by handle number.
+ * This database shall be initiate by GAP, GATT, profiles and application process at
+ * startup and must not change during runtime.
+ *
+ * Database initialization shall be deterministic in order to always have service handle
+ * at same position in database during all product life-cycle. This is required since
+ * database client can save position of services in database to not perform service
+ * discovery at each connection.
+ ***************************************************************************************
+ */
+ struct attm_svc * svcs;
+
+ /**
+ ***************************************************************************************
+ * Last attribute service searched.
+ *
+ * Used as a cached variable, it's used to reduce handle search duration.
+ ***************************************************************************************
+ */
+ struct attm_svc * cache;
+
+ /**
+ * Temporary value used for read operation on service and characteristics attributes
+ */
+ uint8_t temp_val[ATT_UUID_128_LEN + ATT_HANDLE_LEN + ATT_HANDLE_LEN];
+};
+
+
+
+
+
+#endif //(BLE_ATTS)
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+/**
+ * Check if Service handle Range can be allocated in Database, and if handle should be
+ * dynamically allocated, calculate first available handle range.
+ *
+ * @param[in|out] svc_desc Service information to add in DB
+ *
+ * @return status of operation
+ */
+uint8_t attmdb_svc_check_hdl(struct gattm_svc_desc* svc_desc);
+
+/**
+ ****************************************************************************************
+ * @brief Add a service in database.
+ *
+ * According to service start handle and number of attribute, ATTM DB allocate a set of
+ * attribute handles, then using other parameters it allocate a buffer used to describe
+ * service, and allocate attributes + their values.
+ *
+ * If start_hdl = 0, it allocated service using first available handle (start_hdl is
+ * modified); else it will allocate service according to given start handle.
+ *
+ *
+ * @param[in|out] svc_desc Service description.
+ *
+ * @return Command status code:
+ * - @ref ATT_ERR_NO_ERROR: If service allocation succeeds.
+ * - @ref ATT_ERR_INVALID_HANDLE: If start_hdl given in parameter or UUIDs value invalid
+ * - @ref ATT_ERR_INSUFF_RESOURCE: There is not enough memory to allocate service buffer.
+ ****************************************************************************************
+ */
+uint8_t attmdb_add_service(struct gattm_svc_desc* svc_desc);
+
+
+
+
+/**
+ ****************************************************************************************
+ * @brief Search in database from which service attribute handle comes from.
+ *
+ * @param[in] handle Attribute handle.
+ *
+ * @return Services that contains attribute handle; NULL if handle not available in
+ * database.
+ ****************************************************************************************
+ */
+struct attm_svc * attmdb_get_service(uint16_t handle);
+
+/**
+ ****************************************************************************************
+ * @brief Search in database Attribute pointer using attribute handle.
+ *
+ * @param[in] handle Attribute handle.
+ * @param[out] elmt Attribute element to fill
+ *
+ * @return Command status code:
+ * - @ref ATT_ERR_NO_ERROR: If attribute found.
+ * - @ref ATT_ERR_INVALID_HANDLE: If No Attribute found
+ ****************************************************************************************
+ */
+uint8_t attmdb_get_attribute(uint16_t handle, struct attm_elmt*elmt);
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve attribute at or after specified handle
+ *
+ * Retrieve first attribute with handle >= parameter handle.
+ * Parameter handle is updated according found attribute.
+ *
+ * @param[in|out] handle Attribute handle.
+ * @param[out] elmt Attribute element to fill
+ *
+ * @return Command status code:
+ * - @ref ATT_ERR_NO_ERROR: If attribute found.
+ * - @ref ATT_ERR_INVALID_HANDLE: If No Attribute found
+ ****************************************************************************************
+ */
+uint8_t attmdb_get_next_att(uint16_t * handle, struct attm_elmt*elmt);
+
+/**
+ ****************************************************************************************
+ * Check if attribute element UUID is equals to uuid given in parameter.
+ *
+ * @param elmt Attribute element that can be a UUID 16 or 128 bits
+ * @param uuid16 UUID 16 bits to compare
+ *
+ * @return True if UUIDs matches, False else.
+ ****************************************************************************************
+ */
+bool attmdb_uuid16_comp(struct attm_elmt *elmt, uint16_t uuid16);
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve attribute value Max Length
+ *
+ * @param[in] elmt Attribute element information
+ * @param[out] length Max length Size of attribute value
+ *
+ * @return Command status code:
+ * - @ref ATT_ERR_NO_ERROR: If request succeeds
+ * - @ref ATT_ERR_REQUEST_NOT_SUPPORTED: If attribute is read only
+ ****************************************************************************************
+ */
+uint8_t attmdb_get_max_len(struct attm_elmt* elmt, att_size_t* length);
+
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve attribute UUID
+ *
+ * @param[in] elmt Attribute information.
+ * @param[out] uuid_len Size of attribute UUID
+ * @param[out] uuid UUID value to update
+ * @param[in] srv_uuid For a service, if set, return service UUID
+ * @param[in] air Prepare UUID for the air (For a 32 bit UUID, returns a 128 bit UUID)
+ *
+ * @return Command status code:
+ * - @ref ATT_ERR_NO_ERROR: If request succeeds
+ * - @ref ATT_ERR_INVALID_HANDLE: If handle doesn't exist in database
+ ****************************************************************************************
+ */
+uint8_t attmdb_get_uuid(struct attm_elmt *elmt, uint8_t* uuid_len, uint8_t* uuid, bool srv_uuid, bool air);
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve attribute permission
+ * If access mask is set, service authentication or encryption key size value can be loaded.
+ *
+ * @param[in] handle Attribute handle.
+ * @param[out] perm Permission value to return
+ * @param[in] mode_mask Mode Access mask to check type of access
+ * parameter (0 return full attribute permission)
+ * @param[in] perm_mask Permission Access mask to check only specific permission
+ * @param[in|out] elmt Attribute information
+ *
+ * @return Command status code:
+ * - @ref ATT_ERR_NO_ERROR: If request succeeds
+ * - @ref ATT_ERR_INVALID_HANDLE: If handle doesn't exist in database.
+ * - @ref ATT_ERR_REQUEST_NOT_SUPPORTED: If mode is disabled.
+ * - @ref ATT_ERR_INSUFF_AUTHOR: when service is disabled.
+ * - @ref ATT_ERR_INSUFF_ENC_KEY_SIZE:
+ ****************************************************************************************
+ */
+uint8_t attmdb_att_get_permission(uint16_t handle, uint16_t* perm, uint16_t mode_mask,
+ uint16_t perm_mask, struct attm_elmt *elmt);
+
+
+#if (BLE_DEBUG)
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve number of services.
+ *
+ * @return number of services
+ ****************************************************************************************
+ */
+uint8_t attmdb_get_nb_svc(void);
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve services informations
+ *
+ * @param[in] svc_info Services information array to update
+ ****************************************************************************************
+ */
+void attmdb_get_svc_info(struct gattm_svc_info* svc_info);
+#endif /* (BLE_DEBUG) */
+
+#endif // #if (BLE_ATTS)
+
+/// @} ATTDB
+#endif // ATTM_DB_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/atts.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/atts.h
new file mode 100644
index 0000000000..850ce94d5b
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/atts.h
@@ -0,0 +1,158 @@
+/**
+ ****************************************************************************************
+ *
+ * @file atts.h
+ *
+ * @brief Header file - ATTS.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef ATTS_H_
+#define ATTS_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup ATTS Attribute Server
+ * @ingroup ATT
+ * @brief Attribute Protocol Server
+ *
+ * The ATTS module is responsible for handling messages intended for the attribute
+ * profile server. It has defined interfaces with @ref ATTM "ATTM".
+ *
+ *
+ * @{
+ *
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "rwip_config.h"
+#if (BLE_ATTS)
+#include "att.h"
+//#include "compiler.h"
+#include "ble_arch.h"
+#include
+#include "co_list.h"
+#include "gattc_task.h"
+#include "l2cc.h"
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+
+
+/*
+ * GLOBAL VARIABLE DECLARATIONS
+ ****************************************************************************************
+ */
+
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+
+/**
+ * Confirmation of write signed (signature verified)
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] length Signed Data Length
+ * @param[in] sign_data Signed Data
+ */
+void atts_write_signed_cfm(uint8_t conidx, uint16_t length, uint8_t* sign_data);
+
+
+/**
+ ****************************************************************************************
+ * @brief Send an attribute error response to peer.
+ *
+ * @param[in] conidx Index of the connection with the peer device
+ * @param[in] opcode failing operation code
+ * @param[in] uuid attribute UUID
+ * @param[in] error error code
+ ****************************************************************************************
+ */
+void atts_send_error(uint8_t conidx, uint8_t opcode, uint16_t uuid, uint8_t error);
+
+
+/**
+ ****************************************************************************************
+ * @brief Format the Write Response PDU and send it after receiving a Write Request PDU
+ * @param[in] conidx Index of the connection with the peer device
+ * @param[in] atthdl Attribute handle for which to send the response
+ * @param[in] status ATT error code
+ ****************************************************************************************
+ */
+void atts_write_rsp_send(uint8_t conidx, uint16_t atthdl, uint8_t status);
+
+
+/**
+ ****************************************************************************************
+ * @brief Sends a value notification/indication command
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] event Event parameters to send
+ *
+ * @return If notification can be sent or not
+ ****************************************************************************************
+ */
+uint8_t atts_send_event(uint8_t conidx, struct gattc_send_evt_cmd *event);
+
+
+/**
+ * @brief Clear allocated prepare write temporary data.
+ *
+ * @param[in] conidx connection index
+ */
+void atts_clear_prep_data(uint8_t conidx);
+
+
+/**
+ * @brief Clear allocated temporary data used for ATTS response.
+ *
+ * @param[in] conidx connection index
+ */
+void atts_clear_rsp_data(uint8_t conidx);
+
+/**
+ * @brief Clear temporary attribute read data present in cache.
+ *
+ * @param[in] conidx connection index
+ */
+void atts_clear_read_cache(uint8_t conidx);
+
+/**
+ * @brief Process execution of a received ATTS PDU.
+ *
+ * @param conidx connection index
+ */
+void atts_process_pdu(uint8_t conidx);
+
+/// @} ATTS
+#endif /* (BLE_ATTS) */
+
+#if (BLE_CENTRAL || BLE_PERIPHERAL)
+/**
+ ****************************************************************************************
+ * @brief Handles reception of PDU Packet
+ *
+ * @param[in] conidx Index of the connection with the peer device
+ * @param[in] param Received PDU Packet
+ *
+ * @return If message has been proceed or consumed
+ ****************************************************************************************
+ */
+int atts_l2cc_pdu_recv_handler(uint8_t conidx, struct l2cc_pdu_recv_ind *param);
+#endif /* #if (BLE_CENTRAL || BLE_PERIPHERAL) */
+
+#endif // ATTS_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ble_arch.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ble_arch.h
new file mode 100644
index 0000000000..a343638a48
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ble_arch.h
@@ -0,0 +1,283 @@
+/**
+ ****************************************************************************************
+ *
+ * @file ble_arch.h
+ *
+ * @brief This file contains the definitions of the macros and functions that are
+ * architecture dependent. The implementation of those is implemented in the
+ * appropriate architecture directory.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+
+#ifndef _BLE_ARCH_H_
+#define _BLE_ARCH_H_
+
+/**
+ ****************************************************************************************
+ * @defgroup REFIP
+ * @brief Reference IP Platform
+ *
+ * This module contains reference platform components - REFIP.
+ *
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @defgroup DRIVERS
+ * @ingroup REFIP
+ * @brief Reference IP Platform Drivers
+ *
+ * This module contains the necessary drivers to run the platform with the
+ * RW BT SW protocol stack.
+ *
+ * This has the declaration of the platform architecture API.
+ *
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include // standard integer definition
+#include
+#include
+#include "rwip_config.h"
+
+#define GLOBAL_INT_DISABLE() \
+do{\
+ __disable_irq();\ //__set_PRIMASK(1);\
+}while (0);\
+
+#define GLOBAL_INT_RESTORE() \
+do{\
+ __enable_irq();\ // __set_PRIMASK(0);\
+}while (0);\
+
+//#include "compiler.h" // inline functions
+#define __INLINE inline
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+/// define the IRQ handler attribute for this compiler
+#define __IRQ __attribute__ ((interrupt))
+/// define the BLE IRQ handler attribute for this compiler
+#define __BTIRQ
+
+/// define the BLE IRQ handler attribute for this compiler
+#define __BLEIRQ
+
+/// define the FIQ handler attribute for this compiler
+#define __FIQ __attribute__ ((interrupt))
+/// define size of an empty array (used to declare structure with an array size not defined)
+#define __ARRAY_EMPTY
+
+/// Put a variable in a memory maintained during deep sleep
+#define __LOWPOWER_SAVED
+
+
+/*
+ * CPU WORD SIZE
+ ****************************************************************************************
+ */
+/// ARM is a 32-bit CPU
+#define CPU_WORD_SIZE 4
+
+/*
+ * CPU Endianness
+ ****************************************************************************************
+ */
+/// ARM is little endian
+#define CPU_LE 1
+
+
+
+/*
+ * NVDS
+ ****************************************************************************************
+ */
+
+/// NVDS
+#ifdef CFG_NVDS
+#define PLF_NVDS 1
+#else // CFG_NVDS
+#define PLF_NVDS 0
+#endif // CFG_NVDS
+
+
+/*
+ * UART
+ ****************************************************************************************
+ */
+
+/// UART
+#define PLF_UART 1
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/// Possible errors detected by FW
+#define RESET_NO_ERROR 0x00000000
+#define RESET_MEM_ALLOC_FAIL 0xF2F2F2F2
+
+/// Reset platform and stay in ROM
+#define RESET_TO_ROM 0xA5A5A5A5
+/// Reset platform and reload FW
+#define RESET_AND_LOAD_FW 0xC3C3C3C3
+
+/// Exchange memory size limit
+#define EM_SIZE_LIMIT 0x8000
+/*
+ * EXPORTED FUNCTION DECLARATION
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief Compute size of SW stack used.
+ *
+ * This function is compute the maximum size stack used by SW.
+ *
+ * @return Size of stack used (in bytes)
+ ****************************************************************************************
+ */
+uint16_t get_stack_usage(void);
+
+/**
+ ****************************************************************************************
+ * @brief Re-boot FW.
+ *
+ * This function is used to re-boot the FW when error has been detected, it is the end of
+ * the current FW execution.
+ * After waiting transfers on UART to be finished, and storing the information that
+ * FW has re-booted by itself in a non-loaded area, the FW restart by branching at FW
+ * entry point.
+ *
+ * Note: when calling this function, the code after it will not be executed.
+ *
+ * @param[in] error Error detected by FW
+ ****************************************************************************************
+ */
+void platform_reset(uint32_t error);
+
+#if PLF_DEBUG
+/**
+ ****************************************************************************************
+ * @brief Print the assertion error reason and loop forever.
+ *
+ * @param condition C string containing the condition.
+ * @param file C string containing file where the assertion is located.
+ * @param line Line number in the file where the assertion is located.
+ ****************************************************************************************
+ */
+void eif_assert_err(const char *condition, const char * file, int line);
+
+/**
+ ****************************************************************************************
+ * @brief Print the assertion error reason and loop forever.
+ * The parameter value that is causing the assertion will also be disclosed.
+ *
+ * @param param0 parameter value 0.
+ * @param param1 parameter value 1.
+ * @param file C string containing file where the assertion is located.
+ * @param line Line number in the file where the assertion is located.
+ ****************************************************************************************
+ */
+void eif_assert_param(int param0, int param1, const char * file, int line);
+
+/**
+ ****************************************************************************************
+ * @brief Print the assertion warning reason.
+ *
+ * @param param0 parameter value 0.
+ * @param param1 parameter value 1.
+ * @param file C string containing file where the assertion is located.
+ * @param line Line number in the file where the assertion is located.
+ ****************************************************************************************
+ */
+void eif_assert_warn(int param0, int param1, const char * file, int line);
+
+
+/**
+ ****************************************************************************************
+ * @brief Dump data value into FW.
+ *
+ * @param data start pointer of the data.
+ * @param length data size to dump
+ ****************************************************************************************
+ */
+void dump_data(uint8_t* data, uint16_t length);
+#endif //PLF_DEBUG
+
+
+/*
+ * ASSERTION CHECK
+ ****************************************************************************************
+ */
+#if PLF_DEBUG
+
+
+/// Assertions showing a critical error that could require a full system reset
+#define ASSERT_ERR(cond) \
+ do { \
+ if (!(cond)) { \
+ eif_assert_err(#cond, __MODULE__, __LINE__); \
+ } \
+ } while (0)
+
+/// Assertions showing a critical error that could require a full system reset
+#define ASSERT_INFO(cond, param0, param1) \
+ do { \
+ if (!(cond)) { \
+ eif_assert_param((int)param0, (int)param1, __MODULE__, __LINE__); \
+ } \
+ } while (0)
+
+/// Assertions showing a non-critical problem that has to be fixed by the SW
+#define ASSERT_WARN(cond, param0, param1) \
+ do { \
+ if (!(cond)) { \
+ eif_assert_warn((int)param0, (int)param1, __MODULE__, __LINE__); \
+ } \
+ } while (0)
+
+#define DUMP_DATA(data, length) \
+ dump_data((uint8_t*)data, length)
+
+#else
+/// Assertions showing a critical error that could require a full system reset
+#define ASSERT_ERR(cond)
+
+/// Assertions showing a critical error that could require a full system reset
+#define ASSERT_INFO(cond, param0, param1)
+
+/// Assertions showing a non-critical problem that has to be fixed by the SW
+#define ASSERT_WARN(cond, param0, param1)
+
+/// DUMP data array present in the SW.
+#define DUMP_DATA(data, length)
+#endif //PLF_DEBUG
+
+
+/// Object allocated in shared memory - check linker script
+#define __SHARED __attribute__ ((section("shram")))
+
+// required to define GLOBAL_INT_** macros as inline assembly. This file is included after
+// definition of ASSERT macros as they are used inside ll.h
+//#include "ll.h" // ll definitions
+/// @} DRIVERS
+#endif // _BLE_ARCH_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_bt.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_bt.h
new file mode 100644
index 0000000000..ba42fd70f6
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_bt.h
@@ -0,0 +1,62 @@
+/**
+ ****************************************************************************************
+ *
+ * @file co_bt.h
+ *
+ * @brief This file contains the common Bluetooth defines, enumerations and structures
+ * definitions for use by all modules in RW stack.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef CO_BT_H_
+#define CO_BT_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup COMMON Common SW Block
+ * @ingroup ROOT
+ * @brief The Common RW SW Block.
+ *
+ * The COMMON is the block with Bluetooth definitions and structures shared
+ * to all the protocol stack blocks. This also contain software wide error code
+ * definitions, mathematical functions, help functions, list and buffer definitions.
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @addtogroup CO_BT Common Bluetooth defines
+ * @ingroup COMMON
+ * @brief Common Bluetooth definitions and structures.
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include // standard boolean definitions
+#include // standard definitions
+#include // standard integer definitions
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+#include "co_bt_defines.h" // Bluetooth defines
+#include "co_lmp.h" // Bluetooth LMP definitions
+#include "co_hci.h" // Bluetooth HCI definitions
+#include "co_error.h" // Bluetooth error codes definitions
+
+/// @} CO_BT
+#endif // CO_BT_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_bt_defines.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_bt_defines.h
new file mode 100644
index 0000000000..1ff9289315
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_bt_defines.h
@@ -0,0 +1,2120 @@
+/**
+ ****************************************************************************************
+ *
+ * @file co_bt_defines.h
+ *
+ * @brief This file contains the common Bluetooth defines, enumerations and structures
+ * definitions for use by all modules in RW stack.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef CO_BT_DEFINES_H_
+#define CO_BT_DEFINES_H_
+
+
+/**
+ ****************************************************************************************
+ * @addtogroup CO_BT_DEFINES Common Bluetooth defines
+ * @ingroup CO_BT
+ * @brief Common Bluetooth definitions and structures.
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/**
+ * BD Address format (values in bytes)
+ * | 3B | 1B | 2B |
+ * | LAP | UAP | NAP |
+ */
+#define BD_ADDR_LEN 6
+#define BD_ADDR_LAP_POS 0
+#define BD_ADDR_LAP_LEN 3
+#define BD_ADDR_UAP_POS BD_ADDR_LAP_LEN
+#define BD_ADDR_UAP_LEN 1
+#define BD_ADDR_NAP_POS BD_ADDR_UAP_LEN
+#define BD_ADDR_NAP_LEN 2
+
+///Length of fields in Bluetooth messages, in number of bytes
+#define EVT_MASK_LEN 8
+#define DEV_CLASS_LEN 3
+#define ACO_LEN 12
+#define SRES_LEN 0x04
+#define ACCESS_ADDR_LEN 0x04
+#define LE_PASSKEY_LEN 0x04
+#define BD_NAME_SIZE 0x20//0xF8 // Was 0x20 for BLE HL
+#define ADV_DATA_LEN 0x1F
+#define BLE_DATA_LEN 0x1B
+#define SCAN_RSP_DATA_LEN 0x1F
+#define LE_CHNL_MAP_LEN 0x05
+#define CHNL_MAP_LEN 0x0A
+#define KEY_LEN 0x10
+#define PIN_CODE_MIN_LEN 0x01
+#define PIN_CODE_MAX_LEN 0x10
+#define PRIV_KEY_192_LEN 24
+#define PUB_KEY_192_LEN 48
+#define PRIV_KEY_256_LEN 32
+#define PUB_KEY_256_LEN 64
+#define CFM_LEN 0x10
+#define ENC_DATA_LEN 0x10
+#define RAND_VAL_LEN 0x10
+#define RAND_NB_LEN 0x08
+#define LE_FEATS_LEN 0x08
+#define SUPP_CMDS_LEN 0x40
+#define FEATS_LEN 0x08
+#define NAME_VECT_SIZE 14
+#define LMP_FEATS_LEN 0x08
+#define LE_STATES_LEN 0x08
+#define WHITE_LIST_LEN 0x0A
+#define LE_FREQ_LEN 0x28
+#define LE_DATA_FREQ_LEN 0x25
+#define CRC_INIT_LEN 0x03
+#define SESS_KEY_DIV_LEN 0x08
+#define INIT_VECT_LEN 0x04
+#define MIC_LEN 0x04
+#define IV_LEN 0x08
+
+// BT 4.2 - Secure Connections
+#define PUBLIC_KEY_P256_LEN 0x20
+#define DHKEY_CHECK_LEN 0x10
+
+#define DH_KEY_LEN 0x20
+
+/// Maximum maskable event code
+#define EVT_MASK_CODE_MAX EVT_MASK_LEN * 8
+
+/// Format of the Advertising packets
+#define ADV_ADDR_OFFSET 0
+#define ADV_ADDR_LEN BD_ADDR_LEN
+#define ADV_DATA_OFFSET (ADV_ADDR_OFFSET + ADV_ADDR_LEN)
+
+/// BLE supported features
+//byte 0
+#define BLE_ENC_FEATURE 0x01
+#define BLE_CON_PARAM_REQ_PROC_FEATURE 0x02
+#define BLE_REJ_IND_EXT_FEATURE 0x04
+#define BLE_SLAVE_INIT_EXCHG_FEATURE 0x08
+#define BLE_PING_FEATURE 0x10
+#define BLE_LENGTH_EXT_FEATURE 0x20
+#define BLE_LL_PRIVACY_FEATURE 0x40
+#define BLE_EXT_SCAN_POLICY_FEATURE 0x80
+
+/// BLE supported states
+//byte 0
+#define BLE_NON_CON_ADV_STATE 0x01
+#define BLE_DISC_ADV_STATE 0x02
+#define BLE_CON_ADV_STATE 0x04
+#define BLE_HDC_DIRECT_ADV_STATE 0x08
+#define BLE_PASS_SCAN_STATE 0x10
+#define BLE_ACTIV_SCAN_STATE 0x20
+#define BLE_INIT_MASTER_STATE 0x40
+#define BLE_CON_SLAVE_STATE 0x80
+
+//byte 1
+#define BLE_NON_CON_ADV_PASS_SCAN_STATE 0x01
+#define BLE_DISC_ADV_PASS_SCAN_STATE 0x02
+#define BLE_CON_ADV_PASS_SCAN_STATE 0x04
+#define BLE_HDC_DIRECT_ADV_PASS_SCAN_STATE 0x08
+#define BLE_NON_CON_ADV_ACTIV_SCAN_STATE 0x10
+#define BLE_DISC_ADV_ACTIV_SCAN_STATE 0x20
+#define BLE_CON_ADV_ACTIV_SCAN_STATE 0x40
+#define BLE_HDC_DIRECT_ADV_ACTIV_SCAN_STATE 0x80
+
+//byte 2
+#define BLE_NON_CON_ADV_INIT_STATE 0x01
+#define BLE_DISC_ADV_INIT_STATE 0x02
+#define BLE_NON_CON_ADV_MASTER_STATE 0x04
+#define BLE_DISC_ADV_MASTER_STATE 0x08
+#define BLE_NON_CON_ADV_SLAVE_STATE 0x10
+#define BLE_DISC_ADV_SLAVE_STATE 0x20
+#define BLE_PASS_SCAN_INIT_STATE 0x40
+#define BLE_ACTIV_SCAN_INIT_STATE 0x80
+
+//byte 3
+#define BLE_PASS_SCAN_MASTER_STATE 0x01
+#define BLE_ACTIV_SCAN_MASTER_STATE 0x02
+#define BLE_PASS_SCAN_SLAVE_STATE 0x04
+#define BLE_ACTIV_SCAN_SLAVE_STATE 0x08
+#define BLE_INIT_MASTER_MASTER_STATE 0x10
+#define BLE_LDC_DIRECT_ADV_STATE 0x20
+#define BLE_LDC_DIRECT_ADV_PASS_SCAN_STATE 0x40
+#define BLE_LDC_DIRECT_ADV_ACTIV_SCAN_STATE 0x80
+
+//byte 4
+#define BLE_CON_ADV_INIT_MASTER_SLAVE_STATE 0x01
+#define BLE_HDC_DIRECT_ADV_INIT_MASTER_SLAVE_STATE 0x02
+#define BLE_LDC_DIRECT_ADV_INIT_MASTER_SLAVE_STATE 0x04
+#define BLE_CON_ADV_MASTER_SLAVE_STATE 0x08
+#define BLE_HDC_DIRECT_ADV_MASTER_SLAVE_STATE 0x10
+#define BLE_LDC_DIRECT_ADV_MASTER_SLAVE_STATE 0x20
+#define BLE_CON_ADV_SLAVE_SLAVE_STATE 0x40
+#define BLE_HDC_DIRECT_ADV_SLAVE_SLAVE_STATE 0x80
+
+//byte 5
+#define BLE_LDC_DIRECT_ADV_SLAVE_SLAVE_STATE 0x01
+#define BLE_INIT_MASTER_SLAVE_STATE 0x02
+
+/// BLE supported commands
+//byte0
+#define BLE_DISC_CMD 0x20
+//byte2
+#define BLE_RD_REM_VERS_CMD 0x80
+//byte5
+#define BLE_SET_EVT_MSK_CMD 0x40
+#define BLE_RESET_CMD 0x80
+//byte10
+#define BLE_RD_TX_PWR_CMD 0x04
+#define BLE_SET_CTRL_TO_HL_FCTRL_CMD 0x20
+#define BLE_HL_BUF_SIZE_CMD 0x40
+#define BLE_HL_NB_CMP_PKT_CMD 0x80
+//byte14
+#define BLE_RD_LOC_VERS_CMD 0x08
+#define BLE_RD_LOC_SUP_FEAT_CMD 0x20
+#define BLE_RD_BUF_SIZE_CMD 0x80
+//byte15
+#define BLE_RD_BD_ADDR_CMD 0x02
+#define BLE_RD_RSSI_CMD 0x20
+//byte22
+#define BLE_SET_EVT_MSK_PG2_CMD 0x04
+//byte25
+#define BLE_LE_SET_EVT_MSK_CMD 0x01
+#define BLE_LE_RD_BUF_SIZE_CMD 0x02
+#define BLE_LE_RD_LOC_SUP_FEAT_CMD 0x04
+#define BLE_LE_SET_RAND_ADDR_CMD 0x10
+#define BLE_LE_SET_ADV_PARAM_CMD 0x20
+#define BLE_LE_RD_ADV_TX_PWR_CMD 0x40
+#define BLE_LE_SET_ADV_DATA_CMD 0x80
+//byte26
+#define BLE_LE_SET_SC_RSP_DATA_CMD 0x01
+#define BLE_LE_SET_ADV_EN_CMD 0x02
+#define BLE_LE_SET_SC_PARAM_CMD 0x04
+#define BLE_LE_SET_SC_EN_CMD 0x08
+#define BLE_LE_CREAT_CNX_CMD 0x10
+#define BLE_LE_CREAT_CNX_CNL_CMD 0x20
+#define BLE_LE_RD_WL_SIZE_CMD 0x40
+#define BLE_LE_CLEAR_WL_CMD 0x80
+//byte27
+#define BLE_LE_ADD_DEV_WL_CMD 0x01
+#define BLE_LE_REM_DEV_WL_CMD 0x02
+#define BLE_LE_CNX_UPDATE_CMD 0x04
+#define BLE_LE_SET_HL_CH_CLASS_CMD 0x08
+#define BLE_LE_RD_CH_MAP_CMD 0x10
+#define BLE_LE_RD_REM_USED_FEAT_CMD 0x20
+#define BLE_LE_ENCRYPT_CMD 0x40
+#define BLE_LE_RAND_CMD 0x80
+//byte28
+#define BLE_LE_START_ENC_CMD 0x01
+#define BLE_LE_LTK_REQ_RPLY_CMD 0x02
+#define BLE_LE_LTK_REQ_NEG_RPLY_CMD 0x04
+#define BLE_LE_RD_SUPP_STATES_CMD 0x08
+#define BLE_LE_RX_TEST_CMD 0x10
+#define BLE_LE_TX_TEST_CMD 0x20
+#define BLE_LE_STOP_TEST_CMD 0x40
+
+//byte32
+#define BLE_RD_AUTH_PAYL_TO_CMD 0x10
+#define BLE_WR_AUTH_PAYL_TO_CMD 0x20
+
+
+//byte33
+#define BLE_LE_REM_CON_PARA_REQ_RPLY_CMD 0x10
+#define BLE_LE_REM_CON_PARA_REQ_NEG_RPLY_CMD 0x20
+#define BLE_LE_SET_DATA_LEN_CMD 0x40
+#define BLE_LE_RD_SUGGTED_DFT_DATA_LEN_CMD 0x80
+
+//byte34
+#define BLE_LE_WR_SUGGTED_DFT_DATA_LEN_CMD 0x01
+#define BLE_LE_RD_LOC_P256_PUB_KEY_CMD 0x02
+#define BLE_LE_GEN_DH_KEY_CMD 0x04
+#define BLE_LE_ADD_DEV_TO_RESOLV_LIST_CMD 0x08
+#define BLE_LE_REM_DEV_FROM_RESOLV_LIST_CMD 0x10
+#define BLE_LE_CLEAR_RESOLV_LIST_CMD 0x20
+#define BLE_LE_RD_RESOLV_LIST_SIZE_CMD 0x40
+#define BLE_LE_RD_PEER_RESOLV_ADDR_CMD 0x80
+
+//byte35
+#define BLE_LE_RD_LOCAL_RESOLV_ADDR_CMD 0x01
+#define BLE_LE_SET_ADDR_RESOL_CMD 0x02
+#define BLE_LE_SET_RESOLV_PRIV_ADDR_TO_CMD 0x04
+#define BLE_LE_RD_MAX_DATA_LEN_CMD 0x08
+
+// Inquiry Length HCI:7.1.1
+#define INQ_LEN_MIN 0x01
+#define INQ_LEN_MAX 0x30
+
+// Inquiry Length HCI:7.1.3
+#define INQ_MIN_PER_LEN_MIN 0x0002
+#define INQ_MIN_PER_LEN_MAX 0xFFFE
+#define INQ_MAX_PER_LEN_MIN 0x0003
+#define INQ_MAX_PER_LEN_MAX 0xFFFF
+
+// IAC support
+#define NB_IAC_MIN 0x01
+#define NB_IAC_MAX 0x40
+
+/// Maximum value of a Bluetooth clock (in 625us slots)
+#define MAX_SLOT_CLOCK ((1L<<27) - 1)
+
+
+/// Logical Transport Adresses BB:4.2
+#define LT_ADDR_BCST 0x00
+#define LT_ADDR_MIN 0x01
+#define LT_ADDR_MAX 0x07
+
+/// Link type HCI:7.7.3
+#define SCO_TYPE 0
+#define ACL_TYPE 1
+#define ESCO_TYPE 2
+#define UNKNOWN_TYPE 3 // Used in LM
+#define LE_TYPE 4
+
+
+/// Allow Role Switch HCI:4.6.8
+#define MASTER_ROLE 0
+#define SLAVE_ROLE 1
+#define UNKNOWN_ROLE 0xFF //Used in LC to init the links role
+
+/// Link policy HCI:4.6.9 and HCI:4.6.10
+#define POLICY_SWITCH 0x0001
+#define POLICY_HOLD 0x0002
+#define POLICY_SNIFF 0x0004
+#define POLICY_PARK 0x0008
+
+/// Allow Role Switch HCI:4.5.5
+#define ROLE_SWITCH_NOT_ALLOWED 0
+#define ROLE_SWITCH_ALLOWED 1
+
+/// AcceptConnection Role HCI:4.5.8
+#define ACCEPT_SWITCH_TO_MASTER 0
+#define ACCEPT_REMAIN_SLAVE 1
+
+/// Packet Type Flags HCI:7.1.14
+#define PACKET_TYPE_EDR_MSK 0x330E
+#define PACKET_TYPE_GFSK_MSK 0xCCF8
+#define PACKET_TYPE_NO_2_DH1_FLAG 0x0002
+#define PACKET_TYPE_NO_3_DH1_FLAG 0x0004
+#define PACKET_TYPE_DM1_FLAG 0x0008
+#define PACKET_TYPE_DH1_FLAG 0x0010
+#define PACKET_TYPE_HV1_FLAG 0x0020
+#define PACKET_TYPE_HV2_FLAG 0x0040
+#define PACKET_TYPE_HV3_FLAG 0x0080
+#define PACKET_TYPE_NO_2_DH3_FLAG 0x0100
+#define PACKET_TYPE_NO_3_DH3_FLAG 0x0200
+#define PACKET_TYPE_DM3_FLAG 0x0400
+#define PACKET_TYPE_DH3_FLAG 0x0800
+#define PACKET_TYPE_NO_2_DH5_FLAG 0x1000
+#define PACKET_TYPE_NO_3_DH5_FLAG 0x2000
+#define PACKET_TYPE_DM5_FLAG 0x4000
+#define PACKET_TYPE_DH5_FLAG 0x8000
+
+/// Synchronous Packet Types HCI:7.1.14
+#define SYNC_PACKET_TYPE_HV1_FLAG 0x0001
+#define SYNC_PACKET_TYPE_HV2_FLAG 0x0002
+#define SYNC_PACKET_TYPE_HV3_FLAG 0x0004
+#define SYNC_PACKET_TYPE_EV3_FLAG 0x0008
+#define SYNC_PACKET_TYPE_EV4_FLAG 0x0010
+#define SYNC_PACKET_TYPE_EV5_FLAG 0x0020
+
+#define SYNC_PACKET_TYPE_NO_EV3_2_FLAG 0x0040
+#define SYNC_PACKET_TYPE_NO_EV3_3_FLAG 0x0080
+#define SYNC_PACKET_TYPE_NO_EV5_2_FLAG 0x0100
+#define SYNC_PACKET_TYPE_NO_EV5_3_FLAG 0x0200
+
+#define SYNC_PACKET_TYPE_EV3_2_FLAG 0x0040
+#define SYNC_PACKET_TYPE_EV3_3_FLAG 0x0080
+#define SYNC_PACKET_TYPE_EV5_2_FLAG 0x0100
+#define SYNC_PACKET_TYPE_EV5_3_FLAG 0x0200
+
+/// RWBT 1.2
+#define SYNC_EV3_PACKET_SIZE 30
+#define SYNC_EV4_PACKET_SIZE 120
+#define SYNC_EV5_PACKET_SIZE 180
+
+/// Packet Boundary Flag HCI:5.4.2
+#define PBF_1ST_NF_HL_FRAG 0x00 // Non-flushable packets
+#define PBF_CONT_HL_FRAG 0x01
+#define PBF_1ST_HL_FRAG 0x02
+#define PBF_CMP_PDU 0x03
+#define PBF_MASK 0x03
+
+/// Broadcast Flag HCI:5.4.2
+#define BCF_P2P 0x00
+#define BCF_ACTIVE_SLV_BCST 0x04
+#define BCF_PARK_SLV_BCST 0x08
+#define BCF_MASK 0x0C
+
+/// Synchronous Packet Status Flag HCI:5.4.3
+#define CORRECTLY_RX_FLAG 0x00
+#define POSSIBLY_INVALID_FLAG 0x01
+#define NO_RX_DATA_FLAG 0x02
+#define PARTIALLY_LOST_FLAG 0x03
+
+/// Park mode defines LMP:3.17
+#define MACCESS_MSK 0x0F
+#define ACCSCHEM_MSK 0xF0
+
+/// Support 3 feature pages
+#define FEATURE_PAGE_MAX 3
+
+#define FEATURE_PAGE_0 0
+#define FEATURE_PAGE_1 1
+#define FEATURE_PAGE_2 2
+
+/// Feature mask definition LMP:3.3
+#define B0_3_SLOT_POS 0
+#define B0_3_SLOT_MSK 0x01
+#define B0_5_SLOT_POS 1
+#define B0_5_SLOT_MSK 0x02
+#define B0_ENC_POS 2
+#define B0_ENC_MSK 0x04
+#define B0_SLOT_OFF_POS 3
+#define B0_SLOT_OFF_MSK 0x08
+#define B0_TIMING_ACCU_POS 4
+#define B0_TIMING_ACCU_MSK 0x10
+#define B0_ROLE_SWITCH_POS 5
+#define B0_ROLE_SWITCH_MSK 0x20
+#define B0_HOLD_MODE_POS 6
+#define B0_HOLD_MODE_MSK 0x40
+#define B0_SNIFF_MODE_POS 7
+#define B0_SNIFF_MODE_MSK 0x80
+
+#define B1_PARK_POS 0
+#define B1_PARK_MSK 0x01
+#define B1_RSSI_POS 1
+#define B1_RSSI_MSK 0x02
+#define B1_CQDDR_POS 2
+#define B1_CQDDR_MSK 0x04
+#define B1_SCO_POS 3
+#define B1_SCO_MSK 0x08
+#define B1_HV2_POS 4
+#define B1_HV2_MSK 0x10
+#define B1_HV3_POS 5
+#define B1_HV3_MSK 0x20
+#define B1_MULAW_POS 6
+#define B1_MULAW_MSK 0x40
+#define B1_ALAW_POS 7
+#define B1_ALAW_MSK 0x80
+
+#define B2_CVSD_POS 0
+#define B2_CVSD_MSK 0x01
+#define B2_PAGING_PAR_NEGO_POS 1
+#define B2_PAGING_PAR_NEGO_MSK 0x02
+#define B2_PWR_CTRL_POS 2
+#define B2_PWR_CTRL_MSK 0x04
+#define B2_TRANSPARENT_SCO_POS 3
+#define B2_TRANSPARENT_SCO_MSK 0x08
+#define B2_FLOW_CTRL_LAG_POS 4
+#define B2_FLOW_CTRL_LAG_MSK 0x70
+#define B2_BCAST_ENC_POS 7
+#define B2_BCAST_ENC_MSK 0x80
+
+#define B3_EDR_2MBPS_ACL_POS 1
+#define B3_EDR_2MBPS_ACL_MSK 0x02
+#define B3_EDR_3MBPS_ACL_POS 2
+#define B3_EDR_3MBPS_ACL_MSK 0x04
+#define B3_ENH_INQSCAN_POS 3
+#define B3_ENH_INQSCAN_MSK 0x08
+#define B3_INT_INQSCAN_POS 4
+#define B3_INT_INQSCAN_MSK 0x10
+#define B3_INT_PAGESCAN_POS 5
+#define B3_INT_PAGESCAN_MSK 0x20
+#define B3_RSSI_INQ_RES_POS 6
+#define B3_RSSI_INQ_RES_MSK 0x40
+#define B3_ESCO_EV3_POS 7
+#define B3_ESCO_EV3_MSK 0x80
+
+#define B4_EV4_PKT_POS 0
+#define B4_EV4_PKT_MSK 0x01
+#define B4_EV5_PKT_POS 1
+#define B4_EV5_PKT_MSK 0x02
+#define B4_AFH_CAP_SLV_POS 3
+#define B4_AFH_CAP_SLV_MSK 0x08
+#define B4_AFH_CLASS_SLV_POS 4
+#define B4_AFH_CLASS_SLV_MSK 0x10
+#define B4_BR_EDR_NOT_SUPP_POS 5
+#define B4_BR_EDR_NOT_SUPP_MSK 0x20
+#define B4_LE_SUPP_POS 6
+#define B4_LE_SUPP_MSK 0x40
+#define B4_3_SLOT_EDR_ACL_POS 7
+#define B4_3_SLOT_EDR_ACL_MSK 0x80
+
+#define B5_5_SLOT_EDR_ACL_POS 0
+#define B5_5_SLOT_EDR_ACL_MSK 0x01
+#define B5_SSR_POS 1
+#define B5_SSR_MSK 0x02
+#define B5_PAUSE_ENC_POS 2
+#define B5_PAUSE_ENC_MSK 0x04
+#define B5_AFH_CAP_MST_POS 3
+#define B5_AFH_CAP_MST_MSK 0x08
+#define B5_AFH_CLASS_MST_POS 4
+#define B5_AFH_CLASS_MST_MSK 0x10
+#define B5_EDR_ESCO_2MBPS_POS 5
+#define B5_EDR_ESCO_2MBPS_MSK 0x20
+#define B5_EDR_ESCO_3MBPS_POS 6
+#define B5_EDR_ESCO_3MBPS_MSK 0x40
+#define B5_3_SLOT_EDR_ESCO_POS 7
+#define B5_3_SLOT_EDR_ESCO_MSK 0x80
+
+#define B6_EIR_POS 0
+#define B6_EIR_MSK 0x01
+#define B6_SIM_LE_BREDR_DEV_CAP_POS 1
+#define B6_SIM_LE_BREDR_DEV_CAP_MSK 0x02
+#define B6_SSP_POS 3
+#define B6_SSP_MSK 0x08
+#define B6_ENCAPS_PDU_POS 4
+#define B6_ENCAPS_PDU_MSK 0x10
+#define B6_ERR_DATA_REP_POS 5
+#define B6_ERR_DATA_REP_MSK 0x20
+#define B6_NONFLUSH_PBF_POS 6
+#define B6_NONFLUSH_PBF_MSK 0x40
+
+#define B7_LST_CHANGE_EVT_POS 0
+#define B7_LST_CHANGE_EVT_MSK 0x01
+#define B7_INQRES_TXPOW_POS 1
+#define B7_INQRES_TXPOW_MSK 0x02
+#define B7_ENH_PWR_CTRL_POS 2
+#define B7_ENH_PWR_CTRL_MSK 0x04
+#define B7_EXT_FEATS_POS 7
+#define B7_EXT_FEATS_MSK 0x80
+
+/// Extended feature mask definition page 1 LMP:3.3
+#define B0_HOST_SSP_POS 0
+#define B0_HOST_SSP_MSK 0x01
+#define B0_HOST_LE_POS 1
+#define B0_HOST_LE_MSK 0x02
+#define B0_HOST_LE_BR_EDR_POS 2
+#define B0_HOST_LE_BR_EDR_MSK 0x04
+#define B0_HOST_SECURE_CON_POS 3
+#define B0_HOST_SECURE_CON_MSK 0x08
+
+/// Extended feature mask definition page 2 LMP:3.3
+#define B0_CSB_MASTER_POS 0
+#define B0_CSB_MASTER_MSK 0x01
+#define B0_CSB_SLAVE_POS 1
+#define B0_CSB_SLAVE_MSK 0x02
+#define B0_SYNC_TRAIN_POS 2
+#define B0_SYNC_TRAIN_MSK 0x04
+#define B0_SYNC_SCAN_POS 3
+#define B0_SYNC_SCAN_MSK 0x08
+#define B0_INQ_RES_NOTIF_EVT_POS 4
+#define B0_INQ_RES_NOTIF_EVT_MSK 0x10
+#define B0_GEN_INTERL_SCAN_POS 5
+#define B0_GEN_INTERL_SCAN_MSK 0x20
+#define B0_COARSE_CLK_ADJ_POS 6
+#define B0_COARSE_CLK_ADJ_MSK 0x40
+
+#define B1_SEC_CON_CTRL_POS 0
+#define B1_SEC_CON_CTRL_MSK 0x01
+#define B1_PING_POS 1
+#define B1_PING_MSK 0x02
+#define B1_TRAIN_NUDGING_POS 3
+#define B1_TRAIN_NUDGING_MSK 0x08
+
+/// Features definitions
+#define FEAT_3_SLOT_BIT_POS 0
+#define FEAT_5_SLOT_BIT_POS 1
+#define FEAT_ENC_BIT_POS 2
+#define FEAT_SLOT_OFFSET_BIT_POS 3
+#define FEAT_TIMING_ACC_BIT_POS 4
+#define FEAT_SWITCH_BIT_POS 5
+#define FEAT_HOLD_BIT_POS 6
+#define FEAT_SNIFF_BIT_POS 7
+
+#define FEAT_PARK_BIT_POS 8
+#define FEAT_RSSI_BIT_POS 9
+#define FEAT_QUALITY_BIT_POS 10
+#define FEAT_SCO_BIT_POS 11
+#define FEAT_HV2_BIT_POS 12
+#define FEAT_HV3_BIT_POS 13
+#define FEAT_ULAW_BIT_POS 14
+#define FEAT_ALAW_BIT_POS 15
+
+#define FEAT_CVSD_BIT_POS 16
+#define FEAT_PAGING_BIT_POS 17
+#define FEAT_POWER_BIT_POS 18
+#define FEAT_TRANSP_SCO_BIT_POS 19
+#define FEAT_BCAST_ENCRYPT_BIT_POS 23
+
+#define FEAT_EDR_2MB_BIT_POS 25
+#define FEAT_EDR_3MB_BIT_POS 26
+#define FEAT_ENH_INQSCAN_BIT_POS 27
+#define FEAT_INT_INQSCAN_BIT_POS 28
+#define FEAT_INT_PAGESCAN_BIT_POS 29
+#define FEAT_RSSI_INQRES_BIT_POS 30
+#define FEAT_EV3_BIT_POS 31
+
+#define FEAT_EV4_BIT_POS 32
+#define FEAT_EV5_BIT_POS 33
+#define FEAT_AFH_CAPABLE_S_BIT_POS 35
+#define FEAT_AFH_CLASS_S_BIT_POS 36
+#define FEAT_BR_EDR_NO_SUPP_BIT_POS 37
+#define FEAT_LE_BIT_POS 38
+#define FEAT_3_SLOT_EDR_BIT_POS 39
+#define FEAT_5_SLOT_EDR_BIT_POS 40
+#define FEAT_SNIFF_SUBRAT_BIT_POS 41
+#define FEAT_PAUSE_ENCRYPT_BIT_POS 42
+#define FEAT_AFH_CAPABLE_M_BIT_POS 43
+#define FEAT_AFH_CLASS_M_BIT_POS 44
+#define FEAT_EDR_ESCO_2MB_BIT_POS 45
+#define FEAT_EDR_ESCO_3MB_BIT_POS 46
+#define FEAT_3_SLOT_EDR_ESCO_BIT_POS 47
+#define FEAT_EIR_BIT_POS 48
+#define FEAT_LE_BR_EDR_BIT_POS 49
+#define FEAT_SSP_BIT_POS 51
+#define FEAT_ENCAP_PDU_BIT_POS 52
+#define FEAT_ERRO_DATA_REP_BIT_POS 53
+#define FEAT_NFLUSH_PBF_BIT_POS 54
+#define FEAT_LSTO_CHG_EVT_BIT_POS 56
+#define FEAT_INQ_TXPWR_BIT_POS 57
+#define FEAT_EPC_BIT_POS 58
+#define FEAT_EXT_FEATS_BIT_POS 63
+#define FEAT_SSP_HOST_BIT_POS 64
+#define FEAT_LE_HOST_BIT_POS 65
+#define FEAT_LE_BR_EDR_HOST_BIT_POS 66
+#define FEAT_SEC_CON_HOST_BIT_POS 67
+
+#define FEAT_CSB_MASTER_BIT_POS 128
+#define FEAT_CSB_SLAVE_BIT_POS 129
+#define FEAT_SYNC_TRAIN_BIT_POS 130
+#define FEAT_SYNC_SCAN_BIT_POS 131
+#define FEAT_INQ_RES_NOTIF_EVT_BIT_POS 132
+#define FEAT_GEN_INTERL_SCAN_BIT_POS 133
+#define FEAT_COARSE_CLK_ADJ_BIT_POS 134
+#define FEAT_SEC_CON_CTRL_BIT_POS 136
+#define FEAT_PING_BIT_POS 137
+#define FEAT_TRAIN_NUDGING_BIT_POS 139
+
+/// Maximum number of feature bits per page (8 bytes x 8 bits)
+#define MAX_FEAT_BITS_PER_PAGE 64
+
+/// Poll interval defines LMP:5.2
+#define POLL_INTERVAL_MIN 0x0006
+#define POLL_INTERVAL_DFT 0x0028
+#define POLL_INTERVAL_MAX 0x1000
+
+/// Power Adjustment Request LMP:5.2
+#define PWR_ADJ_REQ_DEC_1_STEP 0x00
+#define PWR_ADJ_REQ_INC_1_STEP 0x01
+#define PWR_ADJ_REQ_INC_MAX 0x02
+
+/// Power Adjustment Response LMP:5.2
+#define PWR_ADJ_RES_GFSK_POS 0
+#define PWR_ADJ_RES_GFSK_MASK 0x03
+#define PWR_ADJ_RES_DQPSK_POS 2
+#define PWR_ADJ_RES_DQPSK_MASK 0x0C
+#define PWR_ADJ_RES_8DPSK_POS 4
+#define PWR_ADJ_RES_8DPSK_MASK 0x30
+
+#define PWR_ADJ_RES_NOT_SUPP 0x00
+#define PWR_ADJ_RES_CHG_1_STEP 0x01
+#define PWR_ADJ_RES_MAX 0x02
+#define PWR_ADJ_RES_MIN 0x03
+
+/// Nb of Broadcast retransmissions defines
+#define NB_BROADCAST_DFT 0x01
+
+/// Nb of Broadcast CLK_ADJ PDU Baseband:4.1.14.1
+#define NB_BROADCAST_CLK_ADJ 0x06
+
+/// Min PCA clk_adj_instant (in slots) LMP:4.1.14.1
+#define PCA_INSTANT_MIN 12
+
+/// Piconet Clock Adjustment clk_adj_mode LMP:4.1.14.1
+#define CLK_ADJ_BEFORE_INSTANT 0
+#define CLK_ADJ_AFTER_INSTANT 1
+
+
+/// Different packet types BaseBand:6.7
+/* Packet and buffer sizes. These sizes do not include payload header (except for FHS
+ * packet where there is no payload header) since payload header is written or read by
+ * the RWBT in a different control structure part (TX/RXPHDR) */
+#define FHS_PACKET_SIZE 18
+#define DM1_PACKET_SIZE 17
+#define DH1_PACKET_SIZE 27
+#define DH1_2_PACKET_SIZE 54
+#define DH1_3_PACKET_SIZE 83
+#define DV_ACL_PACKET_SIZE 9
+#define DM3_PACKET_SIZE 121
+#define DH3_PACKET_SIZE 183
+#define DH3_2_PACKET_SIZE 367
+#define DH3_3_PACKET_SIZE 552
+#define DM5_PACKET_SIZE 224
+#define DH5_PACKET_SIZE 339
+#define DH5_2_PACKET_SIZE 679
+#define DH5_3_PACKET_SIZE 1021
+#define AUX1_PACKET_SIZE 29
+
+#define HV1_PACKET_SIZE 10
+#define HV2_PACKET_SIZE 20
+#define HV3_PACKET_SIZE 30
+#define EV3_PACKET_SIZE 30
+#define EV3_2_PACKET_SIZE 60
+#define EV3_3_PACKET_SIZE 90
+#define EV4_PACKET_SIZE 120
+#define EV5_PACKET_SIZE 180
+#define EV5_2_PACKET_SIZE 360
+#define EV5_3_PACKET_SIZE 540
+
+/// SCO Packet coding LMP:5.2
+#define SCO_PACKET_HV1 0x00
+#define SCO_PACKET_HV2 0x01
+#define SCO_PACKET_HV3 0x02
+
+/// eSCO Packet coding LMP:5.2
+#define ESCO_PACKET_NULL 0x00
+#define ESCO_PACKET_EV3 0x07
+#define ESCO_PACKET_EV4 0x0C
+#define ESCO_PACKET_EV5 0x0D
+#define ESCO_PACKET_EV3_2 0x26
+#define ESCO_PACKET_EV3_3 0x37
+#define ESCO_PACKET_EV5_2 0x2C
+#define ESCO_PACKET_EV5_3 0x3D
+
+/// Max number of HV packet BaseBand:4.4.2.1
+#define MAX_NB_HV1 1
+#define MAX_NB_HV2 2
+#define MAX_NB_HV3 3
+
+/// Tsco (ScoInterval) BaseBand:4.4.2.1
+#define TSCO_HV1 2
+#define TSCO_HV2 4
+#define TSCO_HV3 6
+
+/* Inquiry train repetition length , Baseband :Table 10.4
+ * - 256 repetitions if no SCO
+ * - 512 repetitions if 1 SCO
+ * - 768 repetitions if 2 SCO */
+#define INQ_TRAIN_LENGTH_NO_SCO 256
+#define INQ_TRAIN_LENGTH_1_SCO 512
+#define INQ_TRAIN_LENGTH_2_SCO 768
+
+/* Counter for train length, Npage (N*16 slots) depends on the slave page scan mode and
+ * the number of active SCO:
+ * | SR mode | no SCO | one SCO | two SCO |
+ * | R0 | >=1 | >=2 | >=3 |
+ * | R1 | >=128 | >=256 | >=384 |
+ * | R2 | >=256 | >=512 | >=768 | */
+#define PAGE_TRAIN_LENGTH_R0 1
+#define PAGE_TRAIN_LENGTH_R1 128
+#define PAGE_TRAIN_LENGTH_R2 256
+
+/// Synchronisation defines
+#define NORMAL_SYNC_POS (64 + 4) // End of Synchro word at bit 68 (64 + 4)
+#define SLOT_SIZE 625 // A slot is 625 us
+
+/// Baseband timeout default value, Baseband timers: 1.1
+#define PAGE_RESP_TO_DEF 8
+#define INQ_RESP_TO_DEF 128
+#define NEW_CONNECTION_TO 32
+
+/// LMP Response Timeout (in sec)
+#define LMP_RSP_TO 30
+
+/// Athenticated Payload Timeout (in units of 10 ms)
+#define AUTH_PAYL_TO_DFT 0x0BB8 // 30 secs
+#define AUTH_PAYL_TO_MIN 0x0001
+
+/// Voice mute pattern defines
+#define MU_LAW_MUTE 0xFF
+#define ALAW_CVSD_MUTE 0x55
+#define TRANSP_MUTE 0x00
+
+/// Air Mode LMP:5.2
+#define MU_LAW_MODE 0
+#define A_LAW_MODE 1
+#define CVSD_MODE 2
+#define TRANS_MODE 3
+
+/// eSCO negotiation State LMP:5.2
+#define ESCO_NEGO_INIT 0
+#define ESCO_NEGO_LATEST_POSSIBLE 1
+#define ESCO_NEGO_SLOT_VIOLATION 2
+#define ESCO_NEGO_LAT_VIOLATION 3
+#define ESCO_NEGO_UNSUPPORTED 4
+
+#define SCO_BANDWIDTH 8000
+#define SYNC_BANDWIDTH_DONT_CARE 0xFFFFFFFF
+
+#define SYNC_MIN_LATENCY 0x0004
+#define SYNC_MAX_LATENCY_ESCO_S1 0x0007
+#define SYNC_MAX_LATENCY_ESCO_S2 0x0007
+#define SYNC_MAX_LATENCY_ESCO_S3 0x000A
+#define SYNC_DONT_CARE_LATENCY 0xFFFF
+
+#define SYNC_NO_RE_TX 0x00
+#define SYNC_RE_TX_POWER 0x01
+#define SYNC_RE_TX_QUALITY 0x02
+#define SYNC_RE_TX_DONT_CARE 0xFF
+
+/// Timing Control Flags LMP:5.2
+#define TIM_CHANGE_FLAG 0x01
+#define INIT2_FLAG 0x02
+#define ACCESS_WIN_FLAG 0x04
+
+/// Packet Type Table defines LMP:4.1.11
+#define PACKET_TABLE_1MBPS 0x00
+#define PACKET_TABLE_2_3MBPS 0x01
+
+/// Data Rate defines LMP:5.2
+#define FEC_RATE_MSK 0x01
+#define USE_FEC_RATE 0x00
+#define NO_FEC_RATE 0x01
+#define PREF_PACK_MSK 0x06
+#define NO_PREF_PACK_SIZE 0x00
+#define USE_1_SLOT_PACKET 0x02
+#define USE_3_SLOT_PACKET 0x04
+#define USE_5_SLOT_PACKET 0x06
+#define PREF_EDR_MSK 0x18
+#define USE_DM1_ONLY 0x00
+#define USE_2_MBPS_RATE 0x08
+#define USE_3_MBPS_RATE 0x10
+#define PREF_PACK_EDR_MSK 0x60
+#define USE_1_SLOT_EDR_PKT 0x20
+#define USE_3_SLOT_EDR_PKT 0x40
+#define USE_5_SLOT_EDR_PKT 0x60
+
+/// EIR Data Size HCI:6.24
+#define EIR_DATA_SIZE 240
+
+/// Voice setting HCI:4.7.29 & 4.7.30
+#define INPUT_COD_LIN 0x0000
+#define INPUT_COD_MULAW 0x0100
+#define INPUT_COD_ALAW 0x0200
+#define INPUT_COD_MSK 0x0300
+#define INPUT_COD_OFF 8
+#define INPUT_DATA_1COMP 0x0000
+#define INPUT_DATA_2COMP 0x0040
+#define INPUT_DATA_SMAG 0x0080
+#define INPUT_DATA_UNSIGNED 0x00C0
+#define INPUT_DATAFORM_MSK 0x00C0
+#define INPUT_DATAFORM_OFF 6
+#define INPUT_SAMP_8BIT 0x0000
+#define INPUT_SAMP_16BIT 0x0020
+#define INPUT_SAMPSIZE_MSK 0x0020
+#define INPUT_SAMPSIZE_OFF 5
+#define LIN_PCM_BIT_POS_MSK 0x001C
+#define LIN_PCM_BIT_POS_OFF 2
+#define AIR_COD_CVSD 0x0000
+#define AIR_COD_MULAW 0x0001
+#define AIR_COD_ALAW 0x0002
+#define AIR_COD_TRANS 0x0003
+#define AIR_COD_MSK 0x0003
+#define AIR_COD_OFF 0
+
+/// ScanEnable HCI:6.1
+#define BOTH_SCAN_DISABLE 0
+#define INQUIRY_SCAN_ENABLE 1
+#define PAGE_SCAN_ENABLE 2
+#define BOTH_SCAN_ENABLE 3
+
+/// PageScanInterval HCI:6.8
+#define PAGE_SCAN_INTV_MIN 0x0012
+#define PAGE_SCAN_INTV_MAX 0x1000
+#define PAGE_SCAN_INTV_DFT 0x0800
+
+/// PageScanWindow HCI:6.9
+#define PAGE_SCAN_WIN_MIN 0x0011
+#define PAGE_SCAN_WIN_MAX 0x1000
+#define PAGE_SCAN_WIN_DFT 0x0012
+
+/// InquiryScanInterval HCI:6.2
+#define INQ_SCAN_INTV_MIN 0x0012
+#define INQ_SCAN_INTV_MAX 0x1000
+#define INQ_SCAN_INTV_DFT 0x1000
+
+/// InquiryScanWindow HCI:6.3
+#define INQ_SCAN_WIN_MIN 0x0011
+#define INQ_SCAN_WIN_MAX 0x1000
+#define INQ_SCAN_WIN_DFT 0x0012
+
+/// General/Unlimited Inquiry Access Code (GIAC)
+#define GIAC_LAP_0 0x33
+#define GIAC_LAP_1 0x8B
+#define GIAC_LAP_2 0x9E
+
+/// Limited Dedicated Inquiry Access Code (LIAC)
+#define LIAC_LAP_0 0x00
+#define LIAC_LAP_1 0x8B
+#define LIAC_LAP_2 0x9E
+
+/// Maximum Dedicated Inquiry Access Code (DIAC MAX)
+#define DIAC_MAX_LAP_0 0x3F
+#define DIAC_MAX_LAP_1 0x8B
+#define DIAC_MAX_LAP_2 0x9E
+
+/// PIN Type HCI:6.13
+#define VARIABLE_PIN 0
+#define FIXED_PIN 1
+
+/// ConnectionAcceptTimeout HCI:6.7
+#define CON_ACCEPT_TO_MIN 0x00A0
+#define CON_ACCEPT_TO_MAX 0xB540
+#define CON_ACCEPT_TO_DFT 0x1FA0
+
+/// PageTimeout HCI:6.6
+#define PAGE_TO_MIN 0x0016
+#define PAGE_TO_MAX 0xFFFF
+#define PAGE_TO_DFT 0x2000
+
+/// Clock offset valid flag in clock offset field HCI:7.1.5/7.1.19
+#define CLK_OFFSET_VALID_FLAG_POS 15
+#define CLK_OFFSET_VALID_FLAG_MSK 0x8000
+
+/// AuthenticationEnable HCI:4.7.24
+#define AUTH_DISABLED 0x00 // Default
+#define AUTH_ENABLED 0x01
+
+/// EncryptionMode HCI:4.7.26
+#define ENC_DISABLED 0x00 // Default
+#define ENC_PP_ENABLED 0x01
+#define ENC_PP_BC_ENABLED 0x02
+
+/// AutomaticFlushTimeout HCI:4.7.32
+#define AUTO_FLUSH_TIMEOUT_MAX 0x07FF
+#define AUTO_FLUSH_TIMEOUT_OFF 0x0000
+#define AUTO_FLUSH_TIMEOUT_DFT AUTO_FLUSH_TIMEOUT_OFF // Default (no automatic flush timeout)
+
+/// Link Supervision Time Out (in slots) HCI:6.21
+#define LSTO_OFF 0x0000
+#define LSTO_MIN 0x0001
+#define LSTO_DFT 0x7D00 // Default is 20 s
+#define LSTO_MAX 0xFFFF
+
+/// PageScanRepetitionMode HCI:4.5.5
+#define R0 0x00
+#define R1 0x01
+#define R2 0x02
+#define PAGESCAN_REP_DEF R1 // Default
+
+/// PageScanPeriodMode HCI:4.7.49
+#define P0 0x00 // Default
+#define P1 0x01
+#define P2 0x02
+
+/// PageScanMode HCI:4.7.51
+#define MANDATORY_PAGE_SCAN_MODE 0x00 // Default
+
+#define OPT_PAGE_SCAN_MODE_1 0x01
+#define OPT_PAGE_SCAN_MODE_2 0x02
+#define OPT_PAGE_SCAN_MODE_3 0x03
+
+/// Encryption Enable HCI:4.5.17
+#define ENCRYPTION_OFF 0x00
+#define ENCRYPTION_ON 0x01
+
+/// Country Code HCI:4.8.4
+#define NORTH_AMERICA_EUROPE 0x00
+#define FRANCE 0x01
+#define SPAIN 0x02
+#define JAPAN 0x03
+
+/// Loopback mode HCI:7.6.2
+#define NO_LOOPBACK 0x00 // Default
+#define LOCAL_LOOPBACK 0x01
+#define REMOTE_LOOPBACK 0x02
+
+/// Erroneous Data Reporting HCI:7.3.65
+#define ERR_DATA_REP_DIS 0x00 // Default
+#define ERR_DATA_REP_EN 0x01
+
+/// LM modes HCI:5.2.20
+#define LM_ACTIVE_MODE 0x00
+#define LM_HOLD_MODE 0x01
+#define LM_SNIFF_MODE 0x02
+#define LM_PARK_MODE 0x03
+
+/// Key Type HCI:5.2.24
+#define COMB_KEY 0
+#define LOCAL_UNIT_KEY 1
+#define REMOTE_UNIT_KEY 2
+#define DEBUG_COMB_KEY 3
+#define UNAUTH_COMB_KEY_192 4
+#define AUTH_COMB_KEY_192 5
+#define CHANGED_COMB_KEY 6
+#define UNAUTH_COMB_KEY_256 7
+#define AUTH_COMB_KEY_256 8
+
+/// Key Flag HCI:5.4.18
+#define SEMI_PERMANENT_KEY 0x00
+#define TEMPORARY_KEY 0x01
+
+/// QOS Service Type HCI:4.6.6
+#define QOS_NO_TRAFFIC 0x00
+#define QOS_BEST_EFFORT 0x01
+#define QOS_GUARANTEED 0x02
+#define QOS_NOTSPECIFIED 0xFF
+
+#define QOS_WILD_CARD 0xFFFFFFFF
+
+/// RSSI golden range
+#define RSSI_GOLDEN_RG 0x00
+
+/// Inquiry TX power level (in dBm) HCI:7.3.62
+#define INQ_TX_PWR_DBM_MIN -70
+#define INQ_TX_PWR_DBM_DFT 0
+#define INQ_TX_PWR_DBM_MAX +20
+
+/// Bluetooth Test Mode defines Bluetooth Test Mode: Table 3.2
+
+#define PAUSE_MODE 0x00
+#define TXTEST0_MODE 0x01
+#define TXTEST1_MODE 0x02
+#define TXTEST10_MODE 0x03
+#define PRAND_MODE 0x04
+#define ACLLOOP_MODE 0x05
+#define SCOLOOP_MODE 0x06
+#define ACLNOWHIT_MODE 0x07
+#define SCONOWHIT_MODE 0x08
+#define TXTEST1100_MODE 0x09
+#define EXITTEST_MODE 0xFF
+
+#define HOPSINGLE 0x00
+#define HOPUSA 0x01
+
+#define FIXTXPOW 0x00
+#define ADAPTTXPOW 0x01
+
+/// Packet type parameter bit field of LMP_test_control
+#define LMP_TEST_CTRL_PKT_TYPE_CODE_POS 0
+#define LMP_TEST_CTRL_PKT_TYPE_CODE_MSK 0x0F
+#define LMP_TEST_CTRL_PKT_TYPE_LINK_POS 4
+#define LMP_TEST_CTRL_PKT_TYPE_LINK_MSK 0xF0
+#define TEST_ACLSCO 0
+#define TEST_ESCO 1
+#define TEST_EDRACL 2
+#define TEST_EDRESCO 3
+
+/// LMP_encapsulated_header parameters LMP:5.3
+#define LMP_ENCAPS_P192_MAJ_TYPE 1
+#define LMP_ENCAPS_P192_MIN_TYPE 1
+#define LMP_ENCAPS_P192_PAYL_LEN 48
+#define LMP_ENCAPS_P192_PAYL_NB 3
+#define LMP_ENCAPS_P256_MAJ_TYPE 1
+#define LMP_ENCAPS_P256_MIN_TYPE 2
+#define LMP_ENCAPS_P256_PAYL_LEN 64
+#define LMP_ENCAPS_P256_PAYL_NB 4
+
+/// Number of bits in the passkey code used during Secure Simple Pairing
+#define SSP_PASSKEY_NB_BITS 20
+
+// Event Filter HCI 4.7.3
+
+/// Filter type
+#define CLEAR_ALL_FILTER_TYPE 0x00
+#define INQUIRY_FILTER_TYPE 0x01
+#define CONNECTION_FILTER_TYPE 0x02
+
+/// Filter size
+#define CLEAR_ALL_FILTER_SIZE 0
+
+/// Inquiry & Connection Setup Filter Condition Type
+#define ALL_FILTER_CONDITION_TYPE 0x00
+#define CLASS_FILTER_CONDITION_TYPE 0x01
+#define BD_ADDR_FILTER_CONDITION_TYPE 0x02
+
+/// Auto Accept Flag
+#define DO_NOT_AUTO_ACCEPT_CONNECTION 0x01
+#define ACCEPT_CONNECTION_SLAVE 0x02
+#define ACCEPT_CONNECTION_MASTER 0x03
+
+/// Event Mask HCI 4.7.1
+#define NO_EVENTS_SPECIFIED_FILTER 0x00000000
+#define INQUIRY_COMPLETE_EVENT_FILTER 0x00000001
+#define INQUIRY_RESULT_EVENT_FILTER 0x00000002
+#define CONNECTION_COMPLETE_EVENT_FILTER 0x00000004
+#define CONNECTION_REQUEST_EVENT_FILTER 0x00000008
+#define DISCONNECTION_COMPLETE_EVENT_FILTER 0x00000010
+#define AUTHENTICATION_COMPLETE_EVENT_FILTER 0x00000020
+#define REMOTE_NAME_REQUEST_COMPLETE_EVENT_FILTER 0x00000040
+#define ENCRYPTION_CHANGE_EVENT_FILTER 0x00000080
+#define CHANGE_CONNECTION_LINK_KEY_COMPLETE_EVENT_FILTER 0x00000100
+#define MASTER_LINK_KEY_COMPLETE_EVENT_FILTER 0x00000200
+#define READ_REMOTE_SUPPORTED_FEATURES_COMPLETE_EVENT_FILTER 0x00000400
+#define READ_REMOTE_VERSION_INFORMATION_COMPLETE_EVENT_FILTER 0x00000800
+#define QOS_SETUP_COMPLETE_EVENT_FILTER 0x00001000
+#define COMMAND_COMPLETE_EVENT_FILTER 0x00002000 // Unchecked */
+#define COMMAND_STATUS_EVENT_FILTER 0x00004000 // Unchecked */
+#define HARDWARE_ERROR_EVENT_FILTER 0x00008000
+#define FLUSH_OCCURRED_EVENT_FILTER 0x00010000
+#define ROLE_CHANGE_EVENT_FILTER 0x00020000
+#define NUMBER_OF_COMPLETED_PACKETS_EVENT_FILTER 0x00040000 // Unchecked */
+#define MODE_CHANGE_EVENT_FILTER 0x00080000
+#define RETURN_LINK_KEYS_EVENT_FILTER 0x00100000
+#define PIN_CODE_REQUEST_EVENT_FILTER 0x00200000
+#define LINK_KEY_REQUEST_EVENT_FILTER 0x00400000
+#define LINK_KEY_NOTIFICATION_EVENT_FILTER 0x00800000
+#define LOOPBACK_COMMAND_EVENT_FILTER 0x01000000 // Not implemented */
+#define DATA_BUFFER_OVERFLOW_EVENT_FILTER 0x02000000
+#define MAX_SLOTS_CHANGE_EVENT_FILTER 0x04000000
+#define READ_CLOCK_OFFSET_COMPLETE_EVENT_FILTER 0x08000000
+#define CONNECTION_PACKET_TYPE_CHANGED_EVENT_FILTER 0x10000000
+#define QOS_VIOLATION_EVENT_FILTER 0x20000000
+#define PAGE_SCAN_MODE_CHANGE_EVENT_FILTER 0x40000000 // Deprecated */
+#define PAGE_SCAN_REPETITION_MODE_CHANGE_EVENT_FILTER 0x80000000
+
+#define FLOW_SPECIFICATION_COMPLETE_EVENT_FILTER 0x00000001
+#define INQUIRY_RESULT_WITH_RSSI_EVENT_FILTER 0x00000002
+#define READ_REMOTE_EXTENDED_FEATURES_COMPLETE_EVENT_FILTER 0x00000004
+#define SYNCHRONOUS_CONNECTION_COMPLETE_EVENT_FILTER 0x00000800
+#define SYNCHRONOUS_CONNECTION_CHANGE_EVENT_FILTER 0x00001000
+#define SNIFF_SUBRATING_EVENT_FILTER 0x00002000
+#define EXTENDED_INQUIRY_RESULT_EVENT_FILTER 0x00004000
+#define ENCRYPTION_KEY_REFRESH_COMPLETE_EVENT_FILTER 0x00008000
+#define IO_CAPABILITY_REQUEST_EVENT_FILTER 0x00010000
+#define IO_CAPABILITY_REQUEST_REPLY_EVENT_FILTER 0x00020000
+#define USER_CONFIRMATION_REQUEST_EVENT_FILTER 0x00040000
+#define USER_PASSKEY_REQUEST_EVENT_FILTER 0x00080000
+#define REMOTE_OOB_DATA_REQUEST_EVENT_FILTER 0x00100000
+#define SIMPLE_PAIRING_COMPLETE_EVENT_FILTER 0x00200000
+#define LINK_SUPERVISION_TIMEOUT_CHANGE_EVENT_FILTER 0x00800000
+#define ENHANCED_FLUSH_COMPLETE_EVENT_FILTER 0x01000000
+#define USER_PASSKEY_NOTIFICATION_EVENT_FILTER 0x04000000
+#define KEYPRESS_NOTIFICATION_EVENT_FILTER 0x08000000
+#define REM_HOST_SUPPORTED_FEATURES_NOTIFICATION_EVENT_FILTER 0x10000000
+
+/// HostControllerToHostFlowControl (ACL) HCI 7.3.40
+#define FLOW_CONTROL_OFF 0x00
+#define FLOW_CONTROL_ACL 0x01
+#define FLOW_CONTROL_SCO 0x02
+#define FLOW_CONTROL_ACL_SCO 0x03
+
+/// SynchroinousFlowControlEnable (SCO) HCI 7.3.39
+#define SYNC_FLOW_CONTROL_OFF 0x00
+#define SYNC_FLOW_CONTROL_ON 0x01
+
+/// Tx Power HCI:4.7.37
+#define CURRENT_TX_POWER 0x00
+#define MAX_TX_POWER 0x01
+
+/// Flow_direction HCI:7.2.13
+#define FLOW_DIR_OUT 0x00
+#define FLOW_DIR_IN 0x01
+
+/// Drift and Jitter default value LMP 5.2
+#define DRIFT_BLE_DFT 500
+#define DRIFT_BT_DFT 250
+#define JITTER_DFT 10
+#define DRIFT_BT_ACTIVE_MAX 20 // BB:2.2.5
+
+/// Read Stored Link Key HCI:4.7.8
+#define LINK_KEY_BD_ADDR 0x00
+#define LINK_KEY_ALL 0x01
+
+/// Read/Write Hold Mode Activity HCI:4.7.35 and 4.7.36
+#define HOLD_MODE_ACTIV_DEFAULT 0x00
+#define HOLD_MODE_ACTIV_SUSP_PAGE_SCAN 0x01
+#define HOLD_MODE_ACTIV_SUSP_INQUIRY_SCAN 0x02
+#define HOLD_MODE_ACTIV_SUSP_PERIODIC_INQ 0x04
+#define HOLD_MODE_ACTIV_NOT_MASK 0xF8
+
+/// AFH Mode
+#define AFH_DISABLED 0x00
+#define AFH_ENABLED 0x01
+
+/// AFH Reporting Mode
+#define AFH_REPORTING_DISABLED 0x00
+#define AFH_REPORTING_ENABLED 0x01
+
+/// AFH channel assessment Mode
+#define AFH_CH_ASS_DISABLED 0x00
+#define AFH_CH_ASS_ENABLED 0x01
+
+/// AFH MIn/Max interval, in BT slots (1s - 30s)
+#define AFH_REPORT_INTERVAL_MIN 0x0640
+#define AFH_REPORT_INTERVAL_MAX 0xBB80
+
+/// Channel classification values for frequency pairs
+#define AFH_CH_CLASS_UNKNOWN 0x0
+#define AFH_CH_CLASS_GOOD 0x1
+#define AFH_CH_CLASS_RESERVED 0x2
+#define AFH_CH_CLASS_BAD 0x3
+
+/// Maximum number of frequencies used in adapted channel hopping sequence
+#define AFH_NB_CHANNEL_MIN 20
+#define AFH_NB_CHANNEL_MAX 79
+
+/// Number of frequencies available in standard hopping sequence
+#define HOP_NB_CHANNEL 79
+
+/// Base frequency in MHz of first BT hop channel [f=2402+k MHz, k=0,...,78]
+#define HOP_CHANNEL_BASE_MHZ 2402
+
+/// Maximum number of frequencies used in synchronization train BB:2.6.4.8
+#define SYNC_TRAIN_CHANNEL_NB 3
+/// Indices of frequencies used in synchronization train
+#define SYNC_TRAIN_CHANNEL_0 0
+#define SYNC_TRAIN_CHANNEL_1 24
+#define SYNC_TRAIN_CHANNEL_2 78
+
+/// Maximum delay in synchronization train (in slots) BB:2.7.2
+#define SYNC_TRAIN_DELAY_MAX_DFT 16
+/// Maximum delay in synchronization train for Coarse clock adjustment (in slots) BB:2.7.2
+#define SYNC_TRAIN_DELAY_MAX_CLK_ADJ 4
+/// Synchronization train interval for Coarse clock adjustment (in slots) BB:2.7.2
+#define SYNC_TRAIN_INTV_CLK_ADJ 32
+
+/// Future CSB instant value offset for Coarse clock adjustment (in slots) BB: 8.11.2
+#define SYNC_TRAIN_CSB_INSTANT_OFFSET_CLK_ADJ 1600
+
+/// Minimum value for synchronization train interval (in slots) HCI:7.3.90
+#define SYNC_TRAIN_INTV_MIN 0x20
+/// Minimum value for synchronization train timeout (in slots) HCI:7.3.90
+#define SYNC_TRAIN_TO_MIN 0x00000002
+/// Maximum value for synchronization train timeout (in slots) HCI:7.3.90
+#define SYNC_TRAIN_TO_MAX 0x07FFFFFE
+
+/// Default value for synchronization train interval (in slots) HCI:6.36
+#define SYNC_TRAIN_INTV_DEFAULT 0x80
+/// Default value for synchronization train timeout (in slots) HCI:6.37
+#define SYNC_TRAIN_TO_DEFAULT 0x0002EE00
+/// Default value for synchronization train service data HCI:6.39
+#define SYNC_TRAIN_SVC_DATA_DEFAULT 0x00
+
+/// Minimum value for synchronization scan timeout (in slots) HCI:7.1.52
+#define SYNC_SCAN_TO_MIN 0x22
+/// Minimum value for synchronization scan window (in slots) HCI:7.1.52
+#define SYNC_SCAN_WIN_MIN 0x22
+/// Minimum value for synchronization scan interval (in slots) HCI:7.1.52
+#define SYNC_SCAN_INTV_MIN 0x02
+
+/// Default value for synchronization scan timeout (in slots) BB: Apppendix B
+#define SYNC_SCAN_TO_DEFAULT 0x2000
+/// Recommended value for synchronization scan window (91.25ms) GAP: Appendix A
+#define SYNC_SCAN_WIN_DEFAULT 0x0092
+/// Recommended value for synchronization scan interval (320 ms) GAP: Appendix A
+#define SYNC_SCAN_INTV_DEFAULT 0x0200
+
+/// CSB receive enable HCI:7.1.50
+#define CSB_RX_MODE_DIS 0x00
+#define CSB_RX_MODE_EN 0x01
+
+/// CSB fragment HCI:7.2.88
+#define CSB_CONTINUATION_FRAGMENT 0
+#define CSB_STARTING_FRAGMENT 1
+#define CSB_ENDING_FRAGMENT 2
+#define CSB_NO_FRAGMENTATION 3
+
+/// CSB max fragment size HCI:7.2.88
+#define CSB_FRAGMENT_SIZE_MAX 0xFF
+
+/// MWS Channel_Enable
+#define MWS_CHANNEL_DISABLED 0x00
+#define MWS_CHANNEL_ENABLED 0x01
+
+/// MWS Channel_Type
+#define MWS_TDD_CHANNEL_TYPE 0x00
+#define MWS_FDD_CHANNEL_TYPE 0x01
+
+/// MWS Transport_Layer
+#define MWS_SIGNALING_ONLY 0x00
+#define MWS_WCI_1 0x01
+#define MWS_WCI_2 0x02
+#define MWS_TRANSPORT_TYPE_MAX 0x02
+
+/// MWS PATTERN Index
+#define MWS_PATTERN_INDEX_MAX 2
+
+/// MWS PATTERN IntervalType
+#define MWS_PATTERN_NO_TXRX 0
+#define MWS_PATTERN_TX_ALLOWED 1
+#define MWS_PATTERN_RX_ALLOWED 2
+#define MWS_PATTERN_TXRX_ALLOWED 3
+#define MWS_PATTERN_EXT_FRAME 4
+#define MWS_PATTERN_TYPE_MAX 4
+
+
+/// MWS Ext_Num_Periods
+#define MWS_EXT_NUM_PERIODS_MIN 0x01
+#define MWS_EXT_NUM_PERIODS_MAX 0x32
+
+/// MWS Period_Type
+#define MWS_PERIOD_TYPE_DOWNLINK 0x00
+#define MWS_PERIOD_TYPE_UPLINK 0x01
+#define MWS_PERIOD_TYPE_BIDIRECTIONAL 0x02
+#define MWS_PERIOD_TYPE_GUARD_PERIOD 0x03
+#define MWS_PERIOD_TYPE_RESERVED 0x04
+
+/// Simple pairing mode HCI:7.3.58/HCI:7.3.59
+#define SP_MODE_DIS 0x00
+#define SP_MODE_EN 0x01
+
+/// Inquiry Scan Type and Page Scan Type HCI:6.4/HCI:6.11
+#define STANDARD_SCAN 0x00
+#define INTERLACED_SCAN 0x01
+
+/// Default interlace offset used for frequency selection during interlaced inquiry/page scan BB:8.3.1/8.4.1
+#define INTERLACE_OFFSET_DFT 16
+
+/// Inquiry Mode
+#define STANDARD_INQUIRY 0x00
+#define RSSI_INQUIRY 0x01
+#define EXTENDED_INQUIRY 0x02
+
+/// Maximum number of link keys Host can write via HCI Write Stored Link Key Command
+#define NB_LINK_KEY 0x0B
+
+/// LMP Version
+#define BT_LMP_V1_0 0
+#define BT_LMP_V1_1 1
+#define BT_LMP_V1_2 2
+#define BT_LMP_V2_0 3
+#define BT_LMP_V2_1 4
+#define BT_LMP_V3_0 5
+#define BT_LMP_V4_0 6
+#define BT_LMP_V4_1 7
+
+/// WhichClock parameter
+#define LOCAL_CLOCK 0
+#define PICONET_CLOCK 1
+
+/// Clock Accuracy parameter
+#define CLOCK_ACCURACY_UNKNOWN 0xFFFF
+
+#define SP_PASSKEY_STARTED 0x00
+#define SP_PASSKEY_DIGIT_ENTERED 0x01
+#define SP_PASSKEY_DIGIT_ERASED 0x02
+#define SP_PASSKEY_CLEARED 0x03
+#define SP_PASSKEY_COMPLETED 0x04
+
+/// Low Power Mode
+#define PARK_BEACON_MIN 0x000E
+
+/// RWBT Device can be slave of 2 master at max
+#define MAX_SLAVES_FOR_DIFFERENT_MASTERS 2
+// Flags for ld_util_get_nb_acl function
+/// Flag for master link
+#define MASTER_FLAG 0x01
+/// Flag for slave link
+#define SLAVE_FLAG 0x02
+
+/// BLE event mask
+enum le_evt_mask
+{
+ LE_CON_CMP_EVT_BIT = 0,
+ LE_CON_CMP_EVT_MSK = 0x0001,
+ LE_ADV_REP_EVT_BIT = 1,
+ LE_ADV_REP_EVT_MSK = 0x0002,
+ LE_CON_UPD_EVT_BIT = 2,
+ LE_CON_UPD_EVT_MSK = 0x0004,
+ LE_CON_RD_REM_FEAT_EVT_BIT = 3,
+ LE_CON_RD_REM_FEAT_EVT_MSK = 0x0008,
+ LE_LG_TR_KEY_REQ_EVT_BIT = 4,
+ LE_LG_TR_KEY_REQ_EVT_MSK = 0x0010,
+ LE_REM_CON_PARA_REQ_EVT_BIT = 5,
+ LE_REM_CON_PARA_REQ_EVT_MSK = 0x0020,
+ LE_DATA_LEN_CHG_EVT_BIT = 6,
+ LE_DATA_LEN_CHG_EVT_MSK = 0x0040,
+ LE_RD_LOC_P256_PUB_KEY_CMP_EVT_BIT = 7,
+ LE_RD_LOC_P256_PUB_KEY_CMP_EVT_MSK = 0x0080,
+ LE_GEN_DHKEY_CMP_EVT_BIT = 8,
+ LE_GEN_DHKEY_CMP_EVT_MSK = 0x0100,
+ LE_ENH_CON_CMP_EVT_BIT = 9,
+ LE_ENH_CON_CMP_EVT_MSK = 0x0200,
+ LE_DIR_ADV_REP_EVT_BIT = 10,
+ LE_DIR_ADV_REP_EVT_MSK = 0x0400,
+
+ LE_DFT_EVT_MSK = 0x1F,
+};
+
+/// Enhanced Synchronous Connection HCI:7.1.41 & 7.1.42
+#define CODING_FORMAT_ULAW 0x00
+#define CODING_FORMAT_ALAW 0x01
+#define CODING_FORMAT_CVSD 0x02
+#define CODING_FORMAT_TRANSP 0x03
+#define CODING_FORMAT_LINPCM 0x04
+#define CODING_FORMAT_MSBC 0x05
+#define CODING_FORMAT_VENDSPEC 0xFF
+
+#define PCM_FORMAT_NA 0x00
+#define PCM_FORMAT_1SCOMP 0x01
+#define PCM_FORMAT_2SCOMP 0x02
+#define PCM_FORMAT_SIGNMAG 0x03
+#define PCM_FORMAT_UNSIGNED 0x04
+
+#define PCM_SAMPLE_SIZE_8BITS 8
+#define PCM_SAMPLE_SIZE_16BITS 16
+
+#define AUDIO_DATA_PATH_HCI 0
+#define AUDIO_DATA_PATH_PCM 1
+
+/// Default maximum number of slots per packet
+#define MAX_SLOT_DFT 1
+
+/// Packet type code interpretation possibilities BB:6.5
+#define ID_NUL_TYPE 0x0
+#define POLL_TYPE 0x1
+#define FHS_TYPE 0x2
+#define DM1_TYPE 0x3
+#define DH1_TYPE 0x4
+#define DH1_2_TYPE 0x4
+#define DH1_3_TYPE 0x8
+#define HV1_TYPE 0x5
+#define HV2_TYPE 0x6
+#define EV3_2_TYPE 0x6
+#define HV3_TYPE 0x7
+#define EV3_TYPE 0x7
+#define EV3_3_TYPE 0x7
+#define DV_TYPE 0x8
+#define AUX1_TYPE 0x9
+#define DM3_TYPE 0xA
+#define DH3_TYPE 0xB
+#define DH3_2_TYPE 0xA
+#define DH3_3_TYPE 0xB
+#define EV4_TYPE 0xC
+#define EV5_2_TYPE 0xC
+#define EV5_TYPE 0xD
+#define EV5_3_TYPE 0xD
+#define DM5_TYPE 0xE
+#define DH5_TYPE 0xF
+#define DH5_2_TYPE 0xE
+#define DH5_3_TYPE 0xF
+
+/// Format of the FHS payload BB:6.5.1.4
+#define FHS_PAR_BITS_POS 0
+#define FHS_PAR_BITS_LEN 34
+#define FHS_PAR_BITS_END (FHS_PAR_BITS_POS + FHS_PAR_BITS_LEN)
+#define FHS_LAP_POS FHS_PAR_BITS_END
+#define FHS_LAP_LEN 24
+#define FHS_LAP_END (FHS_LAP_POS + FHS_LAP_LEN)
+#define FHS_EIR_POS FHS_LAP_END
+#define FHS_EIR_LEN 1
+#define FHS_EIR_END (FHS_EIR_POS + FHS_EIR_LEN)
+#define FHS_UNDEF_POS FHS_EIR_END
+#define FHS_UNDEF_LEN 1
+#define FHS_UNDEF_END (FHS_UNDEF_POS + FHS_UNDEF_LEN)
+#define FHS_SR_POS FHS_UNDEF_END
+#define FHS_SR_LEN 2
+#define FHS_SR_END (FHS_SR_POS + FHS_SR_LEN)
+#define FHS_RSVD_POS FHS_SR_END
+#define FHS_RSVD_LEN 2
+#define FHS_RSVD_END (FHS_RSVD_POS + FHS_RSVD_LEN)
+#define FHS_UAP_POS FHS_RSVD_END
+#define FHS_UAP_LEN 8
+#define FHS_UAP_END (FHS_UAP_POS + FHS_UAP_LEN)
+#define FHS_NAP_POS FHS_UAP_END
+#define FHS_NAP_LEN 16
+#define FHS_NAP_END (FHS_NAP_POS + FHS_NAP_LEN)
+#define FHS_CLASS_OF_DEV_POS FHS_NAP_END
+#define FHS_CLASS_OF_DEV_LEN 24
+#define FHS_CLASS_OF_DEV_END (FHS_CLASS_OF_DEV_POS + FHS_CLASS_OF_DEV_LEN)
+#define FHS_LT_ADDR_POS FHS_CLASS_OF_DEV_END
+#define FHS_LT_ADDR_LEN 3
+#define FHS_LT_ADDR_END (FHS_LT_ADDR_POS + FHS_LT_ADDR_LEN)
+#define FHS_CLK_POS FHS_LT_ADDR_END
+#define FHS_CLK_LEN 26
+#define FHS_CLK_END (FHS_CLK_POS + FHS_CLK_LEN)
+#define FHS_PAGE_SCAN_MODE_POS FHS_CLK_END
+#define FHS_PAGE_SCAN_MODE_LEN 3
+#define FHS_PAGE_SCAN_MODE_END (FHS_PAGE_SCAN_MODE_POS + FHS_PAGE_SCAN_MODE_LEN)
+
+/// Format of the STP payload BB:8.11.2
+#define STP_CLK_POS 0
+#define STP_CLK_LEN 4
+#define STP_FUT_CSB_INST_POS 4
+#define STP_FUT_CSB_INST_LEN 4
+#define STP_AFH_CH_MAP_POS 8
+#define STP_AFH_CH_MAP_LEN 10
+#define STP_MST_BD_ADDR_POS 18
+#define STP_MST_BD_ADDR_LEN 6
+#define STP_CSB_INTV_POS 24
+#define STP_CSB_INTV_LEN 2
+#define STP_CSB_LT_ADDR_POS 26
+#define STP_CSB_LT_ADDR_LEN 1
+#define STP_SVC_DATA_POS 27
+#define STP_SVC_DATA_LEN 1
+#define STP_PACKET_SIZE 28
+
+/// CSB Receive status HCI:7.7.69
+#define CSB_RX_OK 0x00
+#define CSB_RX_KO 0x01
+
+/*
+ * ENUMERATIONS
+ ****************************************************************************************
+ */
+
+///Transmit Power level types
+enum
+{
+ ///Current Power Level
+ TX_PW_LVL_CURRENT = 0x00,
+ ///Maximum power level
+ TX_PW_LVL_MAX,
+ ///Enumeration end value for power level type value check
+ TX_PW_LVL_END,
+};
+
+///Controller to Host flow control
+enum
+{
+ /// C-> H flow control off
+ FLOW_CTRL_OFF = 0x00,
+ ///C->H ACL flow control on only
+ FLOW_CTRL_ON_ACL_OFF_SYNC,
+ ///C->H Sync flow control on only
+ FLOW_CTRL_OFF_ACL_ON_SYNC,
+ ///C->H ACL and Sync flow control on
+ FLOW_CTRL_ON_ACL_ON_SYNC,
+ ///Enumeration end value for flow control value check
+ FLOW_CTRL_END
+};
+
+///LE Supported Host enable
+enum
+{
+ ///Disable LE supported Host
+ LE_SUPP_HOST_DIS = 0x00,
+ ///Enable LE Supported Host
+ LE_SUPP_HOST_EN,
+ ///Enumeration end value for LE supported Host enable check
+ LE_SUPP_HOST_END
+};
+
+///Simultaneous LE Host enable
+enum
+{
+ ///Disable LE simultaneous Host disable
+ SIMULT_LE_HOST_DIS = 0x00,
+ ///Enable LE simultaneous Host disable
+ SIMULT_LE_HOST_EN,
+ ///Enumeration end value for LE simultaneous Host enable check
+ SIMULT_LE_HOST_END
+};
+
+///Advertising HCI Type
+enum
+{
+ ///Connectable Undirected advertising
+ ADV_CONN_UNDIR = 0x00,
+ ///Connectable high duty cycle directed advertising
+ ADV_CONN_DIR,
+ ///Discoverable undirected advertising
+ ADV_DISC_UNDIR,
+ ///Non-connectable undirected advertising
+ ADV_NONCONN_UNDIR,
+ ///Connectable low duty cycle directed advertising
+ ADV_CONN_DIR_LDC,
+ ///Enumeration end value for advertising type value check
+ ADV_END
+};
+
+///Scanning HCI Type
+enum
+{
+ ///Scan request
+ SCAN_REQ,
+ ///Scan response
+ SCAN_RSP,
+ ///Enumeration end value for scanning type value check
+ SCAN_LEN
+};
+
+///BD address type
+enum
+{
+ ///Public BD address
+ ADDR_PUBLIC = 0x00,
+ ///Random BD Address
+ ADDR_RAND,
+ /// Controller generates Resolvable Private Address based on the
+ /// local IRK from resolving list. If resolving list contains no matching
+ /// entry, use public address.
+ ADDR_RPA_OR_PUBLIC,
+ /// Controller generates Resolvable Private Address based on the
+ /// local IRK from resolving list. If resolving list contains no matching
+ /// entry, use random address.
+ ADDR_RPA_OR_RAND,
+ ///Enumeration end value for BD address type value check
+ ADDR_END,
+
+ /// mask used to determine Address type in the air
+ ADDR_MASK = 0x01,
+ /// mask used to determine if an address is an RPA
+ ADDR_RPA_MASK = 0x02,
+};
+
+/// Random Address type (2 MSB of the LE BD Address)
+enum rnd_addr_type
+{
+ /// Static random address - 11 (MSB->LSB)
+ RND_STATIC_ADDR = 0xC0,
+ /// Private non resolvable address - 01 (MSB->LSB)
+ RND_NON_RSLV_ADDR = 0x00,
+ /// Private resolvable address - 01 (MSB->LSB)
+ RND_RSLV_ADDR = 0x40,
+};
+
+///Advertising channels enables
+enum adv_channel_map
+{
+ ///Byte value for advertising channel map for channel 37 enable
+ ADV_CHNL_37_EN = 0x01,
+ ///Byte value for advertising channel map for channel 38 enable
+ ADV_CHNL_38_EN,
+ ///Byte value for advertising channel map for channel 39 enable
+ ADV_CHNL_39_EN = 0x04,
+ ///Byte value for advertising channel map for channel 37, 38 and 39 enable
+ ADV_ALL_CHNLS_EN = 0x07,
+ ///Enumeration end value for advertising channels enable value check
+ ADV_CHNL_END
+};
+
+///Advertising filter policy
+enum adv_filter_policy
+{
+ ///Allow both scan and connection requests from anyone
+ ADV_ALLOW_SCAN_ANY_CON_ANY = 0x00,
+ ///Allow both scan req from White List devices only and connection req from anyone
+ ADV_ALLOW_SCAN_WLST_CON_ANY,
+ ///Allow both scan req from anyone and connection req from White List devices only
+ ADV_ALLOW_SCAN_ANY_CON_WLST,
+ ///Allow scan and connection requests from White List devices only
+ ADV_ALLOW_SCAN_WLST_CON_WLST,
+ ///Enumeration end value for advertising filter policy value check
+ ADV_ALLOW_SCAN_END
+};
+
+///Advertising enables
+enum
+{
+ ///Disable advertising
+ ADV_DIS = 0x00,
+ ///Enable advertising
+ ADV_EN,
+ ///Enumeration end value for advertising enable value check
+ ADV_EN_END
+};
+
+///LE Scan type
+enum
+{
+ ///Passive scan
+ SCAN_PASSIVE = 0x00,
+ ///Active scan
+ SCAN_ACTIVE,
+ ///Enumeration end value for scan type value check
+ SCAN_END
+};
+
+///Scan filter policy
+enum scan_filter_policy
+{
+ ///Allow advertising packets from anyone
+ SCAN_ALLOW_ADV_ALL = 0x00,
+ ///Allow advertising packets from White List devices only
+ SCAN_ALLOW_ADV_WLST,
+ ///Allow advertising packets from anyone and Direct adv using RPA in InitA
+ SCAN_ALLOW_ADV_ALL_AND_INIT_RPA,
+ ///Allow advertising packets from White List devices only and Direct adv using RPA in InitA
+ SCAN_ALLOW_ADV_WLST_AND_INIT_RPA,
+ ///Enumeration end value for scan filter policy value check
+ SCAN_ALLOW_ADV_END
+};
+
+///Le Scan enables
+enum
+{
+ ///Disable scan
+ SCAN_DIS = 0x00,
+ ///Enable scan
+ SCAN_EN,
+ ///Enumeration end value for scan enable value check
+ SCAN_EN_END
+};
+
+///Filter duplicates
+enum scan_dup_filter_policy
+{
+ ///Disable filtering of duplicate packets
+ SCAN_FILT_DUPLIC_DIS = 0x00,
+ ///Enable filtering of duplicate packets
+ SCAN_FILT_DUPLIC_EN,
+ ///Enumeration end value for scan duplicate filtering value check
+ SCAN_FILT_DUPLIC_END
+};
+
+///Initiator Filter policy
+enum
+{
+ ///Initiator will ignore White List
+ INIT_FILT_IGNORE_WLST = 0x00,
+ ///Initiator will use White List
+ INIT_FILT_USE_WLST,
+ ///Enumeration end value for initiator filter policy value check
+ INIT_FILT_END
+};
+
+///Transmitter test Packet Payload Type
+enum
+{
+ ///Pseudo-random 9 TX test payload type
+ PAYL_PSEUDO_RAND_9 = 0x00,
+ ///11110000 TX test payload type
+ PAYL_11110000,
+ ///10101010 TX test payload type
+ PAYL_10101010,
+ ///Pseudo-random 15 TX test payload type
+ PAYL_PSEUDO_RAND_15,
+ ///All 1s TX test payload type
+ PAYL_ALL_1,
+ ///All 0s TX test payload type
+ PAYL_ALL_0,
+ ///00001111 TX test payload type
+ PAYL_00001111,
+ ///01010101 TX test payload type
+ PAYL_01010101,
+ ///Enumeration end value for TX test payload type value check
+ PAYL_END
+};
+
+/// Constant defining the role
+enum
+{
+ ///Master role
+ ROLE_MASTER,
+ ///Slave role
+ ROLE_SLAVE,
+ ///Enumeration end value for role value check
+ ROLE_END
+};
+
+/// Constant clock accuracy
+enum
+{
+ ///Clock accuracy at 500PPM
+ SCA_500PPM,
+ ///Clock accuracy at 250PPM
+ SCA_250PPM,
+ ///Clock accuracy at 150PPM
+ SCA_150PPM,
+ ///Clock accuracy at 100PPM
+ SCA_100PPM,
+ ///Clock accuracy at 75PPM
+ SCA_75PPM,
+ ///Clock accuracy at 50PPM
+ SCA_50PPM,
+ ///Clock accuracy at 30PPM
+ SCA_30PPM,
+ ///Clock accuracy at 20PPM
+ SCA_20PPM
+};
+
+///Advertising pdu Type
+enum
+{
+ /// Undirected advertising
+ LL_ADV_CONN_UNDIR = 0x00,
+ /// Directed advertising
+ LL_ADV_CONN_DIR,
+ /// Non Connectable advertising
+ LL_ADV_NONCONN_UNDIR,
+ /// Scan Request
+ LL_SCAN_REQ,
+ /// Scan Response
+ LL_SCAN_RSP,
+ /// Connect Request
+ LL_CONNECT_REQ,
+ /// Discoverable advertising
+ LL_ADV_DISC_UNDIR,
+ LL_ADV_END
+};
+
+/// LLID packet
+enum
+{
+ /// Reserved for future use
+ LLID_RFU,
+ /// Continue
+ LLID_CONTINUE,
+ /// Start
+ LLID_START,
+ /// Control
+ LLID_CNTL,
+ /// End
+ LLID_END,
+};
+
+/// Remote OOB Data present parameter value HCI:7.1.29
+enum
+{
+ REM_OOB_DATA_NO = 0x00,
+ REM_OOB_DATA_P192 = 0x01,
+ REM_OOB_DATA_P256 = 0x02,
+ REM_OOB_DATA_P192_P256 = 0x03,
+};
+
+/// Encryption enabled parameter in HCI_Enc_Chg_Evt HCI:7.7.8
+enum
+{
+ ENC_OFF = 0x00,
+ ENC_BRDER_E0_LE_AESCCM = 0x01,
+ ENC_BREDR_AESCC = 0x02,
+};
+
+
+/*
+ * STRUCTURE DEFINITONS
+ ****************************************************************************************
+ */
+
+///BD name structure
+struct bd_name
+{
+ ///length for name
+ uint8_t namelen;
+ ///array of bytes for name
+ uint8_t name[BD_NAME_SIZE];
+};
+
+///Structure device name
+struct device_name
+{
+ ///array of bytes for name
+ uint8_t name[BD_NAME_SIZE];
+};
+
+///Structure name vector
+struct name_vect
+{
+ uint8_t vect[NAME_VECT_SIZE];
+};
+
+/// lap structure
+struct lap
+{
+ /// LAP
+ uint8_t A[BD_ADDR_LAP_LEN];
+};
+
+/// class structure
+struct devclass
+{
+ /// class
+ uint8_t A[DEV_CLASS_LEN];
+};
+
+///Extended inquiry response structure
+struct eir
+{
+ /// eir data
+ uint8_t data[EIR_DATA_SIZE];
+};
+
+///Event mask structure
+struct evt_mask
+{
+ ///8-byte array for mask value
+ uint8_t mask[EVT_MASK_LEN];
+};
+
+///Host number of completed packets structure, for 1 connection handle
+struct host_cmpl_pkts
+{
+ ///Connection handle
+ uint16_t con_hdl;
+ ///Number of completed packets
+ uint16_t nb_cmpl_pkts;
+};
+
+///BD Address structure
+struct bd_addr
+{
+ ///6-byte array address value
+ uint8_t addr[BD_ADDR_LEN];
+};
+
+///Access Address structure
+struct access_addr
+{
+ ///4-byte array access address
+ uint8_t addr[ACCESS_ADDR_LEN];
+};
+
+///Advertising data structure
+struct adv_data
+{
+ ///Maximum length data bytes array
+ uint8_t data[ADV_DATA_LEN];
+};
+
+///Scan response data structure
+struct scan_rsp_data
+{
+ ///Maximum length data bytes array
+ uint8_t data[SCAN_RSP_DATA_LEN];
+};
+
+///Channel map structure
+struct chnl_map
+{
+ ///10-bytes channel map array
+ uint8_t map[CHNL_MAP_LEN];
+};
+
+///Channel map structure
+struct le_chnl_map
+{
+ ///5-byte channel map array
+ uint8_t map[LE_CHNL_MAP_LEN];
+};
+
+///Long Term Key structure
+struct ltk
+{
+ ///16-byte array for LTK value
+ uint8_t ltk[KEY_LEN];
+};
+
+///Identity Resolving Key structure
+struct irk
+{
+ ///16-byte array for IRK value
+ uint8_t key[KEY_LEN];
+};
+
+/// Initialization vector (for AES-CCM encryption)
+struct initialization_vector
+{
+ ///8-byte array
+ uint8_t vect[IV_LEN];
+};
+
+/// Bluetooth address with link key
+struct bd_addr_plus_key
+{
+ /// BD Address
+ struct bd_addr bd_addr;
+ /// Link Key
+ struct ltk link_key;
+};
+
+///Random number structure
+struct rand_nb
+{
+ ///8-byte array for random number
+ uint8_t nb[RAND_NB_LEN];
+};
+
+///Advertising report structure
+struct adv_report
+{
+ ///Event type:
+ /// - ADV_CONN_UNDIR: Connectable Undirected advertising
+ /// - ADV_CONN_DIR: Connectable directed advertising
+ /// - ADV_DISC_UNDIR: Discoverable undirected advertising
+ /// - ADV_NONCONN_UNDIR: Non-connectable undirected advertising
+ uint8_t evt_type;
+ ///Advertising address type: public/random
+ uint8_t adv_addr_type;
+ ///Advertising address value
+ struct bd_addr adv_addr;
+ ///Data length in advertising packet
+ uint8_t data_len;
+ ///Data of advertising packet
+ uint8_t data[ADV_DATA_LEN];
+ ///RSSI value for advertising packet
+ uint8_t rssi;
+};
+
+
+///Direct Advertising report structure
+struct dir_adv_report
+{
+ ///Event type:
+ /// - ADV_CONN_DIR: Connectable directed advertising
+ uint8_t evt_type;
+ ///Address type: public/random
+ uint8_t addr_type;
+ ///Address value
+ struct bd_addr addr;
+ ///Direct address type: public/random
+ uint8_t dir_addr_type;
+ ///Direct address value
+ struct bd_addr dir_addr;
+ ///RSSI value for advertising packet
+ uint8_t rssi;
+};
+
+///Supported LE Features structure
+struct le_features
+{
+ ///8-byte array for LE features
+ uint8_t feats[LE_FEATS_LEN];
+};
+
+///Simple pairing hash structure
+struct hash
+{
+ ///16-byte array for LTK value
+ uint8_t C[KEY_LEN];
+};
+
+///Simple pairing randomizer structure
+struct randomizer
+{
+ ///16-byte array for LTK value
+ uint8_t R[KEY_LEN];
+};
+
+///Pin code structure
+struct pin_code
+{
+ ///16-byte array for PIN value
+ uint8_t pin[PIN_CODE_MAX_LEN];
+};
+
+///Sres structure
+struct sres_nb
+{
+ ///8-byte array for random number
+ uint8_t nb[SRES_LEN];
+};
+
+///aco structure
+struct aco
+{
+ ///8-byte array for random number
+ uint8_t a[ACO_LEN];
+};
+
+///struct byte 16 to stay align with the sdl version
+struct byte16
+{
+ uint8_t A[16];
+};
+
+///Controller number of completed packets structure
+struct nb_cmpl_pk
+{
+ ///Connection handle
+ uint16_t con_hdl;
+ ///Controller number of data packets that have been completed since last time
+ uint16_t nb_hc_cmpl_pkts;
+};
+
+///Supported Features structure
+struct features
+{
+ ///8-byte array for features
+ uint8_t feats[FEATS_LEN];
+};
+
+///Supported commands structure
+struct supp_cmds
+{
+ ///64-byte array for supported commands
+ uint8_t cmds[SUPP_CMDS_LEN];
+};
+
+///Supported LMP features structure
+struct lmp_features
+{
+ ///8-byte array for LMp features
+ uint8_t feats[FEATS_LEN];
+};
+
+///Simple pairing IO capabilities
+struct io_capability
+{
+ ///IO capability
+ uint8_t io_cap;
+ /// Out Of Band Data present
+ bool oob_data_present;
+ ///Authentication Requirement
+ uint8_t aut_req;
+};
+
+///Public key
+struct pub_key_192
+{
+ uint8_t p_key[PUB_KEY_192_LEN/2];
+};
+
+///Public key
+struct pub_key_256
+{
+ uint8_t p_key[PUB_KEY_256_LEN/2];
+};
+
+///Simple pairing public keys 192
+struct sp_pub_key_192
+{
+ ///Public key X
+ struct pub_key_192 X;
+ ///Public key Y
+ struct pub_key_192 Y;
+};
+
+///Simple pairing public keys 256
+struct sp_pub_key_256
+{
+ ///Public key X
+ struct pub_key_256 X;
+ ///Public key Y
+ struct pub_key_256 Y;
+};
+
+///Supported LE states structure
+struct le_states
+{
+ ///8-byte array for LE states
+ uint8_t supp_states[LE_STATES_LEN];
+};
+
+///White List element structure
+struct white_list
+{
+ ///BD address of device entry
+ struct bd_addr wl_bdaddr;
+ ///BD address type of device entry
+ uint8_t wl_bdaddr_type;
+};
+
+///CRC initial value structure
+struct crc_init
+{
+ ///3-byte array CRC initial value
+ uint8_t crc[CRC_INIT_LEN];
+};
+
+///Session key diversifier master or slave structure
+struct sess_k_div_x
+{
+ ///8-byte array for diversifier value
+ uint8_t skdiv[SESS_KEY_DIV_LEN];
+};
+
+///Session key diversifier structure
+struct sess_k_div
+{
+ ///16-byte array for session key diversifier.
+ uint8_t skd[2*SESS_KEY_DIV_LEN];
+};
+
+///Initiator vector
+struct init_vect
+{
+ ///4-byte array for vector
+ uint8_t iv[INIT_VECT_LEN];
+};
+
+typedef struct t_public_key
+{
+ uint8_t x[PUBLIC_KEY_P256_LEN];
+ uint8_t y[PUBLIC_KEY_P256_LEN];
+
+} t_public_key;
+
+
+/// @} CO_BT_DEFINES
+#endif // CO_BT_DEFINES_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_endian.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_endian.h
new file mode 100644
index 0000000000..c567288e54
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_endian.h
@@ -0,0 +1,248 @@
+/**
+ ****************************************************************************************
+ *
+ * @file co_endian.h
+ *
+ * @brief Common endianness conversion functions
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef _CO_ENDIAN_H_
+#define _CO_ENDIAN_H_
+
+#include // standard integer definitions
+#include "rwip_config.h" // stack configuration
+#include "ble_arch.h"
+
+/**
+ ****************************************************************************************
+ * @defgroup CO_ENDIAN Endianness
+ * @ingroup COMMON
+ * @brief Endianness conversion functions.
+ *
+ * This set of functions converts values between the local system
+ * and a external one. It is inspired from the htonl-like functions
+ * from the standard C library.
+ *
+ * Example:
+ * @code
+ * struct eth_header *header = get_header(); // get pointer on Eth II packet header
+ * uint16_t eth_id; // will contain the type of the packet
+ * eth_id = co_ntohs(header->eth_id); // retrieve the type with correct endianness
+ * @endcode
+ *
+ * @{
+ * ****************************************************************************************
+ * */
+
+
+/**
+ ****************************************************************************************
+ * @brief Swap bytes of a 32 bits value.
+ * The swap is done in every case. Should not be called directly.
+ * @param[in] val32 The 32 bits value to swap.
+ * @return The 32 bit swapped value.
+ ****************************************************************************************
+ */
+__INLINE uint32_t co_bswap32(uint32_t val32)
+{
+ return (val32<<24) | ((val32<<8)&0xFF0000) | ((val32>>8)&0xFF00) | ((val32>>24)&0xFF);
+}
+
+/**
+ ****************************************************************************************
+ * @brief Swap bytes of a 16 bits value.
+ * The swap is done in every case. Should not be called directly.
+ * @param[in] val16 The 16 bit value to swap.
+ * @return The 16 bit swapped value.
+ ****************************************************************************************
+ */
+__INLINE uint16_t co_bswap16(uint16_t val16)
+{
+ return ((val16<<8)&0xFF00) | ((val16>>8)&0xFF);
+}
+/// @} CO_ENDIAN
+
+
+
+
+/**
+ * ****************************************************************************************
+ * @defgroup CO_ENDIAN_NET Endianness (Network)
+ * @ingroup CO_ENDIAN
+ * @brief Endianness conversion functions for Network data
+ *
+ * Converts values between the local system and big-endian network data
+ * (e.g. IP, Ethernet, but NOT WLAN).
+ *
+ * The \b host term in the descriptions of these functions refers
+ * to the local system, i.e. \b application or \b embedded system.
+ * Therefore, these functions will behave differently depending on which
+ * side they are used. The reason of this terminology is to keep the
+ * same name than the standard C function.
+ *
+ * Behavior will depends on the endianness of the host:
+ * - little endian: swap bytes;
+ * - big endian: identity function.
+ *
+ * @{
+ * ****************************************************************************************
+ * */
+
+/**
+ ****************************************************************************************
+ * @brief Convert host to network long word.
+ *
+ * @param[in] hostlong Long word value to convert.
+ *
+ * @return The converted long word.
+ ****************************************************************************************
+ */
+__INLINE uint32_t co_htonl(uint32_t hostlong)
+{
+ #if (!CPU_LE)
+ return hostlong;
+ #else
+ return co_bswap32(hostlong);
+ #endif // CPU_LE
+}
+
+/**
+ ****************************************************************************************
+ * @brief Convert host to network short word.
+ *
+ * @param[in] hostshort Short word value to convert.
+ *
+ * @return The converted short word.
+ ****************************************************************************************
+ */
+__INLINE uint16_t co_htons(uint16_t hostshort)
+{
+ #if (!CPU_LE)
+ return hostshort;
+ #else
+ return co_bswap16(hostshort);
+ #endif // CPU_LE
+}
+
+/**
+ ****************************************************************************************
+ * @brief Convert network to host long word.
+ *
+ * @param[in] netlong Long word value to convert.
+ *
+ * @return The converted long word.
+ ****************************************************************************************
+ */
+__INLINE uint32_t co_ntohl(uint32_t netlong)
+{
+ return co_htonl(netlong);
+}
+
+/**
+ ****************************************************************************************
+ * @brief Convert network to host short word.
+ *
+ * @param[in] netshort Short word value to convert.
+ *
+ * @return The converted short word.
+ ****************************************************************************************
+ */
+__INLINE uint16_t co_ntohs(uint16_t netshort)
+{
+ return co_htons(netshort);
+}
+/// @} CO_ENDIAN_NET
+
+/**
+ * ****************************************************************************************
+ * @defgroup CO_ENDIAN_BT Endianness (BT)
+ * @ingroup CO_ENDIAN
+ * @brief Endianness conversion functions for Bluetooth data (HCI and protocol)
+ *
+ * Converts values between the local system and little-endian Bluetooth data.
+ *
+ * The \b host term in the descriptions of these functions refers
+ * to the local system (check \ref CO_ENDIAN_NET "this comment").
+ *
+ * Behavior will depends on the endianness of the host:
+ * - little endian: identity function;
+ * - big endian: swap bytes.
+ *
+ * @addtogroup CO_ENDIAN_BT
+ * @{
+ * ****************************************************************************************
+ * */
+
+/**
+ ****************************************************************************************
+ * @brief Convert host to Bluetooth long word.
+ *
+ * @param[in] hostlong Long word value to convert.
+ *
+ * @return The converted long word.
+ ****************************************************************************************
+ */
+__INLINE uint32_t co_htobl(uint32_t hostlong)
+{
+ #if (CPU_LE)
+ return hostlong;
+ #else
+ return co_bswap32(hostlong);
+ #endif // CPU_LE
+}
+
+/**
+ ****************************************************************************************
+ * @brief Convert host to Bluetooth short word.
+ *
+ * @param[in] hostshort Short word value to convert.
+ *
+ * @return The converted short word.
+ ****************************************************************************************
+ */
+__INLINE uint16_t co_htobs(uint16_t hostshort)
+{
+ #if (CPU_LE)
+ return hostshort;
+ #else
+ return co_bswap16(hostshort);
+ #endif // CPU_LE
+}
+
+
+/**
+ ****************************************************************************************
+ * @brief Convert Bluetooth to host long word.
+ *
+ * @param[in] btlong Long word value to convert.
+ *
+ * @return The converted long word.
+ ****************************************************************************************
+ */
+__INLINE uint32_t co_btohl(uint32_t btlong)
+{
+ return co_htobl(btlong);
+}
+
+
+/**
+ ****************************************************************************************
+ * @brief Convert Bluetooth to host short word.
+ *
+ * @param[in] btshort Short word value to convert.
+ *
+ * @return The converted short word.
+ ****************************************************************************************
+ */
+__INLINE uint16_t co_btohs(uint16_t btshort)
+{
+ return co_htobs(btshort);
+}
+/// @} CO_ENDIAN
+
+#endif // _CO_ENDIAN_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_error.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_error.h
new file mode 100644
index 0000000000..0bcd0f4da1
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_error.h
@@ -0,0 +1,110 @@
+/**
+ ****************************************************************************************
+ *
+ * @file co_error.h
+ *
+ * @brief List of codes for error in RW Software.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef CO_ERROR_H_
+#define CO_ERROR_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup CO_ERROR Error Codes
+ * @ingroup COMMON
+ * @brief Defines error codes in messages.
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+enum co_error
+{
+/*****************************************************
+ *** ERROR CODES ***
+ *****************************************************/
+
+ CO_ERROR_NO_ERROR = 0x00,
+ CO_ERROR_UNKNOWN_HCI_COMMAND = 0x01,
+ CO_ERROR_UNKNOWN_CONNECTION_ID = 0x02,
+ CO_ERROR_HARDWARE_FAILURE = 0x03,
+ CO_ERROR_PAGE_TIMEOUT = 0x04,
+ CO_ERROR_AUTH_FAILURE = 0x05,
+ CO_ERROR_PIN_MISSING = 0x06,
+ CO_ERROR_MEMORY_CAPA_EXCEED = 0x07,
+ CO_ERROR_CON_TIMEOUT = 0x08,
+ CO_ERROR_CON_LIMIT_EXCEED = 0x09,
+ CO_ERROR_SYNC_CON_LIMIT_DEV_EXCEED = 0x0A,
+ CO_ERROR_ACL_CON_EXISTS = 0x0B,
+ CO_ERROR_COMMAND_DISALLOWED = 0x0C,
+ CO_ERROR_CONN_REJ_LIMITED_RESOURCES = 0x0D,
+ CO_ERROR_CONN_REJ_SECURITY_REASONS = 0x0E,
+ CO_ERROR_CONN_REJ_UNACCEPTABLE_BDADDR = 0x0F,
+ CO_ERROR_CONN_ACCEPT_TIMEOUT_EXCEED = 0x10,
+ CO_ERROR_UNSUPPORTED = 0x11,
+ CO_ERROR_INVALID_HCI_PARAM = 0x12,
+ CO_ERROR_REMOTE_USER_TERM_CON = 0x13,
+ CO_ERROR_REMOTE_DEV_TERM_LOW_RESOURCES = 0x14,
+ CO_ERROR_REMOTE_DEV_POWER_OFF = 0x15,
+ CO_ERROR_CON_TERM_BY_LOCAL_HOST = 0x16,
+ CO_ERROR_REPEATED_ATTEMPTS = 0x17,
+ CO_ERROR_PAIRING_NOT_ALLOWED = 0x18,
+ CO_ERROR_UNKNOWN_LMP_PDU = 0x19,
+ CO_ERROR_UNSUPPORTED_REMOTE_FEATURE = 0x1A,
+ CO_ERROR_SCO_OFFSET_REJECTED = 0x1B,
+ CO_ERROR_SCO_INTERVAL_REJECTED = 0x1C,
+ CO_ERROR_SCO_AIR_MODE_REJECTED = 0x1D,
+ CO_ERROR_INVALID_LMP_PARAM = 0x1E,
+ CO_ERROR_UNSPECIFIED_ERROR = 0x1F,
+ CO_ERROR_UNSUPPORTED_LMP_PARAM_VALUE = 0x20,
+ CO_ERROR_ROLE_CHANGE_NOT_ALLOWED = 0x21,
+ CO_ERROR_LMP_RSP_TIMEOUT = 0x22,
+ CO_ERROR_LMP_COLLISION = 0x23,
+ CO_ERROR_LMP_PDU_NOT_ALLOWED = 0x24,
+ CO_ERROR_ENC_MODE_NOT_ACCEPT = 0x25,
+ CO_ERROR_LINK_KEY_CANT_CHANGE = 0x26,
+ CO_ERROR_QOS_NOT_SUPPORTED = 0x27,
+ CO_ERROR_INSTANT_PASSED = 0x28,
+ CO_ERROR_PAIRING_WITH_UNIT_KEY_NOT_SUP = 0x29,
+ CO_ERROR_DIFF_TRANSACTION_COLLISION = 0x2A,
+ CO_ERROR_QOS_UNACCEPTABLE_PARAM = 0x2C,
+ CO_ERROR_QOS_REJECTED = 0x2D,
+ CO_ERROR_CHANNEL_CLASS_NOT_SUP = 0x2E,
+ CO_ERROR_INSUFFICIENT_SECURITY = 0x2F,
+ CO_ERROR_PARAM_OUT_OF_MAND_RANGE = 0x30,
+ CO_ERROR_ROLE_SWITCH_PEND = 0x32, /* LM_ROLE_SWITCH_PENDING */
+ CO_ERROR_RESERVED_SLOT_VIOLATION = 0x34, /* LM_RESERVED_SLOT_VIOLATION */
+ CO_ERROR_ROLE_SWITCH_FAIL = 0x35, /* LM_ROLE_SWITCH_FAILED */
+ CO_ERROR_EIR_TOO_LARGE = 0x36, /* LM_EXTENDED_INQUIRY_RESPONSE_TOO_LARGE */
+ CO_ERROR_SP_NOT_SUPPORTED_HOST = 0x37,
+ CO_ERROR_HOST_BUSY_PAIRING = 0x38,
+ CO_ERROR_CONTROLLER_BUSY = 0x3A,
+ CO_ERROR_UNACCEPTABLE_CONN_INT = 0x3B,
+ CO_ERROR_DIRECT_ADV_TO = 0x3C,
+ CO_ERROR_TERMINATED_MIC_FAILURE = 0x3D,
+ CO_ERROR_CONN_FAILED_TO_BE_EST = 0x3E,
+ CO_ERROR_CCA_REJ_USE_CLOCK_DRAG = 0x40,
+ CO_ERROR_UNDEFINED = 0xFF,
+
+
+/*****************************************************
+ *** HW ERROR CODES ***
+ *****************************************************/
+
+ CO_ERROR_HW_UART_OUT_OF_SYNC = 0x00,
+ CO_ERROR_HW_MEM_ALLOC_FAIL = 0x01,
+};
+
+/// @} CO_ERROR
+
+#endif // CO_ERROR_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_hci.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_hci.h
new file mode 100644
index 0000000000..1617beca2a
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_hci.h
@@ -0,0 +1,4481 @@
+/**
+ ****************************************************************************************
+ *
+ * @file co_hci.h
+ *
+ * @brief This file contains the HCI Bluetooth defines, enumerations and structures
+ * definitions for use by all modules in RW stack.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ ****************************************************************************************
+ */
+
+#ifndef CO_HCI_H_
+#define CO_HCI_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup COMMON Common SW Block
+ * @{
+ ****************************************************************************************
+ */
+
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include // standard boolean definitions
+#include // standard definitions
+#include // standard integer definitions
+
+#include "rwip_config.h" // IP configuration
+#include "ble_arch.h"
+//#include "compiler.h" // compiler definitions
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+
+/******************************************************************************************/
+/* ------------------------- H4TL DEFINITIONS Part IV.A -----------------------------*/
+/******************************************************************************************/
+
+///HCI Transport Header length - change if different transport
+#define HCI_TRANSPORT_HDR_LEN 0x01
+
+///UART header: command message type
+#define HCI_CMD_MSG_TYPE 0x01
+
+///UART header: ACL data message type
+#define HCI_ACL_MSG_TYPE 0x02
+
+///UART header: Synchronous data message type
+#define HCI_SYNC_MSG_TYPE 0x03
+
+///UART header: event message type
+#define HCI_EVT_MSG_TYPE 0x04
+
+///UART header: event message type
+#define HCI_TCI_MSG_TYPE 0xFF
+
+/******************************************************************************************/
+/* ------------------------- HCI DEFINITIONS Part II.E -----------------------------*/
+/******************************************************************************************/
+
+///HCI Command Opcode byte length
+#define HCI_CMD_OPCODE_LEN (0x02)
+
+///HCI Event code byte length
+#define HCI_EVT_CODE_LEN (0x01)
+
+///HCI Command/Event parameter length field byte length
+#define HCI_CMDEVT_PARLEN_LEN (0x01)
+
+///HCI Command header length
+#define HCI_CMD_HDR_LEN (HCI_CMD_OPCODE_LEN + HCI_CMDEVT_PARLEN_LEN)
+
+///HCI Event header length
+#define HCI_EVT_HDR_LEN (HCI_EVT_CODE_LEN + HCI_CMDEVT_PARLEN_LEN)
+
+/// HCI ACL header: handle and flags decoding
+#define HCI_ACL_HDR_HDL_FLAGS_POS (0)
+#define HCI_ACL_HDR_HDL_FLAGS_LEN (2)
+#define HCI_ACL_HDR_HDL_POS (0)
+#define HCI_ACL_HDR_HDL_MASK (0x0FFF)
+#define HCI_ACL_HDR_PB_FLAG_POS (12)
+#define HCI_ACL_HDR_PB_FLAG_MASK (0x3000)
+#define HCI_ACL_HDR_BC_FLAG_POS (14)
+#define HCI_ACL_HDR_BC_FLAG_MASK (0xC000)
+#define HCI_ACL_HDR_DATA_FLAG_POS (12)
+#define HCI_ACL_HDR_DATA_FLAG_MASK (0xF000)
+
+/// HCI ACL header: data length field length
+#define HCI_ACL_HDR_DATA_LEN_POS (HCI_ACL_HDR_HDL_FLAGS_LEN)
+#define HCI_ACL_HDR_DATA_LEN_LEN (2)
+
+///HCI ACL data packet header length
+#define HCI_ACL_HDR_LEN (HCI_ACL_HDR_HDL_FLAGS_LEN + HCI_ACL_HDR_DATA_LEN_LEN)
+
+/// HCI Synchronous header: handle and flags decoding
+#define HCI_SYNC_HDR_HDL_FLAGS_POS (0)
+#define HCI_SYNC_HDR_HDL_FLAGS_LEN (2)
+#define HCI_SYNC_HDR_HDL_POS (0)
+#define HCI_SYNC_HDR_HDL_MASK (0x0FFF)
+#define HCI_SYNC_HDR_PSF_FLAG_POS (12)
+#define HCI_SYNC_HDR_PSF_FLAG_MASK (0x3000)
+#define HCI_SYNC_HDR_RES_FLAG_POS (14)
+#define HCI_SYNC_HDR_RES_FLAG_MASK (0xC000)
+#define HCI_SYNC_HDR_DATA_FLAG_POS (12)
+#define HCI_SYNC_HDR_DATA_FLAG_MASK (0xF000)
+
+/// HCI Synchronous header: data length field length
+#define HCI_SYNC_HDR_DATA_LEN_POS (HCI_SYNC_HDR_HDL_FLAGS_LEN)
+#define HCI_SYNC_HDR_DATA_LEN_LEN (1)
+#define HCI_SYNC_MAX_DATA_SIZE (255)
+
+///HCI sync data packet header length
+#define HCI_SYNC_HDR_LEN (HCI_SYNC_HDR_HDL_FLAGS_LEN + HCI_SYNC_HDR_DATA_LEN_LEN)
+
+///HCI Command Complete Event minimum parameter length: 1(nb_pk)+2(opcode)
+#define HCI_CCEVT_HDR_PARLEN (0x03)
+
+///HCI Command Complete Event header length:1(code)+1(len)+1(pk)+2(opcode)
+#define HCI_CCEVT_HDR_LEN (HCI_EVT_HDR_LEN + HCI_CCEVT_HDR_PARLEN)
+
+///HCI Basic Command Complete Event packet length
+#define HCI_CCEVT_BASIC_LEN (HCI_CCEVT_HDR_LEN + 1)
+
+///HCI Command Status Event parameter length - constant
+#define HCI_CSEVT_PARLEN (0x04)
+
+///HCI Command Status Event length:1(code)+1(len)+1(st)+1(pk)+2(opcode)
+#define HCI_CSEVT_LEN (HCI_EVT_HDR_LEN + HCI_CSEVT_PARLEN)
+
+///HCI Reset Command parameter length
+#define HCI_RESET_CMD_PARLEN 0
+
+/// Default return parameter length for HCI Command Complete Event
+#define HCI_CCEVT_BASIC_RETPAR_LEN 1
+
+/// Max HCI commands param size
+#define HCI_MAX_CMD_PARAM_SIZE 255
+
+/// Macro to extract OCF from OPCODE
+#define HCI_OP2OCF(opcode) ((opcode) & 0x03FF)
+
+/// Macro to extract OGF from OPCODE
+#define HCI_OP2OGF(opcode) ((opcode) >> 10 & 0x003F)
+
+/// Macro to create OPCODE from OGF and OCF
+#define HCI_OPCODE(ocf, ogf) (((ogf) << 10) | ocf)
+
+/**************************************************************************************
+ ************** HCI COMMANDS ****************
+ **************************************************************************************/
+
+///HCI enumeration of possible Command OGF values.
+enum
+{
+ ///HCI Link Control Commands Group OGF code
+ LK_CNTL_OGF = 0x01,
+ ///HCI Link Policy Commands Group OGF code
+ LK_POL_OGF,
+ ///HCI Controller and Baseband Commands Group OGF code
+ CNTLR_BB_OGF,
+ ///HCI Information Parameters Commands Group OGF code
+ INFO_PAR_OGF,
+ ///HCI Status Commands Group OGF code
+ STAT_PAR_OGF,
+ ///HCI Test Commands Group OGF code
+ TEST_OGF,
+ ///HCI Low Energy Commands Group OGF code
+ LE_CNTLR_OGF=0x08,
+ ///HCI Vendor Specific Group OGF code
+ VS_OGF = 0x3F,
+ MAX_OGF
+};
+
+
+///Commands Opcodes: OGF(6b) | OCF(10b)
+/* Some Abbreviation used in names:
+ * - LK = Link Key
+ * - RD = Read
+ * - WR = Write
+ * - REM = Remote
+ * - STG = Settings
+ * - CON = Connection
+ * - CHG = Change
+ * - DFT = Default
+ * - PER = Periodic
+ */
+
+///HCI enumeration of possible Command OP Codes.
+enum hci_opcode
+{
+ HCI_NO_OPERATION_CMD_OPCODE = 0x0000,
+
+ //Link Control Commands
+ HCI_INQ_CMD_OPCODE = 0x0401,
+ HCI_INQ_CANCEL_CMD_OPCODE = 0x0402,
+ HCI_PER_INQ_MODE_CMD_OPCODE = 0x0403,
+ HCI_EXIT_PER_INQ_MODE_CMD_OPCODE = 0x0404,
+ HCI_CREATE_CON_CMD_OPCODE = 0x0405,
+ HCI_DISCONNECT_CMD_OPCODE = 0x0406,
+ HCI_CREATE_CON_CANCEL_CMD_OPCODE = 0x0408,
+ HCI_ACCEPT_CON_REQ_CMD_OPCODE = 0x0409,
+ HCI_REJECT_CON_REQ_CMD_OPCODE = 0x040A,
+ HCI_LK_REQ_REPLY_CMD_OPCODE = 0x040B,
+ HCI_LK_REQ_NEG_REPLY_CMD_OPCODE = 0x040C,
+ HCI_PIN_CODE_REQ_REPLY_CMD_OPCODE = 0x040D,
+ HCI_PIN_CODE_REQ_NEG_REPLY_CMD_OPCODE = 0x040E,
+ HCI_CHG_CON_PKT_TYPE_CMD_OPCODE = 0x040F,
+ HCI_AUTH_REQ_CMD_OPCODE = 0x0411,
+ HCI_SET_CON_ENC_CMD_OPCODE = 0x0413,
+ HCI_CHG_CON_LK_CMD_OPCODE = 0x0415,
+ HCI_MASTER_LK_CMD_OPCODE = 0x0417,
+ HCI_REM_NAME_REQ_CMD_OPCODE = 0x0419,
+ HCI_REM_NAME_REQ_CANCEL_CMD_OPCODE = 0x041A,
+ HCI_RD_REM_SUPP_FEATS_CMD_OPCODE = 0x041B,
+ HCI_RD_REM_EXT_FEATS_CMD_OPCODE = 0x041C,
+ HCI_RD_REM_VER_INFO_CMD_OPCODE = 0x041D,
+ HCI_RD_CLK_OFF_CMD_OPCODE = 0x041F,
+ HCI_RD_LMP_HDL_CMD_OPCODE = 0x0420,
+ HCI_SETUP_SYNC_CON_CMD_OPCODE = 0x0428,
+ HCI_ACCEPT_SYNC_CON_REQ_CMD_OPCODE = 0x0429,
+ HCI_REJECT_SYNC_CON_REQ_CMD_OPCODE = 0x042A,
+ HCI_IO_CAP_REQ_REPLY_CMD_OPCODE = 0x042B,
+ HCI_USER_CFM_REQ_REPLY_CMD_OPCODE = 0x042C,
+ HCI_USER_CFM_REQ_NEG_REPLY_CMD_OPCODE = 0x042D,
+ HCI_USER_PASSKEY_REQ_REPLY_CMD_OPCODE = 0x042E,
+ HCI_USER_PASSKEY_REQ_NEG_REPLY_CMD_OPCODE = 0x042F,
+ HCI_REM_OOB_DATA_REQ_REPLY_CMD_OPCODE = 0x0430,
+ HCI_REM_OOB_DATA_REQ_NEG_REPLY_CMD_OPCODE = 0x0433,
+ HCI_IO_CAP_REQ_NEG_REPLY_CMD_OPCODE = 0x0434,
+ HCI_ENH_SETUP_SYNC_CON_CMD_OPCODE = 0x043D,
+ HCI_ENH_ACCEPT_SYNC_CON_CMD_OPCODE = 0x043E,
+ HCI_TRUNC_PAGE_CMD_OPCODE = 0x043F,
+ HCI_TRUNC_PAGE_CAN_CMD_OPCODE = 0x0440,
+ HCI_SET_CON_SLV_BCST_CMD_OPCODE = 0x0441,
+ HCI_SET_CON_SLV_BCST_REC_CMD_OPCODE = 0x0442,
+ HCI_START_SYNC_TRAIN_CMD_OPCODE = 0x0443,
+ HCI_REC_SYNC_TRAIN_CMD_OPCODE = 0x0444,
+ HCI_REM_OOB_EXT_DATA_REQ_REPLY_CMD_OPCODE = 0x0445,
+
+ //Link Policy Commands
+ HCI_HOLD_MODE_CMD_OPCODE = 0x0801,
+ HCI_SNIFF_MODE_CMD_OPCODE = 0x0803,
+ HCI_EXIT_SNIFF_MODE_CMD_OPCODE = 0x0804,
+ HCI_PARK_STATE_CMD_OPCODE = 0x0805,
+ HCI_EXIT_PARK_STATE_CMD_OPCODE = 0x0806,
+ HCI_QOS_SETUP_CMD_OPCODE = 0x0807,
+ HCI_ROLE_DISCOVERY_CMD_OPCODE = 0x0809,
+ HCI_SWITCH_ROLE_CMD_OPCODE = 0x080B,
+ HCI_RD_LINK_POL_STG_CMD_OPCODE = 0x080C,
+ HCI_WR_LINK_POL_STG_CMD_OPCODE = 0x080D,
+ HCI_RD_DFT_LINK_POL_STG_CMD_OPCODE = 0x080E,
+ HCI_WR_DFT_LINK_POL_STG_CMD_OPCODE = 0x080F,
+ HCI_FLOW_SPEC_CMD_OPCODE = 0x0810,
+ HCI_SNIFF_SUB_CMD_OPCODE = 0x0811,
+
+ //Controller and Baseband Commands
+ HCI_SET_EVT_MASK_CMD_OPCODE = 0x0C01,
+ HCI_RESET_CMD_OPCODE = 0x0C03,
+ HCI_SET_EVT_FILTER_CMD_OPCODE = 0x0C05,
+ HCI_FLUSH_CMD_OPCODE = 0x0C08,
+ HCI_RD_PIN_TYPE_CMD_OPCODE = 0x0C09,
+ HCI_WR_PIN_TYPE_CMD_OPCODE = 0x0C0A,
+ HCI_CREATE_NEW_UNIT_KEY_CMD_OPCODE = 0x0C0B,
+ HCI_RD_STORED_LK_CMD_OPCODE = 0x0C0D,
+ HCI_WR_STORED_LK_CMD_OPCODE = 0x0C11,
+ HCI_DEL_STORED_LK_CMD_OPCODE = 0x0C12,
+ HCI_WR_LOCAL_NAME_CMD_OPCODE = 0x0C13,
+ HCI_RD_LOCAL_NAME_CMD_OPCODE = 0x0C14,
+ HCI_RD_CON_ACCEPT_TO_CMD_OPCODE = 0x0C15,
+ HCI_WR_CON_ACCEPT_TO_CMD_OPCODE = 0x0C16,
+ HCI_RD_PAGE_TO_CMD_OPCODE = 0x0C17,
+ HCI_WR_PAGE_TO_CMD_OPCODE = 0x0C18,
+ HCI_RD_SCAN_EN_CMD_OPCODE = 0x0C19,
+ HCI_WR_SCAN_EN_CMD_OPCODE = 0x0C1A,
+ HCI_RD_PAGE_SCAN_ACT_CMD_OPCODE = 0x0C1B,
+ HCI_WR_PAGE_SCAN_ACT_CMD_OPCODE = 0x0C1C,
+ HCI_RD_INQ_SCAN_ACT_CMD_OPCODE = 0x0C1D,
+ HCI_WR_INQ_SCAN_ACT_CMD_OPCODE = 0x0C1E,
+ HCI_RD_AUTH_EN_CMD_OPCODE = 0x0C1F,
+ HCI_WR_AUTH_EN_CMD_OPCODE = 0x0C20,
+ HCI_RD_CLASS_OF_DEV_CMD_OPCODE = 0x0C23,
+ HCI_WR_CLASS_OF_DEV_CMD_OPCODE = 0x0C24,
+ HCI_RD_VOICE_STG_CMD_OPCODE = 0x0C25,
+ HCI_WR_VOICE_STG_CMD_OPCODE = 0x0C26,
+ HCI_RD_AUTO_FLUSH_TO_CMD_OPCODE = 0x0C27,
+ HCI_WR_AUTO_FLUSH_TO_CMD_OPCODE = 0x0C28,
+ HCI_RD_NB_BDCST_RETX_CMD_OPCODE = 0x0C29,
+ HCI_WR_NB_BDCST_RETX_CMD_OPCODE = 0x0C2A,
+ HCI_RD_HOLD_MODE_ACTIVITY_CMD_OPCODE = 0x0C2B,
+ HCI_WR_HOLD_MODE_ACTIVITY_CMD_OPCODE = 0x0C2C,
+ HCI_RD_TX_PWR_LVL_CMD_OPCODE = 0x0C2D,
+ HCI_RD_SYNC_FLOW_CTRL_EN_CMD_OPCODE = 0x0C2E,
+ HCI_WR_SYNC_FLOW_CTRL_EN_CMD_OPCODE = 0x0C2F,
+ HCI_SET_CTRL_TO_HOST_FLOW_CTRL_CMD_OPCODE = 0x0C31,
+ HCI_HOST_BUF_SIZE_CMD_OPCODE = 0x0C33,
+ HCI_HOST_NB_CMP_PKTS_CMD_OPCODE = 0x0C35,
+ HCI_RD_LINK_SUPV_TO_CMD_OPCODE = 0x0C36,
+ HCI_WR_LINK_SUPV_TO_CMD_OPCODE = 0x0C37,
+ HCI_RD_NB_SUPP_IAC_CMD_OPCODE = 0x0C38,
+ HCI_RD_CURR_IAC_LAP_CMD_OPCODE = 0x0C39,
+ HCI_WR_CURR_IAC_LAP_CMD_OPCODE = 0x0C3A,
+ HCI_SET_AFH_HOST_CH_CLASS_CMD_OPCODE = 0x0C3F,
+ HCI_RD_INQ_SCAN_TYPE_CMD_OPCODE = 0x0C42,
+ HCI_WR_INQ_SCAN_TYPE_CMD_OPCODE = 0x0C43,
+ HCI_RD_INQ_MODE_CMD_OPCODE = 0x0C44,
+ HCI_WR_INQ_MODE_CMD_OPCODE = 0x0C45,
+ HCI_RD_PAGE_SCAN_TYPE_CMD_OPCODE = 0x0C46,
+ HCI_WR_PAGE_SCAN_TYPE_CMD_OPCODE = 0x0C47,
+ HCI_RD_AFH_CH_ASSESS_MODE_CMD_OPCODE = 0x0C48,
+ HCI_WR_AFH_CH_ASSESS_MODE_CMD_OPCODE = 0x0C49,
+ HCI_RD_EXT_INQ_RSP_CMD_OPCODE = 0x0C51,
+ HCI_WR_EXT_INQ_RSP_CMD_OPCODE = 0x0C52,
+ HCI_REFRESH_ENC_KEY_CMD_OPCODE = 0x0C53,
+ HCI_RD_SP_MODE_CMD_OPCODE = 0x0C55,
+ HCI_WR_SP_MODE_CMD_OPCODE = 0x0C56,
+ HCI_RD_LOC_OOB_DATA_CMD_OPCODE = 0x0C57,
+ HCI_RD_INQ_RSP_TX_PWR_LVL_CMD_OPCODE = 0x0C58,
+ HCI_WR_INQ_TX_PWR_LVL_CMD_OPCODE = 0x0C59,
+ HCI_RD_DFT_ERR_DATA_REP_CMD_OPCODE = 0x0C5A,
+ HCI_WR_DFT_ERR_DATA_REP_CMD_OPCODE = 0x0C5B,
+ HCI_ENH_FLUSH_CMD_OPCODE = 0x0C5F,
+ HCI_SEND_KEYPRESS_NOTIF_CMD_OPCODE = 0x0C60,
+ HCI_SET_EVT_MASK_PAGE_2_CMD_OPCODE = 0x0C63,
+ HCI_RD_FLOW_CNTL_MODE_CMD_OPCODE = 0x0C66,
+ HCI_WR_FLOW_CNTL_MODE_CMD_OPCODE = 0x0C67,
+ HCI_RD_ENH_TX_PWR_LVL_CMD_OPCODE = 0x0C68,
+ HCI_RD_LE_HOST_SUPP_CMD_OPCODE = 0x0C6C,
+ HCI_WR_LE_HOST_SUPP_CMD_OPCODE = 0x0C6D,
+ HCI_SET_MWS_CHANNEL_PARAMS_CMD_OPCODE = 0x0C6E,
+ HCI_SET_EXTERNAL_FRAME_CONFIG_CMD_OPCODE = 0x0C6F,
+ HCI_SET_MWS_SIGNALING_CMD_OPCODE = 0x0C70,
+ HCI_SET_MWS_TRANSPORT_LAYER_CMD_OPCODE = 0x0C71,
+ HCI_SET_MWS_SCAN_FREQ_TABLE_CMD_OPCODE = 0x0C72,
+ HCI_SET_MWS_PATTERN_CONFIG_CMD_OPCODE = 0x0C73,
+ HCI_SET_RES_LT_ADDR_CMD_OPCODE = 0x0C74,
+ HCI_DEL_RES_LT_ADDR_CMD_OPCODE = 0x0C75,
+ HCI_SET_CON_SLV_BCST_DATA_CMD_OPCODE = 0x0C76,
+ HCI_RD_SYNC_TRAIN_PARAM_CMD_OPCODE = 0x0C77,
+ HCI_WR_SYNC_TRAIN_PARAM_CMD_OPCODE = 0x0C78,
+ HCI_RD_SEC_CON_HOST_SUPP_CMD_OPCODE = 0x0C79,
+ HCI_WR_SEC_CON_HOST_SUPP_CMD_OPCODE = 0x0C7A,
+ HCI_RD_AUTH_PAYL_TO_CMD_OPCODE = 0x0C7B,
+ HCI_WR_AUTH_PAYL_TO_CMD_OPCODE = 0x0C7C,
+ HCI_RD_LOC_OOB_EXT_DATA_CMD_OPCODE = 0x0C7D,
+ HCI_RD_EXT_PAGE_TO_CMD_OPCODE = 0x0C7E,
+ HCI_WR_EXT_PAGE_TO_CMD_OPCODE = 0x0C7F,
+ HCI_RD_EXT_INQ_LEN_CMD_OPCODE = 0x0C80,
+ HCI_WR_EXT_INQ_LEN_CMD_OPCODE = 0x0C81,
+
+ //Info Params
+ HCI_RD_LOCAL_VER_INFO_CMD_OPCODE = 0x1001,
+ HCI_RD_LOCAL_SUPP_CMDS_CMD_OPCODE = 0x1002,
+ HCI_RD_LOCAL_SUPP_FEATS_CMD_OPCODE = 0x1003,
+ HCI_RD_LOCAL_EXT_FEATS_CMD_OPCODE = 0x1004,
+ HCI_RD_BUFF_SIZE_CMD_OPCODE = 0x1005,
+ HCI_RD_BD_ADDR_CMD_OPCODE = 0x1009,
+ HCI_RD_LOCAL_SUPP_CODECS_CMD_OPCODE = 0x100B,
+
+ //Status Params
+ HCI_RD_FAIL_CONTACT_CNT_CMD_OPCODE = 0x1401,
+ HCI_RST_FAIL_CONTACT_CNT_CMD_OPCODE = 0x1402,
+ HCI_RD_LINK_QUAL_CMD_OPCODE = 0x1403,
+ HCI_RD_RSSI_CMD_OPCODE = 0x1405,
+ HCI_RD_AFH_CH_MAP_CMD_OPCODE = 0x1406,
+ HCI_RD_CLK_CMD_OPCODE = 0x1407,
+ HCI_RD_ENC_KEY_SIZE_CMD_OPCODE = 0x1408,
+ HCI_GET_MWS_TRANSPORT_LAYER_CONFIG_CMD_OPCODE = 0x140C,
+
+ //Testing Commands
+ HCI_RD_LOOPBACK_MODE_CMD_OPCODE = 0x1801,
+ HCI_WR_LOOPBACK_MODE_CMD_OPCODE = 0x1802,
+ HCI_EN_DUT_MODE_CMD_OPCODE = 0x1803,
+ HCI_WR_SP_DBG_MODE_CMD_OPCODE = 0x1804,
+ HCI_WR_SEC_CON_TEST_MODE_CMD_OPCODE = 0x180A,
+
+ /// LE Commands Opcodes
+ HCI_LE_SET_EVT_MASK_CMD_OPCODE = 0x2001,
+ HCI_LE_RD_BUFF_SIZE_CMD_OPCODE = 0x2002,
+ HCI_LE_RD_LOCAL_SUPP_FEATS_CMD_OPCODE = 0x2003,
+ HCI_LE_SET_RAND_ADDR_CMD_OPCODE = 0x2005,
+ HCI_LE_SET_ADV_PARAM_CMD_OPCODE = 0x2006,
+ HCI_LE_RD_ADV_CHNL_TX_PW_CMD_OPCODE = 0x2007,
+ HCI_LE_SET_ADV_DATA_CMD_OPCODE = 0x2008,
+ HCI_LE_SET_SCAN_RSP_DATA_CMD_OPCODE = 0x2009,
+ HCI_LE_SET_ADV_EN_CMD_OPCODE = 0x200A,
+ HCI_LE_SET_SCAN_PARAM_CMD_OPCODE = 0x200B,
+ HCI_LE_SET_SCAN_EN_CMD_OPCODE = 0x200C,
+ HCI_LE_CREATE_CON_CMD_OPCODE = 0x200D,
+ HCI_LE_CREATE_CON_CANCEL_CMD_OPCODE = 0x200E,
+ HCI_LE_RD_WLST_SIZE_CMD_OPCODE = 0x200F,
+ HCI_LE_CLEAR_WLST_CMD_OPCODE = 0x2010,
+ HCI_LE_ADD_DEV_TO_WLST_CMD_OPCODE = 0x2011,
+ HCI_LE_RMV_DEV_FROM_WLST_CMD_OPCODE = 0x2012,
+ HCI_LE_CON_UPDATE_CMD_OPCODE = 0x2013,
+ HCI_LE_SET_HOST_CH_CLASS_CMD_OPCODE = 0x2014,
+ HCI_LE_RD_CHNL_MAP_CMD_OPCODE = 0x2015,
+ HCI_LE_RD_REM_USED_FEATS_CMD_OPCODE = 0x2016,
+ HCI_LE_ENC_CMD_OPCODE = 0x2017,
+ HCI_LE_RAND_CMD_OPCODE = 0x2018,
+ HCI_LE_START_ENC_CMD_OPCODE = 0x2019,
+ HCI_LE_LTK_REQ_REPLY_CMD_OPCODE = 0x201A,
+ HCI_LE_LTK_REQ_NEG_REPLY_CMD_OPCODE = 0x201B,
+ HCI_LE_RD_SUPP_STATES_CMD_OPCODE = 0x201C,
+ HCI_LE_RX_TEST_CMD_OPCODE = 0x201D,
+ HCI_LE_TX_TEST_CMD_OPCODE = 0x201E,
+ HCI_LE_TEST_END_CMD_OPCODE = 0x201F,
+#if !(BLE_QUALIF)
+ HCI_LE_REM_CON_PARAM_REQ_REPLY_CMD_OPCODE = 0x2020,
+ HCI_LE_REM_CON_PARAM_REQ_NEG_REPLY_CMD_OPCODE = 0x2021,
+ HCI_LE_SET_DATA_LEN_CMD_OPCODE = 0x2022,
+ HCI_LE_RD_SUGGTED_DFT_DATA_LEN_CMD_OPCODE = 0x2023,
+ HCI_LE_WR_SUGGTED_DFT_DATA_LEN_CMD_OPCODE = 0x2024,
+ HCI_LE_RD_LOC_P256_PUB_KEY_CMD_OPCODE = 0x2025,
+ HCI_LE_GEN_DHKEY_CMD_OPCODE = 0x2026,
+ HCI_LE_ADD_DEV_TO_RSLV_LIST_CMD_OPCODE = 0x2027,
+ HCI_LE_RMV_DEV_FROM_RSLV_LIST_CMD_OPCODE = 0x2028,
+ HCI_LE_CLEAR_RSLV_LIST_CMD_OPCODE = 0x2029,
+ HCI_LE_RD_RSLV_LIST_SIZE_CMD_OPCODE = 0x202A,
+ HCI_LE_RD_PEER_RSLV_ADDR_CMD_OPCODE = 0x202B,
+ HCI_LE_RD_LOC_RSLV_ADDR_CMD_OPCODE = 0x202C,
+ HCI_LE_SET_ADDR_RESOL_EN_CMD_OPCODE = 0x202D,
+ HCI_LE_SET_RSLV_PRIV_ADDR_TO_CMD_OPCODE = 0x202E,
+ HCI_LE_RD_MAX_DATA_LEN_CMD_OPCODE = 0x202F,
+#endif
+
+ ///Debug commands - OGF = 0x3F (spec)
+ HCI_DBG_RD_MEM_CMD_OPCODE = 0xFC01,
+ HCI_DBG_WR_MEM_CMD_OPCODE = 0xFC02,
+ HCI_DBG_DEL_PAR_CMD_OPCODE = 0xFC03,
+ HCI_DBG_ID_FLASH_CMD_OPCODE = 0xFC05,
+ HCI_DBG_ER_FLASH_CMD_OPCODE = 0xFC06,
+ HCI_DBG_WR_FLASH_CMD_OPCODE = 0xFC07,
+ HCI_DBG_RD_FLASH_CMD_OPCODE = 0xFC08,
+ HCI_DBG_RD_PAR_CMD_OPCODE = 0xFC09,
+ HCI_DBG_WR_PAR_CMD_OPCODE = 0xFC0A,
+ HCI_DBG_WLAN_COEX_CMD_OPCODE = 0xFC0B,
+ HCI_DBG_WLAN_COEXTST_SCEN_CMD_OPCODE = 0xFC0D,
+ HCI_DBG_BT_SEND_LMP_CMD_OPCODE = 0xFC0E,
+ HCI_DBG_SET_LOCAL_CLOCK_CMD_OPCODE = 0xFC0F,
+ HCI_DBG_RD_KE_STATS_CMD_OPCODE = 0xFC10,
+ HCI_DBG_PLF_RESET_CMD_OPCODE = 0xFC11,
+ HCI_DBG_RD_MEM_INFO_CMD_OPCODE = 0xFC12,
+ HCI_DBG_HW_REG_RD_CMD_OPCODE = 0xFC30,
+ HCI_DBG_HW_REG_WR_CMD_OPCODE = 0xFC31,
+ HCI_DBG_SET_BD_ADDR_CMD_OPCODE = 0xFC32,
+ HCI_DBG_SET_TYPE_PUB_CMD_OPCODE = 0xFC33,
+ HCI_DBG_SET_TYPE_RAND_CMD_OPCODE = 0xFC34,
+ HCI_DBG_SET_CRC_CMD_OPCODE = 0xFC35,
+ HCI_DBG_LLCP_DISCARD_CMD_OPCODE = 0xFC36,
+ HCI_DBG_RESET_RX_CNT_CMD_OPCODE = 0xFC37,
+ HCI_DBG_RESET_TX_CNT_CMD_OPCODE = 0xFC38,
+ HCI_DBG_RF_REG_RD_CMD_OPCODE = 0xFC39,
+ HCI_DBG_RF_REG_WR_CMD_OPCODE = 0xFC3A,
+ HCI_DBG_SET_TX_PW_CMD_OPCODE = 0xFC3B,
+ HCI_DBG_RF_SWITCH_CLK_CMD_OPCODE = 0xFC3C,
+ HCI_DBG_RF_WR_DATA_TX_CMD_OPCODE = 0xFC3D,
+ HCI_DBG_RF_RD_DATA_RX_CMD_OPCODE = 0xFC3E,
+ HCI_DBG_RF_CNTL_TX_CMD_OPCODE = 0xFC3F,
+ HCI_DBG_RF_SYNC_P_CNTL_CMD_OPCODE = 0xFC40,
+ HCI_TESTER_SET_LE_PARAMS_CMD_OPCODE = 0xFC40,
+ HCI_DBG_WR_DLE_DFT_VALUE_CMD_OPCODE = 0xFC41,
+ HCI_DBG_BLE_TST_LLCP_PT_EN_CMD_OPCODE = 0xFC42,
+ HCI_DBG_BLE_TST_SEND_LLCP_CMD_OPCODE = 0xFC43,
+ HCI_VS_AUDIO_ALLOCATE_CMD_OPCODE = 0xFC50,
+ HCI_VS_AUDIO_CONFIGURE_CMD_OPCODE = 0xFC51,
+ HCI_VS_AUDIO_SET_MODE_CMD_OPCODE = 0xFC52,
+ HCI_VS_AUDIO_RESET_CMD_OPCODE = 0xFC53,
+ HCI_VS_AUDIO_SET_POINTER_CMD_OPCODE = 0xFC54,
+ HCI_VS_AUDIO_GET_BUFFER_RANGE_CMD_OPCODE = 0xFC55,
+
+ #if (RW_DEBUG && BT_EMB_PRESENT)
+ HCI_DBG_BT_DISCARD_LMP_EN_CMD_OPCODE = 0xFC44,
+ #endif //RW_DEBUG && BT_EMB_PRESENT
+
+ HCI_DBG_MWS_COEX_CMD_OPCODE = 0xFC45,
+ HCI_DBG_MWS_COEXTST_SCEN_CMD_OPCODE = 0xFC46,
+
+ #if CRYPTO_UT
+ HCI_DBG_TEST_CRYPTO_FUNC_CMD_OPCODE = 0xFC60,
+ #endif //CRYPTO_UT
+};
+
+/**************************************************************************************
+ ************** HCI EVENTS ****************
+ **************************************************************************************/
+
+///Event Codes
+enum hci_evt_code
+{
+ HCI_INQ_CMP_EVT_CODE = 0x01,
+ HCI_INQ_RES_EVT_CODE = 0x02,
+ HCI_CON_CMP_EVT_CODE = 0x03,
+ HCI_CON_REQ_EVT_CODE = 0x04,
+ HCI_DISC_CMP_EVT_CODE = 0x05,
+ HCI_AUTH_CMP_EVT_CODE = 0x06,
+ HCI_REM_NAME_REQ_CMP_EVT_CODE = 0x07,
+ HCI_ENC_CHG_EVT_CODE = 0x08,
+ HCI_CHG_CON_LK_CMP_EVT_CODE = 0x09,
+ HCI_MASTER_LK_CMP_EVT_CODE = 0x0A,
+ HCI_RD_REM_SUPP_FEATS_CMP_EVT_CODE = 0x0B,
+ HCI_RD_REM_VER_INFO_CMP_EVT_CODE = 0x0C,
+ HCI_QOS_SETUP_CMP_EVT_CODE = 0x0D,
+ HCI_CMD_CMP_EVT_CODE = 0x0E,
+ HCI_CMD_STATUS_EVT_CODE = 0x0F,
+ HCI_HW_ERR_EVT_CODE = 0x10,
+ HCI_FLUSH_OCCURRED_EVT_CODE = 0x11,
+ HCI_ROLE_CHG_EVT_CODE = 0x12,
+ HCI_NB_CMP_PKTS_EVT_CODE = 0x13,
+ HCI_MODE_CHG_EVT_CODE = 0x14,
+ HCI_RETURN_LINK_KEYS_EVT_CODE = 0x15,
+ HCI_PIN_CODE_REQ_EVT_CODE = 0x16,
+ HCI_LK_REQ_EVT_CODE = 0x17,
+ HCI_LK_NOTIF_EVT_CODE = 0x18,
+ HCI_DATA_BUF_OVFLW_EVT_CODE = 0x1A,
+ HCI_MAX_SLOT_CHG_EVT_CODE = 0x1B,
+ HCI_RD_CLK_OFF_CMP_EVT_CODE = 0x1C,
+ HCI_CON_PKT_TYPE_CHG_EVT_CODE = 0x1D,
+ HCI_QOS_VIOL_EVT_CODE = 0x1E,
+ HCI_PAGE_SCAN_REPET_MODE_CHG_EVT_CODE = 0x20,
+ HCI_FLOW_SPEC_CMP_EVT_CODE = 0x21,
+ HCI_INQ_RES_WITH_RSSI_EVT_CODE = 0x22,
+ HCI_RD_REM_EXT_FEATS_CMP_EVT_CODE = 0x23,
+ HCI_SYNC_CON_CMP_EVT_CODE = 0x2C,
+ HCI_SYNC_CON_CHG_EVT_CODE = 0x2D,
+ HCI_SNIFF_SUB_EVT_CODE = 0x2E,
+ HCI_EXT_INQ_RES_EVT_CODE = 0x2F,
+ HCI_ENC_KEY_REFRESH_CMP_EVT_CODE = 0x30,
+ HCI_IO_CAP_REQ_EVT_CODE = 0x31,
+ HCI_IO_CAP_RSP_EVT_CODE = 0x32,
+ HCI_USER_CFM_REQ_EVT_CODE = 0x33,
+ HCI_USER_PASSKEY_REQ_EVT_CODE = 0x34,
+ HCI_REM_OOB_DATA_REQ_EVT_CODE = 0x35,
+ HCI_SP_CMP_EVT_CODE = 0x36,
+ HCI_LINK_SUPV_TO_CHG_EVT_CODE = 0x38,
+ HCI_ENH_FLUSH_CMP_EVT_CODE = 0x39,
+ HCI_USER_PASSKEY_NOTIF_EVT_CODE = 0x3B,
+ HCI_KEYPRESS_NOTIF_EVT_CODE = 0x3C,
+ HCI_REM_HOST_SUPP_FEATS_NOTIF_EVT_CODE = 0x3D,
+ HCI_LE_META_EVT_CODE = 0x3E,
+ HCI_MAX_EVT_MSK_PAGE_1_CODE = 0x40,
+ HCI_SYNC_TRAIN_CMP_EVT_CODE = 0x4F,
+ HCI_SYNC_TRAIN_REC_EVT_CODE = 0x50,
+ HCI_CON_SLV_BCST_REC_EVT_CODE = 0x51,
+ HCI_CON_SLV_BCST_TO_EVT_CODE = 0x52,
+ HCI_TRUNC_PAGE_CMP_EVT_CODE = 0x53,
+ HCI_SLV_PAGE_RSP_TO_EVT_CODE = 0x54,
+ HCI_CON_SLV_BCST_CH_MAP_CHG_EVT_CODE = 0x55,
+ HCI_AUTH_PAYL_TO_EXP_EVT_CODE = 0x57,
+ HCI_MAX_EVT_MSK_PAGE_2_CODE = 0x58,
+ HCI_DBG_META_EVT_CODE = 0xFF,
+
+ /// LE Events Subcodes
+ HCI_LE_CON_CMP_EVT_SUBCODE = 0x01,
+ HCI_LE_ADV_REPORT_EVT_SUBCODE = 0x02,
+ HCI_LE_CON_UPDATE_CMP_EVT_SUBCODE = 0x03,
+ HCI_LE_RD_REM_USED_FEATS_CMP_EVT_SUBCODE = 0x04,
+ HCI_LE_LTK_REQUEST_EVT_SUBCODE = 0x05,
+ HCI_LE_REM_CON_PARAM_REQ_EVT_SUBCODE = 0x06,
+ HCI_LE_DATA_LEN_CHG_EVT_SUBCODE = 0x07,
+ HCI_LE_RD_LOC_P256_PUB_KEY_CMP_EVT_SUBCODE = 0x08,
+ HCI_LE_GEN_DHKEY_CMP_EVT_SUBCODE = 0x09,
+ HCI_LE_ENH_CON_CMP_EVT_SUBCODE = 0x0A,
+ HCI_LE_DIR_ADV_REP_EVT_SUBCODE = 0x0B,
+
+ /// DBG Events Subcodes
+ #if (BLE_EMB_PRESENT && BLE_TESTER)
+ HCI_DBG_BLE_TST_LLCP_RECV_EVT_SUBCODE = 0x01,
+ #endif // (BLE_EMB_PRESENT && BLE_TESTER)
+ #if (RW_DEBUG)
+ HCI_DBG_ASSERT_ERR_EVT_SUBCODE = 0x02,
+ #endif //(RW_DEBUG)
+};
+
+/// Event mask page enum
+enum hci_evt_mask_page
+{
+ /// page 0
+ HCI_PAGE_0,
+ /// page 1
+ HCI_PAGE_1,
+ /// page 2
+ HCI_PAGE_2,
+ /// Default
+ HCI_PAGE_DFT
+};
+/// HCI ACL data RX packet structure
+struct hci_acl_data_rx
+{
+ /// connection handle
+ uint16_t conhdl;
+ /// broadcast and packet boundary flag
+ uint8_t pb_bc_flag;
+ /// length of the data
+ uint16_t length;
+
+ #if (BLE_EMB_PRESENT)
+ /// Handle of the descriptor containing RX Data
+ uint8_t rx_hdl;
+ #else// (BLE_HOST_PRESENT)
+ /// Pointer to the data buffer
+ uint8_t* buffer;
+ #endif // (BLE_EMB_PRESENT) / (BLE_HOST_PRESENT)
+};
+
+/// HCI ACL data TX packet structure
+struct hci_acl_data_tx
+{
+ /// connection handle
+ uint16_t conhdl;
+ /// broadcast and packet boundary flag
+ uint8_t pb_bc_flag;
+ /// length of the data
+ uint16_t length;
+ #if (BLE_EMB_PRESENT)
+ /// Pointer to the first descriptor containing RX Data
+ struct em_buf_node *buf;
+ #else // (BLE_HOST_PRESENT)
+ /// Pointer to the data buffer
+ uint8_t* buffer;
+ #endif // (BLE_EMB_PRESENT) / (BLE_HOST_PRESENT)
+};
+
+#if (BT_EMB_PRESENT)
+/// HCI ACL data packet structure
+struct hci_bt_acl_data_tx
+{
+ /// Buffer element
+ struct bt_em_acl_buf_elt* buf_elt;
+};
+
+/// HCI ACL data Rx packet structure
+struct hci_bt_acl_data_rx
+{
+ /// EM buffer pointer
+ uint16_t buf_ptr;
+ /// Data length + Data Flags (PBF + BF)
+ uint16_t data_len_flags;
+};
+
+/// HCI Synchronous data packet structure
+struct hci_bt_sync_data_tx
+{
+ /// Buffer element
+ struct bt_em_sync_buf_elt* buf_elt;
+};
+
+/// HCI Synchronous data Rx packet structure
+struct hci_bt_sync_data_rx
+{
+ /// EM buffer pointer
+ uint16_t buf_ptr;
+ /// Data length
+ uint8_t data_len;
+ /// Packet status flag
+ uint8_t packet_status_flag;
+ /// Synchronous link identifier
+ uint8_t sync_link_id;
+};
+#endif // (BT_EMB_PRESENT)
+
+
+/*
+ * HCI COMMANDS PARAMETERS (to classify)
+ ****************************************************************************************
+ */
+
+/// HCI basic command structure with connection handle
+struct hci_basic_conhdl_cmd
+{
+ /// connection handle
+ uint16_t conhdl;
+};
+
+/// HCI basic command structure with BD address
+struct hci_basic_bd_addr_cmd
+{
+ ///BdAddr
+ struct bd_addr bd_addr;
+};
+
+/// HCI Accept connection request command structure
+struct hci_accept_con_req_cmd
+{
+ ///BdAddr
+ struct bd_addr bd_addr;
+ ///Page Scan Repetition Mode
+ uint8_t role;
+};
+
+/// HCI Accept synchronous connection request command structure
+struct hci_accept_sync_con_req_cmd
+{
+ ///BdAddr
+ struct bd_addr bd_addr;
+ ///Transmit bandwidth
+ uint32_t tx_bw;
+ ///Receive bandwidth
+ uint32_t rx_bw;
+ ///Max latency
+ uint16_t max_lat;
+ ///Voice settings
+ uint16_t vx_set;
+ ///Retransmission effort
+ uint8_t retx_eff;
+ ///Packet type
+ uint16_t pkt_type ;
+};
+
+/// HCI Enhanced Accept synchronous connection request command structure
+struct hci_enh_accept_sync_con_cmd
+{
+
+ struct bd_addr bd_addr; // BD address
+ uint32_t tx_bw; // Transmit Bandwidth (in B/sec)
+ uint32_t rx_bw; // Receive Bandwidth (in B/sec)
+ uint8_t tx_cod_fmt[5]; // Transmit Coding Format
+ uint8_t rx_cod_fmt[5]; // Receive Coding Format
+ uint16_t tx_cod_fr_sz; // Transmit Codec Frame Size (in B)
+ uint16_t rx_cod_fr_sz; // Receive Codec Frame Size (in B)
+ uint32_t in_bw; // Input Bandwidth (in B/sec)
+ uint32_t out_bw; // Output Bandwidth (in B/sec)
+ uint8_t in_cod_fmt[5]; // Input Coding Format
+ uint8_t out_cod_fmt[5]; // Output Coding Format
+ uint16_t in_cod_data_sz; // Input Coded Data Size (in bits)
+ uint16_t out_cod_data_sz; // Output Coded Data Size (in bits)
+ uint8_t in_data_fmt; // Input PCM Data Format
+ uint8_t out_data_fmt; // Output PCM Data Format
+ uint8_t in_msb_pos; // Input PCM Sample Payload MSB Position (in bits)
+ uint8_t out_msb_pos; // Output PCM Sample Payload MSB Position (in bits)
+ uint8_t in_data_path; // Input Data Path
+ uint8_t out_data_path; // Output Data Path
+ uint8_t in_tr_unit_sz; // Input Transport Unit Size (in bits)
+ uint8_t out_tr_unit_sz; // Output Transport Unit Size (in bits)
+ uint16_t max_lat; // Max Latency (in ms)
+ uint16_t packet_type; // Packet Type
+ uint8_t retx_eff; // Retransmission Effort
+
+
+};
+
+/// HCI reject connection request command structure
+struct hci_reject_con_req_cmd
+{
+ ///BdAddr
+ struct bd_addr bd_addr;
+ ///Reason
+ uint8_t reason;
+};
+
+/// HCI reject synchronous connection request command structure
+struct hci_reject_sync_con_req_cmd
+{
+ ///BdAddr
+ struct bd_addr bd_addr;
+ ///Reason
+ uint8_t reason;
+};
+
+/// HCI link key request reply command structure
+struct hci_lk_req_reply_cmd
+{
+ ///BdAddr
+ struct bd_addr bd_addr;
+ ///Key
+ struct ltk key;
+};
+
+/// HCI link key request reply command structure
+struct hci_pin_code_req_reply_cmd
+{
+ ///BdAddr
+ struct bd_addr bd_addr;
+ ///Pin code length
+ uint8_t pin_len;
+ ///Key
+ struct pin_code pin;
+};
+
+/// HCI switch role command structure
+struct hci_switch_role_cmd
+{
+ ///BdAddr
+ struct bd_addr bd_addr;
+ ///Read all flag
+ uint8_t role;
+};
+
+/// HCI flow specification command parameters structure
+struct hci_flow_spec_cmd
+{
+ ///Connection handle
+ uint16_t conhdl;
+ ///Flags
+ uint8_t flags;
+ ///Flow direction
+ uint8_t flow_dir;
+ ///Service type
+ uint8_t serv_type;
+ ///Token rate
+ uint32_t tk_rate;
+ ///Token buffer size
+ uint32_t tk_buf_sz;
+ ///Peak bandwidth
+ uint32_t pk_bw;
+ ///Access latency
+ uint32_t acc_lat;
+};
+
+/// HCI enhanced flush command parameters structure
+struct hci_enh_flush_cmd
+{
+ ///Connection handle
+ uint16_t conhdl;
+ ///Packet Type
+ uint8_t pkt_type;
+};
+
+/// HCI command complete event structure for the read auto flush TO command
+struct hci_rd_auto_flush_to_cmd_cmp_evt
+{
+ ///Status for command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ ///Flush timeout
+ uint16_t flush_to;
+};
+
+/// HCI write flush timeout command parameters structure
+struct hci_wr_auto_flush_to_cmd
+{
+ ///Connection handle
+ uint16_t conhdl;
+ ///Flush timeout
+ uint16_t flush_to;
+};
+
+/// HCI change connection packet type command parameters structure
+struct hci_chg_con_pkt_type_cmd
+{
+ ///Connection handle
+ uint16_t conhdl;
+ ///Packet type
+ uint16_t pkt_type;
+};
+
+/// HCI read link policy settings command parameters structure
+struct hci_rd_link_pol_stg_cmd_cmp_evt
+{
+ ///Status for command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ ///Link policy
+ uint16_t lnk_policy;
+};
+
+/// HCI read link policy settings command parameters structure
+struct hci_wr_link_pol_stg_cmd
+{
+ ///Connection handle
+ uint16_t conhdl;
+ ///Link policy
+ uint16_t lnk_policy;
+};
+
+/// HCI sniff mode request command parameters structure
+struct hci_sniff_mode_cmd
+{
+ ///Connection handle
+ uint16_t conhdl;
+ ///Sniff max interval
+ uint16_t max_int;
+ ///Sniff min interval
+ uint16_t min_int;
+ ///Sniff attempt
+ uint16_t attempt;
+ ///Sniff timeout
+ uint16_t timeout;
+};
+
+/// HCI sniff subrating mode request command parameters structure
+struct hci_sniff_sub_cmd
+{
+ ///Connection handle
+ uint16_t conhdl;
+ ///Sniff max latency
+ uint16_t max_lat;
+ ///Minimun remote TO
+ uint16_t min_rem_to;
+ ///Minimun local TO
+ uint16_t min_loc_to;
+};
+
+/// HCI role discovery complete event parameters structure
+struct hci_role_discovery_cmd_cmp_evt
+{
+ ///Status for command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ ///Role
+ uint8_t role;
+
+};
+
+/// HCI read failed contact counter command parameters structure
+struct hci_rd_fail_contact_cnt_cmd_cmp_evt
+{
+ ///Status for command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ ///Fail contact counter
+ uint16_t fail_cnt;
+};
+
+/// HCI read link quality complete event parameters structure
+struct hci_rd_link_qual_cmd_cmp_evt
+{
+ ///Status for command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ ///Quality type
+ uint8_t quality;
+};
+
+/// HCI read afh channel map complete event parameters structure
+struct hci_rd_afh_ch_map_cmd_cmp_evt
+{
+ ///Status for command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ /// AFH mode
+ uint8_t afh_mode;
+ /// AFH channel map
+ struct chnl_map afh_map;
+};
+
+/// HCI read lmp handle complete event parameters structure
+struct hci_rd_lmp_hdl_cmd_cmp_evt
+{
+ ///Status for command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ ///lmp handle
+ uint8_t lmp_hdl;
+ ///rsvd
+ uint32_t rsvd;
+};
+
+/// HCI read remote extended features command parameters structure
+struct hci_rd_rem_ext_feats_cmd
+{
+ ///Connection handle
+ uint16_t conhdl;
+ ///page number
+ uint8_t pg_nb;
+};
+
+/// HCI read encryption key size complete event parameters structure
+struct hci_rd_enc_key_size_cmd_cmp_evt
+{
+ ///Status for command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ ///Key size
+ uint8_t key_sz;
+};
+
+/// HCI read enhanced transmit power command parameters structure
+struct hci_rd_enh_tx_pwr_lvl_cmd
+{
+ ///Connection handle
+ uint16_t conhdl;
+ ///Type
+ uint8_t type;
+};
+
+/// HCI read enhanced transmit power complete event parameters structure
+struct hci_rd_enh_tx_pwr_lvl_cmd_cmp_evt
+{
+ ///Status for command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ ///Transmit power GFSK
+ uint8_t pw_gfsk;
+ ///Transmit power DQPSK
+ uint8_t pw_dqpsk;
+ ///Transmit power 8DPSK
+ uint8_t pw_8dpsk;
+};
+
+
+/*
+ * HCI LINK CONTROL COMMANDS PARAMETERS
+ ****************************************************************************************
+ */
+
+/// Format of the message of the Group: LINK_CONTROL_COMMANDS
+/// HCI Inquiry command parameters structure
+struct hci_inq_cmd
+{
+ ///Lap
+ struct lap lap;
+ ///Inquiry Length
+ uint8_t inq_len;
+ ///Number of response
+ uint8_t nb_rsp;
+};
+struct hci_per_inq_mode_cmd
+{
+ ///Maximum period length
+ uint16_t max_per_len;
+ ///Minimum period length
+ uint16_t min_per_len;
+ ///lap
+ struct lap lap;
+ ///Inquiry length
+ uint8_t inq_len;
+ ///Number of response
+ uint8_t nb_rsp;
+};
+struct hci_create_con_cmd
+{
+ /// BdAddr
+ struct bd_addr bd_addr;
+ /// Packet Type
+ uint16_t pkt_type;
+ /// Page Scan Repetition Mode
+ uint8_t page_scan_rep_mode;
+ /// Reserved
+ uint8_t rsvd;
+ /**
+ * Clock Offset
+ *
+ * Bits 14-0 : Bits 16-2 of CLKNslave-CLK
+ * Bit 15 : Clock_Offset_Valid_Flag
+ * Invalid Clock Offset = 0
+ * Valid Clock Offset = 1
+ */
+ uint16_t clk_off;
+ /// Allow Switch
+ uint8_t switch_en;
+};
+
+/// HCI disconnect command structure
+struct hci_disconnect_cmd
+{
+ /// connection handle
+ uint16_t conhdl;
+ /// reason
+ uint8_t reason;
+};
+
+/// HCI master link key command structure
+struct hci_master_lk_cmd
+{
+ ///Key flag
+ uint8_t key_flag;
+};
+
+/// HCI authentication request command parameters structure
+struct hci_set_con_enc_cmd
+{
+ ///Connection handle
+ uint16_t conhdl;
+ ///Encryption mode
+ uint8_t enc_en;
+};
+
+struct hci_rem_name_req_cmd
+{
+ ///BdAddr
+ struct bd_addr bd_addr;
+ ///Page Scan Repetition Mode
+ uint8_t page_scan_rep_mode;
+ ///Reserved
+ uint8_t rsvd;
+ /**
+ * Clock Offset
+ *
+ * Bits 14-0 : Bits 16-2 of CLKNslave-CLK
+ * Bit 15 : Clock_Offset_Valid_Flag
+ * Invalid Clock Offset = 0
+ * Valid Clock Offset = 1
+ */
+ uint16_t clk_off;
+};
+
+/// HCI remote name request complete event structure
+struct hci_rem_name_req_cmp_evt
+{
+ /// Status
+ uint8_t status;
+ /// BD Addr
+ struct bd_addr bd_addr;
+ /// Name
+ struct device_name name;
+};
+
+/// HCI setup synchronous connection command structure
+struct hci_setup_sync_con_cmd
+{
+ ///Connection handle
+ uint16_t conhdl;
+ ///Transmit bandwidth
+ uint32_t tx_bw;
+ ///Receive bandwidth
+ uint32_t rx_bw;
+ ///Max latency
+ uint16_t max_lat;
+ ///Voice setting
+ uint16_t vx_set;
+ ///Retransmission effort
+ uint8_t retx_eff;
+ ///Packet type
+ uint16_t pkt_type;
+};
+
+/// HCI setup synchronous connection command structure
+struct hci_enh_setup_sync_con_cmd
+{
+ uint16_t conhdl; // Connection Handle
+ uint32_t tx_bw; // Transmit Bandwidth (in B/sec)
+ uint32_t rx_bw; // Receive Bandwidth (in B/sec)
+ uint8_t tx_cod_fmt[5]; // Transmit Coding Format
+ uint8_t rx_cod_fmt[5]; // Receive Coding Format
+ uint16_t tx_cod_fr_sz; // Transmit Codec Frame Size (in B)
+ uint16_t rx_cod_fr_sz; // Receive Codec Frame Size (in B)
+ uint32_t in_bw; // Input Bandwidth (in B/sec)
+ uint32_t out_bw; // Output Bandwidth (in B/sec)
+ uint8_t in_cod_fmt[5]; // Input Coding Format
+ uint8_t out_cod_fmt[5]; // Output Coding Format
+ uint16_t in_cod_data_sz; // Input Coded Data Size (in bits)
+ uint16_t out_cod_data_sz; // Output Coded Data Size (in bits)
+ uint8_t in_data_fmt; // Input PCM Data Format
+ uint8_t out_data_fmt; // Output PCM Data Format
+ uint8_t in_msb_pos; // Input PCM Sample Payload MSB Position (in bits)
+ uint8_t out_msb_pos; // Output PCM Sample Payload MSB Position (in bits)
+ uint8_t in_data_path; // Input Data Path
+ uint8_t out_data_path; // Output Data Path
+ uint8_t in_tr_unit_sz; // Input Transport Unit Size (in bits)
+ uint8_t out_tr_unit_sz; // Output Transport Unit Size (in bits)
+ uint16_t max_lat; // Max Latency (in ms)
+ uint16_t packet_type; // Packet Type
+ uint8_t retx_eff; // Retransmission Effort
+};
+
+/// HCI io capability request reply command structure
+struct hci_io_cap_req_reply_cmd
+{
+ ///BdAddr
+ struct bd_addr bd_addr;
+ ///IO capability
+ uint8_t io_capa;
+ ///OOB data present
+ uint8_t oob_data_pres;
+ ///Authentication requirements
+ uint8_t auth_req;
+
+};
+
+/// HCI io capability request negative reply command structure
+struct hci_io_cap_req_neg_reply_cmd
+{
+ ///BdAddr
+ struct bd_addr bd_addr;
+ ///Reason
+ uint8_t reason;
+};
+
+/// HCI user pass key request reply command structure
+struct hci_user_passkey_req_reply_cmd
+{
+ ///BdAddr
+ struct bd_addr bd_addr;
+ ///Numeric value
+ uint32_t num_val;
+};
+
+/// HCI remote oob data request reply command structure
+struct hci_rem_oob_data_req_reply_cmd
+{
+ ///BdAddr
+ struct bd_addr bd_addr;
+ ///hash part
+ struct hash oob_c;
+ ///random part
+ struct randomizer oob_r;
+};
+
+/// HCI send key press notification command structure
+struct hci_send_keypress_notif_cmd
+{
+ ///BdAddr
+ struct bd_addr bd_addr;
+ ///Notification type
+ uint8_t notif_type;
+};
+
+/// HCI truncated page command structure
+struct hci_trunc_page_cmd
+{
+ ///BdAddr
+ struct bd_addr bd_addr;
+ /// Page Scan Repetition Mode
+ uint8_t page_scan_rep_mode;
+ /**
+ * Clock Offset
+ *
+ * Bits 14-0 : Bits 16-2 of CLKNslave-CLK
+ * Bit 15 : Clock_Offset_Valid_Flag
+ * Invalid Clock Offset = 0
+ * Valid Clock Offset = 1
+ */
+ uint16_t clk_off;
+};
+
+/// HCI truncated page cancel command structure
+struct hci_trunc_page_can_cmd
+{
+ ///BdAddr
+ struct bd_addr bd_addr;
+};
+
+/// HCI set connectionless slave broadcast command structure
+struct hci_set_con_slv_bcst_cmd
+{
+ /// Enable
+ uint8_t enable;
+ /// LT_ADDR
+ uint8_t lt_addr;
+ /// LPO_Allowed
+ uint8_t lpo_allowed;
+ /// Packet_Type
+ uint16_t packet_type;
+ /// Interval_Min (in slots)
+ uint16_t interval_min;
+ /// Interval_Max (in slots)
+ uint16_t interval_max;
+ /// CSB_supervisionTO (in slots)
+ uint16_t csb_supv_to;
+};
+
+/// HCI set connectionless slave broadcast command complete event structure
+struct hci_set_con_slv_bcst_cmd_cmp_evt
+{
+ /// Status
+ uint8_t status;
+ /// LT_ADDR
+ uint8_t lt_addr;
+ /// Interval (in slots)
+ uint16_t interval;
+};
+
+/// HCI set connectionless slave broadcast receive command structure
+struct hci_set_con_slv_bcst_rec_cmd
+{
+ /// Enable
+ uint8_t enable;
+ /// BD_ADDR
+ struct bd_addr bd_addr;
+ /// LT_ADDR
+ uint8_t lt_addr;
+ /// Interval (in slots)
+ uint16_t interval;
+ /// Clock_Offset (28 bits) - (CLKNslave – CLK) modulo 2^28
+ uint32_t clock_offset;
+ /// Next_Connectionless_Slave_Broadcast_Clock (28 bits)
+ uint32_t next_csb_clock;
+ /// CSB_supervisionTO (in slots)
+ uint16_t csb_supv_to;
+ /// Remote_Timing_Accuracy (in ppm)
+ uint8_t remote_timing_accuracy;
+ /// Skip
+ uint8_t skip;
+ /// Packet_Type
+ uint16_t packet_type;
+ /// AFH_Channel_Map
+ struct chnl_map afh_ch_map;
+};
+
+/// HCI set connectionless slave broadcast receive command complete event structure
+struct hci_set_con_slv_bcst_rec_cmd_cmp_evt
+{
+ /// Status
+ uint8_t status;
+ /// BD_ADDR
+ struct bd_addr bd_addr;
+ /// LT_ADDR
+ uint8_t lt_addr;
+};
+
+/// HCI Receive Synchronization Train command structure
+struct hci_rec_sync_train_cmd
+{
+ /// BD_ADDR
+ struct bd_addr bd_addr;
+ /// Synchronization_scanTO (in slots)
+ uint16_t sync_scan_to;
+ /// Sync_Scan_Window (in slots)
+ uint16_t sync_scan_win;
+ /// Sync_Scan_Interval (in slots)
+ uint16_t sync_scan_int;
+};
+
+/// HCI remote oob extended data request reply command structure
+struct hci_rem_oob_ext_data_req_reply_cmd
+{
+ ///BdAddr
+ struct bd_addr bd_addr;
+ ///hash part
+ struct hash oob_c_192;
+ ///random part
+ struct randomizer oob_r_192;
+ ///hash part
+ struct hash oob_c_256;
+ ///random part
+ struct randomizer oob_r_256;
+};
+
+
+struct hci_le_generate_dh_key_cmd
+{
+ uint8_t public_key[64];
+};
+/*
+ * HCI LINK POLICY COMMANDS PARAMETERS
+ ****************************************************************************************
+ */
+
+/// HCI setup quality of service command structure
+struct hci_qos_setup_cmd
+{
+ ///Connection handle
+ uint16_t conhdl;
+ ///Flags
+ uint8_t flags;
+ ///Service type
+ uint8_t serv_type;
+ ///Token rate
+ uint32_t tok_rate;
+ ///Peak bandwidth
+ uint32_t pk_bw;
+ ///Latency
+ uint32_t lat;
+ ///Delay variation
+ uint32_t del_var;
+};
+
+/// HCI command complete event structure for read default link policy command structure
+struct hci_rd_dft_link_pol_stg_cmd_cmp_evt
+{
+ ///Status of the command reception
+ uint8_t status;
+ ///Link policy
+ uint16_t link_pol_stg;
+};
+
+struct hci_wr_dft_link_pol_stg_cmd
+{
+ ///Link policy
+ uint16_t link_pol_stg;
+};
+
+/*
+ * HCI CONTROL & BASEBAND COMMANDS PARAMETERS
+ ****************************************************************************************
+ */
+
+/// HCI set event mask command structure
+struct hci_set_evt_mask_cmd
+{
+ ///Event Mask
+ struct evt_mask event_mask;
+};
+
+/// HCI set event filter command structure
+struct hci_set_evt_filter_cmd
+{
+ /// Filter type
+ uint8_t filter_type;
+
+ /// Filters
+ union hci_filter
+ {
+ uint8_t clear_all_filter_reserved;
+
+ /// Inquiry Result Filter
+ struct inq_res_filter
+ {
+ /// Filter Condition type
+ uint8_t cond_type;
+
+ /// Filter conditions
+ union hci_inq_filter_cond
+ {
+ /// Reserved value (Inquiry Result Filter - condition type 0x00 has no condition)
+ uint8_t cond_0_reserved;
+
+ /// Inquiry Result Filter Condition - condition type 0x01
+ struct inq_res_filter_cond_1
+ {
+ /// Class_of_Device
+ struct devclass class_of_dev;
+ /// Class_of_Device_Mask
+ struct devclass class_of_dev_msk;
+ } cond_1;
+
+ /// Inquiry Result Filter Condition - condition type 0x02
+ struct inq_res_filter_cond_2
+ {
+ /// BD Address
+ struct bd_addr bd_addr;
+ } cond_2;
+ } cond;
+ } inq_res;
+
+ /// Connection Setup Filter
+ struct con_set_filter
+ {
+ /// Filter Condition type
+ uint8_t cond_type;
+
+ /// Filter conditions
+ union hci_con_filter_cond
+ {
+ /// Connection Setup Filter Condition - condition type 0x00
+ struct con_set_filter_cond_0
+ {
+ /// Auto_Accept_Flag
+ uint8_t auto_accept;
+ } cond_0;
+
+ /// Connection Setup Filter Condition - condition type 0x01
+ struct con_set_filter_cond_1
+ {
+ /// Class_of_Device
+ struct devclass class_of_dev;
+ /// Class_of_Device_Mask
+ struct devclass class_of_dev_msk;
+ /// Auto_Accept_Flag
+ uint8_t auto_accept;
+ } cond_1;
+
+ /// Connection Setup Filter Condition - condition type 0x02
+ struct con_set_filter_cond_2
+ {
+ /// BD Address
+ struct bd_addr bd_addr;
+ /// Auto_Accept_Flag
+ uint8_t auto_accept;
+ } cond_2;
+ } cond;
+
+ } con_set;
+
+ } filter;
+};
+
+/// HCI command completed event structure for the flush command
+struct hci_flush_cmd_cmp_evt
+{
+ ///Status for command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+};
+
+/// HCI command complete event structure for the Read pin type command
+struct hci_rd_pin_type_cmd_cmp_evt
+{
+ ///Status of the command
+ uint8_t status;
+ ///PIN type
+ uint8_t pin_type;
+};
+
+struct hci_wr_pin_type_cmd
+{
+ ///PIN type
+ uint8_t pin_type;
+};
+
+struct hci_rd_stored_lk_cmd
+{
+ ///BdAddr
+ struct bd_addr bd_addr;
+ ///Read all flag
+ uint8_t rd_all_flag;
+};
+
+/// HCI command complete event structure for read stored link key command
+struct hci_rd_stored_lk_cmd_cmp_evt
+{
+ /// Status of the command reception
+ uint8_t status;
+ ///Maximum number of key
+ uint16_t num_key_max;
+ ///Read number of key
+ uint16_t num_key_rd;
+};
+
+#if BT_EMB_PRESENT
+struct hci_wr_stored_lk_cmd
+{
+ /// Number of key to write
+ uint8_t num_key_wr;
+
+ /// BD Address + Key table
+ struct bd_addr_plus_key link_keys[HCI_MAX_CMD_PARAM_SIZE / sizeof(struct bd_addr_plus_key)];
+};
+#endif //BT_EMB_PRESENT
+
+/// HCI command complete event structure for write stored link key command
+struct hci_wr_stored_lk_cmd_cmp_evt
+{
+ /// Status of the command reception
+ uint8_t status;
+ ///number of key written
+ uint8_t num_key_wr;
+};
+
+struct hci_del_stored_lk_cmd
+{
+ ///BdAddr
+ struct bd_addr bd_addr;
+ ///Delete all flag
+ uint8_t del_all_flag;
+};
+
+/// HCI command complete event structure for delete stored link key command
+struct hci_del_stored_lk_cmd_cmp_evt
+{
+ /// Status of the command reception
+ uint8_t status;
+ ///Read number of key
+ uint16_t num_key_del;
+};
+
+struct hci_wr_local_name_cmd
+{
+ ///Name
+ struct device_name name;
+};
+
+/// HCI command complete event structure for the read local name command
+struct hci_rd_local_name_cmd_cmp_evt
+{
+ ///Status of the command
+ uint8_t status;
+ ///Name
+ uint8_t name[BD_NAME_SIZE];
+};
+
+/// HCI command complete event structure for the Read connection accept to command
+struct hci_rd_con_accept_to_cmd_cmp_evt
+{
+ ///Status of the command
+ uint8_t status;
+ /// Connection accept timeout (in slots)
+ uint16_t con_acc_to;
+};
+
+struct hci_wr_con_accept_to_cmd
+{
+ /// Connection accept timeout (in slots)
+ uint16_t con_acc_to;
+};
+
+/// HCI command complete event structure for the Read page to command
+struct hci_rd_page_to_cmd_cmp_evt
+{
+ ///Status of the command
+ uint8_t status;
+ /// Page timeout (in slots)
+ uint16_t page_to;
+};
+
+struct hci_wr_page_to_cmd
+{
+ /// Page timeout (in slots)
+ uint16_t page_to;
+};
+
+/// HCI command complete event structure for the Read scan enable command
+struct hci_rd_scan_en_cmd_cmp_evt
+{
+ ///Status of the command
+ uint8_t status;
+ ///Status of the scan enable
+ uint8_t scan_en;
+};
+
+struct hci_wr_scan_en_cmd
+{
+ ///Status of the scan enable
+ uint8_t scan_en;
+};
+
+/// HCI command complete event structure for the Read scan activity command
+struct hci_rd_page_scan_act_cmd_cmp_evt
+{
+ ///Status of the command
+ uint8_t status;
+ /// Page scan interval (in slots)
+ uint16_t page_scan_intv;
+ /// Page scan window (in slots)
+ uint16_t page_scan_win;
+};
+
+struct hci_wr_page_scan_act_cmd
+{
+ /// Page scan interval (in slots)
+ uint16_t page_scan_intv;
+ /// Page scan window (in slots)
+ uint16_t page_scan_win;
+};
+
+/// HCI command complete event structure for the Read inquiry scan activity command
+struct hci_rd_inq_scan_act_cmd_cmp_evt
+{
+ /// Status of the command
+ uint8_t status;
+ /// Inquiry scan interval (in slots)
+ uint16_t inq_scan_intv;
+ /// Inquiry scan window (in slots)
+ uint16_t inq_scan_win;
+};
+
+struct hci_wr_inq_scan_act_cmd
+{
+ /// Inquiry scan interval (in slots)
+ uint16_t inq_scan_intv;
+ /// Inquiry scan window (in slots)
+ uint16_t inq_scan_win;
+};
+
+/// HCI command complete event structure for the Read authentication command
+struct hci_rd_auth_en_cmd_cmp_evt
+{
+ ///Status of the command
+ uint8_t status;
+ ///Value of the authentication
+ uint8_t auth_en;
+};
+
+struct hci_wr_auth_en_cmd
+{
+ ///Value of the authentication
+ uint8_t auth_en;
+};
+
+/// HCI command complete event structure for the read class of device command
+struct hci_rd_class_of_dev_cmd_cmp_evt
+{
+ ///Status of the command
+ uint8_t status;
+ ///Class of device
+ struct devclass class_of_dev;
+};
+
+struct hci_wr_class_of_dev_cmd
+{
+ ///Class of device
+ struct devclass class_of_dev;
+};
+
+/// HCI read voice settings complete event
+struct hci_rd_voice_stg_cmd_cmp_evt
+{
+ ///Status of the command reception
+ uint8_t status;
+ /// Voice setting
+ uint16_t voice_stg;
+};
+
+struct hci_wr_voice_stg_cmd
+{
+ /// voice setting
+ uint16_t voice_stg;
+};
+
+/// HCI command complete event structure for read number of broadcast retrans command
+struct hci_rd_nb_bdcst_retx_cmd_cmp_evt
+{
+ /// Status of the command reception
+ uint8_t status;
+ ///Read number of broadcast retransmission
+ uint8_t num_bcst_ret;
+};
+
+struct hci_wr_nb_bdcst_retx_cmd
+{
+ ///Read number of broadcast retransmission
+ uint8_t num_bcst_ret;
+};
+
+/// HCI command complete event structure for the Read Synchronous Flow Control command
+struct hci_rd_sync_flow_ctrl_en_cmd_cmp_evt
+{
+ /// Status of the command reception
+ uint8_t status;
+ ///Synchronous flow control enable
+ uint8_t sync_flow_ctrl_en;
+};
+
+struct hci_wr_sync_flow_ctrl_en_cmd
+{
+ /// Synchronous Flow Control enable
+ uint8_t sync_flow_ctrl_en;
+};
+
+///HCI set controller to host flow control command
+struct hci_set_ctrl_to_host_flow_ctrl_cmd
+{
+ ///Flow control enable for controller
+ uint8_t flow_cntl;
+};
+
+///HCI host buffer size command
+struct hci_host_buf_size_cmd
+{
+ ///Host ACL packet length
+ uint16_t acl_pkt_len;
+ ///Host synchronous packet length
+ uint8_t sync_pkt_len;
+ ///Host Total number of ACL packets allowed
+ uint16_t nb_acl_pkts;
+ ///Host total number of synchronous packets allowed
+ uint16_t nb_sync_pkts;
+};
+
+#if BT_EMB_PRESENT
+///HCI host number of completed packets command
+struct hci_host_nb_cmp_pkts_cmd
+{
+ ///Number of handles for which the completed packets number is given
+ uint8_t nb_of_hdl;
+ ///Array of connection handles
+ uint16_t con_hdl[MAX_NB_ACTIVE_ACL];
+ ///Array of number of completed packets values for connection handles.
+ uint16_t nb_comp_pkt[MAX_NB_ACTIVE_ACL];
+};
+#elif BLE_EMB_PRESENT || BLE_HOST_PRESENT
+///HCI host number of completed packets command
+struct hci_host_nb_cmp_pkts_cmd
+{
+ ///Number of handles for which the completed packets number is given
+ uint8_t nb_of_hdl;
+ ///Array of connection handles
+ uint16_t con_hdl[BLE_CONNECTION_MAX+1]; // ensure that at least 1 element is present
+ ///Array of number of completed packets values for connection handles.
+ uint16_t nb_comp_pkt[BLE_CONNECTION_MAX+1]; // ensure that at least 1 element is present
+};
+#endif //BLE_EMB_PRESENT || BLE_HOST_PRESENT
+
+/// HCI read link supervision timeout command parameters structure
+struct hci_rd_link_supv_to_cmd_cmp_evt
+{
+ ///Status for command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ ///Link supervision timeout
+ uint16_t lsto_val;
+};
+
+/// HCI write link supervision timeout command parameters structure
+struct hci_wr_link_supv_to_cmd
+{
+ ///Connection handle
+ uint16_t conhdl;
+ ///Link supervision timeout
+ uint16_t lsto_val;
+};
+
+/// HCI command complete event structure for the nb of supported IAC command
+struct hci_rd_nb_supp_iac_cmd_cmp_evt
+{
+ ///Status of the command
+ uint8_t status;
+ ///nb_of iac
+ uint8_t nb_iac;
+};
+
+/// HCI command complete event structure for read current IAC LAP command
+struct hci_rd_curr_iac_lap_cmd_cmp_evt
+{
+ ///Status of the command
+ uint8_t status;
+ ///nb of current iac
+ uint8_t nb_curr_iac;
+ ///lap
+ struct lap iac_lap;
+};
+
+/// HCI write current IAC LAP command structure
+struct hci_wr_curr_iac_lap_cmd
+{
+ /// Number of current iac laps
+ uint8_t nb_curr_iac;
+ ///lap
+ struct lap iac_lap[(HCI_MAX_CMD_PARAM_SIZE / BD_ADDR_LAP_LEN) - 1];
+};
+
+struct hci_set_afh_host_ch_class_cmd
+{
+ ///AFH channel map
+ struct chnl_map afh_ch;
+};
+
+/// HCI command complete event structure for write inquiry scan type command structure
+struct hci_rd_inq_scan_type_cmd_cmp_evt
+{
+ /// Status of the command reception
+ uint8_t status;
+ /// Inquiry scan type
+ uint8_t inq_scan_type;
+};
+
+struct hci_wr_inq_scan_type_cmd
+{
+ /// Inquiry scan type
+ uint8_t inq_scan_type;
+};
+
+/// HCI command complete event structure for read inquiry mode command structure
+struct hci_rd_inq_mode_cmd_cmp_evt
+{
+ /// Status of the command reception
+ uint8_t status;
+ /// Inquiry mode
+ uint8_t inq_mode;
+};
+
+struct hci_wr_inq_mode_cmd
+{
+ /// Inquiry mode
+ uint8_t inq_mode;
+};
+
+/// HCI command complete event structure for write page scan type command structure
+struct hci_rd_page_scan_type_cmd_cmp_evt
+{
+ /// Status of the command reception
+ uint8_t status;
+ /// Page scan type
+ uint8_t page_scan_type;
+};
+
+struct hci_wr_page_scan_type_cmd
+{
+ /// Page scan type
+ uint8_t page_scan_type;
+};
+
+/// HCI command complete event structure for read assessment mode command structure
+struct hci_rd_afh_ch_assess_mode_cmd_cmp_evt
+{
+ /// Status of the command reception
+ uint8_t status;
+ ///AFH channel assessment mode
+ uint8_t afh_ch_ass_mode;
+};
+
+struct hci_wr_afh_ch_assess_mode_cmd
+{
+ ///AFH channel assessment mode
+ uint8_t afh_ch_ass_mode;
+};
+
+/// HCI command complete event structure for remote name request cancel command
+struct hci_rd_ext_inq_rsp_cmd_cmp_evt
+{
+ ///status
+ uint8_t status;
+ ///FEC required
+ uint8_t fec_req;
+ ///Extended inquiry response
+ struct eir eir;
+};
+
+struct hci_wr_ext_inq_rsp_cmd
+{
+ ///FEC required
+ uint8_t fec_req;
+ ///Extended inquiry response
+ struct eir eir;
+};
+
+/// HCI command complete event structure for remote name request cancel command
+struct hci_rd_sp_mode_cmd_cmp_evt
+{
+ ///status
+ uint8_t status;
+ ///Simple pairing mode
+ uint8_t sp_mode;
+};
+
+struct hci_wr_sp_mode_cmd
+{
+ ///Simple pairing mode
+ uint8_t sp_mode;
+};
+
+/// HCI command complete event structure for read oob data command
+struct hci_rd_loc_oob_data_cmd_cmp_evt
+{
+ ///status
+ uint8_t status;
+ ///hash part
+ struct hash oob_c;
+ ///random part
+ struct randomizer oob_r;
+};
+
+/// HCI command complete event structure for read inquiry response transmit power command
+struct hci_rd_inq_rsp_tx_pwr_lvl_cmd_cmp_evt
+{
+ ///status
+ uint8_t status;
+ ///TX power
+ uint8_t tx_pwr;
+};
+
+struct hci_wr_inq_tx_pwr_lvl_cmd
+{
+ ///TX power
+ int8_t tx_pwr;
+};
+
+/// HCI command complete event structure for read erroneous data reporting command
+struct hci_rd_dft_err_data_rep_cmd_cmp_evt
+{
+ ///status
+ uint8_t status;
+ ///Erroneous data reporting
+ uint8_t err_data_rep;
+};
+
+struct hci_wr_dft_err_data_rep_cmd
+{
+ ///Erroneous data reporting
+ uint8_t err_data_rep;
+};
+
+/// HCI read LE Host Supported complete event
+struct hci_rd_le_host_supp_cmd_cmp_evt
+{
+ ///Status
+ uint8_t status;
+ ///LE_Supported_Host
+ uint8_t le_supported_host;
+ ///Simultaneous_LE_Host
+ uint8_t simultaneous_le_host;
+};
+
+/// HCI write LE Host Supported command
+struct hci_wr_le_host_supp_cmd
+{
+ ///LE_Supported_Host
+ uint8_t le_supported_host;
+ ///Simultaneous_LE_Host
+ uint8_t simultaneous_le_host;
+};
+
+/// HCI Set MWS Channel Parameters command
+struct hci_set_mws_channel_params_cmd
+{
+ ///MWS_Channel_Enable
+ uint8_t mws_channel_enable;
+ ///MWS_RX_Center_Frequency
+ uint16_t mws_rx_center_frequency;
+ ///MWS_TX_Center_Frequency
+ uint16_t mws_tx_center_frequency;
+ ///MWS_RX_Channel_Bandwidth
+ uint16_t mws_rx_channel_bandwidth;
+ ///MWS_TX_Channel_Bandwidth
+ uint16_t mws_tx_channel_bandwidth;
+ ///MWS_Channel_Type
+ uint8_t mws_channel_type;
+};
+
+/// HCI Set External Frame Configuration command
+struct hci_set_external_frame_config_cmd
+{
+ /// Ext_Frame_Duration
+ uint16_t ext_fr_duration;
+ /// Ext_Frame_Sync_Assert_Offset
+ int16_t ext_fr_sync_assert_offset;
+ /// Ext_Frame_Sync_Assert_Jitter
+ uint16_t ext_fr_sync_assert_jitter;
+ /// Ext_Frame_Num_Periods
+ uint8_t ext_fr_num_periods;
+ /// Period_Duration[i]
+ uint16_t period_duration[__ARRAY_EMPTY];
+ /// Period_Type[i]
+ //uint8_t period_type[__ARRAY_EMPTY];
+};
+
+/// HCI Set MWS Signaling command
+struct hci_set_mws_signaling_cmd
+{
+ ///MWS_RX_Assert_Offset
+ int16_t mws_rx_assert_offset;
+ ///MWS_RX_Assert_Jitter
+ uint16_t mws_rx_assert_jitter;
+ ///MWS_RX_Deassert_Offset
+ int16_t mws_rx_deassert_offset;
+ ///MWS_RX_Deassert_Jitter
+ uint16_t mws_rx_deassert_jitter;
+ ///MWS_TX_Assert_Offset
+ int16_t mws_tx_assert_offset;
+ ///MWS_TX_Assert_Jitter
+ uint16_t mws_tx_assert_jitter;
+ ///MWS_TX_Deassert_Offset
+ int16_t mws_tx_deassert_offset;
+ ///MWS_TX_Deassert_Jitter
+ uint16_t mws_tx_deassert_jitter;
+ ///MWS_Pattern_Assert_Offset
+ int16_t mws_pattern_assert_offset;
+ ///MWS_Pattern_Assert_Jitter
+ uint16_t mws_pattern_assert_jitter;
+ ///MWS_Inactivity_Duration_Assert_Offset
+ int16_t mws_inactivity_duration_assert_offset;
+ ///MWS_Inactivity_Duration_Assert_Jitter
+ uint16_t mws_inactivity_duration_assert_jitter;
+ ///MWS_Scan_Frequency_Assert_Offset
+ int16_t mws_scan_frequency_assert_offset;
+ ///MWS_Scan_Frequency_Assert_Jitter
+ uint16_t mws_scan_frequency_assert_jitter;
+ ///MWS_Priority_Assert_Offset_Request
+ uint16_t mws_priority_assert_offset_request;
+};
+
+/// HCI Set MWS Signaling command complete event
+struct hci_set_mws_signaling_cmd_cmp_evt
+{
+ ///Status
+ uint8_t status;
+ ///Bluetooth_Rx_Priority_Assert_Offset
+ int16_t bt_rx_prio_assert_offset;
+ ///Bluetooth_Rx_Priority_Assert_Jitter
+ uint16_t bt_rx_prio_assert_jitter;
+ ///Bluetooth_Rx_Priority_Deassert_Offset
+ int16_t bt_rx_prio_deassert_offset;
+ ///Bluetooth_Rx_Priority_Deassert_Jitter
+ uint16_t bt_rx_prio_deassert_jitter;
+ ///802_Rx_Priority_Assert_Offset
+ int16_t _802_rx_prio_assert_offset;
+ ///802_Rx_Priority_Assert_Jitter
+ uint16_t _802_rx_prio_assert_jitter;
+ ///802_Rx_Priority_Deassert_Offset
+ int16_t _802_rx_prio_deasssert_offset;
+ ///802_Rx_Priority_Deassert_Jitter
+ uint16_t _802_rx_prio_deassert_jitter;
+ ///Bluetooth_Tx_On_Assert_Offset
+ int16_t bt_tx_on_assert_offset;
+ ///Bluetooth_Tx_On_Assert_Jitter
+ uint16_t bt_tx_on_assert_jitter;
+ ///Bluetooth_Tx_On_Deassert_Offset
+ int16_t bt_tx_on_deassert_offset;
+ ///Bluetooth_Tx_On_Deassert_Jitter
+ uint16_t bt_tx_on_deassert_jitter;
+ ///802_Tx_On_Assert_Offset
+ int16_t _802_tx_on_assert_offset;
+ ///802_Tx_On_Assert_Jitter
+ uint16_t _802_tx_on_assert_jitter;
+ ///802_Tx_On_Deassert_Offset
+ int16_t _802_tx_on_deassert_offset;
+ ///802_Tx_On_Deassert_Jitter
+ uint16_t _802_tx_on_deassert_jitter;
+};
+
+/// HCI Set MWS Transport Layer command
+struct hci_set_mws_transport_layer_cmd
+{
+ ///Transport_Layer
+ uint8_t transport_layer;
+ ///To_MWS_Baud_Rate
+ uint32_t to_mws_baud_rate;
+ ///From_MWS_Baud_Rate
+ uint32_t from_mws_baud_rate;
+};
+
+/// HCI Set MWS Scan Frequency Table command
+struct hci_set_mws_scan_freq_table_cmd
+{
+ ///Num_Scan_Frequencies
+ uint8_t num_scan_frequencies;
+ ///Scan_Frequency_Low[i]
+ uint16_t scan_frequency_low[1/*__ARRAY_EMPTY*/];
+ ///Scan_Frequency_High[i]
+ uint16_t scan_frequency_high[1/*__ARRAY_EMPTY*/];
+};
+
+/// HCI Set MWS Pattern Configuration command
+struct hci_set_mws_pattern_config_cmd
+{
+ ///MWS_PATTERN_Index
+ uint8_t mws_pattern_index;
+ ///MWS_PATTERN_NumIntervals
+ uint8_t mws_pattern_num_intervals;
+ ///MWS_PATTERN_IntervalDuration[i]
+ uint16_t mws_pattern_interval_duration[1/*__ARRAY_EMPTY*/];
+ ///MWS_PATTERN_IntervalType[i]
+ uint8_t mws_pattern_interval_type[1/*__ARRAY_EMPTY*/];
+};
+
+/// Hci Get MWS Transport Layer Configuration command complete event
+struct hci_get_mws_transport_layer_config_cmd_cmp_evt
+{
+ ///Status
+ uint8_t status;
+ ///Num_Transports
+ uint8_t num_transports;
+ ///Transport_Layer[i]
+ uint8_t transport_layer[1/*__ARRAY_EMPTY*/];
+ ///Num_Baud_Rates[i]
+ uint8_t num_baud_rates[1/*__ARRAY_EMPTY*/];
+ ///To_MWS_Baud_Rate[k]
+ uint32_t to_mws_baud_rate[1/*__ARRAY_EMPTY*/];
+ ///From_MWS_Baud_Rate[k]
+ uint32_t from_mws_baud_rate[1/*__ARRAY_EMPTY*/];
+};
+
+/// HCI read Secure Connections Host Support complete event
+struct hci_rd_sec_con_host_supp_cmd_cmp_evt
+{
+ ///Status
+ uint8_t status;
+ /// Secure Connections Host Support
+ uint8_t sec_con_host_supp;
+};
+
+/// HCI write Secure Connections Host Support command
+struct hci_wr_sec_con_host_supp_cmd
+{
+ /// Secure Connections Host Support
+ uint8_t sec_con_host_supp;
+};
+
+/// HCI write Secure Connections Test Mode command
+struct hci_wr_sec_con_test_mode_cmd
+{
+ /// Connection handle
+ uint16_t conhdl;
+ /// DM1 ACL-U mode
+ uint8_t dm1_acl_u_mode;
+ /// eSCO loopback mode
+ uint8_t esco_loopback_mode;
+};
+
+/// HCI write Secure Connections Test Mode complete event
+struct hci_wr_sec_con_test_mode_cmd_cmp_evt
+{
+ ///Status
+ uint8_t status;
+ /// Connection handle
+ uint16_t conhdl;
+};
+
+/// HCI Set Reserved LT_ADDR command
+struct hci_set_res_lt_addr_cmd
+{
+ /// LT_ADDR
+ uint8_t lt_addr;
+};
+
+/// HCI Set Reserved LT_ADDR command complete event
+struct hci_set_res_lt_addr_cmd_cmp_evt
+{
+ /// Status
+ uint8_t status;
+ /// LT_ADDR
+ uint8_t lt_addr;
+};
+
+/// HCI Delete Reserved LT_ADDR command
+struct hci_del_res_lt_addr_cmd
+{
+ /// LT_ADDR
+ uint8_t lt_addr;
+};
+
+/// HCI Delete Reserved LT_ADDR command complete event
+struct hci_del_res_lt_addr_cmd_cmp_evt
+{
+ /// Status
+ uint8_t status;
+ /// LT_ADDR
+ uint8_t lt_addr;
+};
+
+/// HCI Set Connectionless Slave Broadcast Data command
+struct hci_set_con_slv_bcst_data_cmd
+{
+ /// LT_ADDR
+ uint8_t lt_addr;
+ /// Fragment
+ uint8_t fragment;
+ /// Data_Length (in bytes)
+ uint8_t data_length;
+ /// Data
+ uint8_t data[__ARRAY_EMPTY];
+};
+
+/// HCI Set Connectionless Slave Broadcast Data command complete event
+struct hci_set_con_slv_bcst_data_cmd_cmp_evt
+{
+ /// Status
+ uint8_t status;
+ /// LT_ADDR
+ uint8_t lt_addr;
+};
+
+/// HCI Read Synchronization Train Parameters command complete event
+struct hci_rd_sync_train_param_cmd_cmp_evt
+{
+ /// Status
+ uint8_t status;
+ /// Sync_Train_Interval (in slots)
+ uint16_t sync_train_int;
+ /// synchronization_trainTO (in slots)
+ uint32_t sync_train_to;
+ /// Service_Data
+ uint8_t service_data;
+};
+
+/// HCI Write Synchronization Train Parameters command
+struct hci_wr_sync_train_param_cmd
+{
+ /// Interval_Min (in slots)
+ uint16_t int_min;
+ /// Interval_Max (in slots)
+ uint16_t int_max;
+ /// synchronization_trainTO (in slots)
+ uint32_t sync_train_to;
+ /// Service_Data
+ uint8_t service_data;
+};
+
+/// HCI Write Synchronization Train Parameters command complete event
+struct hci_wr_sync_train_param_cmd_cmp_evt
+{
+ /// Status
+ uint8_t status;
+ /// Sync_Train_Interval (in slots)
+ uint16_t sync_train_int;
+};
+
+// HCI Synchronization Train Complete event
+struct hci_sync_train_cmp_evt
+{
+ /// Status
+ uint8_t status;
+};
+
+/// HCI read authenticated payload timeout command
+struct hci_rd_auth_payl_to_cmd
+{
+ ///Connection handle
+ uint16_t conhdl;
+};
+
+/// HCI command complete event structure for the Read Authenticated Payload Timeout Command
+struct hci_rd_auth_payl_to_cmd_cmp_evt
+{
+ /// Status of the command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ ///Authenticated payload timeout
+ uint16_t auth_payl_to;
+};
+
+/// HCI command complete event structure for read oob extended data command
+struct hci_rd_loc_oob_ext_data_cmd_cmp_evt
+{
+ ///status
+ uint8_t status;
+ ///hash part
+ struct hash oob_c_192;
+ ///random part
+ struct randomizer oob_r_192;
+ ///hash part
+ struct hash oob_c_256;
+ ///random part
+ struct randomizer oob_r_256;
+};
+
+/// HCI read Extended Page Timeout CC event
+struct hci_rd_ext_page_to_cmd_cmp_evt
+{
+ /// Status
+ uint8_t status;
+ /**
+ * Extended Page Timeout measured in Number of Baseband slots. Interval Length = N * 0.625 msec (1 Baseband slot)
+ * Range for N: 0x0000 (default) - 0xFFFF
+ * Time Range: 0 - 40.9 Seconds
+ */
+ uint16_t ext_page_to;
+};
+
+/// HCI write Extended Page Timeout
+struct hci_wr_ext_page_to_cmd
+{
+ /**
+ * Extended Page Timeout measured in Number of Baseband slots. Interval Length = N * 0.625 msec (1 Baseband slot)
+ * Range for N: 0x0000 (default) - 0xFFFF
+ * Time Range: 0 - 40.9 Seconds
+ */
+ uint16_t ext_page_to;
+};
+
+/// HCI read Extended Inquiry Length CC event
+struct hci_rd_ext_inq_len_cmd_cmp_evt
+{
+ /// Status
+ uint8_t status;
+ /// Extended Inquiry Length
+ uint16_t ext_inq_len;
+};
+
+/// HCI write Extended Inquiry Length
+struct hci_wr_ext_inq_len_cmd
+{
+ /// Extended Inquiry Length
+ uint16_t ext_inq_len;
+};
+
+/*
+ * HCI INFORMATIONAL PARAMETERS COMMANDS PARAMETERS
+ ****************************************************************************************
+ */
+
+///HCI command complete event structure for read local version information
+struct hci_rd_local_ver_info_cmd_cmp_evt
+{
+ /// Status of the command reception
+ uint8_t status;
+ ///HCI version number
+ uint8_t hci_ver;
+ ///HCI revision number
+ uint16_t hci_rev;
+ ///LMP version
+ uint8_t lmp_ver;
+ ///manufacturer name
+ uint16_t manuf_name;
+ ///LMP Subversion
+ uint16_t lmp_subver;
+};
+
+///HCI command complete event structure for read local supported commands
+struct hci_rd_local_supp_cmds_cmd_cmp_evt
+{
+ /// Status of the command reception
+ uint8_t status;
+ ///Supported Commands structure
+ struct supp_cmds local_cmds;
+};
+
+/// HCI command complete event structure for read local supported features command
+struct hci_rd_local_supp_feats_cmd_cmp_evt
+{
+ /// Status of the command reception
+ uint8_t status;
+ ///Local supported features
+ struct features feats;
+};
+
+struct hci_rd_local_ext_feats_cmd
+{
+ ///Page number
+ uint8_t page_nb;
+};
+
+/// HCI command complete event structure for read local extended features command
+struct hci_rd_local_ext_feats_cmd_cmp_evt
+{
+ /// Status of the command reception
+ uint8_t status;
+ ///Page number
+ uint8_t page_nb;
+ ///Maximum page number
+ uint8_t page_nb_max;
+ ///Extended LMP features
+ struct features ext_feats;
+};
+
+///HCI command complete event structure for the Read Buffer Size Command
+struct hci_rd_buff_size_cmd_cmp_evt
+{
+ /// Status of the command reception
+ uint8_t status;
+ ///ACL data packet length controller can receive from host
+ uint16_t hc_data_pk_len;
+ ///Synchronous data packet length controller can receive from host
+ uint8_t hc_sync_pk_len;
+ ///Total number of ACL data packets controller can receive from host
+ uint16_t hc_tot_nb_data_pkts;
+ ///Total number of synchronous data packets controller can receive from host
+ uint16_t hc_tot_nb_sync_pkts;
+};
+
+///HCI command complete event structure for read bd address
+struct hci_rd_bd_addr_cmd_cmp_evt
+{
+ /// Status of the command reception
+ uint8_t status;
+ ///BD address
+ struct bd_addr local_addr;
+};
+
+/// HCI command complete event structure for read local supported codecs
+struct hci_rd_local_supp_codecs_cmd_cmp_evt
+{
+ /// Status of the command reception
+ uint8_t status;
+ uint8_t nb_supp_codecs;
+ uint8_t nb_supp_vendor_specific_codecs;
+
+// ///Supported Codecs structure
+// struct supp_codecs local_codecs;
+};
+
+/*
+ * HCI STATUS PARAMETERS COMMANDS PARAMETERS
+ ****************************************************************************************
+ */
+
+/// HCI command complete event structure for read rssi
+struct hci_rd_rssi_cmd_cmp_evt
+{
+ ///Status for command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ ///RSSI value
+ int8_t rssi;
+};
+
+struct hci_rd_clk_cmd
+{
+ ///Connection handle
+ uint16_t conhdl;
+ ///Which clock
+ uint8_t clk_type;
+};
+
+/// HCI read clock command structure
+struct hci_rd_clk_cmd_cmp_evt
+{
+ /// Status of the command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ ///clock
+ uint32_t clk;
+ ///Accuracy
+ uint16_t clk_acc;
+};
+
+
+/*
+ * HCI TESTING COMMANDS PARAMETERS
+ ****************************************************************************************
+ */
+
+/// HCI command complete event structure for read loop back mode command
+struct hci_rd_loopback_mode_cmd_cmp_evt
+{
+ /// Status of the command reception
+ uint8_t status;
+ ///Local supported features
+ uint8_t lb_mode;
+};
+
+struct hci_wr_loopback_mode_cmd
+{
+ ///Local supported features
+ uint8_t lb_mode;
+};
+struct hci_wr_sp_dbg_mode_cmd
+{
+ ///Simple pairing mode
+ uint8_t sp_mode;
+};
+
+
+/// * TCI Event subcodes
+enum tci_evt_subcode
+{
+ TCI_LMP_TX_EVENT = 0x22,
+ TCI_LMP_RX_EVENT = 0x23,
+ TCI_LC_TX_EVENT = 0x24,
+ TCI_LC_RX_EVENT = 0x25,
+ TCI_BB_TX_EVENT = 0x26,
+ TCI_BB_RX_EVENT = 0x27,
+ TCI_HW_ERROR_EVENT = 0x28,
+ TCI_RADIO_EVENT = 0x30,
+ TCI_INTERRUPT_EVENT = 0x40,
+};
+
+/// LMP direction
+#define TCI_LMP_DIR_TX 0
+#define TCI_LMP_DIR_RX 1
+
+/// HCI tci lmp exchange event structure
+struct hci_tci_lmp_evt
+{
+ ///code
+ uint8_t tci_code;
+ ///length
+ uint8_t evt_len;
+ ///subcode
+ uint8_t subcode;
+ ///evt direction
+ uint8_t direction;
+ ///lmp evt body
+ uint8_t body[17];
+};
+
+/*
+ * HCI LE CONTROLLER COMMANDS PARAMETERS
+ ****************************************************************************************
+ */
+
+///HCI LE Set Event Mask Command parameters structure
+struct hci_le_set_evt_mask_cmd
+{
+ ///LE Event Mask
+ struct evt_mask le_mask;
+};
+
+///HCI LE Set Random Address Command parameters structure
+struct hci_le_set_rand_addr_cmd
+{
+ ///Random address to set
+ struct bd_addr rand_addr;
+};
+
+///HCI LE Set Advertising Parameters Command parameters structure
+struct hci_le_set_adv_param_cmd
+{
+ ///Minimum interval for advertising
+ uint16_t adv_intv_min;
+ ///Maximum interval for advertising
+ uint16_t adv_intv_max;
+ ///Advertising type
+ uint8_t adv_type;
+ ///Own address type: public=0 / random=1 / rpa_or_pub=2 / rpa_or_rnd=3
+ uint8_t own_addr_type;
+ ///Peer address type: public=0 / random=1
+ uint8_t peer_addr_type;
+ ///Peer Bluetooth device address
+ struct bd_addr peer_addr;
+ ///Advertising channel map
+ uint8_t adv_chnl_map;
+ ///Advertising filter policy
+ uint8_t adv_filt_policy;
+};
+
+///HCI LE Set Advertising Data Command parameters structure
+struct hci_le_set_adv_data_cmd
+{
+ ///Advertising data length
+ uint8_t adv_data_len;
+ ///Advertising data - maximum 31 bytes
+ struct adv_data data;
+};
+
+///HCI LE Set Scan Response Data Command parameters structure
+struct hci_le_set_scan_rsp_data_cmd
+{
+ ///Scan response data length
+ uint8_t scan_rsp_data_len;
+ ///Scan response data - maximum 31 bytes
+ struct scan_rsp_data data;
+};
+
+///HCI LE Set Advertise Enable Command parameters structure
+struct hci_le_set_adv_en_cmd
+{
+ ///Advertising enable - 0=disabled, 1=enabled
+ uint8_t adv_en;
+};
+
+///HCI LE Set Scan Parameters Command parameters structure
+struct hci_le_set_scan_param_cmd
+{
+ ///Scan type - 0=passive / 1=active
+ uint8_t scan_type;
+ ///Scan interval
+ uint16_t scan_intv;
+ ///Scan window size
+ uint16_t scan_window;
+ ///Own address type - public=0 / random=1 / rpa_or_pub=2 / rpa_or_rnd=3
+ uint8_t own_addr_type;
+ ///Scan filter policy
+ uint8_t scan_filt_policy;
+};
+
+///HCI LE Set Scan Enable Command parameters structure
+struct hci_le_set_scan_en_cmd
+{
+ ///Scan enable - 0=disabled, 1=enabled
+ uint8_t scan_en;
+ ///Enable for duplicates filtering - 0 =disabled/ 1=enabled
+ uint8_t filter_duplic_en;
+};
+
+///HCI LE Create Connection Command parameters structure
+struct hci_le_create_con_cmd
+{
+ ///Scan interval
+ uint16_t scan_intv;
+ ///Scan window size
+ uint16_t scan_window;
+ ///Initiator filter policy
+ uint8_t init_filt_policy;
+ ///Peer address type - public=0 / random=1 / rpa_or_pub=2 / rpa_or_rnd=3
+ uint8_t peer_addr_type;
+ ///Peer BD address
+ struct bd_addr peer_addr;
+ ///Own address type - public=0 / random=1 / rpa_or_pub=2 / rpa_or_rnd=3
+ uint8_t own_addr_type;
+ ///Minimum of connection interval
+ uint16_t con_intv_min;
+ ///Maximum of connection interval
+ uint16_t con_intv_max;
+ ///Connection latency
+ uint16_t con_latency;
+ ///Link supervision timeout
+ uint16_t superv_to;
+ ///Minimum CE length
+ uint16_t ce_len_min;
+ ///Maximum CE length
+ uint16_t ce_len_max;
+};
+
+///HCI LE Add Device to White List Command parameters structure
+struct hci_le_add_dev_to_wlst_cmd
+{
+ ///Type of address of the device to be added to the White List - 0=public/1=random
+ uint8_t dev_addr_type;
+ ///Address of device to be added to White List
+ struct bd_addr dev_addr;
+};
+
+///HCI LE Remove Device from White List Command parameters structure
+struct hci_le_rmv_dev_from_wlst_cmd
+{
+ ///Type of address of the device to be removed from the White List - 0=public/1=random
+ uint8_t dev_addr_type;
+ ///Address of device to be removed from White List
+ struct bd_addr dev_addr;
+};
+
+
+///HCI LE Set Host Channel Classification Command parameters structure
+struct hci_le_set_host_ch_class_cmd
+{
+ ///Channel map
+ struct le_chnl_map chmap;
+};
+
+
+///HCI LE Receiver Test Command parameters structure
+struct hci_le_rx_test_cmd
+{
+ ///RX frequency for Rx test
+ uint8_t rx_freq;
+};
+
+///HCI LE Transmitter Test Command parameters structure
+struct hci_le_tx_test_cmd
+{
+ ///TX frequency for Tx test
+ uint8_t tx_freq;
+ ///TX test data length
+ uint8_t test_data_len;
+ ///TX test payload type - see enum
+ uint8_t pk_payload_type;
+};
+
+///HCI LE Encrypt Command parameters structure
+struct hci_le_enc_cmd
+{
+ ///Long term key structure
+ struct ltk key;
+ ///Pointer to buffer with plain data to encrypt - 16 bytes
+ uint8_t plain_data[16];
+};
+
+/// HCI LE Connection Update Command parameters structure
+struct hci_le_con_update_cmd
+{
+ ///Connection Handle
+ uint16_t conhdl;
+ ///Minimum of connection interval
+ uint16_t con_intv_min;
+ ///Maximum of connection interval
+ uint16_t con_intv_max;
+ ///Connection latency
+ uint16_t con_latency;
+ ///Link supervision timeout
+ uint16_t superv_to;
+ ///Minimum of CE length
+ uint16_t ce_len_min;
+ ///Maximum of CE length
+ uint16_t ce_len_max;
+};
+
+/// HCI LE Start Encryption Command parameters structure
+struct hci_le_start_enc_cmd
+{
+ ///Connection handle
+ uint16_t conhdl;
+ ///Random number - 8B
+ struct rand_nb nb;
+ ///Encryption Diversifier
+ uint16_t enc_div;
+ ///Long term key
+ struct ltk ltk;
+};
+
+/// HCI long term key request reply command parameters structure
+struct hci_le_ltk_req_reply_cmd
+{
+ ///Connection handle
+ uint16_t conhdl;
+ ///Long term key
+ struct ltk ltk;
+};
+
+/// HCI LE remote connection parameter request reply command parameters structure
+struct hci_le_rem_con_param_req_reply_cmd
+{
+ ///Connection handle
+ uint16_t conhdl;
+ ///Interval_Min
+ uint16_t interval_min;
+ ///Interval_Max
+ uint16_t interval_max;
+ ///Latency
+ uint16_t latency;
+ ///Timeout
+ uint16_t timeout;
+ ///Minimum_CE_Length
+ uint16_t min_ce_len;
+ ///Maximum_CE_Length
+ uint16_t max_ce_len;
+};
+
+/// HCI LE remote connection parameter request negative reply command parameters structure
+struct hci_le_rem_con_param_req_neg_reply_cmd
+{
+ ///Connection handle
+ uint16_t conhdl;
+ ///Reason
+ uint8_t reason;
+};
+
+
+/// HCI LE Set Data Length Command parameters structure
+struct hci_le_set_data_len_cmd
+{
+ ///Connection Handle
+ uint16_t conhdl;
+ ///Preferred maximum number of payload octets that the local Controller should include
+ ///in a single Link Layer Data Channel PDU.
+ uint16_t tx_octets;
+ ///Preferred maximum number of microseconds that the local Controller should use to transmit
+ ///a single Link Layer Data Channel PDU
+ uint16_t tx_time;
+};
+
+/// HCI LE Read Suggested Default Data Length Command
+struct hci_le_wr_suggted_dft_data_len_cmd
+{
+ ///Suggested value for the Controller's maximum transmitted number of payload octets to be used
+ uint16_t suggted_max_tx_octets;
+ ///Suggested value for the Controller's maximum packet transmission time to be used
+ uint16_t suggted_max_tx_time;
+};
+
+/// HCI LE Add Device to Resolving List Command
+struct hci_le_add_dev_to_rslv_list_cmd
+{
+ /// Peer Identity Address Type
+ uint8_t peer_id_addr_type;
+ /// Peer Identity Address
+ struct bd_addr peer_id_addr;
+ /// Peer IRK
+ struct irk peer_irk;
+ /// Local IRK
+ struct irk local_irk;
+};
+
+/// HCI LE Remove Device From Resolving List Command
+struct hci_le_rmv_dev_from_rslv_list_cmd
+{
+ /// Peer Identity Address Type
+ uint8_t peer_id_addr_type;
+ /// Peer Identity Address
+ struct bd_addr peer_id_addr;
+};
+
+/// HCI LE Read Peer Resolvable Address Command
+struct hci_le_rd_peer_rslv_addr_cmd
+{
+ /// Peer Identity Address Type
+ uint8_t peer_id_addr_type;
+ /// Peer Identity Address
+ struct bd_addr peer_id_addr;
+};
+
+/// HCI LE Read Local Resolvable Address Command
+struct hci_le_rd_loc_rslv_addr_cmd
+{
+ /// Peer Identity Address Type
+ uint8_t peer_id_addr_type;
+ /// Peer Identity Address
+ struct bd_addr peer_id_addr;
+};
+
+/// HCI LE Set Address Resolution Enable Command
+struct hci_le_set_addr_resol_en_cmd
+{
+ /// Address Resolution Enable
+ uint8_t enable;
+};
+
+/// HCI LE Set Resolvable Private Address Timeout Command
+struct hci_le_set_rslv_priv_addr_to_cmd
+{
+ /// RPA Timeout
+ uint16_t rpa_timeout;
+};
+
+/*
+ * HCI EVENTS PARAMETERS
+ ****************************************************************************************
+ */
+
+/// HCI inquiry complete event structure
+struct hci_inq_cmp_evt
+{
+ ///Status of the procedure
+ uint8_t status;
+};
+
+
+/// HCI Inquiry result event structure (with only 1 result)
+struct hci_inq_res_evt
+{
+
+ ///Number of response
+ uint8_t nb_rsp;
+ ///BdAddr
+ struct bd_addr bd_addr;
+ ///Page Scan Repetition Mode
+ uint8_t page_scan_rep_mode;
+ ///Reserved
+ uint8_t reserved1;
+ ///Reserved
+ uint8_t reserved2;
+ ///class of device
+ struct devclass class_of_dev;
+ ///Clock Offset
+ uint16_t clk_off;
+
+};
+
+/// HCI Inquiry result with rssi event structure (with only 1 result)
+struct hci_inq_res_with_rssi_evt
+{
+ ///Number of response
+ uint8_t nb_rsp;
+ ///BdAddr
+ struct bd_addr bd_addr;
+ ///Page Scan Repetition Mode
+ uint8_t page_scan_rep_mode;
+ ///Reserved
+ uint8_t reserved1;
+ ///class of device
+ struct devclass class_of_dev;
+ ///Clock Offset
+ uint16_t clk_off;
+ ///Rssi
+ uint8_t rssi;
+
+};
+
+/// HCI Extended inquiry result indication structure (with only 1 result)
+struct hci_ext_inq_res_evt
+{
+ ///Number of response
+ uint8_t nb_rsp;
+ ///BdAddr
+ struct bd_addr bd_addr;
+ ///Page Scan Repetition Mode
+ uint8_t page_scan_rep_mode;
+ ///Reserved
+ uint8_t reserved1;
+ ///class of device
+ struct devclass class_of_dev;
+ ///Clock Offset
+ uint16_t clk_off;
+ ///RSSi
+ uint8_t rssi;
+ ///Extended inquiry response data
+ struct eir eir;
+};
+
+/// HCI disconnect complete event structure
+struct hci_disc_cmp_evt
+{
+ ///Status of received command
+ uint8_t status;
+ ///Connection Handle
+ uint16_t conhdl;
+ ///Reason for disconnection
+ uint8_t reason;
+};
+
+/// HCI basic command complete event structure
+struct hci_basic_cmd_cmp_evt
+{
+ ///Status of the command reception
+ uint8_t status;
+};
+
+/// HCI basic command complete event structure with connection handle
+struct hci_basic_conhdl_cmd_cmp_evt
+{
+ /// status
+ uint8_t status;
+ /// connection handle
+ uint16_t conhdl;
+};
+
+/// HCI basic command complete event structure with BD address
+struct hci_basic_bd_addr_cmd_cmp_evt
+{
+ ///status
+ uint8_t status;
+ ///BdAddr
+ struct bd_addr bd_addr;
+};
+
+/// HCI basic event structure with status and BD address
+struct hci_basic_stat_bd_addr_evt
+{
+ ///status
+ uint8_t status;
+ ///BdAddr
+ struct bd_addr bd_addr;
+};
+
+/// HCI basic event including a connection handle as parameter
+struct hci_basic_conhdl_evt
+{
+ ///Connection handle
+ uint16_t conhdl;
+};
+
+/// HCI complete event with status only.
+struct hci_cmd_stat_event
+{
+ /// Status of the command reception
+ uint8_t status;
+};
+
+/// HCI number of packet complete event structure
+struct hci_nb_cmp_pkts_evt
+{
+ /// number of handles
+ uint8_t nb_of_hdl;
+ /// connection handle
+ uint16_t conhdl[1];
+ /// number of completed packets
+ uint16_t nb_comp_pkt[1];
+};
+
+/// HCI data buffer overflow event structure
+struct hci_data_buf_ovflw_evt
+{
+ ///Link type
+ uint8_t link_type;
+};
+
+/// HCI Hardware Error Event parameters structure
+struct hci_hw_err_evt
+{
+ /// HW error code
+ uint8_t hw_code;
+};
+
+/// HCI encryption change event structure
+struct hci_enc_change_evt
+{
+ ///Status for command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ ///Encryption enabled information
+ uint8_t enc_stat;
+};
+
+/// HCI encryption key refresh complete event structure
+struct hci_enc_key_ref_cmp_evt
+{
+ ///Status for command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+};
+
+/// HCI Authenticated Payload Timeout Expired Event structure
+struct hci_auth_payl_to_exp_evt
+{
+ ///Connection handle
+ uint16_t conhdl;
+};
+
+/// HCI command complete event structure for create connection
+struct hci_con_cmp_evt
+{
+ /// Status
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ ///Bluetooth Device address
+ struct bd_addr bd_addr;
+ ///Link type
+ uint8_t link_type;
+ ///Encryption state
+ uint8_t enc_en;
+};
+
+/// HCI command complete event structure for qos setup
+struct hci_qos_setup_cmp_evt
+{
+ ///Status for command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ ///Flags
+ uint8_t flags;
+ ///Service type
+ uint8_t serv_type;
+ ///Token rate
+ uint32_t tok_rate;
+ ///Peak bandwidth
+ uint32_t pk_bw;
+ ///Latency
+ uint32_t lat;
+ ///Delay variation
+ uint32_t del_var;
+};
+
+/// HCI flow specification complete event parameters structure
+struct hci_flow_spec_cmp_evt
+{
+ ///Status for command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ ///Flags
+ uint8_t flags;
+ ///Flow direction
+ uint8_t flow_dir;
+ ///Service type
+ uint8_t serv_type;
+ ///Token rate
+ uint32_t tk_rate;
+ ///Token buffer size
+ uint32_t tk_buf_sz;
+ ///Peak bandwidth
+ uint32_t pk_bw;
+ ///Access latency
+ uint32_t acc_lat;
+};
+
+/// HCI role change event parameters structure
+struct hci_role_chg_evt
+{
+ ///Status
+ uint8_t status;
+ ///BD address
+ struct bd_addr bd_addr;
+ ///New role
+ uint8_t new_role;
+};
+
+/// HCI complete event structure for the read clock offset command
+struct hci_rd_clk_off_cmp_evt
+{
+ ///Status for command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ ///Clock offset
+ uint16_t clk_off_val;
+};
+
+/// HCI event structure for the flush occurred event
+struct hci_flush_occurred_evt
+{
+ ///Connection handle
+ uint16_t conhdl;
+};
+
+/// HCI max slot change event structure
+struct hci_max_slot_chg_evt
+{
+ ///Connection handle
+ uint16_t conhdl;
+ ///Max slot
+ uint8_t max_slot;
+};
+
+/// HCI sniff subrating event parameters structure
+struct hci_sniff_sub_evt
+{
+ ///Status.
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ ///Maximum transmit latency
+ uint16_t max_lat_tx;
+ ///Maximum receive latency
+ uint16_t max_lat_rx;
+ ///Minimum remote TO
+ uint16_t min_rem_to;
+ ///Minimum local TO
+ uint16_t min_loc_to;
+};
+
+/// HCI read remote extended features complete event parameters structure
+struct hci_rd_rem_ext_feats_cmp_evt
+{
+ ///Status for command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ ///page number
+ uint8_t pg_nb;
+ ///page number max
+ uint8_t pg_nb_max;
+ ///ext LMP features
+ struct features ext_feats;
+};
+
+/// HCI read remote extended features complete event parameters structure
+struct hci_rem_host_supp_feats_notif_evt
+{
+ ///BD address
+ struct bd_addr bd_addr;
+ ///ext lmp features
+ struct features ext_feats;
+};
+
+/// HCI command complete event structure for the read remote supported features command
+struct hci_rd_rem_supp_feats_cmp_evt
+{
+ ///Status for command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ ///Remote features
+ struct features rem_feats;
+};
+
+/// HCI command complete event structure for the read remote information version command
+struct hci_rd_rem_ver_info_cmp_evt
+{
+ ///Status for command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ ///LMP version
+ uint8_t vers;
+ ///Manufacturer name
+ uint16_t compid;
+ ///LMP subversion
+ uint16_t subvers;
+};
+
+/// HCI encryption change event structure
+struct hci_enc_chg_evt
+{
+ ///Status for command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ ///Encryption enabled information
+ uint8_t enc_stat;
+};
+
+/// HCI mode change event structure
+struct hci_mode_chg_evt
+{
+ ///Status for command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ ///Current mode
+ uint8_t cur_mode;
+ /// Interval
+ uint16_t interv;
+};
+
+/// HCI simple pairing complete event structure
+struct hci_sp_cmp_evt
+{
+ ///Status for command reception
+ uint8_t status;
+ ///Bluetooth Device address
+ struct bd_addr bd_addr;
+};
+
+/// HCI Authentication complete event structure
+struct hci_auth_cmp_evt
+{
+ ///Status for command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+};
+
+/// HCI change connection link key complete event structure
+struct hci_chg_con_lk_cmp_evt
+{
+ ///Status
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+};
+
+/// HCI encryption key refresh complete event structure
+struct hci_enc_key_refresh_cmp_evt
+{
+ ///Status for command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+};
+
+/// HCI master link key complete event structure
+struct hci_master_lk_cmp_evt
+{
+ ///Status for command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ ///Key flag
+ uint8_t key_flag;
+};
+/// HCI synchronous link connection complete event structure
+struct hci_sync_con_cmp_evt
+{
+ ///Status for command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ ///BD address
+ struct bd_addr bd_addr;
+ ///Link type
+ uint8_t lk_type;
+ ///Transmit interval
+ uint8_t tx_int;
+ ///Retransmission window
+ uint8_t ret_win;
+ ///rx packet length
+ uint16_t rx_pkt_len;
+ ///tx packet length
+ uint16_t tx_pkt_len;
+ ///Air mode
+ uint8_t air_mode;
+
+};
+
+/// HCI synchronous connection change event structure
+struct hci_sync_con_chg_evt
+{
+ ///Status for command reception
+ uint8_t status;
+ ///Synchronous Connection handle
+ uint16_t sync_conhdl;
+ ///Transmit interval
+ uint8_t tx_int;
+ ///Retransmission window
+ uint8_t ret_win;
+ ///rx packet length
+ uint16_t rx_pkt_len;
+ ///tx packet length
+ uint16_t tx_pkt_len;
+};
+
+/// HCI connection packet type change event structure
+struct hci_con_pkt_type_chg_evt
+{
+ ///Status for command reception
+ uint8_t status;
+ ///Synchronous Connection handle
+ uint16_t sync_conhdl;
+ ///Synchronous packet type
+ uint16_t pkt_type;
+};
+
+/// HCI link supervision timeout change event structure
+struct hci_link_supv_to_chg_evt
+{
+ ///Connection handle
+ uint16_t conhdl;
+ ///Link supervision timeout
+ uint16_t lsto_val;
+};
+
+/// HCI link key request event structure
+struct hci_lk_req_evt
+{
+ ///BD address
+ struct bd_addr bd_addr;
+};
+
+/// HCI encryption key refresh event structure
+struct hci_enc_key_refresh_evt
+{
+ ///Status for command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+};
+
+/// HCI connection request event structure
+struct hci_con_req_evt
+{
+ ///BD address
+ struct bd_addr bd_addr;
+ ///Class of device
+ struct devclass classofdev;
+ ///link type
+ uint8_t lk_type;
+};
+
+/// HCI quality of service violation event structure
+struct hci_qos_viol_evt
+{
+ ///Connection handle
+ uint16_t conhdl;
+};
+
+/// HCI io capability response event structure
+struct hci_io_cap_rsp_evt
+{
+ ///BdAddr
+ struct bd_addr bd_addr;
+ ///IO capability
+ uint8_t io_capa;
+ ///OOB data present
+ uint8_t oob_data_pres;
+ ///Authentication requirements
+ uint8_t auth_req;
+
+};
+
+/// HCI IO capability response event structure
+struct hci_io_cap_req_evt
+{
+ ///BdAddr
+ struct bd_addr bd_addr;
+};
+
+/// HCI Return link keys event structure
+struct hci_return_link_keys_evt
+{
+ ///Number of Keys
+ uint8_t num_keys;
+ ///BdAddr
+ struct bd_addr bd_addr;
+ ///Key
+ struct ltk key;
+};
+
+/// HCI pin code request event structure
+struct hci_pin_code_req_evt
+{
+ ///BdAddr
+ struct bd_addr bd_addr;
+};
+
+/// HCI user passkey request event structure
+struct hci_user_passkey_req_evt
+{
+ ///BdAddr
+ struct bd_addr bd_addr;
+};
+
+/// HCI user passkey notification event structure
+struct hci_user_passkey_notif_evt
+{
+ ///BdAddr
+ struct bd_addr bd_addr;
+ ///Passkey
+ uint32_t passkey;
+};
+
+/// HCI remote OOB data request event structure
+struct hci_rem_oob_data_req_evt
+{
+ ///BdAddr
+ struct bd_addr bd_addr;
+};
+
+/// HCI user confirmation request event structure
+struct hci_user_cfm_req_evt
+{
+ ///BdAddr
+ struct bd_addr bd_addr;
+ ///Passkey
+ uint32_t passkey;
+};
+
+/// HCI keypress notification event structure
+struct hci_keypress_notif_evt
+{
+ ///BdAddr
+ struct bd_addr bd_addr;
+ ///type
+ uint8_t type;
+};
+
+/// HCI link key notification event structure
+struct hci_lk_notif_evt
+{
+ ///BdAddr
+ struct bd_addr bd_addr;
+ ///Key
+ struct ltk key;
+ ///type
+ uint8_t key_type;
+};
+
+
+/*
+ * HCI LE META EVENTS PARAMETERS
+ ****************************************************************************************
+ */
+
+
+// LE event structures
+
+/// HCI command complete event structure for the Read Local Supported Features
+struct hci_le_rd_local_supp_feats_cmd_cmp_evt
+{
+ /// Status of the command reception
+ uint8_t status;
+ ///Local LE supported features
+ struct le_features feats;
+};
+
+/// HCI command complete event structure for the Read Advertising Channel Tx Power Command
+struct hci_rd_adv_chnl_tx_pw_cmd_cmp_evt
+{
+ /// Status of the command reception
+ uint8_t status;
+ ///Advertising channel Tx power level
+ int8_t adv_tx_pw_lvl;
+};
+
+///HCI command complete event structure for the Read White List Size Command
+struct hci_rd_wlst_size_cmd_cmp_evt
+{
+ /// Status of the command reception
+ uint8_t status;
+ ///White List size
+ uint8_t wlst_size;
+};
+
+///HCI command complete event structure for the Read Buffer Size Command
+struct hci_le_rd_buff_size_cmd_cmp_evt
+{
+ /// Status of the command reception
+ uint8_t status;
+ ///ACL data packet length that can be sent from host to controller
+ uint16_t hc_data_pk_len;
+ ///Total number of ACL data packets that can be sent from host to controller.
+ uint8_t hc_tot_nb_data_pkts;
+};
+
+///HCI command complete event structure for LE Rand Command
+struct hci_le_rand_cmd_cmp_evt
+{
+ /// Status of the command reception
+ uint8_t status;
+ ///Random number
+ struct rand_nb nb;
+};
+
+///HCI command complete event structure for Read Supported States Command
+struct hci_rd_supp_states_cmd_cmp_evt
+{
+ /// Status of the command reception
+ uint8_t status;
+ ///LE supported states response
+ struct le_states states;
+};
+
+///HCI command complete event structure for Test End
+struct hci_test_end_cmd_cmp_evt
+{
+ /// Status of the command reception
+ uint8_t status;
+ ///Number of RX packets - null if TX test was the ended one
+ uint16_t nb_packet_received;
+};
+
+///HCI LE Encrypt complete event structure
+struct hci_le_enc_cmd_cmp_evt
+{
+ /// Status of the command reception
+ uint8_t status;
+ ///Encrypted data to return to command source.
+ uint8_t encrypted_data[ENC_DATA_LEN];
+};
+
+#if BLE_EMB_PRESENT || BLE_HOST_PRESENT
+///HCI LE advertising report event structure
+struct hci_le_adv_report_evt
+{
+ ///LE Subevent code
+ uint8_t subcode;
+ ///Number of advertising reports in this event
+ uint8_t nb_reports;
+ ///Advertising reports structures array
+ struct adv_report adv_rep[BLE_ADV_REPORTS_MAX];
+};
+#endif //BLE_EMB_PRESENT || BLE_HOST_PRESENT
+
+/// HCI command complete event structure for Read Channel Map Command
+struct hci_le_rd_chnl_map_cmd_cmp_evt
+{
+ ///Status of command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ ///Channel map
+ struct le_chnl_map ch_map;
+};
+
+/// HCI command complete event structure for Long Term Key Request Reply Command
+struct hci_le_ltk_req_reply_cmd_cmp_evt
+{
+ ///Status of command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+};
+
+/// HCI command complete event structure for Long Term Key Request Negative Reply Command
+struct hci_le_ltk_req_neg_reply_cmd_cmp_evt
+{
+ ///Status of command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+};
+
+/// HCI command complete event structure for LE Read Suggested Default Data Length Command
+struct hci_le_rd_suggted_dft_data_len_cmd_cmp_evt
+{
+ ///Status of command reception
+ uint8_t status;
+ ///Host's suggested value for the Controller's maximum transmitted number of payload octets
+ uint16_t suggted_max_tx_octets;
+ ///Host's suggested value for the Controller's maximum packet transmission time
+ uint16_t suggted_max_tx_time;
+};
+/// HCI command complete event structure for LE Read Maximum Data Length Command
+struct hci_le_rd_max_data_len_cmd_cmp_evt
+{
+ ///Status of command reception
+ uint8_t status;
+ ///Maximum number of payload octets that the local Controller supports for transmission
+ uint16_t suppted_max_tx_octets;
+ ///Maximum time, in microseconds, that the local Controller supports for transmission
+ uint16_t suppted_max_tx_time;
+ ///Maximum number of payload octets that the local Controller supports for reception
+ uint16_t suppted_max_rx_octets;
+ ///Maximum time, in microseconds, that the local Controller supports for reception
+ uint16_t suppted_max_rx_time;
+};
+
+/// HCI LE Read Peer Resolvable Address Command Complete Event
+struct hci_le_rd_peer_rslv_addr_cmd_cmp_evt
+{
+ ///Status
+ uint8_t status;
+ /// Peer Resolvable Address
+ struct bd_addr peer_rslv_addr;
+};
+
+/// HCI LE Read Local Resolvable Address Command Complete Event
+struct hci_le_rd_loc_rslv_addr_cmd_cmp_evt
+{
+ ///Status
+ uint8_t status;
+ /// Local Resolvable Address
+ struct bd_addr loc_rslv_addr;
+};
+
+/// HCI LE Read Resolving List Size Command Complete Event
+struct hci_le_rd_rslv_list_size_cmd_cmp_evt
+{
+ ///Status
+ uint8_t status;
+ /// Resolving List Size
+ uint8_t size;
+};
+
+
+/// HCI write authenticated payload timeout command
+struct hci_wr_auth_payl_to_cmd
+{
+ ///Connection handle
+ uint16_t conhdl;
+ ///Authenticated payload timeout
+ uint16_t auth_payl_to;
+};
+
+/// HCI command complete event structure for the Write Authenticated Payload Timeout Command
+struct hci_wr_auth_payl_to_cmd_cmp_evt
+{
+ /// Status of the command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+};
+
+/// HCI command complete event structure for HCI LE Connection Update Command
+struct hci_le_con_update_cmp_evt
+{
+ ///LE Subevent code
+ uint8_t subcode;
+ ///Status of received command
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ ///Connection interval value
+ uint16_t con_interval;
+ ///Connection latency value
+ uint16_t con_latency;
+ ///Supervision timeout
+ uint16_t sup_to;
+};
+
+/// HCI command complete event structure for create connection
+struct hci_le_con_cmp_evt
+{
+ ///LE Subevent code
+ uint8_t subcode;
+ ///Status of received command
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ ///Device role - 0=Master/ 1=Slave
+ uint8_t role;
+ ///Peer address type - 0=public/1=random
+ uint8_t peer_addr_type;
+ ///Peer address
+ struct bd_addr peer_addr;
+ ///Connection interval
+ uint16_t con_interval;
+ ///Connection latency
+ uint16_t con_latency;
+ ///Link supervision timeout
+ uint16_t sup_to;
+ ///Master clock accuracy
+ uint8_t clk_accuracy;
+};
+
+/// HCI LE read remote used feature command parameters structure
+struct hci_le_rd_rem_used_feats_cmd
+{
+ ///Connection handle
+ uint16_t conhdl;
+};
+
+/// HCI command complete event structure for HCI LE read remote used feature Command
+struct hci_le_rd_rem_used_feats_cmd_cmp_evt
+{
+ ///LE Subevent code
+ uint8_t subcode;
+ ///Status of received command
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ ///Le Features used
+ struct le_features feats_used;
+};
+
+/// HCI command structure for the read transmit power level command
+struct hci_rd_tx_pwr_lvl_cmd
+{
+ ///Connection handle
+ uint16_t conhdl;
+ ///Power Level type: current or maximum
+ uint8_t type;
+};
+
+/// HCI command complete event structure for the read transmit power level command
+struct hci_rd_tx_pwr_lvl_cmd_cmp_evt
+{
+ ///Status for command reception
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ ///Value of TX power level
+ uint8_t tx_pow_lvl;
+};
+
+/// HCI read remote information version command parameters structure
+struct hci_rd_rem_ver_info_cmd
+{
+ ///Connection handle
+ uint16_t conhdl;
+};
+
+/// HCI LE remote connection parameter request event
+struct hci_le_rem_con_param_req_evt
+{
+ ///LE Subevent code
+ uint8_t subcode;
+ ///Connection handle
+ uint16_t conhdl;
+ ///Interval_Min
+ uint16_t interval_min;
+ ///Interval_Max
+ uint16_t interval_max;
+ ///Latency
+ uint16_t latency;
+ ///Timeout
+ uint16_t timeout;
+};
+
+
+/// HCI command complete event structure for enhance create connection
+struct hci_le_enh_con_cmp_evt
+{
+ ///LE Subevent code
+ uint8_t subcode;
+ ///Status of received command
+ uint8_t status;
+ ///Connection handle
+ uint16_t conhdl;
+ ///Device role - 0=Master/ 1=Slave
+ uint8_t role;
+ ///Peer address type - 0=public/1=random
+ uint8_t peer_addr_type;
+ ///Peer address
+ struct bd_addr peer_addr;
+ ///Local Resolvable Private Address
+ struct bd_addr loc_rslv_priv_addr;
+ ///Peer Resolvable Private Address
+ struct bd_addr peer_rslv_priv_addr;
+ ///Connection interval
+ uint16_t con_interval;
+ ///Connection latency
+ uint16_t con_latency;
+ ///Link supervision timeout
+ uint16_t sup_to;
+ ///Master clock accuracy
+ uint8_t clk_accuracy;
+};
+
+
+struct hci_generate_dhkey_cmp_evt
+{
+ ///LE Subevent code
+ uint8_t subcode;
+ ///Status of received command
+ uint8_t status;
+ /// The 32 byte Diffie Helman Key
+ uint8_t dh_key[32];
+};
+
+
+struct hci_rd_local_p256_public_key_cmp_evt
+{
+ ///LE Subevent code
+ uint8_t subcode;
+ ///Status of received command
+ uint8_t status;
+ /// The 32 byte Diffie Helman Key
+ uint8_t public_key[64];
+
+};
+
+#if BLE_EMB_PRESENT || BLE_HOST_PRESENT
+/// HCI LE Direct Advertising Report Event
+struct hci_le_dir_adv_rep_evt
+{
+ ///LE Subevent code
+ uint8_t subcode;
+ ///Number of reports
+ uint8_t nb_reports;
+ ///Direct Advertising reports structures array
+ struct dir_adv_report adv_rep[BLE_ADV_REPORTS_MAX];
+};
+#endif //BLE_EMB_PRESENT || BLE_HOST_PRESENT
+
+/// HCI command complete event structure for HCI LE read remote used feature Command
+struct hci_le_ltk_request_evt
+{
+ ///LE Subevent code
+ uint8_t subcode;
+ ///Connection handle
+ uint16_t conhdl;
+ ///Random number
+ struct rand_nb rand;
+ ///Encryption diversifier
+ uint16_t ediv;
+};
+
+/// HCI LE META event LE Data Length Change Event
+struct hci_le_data_len_chg_evt
+{
+ ///LE Subevent code
+ uint8_t subcode;
+ ///Connection handle
+ uint16_t conhdl;
+ ///The maximum number of payload octets in TX
+ uint16_t max_tx_octets;
+ ///The maximum time that the local Controller will take to TX
+ uint16_t max_tx_time;
+ ///The maximum number of payload octets in RX
+ uint16_t max_rx_octets;
+ ///The maximum time that the local Controller will take to RX
+ uint16_t max_rx_time;
+};
+
+
+/// HCI Synchronization Train Received Event
+struct hci_sync_train_rec_evt
+{
+ /// Status
+ uint8_t status;
+ /// BD_ADDR
+ struct bd_addr bd_addr;
+ /// Clock_Offset (28 bits) - (CLKNslave - CLK) modulo 2^28
+ uint32_t clock_offset;
+ /// AFH_Channel_Map
+ struct chnl_map afh_ch_map;
+ /// LT_ADDR
+ uint8_t lt_addr;
+ /// Next_Broadcast_Instant (28 bits)
+ uint32_t next_bcst_instant;
+ /// Connectionless_Slave_Broadcast_Interval (in slots)
+ uint16_t csb_int;
+ /// Service_Data
+ uint8_t service_data;
+};
+
+/// HCI Connectionless Slave Broadcast Receive Event
+struct hci_con_slv_bcst_rec_evt
+{
+ /// BD_ADDR
+ struct bd_addr bd_addr;
+ /// LT_ADDR
+ uint8_t lt_addr;
+ /// CLK (28 bits)
+ uint32_t clk;
+ /// Offset (28 bits) - (CLKNslave - CLK) modulo 2^28
+ uint32_t offset;
+ /// Receive Status
+ uint8_t receive_status;
+ /// Fragment
+ uint8_t fragment;
+ /// Data_Length (in bytes)
+ uint8_t data_length;
+ /// Data
+ uint8_t data[__ARRAY_EMPTY];
+};
+
+/// HCI Connectionless Slave Broadcast Timeout Event
+struct hci_con_slv_bcst_to_evt
+{
+ /// BD_ADDR
+ struct bd_addr bd_addr;
+ /// LT_ADDR
+ uint8_t lt_addr;
+};
+
+/// HCI Connectionless Slave Broadcast Channel Map Change Event
+struct hci_con_slv_bcst_ch_map_chg_evt
+{
+ /// Channel_Map
+ struct chnl_map ch_map;
+};
+
+
+struct hci_le_generate_dhkey_cmp_evt
+{
+ ///LE Subevent code
+ uint8_t subcode;
+ uint8_t status;
+ uint8_t dh_key[32];
+};
+
+struct hci_le_generate_p256_public_key_cmp_evt
+{
+ ///LE Subevent code
+ uint8_t subcode;
+ uint8_t status;
+ t_public_key public_key;
+};
+
+/*
+ * HCI VENDOR SPECIFIC COMMANDS PARAMETERS
+ ****************************************************************************************
+ */
+
+/// Buffer structure
+struct buffer_tag
+{
+ /// length of buffer
+ uint8_t length;
+ /// data of 128 bytes length
+ uint8_t data[128];
+};
+
+/// Common structure for Command Complete Event of HCI Debug Read Memory/Flash/Param complete event parameters - vendor specific
+struct hci_dbg_basic_rd_data_cmd_cmp_evt
+{
+ ///Status
+ uint8_t status;
+ ///buffer structure to return
+ struct buffer_tag buf;
+};
+
+///HCI Debug read memory variable command parameters - vendor specific
+struct hci_dbg_rd_mem_cmd
+{
+ ///Start address to read
+ uint32_t start_addr;
+ ///Access size
+ uint8_t type;
+ ///Length to read
+ uint8_t length;
+};
+
+///HCI Debug write memory variable command parameters - vendor specific
+struct hci_dbg_wr_mem_cmd
+{
+ ///Start address to read
+ uint32_t start_addr;
+ ///Access size
+ uint8_t type;
+ ///buffer structure to return
+ struct buffer_tag buf;
+};
+
+///HCI Debug delete parameter command parameters - vendor specific
+struct hci_dbg_del_param_cmd
+{
+ ///Parameter tag
+ uint16_t param_tag;
+};
+
+///HCI Debug erase flash command parameters - vendor specific
+struct hci_dbg_er_flash_cmd
+{
+ ///Flash type
+ uint8_t flashtype;
+ ///Start offset address
+ uint32_t startoffset;
+ ///Size to erase
+ uint32_t size;
+};
+
+///HCI Debug write flash command parameters - vendor specific
+struct hci_dbg_wr_flash_cmd
+{
+ ///Flash type
+ uint8_t flashtype;
+ ///Start offset address
+ uint32_t startoffset;
+ ///buffer structure
+ struct buffer_tag buf;
+};
+
+///HCI Debug read flash command parameters - vendor specific
+struct hci_dbg_rd_flash_cmd
+{
+ ///Flash type
+ uint8_t flashtype;
+ ///Start offset address
+ uint32_t startoffset;
+ ///Size to read
+ uint8_t size;
+};
+
+///HCI Debug read parameter command parameters - vendor specific
+struct hci_dbg_rd_par_cmd
+{
+ ///Parameter tag
+ uint16_t param_tag;
+};
+
+///HCI Debug read parameters command parameters - vendor specific
+struct hci_dbg_wr_par_cmd
+{
+ ///Parameter tag
+ uint16_t param_tag;
+ ///Structure buffer
+ struct buffer_tag buf;
+};
+
+#if CRYPTO_UT
+struct hci_dbg_test_crypto_func_cmd
+{
+ /// Id of Function to be tested
+ uint8_t function;
+ /// Structure buffer
+ struct buffer_tag buf;
+};
+#endif //CRYPTO_UT
+
+///HCI Debug Read Kernel Statistics complete event parameters - vendor specific
+struct hci_dbg_rd_ke_stats_cmd_cmp_evt
+{
+ ///Status
+ uint8_t status;
+ ///Max message sent
+ uint8_t max_msg_sent;
+ ///Max message saved
+ uint8_t max_msg_saved;
+ ///Max timer used
+ uint8_t max_timer_used;
+ ///Max heap used
+ uint16_t max_heap_used;
+ ///Max stack used
+ uint16_t max_stack_used;
+};
+
+
+/// HCI Debug Read information about memory usage. - vendor specific
+struct hci_dbg_rd_mem_info_cmd_cmp_evt
+{
+ ///Status
+ uint8_t status;
+ /// memory size currently used into each heaps.
+ uint16_t mem_used[KE_MEM_BLOCK_MAX];
+ /// peak of memory usage measured
+ uint32_t max_mem_used;
+};
+
+///HCI Debug identify Flash command complete event parameters - vendor specific
+struct hci_dbg_id_flash_cmd_cmp_evt
+{
+ ///Status
+ uint8_t status;
+ ///Flash identity
+ uint8_t flash_id;
+};
+
+///HCI Debug RF Register read command
+struct hci_dbg_rf_reg_rd_cmd
+{
+ /// register address
+ uint16_t addr;
+};
+
+///HCI Debug RF Register read command complete event
+struct hci_dbg_rf_reg_rd_cmd_cmp_evt
+{
+ /// status
+ uint8_t status;
+ /// register address
+ uint16_t addr;
+ /// register value
+ uint32_t value;
+};
+
+///HCI Debug RF Register write command
+struct hci_dbg_rf_reg_wr_cmd
+{
+ /// register address
+ uint16_t addr;
+ /// register value
+ uint32_t value;
+};
+
+///HCI Debug RF Register write command complete event
+struct hci_dbg_rf_reg_wr_cmd_cmp_evt
+{
+ /// status
+ uint8_t status;
+ /// address
+ uint16_t addr;
+};
+
+///HCI Debug platform reset command parameters - vendor specific
+struct hci_dbg_plf_reset_cmd
+{
+ /// reason
+ uint8_t reason;
+};
+
+#if (RW_DEBUG && BT_EMB_PRESENT)
+/// Discard LMP Packets
+struct hci_dbg_bt_send_lmp_cmd
+{
+ /// Connection handle
+ uint16_t conhdl;
+ ///buffer structure to return
+ struct buffer_tag buf;
+};
+
+/// Discard LMP Packets
+struct hci_dbg_bt_discard_lmp_en_cmd
+{
+ /// Connection handle
+ uint16_t conhdl;
+ /// Enable/Disable LMP discard (0: disable / 1: enable)
+ uint8_t enable;
+};
+
+/// Set local clock
+struct hci_dbg_set_local_clock_cmd
+{
+ /// Clock (in half-slots)
+ uint32_t clock;
+};
+#endif //(RW_DEBUG && BT_EMB_PRESENT)
+
+#if (RW_WLAN_COEX)
+///HCI Debug wlan coexistence command parameters - vendor specific
+struct hci_dbg_wlan_coex_cmd
+{
+ /// State
+ uint8_t state;
+};
+#if (RW_WLAN_COEX_TEST)
+///HCI Debug wlan coexistence test scenario command parameters - vendor specific
+struct hci_dbg_wlan_coextst_scen_cmd
+{
+ /// Scenario
+ uint32_t scenario;
+};
+#endif //RW_WLAN_COEX_TEST
+#endif //RW_WLAN_COEX
+
+#if (RW_MWS_COEX)
+///HCI Debug mws coexistence command parameters - vendor specific
+struct hci_dbg_mws_coex_cmd
+{
+ /// State
+ uint8_t state;
+};
+#if (RW_MWS_COEX_TEST)
+///HCI Debug mws coexistence test scenario command parameters - vendor specific
+struct hci_dbg_mws_coextst_scen_cmd
+{
+ /// Scenario
+ uint32_t scenario;
+};
+#endif //RW_MWS_COEX_TEST
+#endif //RW_MWS_COEX
+
+///HCI Debug HW Register Read command parameters - vendor specific
+struct hci_dbg_hw_reg_rd_cmd
+{
+ /// register address
+ uint16_t reg_addr;
+};
+
+///HCI Debug HW Register write command parameters - vendor specific
+struct hci_dbg_hw_reg_wr_cmd
+{
+ /// register address
+ uint16_t reg_addr;
+ /// extra parameter
+ uint16_t reserved;
+ /// register value
+ uint32_t reg_value;
+};
+
+///HCI Debug HW Register Read Complete event parameters - vendor specific
+struct hci_dbg_hw_reg_rd_cmd_cmp_evt
+{
+ /// status
+ uint8_t status;
+ /// register address
+ uint16_t reg_addr;
+ /// register value
+ uint32_t reg_value;
+};
+
+///HCI Debug HW Register Write Complete event parameters - vendor specific
+struct hci_dbg_hw_reg_wr_cmd_cmp_evt
+{
+ /// status
+ uint8_t status;
+ /// register address
+ uint16_t reg_addr;
+};
+
+///HCI Debug write DLE default value command parameters - vendor specific
+struct hci_dbg_wr_dle_dft_value_cmd
+{
+ /// Max transmit packet size supported
+ uint16_t suppted_max_tx_octets;
+ /// Max transmit packet time supported
+ uint16_t suppted_max_tx_time;
+ /// Max receive packet size supported
+ uint16_t suppted_max_rx_octets;
+ /// Max receive packet time supported
+ uint16_t suppted_max_rx_time;
+
+};
+
+#if (BLE_EMB_PRESENT || BLE_HOST_PRESENT)
+///HCI Debug bd address write command parameters - vendor specific
+struct hci_dbg_set_bd_addr_cmd
+{
+ ///bd address to set
+ struct bd_addr addr;
+};
+
+///HCI Debug crc write command parameters - vendor specific
+struct hci_dbg_set_crc_cmd
+{
+ /// Handle pointing to the connection for which CRC has to be modified
+ uint16_t conhdl;
+ /// CRC to set
+ struct crc_init crc;
+};
+
+///HCI Debug LLC discard command parameters - vendor specific
+struct hci_dbg_llcp_discard_cmd
+{
+ /// Handle pointing to the connection for which LLCP commands have to be discarded
+ uint16_t conhdl;
+ /// Flag indicating if the discarding has to be enabled or disabled
+ uint8_t enable;
+};
+
+///HCI Debug reset RX counter command parameters - vendor specific
+struct hci_dbg_reset_rx_cnt_cmd
+{
+ /// Handle pointing to the connection for which the counter have to be reseted
+ uint16_t conhdl;
+};
+
+///HCI Debug reset TX counter command parameters - vendor specific
+struct hci_dbg_reset_tx_cnt_cmd
+{
+ /// Handle pointing to the connection for which the counter have to be reseted
+ uint16_t conhdl;
+};
+
+///HCI Debug Set TX Power Level Command parameters
+struct hci_dbg_set_tx_pw_cmd
+{
+ /// Connection handle
+ uint16_t conhdl;
+ /// Power level
+ uint8_t pw_lvl;
+};
+
+///HCI Debug configure audio command parameters - vendor specific
+
+struct hci_vs_audio_configure_cmd
+{
+ /// Connection handle
+ uint16_t conhdl;
+ /// Voice channel to be updated
+ uint8_t voice_channel;
+ /// Configure transmitter size in bytes
+ uint8_t tx_size;
+ /// Configure receiver size in bytes
+ uint8_t rx_size;
+ /// Configure transmitter rate
+ uint8_t tx_rate;
+ /// Configure receiver rate
+ uint8_t rx_rate;
+ /// Configure number of retransmission
+ uint8_t nb_retx;
+ /// Audio link priority
+ uint8_t priority;
+ /// Encryption mode
+ uint8_t enc_mode;
+ /// Channel and mute configuration (@see enum audio_cfg)
+ uint8_t chan_mute_cfg;
+ /// Mute Pattern
+ uint8_t mute_pattern;
+ /// Audio interval in frame
+ uint16_t interval;
+};
+
+struct hci_vs_audio_set_pointer_cmd
+{
+ /// Connection handle
+ uint16_t conhdl;
+ /// Voice channel to be updated
+ uint8_t voice_channel;
+ /// Rx or Tx selection
+ uint8_t rx_tx_select;
+ /// Tog to be updated
+ uint8_t tog;
+ /// Exchange memory pointer
+ uint16_t em_ptr;
+};
+///HCI Debug set audio mode command parameters - vendor specific.
+struct hci_vs_audio_set_mode_cmd
+{
+ /// Connection handle
+ uint16_t conhdl;
+ /// Voice channel to be updated
+ uint8_t voice_channel;
+ /// Mode
+ uint8_t mode;
+};
+
+///HCI Debug set audio mode command parameters - vendor specific
+struct hci_vs_audio_reset_cmd
+{
+ /// Connection handle
+ uint16_t conhdl;
+ /// Voice channel to be updated
+ uint8_t voice_channel;
+};
+
+///HCI Debug set audio mode command parameters - vendor specific
+struct hci_vs_audio_allocate_cmd
+{
+ /// Connection handle
+ uint16_t conhdl;
+};
+
+///HCI Debug get audio buffer range - vendor specific
+struct hci_vs_audio_get_buffer_range_cmd
+{
+ /// Rx or Tx selection
+ uint8_t rx_tx_select;
+};
+
+
+///HCI VS basic command complete event - vendor specific
+struct hci_vs_audio_cmd_cmp_evt
+{
+ /// status
+ uint8_t status;
+ /// Connection handle
+ uint16_t conhdl;
+};
+
+
+///HCI Debug allocate audio voice channel complete event - vendor specific
+struct hci_vs_audio_allocate_cmd_cmp_evt
+{
+ /// status
+ uint8_t status;
+ /// Connection handle
+ uint16_t conhdl;
+ /// voice channel allocated
+ uint8_t voice_channel;
+};
+
+///HCI Debug get audio buffer range complete event - vendor specific
+struct hci_vs_audio_get_buffer_range_cmd_cmp_evt
+{
+ /// status
+ uint8_t status;
+ /// start address
+ uint32_t base_address;
+ /// end address
+ uint32_t end_address;
+};
+#if (BLE_TESTER)
+///HCI Tester set LE parameters
+struct hci_tester_set_le_params_cmd
+{
+ /// Connection handle
+ uint16_t conhdl;
+ /// Tester features
+ uint8_t tester_feats;
+ /// Preferred periodicity
+ uint8_t pref_period;
+ /// Offset0
+ uint16_t offset0;
+ /// Offset1
+ uint16_t offset1;
+ /// Offset2
+ uint16_t offset2;
+ /// Offset3
+ uint16_t offset3;
+ /// Offset4
+ uint16_t offset4;
+ /// Offset5
+ uint16_t offset5;
+};
+
+/// HCI BLE Tester: enable LLCP pass through mechanism
+struct hci_dbg_ble_tst_llcp_pt_en_cmd
+{
+ /// Connection handle
+ uint16_t conhdl;
+ /// Enable or not LLCP pass through mechanism
+ uint8_t enable;
+};
+
+/// HCI BLE Tester: send an LLCP PDU
+struct hci_dbg_ble_tst_send_llcp_cmd
+{
+ /// Connection handle
+ uint16_t conhdl;
+ /// length of LLCP PDU
+ uint8_t length;
+ /// LLCP PDU data
+ uint8_t data[26];
+};
+
+
+/// HCI DBG Meta Event trigg when LLCP message received with LLCP pass through mechanism
+struct hci_dbg_ble_tst_llcp_recv_evt
+{
+ ///DBG Subevent code
+ uint8_t subcode;
+ ///Connection handle
+ uint16_t conhdl;
+ /// length of LLCP message
+ uint8_t length;
+ /// LLCP data
+ uint8_t data[26];
+};
+
+#endif //(BLE_TESTER)
+
+#endif //BLE_EMB_PRESENT || BLE_HOST_PRESENT
+
+#if (RW_DEBUG)
+/// HCI DBG Meta Event indicating a SW assertion error
+struct hci_dbg_assert_err_evt
+{
+ ///DBG Subevent code
+ uint8_t subcode;
+ /// Line number
+ uint32_t line;
+ /// Param0
+ uint32_t param0;
+ /// Param1
+ uint32_t param1;
+ /// File name
+ uint8_t file[__ARRAY_EMPTY];
+};
+#endif //(RW_DEBUG)
+
+
+/// @} CO_BT
+#endif // CO_HCI_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_list.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_list.h
new file mode 100644
index 0000000000..4b520f33d0
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_list.h
@@ -0,0 +1,290 @@
+/**
+ ****************************************************************************************
+ *
+ * @file co_list.h
+ *
+ * @brief Common list structures definitions
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef _CO_LIST_H_
+#define _CO_LIST_H_
+
+/**
+ *****************************************************************************************
+ * @defgroup CO_LIST List management
+ * @ingroup COMMON
+ *
+ * @brief List management.
+ *
+ * This module contains the list structures and handling functions.
+ * @{
+ *****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include // standard definition
+#include // boolean definition
+#include // for NULL and size_t
+#include "rwip_config.h" // stack configuration
+#include "ble_arch.h"
+//#include "core_cm0.h" // for __INLINE
+
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+///list type
+enum
+{
+ POOL_LINKED_LIST = 0x00,
+ RING_LINKED_LIST,
+ LINK_TYPE_END
+};
+
+/// structure of a list element header
+struct co_list_hdr
+{
+ /// Pointer to next co_list_hdr
+ struct co_list_hdr *next;
+};
+
+/// structure of a list
+struct co_list
+{
+ /// pointer to first element of the list
+ struct co_list_hdr *first;
+ /// pointer to the last element
+ struct co_list_hdr *last;
+
+ #if (KE_PROFILING)
+ /// number of element in the list
+ uint32_t cnt;
+ /// max number of element in the list
+ uint32_t maxcnt;
+ /// min number of element in the list
+ uint32_t mincnt;
+ #endif //KE_PROFILING
+};
+
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+/**
+ ****************************************************************************************
+ * @brief Initialize a list to defaults values.
+ *
+ * @param list Pointer to the list structure.
+ ****************************************************************************************
+ */
+void co_list_init(struct co_list *list);
+
+/**
+ ****************************************************************************************
+ * @brief Initialize a pool to default values, and initialize the relative free list.
+ *
+ * @param list Pointer to the list structure
+ * @param pool Pointer to the pool to be initialized
+ * @param elmt_size Size of one element of the pool
+ * @param elmt_cnt Nb of elements available in the pool
+ * @param default_value Pointer to the default value of each element (may be NULL)
+ * @param list_type Determine if the it is a ring list or not
+ *
+ ****************************************************************************************
+ */
+void co_list_pool_init(struct co_list *list,
+ void *pool,
+ size_t elmt_size,
+ uint32_t elmt_cnt,
+ void *default_value,
+ uint8_t list_type);
+
+/**
+ ****************************************************************************************
+ * @brief Add an element as last on the list.
+ *
+ * @param list Pointer to the list structure
+ * @param list_hdr Pointer to the header to add at the end of the list
+ *
+ ****************************************************************************************
+ */
+void co_list_push_back(struct co_list *list, struct co_list_hdr *list_hdr);
+
+/**
+ ****************************************************************************************
+ * @brief Add an element as first on the list.
+ *
+ * @param list Pointer to the list structure
+ * @param list_hdr Pointer to the header to add at the beginning of the list
+ ****************************************************************************************
+ */
+void co_list_push_front(struct co_list *list, struct co_list_hdr *list_hdr);
+
+/**
+ ****************************************************************************************
+ * @brief Extract the first element of the list.
+ * @param list Pointer to the list structure
+ * @return The pointer to the element extracted, and NULL if the list is empty.
+ ****************************************************************************************
+ */
+struct co_list_hdr *co_list_pop_front(struct co_list *list);
+
+/**
+ ****************************************************************************************
+ * @brief Search for a given element in the list, and extract it if found.
+ *
+ * @param list Pointer to the list structure
+ * @param list_hdr Element to extract
+ * @param nb_following Number of following elements to extract
+ *
+ * @return true if the element is found in the list, false otherwise
+ ****************************************************************************************
+ */
+bool co_list_extract(struct co_list *list, struct co_list_hdr *list_hdr, uint8_t nb_following);
+
+/**
+ ****************************************************************************************
+ * @brief Extract an element when the previous element is known
+ *
+ * Note: the element to remove shall follow immediately the reference within the list
+ *
+ * @param list Pointer to the list structure
+ * @param elt_ref_hdr Pointer to the referenced element (NULL if element to extract is the first in the list)
+ * @param elt_to_rem_hdr Pointer to the element to be extracted
+ ****************************************************************************************
+ */
+void co_list_extract_after(struct co_list *list, struct co_list_hdr *elt_ref_hdr, struct co_list_hdr *elt_to_rem_hdr);
+
+/**
+ ****************************************************************************************
+ * @brief Searched a given element in the list.
+ *
+ * @param list Pointer to the list structure
+ * @param list_hdr Pointer to the searched element
+ *
+ * @return true if the element is found in the list, false otherwise
+ ****************************************************************************************
+ */
+bool co_list_find(struct co_list *list, struct co_list_hdr *list_hdr);
+
+/**
+ ****************************************************************************************
+ * @brief Merge two lists in a single one.
+ *
+ * This function appends the list pointed by list2 to the list pointed by list1. Once the
+ * merge is done, it empties list2.
+ *
+ * @param list1 Pointer to the destination list
+ * @param list2 Pointer to the list to append to list1
+ ****************************************************************************************
+ */
+void co_list_merge(struct co_list *list1, struct co_list *list2);
+
+/**
+ ****************************************************************************************
+ * @brief Insert a given element in the list before the referenced element.
+ *
+ * @param list Pointer to the list structure
+ * @param elt_ref_hdr Pointer to the referenced element
+ * @param elt_to_add_hdr Pointer to the element to be inserted
+ *
+ * @return true if the element is found in the list, false otherwise
+ ****************************************************************************************
+ */
+void co_list_insert_before(struct co_list *list,
+ struct co_list_hdr *elt_ref_hdr, struct co_list_hdr *elt_to_add_hdr);
+
+/**
+ ****************************************************************************************
+ * @brief Insert a given element in the list after the referenced element.
+ *
+ * @param list Pointer to the list structure
+ * @param elt_ref_hdr Pointer to the referenced element
+ * @param elt_to_add_hdr Pointer to the element to be inserted
+ *
+ * @return true if the element is found in the list, false otherwise
+ ****************************************************************************************
+ */
+void co_list_insert_after(struct co_list *list,
+ struct co_list_hdr *elt_ref_hdr, struct co_list_hdr *elt_to_add_hdr);
+
+
+/**
+ ****************************************************************************************
+ * @brief Count number of elements present in the list
+ *
+ * @param list Pointer to the list structure
+ *
+ * @return Number of elements present in the list
+ ****************************************************************************************
+ */
+uint16_t co_list_size(struct co_list *list);
+
+/**
+ ****************************************************************************************
+ * @brief Check if there is enough element available in the list
+ *
+ * @param list Pointer to the list structure
+ * @param nb_elt_needed Number of element needed
+ *
+ * @return True if enough element are available in the list
+ ****************************************************************************************
+ */
+bool co_list_check_size_available(struct co_list *list, uint8_t nb_elt_needed);
+
+/**
+ ****************************************************************************************
+ * @brief Test if the list is empty.
+ * @param list Pointer to the list structure.
+ * @return true if the list is empty, false else otherwise.
+ ****************************************************************************************
+ */
+
+__INLINE bool co_list_is_empty(const struct co_list *const list)
+{
+ bool listempty;
+ listempty = (list->first == NULL);
+ return (listempty);
+}
+
+/**
+ ****************************************************************************************
+ * @brief Pick the first element from the list without removing it.
+ *
+ * @param list Pointer to the list structure.
+ *
+ * @return First element address. Returns NULL pointer if the list is empty.
+ ****************************************************************************************
+ */
+__INLINE struct co_list_hdr *co_list_pick(const struct co_list *const list)
+{
+ return(list->first);
+}
+
+
+/**
+ ****************************************************************************************
+ * @brief Return following element of a list element.
+ *
+ * @param list_hdr Pointer to the list element.
+ *
+ * @return The pointer to the next element.
+ ****************************************************************************************
+ */
+__INLINE struct co_list_hdr *co_list_next(const struct co_list_hdr *const list_hdr)
+{
+ return(list_hdr->next);
+}
+
+/// @} CO_LIST
+#endif // _CO_LIST_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_llcp.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_llcp.h
new file mode 100644
index 0000000000..3afa3579c1
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_llcp.h
@@ -0,0 +1,431 @@
+/**
+ ****************************************************************************************
+ *
+ * @file co_llcp.h
+ *
+ * @brief This file contains the LLCP Bluetooth defines, enumerations and structures
+ * definitions for use by all modules in RW stack.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ ****************************************************************************************
+ */
+
+#ifndef CO_LLCP_H_
+#define CO_LLCP_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup CO_BT
+ * @{
+ ****************************************************************************************
+ */
+
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "co_bt.h"
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+#define LLCP_OPCODE_MASK (0xFF)
+#define LLCP_OPCODE_POS (0)
+/*
+ * TYPE DEFINITIONS
+ ****************************************************************************************
+ */
+/// Control packet opcode
+enum co_llcp_opcode
+{
+ /// Connection update request
+ LLCP_CONNECTION_UPDATE_IND_OPCODE,
+ /// Channel map request
+ LLCP_CHANNEL_MAP_IND_OPCODE,
+ /// Termination indication
+ LLCP_TERMINATE_IND_OPCODE,
+ /// Encryption request
+ LLCP_ENC_REQ_OPCODE,
+ /// Encryption response
+ LLCP_ENC_RSP_OPCODE,
+ /// Start encryption request
+ LLCP_START_ENC_REQ_OPCODE,
+ /// Start encryption response
+ LLCP_START_ENC_RSP_OPCODE,
+ /// Unknown response
+ LLCP_UNKNOWN_RSP_OPCODE,
+ /// Feature request
+ LLCP_FEATURE_REQ_OPCODE,
+ /// Feature response
+ LLCP_FEATURE_RSP_OPCODE,
+ /// Pause encryption request
+ LLCP_PAUSE_ENC_REQ_OPCODE,
+ /// Pause encryption response
+ LLCP_PAUSE_ENC_RSP_OPCODE,
+ /// Version indication
+ LLCP_VERSION_IND_OPCODE,
+ /// Reject indication
+ LLCP_REJECT_IND_OPCODE,
+#if !(BLE_QUALIF)
+ /// Slave feature request
+ LLCP_SLAVE_FEATURE_REQ_OPCODE,
+ /// Connection parameters request
+ LLCP_CONNECTION_PARAM_REQ_OPCODE,
+ /// Connection parameters response
+ LLCP_CONNECTION_PARAM_RSP_OPCODE,
+ /// Reject indication extended
+ LLCP_REJECT_IND_EXT_OPCODE,
+ /// Ping request
+ LLCP_PING_REQ_OPCODE,
+ /// Ping response
+ LLCP_PING_RSP_OPCODE,
+ /// Length request
+ LLCP_LENGTH_REQ_OPCODE,
+ /// Length response
+ LLCP_LENGTH_RSP_OPCODE,
+#endif // !(BLE_QUALIF)
+ /// Opcode length
+ LLCP_OPCODE_MAX_OPCODE,
+
+ #if (BLE_TESTER)
+ LLCP_OPCODE_DEBUG = 0xFF,
+ #endif // (BLE_TESTER)
+};
+
+/// PDU lengths (including opcode)
+enum co_llcp_length
+{
+ LLCP_CON_REQ_LEN = 34,
+ LLCP_CON_UPD_IND_LEN = 12,
+ LLCP_CH_MAP_REQ_LEN = 8,
+ LLCP_TERM_IND_LEN = 2,
+ LLCP_ENC_REQ_LEN = 23,
+ LLCP_ENC_RSP_LEN = 13,
+ LLCP_ST_ENC_REQ_LEN = 1,
+ LLCP_ST_ENC_RSP_LEN = 1,
+ LLCP_UNKN_RSP_LEN = 2,
+ LLCP_FEAT_REQ_LEN = 9,
+ LLCP_FEAT_RSP_LEN = 9,
+ LLCP_PA_ENC_REQ_LEN = 1,
+ LLCP_PA_ENC_RSP_LEN = 1,
+ LLCP_VERS_IND_LEN = 6,
+ LLCP_REJ_IND_LEN = 2,
+ LLCP_SLAVE_FEATURE_REQ_LEN = 9,
+ LLCP_REJECT_IND_EXT_LEN = 3,
+ LLCP_CON_PARAM_REQ_LEN = 24,
+ LLCP_CON_PARAM_RSP_LEN = 24,
+ LLCP_PING_REQ_LEN = 1,
+ LLCP_PING_RSP_LEN = 1,
+ LLCP_LENGTH_REQ_LEN = 9,
+ LLCP_LENGTH_RSP_LEN = 9,
+ LLCP_PDU_LENGTH_MAX = 34
+};
+
+/*
+ * MESSAGES
+ ****************************************************************************************
+ */
+
+
+/// LLCP_CONNECTION_UPDATE_REQ structure.
+struct llcp_con_upd_ind
+{
+ /// opcode
+ uint8_t opcode;
+ /// window size
+ uint8_t win_size;
+ /// window offset
+ uint16_t win_off;
+ /// interval
+ uint16_t interv;
+ /// latency
+ uint16_t latency;
+ /// timeout
+ uint16_t timeout;
+ /// instant
+ uint16_t instant;
+};
+
+/// LLCP_CHANNEL_MAP_IND structure.
+struct llcp_channel_map_ind
+{
+ /// opcode
+ uint8_t opcode;
+ /// channel mapping
+ struct le_chnl_map ch_map;
+ /// instant
+ uint16_t instant;
+};
+
+/// LLCP_TERMINATE_IND structure.
+struct llcp_terminate_ind
+{
+ /// opcode
+ uint8_t opcode;
+ /// termination code
+ uint8_t err_code;
+};
+
+/// LLCP_ENC_REQ structure.
+struct llcp_enc_req
+{
+ /// opcode
+ uint8_t opcode;
+ /// random value
+ struct rand_nb rand;
+ /// ediv
+ uint8_t ediv[2];
+ /// skdm
+ struct sess_k_div_x skdm;
+ /// ivm
+ struct init_vect ivm;
+};
+
+/// LLCP_ENC_RSP structure.
+struct llcp_enc_rsp
+{
+ /// opcode
+ uint8_t opcode;
+ /// skds
+ struct sess_k_div_x skds;
+ /// ivs
+ struct init_vect ivs;
+};
+
+/// LLCP_START_ENC_REQ structure.
+struct llcp_start_enc_req
+{
+ /// opcode
+ uint8_t opcode;
+};
+
+/// LLCP_START_ENC_RSP structure.
+struct llcp_start_enc_rsp
+{
+ /// opcode
+ uint8_t opcode;
+};
+
+/// LLCP_UNKNOWN_RSP structure.
+struct llcp_unknown_rsp
+{
+ /// opcode
+ uint8_t opcode;
+ /// unknown type
+ uint8_t unk_type;
+};
+
+/// LLCP_FEATURE_REQ structure.
+struct llcp_feats_req
+{
+ /// opcode
+ uint8_t opcode;
+ /// le features
+ struct le_features feats;
+};
+
+/// LLCP_FEATURE_RSP structure.
+struct llcp_feats_rsp
+{
+ /// opcode
+ uint8_t opcode;
+ /// le features
+ struct le_features feats;
+};
+
+/// LLCP_PAUSE_ENC_REQ structure.
+struct llcp_pause_enc_req
+{
+ /// opcode
+ uint8_t opcode;
+};
+
+/// LLCP_PAUSE_ENC_RSP structure.
+struct llcp_pause_enc_rsp
+{
+ /// opcode
+ uint8_t opcode;
+};
+
+/// LLCP_VERS_IND structure
+struct llcp_vers_ind
+{
+ /// opcode
+ uint8_t opcode;
+ /// version
+ uint8_t vers;
+ /// company id
+ uint16_t compid;
+ /// sub version
+ uint16_t subvers;
+};
+
+/// LLCP_REJECT_IND structure.
+struct llcp_reject_ind
+{
+ /// opcode
+ uint8_t opcode;
+ /// reject reason
+ uint8_t err_code;
+};
+
+/// LLCP_SLAVE_FEATURE_REQ structure.
+struct llcp_slave_feature_req
+{
+ /// opcode
+ uint8_t opcode;
+ /// le features
+ struct le_features feats;
+};
+
+/// LLCP_CONNECTION_PARAM_REQ structure.
+struct llcp_con_param_req
+{
+ /// opcode
+ uint8_t opcode;
+ /// minimum value of connInterval
+ uint16_t interval_min;
+ /// maximum value of connInterval
+ uint16_t interval_max;
+ /// connSlaveLatency value
+ uint16_t latency;
+ /// connSupervisionTimeout value
+ uint16_t timeout;
+ /// preferred periodicity
+ uint8_t pref_period;
+ /// ReferenceConnEventCount
+ uint16_t ref_con_event_count;
+ /// Offset0
+ uint16_t offset0;
+ /// Offset1
+ uint16_t offset1;
+ /// Offset2
+ uint16_t offset2;
+ /// Offset3
+ uint16_t offset3;
+ /// Offset4
+ uint16_t offset4;
+ /// Offset5
+ uint16_t offset5;
+};
+
+/// LLCP_CONNECTION_PARAM_RSP structure.
+struct llcp_con_param_rsp
+{
+ /// opcode
+ uint8_t opcode;
+ /// minimum value of connInterval
+ uint16_t interval_min;
+ /// maximum value of connInterval
+ uint16_t interval_max;
+ /// connSlaveLatency value
+ uint16_t latency;
+ /// connSupervisionTimeout value
+ uint16_t timeout;
+ /// preferred periodicity
+ uint8_t pref_period;
+ /// ReferenceConnEventCount
+ uint16_t ref_con_event_count;
+ /// Offset0
+ uint16_t offset0;
+ /// Offset1
+ uint16_t offset1;
+ /// Offset2
+ uint16_t offset2;
+ /// Offset3
+ uint16_t offset3;
+ /// Offset4
+ uint16_t offset4;
+ /// Offset5
+ uint16_t offset5;
+};
+
+/// LLCP_REJECT_IND structure.
+struct llcp_reject_ind_ext
+{
+ /// opcode
+ uint8_t opcode;
+ /// rejected opcode
+ uint8_t rej_opcode;
+ /// reject reason
+ uint8_t err_code;
+};
+
+/// LLCP_PING_REQ structure.
+struct llcp_ping_req
+{
+ /// opcode
+ uint8_t opcode;
+};
+
+/// LLCP_PING_RSP structure.
+struct llcp_ping_rsp
+{
+ /// opcode
+ uint8_t opcode;
+};
+
+/// LLCP_LENGTH_REQ structure.
+struct llcp_length_req
+{
+ /// opcode
+ uint8_t opcode;
+ /// The max size in reception
+ uint16_t max_rx_octets;
+ /// The max time in reception
+ uint16_t max_rx_time;
+ /// The max size in transmission
+ uint16_t max_tx_octets;
+ /// The max time in transmission
+ uint16_t max_tx_time;
+};
+
+/// LLCP_LENGTH_RSP structure.
+struct llcp_length_rsp
+{
+ /// opcode
+ uint8_t opcode;
+ /// The max size in reception
+ uint16_t max_rx_octets;
+ /// The max time in reception
+ uint16_t max_rx_time;
+ /// The max size in transmission
+ uint16_t max_tx_octets;
+ /// The max time in transmission
+ uint16_t max_tx_time;
+};
+
+/// LLCP pdu format
+union llcp_pdu
+{
+ /// opcode
+ uint8_t opcode;
+
+ struct llcp_con_upd_ind con_up_req;
+ struct llcp_channel_map_ind channel_map_req;
+ struct llcp_terminate_ind terminate_ind;
+ struct llcp_enc_req enc_req;
+ struct llcp_enc_rsp enc_rsp;
+ struct llcp_start_enc_req start_enc_req;
+ struct llcp_start_enc_rsp start_enc_rsp;
+ struct llcp_unknown_rsp unknown_rsp;
+ struct llcp_feats_req feats_req;
+ struct llcp_feats_rsp feats_rsp;
+ struct llcp_pause_enc_req pause_enc_req;
+ struct llcp_pause_enc_rsp pause_enc_rsp;
+ struct llcp_vers_ind vers_ind;
+ struct llcp_reject_ind reject_ind;
+ struct llcp_slave_feature_req slave_feature_req;
+ struct llcp_con_param_req con_param_req;
+ struct llcp_con_param_rsp con_param_rsp;
+ struct llcp_reject_ind_ext reject_ind_ext;
+ struct llcp_ping_req ping_req;
+ struct llcp_ping_rsp ping_rsp;
+ struct llcp_length_req length_req;
+ struct llcp_length_rsp length_rsp;
+};
+
+/// @} CO_BT
+#endif // CO_LLCP_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_lmp.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_lmp.h
new file mode 100644
index 0000000000..f0912f57bf
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_lmp.h
@@ -0,0 +1,1238 @@
+/**
+ ****************************************************************************************
+ *
+ * @file co_lmp.h
+ *
+ * @brief This file contains the HCI Bluetooth defines, enumerations and structures
+ * definitions for use by all modules in RW stack.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ ****************************************************************************************
+ */
+
+#ifndef CO_LMP_H_
+#define CO_LMP_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup CO_BT
+ * @{
+ ****************************************************************************************
+ */
+
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "co_bt.h"
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+//LMP Opcodes
+#define LMP_NAME_REQ_OPCODE 1
+#define LMP_NAME_RES_OPCODE 2
+#define LMP_ACCEPTED_OPCODE 3
+#define LMP_NOT_ACCEPTED_OPCODE 4
+#define LMP_CLK_OFF_REQ_OPCODE 5
+#define LMP_CLK_OFF_RES_OPCODE 6
+#define LMP_DETACH_OPCODE 7
+#define LMP_INRAND_OPCODE 8
+#define LMP_COMBKEY_OPCODE 9
+#define LMP_UNITKEY_OPCODE 10
+#define LMP_AURAND_OPCODE 11
+#define LMP_SRES_OPCODE 12
+#define LMP_TEMPRAND_OPCODE 13
+#define LMP_TEMPKEY_OPCODE 14
+#define LMP_ENC_MODE_REQ_OPCODE 15
+#define LMP_ENC_KEY_SIZE_REQ_OPCODE 16
+#define LMP_START_ENC_REQ_OPCODE 17
+#define LMP_STOP_ENC_REQ_OPCODE 18
+#define LMP_SWITCH_REQ_OPCODE 19
+#define LMP_HOLD_OPCODE 20
+#define LMP_HOLD_REQ_OPCODE 21
+#define LMP_SNIFF_REQ_OPCODE 23
+#define LMP_UNSNIFF_REQ_OPCODE 24
+#define LMP_PARK_REQ_OPCODE 25
+#define LMP_SET_BSWIN_OPCODE 27
+#define LMP_MODIF_BEACON_OPCODE 28
+#define LMP_UNPARK_BD_REQ_OPCODE 29
+#define LMP_UNPARK_PM_REQ_OPCODE 30
+#define LMP_INCR_PWR_REQ_OPCODE 31
+#define LMP_DECR_PWR_REQ_OPCODE 32
+#define LMP_MAX_PWR_OPCODE 33
+#define LMP_MIN_PWR_OPCODE 34
+#define LMP_AUTO_RATE_OPCODE 35
+#define LMP_PREF_RATE_OPCODE 36
+#define LMP_VER_REQ_OPCODE 37
+#define LMP_VER_RES_OPCODE 38
+#define LMP_FEATS_REQ_OPCODE 39
+#define LMP_FEATS_RES_OPCODE 40
+#define LMP_QOS_OPCODE 41
+#define LMP_QOS_REQ_OPCODE 42
+#define LMP_SCO_LINK_REQ_OPCODE 43
+#define LMP_RMV_SCO_LINK_REQ_OPCODE 44
+#define LMP_MAX_SLOT_OPCODE 45
+#define LMP_MAX_SLOT_REQ_OPCODE 46
+#define LMP_TIMING_ACCU_REQ_OPCODE 47
+#define LMP_TIMING_ACCU_RES_OPCODE 48
+#define LMP_SETUP_CMP_OPCODE 49
+#define LMP_USE_SEMI_PERM_KEY_OPCODE 50
+#define LMP_HOST_CON_REQ_OPCODE 51
+#define LMP_SLOT_OFF_OPCODE 52
+#define LMP_PAGE_MODE_REQ_OPCODE 53
+#define LMP_PAGE_SCAN_MODE_REQ_OPCODE 54
+#define LMP_SUPV_TO_OPCODE 55
+#define LMP_TEST_ACTIVATE_OPCODE 56
+#define LMP_TEST_CTRL_OPCODE 57
+#define LMP_ENC_KEY_SIZE_MASK_REQ_OPCODE 58
+#define LMP_ENC_KEY_SIZE_MASK_RES_OPCODE 59
+#define LMP_SET_AFH_OPCODE 60
+#define LMP_ENCAPS_HDR_OPCODE 61
+#define LMP_ENCAPS_PAYL_OPCODE 62
+#define LMP_SP_CFM_OPCODE 63
+#define LMP_SP_NB_OPCODE 64
+#define LMP_DHKEY_CHK_OPCODE 65
+#define LMP_PAUSE_ENC_AES_REQ_OPCODE 66
+
+#define LMP_ESC1_OPCODE 124
+#define LMP_ESC2_OPCODE 125
+#define LMP_ESC3_OPCODE 126
+#define LMP_ESC4_OPCODE 127
+
+///LMP Escape 4 Extended Opcodes
+#define LMP_ACCEPTED_EXT_EXTOPCODE 1
+#define LMP_NOT_ACCEPTED_EXT_EXTOPCODE 2
+#define LMP_FEATS_REQ_EXT_EXTOPCODE 3
+#define LMP_FEATS_RES_EXT_EXTOPCODE 4
+#define LMP_CLK_ADJ_EXTOPCODE 5
+#define LMP_CLK_ADJ_ACK_EXTOPCODE 6
+#define LMP_CLK_ADJ_REQ_EXTOPCODE 7
+#define LMP_PKT_TYPE_TBL_REQ_EXTOPCODE 11
+#define LMP_ESCO_LINK_REQ_EXTOPCODE 12
+#define LMP_RMV_ESCO_LINK_REQ_EXTOPCODE 13
+#define LMP_CH_CLASS_REQ_EXTOPCODE 16
+#define LMP_CH_CLASS_EXTOPCODE 17
+#define LMP_SSR_REQ_EXTOPCODE 21
+#define LMP_SSR_RES_EXTOPCODE 22
+#define LMP_PAUSE_ENC_REQ_EXTOPCODE 23
+#define LMP_RESUME_ENC_REQ_EXTOPCODE 24
+#define LMP_IO_CAP_REQ_EXTOPCODE 25
+#define LMP_IO_CAP_RES_EXTOPCODE 26
+#define LMP_NUM_COMPARISON_FAIL_EXTOPCODE 27
+#define LMP_PASSKEY_FAIL_EXTOPCODE 28
+#define LMP_OOB_FAIL_EXTOPCODE 29
+#define LMP_KEYPRESS_NOTIF_EXTOPCODE 30
+#define LMP_PWR_CTRL_REQ_EXTOPCODE 31
+#define LMP_PWR_CTRL_RES_EXTOPCODE 32
+#define LMP_PING_REQ_EXTOPCODE 33
+#define LMP_PING_RES_EXTOPCODE 34
+
+/// PDU lengths (including opcode)
+#define LMP_NAME_REQ_LEN 2
+#define LMP_NAME_RES_LEN 17
+#define LMP_ACCEPTED_LEN 2
+#define LMP_NOT_ACCEPTED_LEN 3
+#define LMP_CLK_OFF_REQ_LEN 1
+#define LMP_CLK_OFF_RES_LEN 3
+#define LMP_DETACH_LEN 2
+#define LMP_INRAND_LEN 17
+#define LMP_COMBKEY_LEN 17
+#define LMP_UNITKEY_LEN 17
+#define LMP_AURAND_LEN 17
+#define LMP_SRES_LEN 5
+#define LMP_TEMPRAND_LEN 17
+#define LMP_TEMPKEY_LEN 17
+#define LMP_ENC_MODE_REQ_LEN 2
+#define LMP_ENC_KEY_SIZE_REQ_LEN 2
+#define LMP_START_ENC_REQ_LEN 17
+#define LMP_STOP_ENC_REQ_LEN 1
+#define LMP_SWITCH_REQ_LEN 5
+#define LMP_HOLD_LEN 7
+#define LMP_HOLD_REQ_LEN 7
+#define LMP_SNIFF_REQ_LEN 10
+#define LMP_UNSNIFF_REQ_LEN 1
+#define LMP_PARK_REQ_LEN 17
+#define LMP_INCR_PWR_REQ_LEN 2
+#define LMP_DECR_PWR_REQ_LEN 2
+#define LMP_MAX_PWR_LEN 1
+#define LMP_MIN_PWR_LEN 1
+#define LMP_AUTO_RATE_LEN 1
+#define LMP_PREF_RATE_LEN 2
+#define LMP_VER_REQ_LEN 6
+#define LMP_VER_RES_LEN 6
+#define LMP_FEATS_REQ_LEN 9
+#define LMP_FEATS_RES_LEN 9
+#define LMP_QOS_LEN 4
+#define LMP_QOS_REQ_LEN 4
+#define LMP_SCO_LINK_REQ_LEN 7
+#define LMP_RMV_SCO_LINK_REQ_LEN 3
+#define LMP_MAX_SLOT_LEN 2
+#define LMP_MAX_SLOT_REQ_LEN 2
+#define LMP_TIMING_ACCU_REQ_LEN 1
+#define LMP_TIMING_ACCU_RES_LEN 3
+#define LMP_SETUP_CMP_LEN 1
+#define LMP_USE_SEMI_PERM_KEY_LEN 1
+#define LMP_HOST_CON_REQ_LEN 1
+#define LMP_SLOT_OFF_LEN 9
+#define LMP_PAGE_MODE_REQ_LEN 3
+#define LMP_PAGE_SCAN_MODE_REQ_LEN 3
+#define LMP_SUPV_TO_LEN 3
+#define LMP_TEST_ACTIVATE_LEN 1
+#define LMP_TEST_CTRL_LEN 10
+#define LMP_ENC_KEY_SIZE_MASK_REQ_LEN 1
+#define LMP_ENC_KEY_SIZE_MASK_RES_LEN 3
+#define LMP_SET_AFH_LEN 16
+#define LMP_ENCAPS_HDR_LEN 4
+#define LMP_ENCAPS_PAYL_LEN 17
+#define LMP_SP_CFM_LEN 17
+#define LMP_SP_NB_LEN 17
+#define LMP_DHKEY_CHK_LEN 17
+#define LMP_PAUSE_ENC_AES_REQ_LEN 17
+
+/// LMP Escape 4 Extended PDU length (including opcode and ext opcode)
+#define LMP_ACCEPTED_EXT_LEN 4
+#define LMP_NOT_ACCEPTED_EXT_LEN 5
+#define LMP_FEATS_REQ_EXT_LEN 12
+#define LMP_FEATS_RES_EXT_LEN 12
+#define LMP_CLK_ADJ_LEN 15
+#define LMP_CLK_ADJ_ACK_LEN 3
+#define LMP_CLK_ADJ_REQ_LEN 6
+#define LMP_PKT_TYPE_TBL_REQ_LEN 3
+#define LMP_ESCO_LINK_REQ_LEN 16
+#define LMP_RMV_ESCO_LINK_REQ_LEN 4
+#define LMP_CH_CLASS_REQ_LEN 7
+#define LMP_CH_CLASS_LEN 12
+#define LMP_SSR_REQ_LEN 9
+#define LMP_SSR_RES_LEN 9
+#define LMP_PAUSE_ENC_REQ_LEN 2
+#define LMP_RESUME_ENC_REQ_LEN 2
+#define LMP_IO_CAP_REQ_LEN 5
+#define LMP_IO_CAP_RES_LEN 5
+#define LMP_NUM_COMPARISON_FAIL_LEN 2
+#define LMP_PASSKEY_FAIL_LEN 2
+#define LMP_OOB_FAIL_LEN 2
+#define LMP_KEYPRESS_NOTIF_LEN 3
+#define LMP_PWR_CTRL_REQ_LEN 3
+#define LMP_PWR_CTRL_RES_LEN 3
+#define LMP_PING_REQ_LEN 2
+#define LMP_PING_RES_LEN 2
+
+/// Maximum LMP PDU size (including opcode and ext opcode)
+#define LMP_MAX_PDU_SIZE DM1_PACKET_SIZE
+
+/// Position of transaction ID in 1st byte
+#define LMP_TR_ID_POS 0
+#define LMP_TR_ID_MASK 0x01
+/// Position of opcode in 1st byte
+#define LMP_OPCODE_POS 1
+#define LMP_OPCODE_MASK 0xFE
+
+#define LMP_OPCODE(opcode, tr_id) (((opcode << LMP_OPCODE_POS) & LMP_OPCODE_MASK) | ((tr_id << LMP_TR_ID_POS) & LMP_TR_ID_MASK))
+/*
+ * MESSAGES
+ ****************************************************************************************
+ */
+
+///LMP_name_req PDU structure
+struct lmp_name_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Offset
+ uint8_t offset;
+};
+
+///LMP_name_res PDU structure
+struct lmp_name_res
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Offset
+ uint8_t offset;
+ ///Name Length
+ uint8_t length;
+ ///Name Fragment
+ struct name_vect name_frag;
+};
+
+///LMP_accepted PDU structure
+struct lmp_accepted
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Opcode of the original LMP
+ uint8_t orig_opcode;
+};
+
+///LMP_not_accepted PDU structure
+struct lmp_not_accepted
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Opcode of the original LMP
+ uint8_t orig_opcode;
+ ///Reason for not accepting the PDU (error code)
+ uint8_t reason;
+};
+
+///LMP_clkoffset_req PDU structure
+struct lmp_clk_off_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+};
+
+///LMP_clkoffset_res PDU structure
+struct lmp_clk_off_res
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Clock Offset value
+ uint16_t clk_offset ;
+};
+
+///LMP_detach PDU structure
+struct lmp_detach
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Reason to detach
+ uint8_t reason;
+};
+
+///LMP_in_rand PDU structure
+struct lmp_inrand
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Random number
+ struct ltk random;
+};
+
+///LMP_comb_key PDU structure
+struct lmp_combkey
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Random number
+ struct ltk random;
+};
+
+///LMP_unit_key PDU structure
+struct lmp_unitkey
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Key
+ struct ltk key;
+};
+
+///LMP_au_rand PDU structure
+struct lmp_aurand
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Random number
+ struct ltk random;
+};
+
+///LMP_sres PDU structure
+struct lmp_sres
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Authentication Response
+ struct sres_nb Sres;
+};
+
+///LMP_temp_rand PDU structure
+struct lmp_temprand
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Random number
+ struct ltk random;
+};
+
+///LMP_temp_key PDU structure
+struct lmp_tempkey
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Key
+ struct ltk key;
+};
+
+///LMP_encryption_mode_req PDU structure
+struct lmp_enc_mode_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Encryption Mode
+ uint8_t enc_mode;
+};
+
+///LMP_encryption_key_size_req PDU structure
+struct lmp_enc_key_size_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Key Size
+ uint8_t key_size;
+};
+
+///LMP_start_encryption_req PDU structure
+struct lmp_start_enc_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Random number
+ struct ltk random;
+};
+
+///LMP_stop_encryption_req PDU structure
+struct lmp_stop_enc_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+};
+
+///LMP_switch_req PDU structure
+struct lmp_switch_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Switch Instant
+ uint32_t switch_inst;
+};
+
+///LMP_sniff_req PDU structure
+struct lmp_sniff_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Timing Control Flags
+ uint8_t flags;
+ ///Dsniff
+ uint16_t d_sniff;
+ ///Tsniff
+ uint16_t t_sniff;
+ ///Sniff attempt
+ uint16_t sniff_attempt;
+ ///Sniff Timeout
+ uint16_t sniff_to;
+};
+
+///LMP_unsniff_req PDU structure
+struct lmp_unsniff_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+};
+
+///LMP_incr_power_req PDU structure
+struct lmp_incr_pwr_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///For future use
+ uint8_t reserved;
+};
+
+///LMP_decr_power_req PDU structure
+struct lmp_decr_pwr_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///For future use
+ uint8_t reserved;
+};
+
+///LMP_max_power PDU structure
+struct lmp_max_pwr
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+};
+
+///LMP_min_power PDU structure
+struct lmp_min_pwr
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+};
+
+///LMP_auto_rate PDU structure
+struct lmp_auto_rate
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+};
+
+///LMP_preferred_rate PDU structure
+struct lmp_pref_rate
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Data Rate
+ uint8_t rate;
+};
+
+///LMP_version_req PDU structure
+struct lmp_ver_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Version number
+ uint8_t ver;
+ ///Company ID
+ uint16_t co_id;
+ ///Subversion number
+ uint16_t subver;
+};
+
+///LMP_version_res PDU structure
+struct lmp_ver_res
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Version number
+ uint8_t ver;
+ ///Company ID
+ uint16_t co_id;
+ ///Subversion number
+ uint16_t subver;
+};
+
+///LMP_features_req PDU structure
+struct lmp_feats_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Features
+ struct features feats;
+};
+
+///LMP_features_res PDU structure
+struct lmp_feats_res
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Features
+ struct features feats;
+};
+
+///LMP_quality_of_service PDU structure
+struct lmp_qos
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Poll interval
+ uint16_t poll_intv;
+ ///Nbc
+ uint8_t nbc;
+};
+
+
+///LMP_quality_of_service_req PDU structure
+struct lmp_qos_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Poll interval
+ uint16_t poll_intv;
+ ///Nbc
+ uint8_t nbc;
+};
+
+///LMP_SCO_link_req PDU structure
+struct lmp_sco_link_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///SCO handle
+ uint8_t sco_hdl;
+ ///timing control flags
+ uint8_t flags;
+ ///Dsco
+ uint8_t d_sco;
+ ///Tsco
+ uint8_t t_sco;
+ ///SCO packet
+ uint8_t sco_pkt;
+ ///Air mode
+ uint8_t air_mode;
+};
+
+///LMP_remove_SCO_link_req PDU structure
+struct lmp_rmv_sco_link_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///SCO handle
+ uint8_t sco_hdl;
+ ///Reason for its removal(error code)
+ uint8_t reason;
+};
+
+///LMP_max_slot PDU structure
+struct lmp_max_slot
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Max slots
+ uint8_t max_slots;
+};
+
+
+///LMP_max_slot_req PDU structure
+struct lmp_max_slot_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Max slots
+ uint8_t max_slots;
+};
+
+///LMP_timing_accuracy_req PDU structure
+struct lmp_timing_accu_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+};
+
+///LMP_timing_accuracy_res PDU structure
+struct lmp_timing_accu_res
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Drift
+ uint8_t drift;
+ ///Jitter
+ uint8_t jitter;
+};
+
+///LMP_setup_complete PDU structure
+struct lmp_setup_cmp
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+};
+
+///LMP_use_semi_permanent_key PDU structure
+struct lmp_use_semi_perm_key
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+};
+
+///LMP_host_connection_req PDU structure
+struct lmp_host_con_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+};
+
+///LMP_slot_offset PDU structure
+struct lmp_slot_off
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Slot Offset
+ uint16_t slot_off;
+ ///BD Address
+ struct bd_addr addr;
+};
+
+///LMP_page_mode_req PDU structure
+struct lmp_page_mode_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Paging scheme
+ uint8_t page_scheme;
+ ///Paging scheme settings
+ uint8_t page_stg;
+};
+
+///LMP_page_scan_mode_req PDU structure
+struct lmp_page_scan_mode_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Paging scheme
+ uint8_t page_scheme;
+ ///Paging scheme settings
+ uint8_t page_stg;
+};
+
+///LMP_supervision_timeout PDU structure
+struct lmp_supv_to
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Supervision Timeout
+ uint16_t supv_to;
+};
+
+///LMP_test_activate PDU structure
+struct lmp_test_activate
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+};
+
+///LMP_test_control PDU structure
+struct lmp_test_ctrl
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Test Scenario
+ uint8_t scenario;
+ ///Hopping Mode
+ uint8_t hop;
+ ///Tx frequency
+ uint8_t tx_freq;
+ ///Rx Frequency
+ uint8_t rx_freq;
+ ///Power Control Mode
+ uint8_t pwr_ctrl;
+ ///Poll period
+ uint8_t poll_period;
+ ///Packet type
+ uint8_t pkt_type;
+ ///length of test data
+ uint16_t data_len;
+};
+
+///LMP_encryption_key_size_mask_req PDU structure
+struct lmp_enc_key_size_mask_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+};
+
+///LMP_encryption_key_size_mask_res PDU structure
+struct lmp_enc_key_size_mask_res
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Encryption Key Size Mask
+ uint16_t mask;
+};
+
+///LMP_set_AFH PDU structure
+struct lmp_set_afh
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///AFH Instant
+ uint32_t instant;
+ ///AFH Mode
+ uint8_t mode;
+ ///AFH channel map
+ struct chnl_map map;
+};
+
+///LMP_encapsulated_header PDU structure
+struct lmp_encaps_hdr
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Encapsulated major type
+ uint8_t maj_type;
+ ///Encapsulated minor type
+ uint8_t min_type;
+ ///Encapsulated Payload Length
+ uint8_t payl_len;
+};
+
+///LMP_encapsulated_payload PDU structure
+struct lmp_encaps_payl
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Encapsulated data
+ struct byte16 data;
+};
+
+///LMP_Simple_Pairing_Confirm PDU structure
+struct lmp_sp_cfm
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Commitment Value
+ struct byte16 commitment_val ;
+};
+
+///LMP_Simple_Pairing_Number PDU structure
+struct lmp_sp_nb
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///nonce Value
+ struct byte16 nonce;
+};
+
+///LMP_DHkey_check PDU structure
+struct lmp_dhkey_chk
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Confirmation Value
+ struct ltk cfm_val;
+};
+
+///LMP_pause_encryption_aes_req PDU structure
+struct lmp_pause_enc_aes_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ /// Random Number
+ struct ltk rand;
+};
+
+/*
+ * Extended PDUs parameter structures - Escape 4
+ ****************************************************************************************/
+
+///LMP_accepted_ext PDU structure
+struct lmp_accepted_ext
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Extended opcode
+ uint8_t ext_opcode;
+ ///Escape opcode of the original LMP
+ uint8_t orig_esc_opcode;
+ ///Extended opcode of the original LMP
+ uint8_t orig_ext_opcode;
+};
+
+///LMP_not_accepted_ext PDU structure
+struct lmp_not_accepted_ext
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Extended opcode
+ uint8_t ext_opcode;
+ ///Escape opcode of the original LMP
+ uint8_t orig_esc_opcode;
+ ///Extended opcode of the original LMP
+ uint8_t orig_ext_opcode;
+ ///Reason
+ uint8_t reason;
+};
+
+///LMP_features_req_ext PDU structure
+struct lmp_feats_req_ext
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Extended opcode
+ uint8_t ext_opcode;
+ ///Features page
+ uint8_t page;
+ ///Max supported page
+ uint8_t max_page;
+ ///Extended features
+ struct features ext_feats;
+};
+
+///LMP_features_res_ext PDU structure
+struct lmp_feats_res_ext
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Extended opcode
+ uint8_t ext_opcode;
+ ///Features page
+ uint8_t page;
+ ///Max supported page
+ uint8_t max_page;
+ ///Extended features
+ struct features ext_feats;
+};
+
+///LMP_clk_adj PDU structure
+struct lmp_clk_adj
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Extended opcode
+ uint8_t ext_opcode;
+ ///Coarse clock adjustment Event ID
+ uint8_t clk_adj_id;
+ ///Coarse clock adjustment instant
+ uint32_t clk_adj_instant;
+ ///Coarse clock adjustment intraslot alignment offset
+ int16_t clk_adj_us;
+ ///Coarse clock adjustment slot offset
+ uint8_t clk_adj_slots;
+ ///Coarse clock adjustment mode (before/after instant)
+ uint8_t clk_adj_mode;
+ ///Coarse clock adjustment PDU CLK instant
+ uint32_t clk_adj_clk;
+};
+
+///LMP_clk_adj_ack PDU structure
+struct lmp_clk_adj_ack
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Extended opcode
+ uint8_t ext_opcode;
+ ///Coarse clock adjustment Event ID
+ uint8_t clk_adj_id;
+};
+
+///LMP_clk_adj_req PDU structure
+struct lmp_clk_adj_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Extended opcode
+ uint8_t ext_opcode;
+ ///Coarse clock adjustment intraslot alignment offset
+ int16_t clk_adj_us;
+ ///Coarse clock adjustment slot offset
+ uint8_t clk_adj_slots;
+ ///Corase clock adjustment period
+ uint8_t clk_adj_period;
+};
+
+///LMP_packet_type_table_req PDU structure
+struct lmp_pkt_type_tbl_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Extended opcode
+ uint8_t ext_opcode;
+ ///Packet Type table
+ uint8_t pkt_type_tbl;
+};
+
+///LMP_eSCO_link_req PDU structure
+struct lmp_esco_link_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Extended opcode
+ uint8_t ext_opcode;
+ ///eSCO handle
+ uint8_t esco_hdl;
+ ///eSCo LT Address
+ uint8_t esco_lt_addr;
+ ///timing control flags
+ uint8_t flags;
+ ///Desco
+ uint8_t d_esco;
+ ///t_esco
+ uint8_t t_esco;
+ ///Wesco
+ uint8_t w_esco;
+ ///eSCO packet type M2S
+ uint8_t m2s_pkt_type;
+ ///eSCO packet type S2M
+ uint8_t s2m_pkt_type;
+ ///Packet Length M2S
+ uint16_t m2s_pkt_len;
+ ///Packet Length S2m
+ uint16_t s2m_pkt_len;
+ ///Air Mode
+ uint8_t air_mode;
+ ///Negotiation state
+ uint8_t negt_st;
+};
+
+///LMP_remove_eSCO_link_req PDU structure
+struct lmp_rmv_esco_link_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Extended opcode
+ uint8_t ext_opcode;
+ ///eSCO handle
+ uint8_t esco_hdl;
+ ///Reason
+ uint8_t reason;
+};
+
+///LMP_channel_classification_req PDU structure
+struct lmp_ch_class_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Extended opcode
+ uint8_t ext_opcode;
+ ///AFH reporting mode
+ uint8_t rep_mode;
+ ///AFH min interval
+ uint16_t min_intv;
+ ///AFH max interval
+ uint16_t max_intv;
+};
+
+///LMP_channel_classification PDU structure
+struct lmp_ch_class
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Extended opcode
+ uint8_t ext_opcode;
+ ///AFh channel classification
+ struct chnl_map ch_class;
+};
+
+///LMP_sniff_subrating_req PDU structure
+struct lmp_ssr_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Extended opcode
+ uint8_t ext_opcode;
+ ///Maximum sniff sub-rate
+ uint8_t max_subrate;
+ ///Minimum sniff mode timeout
+ uint16_t min_to;
+ ///Sniff sub-rating instant
+ uint32_t inst;
+};
+
+///LMP_sniff_subrating_res PDU structure
+struct lmp_ssr_res
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Extended opcode
+ uint8_t ext_opcode;
+ ///Maximum sniff sub-rate
+ uint8_t max_subrate;
+ ///Minimum sniff mode timeout
+ uint16_t min_to;
+ ///Sniff sub-rating instant
+ uint32_t inst;
+};
+
+///LMP_pause_encryption_req PDU structure
+struct lmp_pause_enc_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Extended opcode
+ uint8_t ext_opcode;
+};
+
+///LMP_resume_encryption_req PDU structure
+struct lmp_resume_enc_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Extended opcode
+ uint8_t ext_opcode;
+};
+
+///LMP_IO_capability_req PDU structure
+struct lmp_io_cap_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Extended opcode
+ uint8_t ext_opcode;
+ ///IO Capabilities
+ uint8_t io_cap;
+ /// OOB Authentication data
+ uint8_t oob_auth_data;
+ ///Authentication requirements
+ uint8_t auth_req;
+};
+
+
+///LMP_IO_capability_res PDU structure
+struct lmp_io_cap_res
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Extended opcode
+ uint8_t ext_opcode;
+ ///IO Capabilities
+ uint8_t io_cap;
+ /// OOB Authentication data
+ uint8_t oob_auth_data;
+ ///Authentication requirements
+ uint8_t auth_req;
+};
+
+///LMP_numeric_comparison_failed PDU structure
+struct lmp_num_comparison_fail
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Extended opcode
+ uint8_t ext_opcode;
+};
+
+///LMP_passkey_failed PDU structure
+struct lmp_passkey_fail
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Extended opcode
+ uint8_t ext_opcode;
+};
+
+///LMP_oob_failed PDU structure
+struct lmp_oob_fail
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Extended opcode
+ uint8_t ext_opcode;
+};
+
+///LMP_keypress_notification PDU structure
+struct lmp_keypress_notif
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Extended opcode
+ uint8_t ext_opcode;
+ ///Notification Type
+ uint8_t type;
+};
+
+///LMP_power_control_req PDU structure
+struct lmp_pwr_ctrl_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Extended opcode
+ uint8_t ext_opcode;
+ ///Power adjustment request
+ uint8_t pwr_adj;
+
+};
+
+///LMP_power_control_res PDU structure
+struct lmp_pwr_ctrl_res
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Extended opcode
+ uint8_t ext_opcode;
+ ///Power adjustment response
+ uint8_t pwr_adj;
+};
+
+/// LMP_ping_req PDU structure
+struct lmp_ping_req
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Extended opcode
+ uint8_t ext_opcode;
+};
+
+/// LMP_ping_res PDU structure
+struct lmp_ping_res
+{
+ ///Opcode (including transaction ID)
+ uint8_t opcode;
+ ///Extended opcode
+ uint8_t ext_opcode;
+};
+
+/// Union of all the LMP message structures
+union lmp_pdu_data
+{
+ struct lmp_name_req name_req ;
+ struct lmp_name_res name_res ;
+ struct lmp_accepted accepted ;
+ struct lmp_not_accepted not_accepted ;
+ struct lmp_clk_off_req clk_off_req ;
+ struct lmp_clk_off_res clk_off_res ;
+ struct lmp_detach detach ;
+ struct lmp_inrand inrand ;
+ struct lmp_combkey combkey ;
+ struct lmp_unitkey unitkey ;
+ struct lmp_aurand aurand ;
+ struct lmp_sres sres ;
+ struct lmp_temprand temprand ;
+ struct lmp_tempkey tempkey ;
+ struct lmp_enc_mode_req enc_mode_req ;
+ struct lmp_enc_key_size_req enc_key_size_req ;
+ struct lmp_start_enc_req start_enc_req ;
+ struct lmp_stop_enc_req stop_enc_req ;
+ struct lmp_switch_req switch_req ;
+ struct lmp_sniff_req sniff_req ;
+ struct lmp_unsniff_req unsniff_req ;
+ struct lmp_incr_pwr_req incr_pwr_req ;
+ struct lmp_decr_pwr_req decr_pwr_req ;
+ struct lmp_max_pwr max_pwr ;
+ struct lmp_min_pwr min_pwr ;
+ struct lmp_auto_rate auto_rate ;
+ struct lmp_pref_rate pref_rate ;
+ struct lmp_ver_req ver_req ;
+ struct lmp_ver_res ver_res ;
+ struct lmp_feats_req feats_req ;
+ struct lmp_feats_res feats_res ;
+ struct lmp_clk_adj clk_adj ;
+ struct lmp_clk_adj_ack clk_adj_ack ;
+ struct lmp_clk_adj_req clk_adj_req ;
+ struct lmp_qos qos ;
+ struct lmp_qos_req qos_req ;
+ struct lmp_sco_link_req sco_link_req ;
+ struct lmp_rmv_sco_link_req rmv_sco_link_req ;
+ struct lmp_max_slot max_slot ;
+ struct lmp_max_slot_req max_slot_req ;
+ struct lmp_timing_accu_req timing_accu_req ;
+ struct lmp_timing_accu_res timing_accu_res ;
+ struct lmp_setup_cmp setup_cmp ;
+ struct lmp_use_semi_perm_key use_semi_perm_key ;
+ struct lmp_host_con_req host_con_req ;
+ struct lmp_slot_off slot_off ;
+ struct lmp_page_mode_req page_mode_req ;
+ struct lmp_page_scan_mode_req page_scan_mode_req ;
+ struct lmp_supv_to supv_to ;
+ struct lmp_test_activate test_activate ;
+ struct lmp_test_ctrl test_ctrl ;
+ struct lmp_enc_key_size_mask_req enc_key_size_mask_req ;
+ struct lmp_enc_key_size_mask_res enc_key_size_mask_res ;
+ struct lmp_set_afh set_afh ;
+ struct lmp_encaps_hdr encaps_hdr ;
+ struct lmp_encaps_payl encaps_payl ;
+ struct lmp_sp_cfm sp_cfm ;
+ struct lmp_sp_nb sp_nb ;
+ struct lmp_dhkey_chk dhkey_chk ;
+ struct lmp_accepted_ext accepted_ext ;
+ struct lmp_not_accepted_ext not_accepted_ext ;
+ struct lmp_feats_req_ext feats_req_ext ;
+ struct lmp_feats_res_ext feats_res_ext ;
+ struct lmp_pkt_type_tbl_req pkt_type_tbl_req ;
+ struct lmp_esco_link_req esco_link_req ;
+ struct lmp_rmv_esco_link_req rmv_esco_link_req ;
+ struct lmp_ch_class_req ch_class_req ;
+ struct lmp_ch_class ch_class ;
+ struct lmp_ssr_req ssr_req ;
+ struct lmp_ssr_res ssr_res ;
+ struct lmp_pause_enc_req pause_enc_req ;
+ struct lmp_resume_enc_req resume_enc_req ;
+ struct lmp_io_cap_req io_cap_req ;
+ struct lmp_io_cap_res io_cap_res ;
+ struct lmp_num_comparison_fail num_comparison_fail ;
+ struct lmp_passkey_fail passkey_fail ;
+ struct lmp_oob_fail oob_fail ;
+ struct lmp_keypress_notif keypress_notif ;
+ struct lmp_pwr_ctrl_req pwr_ctrl_req ;
+ struct lmp_pwr_ctrl_res pwr_ctrl_res ;
+ struct lmp_ping_req ping_req ;
+ struct lmp_ping_res ping_res ;
+};
+
+
+/// @} CO_BT
+#endif // CO_LMP_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_math.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_math.h
new file mode 100644
index 0000000000..6e2d1a396c
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_math.h
@@ -0,0 +1,206 @@
+/**
+ ****************************************************************************************
+ *
+ * @file co_math.h
+ *
+ * @brief Common optimized math functions
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef _CO_MATH_H_
+#define _CO_MATH_H_
+
+/**
+ *****************************************************************************************
+ * @defgroup CO_MATH Math functions
+ * @ingroup COMMON
+ * @brief Optimized math functions and other computations.
+ *
+ * @{
+ *****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include // standard integer definitions
+#include // boolean definitions
+#include // standard library
+#include "ble_arch.h"
+
+extern void srand (unsigned int seed);
+extern int rand (void);
+
+/*
+ * MACROS
+ ****************************************************************************************
+ */
+/**
+ ****************************************************************************************
+ * @brief Return value with one bit set.
+ *
+ * @param[in] pos Position of the bit to set.
+ *
+ * @return Value with one bit set. There is no return type since this is a macro and this
+ * will be resolved by the compiler upon assignment to an l-value.
+ ****************************************************************************************
+ */
+#define CO_BIT(pos) (1UL<<(pos))
+
+/**
+ ****************************************************************************************
+ * @brief Align val on the multiple of 4 equal or nearest higher.
+ * @param[in] val Value to align.
+ * @return Value aligned.
+ ****************************************************************************************
+ */
+#define CO_ALIGN4_HI(val) (((val)+3)&~3)
+
+
+/**
+ ****************************************************************************************
+ * @brief Align val on the multiple of 4 equal or nearest lower.
+ * @param[in] val Value to align.
+ * @return Value aligned.
+ ****************************************************************************************
+ */
+#define CO_ALIGN4_LO(val) ((val)&~3)
+
+/**
+ ****************************************************************************************
+ * @brief Align val on the multiple of 2 equal or nearest higher.
+ * @param[in] val Value to align.
+ * @return Value aligned.
+ ****************************************************************************************
+ */
+#define CO_ALIGN2_HI(val) (((val)+1)&~1)
+
+
+/**
+ ****************************************************************************************
+ * @brief Align val on the multiple of 2 equal or nearest lower.
+ * @param[in] val Value to align.
+ * @return Value aligned.
+ ****************************************************************************************
+ */
+#define CO_ALIGN2_LO(val) ((val)&~1)
+
+
+/*
+ * FUNCTION DEFINTIONS
+ ****************************************************************************************
+ */
+/**
+ ****************************************************************************************
+ * @brief Count leading zeros.
+ * @param[in] val Value to count the number of leading zeros on.
+ * @return Number of leading zeros when value is written as 32 bits.
+ ****************************************************************************************
+ */
+__INLINE uint32_t co_clz(uint32_t val)
+{
+ #if defined(__arm__)
+ return __builtin_clz(val);
+ #elif defined(__GNUC__)
+ if (val == 0)
+ {
+ return 32;
+ }
+ return __builtin_clz(val);
+ #else
+ uint32_t i;
+ for (i = 0; i < 32; i++)
+ {
+ if (val & CO_BIT(31 - i))
+ break;
+ }
+ return i;
+ #endif // defined(__arm__)
+}
+
+/**
+ ****************************************************************************************
+ * @brief Function to initialize the random seed.
+ * @param[in] seed The seed number to use to generate the random sequence.
+ ****************************************************************************************
+ */
+__INLINE void co_random_init(uint32_t seed)
+{
+ srand(seed);
+}
+
+/**
+ ****************************************************************************************
+ * @brief Function to get an 8 bit random number.
+ * @return Random byte value.
+ ****************************************************************************************
+ */
+__INLINE uint8_t co_rand_byte(void)
+{
+ return (uint8_t)(rand() & 0xFF);
+}
+
+/**
+ ****************************************************************************************
+ * @brief Function to get an 16 bit random number.
+ * @return Random half word value.
+ ****************************************************************************************
+ */
+__INLINE uint16_t co_rand_hword(void)
+{
+ return (uint16_t)(rand() & 0xFFFF);
+}
+
+/**
+ ****************************************************************************************
+ * @brief Function to get an 32 bit random number.
+ * @return Random word value.
+ ****************************************************************************************
+ */
+__INLINE uint32_t co_rand_word(void)
+{
+ return (uint32_t)rand();
+}
+
+/**
+ ****************************************************************************************
+ * @brief Function to return the smallest of 2 unsigned 32 bits words.
+ * @return The smallest value.
+ ****************************************************************************************
+ */
+__INLINE uint32_t co_min(uint32_t a, uint32_t b)
+{
+ return a < b ? a : b;
+}
+
+/**
+ ****************************************************************************************
+ * @brief Function to return the greatest of 2 unsigned 32 bits words.
+ * @return The greatest value.
+ ****************************************************************************************
+ */
+__INLINE uint32_t co_max(uint32_t a, uint32_t b)
+{
+ return a > b ? a : b;
+}
+
+/**
+ ****************************************************************************************
+ * @brief Function to return the absolute value of a signed integer.
+ * @return The absolute value.
+ ****************************************************************************************
+ */
+__INLINE int co_abs(int val)
+{
+ return val < 0 ? val*(-1) : val;
+}
+
+/// @} CO_MATH
+
+
+#endif // _CO_MATH_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_utils.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_utils.h
new file mode 100644
index 0000000000..7deaab6393
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_utils.h
@@ -0,0 +1,461 @@
+/**
+ ****************************************************************************************
+ *
+ * @file co_utils.h
+ *
+ * @brief Common utilities definitions
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+#ifndef _CO_UTILS_H_
+#define _CO_UTILS_H_
+
+/**
+ ****************************************************************************************
+ * @defgroup CO_UTILS Utilities
+ * @ingroup COMMON
+ * @brief Common utilities
+ *
+ * This module contains the common utilities functions and macros.
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+
+#include // standard definitions
+#include // standard definitions
+#include "co_bt.h" // common bt definitions
+#include "rwip_config.h" // SW configuration
+//#include "core_cm0.h" // for inline functions
+#include "stdint.h"
+/*
+ * MACRO DEFINITIONS
+ ****************************************************************************************
+ */
+
+/// Common constants - bit field definitions
+#define BIT0 0x0001
+#define BIT1 0x0002
+#define BIT2 0x0004
+#define BIT3 0x0008
+#define BIT4 0x0010
+#define BIT5 0x0020
+#define BIT6 0x0040
+#define BIT7 0x0080
+#define BIT8 0x0100
+#define BIT9 0x0200
+#define BIT10 0x0400
+#define BIT11 0x0800
+#define BIT12 0x1000
+#define BIT13 0x2000
+#define BIT14 0x4000
+#define BIT15 0x8000
+
+#define BIT16 0x00010000
+#define BIT17 0x00020000
+#define BIT18 0x00040000
+#define BIT19 0x00080000
+#define BIT20 0x00100000
+#define BIT21 0x00200000
+#define BIT22 0x00400000
+#define BIT23 0x00800000L
+#define BIT24 0x01000000L
+#define BIT25 0x02000000L
+#define BIT26 0x04000000L
+#define BIT27 0x08000000L
+#define BIT28 0x10000000L
+#define BIT29 0x20000000L
+#define BIT30 0x40000000L
+#define BIT31 0x80000000UL
+
+/// Number of '1' bits in a byte
+#define NB_ONE_BITS(byte) (one_bits[byte & 0x0F] + one_bits[byte >> 4])
+
+/// Get the number of elements within an array, give also number of rows in a 2-D array
+#define ARRAY_LEN(array) (sizeof((array))/sizeof((array)[0]))
+
+/// Get the number of columns within a 2-D array
+#define ARRAY_NB_COLUMNS(array) (sizeof((array[0]))/sizeof((array)[0][0]))
+
+
+/// Macro for LMP message handler function declaration or definition
+#define LMP_MSG_HANDLER(msg_name) __STATIC int lmp_##msg_name##_handler(struct lmp_##msg_name const *param, \
+ ke_task_id_t const dest_id)
+
+/// Macro for HCI message handler function declaration or definition (for multi-instanciated tasks)
+#define HCI_CMD_HANDLER_C(cmd_name, param_struct) __STATIC int hci_##cmd_name##_cmd_handler(param_struct const *param, \
+ ke_task_id_t const dest_id, \
+ uint16_t opcode)
+
+/// Macro for HCI message handler function declaration or definition (with parameters)
+#define HCI_CMD_HANDLER(cmd_name, param_struct) __STATIC int hci_##cmd_name##_cmd_handler(param_struct const *param, \
+ uint16_t opcode)
+
+/// Macro for HCI message handler function declaration or definition (with parameters)
+#define HCI_CMD_HANDLER_TAB(task) __STATIC const struct task##_hci_cmd_handler task##_hci_command_handler_tab[] =
+
+
+/*
+ * TYPE DEFINITIONS
+ ****************************************************************************************
+ */
+
+
+/*
+ * CONSTANT DECLARATIONS
+ ****************************************************************************************
+ */
+
+/// Number of '1' bits in values from 0 to 15, used to fasten bit counting
+extern const unsigned char one_bits[16];
+
+/// Conversion table Sleep Clock Accuracy to PPM
+extern const uint16_t co_sca2ppm[];
+
+/// NULL BD address
+extern const struct bd_addr co_null_bdaddr;
+
+/// NULL BD address
+extern const struct bd_addr co_default_bdaddr;
+
+/*
+ * MACROS
+ ****************************************************************************************
+ */
+
+/// MACRO to build a subversion field from the Minor and Release fields
+#define CO_SUBVERSION_BUILD(minor, release) (((minor) << 8) | (release))
+
+
+/// Macro to get a structure from one of its structure field
+#define CONTAINER_OF(ptr, type, member) ((type *)( (char *)ptr - offsetof(type,member) ))
+
+/*
+ * OPERATIONS ON BT CLOCK
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief Clocks addition with 2 operands
+ *
+ * @param[in] clock_a 1st operand value (in BT slots)
+ * @param[in] clock_b 2nd operand value (in BT slots)
+ * @return result operation result (in BT slots)
+ ****************************************************************************************
+ */
+#define CLK_ADD_2(clock_a, clock_b) ((uint32_t)(((clock_a) + (clock_b)) & MAX_SLOT_CLOCK))
+
+/**
+ ****************************************************************************************
+ * @brief Clocks addition with 3 operands
+ *
+ * @param[in] clock_a 1st operand value (in BT slots)
+ * @param[in] clock_b 2nd operand value (in BT slots)
+ * @param[in] clock_c 3rd operand value (in BT slots)
+ * @return result operation result (in BT slots)
+ ****************************************************************************************
+ */
+#define CLK_ADD_3(clock_a, clock_b, clock_c) ((uint32_t)(((clock_a) + (clock_b) + (clock_c)) & MAX_SLOT_CLOCK))
+
+/**
+ ****************************************************************************************
+ * @brief Clocks subtraction
+ *
+ * @param[in] clock_a 1st operand value (in BT slots)
+ * @param[in] clock_b 2nd operand value (in BT slots)
+ * @return result operation result (in BT slots)
+ ****************************************************************************************
+ */
+#define CLK_SUB(clock_a, clock_b) ((uint32_t)(((clock_a) - (clock_b)) & MAX_SLOT_CLOCK))
+
+/**
+ ****************************************************************************************
+ * @brief Clocks time difference
+ *
+ * @param[in] clock_a 1st operand value (in BT slots)
+ * @param[in] clock_b 2nd operand value (in BT slots)
+ * @return result return the time difference from clock A to clock B
+ * - result < 0 => clock_b is in the past
+ * - result == 0 => clock_a is equal to clock_b
+ * - result > 0 => clock_b is in the future
+ ****************************************************************************************
+ */
+#define CLK_DIFF(clock_a, clock_b) ( (CLK_SUB((clock_b), (clock_a)) > ((MAX_SLOT_CLOCK+1) >> 1)) ? \
+ ((int32_t)((-CLK_SUB((clock_a), (clock_b))))) : ((int32_t)((CLK_SUB((clock_b), (clock_a))))) )
+
+/**
+ ****************************************************************************************
+ * @brief Check if an instant is passed
+ *
+ * @param[in] instant Instant reference (in BT slots)
+ * @param[in] clock Current timestamp (in BT slots)
+ * @return result True: clock is after or equal to the instant | False: clock is before the instant
+ ****************************************************************************************
+ */
+#define CLK_INSTANT_PASSED(instant, clock) ((uint32_t)(clock - instant) < (MAX_SLOT_CLOCK >> 1))
+
+/// macro to extract a field from a value containing several fields
+/// @param[in] __r bit field value
+/// @param[in] __f field name
+/// @return the value of the register masked and shifted
+#define GETF(__r, __f) \
+ (( (__r) & (__f##_MASK) ) >> (__f##_LSB))
+
+/// macro to set a field value into a value containing several fields.
+/// @param[in] __r bit field value
+/// @param[in] __f field name
+/// @param[in] __v value to put in field
+#define SETF(__r, __f, __v) \
+ do { \
+ ASSERT_ERR( ( ( ( (__v) << (__f##_LSB) ) & ( ~(__f##_MASK) ) ) ) == 0 ); \
+ __r = (((__r) & ~(__f##_MASK)) | (__v) << (__f##_LSB)); \
+ } while (0)
+
+
+
+/// macro to extract a bit field from a value containing several fields
+/// @param[in] __r bit field value
+/// @param[in] __b bit field name
+/// @return the value of the register masked and shifted
+#define GETB(__r, __b) \
+ (( (__r) & (__b##_BIT) ) >> (__b##_POS))
+
+/// macro to set a bit field value into a value containing several fields.
+/// @param[in] __r bit field value
+/// @param[in] __b bit field name
+/// @param[in] __v value to put in field
+#define SETB(__r, __b, __v) \
+ do { \
+ ASSERT_ERR( ( ( ( (__v) << (__b##_POS) ) & ( ~(__b##_BIT) ) ) ) == 0 ); \
+ __r = (((__r) & ~(__b##_BIT)) | (__v) << (__b##_POS)); \
+ } while (0)
+
+
+
+/*
+ * FUNCTION DEFINITIONS
+ ****************************************************************************************
+ */
+/**
+ ****************************************************************************************
+ * @brief Read an aligned 32 bit word.
+ * @param[in] ptr32 The address of the first byte of the 32 bit word.
+ * @return The 32 bit value.
+ ****************************************************************************************
+ */
+__INLINE uint32_t co_read32(void const *ptr32)
+{
+ return *((uint32_t*)ptr32);
+}
+
+/**
+ ****************************************************************************************
+ * @brief Read an aligned 16 bits word.
+ * @param[in] ptr16 The address of the first byte of the 16 bits word.
+ * @return The 16 bits value.
+ ****************************************************************************************
+ */
+__INLINE uint16_t co_read16(void const *ptr16)
+{
+ return *((uint16_t*)ptr16);
+}
+
+/**
+ ****************************************************************************************
+ * @brief Write an aligned 32 bits word.
+ * @param[in] ptr32 The address of the first byte of the 32 bits word.
+ * @param[in] value The value to write.
+ ****************************************************************************************
+ */
+__INLINE void co_write32(void const *ptr32, uint32_t value)
+{
+ *(uint32_t*)ptr32 = value;
+}
+
+/**
+ ****************************************************************************************
+ * @brief Write an aligned 16 bits word.
+ * @param[in] ptr16 The address of the first byte of the 16 bits word.
+ * @param[in] value The value to write.
+ ****************************************************************************************
+ */
+__INLINE void co_write16(void const *ptr16, uint32_t value)
+{
+ *(uint16_t*)ptr16 = value;
+}
+
+/**
+ ****************************************************************************************
+ * @brief Write a 8 bits word.
+ * @param[in] ptr8 The address of the first byte of the 8 bits word.
+ * @param[in] value The value to write.
+ ****************************************************************************************
+ */
+__INLINE void co_write8(void const *ptr8, uint32_t value)
+{
+ *(uint8_t*)ptr8 = value;
+}
+
+/**
+ ****************************************************************************************
+ * @brief Read a packed 16 bits word.
+ * @param[in] ptr16 The address of the first byte of the 16 bits word.
+ * @return The 16 bits value.
+ ****************************************************************************************
+ */
+#if 1
+#define co_read16p(ptr16) (((uint8_t *)ptr16)[0] | ((uint8_t *)ptr16)[1] << 8)
+#else
+__INLINE uint16_t co_read16p(void const *ptr16)
+{
+ uint16_t value = ((uint8_t *)ptr16)[0] | ((uint8_t *)ptr16)[1] << 8;
+ return value;
+}
+#endif
+
+/**
+ ****************************************************************************************
+ * @brief Read a packed 24 bits word.
+ * @param[in] ptr24 The address of the first byte of the 24 bits word.
+ * @return The 24 bits value.
+ ****************************************************************************************
+ */
+__INLINE uint32_t co_read24p(void const *ptr24)
+{
+ uint16_t addr_l, addr_h;
+ addr_l = co_read16p((uint16_t *)ptr24);
+ addr_h = *((uint16_t *)ptr24 + 1) & 0x00FF;
+ return ((uint32_t)addr_l | (uint32_t)addr_h << 16);
+}
+
+/**
+ ****************************************************************************************
+ * @brief Write a packed 24 bits word.
+ * @param[in] ptr24 The address of the first byte of the 24 bits word.
+ * @param[in] value The value to write.
+ ****************************************************************************************
+ */
+__INLINE void co_write24p(void const *ptr24, uint32_t value)
+{
+ uint8_t *ptr=(uint8_t*)ptr24;
+
+ *ptr++ = (uint8_t)(value&0xff);
+ *ptr++ = (uint8_t)((value&0xff00)>>8);
+ *ptr++ = (uint8_t)((value&0xff0000)>>16);
+}
+
+/**
+ ****************************************************************************************
+ * @brief Read a packed 32 bits word.
+ * @param[in] ptr32 The address of the first byte of the 32 bits word.
+ * @return The 32 bits value.
+ ****************************************************************************************
+ */
+__INLINE uint32_t co_read32p(void const *ptr32)
+{
+ uint16_t addr_l, addr_h;
+ addr_l = co_read16p((uint16_t *)ptr32);
+ addr_h = co_read16p((uint16_t *)ptr32 + 1);
+ return ((uint32_t)addr_l | (uint32_t)addr_h << 16);
+}
+/**
+ ****************************************************************************************
+ * @brief Write a packed 32 bits word.
+ * @param[in] ptr32 The address of the first byte of the 32 bits word.
+ * @param[in] value The value to write.
+ ****************************************************************************************
+ */
+__INLINE void co_write32p(void const *ptr32, uint32_t value)
+{
+ uint8_t *ptr=(uint8_t*)ptr32;
+
+ *ptr++ = (uint8_t)(value&0xff);
+ *ptr++ = (uint8_t)((value&0xff00)>>8);
+ *ptr++ = (uint8_t)((value&0xff0000)>>16);
+ *ptr = (uint8_t)((value&0xff000000)>>24);
+}
+
+/**
+ ****************************************************************************************
+ * @brief Write a packed 16 bits word.
+ * @param[in] ptr16 The address of the first byte of the 16 bits word.
+ * @param[in] value The value to write.
+ ****************************************************************************************
+ */
+__INLINE void co_write16p(void const *ptr16, uint16_t value)
+{
+ uint8_t *ptr=(uint8_t*)ptr16;
+
+ *ptr++ = value&0xff;
+ *ptr = (value&0xff00)>>8;
+}
+
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+#if RW_DEBUG
+/**
+ ****************************************************************************************
+ * @brief Convert bytes to hexadecimal string
+ *
+ * @param[out] dest Pointer to the destination string (must be 2x longer than input table)
+ * @param[in] src Pointer to the bytes table
+ * @param[in] nb_bytes Number of bytes to display in the string
+ ****************************************************************************************
+ */
+void co_bytes_to_string(char* dest, uint8_t* src, uint8_t nb_bytes);
+#endif //RW_DEBUG
+
+/**
+ ****************************************************************************************
+ * @brief Compares two Bluetooth device addresses
+ *
+ * This function checks if the two bd address are equal.
+ *
+ * @param[in] bd_address1 Pointer on the first bd address to be compared.
+ * @param[in] bd_address2 Pointer on the second bd address to be compared.
+ *
+ * @return result of the comparison (true or false).
+ *
+ ****************************************************************************************
+ */
+bool co_bdaddr_compare(struct bd_addr const *bd_address1,
+ struct bd_addr const *bd_address2);
+
+#if (BT_EMB_PRESENT)
+
+/**
+ ******************************************************************************
+ * @brief Convert an duration in baseband slot to a duration in number of ticks.
+ * @param[in] slot_cnt Duration in number of baseband slot
+ * @return Duration (in number of ticks).
+ ******************************************************************************
+ */
+uint32_t co_slot_to_duration(uint16_t slot_cnt);
+
+/**
+ ******************************************************************************
+ * @brief Count the number of good channels in a map
+ * @param[in] map Channel Map (bit fields for the 79 BT RF channels)
+ * @return Number of good channels
+ ******************************************************************************
+ */
+uint8_t co_nb_good_channels(const struct chnl_map* map);
+
+#endif //BT_EMB_PRESENT
+
+/// @} CO_UTILS
+
+#endif // _CO_UTILS_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_version.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_version.h
new file mode 100644
index 0000000000..fa8a11abfa
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_version.h
@@ -0,0 +1,51 @@
+/**
+ ****************************************************************************************
+ *
+ * @file co_version.h
+ *
+ * @brief Version definitions for BT4.2
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef _CO_VERSION_H_
+#define _CO_VERSION_H_
+/**
+ ****************************************************************************************
+ * @defgroup CO_VERSION Version Defines
+ * @ingroup COMMON
+ *
+ * @brief Bluetooth Controller Version definitions.
+ *
+ * @{
+ ****************************************************************************************
+ */
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "rwip_config.h" // SW configuration options
+
+#if (BLE_QUALIF)
+/// RWBT SW Major Version
+#define RWBT_SW_VERSION_MAJOR (RW_BT40_VERSION)
+#else
+/// RWBT SW Major Version
+#define RWBT_SW_VERSION_MAJOR (RW_BT42_VERSION)
+#endif
+/// RWBT SW Minor Version
+#define RWBT_SW_VERSION_MINOR 3
+/// RWBT SW Build Version
+#define RWBT_SW_VERSION_BUILD 31
+
+/// RWBT SW Major Version
+#define RWBT_SW_VERSION_SUB_BUILD 0
+
+
+/// @} CO_VERSION
+
+
+#endif // _CO_VERSION_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gap.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gap.h
new file mode 100644
index 0000000000..2748c6bbbd
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gap.h
@@ -0,0 +1,628 @@
+/**
+ ****************************************************************************************
+ *
+ * @file gap.h
+ *
+ * @brief Header file - GAP.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+#ifndef GAP_H_
+#define GAP_H_
+/**
+ ****************************************************************************************
+ * @addtogroup HOST
+ * @ingroup ROOT
+ * @brief Bluetooth Low Energy Host
+ *
+ * The HOST layer of the stack contains the higher layer protocols (@ref ATT "ATT",
+ * @ref SMP "SMP") and transport module (@ref L2C "L2C"). It also includes the Generic
+ * Access Profile (@ref GAP "GAP"), used for scanning/connection operations.
+ ****************************************************************************************
+ */
+/**
+ ****************************************************************************************
+ * @addtogroup GAP Generic Access Profile
+ * @ingroup HOST
+ * @brief Generic Access Profile.
+ *
+ * The GAP module is responsible for providing an API to the application in order to
+ * configure the device in the desired mode (discoverable, connectable, etc.) and perform
+ * required actions (scanning, connection, pairing, etc.). To achieve this, the GAP
+ * interfaces with both the @ref SMP "SMP", @ref L2C "L2C" and the @ref CONTROLLER "CONTROLLER"
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+#include
+#include "ble_arch.h"
+//#include "compiler.h"
+#include "att.h"
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/// BD address length
+#define GAP_BD_ADDR_LEN (6)
+/// LE Channel map length
+#define GAP_LE_CHNL_MAP_LEN (0x05)
+/// LE Feature Flags Length
+#define GAP_LE_FEATS_LEN (0x08)
+/// ADV Data and Scan Response length
+#define GAP_ADV_DATA_LEN (0x1F)
+#define GAP_SCAN_RSP_DATA_LEN (0x1F)
+/// Random number length
+#define GAP_RAND_NB_LEN (0x08)
+/// Key length
+#define GAP_KEY_LEN (16)
+/// P256 Key Len
+#define GAP_P256_KEY_LEN (0x20)
+
+
+///***** AD Type Flag - Bit set *******/
+/// Limited discovery flag - AD Flag
+#define GAP_LE_LIM_DISCOVERABLE_FLG 0x01
+/// General discovery flag - AD Flag
+#define GAP_LE_GEN_DISCOVERABLE_FLG 0x02
+/// Legacy BT not supported - AD Flag
+#define GAP_BR_EDR_NOT_SUPPORTED 0x04
+/// Dual mode for controller supported (BR/EDR/LE) - AD Flag
+#define GAP_SIMUL_BR_EDR_LE_CONTROLLER 0x08
+/// Dual mode for host supported (BR/EDR/LE) - AD Flag
+#define GAP_SIMUL_BR_EDR_LE_HOST 0x10
+
+/*********** GAP Miscellaneous Defines *************/
+/// Invalid connection index
+#define GAP_INVALID_CONIDX 0xFF
+
+/// Invalid connection handle
+#define GAP_INVALID_CONHDL 0xFFFF
+
+/// Connection interval min (N*1.250ms)
+#define GAP_CNX_INTERVAL_MIN 6 //(0x06)
+/// Connection interval Max (N*1.250ms)
+#define GAP_CNX_INTERVAL_MAX 3200 //(0xC80)
+/// Connection latency min (N*cnx evt)
+#define GAP_CNX_LATENCY_MIN 0 //(0x00)
+/// Connection latency Max (N*cnx evt
+#define GAP_CNX_LATENCY_MAX 499 //(0x1F3)
+/// Supervision TO min (N*10ms)
+#define GAP_CNX_SUP_TO_MIN 10 //(0x0A)
+/// Supervision TO Max (N*10ms)
+#define GAP_CNX_SUP_TO_MAX 3200 //(0xC80)
+
+
+
+/// Length of resolvable random address prand part
+#define GAP_ADDR_PRAND_LEN (3)
+/// Length of resolvable random address hash part
+#define GAP_ADDR_HASH_LEN (3)
+
+
+/*
+ * DEFINES - Optional for BLE application usage
+ ****************************************************************************************
+ */
+
+/// Central idle timer
+/// TGAP(conn_pause_central)
+/// recommended value: 1 s: (100 for ke timer)
+#define GAP_TMR_CONN_PAUSE_CT 0x0064
+
+/// Minimum time upon connection establishment before the peripheral
+/// starts a connection update procedure: TGAP(conn_pause_peripheral)
+/// recommended value: 5 s: (500 for ke timer)
+#define GAP_TMR_CONN_PAUSE_PH 0x01F4
+
+/// Minimum time to perform scanning when user initiated
+/// TGAP(scan_fast_period)
+/// recommended value: 30.72 s: (3072 for ke timer)
+#define GAP_TMR_SCAN_FAST_PERIOD 0x0C00
+
+/// Minimum time to perform advertising when user initiated
+/// TGAP(adv_fast_period)
+/// recommended value: 30 s: (3000 for ke timer)
+#define GAP_TMR_ADV_FAST_PERIOD 0x0BB8
+
+/// Scan interval used during Link Layer Scanning State when
+/// performing the Limited Discovery procedure
+/// TGAP(lim_disc_scan_int)
+/// recommended value: 11.25ms; (18 decimal)
+#define GAP_LIM_DISC_SCAN_INT 0x0012
+
+/// Scan interval in any discovery or connection establishment
+/// procedure when user initiated: TGAP(scan_fast_interval)
+/// recommended value: 30 to 60 ms; N * 0.625
+#define GAP_SCAN_FAST_INTV 0x0030
+
+/// Scan window in any discovery or connection establishment
+/// procedure when user initiated: TGAP(scan_fast_window)
+/// recommended value: 30 ms; N * 0.625
+#define GAP_SCAN_FAST_WIND 0x0030
+
+/// Scan interval in any discovery or connection establishment
+/// procedure when background scanning: TGAP(scan_slow_interval1)
+/// recommended value: 1.28 s : 0x00CD (205); N * 0.625
+#define GAP_SCAN_SLOW_INTV1 0x00CD
+
+/// Scan interval in any discovery or connection establishment
+/// procedure when background scanning: TGAP(scan_slow_interval2)
+/// recommended value: 2.56 s : 0x019A (410); N * 0.625
+#define GAP_SCAN_SLOW_INTV2 0x019A
+
+/// Scan window in any discovery or connection establishment
+/// procedure when background scanning: TGAP(scan_slow_window1)
+/// recommended value: 11.25 ms : 0x0012 (18); N * 0.625
+#define GAP_SCAN_SLOW_WIND1 0x0012
+
+/// Scan window in any discovery or connection establishment
+/// procedure when background scanning: TGAP(scan_slow_window2)
+/// recommended value: 22.5 ms : 0x0024 (36); N * 0.625
+#define GAP_SCAN_SLOW_WIND2 0x0024
+
+/// Minimum to maximum advertisement interval in any discoverable
+/// or connectable mode when user initiated: TGAP(adv_fast_interval1)
+/// recommended value: 30 to 60 ms; N * 0.625
+#define GAP_ADV_FAST_INTV1 0x0030
+
+/// Minimum to maximum advertisement interval in any discoverable
+/// or connectable mode when user initiated: TGAP(adv_fast_interval2)
+/// recommended value: 100 to 150 ms; N * 0.625
+#define GAP_ADV_FAST_INTV2 0x0064
+
+/// Minimum to maximum advertisement interval in any discoverable or
+/// connectable mode when background advertising: TGAP(adv_slow_interval)
+/// recommended value: 1 to 1.2 s : 0x00B0 (176); N * 0.625
+#define GAP_ADV_SLOW_INTV 0x00B0
+
+/// Minimum to maximum connection interval upon any connection
+/// establishment: TGAP(initial_conn_interval)
+/// recommended value: 30 to 50 ms ; N * 1.25 ms
+#define GAP_INIT_CONN_MIN_INTV 0x0018
+#define GAP_INIT_CONN_MAX_INTV 0x0028
+
+/// RW Defines
+#define GAP_INQ_SCAN_INTV 0x0012
+#define GAP_INQ_SCAN_WIND 0x0012
+
+/// Connection supervision timeout
+/// recommended value: 20s
+#define GAP_CONN_SUPERV_TIMEOUT 0x07D0
+
+/// Minimum connection event
+/// default value: 0x0000
+#define GAP_CONN_MIN_CE 0x0000
+
+/// Maximum connection event
+/// default value: 0xFFFF
+#define GAP_CONN_MAX_CE 0xFFFF
+
+/// Connection latency
+/// default value: 0x0000
+#define GAP_CONN_LATENCY 0x0000
+
+/// GAP Device name Characteristic
+/// Default device name
+#define GAP_DEV_NAME "RIVIERAWAVES-BLE"
+
+/// GAP Appearance or Icon Characteristic - 2 octets
+/// Current appearance value is 0x0000 (unknown appearance)
+/// Description:
+/// http://developer.bluetooth.org/gatt/characteristics/Pages/CharacteristicViewer.aspx?u=org.bluetooth.characteristic.gap.appearance.xml
+#define GAP_APPEARANCE 0x0000
+
+///GAP Peripheral Preferred Connection Parameter - 8 octets
+#define GAP_PPCP_CONN_INTV_MAX 0x0064
+#define GAP_PPCP_CONN_INTV_MIN 0x00C8
+#define GAP_PPCP_SLAVE_LATENCY 0x0000
+#define GAP_PPCP_STO_MULT 0x07D0
+
+
+/*
+ * Enumerations
+ ****************************************************************************************
+ */
+/// GAP Advertising Flags
+enum gap_ad_type
+{
+ /// Flag
+ GAP_AD_TYPE_FLAGS = 0x01,
+ /// Use of more than 16 bits UUID
+ GAP_AD_TYPE_MORE_16_BIT_UUID = 0x02,
+ /// Complete list of 16 bit UUID
+ GAP_AD_TYPE_COMPLETE_LIST_16_BIT_UUID = 0x03,
+ /// Use of more than 32 bit UUD
+ GAP_AD_TYPE_MORE_32_BIT_UUID = 0x04,
+ /// Complete list of 32 bit UUID
+ GAP_AD_TYPE_COMPLETE_LIST_32_BIT_UUID = 0x05,
+ /// Use of more than 128 bit UUID
+ GAP_AD_TYPE_MORE_128_BIT_UUID = 0x06,
+ /// Complete list of 128 bit UUID
+ GAP_AD_TYPE_COMPLETE_LIST_128_BIT_UUID = 0x07,
+ /// Shortened device name
+ GAP_AD_TYPE_SHORTENED_NAME = 0x08,
+ /// Complete device name
+ GAP_AD_TYPE_COMPLETE_NAME = 0x09,
+ /// Transmit power
+ GAP_AD_TYPE_TRANSMIT_POWER = 0x0A,
+ /// Class of device
+ GAP_AD_TYPE_CLASS_OF_DEVICE = 0x0D,
+ /// Simple Pairing Hash C
+ GAP_AD_TYPE_SP_HASH_C = 0x0E,
+ /// Simple Pairing Randomizer
+ GAP_AD_TYPE_SP_RANDOMIZER_R = 0x0F,
+ /// Temporary key value
+ GAP_AD_TYPE_TK_VALUE = 0x10,
+ /// Out of Band Flag
+ GAP_AD_TYPE_OOB_FLAGS = 0x11,
+ /// Slave connection interval range
+ GAP_AD_TYPE_SLAVE_CONN_INT_RANGE = 0x12,
+ /// Require 16 bit service UUID
+ GAP_AD_TYPE_RQRD_16_BIT_SVC_UUID = 0x14,
+ /// Require 32 bit service UUID
+ GAP_AD_TYPE_RQRD_32_BIT_SVC_UUID = 0x1F,
+ /// Require 128 bit service UUID
+ GAP_AD_TYPE_RQRD_128_BIT_SVC_UUID = 0x15,
+ /// Service data 16-bit UUID
+ GAP_AD_TYPE_SERVICE_16_BIT_DATA = 0x16,
+ /// Service data 32-bit UUID
+ GAP_AD_TYPE_SERVICE_32_BIT_DATA = 0x20,
+ /// Service data 128-bit UUID
+ GAP_AD_TYPE_SERVICE_128_BIT_DATA = 0x21,
+ /// Public Target Address
+ GAP_AD_TYPE_PUB_TGT_ADDR = 0x17,
+ /// Random Target Address
+ GAP_AD_TYPE_RAND_TGT_ADDR = 0x18,
+ /// Appearance
+ GAP_AD_TYPE_APPEARANCE = 0x19,
+ /// Advertising Interval
+ GAP_AD_TYPE_ADV_INTV = 0x1A,
+ /// LE Bluetooth Device Address
+ GAP_AD_TYPE_LE_BT_ADDR = 0x1B,
+ /// LE Role
+ GAP_AD_TYPE_LE_ROLE = 0x1C,
+ /// Simple Pairing Hash C-256
+ GAP_AD_TYPE_SPAIR_HASH = 0x1D,
+ /// Simple Pairing Randomizer R-256
+ GAP_AD_TYPE_SPAIR_RAND = 0x1E,
+ /// 3D Information Data
+ GAP_AD_TYPE_3D_INFO = 0x3D,
+
+ /// Manufacturer specific data
+ GAP_AD_TYPE_MANU_SPECIFIC_DATA = 0xFF,
+};
+
+
+/// Random Address type
+enum gap_rnd_addr_type
+{
+ /// Static random address - 11 (MSB->LSB)
+ GAP_STATIC_ADDR = 0xC0,
+ /// Private non resolvable address - 01 (MSB->LSB)
+ GAP_NON_RSLV_ADDR = 0x00,
+ /// Private resolvable address - 01 (MSB->LSB)
+ GAP_RSLV_ADDR = 0x40,
+};
+
+/// Boolean value set
+enum
+{
+ /// Disable
+ GAP_DISABLE = 0x00,
+ /// Enable
+ GAP_ENABLE
+};
+
+
+/// GAP Attribute database handles
+/// Generic Access Profile Service
+enum
+{
+ GAP_IDX_PRIM_SVC,
+ GAP_IDX_CHAR_DEVNAME,
+ GAP_IDX_DEVNAME,
+ GAP_IDX_CHAR_ICON,
+ GAP_IDX_ICON,
+ GAP_IDX_CHAR_SLAVE_PREF_PARAM,
+ GAP_IDX_SLAVE_PREF_PARAM,
+ GAP_IDX_CHAR_CNT_ADDR_RESOL,
+ GAP_IDX_CNT_ADDR_RESOL,
+ GAP_IDX_NUMBER
+};
+
+
+
+/****************** GAP Role **********************/
+enum gap_role
+{
+ /// No role set yet
+ GAP_ROLE_NONE = 0x00,
+
+ /// Observer role
+ GAP_ROLE_OBSERVER = 0x01,
+
+ /// Broadcaster role
+ GAP_ROLE_BROADCASTER = 0x02,
+
+ /// Master/Central role
+ GAP_ROLE_CENTRAL = (0x04 | GAP_ROLE_OBSERVER),
+
+ /// Peripheral/Slave role
+ GAP_ROLE_PERIPHERAL = (0x08 | GAP_ROLE_BROADCASTER),
+
+ /// Device has all role, both peripheral and central
+ GAP_ROLE_ALL = (GAP_ROLE_CENTRAL | GAP_ROLE_PERIPHERAL),
+
+ /// Debug mode used to force LL configuration on BLE 4.0
+ GAP_ROLE_DBG_LE_4_0 = 0x80,
+};
+
+/// Advertising mode
+enum gap_adv_mode
+{
+ /// Mode in non-discoverable
+ GAP_NON_DISCOVERABLE,
+ /// Mode in general discoverable
+ GAP_GEN_DISCOVERABLE,
+ /// Mode in limited discoverable
+ GAP_LIM_DISCOVERABLE,
+ /// Broadcaster mode which is a non discoverable and non connectable mode.
+ GAP_BROADCASTER_MODE
+};
+
+/// Scan mode
+enum gap_scan_mode
+{
+ /// Mode in general discovery
+ GAP_GEN_DISCOVERY,
+ /// Mode in limited discovery
+ GAP_LIM_DISCOVERY,
+ /// Observer mode
+ GAP_OBSERVER_MODE,
+ /// Invalid mode
+ GAP_INVALID_MODE
+};
+
+
+
+/// IO Capability Values
+enum gap_io_cap
+{
+ /// Display Only
+ GAP_IO_CAP_DISPLAY_ONLY = 0x00,
+ /// Display Yes No
+ GAP_IO_CAP_DISPLAY_YES_NO,
+ /// Keyboard Only
+ GAP_IO_CAP_KB_ONLY,
+ /// No Input No Output
+ GAP_IO_CAP_NO_INPUT_NO_OUTPUT,
+ /// Keyboard Display
+ GAP_IO_CAP_KB_DISPLAY,
+ GAP_IO_CAP_LAST
+};
+
+/// TK Type
+enum gap_tk_type
+{
+ /// TK get from out of band method
+ GAP_TK_OOB = 0x00,
+ /// TK generated and shall be displayed by local device
+ GAP_TK_DISPLAY,
+ /// TK shall be entered by user using device keyboard
+ GAP_TK_KEY_ENTRY
+};
+
+/// OOB Data Present Flag Values
+enum gap_oob
+{
+ /// OOB Data not present
+ GAP_OOB_AUTH_DATA_NOT_PRESENT = 0x00,
+ /// OOB data present
+ GAP_OOB_AUTH_DATA_PRESENT,
+ GAP_OOB_AUTH_DATA_LAST
+};
+
+/// Authentication mask
+enum gap_auth_mask
+{
+ /// No Flag set
+ GAP_AUTH_NONE = 0,
+ /// Bond authentication
+ GAP_AUTH_BOND = (1 << 0),
+ /// Man In the middle protection
+ GAP_AUTH_MITM = (1 << 2),
+ /// Secure Connection
+ GAP_AUTH_SEC_CON = (1 << 3),
+ /// Key Notification
+ GAP_AUTH_KEY_NOTIF = (1 << 4)
+};
+
+/// Security Link Level
+enum gap_lk_sec_lvl
+{
+ /// No authentication
+ GAP_LK_NO_AUTH = 0,
+ /// Unauthenticated link
+ GAP_LK_UNAUTH,
+ /// Authenticated link
+ GAP_LK_AUTH,
+ /// Secure Connection link
+ GAP_LK_SEC_CON,
+};
+
+/// Authentication Requirements
+enum gap_auth
+{
+ /// No MITM No Bonding
+ GAP_AUTH_REQ_NO_MITM_NO_BOND = (GAP_AUTH_NONE),
+ /// No MITM Bonding
+ GAP_AUTH_REQ_NO_MITM_BOND = (GAP_AUTH_BOND),
+ /// MITM No Bonding
+ GAP_AUTH_REQ_MITM_NO_BOND = (GAP_AUTH_MITM),
+ /// MITM and Bonding
+ GAP_AUTH_REQ_MITM_BOND = (GAP_AUTH_MITM | GAP_AUTH_BOND),
+ /// SEC_CON and No Bonding
+ GAP_AUTH_REQ_SEC_CON_NO_BOND = (GAP_AUTH_SEC_CON),
+ /// SEC_CON and Bonding
+ GAP_AUTH_REQ_SEC_CON_BOND = (GAP_AUTH_SEC_CON | GAP_AUTH_BOND),
+
+ GAP_AUTH_REQ_LAST,
+
+ /// Mask of authentication features without reserved flag
+ GAP_AUTH_REQ_MASK = 0x1F,
+};
+
+/// Key Distribution Flags
+enum gap_kdist
+{
+ /// No Keys to distribute
+ GAP_KDIST_NONE = 0x00,
+ /// Encryption key in distribution
+ GAP_KDIST_ENCKEY = (1 << 0),
+ /// IRK (ID key)in distribution
+ GAP_KDIST_IDKEY = (1 << 1),
+ /// CSRK(Signature key) in distribution
+ GAP_KDIST_SIGNKEY= (1 << 2),
+ /// LTK in distribution
+ GAP_KDIST_LINKKEY= (1 << 3),
+
+ GAP_KDIST_LAST = (1 << 4)
+};
+
+/// Security Defines
+enum gap_sec_req
+{
+ /// No security (no authentication and encryption)
+ GAP_NO_SEC = 0x00,
+ /// Unauthenticated pairing with encryption
+ GAP_SEC1_NOAUTH_PAIR_ENC,
+ /// Authenticated pairing with encryption
+ GAP_SEC1_AUTH_PAIR_ENC,
+ /// Unauthenticated pairing with data signing
+ GAP_SEC2_NOAUTH_DATA_SGN,
+ /// Authentication pairing with data signing
+ GAP_SEC2_AUTH_DATA_SGN,
+ /// Secure Connection pairing with encryption
+ GAP_SEC1_SEC_CON_PAIR_ENC,
+};
+
+/// device name
+struct gap_dev_name
+{
+ /// name length
+ uint16_t length;
+ /// name value
+ uint8_t value[__ARRAY_EMPTY];
+};
+
+/// Slave preferred connection parameters
+struct gap_slv_pref
+{
+ /// Connection interval minimum
+ uint16_t con_intv_min;
+ /// Connection interval maximum
+ uint16_t con_intv_max;
+ /// Slave latency
+ uint16_t slave_latency;
+ /// Connection supervision timeout multiplier
+ uint16_t conn_timeout;
+};
+
+
+
+
+
+/*************** GAP Structures ********************/
+
+///BD Address structure
+typedef struct
+{
+ ///6-byte array address value
+ uint8_t addr[GAP_BD_ADDR_LEN];
+} bd_addr_t;
+
+///Channel map structure
+typedef struct
+{
+ ///5-byte channel map array
+ uint8_t map[GAP_LE_CHNL_MAP_LEN];
+} le_chnl_map_t;
+
+
+///Random number structure
+typedef struct
+{
+ ///8-byte array for random number
+ uint8_t nb[GAP_RAND_NB_LEN];
+} rand_nb_t;
+
+///Advertising report structure
+typedef struct
+{
+ ///Event type:
+ /// - ADV_CONN_UNDIR: Connectable Undirected advertising
+ /// - ADV_CONN_DIR: Connectable directed advertising
+ /// - ADV_DISC_UNDIR: Discoverable undirected advertising
+ /// - ADV_NONCONN_UNDIR: Non-connectable undirected advertising
+ uint8_t evt_type;
+ ///Advertising address type: public/random
+ uint8_t adv_addr_type;
+ ///Advertising address value
+ bd_addr_t adv_addr;
+ ///Data length in advertising packet
+ uint8_t data_len;
+ ///Data of advertising packet
+ uint8_t data[GAP_ADV_DATA_LEN];
+ ///RSSI value for advertising packet
+ uint8_t rssi;
+} adv_report_t;
+
+
+/// P256 Public key data format
+typedef struct
+{
+ /// X Coordinate of the key
+ uint8_t x[GAP_P256_KEY_LEN];
+ /// X Coordinate of the key
+ uint8_t y[GAP_P256_KEY_LEN];
+} public_key_t;
+
+/// Address information about a device address
+struct gap_bdaddr
+{
+ /// BD Address of device
+ bd_addr_t addr;
+ /// Address type of the device 0=public/1=private random
+ uint8_t addr_type;
+};
+
+/// Resolving list device information
+struct gap_ral_dev_info
+{
+ /// Address type of the device 0=public/1=private random
+ uint8_t addr_type;
+ /// BD Address of device
+ bd_addr_t addr;
+ /// Peer IRK
+ uint8_t peer_irk[GAP_KEY_LEN];
+ /// Local IRK
+ uint8_t local_irk[GAP_KEY_LEN];
+};
+
+/// Generic Security key structure
+struct gap_sec_key
+{
+ /// Key value MSB -> LSB
+ uint8_t key[GAP_KEY_LEN];
+};
+
+
+
+/// @} GAP
+#endif // GAP_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc.h
new file mode 100644
index 0000000000..fe7e57dc24
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc.h
@@ -0,0 +1,231 @@
+/**
+ ****************************************************************************************
+ *
+ * @file gapc.h
+ *
+ * @brief Generic Access Profile Controller Header.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ ****************************************************************************************
+ */
+
+
+#ifndef _GAPC_H_
+#define _GAPC_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup GAPC Generic Access Profile Controller
+ * @ingroup GAP
+ * @brief Generic Access Profile Controller.
+ *
+ * The GAP Controller module is responsible for providing an API to the application in
+ * to perform GAP action related to a BLE connection (pairing, update parameters,
+ * disconnect ...). GAP controller is multi-instantiated, one task instance per BLE
+ * connection.
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "rwip_config.h"
+
+#if (BLE_GAPC)
+
+#include "ke_task.h"
+#include "gap.h"
+#include "smpc.h"
+
+
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+
+/// Operation type
+enum gapc_op_type
+{
+ /// Operation used to manage Link (update params, get peer info)
+ GAPC_OP_LINK_INFO = 0x00,
+
+ /// Operation used to manage SMP
+ GAPC_OP_SMP = 0x01,
+
+ /// Operation used to manage connection update
+ GAPC_OP_LINK_UPD = 0x02,
+
+ /// Max number of operations
+ GAPC_OP_MAX
+};
+
+/// Link security status. This status represents the authentication/authorization/bonding levels of the connection
+enum gapc_lk_sec_req
+{
+ /// Link is bonded
+ GAPC_LK_BONDED,
+ /// Link is Encrypted
+ GAPC_LK_ENCRYPTED,
+ /// Link LTK Exchanged during pairing
+ GAPC_LK_LTK_PRESENT,
+};
+
+/*
+ * TYPE DEFINITIONS
+ ****************************************************************************************
+ */
+
+/// GAP controller environment variable structure.
+struct gapc_env_tag
+{
+ /// Request operation Kernel message
+ void* operation[GAPC_OP_MAX];
+ /// Task id requested disconnection
+ ke_task_id_t disc_requester;
+
+
+ /* Connection parameters to keep */
+
+ /// Security Management Protocol environment variables
+ struct smpc_env smpc;
+
+ /// connection handle
+ uint16_t conhdl;
+
+ /// Configuration fields (@see enum gapc_fields)
+ uint8_t fields;
+
+ // BD Address used for the link that should be kept
+ struct gap_bdaddr src[SMPC_INFO_MAX];
+
+ /// Relevant information of peer LE features 8-byte array
+ uint8_t features;
+};
+
+
+
+/*
+ * MACROS
+ ****************************************************************************************
+ */
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve connection index from connection handle.
+ *
+ * @param[in] conhdl Connection handle
+ *
+ * @return Return found connection index, GAP_INVALID_CONIDX if not found.
+ ****************************************************************************************
+ */
+uint8_t gapc_get_conidx(uint16_t conhdl);
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve connection handle from connection index.
+ *
+ * @param[in] conidx Connection index
+ *
+ * @return Return found connection handle, GAP_INVALID_CONHDL if not found.
+ ****************************************************************************************
+ */
+uint16_t gapc_get_conhdl(uint8_t conidx);
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve connection role from connection index.
+ *
+ * @param[in] conidx Connection index
+ *
+ * @return Return found connection role
+ ****************************************************************************************
+ */
+uint8_t gapc_get_role(uint8_t conidx);
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve connection address information on current link.
+ *
+ * @param[in] conidx Connection index
+ * @param[in] src Connection information source
+ *
+ * @return Return found connection address
+ ****************************************************************************************
+ */
+struct gap_bdaddr* gapc_get_bdaddr(uint8_t conidx, uint8_t src);
+
+
+/**
+ ****************************************************************************************
+ * @brief Check if current link support security requirements.
+ *
+ * @param[in] conidx Connection index
+ * @param[in] sec_req Link security requirement to test
+ *
+ * @return True if link requirement is supported, False else.
+ ****************************************************************************************
+ */
+bool gapc_is_sec_set(uint8_t conidx, uint8_t sec_req);
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve Link Security level
+ *
+ * @param[in] conidx Connection index
+ *
+ * @return Link Security level.
+ ****************************************************************************************
+ */
+uint8_t gapc_lk_sec_lvl_get(uint8_t conidx);
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve the encryption key size of the connection
+ *
+ * @param[in] conidx Connection index
+ *
+ * @return encryption key size (size is 7 - 16 byte range)
+ *
+ ****************************************************************************************
+ */
+uint8_t gapc_enc_keysize_get(uint8_t conidx);
+
+/**
+ ****************************************************************************************
+ * @brief Get Service Change Client Configuration
+ *
+ * @param[in] conidx Connection index
+ *
+ * @return Service Change Client Configuration
+ ****************************************************************************************
+ */
+bool gapc_svc_chg_ccc_get(uint8_t conidx);
+
+/**
+ ****************************************************************************************
+ * @brief Set Service Change Client Configuration
+ *
+ * @param[in] conidx Connection index
+ * @param[in] enable True if CCC is enabled, False else
+ *
+ ****************************************************************************************
+ */
+void gapc_svc_chg_ccc_set(uint8_t conidx, bool enable);
+
+
+#endif // (BLE_GAPC)
+/// @} GAPC
+
+#endif /* _GAPC_H_ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc_int.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc_int.h
new file mode 100644
index 0000000000..e1ecdf9345
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc_int.h
@@ -0,0 +1,391 @@
+/**
+ ****************************************************************************************
+ *
+ * @file gapc_int.h
+ *
+ * @brief Generic Access Profile Controller Internal Header.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ ****************************************************************************************
+ */
+#ifndef _GAPC_INT_H_
+#define _GAPC_INT_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup GAPC_INT Generic Access Profile Controller Internals
+ * @ingroup GAPC
+ * @brief Handles ALL Internal GAPC API
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "gapc.h"
+#include "gapc_task.h"
+
+#if (BLE_GAPC)
+
+/*
+ * MACROS
+ ****************************************************************************************
+ */
+
+/// Set link configuration field
+#define GAPC_SET_FIELD(conidx, field, value)\
+ (gapc_env[conidx]->fields) = ((gapc_env[conidx]->fields) & (~GAPC_##field##_MASK)) \
+ | (((value) << GAPC_##field) & (GAPC_##field##_MASK))
+
+
+/// Get link configuration field
+#define GAPC_GET_FIELD(conidx, field)\
+ (((gapc_env[conidx]->fields) & (GAPC_##field##_MASK)) >> GAPC_##field)
+
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/// number of GAP Controller Process
+#define GAPC_IDX_MAX BLE_CONNECTION_MAX
+
+
+
+
+/// states of GAP Controller task
+enum gapc_state_id
+{
+ /// Connection ready state
+ GAPC_READY,
+
+ /// Link Operation on-going
+ GAPC_LINK_INFO_BUSY = (1 << GAPC_OP_LINK_INFO),
+ /// SMP Operation on-going
+ GAPC_SMP_BUSY = (1 << GAPC_OP_SMP),
+ /// Update Operation on-going
+ GAPC_LINK_UPD_BUSY = (1 << GAPC_OP_LINK_UPD),
+ /// SMP start encryption on-going
+ GAPC_ENCRYPT_BUSY = (1 << GAPC_OP_MAX),
+
+ /// Disconnection on-going
+ GAPC_DISC_BUSY = 0x1F,
+ /// Free state
+ GAPC_FREE = 0X3F,
+
+ /// Number of defined states.
+ GAPC_STATE_MAX
+};
+
+
+
+/// fields definitions.
+/// Configuration fields:
+/// 7 6 5 4 3 2 1 0
+/// +----+----+----+----+----+----+----+----+
+/// |RFU |SVCH|ROLE|LTK |ENC |BOND| SEC_LVL |
+/// +----+----+----+----+----+----+----+----+
+enum gapc_fields
+{
+ /// Link Security Level
+ GAPC_SEC_LVL = 0,
+ GAPC_SEC_LVL_MASK = 0x03,
+ /// Link Bonded or not
+ GAPC_BONDED = 2,
+ GAPC_BONDED_MASK = 0x04,
+ /// Encrypted connection or not
+ GAPC_ENCRYPTED = 3,
+ GAPC_ENCRYPTED_MASK = 0x08,
+ /// Ltk present and exchanged during pairing
+ GAPC_LTK_PRESENT = 4,
+ GAPC_LTK_PRESENT_MASK = 0x10,
+ /// Local connection role
+ GAPC_ROLE = 5,
+ GAPC_ROLE_MASK = 0x20,
+ /// Service Changed CCC configuration
+ GAPC_SVC_CHG_CCC = 6,
+ GAPC_SVC_CHG_CCC_MASK = 0x40,
+};
+
+
+/*
+ * GLOBAL VARIABLE DECLARATIONS
+ ****************************************************************************************
+ */
+extern struct gapc_env_tag* gapc_env[GAPC_IDX_MAX];
+
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief Initialize Generic Access Profile Controller Module.
+ *
+ * @param[in] reset true if it's requested by a reset; false if it's boot initialization
+ *
+ ****************************************************************************************
+ */
+void gapc_init(bool reset);
+
+
+/**
+ ****************************************************************************************
+ * @brief A connection has been created, initialize Controller task.
+ *
+ * This function find first available task index available for new connection.
+ * It triggers also connection event to task that has requested the connection.
+ *
+ * @param[in] msgid Message id for normal or enhanced privacy
+ * @param[in] con_params Connection parameters from lower layers
+ * @param[in] requester Task that request the connection to send indication(s)
+ * @param[in] laddr Local BD Address
+ * @param[in] laddr_type Local BD Address Type (PUBLIC or RAND)
+ *
+ * @return Connection index allocated to the new connection.
+ ****************************************************************************************
+ */
+uint8_t gapc_con_create(ke_msg_id_t const msgid, struct hci_le_enh_con_cmp_evt const *con_params,
+ ke_task_id_t requester, bd_addr_t* laddr, uint8_t laddr_type);
+
+/**
+ ****************************************************************************************
+ * @brief A connection has been disconnected, uninitialized Controller task.
+ *
+ * unregister connection, and destroy environment variable allocated for current connection.
+ *
+ * @param[in] conidx Connection index
+ *
+ * @return Connection index of the connection.
+ ****************************************************************************************
+ */
+uint8_t gapc_con_cleanup(uint8_t conidx);
+
+
+/**
+ ****************************************************************************************
+ * @brief Send Disconnection indication to specific task
+ *
+ * @param[in] conidx Connection index
+ * @param[in] reason Disconnection reason
+ * @param[in] conhdl Connection handle
+ * @param[in] dest_id Message destination ID
+ *
+ ****************************************************************************************
+ */
+void gapc_send_disconect_ind(uint8_t conidx, uint8_t reason, uint8_t conhdl,
+ ke_task_id_t dest_id);
+
+
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve connection CSRK information on current link.
+ *
+ * @param[in] conidx Connection index
+ * @param[in] src Connection information source
+ *
+ * @return Return found connection CSRK
+ ****************************************************************************************
+ */
+struct gap_sec_key* gapc_get_csrk(uint8_t conidx, uint8_t src);
+
+/**
+ ****************************************************************************************
+ * @brief Return the sign counter value for the specified connection index.
+ *
+ * @param[in] conidx Connection index
+ * @param[in] src Connection information source
+ *
+ * @return the requested signCounter value
+ ****************************************************************************************
+ */
+uint32_t gapc_get_sign_counter(uint8_t conidx, uint8_t src);
+
+/**
+ * @brief Send a complete event of ongoing executed operation to requester.
+ * It also clean-up variable used for ongoing operation.
+ *
+ * @param[in] conidx Connection index
+ * @param[in] op_type Operation type.
+ * @param[in] status Status of completed operation
+ */
+void gapc_send_complete_evt(uint8_t conidx, uint8_t op_type, uint8_t status);
+
+/**
+ ****************************************************************************************
+ * @brief Send operation completed message with status error code not related to a
+ * running operation.
+ *
+ * @param[in] conidx Connection index
+ * @param[in] operation Operation code
+ * @param[in] requester requester of operation
+ * @param[in] status Error status code
+ ****************************************************************************************
+ */
+void gapc_send_error_evt(uint8_t conidx, uint8_t operation, const ke_task_id_t requester, uint8_t status);
+
+
+/**
+ ****************************************************************************************
+ * @brief Get operation on going
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] op_type Operation type.
+ *
+ * @return operation code on going
+ ****************************************************************************************
+ */
+uint8_t gapc_get_operation(uint8_t conidx, uint8_t op_type);
+
+/**
+ ****************************************************************************************
+ * @brief Get operation pointer
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] op_type Operation type.
+ *
+ * @return operation pointer on going
+ ****************************************************************************************
+ */
+void* gapc_get_operation_ptr(uint8_t conidx, uint8_t op_type);
+
+
+/**
+ ****************************************************************************************
+ * @brief Set operation pointer
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] op_type Operation type.
+ * @param[in] op Operation pointer.
+ *
+ ****************************************************************************************
+ */
+void gapc_set_operation_ptr(uint8_t conidx, uint8_t op_type, void* op);
+
+/**
+ ****************************************************************************************
+ * @brief Operation execution not finish, request kernel to reschedule it in order to
+ * continue its execution
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] op_type Operation type.
+ *
+ * @return if operation has been rescheduled (not done if operation pointer is null)
+ ****************************************************************************************
+ */
+bool gapc_reschedule_operation(uint8_t conidx, uint8_t op_type);
+
+/**
+ ****************************************************************************************
+ * @brief Get requester of on going operation
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] op_type Operation type.
+ *
+ * @return task that requests to execute the operation
+ ****************************************************************************************
+ */
+ke_task_id_t gapc_get_requester(uint8_t conidx, uint8_t op_type);
+
+
+
+
+/**
+ ****************************************************************************************
+ * @brief Set the encryption key size of the connection
+ *
+ * @param[in] conidx Connection index
+ * @param[in] key_size encryption key size (size is 7 - 16 byte range)
+ *
+ ****************************************************************************************
+ */
+void gapc_enc_keysize_set(uint8_t conidx, uint8_t key_size);
+
+
+/**
+ ****************************************************************************************
+ * @brief Update link status, current link is now encrypted
+ *
+ * @param[in] conidx Connection index
+ *
+ ****************************************************************************************
+ */
+void gapc_link_encrypted(uint8_t conidx);
+
+/**
+ ****************************************************************************************
+ * @brief Update link authentication level
+ *
+ * @param[in] conidx Connection index
+ * @param[in] auth Link authentication level
+ * @param[in] ltk_present Link paired and an LTK has been exchanged
+ *
+ ****************************************************************************************
+ */
+void gapc_auth_set(uint8_t conidx, uint8_t auth, bool ltk_present);
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve link authentication level
+ *
+ * @param[in] conidx Connection index
+ * @return Link authentication level
+ ****************************************************************************************
+ */
+uint8_t gapc_auth_get(uint8_t conidx);
+
+/**
+ ****************************************************************************************
+ * @brief Update task state
+ *
+ * @param[in] conidx Connection index
+ * @param[in] state to update
+ * @param[in] set state to busy (true) or idle (false)
+ *
+ ****************************************************************************************
+ */
+void gapc_update_state(uint8_t conidx, ke_state_t state, bool busy);
+
+
+/**
+ ****************************************************************************************
+ * @brief Checks connection parameters values
+ *
+ * @param[in] intv_max maximum interval
+ * @param[in] intv_min minimum interval
+ * @param[in] latency latency
+ * @param[in] timeout timeout value
+ *
+ * @return true if OK, false if not OK
+ ****************************************************************************************
+ */
+bool gapc_param_update_sanity(uint16_t intv_max, uint16_t intv_min, uint16_t latency, uint16_t timeout);
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+int gapc_process_op(uint8_t conidx, uint8_t op_type, void* op_msg, enum gapc_operation* supp_ops);
+
+
+
+
+/*
+ * TASK DESCRIPTOR DECLARATIONS
+ ****************************************************************************************
+ */
+extern const struct ke_state_handler gapc_default_handler;
+extern ke_state_t gapc_state[GAPC_IDX_MAX];
+
+#endif // (BLE_GAPC)
+/// @} GAPC_INT
+
+#endif /* _GAPC_INT_H_ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc_sig.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc_sig.h
new file mode 100644
index 0000000000..352724f30e
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc_sig.h
@@ -0,0 +1,64 @@
+/**
+ ****************************************************************************************
+ *
+ * @file gapc_sig.h
+ *
+ * @brief Generic Access Profile Controller Signaling PDU Handler.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ ****************************************************************************************
+ */
+
+#ifndef _GAPC_SIG_H_
+#define _GAPC_SIG_H_
+
+
+/**
+ ****************************************************************************************
+ * @addtogroup GAPC_SIG Generic Access Profile Controller Signaling PDU Handler.
+ * @ingroup GAPC
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "rwip_config.h"
+
+#if (BLE_GAPC)
+#include "l2cc_pdu.h"
+
+
+#if (BLE_CENTRAL)
+/**
+ ****************************************************************************************
+ * @brief Sends parameter response
+ *
+ * @param[in] conidx connection index
+ * @param[in] result response result
+ * @param[in] pkt_id Packet identifier
+ ****************************************************************************************
+ */
+void gapc_sig_send_param_resp(uint8_t conidx, uint16_t result, uint8_t pkt_id);
+#endif // (BLE_CENTRAL)
+
+/**
+ ****************************************************************************************
+ * @brief Handles reception of L2CAP signaling messages from peer device.
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] pdu PDU Received
+ *
+ * @return If the message was consumed or not.
+ ****************************************************************************************
+ */
+int gapc_sig_pdu_recv_handler(uint8_t conidx, struct l2cc_pdu *pdu);
+
+#endif // (BLE_GAPC)
+
+#endif // _GAPC_SIG_H_
+
+/// @} GAPC_SIG
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc_task.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc_task.h
new file mode 100644
index 0000000000..79632e5d45
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc_task.h
@@ -0,0 +1,931 @@
+/**
+ ****************************************************************************************
+ *
+ * @file gapc_task.h
+ *
+ * @brief Generic Access Profile Controller Task Header.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ ****************************************************************************************
+ */
+#ifndef _GAPC_TASK_H_
+#define _GAPC_TASK_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup GAPC_TASK Generic Access Profile Controller Task
+ * @ingroup GAPC
+ * @brief Handles ALL messages to/from GAP Controller block.
+ *
+ * It handles messages from lower and higher layers related to an ongoing connection.
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "rwip_task.h" // Task definitions
+#include "gap.h"
+#include
+
+
+/*
+ * MACROS
+ ****************************************************************************************
+ */
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+
+/// GAP Controller Task messages
+enum gapc_msg_id
+{
+ /* Default event */
+ /// Command Complete event
+ GAPC_CMP_EVT = TASK_FIRST_MSG(TASK_ID_GAPC),
+
+ /* Connection state information */
+ /// Indicate that a connection has been established
+ GAPC_CONNECTION_REQ_IND,
+ /// Set specific link data configuration.
+ GAPC_CONNECTION_CFM,
+
+ /// Indicate that a link has been disconnected
+ GAPC_DISCONNECT_IND,
+
+ /* Link management command */
+ /// Request disconnection of current link command.
+ GAPC_DISCONNECT_CMD,
+
+ /* Peer device info */
+ /// Retrieve information command
+ GAPC_GET_INFO_CMD,
+ /// Peer device attribute DB info such as Device Name, Appearance or Slave Preferred Parameters
+ GAPC_PEER_ATT_INFO_IND,
+ /// Indication of peer version info
+ GAPC_PEER_VERSION_IND,
+ /// Indication of peer features info
+ GAPC_PEER_FEATURES_IND,
+ /// Indication of ongoing connection RSSI
+ GAPC_CON_RSSI_IND,
+
+ /* Device Name Management */
+ /// Peer device request local device info such as name, appearance or slave preferred parameters
+ GAPC_GET_DEV_INFO_REQ_IND,
+ /// Send requested info to peer device
+ GAPC_GET_DEV_INFO_CFM,
+ /// Peer device request to modify local device info such as name or appearance
+ GAPC_SET_DEV_INFO_REQ_IND,
+ /// Local device accept or reject device info modification
+ GAPC_SET_DEV_INFO_CFM,
+
+ /* Connection parameters update */
+ /// Perform update of connection parameters command
+ GAPC_PARAM_UPDATE_CMD,
+ /// Request of updating connection parameters indication
+ GAPC_PARAM_UPDATE_REQ_IND,
+ /// Master confirm or not that parameters proposed by slave are accepted or not
+ GAPC_PARAM_UPDATE_CFM,
+ /// Connection parameters updated indication
+ GAPC_PARAM_UPDATED_IND,
+
+ /* Bonding procedure */
+ /// Start Bonding command procedure
+ GAPC_BOND_CMD,
+ /// Bonding requested by peer device indication message.
+ GAPC_BOND_REQ_IND,
+ /// Confirm requested bond information.
+ GAPC_BOND_CFM,
+ /// Bonding information indication message
+ GAPC_BOND_IND,
+
+ /* Encryption procedure */
+ /// Start Encryption command procedure
+ GAPC_ENCRYPT_CMD,
+ /// Encryption requested by peer device indication message.
+ GAPC_ENCRYPT_REQ_IND,
+ /// Confirm requested Encryption information.
+ GAPC_ENCRYPT_CFM,
+ /// Encryption information indication message
+ GAPC_ENCRYPT_IND,
+
+ /* Security request procedure */
+ /// Start Security Request command procedure
+ GAPC_SECURITY_CMD,
+ /// Security requested by peer device indication message
+ GAPC_SECURITY_IND,
+
+ /* Signature procedure */
+ /// Indicate the current sign counters to the application
+ GAPC_SIGN_COUNTER_IND,
+
+ /* Device information */
+ /// Indication of ongoing connection Channel Map
+ GAPC_CON_CHANNEL_MAP_IND,
+
+
+ /* Deprecated */
+ /// Deprecated messages
+ GAPC_DEPRECATED_0,
+ GAPC_DEPRECATED_1,
+ GAPC_DEPRECATED_2,
+ GAPC_DEPRECATED_3,
+ GAPC_DEPRECATED_4,
+ GAPC_DEPRECATED_5,
+ GAPC_DEPRECATED_6,
+ GAPC_DEPRECATED_7,
+ GAPC_DEPRECATED_8,
+ GAPC_DEPRECATED_9,
+
+ /* LE Ping */
+ /// Update LE Ping timeout value
+ GAPC_SET_LE_PING_TO_CMD,
+ /// LE Ping timeout indication
+ GAPC_LE_PING_TO_VAL_IND,
+ /// LE Ping timeout expires indication
+ GAPC_LE_PING_TO_IND,
+
+ /* LE Data Length extension*/
+ /// LE Set Data Length Command
+ GAPC_SET_LE_PKT_SIZE_CMD,
+ /// LE Set Data Length Indication
+ GAPC_LE_PKT_SIZE_IND,
+
+ /* Secure Connections */
+ /// Request to inform the remote device when keys have been entered or erased
+ GAPC_KEY_PRESS_NOTIFICATION_CMD,
+ /// Indication that a KeyPress has been performed on the peer device.
+ GAPC_KEY_PRESS_NOTIFICATION_IND,
+
+ // ---------------------- INTERNAL API ------------------------
+ /* Internal messages for timer events, not part of API*/
+ /// Signature procedure
+ GAPC_SIGN_CMD,
+ /// Signature result
+ GAPC_SIGN_IND,
+
+ /// Parameter update procedure timeout indication
+ GAPC_PARAM_UPDATE_TO_IND,
+ /// Pairing procedure timeout indication
+ GAPC_SMP_TIMEOUT_TIMER_IND,
+ /// Pairing repeated attempts procedure timeout indication
+ GAPC_SMP_REP_ATTEMPTS_TIMER_IND,
+};
+
+
+
+
+/// request operation type - application interface
+enum gapc_operation
+{
+ /* Operation Flags */
+ /* No Operation (if nothing has been requested) */
+ /* ************************************************ */
+ /// No operation
+ GAPC_NO_OP = 0x00,
+
+ /* Connection management */
+ /// Disconnect link
+ GAPC_DISCONNECT,
+
+ /* Connection information */
+ /// Retrieve name of peer device.
+ GAPC_GET_PEER_NAME,
+ /// Retrieve peer device version info.
+ GAPC_GET_PEER_VERSION,
+ /// Retrieve peer device features.
+ GAPC_GET_PEER_FEATURES,
+ /// Get Peer device appearance
+ GAPC_GET_PEER_APPEARANCE,
+ /// Get Peer device Slaved Preferred Parameters
+ GAPC_GET_PEER_SLV_PREF_PARAMS,
+ /// Retrieve connection RSSI.
+ GAPC_GET_CON_RSSI,
+ /// Retrieve Connection Channel MAP.
+ GAPC_GET_CON_CHANNEL_MAP,
+
+ /* Connection parameters update */
+ /// Perform update of connection parameters.
+ GAPC_UPDATE_PARAMS,
+
+ /* Security procedures */
+ /// Start bonding procedure.
+ GAPC_BOND,
+ /// Start encryption procedure.
+ GAPC_ENCRYPT,
+ /// Start security request procedure
+ GAPC_SECURITY_REQ,
+
+ /* Deprecated */
+ /// Deprecated operation
+ GAPC_OP_DEPRECATED_0,
+ GAPC_OP_DEPRECATED_1,
+ GAPC_OP_DEPRECATED_2,
+ GAPC_OP_DEPRECATED_3,
+ GAPC_OP_DEPRECATED_4,
+
+ /* LE Ping*/
+ /// get timer timeout value
+ GAPC_GET_LE_PING_TO,
+ /// set timer timeout value
+ GAPC_SET_LE_PING_TO,
+
+ /* LE Data Length extension*/
+ /// LE Set Data Length
+ GAPC_SET_LE_PKT_SIZE,
+
+ /* Central Address resolution supported*/
+ GAPC_GET_ADDR_RESOL_SUPP,
+
+ /* Secure Connections */
+ /// Request to inform the remote device when keys have been entered or erased
+ GAPC_KEY_PRESS_NOTIFICATION,
+
+ // ---------------------- INTERNAL API ------------------------
+ /* Packet signature */
+ /// sign an attribute packet
+ GAPC_SIGN_PACKET,
+ /// Verify signature or an attribute packet
+ GAPC_SIGN_CHECK,
+};
+
+/// Bond event type.
+enum gapc_bond
+{
+ /// Bond Pairing request
+ GAPC_PAIRING_REQ,
+ /// Respond to Pairing request
+ GAPC_PAIRING_RSP,
+
+ /// Pairing Finished information
+ GAPC_PAIRING_SUCCEED,
+ /// Pairing Failed information
+ GAPC_PAIRING_FAILED,
+
+ /// Used to retrieve pairing Temporary Key
+ GAPC_TK_EXCH,
+ /// Used for Identity Resolving Key exchange
+ GAPC_IRK_EXCH,
+ /// Used for Connection Signature Resolving Key exchange
+ GAPC_CSRK_EXCH,
+ /// Used for Long Term Key exchange
+ GAPC_LTK_EXCH,
+
+ /// Bond Pairing request issue, Repeated attempt
+ GAPC_REPEATED_ATTEMPT,
+
+ /// Out of Band - exchange of confirm and rand.
+ GAPC_OOB_EXCH,
+
+ /// Numeric Comparison - Exchange of Numeric Value -
+ GAPC_NC_EXCH
+};
+
+/// List of device info that should be provided by application
+enum gapc_dev_info
+{
+ /// Device Name
+ GAPC_DEV_NAME,
+ /// Device Appearance Icon
+ GAPC_DEV_APPEARANCE,
+ /// Device Slave preferred parameters
+ GAPC_DEV_SLV_PREF_PARAMS,
+ /// Device Central address resolution
+ GAPC_DEV_CTL_ADDR_RESOL,
+ /// maximum device info parameter
+ GAPC_DEV_INFO_MAX,
+};
+
+/// List of features available on a device
+enum gapc_features_list
+{
+ /// LE encryption
+ GAPC_ENCRYPT_FEAT_MASK = (1 << 0),
+ /// Connection Parameters Request Procedure
+ GAPC_CONN_PARAM_REQ_FEAT_MASK = (1 << 1),
+ /// Extended Reject Indication
+ GAPC_EXT_REJECT_IND_FEAT_MASK = (1 << 2),
+ /// Slave-initiated Features Exchange
+ GAPC_SLAVE_FEAT_EXCH_FEAT_MASK = (1 << 3),
+ /// LE ping
+ GAPC_LE_PING_FEAT_MASK = (1 << 4)
+};
+
+/*
+ * TYPE DEFINITIONS
+ ****************************************************************************************
+ */
+
+/// Operation command structure in order to keep requested operation.
+struct gapc_operation_cmd
+{
+ /// GAP request type
+ uint8_t operation;
+};
+
+
+/// Command complete event data structure
+struct gapc_cmp_evt
+{
+ /// GAP request type
+ uint8_t operation;
+ /// Status of the request
+ uint8_t status;
+};
+
+/// Indicate that a connection has been established
+struct gapc_connection_req_ind
+{
+ /// Connection handle
+ uint16_t conhdl;
+ /// Connection interval
+ uint16_t con_interval;
+ /// Connection latency
+ uint16_t con_latency;
+ /// Link supervision timeout
+ uint16_t sup_to;
+ /// Clock accuracy
+ uint8_t clk_accuracy;
+ /// Peer address type
+ uint8_t peer_addr_type;
+ /// Peer BT address
+ bd_addr_t peer_addr;
+};
+
+
+/// Set specific link data configuration.
+struct gapc_connection_cfm
+{
+ /// Local CSRK value
+ struct gap_sec_key lcsrk;
+ /// Local signature counter value
+ uint32_t lsign_counter;
+
+ /// Remote CSRK value
+ struct gap_sec_key rcsrk;
+ /// Remote signature counter value
+ uint32_t rsign_counter;
+
+ /// Authentication (@see gap_auth)
+ uint8_t auth;
+ /// Service Changed Indication enabled
+ uint8_t svc_changed_ind_enable;
+ /// LTK exchanged during pairing.
+ bool ltk_present;
+};
+
+
+/// Request disconnection of current link command.
+struct gapc_disconnect_cmd
+{
+ /// GAP request type:
+ /// - GAPC_DISCONNECT: Disconnect link.
+ uint8_t operation;
+
+ /// Reason of disconnection
+ uint8_t reason;
+};
+
+
+/// Indicate that a link has been disconnected
+struct gapc_disconnect_ind
+{
+ /// Connection handle
+ uint16_t conhdl;
+ /// Reason of disconnection
+ uint8_t reason;
+};
+
+
+/// Retrieve information command
+struct gapc_get_info_cmd
+{
+ /// GAP request type:
+ /// - GAPC_GET_PEER_NAME: Retrieve name of peer device.
+ /// - GAPC_GET_PEER_VERSION: Retrieve peer device version info.
+ /// - GAPC_GET_PEER_FEATURES: Retrieve peer device features.
+ /// - GAPC_GET_CON_RSSI: Retrieve connection RSSI.
+ /// - GAPC_GET_CON_CHANNEL_MAP: Retrieve Connection Channel MAP.
+ /// - GAPC_GET_PEER_APPEARANCE: Get Peer device appearance
+ /// - GAPC_GET_PEER_SLV_PREF_PARAMS: Get Peer device Slaved Preferred Parameters
+ /// - GAPC_GET_ADDR_RESOL_SUPP: Address Resolution Supported
+ /// - GAPC_GET_LE_PING_TIMEOUT: Retrieve LE Ping Timeout Value
+ uint8_t operation;
+};
+
+/// device information data
+union gapc_dev_info_val
+{
+ /// Device name
+ struct gap_dev_name name;
+ /// Appearance Icon
+ uint16_t appearance;
+ /// Slave preferred parameters
+ struct gap_slv_pref slv_params;
+ /// Central address resolution
+ uint8_t cnt_addr_resol;
+};
+
+/// Peer device attribute DB info such as Device Name, Appearance or Slave Preferred Parameters
+struct gapc_peer_att_info_ind
+{
+ /// Requested information
+ /// - GAPC_DEV_NAME: Device Name
+ /// - GAPC_DEV_APPEARANCE: Device Appearance Icon
+ /// - GAPC_DEV_SLV_PREF_PARAMS: Device Slave preferred parameters
+ /// - GAPC_GET_ADDR_RESOL_SUPP: Address resolution supported
+ uint8_t req;
+ /// Attribute handle
+ uint16_t handle;
+
+ /// device information data
+ union gapc_dev_info_val info;
+};
+
+/// Indication of peer version info
+struct gapc_peer_version_ind
+{
+ /// Manufacturer name
+ uint16_t compid;
+ /// LMP subversion
+ uint16_t lmp_subvers;
+ /// LMP version
+ uint8_t lmp_vers;
+};
+
+/// Indication of peer features info
+struct gapc_peer_features_ind
+{
+ /// 8-byte array for LE features
+ uint8_t features[GAP_LE_FEATS_LEN];
+};
+
+/// Indication of ongoing connection RSSI
+struct gapc_con_rssi_ind
+{
+ /// RSSI value
+ int8_t rssi;
+};
+/// Indication of ongoing connection Channel Map
+struct gapc_con_channel_map_ind
+{
+ /// channel map value
+ le_chnl_map_t ch_map;
+};
+
+/// Sign counter value changed due to packet signing or signature verification.
+struct gapc_sign_counter_updated_ind
+{
+ /// New Local signature counter value
+ uint32_t lsign_counter;
+ /// New Remote signature counter value
+ uint32_t rsign_counter;
+};
+
+/// Indication of LE Ping
+struct gapc_le_ping_to_val_ind
+{
+ ///Authenticated payload timeout
+ uint16_t timeout;
+};
+
+
+/// Peer device request local device info such as name, appearance or slave preferred parameters
+struct gapc_get_dev_info_req_ind
+{
+ /// Requested information
+ /// - GAPC_DEV_NAME: Device Name
+ /// - GAPC_DEV_APPEARANCE: Device Appearance Icon
+ /// - GAPC_DEV_SLV_PREF_PARAMS: Device Slave preferred parameters
+ uint8_t req;
+};
+
+
+
+/// Send requested info to peer device
+struct gapc_get_dev_info_cfm
+{
+ /// Requested information
+ /// - GAPC_DEV_NAME: Device Name
+ /// - GAPC_DEV_APPEARANCE: Device Appearance Icon
+ /// - GAPC_DEV_SLV_PREF_PARAMS: Device Slave preferred parameters
+ uint8_t req;
+
+ /// Peer device information data
+ union gapc_dev_info_val info;
+};
+
+/// Peer device request to modify local device info such as name or appearance
+struct gapc_set_dev_info_req_ind
+{
+ /// Requested information
+ /// - GAPC_DEV_NAME: Device Name
+ /// - GAPC_DEV_APPEARANCE: Device Appearance Icon
+ uint8_t req;
+
+ /// device information data
+ union gapc_set_dev_info
+ {
+ /// Device name
+ struct gap_dev_name name;
+ /// Appearance Icon
+ uint16_t appearance;
+ } info;
+};
+
+/// Local device accept or reject device info modification
+struct gapc_set_dev_info_cfm
+{
+ /// Requested information
+ /// - GAPC_DEV_NAME: Device Name
+ /// - GAPC_DEV_APPEARANCE: Device Appearance Icon
+ uint8_t req;
+
+ /// Status code used to know if requested has been accepted or not
+ uint8_t status;
+};
+
+/// Connection Parameter used to update connection parameters
+struct gapc_conn_param
+{
+ /// Connection interval minimum
+ uint16_t intv_min;
+ /// Connection interval maximum
+ uint16_t intv_max;
+ /// Latency
+ uint16_t latency;
+ /// Supervision timeout
+ uint16_t time_out;
+};
+
+/// Perform update of connection parameters command
+struct gapc_param_update_cmd
+{
+ /// GAP request type:
+ /// - GAPC_UPDATE_PARAMS: Perform update of connection parameters.
+ uint8_t operation;
+ /// Internal parameter used to manage internally l2cap packet identifier for signaling
+ uint8_t pkt_id;
+ /// Connection interval minimum
+ uint16_t intv_min;
+ /// Connection interval maximum
+ uint16_t intv_max;
+ /// Latency
+ uint16_t latency;
+ /// Supervision timeout
+ uint16_t time_out;
+ /// Minimum Connection Event Duration
+ uint16_t ce_len_min;
+ /// Maximum Connection Event Duration
+ uint16_t ce_len_max;
+};
+
+/// Request of updating connection parameters indication
+struct gapc_param_update_req_ind
+{
+ /// Connection interval minimum
+ uint16_t intv_min;
+ /// Connection interval maximum
+ uint16_t intv_max;
+ /// Latency
+ uint16_t latency;
+ /// Supervision timeout
+ uint16_t time_out;
+};
+
+/// Connection parameters updated indication
+struct gapc_param_updated_ind
+{
+ ///Connection interval value
+ uint16_t con_interval;
+ ///Connection latency value
+ uint16_t con_latency;
+ ///Supervision timeout
+ uint16_t sup_to;
+};
+
+/// Master confirm or not that parameters proposed by slave are accepted or not
+struct gapc_param_update_cfm
+{
+ /// True to accept slave connection parameters, False else.
+ bool accept;
+ /// Minimum Connection Event Duration
+ uint16_t ce_len_min;
+ /// Maximum Connection Event Duration
+ uint16_t ce_len_max;
+};
+
+/// Pairing parameters
+struct gapc_pairing
+{
+ /// IO capabilities (@see gap_io_cap)
+ uint8_t iocap;
+ /// OOB information (@see gap_oob)
+ uint8_t oob;
+ /// Authentication (@see gap_auth)
+ /// Note in BT 4.1 the Auth Field is extended to include 'Key Notification' and
+ /// and 'Secure Connections'.
+ uint8_t auth;
+ /// Encryption key size (7 to 16)
+ uint8_t key_size;
+ ///Initiator key distribution (@see gap_kdist)
+ uint8_t ikey_dist;
+ ///Responder key distribution (@see gap_kdist)
+ uint8_t rkey_dist;
+
+ /// Device security requirements (minimum security level). (@see gap_sec_req)
+ uint8_t sec_req;
+};
+
+/// Long Term Key information
+struct gapc_ltk
+{
+ /// Long Term Key
+ struct gap_sec_key ltk;
+ /// Encryption Diversifier
+ uint16_t ediv;
+ /// Random Number
+ rand_nb_t randnb;
+ /// Encryption key size (7 to 16)
+ uint8_t key_size;
+
+ uint8_t key_num;
+};
+/// Out of Band Information
+struct gapc_oob
+{
+ /// Confirm Value
+ uint8_t conf[GAP_KEY_LEN];
+ /// Random Number
+ uint8_t rand[GAP_KEY_LEN];
+};
+
+struct gapc_nc
+{
+ uint8_t value[4];
+};
+
+/// Identity Resolving Key information
+struct gapc_irk
+{
+ /// Identity Resolving Key
+ struct gap_sec_key irk;
+ /// Device BD Identity Address
+ struct gap_bdaddr addr;
+};
+
+
+/// Start Bonding command procedure
+struct gapc_bond_cmd
+{
+ /// GAP request type:
+ /// - GAPC_BOND: Start bonding procedure.
+ uint8_t operation;
+ /// Pairing information
+ struct gapc_pairing pairing;
+};
+
+/// Bonding requested by peer device indication message.
+struct gapc_bond_req_ind
+{
+ /// Bond request type (@see gapc_bond)
+ uint8_t request;
+
+ /// Bond procedure requested information data
+ union gapc_bond_req_data
+ {
+ /// Authentication level (@see gap_auth) (if request = GAPC_PAIRING_REQ)
+ uint8_t auth_req;
+ /// LTK Key Size (if request = GAPC_LTK_EXCH)
+ uint8_t key_size;
+ /// Device IO used to get TK: (if request = GAPC_TK_EXCH)
+ /// - GAP_TK_OOB: TK get from out of band method
+ /// - GAP_TK_DISPLAY: TK generated and shall be displayed by local device
+ /// - GAP_TK_KEY_ENTRY: TK shall be entered by user using device keyboard
+ uint8_t tk_type;
+
+ /// Addition OOB Data for the OOB Conf and Rand values
+ struct gapc_oob oob_data;
+ /// Numeric Comparison Data
+ struct gapc_nc nc_data;
+ } data;
+};
+
+/// Confirm requested bond information.
+struct gapc_bond_cfm
+{
+ /// Bond request type (@see gapc_bond)
+ uint8_t request;
+ /// Request accepted
+ uint8_t accept;
+
+ /// Bond procedure information data
+ union gapc_bond_cfm_data
+ {
+ /// Pairing Features (request = GAPC_PAIRING_RSP)
+ struct gapc_pairing pairing_feat;
+ /// LTK (request = GAPC_LTK_EXCH)
+ struct gapc_ltk ltk;
+ /// CSRK (request = GAPC_CSRK_EXCH)
+ struct gap_sec_key csrk;
+ /// TK (request = GAPC_TK_EXCH)
+ struct gap_sec_key tk;
+ /// IRK (request = GAPC_IRK_EXCH)
+ struct gapc_irk irk;
+ /// OOB Confirm and Random from the peer (request = GAPC_OOB_EXCH)
+ struct gapc_oob oob;
+ } data;
+};
+
+/**
+ * Authentication information
+ */
+struct gapc_bond_auth
+{
+ /// Authentication information (@see gap_auth)
+ uint8_t info;
+
+ /// LTK exchanged during pairing.
+ bool ltk_present;
+};
+
+
+
+/// Bonding information indication message
+struct gapc_bond_ind
+{
+ /// Bond information type (@see gapc_bond)
+ uint8_t info;
+
+ /// Bond procedure information data
+ union gapc_bond_data
+ {
+ /// Authentication information (@see gap_auth)
+ /// (if info = GAPC_PAIRING_SUCCEED)
+ struct gapc_bond_auth auth;
+ /// Pairing failed reason (if info = GAPC_PAIRING_FAILED)
+ uint8_t reason;
+ /// Long Term Key information (if info = GAPC_LTK_EXCH)
+ struct gapc_ltk ltk;
+ /// Identity Resolving Key information (if info = GAPC_IRK_EXCH)
+ struct gapc_irk irk;
+ /// Connection Signature Resolving Key information (if info = GAPC_CSRK_EXCH)
+ struct gap_sec_key csrk;
+ } data;
+};
+
+/// Start Encryption command procedure
+struct gapc_encrypt_cmd
+{
+ /// GAP request type:
+ /// - GAPC_ENCRYPT: Start encryption procedure.
+ uint8_t operation;
+ /// Long Term Key information
+ struct gapc_ltk ltk;
+};
+
+/// Encryption requested by peer device indication message.
+struct gapc_encrypt_req_ind
+{
+ /// Encryption Diversifier
+ uint16_t ediv;
+ /// Random Number
+ rand_nb_t rand_nb;
+};
+
+/// Confirm requested Encryption information.
+struct gapc_encrypt_cfm
+{
+ /// Indicate if a LTK has been found for the peer device
+ uint8_t found;
+ /// Long Term Key
+ struct gap_sec_key ltk;
+ /// LTK Key Size
+ uint8_t key_size;
+};
+
+/// Encryption information indication message
+struct gapc_encrypt_ind
+{
+ /// Authentication level (@see gap_auth)
+ uint8_t auth;
+};
+
+/// Start Security Request command procedure
+struct gapc_security_cmd
+{
+ /// GAP request type:
+ /// - GAPC_SECURITY_REQ: Start security request procedure
+ uint8_t operation;
+ /// Authentication level (@see gap_auth)
+ uint8_t auth;
+};
+/// Security requested by peer device indication message
+struct gapc_security_ind
+{
+ /// Authentication level (@see gap_auth)
+ uint8_t auth;
+};
+
+/// Parameters of the @ref GAPC_SIGN_COUNTER_IND message
+struct gapc_sign_counter_ind
+{
+ /// Local SignCounter value
+ uint32_t local_sign_counter;
+ /// Peer SignCounter value
+ uint32_t peer_sign_counter;
+};
+
+
+/// Parameters of the @ref GAPC_SET_LE_PING_TO_CMD message
+struct gapc_set_le_ping_to_cmd
+{
+ /// GAP request type:
+ /// - GAPC_SET_LE_PING_TO : Set the LE Ping timeout value
+ uint8_t operation;
+ /// Authenticated payload timeout
+ uint16_t timeout;
+};
+
+/// Parameters of the @ref GAPC_SET_LE_PKT_SIZE_CMD message
+struct gapc_set_le_pkt_size_cmd
+{
+ /// GAP request type:
+ /// - GAPC_SET_LE_PKT_SIZE : Set the LE Data length value
+ uint8_t operation;
+ ///Preferred maximum number of payload octets that the local Controller should include
+ ///in a single Link Layer Data Channel PDU.
+ uint16_t tx_octets;
+ ///Preferred maximum number of microseconds that the local Controller should use to transmit
+ ///a single Link Layer Data Channel PDU
+ uint16_t tx_time;
+};
+
+/// Parameters of the @ref GAPC_LE_PKT_SIZE_IND message
+struct gapc_le_pkt_size_ind
+{
+ ///The maximum number of payload octets in TX
+ uint16_t max_tx_octets;
+ ///The maximum time that the local Controller will take to TX
+ uint16_t max_tx_time;
+ ///The maximum number of payload octets in RX
+ uint16_t max_rx_octets;
+ ///The maximum time that the local Controller will take to RX
+ uint16_t max_rx_time;
+};
+
+/// Parameters of the @ref GAPC_KEY_PRESS_NOTIFICATION_CMD message
+struct gapc_key_press_notif_cmd
+{
+ /// GAP request type:
+ /// - GAPC_KEY_PRESS_NOTIFICATION_CMD : Inform the remote device when keys have been entered or erased
+ uint8_t operation;
+ /// notification type
+ uint8_t notification_type;
+};
+
+/// Parameters of the @ref GAPC_KEY_PRESS_NOTIFICATION_IND message
+struct gapc_key_press_notif_ind
+{
+ /// notification type
+ uint8_t notification_type;
+};
+
+
+/// Parameters of the @ref GAPC_SIGN_CMD message
+struct gapc_sign_cmd
+{
+ /// GAP request type:
+ /// - GAPC_SIGN_PACKET: Sign an attribute packet
+ /// - GAPC_SIGN_CHECK: Verify signature or an attribute packet
+ uint8_t operation;
+ /// Data PDU length (Bytes)
+ uint16_t byte_len;
+ /// Data PDU + SignCounter if generation, Data PDU + SignCounter + MAC if verification
+ uint8_t msg[__ARRAY_EMPTY];
+};
+
+/// Parameters of the @ref GAPC_SIGN_IND message
+struct gapc_sign_ind
+{
+ /// GAP request type:
+ /// - GAPC_SIGN_PACKET: Sign an attribute packet
+ /// - GAPC_SIGN_CHECK: Verify signature or an attribute packet
+ uint8_t operation;
+ /// Data PDU length (Bytes)
+ uint16_t byte_len;
+ /// Data PDU + SignCounter + MAC
+ uint8_t signed_msg[__ARRAY_EMPTY];
+};
+
+
+/// @} GAPC_TASK
+
+#endif /* _GAPC_TASK_H_ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm.h
new file mode 100644
index 0000000000..3057806204
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm.h
@@ -0,0 +1,349 @@
+/**
+ ****************************************************************************************
+ *
+ * @file gapm.h
+ *
+ * @brief Generic Access Profile Manager Header.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ ****************************************************************************************
+ */
+
+
+#ifndef _GAPM_H_
+#define _GAPM_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup GAPM Generic Access Profile Manager
+ * @ingroup GAP
+ * @brief Generic Access Profile Manager.
+ *
+ * The GAP Manager module is responsible for providing an API to the application in order
+ * to manage all non connected stuff such as configuring device to go in desired mode
+ * (discoverable, connectable, etc.) and perform required actions (scanning, connection,
+ * etc.). GAP Manager is also responsible of managing GAP Controller state according to
+ * corresponding BLE connection states.
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "rwip_config.h"
+#include "ke_task.h"
+#include "gap.h"
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+/// Bit checking
+#define GAPM_ISBITSET(flag, mask) (((flag)&(mask)) == mask)
+
+
+
+
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief Initialize Generic Access Profile Manager Module.
+ *
+ * @param[in] reset true if it's requested by a reset; false if it's boot initialization
+ *
+ ****************************************************************************************
+ */
+void gapm_init(bool reset);
+
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve Task Identifier from Task number
+ * (automatically update index of task in returned task id)
+ *
+ * @param task Task number
+ * @return Task Identifier
+ ****************************************************************************************
+ */
+ke_task_id_t gapm_get_id_from_task(ke_msg_id_t task);
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve Task Number from Task Identifier
+ * (automatically update index of task in returned task id)
+ *
+ * @param id Task Identifier
+ * @return Task Number
+ ****************************************************************************************
+ */
+ke_task_id_t gapm_get_task_from_id(ke_msg_id_t id);
+
+
+
+#if (BLE_GAPC)
+/**
+ ****************************************************************************************
+ * @brief Created link connection parameters (from bond data) has been set, connection
+ * ready to be used.
+ *
+ * @param[in] conidx Connection Index
+ *
+ ****************************************************************************************
+ */
+void gapm_con_enable(uint8_t conidx);
+
+
+/**
+ ****************************************************************************************
+ * @brief A link has been disconnected, clean-up host stack for this connection.
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] conhdl Connection Handle
+ * @param[in] reason Reason of the disconnection
+ *
+ ****************************************************************************************
+ */
+void gapm_con_cleanup(uint8_t conidx, uint16_t conhdl, uint8_t reason);
+
+#endif // (BLE_GAPC)
+
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve device identity key.
+ *
+ * @return Device Identity Key
+ ****************************************************************************************
+ */
+struct gap_sec_key* gapm_get_irk(void);
+
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve local public address.
+ *
+ * @return Return local public address
+ ****************************************************************************************
+ */
+bd_addr_t* gapm_get_bdaddr(void);
+
+
+
+#ifdef BLE_AUDIO_AM0_TASK
+/**
+ ****************************************************************************************
+ * @brief Return if LE Audio Mode 0 is supported or not
+ *
+ * @return True if supported, False else
+ ****************************************************************************************
+ */
+bool gapm_is_audio_am0_sup(void);
+#endif // BLE_AUDIO_AM0_TASK
+
+
+#if (BLE_EMB_PRESENT && HCI_TL_SUPPORT)
+/**
+ ****************************************************************************************
+ * @brief Retrieve if host is embedded or not
+ *
+ * @return True if embedded host is enabled, false else.
+ ****************************************************************************************
+ */
+bool gapm_is_embedded_host(void);
+
+/**
+ ****************************************************************************************
+ * @brief Set if host is embedded or not
+ *
+ * @param[in] enable True to enable embedded host, false else.
+ ****************************************************************************************
+ */
+void gapm_set_embedded_host(bool enable);
+#endif // (BLE_EMB_PRESENT && HCI_TL_SUPPORT)
+
+
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve the device address type (@see enum gapm_addr_type)
+ *
+ * @return address type
+ ****************************************************************************************
+ */
+uint8_t gapm_get_address_type(void);
+
+
+#if (BLE_ATTS)
+
+/**
+ ****************************************************************************************
+ * @brief Get if preferred connection parameters present in GAP ATT database
+ *
+ * @return True if referred connection parameters present in GAP ATT database, False else
+ ****************************************************************************************
+ */
+bool gapm_is_pref_con_param_pres(void);
+
+/**
+ ****************************************************************************************
+ * @brief retrieve gap attribute handle from attribute index.
+ *
+ * @param[in] att_idx Attribute index
+ *
+ * @return Attribute handle
+ ****************************************************************************************
+ */
+uint16_t gapm_get_att_handle(uint8_t att_idx);
+
+#endif // (BLE_ATTS)
+
+#if (SECURE_CONNECTIONS)
+/**
+ ****************************************************************************************
+ * @brief Returns the local Public Key
+ *
+ * @return pointer to the local Public Key
+ ****************************************************************************************
+ */
+public_key_t* gapm_get_local_public_key(void);
+#endif // (SECURE_CONNECTIONS)
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve if Legacy pairing is supported on local device
+ *
+ * @return True if legacy pairing is supported
+ ****************************************************************************************
+ */
+bool gapm_is_legacy_pairing_supp(void);
+
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve if Secure Connection pairing is supported on local device
+ *
+ * @return True if Secure Connection pairing is supported
+ ****************************************************************************************
+ */
+bool gapm_is_sec_con_pairing_supp(void);
+
+
+#if (BLE_LECB)
+/**
+ ****************************************************************************************
+ * @brief Check if LECB connection can be registered (established)
+ *
+ * @param[in] le_psm LE Protocol/Service Multiplexer
+ * @param[in] conidx Connection index for app_task computation
+ * @param[out] app_task Destination application/profile task
+ * @param[out] sec_lvl Security level requirements
+ *
+ *
+ * @return GAP_ERR_NOT_FOUND if LE_PSM not register, GAP_ERR_NO_ERROR else
+ ****************************************************************************************
+ */
+uint8_t gapm_le_psm_get_info(uint16_t le_psm, uint8_t conidx, ke_task_id_t *app_task, uint8_t *sec_lvl);
+
+
+/**
+ ****************************************************************************************
+ * @brief Check if LECB connection can be registered (established)
+ *
+ * @param[in] le_psm LE Protocol/Service Multiplexer
+ * @param[in] peer_con_init Info to know if connection is initiated by peer device
+ *
+ * @return L2C_ERR_NO_RES_AVAIL if all LECB link are established, GAP_ERR_NO_ERROR else
+ ****************************************************************************************
+ */
+uint8_t gapm_lecb_register(uint16_t le_psm, bool peer_con_init);
+
+
+/**
+ ****************************************************************************************
+ * @brief Unregister an existing LECB connection
+ *
+ * @param[in] le_psm LE Protocol/Service Multiplexer
+ * @param[in] peer_con_init Info to know if connection is initiated by peer device
+ *
+ * @return GAP_ERR_NO_ERROR
+ ****************************************************************************************
+ */
+uint8_t gapm_lecb_unregister(uint16_t le_psm, bool peer_con_init);
+
+#endif // (BLE_LECB)
+
+/**
+ ****************************************************************************************
+ * @brief Return the maximal MTU value
+ *
+ * @param[out] Maximal MTU value
+ ****************************************************************************************
+ */
+uint16_t gapm_get_max_mtu(void);
+void gapm_set_max_mtu(uint16_t mtu);
+
+/**
+ ****************************************************************************************
+ * @brief Return the maximal MPS value
+ *
+ * @param[out] Maximal MPS value
+ ****************************************************************************************
+ */
+uint16_t gapm_get_max_mps(void);
+
+
+
+/**
+ ****************************************************************************************
+ * @brief Check If Service changed feature is enabled or not
+ *
+ * @return true if enabled, false else.
+ *
+ ****************************************************************************************
+ */
+bool gapm_svc_chg_en(void);
+
+#if (BLE_DEBUG)
+/**
+ ****************************************************************************************
+ * @brief Check If Debug mode feature is enabled or not
+ *
+ * @return true if enabled, false else.
+ *
+ ****************************************************************************************
+ */
+bool gapm_dbg_mode_en(void);
+
+/**
+ ****************************************************************************************
+ * @brief Force the GAP service start handle
+ ****************************************************************************************
+ */
+void gapm_set_svc_start_hdl(uint16_t start_hdl);
+#endif // (BLE_DEBUG)
+
+/**
+ ****************************************************************************************
+ * Retrieve if current connection index is used for a discovery purpose such as
+ * Name discovery
+ *
+ * @param conidx Index of the specific connection
+ *
+ * @return true if connection has a discovery purpose, False else
+ ****************************************************************************************
+ */
+bool gapm_is_disc_connection(uint8_t conidx);
+
+/// @} GAPM
+
+#endif /* _GAPM_H_ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm_int.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm_int.h
new file mode 100644
index 0000000000..ae2384ff8d
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm_int.h
@@ -0,0 +1,504 @@
+/**
+ ****************************************************************************************
+ *
+ * @file gapm_int.h
+ *
+ * @brief Generic Access Profile Manager Internal Header.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ ****************************************************************************************
+ */
+
+
+#ifndef _GAPM_INT_H_
+#define _GAPM_INT_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup GAPM_INT Generic Access Profile Manager Internal
+ * @ingroup GAPM
+ * @brief defines for internal GAPM usage
+ *
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "gapm.h"
+#include "gapm_task.h"
+#include "co_bt.h"
+
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/// Maximum number of GAP Manager process
+#define GAPM_IDX_MAX 0x01
+
+
+/// Scan filter size
+#define GAPM_SCAN_FILTER_SIZE 10
+
+
+
+/*
+ * INTERNAL API TYPES
+ ****************************************************************************************
+ */
+
+
+/// Retrieve information about memory usage
+struct gapm_dbg_get_mem_info_cmd
+{
+ /// GAPM requested operation:
+ /// - GAPM_DBG_GET_MEM_INFO: Get memory usage
+ uint8_t operation;
+};
+
+/// Indication containing information about memory usage.
+struct gapm_dbg_mem_info_ind
+{
+ /// peak of memory usage measured
+ uint32_t max_mem_used;
+ /// memory size currently used into each heaps.
+ uint16_t mem_used[KE_MEM_BLOCK_MAX];
+};
+
+
+/// Operation type
+enum gapm_op_type
+{
+ /// Configuration operation
+ GAPM_OP_CFG = 0x00,
+
+ /// Air mode operation (scanning, advertising, connection establishment)
+ /// Note: Restriction, only one air operation supported.
+ GAPM_OP_AIR = 0x01,
+#if (SECURE_CONNECTIONS)
+ /// GAP State for DH Key Generation
+ GAPM_OP_DHKEY = 0x02,
+#endif // (SECURE_CONNECTIONS)
+ /// Max number of operations
+ GAPM_OP_MAX
+};
+
+
+/// GAPM states
+enum gapm_state_id
+{
+ /// Idle state - no on going operation
+ GAPM_IDLE,
+
+ /// Busy state - Configuration operation on going
+ GAPM_CFG_BUSY = 1 << GAPM_OP_CFG,
+ /// Busy state - Air operation on going
+ GAPM_AIR_BUSY = 1 << GAPM_OP_AIR,
+ #if (SECURE_CONNECTIONS)
+ /// Busy state - DH Key Calculation operation on going
+ GAPM_DHKEY_BUSY = 1 << GAPM_OP_DHKEY,
+ #endif // (SECURE_CONNECTIONS)
+
+ /// Reset state - Reset operation on going
+ GAPM_DEVICE_SETUP = 1 << GAPM_OP_MAX,
+
+ GAPM_STATE_MAX
+};
+/// Device configuration flags
+/// 7 6 5 4 3 2 1 0
+/// +-----+----+----+----+----+----+----+----+
+/// | DBG | SC | CP | GA | RE |CTLP|HSTP|ADDR|
+/// +-----+----+----+----+----+----+----+----+
+/// - Bit [0-2]: Address Type @see enum gapm_cfg_flag
+/// Bit 0: 0 = Public address, 1 = Private address
+/// Bit 1: 0 = Host-based Privacy disabled, 1 = enabled
+/// Bit 2: 0 = Controller-based Privacy disabled, 1 = enabled
+///
+/// - Bit [3] : Address to renew (only if privacy is enabled, 1 address to renew else 0)
+/// - Bit [4] : Generated Address type (1 = Resolvable, 0 = Non Resolvable)
+/// - Bit [5] : Preferred Connection parameters present in GAP DB
+/// - Bit [6] : Service Change feature present
+/// - Bit [7] : Enable Debug mode
+
+/// Configuration flag bit description
+enum gapm_cfg_flag_def
+{
+ /// Address Type
+ GAPM_MASK_ADDR_TYPE = 0x07,
+ GAPM_POS_ADDR_TYPE = 0x00,
+ /// Address to renew
+ GAPM_MASK_ADDR_RENEW = 0x08,
+ GAPM_POS_ADDR_RENEW = 0x03,
+ /// Generated Address type
+ GAPM_MASK_RESOLV_ADDR = 0x10,
+ GAPM_POS_RESOLV_ADDR = 0x04,
+ /// Preferred Connection parameters present in GAP DB
+ GAPM_MASK_PREF_CON_PAR_PRES = 0x20,
+ GAPM_POS_PREF_CON_PAR_PRES = 0x05,
+ /// Service Change feature present
+ GAPM_MASK_SVC_CHG_EN = 0x40,
+ GAPM_POS_SVC_CHG_EN = 0x06,
+
+#if (BLE_DEBUG)
+ /// L2CAP Debug Mode used to force LE-frames
+ GAPM_MASK_DBG_MODE_EN = 0x80,
+ GAPM_POS_DBG_MODE_EN = 0x07,
+#endif // (BLE_DEBUG)
+
+};
+
+
+/*
+ * MACROS
+ ****************************************************************************************
+ */
+/// Macro used to retrieve field
+#define GAPM_F_GET(data, field)\
+ (((data) & (GAPM_MASK_ ## field)) >> (GAPM_POS_ ## field))
+
+/// Macro used to set field
+#define GAPM_F_SET(data, field, val)\
+ (data) = (((data) & ~(GAPM_MASK_ ## field)) \
+ | ((val << (GAPM_POS_ ## field)) & (GAPM_MASK_ ## field)))
+
+/*
+ * TYPE DEFINITIONS
+ ****************************************************************************************
+ */
+
+/// Information about registered LE_PSM
+struct gapm_le_psm_info
+{
+ /// List header structure to put information within a list
+ struct co_list_hdr hdr;
+
+ /// LE Protocol/Service Multiplexer
+ uint16_t le_psm;
+
+ /// Registered task identifier
+ ke_task_id_t task_id;
+
+ /// Security level
+ /// 7 6 5 4 3 2 1 0
+ /// +---+---+---+---+---+---+---+---+
+ /// |MI | RFU |EKS|SEC_LVL|
+ /// +---+---+---+---+---+---+---+---+
+ /// bit[0-1]: Security level requirement (0=NO_AUTH, 1=UNAUTH, 2=AUTH, 3=SEC_CON)
+ /// bit[2] : Encryption Key Size length must have 16 bytes
+ /// bit[7] : Multi-instantiated task
+ uint8_t sec_lvl;
+
+ /// Number of established link
+ uint8_t nb_est_lk;
+};
+
+/// GAP Manager environment structure
+struct gapm_env_tag
+{
+ /// Request operation Kernel message
+ void* operation[GAPM_OP_MAX];
+
+ #if (BLE_CENTRAL || BLE_OBSERVER)
+ /// Scan filtering Array
+ struct gap_bdaddr* scan_filter;
+ #endif // (BLE_CENTRAL || BLE_OBSERVER)
+
+ #if (BLE_LECB)
+ /// Registered list of LE Protocol/Service Multiplexer for LE Credit Based Connection
+ struct co_list reg_le_psm;
+ #endif // (BLE_LECB)
+
+ #if (BLE_ATTS)
+ /// GAP service start handle
+ uint16_t svc_start_hdl;
+ #endif // (BLE_ATTS)
+
+ /// Duration before regenerate device address when privacy is enabled.
+ uint16_t renew_dur;
+ /// Device IRK used for resolvable random BD address generation (MSB -> LSB)
+ struct gap_sec_key irk;
+
+ /// Current device Address
+ bd_addr_t addr;
+ /// Device Role
+ uint8_t role;
+ /// Number of BLE connection
+ uint8_t connections;
+ /// Device configuration flags - (@see enum gapm_cfg_flag_def)
+ uint8_t cfg_flags;
+ /// Pairing mode authorized (see enum gapm_pairing_mode)
+ uint8_t pairing_mode;
+ /// Maximum device MTU size
+ uint16_t max_mtu;
+ /// Maximum device MPS size
+ uint16_t max_mps;
+ #if (SECURE_CONNECTIONS)
+ /// Local device Public Key
+ public_key_t public_key;
+ #endif // (SECURE_CONNECTIONS)
+
+ #if (BLE_AUDIO)
+ /// Audio configuration flag (see gapm_audio_cfg_flag)
+ uint16_t audio_cfg;
+ #endif // (BLE_AUDIO)
+
+ #if (BLE_EMB_PRESENT && HCI_TL_SUPPORT)
+ /// In Full mode, by default the AHI API is used, but if an HCI Reset is received,
+ /// TL is switched to HCI and embedded host is disabled
+ bool embedded_host;
+ #endif // (BLE_EMB_PRESENT && HCI_TL_SUPPORT)
+
+ #if (BLE_LECB)
+ /// Maximum number of allowed LE Credit Based channels
+ uint8_t max_nb_lecb;
+ /// Current number of LE Credit Based channel connections established
+ uint8_t nb_lecb;
+ #endif // (BLE_LECB)
+};
+
+/*
+ * GLOBAL VARIABLE DECLARATIONS
+ ****************************************************************************************
+ */
+/// GAP Manager environment variable.
+extern struct gapm_env_tag gapm_env;
+
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief Initialize GAP attribute database
+ *
+ * @param[in] start_hdl Service Start Handle
+ * @param[in] feat Attribute database features
+ *
+ * @return status code of attribute database initialization
+ * - @ref ATT_ERR_NO_ERROR: If database creation succeeds.
+ * - @ref ATT_ERR_INVALID_HANDLE: If start_hdl given in parameter + nb of attribute override
+ * some existing services handles.
+ * - @ref ATT_ERR_INSUFF_RESOURCE: There is not enough memory to allocate service buffer.
+ * or of new attribute cannot be added because all expected
+ * attributes already add
+ ****************************************************************************************
+ */
+uint8_t gapm_init_attr(uint16_t start_hdl, uint32_t feat);
+
+/**
+ ****************************************************************************************
+ * @brief Send operation completed message according to operation type.
+ * Perform also am operation clean-up
+ *
+ * @param[in] op_type Operation type
+ * @param[in] status Command status
+ *****************************************************************************************
+ */
+void gapm_send_complete_evt(uint8_t op_type, uint8_t status);
+
+/**
+ ****************************************************************************************
+ * @brief Send operation completed message with status error code not related to a
+ * running operation.
+ *
+ * @param[in] operation Operation code
+ * @param[in] requester requester of operation
+ * @param[in] status Error status code
+ ****************************************************************************************
+ */
+void gapm_send_error_evt(uint8_t operation, const ke_task_id_t requester, uint8_t status);
+
+
+/**
+ ****************************************************************************************
+ * @brief Get operation pointer
+ *
+ * @param[in] op_type Operation type.
+ *
+ * @return operation pointer on going
+ ****************************************************************************************
+ */
+__INLINE void* gapm_get_operation_ptr(uint8_t op_type)
+{
+ ASSERT_ERR(op_type < GAPM_OP_MAX);
+ // return operation pointer
+ return gapm_env.operation[op_type];
+}
+
+
+/**
+ ****************************************************************************************
+ * @brief Set operation pointer
+ *
+ * @param[in] op_type Operation type.
+ * @param[in] op Operation pointer.
+ *
+ ****************************************************************************************
+ */
+__INLINE void gapm_set_operation_ptr(uint8_t op_type, void* op)
+{
+ ASSERT_ERR(op_type < GAPM_OP_MAX);
+ // update operation pointer
+ gapm_env.operation[op_type] = op;
+}
+
+
+/**
+ ****************************************************************************************
+ * @brief Get operation on going
+ *
+ * @param[in] op_type Operation type.
+ *
+ * @return operation code on going
+ ****************************************************************************************
+ */
+uint8_t gapm_get_operation(uint8_t op_type);
+
+
+/**
+ ****************************************************************************************
+ * @brief Operation execution not finish, request kernel to reschedule it in order to
+ * continue its execution
+ *
+ * @param[in] op_type Operation type.
+ *
+ * @return if operation has been rescheduled (not done if operation pointer is null)
+ ****************************************************************************************
+ */
+bool gapm_reschedule_operation(uint8_t op_type);
+
+/**
+ ****************************************************************************************
+ * @brief Get requester of on going operation
+ *
+ * @param[in] op_type Operation type.
+ *
+ * @return task that requests to execute the operation
+ ****************************************************************************************
+ */
+ke_task_id_t gapm_get_requester(uint8_t op_type);
+
+
+
+
+#if (BLE_GAPC)
+/**
+ ****************************************************************************************
+ * @brief A connection has been created, initialize host stack to be ready for connection.
+ *
+ * @param[in] msgid Message id
+ * @param[in] operation Air operation type
+ * @param[in] con_params Connection parameters from lower layers
+ *
+ * @return Connection index allocated to the new connection.
+ ****************************************************************************************
+ */
+uint8_t gapm_con_create(ke_msg_id_t const msgid, uint8_t operation, struct hci_le_enh_con_cmp_evt const *con_params);
+
+#endif // (BLE_GAPC)
+
+/**
+ ****************************************************************************************
+ * Retrieve if current connection index is used for a discovery purpose such as
+ * Name discovery
+ *
+ * @param conidx Index of the specific connection
+ *
+ * @return true if connection has a discovery purpose, False else
+ ****************************************************************************************
+ */
+bool gapm_is_disc_connection(uint8_t conidx);
+
+/**
+ ****************************************************************************************
+ * @brief Set the maximal MTU value
+ *
+ * @param[in] mtu Max MTU value (Minimum is 23)
+ ****************************************************************************************
+ */
+void gapm_set_max_mtu(uint16_t mtu);
+
+/**
+ ****************************************************************************************
+ * @brief Set the maximal MPS value
+ *
+ * @param[in] mps Max MPS value (Minimum is 23)
+ ****************************************************************************************
+ */
+void gapm_set_max_mps(uint16_t mps);
+
+/**
+ ****************************************************************************************
+ * @brief Checks validity of the address type
+ *
+ * @param[in] addr_type Address type
+ ****************************************************************************************
+ */
+uint8_t gapm_addr_check( uint8_t addr_type);
+
+/**
+ ****************************************************************************************
+ * @brief Checks validity of the Data Length Suggested values
+ *
+ * @param[in] sugg_oct Suggested octets
+ * @param[in] sugg_time Suggested time
+ ****************************************************************************************
+ */
+uint8_t gapm_dle_val_check(uint16_t sugg_oct, uint16_t sugg_time);
+
+
+
+/**
+ ****************************************************************************************
+ * @brief Update task state
+ *
+ * @param[in] operation that modify the state
+ * @param[in] set state to busy (true) or idle (false)
+ *
+ ****************************************************************************************
+ */
+void gapm_update_state(uint8_t operation, bool busy);
+
+
+
+#if (BLE_LECB)
+
+
+/**
+ ****************************************************************************************
+ * @brief Find Information about LE_PSM registered in GAPM
+ *
+ * @param[in] le_psm LE Protocol/Service Multiplexer
+ *
+ * @return Null if not found or LE_PSM info structure
+ ****************************************************************************************
+ */
+struct gapm_le_psm_info* gapm_le_psm_find(uint16_t le_psm);
+
+
+/**
+ ****************************************************************************************
+ * @brief Remove all registered LE_PSM
+ ****************************************************************************************
+ */
+void gapm_le_psm_cleanup(void);
+#endif // (BLE_LECB)
+
+/*
+ * TASK DESCRIPTOR DECLARATIONS
+ ****************************************************************************************
+ */
+extern const struct ke_state_handler gapm_default_handler;
+extern ke_state_t gapm_state[GAPM_IDX_MAX];
+
+/// @} GAPM_INT
+
+#endif /* _GAPM_INT_H_ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm_task.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm_task.h
new file mode 100644
index 0000000000..a2c90c2cee
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm_task.h
@@ -0,0 +1,1087 @@
+/**
+ ****************************************************************************************
+ *
+ * @file gapm_task.h
+ *
+ * @brief Generic Access Profile Manager Task Header.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ ****************************************************************************************
+ */
+
+
+#ifndef _GAPM_TASK_H_
+#define _GAPM_TASK_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup GAPM_TASK Generic Access Profile Manager Task
+ * @ingroup GAPM
+ * @brief Handles ALL messages to/from GAP Manager block.
+ *
+ * It handles messages from lower and higher layers not related to an ongoing connection.
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "rwip_task.h" // Task definitions
+#include "gap.h"
+
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/// GAP Manager Message Interface
+enum gapm_msg_id
+{
+ /* Default event */
+ /// Command Complete event
+ GAPM_CMP_EVT = TASK_FIRST_MSG(TASK_ID_GAPM),
+ /// Event triggered to inform that lower layers are ready
+ GAPM_DEVICE_READY_IND,
+
+ /* Default commands */
+ /// Reset link layer and the host command
+ GAPM_RESET_CMD,
+ /// Cancel ongoing operation
+ GAPM_CANCEL_CMD,
+ /* Device Configuration */
+ /// Set device configuration command
+ GAPM_SET_DEV_CONFIG_CMD,
+ /// Set device channel map
+ GAPM_SET_CHANNEL_MAP_CMD,
+ /* Local device information */
+ /// Get local device info command
+ GAPM_GET_DEV_INFO_CMD,
+ /// Local device version indication event
+ GAPM_DEV_VERSION_IND,
+ /// Local device BD Address indication event
+ GAPM_DEV_BDADDR_IND,
+ /// Advertising channel Tx power level
+ GAPM_DEV_ADV_TX_POWER_IND,
+ /// Indication containing information about memory usage.
+ GAPM_DBG_MEM_INFO_IND,
+
+ /* White List */
+ /// White List Management Command
+ GAPM_WHITE_LIST_MGT_CMD,
+ /// White List Size indication event
+ GAPM_WHITE_LIST_SIZE_IND,
+
+ /* Air Operations */
+ /// Set advertising mode Command
+ GAPM_START_ADVERTISE_CMD,
+ /// Update Advertising Data Command - On fly update when device is advertising
+ GAPM_UPDATE_ADVERTISE_DATA_CMD,
+
+ /// Set Scan mode Command
+ GAPM_START_SCAN_CMD,
+ /// Advertising or scanning report information event
+ GAPM_ADV_REPORT_IND,
+
+ /// Set connection initialization Command
+ GAPM_START_CONNECTION_CMD,
+ /// Name of peer device indication
+ GAPM_PEER_NAME_IND,
+ /// Confirm connection to a specific device (Connection Operation in Selective mode)
+ GAPM_CONNECTION_CFM,
+
+ /* Security / Encryption Toolbox */
+ /// Resolve address command
+ GAPM_RESOLV_ADDR_CMD,
+ /// Indicate that resolvable random address has been solved
+ GAPM_ADDR_SOLVED_IND,
+ /// Generate a random address.
+ GAPM_GEN_RAND_ADDR_CMD,
+ /// Use the AES-128 block in the controller
+ GAPM_USE_ENC_BLOCK_CMD,
+ /// AES-128 block result indication
+ GAPM_USE_ENC_BLOCK_IND,
+ /// Generate a 8-byte random number
+ GAPM_GEN_RAND_NB_CMD,
+ /// Random Number Indication
+ GAPM_GEN_RAND_NB_IND,
+
+ /* Profile Management */
+ /// Create new task for specific profile
+ GAPM_PROFILE_TASK_ADD_CMD,
+ /// Inform that profile task has been added.
+ GAPM_PROFILE_ADDED_IND,
+
+ /// Indicate that a message has been received on an unknown task
+ GAPM_UNKNOWN_TASK_IND,
+
+ /* Data Length Extension */
+ /// Suggested Default Data Length indication
+ GAPM_SUGG_DFLT_DATA_LEN_IND,
+ /// Maximum Data Length indication
+ GAPM_MAX_DATA_LEN_IND,
+
+ /* Resolving list for controller-based privacy*/
+ /// Resolving address list management
+ GAPM_RAL_MGT_CMD,
+ /// Resolving address list size indication
+ GAPM_RAL_SIZE_IND,
+ /// Resolving address list address indication
+ GAPM_RAL_ADDR_IND,
+
+ /* Set new IRK */
+ /// Modify current IRK
+ GAPM_SET_IRK_CMD,
+
+ /* LE Protocol/Service Multiplexer Management */
+ /// Register a LE Protocol/Service Multiplexer command
+ GAPM_LEPSM_REGISTER_CMD,
+ /// Unregister a LE Protocol/Service Multiplexer command
+ GAPM_LEPSM_UNREGISTER_CMD,
+
+ /* ************************************************ */
+ /* -------------- Internal usage only ------------- */
+ /* ************************************************ */
+ /// Message received to unknown task received
+ GAPM_UNKNOWN_TASK_MSG,
+
+ /* Secure Connections */
+ /// Request to provide DH Key
+ GAPM_GEN_DH_KEY_CMD,
+ /// Indicates the DH Key computation is complete and available
+ GAPM_GEN_DH_KEY_IND,
+
+ /* Internal messages for timer events, not part of API*/
+ /// Limited discoverable timeout indication
+ GAPM_LIM_DISC_TO_IND,
+ /// Scan timeout indication
+ GAPM_SCAN_TO_IND,
+ /// Address renewal timeout indication
+ GAPM_ADDR_RENEW_TO_IND,
+};
+
+
+/// GAP Manager operation type - application interface
+enum gapm_operation
+{
+ /* No Operation (if nothing has been requested) */
+ /* ************************************************ */
+ /// No operation.
+ GAPM_NO_OP = 0x00,
+
+ /* Default operations */
+ /* ************************************************ */
+ /// Reset BLE subsystem: LL and HL.
+ GAPM_RESET,
+ /// Cancel currently executed operation.
+ GAPM_CANCEL,
+
+ /* Configuration operations */
+ /* ************************************************ */
+ /// Set device configuration
+ GAPM_SET_DEV_CONFIG,
+ /// Set device channel map
+ GAPM_SET_CHANNEL_MAP, //0x04
+
+ /* Retrieve device information */
+ /* ************************************************ */
+ /// Get Local device version
+ GAPM_GET_DEV_VERSION,
+ /// Get Local device BD Address
+ GAPM_GET_DEV_BDADDR,
+ /// Get device advertising power level
+ GAPM_GET_DEV_ADV_TX_POWER,
+
+ /* Operation on White list */
+ /* ************************************************ */
+ /// Get White List Size.
+ GAPM_GET_WLIST_SIZE, //0x08
+ /// Add devices in white list.
+ GAPM_ADD_DEV_IN_WLIST,
+ /// Remove devices form white list.
+ GAPM_RMV_DEV_FRM_WLIST, //0x0a
+ /// Clear all devices from white list.
+ GAPM_CLEAR_WLIST,
+
+ /* Advertise mode operations */
+ /* ************************************************ */
+ /// Start non connectable advertising
+ GAPM_ADV_NON_CONN, //0x0c
+ /// Start undirected connectable advertising
+ GAPM_ADV_UNDIRECT,
+ /// Start directed connectable advertising
+ GAPM_ADV_DIRECT,
+ /// Start directed connectable advertising using Low Duty Cycle
+ GAPM_ADV_DIRECT_LDC,
+ /// Update on the fly advertising data
+ GAPM_UPDATE_ADVERTISE_DATA, //0x10
+
+ /* Scan mode operations */
+ /* ************************************************ */
+ /// Start active scan operation
+ GAPM_SCAN_ACTIVE,
+ /// Start passive scan operation
+ GAPM_SCAN_PASSIVE,
+
+ /* Connection mode operations */
+ /* ************************************************ */
+ /// Direct connection operation
+ GAPM_CONNECTION_DIRECT,
+ /// Automatic connection operation
+ GAPM_CONNECTION_AUTO, //0x014
+ /// Selective connection operation
+ GAPM_CONNECTION_SELECTIVE,
+ /// Name Request operation (requires to start a direct connection)
+ GAPM_CONNECTION_NAME_REQUEST,
+
+ /* Security / Encryption Toolbox */
+ /* ************************************************ */
+ /// Resolve device address
+ GAPM_RESOLV_ADDR,
+ /// Generate a random address
+ GAPM_GEN_RAND_ADDR, //0x18
+ /// Use the controller's AES-128 block
+ GAPM_USE_ENC_BLOCK,
+ /// Generate a 8-byte random number
+ GAPM_GEN_RAND_NB,
+
+ /* Profile Management */
+ /* ************************************************ */
+ /// Create new task for specific profile
+ GAPM_PROFILE_TASK_ADD,
+
+
+ /* DEBUG */
+ /* ************************************************ */
+ /// Get memory usage
+ GAPM_DBG_GET_MEM_INFO, //0x1c
+ /// Perform a platform reset
+ GAPM_PLF_RESET,
+
+ /* Data Length Extension */
+ /* ************************************************ */
+ /// Set Suggested Default LE Data Length
+ GAPM_SET_SUGGESTED_DFLT_LE_DATA_LEN,
+ /// Get Suggested Default LE Data Length
+ GAPM_GET_SUGGESTED_DFLT_LE_DATA_LEN,
+ /// Get Maximum LE Data Length
+ GAPM_GET_MAX_LE_DATA_LEN, // 0x20
+
+ /* Operation on Resolving List */
+ /* ************************************************ */
+ /// Get resolving address list size
+ GAPM_GET_RAL_SIZE,
+ /// Get resolving local address
+ GAPM_GET_RAL_LOC_ADDR,
+ /// Get resolving peer address
+ GAPM_GET_RAL_PEER_ADDR,
+ /// Add device in resolving address list
+ GAPM_ADD_DEV_IN_RAL, // 0x024
+ /// Remove device from resolving address list
+ GAPM_RMV_DEV_FRM_RAL,
+ /// Clear resolving address list
+ GAPM_CLEAR_RAL,
+
+ /* Connection mode operations - cont */
+ /* ************************************************ */
+ /// General connection operation
+ GAPM_CONNECTION_GENERAL,
+
+ /* Change current IRK */
+ /* ************************************************ */
+ /// Set IRK
+ GAPM_SET_IRK, //0x028
+
+ /* LE Protocol/Service Multiplexer management */
+ /* ************************************************ */
+ /// Register a LE Protocol/Service Multiplexer
+ GAPM_LEPSM_REG,
+ /// Unregister a LE Protocol/Service Multiplexer
+ GAPM_LEPSM_UNREG,
+
+ /* Secure Connection - Internal API */
+ /* ************************************************ */
+ /// Generate DH_Key
+ GAPM_GEN_DH_KEY, //0x2b
+};
+
+
+/// Device Address type Configuration
+enum gapm_addr_type
+{
+ /// Device Address is a Public Static address
+ GAPM_CFG_ADDR_PUBLIC = 0,
+ /// Device Address is a Private Static address
+ GAPM_CFG_ADDR_PRIVATE = 1,
+ /// Device Address generated using host-based Privacy feature
+ GAPM_CFG_ADDR_HOST_PRIVACY = 2,
+ /// Device Address generated using controller-based Privacy feature
+ GAPM_CFG_ADDR_CTNL_PRIVACY = 4,
+};
+
+
+/// Own BD address source of the device
+enum gapm_own_addr
+{
+ /// Public or Private Static Address according to device address configuration
+ GAPM_STATIC_ADDR,
+ /// Generated resolvable private random address
+ GAPM_GEN_RSLV_ADDR,
+ /// Generated non-resolvable private random address
+ GAPM_GEN_NON_RSLV_ADDR,
+};
+
+/// Device Attribute write permission requirement
+enum gapm_write_att_perm
+{
+ /// Disable write access
+ GAPM_WRITE_DISABLE = 0,
+ /// Enable write access - no authentication required
+ GAPM_WRITE_NO_AUTH = 1,
+ /// Write access requires unauthenticated link
+ GAPM_WRITE_UNAUTH = 2,
+ /// Write access requires authenticated link
+ GAPM_WRITE_AUTH = 3,
+ /// Write access requires secure connected link
+ GAPM_WRITE_SEC_CON = 4
+};
+
+
+/// Attribute database configuration
+/// 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+/// +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
+/// | DBG | RFU | SC |PCP | APP_PERM | NAME_PERM |
+/// +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
+/// - Bit [0-2] : Device Name write permission requirements for peer device (@see gapm_write_att_perm)
+/// - Bit [3-5] : Device Appearance write permission requirements for peer device (@see gapm_write_att_perm)
+/// - Bit [6] : Slave Preferred Connection Parameters present
+/// - Bit [7] : Service change feature present in GATT attribute database.
+/// - Bit [8-14]: Reserved
+/// - Bit [15] : Enable Debug Mode
+enum gapm_att_cfg_flag
+{
+ /// Device Name write permission requirements for peer device (@see gapm_write_att_perm)
+ GAPM_MASK_ATT_NAME_PERM = 0x0007,
+ GAPM_POS_ATT_NAME_PERM = 0x00,
+ /// Device Appearance write permission requirements for peer device (@see gapm_write_att_perm)
+ GAPM_MASK_ATT_APPEARENCE_PERM = 0x0038,
+ GAPM_POS_ATT_APPEARENCE_PERM = 0x03,
+ /// Slave Preferred Connection Parameters present in GAP attribute database.
+ GAPM_MASK_ATT_SLV_PREF_CON_PAR_EN = 0x0040,
+ GAPM_POS_ATT_SLV_PREF_CON_PAR_EN = 0x06,
+ /// Service change feature present in GATT attribute database.
+ GAPM_MASK_ATT_SVC_CHG_EN = 0x0080,
+ GAPM_POS_ATT_SVC_CHG_EN = 0x07,
+ /// Service change feature present in GATT attribute database.
+ GAPM_MASK_ATT_DBG_MODE_EN = 0x8000,
+ GAPM_POS_ATT_DBG_MODE_EN = 0x0F,
+};
+
+/// Pairing mode authorized on the device
+/// 7 6 5 4 3 2 1 0
+/// +----+----+----+----+----+----+----+----+
+/// |KGEN| RFU | SCP| LP |
+/// +----+----+----+----+----+----+----+----+
+enum gapm_pairing_mode
+{
+ /// No pairing authorized
+ GAPM_PAIRING_DISABLE = 0,
+ /// Legacy pairing Authorized
+ GAPM_PAIRING_LEGACY = (1 << 0),
+ /// Secure Connection pairing Authorized
+ GAPM_PAIRING_SEC_CON = (1 << 1),
+ /// Force re-generation of P256 private and public keys
+ GAPM_PAIRING_FORCE_P256_KEY_GEN = (1<<7),
+};
+
+/// LE Audio Mode Configuration
+/// 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+/// +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
+/// | RFU | AM0|
+/// +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
+enum gapm_audio_cfg_flag
+{
+ /// LE Audio Mode 0 Supported
+ GAPM_MASK_AUDIO_AM0_SUP = 0x0001,
+ GAPM_POS_AUDIO_AM0_SUP = 0x00,
+};
+
+/// Security level
+/// 7 6 5 4 3 2 1 0
+/// +---+---+---+---+---+---+---+---+
+/// |MI | RFU |EKS|SEC_LVL|
+/// +---+---+---+---+---+---+---+---+
+/// bit[0-1]: Security level requirement (0=NO_AUTH, 1=UNAUTH, 2=AUTH, 3=SEC_CON)
+/// bit[2] : Encryption Key Size length must have 16 bytes
+/// bit[7] : Multi-instantiated task
+enum gapm_le_psm_sec_mask
+{
+ /// bit[0-1]: Security level requirement (0=NO_AUTH, 1=UNAUTH, 2=AUTH, 3=SEC_CON)
+ /// bit[2] : Encryption Key Size length must have 16 bytes
+ GAPM_LE_PSM_SEC_LVL_MASK = 0x07,
+ /// bit[7] : Multi-instantiated task
+ GAPM_LE_PSM_MI_TASK_MASK = 0x80,
+};
+
+/*
+ * TYPE DEFINITIONS
+ ****************************************************************************************
+ */
+
+/// Operation command structure in order to keep requested operation.
+struct gapm_operation_cmd
+{
+ /// GAP request type
+ uint8_t operation;
+};
+
+/// Command complete event data structure
+struct gapm_cmp_evt
+{
+ /// GAP requested operation
+ uint8_t operation;
+ /// Status of the request
+ uint8_t status;
+};
+
+/// Reset link layer and the host command
+struct gapm_reset_cmd
+{
+ /// GAPM requested operation:
+ /// - GAPM_RESET: Reset BLE subsystem: LL and HL.
+ uint8_t operation;
+};
+
+/// Set device configuration command
+struct gapm_set_dev_config_cmd
+{
+ /// GAPM requested operation:
+ /// - GAPM_SET_DEV_CONFIG: Set device configuration
+ uint8_t operation;
+ /// Device Role: Central, Peripheral, Observer, Broadcaster or All roles.
+ uint8_t role;
+
+ /// -------------- Privacy Config -----------------------
+ /// Duration before regenerate device address when privacy is enabled.
+ uint16_t renew_dur;
+ /// Provided own static private random address (addr_type = GAPM_CFG_ADDR_PRIVATE)
+ bd_addr_t addr;
+ /// Device IRK used for resolvable random BD address generation (LSB first)
+ struct gap_sec_key irk;
+ /// Device Address Type
+ /// - GAPM_CFG_ADDR_PUBLIC: Device Address is a Public Static address
+ /// - GAPM_CFG_ADDR_PRIVATE: Device Address is a Private Static address
+ /// - GAPM_CFG_ADDR_HOST_PRIVACY: Device Address generated using Host Privacy feature
+ /// - GAPM_CFG_ADDR_CTNL_PRIVACY: Device Address generated using Controller Privacy feature
+ uint8_t addr_type;
+
+ /// -------------- Security Config -----------------------
+
+ /// Pairing mode authorized (see enum gapm_pairing_mode)
+ uint8_t pairing_mode;
+
+ /// -------------- ATT Database Config -----------------------
+
+ /// GAP service start handle
+ uint16_t gap_start_hdl;
+ /// GATT service start handle
+ uint16_t gatt_start_hdl;
+
+ /// Attribute database configuration
+ /// 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+ /// +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
+ /// | DBG | RFU | SC |PCP | APP_PERM | NAME_PERM |
+ /// +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
+ /// - Bit [0-2] : Device Name write permission requirements for peer device (@see gapm_write_att_perm)
+ /// - Bit [3-5] : Device Appearance write permission requirements for peer device (@see gapm_write_att_perm)
+ /// - Bit [6] : Slave Preferred Connection Parameters present
+ /// - Bit [7] : Service change feature present in GATT attribute database.
+ /// - Bit [8-14]: Reserved
+ /// - Bit [15] : Enable Debug Mode
+ uint16_t att_cfg;
+
+ /// -------------- LE Data Length Extension -----------------------
+ ///Suggested value for the Controller's maximum transmitted number of payload octets to be used
+ uint16_t sugg_max_tx_octets;
+ ///Suggested value for the Controller's maximum packet transmission time to be used
+ uint16_t sugg_max_tx_time;
+
+ /// --------------- L2CAP Configuration ---------------------------
+ /// Maximal MTU acceptable for device
+ uint16_t max_mtu;
+ /// Maximal MPS Packet size acceptable for device
+ uint16_t max_mps;
+ /// Maximum number of LE Credit based connection that can be established
+ uint8_t max_nb_lecb;
+
+ /// --------------- LE Audio Mode Supported -----------------------
+ ///
+ /// LE Audio Mode Configuration (@see gapm_audio_cfg_flag)
+ uint16_t audio_cfg;
+
+};
+
+/// Set new IRK
+struct gapm_set_irk_cmd
+{
+ /// GAPM requested operation:
+ /// - GAPM_SET_IRK: Set device configuration
+ uint8_t operation;
+ /// Device IRK used for resolvable random BD address generation (LSB first)
+ struct gap_sec_key irk;
+};
+
+/// Set device channel map
+struct gapm_set_channel_map_cmd
+{
+ /// GAPM requested operation:
+ /// - GAPM_SET_CHANNEL_MAP: Set device channel map.
+ uint8_t operation;
+ /// Channel map
+ le_chnl_map_t chmap;
+};
+
+
+/// Get local device info command
+struct gapm_get_dev_info_cmd
+{
+ /// GAPM requested operation:
+ /// - GAPM_GET_DEV_VERSION: Get Local device version
+ /// - GAPM_GET_DEV_BDADDR: Get Local device BD Address
+ /// - GAPM_GET_DEV_ADV_TX_POWER: Get device advertising power level
+ /// - GAPM_DBG_GET_MEM_INFO: Get memory usage (debug only)
+ uint8_t operation;
+};
+
+/// Local device version indication event
+struct gapm_dev_version_ind
+{
+ /// HCI version
+ uint8_t hci_ver;
+ /// LMP version
+ uint8_t lmp_ver;
+ /// Host version
+ uint8_t host_ver;
+ /// HCI revision
+ uint16_t hci_subver;
+ /// LMP subversion
+ uint16_t lmp_subver;
+ /// Host revision
+ uint16_t host_subver;
+ /// Manufacturer name
+ uint16_t manuf_name;
+};
+
+/// Local device BD Address indication event
+struct gapm_dev_bdaddr_ind
+{
+ /// Local device address information
+ struct gap_bdaddr addr;
+};
+
+/// Advertising channel Tx power level indication event
+struct gapm_dev_adv_tx_power_ind
+{
+ /// Advertising channel Tx power level
+ int8_t power_lvl;
+};
+
+/// Cancel ongoing operation
+struct gapm_cancel_cmd
+{
+ /// GAPM requested operation
+ /// - GAPM_CANCEL: Cancel running operation
+ uint8_t operation;
+};
+
+
+/// White List Management Command
+struct gapm_white_list_mgt_cmd
+{
+ /// GAPM requested operation:
+ /// - GAPM_GET_WLIST_SIZE: Get White List Size.
+ /// - GAPM_ADD_DEV_IN_WLIST: Add devices in white list.
+ /// - GAPM_RMV_DEV_FRM_WLIST: Remove devices form white list.
+ /// - GAPM_CLEAR_WLIST: Clear all devices from white list.
+ uint8_t operation;
+ /// Number of device information present in command
+ uint8_t nb;
+ /// Device address information that can be used to add or remove element in device list.
+ struct gap_bdaddr devices[__ARRAY_EMPTY];
+};
+
+/// White List Size indication event
+struct gapm_white_list_size_ind
+{
+ /// White List size
+ uint8_t size;
+};
+
+/// Resolving List Management Command
+struct gapm_ral_mgt_cmd
+{
+ /// GAPM requested operation:
+ /// - GAPM_GET_RAL_SIZE: Get Resolving List Size.
+ /// - GAPM_GET_RAL_LOC_ADDR: Get Resolving Local Address.
+ /// - GAPM_GET_RAL_PEER_ADDR: Get Resolving Peer Address.
+ /// - GAPM_ADD_DEV_IN_RAL: Add devices in resolving list.
+ /// - GAPM_RMV_DEV_FRM_RAL: Remove devices form resolving list.
+ /// - GAPM_CLEAR_RAL: Clear all devices from resolving list.
+ uint8_t operation;
+ /// Number of device information present in command
+ uint8_t nb;
+ /// Device address information that can be used to add or remove element in device list.
+ struct gap_ral_dev_info devices[__ARRAY_EMPTY];
+};
+
+/// Resolving List Size indication event
+struct gapm_ral_size_ind
+{
+ /// Resolving List size
+ uint8_t size;
+};
+
+/// Resolving Address indication event
+struct gapm_ral_addr_ind
+{
+ /// Peer or local read operation
+ uint8_t operation;
+ /// Resolving List address
+ struct gap_bdaddr addr;
+};
+
+/// Resolve Address command
+struct gapm_resolv_addr_cmd
+{
+ /// GAPM requested operation:
+ /// - GAPM_RESOLV_ADDR: Resolve device address
+ uint8_t operation;
+ /// Number of provided IRK (sahlle be > 0)
+ uint8_t nb_key;
+ /// Resolvable random address to solve
+ bd_addr_t addr;
+ /// Array of IRK used for address resolution (MSB -> LSB)
+ struct gap_sec_key irk[__ARRAY_EMPTY];
+};
+
+
+/// Indicate that resolvable random address has been solved
+struct gapm_addr_solved_ind
+{
+ /// Resolvable random address solved
+ bd_addr_t addr;
+ /// IRK that correctly solved the random address
+ struct gap_sec_key irk;
+};
+
+
+/// Advertising data that contains information set by host.
+struct gapm_adv_host
+{
+ /// Advertising mode :
+ /// - GAP_NON_DISCOVERABLE: Non discoverable mode
+ /// - GAP_GEN_DISCOVERABLE: General discoverable mode
+ /// - GAP_LIM_DISCOVERABLE: Limited discoverable mode
+ /// - GAP_BROADCASTER_MODE: Broadcaster mode
+ uint8_t mode;
+
+ /// Advertising filter policy:
+ /// - ADV_ALLOW_SCAN_ANY_CON_ANY: Allow both scan and connection requests from anyone
+ /// - ADV_ALLOW_SCAN_WLST_CON_ANY: Allow both scan req from White List devices only and
+ /// connection req from anyone
+ /// - ADV_ALLOW_SCAN_ANY_CON_WLST: Allow both scan req from anyone and connection req
+ /// from White List devices only
+ /// - ADV_ALLOW_SCAN_WLST_CON_WLST: Allow scan and connection requests from White List
+ /// devices only
+ uint8_t adv_filt_policy;
+
+ /// Advertising data length - maximum 28 bytes, 3 bytes are reserved to set
+ /// Advertising AD type flags, shall not be set in advertising data
+ uint8_t adv_data_len;
+ /// Advertising data
+ uint8_t adv_data[GAP_ADV_DATA_LEN-3];
+ /// Scan response data length- maximum 31 bytes
+ uint8_t scan_rsp_data_len;
+ /// Scan response data
+ uint8_t scan_rsp_data[GAP_SCAN_RSP_DATA_LEN];
+ /// Peer address
+ struct gap_bdaddr peer_addr;
+};
+
+/// Air operation default parameters
+struct gapm_air_operation
+{
+ /// Operation code.
+ uint8_t code;
+
+ /**
+ * Own BD address source of the device:
+ * - GAPM_STATIC_ADDR: Public or Private Static Address according to device address configuration
+ * - GAPM_GEN_RSLV_ADDR: Generated resolvable private random address
+ * - GAPM_GEN_NON_RSLV_ADDR: Generated non-resolvable private random address
+ */
+ uint8_t addr_src;
+
+ /// Dummy data use to retrieve internal operation state (should be set to 0).
+ uint16_t state;
+};
+
+
+/// Set advertising mode Command
+struct gapm_start_advertise_cmd
+{
+ /// GAPM requested operation:
+ /// - GAPM_ADV_NON_CONN: Start non connectable advertising
+ /// - GAPM_ADV_UNDIRECT: Start undirected connectable advertising
+ /// - GAPM_ADV_DIRECT: Start directed connectable advertising
+ /// - GAPM_ADV_DIRECT_LDC: Start directed connectable advertising using Low Duty Cycle
+ struct gapm_air_operation op;
+
+ /// Minimum interval for advertising
+ uint16_t intv_min;
+ /// Maximum interval for advertising
+ uint16_t intv_max;
+
+ ///Advertising channel map
+ uint8_t channel_map;
+
+ /// Advertising information
+ union gapm_adv_info
+ {
+ /// Host information advertising data (GAPM_ADV_NON_CONN and GAPM_ADV_UNDIRECT)
+ struct gapm_adv_host host;
+ /// Direct address information (GAPM_ADV_DIRECT)
+ /// (used only if reconnection address isn't set or privacy disabled)
+ struct gap_bdaddr direct;
+ } info;
+};
+
+
+/// Update Advertising Data Command - On fly update when device is advertising
+struct gapm_update_advertise_data_cmd
+{
+ /// GAPM requested operation:
+ /// - GAPM_UPDATE_ADVERTISE_DATA: Update on the fly advertising data
+ uint8_t operation;
+ /// Advertising data length - maximum 28 bytes, 3 bytes are reserved to set
+ /// Advertising AD type flags, shall not be set in advertising data
+ uint8_t adv_data_len;
+ /// Advertising data
+ uint8_t adv_data[GAP_ADV_DATA_LEN-3];
+ /// Scan response data length- maximum 31 bytes
+ uint8_t scan_rsp_data_len;
+ /// Scan response data
+ uint8_t scan_rsp_data[GAP_SCAN_RSP_DATA_LEN];
+};
+
+/// Set scan mode Command
+struct gapm_start_scan_cmd
+{
+ /// GAPM requested operation:
+ /// - GAPM_SCAN_ACTIVE: Start active scan operation
+ /// - GAPM_SCAN_PASSIVE: Start passive scan operation
+ struct gapm_air_operation op;
+
+ /// Scan interval
+ uint16_t interval;
+ /// Scan window size
+ uint16_t window;
+
+ /// Scanning mode :
+ /// - GAP_GEN_DISCOVERY: General discovery mode
+ /// - GAP_LIM_DISCOVERY: Limited discovery mode
+ /// - GAP_OBSERVER_MODE: Observer mode
+ uint8_t mode;
+
+ /// Scan filter policy:
+ /// - SCAN_ALLOW_ADV_ALL: Allow advertising packets from anyone
+ /// - SCAN_ALLOW_ADV_WLST: Allow advertising packets from White List devices only
+ uint8_t filt_policy;
+ /// Scan duplicate filtering policy:
+ /// - SCAN_FILT_DUPLIC_DIS: Disable filtering of duplicate packets
+ /// - SCAN_FILT_DUPLIC_EN: Enable filtering of duplicate packets
+ uint8_t filter_duplic;
+};
+
+
+/// Advertising or scanning report information event
+struct gapm_adv_report_ind
+{
+ /// Advertising report structure
+ adv_report_t report;
+};
+
+
+/// Set connection initialization Command
+struct gapm_start_connection_cmd
+{
+ /// GAPM requested operation:
+ /// - GAPM_CONNECTION_DIRECT: Direct connection operation
+ /// - GAPM_CONNECTION_AUTO: Automatic connection operation
+ /// - GAPM_CONNECTION_SELECTIVE: Selective connection operation
+ /// - GAPM_CONNECTION_NAME_REQUEST: Name Request operation (requires to start a direct
+ /// connection)
+ /// - GAPM_CONNECTION_GENERAL: General connection operation
+ struct gapm_air_operation op;
+
+ /// Scan interval
+ uint16_t scan_interval;
+ /// Scan window size
+ uint16_t scan_window;
+
+ /// Minimum of connection interval
+ uint16_t con_intv_min;
+ /// Maximum of connection interval
+ uint16_t con_intv_max;
+ /// Connection latency
+ uint16_t con_latency;
+ /// Link supervision timeout
+ uint16_t superv_to;
+ /// Minimum CE length
+ uint16_t ce_len_min;
+ /// Maximum CE length
+ uint16_t ce_len_max;
+
+ /// Number of peer device information present in message.
+ /// Shall be 1 for GAPM_CONNECTION_DIRECT or GAPM_CONNECTION_NAME_REQUEST operations
+ /// Shall be greater than 0 for other operations
+ uint8_t nb_peers;
+
+ /// Peer device information
+ struct gap_bdaddr peers[__ARRAY_EMPTY];
+};
+
+
+/// Name of peer device indication
+struct gapm_peer_name_ind
+{
+ /// peer device bd address
+ bd_addr_t addr;
+ /// peer device address type
+ uint8_t addr_type;
+ /// peer device name length
+ uint8_t name_len;
+ /// peer device name
+ uint8_t name[__ARRAY_EMPTY];
+};
+
+/// Confirm connection to a specific device (Connection Operation in Selective mode)
+struct gapm_connection_cfm
+{
+ /// peer device bd address
+ bd_addr_t addr;
+ /// peer device address type
+ uint8_t addr_type;
+
+ /// Minimum of connection interval
+ uint16_t con_intv_min;
+ /// Maximum of connection interval
+ uint16_t con_intv_max;
+ /// Connection latency
+ uint16_t con_latency;
+ /// Link supervision timeout
+ uint16_t superv_to;
+ /// Minimum CE length
+ uint16_t ce_len_min;
+ /// Maximum CE length
+ uint16_t ce_len_max;
+};
+
+/// Generate a random address.
+struct gapm_gen_rand_addr_cmd
+{
+ /// GAPM requested operation:
+ /// - GAPM_GEN_RAND_ADDR: Generate a random address
+ uint8_t operation;
+ /// Dummy parameter used to store the prand part of the address
+ uint8_t prand[GAP_ADDR_PRAND_LEN];
+ /// Random address type @see gap_rnd_addr_type
+ /// - GAP_STATIC_ADDR: Static random address
+ /// - GAP_NON_RSLV_ADDR: Private non resolvable address
+ /// - GAP_RSLV_ADDR: Private resolvable address
+ uint8_t rnd_type;
+};
+
+/// Parameters of the @ref GAPM_USE_ENC_BLOCK_CMD message
+struct gapm_use_enc_block_cmd
+{
+ /// Command Operation Code (shall be GAPM_USE_ENC_BLOCK)
+ uint8_t operation;
+ /// Operand 1
+ uint8_t operand_1[GAP_KEY_LEN];
+ /// Operand 2
+ uint8_t operand_2[GAP_KEY_LEN];
+};
+
+/// Parameters of the @ref GAPM_USE_ENC_BLOCK_IND message
+struct gapm_use_enc_block_ind
+{
+ /// Result (16 bytes)
+ uint8_t result[GAP_KEY_LEN];
+};
+
+/// Parameters of the @ref GAPM_GEN_DH_KEY_CMD message
+struct gapm_gen_dh_key_cmd
+{
+ /// Command Operation Code (shall be GAPM_GEN_DH_KEY)
+ uint8_t operation;
+ /// X coordinate
+ uint8_t operand_1[GAP_P256_KEY_LEN];
+ /// Y coordinate
+ uint8_t operand_2[GAP_P256_KEY_LEN];
+};
+
+/// Parameters of the @ref GAPM_GEN_DH_KEY_IND message
+struct gapm_gen_dh_key_ind
+{
+ /// Result (32 bytes)
+ uint8_t result[GAP_P256_KEY_LEN];
+};
+
+/// Parameters of the @ref GAPM_GEN_RAND_NB_CMD message
+struct gapm_gen_rand_nb_cmd
+{
+ /// Command Operation Code (shall be GAPM_GEN_RAND_NB)
+ uint8_t operation;
+};
+
+/// Parameters of the @ref GAPM_GEN_RAND_NB_IND message
+struct gapm_gen_rand_nb_ind
+{
+ /// Generation Random Number (8 bytes)
+ rand_nb_t randnb;
+};
+
+
+
+/// Create new task for specific profile
+struct gapm_profile_task_add_cmd
+{
+ /// GAPM requested operation:
+ /// - GAPM_PROFILE_TASK_ADD: Add new profile task
+ uint8_t operation;
+ /// Security Level :
+ /// 7 6 5 4 3 2 1 0
+ /// +----+----+----+----+----+----+----+----+
+ /// | Reserved |DIS | AUTH |EKS | MI |
+ /// +----+----+----+----+----+----+----+----+
+ ///
+ /// - MI: 1 - Application task is a Multi-Instantiated task, 0 - Mono-Instantiated
+ /// Only applies for service - Ignored by collectors:
+ /// - EKS: Service needs a 16 bytes encryption key
+ /// - AUTH: 0 - Disable, 1 - Enable, 2 - Unauth, 3 - Auth
+ /// - DIS: Disable the service
+ uint8_t sec_lvl;
+ /// Profile task identifier
+ uint16_t prf_task_id;
+ /// Application task number
+ uint16_t app_task;
+ /// Service start handle
+ /// Only applies for services - Ignored by collectors
+ /// 0: dynamically allocated in Attribute database
+ uint16_t start_hdl;
+ /// 32 bits value that contains value to initialize profile (database parameters, etc...)
+ uint32_t param[__ARRAY_EMPTY];
+};
+
+
+/// Inform that profile task has been added.
+struct gapm_profile_added_ind
+{
+ /// Profile task identifier
+ uint16_t prf_task_id;
+ /// Profile task number allocated
+ uint16_t prf_task_nb;
+ /// Service start handle
+ /// Only applies for services - Ignored by collectors
+ uint16_t start_hdl;
+};
+
+/// Indicate that a message has been received on an unknown task
+struct gapm_unknown_task_ind
+{
+ /// Message identifier
+ uint16_t msg_id;
+ /// Task identifier
+ uint16_t task_id;
+};
+
+/// Indicates suggested default data length
+struct gapm_sugg_dflt_data_len_ind
+{
+ ///Host's suggested value for the Controller's maximum transmitted number of payload octets
+ uint16_t suggted_max_tx_octets;
+ ///Host's suggested value for the Controller's maximum packet transmission time
+ uint16_t suggted_max_tx_time;
+};
+
+/// Indicates maximum data length
+struct gapm_max_data_len_ind
+{
+ ///Maximum number of payload octets that the local Controller supports for transmission
+ uint16_t suppted_max_tx_octets;
+ ///Maximum time, in microseconds, that the local Controller supports for transmission
+ uint16_t suppted_max_tx_time;
+ ///Maximum number of payload octets that the local Controller supports for reception
+ uint16_t suppted_max_rx_octets;
+ ///Maximum time, in microseconds, that the local Controller supports for reception
+ uint16_t suppted_max_rx_time;
+};
+
+
+/// Register a LE Protocol/Service Multiplexer command
+struct gapm_lepsm_register_cmd
+{
+ /// GAPM requested operation:
+ /// - GAPM_LEPSM_REG: Register a LE Protocol/Service Multiplexer
+ uint8_t operation;
+ /// LE Protocol/Service Multiplexer
+ uint16_t le_psm;
+ /// Application task number
+ uint16_t app_task;
+ /// Security level
+ /// 7 6 5 4 3 2 1 0
+ /// +---+---+---+---+---+---+---+---+
+ /// |MI | RFU |EKS|SEC_LVL|
+ /// +---+---+---+---+---+---+---+---+
+ /// bit[0-1]: Security level requirement (0=NO_AUTH, 1=UNAUTH, 2=AUTH, 3=SEC_CON)
+ /// bit[2] : Encryption Key Size length must have 16 bytes
+ /// bit[7] : Does the application task is multi-instantiated or not
+ uint8_t sec_lvl;
+};
+
+
+/// Unregister a LE Protocol/Service Multiplexer command
+struct gapm_lepsm_unregister_cmd
+{
+ /// GAPM requested operation:
+ /// - GAPM_LEPSM_UNREG: Unregister a LE Protocol/Service Multiplexer
+ uint8_t operation;
+ /// LE Protocol/Service Multiplexer
+ uint16_t le_psm;
+};
+
+/*
+ * MACROS
+ ****************************************************************************************
+ */
+
+
+/*
+ * GLOBAL VARIABLE DECLARATIONS
+ ****************************************************************************************
+ */
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+
+/// @} GAPM_TASK
+
+#endif /* _GAPM_TASK_H_ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm_util.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm_util.h
new file mode 100644
index 0000000000..dd5ac1e01e
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm_util.h
@@ -0,0 +1,437 @@
+/**
+ ****************************************************************************************
+ *
+ * @file gapm_util.h
+ *
+ * @brief Generic Access Profile Manager Tool Box Header.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+
+#ifndef _GAPM_UTIL_H_
+#define _GAPM_UTIL_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup GAPM_UTIL Generic Access Profile Manager Tool Box
+ * @ingroup GAPM
+ * @brief Generic Access Profile Manager Tool Box
+ *
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "rwip_config.h"
+#include "ke_task.h"
+#include "gapm.h"
+
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+/// GAP Manager operation state - air commands
+enum gapm_op_state
+{
+ /* state in non connected mode */
+ /// Initial state of the operation
+ GAPM_OP_INIT,
+ /// Set operation parameters
+ GAPM_OP_SET_PARAMS,
+ /// Clear White List operation
+ GAPM_OP_CLEAR_WL,
+ /// Set White List operation
+ GAPM_OP_SET_WL,
+ /// Set operation advertise data
+ GAPM_OP_SET_ADV_DATA,
+ /// Set operation scan response data
+ GAPM_OP_SET_SCAN_RSP_DATA,
+ /// Generation of address
+ GAPM_OP_ADDR_GEN,
+ /// Set private address
+ GAPM_OP_ADDR_SET,
+ /// Start operation (advertising, scanning or connecting)
+ GAPM_OP_START,
+ /// Operation is in wait (advertising, scanning or connecting) state
+ GAPM_OP_WAIT,
+ /// Stop operation (advertising, scanning or connecting)
+ GAPM_OP_STOP,
+ /// Operation is finished
+ GAPM_OP_FINISH,
+
+ /// Error state
+ GAPM_OP_ERROR,
+
+
+ /* state in connected mode */
+ /// Connection established
+ GAPM_OP_CONNECT,
+ /// Perform peer device name request
+ GAPM_OP_NAME_REQ,
+ /// Perform peer device disconnection
+ GAPM_OP_DISCONNECT,
+
+ /// Operation is in canceled state and shall be terminated.
+ GAPM_OP_CANCEL,
+ /// Operation is in timeout state and shall be terminated.
+ GAPM_OP_TIMEOUT,
+ /// Operation is terminated due to a timeout.
+ GAPM_OP_TERM_TIMEOUT,
+ /// Renew address generation
+ GAPM_OP_ADDR_RENEW,
+ /// initiate a connection request
+ GAPM_OP_CONNECT_REQ,
+
+
+ /// Mask used to retrieve operation state in state parameter
+ GAPM_OP_MASK = 0x00FF,
+
+ /* Specific bit fields into operation state machine */
+ /// Mask used to know in state parameter if message is in kernel queue
+ GAPM_OP_QUEUED_MASK = 0x0100,
+
+ /// Operation is in canceled state and shall be terminated.
+ GAPM_OP_CANCELED_MASK = 0x0200,
+
+ /// Operation is in timeout state and shall be terminated.
+ GAPM_OP_TIMEOUT_MASK = 0x0400,
+
+ /// Renew address generation
+ GAPM_OP_ADDR_RENEW_MASK = 0x0800,
+
+ /// Mask used to know in state parameter if a connection has been initiated
+ GAPM_OP_CONNECTING_MASK = 0x1000,
+
+ /// Mask used to know if device is currently in scanning state
+ GAPM_OP_SCANNING_MASK = 0x2000
+};
+
+/// state machine of reset operation
+enum gapm_op_reset_state
+{
+ /// initialization of reset operation state machine
+ GAPM_OP_RESET_INIT,
+ /// HCI_RESET_CMD command execution completed
+ GAPM_OP_RESET_HCI,
+ /// SET_ADDR_CMD command execution completed add by wq
+ GAPM_OP_SET_ADDR,
+ /// HCI_SET_EVT_MASK_CMD command execution completed
+ GAPM_OP_RESET_SET_EVT_MASK,
+ /// HCI_LE_SET_EVT_MASK_CMD command execution completed
+ GAPM_OP_RESET_LE_SET_EVT_MASK,
+ /// HCI_RD_BD_ADDR_CMD command execution completed
+ GAPM_OP_RESET_RD_BD_ADDR,
+ #if (BLE_CENTRAL || BLE_PERIPHERAL)
+ /// HCI_LE_RD_BUFF_SIZE_CMD command execution completed
+ GAPM_OP_RESET_LE_RD_BUFF_SIZE,
+ /// HCI_RD_BUFF_SIZE_CMD command execution completed
+ GAPM_OP_RESET_RD_BUFF_SIZE,
+ #endif // (BLE_CENTRAL || BLE_PERIPHERAL)
+};
+
+/// state machine of setup operation
+enum gapm_op_setup_state
+{
+ /// initialization of device setup operation state machine
+ GAPM_OP_SETUP_INIT,
+ #if BLE_DEBUG
+ GAPM_OP_SETUP_SET_4_0_LE_EVT_MASK,
+ #endif // BLE_DEBUG
+ /// HCI_LE_WR_SUGGTED_DFT_DATA_LEN_CMD command execution completed
+ GAPM_OP_SETUP_WR_LE_DFT_DATA_LEN_CMD,
+ /// HCI_LE_SET_RSLV_PRIV_ADDR_TO_CMD command execution completed
+ GAPM_OP_SETUP_SET_RENEW_TO,
+ /// HCI_LE_SET_ADDR_RESOL_EN_CMD command execution completed
+ GAPM_OP_SETUP_EN_CTRL_PRIV,
+ /// Device address management is over:
+ /// HCI_RD_BD_ADDR_CMD command execution completed
+ /// or HCI_LE_SET_RAND_ADDR_CMD command execution completed
+ GAPM_OP_SETUP_ADDR_MGT,
+ #if (SECURE_CONNECTIONS)
+ /// HCI_LE_RD_LOC_P256_PUB_KEY_CMD command execution completed
+ GAPM_OP_SETUP_RD_PRIV_KEY,
+ #endif // (SECURE_CONNECTIONS)
+};
+
+/*
+ * TYPE DEFINITIONS
+ ****************************************************************************************
+ */
+
+
+/*
+ * MACROS
+ ****************************************************************************************
+ */
+/// check if current role is supported by configuration
+#define GAPM_IS_ROLE_SUPPORTED(role_type)\
+ ((gapm_env.role & (role_type)) == (role_type))
+
+/// Get current operation state
+#define GAPM_GET_OP_STATE(operation) \
+ ((operation).state & (GAPM_OP_MASK))
+
+/// Set current operation state
+#define GAPM_SET_OP_STATE(operation, new_state) \
+ (operation).state = (((operation).state & ~(GAPM_OP_MASK)) | (new_state))
+
+
+/// Get if operation is in kernel queue
+#define GAPM_IS_OP_FIELD_SET(operation, field) \
+ ((((operation).state) & (GAPM_OP_##field##_MASK)) != 0)
+
+/// Set operation in kernel queue
+#define GAPM_SET_OP_FIELD(operation, field) \
+ ((operation).state) |= (GAPM_OP_##field##_MASK)
+
+/// Clear operation in kernel queue
+#define GAPM_CLEAR_OP_FIELD(operation, field) \
+ ((operation).state) &= ~(GAPM_OP_##field##_MASK)
+
+
+
+
+/*
+ * GLOBAL VARIABLE DECLARATIONS
+ ****************************************************************************************
+ */
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief Interface to get the device role.
+ *
+ * @return uint8_t device role
+ *
+ ****************************************************************************************
+ */
+uint8_t gapm_get_role(void);
+
+
+#if (BLE_BROADCASTER || BLE_PERIPHERAL)
+/**
+ ****************************************************************************************
+ * @brief Enable or disable advertising mode.
+ *
+ * @param[in] en_flag enabling flag for advertising mode
+ *
+ ****************************************************************************************
+ */
+void gapm_set_adv_mode(uint8_t en_flag);
+/**
+ ****************************************************************************************
+ * Execute Advertising operation according to current operation state.
+ ****************************************************************************************
+ */
+void gapm_execute_adv_op(void);
+
+
+/**
+ ****************************************************************************************
+ * Perform a sanity check on advertising operation
+ *
+ * @return sanity check status: GAP_ERR_NO_ERROR if succeed, error code else.
+ ****************************************************************************************
+ */
+uint8_t gapm_adv_op_sanity(void);
+
+/**
+ ****************************************************************************************
+ * Set the advertising data
+ *
+ * @return length Size of the
+ ****************************************************************************************
+ */
+void gapm_set_adv_data(uint8_t length, uint8_t* data);
+
+#endif // (BLE_BROADCASTER || BLE_PERIPHERAL)
+
+
+#if (BLE_OBSERVER || BLE_CENTRAL)
+/**
+ ****************************************************************************************
+ * @brief Enable or disable scanning mode.
+ *
+ * @param[in] en_flag enabling flag for scanning mode
+ * @param[in] filter_duplic_en enabling duplicate filtering mode
+ *
+ ****************************************************************************************
+ */
+void gapm_set_scan_mode(uint8_t en_flag, uint8_t filter_duplic_en);
+
+
+/**
+ ****************************************************************************************
+ * @brief retrieve AD Type Flag information in advertising data.
+ *
+ * @param[in] data Advertising data
+ * @param[in] length Advertising data length
+ *
+ * @return Advertising AD Type flag value if found, 0x00 else.
+ ****************************************************************************************
+ */
+uint8_t gapm_get_ad_type_flag(uint8_t *data, uint8_t length);
+
+
+/**
+ ****************************************************************************************
+ * @brief Add device to unfiltered device
+ *
+ * @param[in] addr Device address
+ * @param[in] addr_type Device address type
+ ****************************************************************************************
+ */
+void gapm_add_to_filter(bd_addr_t * addr, uint8_t addr_type);
+
+/**
+ ****************************************************************************************
+ * @brief Check if device is filtered or not when a scan response data is received
+ *
+ * If device is not filtered (present in filter list), in that case function returns false
+ * and device is removed from filtered devices.
+ *
+ * @param[in] addr Device address
+ * @param[in] addr_type Device address type
+ *
+ * @return true if device filtered, false else.
+ ****************************************************************************************
+ */
+bool gapm_is_filtered(bd_addr_t * addr, uint8_t addr_type);
+
+/**
+ ****************************************************************************************
+ * @brief Execute Scan operation according to current operation state.
+ *
+ ****************************************************************************************
+ */
+void gapm_execute_scan_op(void);
+
+/**
+ ****************************************************************************************
+ * Perform a sanity check on Scanning operation
+ *
+ * @return sanity check status: GAP_ERR_NO_ERROR if succeed, error code else.
+ ****************************************************************************************
+ */
+uint8_t gapm_scan_op_sanity(void);
+
+#endif // (BLE_OBSERVER || BLE_CENTRAL)
+
+
+#if (BLE_CENTRAL)
+/**
+ ****************************************************************************************
+ * @brief Execute Connection operation according to current operation state.
+ *
+ ****************************************************************************************
+ */
+void gapm_execute_connect_op(void);
+
+
+/**
+ ****************************************************************************************
+ * Perform a sanity check on connection operation
+ *
+ * @return sanity check status: GAP_ERR_NO_ERROR if succeed, error code else.
+ ****************************************************************************************
+ */
+uint8_t gapm_connect_op_sanity(void);
+
+#endif // (BLE_CENTRAL)
+
+/**
+ ****************************************************************************************
+ * @brief Requests current operation state to change.
+ *
+ * 1. Check if new state can be applied to ongoing operation.
+ * 2. Verify that message is not in kernel message queue.
+ * 3. If not push it into @ref TASK_GAPM message queue
+ *
+ * @param[in] op_type Ongoing Air operation type (GAPM_OP_AIR)
+ * @param[in] state New state to set
+ * @param[in] status Status code of the transition
+ *
+ ****************************************************************************************
+ */
+void gapm_update_air_op_state(uint8_t op_type, uint8_t state, uint8_t status);
+
+
+/**
+ ****************************************************************************************
+ * @brief Sends a basic HCI command (with no parameter)
+ *
+ * @param[in] opcode Command opcode
+ ****************************************************************************************
+ */
+void gapm_basic_hci_cmd_send(uint16_t opcode);
+
+/**
+ ****************************************************************************************
+ * @brief General configuration for new connections (including privacy 1.2)
+ *
+ * @param[in] msgid message id
+ * @param[in] event Parameters
+ ****************************************************************************************
+ */
+void gapm_setup_conn(ke_msg_id_t const msgid, struct hci_le_enh_con_cmp_evt const *event);
+
+/**
+ ****************************************************************************************
+ * @brief Get proper advertising mode
+ *
+ * @param[in] operation Operation
+ * @param[in] air_op Air operation
+ *
+ * @return mode
+ ****************************************************************************************
+ */
+uint8_t gapm_get_adv_mode (uint8_t operation, struct gapm_air_operation* air_op);
+
+/**
+ ****************************************************************************************
+ * @brief Get local address type
+ *
+ * @return addres type
+ ****************************************************************************************
+ */
+uint8_t gapm_get_local_addrtype (void);
+
+
+/**
+ ****************************************************************************************
+ * Handles the Reset state machine
+ *
+ *
+ * @param[in] current_state Current operation state (@see enum gapm_reset_state)
+ * @param[in] status Current operation status
+ ****************************************************************************************
+ */
+void gapm_op_reset_continue(uint8_t current_state, uint8_t status);
+
+/**
+ ****************************************************************************************
+ * Handles the Device Setup state machine
+ *
+ *
+ * @param[in] current_state Current operation state (@see enum gapm_reset_state)
+ * @param[in] status Current operation status
+ ****************************************************************************************
+ */
+void gapm_op_setup_continue(uint8_t current_state, uint8_t status);
+
+/// @} GAPM_UTIL
+
+#endif /* _GAPM_UTIL_H_ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gatt.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gatt.h
new file mode 100644
index 0000000000..e09c9ae7d9
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gatt.h
@@ -0,0 +1,83 @@
+/**
+ ****************************************************************************************
+ *
+ * @file gatt.h
+ *
+ * @brief Header file - GATT.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef GATT_H_
+#define GATT_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup GATT Generic Attribute Profile
+ * @ingroup HOST
+ * @brief Generic Attribute Profile.
+ *
+ * The GATT module is responsible for providing an API for all attribute related operations.
+ * It is responsible for all the service framework activities using the Attribute protocol
+ * for discovering services and for reading and writing characteristic values on a peer device.
+ * To achieve this, the GATT interfaces with @ref ATTM "ATTM", @ref ATTC "ATTC" and the
+ * @ref ATTS "ATTS".
+ *
+ * @{
+ ****************************************************************************************
+ */
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "rwip_config.h"
+#include "att.h"
+
+
+/*
+ * DEFINE DECLARATIONS
+ ****************************************************************************************
+ */
+
+/// retrieve gatt attribute handle from attribute index.
+#define GATT_GET_ATT_HANDLE(idx)\
+ ((gattm_svc_get_start_hdl() == 0)? (0) :(gattm_svc_get_start_hdl() + (idx)))
+
+
+
+
+#if (BLE_ATTS)
+/// GATT Attribute database handles
+/// Generic Attribute Profile Service
+enum gatt_db_att
+{
+ GATT_IDX_PRIM_SVC,
+ GATT_IDX_CHAR_SVC_CHANGED,
+ GATT_IDX_SVC_CHANGED,
+ GATT_IDX_SVC_CHANGED_CFG,
+
+ GATT_IDX_NUMBER
+};
+#endif /* (BLE_ATTS)*/
+
+/*
+ * Type Definition
+ ****************************************************************************************
+ */
+
+
+/// Service Changed type definition
+struct gatt_svc_changed
+{
+ /// Service start handle which changed
+ uint16_t start_hdl;
+ /// Service end handle which changed
+ uint16_t end_hdl;
+};
+
+
+/// @} GATT
+#endif // GATT_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattc.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattc.h
new file mode 100644
index 0000000000..2e0f8dfc78
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattc.h
@@ -0,0 +1,176 @@
+/**
+ ****************************************************************************************
+ *
+ * @file gattc.h
+ *
+ * @brief Header file - GATT Controller.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef GATTC_H_
+#define GATTC_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup GATTC Generic Attribute Profile Controller
+ * @ingroup GATT
+ * @brief Generic Attribute Profile Controller.
+ *
+ * This GATT module is responsible for providing an API for all attribute related operations
+ * related to a BLE connection.
+ * It is responsible for all the service framework activities using the Attribute protocol
+ * for discovering services and for reading and writing characteristic values on a peer device.
+ * To achieve this, the GATT interfaces with @ref ATTC "ATTC" and the @ref ATTS "ATTS".
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+/* kernel task */
+#include "rwip_config.h"
+#if (BLE_GATTC)
+
+#include "co_list.h"
+
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/// Operation type
+enum gattc_op_type
+{
+ #if (BLE_ATTS)
+ /// Operation used to Server Request operations
+ GATTC_OP_SERVER,
+ #endif // (BLE_ATTS)
+
+ #if (BLE_ATTC)
+ /// Operation used to Client Request operations
+ GATTC_OP_CLIENT,
+ /// Service Discovery Procedure operation
+ GATTC_OP_SDP,
+ #endif // (BLE_ATTC)
+
+ /// Max number of operations
+ GATTC_OP_MAX
+};
+
+/*
+ * TYPES DEFINITIONS
+ ****************************************************************************************
+ */
+
+#if (BLE_ATTC)
+/// Attribute Client environment variable requirements
+struct attc_env
+{
+ /// List of ATT message used to aggregate long value in a single buffer.
+ struct co_list rsp_list;
+ /// List that contains peer device event registration
+ struct co_list reg_evt;
+ /// List that contains data for service discovery
+ struct co_list sdp_data;
+};
+#endif // (BLE_ATTC)
+
+#if (BLE_ATTS)
+/// Attribute server environment variables
+struct atts_env
+{
+ /// This is used to merge save all the prepare write request received ,
+ /// before receiving the execute or cancel or disconnection.
+ struct co_list prep_wr_req_list;
+ /// This list is used to put any data in order to send a response to peer device
+ struct co_list rsp;
+ /// List of PDU to process
+ struct co_list pdu_queue;
+ /// This structure is used to store in cache latest attribute read value
+ struct gattc_read_cfm* read_cache;
+};
+#endif // (BLE_ATTS)
+
+/// GATT controller environment variable structure.
+struct gattc_env_tag
+{
+ /// Request operation Kernel message
+ void* operation[GATTC_OP_MAX];
+
+ #if (BLE_ATTC)
+ struct attc_env client;
+ #endif // (BLE_ATTC)
+
+ #if (BLE_ATTS)
+ struct atts_env server;
+ #endif // (BLE_ATTS)
+
+ /// Current MTU Size
+ uint16_t mtu_size;
+
+ /// A transaction timeout occurs, reject next attribute commands
+ bool trans_timeout;
+};
+/*
+ * MACRO DEFINITIONS
+ ****************************************************************************************
+ */
+
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+
+/**
+ ****************************************************************************************
+ * @brief Created link connection parameters (from bond data) has been set, connection
+ * ready to be used.
+ *
+ * @param[in] conidx Connection Index
+ *
+ ****************************************************************************************
+ */
+void gattc_con_enable(uint8_t conidx);
+
+
+/**
+ ****************************************************************************************
+ * @brief Gets the negotiated MTU. This function gets the negotiated MTU.
+ *
+ * @param[in] idx connection record index
+ *
+ * @return MTU negotiated
+ *
+ ****************************************************************************************
+ */
+uint16_t gattc_get_mtu(uint8_t idx);
+
+/**
+ ****************************************************************************************
+ * @brief Sets the negotiated MTU This function stores the negotiated MTU.
+ *
+ * @param[in] idx connection record index
+ * @param[in] mtu negotiated MTU
+ *
+ * @return status indicates if the MTU setting operation is successful
+ *
+ ****************************************************************************************
+ */
+void gattc_set_mtu(uint8_t idx, uint16_t mtu);
+
+
+
+#endif /* (BLE_GATTC) */
+
+/// @} GATTC
+#endif // GATTC_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattc_int.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattc_int.h
new file mode 100644
index 0000000000..c186d03d37
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattc_int.h
@@ -0,0 +1,260 @@
+/**
+ ****************************************************************************************
+ *
+ * @file gattc_int.h
+ *
+ * @brief Header file - GATTC_INT.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef GATTC_TASK_INT_H_
+#define GATTC_TASK_INT_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup GATTC_INT Internals
+ * @ingroup GATTC
+ * @brief Internal features of the GATTC module
+ *
+ * @{
+ ****************************************************************************************
+ */
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "rwip_config.h"
+
+#if (BLE_GATTC)
+#include "gattc.h"
+#include "gattc_task.h"
+#include "ke_task.h"
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+/// retrieve on-going operation command
+#define GATT_OPERATION_CMD(conidx, op_type, cmd) \
+ ((struct cmd*) gattc_get_operation_ptr(conidx, op_type))
+
+#define GATT_WRITE_ERROR_CODE (0xFFFF)
+
+
+/// number of GATT Controller Process
+#define GATTC_IDX_MAX BLE_CONNECTION_MAX
+
+
+
+/// states of GATT Controller task
+enum gattc_state_id
+{
+ /// Connection ready state
+ GATTC_READY = 0,
+ #if (BLE_ATTC)
+ /// Client operation on-going
+ GATTC_CLIENT_BUSY = (1 << GATTC_OP_CLIENT),
+ /// Service Discovery Procedure operation on-going
+ GATTC_SDP_BUSY = (1 << GATTC_OP_SDP),
+ #endif // (BLE_ATTC)
+ #if (BLE_ATTS)
+ /// Server operation on-going
+ GATTC_SERVER_BUSY = (1 << GATTC_OP_SERVER),
+ #endif // (BLE_ATTS)
+ /// Connection started but ATTS not ready
+ GATTC_CONNECTED = (1 << (GATTC_OP_MAX + 1)),
+
+ /// Free state
+ GATTC_FREE = (1 << (GATTC_OP_MAX + 2)),
+ /// Number of defined states.
+ GATTC_STATE_MAX
+};
+
+
+
+/*
+ * TYPE DEFINITIONS
+ ****************************************************************************************
+ */
+
+
+
+/*
+ * GLOBAL VARIABLE DECLARATIONS
+ ****************************************************************************************
+ */
+extern struct gattc_env_tag* gattc_env[GATTC_IDX_MAX];
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+
+/**
+ ****************************************************************************************
+ * @brief Initialization of the GATT controller module.
+ * This function performs all the initialization steps of the GATT module.
+ *
+ * @param[in] reset true if it's requested by a reset; false if it's boot initialization
+ *
+ ****************************************************************************************
+ */
+void gattc_init(bool reset);
+
+
+/**
+ ****************************************************************************************
+ * @brief Initialize GATT controller for connection.
+ *
+ * @param[in] conidx connection record index
+ * @param[in] role device role after connection establishment
+ *
+ ****************************************************************************************
+ */
+void gattc_create(uint8_t conidx);
+
+
+
+/**
+ ****************************************************************************************
+ * @brief Cleanup GATT controller resources for connection
+ *
+ * @param[in] conidx connection record index
+ * @param[in] disconnect True if disconnection occurs else request due to init or reset
+ *
+ ****************************************************************************************
+ */
+void gattc_cleanup(uint8_t conidx, bool disconnect);
+
+/**
+ * @brief Send a complete event of ongoing executed operation to requester.
+ * It also clean-up variable used for ongoing operation.
+ *
+ * @param[in] conidx Connection index
+ * @param[in] op_type Operation type.
+ * @param[in] status Status of completed operation
+ */
+void gattc_send_complete_evt(uint8_t conidx, uint8_t op_type, uint8_t status);
+
+/**
+ ****************************************************************************************
+ * @brief Send operation completed message with status error code not related to a
+ * running operation.
+ *
+ * @param[in] conidx Connection index
+ * @param[in] operation Operation code
+ * @param[in] seq_num Operation sequence number
+ * @param[in] requester requester of operation
+ * @param[in] status Error status code
+ ****************************************************************************************
+ */
+void gattc_send_error_evt(uint8_t conidx, uint8_t operation, uint16_t seq_num, const ke_task_id_t requester, uint8_t status);
+
+
+/**
+ ****************************************************************************************
+ * @brief Get operation on going
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] op_type Operation type.
+ *
+ * @return operation code on going
+ ****************************************************************************************
+ */
+uint8_t gattc_get_operation(uint8_t conidx, uint8_t op_type);
+
+/**
+ ****************************************************************************************
+ * @brief Get operation pointer
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] op_type Operation type.
+ *
+ * @return operation pointer on going
+ ****************************************************************************************
+ */
+void* gattc_get_operation_ptr(uint8_t conidx, uint8_t op_type);
+
+
+/**
+ ****************************************************************************************
+ * @brief Set operation pointer
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] op_type Operation type.
+ * @param[in] op Operation pointer.
+ *
+ ****************************************************************************************
+ */
+void gattc_set_operation_ptr(uint8_t conidx, uint8_t op_type, void* op);
+
+/**
+ ****************************************************************************************
+ * @brief Operation execution not finish, request kernel to reschedule it in order to
+ * continue its execution
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] op_type Operation type.
+ *
+ * @return if operation has been rescheduled (not done if operation pointer is null)
+ ****************************************************************************************
+ */
+bool gattc_reschedule_operation(uint8_t conidx, uint8_t op_type);
+
+/**
+ ****************************************************************************************
+ * @brief Get requester of on going operation
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] op_type Operation type.
+ *
+ * @return task that requests to execute the operation
+ ****************************************************************************************
+ */
+ke_task_id_t gattc_get_requester(uint8_t conidx, uint8_t op_type);
+
+
+
+/**
+ ****************************************************************************************
+ * @brief Get Operation Sequence Number
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] op_type Operation type.
+ *
+ * @return Sequence number provided for operation execution
+ ****************************************************************************************
+ */
+uint16_t gattc_get_op_seq_num(uint8_t conidx, uint8_t op_type);
+
+
+/**
+ ****************************************************************************************
+ * @brief Update task state
+ *
+ * @param[in] conidx Connection index
+ * @param[in] state to update
+ * @param[in] set state to busy (true) or idle (false)
+ *
+ ****************************************************************************************
+ */
+void gattc_update_state(uint8_t conidx, ke_state_t state, bool busy);
+
+
+/*
+ * TASK DESCRIPTOR DECLARATIONS
+ ****************************************************************************************
+ */
+extern const struct ke_state_handler gattc_default_handler;
+extern ke_state_t gattc_state[GATTC_IDX_MAX];
+
+
+#endif // (BLE_GATTC)
+
+/// @} GATTCTASK
+#endif // GATTC_INT
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattc_task.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattc_task.h
new file mode 100644
index 0000000000..6ba94f761e
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattc_task.h
@@ -0,0 +1,722 @@
+/**
+ ****************************************************************************************
+ *
+ * @file gattc_task.h
+ *
+ * @brief Header file - GATTCTASK.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef GATTC_TASK_H_
+#define GATTC_TASK_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup GATTCTASK Task
+ * @ingroup GATTC
+ * @brief Handles ALL messages to/from GATT Controller block.
+ *
+ * The GATTCTASK is responsible for managing the messages coming from
+ * the attribute layer and host-level layers for dedicated connection.
+ * The task includes services and characteristic discovery, configuration exchanges
+ * and attribute value access operations (reading, writing, notification and indication).
+ *
+ * Messages may originate from @ref ATTC "ATTC", @ref ATTS "ATTS", @ref GAP "GAP"
+ * and Application.
+ *
+ * @{
+ ****************************************************************************************
+ */
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "att.h"
+#include "rwip_task.h" // Task definitions
+//#include "compiler.h"
+#include "ble_arch.h"
+#include
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/// GATT Task messages
+enum gattc_msg_id
+{
+ /* Default event */
+ /// Command Complete event
+ GATTC_CMP_EVT = TASK_FIRST_MSG(TASK_ID_GATTC),
+
+ /* ATTRIBUTE CLIENT */
+ /// Server configuration request
+ GATTC_EXC_MTU_CMD,
+ /// Indicate that the ATT MTU has been updated (negotiated)
+ GATTC_MTU_CHANGED_IND,
+
+ /*Discover All Services */
+ /*Discover Services by Service UUID*/
+ /*Find Included Services*/
+ /*Discover Characteristics by UUID*/
+ /*Discover All Characteristics of a Service*/
+ /*Discover All Characteristic Descriptors*/
+ /// Discovery command
+ GATTC_DISC_CMD,
+ /* GATT -> HL: Events to Upper layer */
+ /*Discover All Services*/
+ /// Discovery services indication
+ GATTC_DISC_SVC_IND,
+ /*Find Included Services*/
+ /// Discover included services indication
+ GATTC_DISC_SVC_INCL_IND,
+ /*Discover All Characteristics of a Service*/
+ /// Discover characteristic indication
+ GATTC_DISC_CHAR_IND,
+ /*Discover All Characteristic Descriptors*/
+ /// Discovery characteristic descriptor indication
+ GATTC_DISC_CHAR_DESC_IND,
+
+ /*Read Value*/
+ /*Read Using UUID*/
+ /*Read Long Value*/
+ /*Read Multiple Values*/
+ /// Read command
+ GATTC_READ_CMD,
+ /// Read response
+ GATTC_READ_IND,
+
+ /*Write without response*/
+ /*Write without response with Authentication*/
+ /*Write Characteristic Value*/
+ /*Signed Write Characteristic Value*/
+ /*Write Long Characteristic Value*/
+ /*Characteristic Value Reliable Write*/
+ /*Write Characteristic Descriptors*/
+ /*Write Long Characteristic Descriptors*/
+ /*Characteristic Value Reliable Write*/
+ /// Write command request
+ GATTC_WRITE_CMD,
+
+ /* Cancel / Execute pending write operations */
+ /// Execute write characteristic request
+ GATTC_EXECUTE_WRITE_CMD,
+
+ /* Reception of an indication or notification from peer device. */
+ /// peer device triggers an event (notification)
+ GATTC_EVENT_IND,
+ /// peer device triggers an event that requires a confirmation (indication)
+ GATTC_EVENT_REQ_IND,
+ /// Confirm reception of event (trigger a confirmation message)
+ GATTC_EVENT_CFM,
+
+ /// Registration to peer device events (Indication/Notification).
+ GATTC_REG_TO_PEER_EVT_CMD,
+
+ /* -------------------------- ATTRIBUTE SERVER ------------------------------- */
+ /*Notify Characteristic*/
+ /*Indicate Characteristic*/
+ /// send an event to peer device
+ GATTC_SEND_EVT_CMD,
+
+ /* Service Changed Characteristic Indication */
+ /**
+ * Send a Service Changed indication to a device
+ * (message structure is struct gattm_svc_changed_ind_req)
+ */
+ GATTC_SEND_SVC_CHANGED_CMD,
+ /**
+ * Inform the application when sending of Service Changed indications has been
+ * enabled or disabled
+ */
+ GATTC_SVC_CHANGED_CFG_IND,
+
+ /* Indicate that read operation is requested. */
+ /// Read command indicated to upper layers.
+ GATTC_READ_REQ_IND,
+ /// REad command confirmation from upper layers.
+ GATTC_READ_CFM,
+
+ /* Indicate that write operation is requested. */
+ /// Write command indicated to upper layers.
+ GATTC_WRITE_REQ_IND,
+ /// Write command confirmation from upper layers.
+ GATTC_WRITE_CFM,
+
+ /* Indicate that write operation is requested. */
+ /// Request Attribute info to upper layer - could be trigger during prepare write
+ GATTC_ATT_INFO_REQ_IND,
+ /// Attribute info from upper layer confirmation
+ GATTC_ATT_INFO_CFM,
+
+ /* ----------------------- SERVICE DISCOVERY PROCEDURE --------------------------- */
+ /// Service Discovery command
+ GATTC_SDP_SVC_DISC_CMD,
+ /// Service Discovery indicate that a service has been found.
+ GATTC_SDP_SVC_IND,
+
+ /* -------------------------- TRANSACTION ERROR EVENT ----------------------------- */
+ /// Transaction Timeout Error Event no more transaction will be accepted
+ GATTC_TRANSACTION_TO_ERROR_IND,
+
+ /* ------------------------------- Internal API ----------------------------------- */
+ /// Client Response timeout indication
+ GATTC_CLIENT_RTX_IND,
+ /// Server indication confirmation timeout indication
+ GATTC_SERVER_RTX_IND,
+};
+
+
+/// request operation type - application interface
+enum gattc_operation
+{
+ /* Attribute Client Flags */
+ /* No Operation (if nothing has been requested) */
+ /* ************************************************ */
+ /// No operation
+ GATTC_NO_OP = 0x00,
+
+ /* Operation flags for MTU Exchange */
+ /* ************************************************ */
+ /// Perform MTU exchange
+ GATTC_MTU_EXCH,
+
+ /* Operation flags for discovery operation */
+ /* ************************************************ */
+ /// Discover all services
+ GATTC_DISC_ALL_SVC,
+ /// Discover services by UUID
+ GATTC_DISC_BY_UUID_SVC,
+ /// Discover included services
+ GATTC_DISC_INCLUDED_SVC,
+ /// Discover all characteristics
+ GATTC_DISC_ALL_CHAR,
+ /// Discover characteristic by UUID
+ GATTC_DISC_BY_UUID_CHAR,
+ /// Discover characteristic descriptor
+ GATTC_DISC_DESC_CHAR,
+
+ /* Operation flags for reading attributes */
+ /* ************************************************ */
+ /// Read attribute
+ GATTC_READ,
+ /// Read long attribute
+ GATTC_READ_LONG,
+ /// Read attribute by UUID
+ GATTC_READ_BY_UUID,
+ /// Read multiple attribute
+ GATTC_READ_MULTIPLE,
+
+ /* Operation flags for writing/modifying attributes */
+ /* ************************************************ */
+ /// Write attribute
+ GATTC_WRITE,
+ /// Write no response
+ GATTC_WRITE_NO_RESPONSE,
+ /// Write signed
+ GATTC_WRITE_SIGNED,
+ /// Execute write
+ GATTC_EXEC_WRITE,
+
+ /* Operation flags for registering to peer device */
+ /* events */
+ /* ************************************************ */
+ /// Register to peer device events
+ GATTC_REGISTER,
+ /// Unregister from peer device events
+ GATTC_UNREGISTER,
+
+ /* Operation flags for sending events to peer device*/
+ /* ************************************************ */
+ /// Send an attribute notification
+ GATTC_NOTIFY,
+ /// Send an attribute indication
+ GATTC_INDICATE,
+ /// Send a service changed indication
+ GATTC_SVC_CHANGED,
+
+ /* Service Discovery Procedure */
+ /* ************************************************ */
+ /// Search specific service
+ GATTC_SDP_DISC_SVC,
+ /// Search for all services
+ GATTC_SDP_DISC_SVC_ALL,
+ /// Cancel Service Discovery Procedure
+ GATTC_SDP_DISC_CANCEL,
+};
+
+/// Service Discovery Attribute type
+enum gattc_sdp_att_type
+{
+ /// No Attribute Information
+ GATTC_SDP_NONE,
+ /// Included Service Information
+ GATTC_SDP_INC_SVC,
+ /// Characteristic Declaration
+ GATTC_SDP_ATT_CHAR,
+ /// Attribute Value
+ GATTC_SDP_ATT_VAL,
+ /// Attribute Descriptor
+ GATTC_SDP_ATT_DESC,
+};
+
+/// Command complete event data structure
+struct gattc_op_cmd
+{
+ /// GATT request type
+ uint8_t operation;
+ /// operation sequence number
+ uint16_t seq_num;
+};
+
+/// Command complete event data structure
+struct gattc_cmp_evt
+{
+ /// GATT request type
+ uint8_t operation;
+ /// Status of the request
+ uint8_t status;
+ /// operation sequence number - provided when operation is started
+ uint16_t seq_num;
+};
+
+
+/// Service Discovery Command Structure
+struct gattc_exc_mtu_cmd
+{
+ /// GATT request type
+ uint8_t operation;
+ /// operation sequence number
+ uint16_t seq_num;
+};
+
+/// Indicate that the ATT MTU has been updated (negotiated)
+struct gattc_mtu_changed_ind
+{
+ /// Exchanged MTU value
+ uint16_t mtu;
+ /// operation sequence number
+ uint16_t seq_num;
+};
+
+/// Service Discovery Command Structure
+struct gattc_disc_cmd
+{
+ /// GATT request type
+ uint8_t operation;
+ /// UUID length
+ uint8_t uuid_len;
+ /// operation sequence number
+ uint16_t seq_num;
+ /// start handle range
+ uint16_t start_hdl;
+ /// start handle range
+ uint16_t end_hdl;
+ /// UUID
+ uint8_t uuid[__ARRAY_EMPTY];
+};
+
+
+/// Discover Service indication Structure
+struct gattc_disc_svc_ind
+{
+ /// start handle
+ uint16_t start_hdl;
+ /// end handle
+ uint16_t end_hdl;
+ /// UUID length
+ uint8_t uuid_len;
+ /// service UUID
+ uint8_t uuid[__ARRAY_EMPTY];
+};
+
+/// Discover Service indication Structure
+struct gattc_disc_svc_incl_ind
+{
+ /// element handle
+ uint16_t attr_hdl;
+ /// start handle
+ uint16_t start_hdl;
+ /// end handle
+ uint16_t end_hdl;
+ /// UUID length
+ uint8_t uuid_len;
+ /// included service UUID
+ uint8_t uuid[__ARRAY_EMPTY];
+};
+
+/// Discovery All Characteristic indication Structure
+struct gattc_disc_char_ind
+{
+ /// database element handle
+ uint16_t attr_hdl;
+ /// pointer attribute handle to UUID
+ uint16_t pointer_hdl;
+ /// properties
+ uint8_t prop;
+ /// UUID length
+ uint8_t uuid_len;
+ /// characteristic UUID
+ uint8_t uuid[__ARRAY_EMPTY];
+};
+
+/// Discovery Characteristic Descriptor indication Structure
+struct gattc_disc_char_desc_ind
+{
+ /// database element handle
+ uint16_t attr_hdl;
+ /// UUID length
+ uint8_t uuid_len;
+ /// Descriptor UUID
+ uint8_t uuid[__ARRAY_EMPTY];
+};
+
+
+/// Simple Read (GATTC_READ or GATTC_READ_LONG)
+struct gattc_read_simple
+{
+ /// attribute handle
+ uint16_t handle;
+ /// start offset in data payload
+ uint16_t offset;
+ /// Length of data to read (0 = read all)
+ uint16_t length;
+};
+
+/// Read by UUID: search UUID and read it's characteristic value (GATTC_READ_BY_UUID)
+/// Note: it doesn't perform an automatic read long.
+struct gattc_read_by_uuid
+{
+ /// Start handle
+ uint16_t start_hdl;
+ /// End handle
+ uint16_t end_hdl;
+ /// Size of UUID
+ uint8_t uuid_len;
+ /// UUID value
+ uint8_t uuid[__ARRAY_EMPTY];
+};
+
+/// Read Multiple short characteristic (GATTC_READ_MULTIPLE)
+struct gattc_read_multiple
+{
+ /// attribute handle
+ uint16_t handle;
+ /// Known Handle length (shall be != 0)
+ uint16_t len;
+};
+
+/// Read command (Simple, Long, Multiple, or by UUID)
+struct gattc_read_cmd
+{
+ /// request type
+ uint8_t operation;
+ /// number of read (only used for multiple read)
+ uint8_t nb;
+ /// operation sequence number
+ uint16_t seq_num;
+
+ /// request union according to read type
+ union gattc_read_req
+ {
+ /// Simple Read (GATTC_READ or GATTC_READ_LONG)
+ struct gattc_read_simple simple;
+ /// Read by UUID (GATTC_READ_BY_UUID)
+ struct gattc_read_by_uuid by_uuid;
+ /// Read Multiple short characteristic (GATTC_READ_MULTIPLE)
+ struct gattc_read_multiple multiple[1];
+ } req;
+};
+
+/// Attribute value read indication
+struct gattc_read_ind
+{
+ /// Attribute handle
+ uint16_t handle;
+ /// Read offset
+ uint16_t offset;
+ /// Read length
+ uint16_t length;
+ /// Handle value
+ uint8_t value[__ARRAY_EMPTY];
+};
+
+/// Write peer attribute value command
+struct gattc_write_cmd
+{
+ /// Request type
+ uint8_t operation;
+ /// Perform automatic execution
+ /// (if false, an ATT Prepare Write will be used this shall be use for reliable write)
+ bool auto_execute;
+ /// operation sequence number
+ uint16_t seq_num;
+ /// Attribute handle
+ uint16_t handle;
+ /// Write offset
+ uint16_t offset;
+ /// Write length
+ uint16_t length;
+ /// Internal write cursor shall be initialized to 0
+ uint16_t cursor;
+ /// Value to write
+ uint8_t value[__ARRAY_EMPTY];
+};
+
+/// Write peer attribute value command
+struct gattc_execute_write_cmd
+{
+ /// Request type
+ uint8_t operation;
+
+ /// [True = perform/False cancel] pending write operations
+ bool execute;
+ /// operation sequence number
+ uint16_t seq_num;
+};
+/// peer device triggers an event (notification)
+struct gattc_event_ind
+{
+ /// Event Type
+ uint8_t type;
+ /// Data length
+ uint16_t length;
+ /// Attribute handle
+ uint16_t handle;
+ /// Event Value
+ uint8_t value[__ARRAY_EMPTY];
+};
+
+/// peer device triggers an event that requires a confirmation (indication)
+struct gattc_event_req_ind
+{
+ /// Event Type
+ uint8_t type;
+ /// Data length
+ uint16_t length;
+ /// Attribute handle
+ uint16_t handle;
+ /// Event Value
+ uint8_t value[__ARRAY_EMPTY];
+};
+
+/// Confirm reception of event (trigger a confirmation message)
+struct gattc_event_cfm
+{
+ /// Attribute handle
+ uint16_t handle;
+};
+
+/// Register to peer device events command
+struct gattc_reg_to_peer_evt_cmd
+{
+ /// Request type
+ uint8_t operation;
+ /// operation sequence number
+ uint16_t seq_num;
+ /// attribute start handle
+ uint16_t start_hdl;
+ /// attribute end handle
+ uint16_t end_hdl;
+};
+
+/// Send an event to peer device
+struct gattc_send_evt_cmd
+{
+ /// Request type (notification / indication)
+ uint8_t operation;
+ /// operation sequence number
+ uint16_t seq_num;
+ /// characteristic handle
+ uint16_t handle;
+ /// length of packet to send
+ uint16_t length;
+ /// data value
+ uint8_t value[__ARRAY_EMPTY];
+};
+
+/// Inform that attribute value is requested by lower layers.
+struct gattc_read_req_ind
+{
+ /// Handle of the attribute that has to be read
+ uint16_t handle;
+};
+
+/// Confirm Read Request requested by GATT to profile
+struct gattc_read_cfm
+{
+ /// Handle of the attribute read
+ uint16_t handle;
+ /// Data length read
+ uint16_t length;
+ /// Status of read command execution by upper layers
+ uint8_t status;
+ /// attribute data value
+ uint8_t value[__ARRAY_EMPTY];
+};
+
+/// Inform that a modification of database has been requested by peer device.
+struct gattc_write_req_ind
+{
+ /// Handle of the attribute that has to be written
+ uint16_t handle;
+ /// offset at which the data has to be written
+ uint16_t offset;
+ /// Data length to be written
+ uint16_t length;
+ /// Data to be written in attribute database
+ uint8_t value[__ARRAY_EMPTY];
+};
+
+/// Confirm modification of database from upper layer when requested by peer device.
+struct gattc_write_cfm
+{
+ /// Handle of the attribute written
+ uint16_t handle;
+ /// Status of write command execution by upper layers
+ uint8_t status;
+};
+
+/// Parameters for @ref GATTC_SEND_SVC_CHANGED_CMD message
+struct gattc_send_svc_changed_cmd
+{
+ /// Request Type
+ uint8_t operation;
+ /// operation sequence number
+ uint16_t seq_num;
+ /// Start of Affected Attribute Handle Range
+ uint16_t svc_shdl;
+ /// End of Affected Attribute Handle Range
+ uint16_t svc_ehdl;
+};
+
+/// Parameters for @ref GATTC_SVC_CHANGED_CFG_IND and @ref GATTC_SVC_CHANGED_SET_CFG_REQ message
+struct gattc_svc_changed_cfg
+{
+ /**
+ * Current value of the Client Characteristic Configuration descriptor for the Service
+ * Changed characteristic
+ */
+ uint16_t ind_cfg;
+};
+
+
+/// Request Attribute info to upper layer - could be trigger during prepare write
+struct gattc_att_info_req_ind
+{
+ /// Handle of the attribute for which info are requested
+ uint16_t handle;
+};
+
+/// Attribute info from upper layer confirmation
+struct gattc_att_info_cfm
+{
+ /// Handle of the attribute
+ uint16_t handle;
+ /// Current length of the attribute
+ uint16_t length;
+ /// use to know if it's possible to modify the attribute
+ /// can contains authorization or application error code.
+ uint8_t status;
+};
+
+
+/// Service Discovery command
+struct gattc_sdp_svc_disc_cmd
+{
+ /// GATT Request Type
+ /// - GATTC_SDP_DISC_SVC Search specific service
+ /// - GATTC_SDP_DISC_SVC_ALL Search for all services
+ /// - GATTC_SDP_DISC_CANCEL Cancel Service Discovery Procedure
+ uint8_t operation;
+ /// Service UUID Length
+ uint8_t uuid_len;
+ /// operation sequence number
+ uint16_t seq_num;
+ /// Search start handle
+ uint16_t start_hdl;
+ /// Search end handle
+ uint16_t end_hdl;
+ /// Service UUID
+ uint8_t uuid[ATT_UUID_128_LEN];
+};
+
+
+/// Information about included service
+struct gattc_sdp_include_svc
+{
+ /// Attribute Type
+ /// - GATTC_SDP_INC_SVC: Included Service Information
+ uint8_t att_type;
+ /// Included service UUID Length
+ uint8_t uuid_len;
+ /// Included Service UUID
+ uint8_t uuid[ATT_UUID_128_LEN];
+ /// Included service Start Handle
+ uint16_t start_hdl;
+ /// Included service End Handle
+ uint16_t end_hdl;
+};
+
+/// Information about attribute characteristic
+struct gattc_sdp_att_char
+{
+ /// Attribute Type
+ /// - GATTC_SDP_ATT_CHAR: Characteristic Declaration
+ uint8_t att_type;
+ /// Value property
+ uint8_t prop;
+ /// Value Handle
+ uint16_t handle;
+};
+
+/// Information about attribute
+struct gattc_sdp_att
+{
+ /// Attribute Type
+ /// - GATTC_SDP_ATT_VAL: Attribute Value
+ /// - GATTC_SDP_ATT_DESC: Attribute Descriptor
+ uint8_t att_type;
+ /// Attribute UUID Length
+ uint8_t uuid_len;
+ /// Attribute UUID
+ uint8_t uuid[ATT_UUID_128_LEN];
+};
+
+/// Attribute information
+union gattc_sdp_att_info
+{
+ /// Attribute Type
+ uint8_t att_type;
+ /// Information about attribute characteristic
+ struct gattc_sdp_att_char att_char;
+ /// Information about included service
+ struct gattc_sdp_include_svc inc_svc;
+ /// Information about attribute
+ struct gattc_sdp_att att;
+};
+
+
+/// Service Discovery indicate that a service has been found.
+struct gattc_sdp_svc_ind
+{
+ /// Service UUID Length
+ uint8_t uuid_len;
+ /// Service UUID
+ uint8_t uuid[ATT_UUID_128_LEN];
+ /// Service start handle
+ uint16_t start_hdl;
+ /// Service end handle
+ uint16_t end_hdl;
+ /// attribute information present in the service
+ /// (length = end_hdl - start_hdl)
+ union gattc_sdp_att_info info[__ARRAY_EMPTY];
+};
+
+
+
+/// @} GATTCTASK
+#endif // GATTC_TASK_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattm.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattm.h
new file mode 100644
index 0000000000..20467625fe
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattm.h
@@ -0,0 +1,117 @@
+/**
+ ****************************************************************************************
+ *
+ * @file gattm.h
+ *
+ * @brief Header file - GATT Manager.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef GATTM_H_
+#define GATTM_H_
+
+
+
+/**
+ ****************************************************************************************
+ * @addtogroup GATTM Generic Attribute Profile Manager
+ * @ingroup GATT
+ * @brief Generic Attribute Profile.
+ *
+ * The GATT manager module is responsible for providing an API for all action operations
+ * not related to a connection. It's responsible to managing internal database.
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+/* kernel task */
+#include "rwip_config.h"
+
+#if (BLE_CENTRAL || BLE_PERIPHERAL)
+#include
+#include
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief Initialization of the GATT manager module.
+ * This function performs all the initialization steps of the GATT module.
+ *
+ * @param[in] reset true if it's requested by a reset; false if it's boot initialization
+ *
+ ****************************************************************************************
+ */
+void gattm_init(bool reset);
+
+
+/**
+ ****************************************************************************************
+ * @brief Initialize GATT attribute database
+ *
+ * @param[in] start_hdl Service Start Handle
+ * @param[in] svc_chg_en Service Change feature enabled
+ *
+ * @return status code of attribute database initialization
+ * Command status code:
+ * - @ref ATT_ERR_NO_ERROR: If database creation succeeds.
+ * - @ref ATT_ERR_INVALID_HANDLE: If start_hdl given in parameter + nb of attribute override
+ * some existing services handles.
+ * - @ref ATT_ERR_INSUFF_RESOURCE: There is not enough memory to allocate service buffer.
+ * or of new attribute cannot be added because all expected
+ * attributes already add
+ ****************************************************************************************
+ */
+uint8_t gattm_init_attr(uint16_t start_hdl, bool svc_chg_en);
+
+/**
+ ****************************************************************************************
+ * @brief Initialize GATT resources for connection.
+ *
+ * @param[in] conidx connection record index
+ * @param[in] role device role after connection establishment
+ *
+ ****************************************************************************************
+ */
+void gattm_create(uint8_t conidx);
+/**
+ ****************************************************************************************
+ * @brief Cleanup GATT resources for connection
+ *
+ * @param[in] conidx connection record index
+ *
+ ****************************************************************************************
+ */
+void gattm_cleanup(uint8_t conidx);
+
+
+#if (BLE_ATTS)
+/**
+ ****************************************************************************************
+ * @brief Return the start handle of the GATT service in the database *
+ ****************************************************************************************
+ */
+uint16_t gattm_svc_get_start_hdl(void);
+#endif //(BLE_ATTS)
+#endif /* (BLE_CENTRAL || BLE_PERIPHERAL) */
+
+/// @} GATTM
+#endif // GATTM_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattm_int.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattm_int.h
new file mode 100644
index 0000000000..75f2e6d547
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattm_int.h
@@ -0,0 +1,98 @@
+/**
+ ****************************************************************************************
+ *
+ * @file gattm_int.h
+ *
+ * @brief Internal Header file - GATTM.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef GATTM_INT_H_
+#define GATTM_INT_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup GATTM_INT Task
+ * @ingroup GATTM
+ * @brief Internal function required for GATTM usage
+ * @{
+ ****************************************************************************************
+ */
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "ke_task.h"
+#include "gattm_task.h"
+
+#include "attm_db.h"
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/// number of GATT Process
+#define GATTM_IDX_MAX 0x01
+
+
+/// GATT database default features
+#define GATT_DB_DEFAULT_FEAT 0x0001
+/// GATT database Service changed feature
+#define GATT_DB_SVC_CHG_FEAT 0x000E
+
+
+
+/// states of GATT task
+enum gattm_state_id
+{
+ /// idle state
+ GATTM_IDLE,
+ /// busy state
+ GATTM_BUSY,
+ /// Number of defined states.
+ GATTM_STATE_MAX
+};
+
+
+
+/// GATT General Information Manager
+struct gattm_env_tag
+{
+ #if (BLE_ATTS)
+ /// Environment data needed by attribute database
+ struct attm_db db;
+
+ /// GATT service start handle
+ uint16_t svc_start_hdl;
+ #endif // (BLE_ATTS)
+};
+
+/*
+ * GLOBAL VARIABLE DECLARATIONS
+ ****************************************************************************************
+ */
+extern struct gattm_env_tag gattm_env;
+
+
+/*
+ * FUNCTIONS DECLARATIONS
+ ****************************************************************************************
+ */
+
+
+
+/*
+ * TASK DESCRIPTOR DECLARATIONS
+ ****************************************************************************************
+ */
+extern const struct ke_state_handler gattm_default_handler;
+extern ke_state_t gattm_state[GATTM_IDX_MAX];
+
+
+/// @} GATTM_INT
+#endif // GATTM_INT_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattm_task.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattm_task.h
new file mode 100644
index 0000000000..639e1773e9
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattm_task.h
@@ -0,0 +1,388 @@
+/**
+ ****************************************************************************************
+ *
+ * @file gattm_task.h
+ *
+ * @brief Header file - GATTMTASK.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef GATTM_TASK_H_
+#define GATTM_TASK_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup GATTMTASK Task
+ * @ingroup GATTM
+ * @brief Handles ALL GATT block operations not related to a connection.
+ *
+ * The GATTMTASK is responsible for managing internal attribute database and state of
+ * GATT controller which manage GATT block operations related to a connection.
+ *
+ * Messages may originate from @ref ATTM "ATTM", @ref GAP "GAP" and Application.
+ *
+ * @{
+ ****************************************************************************************
+ */
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "rwip_task.h" // Task definitions
+#include "att.h"
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+
+/// GATT Task messages
+enum gattm_msg_id
+{
+ /* Database Management */
+ /// Add service in database request
+ GATTM_ADD_SVC_REQ = TASK_FIRST_MSG(TASK_ID_GATTM),
+ /// Add service in database response
+ GATTM_ADD_SVC_RSP,
+
+ /* Service management */
+ /// Get permission settings of service request
+ GATTM_SVC_GET_PERMISSION_REQ,
+ /// Get permission settings of service response
+ GATTM_SVC_GET_PERMISSION_RSP,
+ /// Set permission settings of service request
+ GATTM_SVC_SET_PERMISSION_REQ,
+ /// Set permission settings of service response
+ GATTM_SVC_SET_PERMISSION_RSP,
+
+ /* Attribute Manipulation */
+ /// Get permission settings of attribute request
+ GATTM_ATT_GET_PERMISSION_REQ,
+ /// Get permission settings of attribute response
+ GATTM_ATT_GET_PERMISSION_RSP,
+ /// Set permission settings of attribute request
+ GATTM_ATT_SET_PERMISSION_REQ,
+ /// Set permission settings of attribute response
+ GATTM_ATT_SET_PERMISSION_RSP,
+
+ /// Get attribute value request
+ GATTM_ATT_GET_VALUE_REQ,
+ /// Get attribute value response
+ GATTM_ATT_GET_VALUE_RSP,
+ /// Set attribute value request
+ GATTM_ATT_SET_VALUE_REQ,
+ /// Set attribute value response
+ GATTM_ATT_SET_VALUE_RSP,
+
+ /* Debug messages */
+ /// DEBUG ONLY: Destroy Attribute database request
+ GATTM_DESTROY_DB_REQ,
+ /// DEBUG ONLY: Destroy Attribute database response
+ GATTM_DESTROY_DB_RSP,
+ /// DEBUG ONLY: Retrieve list of services request
+ GATTM_SVC_GET_LIST_REQ,
+ /// DEBUG ONLY: Retrieve list of services response
+ GATTM_SVC_GET_LIST_RSP,
+ /// DEBUG ONLY: Retrieve information of attribute request
+ GATTM_ATT_GET_INFO_REQ,
+ /// DEBUG ONLY: Retrieve information of attribute response
+ GATTM_ATT_GET_INFO_RSP,
+};
+
+
+/**
+ * Attribute Description
+ */
+struct gattm_att_desc
+{
+ /** Attribute UUID (LSB First) */
+ uint8_t uuid[ATT_UUID_128_LEN];
+
+ /**
+ * Attribute Permission (@see attm_perm_mask)
+ */
+ uint16_t perm;
+
+
+ /**
+ * Maximum length of the attribute
+ *
+ * Note:
+ * For Included Services and Characteristic Declarations, this field contains targeted
+ * handle.
+ *
+ * For Characteristic Extended Properties, this field contains 2 byte value
+ *
+ * Not used Client Characteristic Configuration and Server Characteristic Configuration,
+ * this field is not used.
+ */
+ uint16_t max_len;
+
+ /**
+ * Attribute Extended permissions
+ *
+ * Extended Value permission bit field
+ *
+ * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+ * +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
+ * | RI |UUID_LEN |EKS | Reserved |
+ * +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
+ *
+ * Bit [0-11] : Reserved
+ * Bit [12] : Encryption key Size must be 16 bytes
+ * Bit [13-14]: UUID Length (0 = 16 bits, 1 = 32 bits, 2 = 128 bits, 3 = RFU)
+ * Bit [15] : Trigger Read Indication (0 = Value present in Database, 1 = Value not present in Database)
+ */
+ uint16_t ext_perm;
+};
+
+/**
+ * Service description
+ */
+struct gattm_svc_desc
+{
+ /// Attribute Start Handle (0 = dynamically allocated)
+ uint16_t start_hdl;
+ /// Task identifier that manages service
+ uint16_t task_id;
+
+ /**
+ * 7 6 5 4 3 2 1 0
+ * +----+----+----+----+----+----+----+----+
+ * |SEC |UUID_LEN |DIS | AUTH |EKS | MI |
+ * +----+----+----+----+----+----+----+----+
+ *
+ * Bit [0] : Task that manage service is multi-instantiated (Connection index is conveyed)
+ * Bit [1] : Encryption key Size must be 16 bytes
+ * Bit [2-3]: Service Permission (0 = NO_AUTH, 1 = UNAUTH, 2 = AUTH, 3 = Secure Connect)
+ * Bit [4] : Disable the service
+ * Bit [5-6]: UUID Length (0 = 16 bits, 1 = 32 bits, 2 = 128 bits, 3 = RFU)
+ * Bit [7] : Secondary Service (0 = Primary Service, 1 = Secondary Service)
+ */
+ uint8_t perm;
+
+ /// Number of attributes
+ uint8_t nb_att;
+
+ /** Service UUID */
+ uint8_t uuid[ATT_UUID_128_LEN];
+ /**
+ * List of attribute description present in service.
+ */
+ struct gattm_att_desc atts[__ARRAY_EMPTY];
+};
+
+
+/// Add service in database request
+struct gattm_add_svc_req
+{
+ /// service description
+ struct gattm_svc_desc svc_desc;
+};
+
+/// Add service in database response
+struct gattm_add_svc_rsp
+{
+ /// Start handle of allocated service in attribute database
+ uint16_t start_hdl;
+ /// Return status of service allocation in attribute database.
+ uint8_t status;
+};
+
+/* Service management */
+/// Get permission settings of service request
+struct gattm_svc_get_permission_req
+{
+ /// Service start attribute handle
+ uint16_t start_hdl;
+};
+
+/// Get permission settings of service response
+struct gattm_svc_get_permission_rsp
+{
+ /// Service start attribute handle
+ uint16_t start_hdl;
+ /// service permission
+ uint8_t perm;
+ /// Return status
+ uint8_t status;
+};
+
+/// Set permission settings of service request
+struct gattm_svc_set_permission_req
+{
+ /// Service start attribute handle
+ uint16_t start_hdl;
+ /// service permission
+ uint8_t perm;
+};
+
+/// Set permission settings of service response
+struct gattm_svc_set_permission_rsp
+{
+ /// Service start attribute handle
+ uint16_t start_hdl;
+ /// Return status
+ uint8_t status;
+};
+
+
+/* Attribute management */
+/// Get permission settings of attribute request
+struct gattm_att_get_permission_req
+{
+ /// Handle of the attribute
+ uint16_t handle;
+};
+
+/// Get permission settings of attribute response
+struct gattm_att_get_permission_rsp
+{
+ /// Handle of the attribute
+ uint16_t handle;
+ /// Attribute permission
+ uint16_t perm;
+ /// Extended Attribute permission
+ uint16_t ext_perm;
+ /// Return status
+ uint8_t status;
+};
+
+/// Set permission settings of attribute request
+struct gattm_att_set_permission_req
+{
+ /// Handle of the attribute
+ uint16_t handle;
+ /// Attribute permission
+ uint16_t perm;
+ /// Extended Attribute permission
+ uint16_t ext_perm;
+};
+
+/// Set permission settings of attribute response
+struct gattm_att_set_permission_rsp
+{
+ /// Handle of the attribute
+ uint16_t handle;
+ /// Return status
+ uint8_t status;
+};
+
+
+/// Get attribute value request
+struct gattm_att_get_value_req
+{
+ /// Handle of the attribute
+ uint16_t handle;
+};
+
+/// Get attribute value response
+struct gattm_att_get_value_rsp
+{
+ /// Handle of the attribute
+ uint16_t handle;
+ /// Attribute value length
+ uint16_t length;
+ /// Return status
+ uint8_t status;
+ /// Attribute value
+ uint8_t value[__ARRAY_EMPTY];
+};
+
+/// Set attribute value request
+struct gattm_att_set_value_req
+{
+ /// Handle of the attribute
+ uint16_t handle;
+ /// Attribute value length
+ uint16_t length;
+ /// Attribute value
+ uint8_t value[__ARRAY_EMPTY];
+};
+
+/// Set attribute value response
+struct gattm_att_set_value_rsp
+{
+ /// Handle of the attribute
+ uint16_t handle;
+ /// Return status
+ uint8_t status;
+};
+
+/// DEBUG ONLY: Destroy Attribute database request
+struct gattm_destroy_db_req
+{
+ /// New Gap Start Handle
+ uint16_t gap_hdl;
+ /// New Gatt Start Handle
+ uint16_t gatt_hdl;
+};
+
+/// DEBUG ONLY: Destroy Attribute database Response
+struct gattm_destroy_db_rsp
+{
+ /// Return status
+ uint8_t status;
+};
+
+
+/// Service information
+struct gattm_svc_info
+{
+ /// Service start handle
+ uint16_t start_hdl;
+ /// Service end handle
+ uint16_t end_hdl;
+ /// Service task_id
+ uint16_t task_id;
+ /// Service permission
+ uint8_t perm;
+};
+
+/// DEBUG ONLY: Retrieve list of services response
+struct gattm_svc_get_list_rsp
+{
+ /// Return status
+ uint8_t status;
+ /// Number of services
+ uint8_t nb_svc;
+ /// Array of information about services
+ struct gattm_svc_info svc[__ARRAY_EMPTY];
+};
+
+/// DEBUG ONLY: Retrieve information of attribute request
+struct gattm_att_get_info_req
+{
+ /// Attribute Handle
+ uint16_t handle;
+};
+
+/// DEBUG ONLY: Retrieve information of attribute response
+struct gattm_att_get_info_rsp
+{
+ /// Return status
+ uint8_t status;
+ /// UUID Length
+ uint8_t uuid_len;
+ /// Attribute Handle
+ uint16_t handle;
+ /// Attribute Permissions
+ uint16_t perm;
+ /// Extended Attribute permission
+ uint16_t ext_perm;
+ /// UUID value
+ uint8_t uuid[ATT_UUID_128_LEN];
+};
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+/// @} GATTMTASK
+#endif // GATTM_TASK_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/h4tl.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/h4tl.h
new file mode 100644
index 0000000000..7d9a859748
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/h4tl.h
@@ -0,0 +1,148 @@
+/**
+ ****************************************************************************************
+ *
+ * @file h4tl.h
+ *
+ * @brief H4 UART Transport Layer header file.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef H4TL_H_
+#define H4TL_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup H4TL H4 UART Transport Layer
+ * @ingroup H4TL
+ * @brief H4 UART Transport Layer
+ *
+ * This module creates the abstraction between External UART driver and HCI generic functions
+ * (designed for H4 UART transport layer).
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+
+#include "rwip_config.h" // stack configuration
+
+#if (H4TL_SUPPORT)
+#include "rwip.h" // SW interface
+
+#include // standard integer definition
+#include // standard boolean definition
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+#define H4TL_LOGICAL_CHANNEL_LEN (1)
+
+
+/// Type of transport layer
+enum h4tl_type
+{
+#if (BLE_HOST_PRESENT)
+#if (BLE_EMB_PRESENT) // FULL HOST
+ /// Application Controller Interface Transport Layer
+ H4TL_TYPE_AHI = 0,
+#if (HCI_TL_SUPPORT)
+ /// Host Controller Interface Transport Layer
+ H4TL_TYPE_HCI = 0,
+#endif // (HCI_TL_SUPPORT)
+#else // !(BLE_EMB_PRESENT) // SPLIT HOST
+#if (AHI_TL_SUPPORT)
+ /// Application Controller Interface Transport Layer
+ H4TL_TYPE_AHI,
+#endif // AHI_TL_SUPPORT
+ /// Host Controller Interface Transport Layer
+ H4TL_TYPE_HCI,
+#endif // (BLE_EMB_PRESENT)
+#else // !(BLE_HOST_PRESENT) // SPLIT EMB
+ /// Host Controller Interface Transport Layer
+ H4TL_TYPE_HCI = 0,
+#endif // (BLE_HOST_PRESENT)
+
+ H4TL_TYPE_MAX,
+};
+
+
+/*
+ * GLOBAL VARIABLE DECLARATIONS
+ ****************************************************************************************
+ */
+
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+/**
+ ****************************************************************************************
+ * @brief H4TL transport initialization.
+ *
+ * Puts the External Interface driver in reception, waiting for simple 1 byte message type. Space for
+ * reception is allocated with ke_msg_alloc and the pointer is handed to env.rx. RX
+ * interrupt is enabled.
+ *
+ * @param[in] tl_type Transport Layer Type (@see enum h4tl_type)
+ * @param[in] len Length of the buffer to be transmitted.
+ *
+ *****************************************************************************************
+ */
+void h4tl_init(uint8_t tl_type, const struct rwip_eif_api* eif);
+
+
+/**
+ ****************************************************************************************
+ * @brief H4TL write function.
+ *
+ * @param[in] type Type of the buffer to be transmitted. It can take one of the following
+ * values:
+ * - @ref HCI_EVT_MSG_TYPE for event message
+ * - @ref HCI_ACL_MSG_TYPE for ACL data
+ * - @ref HCI_SYNC_MSG_TYPE for synchronous data
+ *
+ * @param[in] buf Pointer to the buffer to be transmitted. @note The buffer passed as
+ * parameter must have one free byte before the first payload byte, so that the H4TL
+ * module can put the type byte as first transmitted data.
+ *
+ * @param[in] len Length of the buffer to be transmitted.
+ * @param[in] tx_callback Callback for indicating the end of transfer
+ *****************************************************************************************
+ */
+void h4tl_write(uint8_t type, uint8_t *buf, uint16_t len, void (*tx_callback)(void));
+
+#if DEEP_SLEEP
+/**
+ ****************************************************************************************
+ * @brief Start External Interface input flow
+ *
+ *****************************************************************************************
+ */
+void h4tl_start(void);
+
+/**
+ ****************************************************************************************
+ * @brief Stop External Interface input flow if possible
+ *
+ * @return true if External Interface flow was stopped, false otherwise
+ *****************************************************************************************
+ */
+bool h4tl_stop(void);
+#endif //DEEP_SLEEP
+
+#endif //H4TL_SUPPORT
+
+/// @} H4TL
+
+#endif // H4TL_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/hci.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/hci.h
new file mode 100644
index 0000000000..c9e45dfcc2
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/hci.h
@@ -0,0 +1,496 @@
+/**
+ ****************************************************************************************
+ *
+ * @file hci.h
+ *
+ * @brief This file contains definitions related to the HCI module.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef HCI_H_
+#define HCI_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup HCI Host Controller Interface
+ * @ingroup ROOT
+ * @brief HCI module handling communication between lower and higher layers in split
+ * architecture.
+ * @{
+ ****************************************************************************************
+ */
+
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+
+#include "rwip_config.h" // SW configuration
+
+#if (HCI_PRESENT)
+
+#include // standard definition
+#include // standard integer
+#include "co_bt.h" // BT standard definitions
+
+#include "ke_task.h" // SW main module
+#include "rwip_task.h" // Task definitions
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+#if (BLE_EMB_PRESENT || BLE_HOST_PRESENT)
+#if (BLE_CENTRAL || BLE_PERIPHERAL)
+#define HCI_BLE_CON_SUPPORT 1
+#else // (BLE_CENTRAL || BLE_PERIPHERAL)
+#define HCI_BLE_CON_SUPPORT 0
+#endif // (BLE_CENTRAL || BLE_PERIPHERAL)
+#else //(BLE_EMB_PRESENT || BLE_HOST_PRESENT)
+#define HCI_BLE_CON_SUPPORT 0
+#endif //(BLE_EMB_PRESENT || BLE_HOST_PRESENT)
+
+/// Length of HCI Reset Message
+#define HCI_RESET_MSG_LEN 4
+
+/// HCI Reset Message use to resync.
+#define HCI_RESET_MSG_BUF {HCI_CMD_MSG_TYPE, (HCI_RESET_CMD_OPCODE & 0xFF), ((HCI_RESET_CMD_OPCODE >> 8) & 0xFF), 0}
+
+/*
+ * TYPE DEFINITIONS
+ ****************************************************************************************
+ */
+
+/// Message API of the HCI task
+enum HCI_MSG
+{
+ HCI_MSG_ID_FIRST = TASK_FIRST_MSG(TASK_ID_HCI), //0x800
+
+ HCI_CMD_CMP_EVENT,
+ HCI_CMD_STAT_EVENT,
+ HCI_EVENT,
+ HCI_LE_EVENT,
+
+ HCI_COMMAND,
+
+ #if (HCI_BLE_CON_SUPPORT)
+ HCI_ACL_DATA_RX,
+ HCI_ACL_DATA_TX,
+ #endif // (HCI_BLE_CON_SUPPORT)
+
+ #if BT_EMB_PRESENT
+ HCI_BT_ACL_DATA_TX,
+ HCI_BT_ACL_DATA_RX,
+ #if VOICE_OVER_HCI
+ HCI_BT_SYNC_DATA_TX,
+ HCI_BT_SYNC_DATA_RX,
+ #endif //VOICE_OVER_HCI
+ #endif //BT_EMB_PRESENT
+
+ HCI_TCI_LMP,
+
+ HCI_DBG_EVT,
+
+ HCI_MSG_ID_LAST
+};
+
+/// Status of HCI command header processing
+enum HCI_CMD_HDR
+{
+ /// Header is correct
+ HCI_CMD_HDR_STATUS_OK,
+ /// Opcode is unknown
+ HCI_CMD_HDR_STATUS_UNKNOWN,
+ /// Header is not correct
+ HCI_CMD_HDR_STATUS_FAIL
+};
+
+
+
+///HCI Command header components structure
+struct hci_cmd_hdr
+{
+ /// Opcode field
+ uint16_t opcode;
+ ///Parameter length - the number of bytes of the command parameters
+ uint8_t parlen;
+};
+
+///HCI ACL data packets header structure
+struct hci_acl_hdr
+{
+ ///Connection handle & Data Flags
+ uint16_t hdl_flags;
+ ///Data length in number of bytes
+ uint16_t datalen;
+};
+
+#if (BT_EMB_PRESENT)
+#if (VOICE_OVER_HCI)
+///HCI synchronous data packets header structure
+struct hci_sync_hdr
+{
+ /// Connection handle & Data Flags
+ uint16_t conhdl_flags;
+ /// Data total length in number of bytes
+ uint8_t data_total_len;
+};
+#endif // (VOICE_OVER_HCI)
+#endif // (BT_EMB_PRESENT)
+
+///HCI Event header components structure - contains all details possible in an event
+struct hci_evt_hdr
+{
+ ///Event code
+ uint8_t code;
+ ///Event parameters length
+ uint8_t parlen;
+};
+
+/*
+ * GLOBAL VARIABLE DECLARATIONS
+ ****************************************************************************************
+ */
+
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+/**
+****************************************************************************************
+* @brief Initialize HCI (including transport)
+*****************************************************************************************
+*/
+void hci_init(void);
+
+/**
+****************************************************************************************
+* @brief Reset HCI
+*****************************************************************************************
+*/
+void hci_reset(void);
+
+#if (BLE_EMB_PRESENT || BT_EMB_PRESENT)
+/**
+ ****************************************************************************************
+ * @brief Function called when an internal task needs to send a HCI message to Host
+ *
+ * This function decides whether the message is sent externally onto HCI Transport Layer
+ * or redirected into an internal task of the other side of the HCI.
+ *
+ * The input message ID, length and parameters must be filled.
+ * In case the message is an HCI command or event, the source ID must be filled with the
+ * command opcode or event code.
+ * In case the message concerns a particular BT or BLE link, the destination ID must be
+ * filled with the associated link ID.
+ *
+ * @param[in] param Pointer to the parameters of the Kernel message carrying the HCI message
+ *****************************************************************************************
+ */
+void hci_send_2_host(void *param);
+#endif // (BLE_EMB_PRESENT || BT_EMB_PRESENT)
+
+#if BLE_HOST_PRESENT
+/**
+ ****************************************************************************************
+ * @brief Function called when an internal task needs to send a HCI message to Controller
+ *
+ * This function decides whether the message is sent externally onto HCI Transport Layer
+ * or redirected into an internal task of the other side of the HCI.
+ *
+ * The input message ID, length and parameters must be filled.
+ * In case the message is an HCI command or event, the source ID must be filled with the
+ * command opcode or event code.
+ * In case the message concerns a particular BT or BLE link, the destination ID must be
+ * filled with the associated link ID.
+ *
+ * @param[in] param Pointer to the parameters of the Kernel message carrying the HCI message
+ *****************************************************************************************
+ */
+void hci_send_2_controller(void *param);
+#endif //BLE_HOST_PRESENT
+
+#if (BT_EMB_PRESENT)
+/**
+ ****************************************************************************************
+ * @brief Register BD address for a BT ACL connection
+ *
+ * @param[in] link_id BT ACL connection link ID
+ * @param[in] bd_addr Pointer to the device BD address associated to the connection
+ *****************************************************************************************
+ */
+void hci_bt_acl_bdaddr_register(uint8_t link_id, struct bd_addr* bd_addr);
+/**
+ ****************************************************************************************
+ * @brief Register connection handle for a BT ACL connection
+ *
+ * @param[in] link_id BT ACL connection link ID
+ *****************************************************************************************
+ */
+void hci_bt_acl_conhdl_register(uint8_t link_id);
+
+/**
+ ****************************************************************************************
+ * @brief Unregister a BT ACL connection
+ *
+ * @param[in] link_id BT ACL connection link ID
+ *****************************************************************************************
+ */
+void hci_bt_acl_bdaddr_unregister(uint8_t link_id);
+
+#endif //(BT_EMB_PRESENT)
+
+/**
+ ****************************************************************************************
+ * @brief Set the event mask
+ *
+ * @param[in] evt_msk Pointer to the new event mask
+ * @param[in] page indicate which event page should be changed
+ *
+ * @return The status of the event mask saving
+ *****************************************************************************************
+ */
+uint8_t hci_evt_mask_set(struct evt_mask const *evt_msk, uint8_t page);
+
+#if (BT_EMB_PRESENT)
+/**
+ ****************************************************************************************
+ * @brief Add an event filter according to the parameters of the HCI command
+ *
+ * Note: the consistency of the parameters according to the input has already been checked by HCI during the special
+ * unpacking.
+ *
+ * @param[in] param Pointer to the HCI parameter
+ *
+ * @return The status of the filter addition
+ *****************************************************************************************
+ */
+uint8_t hci_evt_filter_add(struct hci_set_evt_filter_cmd const *param);
+
+#if (MAX_NB_SYNC > 0)
+/**
+ ****************************************************************************************
+ * @brief Get voice setting (for SCO auto-accept via event filter)
+ *
+ * @return Voice settings
+ *****************************************************************************************
+ */
+uint16_t hci_voice_settings_get(void);
+
+/**
+ ****************************************************************************************
+ * @brief Set voice setting (for SCO auto-accept via event filter)
+ *
+ * @param[in] voice_settings Voice settings
+ *
+ * @return Status (0: Success | Others: failure)
+ *****************************************************************************************
+ */
+uint8_t hci_voice_settings_set(uint16_t voice_settings);
+#endif // (MAX_NB_SYNC > 0)
+#endif //(BT_EMB_PRESENT)
+
+#if (HCI_TL_SUPPORT)
+#if (BLE_EMB_PRESENT || BT_EMB_PRESENT)
+/**
+ ****************************************************************************************
+ * @brief Get the maximum parameter size for a specific command
+ *
+ * This function is used by TL to know the theoretical maximum parameters size for a
+ * specific HCI command.
+ * Note: if the command is not supported by HCI (unknown), the maximum possible value of
+ * 255 bytes is returned.
+ *
+ * @param[in] opcode Opcode received
+ *
+ * @return The command maximum parameters size / 255 if command is unknown
+ *****************************************************************************************
+ */
+uint8_t hci_cmd_get_max_param_size(uint16_t opcode);
+
+/**
+ ****************************************************************************************
+ * @brief Indicates that a HCI command has been received
+ *
+ * This function is used by TL to indicate the reception of a HCI command.
+ *
+ * @param[in] opcode Command Opcode
+ * @param[in] length Parameters length
+ * @param[in] payload Pointer to payload
+ *****************************************************************************************
+ */
+void hci_cmd_received(uint16_t opcode, uint8_t length, uint8_t *payload);
+
+/**
+ ****************************************************************************************
+ * @brief Allocates the reception buffer for ACL TX data
+ *
+ * @param[in] hdl_flags Connection handle and data flags from HCI ACL packet header
+ * @param[in] len Length to receive (from HCI ACL packet header)
+ *
+ * @return Buffer for data reception (NULL if not possible to allocate one)
+ *****************************************************************************************
+ */
+uint8_t* hci_acl_tx_data_alloc(uint16_t hdl_flags, uint16_t len);
+
+/**
+ ****************************************************************************************
+ * @brief Indicates that a HCI ACL TX data packet has been received
+ *
+ * This function is used by TL to indicate the reception of a HCI ACL TX data.
+ *
+ * @param[in] hdl_flags Connection handle and data flags from HCI ACL packet header
+ * @param[out] datalen Data length
+ * @param[in] payload Pointer to payload
+ *****************************************************************************************
+ */
+void hci_acl_tx_data_received(uint16_t hdl_flags, uint16_t datalen, uint8_t * payload);
+
+#if (BT_EMB_PRESENT)
+#if (VOICE_OVER_HCI)
+/**
+ ****************************************************************************************
+ * @brief Allocates the reception buffer for Sync TX data
+ *
+ * @param[in] conhdl_flags Connection handle and data flags from HCI Sync packet header
+ * @param[in] len Length to receive (from HCI Sync packet header)
+ *
+ * @return Buffer for data reception (NULL if not possible to allocate one)
+ *****************************************************************************************
+ */
+uint8_t* hci_sync_tx_data_alloc(uint16_t conhdl_flags, uint8_t len);
+
+/**
+ ****************************************************************************************
+ * @brief Indicates that a HCI Sync TX data packet has been received
+ *
+ * This function is used by TL to indicate the reception of a HCI Sync TX data.
+ *
+ * @param[in] conhdl_flags Connection handle and data flags from HCI Sync packet header
+ * @param[in] len Length to receive (from HCI Sync packet header)
+ * @param[in] payload Pointer to payload
+ *****************************************************************************************
+ */
+void hci_sync_tx_data_received(uint16_t conhdl_flags, uint8_t len, uint8_t * payload);
+#endif // (VOICE_OVER_HCI)
+#endif // (BT_EMB_PRESENT)
+#endif // (BLE_EMB_PRESENT || BT_EMB_PRESENT)
+
+#if ((BLE_HOST_PRESENT) && (!BLE_EMB_PRESENT))
+/**
+ ****************************************************************************************
+ * @brief Allocates the reception buffer for ACL RX data
+ *
+ * @param[in] hdl_flags Connection handle and data flags from HCI ACL RX packet header
+ * @param[in] len Length to receive (from HCI ACL packet header)
+ *
+ * @return Buffer for data reception (NULL if not possible to allocate one)
+ *****************************************************************************************
+ */
+uint8_t* hci_acl_rx_data_alloc(uint16_t hdl_flags, uint16_t len);
+
+/**
+ ****************************************************************************************
+ * @brief Indicates that a HCI ACL RX data packet has been received
+ *
+ * This function is used by TL to indicate the reception of a HCI ACL RX data.
+ *
+ * @param[in] hdl_flags Connection handle and data flags from HCI ACL packet header
+ * @param[out] datalen Data length
+ * @param[in] payload Pointer to payload
+ *****************************************************************************************
+ */
+void hci_acl_rx_data_received(uint16_t hdl_flags, uint16_t datalen, uint8_t * payload);
+
+/**
+ ****************************************************************************************
+ * @brief Indicates that a HCI event has been received
+ *
+ * This function is used by TL to indicate the reception of a HCI event.
+ *
+ * @param[in] code Event code
+ * @param[in] length Parameters length
+ * @param[in] payload Pointer to payload
+ *
+ * @return status of receive operation
+ *****************************************************************************************
+ */
+uint8_t hci_evt_received(uint8_t code, uint8_t length, uint8_t *payload);
+#endif // ((BLE_HOST_PRESENT) && (!BLE_EMB_PRESENT))
+#endif // HCI_TL_SUPPORT
+
+//common for both BLE & BT
+/**
+ ****************************************************************************************
+ * @brief process HostBufferSize
+ *
+ * @param[in] acl_pkt_len ACL packet length
+ * @param[in] nb_acl_pkts Number of ACL packets
+ *
+ * @return status
+ *****************************************************************************************
+ */
+uint8_t hci_fc_acl_buf_size_set(uint16_t acl_pkt_len, uint16_t nb_acl_pkts);
+/**
+ ****************************************************************************************
+ * @brief process HostBufferSize
+ *
+ * @param[in] sync_pkt_len SYNC packet length
+ * @param[in] nb_sync_pkts Number of SYNC packets
+ *
+ * @return status
+ *****************************************************************************************
+ */
+uint8_t hci_fc_sync_buf_size_set(uint8_t sync_pkt_len, uint16_t nb_sync_pkts);
+
+/**
+ ****************************************************************************************
+ * @brief set the state of the ACL flow control
+ *
+ * @param[in] flow_enable boolean state of control
+ *
+ * @return status
+ *****************************************************************************************
+ */
+uint8_t hci_fc_acl_en(bool flow_enable);
+
+/**
+ ****************************************************************************************
+ * @brief set the state of the SYNC flow control
+ *
+ * @param[in] flow_enable boolean state of control
+ *****************************************************************************************
+ */
+void hci_fc_sync_en(bool flow_enable);
+
+/**
+ ****************************************************************************************
+ * @brief update data packet counters according to HostNumberOfCompletePackets
+ *
+ * @param[in] acl_pkt_nb accumulated number for ACL handles
+ ***************************************************************************************a**
+ */
+void hci_fc_host_nb_acl_pkts_complete(uint16_t acl_pkt_nb);
+
+/**
+ ****************************************************************************************
+ * @brief update data packet counters according to HostNumberOfCompletePackets
+ *
+ * @param[in] sync_pkt_nb accumulated number for SCO handles
+ ***************************************************************************************a**
+ */
+void hci_fc_host_nb_sync_pkts_complete(uint16_t sync_pkt_nb);
+
+#endif //HCI_PRESENT
+
+/// @} HCI
+
+#endif // HCI_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/hci_int.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/hci_int.h
new file mode 100644
index 0000000000..df09b6b9a0
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/hci_int.h
@@ -0,0 +1,494 @@
+/**
+ ****************************************************************************************
+ *
+ * @file hci.h
+ *
+ * @brief This file contains definitions related to the HCI module.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef HCI_INT_H_
+#define HCI_INT_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup HCI Host Controller Interface
+ *@{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+
+#include "rwip_config.h" // SW configuration
+
+#if (HCI_PRESENT)
+
+#include // standard definition
+#include // standard integer
+#include "co_bt.h" // BT standard definitions
+
+#include "ke_msg.h" // Kernel message definitions
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/// Macro to get OCF of a known command
+#define OCF(cmd) (HCI_OP2OCF(HCI_##cmd##_CMD_OPCODE))
+
+/// Unknown opcode identifier
+#define HCI_OPCODE_UNKNOWN 0xFFFF
+
+/**
+ * Destination field decoding
+ *
+ * bit | 7 6 | 5 4 | 3..0 |
+ * def | Rsvd (pkupk) | HL | LL |
+ */
+#define HCI_CMD_DEST_LL_POS 0
+#define HCI_CMD_DEST_LL_MASK 0x0F
+#define HCI_CMD_DEST_HL_POS 4
+#define HCI_CMD_DEST_HL_MASK 0x30
+
+/**
+ * Destination field decoding
+ *
+ * bit | 7..2 | 1 0 |
+ * def | Rsvd | HL |
+ */
+#define HCI_EVT_DEST_HL_POS 0
+#define HCI_EVT_DEST_HL_MASK 0x03
+
+#if (HCI_TL_SUPPORT)
+
+/// Special Pack-Unpack settings for HCI commands (parameters and return parameters)
+/**
+ * Special Pack-Unpack settings for HCI commands (parameters and return parameters)
+ *
+ * bit | 7 | 6 | 5..0 |
+ * def | RET PAR | PAR | Rsvd |
+ */
+#define HCI_CMD_DEST_SPEC_PAR_PK_POS 6
+#define HCI_CMD_DEST_SPEC_PAR_PK_MSK 0x40
+#define HCI_CMD_DEST_SPEC_RET_PAR_PK_POS 7
+#define HCI_CMD_DEST_SPEC_RET_PAR_PK_MSK 0x80
+#define PK_GEN_GEN (0x00)
+#define PK_GEN_SPE (HCI_CMD_DEST_SPEC_RET_PAR_PK_MSK)
+#define PK_SPE_GEN (HCI_CMD_DEST_SPEC_PAR_PK_MSK)
+#define PK_SPE_SPE (HCI_CMD_DEST_SPEC_RET_PAR_PK_MSK | HCI_CMD_DEST_SPEC_PAR_PK_MSK)
+
+/// Special Pack settings for HCI events
+#define PK_GEN 0x00
+#define PK_SPE 0x01
+
+/// Macro for building a command descriptor in split mode (with parameters packing/unpacking)
+#define CMD(opcode, dest_ll, dest_hl, pkupk, par_size_max, par_fmt, ret_fmt) {HCI_##opcode##_CMD_OPCODE, (dest_ll< 0)
+ /**
+ * Voice settings used when SCO connection is auto-accepted
+ */
+ uint16_t voice_settings;
+ #endif //(MAX_NB_SYNC > 0)
+
+ /**
+ * Auto-reject flag, used to filter the complete event when a request has been auto-rejected
+ */
+ bool auto_reject;
+
+ #elif (BLE_HOST_PRESENT && !BLE_EMB_PRESENT && (BLE_CENTRAL || BLE_PERIPHERAL))
+ /// Link association table for BLE link-oriented messages routing
+ struct hci_ble_acl_con_tag ble_acl_con_tab[BLE_CONNECTION_MAX];
+
+ #endif //(BT_EMB_PRESENT || (BLE_HOST_PRESENT && !BLE_EMB_PRESENT))
+};
+
+/*
+ * GLOBAL VARIABLE DECLARATIONS
+ ****************************************************************************************
+ */
+
+#if BLE_HOST_PRESENT
+extern const uint8_t hl_task_type[];
+#endif //BLE_HOST_PRESENT
+
+///HCI environment context
+extern struct hci_env_tag hci_env;
+
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+/**
+****************************************************************************************
+* @brief Look for a command descriptor that could match with the specified opcode
+*
+* @param[in] opcode Command opcode
+*
+* @return Pointer the command descriptor (NULL if not found)
+*****************************************************************************************
+*/
+const struct hci_cmd_desc_tag* hci_look_for_cmd_desc(uint16_t opcode);
+
+/**
+****************************************************************************************
+* @brief Look for an event descriptor that could match with the specified event code
+*
+* @param[in] code event code
+*
+* @return Pointer the event descriptor (NULL if not found)
+*****************************************************************************************
+*/
+const struct hci_evt_desc_tag* hci_look_for_evt_desc(uint8_t code);
+
+
+/**
+****************************************************************************************
+* @brief Look for an event descriptor that could match with the specified DBG subcode
+*
+* @param[in] subcode DBG event subcode
+*
+* @return Pointer the event descriptor (NULL if not found)
+*****************************************************************************************
+*/
+const struct hci_evt_desc_tag* hci_look_for_dbg_evt_desc(uint8_t subcode);
+
+#if (BLE_EMB_PRESENT || BLE_HOST_PRESENT)
+/**
+****************************************************************************************
+* @brief Look for an event descriptor that could match with the specified LE subcode
+*
+* @param[in] subcode LE event subcode
+*
+* @return Pointer the event descriptor (NULL if not found)
+*****************************************************************************************
+*/
+const struct hci_evt_desc_tag* hci_look_for_le_evt_desc(uint8_t subcode);
+
+#endif //(BLE_EMB_PRESENT || BLE_HOST_PRESENT)
+
+#if (HCI_TL_SUPPORT)
+/**
+ ****************************************************************************************
+ * @brief Initialize HIC TL part
+ *****************************************************************************************
+ */
+void hci_tl_init(bool reset);
+
+/**
+ ****************************************************************************************
+ * @brief Send an HCI message over TL
+ *
+ * @param[in] msg Kernel message carrying the HCI message
+ *****************************************************************************************
+ */
+void hci_tl_send(struct ke_msg *msg);
+
+/**
+ ****************************************************************************************
+ * @brief Pack parameters
+ *
+ * This function packs parameters according to a specific format. It takes care of the
+ * endianess, padding, required by the compiler.
+ *
+ * @param[inout] inout Data Buffer
+ * @param[inout] inout_len Input: buffer size / Output: size of packed data
+ * @param[in] format Parameters format
+ *
+ * @return Status of the packing operation
+ *****************************************************************************************
+ */
+enum HCI_PACK_STATUS hci_util_pack(uint8_t* inout, uint16_t* inout_len, const char* format);
+
+/**
+ ****************************************************************************************
+ * @brief Unpack parameters
+ *
+ * This function unpacks parameters according to a specific format. It takes care of the
+ * endianess, padding, required by the compiler.
+ *
+ * Note: the buffer provided must be large enough to contain the unpacked data.
+ *
+ * @param[out] out Unpacked parameters buffer
+ * @param[in] in Packed parameters buffer
+ * @param[inout] out_len Input: buffer size / Output: size of unpacked data
+ * @param[in] in_len Size of the packed data
+ * @param[in] format Parameters format
+ *
+ * @return Status of the unpacking operation
+ *****************************************************************************************
+ */
+enum HCI_PACK_STATUS hci_util_unpack(uint8_t* out, uint8_t* in, uint16_t* out_len, uint16_t in_len, const char* format);
+#endif //(HCI_TL_SUPPORT)
+
+/**
+ ****************************************************************************************
+ * @brief Initialize Flow Control Structure
+ *
+ *****************************************************************************************
+ */
+void hci_fc_init(void);
+
+/**
+ ****************************************************************************************
+ * @brief count ACL packets sent to Host
+ *
+ *****************************************************************************************
+ */
+void hci_fc_acl_packet_sent(void);
+
+/**
+ ****************************************************************************************
+ * @brief count SCO packets sent to Host
+ *
+ *****************************************************************************************
+ */
+void hci_fc_sync_packet_sent(void);
+
+/**
+ ****************************************************************************************
+ * @brief Calculate number of ACL packets slots available on Host side
+ *
+ * @return number of packets available
+ *****************************************************************************************
+ */
+uint16_t hci_fc_check_host_available_nb_acl_packets(void);
+
+/**
+ ****************************************************************************************
+ * @brief Calculate number of SCO packets slots available on Host side
+ *
+ * @return number of packets available
+ *****************************************************************************************
+ */
+uint16_t hci_fc_check_host_available_nb_sync_packets(void);
+
+
+#endif //HCI_PRESENT
+
+/// @} HCI
+
+#endif // HCI_INT_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke.h
new file mode 100644
index 0000000000..5f6c115548
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke.h
@@ -0,0 +1,103 @@
+/**
+ ****************************************************************************************
+ *
+ * @file ke.h
+ *
+ * @brief This file contains the definition of the kernel environment.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef _KE_H_
+#define _KE_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup ENV Environment
+ * @ingroup KERNEL
+ * @brief Kernel Environment
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+
+#include "rwip_config.h" // stack configuration
+
+#include // standard boolean definitions
+#include // standard integer definitions
+
+/*
+ * ENUMERATION
+ ****************************************************************************************
+ */
+
+/// Kernel Error Status
+enum KE_STATUS
+{
+ KE_SUCCESS = 0,
+ KE_FAIL
+};
+
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief This function performs all the initializations of the kernel.
+ *
+ * It initializes first the heap, then the message queues and the events. Then if required
+ * it initializes the trace.
+ *
+ ****************************************************************************************
+ */
+void ke_init(void);
+
+/**
+ ****************************************************************************************
+ * @brief This function flushes all messages, timers and events currently pending in the
+ * kernel.
+ *
+ ****************************************************************************************
+ */
+void ke_flush(void);
+
+/**
+ ****************************************************************************************
+ * @brief This function checks if sleep is possible or kernel is processing
+ *
+ * @return True if sleep is allowed, false otherwise
+ ****************************************************************************************
+ */
+bool ke_sleep_check(void);
+
+#if (KE_PROFILING)
+/**
+ ****************************************************************************************
+ * @brief This function gets the statistics of the kernel usage.
+ *
+ * @param[out] max_msg_sent Max message sent
+ * @param[out] max_msg_saved Max message saved
+ * @param[out] max_timer_used Max timer used
+ * @param[out] max_heap_used Max heap used
+ ****************************************************************************************
+ */
+enum KE_STATUS ke_stats_get(uint8_t* max_msg_sent,
+ uint8_t* max_msg_saved,
+ uint8_t* max_timer_used,
+ uint16_t* max_heap_used);
+#endif //KE_PROFILING
+
+/// @} KE
+
+#endif // _KE_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_config.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_config.h
new file mode 100644
index 0000000000..8f0e0f0675
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_config.h
@@ -0,0 +1,60 @@
+/**
+ ****************************************************************************************
+ *
+ * @file ke_config.h
+ *
+ * @brief This file contains all the constant that can be changed in order to
+ * tailor the kernel.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef _KE_CONFIG_H_
+#define _KE_CONFIG_H_
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "rwip_config.h" // stack configuration
+
+/**
+ ****************************************************************************************
+ * @addtogroup KERNEL KERNEL
+ * @ingroup ROOT
+ * @brief The Kernel module.
+ *
+ * The Kernel is responsible for providing essential OS features like time management,
+ * inter-task communication, task management and message handling and administration.
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @addtogroup CFG Settings and Configuration
+ * @ingroup KERNEL
+ * @brief Kernel Configuration
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * CONSTANT DEFINITIONS
+ ****************************************************************************************
+ */
+#define KE_MEM_RW 1
+#define KE_MEM_LINUX 0
+#define KE_MEM_LIBC 0
+
+#define KE_FULL 1
+#define KE_SEND_ONLY 0
+
+/// @} CFG
+
+#endif // _KE_CONFIG_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_env.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_env.h
new file mode 100644
index 0000000000..c09c4cb4da
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_env.h
@@ -0,0 +1,69 @@
+/**
+ ****************************************************************************************
+ *
+ * @file ke_env.h
+ *
+ * @brief This file contains the definition of the kernel.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef _KE_ENV_H_
+#define _KE_ENV_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup ENV Environment
+ * @ingroup KERNEL
+ * @brief Kernel Environment
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "rwip_config.h" // stack configuration
+#include "ke_config.h" // kernel configuration
+#include "ke_event.h" // kernel event
+#include "co_list.h" // kernel queue definition
+
+// forward declaration
+struct mblock_free;
+
+/// Kernel environment definition
+struct ke_env_tag
+{
+ /// Queue of sent messages but not yet delivered to receiver
+ struct co_list queue_sent;
+ /// Queue of messages delivered but not consumed by receiver
+ struct co_list queue_saved;
+ /// Queue of timers
+ struct co_list queue_timer;
+
+ #if (KE_MEM_RW)
+ /// Root pointer = pointer to first element of heap linked lists
+ struct mblock_free * heap[KE_MEM_BLOCK_MAX];
+ /// Size of heaps
+ uint16_t heap_size[KE_MEM_BLOCK_MAX];
+
+ #if (KE_PROFILING)
+ /// Size of heap used
+ uint16_t heap_used[KE_MEM_BLOCK_MAX];
+ /// Maximum heap memory used
+ uint32_t max_heap_used;
+ #endif //KE_PROFILING
+ #endif //KE_MEM_RW
+};
+
+/// Kernel environment
+extern struct ke_env_tag ke_env;
+
+/// @} ENV
+
+#endif // _KE_ENV_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_event.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_event.h
new file mode 100644
index 0000000000..dca64f3e6b
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_event.h
@@ -0,0 +1,152 @@
+/**
+ ****************************************************************************************
+ *
+ * @file ke_event.h
+ *
+ * @brief This file contains the definition related to kernel events.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef _KE_EVENT_H_
+#define _KE_EVENT_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup EVT Events and Schedule
+ * @ingroup KERNEL
+ * @brief Event scheduling module.
+ *
+ * The KE_EVT module implements event scheduling functions. It can be used to
+ * implement deferred actions.
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+
+#include "rwip_config.h" // stack configuration
+
+#include // standard integer definition
+
+
+/*
+ * CONSTANTS
+ ****************************************************************************************
+ */
+
+
+/// Status of ke_task API functions
+enum KE_EVENT_STATUS
+{
+ KE_EVENT_OK = 0,
+ KE_EVENT_FAIL,
+ KE_EVENT_UNKNOWN,
+ KE_EVENT_CAPA_EXCEEDED,
+ KE_EVENT_ALREADY_EXISTS,
+};
+
+
+/*
+ * TYPE DEFINITION
+ ****************************************************************************************
+ */
+
+
+
+
+/*
+ * FUNCTION PROTOTYPES
+ ****************************************************************************************
+ */
+
+
+
+/**
+ ****************************************************************************************
+ * @brief Initialize Kernel event module.
+ ****************************************************************************************
+ */
+void ke_event_init(void);
+
+/**
+ ****************************************************************************************
+ * @brief Register an event callback.
+ *
+ * @param[in] event_type Event type.
+ * @param[in] p_callback Pointer to callback function.
+ *
+ * @return Status
+ ****************************************************************************************
+ */
+uint8_t ke_event_callback_set(uint8_t event_type, void (*p_callback)(void));
+
+/**
+ ****************************************************************************************
+ * @brief Set an event
+ *
+ * This primitive sets one event. It will trigger the call to the corresponding event
+ * handler in the next scheduling call.
+ *
+ * @param[in] event_type Event to be set.
+ ****************************************************************************************
+ */
+void ke_event_set(uint8_t event_type);
+
+/**
+ ****************************************************************************************
+ * @brief Clear an event
+ *
+ * @param[in] event_type Event to be cleared.
+ ****************************************************************************************
+ */
+void ke_event_clear(uint8_t event_type);
+
+/**
+ ****************************************************************************************
+ * @brief Get the status of an event
+ *
+ * @param[in] event_type Event to get.
+ *
+ * @return Event status (0: not set / 1: set)
+ ****************************************************************************************
+ */
+uint8_t ke_event_get(uint8_t event_type);
+
+/**
+ ****************************************************************************************
+ * @brief Get all event status
+ *
+ * @return Events bit field
+ ****************************************************************************************
+ */
+uint32_t ke_event_get_all(void);
+
+/**
+ ****************************************************************************************
+ * @brief Flush all pending events.
+ ****************************************************************************************
+ */
+void ke_event_flush(void);
+
+/**
+ ****************************************************************************************
+ * @brief Event scheduler entry point.
+ *
+ * This primitive is the entry point of Kernel event scheduling.
+ ****************************************************************************************
+ */
+void ke_event_schedule(void);
+
+
+
+/// @} EVT
+
+#endif //_KE_EVENT_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_mem.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_mem.h
new file mode 100644
index 0000000000..e8f42f3406
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_mem.h
@@ -0,0 +1,185 @@
+/**
+ ****************************************************************************************
+ *
+ * @file ke_mem.h
+ *
+ * @brief API for the heap management module.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef _KE_MEM_H_
+#define _KE_MEM_H_
+
+#include "rwip_config.h" // IP configuration
+#include // standard integer
+#include // standard includes
+#include "ke_config.h" // kernel configuration
+
+/**
+ ****************************************************************************************
+ * @defgroup MEM Memory
+ * @ingroup KERNEL
+ * @brief Heap management module.
+ *
+ * This module implements heap management functions that allow initializing heap,
+ * allocating and freeing memory.
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+#if (KE_MEM_RW)
+
+
+// forward declarations
+struct mblock_free;
+
+/**
+ ****************************************************************************************
+ * @brief Heap initialization.
+ *
+ * This function performs the following operations:
+ * - sanity checks
+ * - check memory allocated is at least large enough to hold two block descriptors to hold
+ * start and end
+ * - initialize the first and last descriptors
+ * - save heap into kernel environment variable.
+ *
+ * @param[in] type Memory type.
+ * @param[in|out] heap Heap pointer
+ * @param[in] heap_size Size of the heap
+ *
+ *
+ ****************************************************************************************
+ */
+void ke_mem_init(uint8_t type, uint8_t* heap, uint16_t heap_size);
+
+/**
+ ****************************************************************************************
+ * @brief Allocation of a block of memory.
+ *
+ * Allocates a memory block whose size is size; if no memory is available return NULL
+ *
+ * @param[in] size Size of the memory area that need to be allocated.
+ * @param[in] type Type of memory block
+ *
+ * @return A pointer to the allocated memory area.
+ *
+ ****************************************************************************************
+ */
+void *ke_malloc(uint32_t size, uint8_t type);
+
+
+/**
+ ****************************************************************************************
+ * @brief Check if it's possible to allocate a block of memory with a specific size.
+ *
+ * @param[in] size Size of the memory area that need to be allocated.
+ * @param[in] type Type of memory block
+ *
+ * @return True if memory block can be allocated, False else.
+ *
+ ****************************************************************************************
+ */
+bool ke_check_malloc(uint32_t size, uint8_t type);
+
+/**
+ ****************************************************************************************
+ * @brief Freeing of a block of memory.
+ *
+ * Free the memory area pointed by mem_ptr : mark the block as free and insert it in
+ * the pool of free block.
+ *
+ * @param[in] mem_ptr Pointer to the memory area that need to be freed.
+ *
+ ****************************************************************************************
+ */
+void ke_free(void *mem_ptr);
+
+
+/**
+ ****************************************************************************************
+ * @brief Check if current heap is empty or not (not used)
+ *
+ * @param[in] type Type of memory heap block
+ *
+ * @return true if heap not used, false else.
+ ****************************************************************************************
+ */
+bool ke_mem_is_empty(uint8_t type);
+
+
+
+/**
+ ****************************************************************************************
+ * @brief Check if current pointer is free or not
+ *
+ * @param[in] mem_ptr pointer to a memory block
+ *
+ * @return true if already free, false else.
+ ****************************************************************************************
+ */
+bool ke_is_free(void* mem_ptr);
+
+#if (KE_PROFILING)
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve memory usage of selected heap.
+ *
+ * @param[in] type Type of memory heap block
+ *
+ * @return current memory usage of current heap.
+ ****************************************************************************************
+ */
+uint16_t ke_get_mem_usage(uint8_t type);
+
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve max memory usage of all heap.
+ * This command also resets max measured value.
+ *
+ * @return max memory usage of all heap.
+ ****************************************************************************************
+ */
+uint32_t ke_get_max_mem_usage(void);
+
+#endif // (KE_PROFILING)
+
+
+
+
+#elif (KE_MEM_LINUX)
+// Wrappers to Linux mem functions here
+
+#include
+
+__INLINE void *ke_malloc(uint32_t size)
+{
+ return kmalloc(size, GFP_KERNEL);
+}
+
+__INLINE void ke_free (void * mem_ptr)
+{
+ kfree(mem_ptr);
+}
+
+#elif (KE_MEM_LIBC)
+// Wrapper to lib C mem functions here
+#include
+
+__INLINE void *ke_malloc(uint32_t size) { return malloc(size); }
+
+__INLINE void ke_free(void * mem_ptr) { free(mem_ptr); }
+
+#endif // KE_MEM_RW
+
+///@} MEM
+
+#endif // _KE_MEM_H_
+
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_msg.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_msg.h
new file mode 100644
index 0000000000..37e03cdfe9
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_msg.h
@@ -0,0 +1,320 @@
+/**
+ ****************************************************************************************
+ *
+ * @file ke_msg.h
+ *
+ * @brief This file contains the definition related to message scheduling.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef _KE_MSG_H_
+#define _KE_MSG_H_
+
+/**
+ ****************************************************************************************
+ * @defgroup MSG Message Exchange
+ * @ingroup KERNEL
+ * @brief Message scheduling module.
+ *
+ * The MSG module implements message scheduling functions.
+
+ * A kernel message has an ID, a receiver task ID and a source task ID.
+ * In most cases, it also has parameters which are defined in
+ * a structure dynamically embedded in the message structure,
+ * so the whole message will be managed internally as one block.
+ *
+ * A message can also have one extra parameter which is referenced
+ * in the normal parameter structure. This extra block is assumed
+ * to be large by the kernel and will be moved by DMA if needed.
+ * This feature allows moving MMPDU from LMAC to UMAC.
+ *
+ * In order to send a message, a function first have to allocate
+ * the memory for this message. It can be done with the wrapper
+ * macro KE_MSG_ALLOC() (which will call ke_msg_alloc()).
+
+ * The message can then be sent with ke_msg_send(). The kernel
+ * will take care of freeing the allocated memory.
+
+ * If the message has no parameters, the ke_msg_send_basic() function
+ * can be used.
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+#include // standard definition
+#include // standard integer
+#include // standard boolean
+#include "ble_arch.h" // architectural definition
+//#include "compiler.h" // compiler definition
+#include "ke_config.h" // kernel configuration
+#include "co_list.h" // list definition
+
+
+/// Task Identifier. Composed by the task type and the task index.
+typedef uint16_t ke_task_id_t;
+
+/// Builds the task identifier from the type and the index of that task.
+#define KE_BUILD_ID(type, index) ( (ke_task_id_t)(((index) << 8)|(type)) )
+
+/// Retrieves task type from task id.
+#define KE_TYPE_GET(ke_task_id) ((ke_task_id) & 0xFF)
+
+/// Retrieves task index number from task id.
+#define KE_IDX_GET(ke_task_id) (((ke_task_id) >> 8) & 0xFF)
+
+/// Task State
+typedef uint8_t ke_state_t;
+
+/// Message Identifier. The number of messages is limited to 0xFFFF.
+/// The message ID is divided in two parts:
+/// bits[15~8]: task index (no more than 255 tasks support)
+/// bits[7~0]: message index(no more than 255 messages per task)
+typedef uint16_t ke_msg_id_t;
+
+/// Message structure.
+struct ke_msg
+{
+ struct co_list_hdr hdr; ///< List header for chaining
+
+ ke_msg_id_t id; ///< Message id.
+ ke_task_id_t dest_id; ///< Destination kernel identifier.
+ ke_task_id_t src_id; ///< Source kernel identifier.
+ uint16_t param_len; ///< Parameter embedded struct length.
+ uint32_t param[1]; ///< Parameter embedded struct. Must be word-aligned.
+};
+
+
+/// Status returned by a task when handling a message
+enum ke_msg_status_tag
+{
+ KE_MSG_CONSUMED = 0, ///< consumed, msg and ext are freed by the kernel
+ KE_MSG_NO_FREE, ///< consumed, nothing is freed by the kernel
+ KE_MSG_SAVED, ///< not consumed, will be pushed in the saved queue
+};
+
+/**
+ ****************************************************************************************
+ * @brief Convert a parameter pointer to a message pointer
+ *
+ * @param[in] param_ptr Pointer to the parameter member of a ke_msg
+ * Usually retrieved by a ke_msg_alloc()
+ *
+ * @return The pointer to the ke_msg
+ ****************************************************************************************
+ */
+__INLINE struct ke_msg * ke_param2msg(void const *param_ptr)
+{
+ return (struct ke_msg*) (((uint8_t*)param_ptr) - offsetof(struct ke_msg, param));
+}
+
+/**
+ ****************************************************************************************
+ * @brief Convert a message pointer to a parameter pointer
+ *
+ * @param[in] msg Pointer to the ke_msg.
+ *
+ * @return The pointer to the param member
+ ****************************************************************************************
+ */
+__INLINE void * ke_msg2param(struct ke_msg const *msg)
+{
+ return (void*) (((uint8_t*) msg) + offsetof(struct ke_msg, param));
+}
+
+/**
+ ****************************************************************************************
+ * @brief Convenient wrapper to ke_msg_alloc()
+ *
+ * This macro calls ke_msg_alloc() and cast the returned pointer to the
+ * appropriate structure. Can only be used if a parameter structure exists
+ * for this message (otherwise, use ke_msg_send_basic()).
+ *
+ * @param[in] id Message identifier
+ * @param[in] dest Destination Identifier
+ * @param[in] src Source Identifier
+ * @param[in] param_str parameter structure tag
+ *
+ * @return Pointer to the parameter member of the ke_msg.
+ ****************************************************************************************
+ */
+#define KE_MSG_ALLOC(id, dest, src, param_str) \
+ (struct param_str*) ke_msg_alloc(id, dest, src, sizeof(struct param_str))
+
+/**
+ ****************************************************************************************
+ * @brief Convenient wrapper to ke_msg_free()
+ *
+ * This macro calls ke_msg_free() with the appropriate msg pointer as parameter, according
+ * to the message parameter pointer passed.
+ *
+ * @param[in] param_ptr parameter structure pointer
+ ****************************************************************************************
+ */
+#define KE_MSG_FREE(param_ptr) ke_msg_free(ke_param2msg((param_ptr)))
+
+/**
+ ****************************************************************************************
+ * @brief Convenient wrapper to ke_msg_alloc()
+ *
+ * This macro calls ke_msg_alloc() and cast the returned pointer to the
+ * appropriate structure with a variable length. Can only be used if a parameter structure exists
+ * for this message (otherwise, use ke_msg_send_basic()).Can only be used if the data array is
+ * located at the end of the structure.
+ *
+ * @param[in] id Message identifier
+ * @param[in] dest Destination Identifier
+ * @param[in] src Source Identifier
+ * @param[in] param_str parameter structure tag
+ * @param[in] length length for the data
+ *
+ * @return Pointer to the parameter member of the ke_msg.
+ ****************************************************************************************
+ */
+#define KE_MSG_ALLOC_DYN(id, dest, src, param_str,length) (struct param_str*)ke_msg_alloc(id, dest, src, \
+ (sizeof(struct param_str) + (length)));
+
+/**
+ ****************************************************************************************
+ * @brief Allocate memory for a message
+ *
+ * This primitive allocates memory for a message that has to be sent. The memory
+ * is allocated dynamically on the heap and the length of the variable parameter
+ * structure has to be provided in order to allocate the correct size.
+ *
+ * Several additional parameters are provided which will be preset in the message
+ * and which may be used internally to choose the kind of memory to allocate.
+ *
+ * The memory allocated will be automatically freed by the kernel, after the
+ * pointer has been sent to ke_msg_send(). If the message is not sent, it must
+ * be freed explicitly with ke_msg_free().
+ *
+ * Allocation failure is considered critical and should not happen.
+ *
+ * @param[in] id Message identifier
+ * @param[in] dest_id Destination Task Identifier
+ * @param[in] src_id Source Task Identifier
+ * @param[in] param_len Size of the message parameters to be allocated
+ *
+ * @return Pointer to the parameter member of the ke_msg. If the parameter
+ * structure is empty, the pointer will point to the end of the message
+ * and should not be used (except to retrieve the message pointer or to
+ * send the message)
+ ****************************************************************************************
+ */
+void *ke_msg_alloc(ke_msg_id_t const id, ke_task_id_t const dest_id,
+ ke_task_id_t const src_id, uint16_t const param_len);
+
+/**
+ ****************************************************************************************
+ * @brief Message sending.
+ *
+ * Send a message previously allocated with any ke_msg_alloc()-like functions.
+ *
+ * The kernel will take care of freeing the message memory.
+ *
+ * Once the function have been called, it is not possible to access its data
+ * anymore as the kernel may have copied the message and freed the original
+ * memory.
+ *
+ * @param[in] param_ptr Pointer to the parameter member of the message that
+ * should be sent.
+ ****************************************************************************************
+ */
+
+void ke_msg_send(void const *param_ptr);
+
+/**
+ ****************************************************************************************
+ * @brief Basic message sending.
+ *
+ * Send a message that has a zero length parameter member. No allocation is
+ * required as it will be done internally.
+ *
+ * @param[in] id Message identifier
+ * @param[in] dest_id Destination Identifier
+ * @param[in] src_id Source Identifier
+ ****************************************************************************************
+ */
+void ke_msg_send_basic(ke_msg_id_t const id, ke_task_id_t const dest_id, ke_task_id_t const src_id);
+
+/**
+ ****************************************************************************************
+ * @brief Message forwarding.
+ *
+ * Forward a message to another task by changing its destination and source tasks IDs.
+ *
+ * @param[in] param_ptr Pointer to the parameter member of the message that
+ * should be sent.
+ * @param[in] dest_id New destination task of the message.
+ * @param[in] src_id New source task of the message.
+ ****************************************************************************************
+ */
+void ke_msg_forward(void const *param_ptr, ke_task_id_t const dest_id, ke_task_id_t const src_id);
+
+/**
+ ****************************************************************************************
+ * @brief Message forwarding.
+ *
+ * Forward a message to another task by changing its message ID and its destination and source tasks IDs.
+ *
+ * @param[in] param_ptr Pointer to the parameter member of the message that
+ * should be sent.
+ * @param[in] msg_id New ID of the message.
+ * @param[in] dest_id New destination task of the message.
+ * @param[in] src_id New source task of the message.
+ ****************************************************************************************
+ */
+void ke_msg_forward_new_id(void const *param_ptr,
+ ke_msg_id_t const msg_id, ke_task_id_t const dest_id, ke_task_id_t const src_id);
+
+/**
+ ****************************************************************************************
+ * @brief Free allocated message
+ *
+ * @param[in] msg Pointer to the message to be freed (not the parameter member!)
+ ****************************************************************************************
+ */
+void ke_msg_free(struct ke_msg const *param);
+
+
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve destination task identifier of a kernel message
+ *
+ * @param[in] param_ptr Pointer to the parameter member of the message.
+ *
+ * @return message destination task
+ ****************************************************************************************
+ */
+ke_msg_id_t ke_msg_dest_id_get(void const *param_ptr);
+
+
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve source task identifier of a kernel message
+ *
+ * @param[in] param_ptr Pointer to the parameter member of the message.
+ *
+ * @return message source task
+ ****************************************************************************************
+ */
+ke_msg_id_t ke_msg_src_id_get(void const *param_ptr);
+
+/**
+ * Used to know if message is present in kernel queue or not.
+ *
+ * @param[in] param_ptr Pointer to the parameter member of the message.
+ *
+ * @return True if message is present in Kernel Queue, False else.
+ */
+bool ke_msg_in_queue(void const *param_ptr);
+/// @} MSG
+
+#endif // _KE_MSG_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_queue.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_queue.h
new file mode 100644
index 0000000000..f2faa6f286
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_queue.h
@@ -0,0 +1,108 @@
+/**
+ ****************************************************************************************
+ *
+ * @file ke_queue.h
+ *
+ * @brief This file contains the definition of the message object, queue element
+ * object and queue object
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef _KE_QUEUE_H_
+#define _KE_QUEUE_H_
+//
+/**
+ ****************************************************************************************
+ * @addtogroup QUEUE Queues and Lists
+ * @ingroup KERNEL
+ * @brief Queue management module
+ *
+ * This module implements the functions used for managing message queues.
+ * These functions must not be called under IRQ!
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include // standard integer
+#include // standard boolean
+#include "ble_arch.h" // compiler definitions
+#include "ke_config.h" // kernel configuration
+#include "co_list.h" // list definition
+
+/*
+ * FUNCTION PROTOTYPES
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief Pop entry to the queue
+ *
+ * @param[in] queue Pointer to the queue.
+ * @param[in] element Pointer to the element.
+ ****************************************************************************************
+ */
+__INLINE void ke_queue_push(struct co_list *const queue, struct co_list_hdr *const element)
+{
+ co_list_push_back(queue, element);
+}
+
+/**
+ ****************************************************************************************
+ * @brief Pop entry from the queue
+ *
+ * @param[in] queue Pointer to the queue.
+ *
+ * @return Pointer to the element.
+ ****************************************************************************************
+ */
+__INLINE struct co_list_hdr *ke_queue_pop(struct co_list *const queue)
+{
+ return co_list_pop_front(queue);
+}
+
+/**
+ ****************************************************************************************
+ * @brief Extracts an element matching a given algorithm.
+ *
+ * @param[in] queue Pointer to the queue.
+ * @param[in] func Matching function.
+ * @param[in] arg Match argument.
+ *
+ * @return Pointer to the element found and removed (NULL otherwise).
+ ****************************************************************************************
+ */
+struct co_list_hdr *ke_queue_extract(struct co_list * const queue,
+ bool (*func)(struct co_list_hdr const * elmt, uint32_t arg),
+ uint32_t arg);
+
+/**
+ ****************************************************************************************
+ * @brief Insert an element in a sorted queue.
+ *
+ * This primitive use a comparison function from the parameter list to select where the
+ * element must be inserted.
+ *
+ * @param[in] queue Pointer to the queue.
+ * @param[in] element Pointer to the element to insert.
+ * @param[in] cmp Comparison function (return true if first element has to be inserted
+ * before the second one).
+ *
+ * @return Pointer to the element found and removed (NULL otherwise).
+ ****************************************************************************************
+ */
+void ke_queue_insert(struct co_list * const queue, struct co_list_hdr * const element,
+ bool (*cmp)(struct co_list_hdr const *elementA,
+ struct co_list_hdr const *elementB));
+
+/// @} QUEUE
+
+#endif // _KE_QUEUE_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_task.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_task.h
new file mode 100644
index 0000000000..eea99c2657
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_task.h
@@ -0,0 +1,236 @@
+/**
+ ****************************************************************************************
+ *
+ * @file ke_task.h
+ *
+ * @brief This file contains the definition related to kernel task management.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef _KE_TASK_H_
+#define _KE_TASK_H_
+
+/**
+ ****************************************************************************************
+ * @defgroup TASK Task and Process
+ * @ingroup KERNEL
+ * @brief Task management module.
+ *
+ * This module implements the functions used for managing tasks.
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include // standard integer
+#include // standard boolean
+
+#include "rwip_config.h" // stack configuration
+#include "ble_arch.h" // compiler defines, INLINE
+#include "ke_msg.h" // kernel message defines
+
+/* Default Message handler code to handle several message type in same handler. */
+#define KE_MSG_DEFAULT_HANDLER (0xFFFF)
+/* Invalid task */
+#define KE_TASK_INVALID (0xFFFF)
+/* Used to know if a message is not present in kernel queue */
+#define KE_MSG_NOT_IN_QUEUE ((struct co_list_hdr *) 0xFFFFFFFF)
+
+/// Status of ke_task API functions
+enum KE_TASK_STATUS
+{
+ KE_TASK_OK = 0,
+ KE_TASK_FAIL,
+ KE_TASK_UNKNOWN,
+ KE_TASK_CAPA_EXCEEDED,
+ KE_TASK_ALREADY_EXISTS,
+};
+
+
+#define MSG_T(msg) ((ke_task_id_t)((msg) >> 8))
+#define MSG_I(msg) ((msg) & ((1<<8)-1))
+
+/// Format of a task message handler function
+typedef int (*ke_msg_func_t)(ke_msg_id_t const msgid, void const *param,
+ ke_task_id_t const dest_id, ke_task_id_t const src_id);
+
+/// Macro for message handler function declaration or definition
+#define KE_MSG_HANDLER(msg_name, param_struct) __STATIC int msg_name##_handler(ke_msg_id_t const msgid, \
+ param_struct const *param, \
+ ke_task_id_t const dest_id, \
+ ke_task_id_t const src_id)
+
+/// Macro for message handlers table declaration or definition
+#define KE_MSG_HANDLER_TAB(task) __STATIC const struct ke_msg_handler task##_default_state[] =
+
+/// Macro for state handler declaration or definition
+#define KE_MSG_STATE(task) const struct ke_state_handler task##_default_handler = KE_STATE_HANDLER(task##_default_state);
+
+/// Element of a message handler table.
+struct ke_msg_handler
+{
+ /// Id of the handled message.
+ ke_msg_id_t id;
+ /// Pointer to the handler function for the msgid above.
+ ke_msg_func_t func;
+};
+
+/// Element of a state handler table.
+struct ke_state_handler
+{
+ /// Pointer to the message handler table of this state.
+ const struct ke_msg_handler *msg_table;
+ /// Number of messages handled in this state.
+ uint16_t msg_cnt;
+};
+
+/// Helps writing the initialization of the state handlers without errors.
+#define KE_STATE_HANDLER(hdl) {hdl, sizeof(hdl)/sizeof(struct ke_msg_handler)}
+
+/// Helps writing empty states.
+#define KE_STATE_HANDLER_NONE {NULL, 0}
+
+/// Task descriptor grouping all information required by the kernel for the scheduling.
+struct ke_task_desc
+{
+ /// Pointer to the state handler table (one element for each state).
+ const struct ke_state_handler* state_handler;
+ /// Pointer to the default state handler (element parsed after the current state).
+ const struct ke_state_handler* default_handler;
+ /// Pointer to the state table (one element for each instance).
+ ke_state_t* state;
+ /// Maximum number of states in the task.
+ uint16_t state_max;
+ /// Maximum index of supported instances of the task.
+ uint16_t idx_max;
+};
+
+/*
+ * FUNCTION PROTOTYPES
+ ****************************************************************************************
+ */
+
+
+/**
+ ****************************************************************************************
+ * @brief Initialize Kernel task module.
+ ****************************************************************************************
+ */
+void ke_task_init(void);
+
+/**
+ ****************************************************************************************
+ * @brief Create a task.
+ *
+ * @param[in] task_type Task type.
+ * @param[in] p_task_desc Pointer to task descriptor.
+ *
+ * @return Status
+ ****************************************************************************************
+ */
+uint8_t ke_task_create(uint8_t task_type, struct ke_task_desc const * p_task_desc);
+
+/**
+ ****************************************************************************************
+ * @brief Delete a task.
+ *
+ * @param[in] task_type Task type.
+ *
+ * @return Status
+ ****************************************************************************************
+ */
+uint8_t ke_task_delete(uint8_t task_type);
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve the state of a task.
+ *
+ * @param[in] id Task id.
+ *
+ * @return Current state of the task
+ ****************************************************************************************
+ */
+ke_state_t ke_state_get(ke_task_id_t const id);
+
+/**
+ ****************************************************************************************
+ * @brief Set the state of the task identified by its Task Id.
+ *
+ * In this function we also handle the SAVE service: when a task state changes we
+ * try to activate all the messages currently saved in the save queue for the given
+ * task identifier.
+ *
+ * @param[in] id Identifier of the task instance whose state is going to be modified
+ * @param[in] state_id New State
+ *
+ ****************************************************************************************
+ */
+void ke_state_set(ke_task_id_t const id, ke_state_t const state_id);
+
+/**
+ ****************************************************************************************
+ * @brief Generic message handler to consume message without handling it in the task.
+ *
+ * @param[in] msgid Id of the message received (probably unused)
+ * @param[in] param Pointer to the parameters of the message.
+ * @param[in] dest_id TaskId of the receiving task.
+ * @param[in] src_id TaskId of the sending task.
+ *
+ * @return KE_MSG_CONSUMED
+ ****************************************************************************************
+ */
+int ke_msg_discard(ke_msg_id_t const msgid, void const *param,
+ ke_task_id_t const dest_id, ke_task_id_t const src_id);
+
+/**
+ ****************************************************************************************
+ * @brief Generic message handler to consume message without handling it in the task.
+ *
+ * @param[in] msgid Id of the message received (probably unused)
+ * @param[in] param Pointer to the parameters of the message.
+ * @param[in] dest_id TaskId of the receiving task.
+ * @param[in] src_id TaskId of the sending task.
+ *
+ * @return KE_MSG_CONSUMED
+ ****************************************************************************************
+ */
+int ke_msg_save(ke_msg_id_t const msgid, void const *param,
+ ke_task_id_t const dest_id, ke_task_id_t const src_id);
+
+
+
+/**
+ ****************************************************************************************
+ * @brief This function flushes all messages, currently pending in the kernel for a
+ * specific task.
+ *
+ * @param[in] task The Task Identifier that shall be flushed.
+ ****************************************************************************************
+ */
+void ke_task_msg_flush(ke_task_id_t task);
+
+
+/**
+ ****************************************************************************************
+ * @brief Check validity of a task. If task type or task instance does not exist,
+ * return invalid task
+ *
+ * @param[in] task Task Identifier to check.
+ *
+ * @return Task identifier if valid, invalid identifier else.
+ ****************************************************************************************
+ */
+ke_task_id_t ke_task_check(ke_task_id_t task);
+
+/// @} TASK
+
+#endif // _KE_TASK_H_
+
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_timer.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_timer.h
new file mode 100644
index 0000000000..ce44859942
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_timer.h
@@ -0,0 +1,143 @@
+/**
+ ****************************************************************************************
+ *
+ * @file ke_timer.h
+ *
+ * @brief This file contains the definitions used for timer management
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef _KE_TIMER_H_
+#define _KE_TIMER_H_
+
+/**
+ ****************************************************************************************
+ * @defgroup TIMER BT Time
+ * @ingroup KERNEL
+ * @brief Timer management module.
+ *
+ * This module implements the functions used for managing kernel timers.
+ *
+ ****************************************************************************************
+ */
+
+#include "rwip_config.h" // stack configuration
+#include "ke_msg.h" // messaging definition
+
+
+/*
+ * DEFINITIONS
+ ****************************************************************************************
+ */
+
+/// Convert timer from second to timer accuracy (10ms)
+#define KE_TIME_IN_SEC(_time) (_time * 100)
+
+
+/*
+ * TYPE DEFINITIONS
+ ****************************************************************************************
+ */
+
+/// Timer Object
+struct ke_timer
+{
+ /// next ke timer
+ struct ke_timer *next;
+ /// message identifier
+ ke_msg_id_t id;
+ /// task identifier
+ ke_task_id_t task;
+ /// time value
+ uint32_t time;
+};
+
+
+/*
+ * FUNCTION PROTOTYPES
+ ****************************************************************************************
+ */
+
+
+/**
+ ****************************************************************************************
+ * @brief Initialize Kernel timer module.
+ ****************************************************************************************
+ */
+void ke_timer_init(void);
+
+/**
+ ****************************************************************************************
+ * @brief Set a timer.
+ *
+ * The function first cancel the timer if it is already existing, then
+ * it creates a new one. The timer can be one-shot or periodic, i.e. it
+ * will be automatically set again after each trigger.
+ *
+ * When the timer expires, a message is sent to the task provided as
+ * argument, with the timer id as message id.
+ *
+ * The timer is programmed in time units (TU is 10ms).
+ *
+ * @param[in] timer_id Timer identifier (message identifier type).
+ * @param[in] task_id Task identifier which will be notified
+ * @param[in] delay Delay in time units.
+ ****************************************************************************************
+ */
+void ke_timer_set(ke_msg_id_t const timer_id, ke_task_id_t const task, uint32_t delay);
+
+/**
+ ****************************************************************************************
+ * @brief Remove an registered timer.
+ *
+ * This function search for the timer identified by its id and its task id.
+ * If found it is stopped and freed, otherwise an error message is returned.
+ *
+ * @param[in] timer_id Timer identifier.
+ * @param[in] task Task identifier.
+ ****************************************************************************************
+ */
+void ke_timer_clear(ke_msg_id_t const timerid, ke_task_id_t const task);
+
+/**
+ ****************************************************************************************
+ * @brief Checks if a requested timer is active.
+ *
+ * This function pops the first timer from the timer queue and notifies the appropriate
+ * task by sending a kernel message. If the timer is periodic, it is set again;
+ * if it is one-shot, the timer is freed. The function checks also the next timers
+ * and process them if they have expired or are about to expire.
+ ****************************************************************************************
+ */
+bool ke_timer_active(ke_msg_id_t const timer_id, ke_task_id_t const task_id);
+
+/**
+ ****************************************************************************************
+ * @brief Adjust all kernel timers by specified adjustment delay.
+ *
+ * This function updates all timers to align to a new SCLK after a system clock adjust.
+ ****************************************************************************************
+ */
+void ke_timer_adjust_all(uint32_t delay);
+
+
+#if (DEEP_SLEEP)
+
+/**
+ ****************************************************************************************
+ * @brief Get the first timer target (in Slot) used for deep sleep decision
+ *
+ * @return Invalid time if nothing programmed; target time else.
+ ****************************************************************************************
+ */
+uint32_t ke_timer_target_get(void);
+
+#endif //DEEP_SLEEP
+void ke_timer_clear(ke_msg_id_t const timer_id, ke_task_id_t const task_id);
+/// @} TIMER
+
+#endif // _KE_TIMER_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc.h
new file mode 100644
index 0000000000..ef5117a2f6
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc.h
@@ -0,0 +1,253 @@
+/**
+ ****************************************************************************************
+ *
+ * @file l2cc.h
+ *
+ * @brief Header file - L2CC.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef L2CC_H_
+#define L2CC_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup L2CC L2CAP Controller
+ * @ingroup L2C
+ * @brief L2CAP block for data processing and per device connection
+ *
+ * The L2CC is responsible for all the data processing related
+ * functions of the L2CAP block per device connection.
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+
+#include "rwip_config.h"
+
+#if (BLE_L2CC)
+
+#include "l2cc_task.h"
+#include "l2cc_pdu.h"
+
+#include
+#include
+#include "co_list.h"
+#include "ke_task.h"
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief Generic way to creates and allocate a Signaling PDU message that can be then
+ * sent to peer device
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] code PDU code
+ * @param[in] src_id Source task ID
+ *
+ * @return Pointer to the PDU payload
+ ****************************************************************************************
+ */
+#define L2CC_SIG_PDU_ALLOC(conidx, code, src_id, type) \
+ ((struct type*) l2cc_pdu_alloc(conidx, L2C_CID_LE_SIGNALING, code, src_id, 0))
+
+/// from PDU, retrieve the send command
+#define L2CC_PDU_TO_CMD(_pdu) \
+ ((struct l2cc_pdu_send_cmd*) (((uint8_t*)_pdu) - offsetof(struct l2cc_pdu_send_cmd, pdu.data.code)))
+
+/// from PDU, retrieve the receive indication
+#define L2CC_PDU_TO_IND(_pdu) \
+ ((struct l2cc_pdu_recv_ind*) (((uint8_t*)_pdu) - offsetof(struct l2cc_pdu_recv_ind, pdu.data.code)))
+
+
+/**
+ ****************************************************************************************
+ * @brief Generic way to creates and allocate a SMP PDU message that can be then sent to
+ * peer device
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] code PDU code
+ * @param[in] src_id Source task ID
+ *
+ * @return Pointer to the PDU payload
+ ****************************************************************************************
+ */
+#define L2CC_SMP_PDU_ALLOC(conidx, code, src_id, type) \
+ ((struct type*) l2cc_pdu_alloc(conidx, L2C_CID_SECURITY, code, src_id, 0))
+
+
+/**
+ ****************************************************************************************
+ * @brief Generic way to creates and allocate an ATT PDU message that can be then sent to
+ * peer device
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] code PDU code
+ * @param[in] src_id Source task ID
+ *
+ * @return Pointer to the PDU payload
+ ****************************************************************************************
+ */
+#define L2CC_ATT_PDU_ALLOC(conidx, code, src_id, type)\
+ ((struct type*) l2cc_pdu_alloc(conidx, L2C_CID_ATTRIBUTE, code, src_id, 0))
+
+
+/**
+ ****************************************************************************************
+ * @brief Generic way to creates and allocate an ATT PDU message that can be then sent to
+ * peer device
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] code PDU code
+ * @param[in] src_id Source task ID
+ * @param[in] length Dynamic payload length to allocate
+ *
+ * @return Pointer to the PDU payload
+ ****************************************************************************************
+ */
+#define L2CC_ATT_PDU_ALLOC_DYN(conidx, code, src_id, type, length)\
+ ((struct type*) l2cc_pdu_alloc(conidx, L2C_CID_ATTRIBUTE, code, src_id, length))
+
+/*
+ * INTERNAL MESSAGES API TYPES
+ ****************************************************************************************
+ */
+
+
+
+/// Send Debug PDU data
+struct l2cc_dbg_pdu_send_cmd
+{
+ /// L2CC request type (@see enum l2cc_operation):
+ /// - L2CC_DBG_PDU_SEND: Send a PDU
+ uint8_t operation;
+ /// offset value information
+ uint16_t offset;
+ /// PDU Data
+ struct l2cc_dbg_pdu pdu;
+};
+
+/// Debug PDU data received
+struct l2cc_dbg_pdu_recv_ind
+{
+ /// Status information
+ uint8_t status;
+ /// offset value information
+ uint16_t offset;
+ /// PDU Data
+ struct l2cc_dbg_pdu pdu;
+};
+
+/// Send Legacy PDU data
+struct l2cc_pdu_send_cmd
+{
+ /// L2CC request type (@see enum l2cc_operation):
+ /// - L2CC_PDU_SEND: Send internal LE Legacy PDU
+ uint8_t operation;
+ /// offset value information
+ uint16_t offset;
+ /// PDU Data
+ struct l2cc_pdu pdu;
+};
+
+
+/// Legacy PDU data received
+struct l2cc_pdu_recv_ind
+{
+ /// Status information
+ uint8_t status;
+ /// offset value information
+ uint16_t offset;
+ /// PDU Data
+ struct l2cc_pdu pdu;
+};
+
+/// Operation type
+enum l2cc_op_type
+{
+ /// Operation used for signaling protocol message exchange
+ L2CC_OP_SIG = 0x00,
+ /// Max number of operations
+ L2CC_OP_MAX,
+};
+
+/*
+ * STRUCTURES
+ ****************************************************************************************
+ */
+
+
+
+/// L2CAP environment structure
+struct l2cc_env_tag
+{
+ /// Ongoing operation
+ void* operation[L2CC_OP_MAX];
+
+ /// Buffer in TX queue
+ struct co_list tx_queue;
+ /// Buffer currently receiving data
+ struct ke_msg* rx_buffer;
+ #if (BLE_LECB)
+ /// List of LE credit based connections
+ struct co_list lecb_list;
+ #endif // (BLE_LECB)
+
+ /// Length of PDU still expected
+ uint16_t rx_pdu_rem_len;
+
+};
+
+
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief Generic way to creates and allocate a PDU message that can be then sent to peer
+ * device
+ *
+ * @note use L2CC_SIG_PDU_ALLOC, L2CC_SMP_PDU_ALLOC, L2CC_ATT_PDU_ALLOC
+ * or L2CC_ATT_PDU_ALLOC_DYN instead of direct function call
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] cid Channel Identifier
+ * @param[in] code PDU code
+ * @param[in] src_id Source task ID
+ * @param[in] length Dynamic payload length to allocate
+ *
+ * @return Generic pointer to the PDU payload
+ ****************************************************************************************
+ */
+void* l2cc_pdu_alloc(uint8_t conidx, uint16_t cid, uint8_t code, ke_task_id_t src_id, uint16_t length);
+
+/**
+ ****************************************************************************************
+ * @brief Generic way to send the PDU message
+ *
+ * @param[in] pdu PDU message to send to peer device
+ ****************************************************************************************
+ */
+void l2cc_pdu_send(void* pdu);
+
+#endif //(BLE_L2CC)
+
+/// @} L2CC
+
+#endif // L2CC_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_int.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_int.h
new file mode 100644
index 0000000000..a2c3e551e2
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_int.h
@@ -0,0 +1,209 @@
+/**
+ ****************************************************************************************
+ *
+ * @file l2cc_int.h
+ *
+ * @brief Header file - L2CCTASK that contains internal API.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef L2CC_INT_H_
+#define L2CC_INT_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup L2CCINT Internals
+ * @ingroup L2CC
+ * @brief Internal API for L2CC module
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "rwip_config.h"
+#if (BLE_L2CC)
+
+#include "l2cc_task.h"
+#include "l2cc.h"
+
+/*
+ * MACRO DEFINITIONS
+ ****************************************************************************************
+ */
+
+
+/// Maximum number of instances of the L2CC task
+#define L2CC_IDX_MAX (BLE_CONNECTION_MAX)
+
+/*
+ * STATES
+ ****************************************************************************************
+ */
+
+
+
+/// states of L2CAP Controller task
+enum l2cc_state_id
+{
+ /// Connection ready state
+ L2CC_READY,
+ /// LE signaling protocol busy
+ L2CC_SIG_BUSY = (1 << L2CC_OP_SIG),
+ /// Free state
+ L2CC_FREE = 0X3F,
+
+ /// Number of defined states.
+ L2CC_STATE_MAX
+};
+
+/*
+ * GLOBAL VARIABLE DECLARATIONS
+ ****************************************************************************************
+ */
+
+/// L2CAP environment pool
+extern struct l2cc_env_tag *l2cc_env[L2CC_IDX_MAX];
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief Create and Initialize the L2CAP controller task.
+ *
+ * @param[in] reset true if it's requested by a reset; false if it's boot initialization
+ *
+ ****************************************************************************************
+ */
+void l2cc_init(bool reset);
+
+/**
+struct l2cc_pdu_recv_ind;
+ *
+ ****************************************************************************************
+ * @brief Initialize the link layer controller task.
+ *
+ * @param[in] conidx Connection index
+ *
+ ****************************************************************************************
+ */
+void l2cc_create(uint8_t conidx);
+
+/**
+ ****************************************************************************************
+ * @brief De-initialize the task.
+ *
+ * @param[in] conidx Connection index
+ * @param[in] reset true if it's requested by a reset; false if it's boot initialization
+ ****************************************************************************************
+ */
+void l2cc_cleanup(uint8_t conidx, bool reset);
+
+/**
+ ****************************************************************************************
+ * @brief Update task state
+ *
+ * @param[in] conidx Connection index
+ * @param[in] state to update
+ * @param[in] set state to busy (true) or idle (false)
+ *
+ ****************************************************************************************
+ */
+void l2cc_update_state(uint8_t conidx, ke_state_t state, bool busy);
+
+
+/**
+ * @brief Send a complete event of ongoing executed operation to requester.
+ * It also clean-up variable used for ongoing operation.
+ *
+ * @param[in] conidx Connection index
+ * @param[in] op_type Operation type.
+ * @param[in] status Status of completed operation
+ */
+void l2cc_send_complete_evt(uint8_t conidx, uint8_t op_type, uint8_t status);
+
+/**
+ ****************************************************************************************
+ * @brief Send operation completed message with status error code not related to a
+ * running operation.
+ *
+ * @param[in] conidx Connection index
+ * @param[in] operation Operation code
+ * @param[in] requester requester of operation
+ * @param[in] status Error status code
+ * @param[in] cid Channel Identifier
+ ****************************************************************************************
+ */
+void l2cc_send_error_evt(uint8_t conidx, uint8_t operation, const ke_task_id_t requester, uint8_t status, uint16_t cid);
+
+
+/**
+ ****************************************************************************************
+ * @brief Get operation on going
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] op_type Operation type.
+ *
+ * @return operation code on going
+ ****************************************************************************************
+ */
+uint8_t l2cc_get_operation(uint8_t conidx, uint8_t op_type);
+
+/**
+ ****************************************************************************************
+ * @brief Get operation pointer
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] op_type Operation type.
+ *
+ * @return operation pointer on going
+ ****************************************************************************************
+ */
+void* l2cc_get_operation_ptr(uint8_t conidx, uint8_t op_type);
+
+
+/**
+ ****************************************************************************************
+ * @brief Set operation pointer
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] op_type Operation type.
+ * @param[in] op Operation pointer.
+ *
+ ****************************************************************************************
+ */
+void l2cc_set_operation_ptr(uint8_t conidx, uint8_t op_type, void* op);
+
+
+
+
+/**
+ ****************************************************************************************
+ * @brief Perform data packet TX over HCI (call of this function is handled by L2CM
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] nb_buffer Number of available TX buffers
+ ****************************************************************************************
+ */
+void l2cc_data_send(uint8_t conidx, uint8_t nb_buffer);
+
+
+
+
+
+
+#endif //(BLE_L2CC)
+
+/// @} L2CCINT
+
+#endif // L2CC_INT_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_lecb.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_lecb.h
new file mode 100644
index 0000000000..70fe6c079a
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_lecb.h
@@ -0,0 +1,262 @@
+/**
+ ****************************************************************************************
+ *
+ * @file l2cc_pdu.h
+ *
+ * @brief Header file - L2CAP LE Credit Based connection management
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ ****************************************************************************************
+ */
+
+
+#ifndef _L2CC_LECB_H_
+#define _L2CC_LECB_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup L2CC_LECB L2Cap Controller LE Credit Based connection management
+ * @ingroup L2CC
+ * @brief This module is in charge of LECB connection management
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+
+#include "rwip_config.h"
+
+#if (BLE_LECB)
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+/// LE Credit Based fields.
+enum l2cc_lecb_fields
+{
+ /// LE Protocol Service Multiplexer
+ L2CC_LECB_LEPSM,
+ /// Local channel ID
+ L2CC_LECB_LOCAL_CID,
+ /// Peer channel ID
+ L2CC_LECB_PEER_CID,
+};
+
+
+/// Status of the LE Credit Based connection
+///
+/// 7 6 5 4 3 2 1 0
+/// +----+----+----+----+----+----+----+----+
+/// | RFU |P_I |TX_W|CON |
+/// +----+----+----+----+----+----+----+----+
+///
+/// bit [2] : Local(0)/Peer (1) initiated connection
+/// bit [1] : TX in Wait state (segment transmission not finished)
+/// bit [0] : LECB Connected
+enum l2cc_lecb_state
+{
+ /// Peer initiated connection
+ L2CC_LECB_PEER_INIT_BIT = (1<<2),
+ L2CC_LECB_PEER_INIT_POS = (2),
+
+ /// TX in Wait state (segment transmission not finished)
+ L2CC_LECB_TX_WAIT_BIT = (1<<1),
+ L2CC_LECB_TX_WAIT_POS = (1),
+
+ /// Channel Connected
+ L2CC_LECB_CONNECTED_BIT = (1<<0),
+ L2CC_LECB_CONNECTED_POS = (0),
+};
+
+
+
+
+
+/*
+ * MACRO DEFINITIONS
+ ****************************************************************************************
+ */
+
+/*
+ * TYPE DEFINITIONS
+ ****************************************************************************************
+ */
+
+
+
+/// LE credit based information for a link started or on-going.
+struct l2cc_lecb_info
+{
+ /// Pointer to the following list
+ struct co_list_hdr hdr;
+ /// SDU waiting to be transfered (required for segmentation algorithm)
+ struct l2cc_lecb_sdu_send_cmd* tx_sdu;
+ /// SDU waiting to be received (required for reassembly algorithm)
+ struct l2cc_lecb_sdu_recv_ind* rx_sdu;
+
+ /// LE Protocol/Service Multiplexer
+ uint16_t le_psm;
+
+ /// Local channel ID
+ uint16_t local_cid;
+ /// Local Maximum Transmission Unit
+ uint16_t local_mtu;
+ /// Local Maximum Packet Size
+ uint16_t local_mps;
+ /// Local credit
+ uint16_t local_credit;
+
+ /// Peer channel ID
+ uint16_t peer_cid;
+ /// Peer Maximum Transmission Unit
+ uint16_t peer_mtu;
+ /// Peer Maximum Packet Size
+ uint16_t peer_mps;
+ /// Peer credit
+ uint16_t peer_credit;
+
+ /// Task id requested connection
+ ke_task_id_t task_id;
+
+ /// Status of the LE Credit Based connection (@see enum l2cc_lecb_state)
+ uint8_t state;
+
+ /// disconnection reason
+ uint8_t disc_reason;
+
+ /// Packet identifier - used for LECB negotiation
+ uint8_t pkt_id;
+};
+
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief Search LE Credit Based channel depending on the parameter
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] field Search field (@see enum l2cc_lecb_fields)
+ * @param[in] value Field value to search
+ *
+ * @return Returns NULL or pointer to the LE Credit Based channel info
+ ****************************************************************************************
+ */
+struct l2cc_lecb_info* l2cc_lecb_find(uint8_t conidx, uint8_t field, uint16_t value);
+
+/**
+ ****************************************************************************************
+ * @brief End of LECB Connection, free information, and send disconnect indication
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] lecb LE Credit Based Connection information
+ * @param[in] disconnect_ind True, sends disconnect indication
+ ****************************************************************************************
+ */
+void l2cc_lecb_free(uint8_t conidx, struct l2cc_lecb_info* lecb, bool disconnect_ind);
+
+
+/**
+ ****************************************************************************************
+ * @brief Sends LE credit based connection request
+ *
+ * @param[in] conidx connection index
+ * @param[in] pkt_id Packet identifier
+ * @param[in] scid Source channel ID
+ * @param[in] credits Credits
+ * @param[in] mps Maximum Packet Size
+ * @param[in] mtu Maximum Transfer Unit
+ ****************************************************************************************
+ */
+void l2cc_lecb_send_con_req(uint8_t conidx, uint8_t pkt_id, uint16_t le_psm, uint16_t scid, uint16_t credits,
+ uint16_t mps, uint16_t mtu);
+
+/**
+ ****************************************************************************************
+ * @brief Sends LE credit based connection response
+ *
+ * @param[in] conidx connection index
+ * @param[in] status status of the connection
+ * @param[in] pkt_id Packet identifier
+ * @param[in] dcid Destination channel ID
+ * @param[in] credits Credits
+ * @param[in] mps Maximum Packet Size
+ * @param[in] mtu Maximum Transfer Unit
+ ****************************************************************************************
+ */
+void l2cc_lecb_send_con_rsp(uint8_t conidx, uint16_t status, uint8_t pkt_id,
+ uint16_t dcid, uint16_t credits, uint16_t mps, uint16_t mtu);
+
+/**
+ ****************************************************************************************
+ * @brief Sends LE credit based disconnection request
+ *
+ * @param[in] conidx connection index
+ * @param[in] pkt_id Packet identifier
+ * @param[in] dcid Destination channel ID
+ * @param[in] scid Source channel ID
+ ****************************************************************************************
+ */
+void l2cc_lecb_send_disc_req(uint8_t conidx, uint8_t pkt_id, uint16_t scid, uint16_t dcid);
+
+/**
+ ****************************************************************************************
+ * @brief Sends LE credit based disconnection response
+ *
+ * @param[in] conidx connection index
+ * @param[in] pkt_id Packet identifier
+ * @param[in] dcid Destination channel ID
+ * @param[in] scid Source channel ID
+ ****************************************************************************************
+ */
+void l2cc_lecb_send_disc_rsp(uint8_t conidx, uint8_t pkt_id, uint16_t dcid, uint16_t scid);
+/**
+ ****************************************************************************************
+ * @brief Sends LE credit based Flow Control credit add message
+ *
+ * @param[in] conidx connection index
+ * @param[in] pkt_id Packet identifier
+ * @param[in] cid Source Channel ID
+ * @param[in] credits Credits
+ ****************************************************************************************
+ */
+void l2cc_lecb_send_credit_add(uint8_t conidx, uint8_t pkt_id, uint16_t cid, uint16_t credits);
+
+
+/**
+ ****************************************************************************************
+ * @brief Due to an error on LECB link, initiate a disconnection of the channel
+ *
+ * @param[in] conidx connection index
+ * @param[in] lecb Information of the channel
+ * @param[in] disc_reason Disconnection reason
+ *
+ ****************************************************************************************
+ */
+void l2cc_lecb_init_disconnect(uint8_t conidx, struct l2cc_lecb_info* lecb, uint8_t disc_reason);
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve LECB error Code from Host error code
+ *
+ * @param[in] h_err Host Error code
+ *
+ * @return LECB Error code
+ ****************************************************************************************
+ */
+uint16_t l2cc_lecb_h2l_err(uint8_t h_err);
+
+#endif //(BLE_LECB)
+
+/// @} L2CC_LECB
+
+#endif /* _L2CC_LECB_H_ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_pdu.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_pdu.h
new file mode 100644
index 0000000000..c16f6037a2
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_pdu.h
@@ -0,0 +1,1111 @@
+/**
+ ****************************************************************************************
+ *
+ * @file l2cc_pdu.h
+ *
+ * @brief Header file - L2CAP Controller PDU packer / unpacker
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+
+#ifndef _L2CC_PDU_H_
+#define _L2CC_PDU_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup L2CC_PDU L2Cap Controller PDU generator/extractor
+ * @ingroup L2CC
+ * @brief This module is in charge to pack or unpack L2CAP packets
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "co_bt.h"
+#include "gap.h"
+#include "att.h"
+//#include "compiler.h"
+#include "ble_arch.h"
+/*
+ * MACROS
+ ****************************************************************************************
+ */
+
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/// Minimal authorized MTU value (defined by Bluetooth SIG)
+#define L2C_MIN_LE_MTUSIG (23)
+
+/// L2CAP mode supported for BLE - only mode accepted
+#define L2C_MODE_BASIC_L2CAP (0x00)
+
+/// Packet partition
+#define L2C_CID_LEN (2)
+#define L2C_LENGTH_LEN (2)
+#define L2C_CODE_LEN (1)
+#define L2C_HEADER_LEN (L2C_CID_LEN + L2C_LENGTH_LEN)
+#define L2C_SDU_LEN (2)
+#define L2C_LECB_HEADER_LEN (L2C_HEADER_LEN + L2C_SDU_LEN)
+
+/// Maximum credit
+#define L2C_LECB_MAX_CREDIT 0xFFFF
+
+
+/* result for connection parameter update response */
+#define L2C_CONN_PARAM_ACCEPT 0x0000
+#define L2C_CONN_PARAM_REJECT 0x0001
+
+/* command reject reasons */
+enum l2cc_pdu_err
+{
+ L2C_CMD_NOT_UNDERSTOOD = 0x0000,
+ L2C_MTU_SIG_EXCEEDED = 0x0001,
+ L2C_INVALID_CID = 0x0002,
+};
+
+/* Flag to describe the packet boundary */
+#define L2C_PB_START_NON_FLUSH 0x00
+#define L2C_PB_CONTINUE 0x01
+#define L2C_PB_START_FLUSH 0x02
+
+/// Check if channel ID is within the correct range
+#define L2C_IS_DYNAMIC_CID(cid) ((cid >= L2C_CID_DYN_MIN) && (cid <= L2C_CID_DYN_MAX))
+
+/// Check if LE PSM is within the correct range
+#define L2C_IS_VALID_LEPSM(lepsm) (lepsm != L2C_LEPSM_RESERVED)
+
+/*
+ * ENUMERATIONS
+ ****************************************************************************************
+ */
+
+/** L2CAP LE PSM limits */
+enum l2cc_lepsm_limits
+{
+ /// Reserved
+ L2C_LEPSM_RESERVED = 0x0000,
+ /// Fixed minimum range SIG assigned
+ L2C_LEPSM_FIXED_MIN = 0x0001,
+ /// Fixed maximum range SIG assigned
+ L2C_LEPSM_FIXED_MAX = 0x007F,
+ /// Dynamic minimum range SIG assigned
+ L2C_LEPSM_DYN_MIN = 0x0080,
+ /// Dynamic maximum range SIG assigned
+ L2C_LEPSM_DYN_MAX = 0x00FF,
+ /// Reserved minimum range SIG assigned
+ L2C_LEPSM_RSV_MIN = 0x0100,
+ /// Reserved maximum range SIG assigned
+ L2C_LEPSM_RSV_MAX = 0xFFFF,
+};
+
+/** L2CAP channels id */
+enum l2cc_cid
+{
+ /// Reserved channel id
+ L2C_CID_RESERVED = 0x0000,
+ /// Attribute channel id
+ L2C_CID_ATTRIBUTE = 0x0004,
+ /// Signaling channel id
+ L2C_CID_LE_SIGNALING = 0x0005,
+ /// Security channel id
+ L2C_CID_SECURITY = 0x0006,
+ /// Dynamically allocated minimum range
+ L2C_CID_DYN_MIN = 0x0040,
+ /// Dynamically allocated maximum range
+ L2C_CID_DYN_MAX = 0x007F,
+};
+
+
+/// signaling codes
+enum l2cc_signal_code
+{
+ /// Reserved code
+ L2C_CODE_RESERVED = 0x00,
+ /// Reject request
+ L2C_CODE_REJECT = 0x01,
+ /// Connection request
+ L2C_CODE_CONNECTION_REQ = 0x02,
+ /// Connection response
+ L2C_CODE_CONNECTION_RESP = 0x03,
+ /// Configuration request
+ L2C_CODE_CONFIGURATION_REQ = 0x04,
+ /// Configuration response
+ L2C_CODE_CONFIGURATION_RESP = 0x05,
+ /// Disconnection request
+ L2C_CODE_DISCONNECTION_REQ = 0x06,
+ /// Disconnection response
+ L2C_CODE_DISCONNECTION_RESP = 0x07,
+ /// Echo request
+ L2C_CODE_ECHO_REQ = 0x08,
+ /// Echo response
+ L2C_CODE_ECHO_RESP = 0x09,
+ /// Information request
+ L2C_CODE_INFORMATION_REQ = 0x0A,
+ /// Information response
+ L2C_CODE_INFORMATION_RESP = 0x0B,
+ /// Create channel request
+ L2C_CODE_CREATE_CHANNEL_REQ = 0x0C,
+ /// Create channel response
+ L2C_CODE_CREATE_CHANNEL_RESP = 0x0D,
+ /// Move channel request
+ L2C_CODE_MOVE_CHANNEL_REQ = 0x0E,
+ /// Move channel response
+ L2C_CODE_MOVE_CHANNEL_RESP = 0x0F,
+ /// Move channel confirmation
+ L2C_CODE_MOVE_CHANNEL_CFM = 0x10,
+ /// Move channel confirmation response
+ L2C_CODE_MOVE_CHANNEL_CFM_RESP = 0x11,
+ /// Connection Parameter Update Request
+ L2C_CODE_CONN_PARAM_UPD_REQ = 0x12,
+ /// Connection Parameter Update Response
+ L2C_CODE_CONN_PARAM_UPD_RESP = 0x13,
+ /// LE Credit Based Connection request
+ L2C_CODE_LE_CB_CONN_REQ = 0x14,
+ /// LE Credit Based Connection response
+ L2C_CODE_LE_CB_CONN_RESP = 0x15,
+ /// LE Flow Control Credit
+ L2C_CODE_LE_FLOW_CONTROL_CREDIT = 0x16,
+
+ /// max number of signaling codes
+ L2C_CODE_SIGNALING_MAX
+};
+
+
+/// security codes
+enum l2cc_security_code
+{
+ /// Pairing Request
+ L2C_CODE_PAIRING_REQUEST = 0x01,
+ /// Pairing Response
+ L2C_CODE_PAIRING_RESPONSE = 0x02,
+ /// Pairing Confirm
+ L2C_CODE_PAIRING_CONFIRM = 0x03,
+ /// Pairing Random
+ L2C_CODE_PAIRING_RANDOM = 0x04,
+ /// Pairing Failed
+ L2C_CODE_PAIRING_FAILED = 0x05,
+ /// Encryption Information
+ L2C_CODE_ENCRYPTION_INFORMATION = 0x06,
+ /// Master Identification
+ L2C_CODE_MASTER_IDENTIFICATION = 0x07,
+ /// Identity Information
+ L2C_CODE_IDENTITY_INFORMATION = 0x08,
+ /// Identity Address Information
+ L2C_CODE_IDENTITY_ADDRESS_INFORMATION = 0x09,
+ /// Signing Information
+ L2C_CODE_SIGNING_INFORMATION = 0x0A,
+ /// Security Request
+ L2C_CODE_SECURITY_REQUEST = 0x0B,
+ // Pairing Public Keys
+ L2C_CODE_PUBLIC_KEY = 0x0C,
+ // Pairing DHKey Check
+ L2C_CODE_DHKEY_CHECK = 0x0D,
+ // Pairing Keypress Notification
+ L2C_CODE_KEYPRESS_NOTIFICATION = 0x0E,
+ /// max number of security codes
+ L2C_CODE_SECURITY_MAX
+};
+
+
+/// attribute protocol PDU codes
+enum l2cc_attribute_code
+{
+ /// Error response
+ L2C_CODE_ATT_ERR_RSP = 0x01,
+ /// Exchange MTU Request
+ L2C_CODE_ATT_MTU_REQ = 0x02,
+ /// Exchange MTU Response
+ L2C_CODE_ATT_MTU_RSP = 0x03,
+ /// Find Information Request
+ L2C_CODE_ATT_FIND_INFO_REQ = 0x04,
+ /// Find Information Response
+ L2C_CODE_ATT_FIND_INFO_RSP = 0x05,
+ /// Find By Type Value Request
+ L2C_CODE_ATT_FIND_BY_TYPE_REQ = 0x06,
+ /// Find By Type Value Response
+ L2C_CODE_ATT_FIND_BY_TYPE_RSP = 0x07,
+ /// Read By Type Request
+ L2C_CODE_ATT_RD_BY_TYPE_REQ = 0x08,
+ /// Read By Type Response
+ L2C_CODE_ATT_RD_BY_TYPE_RSP = 0x09,
+ /// Read Request
+ L2C_CODE_ATT_RD_REQ = 0x0A,
+ /// Read Response
+ L2C_CODE_ATT_RD_RSP = 0x0B,
+ /// Read Blob Request
+ L2C_CODE_ATT_RD_BLOB_REQ = 0x0C,
+ /// Read Blob Response
+ L2C_CODE_ATT_RD_BLOB_RSP = 0x0D,
+ /// Read Multiple Request
+ L2C_CODE_ATT_RD_MULT_REQ = 0x0E,
+ /// Read Multiple Response
+ L2C_CODE_ATT_RD_MULT_RSP = 0x0F,
+ /// Read by Group Type Request
+ L2C_CODE_ATT_RD_BY_GRP_TYPE_REQ = 0x10,
+ /// Read By Group Type Response
+ L2C_CODE_ATT_RD_BY_GRP_TYPE_RSP = 0x11,
+ /// Write Request
+ L2C_CODE_ATT_WR_REQ = 0x12,
+ /// Write Response
+ L2C_CODE_ATT_WR_RSP = 0x13,
+ /// Write Command
+ L2C_CODE_ATT_WR_CMD_INFO = 0x14,
+ L2C_CODE_ATT_WR_CMD = 0x52,
+ /// Signed Write Command
+ L2C_CODE_ATT_SIGN_WR_CMD_INFO = 0x15,
+ L2C_CODE_ATT_SIGN_WR_CMD = 0xD2,
+ /// Prepare Write Request
+ L2C_CODE_ATT_PREP_WR_REQ = 0x16,
+ /// Prepare Write Response
+ L2C_CODE_ATT_PREP_WR_RSP = 0x17,
+ /// Execute Write Request
+ L2C_CODE_ATT_EXE_WR_REQ = 0x18,
+ /// Execute Write Response
+ L2C_CODE_ATT_EXE_WR_RSP = 0x19,
+ /// Handle Value Notification
+ L2C_CODE_ATT_HDL_VAL_NTF = 0x1B,
+ /// Handle Value Indication
+ L2C_CODE_ATT_HDL_VAL_IND = 0x1D,
+ /// Handle Value Confirmation
+ L2C_CODE_ATT_HDL_VAL_CFM = 0x1E,
+
+ /// max number of security codes
+ L2C_CODE_ATT_MAX
+};
+
+/// LE Connection oriented PDU codes
+enum l2cc_le_connor_code
+{
+ /// Data frame
+ L2C_CODE_CON_DATA = 0x01,
+
+ /// max number of connection oriented codes
+ L2C_CODE_CON_MAX
+};
+
+/// Result values for LE Credit Based Connection Response
+enum l2cc_cb_resp_value
+{
+ /// connection successful
+ L2C_CB_CON_SUCCESS = 0x0000,
+ /// Reserved
+ L2C_CB_CON_RSV1,
+ /// Connection refused - LE_PSM not supported
+ L2C_CB_CON_LEPSM_NOT_SUPP,
+ /// Reserved
+ L2C_CB_CON_RSV2,
+ /// Connection refused - no resources available
+ L2C_CB_CON_NO_RES_AVAIL,
+ /// Connection refused - insufficient authentication
+ L2C_CB_CON_INS_AUTH,
+ /// Connection refused - insufficient authorization
+ L2C_CB_CON_INS_AUTHOR,
+ /// Connection refused - insufficient encryption key size
+ L2C_CB_CON_INS_EKS,
+ /// Connection Refused - insufficient encryption
+ L2C_CB_CON_INS_ENCRYPTION,
+
+ /* ESR 09 error codes */
+ /// Connection Refused - invalid Source CID
+ L2C_CB_CON_INVALID_SRC_CID,
+ /// Connection Refused - Source CID already allocated
+ L2C_CB_CON_SRC_CID_ALREADY_ALLOC,
+ /// Connection Refused - Unacceptable parameters
+ L2C_CB_CON_UNACCEPTABLE_PARAM
+};
+
+/*
+ * TYPE DEFINITIONS
+ ****************************************************************************************
+ */
+
+/// Disconnection Request
+struct l2cc_disconnection_req
+{
+ /// Signaling code - 0x06
+ uint8_t code;
+ /// Packet Identifier
+ uint8_t pkt_id;
+ /// data length
+ uint16_t length;
+ /// Destination CID
+ uint16_t dcid;
+ /// Source CID
+ uint16_t scid;
+};
+
+/// Disconnection Response
+struct l2cc_disconnection_rsp
+{
+ /// Signaling code - 0x07
+ uint8_t code;
+ /// Packet Identifier
+ uint8_t pkt_id;
+ /// data length
+ uint16_t length;
+ /// Destination CID
+ uint16_t dcid;
+ /// Source CID
+ uint16_t scid;
+};
+
+/// Connection Parameter Update Request
+struct l2cc_update_param_req
+{
+ /// Signaling code - 0x12
+ uint8_t code;
+ /// Packet Identifier
+ uint8_t pkt_id;
+ /// data length
+ uint16_t length;
+ /// minimum value for the connection event interval
+ uint16_t intv_min;
+ /// maximum value for the connection event interval
+ uint16_t intv_max;
+ /// slave latency parameter
+ uint16_t latency;
+ /// connection timeout parameter
+ uint16_t timeout;
+};
+
+/// Connection Parameter Update Response
+struct l2cc_update_param_rsp
+{
+ /// Signaling code - 0x13
+ uint8_t code;
+ /// Packet Identifier
+ uint8_t pkt_id;
+ /// data length
+ uint16_t length;
+ /// Result field indicates the response to the Connection Parameter Update Request
+ /// - 0x0000 Connection Parameters accepted
+ /// - 0x0001 Connection Parameters rejected
+ uint16_t response;
+};
+
+/// LE Credit based connection request
+struct l2cc_lecb_req
+{
+ /// Signaling code - 0x14
+ uint8_t code;
+ /// Packet Identifier
+ uint8_t pkt_id;
+ /// data length
+ uint16_t length;
+ /// LE Protocol/Service Multiplexer
+ uint16_t le_psm;
+ /// Source CID
+ uint16_t scid;
+ /// Maximum Transmission Unit
+ uint16_t mtu;
+ /// Maximum PDU Size
+ uint16_t mps;
+ /// Initial credits
+ uint16_t initial_credits;
+};
+
+/// LE Credit based connection response
+struct l2cc_lecb_rsp
+{
+ /// Signaling code - 0x15
+ uint8_t code;
+ /// Packet Identifier
+ uint8_t pkt_id;
+ /// data length
+ uint16_t length;
+ /// Destination CID
+ uint16_t dcid;
+ /// Maximum Transmission Unit
+ uint16_t mtu;
+ /// Maximum PDU Size
+ uint16_t mps;
+ /// Initial credits
+ uint16_t initial_credits;
+ /// Result
+ uint16_t result;
+};
+
+/// LE Flow Control Credit
+struct l2cc_le_flow_ctl_credit
+{
+ /// Signaling code - 0x16
+ uint8_t code;
+ /// Packet Identifier
+ uint8_t pkt_id;
+ /// data length
+ uint16_t length;
+ /// CID
+ uint16_t cid;
+ /// Credits
+ uint16_t credits;
+};
+
+/// Command Reject
+struct l2cc_reject
+{
+ /// Signaling code - 0x01
+ uint8_t code;
+ /// Packet Identifier
+ uint8_t pkt_id;
+ /// data length
+ uint16_t length;
+ /// The Reason field describes why the Request packet was rejected
+ /// - 0x0000 Command not understood
+ /// - 0x0001 Signaling MTU exceeded
+ /// - 0x0002 Invalid CID in request
+ uint16_t reason;
+ /// Optional parameters total length
+ uint16_t opt_len;
+ ///16-byte array for optional parameters
+ uint8_t opt[__ARRAY_EMPTY];
+};
+
+
+/// Pairing Request
+struct l2cc_pairing_req
+{
+ /// security code - 0x01
+ uint8_t code;
+ /// IO Capability
+ uint8_t iocap;
+ /// OOB data flag
+ uint8_t oob;
+ /// AuthReq
+ uint8_t auth;
+ /// Maximum Encryption Key Size
+ uint8_t key_size;
+ /// Initiator Key Distribution
+ uint8_t ikey_dist;
+ /// Responder Key Distribution
+ uint8_t rkey_dist;
+};
+/// Pairing Response
+struct l2cc_pairing_rsp
+{
+ /// security code - 0x02
+ uint8_t code;
+ /// IO Capability
+ uint8_t iocap;
+ /// OOB data flag
+ uint8_t oob;
+ /// AuthReq
+ uint8_t auth;
+ /// Maximum Encryption Key Size
+ uint8_t key_size;
+ /// Initiator Key Distribution
+ uint8_t ikey_dist;
+ /// Responder Key Distribution
+ uint8_t rkey_dist;
+};
+/// Pairing Confirm
+struct l2cc_pairing_cfm
+{
+ /// security code - 0x03
+ uint8_t code;
+ ///Confirm value
+ uint8_t cfm_val[CFM_LEN];
+};
+/// Pairing Random
+struct l2cc_pairing_random
+{
+ /// security code - 0x04
+ uint8_t code;
+ ///Random value
+ uint8_t random[RAND_VAL_LEN];
+};
+/// Pairing Failed
+struct l2cc_pairing_failed
+{
+ /// security code - 0x05
+ uint8_t code;
+ /// The Reason field indicates why the pairing failed
+ uint8_t reason;
+};
+/// Encryption Information
+struct l2cc_encryption_inf
+{
+ /// security code - 0x06
+ uint8_t code;
+ ///16-byte array for LTK value
+ uint8_t ltk[GAP_KEY_LEN];
+};
+/// Master Identification
+struct l2cc_master_id
+{
+ /// security code - 0x07
+ uint8_t code;
+ /// key diversifier
+ uint16_t ediv;
+ ///8-byte array for random number
+ uint8_t nb[GAP_RAND_NB_LEN];
+};
+/// Identity Information
+struct l2cc_identity_inf
+{
+ /// security code - 0x08
+ uint8_t code;
+ ///16-byte array for IRK value
+ uint8_t irk[GAP_KEY_LEN];
+};
+/// Identity Address Information
+struct l2cc_id_addr_inf
+{
+ /// security code - 0x09
+ uint8_t code;
+ /// BD Address Type
+ uint8_t addr_type;
+ /// BD Address
+ bd_addr_t addr;
+};
+/// Signing Information
+struct l2cc_signing_inf
+{
+ /// security code - 0x0A
+ uint8_t code;
+ ///16-byte array for CSRK value
+ uint8_t csrk[GAP_KEY_LEN];
+};
+/// Security Request
+struct l2cc_security_req
+{
+ /// security code - 0x0B
+ uint8_t code;
+ /// AuthReq
+ uint8_t auth;
+};
+
+/// Public Key (x,y)
+struct l2cc_publc_key
+{
+ /// security code - 0x0C
+ uint8_t code;
+ /// X and Y co-ordinates of the Public Key
+ uint8_t x[GAP_P256_KEY_LEN];
+ uint8_t y[GAP_P256_KEY_LEN];
+};
+
+/// DH Key Check
+struct l2cc_dhkey_check
+{
+ /// security code - 0x0D
+ uint8_t code;
+ uint8_t check[DHKEY_CHECK_LEN];
+};
+/// Keypress Notification - PassKey method only
+struct l2cc_keypress_noticication
+{
+ /// security code - 0x0E
+ uint8_t code;
+
+ uint8_t notification_type;
+};
+
+
+/* Attribute protocol PDUs */
+
+/// Error response
+struct l2cc_att_err_rsp
+{
+ /// Error Response - 0x01
+ uint8_t code;
+ /// The request that generated this error response
+ uint8_t op_code;
+ /// The attribute handle that generated this error response
+ uint16_t handle;
+ ///The reason why the request has generated an error response
+ uint8_t reason;
+};
+
+/// Exchange MTU Request
+struct l2cc_att_mtu_req
+{
+ /// Exchange MTU Request - 0x02
+ uint8_t code;
+ /// Client Rx MTU size
+ uint16_t mtu_size;
+};
+
+/// Exchange MTU Response
+struct l2cc_att_mtu_rsp
+{
+ /// Exchange MTU Response - 0x03
+ uint8_t code;
+ /// Server Rx MTU size
+ uint16_t mtu_size;
+};
+
+/// Find Information Request
+struct l2cc_att_find_info_req
+{
+ /// Find Information Request - 0x04
+ uint8_t code;
+ /// First requested handle number
+ uint16_t shdl;
+ /// Last requested handle number
+ uint16_t ehdl;
+};
+
+/// Find Information Response
+struct l2cc_att_find_info_rsp
+{
+ /// Find Information Response - 0x05
+ uint8_t code;
+ /// The format of the information data.
+ uint8_t format;
+ /// Data length
+ uint16_t data_len;
+ ///The information data whose format is determined by the Format field
+ uint8_t data[__ARRAY_EMPTY];
+};
+
+/// Find By Type Value Request
+struct l2cc_att_find_by_type_req
+{
+ /// Find By Type Value Request - 0x06
+ uint8_t code;
+ /// First requested handle number
+ uint16_t shdl;
+ /// Last requested handle number
+ uint16_t ehdl;
+ /// 2 octet UUID to find
+ uint16_t type;
+ /// Attribute value length
+ uint16_t val_len;
+ /// Attribute value to find
+ uint8_t val[__ARRAY_EMPTY];
+};
+
+/// Find By Type Value Response
+struct l2cc_att_find_by_type_rsp
+{
+ /// Find By Type Value Response - 0x07
+ uint8_t code;
+ /// data length
+ uint16_t data_len;
+ /// A list of 1 or more Handle Informations.
+ uint8_t data[__ARRAY_EMPTY];
+};
+
+/// Read By Type Request
+struct l2cc_att_rd_by_type_req
+{
+ /// Read By Type Request - 0x08
+ uint8_t code;
+ /// Starting Handle
+ uint16_t shdl;
+ /// Ending Handle
+ uint16_t ehdl;
+ /// Attribute uuid length
+ uint16_t uuid_len;
+ /// Attribute type uuid
+ uint8_t uuid[__ARRAY_EMPTY];
+};
+
+/// Read By Type Response
+struct l2cc_att_rd_by_type_rsp
+{
+ /// Read By Type Response - 0x09
+ uint8_t code;
+ /// size of each attribute handle listed
+ uint8_t each_len;
+ /// Attribute Data length
+ uint16_t data_len;
+ /// A list of Attribute Data.
+ uint8_t data[__ARRAY_EMPTY];
+};
+
+/// Read Request
+struct l2cc_att_rd_req
+{
+ /// Read Request - 0x0A
+ uint8_t code;
+ /// Attribute Handle
+ uint16_t handle;
+};
+
+/// Read Response
+struct l2cc_att_rd_rsp
+{
+ /// Read Response - 0x0B
+ uint8_t code;
+ /// value length
+ uint16_t value_len;
+ /// The value of the attribute with the handle given
+ uint8_t value[__ARRAY_EMPTY];
+};
+
+/// Read Blob Request
+struct l2cc_att_rd_blob_req
+{
+ /// Read Blob Request - 0x0C
+ uint8_t code;
+ /// Attribute Handle
+ uint16_t handle;
+ /// The offset of the first octet to be read
+ uint16_t offset;
+};
+
+/// Read Blob Response
+struct l2cc_att_rd_blob_rsp
+{
+ /// Read Blob Response - 0x0D
+ uint8_t code;
+ /// value length
+ uint16_t value_len;
+ /// Part of the value of the attribute with the handle given
+ uint8_t value[__ARRAY_EMPTY];
+};
+
+/// Read Multiple Request
+struct l2cc_att_rd_mult_req
+{
+ /// Read Multiple Request - 0x0E
+ uint8_t code;
+ /// Number of handles
+ uint16_t nb_handles;
+ /// A set of two or more attribute handles.
+ uint16_t handles[__ARRAY_EMPTY];
+};
+
+/// Read Multiple Response
+struct l2cc_att_rd_mult_rsp
+{
+ /// Read Multiple Response - 0x0F
+ uint8_t code;
+ /// value length
+ uint16_t value_len;
+ /// A set of two or more values.
+ uint8_t value[__ARRAY_EMPTY];
+};
+
+/// Read by Group Type Request
+struct l2cc_att_rd_by_grp_type_req
+{
+ /// Read by Group Type Request - 0x10
+ uint8_t code;
+ /// First requested handle number
+ uint16_t shdl;
+ /// Last requested handle number
+ uint16_t ehdl;
+ /// Attribute uuid length
+ uint16_t uuid_len;
+ /// Attribute type uuid (2 or 16 octet UUID)
+ uint8_t uuid[__ARRAY_EMPTY];
+};
+
+/// Read By Group Type Response
+struct l2cc_att_rd_by_grp_type_rsp
+{
+ /// Read By Group Type Response - 0x11
+ uint8_t code;
+ /// size of each attribute handle listed
+ uint8_t each_len;
+ /// Attribute Data length
+ uint16_t data_len;
+ /// A list of Attribute Data.
+ uint8_t data[__ARRAY_EMPTY];
+};
+
+/// Write Request
+struct l2cc_att_wr_req
+{
+ /// Write Request - 0x12
+ uint8_t code;
+ /// The handle of the attribute to be written
+ uint16_t handle;
+ /// Value length
+ uint16_t value_len;
+ /// The value to be written to the attribute
+ uint8_t value[__ARRAY_EMPTY];
+};
+
+/// Write Response
+struct l2cc_att_wr_rsp
+{
+ /// Write Response - 0x13
+ uint8_t code;
+};
+
+/// Write Command
+struct l2cc_att_wr_cmd
+{
+ /// Write Command - 0x52
+ uint8_t code;
+ /// The handle of the attribute to be written
+ uint16_t handle;
+ /// Value length
+ uint16_t value_len;
+ /// The value to be written to the attribute
+ uint8_t value[__ARRAY_EMPTY];
+};
+
+/// Signed Write Command
+struct l2cc_att_sign_wr_cmd
+{
+ /// Write Command - 0xD2
+ uint8_t code;
+ /// The handle of the attribute to be written
+ uint16_t handle;
+ /// Attribute Data length
+ uint16_t value_len;
+ /// The value to be written to the attribute
+ /// + 12 bytes of signatures:
+ /// Authentication signature for the Attribute Upload, Attribute Handle and Attribute
+ /// Value Parameters
+ uint8_t value[__ARRAY_EMPTY];
+};
+
+/// Prepare Write Request
+struct l2cc_att_prep_wr_req
+{
+ /// Prepare Write Request - 0x16
+ uint8_t code;
+ /// The handle of the attribute to be written
+ uint16_t handle;
+ /// The offset of the first octet to be written
+ uint16_t offset;
+ /// Value length
+ uint16_t value_len;
+ /// The value to be written to the attribute
+ uint8_t value[__ARRAY_EMPTY];
+};
+
+/// Prepare Write Response
+struct l2cc_att_prep_wr_rsp
+{
+ /// Prepare Write Response - 0x17
+ uint8_t code;
+ /// The handle of the attribute to be written
+ uint16_t handle;
+ /// The offset of the first octet to be written
+ uint16_t offset;
+ /// Value length
+ uint16_t value_len;
+ /// The value to be written to the attribute
+ uint8_t value[__ARRAY_EMPTY];
+};
+
+/// Execute Write Request
+struct l2cc_att_exe_wr_req
+{
+ /// Execute Write Request - 0x18
+ uint8_t code;
+ /// 0x00 - Cancel all prepared writes
+ /// 0x01 - Immediately write all pending prepared values
+ uint8_t flags;
+};
+
+/// Execute Write Response
+struct l2cc_att_exe_wr_rsp
+{
+ /// Prepare Write Response - 0x19
+ uint8_t code;
+};
+
+/// Handle Value Notification
+struct l2cc_att_hdl_val_ntf
+{
+ /// Handle Value Notification - 0x1B
+ uint8_t code;
+ /// The handle of the attribute to be written
+ uint16_t handle;
+ /// Value length
+ uint16_t value_len;
+ /// The current value of the attribute
+ uint8_t value[__ARRAY_EMPTY];
+};
+
+/// Handle Value Indication
+struct l2cc_att_hdl_val_ind
+{
+ /// Handle Value Indication - 0x1D
+ uint8_t code;
+ /// The handle of the attribute to be written
+ uint16_t handle;
+ /// Value length
+ uint16_t value_len;
+ /// The current value of the attribute
+ uint8_t value[__ARRAY_EMPTY];
+};
+
+/// Handle Value Confirmation
+struct l2cc_att_hdl_val_cfm
+{
+ /// Handle Value Confirmation - 0x1E
+ uint8_t code;
+};
+
+/* LE Credit Based PDUs */
+
+/// LE Generic send data request (includes total SDU Length)
+struct l2cc_lecb_send_data_req
+{
+ /// Code variable (RFU)
+ uint8_t code;
+ /// SDU data length
+ uint16_t sdu_data_len;
+ /// Data
+ uint8_t sdu_data[__ARRAY_EMPTY];
+};
+
+
+struct l2cc_pdu_data_t
+{
+ /// L2Cap packet code.
+ uint8_t code;
+};
+
+/// Default L2Cap PDU definition
+struct l2cc_pdu
+{
+ /// L2Cap Payload Length
+ uint16_t payld_len;
+ /// L2Cap Channel ID
+ uint16_t chan_id;
+
+ /// Data PDU definition
+ union l2cc_pdu_data
+ {
+ /// L2Cap packet code.
+ uint8_t code;
+
+ /* LE Credit Based packets */
+ /// LE send first frame
+ struct l2cc_lecb_send_data_req send_lecb_data_req;
+
+ /* Connection Signaling Packets */
+ /// Command Reject
+ struct l2cc_reject reject;
+ /// Connection Parameter Update Request
+ struct l2cc_update_param_req update_req;
+ /// Connection Parameter Update Response
+ struct l2cc_update_param_rsp update_rsp;
+ /// LE Credit based connection request
+ struct l2cc_lecb_req credit_con_req;
+ /// LE Credit based connection response
+ struct l2cc_lecb_rsp credit_con_rsp;
+ /// LE Flow Control Credit
+ struct l2cc_le_flow_ctl_credit flow_ctl_credit;
+ /// LE disconnection request
+ struct l2cc_disconnection_req disc_req;
+ /// LE disconnection response
+ struct l2cc_disconnection_rsp disc_rsp;
+
+ /* Security manager PDUs */
+ /// Pairing Request
+ struct l2cc_pairing_req pairing_req;
+ /// Pairing Response
+ struct l2cc_pairing_rsp pairing_rsp;
+ /// Pairing Confirm
+ struct l2cc_pairing_cfm pairing_cfm;
+ /// Pairing Random
+ struct l2cc_pairing_random pairing_random;
+ /// Pairing Failed
+ struct l2cc_pairing_failed pairing_failed;
+ /// Encryption Information
+ struct l2cc_encryption_inf encryption_inf;
+ /// Master Identification
+ struct l2cc_master_id master_id;
+ /// Identity Information
+ struct l2cc_identity_inf identity_inf;
+ /// Identity Address Information
+ struct l2cc_id_addr_inf id_addr_inf;
+ /// Signing Information
+ struct l2cc_signing_inf signing_inf;
+ /// Security Request
+ struct l2cc_security_req security_req;
+ /// Public Keys
+ struct l2cc_publc_key public_key;
+ /// Key Press Notification
+ struct l2cc_keypress_noticication keypress_noticication;
+ /// DH Key Check
+ struct l2cc_dhkey_check dhkey_check;
+ /* Attribute protocol PDUs */
+ /// Error response
+ struct l2cc_att_err_rsp err_rsp;
+ /// Exchange MTU Request
+ struct l2cc_att_mtu_req mtu_req;
+ /// Exchange MTU Response
+ struct l2cc_att_mtu_rsp mtu_rsp;
+ /// Find Information Request
+ struct l2cc_att_find_info_req find_info_req;
+ /// Find Information Response
+ struct l2cc_att_find_info_rsp find_info_rsp;
+ /// Find By Type Value Request
+ struct l2cc_att_find_by_type_req find_by_type_req;
+ /// Find By Type Value Response
+ struct l2cc_att_find_by_type_rsp find_by_type_rsp;
+ /// Read By Type Request
+ struct l2cc_att_rd_by_type_req rd_by_type_req;
+ /// Read By Type Response
+ struct l2cc_att_rd_by_type_rsp rd_by_type_rsp;
+ /// Read Request
+ struct l2cc_att_rd_req rd_req;
+ /// Read Response
+ struct l2cc_att_rd_rsp rd_rsp;
+ /// Read Blob Request
+ struct l2cc_att_rd_blob_req rd_blob_req;
+ /// Read Blob Response
+ struct l2cc_att_rd_blob_rsp rd_blob_rsp;
+ /// Read Multiple Request
+ struct l2cc_att_rd_mult_req rd_mult_req;
+ /// Read Multiple Response
+ struct l2cc_att_rd_mult_rsp rd_mult_rsp;
+ /// Read by Group Type Request
+ struct l2cc_att_rd_by_grp_type_req rd_by_grp_type_req;
+ /// Read By Group Type Response
+ struct l2cc_att_rd_by_grp_type_rsp rd_by_grp_type_rsp;
+ /// Write Request
+ struct l2cc_att_wr_req wr_req;
+ /// Write Response
+ struct l2cc_att_wr_rsp wr_rsp;
+ /// Write Command
+ struct l2cc_att_wr_cmd wr_cmd;
+ /// Signed Write Command
+ struct l2cc_att_sign_wr_cmd sign_wr_cmd;
+ /// Prepare Write Request
+ struct l2cc_att_prep_wr_req prep_wr_req;
+ /// Prepare Write Response
+ struct l2cc_att_prep_wr_rsp prep_wr_rsp;
+ /// Execute Write Request
+ struct l2cc_att_exe_wr_req exe_wr_req;
+ /// Execute Write Response
+ struct l2cc_att_exe_wr_rsp exe_wr_rsp;
+ /// Handle Value Notification
+ struct l2cc_att_hdl_val_ntf hdl_val_ntf;
+ /// Handle Value Indication
+ struct l2cc_att_hdl_val_ind hdl_val_ind;
+ /// Handle Value Confirmation
+ struct l2cc_att_hdl_val_cfm hdl_val_cfm;
+ } data;
+};
+
+/// Default L2Cap DBG pdu definition
+struct l2cc_dbg_pdu
+{
+ /// Data length
+ uint16_t length;
+ /// data
+ uint8_t data[__ARRAY_EMPTY];
+};
+
+/// Default L2Cap SDU definition
+struct l2cc_sdu;
+
+
+/// @} L2CC_PDU
+
+
+#endif /* _L2CC_PDU_H_ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_pdu_int.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_pdu_int.h
new file mode 100644
index 0000000000..1c9bd5ddef
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_pdu_int.h
@@ -0,0 +1,186 @@
+/**
+ ****************************************************************************************
+ *
+ * @file l2cc_pdu_int.h
+ *
+ * @brief Header file - L2CAP Controller PDU packer / unpacker (internal)
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+
+#ifndef _L2CC_PDU_INT_H_
+#define _L2CC_PDU_INT_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup L2CC_PDU_INT L2Cap Controller (internal)
+ * @ingroup L2CC
+ * @brief This module is in charge to pack or unpack L2CAP packets
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+
+#include "rwip_config.h"
+
+#if (BLE_L2CC)
+
+#include "l2cc_pdu.h"
+
+/*
+ * MACROS
+ ****************************************************************************************
+ */
+
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * Pack PDU from firmware readable data to a L2CAP packet using generic method.
+ * (no segmentation)
+ *
+ * @param[in] p_pdu Pointer to the unpacked PDU structure
+ * @param[in|out] p_offset Pointer to address where the next part of PDU will be read
+ * @param[in|out] p_length Pointer to the length of payload that has been packed
+ * @param[in|out] p_buffer Pointer to address where the next part of PDU will be written
+ * @param[in|out] llid LLID of the next packet to send
+ *
+ * @return GAP_ERR_NO_ERROR if packing succeed, else another error code.
+ ****************************************************************************************
+ */
+uint8_t l2cc_pdu_pack(struct l2cc_pdu *p_pdu, uint16_t *p_offset, uint16_t *p_length, uint8_t *p_buffer, uint8_t *llid);
+
+/**
+ ****************************************************************************************
+ * Unpack L2Cap PDU in a generic format that can be used by firmware using generic method.
+ * (no reassembly)
+ *
+ * @param[in] p_pdu Pointer to the unpacked PDU structure
+ * @param[in|out] p_offset Pointer to address where the next part of PDU will be written
+ * @param[in|out] p_rem_len Pointer to the remaining length value of PDU to receive
+ * @param[in|out] p_buffer Pointer to address where the next part of PDU will be read
+ * @param[in] pkt_length Length of the received packet
+ * @param[in] llid LLID of the received packet
+ *
+ * @return GAP_ERR_NO_ERROR if packing succeed, else another error code.
+ ****************************************************************************************
+ */
+uint8_t l2cc_pdu_unpack(struct l2cc_pdu *p_pdu, uint16_t *p_offset, uint16_t *p_rem_len,
+ const uint8_t *p_buffer, uint16_t pkt_length, uint8_t llid);
+
+
+
+#if (BLE_DEBUG)
+/**
+ ****************************************************************************************
+ * Pack DBG PDU (any kind of PDU generated by Host) from firmware readable data to a L2CAP
+ * packet (no segmentation)
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] pdu Pointer to the Debug PDU to send
+ * @param[in|out] p_length Pointer to the length of payload that has been packed
+ * @param[in|out] buffer Pointer to address where the next part of PDU will be written
+ * @param[in|out] offset Pointer to address where the next part of PDU will be read
+ * @param[in|out] llid LLID of the next packet to send
+ *
+ * @return GAP_ERR_NO_ERROR if packing succeed, else another error code.
+ ****************************************************************************************
+ */
+uint8_t l2cc_dbg_pdu_pack(struct l2cc_dbg_pdu *pdu, uint16_t *length, uint8_t *buffer, uint16_t* offset,uint8_t *llid);
+
+
+/**
+ ****************************************************************************************
+ * Unpack L2Cap PDU in a generic format that can be used by firmware for debugging
+ * (no reassembly)
+ *
+ * @param[in|out] sdu Pointer to the unpacked SDU structure
+ * @param[in] buffer Pointer to address where the next part of PDU will be read
+ * @param[in] length Length of the received packet
+ * @param[in|out] offset Pointer to address where the next part of PDU will be written
+ * @param[in] llid LLID of the received packet
+ *
+ * @return GAP_ERR_NO_ERROR if packing succeed, else another error code.
+ ****************************************************************************************
+ */
+uint8_t l2cc_dbg_pdu_unpack(struct l2cc_dbg_pdu *pdu, uint8_t *buffer, uint16_t length, uint16_t* offset, uint8_t llid);
+#endif // (BLE_DEBUG)
+
+#if (BLE_LECB)
+/**
+ ****************************************************************************************
+ * Pack LE Credit Based channel PDU from firmware readable data to a L2CAP packet
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] pdu Pointer to the SDU to send
+ * @param[out] length Pointer to the length of payload that has been packed
+ * @param[in|out] buffer Pointer to address where the next part of PDU will be written
+ * @param[in|out] offset Pointer to address where the next part of PDU will be read
+ * @param[in|out] pdu_len PDU length to transmitt
+ * @param[in] llid LLID of the next packet to send
+ *
+ * @return GAP_ERR_NO_ERROR if packing succeed, else another error code.
+ ****************************************************************************************
+ */
+uint8_t l2cc_lecb_pdu_pack(uint8_t conidx, struct l2cc_sdu *sdu, uint16_t *length, uint8_t *buffer, uint16_t* offset,
+ uint16_t pdu_len, uint8_t llid);
+
+
+/**
+ ****************************************************************************************
+ * Unpack L2Cap LECB SDU in a generic format that can be used by firmware
+ *
+ * @param[in|out] sdu Pointer to the unpacked SDU structure
+ * @param[in] buffer Pointer to address where the next part of PDU will be read
+ * @param[in] length Length of the received packet
+ * @param[in|out] offset Pointer to address where the next part of PDU will be written
+ * @param[in|out] pdu_remain_len Pointer to the data length still expected on segment
+ * @param[in] llid LLID of the received packet
+ *
+ * @return GAP_ERR_NO_ERROR if packing succeed, else another error code.
+ ****************************************************************************************
+ */
+uint8_t l2cc_lecb_pdu_unpack(struct l2cc_sdu *sdu, uint8_t *buffer, uint16_t length, uint16_t* offset,
+ uint16_t* pdu_remain_len, uint8_t llid);
+
+#endif //(BLE_LECB)
+
+/**
+ ****************************************************************************************
+ * @brief Check the PDU packet header channel ID, Length, in order to:
+ * - verify if no error detected
+ * - allocate or retrieve the RX messge for expected destination task
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] buffer RX buffer that contains first PDU fragment
+ *
+ * @return GAP_ERR_NO_ERROR if header sanity check succeed, else an error code to ignore
+ * reception of PDU
+ ****************************************************************************************
+ */
+uint8_t l2cc_pdu_header_check(uint8_t conidx, uint8_t* buffer);
+
+
+/// @} L2CC_PDU_INT
+
+#endif //(BLE_L2CC)
+
+#endif /* _L2CC_PDU_INT_H_ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_sig.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_sig.h
new file mode 100644
index 0000000000..e16bfeb197
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_sig.h
@@ -0,0 +1,96 @@
+/**
+ ****************************************************************************************
+ *
+ * @file l2cc_sig.h
+ *
+ * @brief L2CAP Controller Controller Signaling PDU Handler.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ ****************************************************************************************
+ */
+
+#ifndef _L2CC_SIG_H_
+#define _L2CC_SIG_H_
+
+
+/**
+ ****************************************************************************************
+ * @addtogroup L2CC_SIG L2CAP Controller Signaling PDU Handler.
+ * @ingroup L2CC
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "rwip_config.h"
+
+#if (BLE_L2CC)
+
+#include "l2cc.h"
+#include "l2cc_task.h"
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/*
+ * MACRO DEFINITIONS
+ ****************************************************************************************
+ */
+
+
+
+/*
+ * TYPE DEFINITIONS
+ ****************************************************************************************
+ */
+
+
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+
+/**
+ ****************************************************************************************
+ * @brief Send an L2Cap command rejected signaling packet with command not understood
+ * error code.
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] pkt_id Packet identifier
+ *
+ * @param[in] reason The Reason field describes why the Request packet was rejected
+ * @param[in] opt1 Optional param 1
+ * @param[in] opt2 Optional param 2
+ ****************************************************************************************
+ */
+void l2cc_sig_send_cmd_reject(uint8_t conidx, uint8_t pkt_id, uint16_t reason, uint16_t opt1, uint16_t opt2);
+
+
+/**
+ ****************************************************************************************
+ * @brief Handles reception of L2CAP signaling messages from peer device.
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] pdu PDU Received
+ *
+ * @return If the message was consumed or not.
+ ****************************************************************************************
+ */
+int l2cc_sig_pdu_recv_handler(uint8_t conidx, struct l2cc_pdu *pdu);
+
+
+
+
+#endif // (BLE_L2CC)
+
+#endif // _L2CC_SIG_H_
+
+/// @} L2CC_SIG
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_task.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_task.h
new file mode 100644
index 0000000000..58dfef17d3
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_task.h
@@ -0,0 +1,312 @@
+/**
+ ****************************************************************************************
+ *
+ * @file l2cc_task.h
+ *
+ * @brief Header file - L2CCTASK.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef L2CC_TASK_H_
+#define L2CC_TASK_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup L2CCTASK Task
+ * @ingroup L2CC
+ * @brief Handles ALL messages to/from L2CC block.
+ *
+ * The L2CC task is responsible for L2CAP attribute and security block handling.
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "rwip_task.h" // Task definitions
+//#include "compiler.h"
+#include "ble_arch.h"
+#include
+
+/*
+ * MACRO DEFINITIONS
+ ****************************************************************************************
+ */
+
+/// Number of L2CC Deprecated messages
+#define L2CC_NB_DEPRECATED_MSG (4)
+
+/*
+ * STATES
+ ****************************************************************************************
+ */
+
+/*
+ * MESSAGES
+ ****************************************************************************************
+ */
+
+/// Message API of the L2CC task
+enum l2cc_msg_id
+{
+ /// L2CAP Operation completed event
+ L2CC_CMP_EVT = TASK_FIRST_MSG(TASK_ID_L2CC) + L2CC_NB_DEPRECATED_MSG, //a04
+
+ /* ************* LE Credit Based API ************* */
+ /// LE credit based connection request
+ L2CC_LECB_CONNECT_CMD,
+ /// LE credit based connection request indication
+ L2CC_LECB_CONNECT_REQ_IND,
+ /// LE credit based connection request confirmation
+ L2CC_LECB_CONNECT_CFM,
+ /// LE credit based connection indication
+ L2CC_LECB_CONNECT_IND,
+ /// LE credit based disconnect request
+ L2CC_LECB_DISCONNECT_CMD,
+ /// LE credit based disconnect indication
+ L2CC_LECB_DISCONNECT_IND,
+ /// LE credit based credit addition
+ L2CC_LECB_ADD_CMD,
+ /// LE credit based credit addition indication
+ L2CC_LECB_ADD_IND,
+
+ /// Send data over an LE Credit Based Connection
+ L2CC_LECB_SDU_SEND_CMD,
+ /// Inform that a data packet has been received from a LE Credit Based connection.
+ L2CC_LECB_SDU_RECV_IND,
+
+
+ /* ******************* Debug API ******************* */
+ /// Send Debug PDU data
+ L2CC_DBG_PDU_SEND_CMD, //0xa0f
+ /// Debug PDU data received
+ L2CC_DBG_PDU_RECV_IND,
+
+
+ /* **************** PDU Internal API ****************** */
+ /// Send Legacy PDU data
+ L2CC_PDU_SEND_CMD, //0xa11
+ /// Legacy PDU data received
+ L2CC_PDU_RECV_IND,
+
+ /// Timeout indication for a transaction on signaling channel
+ L2CC_SIGNALING_TRANS_TO_IND,
+};
+
+
+/// request operation type - application interface
+enum l2cc_operation
+{
+ /* Operation Flags */
+ /* No Operation (if nothing has been requested) */
+ /* ************************************************ */
+ /// No operation
+ L2CC_NO_OP = 0x00,
+
+ /* LE Credit Based */
+ /* ************************************************ */
+ /// LE credit based connection request
+ L2CC_LECB_CONNECT,
+ /// LE credit based disconnection request
+ L2CC_LECB_DISCONNECT,
+ /// LE credit addition request
+ L2CC_LECB_CREDIT_ADD,
+ /// Send SDU
+ L2CC_LECB_SDU_SEND,
+
+ /* Debug PDU Transmission (internal) */
+ /* ************************************************ */
+ /// Send a Debug PDU
+ L2CC_DBG_PDU_SEND,
+
+ /* PDU Transmission (internal) */
+ /* ************************************************ */
+ /// Send internal LE Legacy PDU
+ L2CC_PDU_SEND,
+};
+
+
+/// Default L2Cap SDU definition
+struct l2cc_sdu
+{
+ /// Channel Identifier
+ uint16_t cid;
+ /// Number of credit used
+ uint16_t credit;
+ /// SDU Data length
+ uint16_t length;
+ /// data
+ uint8_t data[__ARRAY_EMPTY];
+};
+
+
+/// Operation completed event
+struct l2cc_cmp_evt
+{
+ /// L2CC request type (@see enum l2cc_operation)
+ uint8_t operation;
+ /// Status of request.
+ uint8_t status;
+ /// Channel ID
+ uint16_t cid;
+ /// Number of peer credit used - only relevant for LECB
+ uint16_t credit;
+};
+
+/// LE credit based connection request
+struct l2cc_lecb_connect_cmd
+{
+ /// L2CC request type:
+ /// - L2CC_LECB_CONNECT: LE credit connection
+ uint8_t operation;
+ /// parameter used for internal usage
+ uint8_t pkt_id;
+ /// LE Protocol/Service Multiplexer
+ uint16_t le_psm;
+ /// Local Channel identifier (0: automatically allocate a free channel)
+ uint16_t local_cid;
+ /// Credit allocated for the LE Credit Based Connection
+ /// Shall be at least: floor(((SDU + 2) + (MPS - 1)) / MPS) + 1
+ /// To be sure that 1 SDU can be fully received without requesting credits to application
+ uint16_t local_credit;
+ /// Maximum SDU size - Shall not exceed device MTU
+ uint16_t local_mtu;
+ /// Maximum Packet size - Shall not exceed device MPS
+ uint16_t local_mps;
+};
+
+/// LE credit based connection request indication
+struct l2cc_lecb_connect_req_ind
+{
+ /// LE Protocol/Service Multiplexer
+ uint16_t le_psm;
+ /// Peer Channel identifier
+ uint16_t peer_cid;
+ /// Maximum SDU size
+ uint16_t peer_mtu;
+ /// Maximum Packet size
+ uint16_t peer_mps;
+};
+
+/// LE credit based connection request confirmation
+struct l2cc_lecb_connect_cfm
+{
+ /// LE Protocol/Service Multiplexer
+ uint16_t le_psm;
+ /// Peer Channel identifier
+ uint16_t peer_cid;
+ /// True to accept the incoming connection, False else
+ bool accept;
+ /// Local Channel identifier (0: automatically allocate a free channel)
+ uint16_t local_cid;
+ /// Credit allocated for the LE Credit Based Connection
+ /// Shall be at least: floor(((SDU + 2) + (MPS - 1)) / MPS) + 1
+ /// To be sure that 1 SDU can be fully received without requesting credits to application
+ uint16_t local_credit;
+ /// Maximum SDU size - Shall not exceed device MTU
+ uint16_t local_mtu;
+ /// Maximum Packet size - Shall not exceed device MPS
+ uint16_t local_mps;
+};
+
+/// LE credit based connection indication
+struct l2cc_lecb_connect_ind
+{
+ /// Status
+ uint8_t status;
+ /// LE Protocol/Service Multiplexer
+ uint16_t le_psm;
+ /// Local Channel identifier
+ uint16_t local_cid;
+ /// Peer Channel identifier
+ uint16_t peer_cid;
+ /// Destination Credit for the LE Credit Based Connection
+ uint16_t peer_credit;
+ /// Maximum SDU size
+ uint16_t peer_mtu;
+ /// Maximum Packet size
+ uint16_t peer_mps;
+};
+
+/// LE credit based disconnect request
+struct l2cc_lecb_disconnect_cmd
+{
+ /// L2CC request type:
+ /// - L2CC_LECB_DISCONNECT: LE credit disconnection
+ uint8_t operation;
+ /// parameter used for internal usage
+ uint8_t pkt_id;
+ /// Peer Channel identifier
+ uint16_t peer_cid;
+};
+
+/// LE credit based disconnect indication
+struct l2cc_lecb_disconnect_ind
+{
+ /// LE Protocol/Service Multiplexer
+ uint16_t le_psm;
+ /// Local Channel identifier
+ uint16_t local_cid;
+ /// Peer Channel identifier
+ uint16_t peer_cid;
+ /// Reason
+ uint8_t reason;
+};
+
+/// LE credit based credit addition
+struct l2cc_lecb_add_cmd
+{
+ /// L2CC request type:
+ /// - L2CC_LECB_CREDIT_ADD: LE credit addition
+ uint8_t operation;
+ /// parameter used for internal usage
+ uint8_t pkt_id;
+ /// Local Channel identifier
+ uint16_t local_cid;
+ /// Credit added locally for channel identifier
+ uint16_t credit;
+};
+
+///LE credit based credit addition indication
+struct l2cc_lecb_add_ind
+{
+ /// Peer Channel identifier
+ uint16_t peer_cid;
+ /// Destination added credit (relative value)
+ uint16_t peer_added_credit;
+};
+
+/// Send data over an LE Credit Based Connection
+struct l2cc_lecb_sdu_send_cmd
+{
+ /// L2CC request type (@see enum l2cc_operation):
+ /// - L2CC_LECB_SDU_SEND: Send a SDU
+ uint8_t operation;
+ /// offset value information - for internal use only
+ uint16_t offset;
+ /// SDU information
+ struct l2cc_sdu sdu;
+};
+
+/// Inform that a data packet has been received from a LE Credit Based connection.
+struct l2cc_lecb_sdu_recv_ind
+{
+ /// Status information
+ uint8_t status;
+ /// offset value information
+ uint16_t offset;
+ /// SDU information
+ struct l2cc_sdu sdu;
+};
+
+
+/// @} L2CCTASK
+
+#endif // L2CC_TASK_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cm.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cm.h
new file mode 100644
index 0000000000..47395522c8
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cm.h
@@ -0,0 +1,127 @@
+/**
+ ****************************************************************************************
+ *
+ * @file l2cm.h
+ *
+ * @brief Header file - L2CM.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef L2CM_H_
+#define L2CM_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup L2C Logical Link Control and Adaptation Protocol
+ * @ingroup HOST
+ * @brief Logical Link Control and Adaptation Protocol - BLE Host.
+ *
+ * The L2C module is responsible for L2CAP provides connection-oriented
+ * and connection-less data services to upper layer protocols with protocol
+ * multiplexing capability and segmentation and re-assembly operation.
+ *
+ * @{
+ ****************************************************************************************
+ */
+/**
+ ****************************************************************************************
+ * @addtogroup L2CM L2CAP Manager
+ * @ingroup L2C
+ * @brief L2CAP block for signaling and resource management functions
+ *
+ * The L2CM is an internal L2CAP block responsible for managing
+ * the signaling messages and propagation of connection and disconnection
+ * related L2CAP messages within the Host.
+ *
+ * @{
+ ****************************************************************************************
+ */
+#include "rwip_config.h"
+
+#if (BLE_L2CM)
+#include
+#include
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/*
+ * GLOBAL VARIABLE DECLARATIONS
+ ****************************************************************************************
+ */
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief Create and Initialize the L2CAP manager task.
+ *
+ * @param[in] reset true if it's requested by a reset; false if it's boot initialization
+ *
+ ****************************************************************************************
+ */
+void l2cm_init(bool reset);
+
+
+
+/**
+ ****************************************************************************************
+ * @brief Allocates an L2CAP resource.
+ *
+ * @param[in] conidx connection index
+ *
+ ****************************************************************************************
+ */
+void l2cm_create(uint8_t conidx);
+
+/**
+ ****************************************************************************************
+ * @brief De-initializes the L2CAP resources for specified link.
+ *
+ * @param[in] conidx connection index
+ *
+ ****************************************************************************************
+ */
+void l2cm_cleanup(uint8_t conidx);
+
+
+/**
+ ****************************************************************************************
+ * @brief Sets link layer buffer size capacity
+ *
+ * @param[in] pkt_len length of the packet
+ * @param[in] nb_acl number of acl
+ *
+ ****************************************************************************************
+ */
+void l2cm_set_link_layer_buff_size(uint16_t pkt_len, uint16_t nb_acl);
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve number of low layer buffer available
+ *
+ * @return Number of low layer buffer available
+ ****************************************************************************************
+ */
+uint16_t l2cm_get_nb_buffer_available(void);
+
+/// @} L2CM
+
+#endif //(BLE_L2CM)
+
+#endif // L2CM_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cm_int.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cm_int.h
new file mode 100644
index 0000000000..4dafb639d6
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cm_int.h
@@ -0,0 +1,129 @@
+/**
+ ****************************************************************************************
+ *
+ * @file l2cm_int.h
+ *
+ * @brief Header file - L2CM internal.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef L2CM_INT_H_
+#define L2CM_INT_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup L2C_INT Logical Link Control and Adaptation Protocol internals
+ * @ingroup HOST
+ * @brief Logical Link Control and Adaptation Protocol - Internal API.
+ *
+ * @{
+ ****************************************************************************************
+ */
+#include "rwip_config.h"
+
+#if (BLE_L2CM)
+#include
+#include
+#include "ble_arch.h"
+#include "l2cm.h"
+//
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/*
+ * GLOBAL VARIABLE DECLARATIONS
+ ****************************************************************************************
+ */
+
+/// L2CAP Manager environment structure to be saved
+struct l2cm_env_tag
+{
+ #if (BLE_L2CC)
+ /// bit field used to know per connection if TX activity is on-going
+ uint32_t con_tx_state;
+ #endif // (BLE_L2CC)
+ /// Lower Layer buffers length
+ uint16_t le_acl_data_pkt_len;
+ /// Total number of available Lower Layer buffers
+ uint16_t le_acl_total_nb_acl_pkt;
+ /// Number of available Lower Layer buffers
+ uint16_t nb_buffer_avail;
+ };
+
+/*
+ * GLOBAL VARIABLE DECLARATIONS
+ ****************************************************************************************
+ */
+extern struct l2cm_env_tag l2cm_env;
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief Acquire low layer LE ACL packet
+ ****************************************************************************************
+ */
+__INLINE void l2cm_buffer_acquire(void)
+{
+ l2cm_env.nb_buffer_avail--;
+}
+
+/**
+ ****************************************************************************************
+ * @brief Release low layer LE ACL packet
+ *
+ * @parm[in] nb Number of buffer to release.
+ ****************************************************************************************
+ */
+__INLINE void l2cm_buffer_release(uint16_t nb)
+{
+ l2cm_env.nb_buffer_avail += nb;
+}
+
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve low layer LE ACL Buffers size
+ *
+ * @return size of LE ACL Buffers
+ ****************************************************************************************
+ */
+ __INLINE uint16_t l2cm_get_buffer_size(void)
+ {
+ return l2cm_env.le_acl_data_pkt_len;
+ }
+
+
+/**
+ ****************************************************************************************
+ * @brief Set if TX queue for specific connection is empty or not.
+ *
+ * If not empty, it will request L2CM to start transmission of buffers
+ *
+ * @param[in] conidx Connection index
+ * @param[in] busy False if TX buffer queue is empty, True else
+ *
+ ****************************************************************************************
+ */
+void l2cm_tx_status(uint8_t conidx, bool busy);
+
+/// @} L2CM_INT
+
+#endif //(BLE_L2CM)
+
+#endif // L2CM_INT_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/nvds.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/nvds.h
new file mode 100644
index 0000000000..5f3ec5bbe7
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/nvds.h
@@ -0,0 +1,378 @@
+/**
+ ****************************************************************************************
+ *
+ * @file nvds.h
+ *
+ * @brief Non Volatile Data Storage (NVDS) driver
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ ****************************************************************************************
+ */
+#ifndef _NVDS_H_
+#define _NVDS_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup NVDS
+ * @ingroup COMMON
+ * @brief Non Volatile Data Storage (NVDS)
+ *
+ * Parameters management
+ * there are two compilation options:
+ * + NVDS_8BIT_TAGLENGTH :
+ * if set, each TAG has a maximum length of 256 bytes
+ * if not set, each TAG has a maximum length of 65536 bytes
+ * + NVDS_PACKED :
+ * if not set, all the TAG header structures and TAG data contents are stored with an
+ * alignment on 32 bit boundary
+ * if set, all the TAG header structures and TAG data contents are stored
+ * consecutively without gaps (as would be a structure with pragma packed)
+ * + NVDS_READ_WRITE :
+ * if not set, only GET action on TAGs is provided.
+ * if set, PUT/DEL/LOCK actions are provided in addition of GET action.
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include // boolean definition
+#include // integer definition
+
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/// NVDS is defined as read-write
+#define NVDS_READ_WRITE 1
+
+/// NVDS is defined as packed
+#define NVDS_PACKED 1
+
+/// NVDS has 8-bit length tags
+#define NVDS_8BIT_TAGLENGTH 1
+
+/// Type of the tag length (8 or 16 bits)
+#if (NVDS_8BIT_TAGLENGTH)
+typedef uint8_t nvds_tag_len_t;
+#else
+typedef uint16_t nvds_tag_len_t;
+#endif // NVDS_8BIT_TAGLENGTH
+
+//#define FLASH_BASE_ADDR 0x400
+//#define FLASH_BLE_SIZE 0x400
+/*
+ * ENUMERATION DEFINITIONS
+ ****************************************************************************************
+ */
+
+/// Possible Returned Status
+enum NVDS_STATUS
+{
+ /// NVDS status OK
+ NVDS_OK,
+ /// generic NVDS status KO
+ NVDS_FAIL,
+ /// NVDS TAG unrecognized
+ NVDS_TAG_NOT_DEFINED,
+ /// No space for NVDS
+ NVDS_NO_SPACE_AVAILABLE,
+ /// Length violation
+ NVDS_LENGTH_OUT_OF_RANGE,
+ /// NVDS parameter locked
+ NVDS_PARAM_LOCKED,
+ /// NVDS corrupted
+ NVDS_CORRUPT
+};
+
+/// List of NVDS TAG identifiers
+enum NVDS_TAG
+{
+ /// Definition of the tag associated to each parameters
+ /// Local Bd Address
+ NVDS_TAG_BD_ADDRESS = 0x01,
+ /// Device Name
+ NVDS_TAG_DEVICE_NAME = 0x02,
+ /// Radio Drift
+ NVDS_TAG_LPCLK_DRIFT = 0x07,
+ /// Radio Jitter
+ NVDS_TAG_LPCLK_JITTER = 0x08,
+ /// Radio Class
+ NVDS_TAG_RADIO_CLASS = 0x09,
+ /// Bluejay specific Settings
+ NVDS_TAG_BJ_TXCNTL1 = 0x0A,
+ /// External wake-up time
+ NVDS_TAG_EXT_WAKEUP_TIME = 0x0D,
+ /// Oscillator wake-up time
+ NVDS_TAG_OSC_WAKEUP_TIME = 0x0E,
+ /// Radio wake-up time
+ NVDS_TAG_RM_WAKEUP_TIME = 0x0F,
+ /// UART baudrate
+ NVDS_TAG_UART_BAUDRATE = 0x10,
+ /// Enable sleep mode
+ NVDS_TAG_SLEEP_ENABLE = 0x11,
+ /// Enable External Wakeup
+ NVDS_TAG_EXT_WAKEUP_ENABLE = 0x12,
+ /// SP Private Key 192
+ NVDS_TAG_SP_PRIVATE_KEY_P192 = 0x13,
+ /// SP Public Key 192
+ NVDS_TAG_SP_PUBLIC_KEY_P192 = 0x14,
+ /// Errata adopted check
+ NVDS_TAG_ERRATA_ADOPTED = 0x15,
+ /// CQDDR Tags
+ NVDS_TAG_BASIC_THRESHOLD = 0x16,
+ NVDS_TAG_EDR_THRESHOLD = 0x17,
+ NVDS_TAG_BASIC_ALGORITHM = 0x18,
+ NVDS_TAG_EDR_ALGORITHM = 0x19,
+ NVDS_TAG_BASIC_PACKET_LUT = 0x2A,
+ NVDS_TAG_EDR_PACKET_LUT = 0x2B,
+ /// Synchronous links configuration
+ NVDS_TAG_SYNC_CONFIG = 0x2C,
+ /// PCM Settings
+ NVDS_TAG_PCM_SETTINGS = 0x2D,
+ /// Sleep algorithm duration
+ NVDS_TAG_SLEEP_ALGO_DUR = 0x2E,
+
+ /// Diagport configuration
+ NVDS_TAG_DIAG_BT_HW = 0x30,
+ NVDS_TAG_DIAG_BLE_HW = 0x31,
+ NVDS_TAG_DIAG_SW = 0x32,
+ NVDS_TAG_DIAG_PLF = 0x34,
+ NVDS_TAG_IDCSEL_PLF = 0x37,
+
+ /// RSSI threshold tags
+ NVDS_TAG_RSSI_HIGH_THR = 0x3A,
+ NVDS_TAG_RSSI_LOW_THR = 0x3B,
+ NVDS_TAG_RSSI_INTERF_THR = 0x3C,
+
+ /// BLE Channel Assessment tags
+ NVDS_TAG_BLE_CA_TIMER_DUR = 0x40,
+ NVDS_TAG_BLE_CRA_TIMER_CNT = 0x41,
+ NVDS_TAG_BLE_CA_MIN_THR = 0x42,
+ NVDS_TAG_BLE_CA_MAX_THR = 0x43,
+ NVDS_TAG_BLE_CA_NOISE_THR = 0x44,
+
+ /// AFH algorithm tags
+ NVDS_TAG_AFH_REASS_NBCH = 0x51,
+ NVDS_TAG_AFH_WINLGTH = 0x52,
+ NVDS_TAG_AFH_RSSIMIN = 0x53,
+ NVDS_TAG_AFH_PERTHRESBAD = 0x54,
+ NVDS_TAG_AFH_REASS_INT = 0x55,
+ NVDS_TAG_AFH_NMIN = 0x56,
+ NVDS_TAG_AFH_MAXADAPT = 0x57,
+ NVDS_TAG_AFH_THSMIN = 0x58,
+
+
+ NVDS_TAG_BT_LINK_KEY_FIRST = 0x60,
+ NVDS_TAG_BT_LINK_KEY_LAST = 0x67,
+
+ NVDS_TAG_BLE_LINK_KEY_FIRST = 0x70,
+ NVDS_TAG_BLE_LINK_KEY_LAST = 0x7F,
+ /// SP Private Key (Low Energy)
+ NVDS_TAG_LE_PRIVATE_KEY_P256 = 0x80,
+ /// SP Public Key (Low Energy)
+ NVDS_TAG_LE_PUBLIC_KEY_P256 = 0x81,
+ /// SP Debug: Used Fixed Private Key from NVDS (Low Energy)
+ NVDS_TAG_LE_DBG_FIXED_P256_KEY_EN = 0x82,
+ /// SP Private Key (classic BT)
+ NVDS_TAG_SP_PRIVATE_KEY_P256 = 0x83,
+ /// SP Public Key (classic BT)
+ NVDS_TAG_SP_PUBLIC_KEY_P256 = 0x84,
+
+ /// Application specific
+ NVDS_TAG_APP_SPECIFIC_FIRST = 0x90,
+ NVDS_TAG_APP_SPECIFIC_LAST = 0xAF,
+};
+
+/// List of NVDS Tag lengths
+enum NVDS_LEN
+{
+ // Definition of length associated to each parameters
+ /// Local Bd Address
+ NVDS_LEN_BD_ADDRESS = 6,
+ /// Device Name
+ NVDS_LEN_DEVICE_NAME = 24,
+ /// Low power clock drift
+ NVDS_LEN_LPCLK_DRIFT = 2,
+ /// Low power clock jitter
+ NVDS_LEN_LPCLK_JITTER = 1,
+ /// Radio Class
+ NVDS_LEN_RADIO_CLASS = 1,
+ /// Bluejay specific Settings
+ NVDS_LEN_BJ_TXCNTL1 = 4,
+
+
+ /// External wake-up time
+ NVDS_LEN_EXT_WAKEUP_TIME = 2,
+ /// Oscillator wake-up time
+ NVDS_LEN_OSC_WAKEUP_TIME = 2,
+ /// Radio wake-up time
+ NVDS_LEN_RM_WAKEUP_TIME = 2,
+ /// UART baudrate
+ NVDS_LEN_UART_BAUDRATE = 4,
+ /// Enable sleep mode
+ NVDS_LEN_SLEEP_ENABLE = 1,
+ /// Enable External Wakeup
+ NVDS_LEN_EXT_WAKEUP_ENABLE = 1,
+ /// SP Private Key 192
+ NVDS_LEN_SP_PRIVATE_KEY_P192 = 24,
+ /// SP Public Key 192
+ NVDS_LEN_SP_PUBLIC_KEY_P192 = 48,
+ /// Errata adopted check
+ NVDS_LEN_ERRATA_ADOPTED = 1,
+ /// CQDDR Tags
+ NVDS_LEN_BASIC_THRESHOLD = 70,
+ NVDS_LEN_EDR_THRESHOLD = 70,
+ NVDS_LEN_BASIC_ALGORITHM = 21,
+ NVDS_LEN_EDR_ALGORITHM = 21,
+ NVDS_LEN_BASIC_PACKET_LUT = 16,
+ NVDS_LEN_EDR_PACKET_LUT = 16,
+ /// Synchronous links configuration
+ NVDS_LEN_SYNC_CONFIG = 2,
+ /// PCM Settings
+ NVDS_LEN_PCM_SETTINGS = 8,
+ /// Sleep algorithm duration
+ NVDS_LEN_SLEEP_ALGO_DUR = 2,
+ /// Diagport configuration
+ NVDS_LEN_DIAG_BT_HW = 4,
+ NVDS_LEN_DIAG_BLE_HW = 4,
+ NVDS_LEN_DIAG_SW = 4,
+ NVDS_LEN_DIAG_PLF = 4,
+ NVDS_LEN_IDCSEL_PLF = 4,
+ /// RSSI thresholds
+ NVDS_LEN_RSSI_THR = 1,
+
+
+ NVDS_LEN_BLE_CA_TIMER_DUR = 2,
+ NVDS_LEN_BLE_CRA_TIMER_CNT = 1,
+ NVDS_LEN_BLE_CA_MIN_THR = 1,
+ NVDS_LEN_BLE_CA_MAX_THR = 1,
+ NVDS_LEN_BLE_CA_NOISE_THR = 1,
+
+ /// AFH algorithm tags
+ NVDS_LEN_AFH_REASS_NBCH = 1,
+ NVDS_LEN_AFH_WINLGTH = 1,
+ NVDS_LEN_AFH_RSSIMIN = 1,
+ NVDS_LEN_AFH_PERTHRESBAD = 1,
+ NVDS_LEN_AFH_REASS_INT = 1,
+ NVDS_LEN_AFH_NMIN = 1,
+ NVDS_LEN_AFH_MAXADAPT = 1,
+ NVDS_LEN_AFH_THSMIN = 1,
+ /// Link keys
+ NVDS_LEN_BT_LINK_KEY = 22,
+ NVDS_LEN_BLE_LINK_KEY = 48,
+
+ /// P256
+ NVDS_LEN_LE_PRIVATE_KEY_P256 = 32,
+ NVDS_LEN_LE_PUBLIC_KEY_P256 = 64,
+ NVDS_LEN_LE_DBG_FIXED_P256_KEY_EN = 1,
+ NVDS_LEN_SP_PRIVATE_KEY_P256 = 32,
+ NVDS_LEN_SP_PUBLIC_KEY_P256 = 64,
+};
+
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief Initialize NVDS.
+ * @return NVDS_OK
+ ****************************************************************************************
+ */
+uint8_t nvds_init(uint8_t *base, uint32_t len);
+
+/**
+ ****************************************************************************************
+ * @brief Look for a specific tag and return, if found and matching (in length), the
+ * DATA part of the TAG.
+ *
+ * If the length does not match, the TAG header structure is still filled, in order for
+ * the caller to be able to check the actual length of the TAG.
+ *
+ * @param[in] tag TAG to look for whose DATA is to be retrieved
+ * @param[in] length Expected length of the TAG
+ * @param[out] buf A pointer to the buffer allocated by the caller to be filled with
+ * the DATA part of the TAG
+ *
+ * @return NVDS_OK The read operation was performed
+ * NVDS_LENGTH_OUT_OF_RANGE The length passed in parameter is different than the TAG's
+ ****************************************************************************************
+ */
+uint8_t nvds_get(uint8_t tag, nvds_tag_len_t * lengthPtr, uint8_t *buf);
+
+#if (NVDS_READ_WRITE == 1)
+
+/**
+ ****************************************************************************************
+ * @brief Look for a specific tag and delete it (Status set to invalid)
+ *
+ * Implementation notes
+ * 1. The write function call return status is not handled
+ *
+ * @param[in] tag TAG to mark as deleted
+ *
+ * @return NVDS_OK TAG found and deleted
+ * NVDS_PARAM_LOCKED TAG found but can not be deleted because it is locked
+ * (others) return values from function call @ref nvds_browse_tag
+ ****************************************************************************************
+ */
+uint8_t nvds_del(uint8_t tag);
+
+/**
+ ****************************************************************************************
+ * @brief Look for a specific tag and lock it (Status lock bit set to LOCK).
+ *
+ * The write function call return status is not handled
+ *
+ * @param[in] tag TAG to mark as locked
+ *
+ * @return NVDS_OK TAG found and locked
+ * (others) return values from function call @ref nvds_browse_tag
+ ****************************************************************************************
+ */
+uint8_t nvds_lock(uint8_t tag);
+
+/**
+ ****************************************************************************************
+ * @brief This function adds a specific TAG to the NVDS.
+ *
+ * Steps:
+ * 1) parse all the TAGs to:
+ * 1.1) calculate the total size of all the valid TAGs
+ * 1.2) erase the existing TAGs that have the same ID
+ * 1.3) check if we can use the same TAG area in case of an EEPROM
+ * 1.4) check that the TAG is not locked
+ * 2) if we have to add the new TAG at the end fo the NVDS (cant use same area):
+ * 2.1) allocate the appropriate amount of memory
+ * 2.2) purge the NVDS
+ * 2.3) free the memory allocated
+ * 2.4) check that there is now enough room for the new TAG or return
+ * NO_SPACE_AVAILABLE
+ * 3) add the new TAG
+ *
+ * @param[in] tag TAG to look for whose DATA is to be retrieved
+ * @param[in] length Expected length of the TAG
+ * @param[in] buf Pointer to the buffer containing the DATA part of the TAG to add to
+ * the NVDS
+ *
+ * @return NVDS_OK New TAG correctly written to the NVDS
+ * NVDS_PARAM_LOCKED New TAG is trying to overwrite a TAG that is locked
+ * NO_SPACE_AVAILABLE New TAG can not fit in the available space in the NVDS
+ ****************************************************************************************
+ */
+uint8_t nvds_put(uint8_t tag, nvds_tag_len_t length, uint8_t *buf);
+
+#endif //(NVDS_READ_WRITE == 1)
+
+/// @} NVDS
+
+#endif // _NVDS_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/prf.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/prf.h
new file mode 100644
index 0000000000..ef445c5704
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/prf.h
@@ -0,0 +1,308 @@
+/**
+ ****************************************************************************************
+ *
+ * @file prf.h
+ *
+ * @brief Entry point of profile header file.
+ *
+ * Used to manage life cycle of profiles
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ ****************************************************************************************
+ */
+
+
+#ifndef _PRF_H_
+#define _PRF_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup PROFILE PROFILES
+ * @ingroup ROOT
+ * @brief Bluetooth Low Energy Host Profiles
+ *
+ * The PROFILE of the stack contains the profile layers (@ref PROX "PROXIMITY",
+ * @ref HTP "HTP",@ref FIND "FIND ME" @ref BPS "Blood Pressure").
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @addtogroup PRF
+ * @ingroup PROFILE
+ * @brief Definitions of Profile management API
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "rwip_config.h"
+
+#if (BLE_PROFILES)
+
+#include "ke_task.h"
+#include "gapm_task.h"
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/**
+ * Profile task fields
+ *
+ * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+ * +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
+ * | MI | TASK Number |
+ * +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
+ *
+ * Bit [0-14] : Task number value
+ * Bit [15] : Task is multi-instantiated (Connection index is conveyed)
+ */
+enum prf_perm_mask
+{
+ /// Task number value
+ PERM_MASK_PRF_TASK = 0x7FFF,
+ PERM_POS_PRF_TASK = 0,
+ /// Task is multi-instantiated
+ PERM_MASK_PRF_MI = 0x8000,
+ PERM_POS_PRF_MI = 15,
+};
+/*
+ * TYPE DEFINITIONS
+ ****************************************************************************************
+ */
+
+
+/// Profile Environment Data
+typedef struct prf_env
+{
+ /// Application Task Number - if MSB bit set, Multi-Instantiated task
+ ke_task_id_t app_task;
+ /// Profile Task Number - if MSB bit set, Multi-Instantiated task
+ ke_task_id_t prf_task;
+} prf_env_t;
+
+
+
+/// Profile task environment variable definition to dynamically allocate a Task.
+struct prf_task_env
+{
+ /// Profile Task description
+ struct ke_task_desc desc;
+ /// pointer to the allocated memory used by profile during runtime.
+ prf_env_t* env;
+ /// Profile Task Number
+ ke_task_id_t task;
+ /// Profile Task Identifier
+ ke_task_id_t id;
+};
+
+/**
+ ****************************************************************************************
+ * @brief Initialization of the Profile module.
+ * This function performs all the initializations of the Profile module.
+ * - Creation of database (if it's a service)
+ * - Allocation of profile required memory
+ * - Initialization of task descriptor to register application
+ * - Task State array
+ * - Number of tasks
+ * - Default task handler
+ *
+ * @param[out] env Collector or Service allocated environment data.
+ * @param[in|out] start_hdl Service start handle (0 - dynamically allocated), only applies for services.
+ * @param[in] app_task Application task number.
+ * @param[in] sec_lvl Security level (AUTH, EKS and MI field of @see enum attm_value_perm_mask)
+ * @param[in] param Configuration parameters of profile collector or service (32 bits aligned)
+ *
+ * @return status code to know if profile initialization succeed or not.
+ ****************************************************************************************
+ */
+typedef uint8_t (*prf_init_fnct) (struct prf_task_env* env, uint16_t* start_hdl, uint16_t app_task, uint8_t sec_lvl, void* params);
+
+/**
+ ****************************************************************************************
+ * @brief Destruction of the Profile module - due to a reset for instance.
+ * This function clean-up allocated memory (attribute database is destroyed by another
+ * procedure)
+ *
+ * @param[in|out] env Collector or Service allocated environment data.
+ ****************************************************************************************
+ */
+typedef void (*prf_destroy_fnct) (struct prf_task_env* env);
+
+/**
+ ****************************************************************************************
+ * @brief Handles Connection creation
+ *
+ * @param[in|out] env Collector or Service allocated environment data.
+ * @param[in] conidx Connection index
+ ****************************************************************************************
+ */
+typedef void (*prf_create_fnct) (struct prf_task_env* env, uint8_t conidx);
+
+/**
+ ****************************************************************************************
+ * @brief Handles Disconnection
+ *
+ * @param[in|out] env Collector or Service allocated environment data.
+ * @param[in] conidx Connection index
+ * @param[in] reason Detach reason
+ ****************************************************************************************
+ */
+typedef void (*prf_cleanup_fnct) (struct prf_task_env* env, uint8_t conidx, uint8_t reason);
+
+/// Profile task callbacks.
+struct prf_task_cbs
+{
+ /// Initialization callback
+ prf_init_fnct init;
+ /// Destroy profile callback
+ prf_destroy_fnct destroy;
+ /// Connection callback
+ prf_create_fnct create;
+ /// Disconnection callback
+ prf_cleanup_fnct cleanup;
+};
+
+
+/// Profile Manager environment structure
+struct prf_env_tag
+{
+ /// Array of profile tasks that can be managed by Profile manager.
+ struct prf_task_env prf[BLE_NB_PROFILES];
+};
+
+/*
+ * MACROS
+ ****************************************************************************************
+ */
+
+
+/*
+ * GLOBAL VARIABLE DECLARATIONS
+ ****************************************************************************************
+ */
+extern struct prf_env_tag prf_env;
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief Perform Profile initialization
+ *
+ * @param[in] reset Reset requested or basic initialization
+ ****************************************************************************************
+ */
+void prf_init(bool reset);
+
+
+/**
+ ****************************************************************************************
+ * @brief Create Profile (collector or service) task creation and initialize it.
+ *
+ * @param[in|out] params Collector or Service parameter used for profile task creation
+ * @param[out] prf_task Allocated Task number
+ *
+ * @return status of adding profile task
+ ****************************************************************************************
+ */
+uint8_t prf_add_profile(struct gapm_profile_task_add_cmd * params, ke_task_id_t *prf_task);
+
+
+/**
+ ****************************************************************************************
+ * @brief Link creation event, update profiles states.
+ *
+ * @param[in] conidx connection index
+ *
+ ****************************************************************************************
+ */
+void prf_create(uint8_t conidx);
+
+/**
+ ****************************************************************************************
+ * @brief Link disconnection event, clean-up profiles.
+ *
+ * @param[in] conidx connection index
+ * @param[in] reason detach reason
+ *
+ ****************************************************************************************
+ */
+void prf_cleanup(uint8_t conidx, uint8_t reason);
+
+
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve environment variable allocated for a profile
+ *
+ * @param[in] prf_id Profile Task Identifier
+ *
+ * @return Environment variable allocated for a profile
+ ****************************************************************************************
+ */
+prf_env_t* prf_env_get(uint16_t prf_id);
+
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve source profile task number value
+ *
+ * @param[in] env Profile Environment
+ * @param[in] conidx Connection index
+ *
+ * @return Source profile task number value
+ ****************************************************************************************
+ */
+ke_task_id_t prf_src_task_get(prf_env_t* env, uint8_t conidx);
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve destination application task number value
+ *
+ * @param[in] env Profile Environment
+ * @param[in] conidx Connection index
+ *
+ * @return Destination application task number value
+ ****************************************************************************************
+ */
+ke_task_id_t prf_dst_task_get(prf_env_t* env, uint8_t conidx);
+
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve Task Identifier from Task number
+ * (automatically update index of task in returned task id)
+ *
+ * @param task Task number
+ * @return Task Identifier
+ ****************************************************************************************
+ */
+ke_task_id_t prf_get_id_from_task(ke_msg_id_t task);
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve Task Number from Task Identifier
+ * (automatically update index of task in returned task id)
+ *
+ * @param id Task Identifier
+ * @return Task Number
+ ****************************************************************************************
+ */
+ke_task_id_t prf_get_task_from_id(ke_msg_id_t id);
+
+#endif // (BLE_PROFILES)
+
+/// @} PRF
+
+#endif /* _PRF_H_ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/prf_types.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/prf_types.h
new file mode 100644
index 0000000000..26009304af
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/prf_types.h
@@ -0,0 +1,273 @@
+/**
+ ****************************************************************************************
+ *
+ * @file prf_types.h
+ *
+ * @brief Header file - Profile Types
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+
+#ifndef _PRF_TYPES_H_
+#define _PRF_TYPES_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup PRF_TYPES
+ * @ingroup PROFILE
+ * @brief Definitions of shared profiles types
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "att.h"
+//#include "compiler.h"
+#include "ble_arch.h"
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/// Attribute is mandatory
+#define ATT_MANDATORY (0xFF)
+/// Attribute is optional
+#define ATT_OPTIONAL (0x00)
+
+/// Characteristic Presentation Format Descriptor Size
+#define PRF_CHAR_PRES_FMT_SIZE (7)
+
+
+/// Possible values for setting client configuration characteristics
+enum prf_cli_conf
+{
+ /// Stop notification/indication
+ PRF_CLI_STOP_NTFIND = 0x0000,
+ /// Start notification
+ PRF_CLI_START_NTF,
+ /// Start indication
+ PRF_CLI_START_IND,
+};
+
+/// Possible values for setting server configuration characteristics
+enum prf_srv_conf
+{
+ /// Stop Broadcast
+ PRF_SRV_STOP_BCST = 0x0000,
+ /// Start Broadcast
+ PRF_SRV_START_BCST,
+};
+
+/// Connection type
+enum prf_con_type
+{
+ ///Discovery type connection
+ PRF_CON_DISCOVERY = 0x00,
+ /// Normal type connection
+ PRF_CON_NORMAL = 0x01,
+};
+
+enum prf_svc_type
+{
+ PRF_PRIMARY_SERVICE = 0x00,
+ PRF_SECONDARY_SERVICE = 0x01
+};
+
+/*
+ * TYPE DEFINITIONS
+ ****************************************************************************************
+ */
+
+/**
+ * Characteristic Presentation Format Descriptor structure
+ * Packed size is PRF_CHAR_PRES_FMT_SIZE
+ */
+/// characteristic presentation information
+struct prf_char_pres_fmt
+{
+ /// Unit (The Unit is a UUID)
+ uint16_t unit;
+ /// Description
+ uint16_t description;
+ /// Format
+ uint8_t format;
+ /// Exponent
+ uint8_t exponent;
+ /// Name space
+ uint8_t name_space;
+};
+
+/**
+ * date and time structure
+ * size = 7 bytes
+ */
+/// Time profile information
+struct prf_date_time
+{
+ /// year time element
+ uint16_t year;
+ /// month time element
+ uint8_t month;
+ /// day time element
+ uint8_t day;
+ /// hour time element
+ uint8_t hour;
+ /// minute time element
+ uint8_t min;
+ /// second time element
+ uint8_t sec;
+};
+
+/**
+ * SFLOAT: Short Floating Point Type
+ *
+ * +----------+----------+---------+
+ * | Exponent | Mantissa | Total |
+ * +------+----------+----------+---------+
+ * | size | 4 bits | 12 bits | 16 bits |
+ * +------+----------+----------+---------+
+ */
+typedef uint16_t prf_sfloat;
+
+
+
+/// Attribute information
+struct prf_att_info
+{
+ /// Attribute Handle
+ uint16_t handle;
+ /// Attribute length
+ uint16_t length;
+ /// Status of request
+ uint8_t status;
+ /// Attribute value
+ uint8_t value[__ARRAY_EMPTY];
+};
+
+
+
+
+/// service handles
+struct prf_svc
+{
+ /// start handle
+ uint16_t shdl;
+ /// end handle
+ uint16_t ehdl;
+};
+
+/// service handles
+struct prf_incl_svc
+{
+ /// attribute handle
+ uint16_t handle;
+ /// included service start handle
+ uint16_t start_hdl;
+ /// included service end handle
+ uint16_t end_hdl;
+ /// UUID length
+ uint8_t uuid_len;
+ /// UUID
+ uint8_t uuid[ATT_UUID_128_LEN];
+};
+
+/// characteristic info
+struct prf_char_inf
+{
+ /// Characteristic handle
+ uint16_t char_hdl;
+ /// Value handle
+ uint16_t val_hdl;
+ /// Characteristic properties
+ uint8_t prop;
+ /// End of characteristic offset
+ uint8_t char_ehdl_off;
+};
+
+/// characteristic description
+struct prf_char_desc_inf
+{
+ /// Descriptor handle
+ uint16_t desc_hdl;
+};
+
+
+/// Characteristic definition
+struct prf_char_def
+{
+ /// Characteristic UUID
+ uint16_t uuid;
+ /// Requirement Attribute Flag
+ uint8_t req_flag;
+ /// Mandatory Properties
+ uint8_t prop_mand;
+};
+
+/// Characteristic definition uuid128
+struct prf_char_uuid128_def
+{
+ /// Service UUID Length
+ uint8_t uuid_len;
+ /// 128 bits UUID LSB First
+ uint8_t uuid[ATT_UUID_128_LEN];
+ /// Requirement Attribute Flag
+ uint8_t req_flag;
+ /// Mandatory Properties
+ uint8_t prop_mand;
+};
+
+/// Characteristic Descriptor definition
+struct prf_char_desc_def
+{
+ /// Characteristic Descriptor uuid
+ uint16_t uuid;
+ /// requirement attribute flag
+ uint8_t req_flag;
+ /// Corresponding characteristic code
+ uint8_t char_code;
+};
+
+/// Characteristic Descriptor definition uuid128
+struct prf_char_desc_uuid128_def
+{
+ /// Service UUID Length
+ uint8_t uuid_len;
+ /// 128 bits UUID LSB First
+ uint8_t uuid[ATT_UUID_128_LEN];
+ /// requirement attribute flag
+ uint8_t req_flag;
+ /// Corresponding characteristic code
+ uint8_t char_code;
+};
+
+/// Message structure used to inform APP that a profile client role has been disabled
+struct prf_client_disable_ind
+{
+ /// Status
+ uint8_t status;
+};
+
+
+
+/// Message structure used to inform APP that an error has occured in the profile server role task
+struct prf_server_error_ind
+{
+ /// Message ID
+ uint16_t msg_id;
+ /// Status
+ uint8_t status;
+};
+
+
+/// @} PRF_TYPES
+
+#endif /* _PRF_TYPES_H_ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/prf_utils.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/prf_utils.h
new file mode 100644
index 0000000000..2fc2dc8859
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/prf_utils.h
@@ -0,0 +1,349 @@
+/**
+ ****************************************************************************************
+ *
+ * @file prf_utils.h
+ *
+ * @brief Header file - Profile Utilities
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+
+#ifndef _PRF_UTILS_H_
+#define _PRF_UTILS_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup PRF_UTILS
+ * @ingroup PROFILE
+ *
+ * @brief Definitions of shared profiles functions that can be used by several profiles
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+
+#include "rwip_config.h"
+#if (BLE_SERVER_PRF || BLE_CLIENT_PRF)
+#include "ke_msg.h"
+#include "prf_types.h"
+#include "gattc_task.h"
+#include "gapc.h"
+#include "gapc_task.h"
+#include "attm.h"
+#include "prf.h"
+#endif /* (BLE_SERVER_PRF || BLE_CLIENT_PRF) */
+
+/*
+ * MACROS
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief Macro used to called the prf_client_get_env function.
+ *
+ * @param prf_id Profile Task ID (In Upper case, ex: HTPC, DISC, ...)
+ * @param type Profile task type (In lower case, ex: htpc, disc, ...)
+ ****************************************************************************************
+ */
+#define PRF_ENV_GET(prf_id, type) \
+ ((struct type ## _env_tag *)prf_env_get((TASK_ID_##prf_id)))
+
+
+
+
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+#if (BLE_BATT_SERVER)
+/**
+ ****************************************************************************************
+ * @brief Pack Characteristic Presentation Format descriptor value
+ ****************************************************************************************
+ */
+void prf_pack_char_pres_fmt(uint8_t *packed_val, const struct prf_char_pres_fmt* char_pres_fmt);
+#endif // (BLE_BATT_SERVER)
+
+#if (BLE_BATT_CLIENT)
+/**
+ ****************************************************************************************
+ * @brief Unpack Characteristic Presentation Format descriptor value
+ ****************************************************************************************
+ */
+void prf_unpack_char_pres_fmt(const uint8_t *packed_val, struct prf_char_pres_fmt* char_pres_fmt);
+#endif // (BLE_BATT_CLIENT)
+
+#if (BLE_CLIENT_PRF)
+/**
+ ****************************************************************************************
+ * @brief Request peer device to read an attribute
+ *
+ * @param[in] prf_env Pointer to profile information
+ *
+ * @param conidx Connection index
+ * @param shdl Search Start Handle
+ * @param ehdl Search End Handle
+ *
+ * @param valhdl Value Handle
+ *
+ * @note: if attribute is invalid, nothing is registered
+ ****************************************************************************************
+ */
+void prf_read_char_send(prf_env_t *prf_env, uint8_t conidx,
+ uint16_t shdl, uint16_t ehdl, uint16_t valhdl);
+
+
+/**
+ ****************************************************************************************
+ * @brief register attribute handle in GATT
+ *
+ * @param[in] prf_env Pointer to profile information
+ *
+ * @param conidx Connection index
+ * @param svc Service to register
+ *
+ * @note: if attribute is invalid, nothing is registered
+ ****************************************************************************************
+ */
+void prf_register_atthdl2gatt(prf_env_t *prf_env, uint8_t conidx, struct prf_svc *svc);
+
+/**
+ ****************************************************************************************
+ * @brief Unregister attribute handle in GATT
+ *
+ * @param[in] prf_env Pointer to profile information
+ *
+ * @param conidx Connection index
+ * @param svc Service to register
+ *
+ * @note: if attribute is invalid, nothing is registered
+ ****************************************************************************************
+ */
+void prf_unregister_atthdl2gatt(prf_env_t *prf_env, uint8_t conidx, struct prf_svc *svc);
+
+/**
+ ****************************************************************************************
+ * @brief Request service discovery on peer device.
+ *
+ * This request will be used to retrieve start and end handles of the service.
+ *
+ * @param[in] prf_env Pointer to profile information
+ *
+ * @param conidx Connection index
+ * @param uuid Service UUID
+ ****************************************************************************************
+ */
+void prf_disc_svc_send(prf_env_t *prf_env,uint8_t conidx, uint16_t uuid);
+
+
+/**
+ ****************************************************************************************
+ * @brief Write peer characteristic using GATT.
+ *
+ * It will request write modification of peer handle
+ *
+ * @param[in] prf_env Pointer to profile information
+ * @param[in] conidx Connection index
+ * @param[in] handle Peer handle to modify
+ * @param[in] value New Peer handle value
+ * @param[in] length Value length
+ ****************************************************************************************
+ */
+void prf_gatt_write(prf_env_t *prf_env, uint8_t conidx,
+ uint16_t handle, uint8_t* value, uint16_t length, uint8_t operation);
+
+/**
+ ****************************************************************************************
+ * @brief Modify peer client configuration descriptor using GATT
+ *
+ * It will request write modification of peer client configuration descriptor handle
+ *
+ * @param[in] prf_env Pointer to profile information
+ *
+ * @param[in] conidx Connection index
+ * @param[in] handle Peer client configuration descriptor handle to modify
+ *
+ * @param[in] ntf_ind_cfg Indication/Notification configuration
+ ****************************************************************************************
+ */
+void prf_gatt_write_ntf_ind(prf_env_t *prf_env, uint8_t conidx, uint16_t handle,
+ uint16_t ntf_ind_cfg);
+
+/**
+ ****************************************************************************************
+ * @brief Check service characteristic validity
+ *
+ * For each characteristic in service it verifies handles.
+ *
+ * If some handles are not present, it checks if they shall be present or they are optional.
+ *
+ * @param nb_chars Number of Characteristics in the service
+ * @param chars Characteristics values (char handles, val handles, properties)
+ * @param chars_req Characteristics requirements.
+ *
+ * @return 0x1 if service is valid, 0x00 else.
+ ****************************************************************************************
+ */
+uint8_t prf_check_svc_char_validity(uint8_t nb_chars,
+ const struct prf_char_inf* chars,
+ const struct prf_char_def* chars_req);
+
+/**
+ ****************************************************************************************
+ * @brief Check service characteristic validity
+ *
+ * For each characteristic in service it verifies handles.
+ *
+ * If some handles are not present, it checks if they shall be present or they are optional.
+ *
+ * @param nb_chars Number of Characteristics in the service
+ * @param chars Characteristics values (char handles, val handles, properties)
+ * @param chars_req Characteristics requirements.
+ *
+ * @return 0x1 if service is valid, 0x00 else.
+ ****************************************************************************************
+ */
+uint8_t prf_check_svc_char_uuid128_validity(uint8_t nb_chars,
+ const struct prf_char_inf* chars,
+ const struct prf_char_uuid128_def* chars_req);
+
+/**
+ ****************************************************************************************
+ * @brief Check service characteristic descriptors validity
+ *
+ * For each characteristic descriptors in service it verifies handles.
+ *
+ * If some handles are not present, according to characteristic properties it verify if
+ * descriptor is optional or not.
+ *
+ * @param descs_size Number of Characteristic descriptors in the service
+ * @param descs Characteristic descriptors values (handles)
+ * @param descs_req Characteristics descriptors requirements.
+ *
+ * @return 0x1 if service is valid, 0x00 else.
+ ****************************************************************************************
+ */
+uint8_t prf_check_svc_char_desc_validity(uint8_t descs_size,
+ const struct prf_char_desc_inf* descs,
+ const struct prf_char_desc_def* descs_req,
+ const struct prf_char_inf* chars);
+
+/**
+ ****************************************************************************************
+ * @brief Check service characteristic descriptors validity
+ *
+ * For each characteristic descriptors in service it verifies handles.
+ *
+ * If some handles are not present, according to characteristic properties it verify if
+ * descriptor is optional or not.
+ *
+ * @param descs_size Number of Characteristic descriptors in the service
+ * @param descs Characteristic descriptors values (handles)
+ * @param descs_req Characteristics descriptors requirements.
+ *
+ * @return 0x1 if service is valid, 0x00 else.
+ ****************************************************************************************
+ */
+uint8_t prf_check_svc_char_desc_uuid128_validity(uint8_t descs_size,
+ const struct prf_char_desc_inf* descs,
+ const struct prf_char_desc_uuid128_def* descs_req,
+ const struct prf_char_inf* chars);
+
+/**
+ ****************************************************************************************
+ * @brief Extract information of the service according to the service description
+ *
+ * @param param Service information
+ * @param nb_chars Length of provided arrays (chars and chars_req)
+ * @param chars_req Characteristics requirements
+ * @param chars Characteristics
+ * @param nb_descs Length of provided arrays (descs and descs_req)
+ * @param descs_req Descriptors requirements
+ * @param descs Descriptors
+ ****************************************************************************************
+ */
+void prf_extract_svc_info(const struct gattc_sdp_svc_ind* param,
+ uint8_t nb_chars, const struct prf_char_def* chars_req, struct prf_char_inf* chars,
+ uint8_t nb_descs, const struct prf_char_desc_def* descs_req, struct prf_char_desc_inf* descs);
+
+/**
+ ****************************************************************************************
+ * @brief Extract information of the service according to the service description
+ *
+ * @param param Service information
+ * @param nb_chars Length of provided arrays (chars and chars_req)
+ * @param chars_req Characteristics requirements in UUID128 format
+ * @param chars Characteristics
+ * @param nb_descs Length of provided arrays (descs and descs_req)
+ * @param descs_req Descriptors requirements in UUID128 format
+ * @param descs Descriptors
+ ****************************************************************************************
+ */
+void prf_extract_svc_uuid128_info(const struct gattc_sdp_svc_ind* param,
+ uint8_t nb_chars, const struct prf_char_uuid128_def* chars_uuid128_req, struct prf_char_inf* chars,
+ uint8_t nb_descs, const struct prf_char_desc_uuid128_def* descs_uuid128_req, struct prf_char_desc_inf* descs);
+
+#endif //(BLE_CLIENT_PRF)
+
+
+#if (BLE_CLIENT_PRF || BLE_TIP_SERVER || BLE_AN_SERVER || BLE_PAS_SERVER)
+
+/**
+ ****************************************************************************************
+ * @brief The function is used to send information about peer attribute value
+ *
+ * @param[in] prf_env Pointer to the profile environment variable
+ * @param[in] conidx Connection index
+ * @param[in] msg_id Profile message ID to trigger
+ * @param[in] status Response status code
+ * @param[in] read_ind GATT read message indication
+ ****************************************************************************************
+ */
+void prf_client_att_info_rsp(prf_env_t *prf_env, uint8_t conidx, uint16_t msg_id,
+ uint8_t status, struct gattc_read_ind const* read_ind);
+
+#endif //(BLE_CLIENT_PRF || BLE_TIP_SERVER || BLE_AN_SERVER || BLE_PAS_SERVER)
+
+#if (BLE_SERVER_PRF || BLE_CLIENT_PRF)
+/**
+ ****************************************************************************************
+ * @brief Pack date time value
+ *
+ * @param[out] packed_date packed date time
+ * @param[in] date_time structure date time
+ *
+ * @return size of packed value
+ ****************************************************************************************
+ */
+uint8_t prf_pack_date_time(uint8_t *packed_date, const struct prf_date_time* date_time);
+
+/**
+ ****************************************************************************************
+ * @brief Unpack date time value
+ *
+ * @param[in] packed_date packed date time
+ * @param[out] date_time structure date time
+ *
+ * @return size of packed value
+ ****************************************************************************************
+ */
+uint8_t prf_unpack_date_time(uint8_t *packed_date, struct prf_date_time* date_time);
+
+#endif /* (BLE_SERVER_PRF || BLE_CLIENT_PRF) */
+
+/// @} prf_utils
+
+#endif /* _PRF_UTILS_H_ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwapp_config.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwapp_config.h
new file mode 100644
index 0000000000..3ed1b7a561
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwapp_config.h
@@ -0,0 +1,96 @@
+/**
+ ****************************************************************************************
+ *
+ * @file rwapp_config.h
+ *
+ * @brief Application configuration definition
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ ****************************************************************************************
+ */
+
+
+#ifndef _RWAPP_CONFIG_H_
+#define _RWAPP_CONFIG_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup app
+ * @brief Application configuration definition
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/******************************************************************************************/
+/* ------------------------- BLE APPLICATION SETTINGS -----------------------------*/
+/******************************************************************************************/
+
+
+/// Health Thermometer Application
+#if defined(CFG_APP_HT)
+#define BLE_APP_HT 1
+#else // defined(CFG_APP_HT)
+#define BLE_APP_HT 0
+#endif // defined(CFG_APP_HT)
+
+/// HID Application
+#if defined(CFG_APP_HID)
+#define BLE_APP_HID 1
+#else // defined(CFG_APP_HID)
+#define BLE_APP_HID 0
+#endif // defined(CFG_APP_HID)
+
+/// DIS Application
+#if defined(CFG_APP_DIS)
+#define BLE_APP_DIS 1
+#else // defined(CFG_APP_DIS)
+#define BLE_APP_DIS 0
+#endif // defined(CFG_APP_DIS)
+
+/// Time Application
+#if defined(CFG_APP_TIME)
+#define BLE_APP_TIME 1
+#else // defined(CFG_APP_TIME)
+#define BLE_APP_TIME 0
+#endif // defined(CFG_APP_TIME)
+
+/// Battery Service Application
+#if defined(CFG_PRF_BASS)
+#define BLE_APP_BATT 1
+#else
+#define BLE_APP_BATT 0
+#endif // defined(CFG_PRF_BCSS)
+
+/// Security Application
+#if (defined(CFG_APP_SEC) || BLE_APP_HID || defined(BLE_APP_AM0))
+#define BLE_APP_SEC 1
+//#define BLE_APP_SEC_CON 1
+#else // defined(CFG_APP_SEC)
+#define BLE_APP_SEC 0
+#endif // defined(CFG_APP_SEC)
+
+/// user-defined
+#if defined(CFG_APP_USER)
+#define BLE_APP_USER 1
+#else // defined(CFG_APP_USER)
+#define BLE_APP_USER 0
+#endif // defined(CFG_APP_USER)
+
+
+
+/// @} rwapp_config
+
+#endif /* _RWAPP_CONFIG_H_ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwble_config.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwble_config.h
new file mode 100644
index 0000000000..ae12db561d
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwble_config.h
@@ -0,0 +1,282 @@
+/**
+ ****************************************************************************************
+ *
+ * @file rwble_config.h
+ *
+ * @brief Configuration of the BLE protocol stack (max number of supported connections,
+ * type of partitioning, etc.)
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef RWBLE_CONFIG_H_
+#define RWBLE_CONFIG_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup ROOT
+ * @{
+ * @name BLE stack configuration
+ * @{
+ ****************************************************************************************
+ */
+
+#include "rwip_config.h"
+
+
+/******************************************************************************************/
+/* ------------------------- COEXISTENCE SETUP ------------------------------------*/
+/******************************************************************************************/
+
+///WLAN coex
+#define RW_BLE_WLAN_COEX RW_WLAN_COEX
+///WLAN test mode
+#define RW_BLE_WLAN_COEX_TEST RW_WLAN_COEX_TEST
+
+/// MWS Coexistence
+#define RW_BLE_MWS_COEX RW_MWS_COEX
+///WLAN test mode
+#define RW_BLE_MWS_COEX_TEST RW_MWS_COEX_TEST
+
+///To let the HW using the default values set in the registers
+#define RW_BLE_PTI_PRIO_AUTO 15
+
+
+
+/// PTI configuration index
+enum rwble_pti_config_idx
+{
+ BLE_PTI_CON_IDX,
+ BLE_PTI_ADV_IDX,
+ BLE_PTI_SCAN_IDX,
+ BLE_PTI_INIT_IDX,
+ BLE_PTI_IDX_MAX
+};
+
+
+/******************************************************************************************/
+/* -------------------------- DEBUG SETUP ----------------------------------------*/
+/******************************************************************************************/
+
+/// Flag indicating if tester emulator is available or not
+#if defined(CFG_BLE_TESTER)
+/// Flag indicating if tester emulator is available or not
+#define BLE_TESTER 1
+#else // defined (CFG_BLE_TESTER)
+#define BLE_TESTER 0
+#endif // defined (CFG_BLE_TESTER)
+
+/// Flag indicating if debug mode is activated or not
+#define BLE_DEBUG RW_DEBUG
+#define BLE_SWDIAG RW_SWDIAG
+
+/// Flag indicating if Read/Write memory commands are supported or not
+#define BLE_DEBUG_MEM RW_DEBUG_MEM
+
+/// Flag indicating if Flash debug commands are supported or not
+#define BLE_DEBUG_FLASH RW_DEBUG_FLASH
+
+/// Flag indicating if NVDS feature is supported or not
+#define BLE_DEBUG_NVDS RW_DEBUG_NVDS
+
+/// Flag indicating if CPU stack profiling commands are supported or not
+#define BLE_DEBUG_STACK_PROF RW_DEBUG_STACK_PROF
+
+/******************************************************************************************/
+/* ------------------------- BLE SETUP --------------------------------------------*/
+/******************************************************************************************/
+
+/// Exchange memory presence
+#define BLE_EM_PRESENT (BLE_EMB_PRESENT)
+
+#define BLE_TEST_MODE_SUPPORT (1)
+
+/// Number of devices in the white list
+#define BLE_WHITELIST_MAX (BLE_CONNECTION_MAX + 2)
+
+/// Number of devices in the Resolution Address List
+/// This have to be tuned according to the core frequency. Worst case is having in scan mode
+/// all IRK and valid in resolving list and device receive a Direct Adv Report that contains
+/// RPAs for InitA and AdvA
+#define BLE_RESOL_ADDR_LIST_MAX (3)
+
+/// Connection handle max
+#define BLE_MAX_CONHDL (BLE_CONNECTION_MAX)
+
+/// Number of devices capacity for the scan filtering
+#if (BLE_CENTRAL || BLE_OBSERVER)
+#define BLE_DUPLICATE_FILTER_MAX (10)
+#endif //(BLE_CENTRAL || BLE_OBSERVER)
+
+/** Size of the heap
+ * - For KE messages: (N+1) x 256
+ * - For LLC environment: N x 80 Bytes
+ * - For LLD events/intervals: (2N+1) x (80 + 16)
+ */
+#if (BLE_CENTRAL || BLE_PERIPHERAL)
+ #define BLE_HEAP_MSG_SIZE (256 * (BLE_CONNECTION_MAX+1) + 80 * (BLE_CONNECTION_MAX) + 96 * (2*BLE_CONNECTION_MAX+1))
+ /// Size required to allocate environment variable for one link
+ #define BLE_HEAP_ENV_SIZE (sizeof(struct llc_env_tag) + 4)
+#else
+ #define BLE_HEAP_MSG_SIZE (256)
+ /// Size required to allocate environment variable for one link
+ #define BLE_HEAP_ENV_SIZE (4)
+#endif /* #if (BLE_CENTRAL || BLE_PERIPHERAL) */
+
+
+/******************************************************************************************/
+/* -------------------------- RADIO SETUP ----------------------------------------*/
+/******************************************************************************************/
+/// Class of device
+#define RF_CLASS1 0
+
+/******************************************************************************************/
+/* -------------------------- REGISTER SETUP --------------------------------------*/
+/******************************************************************************************/
+
+#define RW_BLE_CUST1_INST 0
+
+/******************************************************************************************/
+/* -------------------------- SCHEDULING SETUP --------------------------------------*/
+/******************************************************************************************/
+
+/// EA programming latency for only 1 activity
+#define RWBLE_PROG_LATENCY_DFT (2)
+/// EA asap latency
+#define RWBLE_ASAP_LATENCY (2)
+/// Instant value mask
+#define RWBLE_INSTANT_MASK (0x0000FFFF)
+
+/******************************************************************************************/
+/* ----------------------- SUPPORTED HCI COMMANDS --------------------------------*/
+/******************************************************************************************/
+
+//byte0
+#define BLE_CMDS_BYTE0 BLE_DISC_CMD
+//byte2
+#define BLE_CMDS_BYTE2 BLE_RD_REM_VERS_CMD
+//byte5
+#define BLE_CMDS_BYTE5 (BLE_SET_EVT_MSK_CMD | BLE_RESET_CMD)
+//byte10
+#define BLE_CMDS_BYTE10 (BLE_HL_NB_CMP_PKT_CMD | BLE_RD_TX_PWR_CMD\
+ |BLE_HL_BUF_SIZE_CMD | BLE_SET_CTRL_TO_HL_FCTRL_CMD)
+//byte14
+#define BLE_CMDS_BYTE14 (BLE_RD_LOC_VERS_CMD | BLE_RD_LOC_SUP_FEAT_CMD\
+ |BLE_RD_BUF_SIZE_CMD)
+//byte15
+#define BLE_CMDS_BYTE15 (BLE_RD_BD_ADDR_CMD | BLE_RD_RSSI_CMD)
+#if !(BLE_QUALIF)
+//byte22
+#define BLE_CMDS_BYTE22 (BLE_SET_EVT_MSK_PG2_CMD)
+#else
+//byte22
+#define BLE_CMDS_BYTE22 0
+#endif
+//byte25
+#define BLE_CMDS_BYTE25 (BLE_LE_SET_EVT_MSK_CMD | BLE_LE_RD_BUF_SIZE_CMD\
+ |BLE_LE_RD_LOC_SUP_FEAT_CMD | BLE_LE_SET_RAND_ADDR_CMD\
+ |BLE_LE_SET_ADV_PARAM_CMD | BLE_LE_RD_ADV_TX_PWR_CMD\
+ |BLE_LE_SET_ADV_DATA_CMD)
+//byte26
+#define BLE_CMDS_BYTE26 (BLE_LE_SET_SC_RSP_DATA_CMD | BLE_LE_SET_ADV_EN_CMD\
+ |BLE_LE_SET_SC_PARAM_CMD | BLE_LE_SET_SC_EN_CMD\
+ |BLE_LE_CREAT_CNX_CMD | BLE_LE_CREAT_CNX_CNL_CMD\
+ |BLE_LE_RD_WL_SIZE_CMD | BLE_LE_CLEAR_WL_CMD)
+//byte27
+#define BLE_CMDS_BYTE27 (BLE_LE_ADD_DEV_WL_CMD | BLE_LE_REM_DEV_WL_CMD\
+ |BLE_LE_CNX_UPDATE_CMD | BLE_LE_SET_HL_CH_CLASS_CMD\
+ |BLE_LE_RD_CH_MAP_CMD | BLE_LE_RD_REM_USED_FEAT_CMD\
+ |BLE_LE_ENCRYPT_CMD | BLE_LE_RAND_CMD)
+//byte28
+#define BLE_CMDS_BYTE28 (BLE_LE_START_ENC_CMD | BLE_LE_LTK_REQ_RPLY_CMD\
+ |BLE_LE_LTK_REQ_NEG_RPLY_CMD | BLE_LE_RD_SUPP_STATES_CMD\
+ |BLE_LE_RX_TEST_CMD | BLE_LE_TX_TEST_CMD\
+ |BLE_LE_STOP_TEST_CMD)
+#if !(BLE_QUALIF)
+//byte32
+#define BLE_CMDS_BYTE32 (BLE_RD_AUTH_PAYL_TO_CMD | BLE_WR_AUTH_PAYL_TO_CMD)
+//byte33
+#define BLE_CMDS_BYTE33 (BLE_LE_REM_CON_PARA_REQ_RPLY_CMD | BLE_LE_REM_CON_PARA_REQ_NEG_RPLY_CMD\
+ | BLE_LE_SET_DATA_LEN_CMD | BLE_LE_RD_SUGGTED_DFT_DATA_LEN_CMD)
+//byte34
+#define BLE_CMDS_BYTE34 ( BLE_LE_WR_SUGGTED_DFT_DATA_LEN_CMD \
+ | BLE_LE_RD_LOC_P256_PUB_KEY_CMD \
+ | BLE_LE_GEN_DH_KEY_CMD \
+ | BLE_LE_ADD_DEV_TO_RESOLV_LIST_CMD \
+ | BLE_LE_REM_DEV_FROM_RESOLV_LIST_CMD \
+ | BLE_LE_CLEAR_RESOLV_LIST_CMD \
+ | BLE_LE_RD_RESOLV_LIST_SIZE_CMD \
+ | BLE_LE_RD_PEER_RESOLV_ADDR_CMD)
+//byte35
+#define BLE_CMDS_BYTE35 ( BLE_LE_RD_LOCAL_RESOLV_ADDR_CMD \
+ | BLE_LE_SET_ADDR_RESOL_CMD \
+ | BLE_LE_SET_RESOLV_PRIV_ADDR_TO_CMD \
+ | BLE_LE_RD_MAX_DATA_LEN_CMD)
+#else
+//byte32
+#define BLE_CMDS_BYTE32 0
+//byte33
+#define BLE_CMDS_BYTE33 0
+//byte34
+#define BLE_CMDS_BYTE34 0
+//byte35
+#define BLE_CMDS_BYTE35 0
+#endif // BLE_QUALIF
+
+/******************************************************************************************/
+/* ------- SUPPORTED VALUES FOR DATA LENGTH EXTENSION COMMANDS -----------------------*/
+/******************************************************************************************/
+#define BLE_TESTMODE_MAX_OCTETS (255)
+//8 bits preamble
+#define BLE_PREAMBLE_TIME (8)
+//32 bits Access Code
+#define BLE_ACCESS_CODE_BIT_SIZE (32)
+//16 bits header
+#define BLE_HEADER_BIT_SIZE (16)
+//32bits MIC
+#define BLE_MIC_BIT_SIZE (32)
+//24 bits CRC
+#define BLE_CRC_BIT_SIZE (24)
+//8 bits preamble
+#define BLE_PREAMBLE_SIZE (1)
+//4 bytes Access Code
+#define BLE_ACCESS_CODE_SIZE (4)
+//2 bytes header
+#define BLE_HEADER_SIZE (2)
+//4 bytes MIC
+#define BLE_MIC_SIZE (4)
+//3 bytes CRC
+#define BLE_CRC_SIZE (3)
+
+#define BLE_COMMON_BIT_SIZE (BLE_ACCESS_CODE_BIT_SIZE + BLE_HEADER_BIT_SIZE + BLE_CRC_BIT_SIZE)
+/******************************************************************************************/
+/* -------------------------- DLE SETUP ----------------------------------------*/
+/******************************************************************************************/
+
+
+
+#define BLE_MIN_OCTETS (27)
+#define BLE_MIN_TIME (328)
+#if !(BLE_QUALIF)
+#define BLE_MAX_OCTETS (251)
+#define BLE_MAX_TIME (2120)
+#else
+#define BLE_MAX_OCTETS (27)
+#define BLE_MAX_TIME (328)
+#endif
+// Max number of descriptor to be linked under IRQ context to avoid CPU overload
+#define BLE_NB_MAX_CHUNKS (10)
+/******************************************************************************************/
+/* -------------------------- PROCEDURE STARTUP ----------------------------------------*/
+/******************************************************************************************/
+
+#define BLE_DLE_PROCEDURE (1 << 0)
+#define BLE_PHY_PROCEDURE (1 << 1)
+
+/// @} BLE stack configuration
+/// @} ROOT
+
+#endif // RWBLE_CONFIG_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwble_hl.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwble_hl.h
new file mode 100644
index 0000000000..1725862399
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwble_hl.h
@@ -0,0 +1,60 @@
+/**
+ ****************************************************************************************
+ *
+ * @file rwble_hl.h
+ *
+ * @brief Entry points of the BLE HL software
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef RWBLE_HL_H_
+#define RWBLE_HL_H_
+
+#include
+
+/**
+ ****************************************************************************************
+ * @addtogroup ROOT
+ * @brief Entry points of the BLE Host stack
+ *
+ * This module contains the primitives that allow an application accessing and running the
+ * BLE protocol stack
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+
+/**
+ ****************************************************************************************
+ * @brief Initialize the BLE Host stack.
+ ****************************************************************************************
+ */
+void rwble_hl_init(void);
+
+/**
+ ****************************************************************************************
+ * @brief Initialize the host (reset requested)
+ *
+ ****************************************************************************************
+ */
+void rwble_hl_reset(void);
+
+/// @} RWBLE_HL
+
+#endif // RWBLE_HL_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwble_hl_config.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwble_hl_config.h
new file mode 100644
index 0000000000..9e7cbb7060
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwble_hl_config.h
@@ -0,0 +1,254 @@
+/**
+ ****************************************************************************************
+ *
+ * @file rwble_hl_config.h
+ *
+ * @brief Configuration of the BLE protocol stack (max number of supported connections,
+ * type of partitioning, etc.)
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef RWBLE_HL_CONFIG_H_
+#define RWBLE_HL_CONFIG_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup ROOT
+ * @{
+ * @name BLE stack configuration
+ * @{
+ ****************************************************************************************
+ */
+
+#include "rwble_hl_error.h"
+
+/******************************************************************************************/
+/* ------------------------- BLE PARTITIONING -------------------------------------*/
+/******************************************************************************************/
+
+
+/******************************************************************************************/
+/* -------------------------- INTERFACES ----------------------------------------*/
+/******************************************************************************************/
+
+
+#if BLE_APP_PRESENT
+#define APP_MAIN_TASK TASK_APP
+#else // BLE_APP_PRESENT
+#define APP_MAIN_TASK TASK_AHI
+#endif // BLE_APP_PRESENT
+
+// Host Controller Interface (Host side)
+#define BLEHL_HCIH_ITF HCIH_ITF
+
+/******************************************************************************************/
+/* -------------------------- COEX SETUP ----------------------------------------*/
+/******************************************************************************************/
+
+///WLAN coex
+#define BLEHL_WLAN_COEX RW_WLAN_COEX
+///WLAN test mode
+#define BLEHL_WLAN_COEX_TEST RW_WLAN_COEX_TEST
+
+/******************************************************************************************/
+/* -------------------------- HOST MODULES ----------------------------------------*/
+/******************************************************************************************/
+
+#define BLE_GAPM 1
+#if (BLE_CENTRAL || BLE_PERIPHERAL)
+#define BLE_GAPC 1
+#define BLE_GAPC_HEAP_ENV_SIZE (sizeof(struct gapc_env_tag) + KE_HEAP_MEM_RESERVED)
+#else //(BLE_CENTRAL || BLE_PERIPHERAL)
+#define BLE_GAPC 0
+#define BLE_GAPC_HEAP_ENV_SIZE 0
+#endif //(BLE_CENTRAL || BLE_PERIPHERAL)
+
+#if (BLE_CENTRAL || BLE_PERIPHERAL)
+#define BLE_L2CM 1
+#define BLE_L2CC 1
+#define BLE_ATTM 1
+#define BLE_GATTM 1
+#define BLE_GATTC 1
+#define BLE_GATTC_HEAP_ENV_SIZE (sizeof(struct gattc_env_tag) + KE_HEAP_MEM_RESERVED)
+#define BLE_L2CC_HEAP_ENV_SIZE (sizeof(struct l2cc_env_tag) + KE_HEAP_MEM_RESERVED)
+#else //(BLE_CENTRAL || BLE_PERIPHERAL)
+#define BLE_L2CM 0
+#define BLE_L2CC 0
+#define BLE_ATTC 0
+#define BLE_ATTS 0
+#define BLE_ATTM 0
+#define BLE_GATTM 0
+#define BLE_GATTC 0
+#define BLE_GATTC_HEAP_ENV_SIZE 0
+#define BLE_L2CC_HEAP_ENV_SIZE 0
+#endif //(BLE_CENTRAL || BLE_PERIPHERAL)
+
+#define BLE_SMPM 1
+#if (BLE_CENTRAL || BLE_PERIPHERAL)
+#define BLE_SMPC 1
+#else //(BLE_CENTRAL || BLE_PERIPHERAL)
+#define BLE_SMPC 0
+#endif //(BLE_CENTRAL || BLE_PERIPHERAL)
+
+
+/******************************************************************************************/
+/* -------------------------- ATT DB ----------------------------------------*/
+/******************************************************************************************/
+
+//ATT DB,Testing and Qualification related flags
+#if (BLE_CENTRAL || BLE_PERIPHERAL)
+ /// Support of External DB Management
+ #if defined(CFG_EXT_DB)
+ #define BLE_EXT_ATT_DB 1
+ #else
+ #define BLE_EXT_ATT_DB 0
+ #endif // defined(CFG_EXT_DB)
+#else
+ #define BLE_EXT_ATT_DB 0
+#endif // (BLE_CENTRAL || BLE_PERIPHERAL)
+/******************************************************************************************/
+/* -------------------------- PROFILES ----------------------------------------*/
+/******************************************************************************************/
+#ifdef CFG_PRF
+#define BLE_PROFILES (1)
+/// Number of Profile tasks managed by GAP manager.
+#define BLE_NB_PROFILES (CFG_NB_PRF)
+#include "rwprf_config.h"
+#else
+#define BLE_PROFILES (0)
+#define BLE_NB_PROFILES (0)
+#endif // CFG_PRF
+
+
+#ifndef BLE_ATTS
+#if (BLE_CENTRAL || BLE_PERIPHERAL || defined(CFG_ATTS))
+#define BLE_ATTS 1
+#else
+#define BLE_ATTS 0
+#endif // (BLE_CENTRAL || BLE_PERIPHERAL || defined(CFG_ATTS))
+#endif // BLE_ATTS
+
+
+#ifndef BLE_ATTC
+#if (BLE_CENTRAL || defined(CFG_ATTC))
+#define BLE_ATTC 1
+#else
+#define BLE_ATTC 0
+#endif // (BLE_CENTRAL || defined(CFG_ATTC))
+#endif // BLE_ATTC
+
+#ifndef BLE_LECB
+#if (BLE_CENTRAL || BLE_PERIPHERAL)
+#define BLE_LECB 0//1
+#else
+#define BLE_LECB 0
+#endif // (BLE_CENTRAL || defined(CFG_ATTC))
+#endif // BLE_ATTC
+
+
+/// Attribute Server
+#if (BLE_ATTS)
+#define BLE_ATTS 1
+#else
+#define BLE_ATTS 0
+#endif //(BLE_ATTS)
+
+
+/// Size of the heap
+#if (BLE_CENTRAL || BLE_PERIPHERAL)
+ /// some heap must be reserved for attribute database
+ #if (BLE_ATTS || BLE_ATTC)
+ #define BLEHL_HEAP_DB_SIZE 512//(1024)// (3072) by bottle
+ #else
+ #define BLEHL_HEAP_DB_SIZE (0)
+ #endif /* (BLE_ATTS || BLE_ATTC) */
+
+ #define BLEHL_HEAP_MSG_SIZE (256 + 256 * BLE_CONNECTION_MAX)
+#else
+ #define BLEHL_HEAP_MSG_SIZE (256)
+ #define BLEHL_HEAP_DB_SIZE (0)
+#endif /* #if (BLE_CENTRAL || BLE_PERIPHERAL) */
+
+
+
+
+/// Number of BLE HL tasks
+#define BLEHL_TASK_SIZE BLE_HOST_TASK_SIZE + BLE_PRF_TASK_SIZE
+
+/// Size of environment variable needed on BLE Host Stack for one link
+#define BLEHL_HEAP_ENV_SIZE ( BLE_GAPC_HEAP_ENV_SIZE + \
+ BLE_GATTC_HEAP_ENV_SIZE + \
+ BLE_L2CC_HEAP_ENV_SIZE)
+
+
+
+
+
+
+
+/*
+ * DEFINES - Mandatory for BLE Host Layers
+ ****************************************************************************************
+ */
+/// Maximum time to remain advertising when in the Limited
+/// Discover able mode: TGAP(lim_adv_timeout)
+/// required value: 180s: (18000 for ke timer)
+#define GAP_TMR_LIM_ADV_TIMEOUT 0x4650
+
+/// Minimum time to perform scanning when performing
+/// the General Discovery procedure: TGAP(gen_disc_scan_min)
+/// recommended value: 10.24s: (1024 for ke timer)
+#define GAP_TMR_GEN_DISC_SCAN 0x0300
+
+/// Minimum time to perform scanning when performing the
+/// Limited Discovery procedure: TGAP(lim_disc_scan_min)
+/// recommended value: 10.24s: (1024 for ke timer)
+#define GAP_TMR_LIM_DISC_SCAN 0x0300
+
+/// Minimum time interval between private address change
+/// TGAP(private_addr_int)
+/// recommended value: 15 minutes; 0x01F4 for PTS
+/// 0x3A98 is 150 seconds; 0xEA60 is 10 minutes
+#define GAP_TMR_PRIV_ADDR_INT 0x3A98
+
+
+/// Timer used in connection parameter update procedure
+/// TGAP(conn_param_timeout)
+/// recommended value: 30 s: (3000 for ke timer) / *10ms
+#define GAP_TMR_CONN_PARAM_TIMEOUT 0x0BB8
+
+/// Timer used in LE credit based connection procedure
+/// TGAP(lecb_conn_timeout)
+/// recommended value: 30 s: (3000 for ke timer)
+#define GAP_TMR_LECB_CONN_TIMEOUT 0x0BB8
+
+/// Timer used in LE credit based disconnection procedure
+/// TGAP(lecb_disconn_timeout)
+/// recommended value: 30 s: (3000 for ke timer)
+#define GAP_TMR_LECB_DISCONN_TIMEOUT 0x0BB8
+
+/// Maximal authorized MTU value
+#define GAP_MAX_LE_MTU (517)
+
+/// Maximum GAP device name size
+#define GAP_MAX_NAME_SIZE (0x20)
+
+/// Maximum Transmission Unit
+#define ATT_DEFAULT_MTU (23)
+/// 30 seconds transaction timer
+#define ATT_TRANS_RTX (0x0BB8)
+/// Acceptable encryption key size - strict access
+#define ATT_SEC_ENC_KEY_SIZE (0x10)
+
+/// Maximum attribute value length
+#define ATT_MAX_VALUE (GAP_MAX_LE_MTU)
+
+
+/// @} BLE stack configuration
+/// @} ROOT
+
+#endif // RWBLE_HL_CONFIG_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwble_hl_error.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwble_hl_error.h
new file mode 100644
index 0000000000..709c5df5f6
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwble_hl_error.h
@@ -0,0 +1,427 @@
+/**
+ ****************************************************************************************
+ *
+ * @file rwble_hl_error.h
+ *
+ * @brief File that contains all error codes.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef RWBLE_HL_ERROR_H_
+#define RWBLE_HL_ERROR_H_
+
+
+/**
+ ****************************************************************************************
+ * @addtogroup ROOT
+ * @brief High layer error codes
+ *
+ * This module contains the primitives that allow an application accessing and running the
+ * BLE protocol stack
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+
+
+/// Error code from HCI TO HL Range - from 0x90 to 0xD0
+#define RW_ERR_HCI_TO_HL(err) (((err) != 0) ? ((err) + 0x90) : (0))
+
+
+/// Error code from HL TO HCI Range - from 0x90 to 0xD0
+#define RW_ERR_HL_TO_HCI(err) (((err) > 0x90) ? ((err) - 0x90) : (0))
+
+/**
+ * List all HL error codes
+ */
+enum hl_err
+{
+ /// No error
+ GAP_ERR_NO_ERROR = 0x00,
+
+ // ----------------------------------------------------------------------------------
+ // ------------------------- ATT Specific Error ------------------------------------
+ // ----------------------------------------------------------------------------------
+ /// No error
+ ATT_ERR_NO_ERROR = 0x00,
+ /// 0x01: Handle is invalid
+ ATT_ERR_INVALID_HANDLE = 0x01,
+ /// 0x02: Read permission disabled
+ ATT_ERR_READ_NOT_PERMITTED = 0x02,
+ /// 0x03: Write permission disabled
+ ATT_ERR_WRITE_NOT_PERMITTED = 0x03,
+ /// 0x04: Incorrect PDU
+ ATT_ERR_INVALID_PDU = 0x04,
+ /// 0x05: Authentication privilege not enough
+ ATT_ERR_INSUFF_AUTHEN = 0x05,
+ /// 0x06: Request not supported or not understood
+ ATT_ERR_REQUEST_NOT_SUPPORTED = 0x06,
+ /// 0x07: Incorrect offset value
+ ATT_ERR_INVALID_OFFSET = 0x07,
+ /// 0x08: Authorization privilege not enough
+ ATT_ERR_INSUFF_AUTHOR = 0x08,
+ /// 0x09: Capacity queue for reliable write reached
+ ATT_ERR_PREPARE_QUEUE_FULL = 0x09,
+ /// 0x0A: Attribute requested not existing
+ ATT_ERR_ATTRIBUTE_NOT_FOUND = 0x0A,
+ /// 0x0B: Attribute requested not long
+ ATT_ERR_ATTRIBUTE_NOT_LONG = 0x0B,
+ /// 0x0C: Encryption size not sufficient
+ ATT_ERR_INSUFF_ENC_KEY_SIZE = 0x0C,
+ /// 0x0D: Invalid length of the attribute value
+ ATT_ERR_INVALID_ATTRIBUTE_VAL_LEN = 0x0D,
+ /// 0x0E: Operation not fit to condition
+ ATT_ERR_UNLIKELY_ERR = 0x0E,
+ /// 0x0F: Attribute requires encryption before operation
+ ATT_ERR_INSUFF_ENC = 0x0F,
+ /// 0x10: Attribute grouping not supported
+ ATT_ERR_UNSUPP_GRP_TYPE = 0x10,
+ /// 0x11: Resources not sufficient to complete the request
+ ATT_ERR_INSUFF_RESOURCE = 0x11,
+ /// 0x80: Application error (also used in PRF Errors)
+ ATT_ERR_APP_ERROR = 0x80,
+
+ // ----------------------------------------------------------------------------------
+ // -------------------------- L2C Specific Error ------------------------------------
+ // ----------------------------------------------------------------------------------
+ /// Message cannot be sent because connection lost. (disconnected)
+ L2C_ERR_CONNECTION_LOST = 0x30,
+ /// Invalid PDU length exceed MTU
+ L2C_ERR_INVALID_MTU_EXCEED = 0x31,
+ /// Invalid PDU length exceed MPS
+ L2C_ERR_INVALID_MPS_EXCEED = 0x32,
+ /// Invalid Channel ID
+ L2C_ERR_INVALID_CID = 0x33,
+ /// Invalid PDU
+ L2C_ERR_INVALID_PDU = 0x34,
+ /// Connection refused - no resources available
+ L2C_ERR_NO_RES_AVAIL = 0x35,
+ /// Connection refused - insufficient authentication
+ L2C_ERR_INSUFF_AUTHEN = 0x36,
+ /// Connection refused - insufficient authorization
+ L2C_ERR_INSUFF_AUTHOR = 0x37,
+ /// Connection refused - insufficient encryption key size
+ L2C_ERR_INSUFF_ENC_KEY_SIZE = 0x38,
+ /// Connection Refused - insufficient encryption
+ L2C_ERR_INSUFF_ENC = 0x39,
+ /// Connection refused - LE_PSM not supported
+ L2C_ERR_LEPSM_NOT_SUPP = 0x3A,
+ /// No more credit
+ L2C_ERR_INSUFF_CREDIT = 0x3B,
+ /// Command not understood by peer device
+ L2C_ERR_NOT_UNDERSTOOD = 0x3C,
+ /// Credit error, invalid number of credit received
+ L2C_ERR_CREDIT_ERROR = 0x3D,
+ /// Channel identifier already allocated
+ L2C_ERR_CID_ALREADY_ALLOC = 0x3E,
+
+
+ // ----------------------------------------------------------------------------------
+ // -------------------------- GAP Specific Error ------------------------------------
+ // ----------------------------------------------------------------------------------
+ /// Invalid parameters set
+ GAP_ERR_INVALID_PARAM = 0x40,
+ /// Problem with protocol exchange, get unexpected response
+ GAP_ERR_PROTOCOL_PROBLEM = 0x41,
+ /// Request not supported by software configuration
+ GAP_ERR_NOT_SUPPORTED = 0x42,
+ /// Request not allowed in current state.
+ GAP_ERR_COMMAND_DISALLOWED = 0x43,
+ /// Requested operation canceled.
+ GAP_ERR_CANCELED = 0x44,
+ /// Requested operation timeout.
+ GAP_ERR_TIMEOUT = 0x45,
+ /// Link connection lost during operation.
+ GAP_ERR_DISCONNECTED = 0x46,
+ /// Search algorithm finished, but no result found
+ GAP_ERR_NOT_FOUND = 0x47,
+ /// Request rejected by peer device
+ GAP_ERR_REJECTED = 0x48,
+ /// Problem with privacy configuration
+ GAP_ERR_PRIVACY_CFG_PB = 0x49,
+ /// Duplicate or invalid advertising data
+ GAP_ERR_ADV_DATA_INVALID = 0x4A,
+ /// Insufficient resources
+ GAP_ERR_INSUFF_RESOURCES = 0x4B,
+ /// Unexpected Error
+ GAP_ERR_UNEXPECTED = 0x4C,
+ /// Feature mismatch
+ GAP_ERR_MISMATCH = 0x4D,
+
+
+ // ----------------------------------------------------------------------------------
+ // ------------------------- GATT Specific Error ------------------------------------
+ // ----------------------------------------------------------------------------------
+ /// Problem with ATTC protocol response
+ GATT_ERR_INVALID_ATT_LEN = 0x50,
+ /// Error in service search
+ GATT_ERR_INVALID_TYPE_IN_SVC_SEARCH = 0x51,
+ /// Invalid write data
+ GATT_ERR_WRITE = 0x52,
+ /// Signed write error
+ GATT_ERR_SIGNED_WRITE = 0x53,
+ /// No attribute client defined
+ GATT_ERR_ATTRIBUTE_CLIENT_MISSING = 0x54,
+ /// No attribute server defined
+ GATT_ERR_ATTRIBUTE_SERVER_MISSING = 0x55,
+ /// Permission set in service/attribute are invalid
+ GATT_ERR_INVALID_PERM = 0x56,
+
+ // ----------------------------------------------------------------------------------
+ // ------------------------- SMP Specific Error -------------------------------------
+ // ----------------------------------------------------------------------------------
+ // SMP Protocol Errors detected on local device
+ /// The user input of pass key failed, for example, the user canceled the operation.
+ SMP_ERROR_LOC_PASSKEY_ENTRY_FAILED = 0x61,
+ /// The OOB Data is not available.
+ SMP_ERROR_LOC_OOB_NOT_AVAILABLE = 0x62,
+ /// The pairing procedure cannot be performed as authentication requirements cannot be met
+ /// due to IO capabilities of one or both devices.
+ SMP_ERROR_LOC_AUTH_REQ = 0x63,
+ /// The confirm value does not match the calculated confirm value.
+ SMP_ERROR_LOC_CONF_VAL_FAILED = 0x64,
+ /// Pairing is not supported by the device.
+ SMP_ERROR_LOC_PAIRING_NOT_SUPP = 0x65,
+ /// The resultant encryption key size is insufficient for the security requirements of
+ /// this device.
+ SMP_ERROR_LOC_ENC_KEY_SIZE = 0x66,
+ /// The SMP command received is not supported on this device.
+ SMP_ERROR_LOC_CMD_NOT_SUPPORTED = 0x67,
+ /// Pairing failed due to an unspecified reason.
+ SMP_ERROR_LOC_UNSPECIFIED_REASON = 0x68,
+ /// Pairing or Authentication procedure is disallowed because too little time has elapsed
+ /// since last pairing request or security request.
+ SMP_ERROR_LOC_REPEATED_ATTEMPTS = 0x69,
+ /// The command length is invalid or a parameter is outside of the specified range.
+ SMP_ERROR_LOC_INVALID_PARAM = 0x6A,
+ /// Indicates to the remote device that the DHKey Check value received doesn't
+ /// match the one calculated by the local device.
+ SMP_ERROR_LOC_DHKEY_CHECK_FAILED = 0x6B,
+ /// Indicates that the confirm values in the numeric comparison protocol do not match.
+ SMP_ERROR_LOC_NUMERIC_COMPARISON_FAILED = 0x6C,
+ /// Indicates that the pairing over the LE transport failed due to a Pairing Request sent
+ /// over the BR/EDR transport in process.
+ SMP_ERROR_LOC_BREDR_PAIRING_IN_PROGRESS = 0x6D,
+ /// Indicates that the BR/EDR Link Key generated on the BR/EDR transport cannot be
+ /// used to derive and distribute keys for the LE transport.
+ SMP_ERROR_LOC_CROSS_TRANSPORT_KEY_GENERATION_NOT_ALLOWED = 0x6E,
+ // SMP Protocol Errors detected by remote device
+ /// The user input of passkey failed, for example, the user canceled the operation.
+ SMP_ERROR_REM_PASSKEY_ENTRY_FAILED = 0x71,
+ /// The OOB Data is not available.
+ SMP_ERROR_REM_OOB_NOT_AVAILABLE = 0x72,
+ /// The pairing procedure cannot be performed as authentication requirements cannot be
+ /// met due to IO capabilities of one or both devices.
+ SMP_ERROR_REM_AUTH_REQ = 0x73,
+ /// The confirm value does not match the calculated confirm value.
+ SMP_ERROR_REM_CONF_VAL_FAILED = 0x74,
+ /// Pairing is not supported by the device.
+ SMP_ERROR_REM_PAIRING_NOT_SUPP = 0x75,
+ /// The resultant encryption key size is insufficient for the security requirements of
+ /// this device.
+ SMP_ERROR_REM_ENC_KEY_SIZE = 0x76,
+ /// The SMP command received is not supported on this device.
+ SMP_ERROR_REM_CMD_NOT_SUPPORTED = 0x77,
+ /// Pairing failed due to an unspecified reason.
+ SMP_ERROR_REM_UNSPECIFIED_REASON = 0x78,
+ /// Pairing or Authentication procedure is disallowed because too little time has elapsed
+ /// since last pairing request or security request.
+ SMP_ERROR_REM_REPEATED_ATTEMPTS = 0x79,
+ /// The command length is invalid or a parameter is outside of the specified range.
+ SMP_ERROR_REM_INVALID_PARAM = 0x7A,
+ /// Indicates to the remote device that the DHKey Check value received doesn't
+ /// match the one calculated by the local device.
+ SMP_ERROR_REM_DHKEY_CHECK_FAILED = 0x7B,
+ /// Indicates that the confirm values in the numeric comparison protocol do not match.
+ SMP_ERROR_REM_NUMERIC_COMPARISON_FAILED = 0x7C,
+ /// Indicates that the pairing over the LE transport failed due to a Pairing Request sent
+ /// over the BR/EDR transport in process.
+ SMP_ERROR_REM_BREDR_PAIRING_IN_PROGRESS = 0x7D,
+ /// Indicates that the BR/EDR Link Key generated on the BR/EDR transport cannot be
+ /// used to derive and distribute keys for the LE transport.
+ SMP_ERROR_REM_CROSS_TRANSPORT_KEY_GENERATION_NOT_ALLOWED = 0x7E,
+ // SMP Errors triggered by local device
+ /// The provided resolvable address has not been resolved.
+ SMP_ERROR_ADDR_RESOLV_FAIL = 0xD0,
+ /// The Signature Verification Failed
+ SMP_ERROR_SIGN_VERIF_FAIL = 0xD1,
+ /// The encryption procedure failed because the slave device didn't find the LTK
+ /// needed to start an encryption session.
+ SMP_ERROR_ENC_KEY_MISSING = 0xD2,
+ /// The encryption procedure failed because the slave device doesn't support the
+ /// encryption feature.
+ SMP_ERROR_ENC_NOT_SUPPORTED = 0xD3,
+ /// A timeout has occurred during the start encryption session.
+ SMP_ERROR_ENC_TIMEOUT = 0xD4,
+
+ // ----------------------------------------------------------------------------------
+ //------------------------ Profiles specific error codes ----------------------------
+ // ----------------------------------------------------------------------------------
+ /// Application Error
+ PRF_APP_ERROR = 0x80,
+ /// Invalid parameter in request
+ PRF_ERR_INVALID_PARAM = 0x81,
+ /// Inexistent handle for sending a read/write characteristic request
+ PRF_ERR_INEXISTENT_HDL = 0x82,
+ /// Discovery stopped due to missing attribute according to specification
+ PRF_ERR_STOP_DISC_CHAR_MISSING = 0x83,
+ /// Too many SVC instances found -> protocol violation
+ PRF_ERR_MULTIPLE_SVC = 0x84,
+ /// Discovery stopped due to found attribute with incorrect properties
+ PRF_ERR_STOP_DISC_WRONG_CHAR_PROP = 0x85,
+ /// Too many Char. instances found-> protocol violation
+ PRF_ERR_MULTIPLE_CHAR = 0x86,
+ /// Attribute write not allowed
+ PRF_ERR_NOT_WRITABLE = 0x87,
+ /// Attribute read not allowed
+ PRF_ERR_NOT_READABLE = 0x88,
+ /// Request not allowed
+ PRF_ERR_REQ_DISALLOWED = 0x89,
+ /// Notification Not Enabled
+ PRF_ERR_NTF_DISABLED = 0x8A,
+ /// Indication Not Enabled
+ PRF_ERR_IND_DISABLED = 0x8B,
+ /// Feature not supported by profile
+ PRF_ERR_FEATURE_NOT_SUPPORTED = 0x8C,
+ /// Read value has an unexpected length
+ PRF_ERR_UNEXPECTED_LEN = 0x8D,
+ /// Disconnection occurs
+ PRF_ERR_DISCONNECTED = 0x8E,
+ /// Procedure Timeout
+ PRF_ERR_PROC_TIMEOUT = 0x8F,
+ /// Client characteristic configuration improperly configured
+ PRF_CCCD_IMPR_CONFIGURED = 0xFD,
+ /// Procedure already in progress
+ PRF_PROC_IN_PROGRESS = 0xFE,
+ /// Out of Range
+ PRF_OUT_OF_RANGE = 0xFF,
+
+ // ----------------------------------------------------------------------------------
+ //-------------------- LL Error codes conveyed to upper layer -----------------------
+ // ----------------------------------------------------------------------------------
+ /// Unknown HCI Command
+ LL_ERR_UNKNOWN_HCI_COMMAND = 0x91,
+ /// Unknown Connection Identifier
+ LL_ERR_UNKNOWN_CONNECTION_ID = 0x92,
+ /// Hardware Failure
+ LL_ERR_HARDWARE_FAILURE = 0x93,
+ /// BT Page Timeout
+ LL_ERR_PAGE_TIMEOUT = 0x94,
+ /// Authentication failure
+ LL_ERR_AUTH_FAILURE = 0x95,
+ /// Pin code missing
+ LL_ERR_PIN_MISSING = 0x96,
+ /// Memory capacity exceed
+ LL_ERR_MEMORY_CAPA_EXCEED = 0x97,
+ /// Connection Timeout
+ LL_ERR_CON_TIMEOUT = 0x98,
+ /// Connection limit Exceed
+ LL_ERR_CON_LIMIT_EXCEED = 0x99,
+ /// Synchronous Connection limit exceed
+ LL_ERR_SYNC_CON_LIMIT_DEV_EXCEED = 0x9A,
+ /// ACL Connection exits
+ LL_ERR_ACL_CON_EXISTS = 0x9B,
+ /// Command Disallowed
+ LL_ERR_COMMAND_DISALLOWED = 0x9C,
+ /// Connection rejected due to limited resources
+ LL_ERR_CONN_REJ_LIMITED_RESOURCES = 0x9D,
+ /// Connection rejected due to security reason
+ LL_ERR_CONN_REJ_SECURITY_REASONS = 0x9E,
+ /// Connection rejected due to unacceptable BD Addr
+ LL_ERR_CONN_REJ_UNACCEPTABLE_BDADDR = 0x9F,
+ /// Connection rejected due to Accept connection timeout
+ LL_ERR_CONN_ACCEPT_TIMEOUT_EXCEED = 0xA0,
+ /// Not Supported
+ LL_ERR_UNSUPPORTED = 0xA1,
+ /// invalid parameters
+ LL_ERR_INVALID_HCI_PARAM = 0xA2,
+ /// Remote user terminate connection
+ LL_ERR_REMOTE_USER_TERM_CON = 0xA3,
+ /// Remote device terminate connection due to low resources
+ LL_ERR_REMOTE_DEV_TERM_LOW_RESOURCES = 0xA4,
+ /// Remote device terminate connection due to power off
+ LL_ERR_REMOTE_DEV_POWER_OFF = 0xA5,
+ /// Connection terminated by local host
+ LL_ERR_CON_TERM_BY_LOCAL_HOST = 0xA6,
+ /// Repeated attempts
+ LL_ERR_REPEATED_ATTEMPTS = 0xA7,
+ /// Pairing not Allowed
+ LL_ERR_PAIRING_NOT_ALLOWED = 0xA8,
+ /// Unknown PDU Error
+ LL_ERR_UNKNOWN_LMP_PDU = 0xA9,
+ /// Unsupported remote feature
+ LL_ERR_UNSUPPORTED_REMOTE_FEATURE = 0xAA,
+ /// Sco Offset rejected
+ LL_ERR_SCO_OFFSET_REJECTED = 0xAB,
+ /// SCO Interval Rejected
+ LL_ERR_SCO_INTERVAL_REJECTED = 0xAC,
+ /// SCO air mode Rejected
+ LL_ERR_SCO_AIR_MODE_REJECTED = 0xAD,
+ /// Invalid LMP parameters
+ LL_ERR_INVALID_LMP_PARAM = 0xAE,
+ /// Unspecified error
+ LL_ERR_UNSPECIFIED_ERROR = 0xAF,
+ /// Unsupported LMP Parameter value
+ LL_ERR_UNSUPPORTED_LMP_PARAM_VALUE = 0xB0,
+ /// Role Change Not allowed
+ LL_ERR_ROLE_CHANGE_NOT_ALLOWED = 0xB1,
+ /// LMP Response timeout
+ LL_ERR_LMP_RSP_TIMEOUT = 0xB2,
+ /// LMP Collision
+ LL_ERR_LMP_COLLISION = 0xB3,
+ /// LMP Pdu not allowed
+ LL_ERR_LMP_PDU_NOT_ALLOWED = 0xB4,
+ /// Encryption mode not accepted
+ LL_ERR_ENC_MODE_NOT_ACCEPT = 0xB5,
+ /// Link Key Cannot be changed
+ LL_ERR_LINK_KEY_CANT_CHANGE = 0xB6,
+ /// Quality of Service not supported
+ LL_ERR_QOS_NOT_SUPPORTED = 0xB7,
+ /// Error, instant passed
+ LL_ERR_INSTANT_PASSED = 0xB8,
+ /// Pairing with unit key not supported
+ LL_ERR_PAIRING_WITH_UNIT_KEY_NOT_SUP = 0xB9,
+ /// Transaction collision
+ LL_ERR_DIFF_TRANSACTION_COLLISION = 0xBA,
+ /// Unacceptable parameters
+ LL_ERR_QOS_UNACCEPTABLE_PARAM = 0xBC,
+ /// Quality of Service rejected
+ LL_ERR_QOS_REJECTED = 0xBD,
+ /// Channel class not supported
+ LL_ERR_CHANNEL_CLASS_NOT_SUP = 0xBE,
+ /// Insufficient security
+ LL_ERR_INSUFFICIENT_SECURITY = 0xBF,
+ /// Parameters out of mandatory range
+ LL_ERR_PARAM_OUT_OF_MAND_RANGE = 0xC0,
+ /// Role switch pending
+ LL_ERR_ROLE_SWITCH_PEND = 0xC2,
+ /// Reserved slot violation
+ LL_ERR_RESERVED_SLOT_VIOLATION = 0xC4,
+ /// Role Switch fail
+ LL_ERR_ROLE_SWITCH_FAIL = 0xC5,
+ /// Error, EIR too large
+ LL_ERR_EIR_TOO_LARGE = 0xC6,
+ /// Simple pairing not supported by host
+ LL_ERR_SP_NOT_SUPPORTED_HOST = 0xC7,
+ /// Host pairing is busy
+ LL_ERR_HOST_BUSY_PAIRING = 0xC8,
+ /// Controller is busy
+ LL_ERR_CONTROLLER_BUSY = 0xCA,
+ /// Unacceptable connection initialization
+ LL_ERR_UNACCEPTABLE_CONN_INT = 0xCB,
+ /// Direct Advertising Timeout
+ LL_ERR_DIRECT_ADV_TO = 0xCC,
+ /// Connection Terminated due to a MIC failure
+ LL_ERR_TERMINATED_MIC_FAILURE = 0xCD,
+ /// Connection failed to be established
+ LL_ERR_CONN_FAILED_TO_BE_EST = 0xCE,
+};
+
+/// @} RWBLE_HL_ERROR_H
+
+#endif // RWBLE_HL_ERROR_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwip.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwip.h
new file mode 100644
index 0000000000..23427d4239
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwip.h
@@ -0,0 +1,453 @@
+/**
+****************************************************************************************
+*
+* @file rwip.h
+*
+* @brief RW IP SW main module
+*
+* Copyright (C) RivieraWaves 2009-2015
+*
+*
+****************************************************************************************
+*/
+#ifndef _RWIP_H_
+#define _RWIP_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup ROOT
+ * @brief Entry points of the RW IP stacks/modules
+ *
+ * This module contains the primitives that allow an application accessing and running the
+ * RW IP protocol stacks / modules.
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+#include "rwip_config.h" // stack configuration
+
+#include // standard integer definitions
+#include // standard boolean definitions
+
+/// retrieve 10ms time according to clock time
+#define RWIP_CLOCK_TO_10MS_TIME(clock) ((clock) >> 4)
+/// retrieve clock time according to 10ms time
+#define RWIP_10MS_TIME_TO_CLOCK(time) ((time) << 4)
+/// Invalid target time
+#define RWIP_INVALID_TARGET_TIME (0xFFFFFFFFL)
+
+#if (DEEP_SLEEP)
+/// Definition of the bits preventing the system from sleeping
+enum prevent_sleep
+{
+ /// Flag indicating that the wake up process is ongoing
+ RW_WAKE_UP_ONGOING = 0x0001,
+ /// Flag indicating that an TX transfer is ongoing on Transport Layer
+ RW_TL_TX_ONGOING = 0x0002,
+ /// Flag indicating that an RX transfer is ongoing on Transport Layer
+ RW_TL_RX_ONGOING = 0x0004,
+ /// Flag indicating HCI timeout is ongoing
+ RW_AHI_TIMEOUT = 0x0008,
+ /// Flag indicating that an encryption is ongoing
+ RW_CRYPT_ONGOING = 0x0010,
+ /// Flag indicating that a element deletion is on going
+ RW_DELETE_ELT_ONGOING = 0x0020,
+ /// Flag indicating that controller shall not sleep due to not CSB LPO_Allowed
+ RW_CSB_NOT_LPO_ALLOWED = 0x0040,
+ /// Flag indicating the MWS/WLAN Event Generator is in operation
+ RW_MWS_WLAN_EVENT_GENERATOR_ACTIVE = 0x0080
+};
+#endif //DEEP_SLEEP
+
+
+
+/**
+ * External interface type types.
+ */
+enum rwip_eif_types
+{
+ /// Host Controller Interface - Controller part
+ RWIP_EIF_HCIC,
+
+ /// Host Controller Interface - Host part
+ RWIP_EIF_HCIH,
+
+ /// Application Host interface
+ RWIP_EIF_AHI,
+};
+
+
+/// Enumeration of External Interface status codes
+enum rwip_eif_status
+{
+ /// EIF status OK
+ RWIP_EIF_STATUS_OK,
+ /// EIF status KO
+ RWIP_EIF_STATUS_ERROR,
+
+#if (BLE_EMB_PRESENT == 0)
+ /// External interface detached
+ RWIP_EIF_STATUS_DETACHED,
+ /// External interface attached
+ RWIP_EIF_STATUS_ATTACHED,
+#endif // (BLE_EMB_PRESENT == 0)
+};
+
+/// Enumeration of RF modulations
+enum rwip_rf_mod
+{
+ MOD_GFSK = 0x01,
+ MOD_DQPSK = 0x02,
+ MOD_8DPSK = 0x03,
+};
+
+/// API functions of the RF driver that are used by the BLE or BT software
+struct rwip_rf_api
+{
+ /// Function called upon HCI reset command reception
+ void (*reset)(void);
+ /// Function called to enable/disable force AGC mechanism (true: en / false : dis)
+ void (*force_agc_enable)(bool);
+ /// Function called when TX power has to be decreased for a specific link id
+ bool (*txpwr_dec)(uint8_t);
+ /// Function called when TX power has to be increased for a specific link id
+ bool (*txpwr_inc)(uint8_t);
+ /// Function called when TX power has to be set to max for a specific link id
+ void (*txpwr_max_set)(uint8_t);
+ /// Function called to convert a TX power CS power field into the corresponding value in dBm
+ uint8_t (*txpwr_dbm_get)(uint8_t, uint8_t);
+ /// Function called to convert a power in dBm into a control structure tx power field
+ uint8_t (*txpwr_cs_get)(int8_t);
+ /// Function called to convert the RSSI read from the control structure into a real RSSI
+ int8_t (*rssi_convert)(uint8_t);
+ /// Function used to read a RF register
+ uint32_t (*reg_rd)(uint16_t);
+ /// Function used to write a RF register
+ void (*reg_wr)(uint16_t, uint32_t);
+ /// Function called to put the RF in deep sleep mode
+ void (*sleep)(void);
+ /// Index of maximum TX power
+ uint8_t txpwr_max;
+ /// RSSI high threshold ('real' signed value in dBm)
+ int8_t rssi_high_thr;
+ /// RSSI low threshold ('real' signed value in dBm)
+ int8_t rssi_low_thr;
+ /// interferer threshold ('real' signed value in dBm)
+ int8_t rssi_interf_thr;
+ /// RF wakeup delay (in slots)
+ uint8_t wakeup_delay;
+};
+
+/// Internal API for priority
+struct rwip_prio
+{
+ ///value
+ uint8_t value;
+ ///Increment
+ uint8_t increment;
+};
+
+/// Internal API for COEX
+struct rwip_coex
+{
+ ///Coexistence control field
+ uint8_t coex_cntl;
+};
+
+
+/**
+ ****************************************************************************************
+ * @brief Function called when packet transmission/reception is finished.
+
+ * @param[in] dummy Dummy data pointer returned to callback when operation is over.
+ * @param[in] status Ok if action correctly performed, else reason status code.
+ *****************************************************************************************
+ */
+typedef void (*rwip_eif_callback) (void*, uint8_t);
+
+/**
+ * Transport layer communication interface.
+ */
+struct rwip_eif_api
+{
+ /**
+ *************************************************************************************
+ * @brief Starts a data reception.
+ *
+ * @param[out] bufptr Pointer to the RX buffer
+ * @param[in] size Size of the expected reception
+ * @param[in] callback Pointer to the function called back when transfer finished
+ * @param[in] dummy Dummy data pointer returned to callback when reception is finished
+ *************************************************************************************
+ */
+ void (*read) (uint8_t *bufptr, uint32_t size, rwip_eif_callback callback, void* dummy);
+
+ /**
+ *************************************************************************************
+ * @brief Starts a data transmission.
+ *
+ * @param[in] bufptr Pointer to the TX buffer
+ * @param[in] size Size of the transmission
+ * @param[in] callback Pointer to the function called back when transfer finished
+ * @param[in] dummy Dummy data pointer returned to callback when transmission is finished
+ *************************************************************************************
+ */
+ void (*write)(uint8_t *bufptr, uint32_t size, rwip_eif_callback callback, void* dummy);
+
+ /**
+ *************************************************************************************
+ * @brief Enable Interface flow.
+ *************************************************************************************
+ */
+ void (*flow_on)(void);
+
+ /**
+ *************************************************************************************
+ * @brief Disable Interface flow.
+ *
+ * @return True if flow has been disabled, False else.
+ *************************************************************************************
+ */
+ bool (*flow_off)(void);
+};
+
+/*
+ * VARIABLE DECLARATION
+*****************************************************************************************
+ */
+
+/// API for RF driver
+extern struct rwip_rf_api rwip_rf;
+#if (BLE_EMB_PRESENT || BT_EMB_PRESENT)
+/// API for dual mode priority
+extern const struct rwip_prio rwip_priority[RWIP_PRIO_IDX_MAX];
+/// API for COEX
+extern const uint8_t rwip_coex_cfg[RWIP_COEX_CFG_MAX];
+#endif //#if (BLE_EMB_PRESENT || BT_EMB_PRESENT)
+
+/*
+ * MACROS
+ ****************************************************************************************
+ */
+
+/// Get Event status flag
+#define RWIP_COEX_GET(coex_cfg_idx, bit_field) \
+ (uint8_t)(((rwip_coex_cfg[RWIP_COEX_ ## coex_cfg_idx ##_IDX]) >> RWIP_ ## bit_field ## _POS ) & RWIP_COEX_BIT_MASK)
+
+/*
+ * FUNCTION DECLARATION
+*****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief Initializes the RW BT SW.
+ *
+ ****************************************************************************************
+ */
+void rwip_init(uint32_t error);
+
+/**
+ ****************************************************************************************
+ * @brief Reset the RW BT SW.
+ *
+ ****************************************************************************************
+ */
+void rwip_reset(void);
+
+/**
+ ****************************************************************************************
+ * @brief Gives FW/HW versions of RW-BT stack.
+ *
+ ****************************************************************************************
+ */
+void rwip_version(uint8_t* fw_version, uint8_t* hw_version);
+
+/**
+ ****************************************************************************************
+ * @brief Schedule all pending events.
+ *
+ ****************************************************************************************
+ */
+void rwip_schedule(void);
+
+/**
+ ****************************************************************************************
+ * @brief Invoke the sleep function.
+ *
+ * @return true: processor sleep allowed, false otherwise
+ ****************************************************************************************
+ */
+bool rwip_sleep(void);
+
+#if DEEP_SLEEP
+/**
+ ****************************************************************************************
+ * @brief Handle wake-up.
+ ****************************************************************************************
+ */
+void rwip_wakeup(void);
+
+/**
+ ****************************************************************************************
+ * @brief Handle end of wake-up.
+ ****************************************************************************************
+ */
+void rwip_wakeup_end(void);
+
+/**
+ ****************************************************************************************
+ * @brief Set the wake-up delay
+ *
+ * @param[in] wakeup_delay Wake-up delay in us
+ ****************************************************************************************
+ */
+void rwip_wakeup_delay_set(uint16_t wakeup_delay);
+
+/**
+ ****************************************************************************************
+ * @brief Set a bit in the prevent sleep bit field, in order to prevent the system from
+ * going to sleep
+ *
+ * @param[in] prv_slp_bit Bit to be set in the prevent sleep bit field
+ ****************************************************************************************
+ */
+void rwip_prevent_sleep_set(uint16_t prv_slp_bit);
+
+/**
+ ****************************************************************************************
+ * @brief Clears a bit in the prevent sleep bit field, in order to allow the system
+ * going to sleep
+ *
+ * @param[in] prv_slp_bit Bit to be cleared in the prevent sleep bit field
+ ****************************************************************************************
+ */
+void rwip_prevent_sleep_clear(uint16_t prv_slp_bit);
+
+/**
+ ****************************************************************************************
+ * @brief Check if sleep mode is enable
+ *
+ * @return true if sleep is enable, false otherwise
+ ****************************************************************************************
+ */
+bool rwip_sleep_enable(void);
+
+/**
+ ****************************************************************************************
+ * @brief Check if external wake-up is enable
+ *
+ * @return true if external wakeup is enable, false otherwise
+ ****************************************************************************************
+ */
+bool rwip_ext_wakeup_enable(void);
+
+/**
+ ****************************************************************************************
+ * @brief Converts a duration in lp cycles into a duration is us.
+ *
+ * The function converts a duration in lp cycles into a duration is us, according to the
+ * low power clock frequency (32768Hz or 32000Hz).
+ *
+ * To do this the following formulae are applied:
+ *
+ * Tus = x*30.517578125 = 30*x + x/2 + x/64 + x/512 for a 32.768kHz clock or
+ * Tus = x*31.25 = 31*x + x/4 for a 32kHz clock
+ *
+ * @note This function is also performing a compensation of accumulated drift created by
+ * rounding present in the algorithm
+ *
+ * @param[in] lpcycles duration in lp cycles
+ *
+ * @return duration in us
+ ****************************************************************************************
+ */
+uint32_t rwip_sleep_lpcycles_2_us(uint32_t lpcycles);
+
+
+/**
+ ****************************************************************************************
+ * @brief Converts a duration in us into a duration in lp cycles.
+ *
+ * The function converts a duration in us into a duration is lp cycles, according to the
+ * low power clock frequency (32768Hz or 32000Hz).
+ *
+ * @param[in] us duration in us
+ *
+ * @return duration in lpcycles
+ ****************************************************************************************
+ */
+uint32_t rwip_us_2_lpcycles(uint32_t us);
+#endif // DEEP_SLEEP
+
+#if (BT_EMB_PRESENT)
+
+#if PCA_SUPPORT
+/**
+ ****************************************************************************************
+ * @brief Check if clock dragging limitation
+ *
+ * @return true if clock dragging must be used
+ ****************************************************************************************
+ */
+bool rwip_pca_clock_dragging_only(void);
+#endif //PCA_SUPPORT
+
+/**
+ ****************************************************************************************
+ * @brief Set current time
+ *
+ * @param clock value in half-slots
+ ****************************************************************************************
+ */
+void rwip_time_set(uint32_t clock);
+#endif // (BT_EMB_PRESENT)
+
+#if (BT_EMB_PRESENT || BLE_EMB_PRESENT)
+#if (RW_MWS_COEX)
+/**
+ ****************************************************************************************
+ * @brief Enable/Disable the MWS coexistence interface.
+ *
+ * @param[in] CoexSetting Coexistence value
+ *
+ ****************************************************************************************
+ */
+void rwip_mwscoex_set(bool state);
+#endif //RW_MWS_COEX
+
+#if (RW_WLAN_COEX)
+/**
+ ****************************************************************************************
+ * @brief Enable/Disable the Wireless LAN coexistence interface.
+ *
+ * @param[in] CoexSetting Coexistence value
+ *
+ ****************************************************************************************
+ */
+void rwip_wlcoex_set(bool state);
+#endif //RW_WLAN_COEX
+#endif //(BT_EMB_PRESENT || BLE_EMB_PRESENT)
+
+/**
+ ****************************************************************************************
+ * @brief Function to implement in platform in order to retrieve expected external
+ * interface such as UART for Host Control Interface.
+ *
+ * @param[in] type external interface type (@see rwip_eif_types)
+ *
+ * @return External interface api structure
+ ****************************************************************************************
+ */
+
+extern const struct rwip_eif_api spi_api;
+
+extern const struct rwip_eif_api uart_api;
+
+
+
+
+///@} ROOT
+
+#endif // _RWIP_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwip_config.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwip_config.h
new file mode 100644
index 0000000000..4b98e2886b
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwip_config.h
@@ -0,0 +1,1015 @@
+/**
+ ****************************************************************************************
+ *
+ * @file rwip_config.h
+ *
+ * @brief Configuration of the RW IP SW
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef RWIP_CONFIG_H_
+#define RWIP_CONFIG_H_
+/**
+ ****************************************************************************************
+ * @addtogroup ROOT
+ * @{
+ *
+ * Information about RW SW IP options and flags
+ *
+ * BT_DUAL_MODE BT/BLE Dual Mode
+ * BT_STD_MODE BT Only
+ * BLE_STD_MODE BLE Only
+ *
+ * BT_EMB_PRESENT BT controller exists
+ * BLE_EMB_PRESENT BLE controller exists
+ * BLE_HOST_PRESENT BLE host exists
+ *
+ * @name RW Stack Configuration
+ * @{
+ ****************************************************************************************
+ */
+#define CFG_HOST
+#define CFG_BLE
+#define CFG_AHITLx
+#define CFG_HCITL
+#define CFG_APP
+#define CFG_NVDS
+#define CFG_DBGx
+#define CFG_ALLROLESx //CFG_BROADCASTER//CFG_PERIPHERAL
+#define CFG_PERIPHERAL
+#define CFG_ATTS
+#define CFG_ATTC
+
+#define CFG_SLEEP
+#define CFG_UART_ENABLE
+
+
+#define CFG_APP_SEC
+#define CFG_APP_USER
+//#define CFG_PRF_BASS
+//#define CFG_APP_BATT
+#define CFG_PRF_HTPTx
+/*支æŒçš„最大连接数*/
+#define CFG_CON 1
+
+
+#define CFG_APP_HTx
+#define CFG_PRF
+#define CFG_NB_PRF 1 //1
+
+
+
+#if defined(CFG_DBG)
+#define PLF_DEBUG 1
+#else //CFG_DBG
+#define PLF_DEBUG 0
+#endif //CFG_DBG
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/******************************************************************************************/
+/* ------------------------- QUALIFICATION FLAG ------------------------------------*/
+/******************************************************************************************/
+//Downgrade the stack to version 4.0 /*harry modify: if only support bt4.0, let it be 1*/
+#define BLE_QUALIF 0
+
+
+/******************************************************************************************/
+/* -------------------------- GENERAL SETUP --------------------------------------*/
+/******************************************************************************************/
+
+/// Flag indicating if stack is compiled in dual or single mode
+#if defined(CFG_BT)
+ #define BLE_STD_MODE 0
+ #if defined(CFG_BLE)
+ #define BT_DUAL_MODE 1
+ #define BT_STD_MODE 0
+ #else // CFG_BLE
+ #define BT_DUAL_MODE 0
+ #define BT_STD_MODE 1
+ #endif // CFG_BLE
+#elif defined(CFG_BLE)
+ #define BT_DUAL_MODE 0
+ #define BT_STD_MODE 0
+ #define BLE_STD_MODE 1
+#endif // CFG_BT
+
+/******************************************************************************************/
+/* ------------------------- STACK PARTITIONING -----------------------------------*/
+/******************************************************************************************/
+
+#if (BT_DUAL_MODE)
+ #define BT_EMB_PRESENT 1
+ #define BLE_EMB_PRESENT 1
+ #define HCI_PRESENT 1
+ #define BLE_HOST_PRESENT 0
+ #define BLE_APP_PRESENT 0
+#elif (BT_STD_MODE)
+ #define BT_EMB_PRESENT 1
+ #define BLE_EMB_PRESENT 0
+ #define HCI_PRESENT 1
+ #define BLE_HOST_PRESENT 0
+ #define BLE_APP_PRESENT 0
+#elif (BLE_STD_MODE)
+ #define BT_EMB_PRESENT 0
+ #define HCI_PRESENT 1
+ #if defined(CFG_EMB)
+ #define BLE_EMB_PRESENT 1
+ #else
+ #define BLE_EMB_PRESENT 0
+ #endif //CFG_EMB
+ #if defined(CFG_HOST)
+ #define BLE_HOST_PRESENT 1
+ #else
+ #define BLE_HOST_PRESENT 0
+ #endif //CFG_HOST
+ #if defined(CFG_APP)
+ #define BLE_APP_PRESENT 1
+ #else
+ #define BLE_APP_PRESENT 0
+ #endif //CFG_APP
+#endif // BT_DUAL_MODE / BT_STD_MODE / BLE_STD_MODE
+
+#define EA_PRESENT (BT_EMB_PRESENT || BLE_EMB_PRESENT)
+
+/******************************************************************************************/
+/* ------------------------- INTERFACES DEFINITIONS -------------------------------*/
+/******************************************************************************************/
+
+/// Application Host Interface
+#if defined(CFG_AHITL)
+#define AHI_TL_SUPPORT 1
+#else // defined(CFG_AHITL)
+#define AHI_TL_SUPPORT 0
+#endif // defined(CFG_AHITL)
+
+
+/// Host Controller Interface Support (defines if HCI parser is present or not)
+#if defined(CFG_HCITL)
+#define HCI_TL_SUPPORT 1
+#else //defined(CFG_HCITL)
+#define HCI_TL_SUPPORT 0
+#endif //defined(CFG_HCITL)
+
+
+#if BLE_HOST_PRESENT
+#if BLE_EMB_PRESENT
+#define H4TL_SUPPORT (AHI_TL_SUPPORT)
+#else // !BLE_EMB_PRESENT
+#define H4TL_SUPPORT ((AHI_TL_SUPPORT) + (HCI_TL_SUPPORT))
+#endif // BLE_EMB_PRESENT
+#else // !BLE_HOST_PRESENT
+#define H4TL_SUPPORT (HCI_TL_SUPPORT)
+#endif // BLE_HOST_PRESENT
+
+/// TCI LMP trace support
+#define TCI_LMP_ENABLED 0
+
+/******************************************************************************************/
+/* -------------------------- BLE COMMON DEFINITIONS ------------------------------*/
+/******************************************************************************************/
+/// Kernel Heap memory sized reserved for allocate dynamically connection environment
+#define KE_HEAP_MEM_RESERVED (4)
+
+#if defined(CFG_BLE)
+/// Application role definitions
+#define BLE_BROADCASTER (defined(CFG_BROADCASTER) || defined(CFG_ALLROLES))
+#define BLE_OBSERVER (defined(CFG_OBSERVER) || defined(CFG_ALLROLES))
+#define BLE_PERIPHERAL (defined(CFG_PERIPHERAL) || defined(CFG_ALLROLES))
+#define BLE_CENTRAL (defined(CFG_CENTRAL) || defined(CFG_ALLROLES))
+
+#if (!BLE_BROADCASTER) && (!BLE_OBSERVER) && (!BLE_PERIPHERAL) && (!BLE_CENTRAL)
+ #error "No application role defined"
+#endif /* #if (!BLE_BROADCASTER) && (!BLE_OBSERVER) && (!BLE_PERIPHERAL) && (!BLE_CENTRAL) */
+
+
+/// Maximum number of simultaneous connections
+#if (BLE_CENTRAL)
+ #define BLE_CONNECTION_MAX (CFG_CON)
+#elif (BLE_PERIPHERAL)
+ #define BLE_CONNECTION_MAX (1)
+#else
+ #define BLE_CONNECTION_MAX (0)
+#endif /* #if (BLE_CENTRAL) */
+
+/// Maximum number of audio connections
+#if defined(CFG_AUDIO)
+#if (BLE_CENTRAL || BLE_PERIPHERAL)
+#define BLE_AUDIO (1)
+#define BLE_AUDIO_CONNECT_MAX (CFG_AUDIO_CON)
+#else
+#define BLE_AUDIO (0)
+#endif /*(BLE_CENTRAL || BLE_PERIPHERAL)*/
+#else
+#define BLE_AUDIO (0)
+#endif /*defined(CFG_AUDIO)*/
+
+/// Number of TX data buffer
+#if ((BLE_CONNECTION_MAX == 1) || (BLE_CONNECTION_MAX == 0))
+#if (BLE_CENTRAL || BLE_PERIPHERAL)
+#define BLE_TX_BUFF_DATA (3)
+#else
+#define BLE_TX_BUFF_DATA (0)
+#endif //(BLE_CENTRAL || BLE_PERIPHERAL)
+#else
+#define BLE_TX_BUFF_DATA (BLE_CONNECTION_MAX) // Worst case (one way 251 bytes every 7.5ms)
+#endif //((BLE_CONNECTION_MAX == 1) || (BLE_CONNECTION_MAX == 0))
+
+#if (BLE_CENTRAL || BLE_PERIPHERAL)
+/// Number of TX advertising buffer
+#define BLE_TX_BUFF_ADV (3) // Worst case (1 for CONNECT_REQ, 1 for ADV_DATA and 1 for SCAN_RESP_DATA)
+/// Number of TX control buffer
+#define BLE_TX_BUFF_CNTL (BLE_CONNECTION_MAX) // Worst case (1 dedicated packet by link)
+#else
+/// Margin used for LL fragmentation (DLE feature)
+//#define BLE_TX_DESC_MARGING_DLE (0)
+#if (BLE_BROADCASTER)
+/// Number of TX advertising descriptors
+#define BLE_TX_BUFF_ADV (2)
+/// Number of TX control descriptors
+#define BLE_TX_BUFF_CNTL (0)
+#else
+/// Number of TX advertising descriptors
+#define BLE_TX_BUFF_ADV (1)
+/// Number of TX control descriptors
+#define BLE_TX_BUFF_CNTL (0)
+#endif // BLE_BROADCASTER
+#endif //(BLE_CENTRAL || BLE_PERIPHERAL)
+
+/// Number of elements in the TX Descriptor pool
+// Dedicated for DATA
+// Worst case (1 packets (251 bytes) fragmented into 27 byte = 10)
+#define BLE_TX_DESC_DATA ((BLE_TX_BUFF_DATA) * 10)
+// Dedicated for CONTROL
+#define BLE_TX_DESC_CNTL (BLE_TX_BUFF_CNTL)
+// Dedicated for ADVERTISING
+#define BLE_TX_DESC_ADV (BLE_TX_BUFF_ADV)
+
+/// Number of TX Buffers
+#define BLE_TX_BUFFER_CNT (BLE_TX_BUFF_DATA)
+
+/// Total number of elements in the TX Descriptor pool
+#define BLE_TX_DESC_CNT (BLE_TX_DESC_CNTL + BLE_TX_DESC_ADV + BLE_TX_DESC_DATA)
+
+
+/// Number of receive buffers in the RX ring. This number defines the interrupt
+/// rate during a connection event. An interrupt is asserted every BLE_RX_BUFFER_CNT/2
+/// reception. This number has an impact on the size of the exchange memory. This number
+/// may have to be increased when CPU is very slow to free the received data, in order not
+/// to overflow the RX ring of buffers.
+
+#if (BLE_CENTRAL || BLE_PERIPHERAL)
+ /// Number of RX Descriptors
+ #define BLE_RX_DESC_CNT (8)
+#elif (BLE_BROADCASTER)
+ #define BLE_RX_DESC_CNT (1)
+#else
+ #define BLE_RX_DESC_CNT (4)
+#endif //(BLE_CENTRAL || BLE_PERIPHERAL)
+/// Number of RX Buffers
+#define BLE_RX_BUFFER_CNT (BLE_RX_DESC_CNT)
+
+/// Max advertising reports before sending the info to the host
+#define BLE_ADV_REPORTS_MAX 1
+
+
+/// Define Number of AUDIO TX/RX buffers per voice channel
+#if (BLE_AUDIO)
+ #if defined(CFG_AUDIO_AOAHI)
+ // 3 buffers per connection using audio over AHI TL
+ #define BLE_NB_INPUT_BUFF_PER_VC (3)
+ #define BLE_NB_OUTPUT_BUFF_PER_VC (3)
+ #else // defined(CFG_AUDIO_AOAHI)
+ // 2 buffers if a codec is available
+ #define BLE_NB_INPUT_BUFF_PER_VC (2)
+ #define BLE_NB_OUTPUT_BUFF_PER_VC (2)
+ #endif // defined(CFG_AUDIO_AOAHI)
+ // add one more buffer for fake reception and fake transmit
+ #define BLE_TX_AUDIO_BUFFER_CNT ((BLE_AUDIO_CONNECT_MAX * BLE_NB_INPUT_BUFF_PER_VC) + 1)
+ #define BLE_RX_AUDIO_BUFFER_CNT ((BLE_AUDIO_CONNECT_MAX * BLE_NB_OUTPUT_BUFF_PER_VC) + 1)
+#endif // (BLE_AUDIO)
+#endif //defined(CFG_BLE)
+
+
+/******************************************************************************************/
+/* -------------------------- DISPLAY SETUP -------------------------------------*/
+/******************************************************************************************/
+
+/// Display controller enable/disable
+#if defined(CFG_DISPLAY)
+#define DISPLAY_SUPPORT 1
+#else
+#define DISPLAY_SUPPORT 0
+#endif //CFG_DISPLAY
+
+
+/******************************************************************************************/
+/* -------------------------- RTC SETUP -------------------------------------*/
+/******************************************************************************************/
+
+/// RTC enable/disable
+#if defined(CFG_RTC)
+#define RTC_SUPPORT 1
+#else
+#define RTC_SUPPORT 0
+#endif //CFG_DISPLAY
+
+/******************************************************************************************/
+/* -------------------------- PS2 SETUP -------------------------------------*/
+/******************************************************************************************/
+
+/// PS2 enable/disable
+#if defined(CFG_PS2)
+#define PS2_SUPPORT 1
+#else
+#define PS2_SUPPORT 0
+#endif //CFG_PS2
+
+
+/******************************************************************************************/
+/* ------------------------- DEEP SLEEP SETUP -------------------------------------*/
+/******************************************************************************************/
+
+/// DEEP SLEEP enable
+#if defined(CFG_SLEEP) && (BLE_EMB_PRESENT || BT_EMB_PRESENT)
+ #define DEEP_SLEEP 1
+#else
+ #define DEEP_SLEEP 0
+#endif /* CFG_SLEEP */
+
+/// Use 32K Hz Clock if set to 1 else 32,768k is used
+#define HZ32000 0
+
+/// Time to wake-up Radio Module (in us)
+#define SLEEP_RM_WAKEUP_DELAY 625
+/// Time for stabilization of the high frequency oscillator following a sleep-timer expiry (in us)
+#define SLEEP_OSC_NORMAL_WAKEUP_DELAY 5000
+/// Time for stabilization of the high frequency oscillator following an external wake-up request (in us)
+#define SLEEP_OSC_EXT_WAKEUP_DELAY 5000
+
+
+/******************************************************************************************/
+/* ------------------------- PROCESSOR SETUP -------------------------------------*/
+/******************************************************************************************/
+
+/// 8 BIT processor
+#define PROC_8BITS 0
+
+/******************************************************************************************/
+/* -------------------------- RADIO SETUP ----------------------------------------*/
+/******************************************************************************************/
+
+/// Power control features
+#define RF_TXPWR 1
+/// Class of device
+#define RF_CLASS1 0
+
+/******************************************************************************************/
+/* ------------------------- COEXISTENCE SETUP ------------------------------------*/
+/******************************************************************************************/
+
+/// WLAN Coexistence
+#if 1/*defined(CFG_WLAN_COEX)*/
+ #define RW_WLAN_COEX 1
+ #define RW_WLAN_COEX_TEST (defined(CFG_WLAN_COEX_TEST))
+#else
+ #define RW_WLAN_COEX 0
+ #define RW_WLAN_COEX_TEST 0
+#endif // defined(CFG_WLAN_COEX)
+
+/// MWS Coexistence
+#if defined(CFG_MWS_COEX)
+ #define RW_MWS_COEX 1
+ #define RW_MWS_COEX_TEST (defined(CFG_MWS_COEX_TEST))
+#else
+ #define RW_MWS_COEX 0
+ #define RW_MWS_COEX_TEST 0
+#endif // defined(CFG_MWS_COEX)
+
+/******************************************************************************************/
+/* ------------------------- DM ARBITRATION SETUP ---------------------------------*/
+/******************************************************************************************/
+
+#if BT_DUAL_MODE
+/**
+ * Dual mode arbitration margin (in us)
+ *
+ * BREDRMARGIN/BLEMARGIN corresponding to a timing value that allows the RF to power-down properly before any other
+ * activity. This is radio dependent.
+ */
+#define DM_ARB_MARGIN 40
+#endif //BT_DUAL_MODE
+
+/******************************************************************************************/
+/* ------------------------- CHANNEL ASSESSMENT SETUP -----------------------------*/
+/******************************************************************************************/
+
+/// Channel Assessment
+#if defined(CFG_BLE)
+#if (defined(CFG_CHNL_ASSESS) && BLE_CENTRAL)
+ #define BLE_CHNL_ASSESS (1)
+#else
+ #define BLE_CHNL_ASSESS (0)
+#endif //(defined(CFG_CHNL_ASSESS) && BLE_CENTRAL)
+#endif //defined(CFG_BLE)
+
+/******************************************************************************************/
+/* -------------------- SECURE CONNECTIONS SETUP --------------------------------------*/
+/******************************************************************************************/
+#if defined(CFG_SEC_CON)
+ #define SECURE_CONNECTIONS (1)
+ #if defined(CFG_ECC_16_BITS_ALGO)
+ #define ECC_MULT_ALGO_TYPE (16)
+ #else // !defined(CFG_ECC_16_BITS_ALGO)
+ #define ECC_MULT_ALGO_TYPE (32)
+ #endif // defined(CFG_ECC_16_BITS_ALGO)
+ #if defined(CFG_CRYPTO_UT)
+ #define CRYPTO_UT (1)
+ #else //defined(CFG_CRYPTO_UT)
+ #define CRYPTO_UT (0)
+ #endif //defined(CFG_CRYPTO_UT)
+#else // !defined(CFG_SEC_CON)
+ #define SECURE_CONNECTIONS (0)
+ #define CRYPTO_UT (0)
+#endif // defined(CFG_SEC_CON)
+
+/******************************************************************************************/
+/* ---------------------------- AUDIO SETUP ------------------------------------*/
+/******************************************************************************************/
+
+/// Flag indicating if audio is available or not
+#if defined(CFG_HW_AUDIO)
+#define HW_AUDIO 1
+#else // defined (CFG_BLE_AUDIO)
+#define HW_AUDIO 0
+#endif // defined (CFG_BLE_AUDIO)
+
+/******************************************************************************************/
+/* -------------------------- DEBUG SETUP ----------------------------------------*/
+/******************************************************************************************/
+
+/// Flag indicating if debug mode is activated or not
+#if defined(CFG_DBG)
+ #define RW_DEBUG ((BLE_EMB_PRESENT) || (BT_EMB_PRESENT) || (BLE_HOST_PRESENT))
+#if (BLE_EMB_PRESENT || BT_EMB_PRESENT)
+ #define RW_SWDIAG 1
+#else
+ #define RW_SWDIAG 0
+#endif
+ #define KE_PROFILING 1
+#else
+ #define RW_DEBUG 0
+ #define RW_SWDIAG 0
+ #define KE_PROFILING 0
+#endif /* CFG_DBG */
+
+/// Flag indicating if Read/Write memory commands are supported or not
+#if defined(CFG_DBG_MEM)
+ #define RW_DEBUG_MEM 1
+#else //CFG_DBG_MEM
+ #define RW_DEBUG_MEM 0
+#endif //CFG_DBG_MEM
+
+/// Flag indicating if Flash debug commands are supported or not
+#if defined(CFG_DBG_FLASH)
+ #define RW_DEBUG_FLASH 1
+#else //CFG_DBG_FLASH
+ #define RW_DEBUG_FLASH 0
+#endif //CFG_DBG_FLASH
+
+/// Flag indicating if NVDS feature is supported or not
+#if defined(CFG_DBG_NVDS)
+ #define RW_DEBUG_NVDS 1
+#else //CFG_DBG_NVDS
+ #define RW_DEBUG_NVDS 0
+#endif //CFG_DBG_NVDS
+
+/// Flag indicating if CPU stack profiling commands are supported or not
+#if defined(CFG_DBG_STACK_PROF)
+ #define RW_DEBUG_STACK_PROF 1
+#else
+ #define RW_DEBUG_STACK_PROF 0
+#endif // defined (CFG_DBG_STACK_PROF)
+
+/// Modem back to back setup
+#define MODEM2MODEM 0
+/// Special clock testing
+#define CLK_WRAPPING 0
+
+/******************************************************************************************/
+/* -------------------------- NVDS SETUP --------------------------------------*/
+/******************************************************************************************/
+
+/// Flag indicating if NVDS feature is supported or not
+#if defined(CFG_NVDS)
+ #define NVDS_SUPPORT 1
+#else //CFG_DBG_NVDS
+ #define NVDS_SUPPORT 0
+#endif //CFG_DBG_NVDS
+
+/******************************************************************************************/
+/* -------------------------- MISC SETUP --------------------------------------*/
+/******************************************************************************************/
+/// Manufacturer: RivieraWaves SAS
+#define RW_COMP_ID 0x0060
+
+/// Bluetooth technologies version
+#define RW_BT40_VERSION (6)
+#define RW_BT41_VERSION (7)
+#define RW_BT42_VERSION (8)
+
+/******************************************************************************************/
+/* ------------------------- BT / BLE / BLE HL CONFIG -------------------------------*/
+/******************************************************************************************/
+
+#if (BT_EMB_PRESENT)
+#include "rwbt_config.h" // bt stack configuration
+#endif //BT_EMB_PRESENT
+
+#if (BLE_EMB_PRESENT) || (BLE_HOST_PRESENT)
+#include "rwble_config.h" // ble stack configuration
+#endif //BLE_EMB_PRESENT
+
+#if (BLE_HOST_PRESENT)
+#include "rwble_hl_config.h" // ble Host stack configuration
+#endif //BLE_HOST_PRESENT
+
+#if defined(CFG_AUDIO_AM0)
+#include "rwam0_config.h" // Audio Mode 0 configuration
+#endif // defined(CFG_AUDIO_AM0)
+
+#if defined(CFG_APP)
+#include "rwapp_config.h" // Audio Mode 0 configuration
+#endif // defined(CFG_APP)
+
+
+
+/******************************************************************************************/
+/* ------------------------- KERNEL SETUP -------------------------------------*/
+/******************************************************************************************/
+
+/// Flag indicating Kernel is supported
+#define KE_SUPPORT (BLE_EMB_PRESENT || BT_EMB_PRESENT || BLE_HOST_PRESENT || BLE_APP_PRESENT)
+
+
+/// Event types definition
+enum KE_EVENT_TYPE
+{
+ #if DISPLAY_SUPPORT
+ KE_EVENT_DISPLAY ,
+ #endif //DISPLAY_SUPPORT
+
+ #if RTC_SUPPORT
+ KE_EVENT_RTC_1S_TICK ,
+ #endif //RTC_SUPPORT
+
+ #ifdef CFG_AUDIO_RSA
+ KE_EVENT_RSA_SIGN,
+ #endif // CFG_AUDIO_RSA
+
+ #if SECURE_CONNECTIONS
+ KE_EVENT_ECC_MULTIPLICATION,
+ #endif // SECURE_CONNECTIONS
+
+ #if BLE_EMB_PRESENT
+ KE_EVENT_BLE_CRYPT ,
+ #endif //BLE_EMB_PRESENT
+
+ KE_EVENT_KE_MESSAGE , // 0
+ KE_EVENT_KE_TIMER , // 1
+
+ #if (AHI_TL_SUPPORT)
+ KE_EVENT_AHI_TX_DONE ,
+ #endif //(AHI_TL_SUPPORT)
+
+
+ #if H4TL_SUPPORT // 2
+ KE_EVENT_H4TL_TX ,
+ #if (BLE_EMB_PRESENT || BT_EMB_PRESENT)
+ KE_EVENT_H4TL_CMD_HDR_RX ,
+ KE_EVENT_H4TL_CMD_PLD_RX ,
+ #endif //(BLE_EMB_PRESENT || BT_EMB_PRESENT)
+ #endif //H4TL_SUPPORT
+
+ #if (BLE_HOST_PRESENT)
+ #if (BLE_L2CC)
+ KE_EVENT_L2CAP_TX ,// 3
+ #endif //(BLE_L2CC)
+ #endif// (BLE_HOST_PRESENT)
+
+ #if BT_EMB_PRESENT
+ KE_EVENT_BT_PSCAN_PROC ,
+ #endif //BT_EMB_PRESENT
+
+ #if BLE_EMB_PRESENT
+ KE_EVENT_BLE_EVT_DEFER ,
+ KE_EVENT_BLE_EVT_DELETE ,
+ #endif //BLE_EMB_PRESENT
+
+ #if defined(CFG_AUDIO_AOAHI)
+ KE_EVENT_BLE_AUDIO_DEFER ,
+ #endif // defined(CFG_AUDIO_AOAHI)
+
+ KE_EVENT_MAX ,
+};
+
+/// Tasks types definition
+enum KE_TASK_TYPE
+{
+#if (BT_EMB_PRESENT) //0
+ // BT Controller Tasks44
+ TASK_LM,
+ TASK_LC,
+ TASK_LB,
+ TASK_LD,
+ TASK_HCI,
+#endif // (BT_EMB_PRESENT)
+
+#if (BLE_EMB_PRESENT) //0
+ // Link Layer Tasks
+ TASK_LLM ,
+ TASK_LLC ,
+ TASK_LLD ,
+#endif // (BLE_EMB_PRESENT)
+
+#if ((BLE_EMB_PRESENT) || (BT_EMB_PRESENT)) //0
+ TASK_DBG,
+#endif // ((BLE_EMB_PRESENT) || (BT_EMB_PRESENT))
+
+#if (DISPLAY_SUPPORT) //0
+ TASK_DISPLAY,
+#endif // (DISPLAY_SUPPORT)
+
+#if (BLE_APP_PRESENT)
+ TASK_APP,
+#endif // (BLE_APP_PRESENT)
+
+#if (BLE_HOST_PRESENT)
+ TASK_L2CC, // L2CAP Controller Task
+ TASK_GATTM, // Generic Attribute Profile Manager Task
+ TASK_GATTC, // Generic Attribute Profile Controller Task
+ TASK_GAPM, // Generic Access Profile Manager
+ TASK_GAPC, // Generic Access Profile Controller
+
+ // allocate a certain number of profiles task
+ TASK_PRF_MAX = (TASK_GAPC + BLE_NB_PROFILES),
+
+ #ifdef BLE_AUDIO_AM0_TASK
+ TASK_AM0, // BLE Audio Mode 0 Task
+ #endif // BLE_AUDIO_AM0_TASK
+#endif // (BLE_HOST_PRESENT)
+
+#if (AHI_TL_SUPPORT)
+ TASK_AHI,
+#endif // (AHI_TL_SUPPORT)
+
+ /// Maximum number of tasks
+ TASK_MAX,
+
+ TASK_NONE = 0xFF,
+};
+
+/// Kernel memory heaps types.
+enum
+{
+ /// Memory allocated for environment variables
+ KE_MEM_ENV,
+ #if (BLE_HOST_PRESENT)
+ /// Memory allocated for Attribute database
+ KE_MEM_ATT_DB,
+ #endif // (BLE_HOST_PRESENT)
+ /// Memory allocated for kernel messages
+ KE_MEM_KE_MSG,
+ /// Non Retention memory block
+ KE_MEM_NON_RETENTION,
+ KE_MEM_BLOCK_MAX,
+};
+
+
+
+#if (BT_EMB_PRESENT)
+#define BT_HEAP_MSG_SIZE_ BT_HEAP_MSG_SIZE
+#define BT_HEAP_ENV_SIZE_ BT_HEAP_ENV_SIZE
+#else
+#define BT_HEAP_MSG_SIZE_ 0
+#define BT_HEAP_ENV_SIZE_ 0
+#endif //BT_EMB_PRESENT
+
+#if (BLE_EMB_PRESENT)
+#define BLE_HEAP_MSG_SIZE_ BLE_HEAP_MSG_SIZE
+#define BLE_HEAP_ENV_SIZE_ BLE_HEAP_ENV_SIZE
+#else
+#define BLE_HEAP_MSG_SIZE_ 0
+#define BLE_HEAP_ENV_SIZE_ 0
+#endif //BLE_EMB_PRESENT
+
+#if (BLE_HOST_PRESENT)
+
+#define BLEHL_HEAP_MSG_SIZE_ BLEHL_HEAP_MSG_SIZE
+#define BLEHL_HEAP_ENV_SIZE_ BLEHL_HEAP_ENV_SIZE
+#define BLEHL_HEAP_DB_SIZE_ BLEHL_HEAP_DB_SIZE
+#else
+#define BLEHL_HEAP_MSG_SIZE_ 0
+#define BLEHL_HEAP_ENV_SIZE_ 0
+#define BLEHL_HEAP_DB_SIZE_ 0
+#endif //BLE_HOST_PRESENT
+
+/// Kernel Message Heap
+#define RWIP_HEAP_MSG_SIZE ( BT_HEAP_MSG_SIZE_ + \
+ BLE_HEAP_MSG_SIZE_ + \
+ BLEHL_HEAP_MSG_SIZE_ )
+
+/// Number of link in kernel environment
+#define KE_NB_LINK_IN_HEAP_ENV 1 // 4 by bottle
+
+/// Size of Environment heap
+#define RWIP_HEAP_ENV_SIZE ( BT_HEAP_ENV_SIZE_ + \
+ ( BLE_HEAP_ENV_SIZE_ + \
+ BLEHL_HEAP_ENV_SIZE_ ) \
+ * KE_NB_LINK_IN_HEAP_ENV )
+
+/// Size of Attribute database heap
+#define RWIP_HEAP_DB_SIZE ( BLEHL_HEAP_DB_SIZE )
+
+/// Size of non retention heap - 512 bytes per ble link plus 4096 bytes for data throughput should be sufficient and should be tuned
+#if (BLE_EMB_PRESENT || BLE_HOST_PRESENT)
+#define RWIP_HEAP_NON_RET_SIZE (( 512 * BLE_CONNECTION_MAX ) + 3072)
+#else
+#define RWIP_HEAP_NON_RET_SIZE ( 1024 )
+#endif
+
+/// Minimum sleep time to enter in deep sleep (in half slot).
+#define RWIP_MINIMUM_SLEEP_TIME (1)
+
+/******************************************************************************************/
+/* ------------------------- BT-BLE COEX -----------------------------------*/
+/******************************************************************************************/
+#if (BLE_EMB_PRESENT || BT_EMB_PRESENT)
+/// Enable and diable definition for the PTI
+///Enable TX busy signal
+#define RWIP_PTI_TXEN 1
+///Disable TX busy signal
+#define RWIP_PTI_TXDIS 0
+/// Tx busy position
+#define RWIP_TXBSY_POS 0
+
+///Enable RX busy signal
+#define RWIP_PTI_RXEN 1
+///Disable RX busy signal
+#define RWIP_PTI_RXDIS 0
+/// Rx busy position
+#define RWIP_RXBSY_POS 1
+
+///Enable do not abort TX
+#define RWIP_PTI_DNABORTEN 1
+///Disable do not abort TX
+#define RWIP_PTI_DNABORTDIS 0
+/// Do not abort busy position
+#define RWIP_DNABORT_POS 2
+
+///Allows Tx operation in the current frame.
+#define RWIP_MWS_TXEN 0
+///Prevent from any Tx operation in the current frame.
+#define RWIP_MWS_TXDIS 1
+/// MWS transmit disable position
+#define RWIP_MWSTXDSB_POS 3
+
+///Allows Rx operation in the current frame.
+#define RWIP_MWS_RXEN 0
+///Prevent from any Rx operation in the current frame.
+#define RWIP_MWS_RXDIS 1
+/// MWS transmit disable position
+#define RWIP_MWSRXDSB_POS 4
+
+/// Bit masking
+#define RWIP_COEX_BIT_MASK 1
+
+/// Coex configuration index
+enum rwip_coex_config_idx
+{
+ #if (BT_EMB_PRESENT)
+ RWIP_COEX_MSSWITCH_IDX ,
+ RWIP_COEX_SNIFFATT_IDX ,
+ RWIP_COEX_PAGE_IDX,
+ RWIP_COEX_PSCAN_IDX,
+ RWIP_COEX_INQ_IDX,
+ RWIP_COEX_INQRES_IDX,
+ RWIP_COEX_SCORSVD_IDX,
+ RWIP_COEX_BCAST_IDX,
+ RWIP_COEX_CONNECT_IDX,
+ #endif //#if (BT_EMB_PRESENT)
+ #if (BLE_EMB_PRESENT)
+ RWIP_COEX_CON_IDX,
+ RWIP_COEX_CON_DATA_IDX,
+ RWIP_COEX_ADV_IDX,
+ RWIP_COEX_SCAN_IDX,
+ RWIP_COEX_INIT_IDX,
+ #endif // #if (BLE_EMB_PRESENT)
+ /// Max configuration index
+ RWIP_COEX_CFG_MAX,
+};
+/******************************************************************************************/
+/* ------------------------- BT-BLE PRIORITIES -----------------------------------*/
+/******************************************************************************************/
+/// Priority index definition
+enum rwip_prio_idx
+{
+ #if (BT_EMB_PRESENT)
+ /// ACL event default priority
+ RWIP_PRIO_ACL_DFT_IDX,
+ /// ACL event priority with activity
+ RWIP_PRIO_ACL_ACT_IDX,
+ /// ACL Role Switch event default priority
+ RWIP_PRIO_ACL_RSW_IDX,
+ /// ACL sniff event default priority
+ RWIP_PRIO_ACL_SNIFF_DFT_IDX,
+ /// ACL sniff transition event default priority
+ RWIP_PRIO_ACL_SNIFF_TRANS_IDX,
+ #if MAX_NB_SYNC
+ /// SCO event default priority
+ RWIP_PRIO_SCO_DFT_IDX,
+ #endif //MAX_NB_SYNC
+ /// Broadcast ACL event default priority
+ RWIP_PRIO_BCST_DFT_IDX,
+ /// Broadcast ACL event with LMP activity priority
+ RWIP_PRIO_BCST_ACT_IDX,
+ /// CSB RX event default priority
+ RWIP_PRIO_CSB_RX_DFT_IDX,
+ /// CSB TX event default priority
+ RWIP_PRIO_CSB_TX_DFT_IDX,
+ /// Inquiry event default priority
+ RWIP_PRIO_INQ_DFT_IDX,
+ /// Inquiry Scan event default priority
+ RWIP_PRIO_ISCAN_DFT_IDX,
+ /// Page event default priority
+ RWIP_PRIO_PAGE_DFT_IDX,
+ /// Page event default priority
+ RWIP_PRIO_PAGE_1ST_PKT_IDX,
+ /// Page first packet event default priority
+ RWIP_PRIO_PCA_DFT_IDX,
+ /// Page scan event default priority
+ RWIP_PRIO_PSCAN_DFT_IDX,
+ /// Page scan event priority increment when canceled
+ RWIP_PRIO_PSCAN_1ST_PKT_IDX,
+ /// Synchronization Scan event default priority
+ RWIP_PRIO_SSCAN_DFT_IDX,
+ /// Synchronization Train event default priority
+ RWIP_PRIO_STRAIN_DFT_IDX,
+ #endif //#if (BT_EMB_PRESENT)
+ #if (BLE_EMB_PRESENT)
+ /// Default priority for scanning events
+ RWIP_PRIO_SCAN_IDX,
+ /// Default priority for initiating events
+ RWIP_PRIO_INIT_IDX,
+ /// Default priority for Le connection establishment
+ RWIP_PRIO_LE_ESTAB_IDX,
+ /// Default priority for Idle connection
+ RWIP_PRIO_LE_CON_IDLE_IDX,
+ /// Default priority for active connect events
+ RWIP_PRIO_LE_CON_ACT_IDX,
+ /// Default priority for advertising events
+ RWIP_PRIO_ADV_IDX,
+ /// Default priority for advertising high duty cycle events
+ RWIP_PRIO_ADV_HDC_IDX,
+ #endif // #if (BLE_EMB_PRESENT)
+ RWIP_PRIO_IDX_MAX
+};
+/// Default priority value definition
+enum rwip_prio_dft
+{
+ #if (BT_EMB_PRESENT)
+ /// ACL event default priority
+ RWIP_PRIO_ACL_DFT = 5,
+ /// ACL event priority with activity
+ RWIP_PRIO_ACL_ACT = 10,
+ /// ACL Role Switch event default priority
+ RWIP_PRIO_ACL_RSW = 20,
+ /// ACL sniff event default priority
+ RWIP_PRIO_ACL_SNIFF_DFT = 15,
+ /// ACL sniff transition event default priority
+ RWIP_PRIO_ACL_SNIFF_TRANS = 10,
+ #if MAX_NB_SYNC
+ /// SCO event default priority
+ RWIP_PRIO_SCO_DFT = 18,
+ #endif //MAX_NB_SYNC
+ /// Broadcast ACL event default priority
+ RWIP_PRIO_BCST_DFT = 5,
+ /// Broadcast ACL event with LMP activity priority
+ RWIP_PRIO_BCST_ACT = 10,
+ /// CSB RX event default priority
+ RWIP_PRIO_CSB_RX_DFT = 10,
+ /// CSB TX event default priority
+ RWIP_PRIO_CSB_TX_DFT = 10,
+ /// Inquiry event default priority
+ RWIP_PRIO_INQ_DFT = 5,
+ /// Inquiry Scan event default priority
+ RWIP_PRIO_ISCAN_DFT = 5,
+ /// Page event default priority
+ RWIP_PRIO_PAGE_DFT = 8,
+ /// Page first packet event default priority
+ RWIP_PRIO_PAGE_1ST_PKT = 20,
+ /// PCA event default priority
+ RWIP_PRIO_PCA_DFT = 20,
+ /// Page scan event default priority
+ RWIP_PRIO_PSCAN_DFT = 8,
+ /// Page scan event priority increment when canceled
+ RWIP_PRIO_PSCAN_1ST_PKT = 20,
+ /// Synchronization Scan event default priority
+ RWIP_PRIO_SSCAN_DFT = 10,
+ /// Synchronization Train event default priority
+ RWIP_PRIO_STRAIN_DFT = 10,
+ #endif //#if (BT_EMB_PRESENT)
+ #if (BLE_EMB_PRESENT)
+ /// Default priority for scanning events
+ RWIP_PRIO_SCAN_DFT = 5,
+ /// Default priority for initiating events
+ RWIP_PRIO_INIT_DFT = 10,
+ /// Default priority for LE connection establishment
+ RWIP_PRIO_LE_ESTAB_DFT = 20,
+ /// Default priority for Idle connection
+ RWIP_PRIO_LE_CON_IDLE_DFT = 10,
+ /// Default priority for active connect events
+ RWIP_PRIO_LE_CON_ACT_DFT = 15,
+ /// Default priority for advertising events
+ RWIP_PRIO_ADV_DFT = 5,
+ /// Default priority for advertising high duty cycle events
+ RWIP_PRIO_ADV_HDC_DFT = 10,
+ #endif // #if (BLE_EMB_PRESENT)
+ /// Max priority
+ RWIP_PRIO_MAX = 31,
+};
+
+/// Default increment value definition
+enum rwip_incr_dft
+{
+ #if (BT_EMB_PRESENT)
+ /// ACL event default increment
+ RWIP_INCR_ACL_DFT = 1,
+ /// ACL event increment with activity
+ RWIP_INCR_ACL_ACT = 1,
+ /// ACL Role Switch event default increment
+ RWIP_INCR_ACL_RSW = 1,
+ /// ACL sniff event default increment
+ RWIP_INCR_ACL_SNIFF_DFT = 1,
+ /// ACL sniff transition event default increment
+ RWIP_INCR_ACL_SNIFF_TRANS = 1,
+ #if MAX_NB_SYNC
+ /// SCO event default increment
+ RWIP_INCR_SCO_DFT = 1,
+ #endif //MAX_NB_SYNC
+ /// Broadcast ACL event default increment
+ RWIP_INCR_BCST_DFT = 1,
+ /// Broadcast ACL event with LMP activity increment
+ RWIP_INCR_BCST_ACT = 1,
+ /// CSB RX event default increment
+ RWIP_INCR_CSB_RX_DFT = 1,
+ /// CSB TX event default increment
+ RWIP_INCR_CSB_TX_DFT = 1,
+ /// Inquiry event default increment
+ RWIP_INCR_INQ_DFT = 1,
+ /// Inquiry Scan event default increment
+ RWIP_INCR_ISCAN_DFT = 1,
+ /// Page event default increment
+ RWIP_INCR_PAGE_DFT = 1,
+ /// Page event default increment
+ RWIP_INCR_PAGE_1ST_PKT = 2,
+ /// Page first packet event default increment
+ RWIP_INCR_PCA_DFT = 1,
+ /// Page scan event default increment
+ RWIP_INCR_PSCAN_DFT = 1,
+ /// Page scan event increment increment when canceled
+ RWIP_INCR_PSCAN_1ST_PKT = 1,
+ /// Synchronization Scan event default increment
+ RWIP_INCR_SSCAN_DFT = 1,
+ /// Synchronization Train event default increment
+ RWIP_INCR_STRAIN_DFT = 1,
+ #endif //#if (BT_EMB_PRESENT)
+ #if (BLE_EMB_PRESENT)
+ /// Default increment for scanning events
+ RWIP_INCR_SCAN_DFT = 1,
+ /// Default increment for initiating events
+ RWIP_INCR_INIT_DFT = 1,
+ /// Default increment for LE connection establishment
+ RWIP_INCR_LE_ESTAB_DFT = 1,
+ /// Default increment for Idle connection
+ RWIP_INCR_LE_CON_IDLE_DFT = 1,
+ /// Default increment for active connect events
+ RWIP_INCR_LE_CON_ACT_DFT = 11,
+ /// Default increment for advertising events
+ RWIP_INCR_ADV_DFT = 1,
+ /// Default increment for advertising high duty cycle events
+ RWIP_INCR_ADV_HDC_PRIO_DFT = 1,
+ #endif // #if (BLE_EMB_PRESENT)
+};
+#endif //#if (BLE_EMB_PRESENT || BT_EMB_PRESENT)
+/// @} BT Stack Configuration
+/// @} ROOT
+
+#endif //RWIP_CONFIG_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwip_task.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwip_task.h
new file mode 100644
index 0000000000..75da9ee149
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwip_task.h
@@ -0,0 +1,164 @@
+/**
+ ****************************************************************************************
+ *
+ * @file rwip_task.h
+ *
+ * @brief Task Identifier description for the RW IP
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ ****************************************************************************************
+ */
+
+#ifndef RWIP_TASK_H_
+#define RWIP_TASK_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup ROOT
+ * @{
+ *
+ * Information about RW SW TASK
+ *
+ * @name RW TASK Configuration
+ * @{
+ ****************************************************************************************
+ */
+
+#include
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+
+/// Build the first message ID of a task. (in fact a ke_msg_id_t)
+#define TASK_FIRST_MSG(task) ((uint16_t)((task) << 8))
+
+/// Builds the task identifier from the type and the index of that task.
+#define TASK_BUILD(type, index) ((uint16_t)(((index) << 8)|(type)) )
+
+/// Retrieves task type from task id.
+#define TASK_TYPE_GET(ke_task_id) ((uint16_t) & 0xFF)
+
+/// Retrieves task index number from task id.
+#define TASK_IDX_GET(ke_task_id) (((uint16_t) >> 8) & 0xFF)
+
+
+/// Tasks types definition, this value shall be in [0-254] range
+enum TASK_API_ID
+{
+ // Link Layer Tasks
+ TASK_ID_LLM = 0,
+ TASK_ID_LLC = 1,
+ TASK_ID_LLD = 2,
+ TASK_ID_DBG = 3,
+
+ // BT Controller Tasks
+ TASK_ID_LM = 4,
+ TASK_ID_LC = 5,
+ TASK_ID_LB = 6,
+ TASK_ID_LD = 7,
+
+ TASK_ID_HCI = 8,
+ TASK_ID_DISPLAY = 9,
+
+ // -----------------------------------------------------------------------------------
+ // --------------------- BLE HL TASK API Identifiers ---------------------------------
+ // -----------------------------------------------------------------------------------
+
+ TASK_ID_L2CC = 10, // L2CAP Controller Task
+ TASK_ID_GATTM = 11, // Generic Attribute Profile Manager Task
+ TASK_ID_GATTC = 12, // Generic Attribute Profile Controller Task
+ TASK_ID_GAPM = 13, // Generic Access Profile Manager
+ TASK_ID_GAPC = 14, // Generic Access Profile Controller
+
+ TASK_ID_APP = 15, // Application API
+ TASK_ID_AHI = 16, // Application Host Interface
+
+ // -----------------------------------------------------------------------------------
+ // --------------------- BLE Profile TASK API Identifiers ----------------------------
+ // -----------------------------------------------------------------------------------
+ TASK_ID_DISS = 20, // Device Information Service Server Task
+ TASK_ID_DISC = 21, // Device Information Service Client Task
+
+ TASK_ID_PROXM = 22, // Proximity Monitor Task
+ TASK_ID_PROXR = 23, // Proximity Reporter Task
+
+ TASK_ID_FINDL = 24, // Find Me Locator Task
+ TASK_ID_FINDT = 25, // Find Me Target Task
+
+ TASK_ID_HTPC = 26, // Health Thermometer Collector Task
+ TASK_ID_HTPT = 27, // Health Thermometer Sensor Task
+
+ TASK_ID_BLPS = 28, // Blood Pressure Sensor Task
+ TASK_ID_BLPC = 29, // Blood Pressure Collector Task
+
+ TASK_ID_HRPS = 30, // Heart Rate Sensor Task
+ TASK_ID_HRPC = 31, // Heart Rate Collector Task
+
+ TASK_ID_TIPS = 32, // Time Server Task
+ TASK_ID_TIPC = 33, // Time Client Task
+
+ TASK_ID_SCPPS = 34, // Scan Parameter Profile Server Task
+ TASK_ID_SCPPC = 35, // Scan Parameter Profile Client Task
+
+ TASK_ID_BASS = 36, // Battery Service Server Task
+ TASK_ID_BASC = 37, // Battery Service Client Task
+
+ TASK_ID_HOGPD = 38, // HID Device Task
+ TASK_ID_HOGPBH = 39, // HID Boot Host Task
+ TASK_ID_HOGPRH = 40, // HID Report Host Task
+
+ TASK_ID_GLPS = 41, // Glucose Profile Sensor Task
+ TASK_ID_GLPC = 42, // Glucose Profile Collector Task
+
+ TASK_ID_RSCPS = 43, // Running Speed and Cadence Profile Server Task
+ TASK_ID_RSCPC = 44, // Running Speed and Cadence Profile Collector Task
+
+ TASK_ID_CSCPS = 45, // Cycling Speed and Cadence Profile Server Task
+ TASK_ID_CSCPC = 46, // Cycling Speed and Cadence Profile Client Task
+
+ TASK_ID_ANPS = 47, // Alert Notification Profile Server Task
+ TASK_ID_ANPC = 48, // Alert Notification Profile Client Task
+
+ TASK_ID_PASPS = 49, // Phone Alert Status Profile Server Task
+ TASK_ID_PASPC = 50, // Phone Alert Status Profile Client Task
+
+ TASK_ID_CPPS = 51, // Cycling Power Profile Server Task
+ TASK_ID_CPPC = 52, // Cycling Power Profile Client Task
+
+ TASK_ID_LANS = 53, // Location and Navigation Profile Server Task
+ TASK_ID_LANC = 54, // Location and Navigation Profile Client Task
+
+ TASK_ID_IPSS = 55, // Internet Protocol Support Profile Server Task
+ TASK_ID_IPSC = 56, // Internet Protocol Support Profile Client Task
+
+ TASK_ID_ENVS = 57, // Environmental Sensing Profile Server Task
+ TASK_ID_ENVC = 58, // Environmental Sensing Profile Client Task
+
+ TASK_ID_WSCS = 59, // Weight Scale Profile Server Task
+ TASK_ID_WSCC = 60, // Weight Scale Profile Client Task
+
+ TASK_ID_UDSS = 61, // User Data Service Server Task
+ TASK_ID_UDSC = 62, // User Data Service Client Task
+
+ TASK_ID_BCSS = 63, // Body Composition Server Task
+ TASK_ID_BCSC = 64, // Body Composition Client Task
+
+ TASK_ID_WPTS = 65, // Wireless Power Transfer Profile Server Task
+ TASK_ID_WPTC = 66, // Wireless Power Transfer Profile Client Task
+ TASK_ID_USER = 67, // user Service Server Task
+
+ /* 240 -> 241 reserved for Audio Mode 0 */
+ TASK_ID_AM0 = 240, // BLE Audio Mode 0 Task
+ TASK_ID_AM0_HAS = 241, // BLE Audio Mode 0 Hearing Aid Service Task
+
+ TASK_ID_INVALID = 0xFF, // Invalid Task Identifier
+};
+
+/// @} BT Stack Configuration
+/// @} ROOT
+
+#endif //RWIP_CONFIG_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwprf_config.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwprf_config.h
new file mode 100644
index 0000000000..2aed1df2da
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwprf_config.h
@@ -0,0 +1,508 @@
+/**
+ ****************************************************************************************
+ *
+ * @file rwprf_config.h
+ *
+ * @brief Header file - Profile Configuration
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ ****************************************************************************************
+ */
+
+
+#ifndef _RWPRF_CONFIG_H_
+#define _RWPRF_CONFIG_H_
+
+
+/**
+ ****************************************************************************************
+ * @addtogroup PRF_CONFIG
+ * @ingroup PROFILE
+ * @brief Profile configuration
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+//ATT DB,Testing and Qualification related flags
+#if (BLE_CENTRAL || BLE_PERIPHERAL)
+/// Proximity Profile Monitor Role
+#if defined(CFG_PRF_PXPM)
+#define BLE_PROX_MONITOR 1
+#else
+#define BLE_PROX_MONITOR 0
+#endif // defined(CFG_PRF_PXPM)
+
+/// Proximity Profile Reporter Role
+#if defined(CFG_PRF_PXPR)
+#define BLE_PROX_REPORTER 1
+#else
+#define BLE_PROX_REPORTER 0
+#endif // defined(CFG_PRF_PXPR)
+
+///Find Me Profile Locator role
+#if defined(CFG_PRF_FMPL)
+#define BLE_FINDME_LOCATOR 1
+#else
+#define BLE_FINDME_LOCATOR 0
+#endif // defined(CFG_PRF_FMPL)
+
+///Find Me Profile Target role
+#if defined(CFG_PRF_FMPT)
+#define BLE_FINDME_TARGET 1
+#else
+#define BLE_FINDME_TARGET 0
+#endif // defined(CFG_PRF_FMPT)
+
+///Health Thermometer Profile Collector Role
+#if defined(CFG_PRF_HTPC)
+#define BLE_HT_COLLECTOR 1
+#else
+#define BLE_HT_COLLECTOR 0
+#endif // defined(CFG_PRF_HTPC)
+
+///Health Thermometer Profile Thermometer Role
+#if defined(CFG_PRF_HTPT)
+#define BLE_HT_THERMOM 1
+#else
+#define BLE_HT_THERMOM 0
+#endif // defined(CFG_PRF_HTPT)
+
+///Device Information Service Client Role
+#if defined(CFG_PRF_DISC)
+#define BLE_DIS_CLIENT 1
+#else
+#define BLE_DIS_CLIENT 0
+#endif // defined(CFG_PRF_DISC)
+
+///Device Information Service Server Role
+#if defined(CFG_PRF_DISS)
+#define BLE_DIS_SERVER 1
+#else
+#define BLE_DIS_SERVER 0
+#endif // defined(CFG_PRF_DISS)
+
+///Blood Pressure Profile Collector Role
+#if defined(CFG_PRF_BLPC)
+#define BLE_BP_COLLECTOR 1
+#else
+#define BLE_BP_COLLECTOR 0
+#endif // defined(CFG_PRF_BLPC)
+
+///Blood Pressure Profile Sensor Role
+#if defined(CFG_PRF_BLPS)
+#define BLE_BP_SENSOR 1
+#else
+#define BLE_BP_SENSOR 0
+#endif // defined(CFG_PRF_BLPS)
+
+///Time Profile Client Role
+#if defined(CFG_PRF_TIPC)
+#define BLE_TIP_CLIENT 1
+#else
+#define BLE_TIP_CLIENT 0
+#endif // defined(CFG_PRF_TIPC)
+
+///Time Profile Server Role
+#if defined(CFG_PRF_TIPS)
+#define BLE_TIP_SERVER 1
+#else
+#define BLE_TIP_SERVER 0
+#endif // defined(CFG_PRF_TIPS)
+
+///Heart Rate Profile Collector Role
+#if defined(CFG_PRF_HRPC)
+#define BLE_HR_COLLECTOR 1
+#else
+#define BLE_HR_COLLECTOR 0
+#endif // defined(CFG_PRF_HRPC)
+
+///Heart Rate Profile Sensor Role
+#if defined(CFG_PRF_HRPS)
+#define BLE_HR_SENSOR 1
+#else
+#define BLE_HR_SENSOR 0
+#endif // defined(CFG_PRF_HRPS)
+
+///Scan Parameter Profile Client Role
+#if defined(CFG_PRF_SCPPC)
+#define BLE_SP_CLIENT 1
+#else
+#define BLE_SP_CLIENT 0
+#endif // defined(CFG_PRF_SCPPC)
+
+///Scan Parameter Profile Server Role
+#if defined(CFG_PRF_SCPPS)
+#define BLE_SP_SERVER 1
+#else
+#define BLE_SP_SERVER 0
+#endif // defined(CFG_PRF_SCPPS)
+
+///Battery Service Client Role
+#if defined(CFG_PRF_BASC)
+#define BLE_BATT_CLIENT 1
+#else
+#define BLE_BATT_CLIENT 0
+#endif // defined(CFG_PRF_BASC)
+
+///Battery Service Server Role
+#if defined(CFG_PRF_BASS)
+#define BLE_BATT_SERVER 1
+#else
+#define BLE_BATT_SERVER 0
+#endif // defined(CFG_PRF_BASS)
+
+///HID Device Role
+#if defined(CFG_PRF_HOGPD)
+#define BLE_HID_DEVICE 1
+#else
+#define BLE_HID_DEVICE 0
+#endif // defined(CFG_PRF_HOGPD)
+
+///HID Boot Host Role
+#if defined(CFG_PRF_HOGPBH)
+#define BLE_HID_BOOT_HOST 1
+#else
+#define BLE_HID_BOOT_HOST 0
+#endif // defined(CFG_PRF_HOGPBH)
+
+///HID Report Host Role
+#if defined(CFG_PRF_HOGPRH)
+#define BLE_HID_REPORT_HOST 1
+#else
+#define BLE_HID_REPORT_HOST 0
+#endif // defined(CFG_PRF_HOGPRH)
+
+/// Glucose Profile Collector Role
+#if defined(CFG_PRF_GLPC)
+#define BLE_GL_COLLECTOR 1
+#else
+#define BLE_GL_COLLECTOR 0
+#endif // defined(CFG_PRF_GLPC)
+
+/// Glucose Profile Sensor Role
+#if defined(CFG_PRF_GLPS)
+#define BLE_GL_SENSOR 1
+#else
+#define BLE_GL_SENSOR 0
+#endif // defined(CFG_PRF_GLPS)
+
+/// Running Speed and Cadence Profile Collector Role
+#if defined(CFG_PRF_RSCPC)
+#define BLE_RSC_COLLECTOR 1
+#else
+#define BLE_RSC_COLLECTOR 0
+#endif // defined(CFG_PRF_RSCPC)
+
+/// Running Speed and Cadence Profile Server Role
+#if defined(CFG_PRF_RSCPS)
+#define BLE_RSC_SENSOR 1
+#else
+#define BLE_RSC_SENSOR 0
+#endif // defined(CFG_PRF_RSCPS)
+
+/// Cycling Speed and Cadence Profile Collector Role
+#if defined(CFG_PRF_CSCPC)
+#define BLE_CSC_COLLECTOR 1
+#else
+#define BLE_CSC_COLLECTOR 0
+#endif // defined(CFG_PRF_CSCPC)
+
+/// Cycling Speed and Cadence Profile Server Role
+#if defined(CFG_PRF_CSCPS)
+#define BLE_CSC_SENSOR 1
+#else
+#define BLE_CSC_SENSOR 0
+#endif // defined(CFG_PRF_CSCPS)
+
+/// Cycling Power Profile Collector Role
+#if defined(CFG_PRF_CPPC)
+#define BLE_CP_COLLECTOR 1
+#else
+#define BLE_CP_COLLECTOR 0
+#endif // defined (CFG_PRF_CPPC)
+
+/// Cycling Power Profile Server Role
+#if defined(CFG_PRF_CPPS)
+#define BLE_CP_SENSOR 1
+#else
+#define BLE_CP_SENSOR 0
+#endif // defined (CFG_PRF_CPPS)
+
+/// Location and Navigation Profile Collector Role
+#if defined(CFG_PRF_LANC)
+#define BLE_LN_COLLECTOR 1
+#else
+#define BLE_LN_COLLECTOR 0
+#endif // defined (CFG_PRF_LANC)
+
+/// Location and Navigation Profile Server Role
+#if defined(CFG_PRF_LANS)
+#define BLE_LN_SENSOR 1
+#else
+#define BLE_LN_SENSOR 0
+#endif // defined (CFG_PRF_LANS)
+
+/// Alert Notification Profile Client Role
+#if defined(CFG_PRF_ANPC)
+#define BLE_AN_CLIENT 1
+#else
+#define BLE_AN_CLIENT 0
+#endif // defined(CFG_PRF_ANPC)
+
+/// Alert Notification Profile Server Role
+#if defined(CFG_PRF_ANPS)
+#define BLE_AN_SERVER 1
+#else
+#define BLE_AN_SERVER 0
+#endif // defined(CFG_PRF_ANPS)
+
+/// Phone Alert Status Profile Client Role
+#if defined(CFG_PRF_PASPC)
+#define BLE_PAS_CLIENT 1
+#else
+#define BLE_PAS_CLIENT 0
+#endif // defined(CFG_PRF_PASPC)
+
+/// Phone Alert Status Profile Server Role
+#if defined(CFG_PRF_PASPS)
+#define BLE_PAS_SERVER 1
+#else
+#define BLE_PAS_SERVER 0
+#endif // defined(CFG_PRF_PASPS)
+
+/// Internet Protocol Support Profile Server Role
+#if defined(CFG_PRF_IPSS)
+#define BLE_IPS_SERVER 1
+#else
+#define BLE_IPS_SERVER 0
+#endif // defined(CFG_PRF_IPSS)
+
+/// Internet Protocol Support Profile Client Role
+#if defined(CFG_PRF_IPSC)
+#define BLE_IPS_CLIENT 1
+#else
+#define BLE_IPS_CLIENT 0
+#endif // defined(CFG_PRF_IPSC)
+
+/// Environmental Sensing Profile Server Role
+#if defined(CFG_PRF_ENVS)
+#define BLE_ENV_SERVER 1
+#else
+#define BLE_ENV_SERVER 0
+#endif // defined(CFG_PRF_ENVS)
+
+/// Environmental Sensing Profile Client Role
+#if defined(CFG_PRF_ENVC)
+#define BLE_ENV_CLIENT 1
+#else
+#define BLE_ENV_CLIENT 0
+#endif // defined(CFG_PRF_ENVC)
+
+/// Weight Scale Profile Server Role
+#if defined(CFG_PRF_WSCS)
+#define BLE_WSC_SERVER 1
+#else
+#define BLE_WSC_SERVER 0
+#endif // defined(CFG_PRF_WSCS)
+
+/// Weight Scale Profile Client Role
+#if defined(CFG_PRF_WSCC)
+#define BLE_WSC_CLIENT 1
+#else
+#define BLE_WSC_CLIENT 0
+#endif // defined(CFG_PRF_WSCC)
+
+/// Body Composition Server Role
+#if defined(CFG_PRF_BCSS)
+#define BLE_BCS_SERVER 1
+#else
+#define BLE_BCS_SERVER 0
+#endif // defined(CFG_PRF_BCSS)
+
+/// Body Composition Client Role
+#if defined(CFG_PRF_BCSC)
+#define BLE_BCS_CLIENT 1
+#else
+#define BLE_BCS_CLIENT 0
+#endif // defined(CFG_PRF_BCSC)
+
+/// User Data Service Server Role
+#if defined(CFG_PRF_UDSS)
+#define BLE_UDS_SERVER 1
+#else
+#define BLE_UDS_SERVER 0
+#endif // defined(CFG_PRF_UDSS)
+
+/// User Data Service Client Role
+#if defined(CFG_PRF_UDSC)
+#define BLE_UDS_CLIENT 1
+#else
+#define BLE_UDS_CLIENT 0
+#endif // defined(CFG_PRF_UDSC)
+
+/// Wireless Power Transfer Profile Server Role
+#if defined(CFG_PRF_WPTS)
+#define BLE_WPT_SERVER 1
+#else
+#define BLE_WPT_SERVER 0
+#endif // defined(CFG_PRF_WPTS)
+
+/// Wireless Power Transfer Profile Client Role
+#if defined(CFG_PRF_WPTC)
+#define BLE_WPT_CLIENT 1
+#else
+#define BLE_WPT_CLIENT 0
+#endif // defined(CFG_PRF_WPTC)
+///Health Thermometer Profile Thermometer Role
+#if defined(CFG_APP_USER)
+#define BLE_APP_SERVER 1
+#else
+#define BLE_APP_SERVER 0
+#endif // defined(CFG_PRF_HTPT)
+/// BLE_CLIENT_PRF indicates if at least one client profile is present
+#if (BLE_PROX_MONITOR || BLE_FINDME_LOCATOR || BLE_HT_COLLECTOR || BLE_BP_COLLECTOR \
+ || BLE_HR_COLLECTOR || BLE_DIS_CLIENT || BLE_TIP_CLIENT || BLE_SP_CLIENT \
+ || BLE_BATT_CLIENT || BLE_GL_COLLECTOR || BLE_HID_BOOT_HOST || BLE_HID_REPORT_HOST \
+ || BLE_RSC_COLLECTOR || BLE_CSC_COLLECTOR || BLE_CP_COLLECTOR || BLE_LN_COLLECTOR || BLE_AN_CLIENT \
+ || BLE_PAS_CLIENT || BLE_IPS_CLIENT || BLE_ENV_CLIENT || BLE_WSC_CLIENT \
+ || BLE_UDS_CLIENT || BLE_BCS_CLIENT || BLE_WPT_CLIENT)
+#define BLE_CLIENT_PRF 1
+#else
+#define BLE_CLIENT_PRF 0
+#endif //(BLE_PROX_MONITOR || BLE_FINDME_LOCATOR ...)
+
+/// BLE_SERVER_PRF indicates if at least one server profile is present
+#if (BLE_PROX_REPORTER || BLE_FINDME_TARGET || BLE_HT_THERMOM || BLE_BP_SENSOR \
+ || BLE_TIP_SERVER || BLE_HR_SENSOR || BLE_DIS_SERVER || BLE_SP_SERVER \
+ || BLE_BATT_SERVER || BLE_HID_DEVICE || BLE_GL_SENSOR || BLE_RSC_SENSOR \
+ || BLE_CSC_SENSOR || BLE_CP_SENSOR || BLE_LN_SENSOR || BLE_AN_SERVER \
+ || BLE_PAS_SERVER || BLE_IPS_SERVER || BLE_ENV_SERVER || BLE_WSC_SERVER \
+ || BLE_UDS_SERVER || BLE_BCS_SERVER || BLE_WPT_SERVER||BLE_APP_SERVER)
+#define BLE_SERVER_PRF 1
+#else
+#define BLE_SERVER_PRF 0
+#endif //(BLE_PROX_REPORTER || BLE_FINDME_TARGET ...)
+
+//Force ATT parts depending on profile roles or compile options
+/// Attribute Client
+#if (BLE_CLIENT_PRF)
+#define BLE_ATTC 1
+#endif //(BLE_CLIENT_PRF)
+
+/// Attribute Server
+#if (BLE_SERVER_PRF)
+#define BLE_ATTS 1
+#endif //(BLE_SERVER_PRF)
+
+
+#elif (BLE_OBSERVER || BLE_BROADCASTER)
+/// Proximity Profile Monitor Role
+#define BLE_PROX_MONITOR 0
+/// Proximity Profile Reporter Role
+#define BLE_PROX_REPORTER 0
+///Find Me Profile Locator role
+#define BLE_FINDME_LOCATOR 0
+///Find Me Profile Target role
+#define BLE_FINDME_TARGET 0
+///Health Thermometer Profile Collector Role
+#define BLE_HT_COLLECTOR 0
+///Health Thermometer Profile Thermometer Role
+#define BLE_HT_THERMOM 0
+///Blood Pressure Profile Collector Role
+#define BLE_BP_COLLECTOR 0
+///Blood Pressure Profile Sensor Role
+#define BLE_BP_SENSOR 0
+///Heart Rate Profile Collector Role
+#define BLE_HR_COLLECTOR 0
+///Heart Rate Profile Sensor Role
+#define BLE_HR_SENSOR 0
+///Time Profile Client Role
+#define BLE_TIP_CLIENT 0
+///Time Profile Server Role
+#define BLE_TIP_SERVER 0
+/// Device Information Service Client Role
+#define BLE_DIS_CLIENT 0
+/// Device Information Service Server Role
+#define BLE_DIS_SERVER 0
+/// Scan Parameter Profile Client Role
+#define BLE_SP_CLIENT 0
+/// Scan Parameter Profile Server Role
+#define BLE_SP_SERVER 0
+/// Battery Service Client Role
+#define BLE_BATT_CLIENT 0
+/// Battery Service Server Role
+#define BLE_BATT_SERVER 0
+/// HID Device Role
+#define BLE_HID_DEVICE 0
+/// HID Boot Host Role
+#define BLE_HID_BOOT_HOST 0
+/// HID Report Host Role
+#define BLE_HID_REPORT_HOST 0
+/// Glucose Profile Collector Role
+#define BLE_GL_COLLECTOR 0
+/// Glucose Profile Sensor Role
+#define BLE_GL_SENSOR 0
+/// Running Speed and Cadence Collector Role
+#define BLE_RSC_COLLECTOR 0
+/// Running Speed and Cadence Server Role
+#define BLE_RSC_SENSOR 0
+/// Cycling Speed and Cadence Collector Role
+#define BLE_CSC_COLLECTOR 0
+/// Cycling Speed and Cadence Server Role
+#define BLE_CSC_SENSOR 0
+/// Cycling Power Collector Role
+#define BLE_CP_COLLECTOR 0
+/// Cycling Power Server Role
+#define BLE_CP_SENSOR 0
+/// Location and Navigation Collector Role
+#define BLE_LN_COLLECTOR 0
+/// Location and Navigation Server Role
+#define BLE_LN_SENSOR 0
+/// Alert Notification Client Role
+#define BLE_AN_CLIENT 0
+/// Alert Notification Server Role
+#define BLE_AN_SERVER 0
+/// Phone Alert Status Client Role
+#define BLE_PAS_CLIENT 0
+/// Phone Alert Status Server Role
+#define BLE_PAS_SERVER 0
+/// Internet Protocol Support Profile Server Role
+#define BLE_IPS_SERVER 0
+/// Internet Protocol Support Profile Client Role
+#define BLE_IPS_CLIENT 0
+/// Environmental Sensing Profile Server Role
+#define BLE_ENV_SERVER 0
+/// Environmental Sensing Profile Client Role
+#define BLE_ENV_CLIENT 0
+/// Weight Scale Profile Server Role
+#define BLE_WSC_SERVER 0
+/// Weight Scale Profile Client Role
+#define BLE_WSC_CLIENT 0
+/// Body Composition Profile Client Role
+#define BLE_BCS_CLIENT 0
+/// Body Composition Profile Server Role
+#define BLE_BCS_SERVER 0
+/// User Data Service Server Role
+#define BLE_UDS_SERVER 0
+/// User Data Service Client Role
+#define BLE_UDS_CLIENT 0
+/// Wireless Power Transfer Profile Server Role
+#define BLE_WPT_SERVER 0
+/// Wireless Power Transfer Profile Client Role
+#define BLE_WPT_CLIENT 0
+
+//Force ATT parts to 0
+/// External database management
+#define BLE_EXT_ATTS_DB 0
+/// Profile Server
+#define BLE_SERVER_PRF 0
+/// Profile Client
+#define BLE_CLIENT_PRF 0
+#endif //(BLE_OBSERVER || BLE_BROADCASTER)
+
+
+/// @} PRF_CONFIG
+
+#endif /* _RWPRF_CONFIG_H_ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smp_common.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smp_common.h
new file mode 100644
index 0000000000..573fe3869a
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smp_common.h
@@ -0,0 +1,159 @@
+/**
+****************************************************************************************
+*
+* @file smp_common.h
+*
+* @brief Header file - Security Manager Protocol Common Definitions and Functions.
+*
+* Copyright (C) RivieraWaves 2009-2016
+*
+*
+****************************************************************************************
+*/
+
+/**
+ ****************************************************************************************
+ * @addtogroup SMP_COMMON
+ * @ingroup SMP
+ * @{
+ ****************************************************************************************
+ */
+
+#ifndef SMP_COMMON_H_
+#define SMP_COMMON_H_
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+
+#include "rwip_config.h"
+
+#include // Standard Boolean Definitions
+#include // Standard Integer Definitions
+
+#include "co_utils.h"
+#include "co_bt.h" // Common Bluetooth Definitions
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/// Mask applied to a Pairing Failed error triggered by us.
+#define SMP_PAIR_FAIL_REASON_MASK (0x60)
+/// Mask applied to a Pairing Failed error triggered by the peer device.
+#define SMP_PAIR_FAIL_REASON_REM_MASK (0x70)
+
+/*
+ * MACROS
+ ****************************************************************************************
+ */
+
+/// Mask a Pairing Failed reason value with the provided mask.
+#define SMP_GEN_PAIR_FAIL_REASON(mask, reason) (mask | reason)
+/// Extract the mask from a masked Pairing Failed reason value.
+#define SMP_GET_PAIR_FAIL_MASK(reason) (0xF0 & reason)
+/// Extract the Pairing Failed reason value from a masked Pairing Failed reason value.
+#define SMP_GET_PAIR_FAIL_REASON(reason) (0x0F & reason)
+
+/*
+ * ENUMERATIONS
+ ****************************************************************************************
+ */
+
+/**
+ * SMP Pairing Failed Reasons
+ */
+enum smp_pair_fail_reason
+{
+
+ /**
+ * Passkey Entry Failed (0x01)
+ * The user input of passkey failed, for example, the user cancelled the operation.
+ */
+ SMP_ERROR_PASSKEY_ENTRY_FAILED = 0x01,
+ /**
+ * OOB Not Available (0x02)
+ * The OOB Data is not available.
+ */
+ SMP_ERROR_OOB_NOT_AVAILABLE,
+ /**
+ * Authentication Requirements (0x03)
+ * The pairing procedure cannot be performed as authentication requirements cannot be
+ * met due to IO capabilities of one or both devices.
+ */
+ SMP_ERROR_AUTH_REQ,
+ /**
+ * Confirm Value Failed (0x04)
+ * The confirm value does not match the calculated confirm value.
+ */
+ SMP_ERROR_CONF_VAL_FAILED,
+ /**
+ * Pairing Not Supported (0x05)
+ * Pairing is not supported by the device.
+ */
+ SMP_ERROR_PAIRING_NOT_SUPP,
+ /**
+ * Encryption Key Size (0x06)
+ * The resultant encryption key size is insufficient for the security requirements of
+ * this device.
+ */
+ SMP_ERROR_ENC_KEY_SIZE,
+ /**
+ * Command Not Supported (0x07)
+ * The SMP command received is not supported on this device.
+ */
+ SMP_ERROR_CMD_NOT_SUPPORTED,
+ /**
+ * Unspecified Reason (0x08)
+ * Pairing failed due to an unspecified reason.
+ */
+ SMP_ERROR_UNSPECIFIED_REASON,
+ /**
+ * Repeated Attempts (0x09)
+ * Pairing or Authentication procedure is disallowed because too little time has elapsed
+ * since last pairing request or security request.
+ */
+ SMP_ERROR_REPEATED_ATTEMPTS,
+ /**
+ * Invalid Parameters (0x0A)
+ * The command length is invalid or a parameter is outside of the specified range.
+ */
+ SMP_ERROR_INVALID_PARAM,
+ /**
+ * DHKey Check Failed (0x0B)
+ * Indicates to the remote device that the DHKey Check value received doesn't
+ * match the one calculated by the local device.
+ */
+ SMP_ERROR_DHKEY_CHECK_FAILED,
+ /**
+ * Numeric Comparison Failed (0x0C)
+ * Indicates that the confirm values in the numeric comparison protocol do not match.
+ */
+ SMP_ERROR_NUMERIC_COMPARISON_FAILED,
+ /**
+ * BR/EDR pairing in progress (0x0D)
+ * Indicates that the pairing over the LE transport failed due to a Pairing Request sent
+ * over the BR/EDR transport in process.
+ */
+ SMP_ERROR_BREDR_PAIRING_IN_PROGRESS,
+ /**
+ * Cross-transport Key Derivation/Generation not allowed (0x0E)
+ *
+ * Indicates that the BR/EDR Link Key generated on the BR/EDR transport cannot be
+ * used to derive and distribute keys for the LE transport.
+ */
+ SMP_ERROR_CROSS_TRANSPORT_KEY_GENERATION_NOT_ALLOWED,
+};
+
+
+/*
+ * STRUCTURES
+ ****************************************************************************************
+ */
+
+
+#endif // (SMP_COMMON_H_)
+
+/// @} SMP_COMMON
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc.h
new file mode 100644
index 0000000000..38eeabd870
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc.h
@@ -0,0 +1,327 @@
+/**
+ ****************************************************************************************
+ *
+ * @file smpc.h
+ *
+ * @brief Header file - SMPC.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef SMPC_H_
+#define SMPC_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup SMP Security Manager Protocol
+ * @ingroup HOST
+ * @brief Security Manager Protocol.
+ *
+ * The SMP is responsible for the over-all security policies of BLE.
+ * It defines methods for pairing and key distribution, handles encryption,
+ * data signing and privacy features such as random addressing generation and resolution.
+ *
+ * Pairing is performed to exchange pairing features and generate a short term
+ * key for link encryption.
+ * A transport specific key distribution is performed to
+ * share the keys that can be used to encrypt the link in the future
+ * reconnection process, signed data verification and random address
+ * resolution.
+ *
+ * There exist 3 phases in the complete security procedure:
+ * 1. Feature exchange (IO capabilities, OOB flags, Authentication Requirements, Key distributions)
+ * 2. Short Term Key generation
+ * Generation method depends on exchanged features:
+ * - Just Works - use Temporary key = 0
+ * - PassKey Entry - use Temporary Key = 6-digit provided by user
+ * - Out of Band (OOB) - use Temporary Key = 16-octet key, available form OOB source
+ * 3. Transport Specific Key Distribution (TKDP)(LTK+EDIV+RAND_NB, IRK+ADDR, CSRK)
+ *---------------------------------------------------------------------
+ * @addtogroup SMPC Security Manager Protocol Controller
+ * @ingroup SMP
+ * @brief Security Manager Protocol Controller.
+ *
+ * This block handles control of SM procedures for several possible existing connections,
+ * for which the security procedure may be conducted simultaneously.
+ *
+ * It allows flow control for HCI access to encryption and random number generation, used
+ * at different moments in the procedure.
+ *
+ * It handles PDU creation and sending through L2CAP, also their reception from L2CAP
+ * and interpretation.
+ *
+ * Other small utilities such as maximum key size determination and TKDP organization are
+ * implemented in SMPC.
+ * @{
+ *
+ ****************************************************************************************
+ */
+
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "rwip_config.h"
+
+#if (BLE_SMPC)
+#include "co_bt.h"
+#include "gap.h"
+#include "gapc_task.h"
+#include "ke_task.h"
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/// MAC length
+#define SMPC_SIGN_MAC_LEN (8)
+/// SignCounter length
+#define SMPC_SIGN_COUNTER_LEN (4)
+/// Signature length
+#define SMPC_SIGN_LEN (SMPC_SIGN_MAC_LEN + SMPC_SIGN_COUNTER_LEN)
+
+/**
+ * Repeated Attempts Timer Configuration
+ */
+/// Repeated Attempts Timer default value (x10ms)
+#define SMPC_REP_ATTEMPTS_TIMER_DEF_VAL (200) //2s
+/// Repeated Attempts Timer max value (x10ms)
+#define SMPC_REP_ATTEMPTS_TIMER_MAX_VAL (3000) //30s
+/// Repeated Attempts Timer multiplier
+#define SMPC_REP_ATTEMPTS_TIMER_MULT (2)
+
+/**
+ * Timeout Timer Configuration
+ */
+#define SMPC_TIMEOUT_TIMER_DURATION (1000) //30s
+
+#define SMPC_PUBLIC_KEY_256_COORD_LEN 0x20
+/*
+ * ENUMERATIONS
+ ****************************************************************************************
+ */
+
+
+/// Information source.
+enum smpc_addr_src
+{
+ /// Local info.
+ SMPC_INFO_LOCAL,
+ /// Peer info.
+ SMPC_INFO_PEER,
+ /// Maximum info source.
+ SMPC_INFO_MAX
+};
+
+/*
+ * STRUCTURES DEFINITION
+ ****************************************************************************************
+ */
+
+/// Master ID Information Structure
+struct smpc_mst_id_info
+{
+ // Encryption Diversifier
+ uint16_t ediv;
+
+ // Random Number
+ uint8_t randnb[GAP_RAND_NB_LEN];
+};
+
+#if (SECURE_CONNECTIONS)
+struct smp_aes_cmac
+{
+ uint8_t* M; // pointer to memory allocated by calling function
+ uint8_t M_len;
+ uint8_t M_last[16];
+ uint8_t X[16];
+ uint8_t Y[16];
+ uint8_t* K; //[16];
+ uint8_t K1[16];
+ uint8_t K2[16];
+ uint8_t next_block;
+ uint8_t num_blocks;
+ uint8_t state; // Only 3 States - Idle, SubKey Generation, Block AES
+};
+
+struct smp_f4
+{
+ uint8_t M[65];
+ uint8_t X[16]; // The Key
+};
+
+struct smp_f5
+{
+ uint8_t M[53];
+ uint8_t* W;
+ uint8_t T[16];
+ uint8_t SALT[16];
+};
+
+
+struct smp_f6
+{
+ uint8_t W[16];
+ uint8_t M[65];
+};
+
+struct smp_g2
+{
+ uint8_t X[16];
+ uint8_t M[80];
+};
+
+struct gapc_public_key
+{
+ uint8_t x[GAP_P256_KEY_LEN];
+ uint8_t y[GAP_P256_KEY_LEN];
+};
+
+#endif // (SECURE_CONNECTIONS)
+/// Pairing Information
+struct smpc_pair_info
+{
+ /// TK during Phase 2, LTK or IRK during Phase 3
+ struct gap_sec_key key;
+ /// Pairing request command
+ struct gapc_pairing pair_req_feat;
+ /// Pairing response feature
+ struct gapc_pairing pair_rsp_feat;
+ /// Random number value
+ uint8_t rand[RAND_VAL_LEN];
+ /// Remote random number value
+ uint8_t rem_rand[RAND_VAL_LEN];
+ /// Confirm value to check
+ uint8_t conf_value[GAP_KEY_LEN];
+ /// Pairing Method
+ uint8_t pair_method;
+ /// Authentication level
+ uint8_t auth;
+ /// check that LTK exchanged during pairing
+ bool ltk_exchanged;
+ /// Key to be exchanged (transmitted or to be received)
+ uint8_t keys_dist;
+
+
+ #if (SECURE_CONNECTIONS)
+ // AES_CMAC Info
+ struct smp_aes_cmac* aes_cmac;
+ // Structure for Secure Connections Crypto functions
+ struct smp_f4* f4_info;
+ struct smp_f5* f5_info;
+ struct smp_f6* f6_info;
+ struct smp_g2* g2_info;
+
+ bool dh_key_calculation_complete;
+
+ uint8_t MacKey[GAP_KEY_LEN];
+ uint8_t dh_key_check_peer[DHKEY_CHECK_LEN];
+ uint8_t dh_key_local[DH_KEY_LEN];
+
+ uint8_t dh_key_check_local[DHKEY_CHECK_LEN];
+ bool dh_key_check_received_from_peer;
+
+ public_key_t peer_public_key;
+
+ uint8_t passkey_bit_count;
+ uint32_t passkey;
+
+ // Required for OOB
+ uint8_t peer_r[GAP_KEY_LEN];
+ uint8_t local_r[GAP_KEY_LEN];
+ bool peer_rand_received;
+ bool peer_confirm_received;
+ #endif // (SECURE_CONNECTIONS)
+};
+
+/// Signing Information
+struct smpc_sign_info
+{
+ /// Operation requester task id
+ ke_task_id_t requester;
+
+ /// Message offset
+ uint16_t msg_offset;
+ /// Number of block
+ uint8_t block_nb;
+ /// Cn-1 value -> Need to kept this value to retrieve it after L generation
+ uint8_t cn1[GAP_KEY_LEN];
+};
+
+/// SMPC environment structure
+struct smpc_env
+{
+ /// SMPC temporary information
+ union smpc_info
+ {
+ /**
+ * Pairing Information - This structure is allocated at the beginning of a pairing
+ * or procedure. It is freed when a disconnection occurs or at the end of
+ * the pairing procedure. If not enough memory can be found, the procedure will fail
+ * with an "Unspecified Reason" error
+ */
+ struct smpc_pair_info *pair;
+
+ /**
+ * Signature Procedure Information - This structure is allocated at the beginning of a
+ * signing procedure. It is freed when a disconnection occurs or at the end of
+ * the signing procedure. If not enough memory can be found, the procedure will fail
+ * with an "Unspecified Reason" error.
+ */
+ struct smpc_sign_info *sign;
+ } info;
+
+ /// CSRK values (Local and remote)
+ struct gap_sec_key csrk[SMPC_INFO_MAX];
+
+ /// signature counter values (Local and remote)
+ uint32_t sign_counter[SMPC_INFO_MAX];
+
+ /// Repeated Attempt Timer value
+ uint16_t rep_att_timer_val;
+
+ /// Encryption key size
+ uint8_t key_size;
+
+ /**
+ * Contains the current state of the two timers needed in the SMPC task
+ * Bit 0 - Is Timeout Timer running
+ * Bit 1 - Is Repeated Attempt Timer running
+ * Bit 2 - Has task reached a SMP Timeout
+ */
+ uint8_t timer_state;
+
+ /// State of the current procedure
+ uint8_t state;
+
+ #if (SECURE_CONNECTIONS)
+ bool secure_connections_enabled;
+ #endif // (SECURE_CONNECTIONS)
+};
+
+/*
+ * GLOBAL VARIABLES DEFINITION
+ ****************************************************************************************
+ */
+
+
+/*
+ * MACROS
+ ****************************************************************************************
+ */
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+
+#endif //(BLE_SMPC)
+#endif //SMPC_H_
+
+/// @} SMPC
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc_api.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc_api.h
new file mode 100644
index 0000000000..2182833e68
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc_api.h
@@ -0,0 +1,560 @@
+/**
+ ****************************************************************************************
+ *
+ * @file smpc_api.h
+ *
+ * @brief Header file SMPC API.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef SMPC_API_H_
+#define SMPC_API_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup SMPC_API Task
+ * @ingroup SMPC
+ * @brief Provides a SMP API for controller tasks.
+ *
+ * The SMPC api is responsible for all security protocol and secure connections handling.
+ *
+ * @{
+ ****************************************************************************************
+ */
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+
+
+#include "rwip_config.h"
+#if (BLE_SMPC)
+#include "smp_common.h"
+#include "gap.h"
+#include "gapc_task.h"
+#include "l2cc_pdu.h"
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+
+/// check if flag is set
+#define SMPC_IS_FLAG_SET(conidx, flag) ((gapc_env[conidx]->smpc.timer_state & flag) == flag)
+
+#define SMPC_TIMER_SET_FLAG(conidx, flag) (gapc_env[conidx]->smpc.timer_state |= flag)
+
+#define SMPC_TIMER_UNSET_FLAG(conidx, flag) (gapc_env[conidx]->smpc.timer_state &= ~flag)
+
+
+/**
+ * Timer State Masks
+ */
+/// Timeout Timer
+#define SMPC_TIMER_TIMEOUT_FLAG (0x01)
+/// Repeated Attempts Timer
+#define SMPC_TIMER_REP_ATT_FLAG (SMPC_TIMER_TIMEOUT_FLAG << 1)
+/// Blocked because of SMP Timeout
+#define SMPC_TIMER_TIMEOUT_BLOCKED_FLAG (SMPC_TIMER_REP_ATT_FLAG << 1)
+
+
+/// SMPC Internal State Code
+enum smpc_state
+{
+ SMPC_STATE_RESERVED = 0x00,
+
+ /********************************************************
+ * Pairing Procedure
+ ********************************************************/
+
+ /**------------------------------------**
+ * Pairing Features Exchange Phase *
+ **------------------------------------**/
+ /// Is waiting for the pairing response
+ SMPC_PAIRING_RSP_WAIT,
+ /// Is waiting for the pairing features
+ SMPC_PAIRING_FEAT_WAIT,
+
+ /**------------------------------------**
+ * Legacy (Pre BT 4.2 ) Authentication and Encryption Phase *
+ **------------------------------------**/
+
+ /// Is waiting for the TK
+ SMPC_PAIRING_TK_WAIT,
+ /// Is waiting for the TK, peer confirm value has been received
+ SMPC_PAIRING_TK_WAIT_CONF_RCV,
+ /// Calculate the Random Number, part 1
+ SMPC_PAIRING_GEN_RAND_P1,
+ /// Calculate the Random Number, part 2
+ SMPC_PAIRING_GEN_RAND_P2,
+ /// The first part of the device's confirm value is being generated
+ SMPC_PAIRING_CFM_P1, //7
+ /// The device's confirm value is being generated
+ SMPC_PAIRING_CFM_P2,
+ /// The first part of the peer device's confirm value is being generated
+ SMPC_PAIRING_REM_CFM_P1,
+ /// The peer device's confirm value is being generated
+ SMPC_PAIRING_REM_CFM_P2,
+ /// The device is waiting for the confirm value generated by the peer device
+ SMPC_PAIRING_WAIT_CONFIRM, //b
+ /// The device is waiting for the random value generated by the peer device
+ SMPC_PAIRING_WAIT_RAND,
+ /// The STK is being generated
+ SMPC_PAIRING_GEN_STK,
+
+ #if (SECURE_CONNECTIONS)
+ /**------------------------------------**
+ * Secure Connections (BT 4.2 ) Authentication and Encryption Phase *
+ **------------------------------------**/
+ SMPC_PAIRING_SC_W4_PEER_PUBLIC_KEY,
+
+ // Just Works and Numeric Comparison
+ //---------------------------------
+
+ // In Just Works/Numeric Comparison - this state is used while
+ // we are waiting for the LL to generate a Rand.
+ SMPC_PAIRING_SC_W4_LOCAL_RAND_N_P1,
+ SMPC_PAIRING_SC_W4_LOCAL_RAND_N_P2,
+ // Used in Slave during F4 while waiting for AES_CMAC
+ SMPC_PAIRING_SC_W4_F4_COMMITMENT_DETERMINATION,
+
+ // Used in Master to Wait for Peer Commitment Cb
+ SMPC_PAIRING_SC_W4_PEER_COMMITMENT,
+
+ // Used in Master/Slave to Wait for Random Number From peer.
+ SMPC_PAIRING_SC_W4_PEER_RAND,
+
+ // Used in Slave to wait for Random Number Na from Master
+ // SMPC_PAIRING_SC_W4_PAIRING_Na,
+
+ // Used in Master during F4 calculation for Commitment Check
+ SMPC_PAIRING_SC_W4_F4_COMMITMENT_CHECK,
+
+ // Numeric Comparison
+ // States specific to Secure Commenctions - numeric comparison
+
+ // Used in both Master/Slave to wait for the AES-CMAC calculation does to calculated the
+ // PassCode for the user.
+
+ SMPC_PAIRING_SC_W4_G2_AES_CMAC,
+
+ // Wait for the user to enter Accept/Reject for the Numeric Value
+ SMPC_PAIRING_SC_W4_NC_ACCEPT,
+ // Used in both Master/Slave while waiting for the user Pass Code Confirmation.
+
+ SMPC_PAIRING_SC_W4_USER_PASSCODE_CONFIRMATION,
+
+ //-----------------------------
+ // Secure Connections - Passkey
+ //-----------------------------
+
+ // Used in both Master/Slave while the user is entering the PassKey
+ SMPC_PAIRING_SC_PASSKEY_W4_PASSKEY_RAND,
+
+ // Used in both Master/Slave while Random numbers Nai,Nbi are being generated.
+ SMPC_PAIRING_SC_PASSKEY_W4_LOCAL_RAND_N_P1,
+
+ // Used in both Master/Slave while Random numbers Nai,Nbi are being generated.
+ SMPC_PAIRING_SC_PASSKEY_W4_LOCAL_RAND_N_P2,
+
+ // Used in both Master/Slave while waiting for the commitment value Cai,Cbi from the peer
+ SMPC_PAIRING_SC_PASSKEY_W4_PEER_COMMITMENT,
+
+ // Used in both Master/Slave while using AES_CMAC during F4 calculation of the commitment
+ SMPC_PAIRING_SC_PASSKEY_W4_F4_COMMITMENT_DETERMINATION,
+
+ // Used in both Master/Slave while waiting for the random number Nai,Nbi from the peer
+ SMPC_PAIRING_SC_PASSKEY_W4_PEER_RAND,
+
+ // Used in both Master/Slave while using AES_CMAC during F4 calculation for the commitment check
+ SMPC_PAIRING_SC_PASSKEY_W4_F4_COMMITMENT_CHECK,
+
+
+ // OOB
+ SMPC_PAIRING_SC_OOB_W4_LOCAL_RAND_N_P1,
+
+ SMPC_PAIRING_SC_OOB_W4_LOCAL_RAND_N_P2,
+
+ SMPC_PAIRING_SC_OOB_W4_LOCAL_RAND_R_P1,
+
+ SMPC_PAIRING_SC_OOB_W4_LOCAL_RAND_R_P2,
+
+ SMPC_PAIRING_SC_OOB_W4_F4_COMMITMENT_DETERMINATION,
+
+ SMPC_PAIRING_SC_OOB_W4_F4_COMMITMENT_CHECK,
+
+ SMPC_PAIRING_SC_OOB_W4_PEER_RAND,
+
+ // Wait for OOB data (A,Ca,Ra OR B,Cb,Rb) to be recieved from Peer.
+ SMPC_PAIRING_SC_OOB_W4_OOB_DATA,
+
+ // Secure Connections Authentication Phase 2
+
+ // Wait for the AES_CMACsalt to generate T
+ SMPC_PAIRING_SC_W4_F5_P1,
+
+ // Wait for the AES_CMAC to generate MACKEY
+ SMPC_PAIRING_SC_W4_F5_P2,
+
+ // Wait for the AES_CMAC to generate LTK
+ SMPC_PAIRING_SC_W4_F5_P3,
+
+ // Wait for the AES_CMAC to complete the DHKEY check
+ SMPC_PAIRING_SC_W4_F6_DHKEY_CHECK,
+
+ // Wait for DHkey_Check from the peer
+ SMPC_PAIRING_SC_W4_PEER_DHKEY_CHECK,
+
+ SMPC_PAIRING_SC_W4_F6_DHKEY_VERIFICATION,
+
+ SMPC_PAIRING_SC_W4_DHKEY_KEY_COMPLETE,
+
+ SMPC_PAIRING_SC_W4_ENCRYPTION_START,
+
+ SMPC_PAIRING_SC_W4_ENCRYPTION_CHANGE,
+
+ #endif // (SECURE_CONNECTIONS)
+ /**------------------------------------**
+ * Transport Keys Distribution Phase *
+ **------------------------------------**/
+
+ /// Default pairing remote waiting state
+ SMPC_PAIRING_APP_WAIT,
+ /// Is waiting for the LTK from application
+ SMPC_PAIRING_APP_LTK_WAIT,
+ /// Is waiting for the Identity Resolving Key from application
+ SMPC_PAIRING_APP_IRK_WAIT,
+ /// Is waiting for the CSRK from application
+ SMPC_PAIRING_APP_CSRK_WAIT,
+
+
+ /// Default pairing remote waiting state
+ SMPC_PAIRING_REM_WAIT,
+ /// Is waiting for the remote LTK
+ SMPC_PAIRING_REM_LTK_WAIT,
+ /// Is waiting for the remote EDIV and Rand Value
+ SMPC_PAIRING_REM_MST_ID_WAIT,
+ /// Is waiting for the remote IRK
+ SMPC_PAIRING_REM_IRK_WAIT,
+ /// Is waiting for the remote BD Address
+ SMPC_PAIRING_REM_BD_ADDR_WAIT,
+ /// Is waiting for the remote CSRK
+ SMPC_PAIRING_REM_CSRK_WAIT,
+
+ /********************************************************
+ * Signing Procedure
+ ********************************************************/
+ /// Generation of L
+ SMPC_SIGN_L_GEN,
+ /// Generation of Ci
+ SMPC_SIGN_Ci_GEN,
+
+ /********************************************************
+ * Encryption Procedure (STK or LTK)
+ ********************************************************/
+ /// Is waiting the change encryption event with LTK
+ SMPC_START_ENC_LTK,
+ /// Is waiting the change encryption event with STK
+ SMPC_START_ENC_STK
+};
+
+/*
+ * FUNCTION DEFINITION
+ ****************************************************************************************
+ */
+
+#if (BLE_CENTRAL)
+/**
+ ****************************************************************************************
+ * @brief Handles pairing request from GAP, start the pairing procedure
+ *
+ * @param[in] idx Connection Index
+ * @param[in] pairing Pairing Information
+ *
+ * @return Status of Pairing start
+ ****************************************************************************************
+ */
+uint8_t smpc_pairing_start(uint8_t idx, struct gapc_pairing *pairing);
+#endif // (BLE_CENTRAL)
+
+
+/**
+ ****************************************************************************************
+ * @brief Handles TK exchange part of pairing
+ *
+ * @param[in] idx Connection Index
+ * @param[in] accept True if pairing is accepted, False else
+ * @param[in] tk The TK transmitted by application
+ *
+ * @return status of pairing
+ ****************************************************************************************
+ */
+uint8_t smpc_pairing_tk_exch(uint8_t idx, bool accept, struct gap_sec_key *tk);
+
+/**
+ ****************************************************************************************
+ * @brief Handles LTK exchange part of pairing
+ *
+ * @param[in] idx Connection Index
+ * @param[in] ltk The LTK transmitted by application
+ *
+ * @return status of pairing
+ ****************************************************************************************
+ */
+uint8_t smpc_pairing_ltk_exch(uint8_t idx, struct gapc_ltk* ltk);
+
+
+/**
+ ****************************************************************************************
+ * @brief Handles IRK exchange part of pairing
+ *
+ * @param[in] idx Connection Index
+ * @param[in] irk The IRK transmitted by application
+ * @param[in] identity Device identity address
+ *
+ * @return status of pairing
+ ****************************************************************************************
+ */
+uint8_t smpc_pairing_irk_exch(uint8_t idx, struct gap_sec_key* irk, struct gap_bdaddr *identity);
+
+/**
+ ****************************************************************************************
+ * @brief Handles CSRK exchange part of pairing
+ *
+ * @param[in] idx Connection Index
+ * @param[in] csrk The CSRK transmitted by application
+ *
+ * @return status of pairing
+ ****************************************************************************************
+ */
+uint8_t smpc_pairing_csrk_exch(uint8_t idx, struct gap_sec_key *csrk);
+
+#if (SECURE_CONNECTIONS)
+/**
+ ****************************************************************************************
+ * @brief Handles OOB exchange part of pairing
+ *
+ * @param[in] idx Connection Index
+ * @param[in] accept Accept or Reject the OOB (reject if OOB reception not available on the device)
+ * @param[in] csrk The OOB Confirm and OOB Rand from the peer
+ *
+ * @return status of pairing
+ ****************************************************************************************
+ */
+
+uint8_t smpc_pairing_oob_exch(uint8_t idx, bool accept, struct gapc_oob *oob);
+
+/**
+ ****************************************************************************************
+ * @brief Handles Numeric Value Acceptance as part of pairing
+ *
+ * @param[in] idx Connection Index
+ * @param[in] accept Accept or Reject the numeric comparison
+ *
+ * @return status of pairing
+ ****************************************************************************************
+ */
+
+uint8_t smpc_pairing_nc_exch(uint8_t idx,uint8_t accept );
+
+#endif // (SECURE_CONNECTIONS)
+/**
+ ****************************************************************************************
+ * @brief Handles reception of pairing response information
+ *
+ * @param[in] idx Connection Index
+ * @param[in] accept True if pairing is accepted, False else
+ * @param[in] feat Pairing response feature information
+ *
+ * @return status of pairing
+ ****************************************************************************************
+ */
+uint8_t smpc_pairing_rsp(uint8_t idx, bool accept, struct gapc_pairing *feat);
+
+
+#if (BLE_PERIPHERAL)
+
+/**
+ ****************************************************************************************
+ * @brief Handles reception of pairing request information
+ *
+ * @param[in] idx Connection Index
+ * @param[in] feat Pairing request feature information
+ ****************************************************************************************
+ */
+void smpc_pairing_req_handler(uint8_t idx, struct gapc_pairing *feat);
+
+/**
+ ****************************************************************************************
+ * @brief Handles request to send a security request to peer device
+ *
+ * @param[in] idx Connection Index
+ * @param[in] auth Requested Authentication Level
+ *
+ * @return status of the request
+ ****************************************************************************************
+ */
+uint8_t smpc_security_req_send(uint8_t idx, uint8_t auth);
+#endif // (BLE_PERIPHERAL)
+
+
+#if (BLE_CENTRAL)
+/**
+ ****************************************************************************************
+ * @brief Master requests to start encryption
+ *
+ * @param[in] idx Connection Index
+ * @param[in] ltk LTK information
+ *
+ * @return status of the request
+ ****************************************************************************************
+ */
+uint8_t smpc_encrypt_start(uint8_t idx, struct gapc_ltk *ltk);
+#endif //(BLE_CENTRAL)
+
+
+#if (BLE_PERIPHERAL)
+
+/**
+ ****************************************************************************************
+ * @brief Handles reception of encryption request
+ *
+ * @param[in] idx Connection Index
+ * @param[in] ltk LTK to search information
+ ****************************************************************************************
+ */
+void smpc_encrypt_start_handler(uint8_t idx, struct gapc_ltk *ltk);
+
+/**
+ ****************************************************************************************
+ * @brief Slave respond to peer device encryption request
+ *
+ * @param[in] idx Connection Index
+ * @param[in] accept Accept or not to start encryption
+ * @param[in] ltk LTK information
+ * @param[in] key_size Encryption key size
+ ****************************************************************************************
+ */
+void smpc_encrypt_cfm(uint8_t idx, bool accept, struct gap_sec_key *ltk, uint8_t key_size);
+#endif //(BLE_PERIPHERAL)
+
+
+/**
+ ****************************************************************************************
+ * @brief Request to sign an attribute packet or check signature
+ *
+ * @param[in] idx Connection Index
+ * @param[in] param ATT packet information
+ *
+ * @return status of signature request
+ ****************************************************************************************
+ */
+uint8_t smpc_sign_command(uint8_t idx, struct gapc_sign_cmd *param);
+
+
+/**
+ ****************************************************************************************
+ * @brief Continue signature generation or check of an attribute packet after an AES.
+ *
+ * @param[in] idx Connection Index
+ * @param[in] aes_res Result of AES calculation
+ ****************************************************************************************
+ */
+void smpc_sign_cont(uint8_t idx, uint8_t* aes_res);
+
+/**
+ ****************************************************************************************
+ * @brief Continue generation of rand number for confirm value.
+ *
+ * @param[in] idx Connection Index
+ * @param[in] randnb Generated Random Number
+ ****************************************************************************************
+ */
+void smpc_confirm_gen_rand(uint8_t idx, rand_nb_t* randnb);
+
+/**
+ ****************************************************************************************
+ * @brief Continue Calculation of Confirm Value or STK after AES.
+ *
+ * @param[in] idx Connection Index
+ * @param[in] aes_res Result of AES calculation
+ ****************************************************************************************
+ */
+void smpc_calc_confirm_cont(uint8_t idx, uint8_t* aes_res);
+
+/**
+ ****************************************************************************************
+ * @brief Send an KeyPress Notification Event to the Host
+ *
+ * @param[in] idx Connection Index
+ * @param[in] keypress KeyPress Type
+ ****************************************************************************************
+ */
+void smpc_key_press_notification_ind(uint8_t idx, uint8_t keypress);
+
+/**
+ ****************************************************************************************
+ * @brief Stop the timer used to detect a SMP Timeout
+ *
+ * @param[in] conidx Connection Index
+ ****************************************************************************************
+ */
+void smpc_clear_timeout_timer(uint8_t conidx);
+
+
+/**
+ ****************************************************************************************
+ * @brief Handle reception of a SMP PDU sent by the peer device.
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] pdu Unpacked PDU
+ ****************************************************************************************
+ */
+void smpc_pdu_recv(uint8_t conidx, struct l2cc_pdu *pdu);
+
+/**
+ ****************************************************************************************
+ * @brief Send a SMP PDU to the peer device
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] cmd_code Code of the PDU to send
+ * @param[in] value Unpacked value
+ ****************************************************************************************
+ */
+void smpc_pdu_send(uint8_t conidx, uint8_t cmd_code, void *value);
+
+
+/**
+ ****************************************************************************************
+ * @brief Inform the HL that the pairing procedure currently in progress is over.
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] role Current role of the device
+ * @param[in] status Status
+ * @param[in] start_ra_timer Indicate if the repeated attempts timer shall be started in
+ * the case of a pairing failed.
+ ****************************************************************************************
+ */
+void smpc_pairing_end(uint8_t conidx, uint8_t role, uint8_t status, bool start_ra_timer);
+
+
+/**
+ ****************************************************************************************
+ * @brief Handle reception of a DH Key from HCI
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] status Indicates if HCI request Succeeded or Failed
+ * @param[in] dh_key Diffie Helman Key - 32 Bytes
+ ****************************************************************************************
+ */
+void smpc_handle_dh_key_check_complete(uint8_t conidx,const uint8_t* dh_key);
+
+#endif // (BLE_SMPC)
+#endif //(SMPC_API_H_)
+
+/// @} SMPC_API
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc_crypto.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc_crypto.h
new file mode 100644
index 0000000000..6362f785b2
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc_crypto.h
@@ -0,0 +1,177 @@
+/**
+ ****************************************************************************************
+ *
+ * @file smpc_crypto.h
+ *
+ * @brief Header file for SMP Secure Connection Cryptographic Functions
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef SMPC_CRYPTO_H_
+#define SMPC_CRYPTO_H_
+
+#include "rwip_config.h"
+#if (SECURE_CONNECTIONS)
+#include "smp_common.h"
+
+/**
+ ****************************************************************************************
+ * @brief Initiates the F4 crypto function
+ *
+ * @param[in] conidx connection identifier
+ * @param[in] U pointer to array of bytes (see spec)
+ * @param[in] V pointer to array of bytes (see spec)
+ * @param[in] X pointer to array of bytes (see spec)
+ * @param[in] Z single byte value (see spec)
+ * @return none.
+ ****************************************************************************************
+ */
+void smpc_f4_Init(uint8_t conidx,uint8_t* U,uint8_t* V,uint8_t* X,uint8_t Z);
+
+
+/**
+ ****************************************************************************************
+ * @brief Cleans up after the F4 crypto function, freeing any memory which had been allocated
+ *
+ * @param[in] conidx connection identifier
+ * @return none.
+ ****************************************************************************************
+ */
+void smpc_f4_complete(uint8_t conidx);
+
+
+/**
+ ****************************************************************************************
+ * @brief Initiates the G2 crypto function
+ *
+ * @param[in] conidx connection identifier
+ * @param[in] U pointer to array of bytes (see spec)
+ * @param[in] V pointer to array of bytes (see spec)
+ * @param[in] X pointer to array of bytes (see spec)
+ * @param[in] Y pointer to array of bytes (see spec)
+ * @return none.
+ ****************************************************************************************
+ */
+void smpc_g2_init(uint8_t conidx, uint8_t* U, uint8_t* V, uint8_t* X, uint8_t* Y);
+
+/**
+ ****************************************************************************************
+ * @brief Cleans up after the G2 crypto function, freeing any memory which had been allocated
+ *
+ * @param[in] conidx connection identifier
+ * @return none.
+ ****************************************************************************************
+ */
+void smpc_g2_complete(uint8_t conidx);
+
+/**
+ ****************************************************************************************
+ * @brief Initiates the F5 crypto function
+ *
+ * @param[in] conidx connection identifier
+ * @param[in] W pointer to the DH Key
+ * @param[in] N1 pointer to 16 byte random number
+ * @param[in] N2 pointer to 16 byte random number
+ * @param[in] A1 pointer to array representing address of device
+ * @param[in] A2 pointer to array representing address of device
+ * @return none.
+ ****************************************************************************************
+ */
+void smpc_f5_init(uint8_t conidx, uint8_t* W,uint8_t* N1,uint8_t* N2,uint8_t* A1,uint8_t* A2);
+
+/**
+ ****************************************************************************************
+ * @brief Cleans up after the F5 crypto function, freeing any memory which had been allocated
+ *
+ * @param[in] conidx connection identifier
+ * @return none.
+ ****************************************************************************************
+ */
+void smpc_f5_complete(uint8_t conidx);
+
+/**
+ ****************************************************************************************
+ * @brief Initiates the F6 crypto function
+ *
+ * @param[in] conidx connection identifier
+ * @param[in] W pointer to Mac Key
+ * @param[in] N1 pointer to 16 byte random number
+ * @param[in] N2 pointer to 16 byte random number
+ * @param[in] R pointer to array of bytes (see spec)
+ * @param[in] IoCap pointer to array representing IO capabilities of device
+ * @param[in] A1 pointer to array representing address of device
+ * @param[in] A2 pointer to array representing address of device
+ * @return none.
+ ****************************************************************************************
+ */
+void smpc_f6_init(uint8_t conidx,uint8_t* W, uint8_t* N1, uint8_t* N2, uint8_t* R, uint8_t* IOcap, uint8_t* A1, uint8_t* A2);
+
+/**
+ ****************************************************************************************
+ * @brief Cleans up after the F6 crypto function, freeing any memory which had been allocated
+ *
+ * @param[in] conidx connection identifier
+ * @return none.
+ ****************************************************************************************
+ */
+void smpc_f6_complete(uint8_t conidx);
+
+/**
+ ****************************************************************************************
+ * @brief Initiates the AES CMAC crypto function. Allocate memory for the CMAC and
+ * begins the subkey generation
+ *
+ * @param[in] conidx connection identifier
+ * @param[in] K pointer to the Key to be used
+ * @param[in] M pointer to the block of data the data on which the CMAC is performed
+ * @param[in] M_len length (in bytes) of the block of data M
+ * @return none.
+ ****************************************************************************************
+ */
+void smpc_aes_cmac_init(uint8_t conidx,uint8_t* K,uint8_t* M,uint8_t M_len);
+
+/**
+ ****************************************************************************************
+ * @brief Continues subsequent stages of the AES CMAC crypto function
+ *
+ * @param[in] conidx connection identifier
+ * @param[in] aes_res point to the result of the previous stage of the AES CMAC
+ *
+ * @return none.
+ ****************************************************************************************
+ */
+void smpc_aes_cmac_continue(uint8_t conIdx,uint8_t* aes_res);
+
+/**
+ ****************************************************************************************
+ * @brief The final stage of the AES CMAC crypto function
+ *
+ * @param[in] conidx connection identifier
+ * @param[in] aes_res point to the result of the previous stage of the AES CMAC
+ *
+ * @return none.
+ ****************************************************************************************
+ */
+void smpc_aes_cmac_complete(uint8_t conIdx,uint8_t* aes_res);
+
+/**
+ ****************************************************************************************
+ * @brief Process the next stage of the AES CMAC (wrapping smpc_aes_cmac_continue(..) and
+ * smpc_aes_cmac_complete(..)
+ *
+ * @param[in] conidx connection identifier
+ * @param[in] aes_res point to the result of the previous stage of the AES CMAC
+ *
+ * @returns boolean Indicate if the AES CMAC is complete
+ ****************************************************************************************
+ */
+
+bool smpc_process_aes_cmac(uint8_t idx,uint8_t* aes_res);
+#endif // (SECURE_CONNECTIONS)
+
+
+#endif /* SMPC_CRYPTO_H_ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc_int.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc_int.h
new file mode 100644
index 0000000000..3523b12721
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc_int.h
@@ -0,0 +1,511 @@
+/**
+ ****************************************************************************************
+ *
+ * @file smpc_int.h
+ *
+ * @brief Header file - SMPC.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef SMPC_INT_H_
+#define SMPC_INT_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup SMP_INT Security Manager Protocol Internal
+ * @ingroup HOST
+ * @brief Security Manager Protocol Internals.
+ * @{
+ *
+ ****************************************************************************************
+ */
+
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "rwip_config.h"
+
+#if (BLE_SMPC)
+#include "smpc.h"
+
+#include "smp_common.h"
+
+#include
+#include
+
+#include "co_bt.h"
+#include "gap.h"
+
+#include "smpc_api.h"
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/// Minimum Encryption key size
+#define SMPC_MIN_ENC_SIZE_LEN (7)
+/// Maximum Encryption Key size
+#define SMPC_MAX_ENC_SIZE_LEN (16)
+
+
+/// Pairing Request and Pairing Response PDU Length
+#define SMPC_CODE_PAIRING_REQ_RESP_LEN (7)
+
+
+/*
+ * ENUMERATIONS
+ ****************************************************************************************
+ */
+
+
+///Security Properties for distributed keys(all have the issued STK's properties)
+enum
+{
+ ///No security properties
+ SMP_KSEC_NONE = 0x00,
+ ///Unauthenticated no MITM
+ SMP_KSEC_UNAUTH_NO_MITM,
+ ///Authenticated with MITM
+ SMP_KSEC_AUTH_MITM,
+};
+
+/// Repeated Attempts Attack Detection status
+enum smpc_attempts_status
+{
+ /// No attack has been detected
+ SMPC_REP_ATTEMPTS_NO_ERROR = GAP_ERR_NO_ERROR, // 0x00
+ /// An attack has already been detected, drop the message
+ SMPC_REP_ATTEMPTS_ATTACK,
+ /// An attack has been detected, an indication has been sent to the HL
+ SMPC_REP_ATTEMPS_ATTACK_DETECTED,
+ /// Repeated Attempt detected, need to send a Pairing Failed PDU to the peer device
+ SMPC_REP_ATTEMPT = SMP_ERROR_REPEATED_ATTEMPTS // 0x09
+};
+
+
+/// STK generation methods
+enum smpc_method
+{
+ ///Just Works Method
+ SMPC_METH_JW = 0x00,
+ ///PassKey Entry Method
+ SMPC_METH_PK,
+ ////OOB Method
+ SMPC_METH_OOB,
+ ////Numeric Comparison
+ SMPC_METH_NC
+};
+
+/// Signature Command Types
+enum
+{
+ /// Generate Signature
+ SMPC_SIGN_GEN = 0x00,
+ /// Verify Signature
+ SMPC_SIGN_VERIF
+};
+
+enum
+{
+ /// Use of STK in start encryption command
+ SMPC_USE_STK = 0x00,
+ /// Use of LTK in start encryption command
+ SMPC_USE_LTK
+};
+
+#if (SECURE_CONNECTIONS)
+enum
+{
+ SMP_AES_CMAC_KEY_GENERATION = 0x00,
+
+ SMP_AES_CMAC_BLOCK
+};
+
+/// Keypress Notification types
+enum smpc_notification_type
+{
+ /// Passkey entry started
+ SMP_PASSKEY_ENTRY_STARTED = 0x00,
+ /// Passkey digit entered
+ SMP_PASSKEY_DIGIT_ENTERED,
+ /// Passkey digit erased
+ SMP_PASSKEY_DIGIT_ERASED,
+ /// Passkey cleared
+ SMP_PASSKEY_CLEARED,
+ /// Passkey entry completed
+ SMP_PASSKEY_ENTRY_COMPLETED
+};
+#endif // (SECURE_CONNECTIONS)
+/*
+ * STRUCTURES DEFINITION
+ ****************************************************************************************
+ */
+
+/*
+ * GLOBAL VARIABLES DEFINITION
+ ****************************************************************************************
+ */
+
+
+/*
+ * MACROS
+ ****************************************************************************************
+ */
+/// Authentication Request mask
+#define SMPC_MASK_AUTH_REQ(req) (req & 0x07)
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief Send a SMPM_USE_ENC_BLOCK_CMD message to the SMPM. Shall be use when the AES_128
+ * encryption block need to be used.
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] operand_1 First operand
+ * @param[in] operand_2 Second operand
+ ****************************************************************************************
+ */
+void smpc_send_use_enc_block_cmd(uint8_t conidx,
+ uint8_t *operand_1, uint8_t *operand_2);
+
+
+/**
+ ****************************************************************************************
+ * @brief Send a SMPM_GEN_DH_KEY_CMD message to the SMPM. Shall be use when we need to
+ * generate a DH KEy
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] operand_1 X co-ordinate
+ * @param[in] operand_2 Y co-ordinate
+ ****************************************************************************************
+ */
+
+void smpc_send_gen_dh_key_cmd(uint8_t conidx,
+ uint8_t *operand_1, uint8_t *operand_2);
+
+/**
+ ****************************************************************************************
+ * @brief Send a request to the controller to start the encryption procedure.
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] operand_1 First operand
+ * @param[in] operand_2 Second operand
+ ****************************************************************************************
+ */
+void smpc_send_start_enc_cmd(uint8_t idx, uint8_t key_type, uint8_t *key,
+ uint8_t *randnb, uint16_t ediv);
+
+/**
+ ****************************************************************************************
+ * @brief Send the LTK provided by the HL to the controller.
+ *
+ * @param[in] idx Connection Index
+ * @param[in] found Indicate if the requested LTK has been found by the application
+ * @param[in] key Found LTK, used only if found is set to true
+ ****************************************************************************************
+ */
+void smpc_send_ltk_req_rsp(uint8_t idx, bool found, uint8_t *key);
+
+/**
+ ****************************************************************************************
+ * @brief Send a SMPC_PAIRING_REQ_IND message to the HL
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] req_type Kind of request
+ ****************************************************************************************
+ */
+void smpc_send_pairing_req_ind(uint8_t conidx, uint8_t req_type);
+
+/**
+ ****************************************************************************************
+ * @brief Send a SMPC_PAIRING_IND message to the HL
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] ind_type Kind of indication
+ * @param[in] value Value to indicate (keys, ...)
+ ****************************************************************************************
+ */
+void smpc_send_pairing_ind(uint8_t conidx, uint8_t ind_type, void *value);
+
+/**
+ ****************************************************************************************
+ * @brief Check if the provided pairing features are within the specified range.
+ *
+ * @param[in] pair_feat Pairing Features values to check
+ *
+ * @param[out] true if features are valid, else false
+ ****************************************************************************************
+ */
+bool smpc_check_pairing_feat(struct gapc_pairing *pair_feat);
+
+/**
+ ****************************************************************************************
+ * @brief Check if an attack by repeated attempts has been triggered by the peer device
+ *
+ * @param[in] conidx Connection Index
+ ****************************************************************************************
+ */
+uint8_t smpc_check_repeated_attempts(uint8_t conidx);
+
+/**
+ ****************************************************************************************
+ * @brief Compute and check the encryption key size to use during the connection.
+ *
+ * @param[in] conidx Connection Index
+ *
+ * @param[out] true if the resultant EKS is within the specified range [7-16 bytes], else false
+ ****************************************************************************************
+ */
+bool smpc_check_max_key_size(uint8_t conidx);
+
+/**
+ ****************************************************************************************
+ * @brief Check if the keys distribution scheme is compliant with the required security
+ * level
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] sec_level Security level required by the device.
+ ****************************************************************************************
+ */
+bool smpc_check_key_distrib(uint8_t conidx, uint8_t sec_level);
+
+/**
+ ****************************************************************************************
+ * @brief Apply the XOR operator to the two provided operands
+ *
+ * @param[in|out] result Buffer which will contain the result of the XOR operation
+ * @param[in] operand_1 First operand
+ * @param[in] operand_2 Second operand
+ ****************************************************************************************
+ */
+void smpc_xor(uint8_t *result, uint8_t *operand_1, uint8_t *operand_2);
+
+/**
+ ****************************************************************************************
+ * @brief Generate the L value during a signature verification/generation procedure.
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] src Indicate the source of the CSRK which will be used (LOCAL or PEER)
+ ****************************************************************************************
+ */
+void smpc_generate_l(uint8_t conidx, uint8_t src);
+
+/**
+ ****************************************************************************************
+ * @brief Generate one of the Ci value during a signature verification/generation procedure.
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] src Indicate the source of the CSRK which will be used (LOCAL or PEER)
+ * @param[in] ci1 Previous computed Ci value
+ * @param[in] mi 16-byte block used to generate the ci value
+ ****************************************************************************************
+ */
+void smpc_generate_ci(uint8_t conidx, uint8_t src, uint8_t *ci1, uint8_t *mi);
+
+/**
+ ****************************************************************************************
+ * @brief Generate the random value exchanged during the pairing procedure (phase 2)
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] state New state of the SMPC task.
+ ****************************************************************************************
+ */
+void smpc_generate_rand(uint8_t conidx, uint8_t state);
+
+/**
+ ****************************************************************************************
+ * @brief Generate the first value needed in the confirm value generation
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] role Current role of the device
+ * @param[in] local true if the confirm value to generate is the confirm value of the
+ * device, false if it is the remote device's one.
+ ****************************************************************************************
+ */
+void smpc_generate_e1(uint8_t conidx, uint8_t role, bool local);
+
+/**
+ ****************************************************************************************
+ * @brief Generate the confirm value
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] role Current role of the device
+ * @param[in] e1 e1 value
+ ****************************************************************************************
+ */
+void smpc_generate_cfm(uint8_t conidx, uint8_t role, uint8_t *e1);
+
+/**
+ ****************************************************************************************
+ * @brief Generate the STK used to encrypt a link after the pairing procedure
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] role Current role of the device
+ ****************************************************************************************
+ */
+void smpc_generate_stk(uint8_t conidx, uint8_t role);
+
+/**
+ ****************************************************************************************
+ * @brief Calculate one of the subkey used during the signature generation/verification
+ * procedure.
+ *
+ * @param[in] gen_k2 true if the returned subkeys is k2, false if k1
+ * @param[in] l_value L value obtained from the CSRK.
+ * @param[in|out] subkey Buffer which will contain the generated subkey.
+ ****************************************************************************************
+ */
+void smpc_calc_subkeys(bool gen_k2, uint8_t *l_value, uint8_t *subkey);
+
+/**
+ ****************************************************************************************
+ * @brief Start to send the keys defined during the pairing features exchange procedure.
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] role Current role of the device
+ ****************************************************************************************
+ */
+void smpc_tkdp_send_start(uint8_t conidx, uint8_t role);
+
+/**
+ ****************************************************************************************
+ * @brief Define the next step of TKDP procedure (sending side).
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] role Current role of the device
+ ****************************************************************************************
+ */
+void smpc_tkdp_send_continue(uint8_t conidx, uint8_t role);
+
+/**
+ ****************************************************************************************
+ * @brief Put the task in a state allowing to receive the keys defined during the pairing
+ * features exchange procedure.
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] role Current role of the device
+ ****************************************************************************************
+ */
+void smpc_tkdp_rcp_start(uint8_t conidx, uint8_t role);
+
+/**
+ ****************************************************************************************
+ * @brief Define the next step of TKDP procedure (reception side).
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] role Current role of the device
+ ****************************************************************************************
+ */
+void smpc_tkdp_rcp_continue(uint8_t conidx, uint8_t role);
+
+
+/**
+ ****************************************************************************************
+ * @brief Start the timer used to detect a Repeated Attempts attack
+ *
+ * @param[in] conidx Connection Index
+ ****************************************************************************************
+ */
+void smpc_launch_rep_att_timer(uint8_t conidx);
+
+/**
+ ****************************************************************************************
+ * @brief Determine the method which will be used to generate the STK during a pairing
+ * procedure
+ *
+ * @param[in] conidx Connection Index
+ ****************************************************************************************
+ */
+void smpc_get_key_sec_prop(uint8_t conidx);
+
+/**
+ ****************************************************************************************
+ * @brief Check if the security mode requested by the application or the peer device can
+ * be reached with the exchanged pairing features.
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] role Current role of the device
+ ****************************************************************************************
+ */
+bool smpc_is_sec_mode_reached(uint8_t conidx, uint8_t role);
+
+/**
+ ****************************************************************************************
+ * @brief Define what to do once a start encryption procedure has been successfully finished.
+ *
+ * @param[in] conidx Connection Index
+ * @param[in] role Current role of the device
+ * @param[in] status Status
+ ****************************************************************************************
+ */
+void smpc_handle_enc_change_evt(uint8_t conidx, uint8_t role, uint8_t status);
+
+
+#if (SECURE_CONNECTIONS)
+/**
+ ****************************************************************************************
+ * @brief Initiate DHKey Check algorithm
+ *
+ * @param[in] conidx Connection Index
+ ****************************************************************************************
+ */
+void smpc_initiate_dhkey_check(uint8_t conidx);
+
+/**
+ ****************************************************************************************
+ * @brief Initiates the f5 algorithm to calculate the MacKey and LTK for a link
+ *
+ * @param[in] conidx Connection Index
+ *
+ ****************************************************************************************
+ */
+
+void smpc_init_mac_key_calculation(uint8_t conidx);
+
+/**
+ ****************************************************************************************
+ * @brief Initiates the f6 algorithm to verify a DH Key Check.
+ *
+ * @param[in] conidx Connection Index
+ *
+ ****************************************************************************************
+ */
+
+void smpc_initiate_dhkey_verification(uint8_t conidx);
+
+/**
+ ****************************************************************************************
+ * @brief Determines the next bit of the passkey to be used
+ *
+ * @param[in] conidx Connection Index
+ *
+ ****************************************************************************************
+ */
+uint8_t smpc_get_next_passkey_bit(uint8_t conidx);
+
+/**
+ ****************************************************************************************
+ * @brief Checks if secure connections are enabled on a link
+ *
+ * @param[in] conidx Connection Index
+ *
+ ****************************************************************************************
+ */
+bool smpc_secure_connections_enabled(uint8_t idx);
+
+#endif // (SECURE_CONNECTIONS)
+#endif //(BLE_SMPC)
+#endif //SMPC_INT_H_
+
+/// @} SMPC
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc_util.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc_util.h
new file mode 100644
index 0000000000..5e3ed048a9
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc_util.h
@@ -0,0 +1,82 @@
+/**
+ ****************************************************************************************
+ *
+ * @file smpc_util.h
+ *
+ * @brief Header file for SMPC utilities.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef SMPC_UTIL_H_
+#define SMPC_UTIL_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup SMPC_UTIL Utility
+ * @ingroup SMPC
+ * @brief Contains utility functions and macros for SMPC.
+ *
+ * The SMPC Utilities block contains key generating and security related functions
+ * that are useful in accomplishing the task of the security manager protocol
+ * layer of the Bluetooth Low Energy.
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "rwip_config.h"
+#if (BLE_SMPC)
+
+#include "smp_common.h"
+#include
+
+#include "l2cc_pdu.h"
+#include "smpc_int.h"
+
+/*
+ * TYPE DEFINITIONS
+ ****************************************************************************************
+ */
+
+/// SMPC command PDU construct function pointer type definition
+typedef void (*smpc_construct_pdu_t)(struct l2cc_pdu *pdu, void *value);
+
+/// SMPC command PDU reception functions
+typedef void (*smpc_recv_pdu_t)(uint8_t idx, struct l2cc_pdu *pdu);
+
+/*
+ * GLOBAL VARIABLES DECLARATION
+ ****************************************************************************************
+ */
+
+extern const smpc_construct_pdu_t smpc_construct_pdu[L2C_CODE_SECURITY_MAX];
+extern const smpc_recv_pdu_t smpc_recv_pdu[L2C_CODE_SECURITY_MAX];
+
+/*
+ * FUNCTIONS DECLARATION
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief Parameter checking function of SMP PDU packets.
+ *
+ * @param[in] pdu Pointer to the data part of the SMP command PDU.
+ *
+ * @return Value of check parameter status, to be reported to host or back to peer.
+ ****************************************************************************************
+ */
+uint8_t smpc_check_param(struct l2cc_pdu *pdu);
+
+#endif //(BLE_SMPC)
+#endif //(SMPC_UTIL_H_)
+
+/// @} SMPC_UTIL
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpm_api.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpm_api.h
new file mode 100644
index 0000000000..bb27203e61
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpm_api.h
@@ -0,0 +1,125 @@
+/**
+ ****************************************************************************************
+ *
+ * @file smpm_api.h
+ *
+ * @brief Header file - SMPM API
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef SMPM_API_H_
+#define SMPM_API_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup SMPM_API Security Manager Protocol Manager API
+ * @ingroup SMPM
+ * @brief Provide an API to GAPM task
+ *
+ * The SMPM is responsible for all security related functions not related to a
+ * specific connection with a peer.
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+
+
+#include "rwip_config.h"
+#if (BLE_SMPM)
+#include "gap.h" // GAP Definitions
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+
+/*
+ * ENUMERATIONS
+ ****************************************************************************************
+ */
+
+
+/*
+ * STRUCTURES
+ ****************************************************************************************
+*/
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+
+/**
+ ****************************************************************************************
+ * @brief Generate a random address
+ *
+ * @param[in] addr_type Provided address type
+ *
+ * @return If request has been processed or not
+ ****************************************************************************************
+ */
+uint8_t smpm_gen_rand_addr(uint8_t addr_type);
+
+/**
+ ****************************************************************************************
+ * @brief Resolve a random address
+ * Note: address should be resolvable
+ *
+ * @param[in] addr Device address
+ * @param[in] irk IRK used for address resolution
+ *
+ ****************************************************************************************
+ */
+void smpm_resolv_addr(bd_addr_t* addr, struct gap_sec_key *irk);
+
+
+/**
+ ****************************************************************************************
+ * @brief Use the encryption block
+ *
+ * @param[in] operand_1 First operand as encryption block input (16 bytes)
+ * @param[in] operand_2 Second operand as encryption block input (16 bytes)
+ *
+ ****************************************************************************************
+ */
+void smpm_use_enc_block(uint8_t *operand_1, uint8_t *operand_2);
+
+/**
+ ****************************************************************************************
+ * @brief Generate a random number
+ ****************************************************************************************
+ */
+void smpm_gen_rand_nb(void);
+
+
+
+/**
+ ****************************************************************************************
+ * @brief Send an encryption request to the HCI.
+ ****************************************************************************************
+ */
+void smpm_send_encrypt_req(uint8_t *operand_1, uint8_t *operand_2);
+
+#if (SECURE_CONNECTIONS)
+/**
+ ****************************************************************************************
+ * @brief Send a generate DH Key request to the HCI.
+ ****************************************************************************************
+ */
+void smpm_send_generate_dh_key(uint8_t *operand_1, uint8_t *operand_2);
+#endif // (SECURE_CONNECTIONS)
+
+#endif // (BLE_SMPM)
+#endif // (SMPM_API_H_)
+
+/// @} SMPM_API
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/n32wb452_ble_api.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/n32wb452_ble_api.c
new file mode 100644
index 0000000000..0e58815864
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/n32wb452_ble_api.c
@@ -0,0 +1,300 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_ble_api.c
+ * @author Nations
+ * @version v1.0.1
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32wb452.h"
+#include "Eif_uart.h"
+#include "user.h"
+#include "n32wb452_ble_api.h"
+#include "n32wb452_data_fifo.h"
+#include "n32wb452_log_level.h"
+#include "app_task.h"
+#include "eif_spi.h"
+#include "interface.h"
+#include "app.h"
+#include "app_user.h"
+#include "rwip.h"
+#include "ke.h"
+#include "ble_monitor.h"
+#include "main.h"
+
+#define XOTRIM 0
+
+#ifdef N32WB452_BT_API
+
+//static uint32_t g_overtime_count;
+//static uint32_t g_timer_count_flag;
+bt_attr_param * g_bt_init = NULL;
+uint32_t g_bt_start_finished_flag = 0;
+uint32_t g_connnet_start;
+bt_event_callback_handler_t g_pcallback = NULL;
+
+
+void eif_timer_init(void);
+void bt_state_get(void);
+
+void bt_handler(void)
+{
+ eif_spi_recv_irq_handler();
+}
+
+
+
+/***************************************************************************************
+declaraction: int32_t bt_ware_init(bt_attr_param *pinit, bt_event_callback_handler_t pcallback)
+function : åˆå§‹åŒ–è“牙模??
+parameter : è“牙åˆå§‹åŒ–æ•°??
+parameter : è“牙事件回调函数
+return : NONE
+***************************************************************************************/
+int32_t bt_ware_init(bt_attr_param *pinit, bt_event_callback_handler_t pcallback)
+{
+ int32_t ret;
+// uint32_t ble_init_status = 0;
+ g_bt_init = pinit;
+
+ ret = ble_interface_init();
+ if (ret != E_OK) {
+ return BT_RET_OPERATED_FAILDED_ERR;
+ }
+
+ //2
+ ret = ble_hardware_init();
+ if (ret != E_OK) {
+ return BT_RET_OPERATED_FAILDED_ERR;
+ }
+
+ //3
+ ret = ble_initdata_down();
+ if (ret != E_OK) {
+ return BT_RET_OPERATED_FAILDED_ERR;
+ }
+
+#if (XOTRIM)
+ //--crystal frequency accuracy calibration--
+ eif_delay_ms(300);
+
+ //01 03 fd 08 04 00 00 43 ff ff ff ff
+ uint8_t cmd_1[12] ={0x01, 0x03, 0xfd,0x08, 0x04, 0x00, 0x00, 0x43, 0xff, 0xff , 0xff, 0xff};
+ eif_spi_send_bytes(cmd_1, 12);
+ eif_spi_recv_bytes(cmd_1, 7) ; //no need to return
+ //01 03 fd 08 00 00 40 52 0A 00 03 00
+ uint8_t cmd_2[12] ={0x01, 0x03, 0xfd,0x08, 0x00, 0x00, 0x40, 0x52, 0x0a, 0x00, 0x03, 0x00};
+ eif_spi_send_bytes(cmd_2, 12);
+ eif_spi_recv_bytes(cmd_2, 7) ; //no need to return
+ while (1);
+#endif
+
+ //4
+ ret = ble_host_init();
+ if (ret != E_OK) {
+ return BT_RET_OPERATED_FAILDED_ERR;
+ }
+
+ g_pcallback = pcallback;
+
+ gBT_STS = BT_INITIALIZED;
+
+ return BT_RET_SUCCESS;
+}
+
+
+/***************************************************************************************
+declaraction: void bt_run_thread(void)
+function : è“牙è¿è¡Œçš„主线程，用于è“牙接收ã€å‘é€ã€é€šçŸ¥ç‰å¤„??
+parameter : void
+return : NONE
+***************************************************************************************/
+void bt_run_thread(void)
+{
+ BT_handle();
+}
+
+
+/***************************************************************************************
+declaraction: uint32_t bt_rcv_data(uint8_t *data, uint32_t size, uint32_t character)
+function : æ ¹æ®BT_EVENT_RCV_DATA事件，读å–相应æœåŠ¡ç‰¹å¾å—çš„æ•°??
+parameter : uint8_t *data 接收数æ®buf
+parameter : uint32_t size buf大å°(最大ä¸è¶…过512Bytes)
+parameter : uint32_t character å‘生数æ®é€šçŸ¥å¯¹åº”的特å¾å—ID
+return : 返回实际读å–大å°
+***************************************************************************************/
+uint32_t bt_rcv_data(uint8_t *data, uint32_t size, uint32_t character)
+{
+ uint32_t read_size;
+
+ read_size = fifo_read(data, &size);
+ return read_size;
+}
+
+
+/***************************************************************************************
+declaraction: uint32_t bt_rcv_data(const uint8_t *data, uint32_t size, uint32_t character)
+function : å‘é€æ•°æ®åˆ°å¯¹åº”的特å¾å—
+parameter : uint8_t *data å‘é€æ•°æ®buf
+parameter : uint32_t å‘é€æ•°æ®å¤§??最大ä¸è¶…过512Bytes)
+parameter : uint32_t character 对应特å¾å—ID
+return : 返回值0
+***************************************************************************************/
+uint32_t bt_snd_data(const uint8_t *data, uint32_t size, uint32_t character)
+{
+// if (g_connnet_start) {
+// if (data && size && character) {
+ app_user_data_notify(size, (uint8_t *)data, character);
+// return size;
+// }
+// }
+ return 0;
+}
+
+/***************************************************************************************
+declaraction: void bt_disconnect(void)
+function : slave主动æ–å¼€è“牙连接
+parameter : NULL
+return : NULL
+***************************************************************************************/
+void bt_disconnect(void)
+{
+ appm_disconnect();
+}
+
+/***************************************************************************************
+declaraction: uint32_t bluetooth_state_get(void)
+function : 获å–è“牙连接状æ€,ä¸å¯¹å¤–开放
+parameter : NULL
+return : NULL
+***************************************************************************************/
+void bt_state_get(void)
+{
+ static ke_state_t ble_state_last;
+ ke_state_t ble_state;
+// bt_event_enum bt_status = BT_EVENT_DISCONNECTD;
+
+ ble_state = ke_state_get(TASK_APP);
+
+
+ switch (ble_state)
+ {
+ case APPM_CREATE_DB:
+ break;
+ case APPM_ADVERTISING:
+ if (ble_state_last == APPM_CONNECTED)
+ {
+ if (g_pcallback) {
+ g_pcallback(BT_EVENT_DISCONNECTD, NULL, 0, 0);
+ }
+ g_connnet_start = 0;
+ }
+ break;
+ case APPM_CONNECTED:
+ if (ble_state_last == APPM_ADVERTISING)
+ {
+ if (g_pcallback) {
+ g_pcallback(BT_EVENT_CONNECTED, NULL, 0, 0);
+ }
+ g_connnet_start = 1;
+ }
+ break;
+ case APPM_START_ENC:
+ break;
+ case APPM_ENCRYPTED:
+ break;
+ case APPM_INIT:
+ break;
+ }
+ ble_state_last = ble_state;
+}
+
+/*contain standard bluetooth version and frimware version*/
+#define BT_VERSION_INFO "V4.2_1127"
+
+
+/*==============================================================================
+BT_Init
+
+ This function is to initialize bluetooth stack
+==============================================================================*/
+void BT_init(void)
+{
+ rwip_init(RESET_NO_ERROR);
+}
+
+/*==============================================================================
+is_bt_busy
+
+
+ This function is to get the bt kernel processing is ongoing or not.
+ if not onging, then allow to sleep, otherwise not allow to sleep.
+
+
+ 0: bt kernel processing is not ongoing
+ 1: bt kernel processing is ongoing
+==============================================================================*/
+bool is_bt_busy(void)
+{
+ return (!ke_sleep_check());
+}
+
+
+/*==============================================================================
+BT_handle
+
+
+ This function is schedule the BT tasks
+==============================================================================*/
+void BT_handle(void)
+{
+ rwip_schedule();
+}
+
+
+/*==============================================================================
+BT_get_version
+
+
+ This function is to get version of BT API.
+
+
+ version: store the data of the BT API version, size 10 byte;
+==============================================================================*/
+void BT_get_version(uint8_t * version)
+{
+ if (version == NULL)
+ {
+ return;
+ }
+ memcpy(version, BT_VERSION_INFO, sizeof(BT_VERSION_INFO));
+}
+
+#endif
+
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/n32wb452_ble_api.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/n32wb452_ble_api.h
new file mode 100644
index 0000000000..fb9648e46c
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/n32wb452_ble_api.h
@@ -0,0 +1,262 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @brief bluetooth functions.
+ * @file n32wb452_ble_api.h
+ * @author Nations
+ * @version v1.0.1
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __N32WB452_BLE_API_H__
+#define __N32WB452_BLE_API_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32wb452.h"
+
+#define BLE_SERVICE_USED 1 //用到的è“牙æœåŠ¡æ•°é‡
+#define BLE_CHARACTER_USED 1 //用到的特å¾å—æ•°é‡
+
+/**
+ * @brief 返回值类型定义
+ */
+typedef enum bt_ret_enum_t
+{
+ BT_RET_SUCCESS = 0, //æ“作æˆåŠŸ
+ BT_RET_OPERATED_FAILDED_ERR, //æ“作失败
+ BT_RET_PARAM_NULL_ERR, //å‚数为空错误
+ BT_RET_PARAM_ERR, //å‚数错误
+}bt_ret_enum;
+
+
+/**
+ * @brief 定义è“牙事件
+ */
+typedef enum bt_event_enum_t
+{
+ BT_EVENT_VERSION, //返回è“牙软件版本，如'V1000'表示Ver1.000
+ BT_EVENT_CONNECTED, //表示è“牙已连接
+ BT_EVENT_DISCONNECTD, //表示è“牙已æ–å¼€
+ BT_EVENT_RCV_DATA, //表示è“牙模å—接收到了主机端下å‘çš„æ•°æ®
+}bt_event_enum;
+
+/**
+ * @brief 特å¾å—æƒé™
+ */
+typedef enum bt_character_perm_t
+{
+ BT_RD_PERM = 0x00001, //主机åªè¯»
+ BT_WRITE_PERM = 0x00002, //主机å¯å†™ï¼Œè®¾å¤‡ç«¯æ— response
+ BT_WRITE_REQ_PERM = 0x00004, //主机å¯å†™ï¼Œè®¾å¤‡ç«¯æœ‰response
+ BT_NTF_PERM = 0x00008, //设备通知
+}bt_character_perm;
+
+
+typedef void (*bt_event_callback_handler_t)(bt_event_enum event, const uint8_t * data, uint32_t size, uint32_t character_uuid);
+
+
+/**
+ * @brief è“牙控制å‚æ•°é…ç½®
+ */
+typedef struct bt_control_param_t
+{
+ uint32_t multi_mode:1; //0:disable connect multiple,1:enable connect multiple
+ uint32_t reserved:31; //
+}bt_control_param;
+
+/**
+ * @brief è“牙æœåŠ¡å®šä¹‰
+ */
+typedef struct bt_svc_param_t
+{
+ uint16_t svc_uuid; /// 16 bits UUID，从0xFEC1开始
+
+ struct bt_character{
+ uint16_t uuid;
+ uint16_t permission;//reference to bt_character_perm
+ }character[BLE_CHARACTER_USED];
+}bt_svc_param;
+
+
+
+/**
+ * @brief è“牙相关属性é…ç½®
+ */
+typedef struct bt_attr_param_t
+{
+ bt_control_param ctrl_param; //è“牙控制å‚æ•°
+ uint8_t device_name[32]; //è“牙设备å.4å—符以上有效。如全为0x00æˆ–æ— æ•ˆå称，则使用自带默认å称
+ uint8_t scan_rsp_data[31]; //广æ’应ç”æ•°æ®ï¼Œå®žé™…有效长度30
+ uint8_t scan_rsp_data_len; //广æ’应ç”æ•°æ®
+ uint8_t device_addr[20]; //æ ¼å¼å¦‚："11:22:33:44:55:66"。如é…置为0则为默认地å€
+
+ //adv data
+ bt_svc_param service[BLE_SERVICE_USED];
+}bt_attr_param;
+
+
+/***************************************************************************************
+declaraction: int32_t bt_ware_init(bt_event_pcallback pcallback)
+function : åˆå§‹åŒ–è“牙模å—
+parameter : è“牙åˆå§‹åŒ–æ•°æ®
+parameter : è“牙事件回调函数
+return : NONE
+***************************************************************************************/
+int32_t bt_ware_init(bt_attr_param *pinit, bt_event_callback_handler_t pcallback);
+
+
+/***************************************************************************************
+declaraction: void bt_tick_count(void)
+function : è“牙模å—需è¦çš„计时函数(默认定时:5ms)
+parameter : void
+return : NONE
+***************************************************************************************/
+//void bt_tick_count(void);
+
+
+/***************************************************************************************
+declaraction: void bt_handler(void)
+function : è“牙ä¸æ–处ç†
+parameter : void
+return : NONE
+***************************************************************************************/
+void bt_handler(void);
+
+/***************************************************************************************
+declaraction: void bt_run_thread(void)
+function : è“牙è¿è¡Œçš„主线程，用于è“牙接收ã€å‘é€ã€é€šçŸ¥ç‰å¤„ç†
+parameter : void
+return : NONE
+***************************************************************************************/
+void bt_run_thread(void);
+
+
+/***************************************************************************************
+declaraction: uint32_t bt_rcv_data(uint8_t *data, uint32_t size, uint32_t character)
+function : æ ¹æ®BT_EVENT_RCV_DATA事件，读å–相应æœåŠ¡ç‰¹å¾å—çš„æ•°æ®
+parameter : uint8_t *data 接收数æ®buf
+parameter : uint32_t size buf大å°(最大ä¸è¶…过512Bytes)
+parameter : uint32_t character å‘生数æ®é€šçŸ¥å¯¹åº”的特å¾å—ID
+return : 返回实际读å–大å°
+***************************************************************************************/
+uint32_t bt_rcv_data(uint8_t *data, uint32_t size, uint32_t character);
+
+
+/***************************************************************************************
+declaraction: uint32_t bt_rcv_data(const uint8_t *data, uint32_t size, uint32_t character)
+function : å‘é€æ•°æ®åˆ°å¯¹åº”的特å¾å—
+parameter : uint8_t *data å‘é€æ•°æ®buf
+parameter : uint32_t å‘é€æ•°æ®å¤§å°(最大ä¸è¶…过512Bytes)
+parameter : uint32_t character 对应特å¾å—ID
+return : 返回值0
+***************************************************************************************/
+uint32_t bt_snd_data(const uint8_t *data, uint32_t size, uint32_t character);
+
+
+/***************************************************************************************
+declaraction: void bt_disconnect(void)
+function : slave主动æ–å¼€è“牙连接
+parameter : NULL
+return : NULL
+***************************************************************************************/
+void bt_disconnect(void);
+
+/***************************************************************************************
+declaraction: void ble_status_monitor(void)
+function : è“牙状æ€ç›‘控
+parameter : NULL
+return : NULL
+***************************************************************************************/
+void ble_status_monitor(void);
+
+/*==============================================================================
+BT_Init
+
+ This function is to initialize bluetooth stack
+==============================================================================*/
+void BT_init(void);
+
+
+/*==============================================================================
+is_bt_busy
+
+
+ This function is to get the bt kernel processing is ongoing or not.
+ if not onging, then allow to sleep, otherwise not allow to sleep.
+
+
+ 0: bt kernel processing is not ongoing
+ 1: bt kernel processing is ongoing
+==============================================================================*/
+bool is_bt_busy(void);
+
+
+/*==============================================================================
+BT_handle
+
+
+ This function is schedule the BT tasks
+==============================================================================*/
+void BT_handle(void);
+
+/*==============================================================================
+BT_get_version
+
+
+ This function is to get version of BT API.
+
+
+ version: store the data of the BT API version, size 10 byte;
+==============================================================================*/
+void BT_get_version(uint8_t * version);
+
+extern bt_event_callback_handler_t g_pcallback;
+extern uint32_t g_connnet_start;
+
+/*==============================================================================
+ble_get_drv_version
+
+
+
+ This function is to get the version of the ble driver.
+
+
+ version: store the data of the ble driver version, size 6 byte:"V1.0.0";
+==============================================================================*/
+extern void ble_get_drv_version(char *version);
+
+#if defined __cplusplus
+}
+#endif
+#endif // __N32WB452_BLE_API_H__
+
+
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/Eif_debug.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/Eif_debug.c
new file mode 100644
index 0000000000..8c09f77c5a
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/Eif_debug.c
@@ -0,0 +1,25 @@
+#include "Eif_debug.h"
+#include "n32wb452_log_level.h"
+
+#if (PLF_DEBUG)
+void eif_assert_warn(int param0, int param1, const char *file, int line)
+{
+ ble_log(BLE_DEBUG,"WARN: %s %d L, param 0:%d 1:%d\r\n",file, line, param0, param1);
+}
+
+void eif_assert_param(int param0, int param1, const char * file, int line)
+{
+ ble_log(BLE_DEBUG,"INFO: %s %d L, param 0:%d 1:%d\r\n",file, line, param0, param1);
+ while (1);
+}
+
+void eif_assert_err(const char *condition, const char * file, int line)
+{
+ if (condition)
+ {
+ ble_log(BLE_DEBUG,"ERR: %s %d L\r\n", file, line);
+ }
+ while (1);
+}
+#endif ///(PLF_DEBUG)
+
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/Eif_flash.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/Eif_flash.c
new file mode 100644
index 0000000000..990d435507
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/Eif_flash.c
@@ -0,0 +1,53 @@
+#include // standard integer definition
+#include // string manipulation
+#include "Eif_flash.h" // flash definition
+#include "interface.h"
+//#include "flash_app_interface.h"
+
+/// Flash environment structure
+struct flash_env_tag1
+{
+ /// base address
+ uint32_t base_addr;
+ /// length
+ uint32_t length;
+};
+//static struct flash_env_tag1 flash_env;
+
+
+
+void eif_flash_init(void)
+{
+// flash_env.base_addr = FLASH_BASE_ADDR;
+// flash_env.length = FLASH_BASE_ADDR + FLASH_BLE_SIZE;
+
+}
+
+
+uint8_t eif_flash_erase(uint32_t offset, uint32_t size)
+{
+// flash_erase(flash_env.base_addr, 1);
+ return 0;
+}
+
+
+uint8_t eif_flash_write( uint32_t offset, uint32_t length, uint8_t *buffer)
+{
+// uint8_t current_page_data[FLASH_BLE_SIZE];
+// flash_read(flash_env.base_addr, current_page_data, FLASH_BLE_SIZE);
+// flash_erase(flash_env.base_addr, 1);
+// memcpy(current_page_data + offset, buffer, length);
+// flash_write(flash_env.base_addr, current_page_data, FLASH_BLE_SIZE);
+
+ return 0;
+}
+
+
+uint8_t eif_flash_read(uint32_t offset, uint32_t length, uint8_t *buffer)
+{
+// uint32_t start_Ptr = (flash_env.base_addr + offset);
+// flash_read(start_Ptr, buffer, length);
+ return 0;
+}
+/// @} FLASH
+
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/Eif_timer.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/Eif_timer.c
new file mode 100644
index 0000000000..daf7041e93
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/Eif_timer.c
@@ -0,0 +1,105 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file Eif_timer.c
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "Eif_timer.h"
+#include "bsp_timer.h"
+#include "ke_event.h"
+//#include "Eif_iom.h"
+
+
+/*************************************
+*函数å：eif_timer_isr
+*功能：设置一个定时器事件
+*å‚数：void
+*
+*返回值：void
+*备注：
+**************************************/
+void eif_timer_isr(void)
+{
+ ke_event_set(KE_EVENT_KE_TIMER);
+}
+
+/*************************************
+*函数å：eif_timer_init
+*功能：定时器åˆå§‹åŒ–，é…置自动é‡è£…值和分频系数
+*å‚数：void
+*
+*返回值：void
+*备注：
+**************************************/
+void eif_timer_init(void)
+{
+ TIM3_config(9999,35);//36分频,1MHz计数,10ms定时ä¸æ–
+}
+
+/*************************************
+*函数å：eif_set_timeout
+*功能：设置超时时间,10ms计时基数
+*å‚数：to，超时时长
+*
+*返回值：void
+*备注：
+**************************************/
+void eif_set_timeout(uint32_t to)
+{
+ TIM3_set_timeout(to);
+}
+
+/*************************************
+*函数å：eif_get_time
+*功能：获å–超时剩余时间,å•ä½ms
+*å‚数：void
+*
+*返回值：void
+*备注：
+**************************************/
+uint32_t eif_get_time(void)
+{
+ return (TIM3_get_time());
+}
+
+/*************************************
+*函数å：eif_enable_timer
+*功能：å¯åŠ¨æˆ–å…³é—定时器
+*å‚数：enable，1：å¯åŠ¨ï¼› 0：关é—
+*
+*返回值：void
+*备注：
+**************************************/
+void eif_enable_timer(bool enable)
+{
+ TIM3_IRQ_enable(enable);
+}
+
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/Interface.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/Interface.c
new file mode 100644
index 0000000000..0181b414b3
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/Interface.c
@@ -0,0 +1,571 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file Interface.c
+ * @author Nations
+ * @version v1.0.2
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+
+#include
+#include "Interface.h"
+#include "rwip.h"
+#include "Ramcode.h"
+#include "gapm_task.h"
+#include "app.h"
+#include "stdlib.h"
+#include "string.h"
+#include "stdlib.h"
+#include "app_user.h"
+#include "Eif_uart.h"
+#include "ke_event.h"
+#include "Eif_flash.h"
+#include "Eif_timer.h"
+#include "Eif_spi.h"
+#include "Eif_iom.h"
+#include "log.h"
+
+#ifdef N32WB452_BT_API
+#include "n32wb452_data_fifo.h"
+#include "n32wb452_ble_api.h"
+#include "n32wb452_log_level.h"
+
+
+extern uint32_t g_bt_start_finished_flag;
+extern bt_attr_param * g_bt_init;
+
+#endif
+
+#define RAMCODE_CMD 0xBB
+#define PATCH_CMD 0xCC
+#define NVDS_CMD 0xDD
+#define SINGLE_CMD_SIZE 0xFA
+
+uint8_t read_state_flag = READ_STATE_RX_START;
+void data_read_state_handle(uint8_t read_state_value)
+{
+ read_state_flag = read_state_value;
+}
+
+
+const struct rwip_eif_api spi_eif_api =
+{
+ eif_spi_read,
+ eif_spi_write,
+ eif_spi_flow_on,
+ eif_spi_flow_off,
+};
+
+
+const struct rwip_eif_api *rwip_eif_get(uint8_t type)
+{
+ /*harry would add */
+ const struct rwip_eif_api *ret = NULL;
+ switch (type)
+ {
+ case RWIP_EIF_AHI:
+ //ret = &uart_eif_api;
+ break;
+ case RWIP_EIF_HCIH:
+ ret = &spi_eif_api;
+ break;
+
+ default:
+ ASSERT_INFO(0, type, 0);
+ break;
+ }
+ return ret;
+}
+
+
+bool wait_for_status_enable(void)
+{
+#if 0
+ while (!eif_get_status_io_value());
+ eif_delay_us(500); //æ ¹æ®æ—¶é’Ÿé¢‘率设置为延时100us
+ while (!eif_get_status_io_value());
+ return 1;
+#else
+ uint16_t cnt = 25000;
+ while (cnt--)
+ {
+ if (eif_get_status_io_value() == 1)
+ {
+ return 1;
+ }
+ eif_delay_us(50);
+ }
+
+ return 0;
+#endif
+}
+
+void eif_delay_us(uint32_t Cnt)
+{
+ while (Cnt--)
+ for(uint16_t m = 0; m < 28; m++);
+}
+
+void eif_delay_ms(uint32_t Cnt)
+{
+ while (Cnt--)
+ {
+ eif_delay_us(999);
+ }
+}
+
+#ifdef N32WB452_BT_API
+int32_t IsAscii(uint8_t ch)
+{
+ if ((ch >= 0x20) && (ch <= 0x7E)) /*ASCII*/
+ {
+ return E_OK;
+ }
+ else
+ {
+ return E_PAR;
+ }
+}
+#endif
+
+
+extern struct app_env_tag app_env;
+void bt_features_init(void)
+{
+#ifdef N32WB452_BT_API
+ uint32_t size;
+ uint32_t name_len = 0;
+ uint32_t i;
+ uint8_t addr[BD_ADDR_LEN], ch1, ch2;
+ uint8_t device_name[32] = {0};
+ uint8_t *ptmp = "12:34:56:AB:CD:EF";
+#endif
+
+ app_env.adv_para.adv_type = GAPM_ADV_UNDIRECT; // GAP OPCODE direct ,no connect undirect
+ app_env.adv_para.channel_map = 0x7; // BTstack_data.user_config.adv_para.channel_map;//
+ app_env.adv_para.adv_int_min = 0x320; //广æ’间隔时间最å°å€¼ï¼š0.5S = 0x320*0.625 ms
+ app_env.adv_para.adv_int_max = 0x320; //广æ’间隔时间最大值：0.5S = 0x320*0.625 ms
+ app_env.adv_para.discover_mode = GAP_GEN_DISCOVERABLE;
+
+#ifdef N32WB452_BT_API
+ if (g_bt_init) {
+ size = sizeof(g_bt_init->device_name);
+ for (i = 0; i < size; i++) {
+ if (E_OK == IsAscii(g_bt_init->device_name[i])) {
+ device_name[name_len] = g_bt_init->device_name[i];
+ name_len++;
+ }
+ }
+ if (name_len >= 3) {//å¿…é¡»2个å—符以上
+ //fill name in addr data
+ app_env.adv_data_buf[app_env.adv_data_len++] = name_len + 1; // length
+ app_env.adv_data_buf[app_env.adv_data_len++] = 0x08; // device name tag
+ memcpy( &app_env.adv_data_buf[app_env.adv_data_len], device_name, name_len);
+ app_env.adv_data_len += name_len;
+ memcpy(app_env.dev_name, device_name, name_len);
+ ble_log(BLE_DEBUG,"device_name:%0s.\r\n", device_name);
+ } else {
+ uint8_t dev_name[31] = {'N','Z','_','B','L','E'};
+ uint8_t dev_name_len = 6;
+ //fill name in addr data
+ app_env.adv_data_buf[app_env.adv_data_len++] = dev_name_len + 1; // length
+ app_env.adv_data_buf[app_env.adv_data_len++] = 0x08; // device name tag
+ memcpy( &app_env.adv_data_buf[app_env.adv_data_len], dev_name, dev_name_len);
+ app_env.adv_data_len += dev_name_len;
+ memcpy(app_env.dev_name, device_name, name_len);
+ }
+ } else {
+ uint8_t dev_name[31] = {'N','Z','_','B','L','E'};
+ uint8_t dev_name_len = 6;
+ //fill name in addr data
+ app_env.adv_data_buf[app_env.adv_data_len++] = dev_name_len + 1; // length
+ app_env.adv_data_buf[app_env.adv_data_len++] = 0x08; // device name tag
+ memcpy( &app_env.adv_data_buf[app_env.adv_data_len], dev_name, dev_name_len);
+ app_env.adv_data_len += dev_name_len;
+ memcpy(app_env.dev_name, device_name, name_len);
+ }
+#else
+ uint8_t dev_name[31] = {'N','S','_','B','L','E'};
+ uint8_t dev_name_len = 6;
+ //fill name in addr data
+ app_env.adv_data_buf[app_env.adv_data_len++] = dev_name_len + 1; // length
+ app_env.adv_data_buf[app_env.adv_data_len++] = 0x08; // device name tag
+ memcpy( &app_env.adv_data_buf[app_env.adv_data_len], dev_name, dev_name_len);
+ app_env.adv_data_len += dev_name_len;
+ memcpy(app_env.dev_name, device_name, name_len);
+#endif
+
+#ifdef N32WB452_BT_API
+ if (g_bt_init) {
+ memcpy(app_env.scan_rsp_data_buf, g_bt_init->scan_rsp_data, g_bt_init->scan_rsp_data_len);
+ app_env.scan_rsp_data_buf[g_bt_init->scan_rsp_data_len] = 0x00;//最åŽä¸€ä¸ªè®¾ç½®ä¸º0
+ app_env.scan_rsp_data_len = g_bt_init->scan_rsp_data_len;
+ } else {
+ uint8_t scan_rsp_data[31] = "\x09\xFF\x60\x52\x57\x2D\x42\x4C\x45\0x00";
+ memcpy(app_env.scan_rsp_data_buf, scan_rsp_data, 10);
+ app_env.scan_rsp_data_len = 10;
+ }
+#endif
+ app_env.pairing_mode = GAPM_PAIRING_DISABLE/*GAPM_PAIRING_LEGACY*/;
+ app_env.iocap = GAP_IO_CAP_NO_INPUT_NO_OUTPUT;
+
+#ifdef N32WB452_BT_API
+ if (g_bt_init) {
+ //地å€ä¸ºåå…进制如12:34:56:AB:CD:EF
+ size = MIN(strlen((const char *)ptmp), sizeof(g_bt_init->device_addr));
+ for (i = 0; i < size;) {
+ if ((g_bt_init->device_addr[i + 0] && (g_bt_init->device_addr[i + 0] >= '0') && (g_bt_init->device_addr[i + 0] <= '9'))) {
+ ch1 = g_bt_init->device_addr[i + 0] - '0';
+ } else if ((g_bt_init->device_addr[i + 0] && (g_bt_init->device_addr[i + 0] >= 'a') && (g_bt_init->device_addr[i + 0] <= 'f'))) {
+ ch1 = g_bt_init->device_addr[i + 0] - 'a' + 10;
+ } else if ((g_bt_init->device_addr[i + 0] && (g_bt_init->device_addr[i + 0] >= 'A') && (g_bt_init->device_addr[i + 0] <= 'F'))) {
+ ch1 = g_bt_init->device_addr[i + 0] - 'A' + 10;
+ } else {
+ ble_log(BLE_DEBUG,"***err1,addr[%d] = %c.\r\n", i + 0, g_bt_init->device_addr[i + 0]);
+ break;
+ }
+
+ if ((g_bt_init->device_addr[i + 1] && (g_bt_init->device_addr[i + 1] >= '0') && (g_bt_init->device_addr[i + 1] <= '9'))) {
+ ch2 = g_bt_init->device_addr[i + 1] - '0';
+ } else if ((g_bt_init->device_addr[i + 1] && (g_bt_init->device_addr[i + 1] >= 'a') && (g_bt_init->device_addr[i + 1] <= 'f'))) {
+ ch2 = g_bt_init->device_addr[i + 1] - 'a' + 10;
+ } else if ((g_bt_init->device_addr[i + 1] && (g_bt_init->device_addr[i + 1] >= 'A') && (g_bt_init->device_addr[i + 1] <= 'F'))) {
+ ch2 = g_bt_init->device_addr[i + 1] - 'A' + 10;
+ } else {
+ ble_log(BLE_DEBUG,"***err2,addr[%d] = %c.\r\n", i + 1, g_bt_init->device_addr[i + 1]);
+ break;
+ }
+
+ if ((i + 2) < strlen((const char *)ptmp)) {
+ if ((g_bt_init->device_addr[i + 2]) && (g_bt_init->device_addr[i + 2] == ':')) {
+ //nothint to do
+ } else {
+ ble_log(BLE_DEBUG,"***err3,addr[%d] = %c.\r\n", i + 2, g_bt_init->device_addr[i + 2]);
+ break;
+ }
+ }
+
+ addr[i / 3] = ch1 * 16 + ch2;
+ ble_log(BLE_DEBUG,"addr[%d]:%0x.\r\n", i / 3, addr[i / 3]);
+ i += 3;
+ }
+ if (i >= size) {
+ app_env.bdaddr.addr[0] = addr[5];
+ app_env.bdaddr.addr[1] = addr[4];
+ app_env.bdaddr.addr[2] = addr[3];
+ app_env.bdaddr.addr[3] = addr[2];
+ app_env.bdaddr.addr[4] = addr[1];
+ app_env.bdaddr.addr[5] = addr[0];
+
+ ble_log(BLE_DEBUG,"addr set ok\r\n");
+ } else {
+ uint8_t bd_addr[6] = "\x21\x22\x22\x22\x22\x12";
+ memcpy(app_env.bdaddr.addr, bd_addr, 6);
+ }
+ } else {
+ uint8_t bd_addr[6] = "\x21\x22\x22\x22\x22\x12";
+ memcpy(app_env.bdaddr.addr, bd_addr, 6);
+ }
+#else
+ uint8_t bd_addr[6] = "\x21\x22\x22\x22\x22\x12";
+ memcpy(app_env.bdaddr.addr, bd_addr, 6);
+#endif
+
+#ifdef BLE_OTA_WRITE_CHAR_EN
+ //在广æ’ä¸å¢žåŠ manufactureæ•°æ®
+ app_env.adv_data_buf[app_env.adv_data_len++] = 3+sizeof(app_env.bdaddr.addr); // device name tag
+ app_env.adv_data_buf[app_env.adv_data_len++] = 0xff; // device name tag
+ app_env.adv_data_buf[app_env.adv_data_len++] = 0x56; // device name tag
+ app_env.adv_data_buf[app_env.adv_data_len++] = 0x00; // device name tag
+ memcpy(&app_env.adv_data_buf[app_env.adv_data_len], app_env.bdaddr.addr, sizeof(app_env.bdaddr.addr));
+ app_env.adv_data_len += sizeof(app_env.bdaddr.addr);
+
+ //在广æ’ä¸å¢žåŠ æœåŠ¡IDæ•°æ®
+ uint8_t service_uuid_len = sizeof(g_bt_init->service[0].svc_uuid);
+ app_env.adv_data_buf[app_env.adv_data_len++] = service_uuid_len + 1; // length
+ app_env.adv_data_buf[app_env.adv_data_len++] = 0x03; // service uuid tag
+ memcpy(&app_env.adv_data_buf[app_env.adv_data_len], (uint8_t *)&g_bt_init->service[0].svc_uuid, service_uuid_len);
+ app_env.adv_data_len += service_uuid_len;
+#endif
+
+ app_env.bdaddr_type = 0;
+
+ app_env.batt_lvl = 100; // device battery level
+
+#ifdef N32WB452_BT_API
+ g_bt_start_finished_flag = 1;
+#endif
+}
+
+int32_t send_vendor_array(uint8_t cmd_type, const uint8_t * byte_array, uint16_t size, uint16_t crc)
+{
+ uint8_t recv_event[5];
+ uint8_t length_cmd[6] = { 0x01, 0xBB, 0xF1, 0x02, 0x00, 0x00 };
+ length_cmd[1] = cmd_type;
+ length_cmd[4] = size % 0x100;
+ length_cmd[5] = size / 0x100;
+ int32_t ret;
+ //å¢žåŠ SPIå‘é€å’ŒæŽ¥æ”¶
+ // eif_uart_send_bytes(length_cmd, 6);
+ // eif_uart_recv_bytes(recv_event,5);
+ eif_spi_send_bytes(length_cmd, 6);
+
+ ret = eif_spi_recv_bytes(recv_event,5);
+ if (ret == E_WAIT) {
+ ble_log(BLE_DEBUG,"send_vendor_array-wait1.\r\n");
+ return ret;
+ }
+ else if ((recv_event[0] !=0x04) || (recv_event[4] !=0x00))
+ {
+ ASSERT_ERR(0);
+ ble_log(BLE_DEBUG,"send_vendor_array-errdata1.\r\n");
+ return E_ERRDATA;
+ }
+
+ uint16_t left_data_length = 0;
+ uint8_t data_cmd[256] = { 0x01, 0xBB, 0xF2 };
+ data_cmd[1] = cmd_type;
+ for(int i = 0; i*SINGLE_CMD_SIZE < size; i++ )
+ {
+ left_data_length = size - SINGLE_CMD_SIZE*i;
+ if (left_data_length >= SINGLE_CMD_SIZE)
+ {
+ data_cmd[3] = SINGLE_CMD_SIZE;
+ memcpy(&data_cmd[4], &byte_array[SINGLE_CMD_SIZE*i], SINGLE_CMD_SIZE);
+ //eif_uart_send_bytes(data_cmd, SINGLE_CMD_SIZE+4);
+ eif_spi_send_bytes(data_cmd, SINGLE_CMD_SIZE+4);
+ }
+ else
+ {
+ data_cmd[3] = left_data_length;
+ memcpy(&data_cmd[4], &byte_array[size - left_data_length], left_data_length);
+ // eif_uart_send_bytes(data_cmd, left_data_length+4);
+ eif_spi_send_bytes(data_cmd, left_data_length+4);
+ }
+ // eif_uart_recv_bytes(recv_event, 5);
+ ret = eif_spi_recv_bytes(recv_event, 5);
+ if (ret == E_WAIT) {
+ ble_log(BLE_DEBUG,"send_vendor_array-wait2.\r\n");
+ return ret;
+ }
+ else if ((recv_event[0] !=0x04) || (recv_event[4] !=0x00))
+ {
+ ASSERT_ERR(0);
+ ble_log(BLE_DEBUG,"send_vendor_array-errdata2.\r\n");
+ return E_ERRDATA;
+ }
+ }
+
+ uint8_t crc_cmd[6] = { 0x01, 0xBB, 0xF3, 0x02, 0x00, 0x00 };
+ crc_cmd[1] = cmd_type;
+ crc_cmd[4] = crc % 0x100;
+ crc_cmd[5] = crc / 0x100;
+
+// eif_uart_send_bytes(crc_cmd, 6);
+// eif_uart_recv_bytes(recv_event, 5);
+ eif_spi_send_bytes(crc_cmd, 6);
+ ret = eif_spi_recv_bytes(recv_event, 5);
+ if (ret == E_WAIT) {
+ ble_log(BLE_DEBUG,"send_vendor_array-wait3.\r\n");
+ return ret;
+ }
+ else if (recv_event[0] !=0x04 || recv_event[4] !=0x00)
+ {
+ ASSERT_ERR(0);
+ ble_log(BLE_DEBUG,"send_vendor_array-errdata3.\r\n");
+ return E_ERRDATA;
+ }
+
+ return E_OK;
+}
+
+
+
+int32_t send_vendor_bypass_command()
+{
+ int32_t ret;
+ uint8_t passby[6] = { 0x01, 0xEE, 0xf1, 0x02, 0x00, 0x00 };
+ //eif_uart_send_bytes(passby, 6);
+ eif_spi_send_bytes(passby, 6);
+
+ uint8_t recv_event[5];
+ // eif_uart_recv_bytes(recv_event, 5);
+ ret = eif_spi_recv_bytes(recv_event,5);
+ if (ret == E_WAIT) {
+ ble_log(BLE_DEBUG,"send_vendor_bypass_command-wait1.\r\n");
+ return ret;
+ }
+ else if (recv_event[0] !=0x04 || recv_event[4] !=0x00)
+ {
+ ASSERT_ERR(0);
+ ble_log(BLE_DEBUG,"send_vendor_bypass_command-errdata1.\r\n");
+ return E_ERRDATA;
+ }
+
+ return E_OK;
+}
+
+
+
+
+void eif_reset_ble_core(void)
+{
+ eif_delay_ms(20);
+ eif_pull_down_reset_io();
+ //eif_delay_ms(20);
+ eif_delay_ms(50);
+ eif_pull_up_reset_io();
+ //eif_delay_ms(10);
+ eif_delay_ms(50);
+}
+
+
+///Z32HUB system init and timer driver
+static const struct interface_sys_tag interface_sys_api =
+{
+ //timer handle
+ eif_set_timeout,
+ eif_get_time,
+ eif_enable_timer,
+
+ //flash handle
+ eif_flash_init,
+ eif_flash_erase,
+ eif_flash_write,
+ eif_flash_read,
+
+ //init bt feature
+ bt_features_init,
+};
+
+struct interface_sys_tag interface_sys;
+
+
+int32_t ble_interface_init(void)
+{
+ interface_sys = interface_sys_api;
+
+ return E_OK;
+}
+
+extern void eif_spi_init(void);
+int32_t ble_hardware_init(void)
+{
+ eif_spi_recv_irq_enable(0);
+ eif_gpio_init(); //io init
+ eif_timer_init();
+ eif_spi_init();
+ eif_reset_ble_core();
+ return E_OK;
+}
+
+int32_t ble_hardware_reinit(void)
+{
+ ble_interface_init();
+ eif_gpio_ReInit();
+ eif_spi_init();
+ eif_timer_init();
+ return E_OK;
+}
+
+
+int32_t ble_init_check(void)
+{
+ uint8_t length_cmd[6] = { 0x01, 0xBB, 0xF1, 0x02, 0x00, 0x00 };
+ length_cmd[1] = RAMCODE_CMD;
+ length_cmd[4] = CopyArrayLength % 0x100;
+ length_cmd[5] = CopyArrayLength / 0x100;
+ volatile uint32_t i;
+ uint32_t tmp;
+
+ while (1) {
+ //delay
+ eif_delay_ms(100);
+
+ eif_spi_send_bytes(length_cmd, 6);
+
+ for (i = 0; i < 30000; i++) {
+ if (eif_spi_ack_event_check() == E_OK) {
+ break;
+ }
+
+ if ((i > 0) && ((i % 10000) == 0)) {
+ tmp = 100 + i / 10;
+ ble_log(BLE_DEBUG,"reset continue[%d],dly-time[%d].\r\n", i, tmp);
+ eif_reset_ble_core();
+ eif_delay_ms(tmp);
+ eif_spi_send_bytes(length_cmd, 6);
+ }
+ }
+
+ if (i < 10000) {
+ ble_log(BLE_DEBUG,"ble_init_check-ok[%d].\r\n", i);
+ break;
+ } else {
+ ble_log(BLE_DEBUG,"eif_reset_ble_core-again.\r\n");
+ eif_reset_ble_core();
+ }
+ }
+
+ return E_OK;
+ }
+
+
+int32_t ble_initdata_down(void)
+{
+ send_vendor_array(RAMCODE_CMD, CopyArray, CopyArrayLength, CopyCrcValue);
+ send_vendor_bypass_command();
+ send_vendor_array(RAMCODE_CMD, RamcodeArray, RamcodeArrayLength, RamcodeCrcValue);
+ send_vendor_array(PATCH_CMD, PatchArray, PatchArrayLength, PatchCrcValue);
+ send_vendor_array(NVDS_CMD, NvdsArray, NvdsArrayLength, NvdsCrcValue);
+ send_vendor_bypass_command();
+ return E_OK;
+}
+
+
+int32_t ble_host_init(void)
+{
+ //eif_uart_init(500000);
+ //eif_uart_recv_irq_enable(1);
+ eif_spi_recv_irq_enable(1);
+ BT_init();
+ appm_init();
+
+ return E_OK;
+}
+
+void ble_system_Init(void)
+{
+ ble_interface_init();
+ ble_hardware_init();
+ ble_initdata_down();
+ ble_host_init();
+}
+
+
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_debug.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_debug.h
new file mode 100644
index 0000000000..db6044cbf1
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_debug.h
@@ -0,0 +1,11 @@
+#ifndef _EIF_DEBUG_H_
+#define _EIF_DEBUG_H_
+
+#include "stdint.h"
+#include "ble_arch.h"
+#include "rwip_config.h"
+
+
+#endif //_EIF_DEBUG_H_
+
+
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_flash.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_flash.h
new file mode 100644
index 0000000000..25ebc188f0
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_flash.h
@@ -0,0 +1,117 @@
+/**
+ ****************************************************************************************
+ *
+ * @file flash.h
+ *
+ * @brief Flash driver interface
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef FLASH_H_
+#define FLASH_H_
+
+#include // standard integer functions
+
+/**
+ ****************************************************************************************
+ * @addtogroup FLASH
+ * @ingroup DRIVERS
+ *
+ * @brief Flash memory driver
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief Initialize flash driver.
+ ****************************************************************************************
+ */
+void eif_flash_init(void);
+
+/**
+ ****************************************************************************************
+ * @brief Identify the flash device.
+ *
+ * This function is used to read the flash device ID.
+ *
+ * Note: callback parameter is not used
+ *
+ * @param[out] id Pointer to id location
+ * @param[in] callback Callback for end of identification
+ * @return status 0 if operation can start successfully
+ ****************************************************************************************
+ */
+uint8_t eif_flash_identify(uint8_t* id);
+
+/**
+ ****************************************************************************************
+ * @brief Erase a flash section.
+ *
+ * This function is used to erase a part of the flash memory.
+ *
+ * Note: callback parameter is not used
+ *
+ * @param[in] flash_type Flash type
+ * @param[in] offset Starting offset from the beginning of the flash device
+ * @param[in] size Size of the portion of flash to erase
+ * @param[in] callback Callback for end of erase
+ * @return status 0 if operation can start successfully
+ ****************************************************************************************
+ */
+uint8_t eif_flash_erase(uint32_t offset, uint32_t size);
+
+/**
+ ****************************************************************************************
+ * @brief Write a flash section.
+ *
+ * This function is used to write a part of the flash memory.
+ *
+ * Note: callback parameter is not used
+ *
+ * @param[in] offset Starting offset from the beginning of the flash device
+ * @param[in] length Size of the portion of flash to write
+ * @param[in] buffer Pointer on data to write
+ * @return status 0 if operation can start successfully
+ ****************************************************************************************
+ */
+uint8_t eif_flash_write( uint32_t offset, uint32_t length, uint8_t *buffer);
+
+/**
+ ****************************************************************************************
+ * @brief Read a flash section.
+ *
+ * This function is used to read a part of the flash memory.
+ *
+ * Note: callback parameter is not used
+ *
+ * @param[in] offset Starting offset from the beginning of the flash device
+ * @param[in] length Size of the portion of flash to read
+ * @param[out] buffer Pointer on data to read
+ * @return status 0 if operation can start successfully
+ ****************************************************************************************
+ */
+uint8_t eif_flash_read(uint32_t offset, uint32_t length, uint8_t *buffer);
+
+
+/// @} FLASH
+
+#endif // FLASH_H_
+
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_iom.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_iom.h
new file mode 100644
index 0000000000..c25059dd90
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_iom.h
@@ -0,0 +1,33 @@
+#include "stdbool.h"
+#include "stdint.h"
+//#include "main.h"
+
+
+#ifndef __EIF_IOM_H__
+#define __EIF_IOM_H__
+
+void eif_pull_up_wakeup_io(void);
+
+void eif_pull_down_wakeup_io(void);
+
+void eif_pull_up_reset_io(void);
+
+void eif_pull_down_reset_io(void);
+
+uint8_t eif_get_status_io_value(void);
+
+void eif_gpio_init(void);
+
+void eif_gpio_DeInit(void);
+
+void eif_gpio_ReInit(void);
+
+void EXTI_NZ8801_STAIRQ_Config(void);
+
+void EXTI_NZ8801_STAIRQ_Default(void);
+
+#endif //__EIF_IOM_H__
+
+
+
+
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_spi.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_spi.h
new file mode 100644
index 0000000000..d47a7dd559
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_spi.h
@@ -0,0 +1,75 @@
+/*****************************************************************************
+* Nations Microcontroller Software Support
+* ----------------------------------------------------------------------------
+* Copyright (c) 2017, Nations Corporation
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* - Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the disclaimer below.
+*
+* Nations's name may not be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ****************************************************************************/
+/*****************************************************************************
+* 文件å：Spi.h
+* 功能æ述：
+* 版本：V 1.0.0
+* 作者：
+* 日期：
+*****************************************************************************/
+
+#ifndef __SPI_H__
+#define __SPI_H__
+#include "stdint.h"
+
+//------------------------------------------------------------------
+// Headers
+//------------------------------------------------------------------
+
+
+//------------------------------------------------------------------
+// Definitions
+//------------------------------------------------------------------
+
+#ifdef _SPI_C
+void eif_spi_flow_on(void);
+bool eif_spi_flow_off(void);
+void eif_spi_read(uint8_t *bufptr, uint32_t size, void (*callback) (void*, uint8_t), void* dummy);
+void eif_spi_write(uint8_t *bufptr, uint32_t size, void (*callback) (void*, uint8_t), void* dummy);
+void eif_spi_recv_bytes(uint8_t *data ,uint16_t length);
+int32_t eif_spi_ack_event_check(void);
+void eif_spi_send_bytes(uint8_t *src , uint16_t length);
+void eif_spi_init(void);
+void eif_spi_recv_irq_handler(void);
+void eif_spi_recv_irq_enable(uint8_t enable);
+
+#else
+extern void eif_spi_flow_on(void);
+extern bool eif_spi_flow_off(void);
+extern void eif_spi_read(uint8_t *bufptr, uint32_t size, void (*callback) (void*, uint8_t), void* dummy);
+extern void eif_spi_write(uint8_t *bufptr, uint32_t size, void (*callback) (void*, uint8_t), void* dummy);
+extern int32_t eif_spi_recv_bytes(uint8_t *data ,uint16_t length);
+extern int32_t eif_spi_ack_event_check(void);
+extern void eif_spi_send_bytes(uint8_t *src , uint16_t length);
+extern void eif_spi_init(void);
+extern void eif_spi_recv_irq_handler(void);
+extern void eif_spi_recv_irq_enable(uint8_t enable);
+#endif
+
+#endif /*__SPIM0DRV_H__*/
+
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_timer.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_timer.h
new file mode 100644
index 0000000000..6806f628c0
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_timer.h
@@ -0,0 +1,19 @@
+#include "stdbool.h"
+#include "stdint.h"
+
+#ifndef __EIF_TIMER_H_
+#define __EIF_TIMER_H_
+
+void eif_timer_isr(void);
+void eif_timer_init(void);
+
+void eif_set_timeout(uint32_t to);
+
+uint32_t eif_get_time(void);
+
+void eif_enable_timer(bool enable);
+
+
+
+#endif //__EIF_TIMER_H_
+
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_uart.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_uart.h
new file mode 100644
index 0000000000..4dc396a2c4
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_uart.h
@@ -0,0 +1,18 @@
+#include "stdbool.h"
+#include "stdint.h"
+
+#ifndef _UART_EIF_H_
+#define _UART_EIF_H_
+
+void eif_uart_read(uint8_t *bufptr, uint32_t size, void (*callback) (void*, uint8_t), void* dummy);
+void eif_uart_write(uint8_t *bufptr, uint32_t size, void (*callback) (void*, uint8_t), void* dummy);
+void eif_uart_flow_on(void);
+bool eif_uart_flow_off(void);
+
+void eif_uart_recv_bytes(uint8_t *data ,uint16_t len);
+void eif_uart_send_bytes(uint8_t *src , uint16_t );
+void eif_uart_recv_irq_handler(void);
+void eif_uart_recv_irq_enable(uint8_t enable);
+void eif_uart_init(uint32_t bps);
+
+#endif //_UART_EIF_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Interface.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Interface.h
new file mode 100644
index 0000000000..432f27fe9f
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Interface.h
@@ -0,0 +1,63 @@
+#ifndef _INTERFACE_H_
+#define _INTERFACE_H_
+
+#include "ble_arch.h"
+#include "Eif_debug.h"
+#include
+
+#define BLEINFO_ADDR 0X801C800
+///Base address of Flash on system bus
+#define FLASH_BASE_ADDR (BLEINFO_ADDR)
+#define FLASH_BLE_SIZE (0x0400)
+
+
+const struct rwip_eif_api *rwip_eif_get(uint8_t );
+void eif_delay_us(uint32_t);
+void eif_delay_ms(uint32_t);
+
+
+void ble_system_Init(void);
+bool wait_for_status_enable(void);
+
+
+enum read_state
+{
+ READ_STATE_RX_START,
+ READ_STATE_RX_HDR,
+ READ_STATE_RX_PAYL,
+ READ_STATE_RX_OUT_OF_SYNC
+};
+
+extern uint8_t read_state_flag;
+
+struct interface_sys_tag
+{
+ //timer
+ void (*set_timesout)(uint32_t to);
+ uint32_t (*get_time)(void);
+ void (*enable_timer)(bool enable);
+
+ ///flash
+ void (*flash_init)(void);
+ uint8_t (*flash_erase)( uint32_t offset, uint32_t size);
+ uint8_t (*flash_write)(uint32_t offset, uint32_t length, uint8_t *buffer);
+ uint8_t (*falsh_read)( uint32_t offset, uint32_t length, uint8_t *buffer);
+
+ ///feature init
+ void (*user_feature_init)(void);
+};
+extern struct interface_sys_tag interface_sys;
+
+
+
+void SetIPR(uint8_t num,uint8_t pri);
+
+int32_t ble_interface_init(void);
+int32_t ble_hardware_init(void);
+
+int32_t ble_initdata_down(void);
+int32_t ble_host_init(void);
+int32_t ble_hardware_reinit(void);
+
+#endif // _INTERFACE_H_
+
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Ramcode.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Ramcode.h
new file mode 100644
index 0000000000..497a647080
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Ramcode.h
@@ -0,0 +1,429 @@
+//2021.02.08
+//V1.3.2
+#define CopyArrayLength 0x0a52
+#define CopyCrcValue 0x7257
+const unsigned char CopyArray[0x0a52] ={
+0x00,0x11,0x6e,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x81,0x01,0xc3,0x01,
+0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xff,0xff,0xff,0xff,0x70,0xb5,0x00,0x20,0x0c,0x49,0x49,0x88,
+0x0c,0x4a,0x8b,0x18,0x1a,0x88,0x0c,0x49,0x9b,0x1c,0x00,0x24,0x13,0x25,0x2d,0x02,
+0x0c,0x54,0x40,0x1c,0xa8,0x42,0xfb,0xdb,0x00,0x20,0x00,0x2a,0x04,0xdd,0x1c,0x5c,
+0x0c,0x54,0x40,0x1c,0x90,0x42,0xfa,0xdb,0x04,0x48,0x80,0x47,0x00,0x20,0x70,0xbd,
+0x00,0x48,0x00,0x20,0x02,0x48,0x00,0x20,0x00,0x35,0x00,0x20,0x0b,0x34,0x01,0x00,
+0xe0,0x09,0x1f,0xb5,0x00,0x24,0x00,0x98,0x1d,0x28,0x43,0xd2,0x01,0x00,0x79,0x44,
+0x09,0x79,0x49,0x18,0x8f,0x44,0x0e,0x13,0x40,0x1a,0x25,0x40,0x40,0x40,0x40,0x40,
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+0x33,0x78,0x55,0x2b,0x02,0xd0,0x66,0x2b,0x19,0xd0,0x24,0xe0,0x49,0x4b,0xde,0x68,
+0x2e,0x43,0xde,0x60,0x1f,0x68,0x47,0x4e,0x37,0x77,0x5f,0x68,0x77,0x77,0xde,0x68,
+0xae,0x43,0xde,0x60,0xc3,0x69,0x13,0x43,0xc3,0x61,0x08,0x6a,0x40,0x08,0x40,0x00,
+0x08,0x62,0x60,0x68,0x01,0x21,0x49,0x02,0x88,0x43,0x60,0x60,0x0b,0xe0,0xc3,0x69,
+0x93,0x43,0xc3,0x61,0x0a,0x6a,0x04,0x20,0x82,0x43,0x0a,0x62,0x60,0x68,0x01,0x21,
+0xc9,0x02,0x88,0x43,0x60,0x60,0x60,0x68,0x38,0x49,0xa8,0x43,0x09,0x78,0xc9,0x07,
+0x09,0x0e,0x08,0x43,0x60,0x60,0x35,0x48,0x80,0x47,0x01,0x21,0x60,0x68,0x89,0x04,
+0x08,0x43,0x60,0x60,0x33,0x48,0x80,0x47,0x33,0x48,0x81,0x68,0xdf,0x22,0x11,0x40,
+0x81,0x60,0x31,0x48,0x00,0x78,0xaa,0x28,0x1c,0xd1,0x30,0x4d,0x28,0x8b,0x40,0x1c,
+0x80,0xb2,0x28,0x83,0x2f,0x49,0x09,0x68,0x88,0x42,0x13,0xd9,0xa0,0x68,0x80,0x07,
+0x10,0xd1,0x28,0x78,0x01,0x28,0x0d,0xd1,0x2b,0x49,0x00,0x20,0x88,0x47,0x80,0xb2,
+0x2a,0x49,0x2a,0x4a,0x41,0x18,0x91,0x42,0x01,0xd2,0x29,0x49,0x08,0x60,0x00,0x20,
+0x28,0x83,0x28,0x70,0xa1,0x20,0xc0,0x05,0x01,0x6b,0x02,0x22,0x91,0x43,0x11,0x43,
+0x01,0x63,0x01,0x21,0x02,0x6b,0x8a,0x43,0x0a,0x43,0x02,0x63,0x01,0x6b,0x04,0x26,
+0xb1,0x43,0x31,0x43,0x01,0x63,0x1f,0x4d,0x68,0x68,0x1f,0x4c,0x80,0x00,0x04,0xd5,
+0x08,0x20,0xa0,0x47,0x68,0x68,0x80,0x00,0xfa,0xd4,0x1c,0x4d,0x0f,0x20,0x68,0x60,
+0x01,0x20,0xa0,0x47,0x07,0x20,0x68,0x60,0x04,0x20,0xa0,0x47,0x06,0x20,0x68,0x60,
+0x8b,0x21,0x17,0x48,0xc9,0x05,0x08,0x60,0x17,0x48,0x01,0x69,0x31,0x43,0x01,0x61,
+0x30,0xbf,0xf8,0xbd,0x00,0x00,0x39,0x38,0x00,0x00,0x64,0x60,0x00,0x20,0x40,0x00,
+0x80,0x44,0x00,0x00,0x40,0x45,0xe0,0x7f,0x00,0x20,0x3a,0x60,0x00,0x20,0x19,0x40,
+0x01,0x00,0x95,0x9c,0x00,0x00,0x40,0x00,0x00,0x43,0x2c,0x60,0x00,0x20,0xf8,0x67,
+0x00,0x20,0x58,0x60,0x00,0x20,0xd5,0x3a,0x00,0x00,0x9f,0x92,0xff,0xff,0x3f,0x1f,
+0x00,0x00,0x54,0x60,0x00,0x20,0x80,0x00,0x80,0x45,0xa5,0x3c,0x00,0x00,0x40,0x00,
+0x80,0x45,0x26,0x03,0x00,0x00,0x00,0xed,0x00,0xe0,0x10,0xb5,0x0f,0x48,0x00,0x78,
+0xaa,0x28,0x12,0xd1,0x0f,0x48,0x0d,0x4c,0x00,0x68,0x21,0x8b,0x40,0x1e,0x81,0x42,
+0x0b,0xd9,0x43,0x20,0x00,0x06,0x80,0x68,0x80,0x07,0x06,0xd1,0x20,0x78,0x00,0x28,
+0x03,0xd1,0x00,0xf0,0x18,0xf9,0x01,0x20,0x20,0x70,0x06,0x49,0x08,0x69,0xfb,0x22,
+0x10,0x40,0x08,0x61,0x30,0xbf,0x10,0xbd,0x00,0x00,0x2c,0x60,0x00,0x20,0xf8,0x67,
+0x00,0x20,0x58,0x60,0x00,0x20,0x00,0xed,0x00,0xe0,0xf8,0xb5,0x6f,0x4f,0x0f,0x20,
+0x78,0x60,0x8b,0x24,0xe4,0x05,0x20,0x68,0x01,0x21,0x49,0x02,0x88,0x43,0x20,0x60,
+0x6b,0x48,0x80,0x47,0x01,0x20,0x80,0xf3,0x10,0x88,0x78,0x6b,0x00,0x06,0x00,0x0e,
+0x05,0xd0,0xff,0xf7,0x8c,0xfc,0x66,0x48,0x80,0x47,0xff,0xf7,0x8e,0xfc,0x65,0x4d,
+0xe8,0x68,0x80,0x06,0x03,0xd5,0xa8,0x68,0x20,0x21,0x08,0x43,0xa8,0x60,0x87,0x20,
+0xc0,0x05,0x81,0x68,0xc9,0x07,0xfc,0xd0,0x43,0x26,0x36,0x06,0x70,0x68,0x01,0x21,
+0x89,0x04,0x88,0x43,0x70,0x60,0x0d,0x20,0x78,0x60,0xff,0xf7,0x7c,0xfc,0x5a,0x49,
+0x80,0x00,0x06,0xd4,0x20,0x68,0x08,0x22,0x10,0x43,0x20,0x60,0x01,0x20,0x88,0x47,
+0x01,0xe0,0x01,0x20,0x88,0x47,0x55,0x48,0x80,0x47,0x55,0x48,0x80,0x24,0x00,0x78,
+0x55,0x28,0x0b,0xd1,0x54,0x48,0xc1,0x68,0x21,0x43,0xc1,0x60,0x53,0x49,0x0a,0x7f,
+0x02,0x60,0x49,0x7f,0x41,0x60,0xc1,0x68,0xa1,0x43,0xc1,0x60,0x50,0x4f,0x14,0x20,
+0xb8,0x47,0x4f,0x48,0x80,0x47,0x89,0x20,0xc0,0x05,0x01,0x6a,0x02,0x22,0x91,0x43,
+0x01,0x62,0x71,0x68,0x80,0x22,0x11,0x43,0x71,0x60,0x71,0x68,0x52,0x01,0x11,0x43,
+0x71,0x60,0x71,0x68,0x52,0x01,0x11,0x43,0x71,0x60,0x46,0x49,0x0a,0x69,0xa3,0x23,
+0x1a,0x43,0x0a,0x61,0x0a,0x68,0x03,0x23,0x5b,0x05,0x9a,0x43,0x0a,0x60,0x31,0x6a,
+0x49,0x09,0x49,0x01,0x1e,0x31,0x31,0x62,0x40,0x49,0x8b,0x68,0x40,0x22,0x93,0x43,
+0x8b,0x60,0xc3,0x6b,0x93,0x43,0xc3,0x63,0x4b,0x69,0x93,0x43,0x4b,0x61,0x4a,0x68,
+0x52,0x08,0x52,0x00,0x4a,0x60,0x82,0x6b,0x52,0x08,0x52,0x00,0x82,0x63,0x08,0x69,
+0x40,0x08,0x40,0x00,0x08,0x61,0x35,0x4c,0x20,0x68,0x1c,0x21,0x88,0x43,0x10,0x30,
+0x20,0x60,0x20,0x68,0x01,0x21,0x08,0x43,0x20,0x60,0x01,0x20,0xb8,0x47,0xa0,0x68,
+0x00,0x28,0xfc,0xd0,0x2f,0x48,0x80,0x47,0x2f,0x49,0x88,0x86,0x20,0x68,0x40,0x08,
+0x40,0x00,0x20,0x60,0x0a,0x20,0xb8,0x47,0x20,0x68,0x1c,0x21,0x88,0x43,0x08,0x30,
+0x20,0x60,0x20,0x68,0x01,0x21,0x08,0x43,0x20,0x60,0x01,0x20,0xb8,0x47,0xa0,0x68,
+0x00,0x28,0xfc,0xd0,0x0a,0x20,0xb8,0x47,0x22,0x48,0x80,0x47,0x23,0x49,0x48,0x63,
+0x20,0x68,0x40,0x08,0x40,0x00,0x20,0x60,0x11,0x48,0x80,0x47,0x71,0x68,0x1f,0x48,
+0x80,0x24,0x00,0x78,0xa1,0x43,0xc0,0x07,0xc0,0x0f,0xc2,0x01,0x11,0x43,0x71,0x60,
+0x71,0x68,0x62,0x01,0x91,0x43,0x02,0x03,0x11,0x43,0x71,0x60,0x71,0x68,0xa2,0x02,
+0x91,0x43,0x40,0x04,0x01,0x43,0x71,0x60,0x00,0x20,0x80,0xf3,0x10,0x88,0x14,0x48,
+0x80,0x47,0x28,0x69,0xa0,0x43,0x28,0x61,0xf8,0xbd,0x40,0x00,0x80,0x45,0xf1,0x3b,
+0x01,0x00,0x39,0x2a,0x00,0x00,0x40,0x00,0x00,0x43,0x59,0x44,0x01,0x00,0xc9,0x34,
+0x01,0x00,0x64,0x60,0x00,0x20,0x00,0x00,0x40,0x45,0xe0,0x7f,0x00,0x20,0xa5,0x3c,
+0x00,0x00,0xa9,0x4d,0x01,0x00,0x00,0x00,0xc0,0x43,0x40,0x00,0x80,0x44,0x00,0x00,
+0x40,0x51,0x69,0x22,0x00,0x00,0xf8,0x67,0x00,0x20,0xc0,0x7f,0x00,0x20,0x3a,0x60,
+0x00,0x20,0x25,0x35,0x01,0x00,0x10,0xb4,0x43,0x22,0x12,0x06,0x51,0x68,0x01,0x24,
+0xe4,0x03,0x21,0x43,0x51,0x60,0x0c,0x4b,0x19,0x68,0x00,0x28,0x03,0xd0,0x03,0x20,
+0x00,0x06,0x01,0x43,0x04,0xe0,0x01,0x20,0x00,0x06,0x81,0x43,0x40,0x00,0x01,0x43,
+0x19,0x60,0x50,0x68,0x06,0x49,0xa0,0x43,0x09,0x78,0xc9,0x07,0x09,0x0c,0x08,0x43,
+0x50,0x60,0x10,0xbc,0x00,0x20,0x70,0x47,0x00,0x00,0x00,0x00,0x40,0x44,0x3a,0x60,
+0x00,0x20
+};
+
+#define RamcodeArrayLength 0x01dc
+#define RamcodeCrcValue 0xceed
+const unsigned char RamcodeArray[0x01dc] ={
+0x00,0x11,0xda,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x81,0x01,0xc3,0x01,
+0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x1b,0x20,0xa0,0x03,0x1f,0xb5,0x82,0xb0,0x08,0x98,0x00,0x90,
+0x02,0xa8,0x0f,0xc8,0x01,0x4c,0xa0,0x47,0x06,0xb0,0x10,0xbd,0x01,0x35,0x00,0x20,
+0x08,0x98,0x00,0x28,0x01,0xd0,0x01,0x20,0x02,0x90,0x00,0x20,0x60,0x85,0x01,0x48,
+0x00,0x47,0x00,0x00,0x31,0xee,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x10,0x7d,0x08,0x28,0x01,0xd3,0x05,0x20,0x10,0x75,0x02,0x98,0x81,0x79,0x01,0x20,
+0x01,0x43,0x02,0x98,0x81,0x71,0x01,0x48,0x00,0x47,0x00,0x00,0x01,0xf8,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x07,0x48,0x80,0x47,0x02,0x2d,0x05,0xd1,0x06,0x48,0x80,0x47,0x00,0xbf,0x00,0xbf,
+0x05,0x48,0x80,0x47,0x00,0x21,0x03,0x9a,0x04,0x98,0x90,0x47,0x03,0x48,0x00,0x47,
+0x5d,0x4a,0x01,0x00,0xe9,0x4a,0x01,0x00,0x73,0x4a,0x01,0x00,0x53,0x4c,0x01,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x03,0x48,0x01,0x68,0x28,0x22,0x11,0x43,0x50,0x22,0x91,0x43,0x01,0x60,0x70,0x47,
+0x00,0x00,0xc0,0x52,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x03,0x48,0x01,0x68,0x50,0x22,0x11,0x43,0x28,0x22,0x91,0x43,0x01,0x60,0x70,0x47,
+0x00,0x00,0xc0,0x52,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x06,0x48,0x80,0x47,0x02,0x2d,0x03,0xd1,0x05,0x48,0x80,0x47,0x05,0x48,0x80,0x47,
+0x00,0x21,0x03,0x9a,0x04,0x98,0x90,0x47,0x05,0xb0,0xf0,0xbd,0x5d,0x4a,0x01,0x00,
+0xc1,0x4e,0x01,0x00,0x73,0x4a,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x21,0x30,0x46,0xa8,0x47,0x03,0x48,0x01,0x88,0x00,0x29,0x01,0xd1,0x02,0x48,
+0x80,0x47,0xf8,0xbd,0x0a,0x10,0x00,0x20,0x47,0x4e,0x01,0x00
+};
+
+#define PatchArrayLength 0x0c80
+#define PatchCrcValue 0x0277
+const unsigned char PatchArray[0x0c80] ={
+0x00,0x22,0x80,0x0c,0xff,0x7f,0x00,0x00,0xf9,0x4b,0x09,0x00,0x1b,0x54,0x09,0x00,
+0x1d,0x5c,0x09,0x00,0x51,0x64,0x09,0x00,0xb4,0x6b,0x09,0x00,0x19,0x75,0x09,0x00,
+0xdf,0x7b,0x09,0x00,0xfe,0x82,0x09,0x00,0x31,0x8d,0x09,0x00,0x69,0x91,0x09,0x00,
+0x2a,0x9d,0x09,0x00,0xad,0xa0,0x09,0x00,0x4a,0xad,0x09,0x00,0x1d,0xb5,0x09,0x00,
+0x1e,0xbd,0x09,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x04,0x46,0x20,0x46,0x10,0xbd,0x00,0x00,0x5c,0x56,0x01,0x00,
+0x00,0x49,0x08,0x47,0x01,0x4e,0x00,0x20,0xf3,0xf7,0xb0,0xfd,0x7c,0x20,0x00,0x5b,
+0x02,0x90,0x00,0x25,0x00,0x20,0x01,0x90,0x01,0x20,0x80,0xf3,0x10,0x88,0x60,0x6c,
+0x00,0x21,0x81,0xf3,0x10,0x88,0x26,0x46,0x60,0x36,0x00,0x28,0x63,0xd0,0x21,0x46,
+0x44,0x31,0x0a,0x91,0x10,0x88,0x20,0x46,0x44,0x30,0x00,0xf0,0x15,0xf8,0x05,0x46,
+0x20,0x46,0x08,0x30,0x00,0xf0,0x10,0xf8,0x45,0x19,0x20,0x46,0x1c,0x30,0x00,0xf0,
+0x0b,0xf8,0x40,0x19,0xc1,0xb2,0x00,0x29,0x03,0xd0,0x40,0x34,0xa0,0x8f,0xf9,0xf7,
+0x73,0xfd,0x70,0xbd,0x01,0x21,0xe1,0xe7,0x00,0x49,0x08,0x47,0xe9,0x4f,0x00,0x20,
+0x80,0xf3,0x10,0x88,0x01,0x21,0x81,0xf3,0x10,0x88,0xc1,0x68,0x80,0x68,0x8a,0x88,
+0x80,0x88,0x07,0x49,0xc0,0x00,0x41,0x18,0x06,0x48,0xd2,0x00,0x10,0x18,0xc2,0x8c,
+0xd2,0x0b,0xd2,0x03,0x0a,0x43,0xc2,0x84,0x00,0x20,0x80,0xf3,0x10,0x88,0x70,0x47,
+0x66,0x04,0x00,0x00,0x40,0x44,0x80,0x50,0x00,0x49,0x08,0x47,0x55,0x50,0x00,0x20,
+0x11,0x90,0x80,0x8f,0xe3,0x18,0x9b,0xb2,0x93,0x84,0x60,0x30,0x41,0x75,0x18,0x46,
+0x10,0xbc,0x70,0x47,0x00,0x20,0x00,0x20,0x40,0x7d,0x00,0x28,0x00,0xd0,0x01,0x20,
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+0x6f,0x1a,0x97,0x42,0xf9,0xda,0x98,0x42,0x01,0xd9,0x00,0x25,0x34,0xe0,0x04,0x99,
+0x08,0x70,0x81,0x4f,0x81,0x49,0x7e,0x48,0x88,0x47,0x01,0x46,0x00,0x98,0x00,0x28,
+0x12,0xd0,0x00,0x20,0x00,0x90,0xb0,0x7a,0x80,0x07,0x80,0x0f,0x01,0x28,0x09,0xd0,
+0x02,0x20,0x88,0x72,0xf0,0x68,0xc2,0x88,0x02,0x92,0x80,0x88,0x01,0x90,0x09,0xe0,
+0x62,0xe0,0x58,0xe0,0x01,0x20,0xf4,0xe7,0x01,0x20,0x88,0x72,0x02,0x98,0x00,0x19,
+0x80,0xb2,0x02,0x90,0xa5,0x42,0x01,0xdd,0xcc,0x72,0x00,0xe0,0xcd,0x72,0x01,0x98,
+0xc8,0x80,0x02,0x98,0x08,0x81,0x28,0x1b,0x05,0xb2,0x00,0x2d,0x22,0xdc,0x01,0x22,
+0x05,0x9b,0x03,0x98,0xb8,0x47,0x01,0x25,0x00,0x2d,0x20,0xd0,0x68,0x46,0x00,0x7e,
+0x08,0x99,0x09,0x18,0xc9,0xb2,0x08,0x91,0x09,0x99,0x08,0x1a,0x80,0xb2,0x00,0xe0,
+0x35,0xe0,0x09,0x90,0x12,0x98,0xc0,0x69,0x00,0x28,0x1a,0xd0,0x12,0x98,0x00,0x6a,
+0x06,0x60,0x12,0x98,0x06,0x62,0x00,0x20,0x30,0x60,0x08,0x98,0x0a,0x28,0x13,0xd9,
+0x00,0x25,0x24,0xe0,0x00,0x22,0x05,0x9b,0x03,0x98,0xb8,0x47,0xaa,0xe7,0x0d,0x98,
+0x00,0x68,0x00,0x28,0x01,0xd1,0x0d,0x99,0x4e,0x60,0x30,0x60,0x0d,0x98,0x06,0x60,
+0x15,0xe0,0x12,0x98,0xc6,0x61,0xe4,0xe7,0x0d,0x98,0x06,0x68,0x00,0x2e,0x06,0xd0,
+0x0d,0x99,0x30,0x68,0x08,0x60,0x00,0x28,0x01,0xd1,0x0d,0x99,0x48,0x60,0x00,0x2e,
+0x00,0xd0,0x4f,0xe7,0x03,0xe0,0x4a,0x4a,0x0d,0x99,0x0b,0x98,0x90,0x47,0x00,0x2d,
+0x02,0xd0,0x48,0x49,0x0d,0x98,0x88,0x47,0x0b,0x98,0x00,0x68,0x00,0x28,0x03,0xd0,
+0x00,0x20,0x00,0x28,0x02,0xd0,0x4b,0xe0,0x01,0x20,0xfa,0xe7,0x11,0x98,0x80,0x8f,
+0x07,0x28,0x45,0xd2,0x12,0x98,0x80,0x30,0xc0,0x78,0x04,0x28,0x40,0xd1,0x3b,0x49,
+0x37,0x48,0x88,0x47,0x00,0x28,0x3b,0xd0,0x82,0x88,0x00,0x21,0x2b,0x4b,0xd2,0x00,
+0xd2,0x18,0x51,0x85,0x81,0x88,0xc9,0x00,0xc9,0x18,0x8a,0x8d,0x54,0x04,0x64,0x0c,
+0x00,0x22,0x8c,0x85,0x81,0x88,0xc9,0x00,0xc9,0x18,0x0c,0x8d,0xe4,0xb2,0x0c,0x85,
+0x81,0x88,0x01,0x24,0xc9,0x00,0xc9,0x18,0x0d,0x8d,0xad,0x08,0xad,0x00,0x25,0x43,
+0x0d,0x85,0x81,0x88,0xc9,0x00,0xc9,0x18,0xcc,0x8c,0xe4,0x0b,0xe4,0x03,0xcc,0x84,
+0x0b,0x99,0x84,0x88,0x49,0x68,0xe5,0x00,0x1f,0x4c,0x89,0x88,0x2c,0x19,0xc9,0x00,
+0xc9,0x18,0xcb,0x8c,0xdb,0x0b,0xdb,0x03,0x23,0x43,0xcb,0x84,0x0b,0x99,0x09,0x68,
+0x00,0x29,0x0d,0xd0,0x0b,0x99,0x49,0x68,0x08,0x60,0x0b,0x99,0x48,0x60,0x02,0x60,
+0x0b,0x98,0x00,0x68,0x00,0x28,0x06,0xd0,0x00,0x21,0x00,0x29,0x05,0xd0,0x3c,0xe0,
+0x0b,0x99,0x08,0x60,0xf1,0xe7,0x01,0x21,0xf7,0xe7,0x00,0x28,0x0a,0xd0,0x07,0x4a,
+0x81,0x88,0xc9,0x00,0x89,0x18,0xc9,0x8c,0xc9,0x0b,0x00,0x29,0x24,0xd0,0x00,0x68,
+0x00,0x28,0xf5,0xd1,0x00,0x28,0x26,0xd0,0x27,0xe0,0x00,0x00,0x40,0x44,0x80,0x50,
+0x5c,0x61,0x00,0x20,0xdd,0xaf,0x00,0x00,0x1b,0x39,0x00,0x00,0x9d,0x03,0x01,0x00,
+0x00,0x40,0x80,0x50,0x01,0x94,0x00,0x00,0x66,0x04,0x00,0x00,0x6b,0x3a,0x00,0x00,
+0xe0,0x61,0x00,0x20,0xbf,0x3a,0x00,0x00,0x6d,0x00,0x01,0x00,0x49,0x3a,0x00,0x00,
+0x13,0x3a,0x00,0x00,0xb9,0x39,0x00,0x00,0x81,0x88,0xca,0x00,0x07,0x49,0x51,0x18,
+0x89,0xb2,0x0a,0x91,0xd6,0xe7,0x00,0x20,0x0a,0x90,0x0a,0x99,0x0e,0x98,0x5a,0x22,
+0x50,0x43,0x03,0x4a,0x80,0x18,0x81,0x84,0x13,0xb0,0xf0,0xbd,0x66,0x04,0x00,0x00,
+0x80,0x40,0x80,0x50,0xf8,0xb5,0x00,0x24,0x10,0x48,0x00,0x78,0x00,0x28,0x15,0xd1,
+0x0f,0x48,0x80,0x47,0x0f,0x4e,0x0a,0x20,0xb0,0x47,0x37,0x07,0xf8,0x69,0x05,0x05,
+0x2d,0x0d,0x00,0x2d,0x0a,0xd0,0x14,0x20,0xb0,0x47,0xf8,0x69,0x00,0x05,0x00,0x0d,
+0xa8,0x42,0x04,0xd9,0x05,0x46,0x64,0x1c,0x64,0x2c,0xf4,0xd3,0xf8,0xbd,0x03,0x49,
+0x01,0x20,0x08,0x70,0x04,0x49,0x08,0x70,0xf8,0xbd,0x00,0x00,0x01,0x10,0x00,0x20,
+0x5d,0x4a,0x01,0x00,0xa5,0x3c,0x00,0x00,0x00,0x10,0x00,0x20,0x10,0xb5,0x05,0x20,
+0x00,0x07,0xc0,0x69,0x01,0x05,0x0f,0x48,0x00,0x78,0x03,0xd0,0x01,0x28,0x13,0xd0,
+0x02,0x28,0x11,0xd0,0x00,0x28,0x08,0xd0,0x01,0x28,0x06,0xd0,0x02,0x28,0x04,0xd0,
+0x09,0x48,0x80,0x47,0x09,0x49,0x32,0x20,0x88,0x47,0x09,0x49,0x04,0x20,0x88,0x47,
+0x08,0x48,0x80,0x47,0x00,0x20,0x10,0xbd,0x07,0x49,0x04,0x20,0x88,0x47,0x01,0x20,
+0x10,0xbd,0x00,0x00,0x18,0x10,0x00,0x20,0xe9,0x4a,0x01,0x00,0xa5,0x3c,0x00,0x00,
+0x11,0x44,0x01,0x00,0x73,0x4a,0x01,0x00,0x59,0x44,0x01,0x00,0xf0,0xb4,0x00,0x23,
+0x18,0x4c,0xa5,0x6b,0x18,0x49,0x7d,0x22,0x09,0x68,0x12,0x02,0x91,0x42,0x02,0xd3,
+0x8a,0x1a,0x01,0x23,0x00,0xe0,0x52,0x1a,0x06,0x46,0x56,0x43,0xf2,0x13,0x51,0x43,
+0x71,0x1a,0x1e,0x26,0x4e,0x43,0x4f,0x10,0xf6,0x19,0x8f,0x11,0xf6,0x19,0x49,0x12,
+0x71,0x18,0xce,0x13,0x00,0x2b,0x01,0xd0,0x80,0x1a,0x00,0xe0,0x10,0x18,0x42,0x19,
+0x91,0x08,0x8d,0x00,0x52,0x1b,0x00,0x2b,0x04,0xd0,0x43,0x01,0x18,0x1a,0x40,0x18,
+0x80,0x1b,0x03,0xe0,0x43,0x01,0x18,0x1a,0x40,0x18,0x80,0x19,0xa2,0x63,0xf0,0xbc,
+0x70,0x47,0x00,0x00,0x80,0x67,0x00,0x20,0x54,0x60,0x00,0x20,0x10,0xb4,0x00,0x23,
+0x14,0x21,0x02,0x46,0x4a,0x43,0x11,0x49,0x7d,0x24,0x09,0x68,0x24,0x02,0xa1,0x42,
+0x02,0xd9,0x09,0x1b,0x01,0x23,0x00,0xe0,0x61,0x1a,0x48,0x43,0x81,0x00,0x41,0x18,
+0x88,0x0a,0x0c,0x0c,0x00,0x19,0x4c,0x0c,0x00,0x19,0x4c,0x0d,0x00,0x19,0x4c,0x0e,
+0x00,0x19,0xc9,0x0f,0x40,0x18,0xc0,0x08,0x00,0x2b,0x01,0xd0,0x10,0x18,0x01,0xe0,
+0x10,0x1a,0x40,0x1e,0x40,0x1e,0x10,0xbc,0x70,0x47,0x00,0x00,0x54,0x60,0x00,0x20
+};
+
+#define NvdsArrayLength 0x00ba
+#define NvdsCrcValue 0x67f5
+const unsigned char NvdsArray[0x00ba] ={
+0x4e,0x56,0x44,0x53,0x01,0x06,0x06,0xef,0xab,0x26,0x68,0x84,0x66,0x02,0x06,0x0a,
+0x4e,0x5a,0x38,0x38,0x30,0x31,0x56,0x31,0x41,0x00,0x03,0x06,0x01,0x00,0x07,0x06,
+0x02,0xf4,0x01,0x0c,0x06,0x02,0xf4,0x01,0x08,0x06,0x01,0x00,0x09,0x06,0x01,0x00,
+0x0a,0x06,0x04,0x00,0x00,0x00,0x00,0x0b,0x06,0x01,0x96,0x23,0x06,0x01,0x96,0x0d,
+0x06,0x02,0xdc,0x03,0x0e,0x06,0x02,0xdc,0x03,0x0f,0x06,0x02,0x90,0x01,0x10,0x06,
+0x04,0x00,0xc2,0x01,0x00,0x11,0x06,0x01,0x01,0x12,0x06,0x01,0x01,0x13,0x06,0x02,
+0x90,0x02,0x14,0x06,0x02,0x60,0x00,0x15,0x06,0x01,0x08,0x16,0x06,0x01,0x03,0x17,
+0x06,0x01,0x29,0x18,0x06,0x02,0xdc,0x05,0x19,0x06,0x02,0xe2,0x04,0x20,0x06,0x01,
+0x00,0x21,0x06,0x01,0x01,0x22,0x06,0x01,0x00,0x24,0x06,0x04,0x42,0x02,0x60,0x09,
+0x25,0x06,0x01,0x11,0x26,0x06,0x01,0x00,0x27,0x06,0x01,0x03,0x2d,0x06,0x01,0x00,
+0x28,0x06,0x02,0xf6,0x2d,0x29,0x06,0x01,0x08,0x35,0x06,0x01,0x08,0x37,0x06,0x01,
+0xaa,0x05,0x06,0x02,0x34,0x00,0x00,0x00,0x00,0x00
+};
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/ble_monitor.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/ble_monitor.h
new file mode 100644
index 0000000000..a8f7dba25c
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/ble_monitor.h
@@ -0,0 +1,62 @@
+/*****************************************************************************
+* Nations Microcontroller Software Support
+* ----------------------------------------------------------------------------
+* Copyright (c) 2017, Nations Corporation
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* - Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the disclaimer below.
+*
+* Nations's name may not be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ****************************************************************************/
+/*****************************************************************************
+* 文件å：ble_monitor.h
+* 功能æ述：
+* 版本：V 1.0.0
+* 作者：
+* 日期：
+*****************************************************************************/
+
+#ifndef __BLE_MONITOR_H__
+#define __BLE_MONITOR_H__
+
+#include
+#include
+#include
+#include "core_cm4.h"
+
+//------------------------------------------------------------------
+// Headers
+//------------------------------------------------------------------
+
+
+//------------------------------------------------------------------
+// Definitions
+//------------------------------------------------------------------
+extern __IO uint8_t wakeup_flag_5S;
+extern __IO uint8_t stop2_flag;
+extern __IO uint8_t wakeup_flag;
+
+void ble_status_monitor(void);
+void ble_clear_wakeup(void);
+void ble_monitor_callback(void);
+uint8_t ble_monitor_wait(uint32_t timeout);
+
+#endif /*__BLE_MONITOR_H__*/
+
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app.c
new file mode 100644
index 0000000000..a0a892b3f9
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app.c
@@ -0,0 +1,311 @@
+/**
+ ****************************************************************************************
+ *
+ * @file app.c
+ *
+ * @brief Application entry point
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @addtogroup APP
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+
+#include "rwip_config.h" // SW configuration
+#include "stdio.h"
+#if (BLE_APP_PRESENT)
+#include
+
+#include "app_task.h" // Application task Definition
+#include "app.h" // Application Definition
+#include "gap.h" // GAP Definition
+#include "gapm_task.h" // GAP Manager Task API
+#include "gapc_task.h" // GAP Controller Task API
+#include "gapm.h"
+#include "co_bt.h" // Common BT Definition
+#include "co_math.h" // Common Maths Definition
+#include "interface.h"
+#include "gattc_task.h"
+
+#if (BLE_APP_SEC)
+#include "app_sec.h" // Application security Definition
+#endif // (BLE_APP_SEC)
+
+#if (NVDS_SUPPORT)
+#include "nvds.h" // NVDS Definitions
+#endif //(NVDS_SUPPORT)
+
+#if (BLE_APP_USER)
+#include "app_user.h" // Health Thermometer Application Definitions
+#endif
+//#include "BtDrv.h"
+#include "n32wb452_ble_api.h"
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/// Default Device Name if no value can be found in NVDS
+#define APP_DFLT_DEVICE_NAME app_env.dev_name//
+#define APP_DFLT_DEVICE_NAME_LEN (sizeof(APP_DFLT_DEVICE_NAME))
+
+
+#if (BLE_APP_HID)
+// HID Mouse
+#define DEVICE_NAME "Hid Mouse"
+#else
+#define DEVICE_NAME "NZ DEVICE"
+#endif
+
+#define DEVICE_NAME_SIZE sizeof(DEVICE_NAME)
+
+/**
+ * UUID List part of ADV Data
+ * --------------------------------------------------------------------------------------
+ * x03 - Length
+ * x03 - Complete list of 16-bit UUIDs available
+ * x09\x18 - Health Thermometer Service UUID
+ * or
+ * x12\x18 - HID Service UUID
+ * --------------------------------------------------------------------------------------
+ */
+
+#if (BLE_APP_HT)
+#define APP_HT_ADV_DATA_UUID "\x03\x03\x09\x18"
+#define APP_HT_ADV_DATA_UUID_LEN (4)
+#endif //(BLE_APP_HT)
+
+#if (BLE_APP_HID)
+#define APP_HID_ADV_DATA_UUID "\x03\x03\x12\x18"
+#define APP_HID_ADV_DATA_UUID_LEN (4)
+#endif //(BLE_APP_HID)
+
+
+#if (BLE_APP_USER)
+#define APP_USER_ADV_DATA_UUID "\x03\x03\x00\xaa"
+#define APP_USER_ADV_DATA_UUID_LEN (4)
+#endif //(BLE_APP_HT)
+
+
+/*
+ * TYPE DEFINITIONS
+ ****************************************************************************************
+ */
+
+typedef void (*appm_add_svc_func_t)(void);
+
+/*
+ * ENUMERATIONS
+ ****************************************************************************************
+ */
+
+/// List of service to add in the database
+enum appm_svc_list
+{
+
+#if (BLE_APP_BATT)
+ APPM_SVC_BATT,
+#endif //(BLE_APP_BATT)
+
+#if (BLE_APP_USER)
+ APPM_SVC_USER,
+#endif //(BLE_APP_USER)
+ APPM_SVC_LIST_STOP,
+};
+
+/*
+ * LOCAL VARIABLES DEFINITIONS
+ ****************************************************************************************
+ */
+
+/// Application Task Descriptor
+static const struct ke_task_desc TASK_DESC_APP = {NULL, &appm_default_handler,
+ appm_state, APPM_STATE_MAX, APP_IDX_MAX
+};
+
+/// List of functions used to create the database
+static const appm_add_svc_func_t appm_add_svc_func_list[APPM_SVC_LIST_STOP] =
+{
+
+#if (BLE_APP_USER)
+ (appm_add_svc_func_t)app_user_add_users,
+#endif //(BLE_APP_USER)
+
+};
+
+/*
+ * GLOBAL VARIABLE DEFINITIONS
+ ****************************************************************************************
+ */
+
+/// Application Environment Structure
+struct app_env_tag app_env;
+
+/*
+ * FUNCTION DEFINITIONS
+ ****************************************************************************************
+ */
+void app_default_feature_init(void)
+{
+ //wait to fill in the features
+ app_env.max_mtu = 251;
+
+}
+
+void appm_init()
+{
+
+ // Reset the application manager environment
+ memset(&app_env, 0, sizeof(app_env));
+ // Create APP task
+ ke_task_create(TASK_APP, &TASK_DESC_APP);
+ // Initialize Task state
+ ke_state_set(TASK_APP, APPM_INIT);
+
+ app_default_feature_init();
+ interface_sys.user_feature_init();
+
+ // user Module init
+#if (BLE_APP_USER)
+ // Health Thermometer Module
+ app_user_init();
+#endif //(BLE_APP_USER)
+}
+
+bool appm_add_svc(void)
+{
+ // Indicate if more services need to be added in the database
+ bool more_svc = false;
+ // Check if another should be added in the database
+ if (app_env.next_svc != APPM_SVC_LIST_STOP)
+ {
+ // ble_log(BLE_DEBUG,"",app_env.next_svc)
+ ASSERT_INFO(appm_add_svc_func_list[app_env.next_svc] != NULL, app_env.next_svc, 1);
+
+ // Call the function used to add the required service
+ appm_add_svc_func_list[app_env.next_svc]();
+ // Select following service to add
+ app_env.next_svc++;
+ more_svc = true;
+ }
+ return more_svc;
+}
+
+void appm_disconnect(void)
+{
+ struct gapc_disconnect_cmd *cmd = KE_MSG_ALLOC(GAPC_DISCONNECT_CMD,KE_BUILD_ID(TASK_GAPC, app_env.conidx), TASK_APP,gapc_disconnect_cmd);
+ cmd->operation = GAPC_DISCONNECT;
+ cmd->reason = CO_ERROR_REMOTE_USER_TERM_CON;
+ ke_msg_send(cmd); // Send the message
+}
+
+void appm_start_advertising(void)
+{
+ if (ke_state_get(TASK_APP) == APPM_READY)
+ {
+ // Prepare the GAPM_START_ADVERTISE_CMD message
+ struct gapm_start_advertise_cmd *cmd = KE_MSG_ALLOC(GAPM_START_ADVERTISE_CMD,TASK_GAPM, TASK_APP,gapm_start_advertise_cmd);
+ cmd->op.code = app_env.adv_para.adv_type;
+ cmd->op.addr_src = GAPM_STATIC_ADDR; // app_env.adv_para.addr_type_own; //public static addr private static addr
+ cmd->channel_map = app_env.adv_para.channel_map; // BTstack_data.user_config.adv_para.channel_map;//
+ cmd->intv_min = app_env.adv_para.adv_int_min;
+ cmd->intv_max = app_env.adv_para.adv_int_max;
+ cmd->info.host.mode = app_env.adv_para.discover_mode;
+
+ //ASSERT_ERR( app_env.adv_data_len > (GAP_ADV_DATA_LEN-3) );
+
+ memcpy(cmd->info.host.adv_data, app_env.adv_data_buf, app_env.adv_data_len);
+ cmd->info.host.adv_data_len = app_env.adv_data_len;
+
+
+
+ //ASSERT_ERR(app_env.adv_data_len > GAP_SCAN_RSP_DATA_LEN);
+
+ memcpy(cmd->info.host.scan_rsp_data, app_env.scan_rsp_data_buf, app_env.scan_rsp_data_len);
+ cmd->info.host.scan_rsp_data_len = app_env.scan_rsp_data_len;
+
+ // Send the message
+ ke_msg_send(cmd);
+ ke_state_set(TASK_APP, APPM_ADVERTISING);
+ if (g_pcallback) {
+ g_pcallback(BT_EVENT_DISCONNECTD, NULL, 0, 0);
+ }
+ g_connnet_start = 0;
+ }
+
+}
+
+void appm_stop_advertising(void)
+{
+ if (ke_state_get(TASK_APP) == APPM_ADVERTISING)
+ {
+ // Go in ready state
+ ke_state_set(TASK_APP, APPM_READY);
+ // Prepare the GAPM_CANCEL_CMD message
+ struct gapm_cancel_cmd *cmd = KE_MSG_ALLOC(GAPM_CANCEL_CMD,TASK_GAPM, TASK_APP,gapm_cancel_cmd);
+ cmd->operation = GAPM_CANCEL;
+ // Send the message
+ ke_msg_send(cmd);
+ }
+}
+
+void appm_set_mtu(void)
+{
+ // Prepare the GAPC_PARAM_UPDATE_CMD message
+ struct gattc_exc_mtu_cmd *cmd = KE_MSG_ALLOC(GATTC_EXC_MTU_CMD,KE_BUILD_ID(TASK_GATTC, app_env.conidx), TASK_APP,gattc_exc_mtu_cmd);
+ cmd->operation = GATTC_MTU_EXCH;
+ cmd->seq_num = 0;
+ // Send the message
+ ke_msg_send(cmd);
+}
+
+void BT_set_mtu(uint16_t mtu)
+{
+ app_env.max_mtu = mtu;
+
+ gapm_set_max_mtu(mtu);
+
+ appm_set_mtu();
+}
+
+void appm_update_param(struct gapc_conn_param *conn_param)
+{
+ // Prepare the GAPC_PARAM_UPDATE_CMD message
+
+ struct gapc_param_update_cmd *cmd = KE_MSG_ALLOC(GAPC_PARAM_UPDATE_CMD,KE_BUILD_ID(TASK_GAPC, app_env.conidx), TASK_APP,gapc_param_update_cmd);
+ cmd->operation = GAPC_UPDATE_PARAMS;
+ cmd->intv_min = conn_param->intv_min;
+ cmd->intv_max = conn_param->intv_max;
+ cmd->latency = conn_param->latency;
+ cmd->time_out = conn_param->time_out;
+ // not used by a slave device
+ cmd->ce_len_min = 0xFFFF;
+ cmd->ce_len_max = 0xFFFF;
+ // Send the message
+ ke_msg_send(cmd);
+}
+
+uint8_t appm_get_dev_name(uint8_t *name)
+{
+ // copy name to provided pointer
+ memcpy(name, app_env.dev_name, app_env.dev_name_len);
+ // return name length
+ return app_env.dev_name_len;
+}
+
+#endif //(BLE_APP_PRESENT)
+
+
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app_batt.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app_batt.c
new file mode 100644
index 0000000000..5b3a6796c5
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app_batt.c
@@ -0,0 +1,180 @@
+/*****************************************************************************
+* Nations Microcontroller Software Support
+* ----------------------------------------------------------------------------
+* Copyright (c) 2017, Nations Corporation
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* - Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the disclaimer below.
+*
+* Nations's name may not be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ****************************************************************************/
+/*****************************************************************************
+* 文件å :app_batt.c
+* 功能æè¿°:
+* 版本:V 1.0.0
+* 作者:
+* 日期:
+* ****************************************************************************/
+
+
+#include "rwip_config.h" // SW configuration
+
+#if (BLE_APP_BATT)
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+
+#include "app_batt.h" // Battery Application Module Definitions
+#include "app.h" // Application Definitions
+#include "app_task.h" // application task definitions
+#include "bass_task.h" // health thermometer functions
+#include "co_bt.h"
+#include "prf_types.h" // Profile common types definition
+#include "ble_arch.h" // Platform Definitions
+#include "prf.h"
+#include "bass.h"
+#include "string.h"
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/*
+ * GLOBAL VARIABLE DEFINITIONS
+ ****************************************************************************************
+ */
+
+/// Battery Application Module Environment Structure
+struct app_batt_env_tag app_batt_env;
+
+/*
+ * GLOBAL FUNCTION DEFINITIONS
+ ****************************************************************************************
+ */
+
+void app_batt_init(void)
+{
+ // Reset the environment
+ memset(&app_batt_env, 0, sizeof(struct app_batt_env_tag));
+ // Initial battery level: 100
+ app_batt_env.batt_lvl = app_env.batt_lvl; // set battery init level;
+}
+
+void app_batt_add_bas(void)
+{
+ struct bass_db_cfg* db_cfg;
+ // Allocate the BASS_CREATE_DB_REQ
+ struct gapm_profile_task_add_cmd *req = KE_MSG_ALLOC_DYN(GAPM_PROFILE_TASK_ADD_CMD,TASK_GAPM, TASK_APP,gapm_profile_task_add_cmd, sizeof(struct bass_db_cfg));
+ // Fill message
+ req->operation = GAPM_PROFILE_TASK_ADD;
+ req->sec_lvl = PERM(SVC_AUTH, DISABLE); //设置æƒé™
+ req->prf_task_id = TASK_ID_BASS;
+ req->app_task = TASK_APP;
+ req->start_hdl = 0;
+ // Set parameters
+ db_cfg = (struct bass_db_cfg* ) req->param;
+ // Add a BAS instance
+ db_cfg->bas_nb = 1;
+ // Sending of notifications is supported
+ db_cfg->features[0] = BAS_BATT_LVL_NTF_SUP;
+ // Send the message
+ ke_msg_send(req);
+}
+
+
+
+void app_batt_enable_prf(uint8_t conidx)
+{
+ app_batt_env.conidx = conidx;
+ // Allocate the message
+ struct bass_enable_req * req = KE_MSG_ALLOC(BASS_ENABLE_REQ,prf_get_task_from_id(TASK_ID_BASS),TASK_APP,bass_enable_req);
+ // Fill in the parameter structure
+ req->conidx = conidx;
+ // NTF initial status - Disabled
+ req->ntf_cfg = PRF_CLI_STOP_NTFIND;
+ req->old_batt_lvl[0] = app_batt_env.batt_lvl; // init battery level
+ // Send the message
+ ke_msg_send(req);
+}
+
+
+// notify battery level
+void app_batt_send_lvl(uint8_t batt_lvl)
+{
+ ASSERT_ERR(batt_lvl <= BAS_BATTERY_LVL_MAX);
+ // Allocate the message
+ struct bass_batt_level_upd_req * req = KE_MSG_ALLOC(BASS_BATT_LEVEL_UPD_REQ, prf_get_task_from_id(TASK_ID_BASS),TASK_APP,bass_batt_level_upd_req);
+ // Fill in the parameter structure
+ req->bas_instance = 0;
+ req->batt_level = batt_lvl;
+ app_batt_env.batt_lvl = batt_lvl;
+ // Send the message
+ ke_msg_send(req);
+}
+
+static int bass_batt_level_ntf_cfg_ind_handler(ke_msg_id_t const msgid,struct bass_batt_level_ntf_cfg_ind const *param,ke_task_id_t const dest_id,ke_task_id_t const src_id)
+{
+ return (KE_MSG_CONSUMED);
+}
+
+static int batt_level_upd_handler(ke_msg_id_t const msgid,struct bass_batt_level_upd_rsp const *param,ke_task_id_t const dest_id,ke_task_id_t const src_id)
+{
+ return (KE_MSG_CONSUMED);
+}
+
+
+/**
+ ****************************************************************************************
+ * @brief
+ *
+ * @param[in] msgid Id of the message received.
+ * @param[in] param Pointer to the parameters of the message.
+ * @param[in] dest_id ID of the receiving task instance (TASK_GAP).
+ * @param[in] src_id ID of the sending task instance.
+ *
+ * @return If the message was consumed or not.
+ ****************************************************************************************
+ */
+static int app_batt_msg_dflt_handler(ke_msg_id_t const msgid,void const *param,ke_task_id_t const dest_id,ke_task_id_t const src_id)
+{
+ return (KE_MSG_CONSUMED);
+}
+
+/*
+ * LOCAL VARIABLE DEFINITIONS
+ ****************************************************************************************
+ */
+
+/// Default State handlers definition
+const struct ke_msg_handler app_batt_msg_handler_list[] =
+{
+ // Note: first message is latest message checked by kernel so default is put on top.
+ {KE_MSG_DEFAULT_HANDLER, (ke_msg_func_t)app_batt_msg_dflt_handler},
+ {BASS_BATT_LEVEL_NTF_CFG_IND, (ke_msg_func_t)bass_batt_level_ntf_cfg_ind_handler},
+ {BASS_BATT_LEVEL_UPD_RSP, (ke_msg_func_t)batt_level_upd_handler},
+};
+
+const struct ke_state_handler app_batt_table_handler = {&app_batt_msg_handler_list[0], (sizeof(app_batt_msg_handler_list)/sizeof(struct ke_msg_handler))};
+
+#endif //BLE_APP_BATT
+
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app_sec.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app_sec.c
new file mode 100644
index 0000000000..63b6049eca
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app_sec.c
@@ -0,0 +1,501 @@
+/**
+ ****************************************************************************************
+ *
+ * @file app_sec.c
+ *
+ * @brief Application Security Entry Point
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @addtogroup APP
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+
+#include "rwip_config.h"
+#include
+//#include "ble_arch.h"
+
+#if (BLE_APP_SEC)
+
+#include
+#include "co_math.h"
+#include "gapc_task.h" // GAP Controller Task API Definition
+#include "gapm_task.h" // GAPM task API definition
+#include "gap.h" // GAP Definition
+#include "gapc.h" // GAPC Definition
+#include "gapm.h"
+#include "prf_types.h"
+
+#include "app.h" // Application API Definition
+#include "app_sec.h" // Application Security API Definition
+#include "app_task.h" // Application Manager API Definition
+#include "interface.h"
+
+#if (NVDS_SUPPORT)
+#include "nvds.h" // NVDS API Definitions
+#endif //(NVDS_SUPPORT)
+/*
+ * GLOBAL VARIABLE DEFINITIONS
+ ****************************************************************************************
+ */
+
+/// Application Security Environment Structure
+struct app_sec_env_tag app_sec_env;
+
+
+
+//struct current_bond_info_t current_bond_info;
+/*
+ * GLOBAL FUNCTION DEFINITIONS
+ ****************************************************************************************
+ */
+
+static int app_sec_msg_dflt_handler(ke_msg_id_t const msgid,
+ void*param,
+ ke_task_id_t const dest_id,
+ ke_task_id_t const src_id)
+{
+ return (KE_MSG_CONSUMED);
+}
+
+void app_sec_init()
+{
+ /*------------------------------------------------------
+ * RETRIEVE BOND STATUS
+ *------------------------------------------------------*/
+ #if (NVDS_SUPPORT)
+ uint8_t length = NVDS_LEN_PERIPH_BONDED;
+ // Get bond status from NVDS
+ if (nvds_get(NVDS_TAG_PERIPH_BONDED, &length, (uint8_t *)&app_sec_env.bonded) != NVDS_OK)
+ {
+ // If read value is invalid, set status to not bonded
+ app_sec_env.bonded = false;
+ }
+/************************************************************************************************************/
+ uint8_t length1 = NVDS_LEN_DEVICE_NUM;
+
+ if (nvds_get(NVDS_TAG_DEVICE_NUM, &length1, &app_sec_env.device_num) != NVDS_OK)
+ {
+ // If read value is invalid, set device number to 0
+ app_sec_env.device_num = 0;
+ }
+/************************************************************************************************************/
+
+
+
+ #endif //(NVDS_SUPPORT)
+}
+
+
+void app_sec_send_security_req(uint8_t conidx)
+{
+
+ //start to security cmd
+ struct gapc_security_cmd *cmd = KE_MSG_ALLOC(GAPC_SECURITY_CMD,
+ KE_BUILD_ID(TASK_GAPC, app_env.conidx), TASK_APP, gapc_security_cmd);// Security request
+ cmd->operation = GAPC_SECURITY_REQ;
+
+ cmd->auth = GAP_AUTH_REQ_NO_MITM_BOND;
+
+ //iocap will select MITM or not
+
+ // Send the message
+ ke_msg_send(cmd);
+}
+
+
+/**
+ ****************************************************************************************
+ * @brief Handles reception of bond request command
+ *
+ * @param[in] msgid Id of the message received.
+ * @param[in] param Pointer to the parameters of the message.
+ * @param[in] dest_id ID of the receiving task instance (TASK_GAP).
+ * @param[in] src_id ID of the sending task instance.
+ *
+ * @return If the message was consumed or not.
+ ****************************************************************************************
+ */
+static int gapc_bond_req_ind_handler(ke_msg_id_t const msgid,struct gapc_bond_req_ind const *param,ke_task_id_t const dest_id,ke_task_id_t const src_id)
+{
+ struct gapc_bond_cfm *cfm = KE_MSG_ALLOC(GAPC_BOND_CFM,src_id, TASK_APP,gapc_bond_cfm);
+ switch (param->request)
+ {
+ case (GAPC_PAIRING_REQ):
+ {
+ cfm->request = GAPC_PAIRING_RSP;
+ cfm->accept = true;
+
+ // OOB information
+ cfm->data.pairing_feat.oob = GAP_OOB_AUTH_DATA_NOT_PRESENT;
+ // Encryption key size
+ cfm->data.pairing_feat.key_size = KEY_LEN;
+ // IO capabilities
+ cfm->data.pairing_feat.iocap = app_env.iocap;
+ // Authentication requirements
+ cfm->data.pairing_feat.auth = GAP_AUTH_REQ_NO_MITM_BOND; //GAP_AUTH_REQ_NO_MITM_BOND;
+
+ cfm->data.pairing_feat.ikey_dist = GAP_KDIST_NONE;
+ //Responder key distribution
+ cfm->data.pairing_feat.rkey_dist = GAP_KDIST_ENCKEY;
+ //Security requirements
+ cfm->data.pairing_feat.sec_req = GAP_NO_SEC;
+
+ }
+ break;
+
+ case(GAPC_LTK_EXCH):
+ {
+
+ uint8_t counter;
+
+ cfm->data.ltk.ediv = (uint16_t)( (co_rand_word() + app_env.loc_irk[1]*256 + app_env.loc_irk[0]) );
+
+ for(counter = 0; counter < RAND_NB_LEN; counter++)
+ {
+ cfm->data.ltk.randnb.nb[counter] = (uint8_t)((co_rand_word() + app_env.loc_irk[counter]) );
+ }
+
+ for(counter = 0; counter < KEY_LEN; counter++)
+ {
+ cfm->data.ltk.ltk.key[counter] = (uint8_t)((co_rand_word() + app_env.loc_irk[counter]) );
+ }
+
+ cfm->request = GAPC_LTK_EXCH;
+
+ cfm->accept = true;
+
+#if (NVDS_SUPPORT)
+
+ switch (app_sec_env.device_num % 5)
+ {
+ case 0:
+ if (nvds_put(NVDS_TAG_LTK, NVDS_LEN_LTK, (uint8_t *)&cfm->data.ltk) != NVDS_OK)
+ {
+ ASSERT_ERR(0);
+ }
+ break;
+ case 1:
+ if (nvds_put(NVDS_TAG_LTK1, NVDS_LEN_LTK1, (uint8_t *)&cfm->data.ltk) != NVDS_OK)
+ {
+ ASSERT_ERR(0);
+ }
+ break;
+ case 2:
+ if (nvds_put(NVDS_TAG_LTK2, NVDS_LEN_LTK2, (uint8_t *)&cfm->data.ltk) != NVDS_OK)
+ {
+ ASSERT_ERR(0);
+ }
+ break;
+ case 3:
+ if (nvds_put(NVDS_TAG_LTK3, NVDS_LEN_LTK3, (uint8_t *)&cfm->data.ltk) != NVDS_OK)
+ {
+ ASSERT_ERR(0);
+ }
+ break;
+
+ case 4:
+ if (nvds_put(NVDS_TAG_LTK4, NVDS_LEN_LTK4, (uint8_t *)&cfm->data.ltk) != NVDS_OK)
+ {
+ ASSERT_ERR(0);
+ }
+ break;
+ default:
+ break;
+ }
+ app_sec_env.device_num = (app_sec_env.device_num + 1) % 5;
+
+ uint8_t device_num[1]={0};
+ uint8_t length = NVDS_LEN_DEVICE_NUM;
+ nvds_get(NVDS_TAG_DEVICE_NUM, &length, device_num);
+
+ if (device_num[0]request = GAPC_IRK_EXCH;
+ cfm->accept = true;
+
+ // Load IRK
+ memcpy(cfm->data.irk.irk.key, app_env.loc_irk, KEY_LEN);
+ // load device address
+ cfm->data.irk.addr.addr_type = ADDR_PUBLIC;
+ #if (NVDS_SUPPORT)
+ if (nvds_get(NVDS_TAG_BD_ADDRESS, &addr_len, cfm->data.irk.addr.addr.addr) != NVDS_OK)
+ #endif //(NVDS_SUPPORT)
+ {
+ ASSERT_ERR(0);
+ }
+ }
+ break;
+
+
+ case (GAPC_TK_EXCH):
+ {
+ if (param->data.tk_type == GAP_TK_DISPLAY)
+ {
+ cfm->request = GAPC_TK_EXCH;
+ cfm->accept = true;
+
+ memset(cfm->data.tk.key, 0, KEY_LEN);
+ cfm->data.tk.key[0] = (uint8_t)((app_env.pin_code & 0x000000FF) >> 0);
+ cfm->data.tk.key[1] = (uint8_t)((app_env.pin_code & 0x0000FF00) >> 8);
+ cfm->data.tk.key[2] = (uint8_t)((app_env.pin_code & 0x00FF0000) >> 16);
+ cfm->data.tk.key[3] = (uint8_t)((app_env.pin_code & 0xFF000000) >> 24);
+
+ }
+ else
+ {
+ ASSERT_ERR(0);
+ }
+
+ }
+ break;
+
+ default:
+ {
+ ASSERT_ERR(0);
+ }
+ break;
+ }
+
+ // Send the message
+ // interface_env.delay_ms(5);
+ ke_msg_send(cfm);
+
+ return (KE_MSG_CONSUMED);
+}
+
+
+
+/**
+ ****************************************************************************************
+ * @brief Handles reception of bond indication
+ *
+ * @param[in] msgid Id of the message received.
+ * @param[in] param Pointer to the parameters of the message.
+ * @param[in] dest_id ID of the receiving task instance (TASK_GAP).
+ * @param[in] src_id ID of the sending task instance.
+ *
+ * @return If the message was consumed or not.
+ ****************************************************************************************
+ */
+static int gapc_bond_ind_handler(ke_msg_id_t const msgid,struct gapc_bond_ind const *param,ke_task_id_t const dest_id,ke_task_id_t const src_id)
+{
+ switch (param->info)
+ {
+ case (GAPC_PAIRING_SUCCEED):
+ {
+ // Update the bonding status in the environment
+ app_sec_env.bonded = true;
+ ke_state_set(TASK_APP, APPM_ENCRYPTED);//lizhk add
+ // Update the bonding status in the environment
+ #if (PLF_NVDS)
+// if (nvds_put(NVDS_TAG_PERIPH_BONDED, NVDS_LEN_PERIPH_BONDED,(uint8_t *)&app_sec_env.bonded) != NVDS_OK)
+// {
+// // An error has occurred during access to the NVDS
+// ASSERT_ERR(0);
+// }
+// gapc_save_bond_info();
+
+ #endif //(PLF_NVDS)
+
+ }
+ break;
+
+ case (GAPC_REPEATED_ATTEMPT):
+ {
+ appm_disconnect();
+ }
+ break;
+
+ case (GAPC_IRK_EXCH):
+ {
+ }
+ break;
+
+ case (GAPC_PAIRING_FAILED):
+ {
+ app_sec_send_security_req(0);
+ }
+ break;
+
+ // In Secure Connections we get BOND_IND with SMPC calculated LTK
+ case (GAPC_LTK_EXCH) :
+ {
+
+ }
+ break;
+
+ case (GAPC_CSRK_EXCH) :
+ {
+
+ }
+ break;
+
+ default:
+ {
+ ASSERT_ERR(0);
+ }
+ break;
+ }
+
+ return (KE_MSG_CONSUMED);
+}
+extern void BT_handle(void);
+static int gapc_encrypt_req_ind_handler(ke_msg_id_t const msgid,
+ struct gapc_encrypt_req_ind const *param,
+ ke_task_id_t const dest_id,
+ ke_task_id_t const src_id)
+{
+ #if (NVDS_SUPPORT)
+ // LTK value
+ struct gapc_ltk ltk;
+ // Length
+ uint8_t length = NVDS_LEN_LTK;
+
+ #endif // #if (NVDS_SUPPORT)
+
+ // Prepare the GAPC_ENCRYPT_CFM message
+ struct gapc_encrypt_cfm *cfm = KE_MSG_ALLOC(GAPC_ENCRYPT_CFM,src_id, TASK_APP,gapc_encrypt_cfm);
+ cfm->found = false;
+ //移出未使用å˜é‡ app_sec_env.bonded
+
+
+ #if (NVDS_SUPPORT)
+ // Retrieve the required informations from NVD
+ uint8_t err = 1;
+
+ uint8_t device_num[1]={0};
+ uint8_t length1 = NVDS_LEN_DEVICE_NUM;
+ nvds_get(NVDS_TAG_DEVICE_NUM, &length1, device_num);
+
+ for(uint8_t i=0;iediv == ltk.ediv) &&!memcmp(¶m->rand_nb.nb[0], <k.randnb.nb[0], sizeof(struct rand_nb)))
+ {
+ cfm->found = true;
+ cfm->key_size = 16;
+ memcpy(&cfm->ltk, <k.ltk, sizeof(struct gap_sec_key));
+ app_env.con_device_num = i;
+ ke_state_set(TASK_APP,APPM_ENCRYPTED);
+
+ break;
+ }
+
+ }
+ }
+ uint8_t found_flag = cfm->found;
+ #endif // #if (NVDS_SUPPORT)
+ ke_msg_send(cfm);
+
+ if (found_flag == false)
+ {
+ uint8_t schedule_num = 10;
+ while (schedule_num--)
+ {
+ BT_handle();
+ }
+ eif_delay_ms(200);
+ app_sec_send_security_req(0);
+ }
+
+
+ return (KE_MSG_CONSUMED);
+}
+
+
+static int gapc_encrypt_ind_handler(ke_msg_id_t const msgid,
+ struct gapc_encrypt_ind const *param,
+ ke_task_id_t const dest_id,
+ ke_task_id_t const src_id)
+{
+ ke_state_set(TASK_APP, APPM_ENCRYPTED);
+ return (KE_MSG_CONSUMED);
+}
+
+
+
+ /*
+ * LOCAL VARIABLE DEFINITIONS
+ ****************************************************************************************
+ */
+
+/// Default State handlers definition
+const struct ke_msg_handler app_sec_msg_handler_list[] =
+{
+ // Note: first message is latest message checked by kernel so default is put on top.
+ {KE_MSG_DEFAULT_HANDLER, (ke_msg_func_t)app_sec_msg_dflt_handler},
+
+ {GAPC_BOND_REQ_IND, (ke_msg_func_t)gapc_bond_req_ind_handler},
+ {GAPC_BOND_IND, (ke_msg_func_t)gapc_bond_ind_handler},
+
+ {GAPC_ENCRYPT_REQ_IND, (ke_msg_func_t)gapc_encrypt_req_ind_handler},
+ {GAPC_ENCRYPT_IND, (ke_msg_func_t)gapc_encrypt_ind_handler},
+};
+
+const struct ke_state_handler app_sec_table_handler ={&app_sec_msg_handler_list[0], (sizeof(app_sec_msg_handler_list) / sizeof(struct ke_msg_handler))};
+
+#endif //(BLE_APP_SEC)
+
+
+
+/// @} APP
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app_task.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app_task.c
new file mode 100644
index 0000000000..4896c9c523
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app_task.c
@@ -0,0 +1,908 @@
+/**
+ ****************************************************************************************
+ *
+ * @file appm_task.c
+ *
+ * @brief RW APP Task implementation
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @addtogroup APPTASK
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+
+#include "rwip_config.h" // SW configuration
+
+#if (BLE_APP_PRESENT)
+
+#include "app_task.h" // Application Manager Task API
+#include "app.h" // Application Manager Definition
+#include "gapc_task.h" // GAP Controller Task API
+#include "gapm_task.h" // GAP Manager Task API
+#include "ble_arch.h" // Platform Definitions
+#include
+#include "ke_timer.h" // Kernel timer
+#include "ke_task.h"
+#include "gattc_task.h"
+#include "interface.h"
+#include "n32wb452_ble_api.h"
+
+#if (BLE_APP_SEC)
+#include "app_sec.h" // Security Module Definition
+#endif //(BLE_APP_SEC)
+
+#if (BLE_APP_HT)
+#include "app_ht.h" // Health Thermometer Module Definition
+#include "htpt_task.h"
+#endif //(BLE_APP_HT)
+
+#if (BLE_APP_DIS)
+#include "app_dis.h" // Device Information Module Definition
+#include "diss_task.h"
+#endif //(BLE_APP_DIS)
+
+//#if (BLE_APP_BATT)
+//#include "app_batt.h" // Battery Module Definition
+//#include "bass_task.h"
+//#endif //(BLE_APP_BATT)
+
+#if (BLE_APP_HID)
+#include "app_hid.h" // HID Module Definition
+#include "hogpd_task.h"
+#endif //(BLE_APP_HID)
+
+#ifdef BLE_APP_AM0
+#include "am0_app.h" // Audio Mode 0 Application
+#endif //defined(BLE_APP_AM0)
+
+#if (DISPLAY_SUPPORT)
+#include "app_display.h" // Application Display Definition
+#endif //(DISPLAY_SUPPORT)
+
+
+#if (BLE_APP_USER)
+#include "app_user.h" // Health Thermometer Module Definition
+#include "user_task.h"
+#endif //(BLE_APP_HT)
+#include "app.h"
+
+#ifdef N32WB452_BT_API
+#include "n32wb452_log_level.h"
+#endif
+
+/*
+ * LOCAL FUNCTION DEFINITIONS
+ ****************************************************************************************
+ */
+
+extern uint8_t bda_cmd;
+
+static uint8_t appm_get_handler(const struct ke_state_handler *handler_list,
+ ke_msg_id_t msgid,
+ void *param,
+ ke_task_id_t src_id)
+{
+ // Counter
+ uint8_t counter;
+
+ // Get the message handler function by parsing the message table
+ for (counter = handler_list->msg_cnt; 0 < counter; counter--)
+ {
+ struct ke_msg_handler handler =/* (struct ke_msg_handler)*/(*(handler_list->msg_table + counter - 1));
+
+ if ((handler.id == msgid) ||
+ (handler.id == KE_MSG_DEFAULT_HANDLER))
+ {
+ // If handler is NULL, message should not have been received in this state
+ ASSERT_ERR(handler.func);
+
+ return (uint8_t)(handler.func(msgid, param, TASK_APP, src_id));
+ }
+ }
+
+ // If we are here no handler has been found, drop the message
+ return (KE_MSG_CONSUMED);
+}
+
+/*
+ * MESSAGE HANDLERS
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief
+ *
+ * @param[in] msgid Id of the message received.
+ * @param[in] param Pointer to the parameters of the message.
+ * @param[in] dest_id ID of the receiving task instance (TASK_GAP).
+ * @param[in] src_id ID of the sending task instance.
+ *
+ * @return If the message was consumed or not.
+ ****************************************************************************************
+ */
+static int appm_adv_timeout_handler(ke_msg_id_t const msgid,
+ void const *param,
+ ke_task_id_t const dest_id,
+ ke_task_id_t const src_id)
+{
+ #if (BLE_APP_HID)
+ #else
+ // Stop advertising
+ appm_stop_advertising();
+ #endif
+
+ return (KE_MSG_CONSUMED);
+}
+
+/**
+ ****************************************************************************************
+ * @brief Handles ready indication from the GAP. - Reset the stack
+ *
+ * @param[in] msgid Id of the message received.
+ * @param[in] param Pointer to the parameters of the message.
+ * @param[in] dest_id ID of the receiving task instance (TASK_GAP).
+ * @param[in] src_id ID of the sending task instance.
+ *
+ * @return If the message was consumed or not.
+ ****************************************************************************************
+ */
+static int gapm_device_ready_ind_handler(ke_msg_id_t const msgid,
+ void const *param,
+ ke_task_id_t const dest_id,
+ ke_task_id_t const src_id)
+{
+
+ // Application has not been initialized
+ ASSERT_ERR(ke_state_get(dest_id) == APPM_INIT);
+
+ // Reset the stack
+ struct gapm_reset_cmd* cmd = KE_MSG_ALLOC(GAPM_RESET_CMD,
+ TASK_GAPM, TASK_APP,
+ gapm_reset_cmd);
+
+ cmd->operation = GAPM_RESET;
+ ke_msg_send(cmd);
+ return (KE_MSG_CONSUMED);
+}
+
+/**
+ ****************************************************************************************
+ * @brief Handles GAP manager command complete events.
+ *
+ * @param[in] msgid Id of the message received.
+ * @param[in] param Pointer to the parameters of the message.
+ * @param[in] dest_id ID of the receiving task instance (TASK_GAP).
+ * @param[in] src_id ID of the sending task instance.
+ *
+ * @return If the message was consumed or not.
+ ****************************************************************************************
+ */
+static int appm_gapm_cmp_evt_handler(ke_msg_id_t const msgid,
+ struct gapm_cmp_evt const *param,
+ ke_task_id_t const dest_id,
+ ke_task_id_t const src_id)
+{
+ ble_log(BLE_DEBUG,"operation:%x\r\n",param->operation);
+ ble_log(BLE_DEBUG,"status:%x\r\n",param->status);
+ switch (param->operation)
+ {
+ // Reset completed
+ case(GAPM_RESET):
+ {
+ if (param->status == GAP_ERR_NO_ERROR)//GAP_ERR_NO_ERROR
+ {
+ // Set Device configuration
+ struct gapm_set_dev_config_cmd *cmd = KE_MSG_ALLOC(GAPM_SET_DEV_CONFIG_CMD,
+ TASK_GAPM, TASK_APP,
+ gapm_set_dev_config_cmd);
+ // Set the operation
+ cmd->operation = GAPM_SET_DEV_CONFIG;
+ // Set the device role - Peripheral
+ cmd->role = GAP_ROLE_PERIPHERAL;
+ // Set Data length parameters
+
+ cmd->max_mtu = 255;//app_env.max_mtu;//512; //pts test
+ cmd->pairing_mode = app_env.pairing_mode;//GAPM_PAIRING_LEGACY;
+
+ memcpy(cmd->addr.addr, app_env.bdaddr.addr, 6);
+ cmd->addr_type = app_env.bdaddr_type;
+ cmd->sugg_max_tx_octets = BLE_MIN_OCTETS;
+ cmd->sugg_max_tx_time = BLE_MIN_TIME;
+ cmd->max_mtu = app_env.max_mtu;
+
+ cmd->att_cfg |= GAPM_MASK_ATT_SVC_CHG_EN;
+ // load IRK
+ memcpy(cmd->irk.key, app_env.loc_irk, KEY_LEN);
+
+ // Send message
+ ke_msg_send(cmd);
+ }
+ else
+ {
+ ASSERT_ERR(0);
+ }
+ }
+ break;
+
+ case (GAPM_SET_DEV_CONFIG):
+ {
+ //ASSERT_INFO(param->status == GAP_ERR_NO_ERROR, param->operation, param->status);
+ // Go to the create db state
+ ke_state_set(TASK_APP, APPM_CREATE_DB);
+
+ // Add the first required service in the database
+ // and wait for the PROFILE_ADDED_IND
+ appm_add_svc();
+ }
+ break;
+
+ case (GAPM_PROFILE_TASK_ADD):
+ {
+ struct gapm_gen_rand_nb_cmd *cmd = KE_MSG_ALLOC(GAPM_GEN_RAND_NB_CMD,
+ TASK_GAPM, TASK_APP,
+ gapm_gen_rand_nb_cmd);
+
+ cmd->operation = GAPM_GEN_RAND_NB;
+ app_env.rand_cnt = 1;
+ ke_msg_send(cmd);
+ }
+ break;
+
+ case (GAPM_GEN_RAND_NB) :
+ {
+ if (app_env.rand_cnt == 1)
+ {
+ // Generate a second random number
+ app_env.rand_cnt++;
+ struct gapm_gen_rand_nb_cmd *cmd = KE_MSG_ALLOC(GAPM_GEN_RAND_NB_CMD,
+ TASK_GAPM, TASK_APP,
+ gapm_gen_rand_nb_cmd);
+
+ cmd->operation = GAPM_GEN_RAND_NB;
+ ke_msg_send(cmd);
+ }
+ else
+ {
+ // Prepare the GAPM_START_ADVERTISE_CMD message
+ struct gapm_set_irk_cmd *cmd = KE_MSG_ALLOC(GAPM_SET_IRK_CMD,
+ TASK_GAPM, TASK_APP,
+ gapm_set_irk_cmd);
+
+ app_env.rand_cnt=0;
+ /// GAPM requested operation:
+ /// - GAPM_SET_IRK: Set device configuration
+ cmd->operation = GAPM_SET_IRK;
+ memcpy(&cmd->irk.key[0], &app_env.loc_irk[0], KEY_LEN);
+ ke_msg_send(cmd);
+ }
+ }
+ break;
+
+ case (GAPM_SET_IRK):
+ {
+ ASSERT_INFO(param->status == GAP_ERR_NO_ERROR, param->operation, param->status);
+ // Add the next requested service
+ app_env.rand_cnt = 0;
+
+ if (!appm_add_svc())
+ {
+ // Go to the ready state
+ // ke_state_set(TASK_APP, APPM_READY);
+ // No more service to add, start advertising
+ // appm_start_advertising();
+ struct gapm_get_dev_info_cmd* dev_cmd = KE_MSG_ALLOC(GAPM_GET_DEV_INFO_CMD ,
+ TASK_GAPM, TASK_APP, gapm_get_dev_info_cmd);
+
+ // fill parameters
+ dev_cmd->operation = GAPM_GET_DEV_BDADDR;
+
+ ke_msg_send(dev_cmd);
+
+
+ }
+ }
+ break;
+ case (GAPM_GET_DEV_BDADDR):
+ ke_state_set(TASK_APP, APPM_READY);
+ //start advertinsing
+ appm_start_advertising();
+ break;
+
+ case (GAPM_ADV_NON_CONN):
+ case (GAPM_ADV_UNDIRECT):
+ case (GAPM_ADV_DIRECT):
+ case (GAPM_ADV_DIRECT_LDC):
+ case (GAPM_UPDATE_ADVERTISE_DATA):
+ {
+ ASSERT_INFO(param->status == GAP_ERR_NO_ERROR, param->operation, param->status);
+ }
+ break;
+
+
+ default:
+ {
+ // Drop the message
+ }
+ break;
+ }
+
+ return (KE_MSG_CONSUMED);
+}
+
+static int gapc_get_dev_info_req_ind_handler(ke_msg_id_t const msgid,
+ struct gapc_get_dev_info_req_ind const *param,
+ ke_task_id_t const dest_id,
+ ke_task_id_t const src_id)
+{
+ switch (param->req)
+ {
+ case GAPC_DEV_NAME:
+ {
+ struct gapc_get_dev_info_cfm * cfm = KE_MSG_ALLOC_DYN(GAPC_GET_DEV_INFO_CFM,
+ src_id, dest_id,
+ gapc_get_dev_info_cfm, APP_DEVICE_NAME_MAX_LEN);
+ cfm->req = param->req;
+ cfm->info.name.length = appm_get_dev_name(cfm->info.name.value);
+
+ // Send message
+ ke_msg_send(cfm);
+ }
+ break;
+
+ case GAPC_DEV_APPEARANCE:
+ {
+ // Allocate message
+ struct gapc_get_dev_info_cfm *cfm = KE_MSG_ALLOC(GAPC_GET_DEV_INFO_CFM,
+ src_id, dest_id,
+ gapc_get_dev_info_cfm);
+ cfm->req = param->req;
+ // Set the device appearance
+#if (BLE_APP_HT)
+ // Generic Thermometer - TODO: Use a flag
+ cfm->info.appearance = 728;
+#elif (BLE_APP_HID)
+ // HID Mouse
+ cfm->info.appearance = 962;
+#else
+ // No appearance
+ cfm->info.appearance = 0;
+#endif
+
+ // Send message
+ ke_msg_send(cfm);
+ }
+ break;
+
+ case GAPC_DEV_SLV_PREF_PARAMS:
+ {
+ // Allocate message
+ struct gapc_get_dev_info_cfm *cfm = KE_MSG_ALLOC(GAPC_GET_DEV_INFO_CFM,
+ src_id, dest_id,
+ gapc_get_dev_info_cfm);
+ cfm->req = param->req;
+ // Slave preferred Connection interval Min
+ cfm->info.slv_params.con_intv_min = 100;
+ // Slave preferred Connection interval Max
+ cfm->info.slv_params.con_intv_max = 200;
+ // Slave preferred Connection latency
+ cfm->info.slv_params.slave_latency = 4;
+ // Slave preferred Link supervision timeout
+ cfm->info.slv_params.conn_timeout = 600; // 2s (500*10ms)
+
+ // Send message
+ ke_msg_send(cfm);
+ }
+ break;
+
+ default: /* Do Nothing */
+ break;
+ }
+
+
+ return (KE_MSG_CONSUMED);
+}
+/**
+ ****************************************************************************************
+ * @brief Handles GAPC_SET_DEV_INFO_REQ_IND message.
+ *
+ * @param[in] msgid Id of the message received.
+ * @param[in] param Pointer to the parameters of the message.
+ * @param[in] dest_id ID of the receiving task instance (TASK_GAP).
+ * @param[in] src_id ID of the sending task instance.
+ *
+ * @return If the message was consumed or not.
+ ****************************************************************************************
+ */
+static int gapc_set_dev_info_req_ind_handler(ke_msg_id_t const msgid,
+ struct gapc_set_dev_info_req_ind const *param,
+ ke_task_id_t const dest_id,
+ ke_task_id_t const src_id)
+{
+ // Set Device configuration
+ struct gapc_set_dev_info_cfm* cfm = KE_MSG_ALLOC(GAPC_SET_DEV_INFO_CFM, src_id, dest_id,
+ gapc_set_dev_info_cfm);
+ // Reject to change parameters
+ cfm->status = GAP_ERR_REJECTED;
+ cfm->req = param->req;
+ // Send message
+ ke_msg_send(cfm);
+
+ return (KE_MSG_CONSUMED);
+}
+
+/**
+ ****************************************************************************************
+ * @brief Handles connection complete event from the GAP. Enable all required profiles
+ *
+ * @param[in] msgid Id of the message received.
+ * @param[in] param Pointer to the parameters of the message.
+ * @param[in] dest_id ID of the receiving task instance (TASK_GAP).
+ * @param[in] src_id ID of the sending task instance.
+ *
+ * @return If the message was consumed or not.
+ ****************************************************************************************
+ */
+static int gapc_connection_req_ind_handler(ke_msg_id_t const msgid,
+ struct gapc_connection_req_ind const *param,
+ ke_task_id_t const dest_id,
+ ke_task_id_t const src_id)
+{
+ app_env.conidx = KE_IDX_GET(src_id);
+ app_env.rx_data.RxTotalLen =0;
+ app_env.rx_data.RxCurrentLen=0;
+
+ // Check if the received Connection Handle was valid
+
+ //BT_add_white_list(param->peer_addr.addr,param->peer_addr_type);
+
+ if (app_env.conidx != GAP_INVALID_CONIDX)
+ {
+ // Retrieve the connection info from the parameters
+ app_env.conhdl = param->conhdl;
+
+ // Clear the advertising timeout timer
+ if (ke_timer_active(APP_ADV_TIMEOUT_TIMER, TASK_APP))
+ {
+ ke_timer_clear(APP_ADV_TIMEOUT_TIMER, TASK_APP);
+ }
+
+ // Send connection confirmation
+ struct gapc_connection_cfm *cfm = KE_MSG_ALLOC(GAPC_CONNECTION_CFM,
+ KE_BUILD_ID(TASK_GAPC, app_env.conidx), TASK_APP,
+ gapc_connection_cfm);
+
+ // 设置邦定认è¯æ¨¡å¼ 为 GAP_AUTH_REQ_NO_MITM_BOND
+ cfm->auth = GAP_AUTH_REQ_NO_MITM_BOND;
+
+ // Send the message
+ ke_msg_send(cfm);
+
+ // ke_state_set(dest_id, APPM_CONNECTED);
+ ke_state_set(TASK_APP, APPM_CONNECTED);
+ if (g_pcallback) {
+ g_pcallback(BT_EVENT_CONNECTED, NULL, 0, 0);
+ }
+ g_connnet_start = 1;
+
+ /*--------------------------------------------------------------
+ * ENABLE REQUIRED PROFILES
+ *--------------------------------------------------------------*/
+// #if (BLE_APP_BATT)
+// // Enable Battery Service
+// app_batt_enable_prf(app_env.conhdl);
+// #endif //(BLE_APP_BATT)
+
+
+ #if (BLE_APP_USER)
+ //app_user_enable_prf(app_env.conhdl);
+ #endif
+
+
+ }
+ else
+ {
+ // No connection has been establish, restart advertising
+ appm_start_advertising();
+ }
+ //
+ //
+
+ return (KE_MSG_CONSUMED);
+}
+
+/**
+ ****************************************************************************************
+ * @brief Handles GAP controller command complete events.
+ *
+ * @param[in] msgid Id of the message received.
+ * @param[in] param Pointer to the parameters of the message.
+ * @param[in] dest_id ID of the receiving task instance (TASK_GAP).
+ * @param[in] src_id ID of the sending task instance.
+ *
+ * @return If the message was consumed or not.
+ ****************************************************************************************
+ */
+static int appm_gapc_cmp_evt_handler(ke_msg_id_t const msgid,
+ struct gapc_cmp_evt const *param,
+ ke_task_id_t const dest_id,
+ ke_task_id_t const src_id)
+{
+ switch (param->operation)
+ {
+
+ case (GAPC_UPDATE_PARAMS):
+ {
+// extern uint32_t need_rsp_type;
+// if (need_rsp_type == 0xcc )
+// {
+// app_user_updata_temp_send(param->status);
+// }
+ }
+ break;
+
+ default:
+ {
+ }
+ break;
+ }
+
+ return (KE_MSG_CONSUMED);
+}
+static int appm_gapc_param_updated_req_ind_handler(ke_msg_id_t const msgid,
+ struct gapc_param_update_req_ind const *param,
+ ke_task_id_t const dest_id,
+ ke_task_id_t const src_id)
+{
+
+
+ struct gapc_param_update_cfm *cmd = KE_MSG_ALLOC(GAPC_PARAM_UPDATE_CFM,
+ KE_BUILD_ID(TASK_GAPC, app_env.conidx), TASK_APP,
+ gapc_param_update_cfm);
+
+ cmd->accept = true;
+ cmd->ce_len_min = 0xFFFF;
+ cmd->ce_len_max = 0xFFFF;
+ ke_msg_send(cmd);
+ return (KE_MSG_CONSUMED);
+}
+
+
+/**
+ ****************************************************************************************
+ * @brief Handles disconnection complete event from the GAP.
+ *
+ * @param[in] msgid Id of the message received.
+ * @param[in] param Pointer to the parameters of the message.
+ * @param[in] dest_id ID of the receiving task instance (TASK_GAP).
+ * @param[in] src_id ID of the sending task instance.
+ *
+ * @return If the message was consumed or not.
+ ****************************************************************************************
+ */
+static int gapc_disconnect_ind_handler(ke_msg_id_t const msgid,
+ struct gapc_disconnect_ind const *param,
+ ke_task_id_t const dest_id,
+ ke_task_id_t const src_id)
+{
+
+ // Go to the ready state
+ ke_state_set(TASK_APP, APPM_READY);
+
+ #if (BLE_APP_HT)
+ // Stop interval timer
+ app_stop_timer();
+ #endif //(BLE_APP_HT)
+
+ #if (DISPLAY_SUPPORT)
+ // Update Connection State screen
+ app_display_set_con(false);
+ #endif //(DISPLAY_SUPPORT)
+
+ app_env.rx_data.RxTotalLen =0;
+ app_env.rx_data.RxCurrentLen=0;
+ appm_start_advertising();
+
+
+ return (KE_MSG_CONSUMED);
+}
+
+
+static int gapm_profile_added_ind_handler(ke_msg_id_t const msgid,
+ struct gapm_profile_added_ind *param,
+ ke_task_id_t const dest_id,
+ ke_task_id_t const src_id)
+{
+ // Current State
+ uint8_t state = ke_state_get(dest_id);
+ if (state == APPM_CREATE_DB)
+ {
+ switch (param->prf_task_id)
+ {
+ #if defined (BLE_APP_AM0)
+ case (TASK_ID_AM0_HAS):
+ {
+ am0_app_set_prf_task(param->prf_task_nb);
+ }
+ break;
+#endif // defined (BLE_APP_AM0)
+
+ #if BLE_APP_USER
+ case (TASK_ID_USER):
+ {
+
+ } break;
+ #endif // defined (BLE_APP_USER)
+ default: /* Nothing to do */
+ break;
+ }
+ }
+ else
+ {
+ ASSERT_INFO(0, state, src_id);
+ }
+
+ return KE_MSG_CONSUMED;
+}
+
+/**
+ ****************************************************************************************
+ * @brief Handles reception of all messages sent from the lower layers to the application
+ * @param[in] msgid Id of the message received.
+ * @param[in] param Pointer to the parameters of the message.
+ * @param[in] dest_id ID of the receiving task instance
+ * @param[in] src_id ID of the sending task instance.
+ *
+ * @return If the message was consumed or not.
+ ****************************************************************************************
+ */
+static int appm_msg_handler(ke_msg_id_t const msgid,
+ void *param,
+ ke_task_id_t const dest_id,
+ ke_task_id_t const src_id)
+{
+ // Retrieve identifier of the task from received message
+ ke_task_id_t src_task_id = MSG_T(msgid);
+ // Message policy
+ uint8_t msg_pol = KE_MSG_CONSUMED;
+
+ switch (src_task_id)
+ {
+ case (TASK_ID_GAPC):
+ {
+ #if (BLE_APP_SEC)
+ if ((msgid >= GAPC_BOND_CMD) &&
+ (msgid <= GAPC_SECURITY_IND))
+ {
+ // Call the Security Module
+ msg_pol = appm_get_handler(&app_sec_table_handler, msgid, param, src_id);
+ }
+ #endif //(BLE_APP_SEC)
+ // else drop the message
+ }
+ break;
+
+ case (TASK_ID_GATTC):
+ {
+ // Service Changed - Drop
+ } break;
+
+ #if (BLE_APP_HT)
+ case (TASK_ID_HTPT):
+ {
+ // Call the Health Thermometer Module
+ msg_pol = appm_get_handler(&app_ht_table_handler, msgid, param, src_id);
+ }
+ break;
+#endif //(BLE_APP_HT)
+
+ #if (BLE_APP_DIS)
+ case (TASK_ID_DISS):
+ {
+ // Call the Device Information Module
+ msg_pol = appm_get_handler(&app_dis_table_handler, msgid, param, src_id);
+ }
+ break;
+#endif //(BLE_APP_DIS)
+
+ #if (BLE_APP_HID)
+ case(TASK_ID_HOGPD):
+ {
+ // Call the HID Module
+ msg_pol = appm_get_handler(&app_hid_table_handler, msgid, param, src_id);
+ }
+ break;
+#endif //(BLE_APP_HID)
+
+// #if (BLE_APP_BATT)
+// case(TASK_ID_BASS):
+// {
+// // Call the Battery Module
+// msg_pol = appm_get_handler(&app_batt_table_handler, msgid, param, src_id);
+// }
+// break;
+//#endif //(BLE_APP_BATT)
+
+ #if defined(BLE_APP_AM0)
+ case (TASK_ID_AM0):
+ {
+ // Call the Audio Mode 0 Module
+ msg_pol = appm_get_handler(&am0_app_table_handler, msgid, param, src_id);
+ }
+ break;
+ case (TASK_ID_AM0_HAS):
+ {
+ // Call the Audio Mode 0 Module
+ msg_pol = appm_get_handler(&am0_app_has_table_handler, msgid, param, src_id);
+ }
+ break;
+#endif // defined(BLE_APP_AM0)
+#if (BLE_APP_USER)
+ case(TASK_ID_USER):
+ {
+ // Call the Health Thermometer Module
+ msg_pol = appm_get_handler(&app_user_table_handler, msgid, param, src_id);
+ }
+ break;
+#endif //(BLE_APP_HT)
+ default:
+ {
+ #if (BLE_APP_HT)
+ if (msgid == APP_HT_MEAS_INTV_TIMER)
+ {
+ msg_pol = appm_get_handler(&app_ht_table_handler, msgid, param, src_id);
+ }
+ #endif //(BLE_APP_HT)
+
+ #if (BLE_APP_HID)
+ if (msgid == APP_HID_MOUSE_TIMEOUT_TIMER)
+ {
+ msg_pol = appm_get_handler(&app_hid_table_handler, msgid, param, src_id);
+ }
+#endif //(BLE_APP_HID)
+ }
+ break;
+ }
+
+ return (msg_pol);
+}
+
+/**
+ ****************************************************************************************
+ * @brief Handles reception of random number generated message
+ *
+ * @param[in] msgid Id of the message received.
+ * @param[in] param Pointer to the parameters of the message.
+ * @param[in] dest_id ID of the receiving task instance
+ * @param[in] src_id ID of the sending task instance.
+ *
+ * @return If the message was consumed or not.
+ ****************************************************************************************
+ */
+static int appm_gapm_gen_rand_nb_ind_handler(ke_msg_id_t const msgid, struct gapm_gen_rand_nb_ind *param,
+ ke_task_id_t const dest_id, ke_task_id_t const src_id)
+{
+
+ if (app_env.rand_cnt==1) // First part of IRK
+ {
+ memcpy(&app_env.loc_irk[0], ¶m->randnb.nb[0], 8);
+ }
+ else if (app_env.rand_cnt==2) // Second part of IRK
+ {
+ memcpy(&app_env.loc_irk[8], ¶m->randnb.nb[0], 8);
+ }
+
+ return KE_MSG_CONSUMED;
+}
+/*
+ * GLOBAL VARIABLES DEFINITION
+ ****************************************************************************************
+ */
+static int gatt_set_mtu_ind_handler(ke_msg_id_t const msgid, struct gattc_mtu_changed_ind const *param,
+ ke_task_id_t const dest_id, ke_task_id_t const src_id)
+{
+ extern uint32_t need_rsp_type ;
+ app_env.max_mtu = param->mtu;
+//if (need_rsp_type == 0xbb )
+//{
+// app_user_mtu_temp_send(param->mtu);
+// need_rsp_type = 0;
+//}
+
+ return (KE_MSG_CONSUMED);
+}
+
+
+static int gapc_param_updated_ind_handler(ke_msg_id_t const msgid,
+ struct gapc_param_updated_ind const *param,
+ ke_task_id_t const dest_id,
+ ke_task_id_t const src_id)
+{
+ app_env.con_interval = param->con_interval;
+ app_env.con_latency = param->con_latency;
+ app_env.con_time_out = param->sup_to;
+ return (KE_MSG_CONSUMED);
+}
+
+static int gapm_read_wlistsize_req_ind_handler(ke_msg_id_t const msgid,
+ struct gapm_white_list_size_ind const *param,
+ ke_task_id_t const dest_id,
+ ke_task_id_t const src_id)
+{
+
+ app_env.wlst_size = param->size;
+ return (KE_MSG_CONSUMED);
+}
+
+static int gapm_read_bda_req_ind_handler(ke_msg_id_t const msgid,
+ struct gapm_dev_bdaddr_ind const *param,
+ ke_task_id_t const dest_id,
+ ke_task_id_t const src_id)
+{
+
+ return (KE_MSG_CONSUMED);
+}
+
+static int gapm_read_txpower_req_ind_handler(ke_msg_id_t const msgid,
+ struct gapm_dev_adv_tx_power_ind const *param,
+ ke_task_id_t const dest_id,
+ ke_task_id_t const src_id)
+{
+
+ return (KE_MSG_CONSUMED);
+}
+static int gapm_read_RSSI_req_ind_handler(ke_msg_id_t const msgid,
+ struct gapc_con_rssi_ind const *param,
+ ke_task_id_t const dest_id,
+ ke_task_id_t const src_id)
+{
+ app_env.rssi = param->rssi;
+ return (KE_MSG_CONSUMED);
+}
+/* Default State handlers definition. */
+const struct ke_msg_handler appm_default_state[] =
+{
+ // Note: first message is latest message checked by kernel so default is put on top.
+ {KE_MSG_DEFAULT_HANDLER, (ke_msg_func_t)appm_msg_handler},
+
+ {APP_ADV_TIMEOUT_TIMER, (ke_msg_func_t)appm_adv_timeout_handler},
+ {GAPM_DEVICE_READY_IND, (ke_msg_func_t)gapm_device_ready_ind_handler},
+ {GAPM_CMP_EVT, (ke_msg_func_t)appm_gapm_cmp_evt_handler},
+ {GAPC_GET_DEV_INFO_REQ_IND, (ke_msg_func_t)gapc_get_dev_info_req_ind_handler},
+ {GAPC_SET_DEV_INFO_REQ_IND, (ke_msg_func_t)gapc_set_dev_info_req_ind_handler},
+ {GAPC_CONNECTION_REQ_IND, (ke_msg_func_t)gapc_connection_req_ind_handler},
+ {GAPC_CMP_EVT, (ke_msg_func_t)appm_gapc_cmp_evt_handler},
+ {GAPC_DISCONNECT_IND, (ke_msg_func_t)gapc_disconnect_ind_handler},
+ {GAPM_PROFILE_ADDED_IND, (ke_msg_func_t)gapm_profile_added_ind_handler},
+ {GAPM_GEN_RAND_NB_IND, (ke_msg_func_t)appm_gapm_gen_rand_nb_ind_handler},
+ {GAPM_WHITE_LIST_SIZE_IND, (ke_msg_func_t)gapm_read_wlistsize_req_ind_handler},
+ {GAPM_DEV_BDADDR_IND, (ke_msg_func_t)gapm_read_bda_req_ind_handler},
+ {GAPM_DEV_ADV_TX_POWER_IND, (ke_msg_func_t)gapm_read_txpower_req_ind_handler},
+ {GAPC_CON_RSSI_IND, (ke_msg_func_t)gapm_read_RSSI_req_ind_handler},
+ {GATTC_MTU_CHANGED_IND, (ke_msg_func_t)gatt_set_mtu_ind_handler},
+ {GAPC_PARAM_UPDATED_IND, (ke_msg_func_t)gapc_param_updated_ind_handler},
+ {GAPC_PARAM_UPDATE_REQ_IND, (ke_msg_func_t)appm_gapc_param_updated_req_ind_handler},
+
+};
+
+/* Specifies the message handlers that are common to all states. */
+const struct ke_state_handler appm_default_handler = KE_STATE_HANDLER(appm_default_state);
+
+/* Defines the place holder for the states of all the task instances. */
+ke_state_t appm_state[APP_IDX_MAX];
+
+#endif //(BLE_APP_PRESENT)
+
+/// @} APPTASK
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app_user.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app_user.c
new file mode 100644
index 0000000000..65b1e60711
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app_user.c
@@ -0,0 +1,289 @@
+/**
+****************************************************************************************
+*
+* @file app_user.c
+*
+* @brief Health Thermometer Application entry point
+*
+* Copyright (C) RivieraWaves 2009-2015
+*
+*
+****************************************************************************************
+*/
+
+/**
+ ****************************************************************************************
+ * @addtogroup APP
+ * @{
+ ****************************************************************************************
+ */
+
+#include "rwip_config.h" // SW configuration
+#include "n32wb452_ble_api.h"
+#if (BLE_APP_USER)
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+
+#include "app_user.h" // Health Thermometer Application Definitions
+#include "app.h" // Application Definitions
+#include "app_task.h" // application task definitions
+
+#include "co_bt.h"
+#include "prf_types.h"
+#include "prf_utils.h"
+#include "ble_arch.h" // Platform Definitions
+#include "gapm_task.h"
+
+#include "co_math.h"
+#include "ke_timer.h"
+#include "prf.h"
+#include "user_task.h"
+#include "user.h"
+#include "co_utils.h"
+#include "gattc.h"
+#include "gapm.h"
+//#include "interface.h"
+
+#include "co_math.h"
+
+
+#if (DISPLAY_SUPPORT)
+#include "app_display.h"
+#include "display.h"
+#endif //DISPLAY_SUPPORT
+//#include "Bkey_user.h"
+
+#define DEMO_APP
+
+
+
+//uint8_t whitelistsize = 0;
+
+//INT8 rssivalue = 0;
+/*
+ * GLOBAL VARIABLE DEFINITIONS
+ ****************************************************************************************
+ */
+struct app_user_rev_tag app_user_env;
+/*
+ * LOCAL FUNCTION DEFINITIONS
+ ****************************************************************************************
+ */
+uint32_t need_rsp_type = 0;
+void app_user_init(void)
+{
+ memset(&app_user_env, 0, sizeof(app_user_env));
+ ke_timer_set(GAPM_DEVICE_READY_IND, TASK_APP, 10); //10MåŽå¤ä½
+}
+
+
+
+void add_users(uint16_t prf_task_id)
+{
+ struct user_db_cfg *db_cfg;
+
+ struct gapm_profile_task_add_cmd *req = KE_MSG_ALLOC_DYN(GAPM_PROFILE_TASK_ADD_CMD,TASK_GAPM, TASK_APP,gapm_profile_task_add_cmd, sizeof(struct user_db_cfg));
+ // Fill message
+ req->operation = GAPM_PROFILE_TASK_ADD;
+ req->sec_lvl = PERM(SVC_AUTH, DISABLE);
+ req->prf_task_id = prf_task_id;
+ req->app_task = TASK_APP;
+ req->start_hdl = 0;
+
+ // Set parameters
+ db_cfg = (struct user_db_cfg *) req->param;
+ //
+ db_cfg->features = (USER_READ_WRITE_CHAR_SUP | USER_DATA_NOTIFY_CHAR_SUP | USER_DATA_WRITE_CHAR_SUP);
+ db_cfg->txlen = USER_DATA_LEN_MAX;
+ db_cfg->rxlen = USER_DATA_LEN_MAX;
+
+ // Send the message
+ ke_msg_send(req);
+}
+
+void app_user_add_users(void)
+{
+ add_users(TASK_ID_USER);
+}
+
+static uint8_t data_notify_onePackage(uint16_t param_length , uint8_t *param_payload, uint16_t task_id, uint8_t att_idx)
+{
+ struct user_notify_req *req = KE_MSG_ALLOC_DYN(USER_NOTIFY_REQ,
+ prf_get_task_from_id(task_id),
+ TASK_APP,
+ user_notify_req, param_length);
+ req->send_param_length = param_length;
+ req->att_idx = att_idx;
+ memcpy(req->send_param_payload, param_payload, param_length);
+ ke_msg_send(req);
+ for(int i=0; i<8; i++)
+ {
+ BT_handle();
+ }
+ return 0;
+}
+uint8_t data_notify(uint16_t param_length , uint8_t *param_payload, uint16_t task_id, uint8_t att_idx)
+{
+ uint16_t mtu_num = 0;
+ mtu_num = gattc_get_mtu(app_env.conidx) - 3;
+ while (param_length)
+ {
+ struct user_notify_req *req = KE_MSG_ALLOC_DYN(USER_NOTIFY_REQ,
+ prf_get_task_from_id(task_id),
+ TASK_APP,
+ user_notify_req, mtu_num);
+
+
+
+ if (param_length > mtu_num)
+ {
+ req->send_param_length = mtu_num;
+ memcpy(req->send_param_payload, param_payload, mtu_num);
+ req->att_idx = att_idx;
+ ke_msg_send(req);
+ param_length -= mtu_num;
+ param_payload += mtu_num;
+ }
+ else
+ {
+ req->send_param_length = param_length;
+ req->att_idx = att_idx;
+ memcpy(req->send_param_payload, param_payload, param_length);
+ ke_msg_send(req);
+ param_length = 0;
+ }
+ }
+ return 1;
+
+}
+
+#if 0
+uint8_t app_user_data_notify(uint16_t param_length , uint8_t *param_payload, uint8_t att_idx)
+{
+ data_notify(param_length, param_payload, TASK_ID_USER, att_idx);
+ return 0;
+}
+#else
+uint8_t app_user_data_notify(uint16_t param_length , uint8_t *param_payload, uint8_t att_idx)
+{
+ uint16_t mtu_num = 0;
+ mtu_num = gattc_get_mtu(app_env.conidx) - 3;
+ while (param_length)
+ {
+ if (param_length > mtu_num)
+ {
+ data_notify_onePackage(mtu_num , param_payload, TASK_ID_USER, att_idx);
+ param_length -= mtu_num;
+ param_payload += mtu_num;
+ }
+ else
+ {
+ data_notify_onePackage(param_length , param_payload, TASK_ID_USER, att_idx);
+ param_length = 0;
+ }
+ }
+ return 0;
+}
+#endif
+
+
+// static uint8_t Speed_buf[7] ;
+//void app_user_mtu_temp_send(uint16_t mtu)
+//{
+
+//
+
+// Speed_buf[0] = 0x05;
+
+// Speed_buf[1] = 0x00;
+
+// Speed_buf[2] = 0xAA;
+
+// Speed_buf[3] = 0xBB;
+
+// Speed_buf[4] = 0x00;
+
+// Speed_buf[5] = mtu % 256;
+
+// Speed_buf[6] = mtu / 256;
+
+// app_user_data_notify(7, Speed_buf);
+//}
+
+//static uint8_t data_buf[13] ;
+//void app_user_updata_temp_send(uint8_t status)//,uint16_t intv_min, uint16_t intv_max, uint16_t latancy, uint16_t timesout)
+//{
+
+//
+
+// data_buf[0] = 0x0B;
+
+// data_buf[1] = 0x00;
+
+// data_buf[2] = 0xAA;
+
+// data_buf[3] = 0xCC;
+
+// data_buf[4] = status;
+
+// data_buf[5] = app_env.con_intv_min % 256;
+// data_buf[6] = app_env.con_intv_min / 256;
+// data_buf[7] = app_env.con_intv_max % 256;
+// data_buf[8] = app_env.con_intv_max / 256;
+// data_buf[9] = app_env.con_latency % 256;
+// data_buf[10] = app_env.con_latency / 256;
+// data_buf[11] = app_env.con_time_out % 256;
+// data_buf[12] = app_env.con_time_out / 256;
+
+// app_user_data_notify(13, data_buf);
+//}
+
+
+
+
+
+/**
+ ****************************************************************************************
+ * @brief Handles health thermometer timer
+ *
+ * @param[in] msgid Id of the message received.
+ * @param[in] param Pointer to the parameters of the message.
+ * @param[in] dest_id ID of the receiving task instance (TASK_GAP).
+ * @param[in] src_id ID of the sending task instance.
+ *
+ * @return If the message was consumed or not.
+ ****************************************************************************************
+ */
+static int app_user_msg_handler(ke_msg_id_t const msgid,
+ void const *param,
+ ke_task_id_t const dest_id,
+ ke_task_id_t const src_id)
+{
+ // todo
+
+ return (KE_MSG_CONSUMED);
+}
+
+/*
+ * LOCAL VARIABLE DEFINITIONS
+ ****************************************************************************************
+ */
+
+
+/// Default State handlers definition
+const struct ke_msg_handler app_user_msg_handler_list[] =
+{
+ // Note: first message is latest message checked by kernel so default is put on top.
+ {KE_MSG_DEFAULT_HANDLER, (ke_msg_func_t)app_user_msg_handler},
+
+};
+
+const struct ke_state_handler app_user_table_handler =
+{&app_user_msg_handler_list[0], (sizeof(app_user_msg_handler_list) / sizeof(struct ke_msg_handler))};
+
+#endif //BLE_APP_USER
+
+/// @} APP
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/bass.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/bass.c
new file mode 100644
index 0000000000..a50d85e4e1
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/bass.c
@@ -0,0 +1,461 @@
+/*****************************************************************************
+* Nations Microcontroller Software Support
+* ----------------------------------------------------------------------------
+* Copyright (c) 2017, Nations Corporation
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* - Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the disclaimer below.
+*
+* Nations's name may not be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ****************************************************************************/
+/*****************************************************************************
+* 文件å :bass.c
+* 功能æè¿°:
+* 版本:V 1.0.0
+* 作者:
+* 日期:
+* ****************************************************************************/
+
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+
+#include "rwip_config.h"
+
+#if (BLE_BATT_SERVER)
+#include "bass.h"
+#include "bass_task.h"
+#include "prf_utils.h"
+#include "prf.h"
+
+#include "ke_mem.h"
+
+/*
+ * BAS ATTRIBUTES DEFINITION
+ ****************************************************************************************
+ */
+
+/// Full BAS Database Description - Used to add attributes into the database
+const struct attm_desc bas_att_db[BAS_IDX_NB] =
+{
+ // Battery Service Declaration
+ [BAS_IDX_SVC] = {ATT_DECL_PRIMARY_SERVICE, PERM(RD, ENABLE), 0, 0},
+ // Battery Level Characteristic Declaration
+ [BAS_IDX_BATT_LVL_CHAR] = {ATT_DECL_CHARACTERISTIC, PERM(RD, ENABLE), 0, 0},
+ // Battery Level Characteristic Value
+ [BAS_IDX_BATT_LVL_VAL] = {ATT_CHAR_BATTERY_LEVEL, PERM(RD, ENABLE), PERM(RI, ENABLE), 0},
+ // Battery Level Characteristic - Client Characteristic Configuration Descriptor
+ [BAS_IDX_BATT_LVL_NTF_CFG] = {ATT_DESC_CLIENT_CHAR_CFG, PERM(RD, ENABLE)|PERM(WRITE_REQ, ENABLE), 0, 0},
+ // Battery Level Characteristic - Characteristic Presentation Format Descriptor
+ [BAS_IDX_BATT_LVL_PRES_FMT] = {ATT_DESC_CHAR_PRES_FORMAT, PERM(RD, ENABLE), PERM(RI, ENABLE), 0},
+};
+
+
+/*
+ * LOCAL FUNCTION DEFINITIONS
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief Initialization of the BASS module.
+ * This function performs all the initializations of the Profile module.
+ * - Creation of database (if it's a service)
+ * - Allocation of profile required memory
+ * - Initialization of task descriptor to register application
+ * - Task State array
+ * - Number of tasks
+ * - Default task handler
+ *
+ * @param[out] env Collector or Service allocated environment data.
+ * @param[in|out] start_hdl Service start handle (0 - dynamically allocated), only applies for services.
+ * @param[in] app_task Application task number.
+ * @param[in] sec_lvl Security level (AUTH, EKS and MI field of @see enum attm_value_perm_mask)
+ * @param[in] param Configuration parameters of profile collector or service (32 bits aligned)
+ *
+ * @return status code to know if profile initialization succeed or not.
+ ****************************************************************************************
+ */
+static uint8_t bass_init (struct prf_task_env* env, uint16_t* start_hdl, uint16_t app_task, uint8_t sec_lvl, struct bass_db_cfg* params)
+{
+
+ uint16_t shdl[BASS_NB_BAS_INSTANCES_MAX];
+ struct bass_env_tag* bass_env = NULL;
+ // Status
+ uint8_t status = GAP_ERR_NO_ERROR;
+ // Counter
+ uint8_t i;
+
+ // Check number of BAS instances
+ if ((params->bas_nb > 0) && (params->bas_nb <= BASS_NB_BAS_INSTANCES_MAX))
+ {
+ //-------------------- allocate memory required for the profile ---------------------
+ bass_env = (struct bass_env_tag* ) ke_malloc(sizeof(struct bass_env_tag), KE_MEM_ATT_DB);
+ memset(bass_env, 0 , sizeof(struct bass_env_tag));
+ // Save number of BAS
+ bass_env->svc_nb = params->bas_nb;
+ for (i = 0; ((i < params->bas_nb) && (status == GAP_ERR_NO_ERROR)); i++)
+ {
+ // Service content flag
+ uint8_t cfg_flag = BAS_CFG_FLAG_MANDATORY_MASK;
+ // Save database configuration
+ bass_env->features |= (params->features[i]) << i;
+ bass_env->batt_level_pres_format[i] = params->batt_level_pres_format[i];
+
+ // Check if notifications are supported
+ if (params->features[i] == BAS_BATT_LVL_NTF_SUP)
+ {
+ cfg_flag |= BAS_CFG_FLAG_NTF_SUP_MASK;
+ }
+
+ // Check if multiple instances
+ if (bass_env->svc_nb > 1)
+ {
+ cfg_flag |= BAS_CFG_FLAG_MTP_BAS_MASK;
+ }
+
+ shdl[i] = *start_hdl;
+
+ //Create BAS in the DB
+ //------------------ create the attribute database for the profile -------------------
+ status = attm_svc_create_db(&(shdl[i]), ATT_SVC_BATTERY_SERVICE, (uint8_t *)&cfg_flag,BAS_IDX_NB, NULL, env->task, bas_att_db,(sec_lvl & (PERM_MASK_SVC_DIS | PERM_MASK_SVC_AUTH | PERM_MASK_SVC_EKS)));
+ //Set optional permissions
+ if (status == GAP_ERR_NO_ERROR)
+ {
+ // update start handle for next service - only useful if multiple service, else not used.
+ // 4 characteristics + optional notification characteristic.
+ *start_hdl = shdl[i] + BAS_IDX_NB - ((params->features[i] == BAS_BATT_LVL_NTF_SUP) ? 0 : 1);
+ //Set optional permissions
+ if (params->features[i] == BAS_BATT_LVL_NTF_SUP)
+ {
+ // Battery Level characteristic value permissions
+ uint16_t perm = PERM(RD, ENABLE) | PERM(NTF, ENABLE);
+ attm_att_set_permission(shdl[i] + BAS_IDX_BATT_LVL_VAL, perm, 0);
+ }
+ }
+ // Reset configuration flag
+ cfg_flag = BAS_CFG_FLAG_MANDATORY_MASK;
+ }
+ }
+ else
+ {
+ status = PRF_ERR_INVALID_PARAM;
+ }
+
+ //-------------------- Update profile task information ---------------------
+ if (status == ATT_ERR_NO_ERROR)
+ {
+ // allocate BASS required environment variable
+ env->env = (prf_env_t*) bass_env;
+ *start_hdl = shdl[0];
+ bass_env->start_hdl = *start_hdl;
+ bass_env->prf_env.app_task = app_task | (PERM_GET(sec_lvl, SVC_MI) ? PERM(PRF_MI, ENABLE) : PERM(PRF_MI, DISABLE));
+ bass_env->prf_env.prf_task = env->task | PERM(PRF_MI, DISABLE);
+ // initialize environment variable
+ env->id = TASK_ID_BASS;
+ env->desc.idx_max = BASS_IDX_MAX;
+ env->desc.state = bass_env->state;
+ env->desc.default_handler = &bass_default_handler;
+ // service is ready, go into an Idle state
+ ke_state_set(env->task, BASS_IDLE);
+ }
+ else if (bass_env != NULL)
+ {
+ ke_free(bass_env);
+ }
+ return (status);
+}
+/**
+ ****************************************************************************************
+ * @brief Destruction of the BASS module - due to a reset for instance.
+ * This function clean-up allocated memory (attribute database is destroyed by another
+ * procedure)
+ *
+ * @param[in|out] env Collector or Service allocated environment data.
+ ****************************************************************************************
+ */
+static void bass_destroy(struct prf_task_env* env)
+{
+
+ struct bass_env_tag* bass_env = (struct bass_env_tag*) env->env;
+ // clear on-going operation
+ if (bass_env->operation != NULL)
+ {
+ ke_free(bass_env->operation);
+ }
+ // free profile environment variables
+ env->env = NULL;
+ ke_free(bass_env);
+}
+
+/**
+ ****************************************************************************************
+ * @brief Handles Connection creation
+ *
+ * @param[in|out] env Collector or Service allocated environment data.
+ * @param[in] conidx Connection index
+ ****************************************************************************************
+ */
+static void bass_create(struct prf_task_env* env, uint8_t conidx)
+{
+
+ struct bass_env_tag* bass_env = (struct bass_env_tag*) env->env;
+ ASSERT_ERR(conidx < BLE_CONNECTION_MAX);
+ // force notification config to zero when peer device is connected
+ bass_env->ntf_cfg[conidx] = 0;
+}
+
+/**
+ ****************************************************************************************
+ * @brief Handles Disconnection
+ *
+ * @param[in|out] env Collector or Service allocated environment data.
+ * @param[in] conidx Connection index
+ * @param[in] reason Detach reason
+ ****************************************************************************************
+ */
+static void bass_cleanup(struct prf_task_env* env, uint8_t conidx, uint8_t reason)
+{
+
+ struct bass_env_tag* bass_env = (struct bass_env_tag*) env->env;
+ ASSERT_ERR(conidx < BLE_CONNECTION_MAX);
+ // force notification config to zero when peer device is disconnected
+ bass_env->ntf_cfg[conidx] = 0;
+}
+
+
+/**
+ ****************************************************************************************
+ * @brief Trigger battery level notification
+ *
+ * @param bass_env profile environment
+ * @param conidx peer destination connection index
+ * @param svc_idx Service index
+ ****************************************************************************************
+ */
+static void bass_notify_batt_lvl(struct bass_env_tag* bass_env, uint8_t conidx, uint8_t svc_idx)
+{
+
+ // Allocate the GATT notification message
+ struct gattc_send_evt_cmd *batt_lvl = KE_MSG_ALLOC_DYN(GATTC_SEND_EVT_CMD,KE_BUILD_ID(TASK_GATTC, conidx), prf_src_task_get(&(bass_env->prf_env),0),gattc_send_evt_cmd, sizeof(uint8_t));
+ // Fill in the parameter structure
+ batt_lvl->operation = GATTC_NOTIFY;
+ batt_lvl->handle = bass_get_att_handle(svc_idx, BAS_IDX_BATT_LVL_VAL);
+ // pack measured value in database
+ batt_lvl->length = sizeof(uint8_t);
+ batt_lvl->value[0] = bass_env->batt_lvl[svc_idx];
+ // send notification to peer device
+ ke_msg_send(batt_lvl);
+}
+
+/*
+ * GLOBAL VARIABLE DEFINITIONS
+ ****************************************************************************************
+ */
+
+/// BASS Task interface required by profile manager
+const struct prf_task_cbs bass_itf = {
+ (prf_init_fnct) bass_init,
+ bass_destroy,
+ bass_create,
+ bass_cleanup,
+};
+
+/*
+ * GLOBAL FUNCTIONS DEFINITIONS
+ ****************************************************************************************
+ */
+
+const struct prf_task_cbs* bass_prf_itf_get(void)
+{
+ return &bass_itf;
+}
+
+uint16_t bass_get_att_handle(uint8_t svc_idx, uint8_t att_idx)
+{
+
+
+ struct bass_env_tag* bass_env = PRF_ENV_GET(BASS, bass);
+ uint16_t handle = ATT_INVALID_HDL;
+ uint8_t i = 0;
+ if (svc_idx < bass_env ->svc_nb)
+ {
+ handle = bass_env->start_hdl;
+ for(i = 0 ; i < svc_idx ; i++)
+ {
+ // update start handle for next service - only useful if multiple service, else not used.
+ // 4 characteristics + optional notification characteristic.
+ handle += BAS_IDX_NB - ((((bass_env->features >> i) & 0x01) == BAS_BATT_LVL_NTF_SUP) ? 0 : 1);
+ }
+ // increment index according to expected index
+ if (att_idx < BAS_IDX_BATT_LVL_NTF_CFG)
+ {
+ handle += att_idx;
+ }
+ // Battery notification
+ else if ((att_idx == BAS_IDX_BATT_LVL_NTF_CFG) && (((bass_env->features >> i) & 0x01) == BAS_BATT_LVL_NTF_SUP))
+ {
+ handle += BAS_IDX_BATT_LVL_NTF_CFG;
+ }
+ // Battery Level format
+ else if ((att_idx == BAS_IDX_BATT_LVL_PRES_FMT) && (bass_env->svc_nb > 1))
+ {
+ handle += BAS_IDX_BATT_LVL_PRES_FMT - ((((bass_env->features >> i) & 0x01) == BAS_BATT_LVL_NTF_SUP) ? 0 : 1);
+ }
+ else
+ {
+ handle = ATT_INVALID_HDL;
+ }
+ }
+ return handle;
+}
+
+uint8_t bass_get_att_idx(uint16_t handle, uint8_t *svc_idx, uint8_t *att_idx)
+{
+
+
+ struct bass_env_tag* bass_env = PRF_ENV_GET(BASS, bass);
+ uint16_t hdl_cursor = bass_env->start_hdl;
+ uint8_t status = PRF_APP_ERROR;
+
+ // Browse list of services
+ // handle must be greater than current index
+ for(*svc_idx = 0 ; (*svc_idx < bass_env->svc_nb) && (handle >= hdl_cursor) ; (*svc_idx)++)
+ {
+ // check if it's a mandatory index
+ if (handle <= (hdl_cursor + BAS_IDX_BATT_LVL_VAL))
+ {
+ *att_idx = handle -hdl_cursor;
+ status = GAP_ERR_NO_ERROR;
+ break;
+ }
+ hdl_cursor += BAS_IDX_BATT_LVL_VAL;
+
+ // check if it's a notify index
+ if (((bass_env->features >> *svc_idx) & 0x01) == BAS_BATT_LVL_NTF_SUP)
+ {
+ hdl_cursor++;
+ if (handle == hdl_cursor)
+ {
+ *att_idx = BAS_IDX_BATT_LVL_NTF_CFG;
+ status = GAP_ERR_NO_ERROR;
+ break;
+ }
+ }
+ // check if it's battery level format
+ if (bass_env->svc_nb > 1)
+ {
+ hdl_cursor++;
+ if (handle == hdl_cursor)
+ {
+ *att_idx = BAS_IDX_BATT_LVL_PRES_FMT;
+ status = GAP_ERR_NO_ERROR;
+ break;
+ }
+ }
+ hdl_cursor++;
+ }
+ return (status);
+}
+
+void bass_exe_operation(void)
+{
+
+
+ struct bass_env_tag* bass_env = PRF_ENV_GET(BASS, bass);
+ ASSERT_ERR(bass_env->operation != NULL);
+ bool finished = true;
+ uint8_t conidx = GAP_INVALID_CONIDX;
+
+ // Restoring connection information requested
+ if (bass_env->operation->id == BASS_ENABLE_REQ)
+ {
+ struct bass_enable_req * enable = (struct bass_enable_req *) ke_msg2param(bass_env->operation);
+ conidx = enable->conidx;
+ // loop on all services to check if notification should be triggered
+ while (bass_env->cursor < BASS_NB_BAS_INSTANCES_MAX)
+ {
+ if (((bass_env->ntf_cfg[enable->conidx] & (1 << bass_env->cursor)) != 0) && (enable->old_batt_lvl[bass_env->cursor] != bass_env->batt_lvl[bass_env->cursor]))
+ {
+ // trigger notification
+ bass_notify_batt_lvl(bass_env, enable->conidx, bass_env->cursor);
+ finished = false;
+ bass_env->cursor++;
+ break;
+ }
+ bass_env->cursor++;
+ }
+ }
+ // Battery level updated
+ else if (bass_env->operation->id == BASS_BATT_LEVEL_UPD_REQ)
+ {
+ struct bass_batt_level_upd_req * update = (struct bass_batt_level_upd_req *) ke_msg2param(bass_env->operation);
+ // loop on all connection
+ while (bass_env->cursor < BLE_CONNECTION_MAX)
+ {
+ if ((bass_env->ntf_cfg[bass_env->cursor] & (1 << update->bas_instance)) != 0)
+ {
+ // trigger notification
+ bass_notify_batt_lvl(bass_env, bass_env->cursor, update->bas_instance);
+ finished = false;
+ bass_env->cursor++;
+ break;
+ }
+ bass_env->cursor++;
+ }
+ }
+ else
+ {
+ ASSERT_ERR(0);
+ }
+
+ // check if operation is finished
+ if (finished)
+ {
+ // trigger response message
+ if (bass_env->operation->id == BASS_ENABLE_REQ)
+ {
+ struct bass_enable_rsp * rsp = KE_MSG_ALLOC(BASS_ENABLE_RSP, bass_env->operation->src_id,bass_env->operation->dest_id, bass_enable_rsp);
+ rsp->conidx = conidx;
+ rsp->status = GAP_ERR_NO_ERROR;
+ ke_msg_send(rsp);
+ }
+ else if (bass_env->operation->id == BASS_BATT_LEVEL_UPD_REQ)
+ {
+ struct bass_batt_level_upd_rsp * rsp = KE_MSG_ALLOC(BASS_BATT_LEVEL_UPD_RSP, bass_env->operation->src_id,bass_env->operation->dest_id, bass_batt_level_upd_rsp);
+ rsp->status = GAP_ERR_NO_ERROR;
+ ke_msg_send(rsp);
+ }
+ // free operation
+ ke_free(bass_env->operation);
+ bass_env->operation = NULL;
+ // go back to idle state
+ ke_state_set(prf_src_task_get(&(bass_env->prf_env), 0), BASS_IDLE);
+ }
+}
+
+
+#endif // (BLE_BATT_SERVER)
+
+/// @} BASS
+
+
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/bass_task.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/bass_task.c
new file mode 100644
index 0000000000..08fb4b7e52
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/bass_task.c
@@ -0,0 +1,379 @@
+/*****************************************************************************
+* Nations Microcontroller Software Support
+* ----------------------------------------------------------------------------
+* Copyright (c) 2017, Nations Corporation
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* - Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the disclaimer below.
+*
+* Nations's name may not be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ****************************************************************************/
+/*****************************************************************************
+* 文件å :bass_task.c
+* 功能æè¿°:
+* 版本:V 1.0.0
+* 作者:
+* 日期:
+* ****************************************************************************/
+
+/**
+ ****************************************************************************************
+ * @addtogroup BASSTASK
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+
+#include "rwip_config.h"
+
+#if (BLE_BATT_SERVER)
+
+#include "gap.h"
+#include "gattc_task.h"
+
+#include "bass.h"
+#include "bass_task.h"
+
+#include "prf_utils.h"
+
+#include "co_utils.h"
+
+/*
+ * GLOBAL FUNCTIONS DEFINITIONS
+ ****************************************************************************************
+ */
+
+
+/**
+ ****************************************************************************************
+ * @brief Handles reception of the @ref BAPS_ENABLE_REQ message.
+ * The handler enables the Battery 'Profile' Server Role.
+ * @param[in] msgid Id of the message received (probably unused).
+ * @param[in] param Pointer to the parameters of the message.
+ * @param[in] dest_id ID of the receiving task instance (probably unused).
+ * @param[in] src_id ID of the sending task instance.
+ * @return If the message was consumed or not.
+ ****************************************************************************************
+ */
+static int bass_enable_req_handler(ke_msg_id_t const msgid,struct bass_enable_req const *param,ke_task_id_t const dest_id,ke_task_id_t const src_id)
+{
+
+ int msg_status = KE_MSG_SAVED;
+ uint8_t state = ke_state_get(dest_id);
+ uint8_t conidx = KE_IDX_GET(src_id);
+ // check state of the task
+ if (state == BASS_IDLE)
+ {
+ struct bass_env_tag* bass_env = PRF_ENV_GET(BASS, bass);
+ // Check provided values
+ if ((param->conidx > BLE_CONNECTION_MAX) || (gapc_get_conhdl(param->conidx) == GAP_INVALID_CONHDL))
+ {
+ // an error occurs, trigg it.
+ struct bass_enable_rsp* rsp = KE_MSG_ALLOC(BASS_ENABLE_RSP, src_id,dest_id, bass_enable_rsp);
+ rsp->conidx = param->conidx;
+ rsp->status = (param->conidx > BLE_CONNECTION_MAX) ? GAP_ERR_INVALID_PARAM : PRF_ERR_REQ_DISALLOWED;
+ ke_msg_send(rsp);
+ msg_status = KE_MSG_CONSUMED;
+ }
+ else
+ {
+ // put task in a busy state
+ msg_status = KE_MSG_NO_FREE;
+ ke_state_set(dest_id, BASS_BUSY);
+ bass_env->batt_lvl[conidx] = param->old_batt_lvl[conidx];
+ bass_env->ntf_cfg[param->conidx] = param->ntf_cfg;
+ bass_env->operation = ke_param2msg(param);
+ bass_env->cursor = 0;
+ // trigger notification
+ bass_exe_operation();
+ }
+ }
+ return msg_status;
+}
+
+/**
+ ****************************************************************************************
+ * @brief Handles reception of the @ref BAPS_BATT_LEVEL_SEND_REQ message.
+ * @param[in] msgid Id of the message received (probably unused).
+ * @param[in] param Pointer to the parameters of the message.
+ * @param[in] dest_id ID of the receiving task instance (probably unused).
+ * @param[in] src_id ID of the sending task instance.
+ * @return If the message was consumed or not.
+ ****************************************************************************************
+ */
+static int bass_batt_level_upd_req_handler(ke_msg_id_t const msgid,struct bass_batt_level_upd_req const *param,ke_task_id_t const dest_id,ke_task_id_t const src_id)
+{
+
+
+ int msg_status = KE_MSG_SAVED;
+ uint8_t state = ke_state_get(dest_id);
+ // check state of the task
+ if (state == BASS_IDLE)
+ {
+ struct bass_env_tag* bass_env = PRF_ENV_GET(BASS, bass);
+ // Check provided values
+ if ((param->bas_instance < bass_env->svc_nb) && (param->batt_level <= BAS_BATTERY_LVL_MAX))
+ {
+ // update the battery level value
+ bass_env->batt_lvl[param->bas_instance] = param->batt_level;
+ // put task in a busy state
+ msg_status = KE_MSG_NO_FREE;
+ ke_state_set(dest_id, BASS_BUSY);
+ bass_env->operation = ke_param2msg(param);
+ bass_env->cursor = 0;
+ // trigger notification
+ bass_exe_operation();
+ }
+ else
+ {
+ // an error occurs, trigg it.
+ struct bass_batt_level_upd_rsp * rsp = KE_MSG_ALLOC(BASS_BATT_LEVEL_UPD_RSP, src_id,dest_id, bass_batt_level_upd_rsp);
+ rsp->status = PRF_ERR_INVALID_PARAM;
+ ke_msg_send(rsp);
+ msg_status = KE_MSG_CONSUMED;
+ }
+ }
+ return (msg_status);
+}
+
+/**
+ ****************************************************************************************
+ * @brief Handles reception of the attribute info request message.
+ *
+ * @param[in] msgid Id of the message received (probably unused).
+ * @param[in] param Pointer to the parameters of the message.
+ * @param[in] dest_id ID of the receiving task instance (probably unused).
+ * @param[in] src_id ID of the sending task instance.
+ * @return If the message was consumed or not.
+ ****************************************************************************************
+ */
+static int gattc_att_info_req_ind_handler(ke_msg_id_t const msgid,struct gattc_att_info_req_ind *param,ke_task_id_t const dest_id,ke_task_id_t const src_id)
+{
+
+ struct gattc_att_info_cfm * cfm;
+ uint8_t svc_idx = 0, att_idx = 0;
+ // retrieve handle information
+ uint8_t status = bass_get_att_idx(param->handle, &svc_idx, &att_idx);
+ //Send write response
+ cfm = KE_MSG_ALLOC(GATTC_ATT_INFO_CFM, src_id, dest_id, gattc_att_info_cfm);
+ cfm->handle = param->handle;
+ if (status == GAP_ERR_NO_ERROR)
+ {
+ // check if it's a client configuration char
+ if (att_idx == BAS_IDX_BATT_LVL_NTF_CFG)
+ {
+ // CCC attribute length = 2
+ cfm->length = 2;
+ }
+ // not expected request
+ else
+ {
+ cfm->length = 0;
+ status = ATT_ERR_WRITE_NOT_PERMITTED;
+ }
+ }
+ cfm->status = status;
+ ke_msg_send(cfm);
+ return (KE_MSG_CONSUMED);
+}
+
+
+/**
+ ****************************************************************************************
+ * @brief Handles reception of the @ref GATTC_WRITE_REQ_IND message.
+ * @param[in] msgid Id of the message received (probably unused).
+ * @param[in] param Pointer to the parameters of the message.
+ * @param[in] dest_id ID of the receiving task instance (probably unused).
+ * @param[in] src_id ID of the sending task instance.
+ * @return If the message was consumed or not.
+ ****************************************************************************************
+ */
+static int gattc_write_req_ind_handler(ke_msg_id_t const msgid, struct gattc_write_req_ind const *param,ke_task_id_t const dest_id, ke_task_id_t const src_id)
+{
+
+ struct gattc_write_cfm * cfm;
+ uint8_t svc_idx = 0, att_idx = 0;
+ uint8_t conidx = KE_IDX_GET(src_id);
+ // retrieve handle information
+ uint8_t status = bass_get_att_idx(param->handle, &svc_idx, &att_idx);
+ // If the attribute has been found, status is GAP_ERR_NO_ERROR
+ if (status == GAP_ERR_NO_ERROR)
+ {
+ struct bass_env_tag* bass_env = PRF_ENV_GET(BASS, bass);
+ // Extract value before check
+ uint16_t ntf_cfg = co_read16p(¶m->value[0]);
+ // Only update configuration if value for stop or notification enable
+ if ((att_idx == BAS_IDX_BATT_LVL_NTF_CFG)&& ((ntf_cfg == PRF_CLI_STOP_NTFIND) || (ntf_cfg == PRF_CLI_START_NTF)))
+ {
+ // Conserve information in environment
+ if (ntf_cfg == PRF_CLI_START_NTF)
+ {
+ // Ntf cfg bit set to 1
+ bass_env->ntf_cfg[conidx] |= (BAS_BATT_LVL_NTF_SUP << svc_idx);
+ }
+ else
+ {
+ // Ntf cfg bit set to 0
+ bass_env->ntf_cfg[conidx] &= ~(BAS_BATT_LVL_NTF_SUP << svc_idx);
+ }
+
+ // Inform APP of configuration change
+ struct bass_batt_level_ntf_cfg_ind * ind = KE_MSG_ALLOC(BASS_BATT_LEVEL_NTF_CFG_IND,prf_dst_task_get(&(bass_env->prf_env), conidx), dest_id,bass_batt_level_ntf_cfg_ind);
+ ind->conidx = conidx;
+ ind->ntf_cfg = bass_env->ntf_cfg[conidx];
+ ke_msg_send(ind);
+ }
+ else
+ {
+ status = PRF_APP_ERROR;
+ }
+ }
+ //Send write response
+ cfm = KE_MSG_ALLOC(GATTC_WRITE_CFM, src_id, dest_id, gattc_write_cfm);
+ cfm->handle = param->handle;
+ cfm->status = status;
+ ke_msg_send(cfm);
+ return (KE_MSG_CONSUMED);
+}
+
+
+/**
+ ****************************************************************************************
+ * @brief Handles reception of the @ref GATTC_READ_REQ_IND message.
+ * @param[in] msgid Id of the message received (probably unused).
+ * @param[in] param Pointer to the parameters of the message.
+ * @param[in] dest_id ID of the receiving task instance (probably unused).
+ * @param[in] src_id ID of the sending task instance.
+ * @return If the message was consumed or not.
+ ****************************************************************************************
+ */
+static int gattc_read_req_ind_handler(ke_msg_id_t const msgid, struct gattc_read_req_ind const *param,ke_task_id_t const dest_id, ke_task_id_t const src_id)
+{
+
+ struct gattc_read_cfm * cfm;
+ uint8_t svc_idx = 0, att_idx = 0;
+ uint8_t conidx = KE_IDX_GET(src_id);
+ // retrieve handle information
+ uint8_t status = bass_get_att_idx(param->handle, &svc_idx, &att_idx);
+ uint16_t length = 0;
+ struct bass_env_tag* bass_env = PRF_ENV_GET(BASS, bass);
+ // If the attribute has been found, status is GAP_ERR_NO_ERROR
+ if (status == GAP_ERR_NO_ERROR)
+ {
+ // read notification information
+ if (att_idx == BAS_IDX_BATT_LVL_VAL)
+ {
+ length = sizeof(uint8_t);
+ }
+ // read notification information
+ else if (att_idx == BAS_IDX_BATT_LVL_NTF_CFG)
+ {
+ length = sizeof(uint16_t);
+ }
+ else if (att_idx == BAS_IDX_BATT_LVL_PRES_FMT)
+ {
+ length = PRF_CHAR_PRES_FMT_SIZE;
+ }
+ else
+ {
+ status = PRF_APP_ERROR;
+ }
+ }
+ //Send write response
+ cfm = KE_MSG_ALLOC_DYN(GATTC_READ_CFM, src_id, dest_id, gattc_read_cfm, length);
+ cfm->handle = param->handle;
+ cfm->status = status;
+ cfm->length = length;
+
+ if (status == GAP_ERR_NO_ERROR)
+ {
+ // read notification information
+ if (att_idx == BAS_IDX_BATT_LVL_VAL)
+ {
+ cfm->value[conidx] = bass_env->batt_lvl[svc_idx]; //read batt_lvel
+ }
+ // retrieve notification config
+ else if (att_idx == BAS_IDX_BATT_LVL_NTF_CFG)
+ {
+ uint16_t ntf_cfg = (bass_env->ntf_cfg[conidx] >> svc_idx & BAS_BATT_LVL_NTF_SUP) ? PRF_CLI_START_NTF : PRF_CLI_STOP_NTFIND;
+ co_write16p(cfm->value, ntf_cfg);
+ }
+ // retrieve battery level format
+ else if (att_idx == BAS_IDX_BATT_LVL_PRES_FMT)
+ {
+ prf_pack_char_pres_fmt(cfm->value, &(bass_env->batt_level_pres_format[svc_idx]));
+ }
+ else
+ {
+ /* Not Possible */
+ }
+ }
+ ke_msg_send(cfm);
+ return (KE_MSG_CONSUMED);
+}
+/**
+ ****************************************************************************************
+ * @brief Handles @ref GATTC_CMP_EVT for GATTC_NOTIFY message meaning that Measurement
+ * notification has been correctly sent to peer device (but not confirmed by peer device).
+ * *
+ * @param[in] msgid Id of the message received.
+ * @param[in] param Pointer to the parameters of the message.
+ * @param[in] dest_id ID of the receiving task instance
+ * @param[in] src_id ID of the sending task instance.
+ * @return If the message was consumed or not.
+ ****************************************************************************************
+ */
+static int gattc_cmp_evt_handler(ke_msg_id_t const msgid, struct gattc_cmp_evt const *param,ke_task_id_t const dest_id, ke_task_id_t const src_id)
+{
+
+ if (param->operation == GATTC_NOTIFY)
+ {
+ // continue operation execution
+ bass_exe_operation();
+ }
+ return (KE_MSG_CONSUMED);
+}
+
+/*
+ * GLOBAL VARIABLE DEFINITIONS
+ ****************************************************************************************
+ */
+
+/// Default State handlers definition
+const struct ke_msg_handler bass_default_state[] =
+{
+ {BASS_ENABLE_REQ, (ke_msg_func_t) bass_enable_req_handler},
+ {BASS_BATT_LEVEL_UPD_REQ, (ke_msg_func_t) bass_batt_level_upd_req_handler},
+ {GATTC_ATT_INFO_REQ_IND, (ke_msg_func_t) gattc_att_info_req_ind_handler},
+ {GATTC_WRITE_REQ_IND, (ke_msg_func_t) gattc_write_req_ind_handler},
+ {GATTC_READ_REQ_IND, (ke_msg_func_t) gattc_read_req_ind_handler},
+ {GATTC_CMP_EVT, (ke_msg_func_t) gattc_cmp_evt_handler},
+};
+
+/// Specifies the message handlers that are common to all states.
+const struct ke_state_handler bass_default_handler = KE_STATE_HANDLER(bass_default_state);
+
+#endif /* #if (BLE_BATT_SERVER) */
+
+/// @} BASSTASK
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app.h
new file mode 100644
index 0000000000..6c4dd7583c
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app.h
@@ -0,0 +1,386 @@
+/**
+ ****************************************************************************************
+ *
+ * @file app.h
+ *
+ * @brief Application entry point
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef APP_H_
+#define APP_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup APP
+ * @ingroup RICOW
+ *
+ * @brief Application entry point.
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+
+#include "rwip_config.h" // SW configuration
+
+#if (BLE_APP_PRESENT)
+
+#include // Standard Integer Definition
+#include // Common BT Definitions
+#include "ble_arch.h"
+#include "gapc.h" // GAPC Definitions
+#include "gap.h"
+
+#if (NVDS_SUPPORT)
+#include "nvds.h"
+#endif // (NVDS_SUPPORT)
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+/// Maximal length of the Device Name value
+#define APP_DEVICE_NAME_MAX_LEN (16)
+
+/*
+ * TYPE DEFINITIONS
+ ****************************************************************************************
+ */
+
+#if (NVDS_SUPPORT)
+#ifdef default
+/// List of Application NVDS TAG identifiers
+enum app_nvds_tag
+{
+ /// BLE Application Advertising data
+ NVDS_TAG_APP_BLE_ADV_DATA = 0x0B,
+ NVDS_LEN_APP_BLE_ADV_DATA = 32,
+
+ /// BLE Application Scan response data
+ NVDS_TAG_APP_BLE_SCAN_RESP_DATA = 0x0C,
+ NVDS_LEN_APP_BLE_SCAN_RESP_DATA = 32,
+
+ /// Mouse Sample Rate
+ NVDS_TAG_MOUSE_SAMPLE_RATE = 0x38,
+ NVDS_LEN_MOUSE_SAMPLE_RATE = 1,
+ /// Peripheral Bonded
+ NVDS_TAG_PERIPH_BONDED = 0x39,
+ NVDS_LEN_PERIPH_BONDED = 1,
+ /// Mouse NTF Cfg
+ NVDS_TAG_MOUSE_NTF_CFG = 0x3A,
+ NVDS_LEN_MOUSE_NTF_CFG = 2,
+ /// Mouse Timeout value
+ NVDS_TAG_MOUSE_TIMEOUT = 0x3B,
+ NVDS_LEN_MOUSE_TIMEOUT = 2,
+ /// Peer Device BD Address
+ NVDS_TAG_PEER_BD_ADDRESS = 0x3C,
+ NVDS_LEN_PEER_BD_ADDRESS = 7,
+ /// Mouse Energy Safe
+ NVDS_TAG_MOUSE_ENERGY_SAFE = 0x3D,
+ NVDS_LEN_MOUSE_SAFE_ENERGY = 2,
+ /// EDIV (2bytes), RAND NB (8bytes), LTK (16 bytes), Key Size (1 byte)
+ NVDS_TAG_LTK = 0x3E,
+ NVDS_LEN_LTK = 28,
+ /// PAIRING
+ NVDS_TAG_PAIRING = 0x3F,
+ NVDS_LEN_PAIRING = 54,
+};
+#else
+enum app_nvds_tag
+{
+ /// BLE Application Advertising data
+ NVDS_TAG_APP_BLE_ADV_DATA = 0x0B,
+ NVDS_LEN_APP_BLE_ADV_DATA = 32,
+
+ /// BLE Application Scan response data
+ NVDS_TAG_APP_BLE_SCAN_RESP_DATA = 0x0C,
+ NVDS_LEN_APP_BLE_SCAN_RESP_DATA = 32,
+
+ /// Peripheral Bonded
+ NVDS_TAG_PERIPH_BONDED = 0x39,
+ NVDS_LEN_PERIPH_BONDED = 1,
+
+ /// Peer Device BD Address
+ NVDS_TAG_PEER_BD_ADDRESS = 0x3A,
+ NVDS_LEN_PEER_BD_ADDRESS = 7,
+
+ NVDS_TAG_PEER_BD_ADDRESS1 = 0x3B,
+ NVDS_LEN_PEER_BD_ADDRESS1 = 7,
+
+ NVDS_TAG_PEER_BD_ADDRESS2 = 0x3C,
+ NVDS_LEN_PEER_BD_ADDRESS2 = 7,
+
+ NVDS_TAG_PEER_BD_ADDRESS3 = 0x3D,
+ NVDS_LEN_PEER_BD_ADDRESS3 = 7,
+
+ NVDS_TAG_PEER_BD_ADDRESS4 = 0x3E,
+ NVDS_LEN_PEER_BD_ADDRESS4 = 7,
+
+ NVDS_TAG_DEVICE_NUM = 0x3F,
+ NVDS_LEN_DEVICE_NUM = 1,
+
+ /// EDIV (2bytes), RAND NB (8bytes), LTK (16 bytes), Key Size (1 byte)
+ NVDS_TAG_LTK = 0x40,
+ NVDS_LEN_LTK = 28,
+
+ NVDS_TAG_LTK1 = 0x41,
+ NVDS_LEN_LTK1 = 28,
+
+ NVDS_TAG_LTK2 = 0x42,
+ NVDS_LEN_LTK2 = 28,
+
+ NVDS_TAG_LTK3 = 0x43,
+ NVDS_LEN_LTK3 = 28,
+
+ NVDS_TAG_LTK4 = 0x44,
+ NVDS_LEN_LTK4 = 28,
+
+};
+
+#endif
+enum app_loc_nvds_tag
+{
+ /// Audio mode 0 task
+ NVDS_TAG_AM0_FIRST = NVDS_TAG_APP_SPECIFIC_FIRST,
+
+ NVDS_TAG_AM0_LAST = NVDS_TAG_APP_SPECIFIC_FIRST+16,
+
+ /// Local device Identity resolving key
+ NVDS_TAG_LOC_IRK,
+ /// Peer device Resolving identity key (+identity address)
+ NVDS_TAG_PEER_IRK,
+ /// size of local identity resolving key
+ NVDS_LEN_LOC_IRK = KEY_LEN,
+ /// size of Peer device identity resolving key (+identity address)
+ NVDS_LEN_PEER_IRK = sizeof(struct gapc_irk),
+};
+#endif // (NVDS_SUPPORT)
+
+/************************************************************************************************/
+//add by bottle.mao
+
+#define BD_ADDR_LEN 6
+
+typedef uint8_t bd_addr[BD_ADDR_LEN];
+
+
+
+
+
+
+//add by bottle.mao
+struct devicc_adv_parameter
+{
+ //advert_data
+ uint16_t adv_int_min;
+
+ uint16_t adv_int_max;
+
+ uint8_t adv_type;
+
+ uint8_t addr_type_own;
+
+ uint8_t channel_map;
+
+ uint8_t adv_filter_policy;
+
+ uint8_t discover_mode;
+};
+
+
+
+
+
+
+#define RX_DAT_BUF_SIZE 320
+
+struct RX_BUF_S
+{
+ uint16_t RxCurrentLen;
+ uint16_t RxTotalLen;
+ // received data value
+#ifndef N32WB452_BT_API
+ uint8_t RxBuf[RX_DAT_BUF_SIZE];
+#endif
+ // received data length
+};
+
+/************************************************************************************************/
+
+/// Application environment structure
+struct app_env_tag
+{
+
+
+ /// send data timesout
+ uint32_t timesout;
+
+ /// Connection handle
+ uint16_t conhdl;
+ /// Connection interval
+ uint16_t con_interval;
+ uint16_t con_intv_min;
+ uint16_t con_intv_max;
+ uint16_t con_latency;
+ uint16_t con_time_out;
+ /// Advertising parameter
+ struct devicc_adv_parameter adv_para;
+
+ /// MTU
+ uint16_t max_mtu;
+ /// Received data information
+ struct RX_BUF_S rx_data;
+
+
+ /// Connection Index
+ uint8_t conidx;
+
+ /// Last initialized profile
+ uint8_t next_svc;
+
+ /// Bonding status
+ bool bonded;
+
+ /// Device Name length
+ uint8_t dev_name_len;
+ /// Device Name
+ uint8_t dev_name[APP_DEVICE_NAME_MAX_LEN];
+
+
+ /// Counter used to generate IRK
+ uint8_t rand_cnt;
+ /// Local device IRK
+ uint8_t loc_irk[KEY_LEN];
+
+/*******************************************************************************/
+ /// Connection security enable
+ bool security_enable;
+
+/// receivce data flag
+ uint8_t rec_flag;
+
+//*******************************************************************************/
+/// Pairing mode
+ uint8_t pairing_mode;
+/// sec iocap
+ uint8_t iocap;
+/// Pin code required
+ uint32_t pin_code;
+
+
+/// RSSI value
+ int8_t rssi;
+
+/// White List size
+ uint8_t wlst_size;
+
+/// current connect device number
+ uint8_t con_device_num;
+
+/// local device bda
+ struct bd_addr bdaddr;
+/// addr type
+ uint8_t bdaddr_type;
+
+/// adv data buf
+ uint8_t adv_data_buf[31];
+/// adv data buf len
+ uint8_t adv_data_len;
+
+/// scan response data buf
+ uint8_t scan_rsp_data_buf[31];
+
+/// scan response data buf len
+ uint8_t scan_rsp_data_len;
+
+/// battery level
+ uint8_t batt_lvl;
+
+
+
+/*******************************************************************************/
+};
+
+
+
+/// Application environment
+extern struct app_env_tag app_env;
+
+
+
+/**
+ ****************************************************************************************
+ * @brief Initialize the BLE demo application.
+ ****************************************************************************************
+ */
+void appm_init(void);
+
+/**
+ ****************************************************************************************
+ * @brief Add a required service in the database
+ ****************************************************************************************
+ */
+bool appm_add_svc(void);
+
+/**
+ ****************************************************************************************
+ * @brief Put the device in general discoverable and connectable mode
+ ****************************************************************************************
+ */
+void appm_start_advertising(void);
+
+/**
+ ****************************************************************************************
+ * @brief Put the device in non discoverable and non connectable mode
+ ****************************************************************************************
+ */
+void appm_stop_advertising(void);
+
+/**
+ ****************************************************************************************
+ * @brief Send to request to update the connection parameters
+ ****************************************************************************************
+ */
+void appm_update_param(struct gapc_conn_param *conn_param);
+
+void appm_set_mtu(void);
+
+/**
+ ****************************************************************************************
+ * @brief Send a disconnection request
+ ****************************************************************************************
+ */
+void appm_disconnect(void);
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve device name
+ *
+ * @param[out] device name
+ *
+ * @return name length
+ ****************************************************************************************
+ */
+uint8_t appm_get_dev_name(uint8_t* name);
+
+
+/**
+ ****************************************************************************************
+ * @brief Return if the device is currently bonded
+ ****************************************************************************************
+ */
+bool app_sec_get_bond_status(void);
+
+
+#endif
+
+#endif
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app_batt.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app_batt.h
new file mode 100644
index 0000000000..dc23bd6387
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app_batt.h
@@ -0,0 +1,110 @@
+/**
+ ****************************************************************************************
+ *
+ * @file app_batt.h
+ *
+ * @brief Battery Application Module entry point
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef APP_BATT_H_
+#define APP_BATT_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup APP
+ * @ingroup RICOW
+ *
+ * @brief Battery Application Module entry point
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+
+#include "rwip_config.h" // SW configuration
+
+#if (BLE_APP_BATT)
+
+#include // Standard Integer Definition
+#include "ke_task.h" // Kernel Task Definition
+
+/*
+ * STRUCTURES DEFINITION
+ ****************************************************************************************
+ */
+
+/// Battery Application Module Environment Structure
+struct app_batt_env_tag
+{
+ /// Connection handle
+ uint8_t conidx;
+ /// Current Battery Level
+ uint8_t batt_lvl;
+};
+
+/*
+ * GLOBAL VARIABLES DECLARATIONS
+ ****************************************************************************************
+ */
+
+/// Battery Application environment
+extern struct app_batt_env_tag app_batt_env;
+
+/// Table of message handlers
+extern const struct ke_state_handler app_batt_table_handler;
+
+/*
+ * FUNCTIONS DECLARATION
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ *
+ * Health Thermometer Application Functions
+ *
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief Initialize Battery Application Module
+ ****************************************************************************************
+ */
+void app_batt_init(void);
+
+/**
+ ****************************************************************************************
+ * @brief Add a Battery Service instance in the DB
+ ****************************************************************************************
+ */
+void app_batt_add_bas(void);
+
+/**
+ ****************************************************************************************
+ * @brief Enable the Battery Service
+ ****************************************************************************************
+ */
+void app_batt_enable_prf(uint8_t conidx);
+
+/**
+ ****************************************************************************************
+ * @brief Send a Battery level value
+ ****************************************************************************************
+ */
+void app_batt_send_lvl(uint8_t batt_lvl);
+
+#endif //(BLE_APP_BATT)
+
+/// @} APP
+
+#endif // APP_BATT_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app_sec.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app_sec.h
new file mode 100644
index 0000000000..1bb3a8cc30
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app_sec.h
@@ -0,0 +1,100 @@
+/**
+ ****************************************************************************************
+ *
+ * @file app_sec.h
+ *
+ * @brief Application Security Entry Point
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @addtogroup APP_SEC
+ * @{
+ ****************************************************************************************
+ */
+
+#ifndef APP_SEC_H_
+#define APP_SEC_H_
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "stdbool.h"
+#include "rwip_config.h"
+
+#if (BLE_APP_SEC)
+
+#include // Standard Integer Definition
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/*
+ * STRUCTURES DEFINITIONS
+ ****************************************************************************************
+ */
+
+struct app_sec_env_tag
+{
+ // Bond status
+ bool bonded;
+ uint8_t device_num;
+};
+
+/*
+ * GLOBAL VARIABLE DECLARATIONS
+ ****************************************************************************************
+ */
+
+/// Application Security Environment
+extern struct app_sec_env_tag app_sec_env;
+
+/// Table of message handlers
+extern const struct ke_state_handler app_sec_table_handler;
+
+/*
+ * GLOBAL FUNCTIONS DECLARATIONS
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief Initialize the Application Security Module
+ ****************************************************************************************
+ */
+void app_sec_init(void);
+
+
+#if (NVDS_SUPPORT)
+/**
+ ****************************************************************************************
+ * @brief Remove all bond data stored in NVDS
+ ****************************************************************************************
+ */
+void app_sec_remove_bond(void);
+#endif //(NVDS_SUPPORT)
+
+/**
+ ****************************************************************************************
+ * @brief Send a security request to the peer device. This function is used to require the
+ * central to start the encryption with a LTK that would have shared during a previous
+ * bond procedure.
+ *
+ * @param[in] - conidx: Connection Index
+ ****************************************************************************************
+ */
+void app_sec_send_security_req(uint8_t conidx);
+
+#endif //(BLE_APP_SEC)
+
+#endif // APP_SEC_H_
+
+/// @} APP_SEC
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app_task.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app_task.h
new file mode 100644
index 0000000000..779c69802e
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app_task.h
@@ -0,0 +1,110 @@
+/**
+ ****************************************************************************************
+ *
+ * @file app_task.h
+ *
+ * @brief Header file - APPTASK.
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef APP_TASK_H_
+#define APP_TASK_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup APPTASK Task
+ * @ingroup APP
+ * @brief Routes ALL messages to/from APP block.
+ *
+ * The APPTASK is the block responsible for bridging the final application with the
+ * RWBLE software host stack. It communicates with the different modules of the BLE host,
+ * i.e. @ref SMP, @ref GAP and @ref GATT.
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+
+#include "rwip_config.h" // SW configuration
+
+#if (BLE_APP_PRESENT)
+
+#include // Standard Integer
+#include "rwip_task.h" // Task definitions
+#include "ke_task.h" // Kernel Task
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/// Number of APP Task Instances
+#define APP_IDX_MAX (1)
+
+/*
+ * ENUMERATIONS
+ ****************************************************************************************
+ */
+
+/// States of APP task
+enum appm_state
+{
+ /// Initialization state
+ APPM_INIT,
+ /// Database create state
+ APPM_CREATE_DB,
+ /// Ready State
+ APPM_READY,
+ /// Advertising state
+ APPM_ADVERTISING,
+ /// Connected state
+ APPM_CONNECTED,
+ /// start encypt
+ APPM_START_ENC,
+ /// BO
+ APPM_ENCRYPTED,
+ /// Number of defined states.
+ APPM_STATE_MAX
+};
+
+/// APP Task messages
+enum appm_msg
+{
+ APPM_DUMMY_MSG = TASK_FIRST_MSG(TASK_ID_APP),
+
+ /// Timer used to automatically stop advertising
+ APP_ADV_TIMEOUT_TIMER,
+
+ #if (BLE_APP_HT)
+ /// Timer used to refresh the temperature measurement value
+ APP_HT_MEAS_INTV_TIMER,
+ #endif //(BLE_APP_HT)
+
+ #if (BLE_APP_HID)
+ /// Timer used to disconnect the moue if no activity is detecter
+ APP_HID_MOUSE_TIMEOUT_TIMER,
+ #endif //(BLE_APP_HID)
+};
+
+
+/*
+ * GLOBAL VARIABLE DECLARATIONS
+ ****************************************************************************************
+ */
+
+extern const struct ke_state_handler appm_default_handler;
+extern ke_state_t appm_state[APP_IDX_MAX];
+
+/// @} APPTASK
+
+#endif //(BLE_APP_PRESENT)
+
+#endif // APP_TASK_H_
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app_user.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app_user.h
new file mode 100644
index 0000000000..dcf73a3bfe
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app_user.h
@@ -0,0 +1,127 @@
+/**
+ ****************************************************************************************
+ *
+ * @file app_user.h
+ *
+ * @brief user-defined service entry point
+ *
+ * Copyright (C) RivieraWaves 2009-2015
+ *
+ *
+ ****************************************************************************************
+ */
+#ifndef APP_USER_H_
+#define APP_USER_H_
+
+
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+
+#include "rwip_config.h" // SW configuration
+
+#if (BLE_APP_USER)
+
+#include // Standard Integer Definition
+#include "ke_task.h"
+#include "att.h"
+
+/*
+ * TYPE DEFINITIONS
+ ****************************************************************************************
+ */
+extern struct app_env_tag app_env;
+
+/// health thermometer application environment structure
+struct app_user_rev_tag
+{
+ //todo
+ uint16_t length;
+
+ // uint8_t data[ATT_VALUE_LEN_MAX/*__ARRAY_EMPTY*/];
+
+ uint16_t receive_length;
+
+ uint8_t *receive_data;
+
+ bool receive_flag;
+
+ bool receive_header;
+
+ uint16_t receive_current_length;
+};
+
+/*
+ * GLOBAL VARIABLES DECLARATIONS
+ ****************************************************************************************
+ */
+
+/// Health Thermomter Application environment
+//extern struct app_user_env_tag app_user_env;
+
+/// Table of message handlers
+extern struct app_user_rev_tag app_user_env;
+
+extern const struct ke_state_handler app_user_table_handler;
+
+/*
+ * FUNCTIONS DECLARATION
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ *
+ * Health Thermometer Application Functions
+ *
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief Initialize Health Thermometer Application
+ ****************************************************************************************
+ */
+void app_user_init(void);
+
+/**
+ ****************************************************************************************
+ * @brief Add a Health Thermometer instance in the DB
+ ****************************************************************************************
+ */
+void app_user_add_users(void);
+
+/**
+ ****************************************************************************************
+ * @brief Stop the interval measurement timer if used
+ ****************************************************************************************
+ */
+void app_stop_timer (void);
+
+/**
+ ****************************************************************************************
+ * @brief Enable the health thermometer profile
+ ****************************************************************************************
+ */
+//void app_user_enable_prf(uint8_t conidx);
+
+void app_user_data_send(void);
+
+void app_user_mtu_temp_send(uint16_t mtu);
+
+void app_user_updata_temp_send(uint8_t status);//,uint16_t intv_min, uint16_t intv_max, uint16_t latancy, uint16_t timesout);
+
+void app_user_data_rec(uint16_t param_length , uint8_t * param_payload);
+
+
+uint8_t app_user_data_notify(uint16_t param_length , uint8_t * param_payload, uint8_t att_idx);
+
+
+#endif //(BLE_APP_USER)
+
+/// @} APP
+
+#endif // APP_HT_H_
+
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/bass.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/bass.h
new file mode 100644
index 0000000000..ebdf2b2973
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/bass.h
@@ -0,0 +1,178 @@
+/**
+ ****************************************************************************************
+ *
+ * @file bass.h
+ *
+ * @brief Header file - Battery Service Server Role
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef _BASS_H_
+#define _BASS_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup BAPS Battery 'Profile' Server
+ * @ingroup BAP
+ * @brief Battery 'Profile' Server
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "rwip_config.h"
+
+#if (BLE_BATT_SERVER)
+
+#include "bass_task.h"
+#include "prf_types.h"
+#include "prf.h"
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+///Maximum number of Battery Server task instances
+#define BASS_IDX_MAX 0x01
+
+#define BAS_CFG_FLAG_MANDATORY_MASK (0x07)
+#define BAS_CFG_FLAG_NTF_SUP_MASK (0x08)
+#define BAS_CFG_FLAG_MTP_BAS_MASK (0x10)
+
+#define BASS_FLAG_NTF_CFG_BIT (0x02)
+
+/*
+ * ENUMERATIONS
+ ****************************************************************************************
+ */
+
+/// Possible states of the BASS task
+enum bass_state
+{
+ /// Idle state
+ BASS_IDLE,
+ /// busy state
+ BASS_BUSY,
+ /// Number of defined states.
+ BASS_STATE_MAX
+};
+
+/// Battery Service Attributes Indexes
+enum
+{
+ BAS_IDX_SVC,
+
+ BAS_IDX_BATT_LVL_CHAR,
+ BAS_IDX_BATT_LVL_VAL,
+ BAS_IDX_BATT_LVL_NTF_CFG,
+ BAS_IDX_BATT_LVL_PRES_FMT,
+
+ BAS_IDX_NB,
+};
+
+/*
+ * TYPE DEFINITIONS
+ ****************************************************************************************
+ */
+
+/// Battery 'Profile' Server environment variable
+struct bass_env_tag
+{
+ /// profile environment
+ prf_env_t prf_env;
+ /// Battery Level Characteristic Presentation Format - Should not change during connection
+ struct prf_char_pres_fmt batt_level_pres_format[BASS_NB_BAS_INSTANCES_MAX];
+ /// On-going operation
+ struct ke_msg * operation;
+ /// BAS Services Start Handle
+ uint16_t start_hdl;
+ /// Level of the battery
+ uint8_t batt_lvl[BASS_NB_BAS_INSTANCES_MAX];
+ /// BASS task state
+ ke_state_t state[BASS_IDX_MAX];
+ /// Notification configuration of peer devices.
+ uint8_t ntf_cfg[BLE_CONNECTION_MAX];
+ /// Database features
+ uint8_t features;
+ /// Number of BAS
+ uint8_t svc_nb;
+ /// Cursor on connection used to notify peer devices when battery level changes
+ uint8_t cursor;
+};
+
+/*
+ * GLOBAL VARIABLE DECLARATIONS
+ ****************************************************************************************
+ */
+
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve BAS service profile interface
+ *
+ * @return BAS service profile interface
+ ****************************************************************************************
+ */
+const struct prf_task_cbs* bass_prf_itf_get(void);
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve Attribute handle from service and attribute index
+ *
+ * @param[in] svc_idx BAS Service index
+ * @param[in] att_idx Attribute index
+ *
+ * @return BAS attribute handle or INVALID HANDLE if nothing found
+ ****************************************************************************************
+ */
+uint16_t bass_get_att_handle(uint8_t svc_idx, uint8_t att_idx);
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve Service and attribute index form attribute handle
+ *
+ * @param[out] handle Attribute handle
+ * @param[out] svc_idx BAS Service index
+ * @param[out] att_idx Attribute index
+ *
+ * @return Success if attribute and service index found, else Application error
+ ****************************************************************************************
+ */
+uint8_t bass_get_att_idx(uint16_t handle, uint8_t *svc_idx, uint8_t *att_idx);
+
+/**
+ ****************************************************************************************
+ * @brief This function fully manage notification of battery level to peer(s) device(s)
+ * according to on-going operation requested by application:
+ * - Modification of Battery Level
+ * - Indicate to a known device that battery level has change
+ ****************************************************************************************
+ */
+void bass_exe_operation(void);
+
+/*
+ * TASK DESCRIPTOR DECLARATIONS
+ ****************************************************************************************
+ */
+
+extern const struct ke_state_handler bass_default_handler;
+
+
+#endif /* #if (BLE_BATT_SERVER) */
+
+/// @} BASS
+
+#endif /* _BASS_H_ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/bass_task.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/bass_task.h
new file mode 100644
index 0000000000..0c7766e8c7
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/bass_task.h
@@ -0,0 +1,144 @@
+/**
+ ****************************************************************************************
+ *
+ * @file bass_task.h
+ *
+ * @brief Header file - Battery Service Server Role Task.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+
+#ifndef _BASS_TASK_H_
+#define _BASS_TASK_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup BAPSTASK Task
+ * @ingroup BAPS
+ * @brief Battery 'Profile' Task.
+ *
+ * The BAPS_TASK is responsible for handling the messages coming in and out of the
+ * @ref BAPS block of the BLE Host.
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "prf_types.h"
+#include "rwip_task.h" // Task definitions
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+#define BAS_BATTERY_LVL_MAX (100)
+
+
+///Maximal number of BAS that can be added in the DB
+#define BASS_NB_BAS_INSTANCES_MAX (2)
+
+
+/*
+ * TYPE DEFINITIONS
+ ****************************************************************************************
+ */
+
+
+/// Messages for Battery Server
+enum bass_msg_id
+{
+ /// Start the Battery Server - at connection used to restore bond data
+ BASS_ENABLE_REQ = TASK_FIRST_MSG(TASK_ID_BASS),
+ /// Confirmation of the Battery Server start
+ BASS_ENABLE_RSP,
+ /// Battery Level Value Update Request
+ BASS_BATT_LEVEL_UPD_REQ,
+ /// Inform APP if Battery Level value has been notified or not
+ BASS_BATT_LEVEL_UPD_RSP,
+ /// Inform APP that Battery Level Notification Configuration has been changed - use to update bond data
+ BASS_BATT_LEVEL_NTF_CFG_IND,
+};
+
+/// Features Flag Masks
+enum bass_features
+{
+ /// Battery Level Characteristic doesn't support notifications
+ BAS_BATT_LVL_NTF_NOT_SUP,
+ /// Battery Level Characteristic support notifications
+ BAS_BATT_LVL_NTF_SUP,
+};
+
+
+/*
+ * APIs Structures
+ ****************************************************************************************
+ */
+
+/// Parameters for the database creation
+struct bass_db_cfg
+{
+ /// Number of BAS to add
+ uint8_t bas_nb;
+ /// Features of each BAS instance
+ uint8_t features[BASS_NB_BAS_INSTANCES_MAX];
+ /// Battery Level Characteristic Presentation Format - Should not change during connection
+ struct prf_char_pres_fmt batt_level_pres_format[BASS_NB_BAS_INSTANCES_MAX];
+};
+
+/// Parameters of the @ref BASS_ENABLE_REQ message
+struct bass_enable_req
+{
+ /// connection index
+ uint8_t conidx;
+ /// Notification Configuration
+ uint8_t ntf_cfg;
+ /// Old Battery Level used to decide if notification should be triggered
+ uint8_t old_batt_lvl[BASS_NB_BAS_INSTANCES_MAX];
+};
+
+/// Parameters of the @ref BASS_ENABLE_RSP message
+struct bass_enable_rsp
+{
+ /// connection index
+ uint8_t conidx;
+ ///status
+ uint8_t status;
+};
+
+///Parameters of the @ref BASS_BATT_LEVEL_UPD_REQ message
+struct bass_batt_level_upd_req
+{
+ /// BAS instance
+ uint8_t bas_instance;
+ /// Battery Level
+ uint8_t batt_level;
+};
+
+///Parameters of the @ref BAPS_BATT_LEVEL_UPD_RSP message
+struct bass_batt_level_upd_rsp
+{
+ ///status
+ uint8_t status;
+};
+
+///Parameters of the @ref BASS_BATT_LEVEL_NTF_CFG_IND message
+struct bass_batt_level_ntf_cfg_ind
+{
+ /// connection index
+ uint8_t conidx;
+ ///Notification Configuration
+ uint8_t ntf_cfg;
+};
+
+/// @} BASSTASK
+
+#endif /* _BASS_TASK_H_ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/rwapp_config.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/rwapp_config.h
new file mode 100644
index 0000000000..e5a23cf381
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/rwapp_config.h
@@ -0,0 +1,96 @@
+/**
+ ****************************************************************************************
+ *
+ * @file rwapp_config.h
+ *
+ * @brief Application configuration definition
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ ****************************************************************************************
+ */
+
+
+#ifndef _RWAPP_CONFIG_H_
+#define _RWAPP_CONFIG_H_
+
+/**
+ ****************************************************************************************
+ * @addtogroup app
+ * @brief Application configuration definition
+ *
+ * @{
+ ****************************************************************************************
+ */
+
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/******************************************************************************************/
+/* ------------------------- BLE APPLICATION SETTINGS -----------------------------*/
+/******************************************************************************************/
+
+
+/// Health Thermometer Application
+#if defined(CFG_APP_HT)
+#define BLE_APP_HT 1
+#else // defined(CFG_APP_HT)
+#define BLE_APP_HT 0
+#endif // defined(CFG_APP_HT)
+
+/// HID Application
+#if defined(CFG_APP_HID)
+#define BLE_APP_HID 1
+#else // defined(CFG_APP_HID)
+#define BLE_APP_HID 0
+#endif // defined(CFG_APP_HID)
+
+/// DIS Application
+#if defined(CFG_APP_DIS)
+#define BLE_APP_DIS 1
+#else // defined(CFG_APP_DIS)
+#define BLE_APP_DIS 0
+#endif // defined(CFG_APP_DIS)
+
+/// Time Application
+#if defined(CFG_APP_TIME)
+#define BLE_APP_TIME 1
+#else // defined(CFG_APP_TIME)
+#define BLE_APP_TIME 0
+#endif // defined(CFG_APP_TIME)
+
+/// Battery Service Application
+#if (BLE_APP_HID)
+#define BLE_APP_BATT 1
+#else
+#define BLE_APP_BATT 0
+#endif // (BLE_APP_HID)
+
+/// Security Application
+#if (defined(CFG_APP_SEC) || BLE_APP_HID || defined(BLE_APP_AM0))
+#define BLE_APP_SEC 1
+//#define BLE_APP_SEC_CON 1
+#else // defined(CFG_APP_SEC)
+#define BLE_APP_SEC 0
+#endif // defined(CFG_APP_SEC)
+
+/// user-defined
+#if defined(CFG_APP_USER)
+#define BLE_APP_USER 1
+#else // defined(CFG_APP_USER)
+#define BLE_APP_USER 0
+#endif // defined(CFG_APP_USER)
+
+
+
+/// @} rwapp_config
+
+#endif /* _RWAPP_CONFIG_H_ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/user.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/user.h
new file mode 100644
index 0000000000..8b77b7e6f0
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/user.h
@@ -0,0 +1,189 @@
+/**
+ ****************************************************************************************
+ *
+ * @file user.h
+ *
+ * @brief Header file - user defined.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+#ifndef USER_H_
+#define USER_H_
+
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "rwip_config.h"
+#if (BLE_APP_USER)
+#include
+#include
+//#include "htp_common.h"
+#include "prf_types.h"
+#include "prf_utils.h"
+#include "prf.h"
+#include "gap.h"
+
+/*
+ * MACROS
+ ****************************************************************************************
+ */
+#define USER_IS_FEATURE_SUPPORTED(feat, bit_mask) (((feat & bit_mask) == bit_mask))
+
+#define USER_HANDLE(idx) (user_att_hdl_get(user_env, (idx)))
+
+#define USER_IDX(hdl) (user_att_idx_get(user_env, (hdl)))
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+#define USER_DATA_LEN_MAX (1024)//(64)
+
+#define USER_READ_WRITE_ATT_NB (3)
+#define USER_DTAA_NOTIFY_ATT_NB (3)
+#define USER_DATA_WRITE_ATT_NB (2)
+#define USER_DATA_INTV_ATT_NB (3)
+
+#define USER_IND_NTF_CFG_MAX_LEN (2)
+/// Possible states of the HTPT task
+enum user_state
+{
+ /// Idle state
+ USER_IDLE,
+ /// Busy state
+ USER_BUSY,
+
+ /// Number of defined states.
+ USER_STATE_MAX
+};
+///Attributes database elements
+/// 修改æœåŠ¡åˆ—表
+enum user_att_db_list
+{
+ USER_IDX_SVC,
+
+ USER_IDX_WRITE_NOTIFY_CHAR,
+ USER_IDX_WRITE_NOTIFY_VAL,
+ USER_IDX_WRITE_NOTIFY_CFG,
+
+#ifdef BLE_OTA_WRITE_CHAR_EN
+ USER_IDX_READ_NOTIFY_CHAR,
+ USER_IDX_READ_NOTIFY_VAL,
+ USER_IDX_WRITE_NOTIFY2_CFG,
+#endif
+ USER_IDX_NB,
+};
+/// ongoing operation information
+struct user_op
+{
+ /// Operation
+ uint8_t op;
+ /// Cursor on connection
+ uint8_t cursor;
+ /// Handle of the attribute to indicate/notify
+ uint16_t handle;
+ /// Task that request the operation that should receive completed message response
+ uint16_t dest_id;
+ /// Packed notification/indication data size
+ uint8_t length;
+ /// used to know on which device interval update has been requested, and to prevent
+ /// indication to be triggered on this connection index
+ uint8_t conidx;
+ /// Packed notification/indication data
+ uint8_t data[__ARRAY_EMPTY];
+};
+
+//Health Thermometer Profile Thermometer Environment Variable
+struct user_env_tag
+{
+ /// profile environment
+ prf_env_t prf_env;
+ /// On-going operation
+ struct user_op * operation;
+ /// Service Start Handle
+ uint16_t shdl;
+ /// Database configuration
+ uint16_t features;
+ uint8_t ntf_ind_cfg[USER_IDX_NB];
+ ke_state_t state[1];
+
+ // uint8_t data[ATT_VALUE_LEN_MAX/*__ARRAY_EMPTY*/];
+
+ uint16_t receive_length;
+ uint8_t *receive_data;
+ bool receive_flag;
+ bool receive_header;
+ uint16_t receive_current_length;
+ uint16_t send_current_length; //wait to check
+};
+/*
+ * GLOBAL VARIABLE DECLARATIONS
+ ****************************************************************************************
+ */
+
+/*
+ * FUNCTION DECLARATIONS
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief Compute the offset of the valid range descriptor.
+ * The Measurement Interval characteristic has two optional descriptors. In the database,
+ * the Client Characteristic Configuration descriptor will always be placed just after the
+ * characteristic value. Thus, this function checks if the CCC descriptor has been added.
+ * @return 0 if Measurement Interval Char. is not writable (no Valid Range descriptor)
+ * 1 if Measurement Interval Char. doesn't support indications (no CCC descriptor)
+ * 2 otherwise
+ ****************************************************************************************
+ */
+uint8_t user_get_valid_rge_offset(uint16_t features);
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve HTS service profile interface
+ *
+ * @return HTS service profile interface
+ ****************************************************************************************
+ */
+const struct prf_task_cbs* user_prf_itf_get(void);
+//const struct prf_task_cbs* user1_prf_itf_get(void);
+//const struct prf_task_cbs* user2_prf_itf_get(void);
+uint16_t user_att_hdl_get(struct user_env_tag* htpt_env, uint8_t att_idx);
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve attribute index from attribute handle
+ *
+ * @param[in] htpt_env Environment variable
+ * @param[in] handle Attribute Handle
+ *
+ * @return attribute Index
+ ****************************************************************************************
+ */
+uint8_t user_att_idx_get(struct user_env_tag* htpt_env, uint16_t handle);
+
+void user_exe_operation(void);
+
+uint8_t user_update_ntf_ind_cfg(uint8_t conidx, uint8_t cfg, uint16_t valid_val,uint8_t idx,uint16_t value);
+
+/*
+ * TASK DESCRIPTOR DECLARATIONS
+ ****************************************************************************************
+ */
+extern const struct ke_state_handler user_default_handler;
+//extern const struct ke_state_handler user1_default_handler;
+//extern const struct ke_state_handler user2_default_handler;
+
+#endif //BLE_HT_THERMOM
+
+/// @} HTPT
+
+#endif // HTPT_H_
+
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/user_task.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/user_task.h
new file mode 100644
index 0000000000..9e5988939c
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/user_task.h
@@ -0,0 +1,128 @@
+#include "rwip_task.h" // Task definitions
+#include "stdbool.h"
+#include "ble_arch.h"
+struct user_db_cfg
+{
+ /// Feature (@see enum user_features)
+ uint8_t features;
+
+ uint16_t rxlen;
+ uint16_t txlen;
+ uint8_t *prx;
+ uint8_t *ptx;
+ /// Measurement interval timer enable
+ bool timer_enable;
+
+};
+
+/// Parameters of the @ref HTPT_ENABLE_REQ message
+struct user_enable_req
+{
+ /// Connection index
+ uint8_t conidx;
+ /// Notification configuration (Bond Data to restore: @see enum htpt_ntf_ind_cfg)
+ uint8_t ntf_ind_cfg;
+
+
+};
+struct user_notify_req
+{
+ uint8_t att_idx;
+ uint16_t send_param_length;
+ uint8_t send_param_payload[__ARRAY_EMPTY];
+};
+/// Parameters of the @ref HTPT_ENABLE_RSP message
+struct user_enable_rsp
+{
+ /// Connection index
+ uint8_t conidx;
+ /// Status of enable request
+ uint8_t status;
+};
+/// Parameters of the @ref HTPT_TEMP_SEND_RSP message
+struct user_notify_rsp
+{
+ /// Status
+ uint8_t status;
+};
+struct user_write_rsp
+{
+ /// Status
+ uint16_t len;
+ uint8_t status;
+};
+struct user_read_rsp
+{
+ /// Status
+ uint8_t status;
+};
+struct user_upd_rsp
+{
+ /// status
+ uint8_t status;
+};
+/// Parameters of the @ref HTPT_CFG_INDNTF_IND message
+struct user_cfg_indntf_ind
+{
+ /// connection index
+ uint8_t conidx;
+ /// Notification Configuration (@see enum htpt_ntf_ind_cfg)
+ uint8_t ntf_ind_cfg;
+};
+/// Messages for Health Thermometer Profile Thermometer
+enum user_msg_id
+{
+ /// Start the Health Thermometer Profile Thermometer profile - at connection
+ USER_ENABLE_REQ = TASK_FIRST_MSG(TASK_ID_USER),
+ /// Enable confirmation
+ USER_ENABLE_RSP,
+
+ /// Send DATA value
+ USER_DATA_WRITE_REQ,
+ /// Send DATA response
+ USER_DATA_WRITE_RSP,
+
+ /// RECEIVE DATA value
+ USER_DATA_READ_REQ,
+ /// RECEIVE DATA response
+ USER_DATA_READ_RSP,
+
+ /// Indicate Measurement Interval
+ USER_NOTIFY_REQ,
+ /// Send Measurement Interval response
+ USER_NOTIFY_RSP,
+
+ /// Indicate Measurement Interval
+ USER_INTV_REQ,
+ /// Send Measurement Interval response
+ USER_INTV_RSP,
+ /// Inform APP that Indication Configuration has been changed - use to update bond data
+ USER_CFG_INDNTF_IND,
+};
+/// Database Feature Configuration Flags
+enum user_features
+{
+ /// Indicate if READ_WRITE Char. is supported
+ USER_READ_WRITE_CHAR_SUP = 0x01,
+ /// Indicate if DATA_NOTIFY Char. is supported
+ USER_DATA_NOTIFY_CHAR_SUP = 0x02,
+ /// Indicate if DATA_WRITE Char. is supported
+ USER_DATA_WRITE_CHAR_SUP = 0x04,
+ /// Indicate if indication Char. supports indications
+ USER_DATA_IND_CHAR_SUP = 0x08,
+ /// All Features supported
+ USER_ALL_FEAT_SUP = 0xF,
+};
+enum user_ntf_ind_cfg
+{
+ USER_DATA_NTF_IND_DISABLE = 0,
+ /// æ•°æ®å‘é€æ–¹å¼ä¸ºnotify
+ USER_DATA_NTF = (1 << 0),
+ /// æ•°æ®å‘é€æ–¹å¼ä¸ºindication
+ USER_DATA_IND = (1 << 1),
+};
+
+
+
+
+
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/prf.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/prf.c
new file mode 100644
index 0000000000..2d1b2d7c46
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/prf.c
@@ -0,0 +1,810 @@
+/**
+ ****************************************************************************************
+ *
+ * @file prf.c
+ *
+ * @brief Entry point of profile source file.
+ *
+ * Used to manage life cycle of profiles
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ ****************************************************************************************
+ */
+
+
+/**
+ ****************************************************************************************
+ * @addtogroup PRF
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+
+#include "rwip_config.h"
+
+#if (BLE_PROFILES)
+#include "prf.h"
+#include "att.h"
+
+
+#if (BLE_HT_THERMOM)
+extern const struct prf_task_cbs* htpt_prf_itf_get(void);
+#endif // (BLE_HT_THERMOM)
+
+#if (BLE_HT_COLLECTOR)
+extern const struct prf_task_cbs* htpc_prf_itf_get(void);
+#endif // (BLE_HT_COLLECTOR)
+
+#if (BLE_DIS_SERVER)
+extern const struct prf_task_cbs* diss_prf_itf_get(void);
+#endif // (BLE_HT_THERMOM)
+
+#if (BLE_DIS_CLIENT)
+extern const struct prf_task_cbs* disc_prf_itf_get(void);
+#endif // (BLE_DIS_CLIENT)
+
+#if (BLE_BP_SENSOR)
+extern const struct prf_task_cbs* blps_prf_itf_get(void);
+#endif // (BLE_BP_SENSOR)
+
+#if (BLE_BP_COLLECTOR)
+extern const struct prf_task_cbs* blpc_prf_itf_get(void);
+#endif // (BLE_BP_COLLECTOR)
+
+#if (BLE_TIP_SERVER)
+extern const struct prf_task_cbs* tips_prf_itf_get(void);
+#endif // (BLE_TIP_SERVER)
+
+#if (BLE_TIP_CLIENT)
+extern const struct prf_task_cbs* tipc_prf_itf_get(void);
+#endif // (BLE_TIP_CLIENT)
+
+#if (BLE_HR_SENSOR)
+extern const struct prf_task_cbs* hrps_prf_itf_get(void);
+#endif // (BLE_HR_SENSOR)
+
+#if (BLE_HR_COLLECTOR)
+extern const struct prf_task_cbs* hrpc_prf_itf_get(void);
+#endif // (BLE_HR_COLLECTOR)
+
+#if (BLE_FINDME_LOCATOR)
+extern const struct prf_task_cbs* findl_prf_itf_get(void);
+#endif // (BLE_FINDME_LOCATOR)
+
+#if (BLE_FINDME_TARGET)
+extern const struct prf_task_cbs* findt_prf_itf_get(void);
+#endif // (BLE_FINDME_TARGET)
+
+#if (BLE_PROX_MONITOR)
+extern const struct prf_task_cbs* proxm_prf_itf_get(void);
+#endif // (BLE_PROX_MONITOR)
+
+#if (BLE_PROX_REPORTER)
+extern const struct prf_task_cbs* proxr_prf_itf_get(void);
+#endif // (BLE_PROX_REPORTER)
+
+#if (BLE_SP_CLIENT)
+extern const struct prf_task_cbs* scppc_prf_itf_get(void);
+#endif // (BLE_SP_CLENT)
+
+#if (BLE_SP_SERVER)
+extern const struct prf_task_cbs* scpps_prf_itf_get(void);
+#endif // (BLE_SP_SERVER)
+
+#if (BLE_BATT_CLIENT)
+extern const struct prf_task_cbs* basc_prf_itf_get(void);
+#endif // (BLE_BATT_CLIENT)
+
+//#if (BLE_BATT_SERVER)
+//extern const struct prf_task_cbs* bass_prf_itf_get(void);
+//#endif // (BLE_BATT_SERVER)
+
+#if (BLE_HID_DEVICE)
+extern const struct prf_task_cbs* hogpd_prf_itf_get(void);
+#endif // (BLE_HID_DEVICE)
+
+#if (BLE_HID_BOOT_HOST)
+extern const struct prf_task_cbs* hogpbh_prf_itf_get(void);
+#endif // (BLE_HID_BOOT_HOST)
+
+#if (BLE_HID_REPORT_HOST)
+extern const struct prf_task_cbs* hogprh_prf_itf_get(void);
+#endif // (BLE_HID_REPORT_HOST)
+
+#if (BLE_GL_COLLECTOR)
+extern const struct prf_task_cbs* glpc_prf_itf_get(void);
+#endif // (BLE_GL_COLLECTOR)
+
+#if (BLE_GL_SENSOR)
+extern const struct prf_task_cbs* glps_prf_itf_get(void);
+#endif // (BLE_GL_SENSOR)
+
+#if (BLE_RSC_COLLECTOR)
+extern const struct prf_task_cbs* rscpc_prf_itf_get(void);
+#endif // (BLE_RSC_COLLECTOR)
+
+#if (BLE_RSC_SENSOR)
+extern const struct prf_task_cbs* rscps_prf_itf_get(void);
+#endif // (BLE_RSC_COLLECTOR)
+
+#if (BLE_CSC_COLLECTOR)
+extern const struct prf_task_cbs* cscpc_prf_itf_get(void);
+#endif // (BLE_CSC_COLLECTOR)
+
+#if (BLE_CSC_SENSOR)
+extern const struct prf_task_cbs* cscps_prf_itf_get(void);
+#endif // (BLE_CSC_COLLECTOR)
+
+#if (BLE_AN_CLIENT)
+extern const struct prf_task_cbs* anpc_prf_itf_get(void);
+#endif // (BLE_AN_CLIENT)
+
+#if (BLE_AN_SERVER)
+extern const struct prf_task_cbs* anps_prf_itf_get(void);
+#endif // (BLE_AN_SERVER)
+
+#if (BLE_PAS_CLIENT)
+extern const struct prf_task_cbs* paspc_prf_itf_get(void);
+#endif // (BLE_PAS_CLIENT)
+
+#if (BLE_PAS_SERVER)
+extern const struct prf_task_cbs* pasps_prf_itf_get(void);
+#endif // (BLE_PAS_SERVER)
+
+#if (BLE_CP_COLLECTOR)
+extern const struct prf_task_cbs* cppc_prf_itf_get(void);
+#endif //(BLE_CP_COLLECTOR)
+
+#if (BLE_CP_SENSOR)
+extern const struct prf_task_cbs* cpps_prf_itf_get(void);
+#endif //(BLE_CP_SENSOR)
+
+#if (BLE_LN_COLLECTOR)
+extern const struct prf_task_cbs* lanc_prf_itf_get(void);
+#endif //(BLE_CP_COLLECTOR)
+
+#if (BLE_LN_SENSOR)
+extern const struct prf_task_cbs* lans_prf_itf_get(void);
+#endif //(BLE_CP_SENSOR)
+
+#if (BLE_IPS_SERVER)
+extern const struct prf_task_cbs* ipss_prf_itf_get(void);
+#endif //(BLE_IPS_SERVER)
+
+#if (BLE_IPS_CLIENT)
+extern const struct prf_task_cbs* ipsc_prf_itf_get(void);
+#endif //(BLE_IPS_CLIENT)
+
+#if (BLE_ENV_SERVER)
+extern const struct prf_task_cbs* envs_prf_itf_get(void);
+#endif //(BLE_ENV_SERVER)
+
+#if (BLE_ENV_CLIENT)
+extern const struct prf_task_cbs* envc_prf_itf_get(void);
+#endif //(BLE_ENV_CLIENT
+
+#if (BLE_WSC_SERVER)
+extern const struct prf_task_cbs* wscs_prf_itf_get(void);
+#endif //(BLE_WSC_SERVER)
+
+#if (BLE_WSC_CLIENT)
+extern const struct prf_task_cbs* wscc_prf_itf_get(void);
+#endif //(BLE_WSC_CLIENT
+
+#if (BLE_BCS_SERVER)
+extern const struct prf_task_cbs* bcss_prf_itf_get(void);
+#endif //(BLE_BCS_SERVER)
+
+#if (BLE_BCS_CLIENT)
+extern const struct prf_task_cbs* bcsc_prf_itf_get(void);
+#endif //(BLE_BCS_CLIENT)
+
+#if (BLE_WPT_SERVER)
+extern const struct prf_task_cbs* wpts_prf_itf_get(void);
+#endif //(BLE_WPT_SERVER)
+
+#if (BLE_WPT_CLIENT)
+extern const struct prf_task_cbs* wptc_prf_itf_get(void);
+#endif //(BLE_WPT_CLIENT
+
+
+
+
+#ifdef BLE_AM0_HEARING_AID_SERV
+extern const struct prf_task_cbs* am0_has_prf_itf_get(void);
+#endif // BLE_AM0_HEARING_AID_SERV
+
+#if (BLE_UDS_SERVER)
+extern const struct prf_task_cbs* udss_prf_itf_get(void);
+#endif //(BLE_UDS_SERVER)
+
+#if (BLE_UDS_CLIENT)
+extern const struct prf_task_cbs* udsc_prf_itf_get(void);
+#endif //(BLE_UDS_SERVER)
+
+#if (BLE_APP_USER)
+extern const struct prf_task_cbs* user_prf_itf_get(void);
+#endif //(BLE_APP_USER)
+
+/*
+ * TYPE DEFINITIONS
+ ****************************************************************************************
+ */
+
+
+/*
+ * DEFINES
+ ****************************************************************************************
+ */
+
+/*
+ * MACROS
+ ****************************************************************************************
+ */
+
+
+/*
+ * GLOBAL VARIABLE DEFINITIONS
+ ****************************************************************************************
+ */
+struct prf_env_tag prf_env;
+
+/*
+ * LOCAL FUNCTIONS DEFINITIONS
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @brief Retrieve profile interface
+ ****************************************************************************************
+ */
+static const struct prf_task_cbs * prf_itf_get(uint16_t task_id)
+{
+ const struct prf_task_cbs* prf_cbs = NULL;
+
+ switch (KE_TYPE_GET(task_id))
+ {
+ #if (BLE_HT_THERMOM)
+ case TASK_ID_HTPT:
+ prf_cbs = htpt_prf_itf_get();
+ break;
+ #endif // (BLE_HT_THERMOM)
+
+ #if (BLE_HT_COLLECTOR)
+ case TASK_ID_HTPC:
+ prf_cbs = htpc_prf_itf_get();
+ break;
+ #endif // (BLE_HT_COLLECTOR)
+
+ #if (BLE_DIS_SERVER)
+ case TASK_ID_DISS:
+ prf_cbs = diss_prf_itf_get();
+ break;
+ #endif // (BLE_DIS_SERVER)
+
+ #if (BLE_DIS_CLIENT)
+ case TASK_ID_DISC:
+ prf_cbs = disc_prf_itf_get();
+ break;
+ #endif // (BLE_DIS_CLIENT)
+
+ #if (BLE_BP_SENSOR)
+ case TASK_ID_BLPS:
+ prf_cbs = blps_prf_itf_get();
+ break;
+ #endif // (BLE_BP_SENSOR)
+
+ #if (BLE_BP_COLLECTOR)
+ case TASK_ID_BLPC:
+ prf_cbs = blpc_prf_itf_get();
+ break;
+ #endif // (BLE_BP_COLLECTOR)
+
+ #if (BLE_TIP_SERVER)
+ case TASK_ID_TIPS:
+ prf_cbs = tips_prf_itf_get();
+ break;
+ #endif // (BLE_TIP_SERVER)
+
+ #if (BLE_TIP_CLIENT)
+ case TASK_ID_TIPC:
+ prf_cbs = tipc_prf_itf_get();
+ break;
+ #endif // (BLE_TIP_CLIENT)
+
+ #if (BLE_HR_SENSOR)
+ case TASK_ID_HRPS:
+ prf_cbs = hrps_prf_itf_get();
+ break;
+ #endif // (BLE_HR_SENSOR)
+
+ #if (BLE_HR_COLLECTOR)
+ case TASK_ID_HRPC:
+ prf_cbs = hrpc_prf_itf_get();
+ break;
+ #endif // (BLE_HR_COLLECTOR)
+
+ #if (BLE_FINDME_LOCATOR)
+ case TASK_ID_FINDL:
+ prf_cbs = findl_prf_itf_get();
+ break;
+ #endif // (BLE_FINDME_LOCATOR)
+
+ #if (BLE_FINDME_TARGET)
+ case TASK_ID_FINDT:
+ prf_cbs = findt_prf_itf_get();
+ break;
+ #endif // (BLE_FINDME_TARGET)
+
+ #if (BLE_PROX_MONITOR)
+ case TASK_ID_PROXM:
+ prf_cbs = proxm_prf_itf_get();
+ break;
+ #endif // (BLE_PROX_MONITOR)
+
+ #if (BLE_PROX_REPORTER)
+ case TASK_ID_PROXR:
+ prf_cbs = proxr_prf_itf_get();
+ break;
+ #endif // (BLE_PROX_REPORTER)
+
+ #if (BLE_SP_SERVER)
+ case TASK_ID_SCPPS:
+ prf_cbs = scpps_prf_itf_get();
+ break;
+ #endif // (BLE_SP_SERVER)
+
+ #if (BLE_SP_CLIENT)
+ case TASK_ID_SCPPC:
+ prf_cbs = scppc_prf_itf_get();
+ break;
+ #endif // (BLE_SP_CLIENT)
+
+// #if (BLE_BATT_SERVER)
+// case TASK_ID_BASS:
+// prf_cbs = bass_prf_itf_get();
+// break;
+// #endif // (BLE_BATT_SERVER)
+
+ #if (BLE_BATT_CLIENT)
+ case TASK_ID_BASC:
+ prf_cbs = basc_prf_itf_get();
+ break;
+ #endif // (BLE_BATT_CLIENT)
+
+ #if (BLE_HID_DEVICE)
+ case TASK_ID_HOGPD:
+ prf_cbs = hogpd_prf_itf_get();
+ break;
+ #endif // (BLE_HID_DEVICE)
+
+ #if (BLE_HID_BOOT_HOST)
+ case TASK_ID_HOGPBH:
+ prf_cbs = hogpbh_prf_itf_get();
+ break;
+ #endif // (BLE_HID_BOOT_HOST)
+
+ #if (BLE_HID_REPORT_HOST)
+ case TASK_ID_HOGPRH:
+ prf_cbs = hogprh_prf_itf_get();
+ break;
+ #endif // (BLE_HID_REPORT_HOST)
+
+ #if (BLE_GL_COLLECTOR)
+ case TASK_ID_GLPC:
+ prf_cbs = glpc_prf_itf_get();
+ break;
+ #endif // (BLE_GL_COLLECTOR)
+
+ #if (BLE_GL_SENSOR)
+ case TASK_ID_GLPS:
+ prf_cbs = glps_prf_itf_get();
+ break;
+ #endif // (BLE_GL_SENSOR)
+
+ #if (BLE_RSC_COLLECTOR)
+ case TASK_ID_RSCPC:
+ prf_cbs = rscpc_prf_itf_get();
+ break;
+ #endif // (BLE_RSC_COLLECTOR)
+
+ #if (BLE_RSC_SENSOR)
+ case TASK_ID_RSCPS:
+ prf_cbs = rscps_prf_itf_get();
+ break;
+ #endif // (BLE_RSC_SENSOR)
+
+ #if (BLE_CSC_COLLECTOR)
+ case TASK_ID_CSCPC:
+ prf_cbs = cscpc_prf_itf_get();
+ break;
+ #endif // (BLE_CSC_COLLECTOR)
+
+ #if (BLE_CSC_SENSOR)
+ case TASK_ID_CSCPS:
+ prf_cbs = cscps_prf_itf_get();
+ break;
+ #endif // (BLE_CSC_SENSOR)
+
+ #if (BLE_CP_COLLECTOR)
+ case TASK_ID_CPPC:
+ prf_cbs = cppc_prf_itf_get();
+ break;
+ #endif // (BLE_CP_COLLECTOR)
+
+ #if (BLE_CP_SENSOR)
+ case TASK_ID_CPPS:
+ prf_cbs = cpps_prf_itf_get();
+ break;
+ #endif // (BLE_CP_SENSOR)
+
+ #if (BLE_LN_COLLECTOR)
+ case TASK_ID_LANC:
+ prf_cbs = lanc_prf_itf_get();
+ break;
+ #endif // (BLE_LN_COLLECTOR)
+
+ #if (BLE_LN_SENSOR)
+ case TASK_ID_LANS:
+ prf_cbs = lans_prf_itf_get();
+ break;
+ #endif // (BLE_LN_SENSOR)
+
+ #if (BLE_AN_CLIENT)
+ case TASK_ID_ANPC:
+ prf_cbs = anpc_prf_itf_get();
+ break;
+ #endif // (BLE_AN_CLIENT)
+
+ #if (BLE_AN_SERVER)
+ case TASK_ID_ANPS:
+ prf_cbs = anps_prf_itf_get();
+ break;
+ #endif // (BLE_AN_SERVER)
+
+ #if (BLE_PAS_CLIENT)
+ case TASK_ID_PASPC:
+ prf_cbs = paspc_prf_itf_get();
+ break;
+ #endif // (BLE_PAS_CLIENT)
+
+ #if (BLE_PAS_SERVER)
+ case TASK_ID_PASPS:
+ prf_cbs = pasps_prf_itf_get();
+ break;
+ #endif // (BLE_PAS_SERVER)
+
+ #ifdef BLE_AM0_HEARING_AID_SERV
+ case TASK_ID_AM0_HAS:
+ prf_cbs = am0_has_prf_itf_get();
+ break;
+ #endif // defined(BLE_AM0_HEARING_AID_SERV)
+
+ #if (BLE_IPS_SERVER)
+ case TASK_ID_IPSS:
+ prf_cbs = ipss_prf_itf_get();
+ break;
+ #endif //(BLE_IPS_SERVER)
+
+ #if (BLE_IPS_CLIENT)
+ case TASK_ID_IPSC:
+ prf_cbs = ipsc_prf_itf_get();
+ break;
+ #endif //(BLE_IPS_CLIENT)
+
+ #if (BLE_ENV_SERVER)
+ case TASK_ID_ENVS:
+ prf_cbs = envs_prf_itf_get();
+ break;
+ #endif //(BLE_ENV_SERVER)
+
+ #if (BLE_ENV_CLIENT)
+ case TASK_ID_ENVC:
+ prf_cbs = envc_prf_itf_get();
+ break;
+ #endif //(BLE_ENV_CLIENT
+
+ #if (BLE_WSC_SERVER)
+ case TASK_ID_WSCS:
+ prf_cbs = wscs_prf_itf_get();
+ break;
+ #endif //(BLE_WSC_SERVER)
+
+ #if (BLE_WSC_CLIENT)
+ case TASK_ID_WSCC:
+ prf_cbs = wscc_prf_itf_get();
+ break;
+ #endif //(BLE_WSC_CLIENT
+ #if (BLE_BCS_SERVER)
+ case TASK_ID_BCSS:
+ prf_cbs = bcss_prf_itf_get();
+ break;
+ #endif //(BLE_BCS_SERVER)
+
+ #if (BLE_BCS_CLIENT)
+ case TASK_ID_BCSC:
+ prf_cbs = bcsc_prf_itf_get();
+ break;
+ #endif //(BLE_BCS_CLIENT)
+
+ #if (BLE_UDS_SERVER)
+ case TASK_ID_UDSS:
+ prf_cbs = udss_prf_itf_get();
+ break;
+ #endif //(BLE_UDS_SERVER)
+
+ #if (BLE_UDS_CLIENT)
+ case TASK_ID_UDSC:
+ prf_cbs = udsc_prf_itf_get();
+ break;
+ #endif //(BLE_UDS_CLIENT)
+
+ #if (BLE_WPT_SERVER)
+ case TASK_ID_WPTS:
+ prf_cbs = wpts_prf_itf_get();
+ break;
+ #endif //(BLE_WPT_SERVER)
+
+ #if (BLE_WPT_CLIENT)
+ case TASK_ID_WPTC:
+ prf_cbs = wptc_prf_itf_get();
+ break;
+ #endif //(BLE_WPT_CLIENT)
+ #if (BLE_APP_USER)
+ case TASK_ID_USER:
+ prf_cbs = user_prf_itf_get();
+ break;
+
+ #endif // (BLE_APP_USER)
+
+ default: /* Nothing to do */ break;
+ }
+
+ return prf_cbs;
+}
+
+/*
+ * EXPORTED FUNCTIONS DEFINITIONS
+ ****************************************************************************************
+ */
+void prf_init(bool reset)
+{
+
+ uint8_t i;
+ if (!reset)
+ {
+ // FW boot profile initialization
+ for(i = 0; i < BLE_NB_PROFILES ; i++)
+ {
+ prf_env.prf[i].env = NULL;
+ prf_env.prf[i].task = TASK_GAPC + i +1;
+ prf_env.prf[i].id = TASK_ID_INVALID;
+
+ // Initialize Task Descriptor
+ prf_env.prf[i].desc.default_handler = NULL;
+ prf_env.prf[i].desc.state = NULL;
+ prf_env.prf[i].desc.idx_max = 0;
+
+ prf_env.prf[i].desc.state_max = 0;
+ prf_env.prf[i].desc.state_handler = NULL;
+
+ ke_task_create(prf_env.prf[i].task, &(prf_env.prf[i].desc));
+ }
+ }
+ else
+ {
+ // FW boot profile destruction
+ for(i = 0; i < BLE_NB_PROFILES ; i++)
+ {
+ // Get Profile API
+ const struct prf_task_cbs * cbs = prf_itf_get(prf_env.prf[i].id);
+ if (cbs != NULL)
+ {
+ // request to destroy profile
+ cbs->destroy(&(prf_env.prf[i]));
+ }
+ // unregister profile
+ prf_env.prf[i].id = TASK_ID_INVALID;
+ prf_env.prf[i].desc.default_handler = NULL;
+ prf_env.prf[i].desc.state = NULL;
+ prf_env.prf[i].desc.idx_max = 0;
+
+ // Request kernel to flush task messages
+ ke_task_msg_flush(KE_TYPE_GET(prf_env.prf[i].task));
+ }
+ }
+}
+
+
+uint8_t prf_add_profile(struct gapm_profile_task_add_cmd * params, ke_task_id_t* prf_task)
+{
+ uint8_t i;
+ uint8_t status = GAP_ERR_NO_ERROR;
+
+ // retrieve profile callback
+ const struct prf_task_cbs * cbs = prf_itf_get(params->prf_task_id);
+ if (cbs == NULL)
+ {
+ // profile API not available
+ status = GAP_ERR_INVALID_PARAM;
+ }
+
+ // check if profile not already present in task list
+ if (status == GAP_ERR_NO_ERROR)
+ {
+ for(i = 0; i < BLE_NB_PROFILES ; i++)
+ {
+ if (prf_env.prf[i].id == params->prf_task_id)
+ {
+ status = GAP_ERR_NOT_SUPPORTED;
+ break;
+ }
+ }
+ }
+
+ if (status == GAP_ERR_NO_ERROR)
+ {
+ // find fist available task
+ for(i = 0; i < BLE_NB_PROFILES ; i++)
+ {
+ // available task found
+ if (prf_env.prf[i].id == TASK_ID_INVALID)
+ {
+ // initialize profile
+ status = cbs->init(&(prf_env.prf[i]), &(params->start_hdl), params->app_task, params->sec_lvl, params->param);
+
+ // initialization succeed
+ if (status == GAP_ERR_NO_ERROR)
+ {
+ // register profile
+ prf_env.prf[i].id = params->prf_task_id;
+ *prf_task = prf_env.prf[i].task;
+ }
+ break;
+ }
+ }
+
+ if (i == BLE_NB_PROFILES)
+ {
+ status = GAP_ERR_INSUFF_RESOURCES;
+ }
+ }
+
+ return (status);
+}
+
+
+
+void prf_create(uint8_t conidx)
+{
+ uint8_t i;
+ /* simple connection creation handler, nothing to do. */
+
+ // execute create function of each profiles
+ for(i = 0; i < BLE_NB_PROFILES ; i++)
+ {
+ // Get Profile API
+ const struct prf_task_cbs * cbs = prf_itf_get(prf_env.prf[i].id);
+ if (cbs != NULL)
+ {
+ // call create callback
+ cbs->create(&(prf_env.prf[i]), conidx);
+ }
+ }
+}
+
+
+void prf_cleanup(uint8_t conidx, uint8_t reason)
+{
+ uint8_t i;
+ /* simple connection creation handler, nothing to do. */
+
+ // execute create function of each profiles
+ for(i = 0; i < BLE_NB_PROFILES ; i++)
+ {
+ // Get Profile API
+ const struct prf_task_cbs * cbs = prf_itf_get(prf_env.prf[i].id);
+ if (cbs != NULL)
+ {
+ // call cleanup callback
+ cbs->cleanup(&(prf_env.prf[i]), conidx, reason);
+ }
+ }
+}
+
+
+prf_env_t* prf_env_get(uint16_t prf_id)
+{
+ prf_env_t* env = NULL;
+ uint8_t i;
+ // find if profile present in profile tasks
+ for(i = 0; i < BLE_NB_PROFILES ; i++)
+ {
+ // check if profile identifier is known
+ if (prf_env.prf[i].id == prf_id)
+ {
+ env = prf_env.prf[i].env;
+ break;
+ }
+ }
+
+ return env;
+}
+
+ke_task_id_t prf_src_task_get(prf_env_t* env, uint8_t conidx)
+{
+ ke_task_id_t task = PERM_GET(env->prf_task, PRF_TASK);
+
+ if (PERM_GET(env->prf_task, PRF_MI))
+ {
+ task = KE_BUILD_ID(task, conidx);
+ }
+
+ return task;
+}
+
+ke_task_id_t prf_dst_task_get(prf_env_t* env, uint8_t conidx)
+{
+ ke_task_id_t task = PERM_GET(env->app_task, PRF_TASK);
+
+ if (PERM_GET(env->app_task, PRF_MI))
+ {
+ task = KE_BUILD_ID(task, conidx);
+ }
+
+ return task;
+}
+
+
+ke_task_id_t prf_get_id_from_task(ke_msg_id_t task)
+{
+ ke_task_id_t id = TASK_ID_INVALID;
+ uint8_t idx = KE_IDX_GET(task);
+ uint8_t i;
+ task = KE_TYPE_GET(task);
+
+ // find if profile present in profile tasks
+ for(i = 0; i < BLE_NB_PROFILES ; i++)
+ {
+ // check if profile identifier is known
+ if (prf_env.prf[i].task == task)
+ {
+ id = prf_env.prf[i].id;
+ break;
+ }
+ }
+
+ return KE_BUILD_ID(id, idx);
+}
+
+ke_task_id_t prf_get_task_from_id(ke_msg_id_t id)
+{
+ ke_task_id_t task = TASK_NONE;
+ uint8_t idx = KE_IDX_GET(id);
+ uint8_t i;
+ id = KE_TYPE_GET(id);
+
+ // find if profile present in profile tasks
+ for(i = 0; i < BLE_NB_PROFILES ; i++)
+ {
+ // check if profile identifier is known
+ if (prf_env.prf[i].id == id)
+ {
+ task = prf_env.prf[i].task;
+ break;
+ }
+ }
+
+ return KE_BUILD_ID(task, idx);
+}
+
+
+#endif // (BLE_PROFILES)
+
+/// @} PRF
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/prf_utils.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/prf_utils.c
new file mode 100644
index 0000000000..cbbf227479
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/prf_utils.c
@@ -0,0 +1,537 @@
+/**
+ ****************************************************************************************
+ *
+ * @file prf_utils.c
+ *
+ * @brief Implementation of Profile Utilities
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+
+/**
+ ****************************************************************************************
+ * @addtogroup PRF_UTILS
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "rwip_config.h"
+#if (BLE_PROFILES)
+#if (BLE_SERVER_PRF || BLE_CLIENT_PRF)
+
+#include
+#include
+#include "ke_task.h"
+#include "attm.h"
+#include "gattc_task.h"
+#include "prf_utils.h"
+#include "gap.h"
+#include "gapc.h"
+
+#include "ke_mem.h"
+#include "co_utils.h"
+#include "co_error.h"
+
+#endif /* (BLE_SERVER_PRF || BLE_CLIENT_PRF) */
+
+/*
+ * LOCAL FUNCTIONS DEFINITIONS
+ ****************************************************************************************
+ */
+
+/*
+ * EXPORTED FUNCTIONS DEFINITIONS
+ ****************************************************************************************
+ */
+
+#if (BLE_BATT_SERVER)
+void prf_pack_char_pres_fmt(uint8_t *packed_val, const struct prf_char_pres_fmt* char_pres_fmt)
+{
+ *packed_val = char_pres_fmt->format;
+ *(packed_val + 1) = char_pres_fmt->exponent;
+ co_write16p(packed_val + 2, char_pres_fmt->unit);
+ *(packed_val + 4) = char_pres_fmt->name_space;
+ co_write16p(packed_val + 5, char_pres_fmt->description);
+}
+#endif // (BLE_BATT_SERVER)
+
+#if (BLE_BATT_CLIENT)
+void prf_unpack_char_pres_fmt(const uint8_t *packed_val, struct prf_char_pres_fmt* char_pres_fmt)
+{
+
+ char_pres_fmt->format = *packed_val;
+ char_pres_fmt->exponent = *(packed_val + 1);
+ char_pres_fmt->unit = co_read16p(packed_val + 2);
+ char_pres_fmt->name_space = *(packed_val + 4);
+ char_pres_fmt->description = co_read16p(packed_val + 5);
+}
+#endif // (BLE_BATT_CLIENT)
+
+
+#if (BLE_CLIENT_PRF)
+void prf_read_char_send(prf_env_t *prf_env, uint8_t conidx,
+ uint16_t shdl, uint16_t ehdl, uint16_t valhdl)
+{
+ struct gattc_read_cmd * req = KE_MSG_ALLOC(GATTC_READ_CMD, KE_BUILD_ID(TASK_GATTC, conidx),
+ prf_src_task_get(prf_env, conidx), gattc_read_cmd);
+ //request type
+ req->operation = GATTC_READ;
+ req->nb = 1;
+ req->req.simple.offset = 0;
+ req->req.simple.length = 0;
+ req->req.simple.handle = valhdl;
+
+ //send request to GATT
+ ke_msg_send(req);
+}
+
+void prf_register_atthdl2gatt(prf_env_t *prf_env, uint8_t conidx, struct prf_svc *svc)
+{
+ if (svc->shdl != ATT_INVALID_HANDLE)
+ {
+ //register profile task in gatt for indication/notifications
+ struct gattc_reg_to_peer_evt_cmd * reg = KE_MSG_ALLOC(GATTC_REG_TO_PEER_EVT_CMD,
+ KE_BUILD_ID(TASK_GATTC, conidx), prf_src_task_get(prf_env, conidx),
+ gattc_reg_to_peer_evt_cmd);
+
+ reg->operation = GATTC_REGISTER;
+ reg->start_hdl = svc->shdl;
+ reg->end_hdl = svc->ehdl;
+
+ ke_msg_send(reg);
+ }
+}
+
+void prf_unregister_atthdl2gatt(prf_env_t *prf_env, uint8_t conidx, struct prf_svc *svc)
+{
+ if (svc->shdl != ATT_INVALID_HANDLE)
+ {
+ //un register profile task in gatt for indication/notifications
+ struct gattc_reg_to_peer_evt_cmd * reg = KE_MSG_ALLOC(GATTC_REG_TO_PEER_EVT_CMD,
+ KE_BUILD_ID(TASK_GATTC, conidx), prf_src_task_get(prf_env, conidx),
+ gattc_reg_to_peer_evt_cmd);
+
+ reg->operation = GATTC_UNREGISTER;
+ reg->start_hdl = svc->shdl;
+ reg->end_hdl = svc->ehdl;
+
+ ke_msg_send(reg);
+ }
+}
+
+
+void prf_disc_svc_send(prf_env_t *prf_env, uint8_t conidx, uint16_t uuid)
+{
+ //send GATT discover primary services by UUID request
+ struct gattc_sdp_svc_disc_cmd * svc_req = KE_MSG_ALLOC_DYN(GATTC_SDP_SVC_DISC_CMD,
+ KE_BUILD_ID(TASK_GATTC, conidx), prf_src_task_get(prf_env, conidx),
+ gattc_sdp_svc_disc_cmd, ATT_UUID_16_LEN);
+
+ //gatt request type: by UUID
+ svc_req->operation = GATTC_SDP_DISC_SVC;
+ //start handle;
+ svc_req->start_hdl = ATT_1ST_REQ_START_HDL;
+ //end handle
+ svc_req->end_hdl = ATT_1ST_REQ_END_HDL;
+
+ // UUID search
+ svc_req->uuid_len = ATT_UUID_16_LEN;
+
+ //set the first two bytes to the value array, LSB to MSB:Health Thermometer Service UUID first
+ co_write16p(&(svc_req->uuid[0]), uuid);
+
+ //send the message to GATT, which will send back the response when it gets it
+ ke_msg_send(svc_req);
+}
+
+
+
+void prf_gatt_write(prf_env_t *prf_env, uint8_t conidx,
+ uint16_t handle, uint8_t* value, uint16_t length, uint8_t operation)
+{
+ if (handle != ATT_INVALID_HANDLE)
+ {
+ struct gattc_write_cmd *wr_char = KE_MSG_ALLOC_DYN(GATTC_WRITE_CMD,
+ KE_BUILD_ID(TASK_GATTC, conidx), prf_src_task_get(prf_env, conidx),
+ gattc_write_cmd, length);
+
+ // Offset
+ wr_char->offset = 0x0000;
+ // cursor always 0
+ wr_char->cursor = 0x0000;
+ // Write Type
+ wr_char->operation = operation;
+ // Characteristic Value attribute handle
+ wr_char->handle = handle;
+ // Value Length
+ wr_char->length = length;
+ // Auto Execute
+ wr_char->auto_execute = true;
+ // Value
+ memcpy(&wr_char->value[0], value, length);
+
+ // Send the message
+ ke_msg_send(wr_char);
+ }
+}
+
+void prf_gatt_write_ntf_ind(prf_env_t *prf_env, uint8_t conidx, uint16_t handle, uint16_t ntf_ind_cfg)
+{
+ uint8_t value[2];
+
+ // put value in air format
+ co_write16p((&value[0]), ntf_ind_cfg);
+ // write value over GATT
+ prf_gatt_write(prf_env, conidx, handle, value, 2, GATTC_WRITE);
+}
+
+uint8_t prf_check_svc_char_validity(uint8_t nb_chars,
+ const struct prf_char_inf* chars,
+ const struct prf_char_def* chars_req)
+{
+ uint8_t status = GAP_ERR_NO_ERROR;
+ uint8_t i;
+
+ for(i = 0; ((i < nb_chars) && (status == GAP_ERR_NO_ERROR)); i++)
+ {
+ if (chars[i].char_hdl == ATT_INVALID_HANDLE)
+ {
+ //If Characteristic is not present, check requirements
+ if (chars_req[i].req_flag == ATT_MANDATORY)
+ {
+ status = PRF_ERR_STOP_DISC_CHAR_MISSING;
+ }
+ }
+ else
+ {
+ //If Characteristic is present, check properties
+ if ((chars[i].prop & chars_req[i].prop_mand) != chars_req[i].prop_mand)
+ {
+ status = PRF_ERR_STOP_DISC_WRONG_CHAR_PROP;
+ }
+ }
+ }
+
+ return (status);
+}
+
+
+uint8_t prf_check_svc_char_uuid128_validity(uint8_t nb_chars,
+ const struct prf_char_inf* chars,
+ const struct prf_char_uuid128_def* chars_req)
+{
+ uint8_t status = GAP_ERR_NO_ERROR;
+ uint8_t i;
+
+ for(i = 0; ((i < nb_chars) && (status == GAP_ERR_NO_ERROR)); i++)
+ {
+ if (chars[i].char_hdl == ATT_INVALID_HANDLE)
+ {
+ //If Characteristic is not present, check requirements
+ if (chars_req[i].req_flag == ATT_MANDATORY)
+ {
+ status = PRF_ERR_STOP_DISC_CHAR_MISSING;
+ }
+ }
+ else
+ {
+ //If Characteristic is present, check properties
+ if ((chars[i].prop & chars_req[i].prop_mand) != chars_req[i].prop_mand)
+ {
+ status = PRF_ERR_STOP_DISC_WRONG_CHAR_PROP;
+ }
+ }
+ }
+
+ return (status);
+}
+
+
+uint8_t prf_check_svc_char_desc_validity(uint8_t descs_size,
+ const struct prf_char_desc_inf* descs,
+ const struct prf_char_desc_def* descs_req,
+ const struct prf_char_inf* chars)
+{
+ uint8_t status = GAP_ERR_NO_ERROR;
+ uint8_t i;
+
+ for(i = 0; ((i < descs_size) && (status == GAP_ERR_NO_ERROR)) ; i++)
+ {
+ if (descs[i].desc_hdl == ATT_INVALID_HANDLE)
+ {
+ //If Descriptor is missing, check if it is mandatory
+ if (descs_req[i].req_flag == ATT_MANDATORY)
+ {
+ //Check if Char is present
+ if (chars[descs_req[i].char_code].char_hdl != ATT_INVALID_HANDLE)
+ {
+ //Char. is present and descriptor not, error
+ status = PRF_ERR_STOP_DISC_CHAR_MISSING;
+ }
+ }
+ }
+ }
+
+ return (status);
+}
+
+
+uint8_t prf_check_svc_char_desc_uuid128_validity(uint8_t descs_size,
+ const struct prf_char_desc_inf* descs,
+ const struct prf_char_desc_uuid128_def* descs_req,
+ const struct prf_char_inf* chars)
+{
+ uint8_t status = GAP_ERR_NO_ERROR;
+ uint8_t i;
+
+ for(i = 0; ((i < descs_size) && (status == GAP_ERR_NO_ERROR)) ; i++)
+ {
+ if (descs[i].desc_hdl == ATT_INVALID_HANDLE)
+ {
+ //If Descriptor is missing, check if it is mandatory
+ if (descs_req[i].req_flag == ATT_MANDATORY)
+ {
+ //Check if Char is present
+ if (chars[descs_req[i].char_code].char_hdl != ATT_INVALID_HANDLE)
+ {
+ //Char. is present and descriptor not, error
+ status = PRF_ERR_STOP_DISC_CHAR_MISSING;
+ }
+ }
+ }
+ }
+
+ return (status);
+}
+
+void prf_extract_svc_info(const struct gattc_sdp_svc_ind* param,
+ uint8_t nb_chars, const struct prf_char_def* chars_req, struct prf_char_inf* chars,
+ uint8_t nb_descs, const struct prf_char_desc_def* descs_req, struct prf_char_desc_inf* descs)
+{
+ //Counters
+ uint8_t svc_char;
+ uint8_t svc_desc;
+ uint8_t fnd_att;
+
+ for (fnd_att=0; fnd_att< (param->end_hdl - param->start_hdl); fnd_att++)
+ {
+ if (param->info[fnd_att].att_type == GATTC_SDP_ATT_CHAR)
+ {
+ uint16_t char_hdl = param->start_hdl+ 1 + fnd_att;
+ uint16_t val_hdl = param->info[fnd_att].att_char.handle;
+ uint8_t val_prop = param->info[fnd_att].att_char.prop;
+ uint8_t char_idx = fnd_att;
+
+ // check that value handle is in a valid range
+ if ((val_hdl <= param->end_hdl) && (val_hdl > (param->start_hdl + fnd_att)))
+ {
+ // retrieve value index
+ uint8_t val_idx = (val_hdl - param->start_hdl - 1);
+
+ //Look over requested characteristics
+ for (svc_char=0; svc_charinfo[val_idx].att.uuid,
+ param->info[val_idx].att.uuid_len, chars_req[svc_char].uuid))
+ {
+ //Save properties and handles
+ chars[svc_char].char_hdl = char_hdl;
+ chars[svc_char].val_hdl = val_hdl;
+ chars[svc_char].prop = val_prop;
+
+ // find end of characteristic handle and discover descriptors
+ do
+ {
+ fnd_att++;
+
+ // found a descriptor
+ if (param->info[fnd_att].att_type == GATTC_SDP_ATT_DESC)
+ {
+ //Retrieve characteristic descriptor handle using UUID
+ for(svc_desc = 0; svc_descinfo[fnd_att].att.uuid,
+ param->info[fnd_att].att.uuid_len, descs_req[svc_desc].uuid)))
+ {
+ descs[svc_desc].desc_hdl = param->start_hdl + 1 + fnd_att;
+ // search for next descriptor
+ break;
+ }
+ }
+ }
+ } while (((param->start_hdl+ 1 + fnd_att) <= param->end_hdl)
+ && (param->info[fnd_att].att_type != GATTC_SDP_ATT_CHAR)
+ && (param->info[fnd_att].att_type != GATTC_SDP_INC_SVC));
+
+ // return to previous valid value
+ fnd_att--;
+ // previous handle was end of the characteristic
+ chars[svc_char].char_ehdl_off = fnd_att - char_idx;
+
+ // search next characteristic
+ break;
+ }
+ }
+ }
+ }
+ }
+}
+
+
+void prf_extract_svc_uuid128_info(const struct gattc_sdp_svc_ind* param,
+ uint8_t nb_chars, const struct prf_char_uuid128_def* chars_uuid128_req, struct prf_char_inf* chars,
+ uint8_t nb_descs, const struct prf_char_desc_uuid128_def* descs_uuid128_req, struct prf_char_desc_inf* descs)
+{
+ //Counters
+ uint8_t svc_char;
+ uint8_t svc_desc;
+ uint8_t fnd_att;
+
+ for (fnd_att=0; fnd_att< (param->end_hdl - param->start_hdl); fnd_att++)
+ {
+ if (param->info[fnd_att].att_type == GATTC_SDP_ATT_CHAR)
+ {
+ uint16_t char_hdl = param->start_hdl+ 1 + fnd_att;
+ uint16_t val_hdl = param->info[fnd_att].att_char.handle;
+ uint8_t val_prop = param->info[fnd_att].att_char.prop;
+ uint8_t char_idx = fnd_att;
+
+ // check that value handle is in a valid range
+ if ((val_hdl <= param->end_hdl) && (val_hdl > (param->start_hdl + fnd_att)))
+ {
+ // retrieve value index
+ uint8_t val_idx = (val_hdl - param->start_hdl - 1);
+
+ //Look over requested characteristics
+ for (svc_char=0; svc_charinfo[val_idx].att.uuid,
+ param->info[val_idx].att.uuid_len, &chars_uuid128_req[svc_char].uuid[0], chars_uuid128_req[svc_char].uuid_len))
+ {
+ //Save properties and handles
+ chars[svc_char].char_hdl = char_hdl;
+ chars[svc_char].val_hdl = val_hdl;
+ chars[svc_char].prop = val_prop;
+
+ // find end of characteristic handle and discover descriptors
+ do
+ {
+ fnd_att++;
+
+ // found a descriptor
+ if (param->info[fnd_att].att_type == GATTC_SDP_ATT_DESC)
+ {
+ //Retrieve characteristic descriptor handle using UUID
+ for(svc_desc = 0; svc_descinfo[fnd_att].att.uuid,
+ param->info[fnd_att].att.uuid_len, descs_uuid128_req[svc_desc].uuid, descs_uuid128_req[svc_desc].uuid_len)))
+ {
+ descs[svc_desc].desc_hdl = param->start_hdl + 1 + fnd_att;
+ // search for next descriptor
+ break;
+ }
+ }
+ }
+ } while (((param->start_hdl+ 1 + fnd_att) <= param->end_hdl)
+ && (param->info[fnd_att].att_type != GATTC_SDP_ATT_CHAR)
+ && (param->info[fnd_att].att_type != GATTC_SDP_INC_SVC));
+
+ // return to previous valid value
+ fnd_att--;
+ // previous handle was end of the characteristic
+ chars[svc_char].char_ehdl_off = fnd_att - char_idx;
+
+ // search next characteristic
+ break;
+ }
+ }
+ }
+ }
+ }
+}
+
+
+#endif //(BLE_CLIENT_PRF)
+
+#if (BLE_CLIENT_PRF || BLE_TIP_SERVER || BLE_AN_SERVER || BLE_PAS_SERVER)
+
+void prf_client_att_info_rsp(prf_env_t *prf_env, uint8_t conidx, uint16_t msg_id,
+ uint8_t status, struct gattc_read_ind const* read_ind)
+{
+ // retrieve value length
+ uint16_t length = 0;
+ if (status == GAP_ERR_NO_ERROR)
+ {
+ length = read_ind->length;
+ }
+
+ // prepare response
+ struct prf_att_info *rsp = KE_MSG_ALLOC_DYN(msg_id,
+ prf_dst_task_get(prf_env, conidx), prf_src_task_get(prf_env, conidx),
+ prf_att_info, length);
+
+ rsp->status = status;
+ rsp->handle = ATT_INVALID_HDL;
+ rsp->length = length;
+
+ // set value array
+ if (read_ind != NULL)
+ {
+ rsp->handle = read_ind->handle;
+ memcpy(&(rsp->value[0]), &(read_ind->value[0]), length);
+ }
+
+ ke_msg_send(rsp);
+}
+#endif //(BLE_CLIENT_PRF || BLE_TIP_SERVER || BLE_AN_SERVER || BLE_PAS_SERVER)
+
+
+#if ((BLE_SERVER_PRF || BLE_CLIENT_PRF))
+
+uint8_t prf_pack_date_time(uint8_t *packed_date, const struct prf_date_time* date_time)
+{
+ co_write16p(packed_date, date_time->year);
+ *(packed_date + 2) = date_time->month;
+ *(packed_date + 3) = date_time->day;
+ *(packed_date + 4) = date_time->hour;
+ *(packed_date + 5) = date_time->min;
+ *(packed_date + 6) = date_time->sec;
+
+ return 7;
+}
+uint8_t prf_unpack_date_time(uint8_t *packed_date, struct prf_date_time* date_time)
+{
+ date_time->year = co_read16p(&(packed_date[0]));
+ date_time->month = packed_date[2];
+ date_time->day = packed_date[3];
+ date_time->hour = packed_date[4];
+ date_time->min = packed_date[5];
+ date_time->sec = packed_date[6];
+
+ return 7;
+}
+
+
+#endif /* ((BLE_SERVER_PRF || BLE_CLIENT_PRF)) */
+#endif // (BLE_PROFILES)
+/// @} PRF_UTILS
+
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/user.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/user.c
new file mode 100644
index 0000000000..40c983c437
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/user.c
@@ -0,0 +1,365 @@
+/**
+ ****************************************************************************************
+ *
+ * @file user.c
+ *
+ * @brief user defined.
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @addtogroup USER
+ * @{
+ ****************************************************************************************
+ */
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "rwip_config.h"
+#include "app.h"
+
+#if (BLE_APP_USER)
+#include "attm.h"
+#include "user.h"
+#include "user_task.h"
+#include "co_utils.h"
+#include "co_endian.h"
+#include "prf_utils.h"
+
+#include "ke_mem.h"
+//#include "interface.h"
+#include "ble_arch.h"
+
+#ifdef N32WB452_BT_API
+#include "n32wb452_ble_api.h"
+
+extern bt_attr_param * g_bt_init;
+#endif
+//#include "att.h"
+/*
+ * HTPT PROFILE ATTRIBUTES
+ *****************************************************************************************/
+
+
+/// Full HTS Database Description - Used to add attributes into the database
+
+const struct attm_desc user_att_db[USER_IDX_NB] =
+{
+ // FF00 Service Declaration
+ [USER_IDX_SVC] = {ATT_DECL_PRIMARY_SERVICE, PERM(RD, ENABLE), 0, 0},
+
+ // FF01 Characteristic Declaration
+ [USER_IDX_WRITE_NOTIFY_CHAR] = {ATT_DECL_CHARACTERISTIC, PERM(RD, ENABLE) | PERM(WRITE_REQ, ENABLE), 0, 0},
+ // Characteristic Value
+
+#ifndef BLE_OTA_WRITE_CHAR_EN
+
+ // Characteristic Value
+ [USER_IDX_WRITE_NOTIFY_VAL] = {ATT_CHAR_WRITE_NOTIFY, PERM(WRITE_COMMAND, ENABLE)|PERM(NTF, ENABLE), PERM(RI, ENABLE), 0x300},
+ //Client Characteristic Configuration Descriptor
+ [USER_IDX_WRITE_NOTIFY_CFG] = {ATT_DESC_CLIENT_CHAR_CFG, PERM(RD, ENABLE) | PERM(WRITE_REQ, ENABLE), 0/*PERM(RI, ENABLE)*/, 0x200},
+#endif
+#ifdef BLE_OTA_WRITE_CHAR_EN
+ // Characteristic Value
+ [USER_IDX_WRITE_NOTIFY_VAL] = {ATT_CHAR_WRITE_NOTIFY,
+ PERM(WRITE_REQ, ENABLE) | PERM(WRITE_COMMAND, ENABLE) /*|PERM(NTF, ENABLE)*/,
+ 0 /*PERM(RI, ENABLE)*/,
+ 0x300},
+ // Client Characteristic Configuration Descriptor
+ [USER_IDX_WRITE_NOTIFY_CFG] = {ATT_DESC_CLIENT_CHAR_CFG,
+ PERM(RD, ENABLE) | PERM(WRITE_REQ, ENABLE),
+ 0 /*PERM(RI, ENABLE)*/,
+ 0x200},
+
+ // Characteristic Declaration
+ [USER_IDX_READ_NOTIFY_CHAR] = {ATT_DECL_CHARACTERISTIC, PERM(RD, ENABLE), 0, 0},
+ // Characteristic Value
+ [USER_IDX_READ_NOTIFY_VAL] = {ATT_CHAR_READ_NOTIFY,
+ /*PERM(RD, ENABLE) |*/ PERM(NTF, ENABLE),
+ (/*PERM(RI, ENABLE)|*/ PERM(NTF, ENABLE)),
+ 0x200},
+ //[USER_IDX_READ_NOTIFY_VAL] = {ATT_CHAR_READ_NOTIFY, PERM(RD, ENABLE) |PERM(NTF, ENABLE), (PERM(RI, ENABLE)|PERM(NTF, ENABLE)), 0x200},
+ //Client Characteristic Configuration Descriptor
+ [USER_IDX_WRITE_NOTIFY2_CFG] = {ATT_DESC_CLIENT_CHAR_CFG, PERM(RD, ENABLE) | /* PERM(WP,ENABLE)|*/PERM(WRITE_REQ, ENABLE), 0/*PERM(RI, ENABLE)*/, 0x200},
+#endif
+};
+
+#ifdef N32WB452_BT_API
+uint16_t get_user_character_perm(uint16_t perm)
+{
+ uint16_t ret = 0;
+
+// ble_log(BLE_DEBUG,"PERM(WRITE_COMMAND, ENABLE) = %0x.\r\n", PERM(WRITE_COMMAND, ENABLE));
+// ble_log(BLE_DEBUG,"PERM(NTF, ENABLE) = %0x.\r\n", PERM(NTF, ENABLE));
+
+ if (perm & BT_RD_PERM) {
+ ret |= PERM(RD, ENABLE);
+ }
+
+ if (perm & BT_WRITE_PERM) {
+ ret |= PERM(WRITE_COMMAND, ENABLE);
+// ble_log(BLE_DEBUG,"ret1 = %x.\r\n", ret);
+ }
+
+ if (perm & BT_WRITE_REQ_PERM) {
+ ret |= PERM(WRITE_REQ, ENABLE);
+ }
+
+ if (perm & BT_NTF_PERM) {
+ ret |= PERM(NTF, ENABLE);
+// ble_log(BLE_DEBUG,"ret2 = %x.\r\n", ret);
+ }
+
+ return ret;
+}
+#endif
+
+/*
+ * LOCAL FUNCTION DEFINITIONS
+ ****************************************************************************************
+ */
+static uint8_t user_init(struct prf_task_env *env, uint16_t *start_hdl, uint16_t app_task,uint8_t sec_lvl, struct user_db_cfg *params)
+{
+#ifdef N32WB452_BT_API
+ //uint16_t perm;
+ volatile struct attm_desc user_att_db_api_define[USER_IDX_NB] = {0};
+#endif
+
+ // Service content flag
+ uint16_t cfg_flag = (1<service[0].character[0].uuid \
+ && (g_bt_init->service[0].character[0].permission & BT_WRITE_PERM)
+ && (g_bt_init->service[0].character[0].permission & BT_NTF_PERM)) {
+ user_att_db_api_define[USER_IDX_WRITE_NOTIFY_VAL].uuid = ATT_UUID_16(g_bt_init->service[0].character[0].uuid);
+ user_att_db_api_define[USER_IDX_WRITE_NOTIFY_VAL].perm = get_user_character_perm(g_bt_init->service[0].character[0].permission);
+ user_att_db_api_define[USER_IDX_WRITE_NOTIFY_VAL].ext_perm = 0;
+ user_att_db_api_define[USER_IDX_WRITE_NOTIFY_VAL].max_size = 0x300;
+ }
+
+ user_att_db_api_define[USER_IDX_WRITE_NOTIFY_VAL].uuid = ATT_UUID_16(g_bt_init->service[0].character[0].uuid);
+
+ status = attm_svc_create_db(start_hdl, (uint16_t)g_bt_init->service[0].svc_uuid, (uint8_t *)&cfg_flag,USER_IDX_NB, NULL, env->task, &user_att_db_api_define[0],(sec_lvl & (PERM_MASK_SVC_DIS | PERM_MASK_SVC_AUTH | PERM_MASK_SVC_EKS)) | PERM(SVC_MI, DISABLE));
+ } else {
+ status = attm_svc_create_db(start_hdl, (uint16_t)ATT_SVC_UKEY_SERVICE, (uint8_t *)&cfg_flag,USER_IDX_NB, NULL, env->task, &user_att_db[0],(sec_lvl & (PERM_MASK_SVC_DIS | PERM_MASK_SVC_AUTH | PERM_MASK_SVC_EKS)) | PERM(SVC_MI, DISABLE));
+ }
+#else
+ status = attm_svc_create_db(start_hdl, (uint16_t)ATT_SVC_UKEY_SERVICE, (uint8_t *)&cfg_flag,USER_IDX_NB, NULL, env->task, &user_att_db[0],(sec_lvl & (PERM_MASK_SVC_DIS | PERM_MASK_SVC_AUTH | PERM_MASK_SVC_EKS)) | PERM(SVC_MI, DISABLE));
+#endif
+ if (status == ATT_ERR_NO_ERROR)
+ {
+ //-------------------- allocate memory required for the profile ---------------------
+ struct user_env_tag *user_env =
+ (struct user_env_tag *) ke_malloc(sizeof(struct user_env_tag), KE_MEM_ATT_DB);
+
+ // allocate PROXR required environment variable
+ env->env = (prf_env_t *) user_env;
+
+ user_env->shdl = *start_hdl;
+ user_env->prf_env.app_task = app_task | (PERM_GET(sec_lvl, SVC_MI) ? PERM(PRF_MI, ENABLE) : PERM(PRF_MI, DISABLE));
+ user_env->prf_env.prf_task = env->task | PERM(PRF_MI, DISABLE);
+
+ // initialize environment variable
+ env->id = TASK_ID_USER;
+ env->desc.idx_max = 1;
+ env->desc.state = user_env->state;
+ env->desc.default_handler = &user_default_handler;
+
+ //Save features on the environment
+ user_env->features = params->features;
+ user_env->operation = NULL;
+ memset(user_env->ntf_ind_cfg, 0 , sizeof(user_env->ntf_ind_cfg));
+
+ // service is ready, go into an Idle state
+ ke_state_set(env->task, USER_IDLE);
+ }
+ return (status);
+}
+
+
+static void user_destroy(struct prf_task_env *env)
+{
+ struct user_env_tag *user_env = (struct user_env_tag *) env->env;
+
+ // free profile environment variables
+ if (user_env->operation != NULL)
+ {
+ ke_free(user_env->operation);
+ }
+
+
+ env->env = NULL;
+ ke_free(user_env);
+}
+
+static void user_create(struct prf_task_env *env, uint8_t conidx)
+{
+ /* Clear configuration for this connection */
+ struct user_env_tag *user_env = (struct user_env_tag *) env->env;
+ //user_env->ntf_ind_cfg[conidx] = 0x03;
+ user_env->ntf_ind_cfg[USER_IDX_WRITE_NOTIFY_CFG] = USER_DATA_NTF;
+#ifdef BLE_OTA_WRITE_CHAR_EN
+ user_env->ntf_ind_cfg[USER_IDX_WRITE_NOTIFY2_CFG] = USER_DATA_NTF;
+#endif
+}
+
+static void user_cleanup(struct prf_task_env *env, uint8_t conidx, uint8_t reason)
+{
+ /* Clear configuration for this connection */
+ struct user_env_tag *user_env = (struct user_env_tag *) env->env;
+ user_env->ntf_ind_cfg[USER_IDX_WRITE_NOTIFY_CFG] = USER_DATA_NTF_IND_DISABLE;
+#ifdef BLE_OTA_WRITE_CHAR_EN
+ user_env->ntf_ind_cfg[USER_IDX_WRITE_NOTIFY2_CFG] = USER_DATA_NTF_IND_DISABLE;
+#endif
+
+}
+
+
+/*
+ * GLOBAL VARIABLE DEFINITIONS
+ ****************************************************************************************
+ */
+
+/// HTPT Task interface required by profile manager
+const struct prf_task_cbs user_itf =
+{
+ (prf_init_fnct) user_init,
+ user_destroy,
+ user_create,
+ user_cleanup,
+};
+
+
+
+
+const struct prf_task_cbs *user_prf_itf_get(void)
+{
+ return &user_itf;
+}
+
+
+uint16_t user_att_hdl_get(struct user_env_tag *user_env, uint8_t att_idx)
+{
+ uint16_t handle = user_env->shdl;
+
+ handle += att_idx;
+
+ return handle;
+}
+
+uint8_t user_att_idx_get(struct user_env_tag *user_env, uint16_t handle)
+{
+ uint16_t handle_ref = user_env->shdl;
+ uint8_t att_idx = ATT_INVALID_IDX;
+
+ if (handle >handle_ref)
+ {
+ att_idx = handle - handle_ref;
+ }
+
+ return att_idx;
+}
+
+void user_exe_operation(void)
+{
+ struct user_env_tag *user_env = PRF_ENV_GET(USER, user);
+
+ ASSERT_ERR(user_env->operation != NULL);
+
+ bool finished = true;
+
+ while (user_env->operation->cursor < BLE_CONNECTION_MAX)
+ {
+ // check if this type of event is enabled
+ if (( ( /*user_env->ntf_ind_cfg[user_env->operation->cursor] & */ user_env->operation->op) != 0) /*&& (user_env->operation->conidx != user_env->operation->cursor)*/)
+ {
+ // trigger the event
+ struct gattc_send_evt_cmd *evt = KE_MSG_ALLOC_DYN(GATTC_SEND_EVT_CMD,KE_BUILD_ID(TASK_GATTC , user_env->operation->cursor), prf_src_task_get(&user_env->prf_env, 0),gattc_send_evt_cmd, user_env->operation->length);
+ evt->operation = (user_env->operation->op != USER_DATA_NTF) ? GATTC_INDICATE : GATTC_NOTIFY;
+ evt->length = user_env->operation->length;
+ evt->handle = user_env->operation->handle;
+ memcpy(evt->value, user_env->operation->data, evt->length);
+ ke_msg_send(evt);
+
+ finished = false;
+ user_env->operation->cursor++;
+ break;
+ }
+ user_env->operation->cursor++;
+ }
+
+ // check if operation is finished
+ if (finished)
+ {
+
+ // do not send response if operation has been locally requested
+ if (user_env->operation->dest_id != prf_src_task_get(&user_env->prf_env, 0))
+ {
+
+ // send response to requester
+ struct user_upd_rsp *rsp = KE_MSG_ALLOC(((user_env->operation->op == USER_DATA_NTF) ? USER_NOTIFY_RSP : USER_INTV_RSP),user_env->operation->dest_id, prf_src_task_get(&user_env->prf_env, 0),user_upd_rsp);
+ rsp->status = GAP_ERR_NO_ERROR;
+ ke_msg_send(rsp);
+ }
+
+ // free operation
+ ke_free(user_env->operation);
+ user_env->operation = NULL;
+ // go back to idle state
+ ke_state_set(prf_src_task_get(&(user_env->prf_env), 0), USER_IDLE);
+ }
+}
+
+
+
+uint8_t user_update_ntf_ind_cfg(uint8_t conidx, uint8_t cfg, uint16_t valid_val, uint8_t idx, uint16_t value)
+{
+ struct user_env_tag *user_env = PRF_ENV_GET(USER, user);
+ uint8_t status = GAP_ERR_NO_ERROR;
+
+ if ((value != valid_val) && (value != PRF_CLI_STOP_NTFIND))
+ {
+ status = PRF_APP_ERROR;
+ }
+
+ user_env->ntf_ind_cfg[idx] = value;
+// else if (value == valid_val)
+// {
+// user_env->ntf_ind_cfg[idx]|= cfg;
+// }
+// else
+// {
+// user_env->ntf_ind_cfg[idx] &= ~cfg;
+// }
+
+ if (status == GAP_ERR_NO_ERROR)
+ {
+ // no msg handler blank by ding.yuanwwu
+ // inform application that notification/indication configuration has changed
+// struct user_cfg_indntf_ind *ind = KE_MSG_ALLOC(USER_CFG_INDNTF_IND, prf_dst_task_get(&user_env->prf_env, conidx), prf_src_task_get(&user_env->prf_env, conidx),user_cfg_indntf_ind);
+// ind->conidx = conidx;
+// ind->ntf_ind_cfg = user_env->ntf_ind_cfg[conidx];
+// ke_msg_send(ind);
+ }
+
+ return (status);
+}
+
+#endif //BLE_HT_THERMOM
+
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/user_task.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/user_task.c
new file mode 100644
index 0000000000..38870b7aba
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/user_task.c
@@ -0,0 +1,438 @@
+/**
+ ****************************************************************************************
+ *
+ * @file user_task.c
+ *
+ * @brief
+ *
+ * Copyright (C) RivieraWaves 2009-2016
+ *
+ *
+ ****************************************************************************************
+ */
+
+/**
+ ****************************************************************************************
+ * @addtogroup HTPTTASK
+ * @{
+ ****************************************************************************************
+ */
+
+
+/*
+ * INCLUDE FILES
+ ****************************************************************************************
+ */
+#include "rwip_config.h"
+
+#if (BLE_APP_USER)
+#include "app.h"
+#include "gap.h"
+#include "gattc_task.h"
+#include "attm.h"
+#include "user.h"
+#include "user_task.h"
+#include "prf_utils.h"
+#include "app_user.h"
+#include "app_task.h"
+#include "ke_mem.h"
+#include "co_utils.h"
+//#include "interface.h"
+#include "ble_arch.h"
+#include "ke_timer.h"
+
+#ifdef N32WB452_BT_API
+#include "n32wb452_data_fifo.h"
+#include "n32wb452_ble_api.h"
+#include "n32wb452_log_level.h"
+
+extern uint8_t rx_fff5_chr[300];
+extern uint16_t rx_fff5_len;
+extern uint8_t rx_fff5_flag;
+extern uint16_t rvc_total;
+
+extern bt_event_callback_handler_t g_pcallback;
+
+#endif
+
+/*
+ * FUNCTION DEFINITIONS
+ ****************************************************************************************
+ */
+//#include "Bkey_user.h"
+/**
+ ****************************************************************************************
+ * @brief Handles reception of the @ref HTPT_ENABLE_REQ message.
+ * The handler enables the Health Thermometer Profile Thermometer Role.
+ * @param[in] msgid Id of the message received (probably unused).
+ * @param[in] param Pointer to the parameters of the message.
+ * @param[in] dest_id ID of the receiving task instance (probably unused).
+ * @param[in] src_id ID of the sending task instance.
+ * @return If the message was consumed or not.
+ ****************************************************************************************
+ */
+static int user_enable_req_handler(ke_msg_id_t const msgid,
+ struct user_enable_req const *param,
+ ke_task_id_t const dest_id,
+ ke_task_id_t const src_id)
+{
+ uint8_t status = PRF_ERR_REQ_DISALLOWED;
+ // check state of the task
+ if (gapc_get_conhdl(param->conidx) != GAP_INVALID_CONHDL)
+ {
+ // restore Bond Data
+ struct user_env_tag *user_env = PRF_ENV_GET(USER, user);
+ user_env->ntf_ind_cfg[param->conidx] = param->ntf_ind_cfg;
+ status = GAP_ERR_NO_ERROR;
+
+ }
+
+ // send response
+ struct user_enable_rsp *rsp = KE_MSG_ALLOC(USER_ENABLE_RSP, src_id, dest_id, user_enable_rsp);
+ rsp->conidx = param->conidx;
+ rsp->status = status;
+ ke_msg_send(rsp);
+
+ return (KE_MSG_CONSUMED);
+}
+
+/**
+ ****************************************************************************************
+ * @brief Handles reception of the @ref HTPT_TEMP_SEND_REQ message.
+ * @param[in] msgid Id of the message received (probably unused).
+ * @param[in] param Pointer to the parameters of the message.
+ * @param[in] dest_id ID of the receiving task instance (probably unused).
+ * @param[in] src_id ID of the sending task instance.
+ * @return If the message was consumed or not.
+ ****************************************************************************************
+ */
+static int user_data_notify_req_handler(ke_msg_id_t const msgid,
+ struct user_notify_req const *param,
+ ke_task_id_t const dest_id,
+ ke_task_id_t const src_id)
+{
+ // Status
+ int msg_status = KE_MSG_SAVED;
+ uint8_t state = ke_state_get(dest_id);
+
+ // check state of the task
+ if (state == USER_IDLE)
+ {
+ // Get the address of the environment
+ struct user_env_tag *user_env = PRF_ENV_GET(USER, user);
+
+ // for intermediate measurement, feature must be enabled
+ if (/*!(param->send_param_length) &&*/ (!USER_IS_FEATURE_SUPPORTED(user_env->features, USER_DATA_NOTIFY_CHAR_SUP)))
+ {
+ struct user_notify_rsp *rsp = KE_MSG_ALLOC(USER_NOTIFY_RSP, src_id, dest_id, user_notify_rsp);
+ rsp->status = PRF_ERR_FEATURE_NOT_SUPPORTED;
+ ke_msg_send(rsp);
+ }
+ else
+ {
+ // allocate operation to execute
+ user_env->operation = (struct user_op *) ke_malloc(sizeof(struct user_op) + param->send_param_length, KE_MEM_ATT_DB);
+
+ // Initialize operation parameters
+ user_env->operation->cursor = 0;
+ user_env->operation->dest_id = src_id;
+ user_env->operation->conidx = GAP_INVALID_CONIDX;
+
+ // Stable measurement indication or intermediate measurement notification
+
+ user_env->operation->op = user_env->ntf_ind_cfg[param->att_idx+1];// USER_DATA_NTF;
+ //è“牙 notify handle
+ user_env->operation->handle = USER_HANDLE(param->att_idx);
+
+
+ //Pack the temperature measurement value
+
+ user_env->operation->length = param->send_param_length;
+ memcpy(&(user_env->operation->data[0]), param->send_param_payload, user_env->operation->length);
+ // put task in a busy state
+
+ ke_state_set(dest_id, USER_BUSY);
+
+ user_exe_operation();
+ }
+
+ msg_status = KE_MSG_CONSUMED;
+ }
+
+ return (msg_status);
+}
+
+
+/**
+ ****************************************************************************************
+ * @brief Handles reception of the attribute info request message.
+ *
+ * @param[in] msgid Id of the message received (probably unused).
+ * @param[in] param Pointer to the parameters of the message.
+ * @param[in] dest_id ID of the receiving task instance (probably unused).
+ * @param[in] src_id ID of the sending task instance.
+ * @return If the message was consumed or not.
+ ****************************************************************************************
+ */
+static int user_gattc_att_info_req_ind_handler(ke_msg_id_t const msgid,
+ struct gattc_att_info_req_ind *param,
+ ke_task_id_t const dest_id,
+ ke_task_id_t const src_id)
+{
+
+ struct user_env_tag *user_env = PRF_ENV_GET(USER, user);
+
+ uint8_t att_idx = USER_IDX(param->handle);
+ struct gattc_att_info_cfm *cfm;
+
+ //Send write response
+ cfm = KE_MSG_ALLOC(GATTC_ATT_INFO_CFM, src_id, dest_id, gattc_att_info_cfm);
+ cfm->handle = param->handle;
+
+
+ ke_msg_send(cfm);
+
+ return (KE_MSG_CONSUMED);
+}
+
+
+
+
+
+
+/**
+ ****************************************************************************************
+ * @brief Handles reception of the @ref GL2C_CODE_ATT_WR_CMD_IND message.
+ * The handler compares the new values with current ones and notifies them if they changed.
+ * @param[in] msgid Id of the message received (probably unused).
+ * @param[in] param Pointer to the parameters of the message.
+ * @param[in] dest_id ID of the receiving task instance (probably unused).
+ * @param[in] src_id ID of the sending task instance.
+ * @return If the message was consumed or not.
+ ****************************************************************************************
+ */
+static int user_gattc_write_req_ind_handler(ke_msg_id_t const msgid,
+ struct gattc_write_req_ind const *param,
+ ke_task_id_t const dest_id,
+ ke_task_id_t const src_id)
+{
+#ifdef N32WB452_BT_API
+ int32_t ret;
+#endif
+
+
+ struct user_env_tag *user_env = PRF_ENV_GET(USER, user);
+ uint8_t status = ATT_ERR_NO_ERROR;
+ int msg_status = KE_MSG_CONSUMED;
+ uint8_t conidx = KE_IDX_GET(src_id);
+ // to check if confirmation message should be send
+ uint8_t att_idx = USER_IDX(param->handle);
+// uint32_t i;
+ // ble_log(BLE_DEBUG,"%d\r\n",att_idx);
+ if (param->length > USER_DATA_LEN_MAX)
+ {
+ status = PRF_ERR_UNEXPECTED_LEN;
+ }
+ else
+ {
+// printf("user_gattc_write_req_ind_handler, idx = %x\r\n", att_idx);
+ switch (att_idx)
+ {
+ case USER_IDX_WRITE_NOTIFY_VAL:
+ {
+#ifdef N32WB452_BT_API
+
+ ble_log(BLE_DEBUG,"w[%x,%d].\r\n", param->value, param->length);
+ ret = fifo_write(param->value, param->length);
+ if (ret != E_OK) {
+ ble_log(BLE_DEBUG,"write err.\r\n");
+ }
+
+ if (g_pcallback) {
+ (*g_pcallback)(BT_EVENT_RCV_DATA, param->value, param->length, att_idx);
+ }
+#else
+
+ // test for NK-bluetooth apk test
+ ble_log(BLE_DEBUG,"curlen=%d,totallen=%d,buf=0x%x[basebuf:%x].\r\n", app_env.rx_data.RxCurrentLen, app_env.rx_data.RxTotalLen, param->value, app_env.rx_data.RxBuf);
+ ble_log(BLE_DEBUG,"RECV[%02x]: ",param->length);
+ for(i=0; ilength; i++)
+ {
+ ble_log(BLE_DEBUG,"%02X, ",param->value[i]);
+ }
+ ble_log(BLE_DEBUG,"\r\n");
+ ble_log(BLE_DEBUG,"1 curlen=%d, TotalLen = %d.\r\n", app_env.rx_data.RxCurrentLen, app_env.rx_data.RxTotalLen);
+
+ if (app_env.rx_data.RxTotalLen == 0)
+ {
+ app_env.rx_data.RxCurrentLen = 0;
+ app_env.rx_data.RxTotalLen = param->value[0] + (param->value[1]<<8) + 2;
+ ble_log(BLE_DEBUG,"2RxTotalLen = %d.\r\n", app_env.rx_data.RxTotalLen);
+
+ ASSERT_ERR( app_env.rx_data.RxTotalLen < RX_DAT_BUF_SIZE );
+ }
+
+ memcpy(app_env.rx_data.RxBuf+app_env.rx_data.RxCurrentLen, param->value,param->length);
+ app_env.rx_data.RxCurrentLen += param->length;
+ if (app_env.rx_data.RxCurrentLen >= app_env.rx_data.RxTotalLen)
+ {
+ ble_log(BLE_DEBUG,"3data_notify[%d,%d].\r\n", app_env.rx_data.RxCurrentLen, app_env.rx_data.RxTotalLen);
+
+ app_user_data_notify(app_env.rx_data.RxTotalLen, app_env.rx_data.RxBuf, USER_IDX_WRITE_NOTIFY_VAL);
+ app_env.rx_data.RxTotalLen = 0;
+ app_env.rx_data.RxCurrentLen = 0;
+ }
+#endif
+ }
+
+ break;
+#ifdef BLE_OTA_WRITE_CHAR_EN
+ case USER_IDX_WRITE_NOTIFY2_CFG:
+ {
+ status = user_update_ntf_ind_cfg(conidx, USER_DATA_NTF, PRF_CLI_START_NTF, att_idx, co_read16p(param->value));
+ }
+ break;
+#endif
+ case USER_IDX_WRITE_NOTIFY_CFG: //0xFFF5 NOTIFY ENABLE
+ {
+ status = user_update_ntf_ind_cfg(conidx, USER_DATA_NTF, PRF_CLI_START_NTF, att_idx, co_read16p(param->value));
+ }
+ break;
+
+ default:
+ {
+ status = ATT_ERR_REQUEST_NOT_SUPPORTED;
+ }
+ break;
+ }
+ }
+ //Send write response
+ struct gattc_write_cfm *cfm = KE_MSG_ALLOC(GATTC_WRITE_CFM, src_id, dest_id, gattc_write_cfm);
+ cfm->handle = param->handle;
+ cfm->status = status;
+ ke_msg_send(cfm);
+
+ return (msg_status);
+}
+
+
+/**
+ ****************************************************************************************
+ * @brief Handles reception of the @ref GATTC_READ_REQ_IND message.
+ * @param[in] msgid Id of the message received (probably unused).
+ * @param[in] param Pointer to the parameters of the message.
+ * @param[in] dest_id ID of the receiving task instance (probably unused).
+ * @param[in] src_id ID of the sending task instance.
+ * @return If the message was consumed or not.
+ ****************************************************************************************
+ */
+static int user_gattc_read_req_ind_handler(ke_msg_id_t const msgid, struct gattc_read_req_ind const *param,
+ ke_task_id_t const dest_id, ke_task_id_t const src_id)
+{
+ struct user_env_tag *user_env = PRF_ENV_GET(USER, user);
+ uint8_t value_size = 0;
+ uint8_t status = ATT_ERR_NO_ERROR;
+ uint8_t value[USER_DATA_LEN_MAX];
+ // retrieve handle information
+ uint8_t att_idx = USER_IDX(param->handle);
+ switch (att_idx)
+ {
+#ifdef BLE_OTA_WRITE_CHAR_EN
+ case USER_IDX_READ_NOTIFY_VAL:
+ {
+#if 1 // lizhk add, fff7 read encryption status.
+ if (ke_state_get(TASK_APP)!= APPM_ENCRYPTED)
+ {
+ memcpy(value, (uint8_t *)"\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 20);
+ value_size = 20;
+ }
+ else
+ {
+ memcpy(value, (uint8_t *)"\x17\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 20);
+ value_size = 20;
+ }
+#endif
+ break;
+ }
+#endif
+
+ case USER_IDX_WRITE_NOTIFY_CFG:
+#if BLE_OTA_WRITE_CHAR_EN
+ case USER_IDX_WRITE_NOTIFY2_CFG:
+ {
+ *(uint16_t *)value = user_env->ntf_ind_cfg[att_idx];
+ value_size = 2;
+ }
+ break;
+#endif
+
+ default:
+ {
+ status = ATT_ERR_REQUEST_NOT_SUPPORTED;
+ }
+ break;
+ }
+ // Send data to peer device
+ struct gattc_read_cfm *cfm = KE_MSG_ALLOC_DYN(GATTC_READ_CFM, src_id, dest_id, gattc_read_cfm, value_size);
+ cfm->length = value_size;
+ memcpy(cfm->value, value, value_size);
+ cfm->handle = param->handle;
+ cfm->status = status;
+ ke_msg_send(cfm);// Send value to peer device.
+ return (KE_MSG_CONSUMED);
+}
+
+/**
+ ****************************************************************************************
+ * @brief Handles @ref GATTC_CMP_EVT for GATTC_NOTIFY and GATT_INDICATE message meaning
+ * that Measurement notification/indication has been correctly sent to peer device
+ *
+ *
+ * @param[in] msgid Id of the message received.
+ * @param[in] param Pointer to the parameters of the message.
+ * @param[in] dest_id ID of the receiving task instance
+ * @param[in] src_id ID of the sending task instance.
+ * @return If the message was consumed or not.
+ ****************************************************************************************
+ */
+static int user_gattc_cmp_evt_handler(ke_msg_id_t const msgid, struct gattc_cmp_evt const *param,
+ ke_task_id_t const dest_id, ke_task_id_t const src_id)
+{
+ // continue operation execution
+
+ user_exe_operation();
+
+ return (KE_MSG_CONSUMED);
+}
+
+
+/*
+ * GLOBAL VARIABLE DEFINITIONS
+ ****************************************************************************************
+ */
+
+
+
+/// Default State handlers definition
+const struct ke_msg_handler user_default_state[] =
+{
+ {USER_ENABLE_REQ, (ke_msg_func_t) user_enable_req_handler},
+ {USER_NOTIFY_REQ, (ke_msg_func_t) user_data_notify_req_handler},
+
+ {GATTC_ATT_INFO_REQ_IND, (ke_msg_func_t) user_gattc_att_info_req_ind_handler},
+ {GATTC_WRITE_REQ_IND, (ke_msg_func_t) user_gattc_write_req_ind_handler},
+ {GATTC_READ_REQ_IND, (ke_msg_func_t) user_gattc_read_req_ind_handler},
+ {GATTC_CMP_EVT, (ke_msg_func_t) user_gattc_cmp_evt_handler},
+
+};
+
+
+///Specifies the message handlers that are common to all states.
+const struct ke_state_handler user_default_handler = KE_STATE_HANDLER(user_default_state);
+//const struct ke_state_handler user1_default_handler = KE_STATE_HANDLER(user1_default_state);
+//const struct ke_state_handler user2_default_handler = KE_STATE_HANDLER(user2_default_state);
+
+#endif //BLE_HT_THERMOM
+
+/// @} HTPTTASK
+
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/misc.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/misc.h
new file mode 100644
index 0000000000..caa55e8b96
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/misc.h
@@ -0,0 +1,228 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file misc.h
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __MISC_H__
+#define __MISC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32wb452.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup MISC
+ * @{
+ */
+
+/** @addtogroup MISC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief NVIC Init Structure definition
+ */
+
+typedef struct
+{
+ uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
+ This parameter can be a value of @ref IRQn_Type
+ (For the complete N32WB452 Devices IRQ Channels list, please
+ refer to n32wb452.h file) */
+
+ uint8_t
+ NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
+ specified in NVIC_IRQChannel. This parameter can be a value
+ between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+ uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
+ in NVIC_IRQChannel. This parameter can be a value
+ between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+ FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
+ will be enabled or disabled.
+ This parameter can be set either to ENABLE or DISABLE */
+} NVIC_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup NVIC_Priority_Table
+ * @{
+ */
+
+/**
+@code
+ The table below gives the allowed values of the pre-emption priority and subpriority according
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
+ ============================================================================================================================
+ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
+ ============================================================================================================================
+ NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption
+priority | | | 4 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption
+priority | | | 3 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption
+priority | | | 2 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption
+priority | | | 1 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption
+priority | | | 0 bits for subpriority
+ ============================================================================================================================
+@endcode
+*/
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup Vector_Table_Base
+ * @{
+ */
+
+#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
+#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || ((VECTTAB) == NVIC_VectTab_FLASH))
+/**
+ * @}
+ */
+
+/** @addtogroup System_Low_Power
+ * @{
+ */
+
+#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || ((LP) == NVIC_LP_SLEEPDEEP) || ((LP) == NVIC_LP_SLEEPONEXIT))
+/**
+ * @}
+ */
+
+/** @addtogroup Preemption_Priority_Group
+ * @{
+ */
+
+#define NVIC_PriorityGroup_0 \
+ ((uint32_t)0x700) /*!< 0 bits for pre-emption priority \
+ 4 bits for subpriority */
+#define NVIC_PriorityGroup_1 \
+ ((uint32_t)0x600) /*!< 1 bits for pre-emption priority \
+ 3 bits for subpriority */
+#define NVIC_PriorityGroup_2 \
+ ((uint32_t)0x500) /*!< 2 bits for pre-emption priority \
+ 2 bits for subpriority */
+#define NVIC_PriorityGroup_3 \
+ ((uint32_t)0x400) /*!< 3 bits for pre-emption priority \
+ 1 bits for subpriority */
+#define NVIC_PriorityGroup_4 \
+ ((uint32_t)0x300) /*!< 4 bits for pre-emption priority \
+ 0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP) \
+ (((GROUP) == NVIC_PriorityGroup_0) || ((GROUP) == NVIC_PriorityGroup_1) || ((GROUP) == NVIC_PriorityGroup_2) \
+ || ((GROUP) == NVIC_PriorityGroup_3) || ((GROUP) == NVIC_PriorityGroup_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup SysTick_clock_source
+ * @{
+ */
+
+//#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) ((SOURCE) == SysTick_CLKSource_HCLK)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Exported_Functions
+ * @{
+ */
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitType* NVIC_InitStruct);
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState Cmd);
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MISC_H__ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_adc.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_adc.h
new file mode 100644
index 0000000000..c8984596ed
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_adc.h
@@ -0,0 +1,612 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_adc.h
+ * @author Nations
+ * @version v1.0.3
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32WB452_ADC_H__
+#define __N32WB452_ADC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32wb452.h"
+#include
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+#define VREF1P2_CTRL (*(uint32_t*)(0x40001800+0x20))
+#define _EnVref1p2() do{VREF1P2_CTRL|=(1<<10);}while (0);
+#define _DisVref1p2() do{VREF1P2_CTRL&=~(1<<10);}while (0);
+/** @addtogroup ADC
+ * @{
+ */
+
+/** @addtogroup ADC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief ADC Init structure definition
+ */
+typedef struct
+{
+ uint32_t WorkMode; /*!< Configures the ADC to operate in independent or
+ dual mode.
+ This parameter can be a value of @ref ADC_mode */
+
+ FunctionalState MultiChEn; /*!< Specifies whether the conversion is performed in
+ Scan (multichannels) or Single (one channel) mode.
+ This parameter can be set to ENABLE or DISABLE */
+
+ FunctionalState ContinueConvEn; /*!< Specifies whether the conversion is performed in
+ Continuous or Single mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t ExtTrigSelect; /*!< Defines the external trigger used to start the analog
+ to digital conversion of regular channels. This parameter
+ can be a value of @ref
+ ADC_external_trigger_sources_for_regular_channels_conversion */
+
+ uint32_t DatAlign; /*!< Specifies whether the ADC data alignment is left or right.
+ This parameter can be a value of @ref ADC_data_align */
+
+ uint8_t ChsNumber; /*!< Specifies the number of ADC channels that will be converted
+ using the sequencer for regular channel group.
+ This parameter must range from 1 to 16. */
+} ADC_InitType;
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Exported_Constants
+ * @{
+ */
+
+#define IsAdcModule(PERIPH) (((PERIPH) == ADC1) || ((PERIPH) == ADC2))
+
+#define IsAdcDmaModule(PERIPH) (((PERIPH) == ADC1) || ((PERIPH) == ADC2))
+
+/** @addtogroup ADC_mode
+ * @{
+ */
+
+#define ADC_WORKMODE_INDEPENDENT ((uint32_t)0x00000000)
+#define ADC_WORKMODE_REG_INJECT_SIMULT ((uint32_t)0x00010000)
+#define ADC_WORKMODE_REG_SIMULT_ALTER_TRIG ((uint32_t)0x00020000)
+#define ADC_WORKMODE_INJ_SIMULT_FAST_INTERL ((uint32_t)0x00030000)
+#define ADC_WORKMODE_INJ_SIMULT_SLOW_INTERL ((uint32_t)0x00040000)
+#define ADC_WORKMODE_INJ_SIMULT ((uint32_t)0x00050000)
+#define ADC_WORKMODE_REG_SIMULT ((uint32_t)0x00060000)
+#define ADC_WORKMODE_FAST_INTERL ((uint32_t)0x00070000)
+#define ADC_WORKMODE_SLOW_INTERL ((uint32_t)0x00080000)
+#define ADC_WORKMODE_ALTER_TRIG ((uint32_t)0x00090000)
+
+#define IsAdcWorkMode(MODE) \
+ (((MODE) == ADC_WORKMODE_INDEPENDENT) || ((MODE) == ADC_WORKMODE_REG_INJECT_SIMULT) \
+ || ((MODE) == ADC_WORKMODE_REG_SIMULT_ALTER_TRIG) || ((MODE) == ADC_WORKMODE_INJ_SIMULT_FAST_INTERL) \
+ || ((MODE) == ADC_WORKMODE_INJ_SIMULT_SLOW_INTERL) || ((MODE) == ADC_WORKMODE_INJ_SIMULT) \
+ || ((MODE) == ADC_WORKMODE_REG_SIMULT) || ((MODE) == ADC_WORKMODE_FAST_INTERL) \
+ || ((MODE) == ADC_WORKMODE_SLOW_INTERL) || ((MODE) == ADC_WORKMODE_ALTER_TRIG))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_external_trigger_sources_for_regular_channels_conversion
+ * @{
+ */
+
+#define ADC_EXT_TRIGCONV_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */
+#define ADC_EXT_TRIGCONV_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */
+#define ADC_EXT_TRIGCONV_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */
+#define ADC_EXT_TRIGCONV_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */
+#define ADC_EXT_TRIGCONV_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */
+#define ADC_EXT_TRIGCONV_EXT_INT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */
+
+#define ADC_EXT_TRIGCONV_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 */
+#define ADC_EXT_TRIGCONV_NONE ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 */
+
+
+#define IsAdcExtTrig(REGTRIG) \
+ (((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC2) \
+ || ((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC3) || ((REGTRIG) == ADC_EXT_TRIGCONV_T2_CC2) \
+ || ((REGTRIG) == ADC_EXT_TRIGCONV_T3_TRGO) || ((REGTRIG) == ADC_EXT_TRIGCONV_T4_CC4) \
+ || ((REGTRIG) == ADC_EXT_TRIGCONV_EXT_INT11_TIM8_TRGO) || ((REGTRIG) == ADC_EXT_TRIGCONV_NONE))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_data_align
+ * @{
+ */
+
+#define ADC_DAT_ALIGN_R ((uint32_t)0x00000000)
+#define ADC_DAT_ALIGN_L ((uint32_t)0x00000800)
+#define IsAdcDatAlign(ALIGN) (((ALIGN) == ADC_DAT_ALIGN_R) || ((ALIGN) == ADC_DAT_ALIGN_L))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_channels
+ * @{
+ */
+
+#define ADC_CH_0 ((uint8_t)0x00)
+#define ADC_CH_1 ((uint8_t)0x01)
+#define ADC_CH_2 ((uint8_t)0x02)
+#define ADC_CH_3 ((uint8_t)0x03)
+#define ADC_CH_4 ((uint8_t)0x04)
+#define ADC_CH_5 ((uint8_t)0x05)
+#define ADC_CH_6 ((uint8_t)0x06)
+#define ADC_CH_7 ((uint8_t)0x07)
+#define ADC_CH_8 ((uint8_t)0x08)
+#define ADC_CH_9 ((uint8_t)0x09)
+#define ADC_CH_10 ((uint8_t)0x0A)
+#define ADC_CH_11 ((uint8_t)0x0B)
+#define ADC_CH_12 ((uint8_t)0x0C)
+#define ADC_CH_13 ((uint8_t)0x0D)
+#define ADC_CH_14 ((uint8_t)0x0E)
+#define ADC_CH_15 ((uint8_t)0x0F)
+#define ADC_CH_16 ((uint8_t)0x10)
+#define ADC_CH_17 ((uint8_t)0x11)
+#define ADC_CH_18 ((uint8_t)0x12)
+
+#define ADC_CH_TEMP_SENSOR ((uint8_t)ADC_CH_16)
+#define ADC_CH_INT_VREF ((uint8_t)ADC_CH_18)
+
+#define IsAdcChannel(CHANNEL) \
+ (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) \
+ || ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) \
+ || ((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9) || ((CHANNEL) == ADC_CH_10) || ((CHANNEL) == ADC_CH_11) \
+ || ((CHANNEL) == ADC_CH_12) || ((CHANNEL) == ADC_CH_13) || ((CHANNEL) == ADC_CH_14) || ((CHANNEL) == ADC_CH_15) \
+ || ((CHANNEL) == ADC_CH_16) || ((CHANNEL) == ADC_CH_17) || ((CHANNEL) == ADC_CH_18))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_sampling_time
+ * @{
+ */
+
+#define ADC_SAMP_TIME_1CYCLES5 ((uint8_t)0x00)
+#define ADC_SAMP_TIME_7CYCLES5 ((uint8_t)0x01)
+#define ADC_SAMP_TIME_13CYCLES5 ((uint8_t)0x02)
+#define ADC_SAMP_TIME_28CYCLES5 ((uint8_t)0x03)
+#define ADC_SAMP_TIME_41CYCLES5 ((uint8_t)0x04)
+#define ADC_SAMP_TIME_55CYCLES5 ((uint8_t)0x05)
+#define ADC_SAMP_TIME_71CYCLES5 ((uint8_t)0x06)
+#define ADC_SAMP_TIME_239CYCLES5 ((uint8_t)0x07)
+#define IsAdcSampleTime(TIME) \
+ (((TIME) == ADC_SAMP_TIME_1CYCLES5) || ((TIME) == ADC_SAMP_TIME_7CYCLES5) || ((TIME) == ADC_SAMP_TIME_13CYCLES5) \
+ || ((TIME) == ADC_SAMP_TIME_28CYCLES5) || ((TIME) == ADC_SAMP_TIME_41CYCLES5) \
+ || ((TIME) == ADC_SAMP_TIME_55CYCLES5) || ((TIME) == ADC_SAMP_TIME_71CYCLES5) \
+ || ((TIME) == ADC_SAMP_TIME_239CYCLES5))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_external_trigger_sources_for_injected_channels_conversion
+ * @{
+ */
+
+#define ADC_EXT_TRIG_INJ_CONV_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */
+#define ADC_EXT_TRIG_INJ_CONV_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */
+#define ADC_EXT_TRIG_INJ_CONV_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */
+#define ADC_EXT_TRIG_INJ_CONV_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */
+#define ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */
+
+#define ADC_EXT_TRIG_INJ_CONV_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 */
+#define ADC_EXT_TRIG_INJ_CONV_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 */
+#define ADC_EXT_TRIG_INJ_CONV_NONE ((uint32_t)0x00007000) /*!< For ADC1, ADC2 */
+
+#define IsAdcExtInjTrig(INJTRIG) \
+ (((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T1_TRGO) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T1_CC4) \
+ || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T2_TRGO) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T2_CC1) \
+ || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T3_CC4) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T4_TRGO) \
+ || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_NONE))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_injected_channel_selection
+ * @{
+ */
+
+#define ADC_INJ_CH_1 ((uint8_t)0x14)
+#define ADC_INJ_CH_2 ((uint8_t)0x18)
+#define ADC_INJ_CH_3 ((uint8_t)0x1C)
+#define ADC_INJ_CH_4 ((uint8_t)0x20)
+#define IsAdcInjCh(CHANNEL) \
+ (((CHANNEL) == ADC_INJ_CH_1) || ((CHANNEL) == ADC_INJ_CH_2) || ((CHANNEL) == ADC_INJ_CH_3) \
+ || ((CHANNEL) == ADC_INJ_CH_4))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_analog_watchdog_selection
+ * @{
+ */
+
+#define ADC_ANALOG_WTDG_SINGLEREG_ENABLE ((uint32_t)0x00800200)
+#define ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE ((uint32_t)0x00400200)
+#define ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE ((uint32_t)0x00C00200)
+#define ADC_ANALOG_WTDG_ALLREG_ENABLE ((uint32_t)0x00800000)
+#define ADC_ANALOG_WTDG_ALLINJEC_ENABLE ((uint32_t)0x00400000)
+#define ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE ((uint32_t)0x00C00000)
+#define ADC_ANALOG_WTDG_NONE ((uint32_t)0x00000000)
+
+#define IsAdcAnalogWatchdog(WATCHDOG) \
+ (((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEREG_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE) \
+ || ((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLREG_ENABLE) \
+ || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLINJEC_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE) \
+ || ((WATCHDOG) == ADC_ANALOG_WTDG_NONE))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_interrupts_definition
+ * @{
+ */
+
+#define ADC_INT_ENDC ((uint16_t)0x0220)
+#define ADC_INT_AWD ((uint16_t)0x0140)
+#define ADC_INT_JENDC ((uint16_t)0x0480)
+
+#define IsAdcInt(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))
+
+#define IsAdcGetInt(IT) (((IT) == ADC_INT_ENDC) || ((IT) == ADC_INT_AWD) || ((IT) == ADC_INT_JENDC))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_flags_definition
+ * @{
+ */
+
+#define ADC_FLAG_AWDG ((uint8_t)0x01)
+#define ADC_FLAG_ENDC ((uint8_t)0x02)
+#define ADC_FLAG_JENDC ((uint8_t)0x04)
+#define ADC_FLAG_JSTR ((uint8_t)0x08)
+#define ADC_FLAG_STR ((uint8_t)0x10)
+#define ADC_FLAG_EOC_ANY ((uint8_t)0x20)
+#define ADC_FLAG_JEOC_ANY ((uint8_t)0x40)
+#define IsAdcClrFlag(FLAG) ((((FLAG) & (uint8_t)0x80) == 0x00) && ((FLAG) != 0x00))
+#define IsAdcGetFlag(FLAG) \
+ (((FLAG) == ADC_FLAG_AWDG) || ((FLAG) == ADC_FLAG_ENDC) || ((FLAG) == ADC_FLAG_JENDC) || ((FLAG) == ADC_FLAG_JSTR) \
+ || ((FLAG) == ADC_FLAG_STR) || ((FLAG) == ADC_FLAG_EOC_ANY) || ((FLAG) == ADC_FLAG_JEOC_ANY))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_thresholds
+ * @{
+ */
+#define IsAdcValid(THRESHOLD) ((THRESHOLD) <= 0xFFF)
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_injected_offset
+ * @{
+ */
+
+#define IsAdcOffsetValid(OFFSET) ((OFFSET) <= 0xFFF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_injected_length
+ * @{
+ */
+
+#define IsAdcInjLenValid(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_injected_rank
+ * @{
+ */
+
+#define IsAdcInjRankValid(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_regular_length
+ * @{
+ */
+
+#define IsAdcSeqLenValid(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_regular_rank
+ * @{
+ */
+
+#define IsAdcReqRankValid(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_regular_discontinuous_mode_number
+ * @{
+ */
+
+#define IsAdcSeqDiscNumberValid(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
+
+/**
+ * @}
+ */
+
+/************************** fllowing bit seg in ex register **********************/
+/**@addtogroup ADC_channels_ex_style
+ * @{
+ */
+#define ADC1_Channel_01_PA0 ((uint8_t)0x01)
+#define ADC1_Channel_02_PA1 ((uint8_t)0x02)
+#define ADC1_Channel_03_PA6 ((uint8_t)0x03)
+#define ADC1_Channel_04_PA3 ((uint8_t)0x04)
+#define ADC1_Channel_05_PF4 ((uint8_t)0x05)
+#define ADC1_Channel_06_PC0 ((uint8_t)0x06)
+#define ADC1_Channel_07_PC1 ((uint8_t)0x07)
+#define ADC1_Channel_08_PC2 ((uint8_t)0x08)
+#define ADC1_Channel_09_PC3 ((uint8_t)0x09)
+#define ADC1_Channel_10_PF2 ((uint8_t)0x0A)
+#define ADC1_Channel_11_PA2 ((uint8_t)0x0B)
+
+#define ADC2_Channel_01_PA4 ((uint8_t)0x01)
+#define ADC2_Channel_02_PA5 ((uint8_t)0x02)
+#define ADC2_Channel_03_PB1 ((uint8_t)0x03)
+#define ADC2_Channel_04_PA7 ((uint8_t)0x04)
+#define ADC2_Channel_05_PC4 ((uint8_t)0x05)
+#define ADC2_Channel_06_PC0 ((uint8_t)0x06)
+#define ADC2_Channel_07_PC1 ((uint8_t)0x07)
+#define ADC2_Channel_08_PC2 ((uint8_t)0x08)
+#define ADC2_Channel_09_PC3 ((uint8_t)0x09)
+#define ADC2_Channel_10_PF2 ((uint8_t)0x0A)
+#define ADC2_Channel_11_PA2 ((uint8_t)0x0B)
+#define ADC2_Channel_12_PC5 ((uint8_t)0x0C)
+#define ADC2_Channel_13_PB2 ((uint8_t)0x0D)
+
+#define ADC_CH_0 ((uint8_t)0x00)
+#define ADC_CH_1 ((uint8_t)0x01)
+#define ADC_CH_2 ((uint8_t)0x02)
+#define ADC_CH_3 ((uint8_t)0x03)
+#define ADC_CH_4 ((uint8_t)0x04)
+#define ADC_CH_5 ((uint8_t)0x05)
+#define ADC_CH_6 ((uint8_t)0x06)
+#define ADC_CH_7 ((uint8_t)0x07)
+#define ADC_CH_8 ((uint8_t)0x08)
+#define ADC_CH_9 ((uint8_t)0x09)
+#define ADC_CH_10 ((uint8_t)0x0A)
+#define ADC_CH_11 ((uint8_t)0x0B)
+#define ADC_CH_12 ((uint8_t)0x0C)
+#define ADC_CH_13 ((uint8_t)0x0D)
+#define ADC_CH_14 ((uint8_t)0x0E)
+#define ADC_CH_15 ((uint8_t)0x0F)
+#define ADC_CH_16 ((uint8_t)0x10)
+#define ADC_CH_17 ((uint8_t)0x11)
+#define ADC_CH_18 ((uint8_t)0x12)
+/**
+ * @}
+ */
+
+/**@addtogroup ADC_dif_sel_ch_definition
+ * @{
+ */
+#define ADC_DIFSEL_CHS_MASK ((uint32_t)0x0007FFFE)
+#define ADC_DIFSEL_CHS_1 ((uint32_t)0x00000002)
+#define ADC_DIFSEL_CHS_2 ((uint32_t)0x00000004)
+#define ADC_DIFSEL_CHS_3 ((uint32_t)0x00000008)
+#define ADC_DIFSEL_CHS_4 ((uint32_t)0x00000010)
+#define ADC_DIFSEL_CHS_5 ((uint32_t)0x00000020)
+#define ADC_DIFSEL_CHS_6 ((uint32_t)0x00000040)
+#define ADC_DIFSEL_CHS_7 ((uint32_t)0x00000080)
+#define ADC_DIFSEL_CHS_8 ((uint32_t)0x00000100)
+#define ADC_DIFSEL_CHS_9 ((uint32_t)0x00000200)
+#define ADC_DIFSEL_CHS_10 ((uint32_t)0x00000400)
+#define ADC_DIFSEL_CHS_11 ((uint32_t)0x00000800)
+#define ADC_DIFSEL_CHS_12 ((uint32_t)0x00001000)
+#define ADC_DIFSEL_CHS_13 ((uint32_t)0x00002000)
+#define ADC_DIFSEL_CHS_14 ((uint32_t)0x00004000)
+#define ADC_DIFSEL_CHS_15 ((uint32_t)0x00008000)
+#define ADC_DIFSEL_CHS_16 ((uint32_t)0x00010000)
+#define ADC_DIFSEL_CHS_17 ((uint32_t)0x00020000)
+#define ADC_DIFSEL_CHS_18 ((uint32_t)0x00040000)
+/**
+ * @}
+ */
+
+/**@addtogroup ADC_calfact_definition
+ * @{
+ */
+#define ADC_CALFACT_CALFACTD_MSK ((uint32_t)0x3FL << 16)
+#define ADC_CALFACT_CALFACTS_MSK ((uint32_t)0x3FL << 0)
+/**
+ * @}
+ */
+
+/**@addtogroup ADC_ctrl3_definition
+ * @{
+ */
+#define ADC_CTRL3_VABTMEN_MSK ((uint32_t)0x01L << 11)
+#define ADC_CTRL3_DPWMOD_MSK ((uint32_t)0x01L << 10)
+#define ADC_CTRL3_JENDCAIEN_MSK ((uint32_t)0x01L << 9)
+#define ADC_CTRL3_ENDCAIEN_MSK ((uint32_t)0x01L << 8)
+#define ADC_CTRL3_BPCAL_MSK ((uint32_t)0x01L << 7)
+#define ADC_CTRL3_PDRDY_MSK ((uint32_t)0x01L << 6)
+#define ADC_CTRL3_RDY_MSK ((uint32_t)0x01L << 5)
+#define ADC_CTRL3_CKMOD_MSK ((uint32_t)0x01L << 4)
+#define ADC_CTRL3_CALALD_MSK ((uint32_t)0x01L << 3)
+#define ADC_CTRL3_CALDIF_MSK ((uint32_t)0x01L << 2)
+#define ADC_CTRL3_RES_MSK ((uint32_t)0x03L << 0)
+/**
+ * @}
+ */
+
+#define ADC_CLOCK_PLL ((uint32_t)ADC_CTRL3_CKMOD_MSK)
+#define ADC_CLOCK_AHB ((uint32_t)(~ADC_CTRL3_CKMOD_MSK))
+
+/**@addtogroup ADC_sampt3_definition
+ * @{
+ */
+#define ADC_SAMPT3_SAMPSEL_MSK ((uint32_t)0x01L << 3)
+/**
+ * @}
+ */
+
+typedef enum
+{
+ ADC_CTRL3_CKMOD_AHB = 0,
+ ADC_CTRL3_CKMOD_PLL = 1,
+} ADC_CTRL3_CKMOD;
+typedef enum
+{
+ ADC_CTRL3_RES_12BIT = 3,
+ ADC_CTRL3_RES_10BIT = 2,
+ ADC_CTRL3_RES_8BIT = 1,
+ ADC_CTRL3_RES_6BIT = 0,
+} ADC_CTRL3_RES;
+typedef struct
+{
+ FunctionalState VbatMinitEn;
+ FunctionalState DeepPowerModEn;
+ FunctionalState JendcIntEn;
+ FunctionalState EndcIntEn;
+ ADC_CTRL3_CKMOD ClkMode;
+ FunctionalState CalAtuoLoadEn;
+ bool DifModCal;
+ ADC_CTRL3_RES ResBit;
+ bool Samp303Style;
+} ADC_InitTypeEx;
+/**
+ * @}
+ */
+
+/*ADC_SAMPT3 only have samp time and smp18[2:0],samp18 is refint ch, change to row function*/
+/*ADC_IPTST reseverd register ,not to do it*/
+
+/**@addtogroup ADC_bit_num_definition
+ * @{
+ */
+#define ADC_RST_BIT_12 ((uint32_t)0x03)
+#define ADC_RST_BIT_10 ((uint32_t)0x02)
+#define ADC_RST_BIT_8 ((uint32_t)0x01)
+#define ADC_RESULT_BIT_6 ((uint32_t)0x00)
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_flags_ex_definition
+ * @{
+ */
+#define ADC_FLAG_RDY ((uint8_t)0x20)
+#define ADC_FLAG_PD_RDY ((uint8_t)0x40)
+#define IS_ADC_GET_READY(FLAG) (((FLAG) == ADC_FLAG_RDY) || ((FLAG) == ADC_FLAG_PD_RDY)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Exported_Functions
+ * @{
+ */
+
+void ADC_DeInit(ADC_Module* ADCx);
+void ADC_Init(ADC_Module* ADCx, ADC_InitType* ADC_InitStruct);
+void ADC_InitStruct(ADC_InitType* ADC_InitStruct);
+void ADC_Enable(ADC_Module* ADCx, FunctionalState Cmd);
+void ADC_EnableDMA(ADC_Module* ADCx, FunctionalState Cmd);
+void ADC_ConfigInt(ADC_Module* ADCx, uint16_t ADC_IT, FunctionalState Cmd);
+void ADC_StartCalibration(ADC_Module* ADCx);
+FlagStatus ADC_GetCalibrationStatus(ADC_Module* ADCx);
+void ADC_EnableSoftwareStartConv(ADC_Module* ADCx, FunctionalState Cmd);
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_Module* ADCx);
+void ADC_ConfigDiscModeChannelCount(ADC_Module* ADCx, uint8_t Number);
+void ADC_EnableDiscMode(ADC_Module* ADCx, FunctionalState Cmd);
+void ADC_ConfigRegularChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_EnableExternalTrigConv(ADC_Module* ADCx, FunctionalState Cmd);
+uint16_t ADC_GetDat(ADC_Module* ADCx);
+uint32_t ADC_GetDualModeConversionDat(ADC_Module* ADCx);
+void ADC_EnableAutoInjectedConv(ADC_Module* ADCx, FunctionalState Cmd);
+void ADC_EnableInjectedDiscMode(ADC_Module* ADCx, FunctionalState Cmd);
+void ADC_ConfigExternalTrigInjectedConv(ADC_Module* ADCx, uint32_t ADC_ExternalTrigInjecConv);
+void ADC_EnableExternalTrigInjectedConv(ADC_Module* ADCx, FunctionalState Cmd);
+void ADC_EnableSoftwareStartInjectedConv(ADC_Module* ADCx, FunctionalState Cmd);
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_Module* ADCx);
+void ADC_ConfigInjectedChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_ConfigInjectedSequencerLength(ADC_Module* ADCx, uint8_t Length);
+void ADC_SetInjectedOffsetDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
+uint16_t ADC_GetInjectedConversionDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel);
+void ADC_ConfigAnalogWatchdogWorkChannelType(ADC_Module* ADCx, uint32_t ADC_AnalogWatchdog);
+void ADC_ConfigAnalogWatchdogThresholds(ADC_Module* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
+void ADC_ConfigAnalogWatchdogSingleChannel(ADC_Module* ADCx, uint8_t ADC_Channel);
+void ADC_EnableTempSensorVrefint(FunctionalState Cmd);
+FlagStatus ADC_GetFlagStatus(ADC_Module* ADCx, uint8_t ADC_FLAG);
+void ADC_ClearFlag(ADC_Module* ADCx, uint8_t ADC_FLAG);
+INTStatus ADC_GetIntStatus(ADC_Module* ADCx, uint16_t ADC_IT);
+void ADC_ClearIntPendingBit(ADC_Module* ADCx, uint16_t ADC_IT);
+
+void ADC_InitEx(ADC_Module* ADCx, ADC_InitTypeEx* ADC_InitStructEx);
+void ADC_SetDifChs(ADC_Module* ADCx,uint32_t DifChs);
+FlagStatus ADC_GetFlagStatusNew(ADC_Module* ADCx, uint8_t ADC_FLAG_NEW);
+void ADC_SetBypassCalibration(ADC_Module* ADCx, FunctionalState en);
+void ADC_SetConvResultBitNum(ADC_Module* ADCx, uint32_t ResultBitNum);
+
+void ADC_ConfigClk(ADC_CTRL3_CKMOD ADC_ClkMode, uint32_t RCC_ADCHCLKPrescaler);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32WB452_ADC_H__ */
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_bkp.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_bkp.h
new file mode 100644
index 0000000000..0203d008ec
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_bkp.h
@@ -0,0 +1,182 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_bkp.h
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32WB452_BKP_H__
+#define __N32WB452_BKP_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32wb452.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup BKP
+ * @{
+ */
+
+/** @addtogroup BKP_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup BKP_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup Tamper_Pin_active_level
+ * @{
+ */
+
+#define BKP_TP_HIGH ((uint16_t)0x0000)
+#define BKP_TP_LOW ((uint16_t)0x0001)
+#define IS_BKP_TP_LEVEL(LEVEL) (((LEVEL) == BKP_TP_HIGH) || ((LEVEL) == BKP_TP_LOW))
+/**
+ * @}
+ */
+
+
+/** @addtogroup Data_Backup_Register
+ * @{
+ */
+
+#define BKP_DAT1 ((uint16_t)0x0004)
+#define BKP_DAT2 ((uint16_t)0x0008)
+#define BKP_DAT3 ((uint16_t)0x000C)
+#define BKP_DAT4 ((uint16_t)0x0010)
+#define BKP_DAT5 ((uint16_t)0x0014)
+#define BKP_DAT6 ((uint16_t)0x0018)
+#define BKP_DAT7 ((uint16_t)0x001C)
+#define BKP_DAT8 ((uint16_t)0x0020)
+#define BKP_DAT9 ((uint16_t)0x0024)
+#define BKP_DAT10 ((uint16_t)0x0028)
+#define BKP_DAT11 ((uint16_t)0x0040)
+#define BKP_DAT12 ((uint16_t)0x0044)
+#define BKP_DAT13 ((uint16_t)0x0048)
+#define BKP_DAT14 ((uint16_t)0x004C)
+#define BKP_DAT15 ((uint16_t)0x0050)
+#define BKP_DAT16 ((uint16_t)0x0054)
+#define BKP_DAT17 ((uint16_t)0x0058)
+#define BKP_DAT18 ((uint16_t)0x005C)
+#define BKP_DAT19 ((uint16_t)0x0060)
+#define BKP_DAT20 ((uint16_t)0x0064)
+#define BKP_DAT21 ((uint16_t)0x0068)
+#define BKP_DAT22 ((uint16_t)0x006C)
+#define BKP_DAT23 ((uint16_t)0x0070)
+#define BKP_DAT24 ((uint16_t)0x0074)
+#define BKP_DAT25 ((uint16_t)0x0078)
+#define BKP_DAT26 ((uint16_t)0x007C)
+#define BKP_DAT27 ((uint16_t)0x0080)
+#define BKP_DAT28 ((uint16_t)0x0084)
+#define BKP_DAT29 ((uint16_t)0x0088)
+#define BKP_DAT30 ((uint16_t)0x008C)
+#define BKP_DAT31 ((uint16_t)0x0090)
+#define BKP_DAT32 ((uint16_t)0x0094)
+#define BKP_DAT33 ((uint16_t)0x0098)
+#define BKP_DAT34 ((uint16_t)0x009C)
+#define BKP_DAT35 ((uint16_t)0x00A0)
+#define BKP_DAT36 ((uint16_t)0x00A4)
+#define BKP_DAT37 ((uint16_t)0x00A8)
+#define BKP_DAT38 ((uint16_t)0x00AC)
+#define BKP_DAT39 ((uint16_t)0x00B0)
+#define BKP_DAT40 ((uint16_t)0x00B4)
+#define BKP_DAT41 ((uint16_t)0x00B8)
+#define BKP_DAT42 ((uint16_t)0x00BC)
+
+#define IS_BKP_DAT(DAT) \
+ (((DAT) == BKP_DAT1) || ((DAT) == BKP_DAT2) || ((DAT) == BKP_DAT3) || ((DAT) == BKP_DAT4) || ((DAT) == BKP_DAT5) \
+ || ((DAT) == BKP_DAT6) || ((DAT) == BKP_DAT7) || ((DAT) == BKP_DAT8) || ((DAT) == BKP_DAT9) \
+ || ((DAT) == BKP_DAT10) || ((DAT) == BKP_DAT11) || ((DAT) == BKP_DAT12) || ((DAT) == BKP_DAT13) \
+ || ((DAT) == BKP_DAT14) || ((DAT) == BKP_DAT15) || ((DAT) == BKP_DAT16) || ((DAT) == BKP_DAT17) \
+ || ((DAT) == BKP_DAT18) || ((DAT) == BKP_DAT19) || ((DAT) == BKP_DAT20) || ((DAT) == BKP_DAT21) \
+ || ((DAT) == BKP_DAT22) || ((DAT) == BKP_DAT23) || ((DAT) == BKP_DAT24) || ((DAT) == BKP_DAT25) \
+ || ((DAT) == BKP_DAT26) || ((DAT) == BKP_DAT27) || ((DAT) == BKP_DAT28) || ((DAT) == BKP_DAT29) \
+ || ((DAT) == BKP_DAT30) || ((DAT) == BKP_DAT31) || ((DAT) == BKP_DAT32) || ((DAT) == BKP_DAT33) \
+ || ((DAT) == BKP_DAT34) || ((DAT) == BKP_DAT35) || ((DAT) == BKP_DAT36) || ((DAT) == BKP_DAT37) \
+ || ((DAT) == BKP_DAT38) || ((DAT) == BKP_DAT39) || ((DAT) == BKP_DAT40) || ((DAT) == BKP_DAT41) \
+ || ((DAT) == BKP_DAT42))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup BKP_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup BKP_Exported_Functions
+ * @{
+ */
+
+void BKP_DeInit(void);
+void BKP_ConfigTPLevel(uint16_t BKP_TamperPinLevel);
+void BKP_TPEnable(FunctionalState Cmd);
+void BKP_TPIntEnable(FunctionalState Cmd);
+void BKP_WriteBkpData(uint16_t BKP_DAT, uint16_t Data);
+uint16_t BKP_ReadBkpData(uint16_t BKP_DAT);
+FlagStatus BKP_GetTEFlag(void);
+void BKP_ClrTEFlag(void);
+INTStatus BKP_GetTINTFlag(void);
+void BKP_ClrTINTFlag(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32WB452_BKP_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_can.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_can.h
new file mode 100644
index 0000000000..3b9ba20849
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_can.h
@@ -0,0 +1,671 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_can.h
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32WB452_CAN_H__
+#define __N32WB452_CAN_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32wb452.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CAN
+ * @{
+ */
+
+/** @addtogroup CAN_Exported_Types
+ * @{
+ */
+
+#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || ((PERIPH) == CAN2))
+
+/**
+ * @brief CAN init structure definition
+ */
+
+typedef struct
+{
+ uint16_t BaudRatePrescaler; /*!< Specifies the length of a time quantum.
+ It ranges from 1 to 1024. */
+
+ uint8_t OperatingMode; /*!< Specifies the CAN operating mode.
+ This parameter can be a value of
+ @ref CAN_operating_mode */
+
+ uint8_t RSJW; /*!< Specifies the maximum number of time quanta
+ the CAN hardware is allowed to lengthen or
+ shorten a bit to perform resynchronization.
+ This parameter can be a value of
+ @ref CAN_synchronisation_jump_width */
+
+ uint8_t TBS1; /*!< Specifies the number of time quanta in Bit
+ Segment 1. This parameter can be a value of
+ @ref CAN_time_quantum_in_bit_segment_1 */
+
+ uint8_t TBS2; /*!< Specifies the number of time quanta in Bit
+ Segment 2.
+ This parameter can be a value of
+ @ref CAN_time_quantum_in_bit_segment_2 */
+
+ FunctionalState TTCM; /*!< Enable or disable the time triggered
+ communication mode. This parameter can be set
+ either to ENABLE or DISABLE. */
+
+ FunctionalState ABOM; /*!< Enable or disable the automatic bus-off
+ management. This parameter can be set either
+ to ENABLE or DISABLE. */
+
+ FunctionalState AWKUM; /*!< Enable or disable the automatic wake-up mode.
+ This parameter can be set either to ENABLE or
+ DISABLE. */
+
+ FunctionalState NART; /*!< Enable or disable the no-automatic
+ retransmission mode. This parameter can be
+ set either to ENABLE or DISABLE. */
+
+ FunctionalState RFLM; /*!< Enable or disable the Receive DATFIFO Locked mode.
+ This parameter can be set either to ENABLE
+ or DISABLE. */
+
+ FunctionalState TXFP; /*!< Enable or disable the transmit DATFIFO priority.
+ This parameter can be set either to ENABLE
+ or DISABLE. */
+} CAN_InitType;
+
+/**
+ * @brief CAN filter init structure definition
+ */
+
+typedef struct
+{
+ uint16_t Filter_HighId; /*!< Specifies the filter identification number (MSBs for a 32-bit
+ configuration, first one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t Filter_LowId; /*!< Specifies the filter identification number (LSBs for a 32-bit
+ configuration, second one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t FilterMask_HighId; /*!< Specifies the filter mask number or identification number,
+ according to the mode (MSBs for a 32-bit configuration,
+ first one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t FilterMask_LowId; /*!< Specifies the filter mask number or identification number,
+ according to the mode (LSBs for a 32-bit configuration,
+ second one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t Filter_FIFOAssignment; /*!< Specifies the DATFIFO (0 or 1) which will be assigned to the filter.
+ This parameter can be a value of @ref CAN_filter_FIFO */
+
+ uint8_t Filter_Num; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
+
+ uint8_t Filter_Mode; /*!< Specifies the filter mode to be initialized.
+ This parameter can be a value of @ref CAN_filter_mode */
+
+ uint8_t Filter_Scale; /*!< Specifies the filter scale.
+ This parameter can be a value of @ref CAN_filter_scale */
+
+ FunctionalState Filter_Act; /*!< Enable or disable the filter.
+ This parameter can be set either to ENABLE or DISABLE. */
+} CAN_FilterInitType;
+
+/**
+ * @brief CAN Tx message structure definition
+ */
+
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter can be a value between 0 to 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+ uint8_t IDE; /*!< Specifies the type of identifier for the message that
+ will be transmitted. This parameter can be a value
+ of @ref CAN_identifier_type */
+
+ uint8_t RTR; /*!< Specifies the type of frame for the message that will
+ be transmitted. This parameter can be a value of
+ @ref CAN_remote_transmission_request */
+
+ uint8_t DLC; /*!< Specifies the length of the frame that will be
+ transmitted. This parameter can be a value between
+ 0 to 8 */
+
+ uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
+ to 0xFF. */
+} CanTxMessage;
+
+/**
+ * @brief CAN Rx message structure definition
+ */
+
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter can be a value between 0 to 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+ uint8_t IDE; /*!< Specifies the type of identifier for the message that
+ will be received. This parameter can be a value of
+ @ref CAN_identifier_type */
+
+ uint8_t RTR; /*!< Specifies the type of frame for the received message.
+ This parameter can be a value of
+ @ref CAN_remote_transmission_request */
+
+ uint8_t DLC; /*!< Specifies the length of the frame that will be received.
+ This parameter can be a value between 0 to 8 */
+
+ uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
+ 0xFF. */
+
+ uint8_t FMI; /*!< Specifies the index of the filter the message stored in
+ the mailbox passes through. This parameter can be a
+ value between 0 to 0xFF */
+} CanRxMessage;
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup CAN_sleep_constants
+ * @{
+ */
+
+#define CAN_InitSTS_Failed ((uint8_t)0x00) /*!< CAN initialization failed */
+#define CAN_InitSTS_Success ((uint8_t)0x01) /*!< CAN initialization OK */
+
+/**
+ * @}
+ */
+
+/** @addtogroup OperatingMode
+ * @{
+ */
+
+#define CAN_Normal_Mode ((uint8_t)0x00) /*!< normal mode */
+#define CAN_LoopBack_Mode ((uint8_t)0x01) /*!< loopback mode */
+#define CAN_Silent_Mode ((uint8_t)0x02) /*!< silent mode */
+#define CAN_Silent_LoopBack_Mode ((uint8_t)0x03) /*!< loopback combined with silent mode */
+
+#define IS_CAN_MODE(MODE) \
+ (((MODE) == CAN_Normal_Mode) || ((MODE) == CAN_LoopBack_Mode) || ((MODE) == CAN_Silent_Mode) \
+ || ((MODE) == CAN_Silent_LoopBack_Mode))
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup CAN_operating_mode
+ * @{
+ */
+#define CAN_Operating_InitMode ((uint8_t)0x00) /*!< Initialization mode */
+#define CAN_Operating_NormalMode ((uint8_t)0x01) /*!< Normal mode */
+#define CAN_Operating_SleepMode ((uint8_t)0x02) /*!< sleep mode */
+
+#define IS_CAN_OPERATING_MODE(MODE) \
+ (((MODE) == CAN_Operating_InitMode) || ((MODE) == CAN_Operating_NormalMode) || ((MODE) == CAN_Operating_SleepMode))
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup CAN_Mode_Status
+ * @{
+ */
+
+#define CAN_ModeSTS_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */
+#define CAN_ModeSTS_Success ((uint8_t)!CAN_ModeSTS_Failed) /*!< CAN entering the specific mode Succeed */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_synchronisation_jump_width
+ * @{
+ */
+
+#define CAN_RSJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_RSJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_RSJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_RSJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+
+#define IS_CAN_RSJW(SJW) \
+ (((SJW) == CAN_RSJW_1tq) || ((SJW) == CAN_RSJW_2tq) || ((SJW) == CAN_RSJW_3tq) || ((SJW) == CAN_RSJW_4tq))
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_time_quantum_in_bit_segment_1
+ * @{
+ */
+
+#define CAN_TBS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_TBS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_TBS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_TBS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+#define CAN_TBS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */
+#define CAN_TBS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */
+#define CAN_TBS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */
+#define CAN_TBS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */
+#define CAN_TBS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */
+#define CAN_TBS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */
+#define CAN_TBS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */
+#define CAN_TBS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */
+#define CAN_TBS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */
+#define CAN_TBS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */
+#define CAN_TBS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */
+#define CAN_TBS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */
+
+#define IS_CAN_TBS1(BS1) ((BS1) <= CAN_TBS1_16tq)
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_time_quantum_in_bit_segment_2
+ * @{
+ */
+
+#define CAN_TBS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_TBS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_TBS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_TBS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+#define CAN_TBS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */
+#define CAN_TBS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */
+#define CAN_TBS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */
+#define CAN_TBS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */
+
+#define IS_CAN_TBS2(BS2) ((BS2) <= CAN_TBS2_8tq)
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_clock_prescaler
+ * @{
+ */
+
+#define IS_CAN_BAUDRATEPRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_filter_number
+ * @{
+ */
+#define IS_CAN_FILTER_NUM(NUMBER) ((NUMBER) <= 13)
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_filter_mode
+ * @{
+ */
+
+#define CAN_Filter_IdMaskMode ((uint8_t)0x00) /*!< identifier/mask mode */
+#define CAN_Filter_IdListMode ((uint8_t)0x01) /*!< identifier list mode */
+
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_Filter_IdMaskMode) || ((MODE) == CAN_Filter_IdListMode))
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_filter_scale
+ * @{
+ */
+
+#define CAN_Filter_16bitScale ((uint8_t)0x00) /*!< Two 16-bit filters */
+#define CAN_Filter_32bitScale ((uint8_t)0x01) /*!< One 32-bit filter */
+
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_Filter_16bitScale) || ((SCALE) == CAN_Filter_32bitScale))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_filter_FIFO
+ * @{
+ */
+
+#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter DATFIFO 0 assignment for filter x */
+#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter DATFIFO 1 assignment for filter x */
+#define IS_CAN_FILTER_FIFO(DATFIFO) (((DATFIFO) == CAN_FilterFIFO0) || ((DATFIFO) == CAN_FilterFIFO1))
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Tx
+ * @{
+ */
+
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_identifier_type
+ * @{
+ */
+
+#define CAN_Standard_Id ((uint32_t)0x00000000) /*!< Standard Id */
+#define CAN_Extended_Id ((uint32_t)0x00000004) /*!< Extended Id */
+#define IS_CAN_ID(IDTYPE) (((IDTYPE) == CAN_Standard_Id) || ((IDTYPE) == CAN_Extended_Id))
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_remote_transmission_request
+ * @{
+ */
+
+#define CAN_RTRQ_Data ((uint32_t)0x00000000) /*!< Data frame */
+#define CAN_RTRQ_Remote ((uint32_t)0x00000002) /*!< Remote frame */
+#define IS_CAN_RTRQ(RTR) (((RTR) == CAN_RTRQ_Data) || ((RTR) == CAN_RTRQ_Remote))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_transmit_constants
+ * @{
+ */
+
+#define CAN_TxSTS_Failed ((uint8_t)0x00) /*!< CAN transmission failed */
+#define CAN_TxSTS_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */
+#define CAN_TxSTS_Pending ((uint8_t)0x02) /*!< CAN transmission pending */
+#define CAN_TxSTS_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_receive_FIFO_number_constants
+ * @{
+ */
+
+#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN DATFIFO 0 used to receive */
+#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN DATFIFO 1 used to receive */
+
+#define IS_CAN_FIFO(DATFIFO) (((DATFIFO) == CAN_FIFO0) || ((DATFIFO) == CAN_FIFO1))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_sleep_constants
+ * @{
+ */
+
+#define CAN_SLEEP_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
+#define CAN_SLEEP_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_wake_up_constants
+ * @{
+ */
+
+#define CAN_WKU_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
+#define CAN_WKU_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
+
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup CAN_Error_Code_constants
+ * @{
+ */
+
+#define CAN_ERRCode_NoErr ((uint8_t)0x00) /*!< No Error */
+#define CAN_ERRCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */
+#define CAN_ERRCode_FormErr ((uint8_t)0x20) /*!< Form Error */
+#define CAN_ERRCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */
+#define CAN_ERRCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */
+#define CAN_ERRCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */
+#define CAN_ERRCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */
+#define CAN_ERRCode_SWSetErr ((uint8_t)0x70) /*!< Software Set Error */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_flags
+ * @{
+ */
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagSTS()
+ and CAN_ClearFlag() functions. */
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagSTS() function. */
+
+/* Transmit Flags */
+#define CAN_FLAG_RQCPM0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
+#define CAN_FLAG_RQCPM1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
+#define CAN_FLAG_RQCPM2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
+
+/* Receive Flags */
+#define CAN_FLAG_FFMP0 ((uint32_t)0x12000003) /*!< DATFIFO 0 Message Pending Flag */
+#define CAN_FLAG_FFULL0 ((uint32_t)0x32000008) /*!< DATFIFO 0 Full Flag */
+#define CAN_FLAG_FFOVR0 ((uint32_t)0x32000010) /*!< DATFIFO 0 Overrun Flag */
+#define CAN_FLAG_FFMP1 ((uint32_t)0x14000003) /*!< DATFIFO 1 Message Pending Flag */
+#define CAN_FLAG_FFULL1 ((uint32_t)0x34000008) /*!< DATFIFO 1 Full Flag */
+#define CAN_FLAG_FFOVR1 ((uint32_t)0x34000010) /*!< DATFIFO 1 Overrun Flag */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */
+#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
+/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible.
+ In this case the SLAK bit can be polled.*/
+
+/* Error Flags */
+#define CAN_FLAG_EWGFL ((uint32_t)0x10F00001) /*!< Error Warning Flag */
+#define CAN_FLAG_EPVFL ((uint32_t)0x10F00002) /*!< Error Passive Flag */
+#define CAN_FLAG_BOFFL ((uint32_t)0x10F00004) /*!< Bus-Off Flag */
+#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */
+
+#define IS_CAN_GET_FLAG(FLAG) \
+ (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOFFL) || ((FLAG) == CAN_FLAG_EPVFL) \
+ || ((FLAG) == CAN_FLAG_EWGFL) || ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FFOVR0) \
+ || ((FLAG) == CAN_FLAG_FFULL0) || ((FLAG) == CAN_FLAG_FFMP0) || ((FLAG) == CAN_FLAG_FFOVR1) \
+ || ((FLAG) == CAN_FLAG_FFULL1) || ((FLAG) == CAN_FLAG_FFMP1) || ((FLAG) == CAN_FLAG_RQCPM2) \
+ || ((FLAG) == CAN_FLAG_RQCPM1) || ((FLAG) == CAN_FLAG_RQCPM0) || ((FLAG) == CAN_FLAG_SLAK))
+
+#define IS_CAN_CLEAR_FLAG(FLAG) \
+ (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCPM2) || ((FLAG) == CAN_FLAG_RQCPM1) \
+ || ((FLAG) == CAN_FLAG_RQCPM0) || ((FLAG) == CAN_FLAG_FFULL0) || ((FLAG) == CAN_FLAG_FFOVR0) \
+ || ((FLAG) == CAN_FLAG_FFULL1) || ((FLAG) == CAN_FLAG_FFOVR1) || ((FLAG) == CAN_FLAG_WKU) \
+ || ((FLAG) == CAN_FLAG_SLAK))
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_interrupts
+ * @{
+ */
+
+#define CAN_INT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
+
+/* Receive Interrupts */
+#define CAN_INT_FMP0 ((uint32_t)0x00000002) /*!< DATFIFO 0 message pending Interrupt*/
+#define CAN_INT_FF0 ((uint32_t)0x00000004) /*!< DATFIFO 0 full Interrupt*/
+#define CAN_INT_FOV0 ((uint32_t)0x00000008) /*!< DATFIFO 0 overrun Interrupt*/
+#define CAN_INT_FMP1 ((uint32_t)0x00000010) /*!< DATFIFO 1 message pending Interrupt*/
+#define CAN_INT_FF1 ((uint32_t)0x00000020) /*!< DATFIFO 1 full Interrupt*/
+#define CAN_INT_FOV1 ((uint32_t)0x00000040) /*!< DATFIFO 1 overrun Interrupt*/
+
+/* Operating Mode Interrupts */
+#define CAN_INT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
+#define CAN_INT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
+
+/* Error Interrupts */
+#define CAN_INT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
+#define CAN_INT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
+#define CAN_INT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
+#define CAN_INT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
+#define CAN_INT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/
+
+/* Flags named as Interrupts : kept only for FW compatibility */
+#define CAN_INT_RQCPM0 CAN_INT_TME
+#define CAN_INT_RQCPM1 CAN_INT_TME
+#define CAN_INT_RQCPM2 CAN_INT_TME
+
+#define IS_CAN_INT(IT) \
+ (((IT) == CAN_INT_TME) || ((IT) == CAN_INT_FMP0) || ((IT) == CAN_INT_FF0) || ((IT) == CAN_INT_FOV0) \
+ || ((IT) == CAN_INT_FMP1) || ((IT) == CAN_INT_FF1) || ((IT) == CAN_INT_FOV1) || ((IT) == CAN_INT_EWG) \
+ || ((IT) == CAN_INT_EPV) || ((IT) == CAN_INT_BOF) || ((IT) == CAN_INT_LEC) || ((IT) == CAN_INT_ERR) \
+ || ((IT) == CAN_INT_WKU) || ((IT) == CAN_INT_SLK))
+
+#define IS_CAN_CLEAR_INT(IT) \
+ (((IT) == CAN_INT_TME) || ((IT) == CAN_INT_FF0) || ((IT) == CAN_INT_FOV0) || ((IT) == CAN_INT_FF1) \
+ || ((IT) == CAN_INT_FOV1) || ((IT) == CAN_INT_EWG) || ((IT) == CAN_INT_EPV) || ((IT) == CAN_INT_BOF) \
+ || ((IT) == CAN_INT_LEC) || ((IT) == CAN_INT_ERR) || ((IT) == CAN_INT_WKU) || ((IT) == CAN_INT_SLK))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Legacy
+ * @{
+ */
+#define CANINITSTSFAILED CAN_InitSTS_Failed
+#define CANINITSTSOK CAN_InitSTS_Success
+#define CAN_FilterFIFO0 CAN_Filter_FIFO0
+#define CAN_FilterFIFO1 CAN_Filter_FIFO1
+#define CAN_ID_STD CAN_Standard_Id
+#define CAN_ID_EXT CAN_Extended_Id
+#define CAN_RTRQ_DATA CAN_RTRQ_Data
+#define CAN_RTRQ_REMOTE CAN_RTRQ_Remote
+#define CANTXSTSFAILE CAN_TxSTS_Failed
+#define CANTXSTSOK CAN_TxSTS_Ok
+#define CANTXSTSPENDING CAN_TxSTS_Pending
+#define CAN_STS_NO_MB CAN_TxSTS_NoMailBox
+#define CANSLEEPFAILED CAN_SLEEP_Failed
+#define CANSLEEPOK CAN_SLEEP_Ok
+#define CANWKUFAILED CAN_WKU_Failed
+#define CANWKUOK CAN_WKU_Ok
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions
+ * @{
+ */
+/* Function used to set the CAN configuration to the default reset state *****/
+void CAN_DeInit(CAN_Module* CANx);
+
+/* Initialization and Configuration functions *********************************/
+uint8_t CAN_Init(CAN_Module* CANx, CAN_InitType* CAN_InitParam);
+void CAN1_InitFilter(CAN_FilterInitType* CAN_InitFilterStruct);
+void CAN2_InitFilter(CAN_FilterInitType* CAN_InitFilterStruct);
+void CAN_InitStruct(CAN_InitType* CAN_InitParam);
+void CAN_DebugFreeze(CAN_Module* CANx, FunctionalState Cmd);
+void CAN_EnTTComMode(CAN_Module* CANx, FunctionalState Cmd);
+
+/* Transmit functions *********************************************************/
+uint8_t CAN_TransmitMessage(CAN_Module* CANx, CanTxMessage* TxMessage);
+uint8_t CAN_TransmitSTS(CAN_Module* CANx, uint8_t TransmitMailbox);
+void CAN_CancelTransmitMessage(CAN_Module* CANx, uint8_t Mailbox);
+
+/* Receive functions **********************************************************/
+void CAN_ReceiveMessage(CAN_Module* CANx, uint8_t FIFONum, CanRxMessage* RxMessage);
+void CAN_ReleaseFIFO(CAN_Module* CANx, uint8_t FIFONum);
+uint8_t CAN_PendingMessage(CAN_Module* CANx, uint8_t FIFONum);
+
+/* Operation modes functions **************************************************/
+uint8_t CAN_OperatingModeReq(CAN_Module* CANx, uint8_t CAN_OperatingMode);
+uint8_t CAN_EnterSleep(CAN_Module* CANx);
+uint8_t CAN_WakeUp(CAN_Module* CANx);
+
+/* Error management functions *************************************************/
+uint8_t CAN_GetLastErrCode(CAN_Module* CANx);
+uint8_t CAN_GetReceiveErrCounter(CAN_Module* CANx);
+uint8_t CAN_GetLSBTransmitErrCounter(CAN_Module* CANx);
+
+/* Interrupts and flags management functions **********************************/
+void CAN_INTConfig(CAN_Module* CANx, uint32_t CAN_INT, FunctionalState Cmd);
+FlagStatus CAN_GetFlagSTS(CAN_Module* CANx, uint32_t CAN_FLAG);
+void CAN_ClearFlag(CAN_Module* CANx, uint32_t CAN_FLAG);
+INTStatus CAN_GetIntStatus(CAN_Module* CANx, uint32_t CAN_INT);
+void CAN_ClearINTPendingBit(CAN_Module* CANx, uint32_t CAN_INT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32WB452_CAN_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_crc.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_crc.h
new file mode 100644
index 0000000000..61cedc9ffd
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_crc.h
@@ -0,0 +1,105 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_crc.h
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32WB452_CRC_H__
+#define __N32WB452_CRC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32wb452.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CRC
+ * @{
+ */
+
+/** @addtogroup CRC_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Exported_Functions
+ * @{
+ */
+
+void CRC32_ResetCrc(void);
+uint32_t CRC32_CalcCrc(uint32_t Data);
+uint32_t CRC32_CalcBufCrc(uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t CRC32_GetCrc(void);
+void CRC32_SetIDat(uint8_t IDValue);
+uint8_t CRC32_GetIDat(void);
+
+uint16_t CRC16_CalcBufCrc(uint8_t pBuffer[], uint32_t BufferLength);
+uint16_t CRC16_CalcCRC(uint8_t Data);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32WB452_CRC_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_dac.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_dac.h
new file mode 100644
index 0000000000..77626946c7
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_dac.h
@@ -0,0 +1,307 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_dac.h
+ * @author Nations
+ * @version v1.0.1
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32WB452_DAC_H__
+#define __N32WB452_DAC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32wb452.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DAC
+ * @{
+ */
+
+/** @addtogroup DAC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief DAC Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t Trigger; /*!< Specifies the external trigger for the selected DAC channel.
+ This parameter can be a value of @ref DAC_trigger_selection */
+
+ uint32_t WaveGen; /*!< Specifies whether DAC channel noise waves or triangle waves
+ are generated, or whether no wave is generated.
+ This parameter can be a value of @ref DAC_wave_generation */
+
+ uint32_t
+ LfsrUnMaskTriAmp; /*!< Specifies the LFSR mask for noise wave generation or
+ the maximum amplitude triangle generation for the DAC channel.
+ This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
+
+ uint32_t BufferOutput; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+ This parameter can be a value of @ref DAC_output_buffer */
+} DAC_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup DAC_trigger_selection
+ * @{
+ */
+
+#define DAC_TRG_NONE \
+ ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register \
+ has been loaded, and not by external trigger */
+#define DAC_TRG_T6_TRGO \
+ ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel \
+ */
+#define DAC_TRG_T8_TRGO \
+ ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel \
+ only in High-density devices*/
+#define DAC_TRG_T3_TRGO \
+ ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel \
+ only in Connectivity line, Medium-density and Low-density Value Line devices */
+#define DAC_TRG_T7_TRGO \
+ ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel \
+ */
+#define DAC_TRG_T5_TRGO \
+ ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel \
+ */
+#define DAC_TRG_T15_TRGO \
+ ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel \
+ only in Medium-density and Low-density Value Line devices*/
+#define DAC_TRG_T2_TRGO \
+ ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel \
+ */
+#define DAC_TRG_T4_TRGO \
+ ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel \
+ */
+#define DAC_TRG_EXT_IT9 \
+ ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRG_SOFTWARE ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER) \
+ (((TRIGGER) == DAC_TRG_NONE) || ((TRIGGER) == DAC_TRG_T6_TRGO) || ((TRIGGER) == DAC_TRG_T8_TRGO) \
+ || ((TRIGGER) == DAC_TRG_T7_TRGO) || ((TRIGGER) == DAC_TRG_T5_TRGO) || ((TRIGGER) == DAC_TRG_T2_TRGO) \
+ || ((TRIGGER) == DAC_TRG_T4_TRGO) || ((TRIGGER) == DAC_TRG_EXT_IT9) || ((TRIGGER) == DAC_TRG_SOFTWARE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_wave_generation
+ * @{
+ */
+
+#define DAC_WAVEGEN_NONE ((uint32_t)0x00000000)
+#define DAC_WAVEGEN_NOISE ((uint32_t)0x00000040)
+#define DAC_WAVEGEN_TRIANGLE ((uint32_t)0x00000080)
+#define IS_DAC_GENERATE_WAVE(WAVE) \
+ (((WAVE) == DAC_WAVEGEN_NONE) || ((WAVE) == DAC_WAVEGEN_NOISE) || ((WAVE) == DAC_WAVEGEN_TRIANGLE))
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_lfsrunmask_triangleamplitude
+ * @{
+ */
+
+#define DAC_UNMASK_LFSRBIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_UNMASK_LFSRBITS1_0 \
+ ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS2_0 \
+ ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS3_0 \
+ ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS4_0 \
+ ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS5_0 \
+ ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS6_0 \
+ ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS7_0 \
+ ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS8_0 \
+ ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS9_0 \
+ ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation \
+ */
+#define DAC_UNMASK_LFSRBITS10_0 \
+ ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_UNMASK_LFSRBITS11_0 \
+ ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TRIAMP_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TRIAMP_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
+#define DAC_TRIAMP_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
+#define DAC_TRIAMP_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
+#define DAC_TRIAMP_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
+#define DAC_TRIAMP_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
+#define DAC_TRIAMP_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
+#define DAC_TRIAMP_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
+#define DAC_TRIAMP_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
+#define DAC_TRIAMP_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TRIAMP_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TRIAMP_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) \
+ (((VALUE) == DAC_UNMASK_LFSRBIT0) || ((VALUE) == DAC_UNMASK_LFSRBITS1_0) || ((VALUE) == DAC_UNMASK_LFSRBITS2_0) \
+ || ((VALUE) == DAC_UNMASK_LFSRBITS3_0) || ((VALUE) == DAC_UNMASK_LFSRBITS4_0) \
+ || ((VALUE) == DAC_UNMASK_LFSRBITS5_0) || ((VALUE) == DAC_UNMASK_LFSRBITS6_0) \
+ || ((VALUE) == DAC_UNMASK_LFSRBITS7_0) || ((VALUE) == DAC_UNMASK_LFSRBITS8_0) \
+ || ((VALUE) == DAC_UNMASK_LFSRBITS9_0) || ((VALUE) == DAC_UNMASK_LFSRBITS10_0) \
+ || ((VALUE) == DAC_UNMASK_LFSRBITS11_0) || ((VALUE) == DAC_TRIAMP_1) || ((VALUE) == DAC_TRIAMP_3) \
+ || ((VALUE) == DAC_TRIAMP_7) || ((VALUE) == DAC_TRIAMP_15) || ((VALUE) == DAC_TRIAMP_31) \
+ || ((VALUE) == DAC_TRIAMP_63) || ((VALUE) == DAC_TRIAMP_127) || ((VALUE) == DAC_TRIAMP_255) \
+ || ((VALUE) == DAC_TRIAMP_511) || ((VALUE) == DAC_TRIAMP_1023) || ((VALUE) == DAC_TRIAMP_2047) \
+ || ((VALUE) == DAC_TRIAMP_4095))
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_output_buffer
+ * @{
+ */
+
+#define DAC_BUFFOUTPUT_ENABLE ((uint32_t)0x00000002)
+#define DAC_BUFFOUTPUT_DISABLE ((uint32_t)0x00000000)
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_BUFFOUTPUT_ENABLE) || ((STATE) == DAC_BUFFOUTPUT_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Channel_selection
+ * @{
+ */
+
+#define DAC_CHANNEL_1 ((uint32_t)0x00000000)
+#define DAC_CHANNEL_2 ((uint32_t)0x00000010)
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || ((CHANNEL) == DAC_CHANNEL_2))
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_data_alignment
+ * @{
+ */
+
+#define DAC_ALIGN_R_12BIT ((uint32_t)0x00000000)
+#define DAC_ALIGN_L_12BIT ((uint32_t)0x00000004)
+#define DAC_ALIGN_R_8BIT ((uint32_t)0x00000008)
+#define IS_DAC_ALIGN(ALIGN) \
+ (((ALIGN) == DAC_ALIGN_R_12BIT) || ((ALIGN) == DAC_ALIGN_L_12BIT) || ((ALIGN) == DAC_ALIGN_R_8BIT))
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_wave_generation
+ * @{
+ */
+
+#define DAC_WAVE_NOISE ((uint32_t)0x00000040)
+#define DAC_WAVE_TRIANGLE ((uint32_t)0x00000080)
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NOISE) || ((WAVE) == DAC_WAVE_TRIANGLE))
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_data
+ * @{
+ */
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Functions
+ * @{
+ */
+
+void DAC_DeInit(void);
+void DAC_Init(uint32_t DAC_Channel, DAC_InitType* DAC_InitStruct);
+void DAC_ClearStruct(DAC_InitType* DAC_InitStruct);
+void DAC_Enable(uint32_t DAC_Channel, FunctionalState Cmd);
+
+void DAC_DmaEnable(uint32_t DAC_Channel, FunctionalState Cmd);
+void DAC_SoftTrgEnable(uint32_t DAC_Channel, FunctionalState Cmd);
+void DAC_DualSoftwareTrgEnable(FunctionalState Cmd);
+void DAC_WaveGenerationEnable(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState Cmd);
+void DAC_SetCh1Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetCh2Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetDualChData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
+uint16_t DAC_GetOutputDataVal(uint32_t DAC_Channel);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32WB452_DAC_H__ */
+ /**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_dbg.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_dbg.h
new file mode 100644
index 0000000000..bf52e782e0
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_dbg.h
@@ -0,0 +1,124 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_dbg.h
+ * @author Nations
+ * @version v1.0.1
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32WB452_DBG_H__
+#define __N32WB452_DBG_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32wb452.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DBG
+ * @{
+ */
+
+/** @addtogroup DBGMCU_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Exported_Constants
+ * @{
+ */
+
+#define DBG_SLEEP ((uint32_t)0x00000001)
+#define DBG_STOP ((uint32_t)0x00000002)
+#define DBG_STDBY ((uint32_t)0x00000004)
+#define DBG_IWDG_STOP ((uint32_t)0x00000100)
+#define DBG_WWDG_STOP ((uint32_t)0x00000200)
+#define DBG_TIM1_STOP ((uint32_t)0x00000400)
+#define DBG_TIM2_STOP ((uint32_t)0x00000800)
+#define DBG_TIM3_STOP ((uint32_t)0x00001000)
+#define DBG_TIM4_STOP ((uint32_t)0x00002000)
+#define DBG_CAN1_STOP ((uint32_t)0x00004000)
+#define DBG_I2C1SMBUS_TIMEOUT ((uint32_t)0x00008000)
+#define DBG_I2C2SMBUS_TIMEOUT ((uint32_t)0x00010000)
+#define DBG_TIM8_STOP ((uint32_t)0x00020000)
+#define DBG_TIM5_STOP ((uint32_t)0x00040000)
+#define DBG_TIM6_STOP ((uint32_t)0x00080000)
+#define DBG_TIM7_STOP ((uint32_t)0x00100000)
+#define DBG_CAN2_STOP ((uint32_t)0x00200000)
+
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH)&0xFFC000F8) == 0x00) && ((PERIPH) != 0x00))
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Exported_Functions
+ * @{
+ */
+
+void GetUCID(uint8_t *UCIDbuf);
+void GetUID(uint8_t *UIDbuf);
+void GetDBGMCU_ID(uint8_t *DBGMCU_IDbuf);
+uint32_t DBG_GetRevNum(void);
+uint32_t DBG_GetDevNum(void);
+void DBG_ConfigPeriph(uint32_t DBG_Periph, FunctionalState Cmd);
+
+uint32_t DBG_GetFlashSize(void);
+uint32_t DBG_GetSramSize(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32WB452_DBG_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_dma.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_dma.h
new file mode 100644
index 0000000000..4c5f249086
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_dma.h
@@ -0,0 +1,564 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_dma.h
+ * @author Nations
+ * @version v1.0.1
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32WB452_DMA_H__
+#define __N32WB452_DMA_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32wb452.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @{
+ */
+
+/** @addtogroup DMA_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief DMA Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t PeriphAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
+
+ uint32_t MemAddr; /*!< Specifies the memory base address for DMAy Channelx. */
+
+ uint32_t Direction; /*!< Specifies if the peripheral is the source or destination.
+ This parameter can be a value of @ref DMA_data_transfer_direction */
+
+ uint32_t BufSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
+ The data unit is equal to the configuration set in PeriphDataSize
+ or MemDataSize members depending in the transfer direction. */
+
+ uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register is incremented or not.
+ This parameter can be a value of @ref DMA_peripheral_incremented_mode */
+
+ uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
+ This parameter can be a value of @ref DMA_memory_incremented_mode */
+
+ uint32_t PeriphDataSize; /*!< Specifies the Peripheral data width.
+ This parameter can be a value of @ref DMA_peripheral_data_size */
+
+ uint32_t MemDataSize; /*!< Specifies the Memory data width.
+ This parameter can be a value of @ref DMA_memory_data_size */
+
+ uint32_t CircularMode; /*!< Specifies the operation mode of the DMAy Channelx.
+ This parameter can be a value of @ref DMA_circular_normal_mode.
+ @note: The circular buffer mode cannot be used if the memory-to-memory
+ data transfer is configured on the selected Channel */
+
+ uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
+ This parameter can be a value of @ref DMA_priority_level */
+
+ uint32_t Mem2Mem; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
+ This parameter can be a value of @ref DMA_memory_to_memory */
+} DMA_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Constants
+ * @{
+ */
+
+#define IS_DMA_ALL_PERIPH(PERIPH) \
+ (((PERIPH) == DMA1_CH1) || ((PERIPH) == DMA1_CH2) || ((PERIPH) == DMA1_CH3) || ((PERIPH) == DMA1_CH4) \
+ || ((PERIPH) == DMA1_CH5) || ((PERIPH) == DMA1_CH6) || ((PERIPH) == DMA1_CH7) || ((PERIPH) == DMA1_CH8) \
+ || ((PERIPH) == DMA2_CH1) || ((PERIPH) == DMA2_CH2) || ((PERIPH) == DMA2_CH3) || ((PERIPH) == DMA2_CH4) \
+ || ((PERIPH) == DMA2_CH5) || ((PERIPH) == DMA2_CH6) || ((PERIPH) == DMA2_CH7) || ((PERIPH) == DMA2_CH8))
+
+/** @addtogroup DMA_data_transfer_direction
+ * @{
+ */
+
+#define DMA_DIR_PERIPH_DST ((uint32_t)0x00000010)
+#define DMA_DIR_PERIPH_SRC ((uint32_t)0x00000000)
+#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PERIPH_DST) || ((DIR) == DMA_DIR_PERIPH_SRC))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_peripheral_incremented_mode
+ * @{
+ */
+
+#define DMA_PERIPH_INC_ENABLE ((uint32_t)0x00000040)
+#define DMA_PERIPH_INC_DISABLE ((uint32_t)0x00000000)
+#define IS_DMA_PERIPH_INC_STATE(STATE) (((STATE) == DMA_PERIPH_INC_ENABLE) || ((STATE) == DMA_PERIPH_INC_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_memory_incremented_mode
+ * @{
+ */
+
+#define DMA_MEM_INC_ENABLE ((uint32_t)0x00000080)
+#define DMA_MEM_INC_DISABLE ((uint32_t)0x00000000)
+#define IS_DMA_MEM_INC_STATE(STATE) (((STATE) == DMA_MEM_INC_ENABLE) || ((STATE) == DMA_MEM_INC_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_peripheral_data_size
+ * @{
+ */
+
+#define DMA_PERIPH_DATA_SIZE_BYTE ((uint32_t)0x00000000)
+#define DMA_PERIPH_DATA_SIZE_HALFWORD ((uint32_t)0x00000100)
+#define DMA_PERIPH_DATA_SIZE_WORD ((uint32_t)0x00000200)
+#define IS_DMA_PERIPH_DATA_SIZE(SIZE) \
+ (((SIZE) == DMA_PERIPH_DATA_SIZE_BYTE) || ((SIZE) == DMA_PERIPH_DATA_SIZE_HALFWORD) \
+ || ((SIZE) == DMA_PERIPH_DATA_SIZE_WORD))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_memory_data_size
+ * @{
+ */
+
+#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
+#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
+#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) \
+ (((SIZE) == DMA_MemoryDataSize_Byte) || ((SIZE) == DMA_MemoryDataSize_HalfWord) \
+ || ((SIZE) == DMA_MemoryDataSize_Word))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_circular_normal_mode
+ * @{
+ */
+
+#define DMA_MODE_CIRCULAR ((uint32_t)0x00000020)
+#define DMA_MODE_NORMAL ((uint32_t)0x00000000)
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_MODE_CIRCULAR) || ((MODE) == DMA_MODE_NORMAL))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_priority_level
+ * @{
+ */
+
+#define DMA_PRIORITY_VERY_HIGH ((uint32_t)0x00003000)
+#define DMA_PRIORITY_HIGH ((uint32_t)0x00002000)
+#define DMA_PRIORITY_MEDIUM ((uint32_t)0x00001000)
+#define DMA_PRIORITY_LOW ((uint32_t)0x00000000)
+#define IS_DMA_PRIORITY(PRIORITY) \
+ (((PRIORITY) == DMA_PRIORITY_VERY_HIGH) || ((PRIORITY) == DMA_PRIORITY_HIGH) \
+ || ((PRIORITY) == DMA_PRIORITY_MEDIUM) || ((PRIORITY) == DMA_PRIORITY_LOW))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_memory_to_memory
+ * @{
+ */
+
+#define DMA_M2M_ENABLE ((uint32_t)0x00004000)
+#define DMA_M2M_DISABLE ((uint32_t)0x00000000)
+#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_ENABLE) || ((STATE) == DMA_M2M_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_interrupts_definition
+ * @{
+ */
+
+#define DMA_INT_TXC ((uint32_t)0x00000002)
+#define DMA_INT_HTX ((uint32_t)0x00000004)
+#define DMA_INT_ERR ((uint32_t)0x00000008)
+#define IS_DMA_CONFIG_INT(IT) ((((IT)&0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
+
+#define DMA1_INT_GLB1 ((uint32_t)0x00000001)
+#define DMA1_INT_TXC1 ((uint32_t)0x00000002)
+#define DMA1_INT_HTX1 ((uint32_t)0x00000004)
+#define DMA1_INT_ERR1 ((uint32_t)0x00000008)
+#define DMA1_INT_GLB2 ((uint32_t)0x00000010)
+#define DMA1_INT_TXC2 ((uint32_t)0x00000020)
+#define DMA1_INT_HTX2 ((uint32_t)0x00000040)
+#define DMA1_INT_ERR2 ((uint32_t)0x00000080)
+#define DMA1_INT_GLB3 ((uint32_t)0x00000100)
+#define DMA1_INT_TXC3 ((uint32_t)0x00000200)
+#define DMA1_INT_HTX3 ((uint32_t)0x00000400)
+#define DMA1_INT_ERR3 ((uint32_t)0x00000800)
+#define DMA1_INT_GLB4 ((uint32_t)0x00001000)
+#define DMA1_INT_TXC4 ((uint32_t)0x00002000)
+#define DMA1_INT_HTX4 ((uint32_t)0x00004000)
+#define DMA1_INT_ERR4 ((uint32_t)0x00008000)
+#define DMA1_INT_GLB5 ((uint32_t)0x00010000)
+#define DMA1_INT_TXC5 ((uint32_t)0x00020000)
+#define DMA1_INT_HTX5 ((uint32_t)0x00040000)
+#define DMA1_INT_ERR5 ((uint32_t)0x00080000)
+#define DMA1_INT_GLB6 ((uint32_t)0x00100000)
+#define DMA1_INT_TXC6 ((uint32_t)0x00200000)
+#define DMA1_INT_HTX6 ((uint32_t)0x00400000)
+#define DMA1_INT_ERR6 ((uint32_t)0x00800000)
+#define DMA1_INT_GLB7 ((uint32_t)0x01000000)
+#define DMA1_INT_TXC7 ((uint32_t)0x02000000)
+#define DMA1_INT_HTX7 ((uint32_t)0x04000000)
+#define DMA1_INT_ERR7 ((uint32_t)0x08000000)
+#define DMA1_INT_GLB8 ((uint32_t)0x10000000)
+#define DMA1_INT_TXC8 ((uint32_t)0x20000000)
+#define DMA1_INT_HTX8 ((uint32_t)0x40000000)
+#define DMA1_INT_ERR8 ((uint32_t)0x80000000)
+
+#define DMA2_INT_GLB1 ((uint32_t)0x00000001)
+#define DMA2_INT_TXC1 ((uint32_t)0x00000002)
+#define DMA2_INT_HTX1 ((uint32_t)0x00000004)
+#define DMA2_INT_ERR1 ((uint32_t)0x00000008)
+#define DMA2_INT_GLB2 ((uint32_t)0x00000010)
+#define DMA2_INT_TXC2 ((uint32_t)0x00000020)
+#define DMA2_INT_HTX2 ((uint32_t)0x00000040)
+#define DMA2_INT_ERR2 ((uint32_t)0x00000080)
+#define DMA2_INT_GLB3 ((uint32_t)0x00000100)
+#define DMA2_INT_TXC3 ((uint32_t)0x00000200)
+#define DMA2_INT_HTX3 ((uint32_t)0x00000400)
+#define DMA2_INT_ERR3 ((uint32_t)0x00000800)
+#define DMA2_INT_GLB4 ((uint32_t)0x00001000)
+#define DMA2_INT_TXC4 ((uint32_t)0x00002000)
+#define DMA2_INT_HTX4 ((uint32_t)0x00004000)
+#define DMA2_INT_ERR4 ((uint32_t)0x00008000)
+#define DMA2_INT_GLB5 ((uint32_t)0x00010000)
+#define DMA2_INT_TXC5 ((uint32_t)0x00020000)
+#define DMA2_INT_HTX5 ((uint32_t)0x00040000)
+#define DMA2_INT_ERR5 ((uint32_t)0x00080000)
+#define DMA2_INT_GLB6 ((uint32_t)0x00100000)
+#define DMA2_INT_TXC6 ((uint32_t)0x00200000)
+#define DMA2_INT_HTX6 ((uint32_t)0x00400000)
+#define DMA2_INT_ERR6 ((uint32_t)0x00800000)
+#define DMA2_INT_GLB7 ((uint32_t)0x01000000)
+#define DMA2_INT_TXC7 ((uint32_t)0x02000000)
+#define DMA2_INT_HTX7 ((uint32_t)0x04000000)
+#define DMA2_INT_ERR7 ((uint32_t)0x08000000)
+#define DMA2_INT_GLB8 ((uint32_t)0x10000000)
+#define DMA2_INT_TXC8 ((uint32_t)0x20000000)
+#define DMA2_INT_HTX8 ((uint32_t)0x40000000)
+#define DMA2_INT_ERR8 ((uint32_t)0x80000000)
+
+#define IS_DMA_CLR_INT(IT) ((IT) != 0x00)
+
+#define IS_DMA_GET_IT(IT) \
+ (((IT) == DMA1_INT_GLB1) || ((IT) == DMA1_INT_TXC1) || ((IT) == DMA1_INT_HTX1) || ((IT) == DMA1_INT_ERR1) \
+ || ((IT) == DMA1_INT_GLB2) || ((IT) == DMA1_INT_TXC2) || ((IT) == DMA1_INT_HTX2) || ((IT) == DMA1_INT_ERR2) \
+ || ((IT) == DMA1_INT_GLB3) || ((IT) == DMA1_INT_TXC3) || ((IT) == DMA1_INT_HTX3) || ((IT) == DMA1_INT_ERR3) \
+ || ((IT) == DMA1_INT_GLB4) || ((IT) == DMA1_INT_TXC4) || ((IT) == DMA1_INT_HTX4) || ((IT) == DMA1_INT_ERR4) \
+ || ((IT) == DMA1_INT_GLB5) || ((IT) == DMA1_INT_TXC5) || ((IT) == DMA1_INT_HTX5) || ((IT) == DMA1_INT_ERR5) \
+ || ((IT) == DMA1_INT_GLB6) || ((IT) == DMA1_INT_TXC6) || ((IT) == DMA1_INT_HTX6) || ((IT) == DMA1_INT_ERR6) \
+ || ((IT) == DMA1_INT_GLB7) || ((IT) == DMA1_INT_TXC7) || ((IT) == DMA1_INT_HTX7) || ((IT) == DMA1_INT_ERR7) \
+ || ((IT) == DMA1_INT_GLB8) || ((IT) == DMA1_INT_TXC8) || ((IT) == DMA1_INT_HTX8) || ((IT) == DMA1_INT_ERR8) \
+ || ((IT) == DMA2_INT_GLB1) || ((IT) == DMA2_INT_TXC1) || ((IT) == DMA2_INT_HTX1) || ((IT) == DMA2_INT_ERR1) \
+ || ((IT) == DMA2_INT_GLB2) || ((IT) == DMA2_INT_TXC2) || ((IT) == DMA2_INT_HTX2) || ((IT) == DMA2_INT_ERR2) \
+ || ((IT) == DMA2_INT_GLB3) || ((IT) == DMA2_INT_TXC3) || ((IT) == DMA2_INT_HTX3) || ((IT) == DMA2_INT_ERR3) \
+ || ((IT) == DMA2_INT_GLB4) || ((IT) == DMA2_INT_TXC4) || ((IT) == DMA2_INT_HTX4) || ((IT) == DMA2_INT_ERR4) \
+ || ((IT) == DMA2_INT_GLB5) || ((IT) == DMA2_INT_TXC5) || ((IT) == DMA2_INT_HTX5) || ((IT) == DMA2_INT_ERR5) \
+ || ((IT) == DMA2_INT_GLB6) || ((IT) == DMA2_INT_TXC6) || ((IT) == DMA2_INT_HTX6) || ((IT) == DMA2_INT_ERR6) \
+ || ((IT) == DMA2_INT_GLB7) || ((IT) == DMA2_INT_TXC7) || ((IT) == DMA2_INT_HTX7) || ((IT) == DMA2_INT_ERR7) \
+ || ((IT) == DMA2_INT_GLB8) || ((IT) == DMA2_INT_TXC8) || ((IT) == DMA2_INT_HTX8) || ((IT) == DMA2_INT_ERR8))
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_flags_definition
+ * @{
+ */
+#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
+#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
+#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
+#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
+#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
+#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
+#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
+#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
+#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
+#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
+#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
+#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
+#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
+#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
+#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
+#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
+#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
+#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
+#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
+#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
+#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
+#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
+#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
+#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
+#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
+#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
+#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
+#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
+#define DMA1_FLAG_GL8 ((uint32_t)0x10000000)
+#define DMA1_FLAG_TC8 ((uint32_t)0x20000000)
+#define DMA1_FLAG_HT8 ((uint32_t)0x40000000)
+#define DMA1_FLAG_TE8 ((uint32_t)0x80000000)
+
+#define DMA2_FLAG_GL1 ((uint32_t)0x00000001)
+#define DMA2_FLAG_TC1 ((uint32_t)0x00000002)
+#define DMA2_FLAG_HT1 ((uint32_t)0x00000004)
+#define DMA2_FLAG_TE1 ((uint32_t)0x00000008)
+#define DMA2_FLAG_GL2 ((uint32_t)0x00000010)
+#define DMA2_FLAG_TC2 ((uint32_t)0x00000020)
+#define DMA2_FLAG_HT2 ((uint32_t)0x00000040)
+#define DMA2_FLAG_TE2 ((uint32_t)0x00000080)
+#define DMA2_FLAG_GL3 ((uint32_t)0x00000100)
+#define DMA2_FLAG_TC3 ((uint32_t)0x00000200)
+#define DMA2_FLAG_HT3 ((uint32_t)0x00000400)
+#define DMA2_FLAG_TE3 ((uint32_t)0x00000800)
+#define DMA2_FLAG_GL4 ((uint32_t)0x00001000)
+#define DMA2_FLAG_TC4 ((uint32_t)0x00002000)
+#define DMA2_FLAG_HT4 ((uint32_t)0x00004000)
+#define DMA2_FLAG_TE4 ((uint32_t)0x00008000)
+#define DMA2_FLAG_GL5 ((uint32_t)0x00010000)
+#define DMA2_FLAG_TC5 ((uint32_t)0x00020000)
+#define DMA2_FLAG_HT5 ((uint32_t)0x00040000)
+#define DMA2_FLAG_TE5 ((uint32_t)0x00080000)
+#define DMA2_FLAG_GL6 ((uint32_t)0x00100000)
+#define DMA2_FLAG_TC6 ((uint32_t)0x00200000)
+#define DMA2_FLAG_HT6 ((uint32_t)0x00400000)
+#define DMA2_FLAG_TE6 ((uint32_t)0x00800000)
+#define DMA2_FLAG_GL7 ((uint32_t)0x01000000)
+#define DMA2_FLAG_TC7 ((uint32_t)0x02000000)
+#define DMA2_FLAG_HT7 ((uint32_t)0x04000000)
+#define DMA2_FLAG_TE7 ((uint32_t)0x08000000)
+#define DMA2_FLAG_GL8 ((uint32_t)0x10000000)
+#define DMA2_FLAG_TC8 ((uint32_t)0x20000000)
+#define DMA2_FLAG_HT8 ((uint32_t)0x40000000)
+#define DMA2_FLAG_TE8 ((uint32_t)0x80000000)
+
+#define IS_DMA_CLEAR_FLAG(FLAG) ((FLAG) != 0x00)
+
+#define IS_DMA_GET_FLAG(FLAG) \
+ (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) \
+ || ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || ((FLAG) == DMA1_FLAG_HT2) \
+ || ((FLAG) == DMA1_FLAG_TE2) || ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) \
+ || ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || ((FLAG) == DMA1_FLAG_GL4) \
+ || ((FLAG) == DMA1_FLAG_TC4) || ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) \
+ || ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || ((FLAG) == DMA1_FLAG_HT5) \
+ || ((FLAG) == DMA1_FLAG_TE5) || ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) \
+ || ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || ((FLAG) == DMA1_FLAG_GL7) \
+ || ((FLAG) == DMA1_FLAG_TC7) || ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) \
+ || ((FLAG) == DMA1_FLAG_GL8) || ((FLAG) == DMA1_FLAG_TC8) || ((FLAG) == DMA1_FLAG_HT8) \
+ || ((FLAG) == DMA1_FLAG_TE8) || ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) \
+ || ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || ((FLAG) == DMA2_FLAG_GL2) \
+ || ((FLAG) == DMA2_FLAG_TC2) || ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) \
+ || ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || ((FLAG) == DMA2_FLAG_HT3) \
+ || ((FLAG) == DMA2_FLAG_TE3) || ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) \
+ || ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || ((FLAG) == DMA2_FLAG_GL5) \
+ || ((FLAG) == DMA2_FLAG_TC5) || ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5) \
+ || ((FLAG) == DMA2_FLAG_GL6) || ((FLAG) == DMA2_FLAG_TC6) || ((FLAG) == DMA2_FLAG_HT6) \
+ || ((FLAG) == DMA2_FLAG_TE6) || ((FLAG) == DMA2_FLAG_GL7) || ((FLAG) == DMA2_FLAG_TC7) \
+ || ((FLAG) == DMA2_FLAG_HT7) || ((FLAG) == DMA2_FLAG_TE7) || ((FLAG) == DMA2_FLAG_GL8) \
+ || ((FLAG) == DMA2_FLAG_TC8) || ((FLAG) == DMA2_FLAG_HT8) || ((FLAG) == DMA2_FLAG_TE8))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Buffer_Size
+ * @{
+ */
+
+#define IS_DMA_BUF_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_remap_request_definition
+ * @{
+ */
+#define DMA1_REMAP_ADC1 ((uint32_t)0x00000000)
+#define DMA1_REMAP_UART5_TX ((uint32_t)0x00000001)
+#define DMA1_REMAP_I2C3_TX ((uint32_t)0x00000002)
+#define DMA1_REMAP_TIM2_CH3 ((uint32_t)0x00000003)
+#define DMA1_REMAP_TIM4_CH1 ((uint32_t)0x00000004)
+#define DMA1_REMAP_USART3_TX ((uint32_t)0x00000005)
+#define DMA1_REMAP_I2C3_RX ((uint32_t)0x00000006)
+#define DMA1_REMAP_TIM1_CH1 ((uint32_t)0x00000007)
+#define DMA1_REMAP_TIM2_UP ((uint32_t)0x00000008)
+#define DMA1_REMAP_TIM3_CH3 ((uint32_t)0x00000009)
+#define DMA1_REMAP_SPI1_RX ((uint32_t)0x0000000A)
+#define DMA1_REMAP_USART3_RX ((uint32_t)0x0000000B)
+#define DMA1_REMAP_TIM1_CH2 ((uint32_t)0x0000000C)
+#define DMA1_REMAP_TIM3_CH4 ((uint32_t)0x0000000D)
+#define DMA1_REMAP_TIM3_UP ((uint32_t)0x0000000E)
+#define DMA1_REMAP_SPI1_TX ((uint32_t)0x0000000F)
+#define DMA1_REMAP_USART1_TX ((uint32_t)0x00000010)
+#define DMA1_REMAP_TIM1_CH4 ((uint32_t)0x00000011)
+#define DMA1_REMAP_TIM1_TRIG ((uint32_t)0x00000012)
+#define DMA1_REMAP_TIM1_COM ((uint32_t)0x00000013)
+#define DMA1_REMAP_TIM4_CH2 ((uint32_t)0x00000014)
+#define DMA1_REMAP_SPI_I2S2_RX ((uint32_t)0x00000015)
+#define DMA1_REMAP_I2C2_TX ((uint32_t)0x00000016)
+#define DMA1_REMAP_USART1_RX ((uint32_t)0x00000017)
+#define DMA1_REMAP_TIM1_UP ((uint32_t)0x00000018)
+#define DMA1_REMAP_SPI_I2S2_TX ((uint32_t)0x00000019)
+#define DMA1_REMAP_TIM4_CH3 ((uint32_t)0x0000001B)
+#define DMA1_REMAP_I2C2_RX ((uint32_t)0x0000001C)
+#define DMA1_REMAP_TIM2_CH1 ((uint32_t)0x0000001A)
+#define DMA1_REMAP_USART2_RX ((uint32_t)0x0000001D)
+#define DMA1_REMAP_TIM1_CH3 ((uint32_t)0x0000001E)
+#define DMA1_REMAP_TIM3_CH1 ((uint32_t)0x0000001F)
+#define DMA1_REMAP_TIM3_TRIG ((uint32_t)0x00000020)
+#define DMA1_REMAP_I2C1_TX ((uint32_t)0x00000021)
+#define DMA1_REMAP_USART2_TX ((uint32_t)0x00000022)
+#define DMA1_REMAP_TIM2_CH2 ((uint32_t)0x00000023)
+#define DMA1_REMAP_TIM2_CH4 ((uint32_t)0x00000024)
+#define DMA1_REMAP_TIM4_UP ((uint32_t)0x00000025)
+#define DMA1_REMAP_I2C1_RX ((uint32_t)0x00000026)
+#define DMA1_REMAP_ADC2 ((uint32_t)0x00000027)
+#define DMA1_REMAP_UART5_RX ((uint32_t)0x00000028)
+#define DMA2_REMAP_TIM5_CH4 ((uint32_t)0x00000000)
+#define DMA2_REMAP_TIM5_TRIG ((uint32_t)0x00000001)
+#define DMA2_REMAP_TIM8_CH3 ((uint32_t)0x00000002)
+#define DMA2_REMAP_TIM8_UP ((uint32_t)0x00000003)
+#define DMA2_REMAP_SPI_I2S3_RX ((uint32_t)0x00000004)
+#define DMA2_REMAP_UART6_RX ((uint32_t)0x00000005)
+#define DMA2_REMAP_TIM8_CH4 ((uint32_t)0x00000006)
+#define DMA2_REMAP_TIM8_TRIG ((uint32_t)0x00000007)
+#define DMA2_REMAP_TIM8_COM ((uint32_t)0x00000008)
+#define DMA2_REMAP_TIM5_CH3 ((uint32_t)0x00000009)
+#define DMA2_REMAP_TIM5_UP ((uint32_t)0x0000000A)
+#define DMA2_REMAP_SPI_I2S3_TX ((uint32_t)0x0000000B)
+#define DMA2_REMAP_UART6_TX ((uint32_t)0x0000000C)
+#define DMA2_REMAP_TIM8_CH1 ((uint32_t)0x0000000D)
+#define DMA2_REMAP_UART4_RX ((uint32_t)0x0000000E)
+#define DMA2_REMAP_TIM6_UP ((uint32_t)0x0000000F)
+#define DMA2_REMAP_DAC1 ((uint32_t)0x00000010)
+#define DMA2_REMAP_TIM5_CH2 ((uint32_t)0x00000011)
+#define DMA2_REMAP_SDIO ((uint32_t)0x00000012)
+#define DMA2_REMAP_TIM7_UP ((uint32_t)0x00000013)
+#define DMA2_REMAP_DAC2 ((uint32_t)0x00000014)
+#define DMA2_REMAP_TIM8_CH2 ((uint32_t)0x00000016)
+#define DMA2_REMAP_TIM5_CH1 ((uint32_t)0x00000017)
+#define DMA2_REMAP_UART4_TX ((uint32_t)0x00000018)
+#define DMA2_REMAP_I2C4_TX ((uint32_t)0x0000001A)
+#define DMA2_REMAP_UART7_RX ((uint32_t)0x0000001B)
+#define DMA2_REMAP_I2C4_RX ((uint32_t)0x0000001D)
+#define DMA2_REMAP_UART7_TX ((uint32_t)0x0000001E)
+#define DMA2_REMAP_DVP ((uint32_t)0x00000020)
+
+#define IS_DMA_REMAP(FLAG) \
+ (((FLAG) == DMA1_REMAP_ADC1) || ((FLAG) == DMA1_REMAP_UART5_TX) || ((FLAG) == DMA1_REMAP_I2C3_TX) \
+ || ((FLAG) == DMA1_REMAP_TIM2_CH3) || ((FLAG) == DMA1_REMAP_TIM4_CH1) || ((FLAG) == DMA1_REMAP_USART3_TX) \
+ || ((FLAG) == DMA1_REMAP_I2C3_RX) || ((FLAG) == DMA1_REMAP_TIM1_CH1) || ((FLAG) == DMA1_REMAP_TIM2_UP) \
+ || ((FLAG) == DMA1_REMAP_TIM3_CH3) || ((FLAG) == DMA1_REMAP_SPI1_RX) || ((FLAG) == DMA1_REMAP_USART3_RX) \
+ || ((FLAG) == DMA1_REMAP_TIM1_CH2) || ((FLAG) == DMA1_REMAP_TIM3_CH4) || ((FLAG) == DMA1_REMAP_TIM3_UP) \
+ || ((FLAG) == DMA1_REMAP_SPI1_TX) || ((FLAG) == DMA1_REMAP_USART1_TX) || ((FLAG) == DMA1_REMAP_TIM1_CH4) \
+ || ((FLAG) == DMA1_REMAP_TIM1_TRIG) || ((FLAG) == DMA1_REMAP_TIM1_COM) || ((FLAG) == DMA1_REMAP_TIM4_CH2) \
+ || ((FLAG) == DMA1_REMAP_SPI_I2S2_RX) || ((FLAG) == DMA1_REMAP_I2C2_TX) || ((FLAG) == DMA1_REMAP_USART1_RX) \
+ || ((FLAG) == DMA1_REMAP_TIM1_UP) || ((FLAG) == DMA1_REMAP_SPI_I2S2_TX) || ((FLAG) == DMA1_REMAP_TIM4_CH3) \
+ || ((FLAG) == DMA1_REMAP_I2C2_RX) || ((FLAG) == DMA1_REMAP_TIM2_CH1) || ((FLAG) == DMA1_REMAP_USART2_RX) \
+ || ((FLAG) == DMA1_REMAP_TIM1_CH3) || ((FLAG) == DMA1_REMAP_TIM3_CH1) || ((FLAG) == DMA1_REMAP_TIM3_TRIG) \
+ || ((FLAG) == DMA1_REMAP_I2C1_TX) || ((FLAG) == DMA1_REMAP_USART2_TX) || ((FLAG) == DMA1_REMAP_TIM2_CH2) \
+ || ((FLAG) == DMA1_REMAP_TIM2_CH4) || ((FLAG) == DMA1_REMAP_TIM4_UP) || ((FLAG) == DMA1_REMAP_I2C1_RX) \
+ || ((FLAG) == DMA1_REMAP_ADC2) || ((FLAG) == DMA1_REMAP_UART5_RX) || ((FLAG) == DMA2_REMAP_TIM5_CH4) \
+ || ((FLAG) == DMA2_REMAP_TIM5_TRIG) || ((FLAG) == DMA2_REMAP_TIM8_CH3) || ((FLAG) == DMA2_REMAP_TIM8_UP) \
+ || ((FLAG) == DMA2_REMAP_SPI_I2S3_RX) || ((FLAG) == DMA2_REMAP_UART6_RX) || ((FLAG) == DMA2_REMAP_TIM8_CH4) \
+ || ((FLAG) == DMA2_REMAP_TIM8_TRIG) || ((FLAG) == DMA2_REMAP_TIM8_COM) || ((FLAG) == DMA2_REMAP_TIM5_CH3) \
+ || ((FLAG) == DMA2_REMAP_TIM5_UP) || ((FLAG) == DMA2_REMAP_SPI_I2S3_TX) || ((FLAG) == DMA2_REMAP_UART6_TX) \
+ || ((FLAG) == DMA2_REMAP_TIM8_CH1) || ((FLAG) == DMA2_REMAP_UART4_RX) || ((FLAG) == DMA2_REMAP_TIM6_UP) \
+ || ((FLAG) == DMA2_REMAP_DAC1) || ((FLAG) == DMA2_REMAP_TIM5_CH2) || ((FLAG) == DMA2_REMAP_SDIO) \
+ || ((FLAG) == DMA2_REMAP_TIM7_UP) || ((FLAG) == DMA2_REMAP_DAC2) || ((FLAG) == DMA2_REMAP_TIM8_CH2) \
+ || ((FLAG) == DMA2_REMAP_TIM5_CH1) || ((FLAG) == DMA2_REMAP_UART4_TX) || ((FLAG) == DMA2_REMAP_I2C4_TX) \
+ || ((FLAG) == DMA2_REMAP_UART7_RX) || ((FLAG) == DMA2_REMAP_I2C4_RX) || ((FLAG) == DMA2_REMAP_UART7_TX) \
+ || ((FLAG) == DMA2_REMAP_DVP))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Functions
+ * @{
+ */
+
+void DMA_DeInit(DMA_ChannelType* DMAyChx);
+void DMA_Init(DMA_ChannelType* DMAyChx, DMA_InitType* DMA_InitParam);
+void DMA_StructInit(DMA_InitType* DMA_InitParam);
+void DMA_EnableChannel(DMA_ChannelType* DMAyChx, FunctionalState Cmd);
+void DMA_ConfigInt(DMA_ChannelType* DMAyChx, uint32_t DMAInt, FunctionalState Cmd);
+void DMA_SetCurrDataCounter(DMA_ChannelType* DMAyChx, uint16_t DataNumber);
+uint16_t DMA_GetCurrDataCounter(DMA_ChannelType* DMAyChx);
+FlagStatus DMA_GetFlagStatus(uint32_t DMAyFlag, DMA_Module* DMAy);
+void DMA_ClearFlag(uint32_t DMAyFlag, DMA_Module* DMAy);
+INTStatus DMA_GetIntStatus(uint32_t DMAy_IT, DMA_Module* DMAy);
+void DMA_ClrIntPendingBit(uint32_t DMAy_IT, DMA_Module* DMAy);
+void DMA_RequestRemap(uint32_t DMAy_REMAP, DMA_Module* DMAy, DMA_ChannelType* DMAyChx, FunctionalState Cmd);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32WB452_DMA_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_dvp.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_dvp.h
new file mode 100644
index 0000000000..54537ea23c
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_dvp.h
@@ -0,0 +1,602 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_dvp.h
+ * @author Nations
+ * @version v1.0.3
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+
+#ifndef __N32WB452_DVP_H__
+#define __N32WB452_DVP_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32wb452.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DVP
+ * @brief DVP driver modules
+ * @{
+ */
+
+/** @addtogroup DVP_Exported_Types
+ * @{
+ */
+/**
+ * @brief DVP Init Structure definition
+ */
+typedef struct
+{
+ uint32_t FifoWatermark; /*!< Specifies the max number of fifo data which will request INT or DMA
+ This parameter can be a value of @ref DVP_FifoWatermark */
+
+ uint16_t LineCapture; /*!< Specifies the number of data line captuered in x lines.
+ This parameter can be a value of @ref DVP_LineSelect_Mode */
+
+ uint16_t ByteCapture; /*!< Specifies the number of stop byte captuered in x bytes.
+ This parameter can be a value of @ref DVP_ByteSelect_Mode */
+
+ uint16_t DataInvert; /*!< Specifies the data invert.
+ This parameter can be a value of @ref DVP_DATA_INVERT */
+
+ uint16_t PixelClkPolarity; /*!< Specifies the pixel clock polarity
+ This parameter can be a value of @ref DVP_Pixel_Polarity */
+
+ uint16_t VsyncPolarity; /*!< Specifies the vertical synchronization polarity
+ This parameter can be a value of @ref DVP_Vsync_Polarity */
+
+ uint16_t HsyncPolarity; /*!< Specifies the Horizontal synchronization polarity
+ This parameter can be a value of @ref DVP_Hsync_Polarity */
+
+ uint16_t CaptureMode; /*!< Specifies the capture mode.
+ This parameter can be a value of @ref DVP_Capture_Mode */
+
+ uint16_t RowStart; /*!< Specifies the startint row of the pixel array in a frame */
+
+ uint16_t ColumnStart; /*!< Specifies the starting column of the pixel array row in a frame */
+
+ uint16_t ImageHeight; /*!< Specifies the image's height in a frame */
+
+ uint16_t ImageWidth; /*!< Specifies the image's width in a frame */
+
+} DVP_InitType;
+/**
+ * @}
+ */
+
+/** @addtogroup DVP_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup DVP_FIFO_SOFT_RESET
+ * @{
+ */
+#define DVP_FIFO_SOFT_RESET (DVP_CTRL_FFSWRST)
+/**
+ * @}
+ */
+
+/** @addtogroup DVP_LineSelect_Mode
+ * @{
+ */
+#define DVP_LINE_CAPTURE_ALL (0x00000000)
+#define DVP_LINE_CAPTURE_1_2 (0x1UL << DVP_CTRL_LSM_SHIFT)
+#define DVP_LINE_CAPTURE_1_3 (0x2UL << DVP_CTRL_LSM_SHIFT)
+#define DVP_LINE_CAPTURE_1_4 (0x3UL << DVP_CTRL_LSM_SHIFT)
+#define DVP_LINE_CAPTURE_1_5 (0x4UL << DVP_CTRL_LSM_SHIFT)
+#define DVP_LINE_CAPTURE_1_6 (0x5UL << DVP_CTRL_LSM_SHIFT)
+#define DVP_LINE_CAPTURE_1_7 (0x6UL << DVP_CTRL_LSM_SHIFT)
+#define DVP_LINE_CAPTURE_1_8 (0x7UL << DVP_CTRL_LSM_SHIFT)
+#define IS_DVP_LINE_CAPTURE(_LSM_) (((_LSM_) & (~DVP_CTRL_LSM_MASK) )==0)
+/**
+ * @}
+ */
+
+/** @addtogroup DVP_ByteSelect_Mode
+ * @{
+ */
+#define DVP_BYTE_CAPTURE_ALL (0x00000000)
+#define DVP_BYTE_CAPTURE_1_2 (0x1UL << DVP_CTRL_BSM_SHIFT)
+#define DVP_BYTE_CAPTURE_1_3 (0x2UL << DVP_CTRL_BSM_SHIFT)
+#define DVP_BYTE_CAPTURE_1_4 (0x3UL << DVP_CTRL_BSM_SHIFT)
+#define DVP_BYTE_CAPTURE_1_5 (0x4UL << DVP_CTRL_BSM_SHIFT)
+#define DVP_BYTE_CAPTURE_1_6 (0x5UL << DVP_CTRL_BSM_SHIFT)
+#define DVP_BYTE_CAPTURE_1_7 (0x6UL << DVP_CTRL_BSM_SHIFT)
+#define DVP_BYTE_CAPTURE_1_8 (0x7UL << DVP_CTRL_BSM_SHIFT)
+#define IS_DVP_BYTE_CAPTURE(_BSM_) (((_BSM_) & (~DVP_CTRL_BSM_MASK) )==0)
+
+/**
+ * @}
+ */
+
+/** @addtogroup DVP_DATA_INVERT
+ * @{
+ */
+#define DVP_DATA_INVERT (DVP_CTRL_DATINV)
+#define DVP_DATA_NOTINVERT (0x00000000)
+#define IS_DVP_DATA_INVERT(_INV_) (((_INV_) & (~DVP_CTRL_DATINV_MASK) )==0)
+/**
+ * @}
+ */
+
+/** @addtogroup DVP_Pixel_Polarity
+ * @{
+ */
+#define DVP_PIXEL_POLARITY_FALLING (0x00000000)
+#define DVP_PIXEL_POLARITY_RISING (DVP_CTRL_PCKPOL)
+#define IS_DVP_PIXEL_POLARITY(_POL_) (((_POL_) & (~DVP_CTRL_PCKPOL_MASK) )==0)
+/**
+ * @}
+ */
+
+/** @addtogroup DVP_FifoWatermark
+ * @{
+ */
+#define DVP_WATER_MARK_0 (0x00000000)
+#define DVP_WATER_MARK_1 (0x1UL << DVP_CTRL_FWM_SHIFT)
+#define DVP_WATER_MARK_2 (0x2UL << DVP_CTRL_FWM_SHIFT)
+#define DVP_WATER_MARK_3 (0x3UL << DVP_CTRL_FWM_SHIFT)
+#define DVP_WATER_MARK_4 (0x4UL << DVP_CTRL_FWM_SHIFT)
+#define DVP_WATER_MARK_5 (0x5UL << DVP_CTRL_FWM_SHIFT)
+#define DVP_WATER_MARK_6 (0x6UL << DVP_CTRL_FWM_SHIFT)
+#define DVP_WATER_MARK_7 (0x7UL << DVP_CTRL_FWM_SHIFT)
+
+#define IS_DVP_FIFOWATERMARK(_WATER_) (((_WATER_) >= DVP_WATER_MARK_1) && ((_WATER_) <= DVP_WATER_MARK_7))
+
+/** @addtogroup DVP_Vsync_Polarity
+ * @{
+ */
+#define DVP_VSYNC_POLARITY_HIGH (DVP_CTRL_VSPOL)
+#define DVP_VSYNC_POLARITY_LOW (0x00000000)
+#define IS_DVP_VSYNC_POLARITY(_POL_) (((_POL_) == DVP_VSYNC_POLARITY_HIGH) || ((_POL_) == DVP_VSYNC_POLARITY_LOW))
+/**
+ * @}
+ */
+
+/** @addtogroup DVP_Hsync_Polarity
+ * @{
+ */
+#define DVP_HSYNC_POLARITY_HIGH (DVP_CTRL_HSPOL)
+#define DVP_HSYNC_POLARITY_LOW (0x00000000)
+#define IS_DVP_HSYNC_POLARITY(_POL_) (((_POL_) == DVP_HSYNC_POLARITY_HIGH) || ((_POL_) == DVP_HSYNC_POLARITY_LOW))
+/**
+ * @}
+ */
+
+/** @addtogroup DVP_Capture_Mode
+ * @{
+ */
+#define DVP_CAPTURE_MODE_SINGLE (0x00000000)
+#define DVP_CAPTURE_MODE_CONTINUE (DVP_CTRL_CM)
+#define IS_DVP_CAPTURE_MODE(_MODE_) (((_MODE_) == DVP_CAPTURE_MODE_SINGLE) || ((_MODE_) == DVP_CAPTURE_MODE_CONTINUE))
+/**
+ * @}
+ */
+
+/** @addtogroup DVP_CAPTURE_ENABLE
+ * @{
+ */
+#define DVP_CAPTURE_DISABLE (0x00000000)
+#define DVP_CAPTURE_ENABLE (DVP_CTRL_CAPTURE)
+#define IS_DVP_CAPTURE(_CAPTURE_) (((_CAPTURE_) == DVP_CAPTURE_DISABLE) || ((_CAPTURE_) == DVP_CAPTURE_ENABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup DVP_DMA
+ * @{
+ */
+#define DVP_DMA_DISABLE (0x00000000)
+#define DVP_DMA_ENABLE (DVP_INTEN_DMAEN)
+/**
+ * @}
+ */
+
+/** @addtogroup DVP_StatusFlag
+ * @{
+ */
+#define DVP_FLAG_HERR (DVP_INTSTS_HERRIS)
+#define DVP_FLAG_VERR (DVP_INTSTS_VERRIS)
+#define DVP_FLAG_FO (DVP_INTSTS_FOIS)
+#define DVP_FLAG_FW (DVP_INTSTS_FWIS)
+#define DVP_FLAG_FF (DVP_INTSTS_FFIS)
+#define DVP_FLAG_FE (DVP_INTSTS_FEIS)
+#define DVP_FLAG_LE (DVP_INTSTS_LEIS)
+#define DVP_FLAG_LS (DVP_INTSTS_LSIS)
+#define DVP_FLAG_FME (DVP_INTSTS_FMEIS)
+#define DVP_FLAG_FMS (DVP_INTSTS_FMSIS)
+#define DVP_FLAG_MASK (DVP_FLAG_HERR |DVP_FLAG_VERR |DVP_FLAG_FO \
+ |DVP_FLAG_FW |DVP_FLAG_FF |DVP_FLAG_FE \
+ |DVP_FLAG_LE |DVP_FLAG_LS |DVP_FLAG_FME \
+ |DVP_FLAG_FMS)
+#define IS_DVP_FLAG(_FLAG_) (((_FLAG_) & (~DVP_FLAG_MASK))==0)
+
+/** @addtogroup DVP_ClearFlag
+ * @{
+ */
+#define DVP_CLEAR_FLAG_HERR (DVP_INTSTS_HERRIS)
+#define DVP_CLEAR_FLAG_VERR (DVP_INTSTS_VERRIS)
+#define DVP_CLEAR_FLAG_FO (DVP_INTSTS_FOIS)
+#define DVP_CLEAR_FLAG_FE (DVP_INTSTS_FEIS)
+#define DVP_CLEAR_FLAG_LE (DVP_INTSTS_LEIS)
+#define DVP_CLEAR_FLAG_LS (DVP_INTSTS_LSIS)
+#define DVP_CLEAR_FLAG_FME (DVP_INTSTS_FMEIS)
+#define DVP_CLEAR_FLAG_FMS (DVP_INTSTS_FMSIS)
+#define DVP_CLEAR_FLAG_MASK (DVP_CLEAR_FLAG_HERR |DVP_CLEAR_FLAG_VERR \
+ |DVP_CLEAR_FLAG_FO |DVP_CLEAR_FLAG_FE \
+ |DVP_CLEAR_FLAG_LE |DVP_CLEAR_FLAG_LS \
+ |DVP_CLEAR_FLAG_FME |DVP_CLEAR_FLAG_FMS)
+#define IS_DVP_CLEAR_FLAG(_FLAG_) (((_FLAG_) & (~DVP_CLEAR_FLAG_MASK))==0)
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup DVP_IntEnable
+ * @{
+ */
+#define DVP_INTEN_HERR (DVP_INTEN_HERRIE)
+#define DVP_INTEN_VERR (DVP_INTEN_VERRIE)
+#define DVP_INTEN_FO (DVP_INTEN_FOIE)
+#define DVP_INTEN_FW (DVP_INTEN_FWIE)
+#define DVP_INTEN_FF (DVP_INTEN_FFIE)
+#define DVP_INTEN_FE (DVP_INTEN_FEIE)
+#define DVP_INTEN_LE (DVP_INTEN_LEIE)
+#define DVP_INTEN_LS (DVP_INTEN_LSIE)
+#define DVP_INTEN_FME (DVP_INTEN_FMEIE)
+#define DVP_INTEN_FMS (DVP_INTEN_FMSIE)
+#define DVP_INTEN_MASK (DVP_INTEN_HERR |DVP_INTEN_VERR |DVP_INTEN_FO |DVP_INTEN_FW \
+ |DVP_INTEN_FF |DVP_INTEN_FE |DVP_INTEN_LE |DVP_INTEN_LS \
+ |DVP_INTEN_FME |DVP_INTEN_FMS)
+#define IS_DVP_INTEN(_INT_) (((_INT_) & (~DVP_INTEN_MASK))==0)
+/**
+ * @}
+ */
+
+/** @addtogroup DVP_IntMark
+ * @{
+ */
+#define DVP_MINT_HERR (DVP_MINTSTS_HERRMIS)
+#define DVP_MINT_VERR (DVP_MINTSTS_VERRMIS)
+#define DVP_MINT_FO (DVP_MINTSTS_FOMIS)
+#define DVP_MINT_FW (DVP_MINTSTS_FWMIS)
+#define DVP_MINT_FF (DVP_MINTSTS_FFMIS)
+#define DVP_MINT_FE (DVP_MINTSTS_FEMIS)
+#define DVP_MINT_LE (DVP_MINTSTS_LEMIS)
+#define DVP_MINT_LS (DVP_MINTSTS_LSMIS)
+#define DVP_MINT_FME (DVP_MINTSTS_FMEMIS)
+#define DVP_MINT_FMS (DVP_MINTSTS_FMSMIS)
+#define DVP_MINT_MASK (DVP_MINT_HERR |DVP_MINT_VERR |DVP_MINT_FO |DVP_MINT_FW \
+ |DVP_MINT_FF |DVP_MINT_FE |DVP_MINT_LE |DVP_MINT_LS \
+ |DVP_MINT_FME |DVP_MINT_FMS)
+#define IS_DVP_MINT(_MINT_) (((_MINT_) & (~DVP_MINT_MASK))==0)
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @addtogroup DVP_Exported_Macros
+ * @{
+ */
+
+/**
+ * @brief Config the water mark of FIFO.
+ * @param _Watermark_ Select the new water mark of FIFO.
+ * This parameter can be one of the following values:
+ * @arg DVP_WATER_MARK_1
+ * @arg DVP_WATER_MARK_2
+ * @arg DVP_WATER_MARK_3
+ * @arg DVP_WATER_MARK_4
+ * @retval None
+ */
+#define __DVP_SetFifoWatermark(_Watermark_) (MODIFY_REG(DVP->CTRL, DVP_CTRL_FWM_MASK, _Watermark_))
+
+/**
+ * @brief Config the line capture mode.
+ * @param _LSM_ Specifies the new mode of line capture.
+ * This parameter can be one of the following values:
+ * @arg DVP_LINE_CAPTURE_ALL Capture all lines
+ * @arg DVP_LINE_CAPTURE_1_2 Capture 1 line of each 2 lines
+ * @arg DVP_LINE_CAPTURE_1_3 Capture 1 line of each 3 lines
+ * @arg DVP_LINE_CAPTURE_1_4 Capture 1 line of each 4 lines
+ * @arg DVP_LINE_CAPTURE_1_5 Capture 1 line of each 5 lines
+ * @arg DVP_LINE_CAPTURE_1_6 Capture 1 line of each 6 lines
+ * @arg DVP_LINE_CAPTURE_1_7 Capture 1 line of each 7 lines
+ * @arg DVP_LINE_CAPTURE_1_8 Capture 1 line of each 8 lines
+ * @retval None
+ */
+#define __DVP_SetLineCaptureMode(_LSM_) (MODIFY_REG(DVP->CTRL, DVP_CTRL_LSM_MASK, _LSM_))
+
+/**
+ * @brief Config the byte capture mode.
+ * @param _BSM_ Specifies the new mode of byte capture.
+ * This parameter can be one of the following values:
+ * @arg DVP_BYTE_CAPTURE_ALL Capture all pixels
+ * @arg DVP_BYTE_CAPTURE_1_2 Capture 1 pixel of each 2 pixels
+ * @arg DVP_BYTE_CAPTURE_1_3 Capture 1 pixel of each 3 pixels
+ * @arg DVP_BYTE_CAPTURE_1_4 Capture 1 pixel of each 4 pixels
+ * @arg DVP_BYTE_CAPTURE_1_5 Capture 1 pixel of each 5 pixels
+ * @arg DVP_BYTE_CAPTURE_1_6 Capture 1 pixel of each 6 pixels
+ * @arg DVP_BYTE_CAPTURE_1_7 Capture 1 pixel of each 7 pixels
+ * @arg DVP_BYTE_CAPTURE_1_8 Capture 1 pixel of each 8 pixels
+ * @retval None
+ */
+#define __DVP_SetByteCaptureMode(_BSM_) (MODIFY_REG(DVP->CTRL, DVP_CTRL_BSM_MASK, _BSM_))
+
+/**
+ * @brief Config the data invert function.
+ * @param _INV_ Specifies the data invert or not.
+ * This parameter can be one of the following values:
+ * @arg DVP_DATA_INVERT Invert capture data
+ * @arg DVP_DATA_NOTINVERT Capture data not invert
+ * @retval None
+ */
+#define __DVP_SetDataInvert(_INV_) (MODIFY_REG(DVP->CTRL, DVP_CTRL_DATINV_MASK, _INV_))
+
+/**
+ * @brief Config the pixel clock polarity.
+ * @param _POL_ Specifies the clock edge of pixel clock.
+ * This parameter can be one of the following values:
+ * @arg DVP_PIXEL_POLARITY_FALLING Get data at falling edge
+ * @arg DVP_PIXEL_POLARITY_RISING Get data at rising edge
+ * @retval None
+ */
+#define __DVP_SetPclkPol(_POL_) (MODIFY_REG(DVP->CTRL, DVP_CTRL_PCKPOL_MASK, _POL_))
+
+/**
+ * @brief Config the VSYNC polarity.
+ * @param _POL_ Specifies the active polarity of VSYNC pin.
+ * This parameter can be one of the following values:
+ * @arg DVP_VSYNC_POLARITY_HIGH VSYNC active high
+ * @arg DVP_VSYNC_POLARITY_LOW VSYNC active low
+ * @retval None
+ */
+#define __DVP_SetVsyncPol(_POL_) (MODIFY_REG(DVP->CTRL, DVP_CTRL_VSPOL_MASK, _POL_))
+
+/**
+ * @brief Config the HSYNC polarity.
+ * @param _POL_ Specifies the active polarity of HSYNC pin.
+ * This parameter can be one of the following values:
+ * @arg DVP_HSYNC_POLARITY_HIGH VSYNC active high
+ * @arg DVP_HSYNC_POLARITY_LOW VSYNC active low
+ * @retval None
+ */
+#define __DVP_SetHsyncPol(_POL_) (MODIFY_REG(DVP->CTRL, DVP_CTRL_HSPOL_MASK, _POL_))
+
+/**
+ * @brief Config the capture mode.
+ * @param _POL_ Specifies the new capture mode.
+ * This parameter can be one of the following values:
+ * @arg DVP_CAPTURE_MODE_SINGLE Capture one frame
+ * @arg DVP_CAPTURE_MODE_CONTINUE Capture many frames
+ * @retval None
+ */
+#define __DVP_SetCaptureMode(_MODE_) (MODIFY_REG(DVP->CTRL, DVP_CTRL_CM_MASK, _MODE_))
+
+/**
+ * @brief Enable DVP interface.
+ * @param None
+ * @retval None
+ */
+#define __DVP_StartCapture() (SET_BIT(DVP->CTRL, DVP_CAPTURE_ENABLE))
+
+/**
+ * @brief Disable DVP interface.
+ * @param None
+ * @retval None
+ */
+#define __DVP_StopCapture() (CLEAR_BIT(DVP->CTRL, DVP_CAPTURE_ENABLE))
+
+/**
+ * @brief Disable DVP interface.
+ * @param None
+ * @retval None
+ */
+#define __FIFOIsNotEmpty() (READ_BIT(DVP->STS, DVP_STS_FNE))
+
+/**
+ * @brief Checks whether the specified DVP flag is set.
+ * @param _FLAG_ specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg DVP_FLAG_HERR Hsync error interrupt flag
+ * @arg DVP_FLAG_VERR Vsync error interrupt flag
+ * @arg DVP_FLAG_FO FIFO overflow intterrupt flag
+ * @arg DVP_FLAG_FW FIFO watermark interrupt flag
+ * @arg DVP_FLAG_FF FIFO full interrupt flag
+ * @arg DVP_FLAG_FE FIFO empty interrupt flag
+ * @arg DVP_FLAG_LE Line end interrupt flag
+ * @arg DVP_FLAG_LS Line start interrupt flag
+ * @arg DVP_FLAG_FME Frame end interrupt flag
+ * @arg DVP_FLAG_FMS Frame start interrupt flag
+ * @retval true or false.
+ */
+#define __DVP_FlagIsSet(_FLAG_) (((DVP->INTSTS) & (_FLAG_))==(_FLAG_))
+
+/**
+ * @brief Checks whether the specified DVP flag is not set.
+ * @param _FLAG_ specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg DVP_FLAG_HERR Hsync error interrupt flag
+ * @arg DVP_FLAG_VERR Vsync error interrupt flag
+ * @arg DVP_FLAG_FO FIFO overflow intterrupt flag
+ * @arg DVP_FLAG_FW FIFO watermark interrupt flag
+ * @arg DVP_FLAG_FF FIFO full interrupt flag
+ * @arg DVP_FLAG_FE FIFO empty interrupt flag
+ * @arg DVP_FLAG_LE Line end interrupt flag
+ * @arg DVP_FLAG_LS Line start interrupt flag
+ * @arg DVP_FLAG_FME Frame end interrupt flag
+ * @arg DVP_FLAG_FMS Frame start interrupt flag
+ * @retval true or false.
+ */
+#define __DVP_FlagIsNotSet(_FLAG_) (((DVP->INTSTS) & (_FLAG_))!=(_FLAG_))
+
+/**
+ * @brief Clears the DVP flags.
+ * @param _FLAG_ specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DVP_CLEAR_FLAG_HERR Hsync error interrupt flag clear
+ * @arg DVP_CLEAR_FLAG_VERR Vsync error interrupt flag clear
+ * @arg DVP_CLEAR_FLAG_FO FIFO overflow intterrupt flag clear
+ * @arg DVP_CLEAR_FLAG_FE FIFO empty interrupt flag clear
+ * @arg DVP_CLEAR_FLAG_LE Line end interrupt flag clear
+ * @arg DVP_CLEAR_FLAG_LS Line start interrupt flag clear
+ * @arg DVP_CLEAR_FLAG_FME Frame end interrupt flag clear
+ * @arg DVP_CLEAR_FLAG_FMS Frame start interrupt flag clear
+ * @retval None.
+ */
+#define __DVP_ClrFlag(_FLAG_) (DVP->INTSTS = (~(_FLAG_)) & DVP_CLEAR_FLAG_MASK)
+
+/**
+ * @brief Enable DVP interrupts.
+ * @param _INT_ specifies the interrupt to be enable.
+ * This parameter can be any combination of the following values:
+ * @arg DVP_INTEN_HERR Hsync error interrupt enable
+ * @arg DVP_INTEN_VERR Vsync error interrupt enable
+ * @arg DVP_INTEN_FO FIFO overflow intterrupt enable
+ * @arg DVP_INTEN_FE FIFO empty interrupt enable
+ * @arg DVP_INTEN_LE Line end interrupt enable
+ * @arg DVP_INTEN_LS Line start interrupt enable
+ * @arg DVP_INTEN_FME Frame end interrupt enable
+ * @arg DVP_INTEN_FMS Frame start interrupt enable
+ * @retval None.
+ */
+#define __DVP_EnableInt(_INT_) (SET_BIT(DVP->INTEN, _INT_))
+
+/**
+ * @brief Disable DVP interrupts.
+ * @param _INT_ specifies the interrupt to be disable.
+ * This parameter can be any combination of the following values:
+ * @arg DVP_INTEN_HERR Hsync error interrupt disable
+ * @arg DVP_INTEN_VERR Vsync error interrupt disable
+ * @arg DVP_INTEN_FO FIFO overflow intterrupt disable
+ * @arg DVP_INTEN_FE FIFO empty interrupt disable
+ * @arg DVP_INTEN_LE Line end interrupt disable
+ * @arg DVP_INTEN_LS Line start interrupt disable
+ * @arg DVP_INTEN_FME Frame end interrupt disable
+ * @arg DVP_INTEN_FMS Frame start interrupt disable
+ * @retval None.
+ */
+#define __DVP_DisableInt(_INT_) (CLEAR_BIT(DVP->INTEN, _INT_))
+
+/**
+ * @brief Enable DVP DMA.
+ * @param None.
+ * @retval None.
+ */
+#define __DVP_EnableDMA() (SET_BIT(DVP->INTEN, DVP_INTEN_DMAEN))
+
+/**
+ * @brief Enable DVP DMA.
+ * @param None.
+ * @retval None.
+ */
+#define __DVP_DisableDMA() (CLEAR_BIT(DVP->INTEN, DVP_INTEN_DMAEN))
+
+/**
+ * @brief Checks whether the specified DVP interrupt has occurred or not.
+ * @param _INT_ specifies the DVP interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DVP_MINT_HERR Hsync error interrupt
+ * @arg DVP_MINT_VERR Vsync error interrupt
+ * @arg DVP_MINT_FO FIFO overflow intterrupt
+ * @arg DVP_MINT_FW FIFO watermark interrupt
+ * @arg DVP_MINT_FF FIFO full interrupt
+ * @arg DVP_MINT_FE FIFO empty interrupt
+ * @arg DVP_MINT_LE Line end interrupt
+ * @arg DVP_MINT_LS Line start interrupt
+ * @arg DVP_MINT_FME Frame end interrupt
+ * @arg DVP_MINT_FMS Frame start interrupt
+ * @retval The state of _INT_ (SET or RESET).
+ */
+#define __DVP_GetIntMark(_INT_) (((DVP->MINTSTS) & (_INT_))==(_INT_))
+
+/**
+ * @brief Config the positon of first capture pixel .
+ * @param _VST_ specifies the line positon.
+ * This parameter must be less than 2048.
+ * @param _HST_ specifies the pixel positon.
+ * This parameter must be less than 2048.
+ * @retval None.
+ */
+#define __DVP_SetStartSHIFT(_VST_,_HST_) (DVP->WST=((_VST_)<WSIZE=((_VLINE_)<FIFO))
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup DVP_Exported_Functions
+ * @{
+ */
+void DVP_ResetReg(void);
+void DVP_Init(DVP_InitType* DVP_InitStruct);
+void DVP_DafaultInitParam(DVP_InitType* DVP_InitStruct);
+uint32_t DVP_GetFifoCount(void);
+void DVP_ResetFifo(void);
+void DVP_ConfigDma( FunctionalState Cmd);
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_exti.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_exti.h
new file mode 100644
index 0000000000..f502104f67
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_exti.h
@@ -0,0 +1,206 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_exti.h
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32WB452_EXTI_H__
+#define __N32WB452_EXTI_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32wb452.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup EXTI
+ * @{
+ */
+
+/** @addtogroup EXTI_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief EXTI mode enumeration
+ */
+
+typedef enum
+{
+ EXTI_Mode_Interrupt = 0x00,
+ EXTI_Mode_Event = 0x04
+} EXTI_ModeType;
+
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
+
+/**
+ * @brief EXTI Trigger enumeration
+ */
+
+typedef enum
+{
+ EXTI_Trigger_Rising = 0x08,
+ EXTI_Trigger_Falling = 0x0C,
+ EXTI_Trigger_Rising_Falling = 0x10
+} EXTI_TriggerType;
+
+#define IS_EXTI_TRIGGER(TRIGGER) \
+ (((TRIGGER) == EXTI_Trigger_Rising) || ((TRIGGER) == EXTI_Trigger_Falling) \
+ || ((TRIGGER) == EXTI_Trigger_Rising_Falling))
+/**
+ * @brief EXTI Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
+ This parameter can be any combination of @ref EXTI_Lines */
+
+ EXTI_ModeType EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
+ This parameter can be a value of @ref EXTI_ModeType */
+
+ EXTI_TriggerType EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+ This parameter can be a value of @ref EXTI_ModeType */
+
+ FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
+ This parameter can be set either to ENABLE or DISABLE */
+} EXTI_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup EXTI_Lines
+ * @{
+ */
+
+#define EXTI_LINE0 ((uint32_t)0x00001) /*!< External interrupt line 0 */
+#define EXTI_LINE1 ((uint32_t)0x00002) /*!< External interrupt line 1 */
+#define EXTI_LINE2 ((uint32_t)0x00004) /*!< External interrupt line 2 */
+#define EXTI_LINE3 ((uint32_t)0x00008) /*!< External interrupt line 3 */
+#define EXTI_LINE4 ((uint32_t)0x00010) /*!< External interrupt line 4 */
+#define EXTI_LINE5 ((uint32_t)0x00020) /*!< External interrupt line 5 */
+#define EXTI_LINE6 ((uint32_t)0x00040) /*!< External interrupt line 6 */
+#define EXTI_LINE7 ((uint32_t)0x00080) /*!< External interrupt line 7 */
+#define EXTI_LINE8 ((uint32_t)0x00100) /*!< External interrupt line 8 */
+#define EXTI_LINE9 ((uint32_t)0x00200) /*!< External interrupt line 9 */
+#define EXTI_LINE10 ((uint32_t)0x00400) /*!< External interrupt line 10 */
+#define EXTI_LINE11 ((uint32_t)0x00800) /*!< External interrupt line 11 */
+#define EXTI_LINE12 ((uint32_t)0x01000) /*!< External interrupt line 12 */
+#define EXTI_LINE13 ((uint32_t)0x02000) /*!< External interrupt line 13 */
+#define EXTI_LINE14 ((uint32_t)0x04000) /*!< External interrupt line 14 */
+#define EXTI_LINE15 ((uint32_t)0x08000) /*!< External interrupt line 15 */
+#define EXTI_LINE16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */
+#define EXTI_LINE17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#define EXTI_LINE18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS Wakeup from suspend event */
+#define EXTI_LINE19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
+#define EXTI_LINE20 ((uint32_t)0x100000) /*!< External interrupt line 20 Connected to the RTC Wakeup event */
+#define EXTI_LINE21 ((uint32_t)0x200000) /*!< External interrupt line 21 Connected to the TSC event */
+
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFC00000) == 0x00) && ((LINE) != (uint16_t)0x00))
+#define IS_GET_EXTI_LINE(LINE) \
+ (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) \
+ || ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) \
+ || ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) \
+ || ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) \
+ || ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) \
+ || ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21))
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_TSSEL_Line
+ * @{
+ */
+
+
+#define IS_EXTI_TSSEL_LINE(LINE) \
+ (((LINE) == EXTI_TSSEL_LINE0) || ((LINE) == EXTI_TSSEL_LINE1) || ((LINE) == EXTI_TSSEL_LINE2) \
+ || ((LINE) == EXTI_TSSEL_LINE3) || ((LINE) == EXTI_TSSEL_LINE4) || ((LINE) == EXTI_TSSEL_LINE5) \
+ || ((LINE) == EXTI_TSSEL_LINE6) || ((LINE) == EXTI_TSSEL_LINE7) || ((LINE) == EXTI_TSSEL_LINE8) \
+ || ((LINE) == EXTI_TSSEL_LINE9) || ((LINE) == EXTI_TSSEL_LINE10) || ((LINE) == EXTI_TSSEL_LINE11) \
+ || ((LINE) == EXTI_TSSEL_LINE12) || ((LINE) == EXTI_TSSEL_LINE13) || ((LINE) == EXTI_TSSEL_LINE14) \
+ || ((LINE) == EXTI_TSSEL_LINE15))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Exported_Functions
+ * @{
+ */
+
+void EXTI_DeInit(void);
+void EXTI_InitPeripheral(EXTI_InitType* EXTI_InitStruct);
+void EXTI_InitStruct(EXTI_InitType* EXTI_InitStruct);
+void EXTI_TriggerSWInt(uint32_t EXTI_Line);
+FlagStatus EXTI_GetStatusFlag(uint32_t EXTI_Line);
+void EXTI_ClrStatusFlag(uint32_t EXTI_Line);
+INTStatus EXTI_GetITStatus(uint32_t EXTI_Line);
+void EXTI_ClrITPendBit(uint32_t EXTI_Line);
+void EXTI_RTCTimeStampSel(uint32_t EXTI_TSSEL_Line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32WB452_EXTI_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_flash.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_flash.h
new file mode 100644
index 0000000000..d94acbfafd
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_flash.h
@@ -0,0 +1,375 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_flash.h
+ * @author Nations
+ * @version v1.0.2
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32WB452_FLASH_H__
+#define __N32WB452_FLASH_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32wb452.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @{
+ */
+
+/** @addtogroup FLASH_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief FLASH Status
+ */
+
+typedef enum
+{
+ FLASH_BUSY = 1,
+ FLASH_RESERVED,
+ FLASH_ERR_PG,
+ FLASH_ERR_PV,
+ FLASH_ERR_WRP,
+ FLASH_COMPL,
+ FLASH_ERR_EV,
+ FLASH_ERR_RDP2,
+ FLASH_ERR_ADD,
+ FLASH_TIMEOUT
+} FLASH_STS;
+
+typedef enum
+{
+ FLASH_SMP1 = 0,
+ FLASH_SMP2
+} FLASH_SMPSEL;
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup Flash_Latency
+ * @{
+ */
+
+#define FLASH_LATENCY_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
+#define FLASH_LATENCY_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */
+#define FLASH_LATENCY_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */
+#define FLASH_LATENCY_3 ((uint32_t)0x00000003) /*!< FLASH Three Latency cycles */
+#define FLASH_LATENCY_4 ((uint32_t)0x00000004) /*!< FLASH Four Latency cycles */
+#define IS_FLASH_LATENCY(LATENCY) \
+ (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || ((LATENCY) == FLASH_LATENCY_2) \
+ || ((LATENCY) == FLASH_LATENCY_3) || ((LATENCY) == FLASH_LATENCY_4))
+/**
+ * @}
+ */
+
+/** @addtogroup Prefetch_Buffer_Enable_Disable
+ * @{
+ */
+
+#define FLASH_PrefetchBuf_EN ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */
+#define FLASH_PrefetchBuf_DIS ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */
+#define IS_FLASH_PREFETCHBUF_STATE(STATE) (((STATE) == FLASH_PrefetchBuf_EN) || ((STATE) == FLASH_PrefetchBuf_DIS))
+/**
+ * @}
+ */
+
+/** @addtogroup iCache_Enable_Disable
+ * @{
+ */
+
+#define FLASH_iCache_EN ((uint32_t)0x00000080) /*!< FLASH iCache Enable */
+#define FLASH_iCache_DIS ((uint32_t)0x00000000) /*!< FLASH iCache Disable */
+#define IS_FLASH_ICACHE_STATE(STATE) (((STATE) == FLASH_iCache_EN) || ((STATE) == FLASH_iCache_DIS))
+/**
+ * @}
+ */
+
+/** @addtogroup SMPSEL_SMP1_SMP2
+ * @{
+ */
+
+#define FLASH_SMPSEL_SMP1 ((uint32_t)0x00000000) /*!< FLASH SMPSEL SMP1 */
+#define FLASH_SMPSEL_SMP2 ((uint32_t)0x00000100) /*!< FLASH SMPSEL SMP2 */
+#define IS_FLASH_SMPSEL_STATE(STATE) (((STATE) == FLASH_SMPSEL_SMP1) || ((STATE) == FLASH_SMPSEL_SMP2))
+/**
+ * @}
+ */
+
+/* Values to be used with N32WB452 devices */
+#define FLASH_WRP_Pages0to1 \
+ ((uint32_t)0x00000001) /*!< N32WB452 devices: \
+ Write protection of page 0 to 1 */
+#define FLASH_WRP_Pages2to3 \
+ ((uint32_t)0x00000002) /*!< N32WB452 devices: \
+ Write protection of page 2 to 3 */
+#define FLASH_WRP_Pages4to5 \
+ ((uint32_t)0x00000004) /*!< N32WB452 devices: \
+ Write protection of page 4 to 5 */
+#define FLASH_WRP_Pages6to7 \
+ ((uint32_t)0x00000008) /*!< N32WB452 devices: \
+ Write protection of page 6 to 7 */
+#define FLASH_WRP_Pages8to9 \
+ ((uint32_t)0x00000010) /*!< N32WB452 devices: \
+ Write protection of page 8 to 9 */
+#define FLASH_WRP_Pages10to11 \
+ ((uint32_t)0x00000020) /*!< N32WB452 devices: \
+ Write protection of page 10 to 11 */
+#define FLASH_WRP_Pages12to13 \
+ ((uint32_t)0x00000040) /*!< N32WB452 devices: \
+ Write protection of page 12 to 13 */
+#define FLASH_WRP_Pages14to15 \
+ ((uint32_t)0x00000080) /*!< N32WB452 devices: \
+ Write protection of page 14 to 15 */
+#define FLASH_WRP_Pages16to17 \
+ ((uint32_t)0x00000100) /*!< N32WB452 devices: \
+ Write protection of page 16 to 17 */
+#define FLASH_WRP_Pages18to19 \
+ ((uint32_t)0x00000200) /*!< N32WB452 devices: \
+ Write protection of page 18 to 19 */
+#define FLASH_WRP_Pages20to21 \
+ ((uint32_t)0x00000400) /*!< N32WB452 devices: \
+ Write protection of page 20 to 21 */
+#define FLASH_WRP_Pages22to23 \
+ ((uint32_t)0x00000800) /*!< N32WB452 devices: \
+ Write protection of page 22 to 23 */
+#define FLASH_WRP_Pages24to25 \
+ ((uint32_t)0x00001000) /*!< N32WB452 devices: \
+ Write protection of page 24 to 25 */
+#define FLASH_WRP_Pages26to27 \
+ ((uint32_t)0x00002000) /*!< N32WB452 devices: \
+ Write protection of page 26 to 27 */
+#define FLASH_WRP_Pages28to29 \
+ ((uint32_t)0x00004000) /*!< N32WB452 devices: \
+ Write protection of page 28 to 29 */
+#define FLASH_WRP_Pages30to31 \
+ ((uint32_t)0x00008000) /*!< N32WB452 devices: \
+ Write protection of page 30 to 31 */
+#define FLASH_WRP_Pages32to33 \
+ ((uint32_t)0x00010000) /*!< N32WB452 devices: \
+ Write protection of page 32 to 33 */
+#define FLASH_WRP_Pages34to35 \
+ ((uint32_t)0x00020000) /*!< N32WB452 devices: \
+ Write protection of page 34 to 35 */
+#define FLASH_WRP_Pages36to37 \
+ ((uint32_t)0x00040000) /*!< N32WB452 devices: \
+ Write protection of page 36 to 37 */
+#define FLASH_WRP_Pages38to39 \
+ ((uint32_t)0x00080000) /*!< N32WB452 devices: \
+ Write protection of page 38 to 39 */
+#define FLASH_WRP_Pages40to41 \
+ ((uint32_t)0x00100000) /*!< N32WB452 devices: \
+ Write protection of page 40 to 41 */
+#define FLASH_WRP_Pages42to43 \
+ ((uint32_t)0x00200000) /*!< N32WB452 devices: \
+ Write protection of page 42 to 43 */
+#define FLASH_WRP_Pages44to45 \
+ ((uint32_t)0x00400000) /*!< N32WB452 devices: \
+ Write protection of page 44 to 45 */
+#define FLASH_WRP_Pages46to47 \
+ ((uint32_t)0x00800000) /*!< N32WB452 devices: \
+ Write protection of page 46 to 47 */
+#define FLASH_WRP_Pages48to49 \
+ ((uint32_t)0x01000000) /*!< N32WB452 devices: \
+ Write protection of page 48 to 49 */
+#define FLASH_WRP_Pages50to51 \
+ ((uint32_t)0x02000000) /*!< N32WB452 devices: \
+ Write protection of page 50 to 51 */
+#define FLASH_WRP_Pages52to53 \
+ ((uint32_t)0x04000000) /*!< N32WB452 devices: \
+ Write protection of page 52 to 53 */
+#define FLASH_WRP_Pages54to55 \
+ ((uint32_t)0x08000000) /*!< N32WB452 devices: \
+ Write protection of page 54 to 55 */
+#define FLASH_WRP_Pages56to57 \
+ ((uint32_t)0x10000000) /*!< N32WB452 devices: \
+ Write protection of page 56 to 57 */
+#define FLASH_WRP_Pages58to59 \
+ ((uint32_t)0x20000000) /*!< N32WB452 devices: \
+ Write protection of page 58 to 59 */
+#define FLASH_WRP_Pages60to61 \
+ ((uint32_t)0x40000000) /*!< N32WB452 devices: \
+ Write protection of page 60 to 61 */
+#define FLASH_WRP_Pages62to127 \
+ ((uint32_t)0x80000000) /*!< N32WB452 - 256KB devices: Write protection of page 62 to 127 */
+#define FLASH_WRP_Pages62to255 \
+ ((uint32_t)0x80000000) /*!< N32WB452 - 512KB devices: Write protection of page 62 to 255 */
+
+#define FLASH_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
+
+#define IS_FLASH_WRP_PAGE(PAGE) (((PAGE) != 0x00000000))
+
+#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0807FFFF))
+
+#define IS_OB_DATA_ADDRESS(ADDRESS) ((ADDRESS) == 0x1FFFF804)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_IWatchdog
+ * @{
+ */
+
+#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */
+#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_nRST_STOP
+ * @{
+ */
+
+#define OB_STOP0_NORST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
+#define OB_STOP0_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
+#define IS_OB_STOP0_SOURCE(SOURCE) (((SOURCE) == OB_STOP0_NORST) || ((SOURCE) == OB_STOP0_RST))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_nRST_STDBY
+ * @{
+ */
+
+#define OB_STDBY_NORST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NORST) || ((SOURCE) == OB_STDBY_RST))
+
+/**
+ * @}
+ */
+/** @addtogroup FLASH_Interrupts
+ * @{
+ */
+#define FLASH_INT_ERRIE ((uint32_t)0x00000400) /*!< PGERR WRPERR ERROR error interrupt source */
+#define FLASH_INT_FERR ((uint32_t)0x00000800) /*!< EVERR PVERR interrupt source */
+#define FLASH_INT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */
+
+#define IS_FLASH_INT(IT) ((((IT) & (uint32_t)0xFFFFE3FF) == 0x00000000) && (((IT) != 0x00000000)))
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Flags
+ * @{
+ */
+#define FLASH_FLAG_BUSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */
+#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */
+#define FLASH_FLAG_PVERR ((uint32_t)0x00000008) /*!< FLASH Program Verify ERROR flag after program */
+#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */
+#define FLASH_FLAG_EVERR ((uint32_t)0x00000040) /*!< FLASH Erase Verify ERROR flag after page erase */
+#define FLASH_FLAG_OBERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */
+
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & 0xFFFFFF83) == 0x00) && (FLAG != 0x00))
+
+#define IS_FLASH_GET_FLAG(FLAG) \
+ (((FLAG) == FLASH_FLAG_BUSY) || ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_PVERR) \
+ || ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_EVERR) \
+ || ((FLAG) == FLASH_FLAG_OBERR))
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_STS_CLRFLAG
+ * @{
+ */
+#define FLASH_STS_CLRFLAG (FLASH_FLAG_PGERR | FLASH_FLAG_PVERR | FLASH_FLAG_WRPERR | FLASH_FLAG_EOP |FLASH_FLAG_EVERR)
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Exported_Functions
+ * @{
+ */
+
+/*------------ Functions used for N32WB452 devices -----*/
+void FLASH_SetLatency(uint32_t FLASH_Latency);
+void FLASH_PrefetchBufSet(uint32_t FLASH_PrefetchBuf);
+void FLASH_iCacheRST(void);
+void FLASH_iCacheCmd(uint32_t FLASH_iCache);
+void FLASH_Unlock(void);
+void FLASH_Lock(void);
+FLASH_STS FLASH_EraseOnePage(uint32_t Page_Address);
+FLASH_STS FLASH_MassErase(void);
+FLASH_STS FLASH_EraseOB(void);
+FLASH_STS FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+FLASH_STS FLASH_ProgramOBData(uint32_t Address, uint32_t Data);
+FLASH_STS FLASH_EnWriteProtection(uint32_t FLASH_Pages);
+FLASH_STS FLASH_ReadOutProtectionL1(FunctionalState Cmd);
+FLASH_STS FLASH_ReadOutProtectionL2_ENABLE(void);
+FLASH_STS FLASH_ConfigUserOB(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
+uint32_t FLASH_GetUserOB(void);
+uint32_t FLASH_GetWriteProtectionOB(void);
+FlagStatus FLASH_GetReadOutProtectionSTS(void);
+FlagStatus FLASH_GetReadOutProtectionL2STS(void);
+FlagStatus FLASH_GetPrefetchBufSTS(void);
+void FLASH_SetSMPSELStatus(uint32_t FLASH_smpsel);
+FLASH_SMPSEL FLASH_GetSMPSELStatus(void);
+void FLASH_INTConfig(uint32_t FLASH_INT, FunctionalState Cmd);
+FlagStatus FLASH_GetFlagSTS(uint32_t FLASH_FLAG);
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);
+FLASH_STS FLASH_GetSTS(void);
+FLASH_STS FLASH_WaitForLastOpt(uint32_t Timeout);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32WB452_FLASH_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_gpio.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_gpio.h
new file mode 100644
index 0000000000..c8a87998da
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_gpio.h
@@ -0,0 +1,442 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_gpio.h
+ * @author Nations
+ * @version v1.0.1
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32WB452_GPIO_H__
+#define __N32WB452_GPIO_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32wb452.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/** @addtogroup GPIO_Exported_Types
+ * @{
+ */
+
+#define IS_GPIO_ALL_PERIPH(PERIPH) \
+ (((PERIPH) == GPIOA) || ((PERIPH) == GPIOB) || ((PERIPH) == GPIOC) || ((PERIPH) == GPIOD) || ((PERIPH) == GPIOE))
+
+/**
+ * @brief Output Maximum frequency selection
+ */
+
+typedef enum
+{
+ GPIO_INPUT = 0,
+ GPIO_Speed_2MHz = 1,
+ GPIO_Speed_10MHz,
+ GPIO_Speed_50MHz
+} GPIO_SpeedType;
+#define IS_GPIO_SPEED(SPEED) \
+ (((SPEED) == GPIO_INPUT) || ((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) \
+ || ((SPEED) == GPIO_Speed_50MHz))
+
+/**
+ * @brief Configuration Mode enumeration
+ */
+
+typedef enum
+{
+ GPIO_Mode_AIN = 0x0,
+ GPIO_Mode_IN_FLOATING = 0x04,
+ GPIO_Mode_IPD = 0x28,
+ GPIO_Mode_IPU = 0x48,
+ GPIO_Mode_Out_OD = 0x14,
+ GPIO_Mode_Out_PP = 0x10,
+ GPIO_Mode_AF_OD = 0x1C,
+ GPIO_Mode_AF_PP = 0x18
+} GPIO_ModeType;
+
+#define IS_GPIO_MODE(MODE) \
+ (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || ((MODE) == GPIO_Mode_IPD) \
+ || ((MODE) == GPIO_Mode_IPU) || ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) \
+ || ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP))
+
+/**
+ * @brief GPIO Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_pins_define */
+
+ GPIO_SpeedType GPIO_Speed; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIO_SpeedType */
+
+ GPIO_ModeType GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIO_ModeType */
+} GPIO_InitType;
+
+/**
+ * @brief Bit_SET and Bit_RESET enumeration
+ */
+
+typedef enum
+{
+ Bit_RESET = 0,
+ Bit_SET
+} Bit_OperateType;
+
+#define IS_GPIO_BIT_OPERATE(OPERATE) (((OPERATE) == Bit_RESET) || ((OPERATE) == Bit_SET))
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup GPIO_pins_define
+ * @{
+ */
+
+#define GPIO_PIN_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
+#define GPIO_PIN_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
+#define GPIO_PIN_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
+#define GPIO_PIN_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
+#define GPIO_PIN_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
+#define GPIO_PIN_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
+#define GPIO_PIN_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
+#define GPIO_PIN_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
+#define GPIO_PIN_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
+#define GPIO_PIN_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
+#define GPIO_PIN_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
+#define GPIO_PIN_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
+#define GPIO_PIN_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
+#define GPIO_PIN_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
+#define GPIO_PIN_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
+#define GPIO_PIN_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
+#define GPIO_PIN_ALL ((uint16_t)0xFFFF) /*!< All pins selected */
+
+#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
+
+#define IS_GET_GPIO_PIN(PIN) \
+ (((PIN) == GPIO_PIN_0) || ((PIN) == GPIO_PIN_1) || ((PIN) == GPIO_PIN_2) || ((PIN) == GPIO_PIN_3) \
+ || ((PIN) == GPIO_PIN_4) || ((PIN) == GPIO_PIN_5) || ((PIN) == GPIO_PIN_6) || ((PIN) == GPIO_PIN_7) \
+ || ((PIN) == GPIO_PIN_8) || ((PIN) == GPIO_PIN_9) || ((PIN) == GPIO_PIN_10) || ((PIN) == GPIO_PIN_11) \
+ || ((PIN) == GPIO_PIN_12) || ((PIN) == GPIO_PIN_13) || ((PIN) == GPIO_PIN_14) || ((PIN) == GPIO_PIN_15))
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Remap_define
+ * @{
+ */
+
+#define GPIO_RMP_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */
+#define GPIO_RMP_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */
+#define GPIO_RMP_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */
+#define GPIO_RMP_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */
+#define GPIO_PART_RMP_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */
+#define GPIO_ALL_RMP_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */
+#define GPIO_PART1_RMP_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */
+#define GPIO_PART2_RMP_TIM1 ((uint32_t)0x00160080) /*!< TIM1 Partial Alternate Function mapping */
+#define GPIO_ALL_RMP_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */
+#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */
+#define GPIO_PART2_RMP_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */
+#define GPIO_ALL_RMP_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */
+#define GPIO_PART1_RMP_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */
+#define GPIO_ALL_RMP_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */
+#define GPIO_RMP_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */
+#define GPIO_RMP1_CAN1 ((uint32_t)0x001D2000) /*!< CAN1 Alternate Function mapping */
+#define GPIO_RMP2_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */
+#define GPIO_RMP3_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */
+#define GPIO_RMP_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */
+#define GPIO_RMP_TIM5CH4 ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */
+#define GPIO_RMP_ADC1_ETRI ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */
+#define GPIO_RMP_ADC1_ETRR ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */
+#define GPIO_RMP_ADC2_ETRI ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */
+#define GPIO_RMP_ADC2_ETRR ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */
+#define GPIO_RMP_MII_RMII_SEL ((uint32_t)0x00200080) /*!< MII_RMII_SEL remapping */
+#define GPIO_RMP_SW_JTAG_NO_NJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
+#define GPIO_RMP_SW_JTAG_SW_ENABLE ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define GPIO_RMP_SW_JTAG_DISABLE ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */
+
+/* AFIO_RMP_CFG3 */
+#define GPIO_RMP_SDIO ((uint32_t)0x40000001) /*!< SDIO Alternate Function mapping */
+#define GPIO_RMP1_CAN2 ((uint32_t)0x40110002) /*!< CAN2 Alternate Function mapping */
+#define GPIO_RMP3_CAN2 ((uint32_t)0x40110006) /*!< CAN2 Alternate Function mapping */
+#define GPIO_RMP1_I2C2 ((uint32_t)0x40160040) /*!< I2C2 Alternate Function mapping */
+#define GPIO_RMP3_I2C2 ((uint32_t)0x401600C0) /*!< I2C2 Alternate Function mapping */
+#define GPIO_RMP2_I2C3 ((uint32_t)0x40180200) /*!< I2C3 Alternate Function mapping */
+#define GPIO_RMP3_I2C3 ((uint32_t)0x40180300) /*!< I2C3 Alternate Function mapping */
+#define GPIO_RMP1_I2C4 ((uint32_t)0x401A0400) /*!< I2C4 Alternate Function mapping */
+#define GPIO_RMP3_I2C4 ((uint32_t)0x401A0C00) /*!< I2C4 Alternate Function mapping */
+#define GPIO_RMP1_SPI2 ((uint32_t)0x401C1000) /*!< SPI2 Alternate Function mapping */
+#define GPIO_RMP2_SPI2 ((uint32_t)0x401C3000) /*!< SPI2 Alternate Function mapping */
+#define GPIO_RMP1_SPI3 ((uint32_t)0x401E4000) /*!< SPI3 Alternate Function mapping */
+#define GPIO_RMP2_SPI3 ((uint32_t)0x401E8000) /*!< SPI3 Alternate Function mapping */
+#define GPIO_RMP3_SPI3 ((uint32_t)0x401EC000) /*!< SPI3 Alternate Function mapping */
+#define GPIO_RMP1_ETH ((uint32_t)0x40300001) /*!< ETH Alternate Function mapping */
+#define GPIO_RMP2_ETH ((uint32_t)0x40300002) /*!< ETH Alternate Function mapping */
+#define GPIO_RMP3_ETH ((uint32_t)0x40300003) /*!< ETH Alternate Function mapping */
+#define GPIO_RMP1_SPI1 ((uint32_t)0x41200000) /*!< SPI1 Alternate Function mapping */
+#define GPIO_RMP2_SPI1 ((uint32_t)0x41200004) /*!< SPI1 Alternate Function mapping */
+#define GPIO_RMP3_SPI1 ((uint32_t)0x43200004) /*!< SPI1 Alternate Function mapping */
+#define GPIO_RMP1_USART2 ((uint32_t)0x44200000) /*!< USART2 Alternate Function mapping */
+#define GPIO_RMP2_USART2 ((uint32_t)0x44200008) /*!< USART2 Alternate Function mapping */
+#define GPIO_RMP3_USART2 ((uint32_t)0x46200008) /*!< USART2 Alternate Function mapping */
+#define GPIO_RMP1_UART4 ((uint32_t)0x40340010) /*!< UART4 Alternate Function mapping */
+#define GPIO_RMP2_UART4 ((uint32_t)0x40340020) /*!< UART4 Alternate Function mapping */
+#define GPIO_RMP3_UART4 ((uint32_t)0x40340030) /*!< UART4 Alternate Function mapping */
+#define GPIO_RMP1_UART5 ((uint32_t)0x40360040) /*!< UART5 Alternate Function mapping */
+#define GPIO_RMP2_UART5 ((uint32_t)0x40360080) /*!< UART5 Alternate Function mapping */
+#define GPIO_RMP3_UART5 ((uint32_t)0x403600C0) /*!< UART5 Alternate Function mapping */
+#define GPIO_RMP2_UART6 ((uint32_t)0x40380200) /*!< UART6 Alternate Function mapping */
+#define GPIO_RMP3_UART6 ((uint32_t)0x40380300) /*!< UART6 Alternate Function mapping */
+#define GPIO_RMP1_UART7 ((uint32_t)0x403A0400) /*!< UART7 Alternate Function mapping */
+#define GPIO_RMP3_UART7 ((uint32_t)0x403A0C00) /*!< UART7 Alternate Function mapping */
+#define GPIO_RMP1_TIM8 ((uint32_t)0x403E4000) /*!< TIM8 Alternate Function mapping */
+#define GPIO_RMP3_TIM8 ((uint32_t)0x403EC000) /*!< TIM8 Alternate Function mapping */
+
+/* AFIO_RMP_CFG4 */
+#define GPIO_RMP1_COMP1 ((uint32_t)0x20100001) /*!< COMP1 Alternate Function mapping */
+#define GPIO_RMP2_COMP1 ((uint32_t)0x20100002) /*!< COMP1 Alternate Function mapping */
+#define GPIO_RMP3_COMP1 ((uint32_t)0x20100003) /*!< COMP1 Alternate Function mapping */
+#define GPIO_RMP1_COMP2 ((uint32_t)0x20120004) /*!< COMP2 Alternate Function mapping */
+#define GPIO_RMP2_COMP2 ((uint32_t)0x20120008) /*!< COMP2 Alternate Function mapping */
+#define GPIO_RMP3_COMP2 ((uint32_t)0x2012000C) /*!< COMP2 Alternate Function mapping */
+#define GPIO_RMP1_COMP3 ((uint32_t)0x20140010) /*!< COMP3 Alternate Function mapping */
+#define GPIO_RMP3_COMP3 ((uint32_t)0x20140030) /*!< COMP3 Alternate Function mapping */
+#define GPIO_RMP1_COMP4 ((uint32_t)0x20160040) /*!< COMP4 Alternate Function mapping */
+#define GPIO_RMP3_COMP4 ((uint32_t)0x201600C0) /*!< COMP4 Alternate Function mapping */
+#define GPIO_RMP1_COMP5 ((uint32_t)0x20180100) /*!< COMP5 Alternate Function mapping */
+#define GPIO_RMP2_COMP5 ((uint32_t)0x20180200) /*!< COMP5 Alternate Function mapping */
+#define GPIO_RMP3_COMP5 ((uint32_t)0x20180300) /*!< COMP5 Alternate Function mapping */
+#define GPIO_RMP1_COMP6 ((uint32_t)0x201A0400) /*!< COMP6 Alternate Function mapping */
+#define GPIO_RMP3_COMP6 ((uint32_t)0x201A0C00) /*!< COMP6 Alternate Function mapping */
+#define GPIO_RMP_COMP7 ((uint32_t)0x20001000) /*!< COMP7 Alternate Function mapping */
+#define GPIO_RMP_TSC_OUT_CTRL ((uint32_t)0x20200004) /*!< TSC_OUT_CTRL Alternate Function mapping */
+#define GPIO_RMP1_DVP ((uint32_t)0x20340010) /*!< DVP Alternate Function mapping */
+#define GPIO_RMP3_DVP ((uint32_t)0x20340030) /*!< DVP Alternate Function mapping */
+#define GPIO_Remap_SPI1_NSS ((uint32_t)0x20200040) /*!< SPI1 NSS Alternate Function mapping */
+#define GPIO_Remap_SPI2_NSS ((uint32_t)0x20200080) /*!< SPI2 NSS Alternate Function mapping */
+#define GPIO_Remap_SPI3_NSS ((uint32_t)0x20200100) /*!< SPI3 NSS Alternate Function mapping */
+
+/* AFIO_RMP_CFG5 */
+#define GPIO_Remap_DET_EN_EGB4 ((uint32_t)0x10200080) /*!< EGB4 Detect Alternate Function mapping*/
+#define GPIO_Remap_DET_EN_EGB3 ((uint32_t)0x10200040) /*!< EGB4 Detect Alternate Function mapping*/
+#define GPIO_Remap_DET_EN_EGB2 ((uint32_t)0x10200020) /*!< EGB4 Detect Alternate Function mapping*/
+#define GPIO_Remap_DET_EN_EGB1 ((uint32_t)0x10200010) /*!< EGB4 Detect Alternate Function mapping*/
+#define GPIO_Remap_DET_EN_EGBN4 ((uint32_t)0x10200008) /*!< EGBN4 Detect Alternate Function mapping*/
+#define GPIO_Remap_DET_EN_EGBN3 ((uint32_t)0x10200004) /*!< EGBN3 Detect Alternate Function mapping*/
+#define GPIO_Remap_DET_EN_EGBN2 ((uint32_t)0x10200002) /*!< EGBN2 Detect Alternate Function mapping*/
+#define GPIO_Remap_DET_EN_EGBN1 ((uint32_t)0x10200001) /*!< EGBN1 Detect Alternate Function mapping*/
+#define GPIO_Remap_DET_EN_ECLAMP4 ((uint32_t)0x10008000) /*!< ECLAMP4 Detect Alternate Function mapping*/
+#define GPIO_Remap_DET_EN_ECLAMP3 ((uint32_t)0x10004000) /*!< ECLAMP3 Detect Alternate Function mapping*/
+#define GPIO_Remap_DET_EN_ECLAMP2 ((uint32_t)0x10002000) /*!< ECLAMP2 Detect Alternate Function mapping*/
+#define GPIO_Remap_DET_EN_ECLAMP1 ((uint32_t)0x10001000) /*!< ECLAMP1 Detect Alternate Function mapping*/
+#define GPIO_Remap_RST_EN_EGB4 ((uint32_t)0x10000800) /*!< EGB4 Reset Alternate Function mapping*/
+#define GPIO_Remap_RST_EN_EGB3 ((uint32_t)0x10000400) /*!< EGB3 Reset Alternate Function mapping*/
+#define GPIO_Remap_RST_EN_EGB2 ((uint32_t)0x10000200) /*!< EGB2 Reset Alternate Function mapping*/
+#define GPIO_Remap_RST_EN_EGB1 ((uint32_t)0x10000100) /*!< EGB1 Reset Alternate Function mapping*/
+#define GPIO_Remap_RST_EN_EGBN4 ((uint32_t)0x10000080) /*!< EGBN4 Reset Alternate Function mapping*/
+#define GPIO_Remap_RST_EN_EGBN3 ((uint32_t)0x10000040) /*!< EGBN3 Reset Alternate Function mapping*/
+#define GPIO_Remap_RST_EN_EGBN2 ((uint32_t)0x10000020) /*!< EGBN2 Reset Alternate Function mapping*/
+#define GPIO_Remap_RST_EN_EGBN1 ((uint32_t)0x10000010) /*!< EGBN1 Reset Alternate Function mapping*/
+#define GPIO_Remap_RST_EN_ECLAMP4 ((uint32_t)0x10000008) /*!< ECLAMP4 Reset Alternate Function mapping*/
+#define GPIO_Remap_RST_EN_ECLAMP3 ((uint32_t)0x10000004) /*!< ECLAMP3 Reset Alternate Function mapping*/
+#define GPIO_Remap_RST_EN_ECLAMP2 ((uint32_t)0x10000002) /*!< ECLAMP2 Reset Alternate Function mapping*/
+#define GPIO_Remap_RST_EN_ECLAMP1 ((uint32_t)0x10000001) /*!< ECLAMP1 Reset Alternate Function mapping*/
+
+#define IS_GPIO_REMAP(REMAP) \
+ (((REMAP) == GPIO_RMP_SPI1) || ((REMAP) == GPIO_RMP_I2C1) || ((REMAP) == GPIO_RMP_USART1) \
+ || ((REMAP) == GPIO_RMP_USART2) || ((REMAP) == GPIO_PART_RMP_USART3) || ((REMAP) == GPIO_ALL_RMP_USART3) \
+ || ((REMAP) == GPIO_PART1_RMP_TIM1) || ((REMAP) == GPIO_ALL_RMP_TIM1) || ((REMAP) == GPIO_PartialRemap1_TIM2) \
+ || ((REMAP) == GPIO_PART2_RMP_TIM2) || ((REMAP) == GPIO_ALL_RMP_TIM2) || ((REMAP) == GPIO_PART1_RMP_TIM3) \
+ || ((REMAP) == GPIO_ALL_RMP_TIM3) || ((REMAP) == GPIO_RMP_TIM4) || ((REMAP) == GPIO_RMP1_CAN1) \
+ || ((REMAP) == GPIO_RMP2_CAN1) || ((REMAP) == GPIO_RMP3_CAN1) || ((REMAP) == GPIO_RMP_PD01) || ((REMAP) == GPIO_RMP_TIM5CH4) \
+ || ((REMAP) == GPIO_RMP_ADC1_ETRI) || ((REMAP) == GPIO_RMP_ADC1_ETRR) || ((REMAP) == GPIO_RMP_ADC2_ETRI) \
+ || ((REMAP) == GPIO_RMP_ADC2_ETRR) || ((REMAP) == GPIO_RMP_SW_JTAG_NO_NJTRST) \
+ || ((REMAP) == GPIO_RMP_SW_JTAG_SW_ENABLE) || ((REMAP) == GPIO_RMP_SW_JTAG_DISABLE) \
+ || ((REMAP) == GPIO_RMP_SDIO) || ((REMAP) == GPIO_RMP1_CAN2) \
+ || ((REMAP) == GPIO_RMP3_CAN2) \
+ || ((REMAP) == GPIO_RMP1_I2C2) || ((REMAP) == GPIO_RMP3_I2C2) || ((REMAP) == GPIO_RMP2_I2C3) \
+ || ((REMAP) == GPIO_RMP3_I2C3) || ((REMAP) == GPIO_RMP1_I2C4) || ((REMAP) == GPIO_RMP3_I2C4) \
+ || ((REMAP) == GPIO_RMP1_SPI2) || ((REMAP) == GPIO_RMP2_SPI2) || ((REMAP) == GPIO_RMP1_SPI3) \
+ || ((REMAP) == GPIO_RMP2_SPI3) || ((REMAP) == GPIO_RMP3_SPI3) || ((REMAP) == GPIO_RMP1_ETH) \
+ || ((REMAP) == GPIO_RMP2_ETH) || ((REMAP) == GPIO_RMP3_ETH) || ((REMAP) == GPIO_RMP1_SPI1) \
+ || ((REMAP) == GPIO_RMP2_SPI1) || ((REMAP) == GPIO_RMP3_SPI1) || ((REMAP) == GPIO_RMP1_USART2) \
+ || ((REMAP) == GPIO_RMP2_USART2) || ((REMAP) == GPIO_RMP3_USART2) || ((REMAP) == GPIO_RMP1_UART4) \
+ || ((REMAP) == GPIO_RMP2_UART4) || ((REMAP) == GPIO_RMP3_UART4) || ((REMAP) == GPIO_RMP1_UART5) \
+ || ((REMAP) == GPIO_RMP2_UART5) || ((REMAP) == GPIO_RMP3_UART5) || ((REMAP) == GPIO_RMP2_UART6) \
+ || ((REMAP) == GPIO_RMP3_UART6) || ((REMAP) == GPIO_RMP1_UART7) || ((REMAP) == GPIO_RMP3_UART7) \
+ || ((REMAP) == GPIO_RMP1_TIM8) \
+ || ((REMAP) == GPIO_RMP3_TIM8) || ((REMAP) == GPIO_RMP1_COMP1) || ((REMAP) == GPIO_RMP2_COMP1) \
+ || ((REMAP) == GPIO_RMP3_COMP1) || ((REMAP) == GPIO_RMP1_COMP2) || ((REMAP) == GPIO_RMP2_COMP2) \
+ || ((REMAP) == GPIO_RMP3_COMP2) || ((REMAP) == GPIO_RMP1_COMP3) || ((REMAP) == GPIO_RMP3_COMP3) \
+ || ((REMAP) == GPIO_RMP1_COMP4) || ((REMAP) == GPIO_RMP3_COMP4) || ((REMAP) == GPIO_RMP1_COMP5) \
+ || ((REMAP) == GPIO_RMP2_COMP5) || ((REMAP) == GPIO_RMP3_COMP5) || ((REMAP) == GPIO_RMP1_COMP6) \
+ || ((REMAP) == GPIO_RMP3_COMP6) || ((REMAP) == GPIO_RMP_COMP7) \
+ || ((REMAP) == GPIO_RMP_TSC_OUT_CTRL) || ((REMAP) == GPIO_RMP1_DVP) \
+ || ((REMAP) == GPIO_RMP3_DVP) || ((REMAP) == GPIO_Remap_SPI1_NSS) || ((REMAP) == GPIO_Remap_SPI2_NSS) \
+ || ((REMAP) == GPIO_Remap_SPI3_NSS) || ((REMAP) == GPIO_RMP_MII_RMII_SEL) \
+ || ((REMAP) == GPIO_PART2_RMP_TIM1) || ((REMAP) == GPIO_Remap_DET_EN_EGB4) || ((REMAP) == GPIO_Remap_DET_EN_EGB3) \
+ || ((REMAP) == GPIO_Remap_DET_EN_EGB2) || ((REMAP) == GPIO_Remap_DET_EN_EGB1) \
+ || ((REMAP) == GPIO_Remap_DET_EN_EGBN4) || ((REMAP) == GPIO_Remap_DET_EN_EGBN3) \
+ || ((REMAP) == GPIO_Remap_DET_EN_EGBN2) || ((REMAP) == GPIO_Remap_DET_EN_EGBN1) \
+ || ((REMAP) == GPIO_Remap_DET_EN_ECLAMP4) || ((REMAP) == GPIO_Remap_DET_EN_ECLAMP3) \
+ || ((REMAP) == GPIO_Remap_DET_EN_ECLAMP2) || ((REMAP) == GPIO_Remap_DET_EN_ECLAMP1) \
+ || ((REMAP) == GPIO_Remap_RST_EN_EGB4) || ((REMAP) == GPIO_Remap_RST_EN_EGB3) \
+ || ((REMAP) == GPIO_Remap_RST_EN_EGB2) || ((REMAP) == GPIO_Remap_RST_EN_EGB1) \
+ || ((REMAP) == GPIO_Remap_RST_EN_EGBN4) || ((REMAP) == GPIO_Remap_RST_EN_EGBN3) \
+ || ((REMAP) == GPIO_Remap_RST_EN_EGBN2) || ((REMAP) == GPIO_Remap_RST_EN_EGBN1) \
+ || ((REMAP) == GPIO_Remap_RST_EN_ECLAMP4) || ((REMAP) == GPIO_Remap_RST_EN_ECLAMP3) \
+ || ((REMAP) == GPIO_Remap_RST_EN_ECLAMP2) || ((REMAP) == GPIO_Remap_RST_EN_ECLAMP1))
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Port_Sources
+ * @{
+ */
+
+#define GPIOA_PORT_SOURCE ((uint8_t)0x00)
+#define GPIOB_PORT_SOURCE ((uint8_t)0x01)
+#define GPIOC_PORT_SOURCE ((uint8_t)0x02)
+#define GPIOD_PORT_SOURCE ((uint8_t)0x03)
+#define GPIOE_PORT_SOURCE ((uint8_t)0x04)
+#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) \
+ (((PORTSOURCE) == GPIOA_PORT_SOURCE) || ((PORTSOURCE) == GPIOB_PORT_SOURCE) || ((PORTSOURCE) == GPIOC_PORT_SOURCE) \
+ || ((PORTSOURCE) == GPIOD_PORT_SOURCE) || ((PORTSOURCE) == GPIOE_PORT_SOURCE))
+
+#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) \
+ (((PORTSOURCE) == GPIOA_PORT_SOURCE) || ((PORTSOURCE) == GPIOB_PORT_SOURCE) || ((PORTSOURCE) == GPIOC_PORT_SOURCE) \
+ || ((PORTSOURCE) == GPIOD_PORT_SOURCE) || ((PORTSOURCE) == GPIOE_PORT_SOURCE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Pin_sources
+ * @{
+ */
+
+#define GPIO_PIN_SOURCE0 ((uint8_t)0x00)
+#define GPIO_PIN_SOURCE1 ((uint8_t)0x01)
+#define GPIO_PIN_SOURCE2 ((uint8_t)0x02)
+#define GPIO_PIN_SOURCE3 ((uint8_t)0x03)
+#define GPIO_PIN_SOURCE4 ((uint8_t)0x04)
+#define GPIO_PIN_SOURCE5 ((uint8_t)0x05)
+#define GPIO_PIN_SOURCE6 ((uint8_t)0x06)
+#define GPIO_PIN_SOURCE7 ((uint8_t)0x07)
+#define GPIO_PIN_SOURCE8 ((uint8_t)0x08)
+#define GPIO_PIN_SOURCE9 ((uint8_t)0x09)
+#define GPIO_PIN_SOURCE10 ((uint8_t)0x0A)
+#define GPIO_PIN_SOURCE11 ((uint8_t)0x0B)
+#define GPIO_PIN_SOURCE12 ((uint8_t)0x0C)
+#define GPIO_PIN_SOURCE13 ((uint8_t)0x0D)
+#define GPIO_PIN_SOURCE14 ((uint8_t)0x0E)
+#define GPIO_PIN_SOURCE15 ((uint8_t)0x0F)
+
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) \
+ (((PINSOURCE) == GPIO_PIN_SOURCE0) || ((PINSOURCE) == GPIO_PIN_SOURCE1) || ((PINSOURCE) == GPIO_PIN_SOURCE2) \
+ || ((PINSOURCE) == GPIO_PIN_SOURCE3) || ((PINSOURCE) == GPIO_PIN_SOURCE4) || ((PINSOURCE) == GPIO_PIN_SOURCE5) \
+ || ((PINSOURCE) == GPIO_PIN_SOURCE6) || ((PINSOURCE) == GPIO_PIN_SOURCE7) || ((PINSOURCE) == GPIO_PIN_SOURCE8) \
+ || ((PINSOURCE) == GPIO_PIN_SOURCE9) || ((PINSOURCE) == GPIO_PIN_SOURCE10) || ((PINSOURCE) == GPIO_PIN_SOURCE11) \
+ || ((PINSOURCE) == GPIO_PIN_SOURCE12) || ((PINSOURCE) == GPIO_PIN_SOURCE13) || ((PINSOURCE) == GPIO_PIN_SOURCE14) \
+ || ((PINSOURCE) == GPIO_PIN_SOURCE15))
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Exported_Functions
+ * @{
+ */
+
+void GPIO_DeInit(GPIO_Module* GPIOx);
+void GPIO_AFIOInitDefault(void);
+void GPIO_InitPeripheral(GPIO_Module* GPIOx, GPIO_InitType* GPIO_InitStruct);
+void GPIO_InitStruct(GPIO_InitType* GPIO_InitStruct);
+uint8_t GPIO_ReadInputDataBit(GPIO_Module* GPIOx, uint16_t Pin);
+uint16_t GPIO_ReadInputData(GPIO_Module* GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_Module* GPIOx, uint16_t Pin);
+uint16_t GPIO_ReadOutputData(GPIO_Module* GPIOx);
+void GPIO_SetBits(GPIO_Module* GPIOx, uint16_t Pin);
+void GPIO_ResetBits(GPIO_Module* GPIOx, uint16_t Pin);
+void GPIO_WriteBit(GPIO_Module* GPIOx, uint16_t Pin, Bit_OperateType BitCmd);
+void GPIO_Write(GPIO_Module* GPIOx, uint16_t PortVal);
+void GPIO_ConfigPinLock(GPIO_Module* GPIOx, uint16_t Pin);
+void GPIO_ConfigEventOutput(uint8_t PortSource, uint8_t PinSource);
+void GPIO_CtrlEventOutput(FunctionalState Cmd);
+void GPIO_ConfigPinRemap(uint32_t RmpPin, FunctionalState Cmd);
+void GPIO_ConfigEXTILine(uint8_t PortSource, uint8_t PinSource);
+void GPIO_SetBitsHigh16(GPIO_Module* GPIOx, uint32_t Pin);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32WB452_GPIO_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_i2c.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_i2c.h
new file mode 100644
index 0000000000..caa597a0f7
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_i2c.h
@@ -0,0 +1,671 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_i2c.h
+ * @author Nations
+ * @version v1.0.1
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32WB452_I2C_H__
+#define __N32WB452_I2C_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32wb452.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @{
+ */
+
+/** @addtogroup I2C_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief I2C Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t ClkSpeed; /*!< Specifies the clock frequency.
+ This parameter must be set to a value lower than 400kHz */
+
+ uint16_t BusMode; /*!< Specifies the I2C mode.
+ This parameter can be a value of @ref I2C_BusMode */
+
+ uint16_t FmDutyCycle; /*!< Specifies the I2C fast mode duty cycle.
+ This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+ uint16_t OwnAddr1; /*!< Specifies the first device own address.
+ This parameter can be a 7-bit or 10-bit address. */
+
+ uint16_t AckEnable; /*!< Enables or disables the acknowledgement.
+ This parameter can be a value of @ref I2C_acknowledgement */
+
+ uint16_t AddrMode; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
+ This parameter can be a value of @ref I2C_acknowledged_address */
+} I2C_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Exported_Constants
+ * @{
+ */
+
+#define IS_I2C_PERIPH(PERIPH) (((PERIPH) == I2C1) || ((PERIPH) == I2C2) || ((PERIPH) == I2C3) || ((PERIPH) == I2C4))
+/** @addtogroup I2C_BusMode
+ * @{
+ */
+
+#define I2C_BUSMODE_I2C ((uint16_t)0x0000)
+#define I2C_BUSMODE_SMBDEVICE ((uint16_t)0x0002)
+#define I2C_BUSMODE_SMBHOST ((uint16_t)0x000A)
+#define IS_I2C_BUS_MODE(MODE) \
+ (((MODE) == I2C_BUSMODE_I2C) || ((MODE) == I2C_BUSMODE_SMBDEVICE) || ((MODE) == I2C_BUSMODE_SMBHOST))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_duty_cycle_in_fast_mode
+ * @{
+ */
+
+#define I2C_FMDUTYCYCLE_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
+#define I2C_FMDUTYCYCLE_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
+#define IS_I2C_FM_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_FMDUTYCYCLE_16_9) || ((CYCLE) == I2C_FMDUTYCYCLE_2))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_acknowledgement
+ * @{
+ */
+
+#define I2C_ACKEN ((uint16_t)0x0400)
+#define I2C_ACKDIS ((uint16_t)0x0000)
+#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_ACKEN) || ((STATE) == I2C_ACKDIS))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_transfer_direction
+ * @{
+ */
+
+#define I2C_DIRECTION_SEND ((uint8_t)0x00)
+#define I2C_DIRECTION_RECV ((uint8_t)0x01)
+#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_DIRECTION_SEND) || ((DIRECTION) == I2C_DIRECTION_RECV))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_acknowledged_address
+ * @{
+ */
+
+#define I2C_ADDR_MODE_7BIT ((uint16_t)0x4000)
+#define I2C_ADDR_MODE_10BIT ((uint16_t)0xC000)
+#define IS_I2C_ADDR_MODE(ADDRESS) (((ADDRESS) == I2C_ADDR_MODE_7BIT) || ((ADDRESS) == I2C_ADDR_MODE_10BIT))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_registers
+ * @{
+ */
+
+#define I2C_REG_CTRL1 ((uint8_t)0x00)
+#define I2C_REG_CTRL2 ((uint8_t)0x04)
+#define I2C_REG_OADDR1 ((uint8_t)0x08)
+#define I2C_REG_OADDR2 ((uint8_t)0x0C)
+#define I2C_REG_DAT ((uint8_t)0x10)
+#define I2C_REG_STS1 ((uint8_t)0x14)
+#define I2C_REG_STS2 ((uint8_t)0x18)
+#define I2C_REG_CLKCTRL ((uint8_t)0x1C)
+#define I2C_REG_TMRISE ((uint8_t)0x20)
+#define IS_I2C_REG(REGISTER) \
+ (((REGISTER) == I2C_REG_CTRL1) || ((REGISTER) == I2C_REG_CTRL2) || ((REGISTER) == I2C_REG_OADDR1) \
+ || ((REGISTER) == I2C_REG_OADDR2) || ((REGISTER) == I2C_REG_DAT) || ((REGISTER) == I2C_REG_STS1) \
+ || ((REGISTER) == I2C_REG_STS2) || ((REGISTER) == I2C_REG_CLKCTRL) || ((REGISTER) == I2C_REG_TMRISE))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_SMBus_alert_pin_level
+ * @{
+ */
+
+#define I2C_SMBALERT_LOW ((uint16_t)0x2000)
+#define I2C_SMBALERT_HIGH ((uint16_t)0xDFFF)
+#define IS_I2C_SMB_ALERT(ALERT) (((ALERT) == I2C_SMBALERT_LOW) || ((ALERT) == I2C_SMBALERT_HIGH))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_PEC_position
+ * @{
+ */
+
+#define I2C_PEC_POS_NEXT ((uint16_t)0x0800)
+#define I2C_PEC_POS_CURRENT ((uint16_t)0xF7FF)
+#define IS_I2C_PEC_POS(POSITION) (((POSITION) == I2C_PEC_POS_NEXT) || ((POSITION) == I2C_PEC_POS_CURRENT))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_NCAK_position
+ * @{
+ */
+
+#define I2C_NACK_POS_NEXT ((uint16_t)0x0800)
+#define I2C_NACK_POS_CURRENT ((uint16_t)0xF7FF)
+#define IS_I2C_NACK_POS(POSITION) (((POSITION) == I2C_NACK_POS_NEXT) || ((POSITION) == I2C_NACK_POS_CURRENT))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_interrupts_definition
+ * @{
+ */
+
+#define I2C_INT_BUF ((uint16_t)0x0400)
+#define I2C_INT_EVENT ((uint16_t)0x0200)
+#define I2C_INT_ERR ((uint16_t)0x0100)
+#define IS_I2C_CFG_INT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_interrupts_definition
+ * @{
+ */
+
+#define I2C_INT_SMBALERT ((uint32_t)0x01008000)
+#define I2C_INT_TIMOUT ((uint32_t)0x01004000)
+#define I2C_INT_PECERR ((uint32_t)0x01001000)
+#define I2C_INT_OVERRUN ((uint32_t)0x01000800)
+#define I2C_INT_ACKFAIL ((uint32_t)0x01000400)
+#define I2C_INT_ARLOST ((uint32_t)0x01000200)
+#define I2C_INT_BUSERR ((uint32_t)0x01000100)
+#define I2C_INT_TXDATE ((uint32_t)0x06000080)
+#define I2C_INT_RXDATNE ((uint32_t)0x06000040)
+#define I2C_INT_STOPF ((uint32_t)0x02000010)
+#define I2C_INT_ADDR10F ((uint32_t)0x02000008)
+#define I2C_INT_BYTEF ((uint32_t)0x02000004)
+#define I2C_INT_ADDRF ((uint32_t)0x02000002)
+#define I2C_INT_STARTBF ((uint32_t)0x02000001)
+
+#define IS_I2C_CLR_INT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
+
+#define IS_I2C_GET_INT(IT) \
+ (((IT) == I2C_INT_SMBALERT) || ((IT) == I2C_INT_TIMOUT) || ((IT) == I2C_INT_PECERR) || ((IT) == I2C_INT_OVERRUN) \
+ || ((IT) == I2C_INT_ACKFAIL) || ((IT) == I2C_INT_ARLOST) || ((IT) == I2C_INT_BUSERR) || ((IT) == I2C_INT_TXDATE) \
+ || ((IT) == I2C_INT_RXDATNE) || ((IT) == I2C_INT_STOPF) || ((IT) == I2C_INT_ADDR10F) || ((IT) == I2C_INT_BYTEF) \
+ || ((IT) == I2C_INT_ADDRF) || ((IT) == I2C_INT_STARTBF))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_flags_definition
+ * @{
+ */
+
+/**
+ * @brief STS2 register flags
+ */
+
+#define I2C_FLAG_DUALFLAG ((uint32_t)0x00800000)
+#define I2C_FLAG_SMBHADDR ((uint32_t)0x00400000)
+#define I2C_FLAG_SMBDADDR ((uint32_t)0x00200000)
+#define I2C_FLAG_GCALLADDR ((uint32_t)0x00100000)
+#define I2C_FLAG_TRF ((uint32_t)0x00040000)
+#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
+#define I2C_FLAG_MSMODE ((uint32_t)0x00010000)
+
+/**
+ * @brief STS1 register flags
+ */
+
+#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
+#define I2C_FLAG_TIMOUT ((uint32_t)0x10004000)
+#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
+#define I2C_FLAG_OVERRUN ((uint32_t)0x10000800)
+#define I2C_FLAG_ACKFAIL ((uint32_t)0x10000400)
+#define I2C_FLAG_ARLOST ((uint32_t)0x10000200)
+#define I2C_FLAG_BUSERR ((uint32_t)0x10000100)
+#define I2C_FLAG_TXDATE ((uint32_t)0x10000080)
+#define I2C_FLAG_RXDATNE ((uint32_t)0x10000040)
+#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
+#define I2C_FLAG_ADDR10F ((uint32_t)0x10000008)
+#define I2C_FLAG_BYTEF ((uint32_t)0x10000004)
+#define I2C_FLAG_ADDRF ((uint32_t)0x10000002)
+#define I2C_FLAG_STARTBF ((uint32_t)0x10000001)
+
+#define IS_I2C_CLR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
+
+#define IS_I2C_GET_FLAG(FLAG) \
+ (((FLAG) == I2C_FLAG_DUALFLAG) || ((FLAG) == I2C_FLAG_SMBHADDR) || ((FLAG) == I2C_FLAG_SMBDADDR) \
+ || ((FLAG) == I2C_FLAG_GCALLADDR) || ((FLAG) == I2C_FLAG_TRF) || ((FLAG) == I2C_FLAG_BUSY) \
+ || ((FLAG) == I2C_FLAG_MSMODE) || ((FLAG) == I2C_FLAG_SMBALERT) || ((FLAG) == I2C_FLAG_TIMOUT) \
+ || ((FLAG) == I2C_FLAG_PECERR) || ((FLAG) == I2C_FLAG_OVERRUN) || ((FLAG) == I2C_FLAG_ACKFAIL) \
+ || ((FLAG) == I2C_FLAG_ARLOST) || ((FLAG) == I2C_FLAG_BUSERR) || ((FLAG) == I2C_FLAG_TXDATE) \
+ || ((FLAG) == I2C_FLAG_RXDATNE) || ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADDR10F) \
+ || ((FLAG) == I2C_FLAG_BYTEF) || ((FLAG) == I2C_FLAG_ADDRF) || ((FLAG) == I2C_FLAG_STARTBF))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Events
+ * @{
+ */
+
+/*========================================
+
+ I2C Master Events (Events grouped in order of communication)
+ ==========================================*/
+/**
+ * @brief Communication start
+ *
+ * After sending the START condition (I2C_GenerateStart() function) the master
+ * has to wait for this event. It means that the Start condition has been correctly
+ * released on the I2C bus (the bus is free, no other devices is communicating).
+ *
+ */
+/* Master mode */
+#define I2C_ROLE_MASTER ((uint32_t)0x00010000) /* MSMODE */
+/* --EV5 */
+#define I2C_EVT_MASTER_MODE_FLAG ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
+
+/**
+ * @brief Address Acknowledge
+ *
+ * After checking on EV5 (start condition correctly released on the bus), the
+ * master sends the address of the slave(s) with which it will communicate
+ * (I2C_SendAddr7bit() function, it also determines the direction of the communication:
+ * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
+ * his address. If an acknowledge is sent on the bus, one of the following events will
+ * be set:
+ *
+ * 1) In case of Master Receiver (7-bit addressing): the I2C_EVT_MASTER_RXMODE_FLAG
+ * event is set.
+ *
+ * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVT_MASTER_TXMODE_FLAG
+ * is set
+ *
+ * 3) In case of 10-Bit addressing mode, the master (just after generating the START
+ * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
+ * function). Then master should wait on EV9. It means that the 10-bit addressing
+ * header has been correctly sent on the bus. Then master should send the second part of
+ * the 10-bit address (LSB) using the function I2C_SendAddr7bit(). Then master
+ * should wait for event EV6.
+ *
+ */
+
+/* --EV6 */
+#define I2C_EVT_MASTER_TXMODE_FLAG ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
+#define I2C_EVT_MASTER_RXMODE_FLAG ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
+/* --EV9 */
+#define I2C_EVT_MASTER_MODE_ADDRESS10_FLAG ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
+
+/**
+ * @brief Communication events
+ *
+ * If a communication is established (START condition generated and slave address
+ * acknowledged) then the master has to check on one of the following events for
+ * communication procedures:
+ *
+ * 1) Master Receiver mode: The master has to wait on the event EV7 then to read
+ * the data received from the slave (I2C_RecvData() function).
+ *
+ * 2) Master Transmitter mode: The master has to send data (I2C_SendData()
+ * function) then to wait on event EV8 or EV8_2.
+ * These two events are similar:
+ * - EV8 means that the data has been written in the data register and is
+ * being shifted out.
+ * - EV8_2 means that the data has been physically shifted out and output
+ * on the bus.
+ * In most cases, using EV8 is sufficient for the application.
+ * Using EV8_2 leads to a slower communication but ensure more reliable test.
+ * EV8_2 is also more suitable than EV8 for testing on the last data transmission
+ * (before Stop condition generation).
+ *
+ * @note In case the user software does not guarantee that this event EV7 is
+ * managed before the current byte end of transfer, then user may check on EV7
+ * and BTF flag at the same time (ie. (I2C_EVT_MASTER_DATA_RECVD_FLAG | I2C_FLAG_BYTEF)).
+ * In this case the communication may be slower.
+ *
+ */
+
+/* Master RECEIVER mode -----------------------------*/
+/* --EV7 */
+#define I2C_EVT_MASTER_DATA_RECVD_FLAG ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
+/* EV7x shifter register full */
+#define I2C_EVT_MASTER_SFT_DATA_RECVD_FLAG ((uint32_t)0x00030044) /* BUSY, MSMODE, BSF and RXDATNE flags */
+
+/* Master TRANSMITTER mode --------------------------*/
+/* --EV8 */
+#define I2C_EVT_MASTER_DATA_SENDING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
+/* --EV8_2 */
+#define I2C_EVT_MASTER_DATA_SENDED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
+
+/*========================================
+
+ I2C Slave Events (Events grouped in order of communication)
+ ==========================================*/
+
+/**
+ * @brief Communication start events
+ *
+ * Wait on one of these events at the start of the communication. It means that
+ * the I2C peripheral detected a Start condition on the bus (generated by master
+ * device) followed by the peripheral address. The peripheral generates an ACK
+ * condition on the bus (if the acknowledge feature is enabled through function
+ * I2C_ConfigAck()) and the events listed above are set :
+ *
+ * 1) In normal case (only one address managed by the slave), when the address
+ * sent by the master matches the own address of the peripheral (configured by
+ * OwnAddr1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
+ * (where XXX could be TRANSMITTER or RECEIVER).
+ *
+ * 2) In case the address sent by the master matches the second address of the
+ * peripheral (configured by the function I2C_ConfigOwnAddr2() and enabled
+ * by the function I2C_EnableDualAddr()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
+ * (where XXX could be TRANSMITTER or RECEIVER) are set.
+ *
+ * 3) In case the address sent by the master is General Call (address 0x00) and
+ * if the General Call is enabled for the peripheral (using function I2C_EnableGeneralCall())
+ * the following event is set I2C_EVT_SLAVE_GCALLADDR_MATCHED.
+ *
+ */
+
+/* --EV1 (all the events below are variants of EV1) */
+/* 1) Case of One Single Address managed by the slave */
+#define I2C_EVT_SLAVE_RECV_ADDR_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
+#define I2C_EVT_SLAVE_SEND_ADDR_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
+
+/* 2) Case of Dual address managed by the slave */
+#define I2C_EVT_SLAVE_RECV_ADDR2_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
+#define I2C_EVT_SLAVE_SEND_ADDR2_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
+
+/* 3) Case of General Call enabled for the slave */
+#define I2C_EVT_SLAVE_GCALLADDR_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
+
+/**
+ * @brief Communication events
+ *
+ * Wait on one of these events when EV1 has already been checked and:
+ *
+ * - Slave RECEIVER mode:
+ * - EV2: When the application is expecting a data byte to be received.
+ * - EV4: When the application is expecting the end of the communication: master
+ * sends a stop condition and data transmission is stopped.
+ *
+ * - Slave Transmitter mode:
+ * - EV3: When a byte has been transmitted by the slave and the application is expecting
+ * the end of the byte transmission. The two events I2C_EVT_SLAVE_DATA_SENDED and
+ * I2C_EVT_SLAVE_DATA_SENDING are similar. The second one can optionally be
+ * used when the user software doesn't guarantee the EV3 is managed before the
+ * current byte end of transfer.
+ * - EV3_2: When the master sends a NACK in order to tell slave that data transmission
+ * shall end (before sending the STOP condition). In this case slave has to stop sending
+ * data bytes and expect a Stop condition on the bus.
+ *
+ * @note In case the user software does not guarantee that the event EV2 is
+ * managed before the current byte end of transfer, then user may check on EV2
+ * and BTF flag at the same time (ie. (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_BYTEF)).
+ * In this case the communication may be slower.
+ *
+ */
+
+/* Slave RECEIVER mode --------------------------*/
+/* --EV2 */
+#define I2C_EVT_SLAVE_DATA_RECVD ((uint32_t)0x00020040) /* BUSY and RXNE flags */
+/* --EV2x */
+#define I2C_EVT_SLAVE_DATA_RECVD_NOBUSY ((uint32_t)0x00000040) /* no BUSY and RXDATNE flags */
+/* --EV4 */
+#define I2C_EVT_SLAVE_STOP_RECVD ((uint32_t)0x00000010) /* STOPF flag */
+
+/* Slave TRANSMITTER mode -----------------------*/
+/* --EV3 */
+#define I2C_EVT_SLAVE_DATA_SENDED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
+#define I2C_EVT_SLAVE_DATA_SENDING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
+/* --EV3_2 */
+#define I2C_EVT_SLAVE_ACK_MISS ((uint32_t)0x00000400) /* AF flag */
+
+/*=========================== End of Events Description ==========================================*/
+
+#define IS_I2C_EVT(EVENT) \
+ (((EVENT) == I2C_EVT_SLAVE_SEND_ADDR_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_RECV_ADDR_MATCHED) \
+ || ((EVENT) == I2C_EVT_SLAVE_SEND_ADDR2_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_RECV_ADDR2_MATCHED) \
+ || ((EVENT) == I2C_EVT_SLAVE_GCALLADDR_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_DATA_RECVD) \
+ || ((EVENT) == (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_DUALFLAG)) \
+ || ((EVENT) == (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_GCALLADDR)) || ((EVENT) == I2C_EVT_SLAVE_DATA_SENDED) \
+ || ((EVENT) == (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_DUALFLAG)) \
+ || ((EVENT) == (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_GCALLADDR)) || ((EVENT) == I2C_EVT_SLAVE_STOP_RECVD) \
+ || ((EVENT) == I2C_EVT_MASTER_MODE_FLAG) || ((EVENT) == I2C_EVT_MASTER_TXMODE_FLAG) \
+ || ((EVENT) == I2C_EVT_MASTER_RXMODE_FLAG) || ((EVENT) == I2C_EVT_MASTER_DATA_RECVD_FLAG) \
+ || ((EVENT) == I2C_EVT_MASTER_DATA_SENDED) || ((EVENT) == I2C_EVT_MASTER_DATA_SENDING) \
+ || ((EVENT) == I2C_EVT_MASTER_MODE_ADDRESS10_FLAG) || ((EVENT) == I2C_EVT_SLAVE_ACK_MISS))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_own_address1
+ * @{
+ */
+
+#define IS_I2C_OWN_ADDR1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_clock_speed
+ * @{
+ */
+
+//#define IS_I2C_CLK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
+#define IS_I2C_CLK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 1000000))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Exported_Functions
+ * @{
+ */
+
+void I2C_DeInit(I2C_Module* I2Cx);
+void I2C_Init(I2C_Module* I2Cx, I2C_InitType* I2C_InitStruct);
+void I2C_InitStruct(I2C_InitType* I2C_InitStruct);
+void I2C_Enable(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_EnableDMA(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_EnableDmaLastSend(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_GenerateStart(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_GenerateStop(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_ConfigAck(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_ConfigOwnAddr2(I2C_Module* I2Cx, uint8_t Address);
+void I2C_EnableDualAddr(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_EnableGeneralCall(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_ConfigInt(I2C_Module* I2Cx, uint16_t I2C_IT, FunctionalState Cmd);
+void I2C_SendData(I2C_Module* I2Cx, uint8_t Data);
+uint8_t I2C_RecvData(I2C_Module* I2Cx);
+void I2C_SendAddr7bit(I2C_Module* I2Cx, uint8_t Address, uint8_t I2C_Direction);
+uint16_t I2C_GetRegister(I2C_Module* I2Cx, uint8_t I2C_Register);
+void I2C_EnableSoftwareReset(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_ConfigNackLocation(I2C_Module* I2Cx, uint16_t I2C_NACKPosition);
+void I2C_ConfigSmbusAlert(I2C_Module* I2Cx, uint16_t I2C_SMBusAlert);
+void I2C_SendPEC(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_ConfigPecLocation(I2C_Module* I2Cx, uint16_t I2C_PECPosition);
+void I2C_ComputePec(I2C_Module* I2Cx, FunctionalState Cmd);
+uint8_t I2C_GetPec(I2C_Module* I2Cx);
+void I2C_EnableArp(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_EnableExtendClk(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_ConfigFastModeDutyCycle(I2C_Module* I2Cx, uint16_t FmDutyCycle);
+
+/**
+ * @brief
+ ****************************************************************************************
+ *
+ * I2C State Monitoring Functions
+ *
+ ****************************************************************************************
+ * This I2C driver provides three different ways for I2C state monitoring
+ * depending on the application requirements and constraints:
+ *
+ *
+ * 1) Basic state monitoring:
+ * Using I2C_CheckEvent() function:
+ * It compares the status registers (STS1 and STS2) content to a given event
+ * (can be the combination of one or more flags).
+ * It returns SUCCESS if the current status includes the given flags
+ * and returns ERROR if one or more flags are missing in the current status.
+ * - When to use:
+ * - This function is suitable for most applications as well as for startup
+ * activity since the events are fully described in the product reference manual
+ * (RM0008).
+ * - It is also suitable for users who need to define their own events.
+ * - Limitations:
+ * - If an error occurs (ie. error flags are set besides to the monitored flags),
+ * the I2C_CheckEvent() function may return SUCCESS despite the communication
+ * hold or corrupted real state.
+ * In this case, it is advised to use error interrupts to monitor the error
+ * events and handle them in the interrupt IRQ handler.
+ *
+ * @note
+ * For error management, it is advised to use the following functions:
+ * - I2C_ConfigInt() to configure and enable the error interrupts (I2C_INT_ERR).
+ * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
+ * Where x is the peripheral instance (I2C1, I2C2 ...)
+ * - I2C_GetFlag() or I2C_GetIntStatus() to be called into I2Cx_ER_IRQHandler()
+ * in order to determine which error occurred.
+ * - I2C_ClrFlag() or I2C_ClrIntPendingBit() and/or I2C_EnableSoftwareReset()
+ * and/or I2C_GenerateStop() in order to clear the error flag and source,
+ * and return to correct communication status.
+ *
+ *
+ * 2) Advanced state monitoring:
+ * Using the function I2C_GetLastEvent() which returns the image of both status
+ * registers in a single word (uint32_t) (Status Register 2 value is shifted left
+ * by 16 bits and concatenated to Status Register 1).
+ * - When to use:
+ * - This function is suitable for the same applications above but it allows to
+ * overcome the limitations of I2C_GetFlag() function (see below).
+ * The returned value could be compared to events already defined in the
+ * library (n32wb452_i2c.h) or to custom values defined by user.
+ * - This function is suitable when multiple flags are monitored at the same time.
+ * - At the opposite of I2C_CheckEvent() function, this function allows user to
+ * choose when an event is accepted (when all events flags are set and no
+ * other flags are set or just when the needed flags are set like
+ * I2C_CheckEvent() function).
+ * - Limitations:
+ * - User may need to define his own events.
+ * - Same remark concerning the error management is applicable for this
+ * function if user decides to check only regular communication flags (and
+ * ignores error flags).
+ *
+ *
+ * 3) Flag-based state monitoring:
+ * Using the function I2C_GetFlag() which simply returns the status of
+ * one single flag (ie. I2C_FLAG_RXDATNE ...).
+ * - When to use:
+ * - This function could be used for specific applications or in debug phase.
+ * - It is suitable when only one flag checking is needed (most I2C events
+ * are monitored through multiple flags).
+ * - Limitations:
+ * - When calling this function, the Status register is accessed. Some flags are
+ * cleared when the status register is accessed. So checking the status
+ * of one Flag, may clear other ones.
+ * - Function may need to be called twice or more in order to monitor one
+ * single event.
+ *
+ */
+
+/**
+ *
+ * 1) Basic state monitoring
+ *******************************************************************************
+ */
+ErrorStatus I2C_CheckEvent(I2C_Module* I2Cx, uint32_t I2C_EVENT);
+/**
+ *
+ * 2) Advanced state monitoring
+ *******************************************************************************
+ */
+uint32_t I2C_GetLastEvent(I2C_Module* I2Cx);
+/**
+ *
+ * 3) Flag-based state monitoring
+ *******************************************************************************
+ */
+FlagStatus I2C_GetFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG);
+/**
+ *
+ *******************************************************************************
+ */
+
+void I2C_ClrFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG);
+INTStatus I2C_GetIntStatus(I2C_Module* I2Cx, uint32_t I2C_IT);
+void I2C_ClrIntPendingBit(I2C_Module* I2Cx, uint32_t I2C_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32WB452_I2C_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_iwdg.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_iwdg.h
new file mode 100644
index 0000000000..87d5571d57
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_iwdg.h
@@ -0,0 +1,145 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_iwdg.h
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32WB452_IWDG_H__
+#define __N32WB452_IWDG_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32wb452.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup IWDG
+ * @{
+ */
+
+/** @addtogroup IWDG_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup IWDG_WriteAccess
+ * @{
+ */
+
+#define IWDG_WRITE_ENABLE ((uint16_t)0x5555)
+#define IWDG_WRITE_DISABLE ((uint16_t)0x0000)
+#define IS_IWDG_WRITE(ACCESS) (((ACCESS) == IWDG_WRITE_ENABLE) || ((ACCESS) == IWDG_WRITE_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_prescaler
+ * @{
+ */
+
+#define IWDG_PRESCALER_DIV4 ((uint8_t)0x00)
+#define IWDG_PRESCALER_DIV8 ((uint8_t)0x01)
+#define IWDG_PRESCALER_DIV16 ((uint8_t)0x02)
+#define IWDG_PRESCALER_DIV32 ((uint8_t)0x03)
+#define IWDG_PRESCALER_DIV64 ((uint8_t)0x04)
+#define IWDG_PRESCALER_DIV128 ((uint8_t)0x05)
+#define IWDG_PRESCALER_DIV256 ((uint8_t)0x06)
+#define IS_IWDG_PRESCALER_DIV(PRESCALER) \
+ (((PRESCALER) == IWDG_PRESCALER_DIV4) || ((PRESCALER) == IWDG_PRESCALER_DIV8) \
+ || ((PRESCALER) == IWDG_PRESCALER_DIV16) || ((PRESCALER) == IWDG_PRESCALER_DIV32) \
+ || ((PRESCALER) == IWDG_PRESCALER_DIV64) || ((PRESCALER) == IWDG_PRESCALER_DIV128) \
+ || ((PRESCALER) == IWDG_PRESCALER_DIV256))
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Flag
+ * @{
+ */
+
+#define IWDG_PVU_FLAG ((uint16_t)0x0001)
+#define IWDG_CRVU_FLAG ((uint16_t)0x0002)
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_PVU_FLAG) || ((FLAG) == IWDG_CRVU_FLAG))
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Exported_Functions
+ * @{
+ */
+
+void IWDG_WriteConfig(uint16_t IWDG_WriteAccess);
+void IWDG_SetPrescalerDiv(uint8_t IWDG_Prescaler);
+void IWDG_CntReload(uint16_t Reload);
+void IWDG_ReloadKey(void);
+void IWDG_Enable(void);
+FlagStatus IWDG_GetStatus(uint16_t IWDG_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32WB452_IWDG_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_pwr.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_pwr.h
new file mode 100644
index 0000000000..0e8641dfde
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_pwr.h
@@ -0,0 +1,179 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_pwr.h
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32WB452_PWR_H__
+#define __N32WB452_PWR_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32wb452.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup PWR
+ * @{
+ */
+
+/** @addtogroup PWR_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup PVD_detection_level
+ * @{
+ */
+
+#define PWR_PVDRANGRE_2V2 ((uint32_t)0x00000000)
+#define PWR_PVDRANGRE_2V3 ((uint32_t)0x00000020)
+#define PWR_PVDRANGRE_2V4 ((uint32_t)0x00000040)
+#define PWR_PVDRANGRE_2V5 ((uint32_t)0x00000060)
+#define PWR_PVDRANGRE_2V6 ((uint32_t)0x00000080)
+#define PWR_PVDRANGRE_2V7 ((uint32_t)0x000000A0)
+#define PWR_PVDRANGRE_2V8 ((uint32_t)0x000000C0)
+#define PWR_PVDRANGRE_2V9 ((uint32_t)0x000000E0)
+
+#define PWR_PVDRANGE_1V78 ((uint32_t)0x00000200)
+#define PWR_PVDRANGE_1V88 ((uint32_t)0x00000220)
+#define PWR_PVDRANGE_1V98 ((uint32_t)0x00000240)
+#define PWR_PVDRANGE_2V08 ((uint32_t)0x00000260)
+#define PWR_PVDRANGE_3V06 ((uint32_t)0x00000280)
+#define PWR_PVDRANGE_3V24 ((uint32_t)0x000002A0)
+#define PWR_PVDRANGE_3V42 ((uint32_t)0x000002C0)
+#define PWR_PVDRANGE_3V60 ((uint32_t)0x000002E0)
+#define IS_PWR_PVD_LEVEL(LEVEL) \
+ (((LEVEL) == PWR_PVDRANGRE_2V2) || ((LEVEL) == PWR_PVDRANGRE_2V3) || ((LEVEL) == PWR_PVDRANGRE_2V4) \
+ || ((LEVEL) == PWR_PVDRANGRE_2V5) || ((LEVEL) == PWR_PVDRANGRE_2V6) || ((LEVEL) == PWR_PVDRANGRE_2V7) \
+ || ((LEVEL) == PWR_PVDRANGRE_2V8) || ((LEVEL) == PWR_PVDRANGRE_2V9) || ((LEVEL) == PWR_PVDRANGE_1V78) \
+ || ((LEVEL) == PWR_PVDRANGE_1V88) || ((LEVEL) == PWR_PVDRANGE_1V98) || ((LEVEL) == PWR_PVDRANGE_2V08) \
+ || ((LEVEL) == PWR_PVDRANGE_3V06) || ((LEVEL) == PWR_PVDRANGE_3V24) || ((LEVEL) == PWR_PVDRANGE_3V42) \
+ || ((LEVEL) == PWR_PVDRANGE_3V60))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Regulator_state_is_STOP_mode
+ * @{
+ */
+
+#define PWR_REGULATOR_ON ((uint32_t)0x00000000)
+#define PWR_REGULATOR_LOWPOWER ((uint32_t)0x00000001)
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_REGULATOR_ON) || ((REGULATOR) == PWR_REGULATOR_LOWPOWER))
+/**
+ * @}
+ */
+
+/** @addtogroup STOP_mode_entry
+ * @{
+ */
+
+#define PWR_STOPENTRY_WFI ((uint8_t)0x01)
+#define PWR_STOPENTRY_WFE ((uint8_t)0x02)
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Flag
+ * @{
+ */
+
+#define PWR_WU_FLAG ((uint32_t)0x00000001)
+#define PWR_SB_FLAG ((uint32_t)0x00000002)
+#define PWR_PVDO_FLAG ((uint32_t)0x00000004)
+#define PWR_VBATF_FLAG ((uint32_t)0x00000008)
+#define IS_PWR_GET_FLAG(FLAG) \
+ (((FLAG) == PWR_WU_FLAG) || ((FLAG) == PWR_SB_FLAG) || ((FLAG) == PWR_PVDO_FLAG) || ((FLAG) == PWR_VBATF_FLAG))
+
+#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_WU_FLAG) || ((FLAG) == PWR_SB_FLAG) || ((FLAG) == PWR_VBATF_FLAG))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Exported_Functions
+ * @{
+ */
+
+void PWR_DeInit(void);
+void PWR_BackupAccessEnable(FunctionalState Cmd);
+void PWR_PvdEnable(FunctionalState Cmd);
+void PWR_PvdRangeConfig(uint32_t PWR_PVDLevel);
+void PWR_WakeUpPinEnable(FunctionalState Cmd);
+void PWR_EnterStopState(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+void PWR_EnterSLEEPMode(uint8_t SLEEPONEXIT, uint8_t PWR_STOPEntry);
+void PWR_EnterSTOP2Mode(uint8_t PWR_STOPEntry);
+void PWR_EnterStandbyState(void);
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
+void PWR_ClearFlag(uint32_t PWR_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32WB452_PWR_H__ */
+ /**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_rcc.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_rcc.h
new file mode 100644
index 0000000000..5ef241884e
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_rcc.h
@@ -0,0 +1,718 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_rcc.h
+ * @author Nations
+ * @version v1.0.3
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32WB452_RCC_H__
+#define __N32WB452_RCC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32wb452.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RCC
+ * @{
+ */
+
+/** @addtogroup RCC_Exported_Types
+ * @{
+ */
+
+typedef struct
+{
+ uint32_t SysclkFreq; /*!< returns SYSCLK clock frequency expressed in Hz */
+ uint32_t HclkFreq; /*!< returns HCLK clock frequency expressed in Hz */
+ uint32_t Pclk1Freq; /*!< returns PCLK1 clock frequency expressed in Hz */
+ uint32_t Pclk2Freq; /*!< returns PCLK2 clock frequency expressed in Hz */
+ uint32_t AdcPllClkFreq; /*!< returns ADCPLLCLK clock frequency expressed in Hz */
+ uint32_t AdcHclkFreq; /*!< returns ADCHCLK clock frequency expressed in Hz */
+} RCC_ClocksType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup HSE_configuration
+ * @{
+ */
+
+#define RCC_HSE_DISABLE ((uint32_t)0x00000000)
+#define RCC_HSE_ENABLE ((uint32_t)0x00010000)
+#define RCC_HSE_BYPASS ((uint32_t)0x00040000)
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_DISABLE) || ((HSE) == RCC_HSE_ENABLE) || ((HSE) == RCC_HSE_BYPASS))
+
+/**
+ * @}
+ */
+
+/** @addtogroup PLL_entry_clock_source
+ * @{
+ */
+
+#define RCC_PLL_SRC_HSI_DIV2 ((uint32_t)0x00000000)
+
+#define RCC_PLL_SRC_HSE_DIV1 ((uint32_t)0x00010000)
+#define RCC_PLL_SRC_HSE_DIV2 ((uint32_t)0x00030000)
+#define IS_RCC_PLL_SRC(SOURCE) \
+ (((SOURCE) == RCC_PLL_SRC_HSI_DIV2) || ((SOURCE) == RCC_PLL_SRC_HSE_DIV1) || ((SOURCE) == RCC_PLL_SRC_HSE_DIV2))
+
+/**
+ * @}
+ */
+
+/** @addtogroup PLL_multiplication_factor
+ * @{
+ */
+#define RCC_PLL_MUL_2 ((uint32_t)0x00000000)
+#define RCC_PLL_MUL_3 ((uint32_t)0x00040000)
+#define RCC_PLL_MUL_4 ((uint32_t)0x00080000)
+#define RCC_PLL_MUL_5 ((uint32_t)0x000C0000)
+#define RCC_PLL_MUL_6 ((uint32_t)0x00100000)
+#define RCC_PLL_MUL_7 ((uint32_t)0x00140000)
+#define RCC_PLL_MUL_8 ((uint32_t)0x00180000)
+#define RCC_PLL_MUL_9 ((uint32_t)0x001C0000)
+#define RCC_PLL_MUL_10 ((uint32_t)0x00200000)
+#define RCC_PLL_MUL_11 ((uint32_t)0x00240000)
+#define RCC_PLL_MUL_12 ((uint32_t)0x00280000)
+#define RCC_PLL_MUL_13 ((uint32_t)0x002C0000)
+#define RCC_PLL_MUL_14 ((uint32_t)0x00300000)
+#define RCC_PLL_MUL_15 ((uint32_t)0x00340000)
+#define RCC_PLL_MUL_16 ((uint32_t)0x00380000)
+#define RCC_PLL_MUL_17 ((uint32_t)0x08000000)
+#define RCC_PLL_MUL_18 ((uint32_t)0x08040000)
+#define RCC_PLL_MUL_19 ((uint32_t)0x08080000)
+#define RCC_PLL_MUL_20 ((uint32_t)0x080C0000)
+#define RCC_PLL_MUL_21 ((uint32_t)0x08100000)
+#define RCC_PLL_MUL_22 ((uint32_t)0x08140000)
+#define RCC_PLL_MUL_23 ((uint32_t)0x08180000)
+#define RCC_PLL_MUL_24 ((uint32_t)0x081C0000)
+#define RCC_PLL_MUL_25 ((uint32_t)0x08200000)
+#define RCC_PLL_MUL_26 ((uint32_t)0x08240000)
+#define RCC_PLL_MUL_27 ((uint32_t)0x08280000)
+#define RCC_PLL_MUL_28 ((uint32_t)0x082C0000)
+#define RCC_PLL_MUL_29 ((uint32_t)0x08300000)
+#define RCC_PLL_MUL_30 ((uint32_t)0x08340000)
+#define RCC_PLL_MUL_31 ((uint32_t)0x08380000)
+#define RCC_PLL_MUL_32 ((uint32_t)0x083C0000)
+#define IS_RCC_PLL_MUL(MUL) \
+ (((MUL) == RCC_PLL_MUL_2) || ((MUL) == RCC_PLL_MUL_3) || ((MUL) == RCC_PLL_MUL_4) || ((MUL) == RCC_PLL_MUL_5) \
+ || ((MUL) == RCC_PLL_MUL_6) || ((MUL) == RCC_PLL_MUL_7) || ((MUL) == RCC_PLL_MUL_8) || ((MUL) == RCC_PLL_MUL_9) \
+ || ((MUL) == RCC_PLL_MUL_10) || ((MUL) == RCC_PLL_MUL_11) || ((MUL) == RCC_PLL_MUL_12) \
+ || ((MUL) == RCC_PLL_MUL_13) || ((MUL) == RCC_PLL_MUL_14) || ((MUL) == RCC_PLL_MUL_15) \
+ || ((MUL) == RCC_PLL_MUL_16) || ((MUL) == RCC_PLL_MUL_17) || ((MUL) == RCC_PLL_MUL_18) \
+ || ((MUL) == RCC_PLL_MUL_19) || ((MUL) == RCC_PLL_MUL_20) || ((MUL) == RCC_PLL_MUL_21) \
+ || ((MUL) == RCC_PLL_MUL_22) || ((MUL) == RCC_PLL_MUL_23) || ((MUL) == RCC_PLL_MUL_24) \
+ || ((MUL) == RCC_PLL_MUL_25) || ((MUL) == RCC_PLL_MUL_26) || ((MUL) == RCC_PLL_MUL_27) \
+ || ((MUL) == RCC_PLL_MUL_28) || ((MUL) == RCC_PLL_MUL_29) || ((MUL) == RCC_PLL_MUL_30) \
+ || ((MUL) == RCC_PLL_MUL_31) || ((MUL) == RCC_PLL_MUL_32))
+
+/**
+ * @}
+ */
+
+/** @addtogroup System_clock_source
+ * @{
+ */
+
+#define RCC_SYSCLK_SRC_HSI ((uint32_t)0x00000000)
+#define RCC_SYSCLK_SRC_HSE ((uint32_t)0x00000001)
+#define RCC_SYSCLK_SRC_PLLCLK ((uint32_t)0x00000002)
+#define IS_RCC_SYSCLK_SRC(SOURCE) \
+ (((SOURCE) == RCC_SYSCLK_SRC_HSI) || ((SOURCE) == RCC_SYSCLK_SRC_HSE) || ((SOURCE) == RCC_SYSCLK_SRC_PLLCLK))
+/**
+ * @}
+ */
+
+/** @addtogroup AHB_clock_source
+ * @{
+ */
+
+#define RCC_SYSCLK_DIV1 ((uint32_t)0x00000000)
+#define RCC_SYSCLK_DIV2 ((uint32_t)0x00000080)
+#define RCC_SYSCLK_DIV4 ((uint32_t)0x00000090)
+#define RCC_SYSCLK_DIV8 ((uint32_t)0x000000A0)
+#define RCC_SYSCLK_DIV16 ((uint32_t)0x000000B0)
+#define RCC_SYSCLK_DIV64 ((uint32_t)0x000000C0)
+#define RCC_SYSCLK_DIV128 ((uint32_t)0x000000D0)
+#define RCC_SYSCLK_DIV256 ((uint32_t)0x000000E0)
+#define RCC_SYSCLK_DIV512 ((uint32_t)0x000000F0)
+#define IS_RCC_SYSCLK_DIV(HCLK) \
+ (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || ((HCLK) == RCC_SYSCLK_DIV4) \
+ || ((HCLK) == RCC_SYSCLK_DIV8) || ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) \
+ || ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || ((HCLK) == RCC_SYSCLK_DIV512))
+/**
+ * @}
+ */
+
+/** @addtogroup APB1_APB2_clock_source
+ * @{
+ */
+
+#define RCC_HCLK_DIV1 ((uint32_t)0x00000000)
+#define RCC_HCLK_DIV2 ((uint32_t)0x00000400)
+#define RCC_HCLK_DIV4 ((uint32_t)0x00000500)
+#define RCC_HCLK_DIV8 ((uint32_t)0x00000600)
+#define RCC_HCLK_DIV16 ((uint32_t)0x00000700)
+#define IS_RCC_HCLK_DIV(PCLK) \
+ (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) \
+ || ((PCLK) == RCC_HCLK_DIV16))
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Interrupt_source
+ * @{
+ */
+
+#define RCC_INT_LSIRDIF ((uint8_t)0x01)
+#define RCC_INT_LSERDIF ((uint8_t)0x02)
+#define RCC_INT_HSIRDIF ((uint8_t)0x04)
+#define RCC_INT_HSERDIF ((uint8_t)0x08)
+#define RCC_INT_PLLRDIF ((uint8_t)0x10)
+#define RCC_INT_CLKSSIF ((uint8_t)0x80)
+
+#define IS_RCC_INT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00))
+#define IS_RCC_GET_INT(IT) \
+ (((IT) == RCC_INT_LSIRDIF) || ((IT) == RCC_INT_LSERDIF) || ((IT) == RCC_INT_HSIRDIF) || ((IT) == RCC_INT_HSERDIF) \
+ || ((IT) == RCC_INT_PLLRDIF) || ((IT) == RCC_INT_CLKSSIF))
+#define IS_RCC_CLR_INT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @addtogroup USB_Device_clock_source
+ * @{
+ */
+
+#define RCC_USBCLK_SRC_PLLCLK_DIV1_5 ((uint8_t)0x00)
+#define RCC_USBCLK_SRC_PLLCLK_DIV1 ((uint8_t)0x01)
+#define RCC_USBCLK_SRC_PLLCLK_DIV2 ((uint8_t)0x02)
+#define RCC_USBCLK_SRC_PLLCLK_DIV3 ((uint8_t)0x03)
+
+#define IS_RCC_USBCLK_SRC(SOURCE) \
+ (((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV1_5) || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV1) \
+ || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV2) || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV3))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_clock_source
+ * @{
+ */
+
+#define RCC_PCLK2_DIV2 ((uint32_t)0x00000000)
+#define RCC_PCLK2_DIV4 ((uint32_t)0x00004000)
+#define RCC_PCLK2_DIV6 ((uint32_t)0x00008000)
+#define RCC_PCLK2_DIV8 ((uint32_t)0x0000C000)
+#define IS_RCC_PCLK2_DIV(ADCCLK) \
+ (((ADCCLK) == RCC_PCLK2_DIV2) || ((ADCCLK) == RCC_PCLK2_DIV4) || ((ADCCLK) == RCC_PCLK2_DIV6) \
+ || ((ADCCLK) == RCC_PCLK2_DIV8))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_CFGR2_Config
+ * @{
+ */
+#define RCC_TIM18CLK_SRC_TIM18CLK ((uint32_t)0x00000000)
+#define RCC_TIM18CLK_SRC_SYSCLK ((uint32_t)0x20000000)
+#define IS_RCC_TIM18CLKSRC(TIM18CLK) \
+ (((TIM18CLK) == RCC_TIM18CLK_SRC_TIM18CLK) || ((TIM18CLK) == RCC_TIM18CLK_SRC_SYSCLK))
+
+#define RCC_RNGCCLK_SYSCLK_DIV1 ((uint32_t)0x00000000)
+#define RCC_RNGCCLK_SYSCLK_DIV2 ((uint32_t)0x01000000)
+#define RCC_RNGCCLK_SYSCLK_DIV3 ((uint32_t)0x02000000)
+#define RCC_RNGCCLK_SYSCLK_DIV4 ((uint32_t)0x03000000)
+#define RCC_RNGCCLK_SYSCLK_DIV5 ((uint32_t)0x04000000)
+#define RCC_RNGCCLK_SYSCLK_DIV6 ((uint32_t)0x05000000)
+#define RCC_RNGCCLK_SYSCLK_DIV7 ((uint32_t)0x06000000)
+#define RCC_RNGCCLK_SYSCLK_DIV8 ((uint32_t)0x07000000)
+#define RCC_RNGCCLK_SYSCLK_DIV9 ((uint32_t)0x08000000)
+#define RCC_RNGCCLK_SYSCLK_DIV10 ((uint32_t)0x09000000)
+#define RCC_RNGCCLK_SYSCLK_DIV11 ((uint32_t)0x0A000000)
+#define RCC_RNGCCLK_SYSCLK_DIV12 ((uint32_t)0x0B000000)
+#define RCC_RNGCCLK_SYSCLK_DIV13 ((uint32_t)0x0C000000)
+#define RCC_RNGCCLK_SYSCLK_DIV14 ((uint32_t)0x0D000000)
+#define RCC_RNGCCLK_SYSCLK_DIV15 ((uint32_t)0x0E000000)
+#define RCC_RNGCCLK_SYSCLK_DIV16 ((uint32_t)0x0F000000)
+#define RCC_RNGCCLK_SYSCLK_DIV17 ((uint32_t)0x10000000)
+#define RCC_RNGCCLK_SYSCLK_DIV18 ((uint32_t)0x11000000)
+#define RCC_RNGCCLK_SYSCLK_DIV19 ((uint32_t)0x12000000)
+#define RCC_RNGCCLK_SYSCLK_DIV20 ((uint32_t)0x13000000)
+#define RCC_RNGCCLK_SYSCLK_DIV21 ((uint32_t)0x14000000)
+#define RCC_RNGCCLK_SYSCLK_DIV22 ((uint32_t)0x15000000)
+#define RCC_RNGCCLK_SYSCLK_DIV23 ((uint32_t)0x16000000)
+#define RCC_RNGCCLK_SYSCLK_DIV24 ((uint32_t)0x17000000)
+#define RCC_RNGCCLK_SYSCLK_DIV25 ((uint32_t)0x18000000)
+#define RCC_RNGCCLK_SYSCLK_DIV26 ((uint32_t)0x19000000)
+#define RCC_RNGCCLK_SYSCLK_DIV27 ((uint32_t)0x1A000000)
+#define RCC_RNGCCLK_SYSCLK_DIV28 ((uint32_t)0x1B000000)
+#define RCC_RNGCCLK_SYSCLK_DIV29 ((uint32_t)0x1C000000)
+#define RCC_RNGCCLK_SYSCLK_DIV30 ((uint32_t)0x1D000000)
+#define RCC_RNGCCLK_SYSCLK_DIV31 ((uint32_t)0x1E000000)
+#define RCC_RNGCCLK_SYSCLK_DIV32 ((uint32_t)0x1F000000)
+#define IS_RCC_RNGCCLKPRE(DIV) \
+ (((DIV) == RCC_RNGCCLK_SYSCLK_DIV1) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV2) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV3) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV4) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV5) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV6) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV7) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV8) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV9) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV10) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV11) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV12) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV13) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV14) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV15) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV16) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV17) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV18) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV19) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV20) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV21) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV22) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV23) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV24) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV25) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV26) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV27) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV28) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV29) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV30) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV31) \
+ || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV32))
+
+#define RCC_ADC1MCLK_SRC_HSI ((uint32_t)0x00000000)
+#define RCC_ADC1MCLK_SRC_HSE ((uint32_t)0x00000400)
+#define IS_RCC_ADC1MCLKSRC(ADC1MCLK) (((ADC1MCLK) == RCC_ADC1MCLK_SRC_HSI) || ((ADC1MCLK) == RCC_ADC1MCLK_SRC_HSE))
+
+#define RCC_ADC1MCLK_DIV1 ((uint32_t)0x00000000)
+#define RCC_ADC1MCLK_DIV2 ((uint32_t)0x00000800)
+#define RCC_ADC1MCLK_DIV3 ((uint32_t)0x00001000)
+#define RCC_ADC1MCLK_DIV4 ((uint32_t)0x00001800)
+#define RCC_ADC1MCLK_DIV5 ((uint32_t)0x00002000)
+#define RCC_ADC1MCLK_DIV6 ((uint32_t)0x00002800)
+#define RCC_ADC1MCLK_DIV7 ((uint32_t)0x00003000)
+#define RCC_ADC1MCLK_DIV8 ((uint32_t)0x00003800)
+#define RCC_ADC1MCLK_DIV9 ((uint32_t)0x00004000)
+#define RCC_ADC1MCLK_DIV10 ((uint32_t)0x00004800)
+#define RCC_ADC1MCLK_DIV11 ((uint32_t)0x00005000)
+#define RCC_ADC1MCLK_DIV12 ((uint32_t)0x00005800)
+#define RCC_ADC1MCLK_DIV13 ((uint32_t)0x00006000)
+#define RCC_ADC1MCLK_DIV14 ((uint32_t)0x00006800)
+#define RCC_ADC1MCLK_DIV15 ((uint32_t)0x00007000)
+#define RCC_ADC1MCLK_DIV16 ((uint32_t)0x00007800)
+#define RCC_ADC1MCLK_DIV17 ((uint32_t)0x00008000)
+#define RCC_ADC1MCLK_DIV18 ((uint32_t)0x00008800)
+#define RCC_ADC1MCLK_DIV19 ((uint32_t)0x00009000)
+#define RCC_ADC1MCLK_DIV20 ((uint32_t)0x00009800)
+#define RCC_ADC1MCLK_DIV21 ((uint32_t)0x0000A000)
+#define RCC_ADC1MCLK_DIV22 ((uint32_t)0x0000A800)
+#define RCC_ADC1MCLK_DIV23 ((uint32_t)0x0000B000)
+#define RCC_ADC1MCLK_DIV24 ((uint32_t)0x0000B800)
+#define RCC_ADC1MCLK_DIV25 ((uint32_t)0x0000C000)
+#define RCC_ADC1MCLK_DIV26 ((uint32_t)0x0000C800)
+#define RCC_ADC1MCLK_DIV27 ((uint32_t)0x0000D000)
+#define RCC_ADC1MCLK_DIV28 ((uint32_t)0x0000D800)
+#define RCC_ADC1MCLK_DIV29 ((uint32_t)0x0000E000)
+#define RCC_ADC1MCLK_DIV30 ((uint32_t)0x0000E800)
+#define RCC_ADC1MCLK_DIV31 ((uint32_t)0x0000F000)
+#define RCC_ADC1MCLK_DIV32 ((uint32_t)0x0000F800)
+#define IS_RCC_ADC1MCLKPRE(DIV) \
+ (((DIV) == RCC_ADC1MCLK_DIV1) || ((DIV) == RCC_ADC1MCLK_DIV2) || ((DIV) == RCC_ADC1MCLK_DIV3) \
+ || ((DIV) == RCC_ADC1MCLK_DIV4) || ((DIV) == RCC_ADC1MCLK_DIV5) || ((DIV) == RCC_ADC1MCLK_DIV6) \
+ || ((DIV) == RCC_ADC1MCLK_DIV7) || ((DIV) == RCC_ADC1MCLK_DIV8) || ((DIV) == RCC_ADC1MCLK_DIV9) \
+ || ((DIV) == RCC_ADC1MCLK_DIV10) || ((DIV) == RCC_ADC1MCLK_DIV11) || ((DIV) == RCC_ADC1MCLK_DIV12) \
+ || ((DIV) == RCC_ADC1MCLK_DIV13) || ((DIV) == RCC_ADC1MCLK_DIV14) || ((DIV) == RCC_ADC1MCLK_DIV15) \
+ || ((DIV) == RCC_ADC1MCLK_DIV16) || ((DIV) == RCC_ADC1MCLK_DIV17) || ((DIV) == RCC_ADC1MCLK_DIV18) \
+ || ((DIV) == RCC_ADC1MCLK_DIV19) || ((DIV) == RCC_ADC1MCLK_DIV20) || ((DIV) == RCC_ADC1MCLK_DIV21) \
+ || ((DIV) == RCC_ADC1MCLK_DIV22) || ((DIV) == RCC_ADC1MCLK_DIV23) || ((DIV) == RCC_ADC1MCLK_DIV24) \
+ || ((DIV) == RCC_ADC1MCLK_DIV25) || ((DIV) == RCC_ADC1MCLK_DIV26) || ((DIV) == RCC_ADC1MCLK_DIV27) \
+ || ((DIV) == RCC_ADC1MCLK_DIV28) || ((DIV) == RCC_ADC1MCLK_DIV29) || ((DIV) == RCC_ADC1MCLK_DIV30) \
+ || ((DIV) == RCC_ADC1MCLK_DIV31) || ((DIV) == RCC_ADC1MCLK_DIV32))
+
+#define RCC_ADCPLLCLK_DISABLE ((uint32_t)0xFFFFFEFF)
+#define RCC_ADCPLLCLK_DIV1 ((uint32_t)0x00000100)
+#define RCC_ADCPLLCLK_DIV2 ((uint32_t)0x00000110)
+#define RCC_ADCPLLCLK_DIV4 ((uint32_t)0x00000120)
+#define RCC_ADCPLLCLK_DIV6 ((uint32_t)0x00000130)
+#define RCC_ADCPLLCLK_DIV8 ((uint32_t)0x00000140)
+#define RCC_ADCPLLCLK_DIV10 ((uint32_t)0x00000150)
+#define RCC_ADCPLLCLK_DIV12 ((uint32_t)0x00000160)
+#define RCC_ADCPLLCLK_DIV16 ((uint32_t)0x00000170)
+#define RCC_ADCPLLCLK_DIV32 ((uint32_t)0x00000180)
+#define RCC_ADCPLLCLK_DIV64 ((uint32_t)0x00000190)
+#define RCC_ADCPLLCLK_DIV128 ((uint32_t)0x000001A0)
+#define RCC_ADCPLLCLK_DIV256 ((uint32_t)0x000001B0)
+#define RCC_ADCPLLCLK_DIV_OTHERS ((uint32_t)0x000001C0)
+#define IS_RCC_ADCPLLCLKPRE(DIV) \
+ (((DIV) == RCC_ADCPLLCLK_DIV1) || ((DIV) == RCC_ADCPLLCLK_DIV2) || ((DIV) == RCC_ADCPLLCLK_DIV4) \
+ || ((DIV) == RCC_ADCPLLCLK_DIV6) || ((DIV) == RCC_ADCPLLCLK_DIV8) || ((DIV) == RCC_ADCPLLCLK_DIV10) \
+ || ((DIV) == RCC_ADCPLLCLK_DIV12) || ((DIV) == RCC_ADCPLLCLK_DIV16) || ((DIV) == RCC_ADCPLLCLK_DIV32) \
+ || ((DIV) == RCC_ADCPLLCLK_DIV64) || ((DIV) == RCC_ADCPLLCLK_DIV128) || ((DIV) == RCC_ADCPLLCLK_DIV256) \
+ || ((DIV) == RCC_ADC1MCLK_DIV15) || ((DIV) == RCC_ADCPLLCLK_DIV16) \
+ || (((DIV)&RCC_ADCPLLCLK_DIV_OTHERS) == 0x000001C0))
+
+#define RCC_ADCHCLK_DIV1 ((uint32_t)0x00000000)
+#define RCC_ADCHCLK_DIV2 ((uint32_t)0x00000001)
+#define RCC_ADCHCLK_DIV4 ((uint32_t)0x00000002)
+#define RCC_ADCHCLK_DIV6 ((uint32_t)0x00000003)
+#define RCC_ADCHCLK_DIV8 ((uint32_t)0x00000004)
+#define RCC_ADCHCLK_DIV10 ((uint32_t)0x00000005)
+#define RCC_ADCHCLK_DIV12 ((uint32_t)0x00000006)
+#define RCC_ADCHCLK_DIV16 ((uint32_t)0x00000007)
+#define RCC_ADCHCLK_DIV32 ((uint32_t)0x00000008)
+#define RCC_ADCHCLK_DIV_OTHERS ((uint32_t)0x00000008)
+#define IS_RCC_ADCHCLKPRE(DIV) \
+ (((DIV) == RCC_ADCHCLK_DIV1) || ((DIV) == RCC_ADCHCLK_DIV2) || ((DIV) == RCC_ADCHCLK_DIV4) \
+ || ((DIV) == RCC_ADCHCLK_DIV6) || ((DIV) == RCC_ADCHCLK_DIV8) || ((DIV) == RCC_ADCHCLK_DIV10) \
+ || ((DIV) == RCC_ADCHCLK_DIV12) || ((DIV) == RCC_ADCHCLK_DIV16) || ((DIV) == RCC_ADCHCLK_DIV32) \
+ || (((DIV)&RCC_ADCHCLK_DIV_OTHERS) != 0x00))
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_CFGR3_Config
+ * @{
+ */
+#define RCC_BOR_RST_ENABLE ((uint32_t)0x00000040)
+
+#define RCC_TRNG1MCLK_ENABLE ((uint32_t)0x00040000)
+#define RCC_TRNG1MCLK_DISABLE ((uint32_t)0xFFFBFFFF)
+
+#define RCC_TRNG1MCLK_SRC_HSI ((uint32_t)0x00000000)
+#define RCC_TRNG1MCLK_SRC_HSE ((uint32_t)0x00020000)
+#define IS_RCC_TRNG1MCLK_SRC(TRNG1MCLK) \
+ (((TRNG1MCLK) == RCC_TRNG1MCLK_SRC_HSI) || ((TRNG1MCLK) == RCC_TRNG1MCLK_SRC_HSE))
+
+#define RCC_TRNG1MCLK_DIV2 ((uint32_t)0x00000800)
+#define RCC_TRNG1MCLK_DIV4 ((uint32_t)0x00001800)
+#define RCC_TRNG1MCLK_DIV6 ((uint32_t)0x00002800)
+#define RCC_TRNG1MCLK_DIV8 ((uint32_t)0x00003800)
+#define RCC_TRNG1MCLK_DIV10 ((uint32_t)0x00004800)
+#define RCC_TRNG1MCLK_DIV12 ((uint32_t)0x00005800)
+#define RCC_TRNG1MCLK_DIV14 ((uint32_t)0x00006800)
+#define RCC_TRNG1MCLK_DIV16 ((uint32_t)0x00007800)
+#define RCC_TRNG1MCLK_DIV18 ((uint32_t)0x00008800)
+#define RCC_TRNG1MCLK_DIV20 ((uint32_t)0x00009800)
+#define RCC_TRNG1MCLK_DIV22 ((uint32_t)0x0000A800)
+#define RCC_TRNG1MCLK_DIV24 ((uint32_t)0x0000B800)
+#define RCC_TRNG1MCLK_DIV26 ((uint32_t)0x0000C800)
+#define RCC_TRNG1MCLK_DIV28 ((uint32_t)0x0000D800)
+#define RCC_TRNG1MCLK_DIV30 ((uint32_t)0x0000E800)
+#define RCC_TRNG1MCLK_DIV32 ((uint32_t)0x0000F800)
+#define IS_RCC_TRNG1MCLKPRE(VAL) \
+ (((VAL) == RCC_TRNG1MCLK_DIV2) || ((VAL) == RCC_TRNG1MCLK_DIV4) || ((VAL) == RCC_TRNG1MCLK_DIV6) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV8) || ((VAL) == RCC_TRNG1MCLK_DIV10) || ((VAL) == RCC_TRNG1MCLK_DIV12) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV14) || ((VAL) == RCC_TRNG1MCLK_DIV16) || ((VAL) == RCC_TRNG1MCLK_DIV18) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV20) || ((VAL) == RCC_TRNG1MCLK_DIV22) || ((VAL) == RCC_TRNG1MCLK_DIV24) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV26) || ((VAL) == RCC_TRNG1MCLK_DIV28) || ((VAL) == RCC_TRNG1MCLK_DIV30) \
+ || ((VAL) == RCC_TRNG1MCLK_DIV32))
+
+/**
+ * @}
+ */
+
+/** @addtogroup LSE_configuration
+ * @{
+ */
+
+#define RCC_LSE_DISABLE ((uint8_t)0x00)
+#define RCC_LSE_ENABLE ((uint8_t)0x01)
+#define RCC_LSE_BYPASS ((uint8_t)0x04)
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_DISABLE) || ((LSE) == RCC_LSE_ENABLE) || ((LSE) == RCC_LSE_BYPASS))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_clock_source
+ * @{
+ */
+
+#define RCC_RTCCLK_SRC_LSE ((uint32_t)0x00000100)
+#define RCC_RTCCLK_SRC_LSI ((uint32_t)0x00000200)
+#define RCC_RTCCLK_SRC_HSE_DIV128 ((uint32_t)0x00000300)
+#define IS_RCC_RTCCLK_SRC(SOURCE) \
+ (((SOURCE) == RCC_RTCCLK_SRC_LSE) || ((SOURCE) == RCC_RTCCLK_SRC_LSI) || ((SOURCE) == RCC_RTCCLK_SRC_HSE_DIV128))
+/**
+ * @}
+ */
+
+/** @addtogroup AHB_peripheral
+ * @{
+ */
+
+#define RCC_AHB_PERIPH_DMA1 ((uint32_t)0x00000001)
+#define RCC_AHB_PERIPH_DMA2 ((uint32_t)0x00000002)
+#define RCC_AHB_PERIPH_SRAM ((uint32_t)0x00000004)
+#define RCC_AHB_PERIPH_FLITF ((uint32_t)0x00000010)
+#define RCC_AHB_PERIPH_CRC ((uint32_t)0x00000040)
+#define RCC_AHB_PERIPH_RNGC ((uint32_t)0x00000200)
+#define RCC_AHB_PERIPH_SDIO ((uint32_t)0x00000400)
+#define RCC_AHB_PERIPH_SAC ((uint32_t)0x00000800)
+#define RCC_AHB_PERIPH_ADC1 ((uint32_t)0x00001000)
+#define RCC_AHB_PERIPH_ADC2 ((uint32_t)0x00002000)
+#define RCC_AHB_PERIPH_QSPI ((uint32_t)0x00020000)
+
+#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH)&0xFFFC02A8) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @addtogroup APB2_peripheral
+ * @{
+ */
+
+#define RCC_APB2_PERIPH_AFIO ((uint32_t)0x00000001)
+#define RCC_APB2_PERIPH_GPIOA ((uint32_t)0x00000004)
+#define RCC_APB2_PERIPH_GPIOB ((uint32_t)0x00000008)
+#define RCC_APB2_PERIPH_GPIOC ((uint32_t)0x00000010)
+#define RCC_APB2_PERIPH_GPIOD ((uint32_t)0x00000020)
+#define RCC_APB2_PERIPH_GPIOE ((uint32_t)0x00000040)
+#define RCC_APB2_PERIPH_TIM1 ((uint32_t)0x00000800)
+#define RCC_APB2_PERIPH_SPI1 ((uint32_t)0x00001000)
+#define RCC_APB2_PERIPH_TIM8 ((uint32_t)0x00002000)
+#define RCC_APB2_PERIPH_USART1 ((uint32_t)0x00004000)
+#define RCC_APB2_PERIPH_DVP ((uint32_t)0x00010000)
+#define RCC_APB2_PERIPH_UART6 ((uint32_t)0x00020000)
+#define RCC_APB2_PERIPH_UART7 ((uint32_t)0x00040000)
+#define RCC_APB2_PERIPH_I2C3 ((uint32_t)0x00080000)
+#define RCC_APB2_PERIPH_I2C4 ((uint32_t)0x00100000)
+
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH)&0xFFE08602) == 0x00) && ((PERIPH) != 0x00))
+/**
+ * @}
+ */
+
+/** @addtogroup APB1_peripheral
+ * @{
+ */
+
+#define RCC_APB1_PERIPH_TIM2 ((uint32_t)0x00000001)
+#define RCC_APB1_PERIPH_TIM3 ((uint32_t)0x00000002)
+#define RCC_APB1_PERIPH_TIM4 ((uint32_t)0x00000004)
+#define RCC_APB1_PERIPH_TIM5 ((uint32_t)0x00000008)
+#define RCC_APB1_PERIPH_TIM6 ((uint32_t)0x00000010)
+#define RCC_APB1_PERIPH_TIM7 ((uint32_t)0x00000020)
+#define RCC_APB1_PERIPH_COMP ((uint32_t)0x00000040)
+#define RCC_APB1_PERIPH_COMP_FILT ((uint32_t)0x00000080)
+#define RCC_APB1_PERIPH_TSC ((uint32_t)0x00000400)
+#define RCC_APB1_PERIPH_WWDG ((uint32_t)0x00000800)
+#define RCC_APB1_PERIPH_SPI2 ((uint32_t)0x00004000)
+#define RCC_APB1_PERIPH_SPI3 ((uint32_t)0x00008000)
+#define RCC_APB1_PERIPH_USART2 ((uint32_t)0x00020000)
+#define RCC_APB1_PERIPH_USART3 ((uint32_t)0x00040000)
+#define RCC_APB1_PERIPH_UART4 ((uint32_t)0x00080000)
+#define RCC_APB1_PERIPH_UART5 ((uint32_t)0x00100000)
+#define RCC_APB1_PERIPH_I2C1 ((uint32_t)0x00200000)
+#define RCC_APB1_PERIPH_I2C2 ((uint32_t)0x00400000)
+#define RCC_APB1_PERIPH_USB ((uint32_t)0x00800000)
+#define RCC_APB1_PERIPH_CAN1 ((uint32_t)0x02000000)
+#define RCC_APB1_PERIPH_CAN2 ((uint32_t)0x04000000)
+#define RCC_APB1_PERIPH_BKP ((uint32_t)0x08000000)
+#define RCC_APB1_PERIPH_PWR ((uint32_t)0x10000000)
+#define RCC_APB1_PERIPH_DAC ((uint32_t)0x20000000)
+#define RCC_APB1_PERIPH_OPAMP ((uint32_t)0x80000000)
+
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH)&0x41013300) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+
+#define RCC_MCO_PLLCLK_DIV2 ((uint32_t)0x20000000)
+#define RCC_MCO_PLLCLK_DIV3 ((uint32_t)0x30000000)
+#define RCC_MCO_PLLCLK_DIV4 ((uint32_t)0x40000000)
+#define RCC_MCO_PLLCLK_DIV5 ((uint32_t)0x50000000)
+#define RCC_MCO_PLLCLK_DIV6 ((uint32_t)0x60000000)
+#define RCC_MCO_PLLCLK_DIV7 ((uint32_t)0x70000000)
+#define RCC_MCO_PLLCLK_DIV8 ((uint32_t)0x80000000)
+#define RCC_MCO_PLLCLK_DIV9 ((uint32_t)0x90000000)
+#define RCC_MCO_PLLCLK_DIV10 ((uint32_t)0xA0000000)
+#define RCC_MCO_PLLCLK_DIV11 ((uint32_t)0xB0000000)
+#define RCC_MCO_PLLCLK_DIV12 ((uint32_t)0xC0000000)
+#define RCC_MCO_PLLCLK_DIV13 ((uint32_t)0xD0000000)
+#define RCC_MCO_PLLCLK_DIV14 ((uint32_t)0xE0000000)
+#define RCC_MCO_PLLCLK_DIV15 ((uint32_t)0xF0000000)
+#define IS_RCC_MCOPLLCLKPRE(DIV) \
+ (((DIV) == RCC_MCO_PLLCLK_DIV2) || ((DIV) == RCC_MCO_PLLCLK_DIV3) || ((DIV) == RCC_MCO_PLLCLK_DIV4) \
+ || ((DIV) == RCC_MCO_PLLCLK_DIV5) || ((DIV) == RCC_MCO_PLLCLK_DIV6) || ((DIV) == RCC_MCO_PLLCLK_DIV7) \
+ || ((DIV) == RCC_MCO_PLLCLK_DIV8) || ((DIV) == RCC_MCO_PLLCLK_DIV9) || ((DIV) == RCC_MCO_PLLCLK_DIV10) \
+ || ((DIV) == RCC_MCO_PLLCLK_DIV11) || ((DIV) == RCC_MCO_PLLCLK_DIV12) || ((DIV) == RCC_MCO_PLLCLK_DIV13) \
+ || ((DIV) == RCC_MCO_PLLCLK_DIV14) || ((DIV) == RCC_MCO_PLLCLK_DIV15))
+
+/** @addtogroup Clock_source_to_output_on_MCO_pin
+ * @{
+ */
+
+#define RCC_MCO_NOCLK ((uint8_t)0x00)
+#define RCC_MCO_SYSCLK ((uint8_t)0x04)
+#define RCC_MCO_HSI ((uint8_t)0x05)
+#define RCC_MCO_HSE ((uint8_t)0x06)
+#define RCC_MCO_PLLCLK ((uint8_t)0x07)
+
+#define IS_RCC_MCO(MCO) \
+ (((MCO) == RCC_MCO_NOCLK) || ((MCO) == RCC_MCO_HSI) || ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) \
+ || ((MCO) == RCC_MCO_PLLCLK))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Flag
+ * @{
+ */
+#define RCC_FLAG_HSIRD ((uint8_t)0x21)
+#define RCC_FLAG_HSERD ((uint8_t)0x31)
+#define RCC_FLAG_PLLRD ((uint8_t)0x39)
+#define RCC_FLAG_LSERD ((uint8_t)0x41)
+#define RCC_FLAG_LSIRD ((uint8_t)0x61)
+#define RCC_FLAG_BORRST ((uint8_t)0x73)
+#define RCC_FLAG_RETEMC ((uint8_t)0x74)
+#define RCC_FLAG_BKPEMC ((uint8_t)0x75)
+#define RCC_FLAG_RAMRST ((uint8_t)0x77)
+#define RCC_FLAG_MMURST ((uint8_t)0x79)
+#define RCC_FLAG_PINRST ((uint8_t)0x7A)
+#define RCC_FLAG_PORRST ((uint8_t)0x7B)
+#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
+#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
+#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
+#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
+
+#define IS_RCC_FLAG(FLAG) \
+ (((FLAG) == RCC_FLAG_HSIRD) || ((FLAG) == RCC_FLAG_HSERD) || ((FLAG) == RCC_FLAG_PLLRD) \
+ || ((FLAG) == RCC_FLAG_LSERD) || ((FLAG) == RCC_FLAG_LSIRD) || ((FLAG) == RCC_FLAG_BORRST) \
+ || ((FLAG) == RCC_FLAG_RETEMC) || ((FLAG) == RCC_FLAG_BKPEMC) || ((FLAG) == RCC_FLAG_RAMRST) \
+ || ((FLAG) == RCC_FLAG_MMURST) || ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) \
+ || ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST) || ((FLAG) == RCC_FLAG_WWDGRST) \
+ || ((FLAG) == RCC_FLAG_LPWRRST))
+
+#define IS_RCC_CALIB_VALUE(VALUE) ((VALUE) <= 0x1F)
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_SYSCLKConfigFromSTOP
+ * @{
+ */
+
+#define PLL_STARTUP_TIMEOUT ((uint16_t)0xF000)
+#define SYSCLK_STARTUP_TIMEOUT ((uint16_t)0xF000)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Exported_Functions
+ * @{
+ */
+
+void RCC_DeInit(void);
+void RCC_ConfigHse(uint32_t RCC_HSE);
+ErrorStatus RCC_WaitHseStable(void);
+void RCC_SetHsiCalibValue(uint8_t HSICalibrationValue);
+void RCC_EnableHsi(FunctionalState Cmd);
+void RCC_ConfigPll(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
+void RCC_EnablePll(FunctionalState Cmd);
+
+void RCC_ConfigSysclk(uint32_t RCC_SYSCLKSource);
+uint8_t RCC_GetSysclkSrc(void);
+void RCC_ConfigHclk(uint32_t RCC_SYSCLK);
+void RCC_ConfigPclk1(uint32_t RCC_HCLK);
+void RCC_ConfigPclk2(uint32_t RCC_HCLK);
+void RCC_ConfigInt(uint8_t RccInt, FunctionalState Cmd);
+
+void RCC_ConfigUsbClk(uint32_t RCC_USBCLKSource);
+
+void RCC_ConfigTim18Clk(uint32_t RCC_TIM18CLKSource);
+void RCC_ConfigRngcClk(uint32_t RCC_RNGCCLKPrescaler);
+
+void RCC_ConfigAdc1mClk(uint32_t RCC_ADC1MCLKSource, uint32_t RCC_ADC1MPrescaler);
+void RCC_ConfigAdcPllClk(uint32_t RCC_ADCPLLCLKPrescaler, FunctionalState Cmd);
+void RCC_ConfigAdcHclk(uint32_t RCC_ADCHCLKPrescaler);
+
+void RCC_ConfigTrng1mClk(uint32_t RCC_TRNG1MCLKSource, uint32_t RCC_TRNG1MPrescaler);
+void RCC_EnableTrng1mClk(FunctionalState Cmd);
+
+void RCC_ConfigLse(uint8_t RCC_LSE);
+void RCC_EnableLsi(FunctionalState Cmd);
+void RCC_ConfigRtcClk(uint32_t RCC_RTCCLKSource);
+void RCC_EnableRtcClk(FunctionalState Cmd);
+void RCC_GetClocksFreqValue(RCC_ClocksType* RCC_Clocks);
+void RCC_EnableAHBPeriphClk(uint32_t RCC_AHBPeriph, FunctionalState Cmd);
+void RCC_EnableAPB2PeriphClk(uint32_t RCC_APB2Periph, FunctionalState Cmd);
+void RCC_EnableAPB1PeriphClk(uint32_t RCC_APB1Periph, FunctionalState Cmd);
+
+void RCC_EnableAHBPeriphReset(uint32_t RCC_AHBPeriph, FunctionalState Cmd);
+void RCC_EnableAPB2PeriphReset(uint32_t RCC_APB2Periph, FunctionalState Cmd);
+void RCC_EnableAPB1PeriphReset(uint32_t RCC_APB1Periph, FunctionalState Cmd);
+void RCC_EnableBORReset(FunctionalState Cmd);
+void RCC_EnableBackupReset(FunctionalState Cmd);
+void RCC_EnableClockSecuritySystem(FunctionalState Cmd);
+void RCC_ConfigMcoPllClk(uint32_t RCC_MCOPLLCLKPrescaler);
+void RCC_ConfigMco(uint8_t RCC_MCO);
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
+void RCC_ClrFlag(void);
+INTStatus RCC_GetIntStatus(uint8_t RccInt);
+void RCC_ClrIntPendingBit(uint8_t RccInt);
+
+void RCC_SYSCLKConfigFromSTOP(uint32_t Rcc_PLLMul, uint32_t FLASH_Latency);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32WB452_RCC_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_rtc.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_rtc.h
new file mode 100644
index 0000000000..75fb020076
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_rtc.h
@@ -0,0 +1,662 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_rtc.h
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32WB452_RTC_H__
+#define __N32WB452_RTC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32wb452.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RTC
+ * @{
+ */
+
+/**
+ * @brief RTC Init structures definition
+ */
+typedef struct
+{
+ uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format.
+ This parameter can be a value of @ref RTC_Hour_Formats */
+
+ uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
+ This parameter must be set to a value lower than 0x7F */
+
+ uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
+ This parameter must be set to a value lower than 0x7FFF */
+} RTC_InitType;
+
+/**
+ * @brief RTC Time structure definition
+ */
+typedef struct
+{
+ uint8_t Hours; /*!< Specifies the RTC Time Hour.
+ This parameter must be set to a value in the 0-12 range
+ if the RTC_12HOUR_FORMAT is selected or 0-23 range if
+ the RTC_24HOUR_FORMAT is selected. */
+
+ uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
+ This parameter must be set to a value in the 0-59 range. */
+
+ uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
+ This parameter must be set to a value in the 0-59 range. */
+
+ uint8_t H12; /*!< Specifies the RTC AM/PM Time.
+ This parameter can be a value of @ref RTC_AM_PM_Definitions */
+} RTC_TimeType;
+
+/**
+ * @brief RTC Date structure definition
+ */
+typedef struct
+{
+ uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
+ This parameter can be a value of @ref RTC_WeekDay_Definitions */
+
+ uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
+ This parameter can be a value of @ref RTC_Month_Date_Definitions */
+
+ uint8_t Date; /*!< Specifies the RTC Date.
+ This parameter must be set to a value in the 1-31 range. */
+
+ uint8_t Year; /*!< Specifies the RTC Date Year.
+ This parameter must be set to a value in the 0-99 range. */
+} RTC_DateType;
+
+/**
+ * @brief RTC Alarm structure definition
+ */
+typedef struct
+{
+ RTC_TimeType AlarmTime; /*!< Specifies the RTC Alarm Time members. */
+
+ uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
+ This parameter can be a value of @ref RTC_AlarmMask_Definitions */
+
+ uint32_t DateWeekMode; /*!< Specifies the RTC Alarm is on Date or WeekDay.
+ This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
+
+ uint8_t DateWeekValue; /*!< Specifies the RTC Alarm Date/WeekDay.
+ If the Alarm Date is selected, this parameter
+ must be set to a value in the 1-31 range.
+ If the Alarm WeekDay is selected, this
+ parameter can be a value of @ref RTC_WeekDay_Definitions */
+} RTC_AlarmType;
+
+/** @addtogroup RTC_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup RTC_Hour_Formats
+ * @{
+ */
+#define RTC_24HOUR_FORMAT ((uint32_t)0x00000000)
+#define RTC_12HOUR_FORMAT ((uint32_t)0x00000040)
+#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_12HOUR_FORMAT) || ((FORMAT) == RTC_24HOUR_FORMAT))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Asynchronous_Predivider
+ * @{
+ */
+#define IS_RTC_PREDIV_ASYNCH(PREDIV) ((PREDIV) <= 0x7F)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Synchronous_Predivider
+ * @{
+ */
+#define IS_RTC_PREDIV_SYNCH(PREDIV) ((PREDIV) <= 0x7FFF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Time_Definitions
+ * @{
+ */
+#define IS_RTC_12HOUR(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))
+#define IS_RTC_24HOUR(HOUR) ((HOUR) <= 23)
+#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)
+#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_AM_PM_Definitions
+ * @{
+ */
+#define RTC_AM_H12 ((uint8_t)0x00)
+#define RTC_PM_H12 ((uint8_t)0x40)
+#define IS_RTC_H12(PM) (((PM) == RTC_AM_H12) || ((PM) == RTC_PM_H12))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Year_Date_Definitions
+ * @{
+ */
+#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Month_Date_Definitions
+ * @{
+ */
+
+/* Coded in BCD format */
+#define RTC_MONTH_JANUARY ((uint8_t)0x01)
+#define RTC_MONTH_FEBRURY ((uint8_t)0x02)
+#define RTC_MONTH_MARCH ((uint8_t)0x03)
+#define RTC_MONTH_APRIL ((uint8_t)0x04)
+#define RTC_MONTH_MAY ((uint8_t)0x05)
+#define RTC_MONTH_JUNE ((uint8_t)0x06)
+#define RTC_MONTH_JULY ((uint8_t)0x07)
+#define RTC_MONTH_AUGUST ((uint8_t)0x08)
+#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
+#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
+#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
+#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
+#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))
+#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_WeekDay_Definitions
+ * @{
+ */
+
+#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
+#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
+#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
+#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
+#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
+#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
+#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
+#define IS_RTC_WEEKDAY(WEEKDAY) \
+ (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) \
+ || ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) \
+ || ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Alarm_Definitions
+ * @{
+ */
+#define IS_RTC_ALARM_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
+#define IS_RTC_ALARM_WEEKDAY_WEEKDAY(WEEKDAY) \
+ (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) \
+ || ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) \
+ || ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_AlarmDateWeekDay_Definitions
+ * @{
+ */
+#define RTC_ALARM_SEL_WEEKDAY_DATE ((uint32_t)0x00000000)
+#define RTC_ALARM_SEL_WEEKDAY_WEEKDAY ((uint32_t)0x40000000)
+
+#define IS_RTC_ALARM_WEEKDAY_SEL(SEL) \
+ (((SEL) == RTC_ALARM_SEL_WEEKDAY_DATE) || ((SEL) == RTC_ALARM_SEL_WEEKDAY_WEEKDAY))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_AlarmMask_Definitions
+ * @{
+ */
+#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000)
+#define RTC_ALARMMASK_WEEKDAY ((uint32_t)0x80000000)
+#define RTC_ALARMMASK_HOURS ((uint32_t)0x00800000)
+#define RTC_ALARMMASK_MINUTES ((uint32_t)0x00008000)
+#define RTC_ALARMMASK_SECONDS ((uint32_t)0x00000080)
+#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080)
+#define IS_ALARM_MASK(INTEN) (((INTEN)&0x7F7F7F7F) == (uint32_t)RESET)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Alarms_Definitions
+ * @{
+ */
+#define RTC_A_ALARM ((uint32_t)0x00000100)
+#define RTC_B_ALARM ((uint32_t)0x00000200)
+#define IS_RTC_ALARM_SEL(ALARM) (((ALARM) == RTC_A_ALARM) || ((ALARM) == RTC_B_ALARM))
+#define IS_RTC_ALARM_ENABLE(ALARM) (((ALARM) & (RTC_A_ALARM | RTC_B_ALARM)) != (uint32_t)RESET)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Alarm_Sub_Seconds_Masks_Definitions
+ * @{
+ */
+#define RTC_SUBS_MASK_ALL \
+ ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. \
+ There is no comparison on sub seconds \
+ for Alarm */
+#define RTC_SUBS_MASK_SS14_1 \
+ ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm \
+ comparison. Only SS[0] is compared. */
+#define RTC_SUBS_MASK_SS14_2 \
+ ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm \
+ comparison. Only SS[1:0] are compared */
+#define RTC_SUBS_MASK_SS14_3 \
+ ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm \
+ comparison. Only SS[2:0] are compared */
+#define RTC_SUBS_MASK_SS14_4 \
+ ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm \
+ comparison. Only SS[3:0] are compared */
+#define RTC_SUBS_MASK_SS14_5 \
+ ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm \
+ comparison. Only SS[4:0] are compared */
+#define RTC_SUBS_MASK_SS14_6 \
+ ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm \
+ comparison. Only SS[5:0] are compared */
+#define RTC_SUBS_MASK_SS14_7 \
+ ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm \
+ comparison. Only SS[6:0] are compared */
+#define RTC_SUBS_MASK_SS14_8 \
+ ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm \
+ comparison. Only SS[7:0] are compared */
+#define RTC_SUBS_MASK_SS14_9 \
+ ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm \
+ comparison. Only SS[8:0] are compared */
+#define RTC_SUBS_MASK_SS14_10 \
+ ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm \
+ comparison. Only SS[9:0] are compared */
+#define RTC_SUBS_MASK_SS14_11 \
+ ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm \
+ comparison. Only SS[10:0] are compared */
+#define RTC_SUBS_MASK_SS14_12 \
+ ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm \
+ comparison.Only SS[11:0] are compared */
+#define RTC_SUBS_MASK_SS14_13 \
+ ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm \
+ comparison. Only SS[12:0] are compared */
+#define RTC_SUBS_MASK_SS14_14 \
+ ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm \
+ comparison.Only SS[13:0] are compared */
+#define RTC_SUBS_MASK_NONE \
+ ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match \
+ to activate alarm. */
+#define IS_RTC_ALARM_SUB_SECOND_MASK_MODE(INTEN) \
+ (((INTEN) == RTC_SUBS_MASK_ALL) || ((INTEN) == RTC_SUBS_MASK_SS14_1) || ((INTEN) == RTC_SUBS_MASK_SS14_2) \
+ || ((INTEN) == RTC_SUBS_MASK_SS14_3) || ((INTEN) == RTC_SUBS_MASK_SS14_4) || ((INTEN) == RTC_SUBS_MASK_SS14_5) \
+ || ((INTEN) == RTC_SUBS_MASK_SS14_6) || ((INTEN) == RTC_SUBS_MASK_SS14_7) || ((INTEN) == RTC_SUBS_MASK_SS14_8) \
+ || ((INTEN) == RTC_SUBS_MASK_SS14_9) || ((INTEN) == RTC_SUBS_MASK_SS14_10) || ((INTEN) == RTC_SUBS_MASK_SS14_11) \
+ || ((INTEN) == RTC_SUBS_MASK_SS14_12) || ((INTEN) == RTC_SUBS_MASK_SS14_13) || ((INTEN) == RTC_SUBS_MASK_SS14_14) \
+ || ((INTEN) == RTC_SUBS_MASK_NONE))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Alarm_Sub_Seconds_Value
+ * @{
+ */
+
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Wakeup_Timer_Definitions
+ * @{
+ */
+#define RTC_WKUPCLK_RTCCLK_DIV16 ((uint32_t)0x00000000)
+#define RTC_WKUPCLK_RTCCLK_DIV8 ((uint32_t)0x00000001)
+#define RTC_WKUPCLK_RTCCLK_DIV4 ((uint32_t)0x00000002)
+#define RTC_WKUPCLK_RTCCLK_DIV2 ((uint32_t)0x00000003)
+#define RTC_WKUPCLK_CK_SPRE_16BITS ((uint32_t)0x00000004)
+
+#define IS_RTC_WKUP_CLOCK(CLOCK) \
+ (((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV16) || ((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV8) \
+ || ((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV4) || ((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV2) \
+ || ((CLOCK) == RTC_WKUPCLK_CK_SPRE_16BITS))
+#define IS_RTC_WKUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Time_Stamp_Edges_definitions
+ * @{
+ */
+#define RTC_TIMESTAMP_EDGE_RISING ((uint32_t)0x00000000)
+#define RTC_TIMESTAMP_EDGE_FALLING ((uint32_t)0x00000008)
+#define IS_RTC_TIMESTAMP_EDGE_MODE(EDGE) \
+ (((EDGE) == RTC_TIMESTAMP_EDGE_RISING) || ((EDGE) == RTC_TIMESTAMP_EDGE_FALLING))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Output_selection_Definitions
+ * @{
+ */
+#define RTC_OUTPUT_DIS ((uint32_t)0x00000000)
+#define RTC_OUTPUT_ALA ((uint32_t)0x00200000)
+#define RTC_OUTPUT_ALB ((uint32_t)0x00400000)
+#define RTC_OUTPUT_WKUP ((uint32_t)0x00600000)
+
+#define IS_RTC_OUTPUT_MODE(OUTPUT) \
+ (((OUTPUT) == RTC_OUTPUT_DIS) || ((OUTPUT) == RTC_OUTPUT_ALA) || ((OUTPUT) == RTC_OUTPUT_ALB) \
+ || ((OUTPUT) == RTC_OUTPUT_WKUP))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Output_Polarity_Definitions
+ * @{
+ */
+#define RTC_OUTPOL_HIGH ((uint32_t)0x00000000)
+#define RTC_OUTPOL_LOW ((uint32_t)0x00100000)
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPOL_HIGH) || ((POL) == RTC_OUTPOL_LOW))
+/**
+ * @}
+ */
+
+
+/** @addtogroup RTC_Calib_Output_selection_Definitions
+ * @{
+ */
+#define RTC_CALIB_OUTPUT_256HZ ((uint32_t)0x00000000)
+#define RTC_CALIB_OUTPUT_1HZ ((uint32_t)0x00080000)
+#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIB_OUTPUT_256HZ) || ((OUTPUT) == RTC_CALIB_OUTPUT_1HZ))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Smooth_calib_period_Definitions
+ * @{
+ */
+#define SMOOTH_CALIB_32SEC \
+ ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \
+ period is 32s, else 2exp20 RTCCLK seconds */
+#define SMOOTH_CALIB_16SEC \
+ ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \
+ period is 16s, else 2exp19 RTCCLK seconds */
+#define SMOOTH_CALIB_8SEC \
+ ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \
+ period is 8s, else 2exp18 RTCCLK seconds */
+#define IS_RTC_SMOOTH_CALIB_PERIOD_SEL(PERIOD) \
+ (((PERIOD) == SMOOTH_CALIB_32SEC) || ((PERIOD) == SMOOTH_CALIB_16SEC) || ((PERIOD) == SMOOTH_CALIB_8SEC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Smooth_calib_Plus_pulses_Definitions
+ * @{
+ */
+#define RTC_SMOOTH_CALIB_PLUS_PULSES_SET \
+ ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added \
+ during a X -second window = Y - CALM[8:0]. \
+ with Y = 512, 256, 128 when X = 32, 16, 8 */
+#define RTC_SMOOTH_CALIB_PLUS_PULSES__RESET \
+ ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited \
+ during a 32-second window = CALM[8:0]. */
+#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) \
+ (((PLUS) == RTC_SMOOTH_CALIB_PLUS_PULSES_SET) || ((PLUS) == RTC_SMOOTH_CALIB_PLUS_PULSES__RESET))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Smooth_calib_Minus_pulses_Definitions
+ * @{
+ */
+#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_DayLightSaving_Definitions
+ * @{
+ */
+#define RTC_DAYLIGHT_SAVING_SUB1H ((uint32_t)0x00020000)
+#define RTC_DAYLIGHT_SAVING_ADD1H ((uint32_t)0x00010000)
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHT_SAVING_SUB1H) || ((SAVE) == RTC_DAYLIGHT_SAVING_ADD1H))
+
+#define RTC_STORE_OPERATION_RESET ((uint32_t)0x00000000)
+#define RTC_STORE_OPERATION_SET ((uint32_t)0x00040000)
+#define IS_RTC_STORE_OPERATION(OPERATION) \
+ (((OPERATION) == RTC_STORE_OPERATION_RESET) || ((OPERATION) == RTC_STORE_OPERATION_SET))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Output_Type_ALARM_OUT
+ * @{
+ */
+#define RTC_OUTPUT_OPENDRAIN ((uint32_t)0x00000000)
+#define RTC_OUTPUT_PUSHPULL ((uint32_t)0x00000001)
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_OPENDRAIN) || ((TYPE) == RTC_OUTPUT_PUSHPULL))
+
+/**
+ * @}
+ */
+/** @addtogroup RTC_Add_Fraction_Of_Second_Value
+ * @{
+ */
+#define RTC_SHIFT_SUB1S_DISABLE ((uint32_t)0x00000000)
+#define RTC_SHIFT_SUB1S_ENABLE ((uint32_t)0x80000000)
+#define IS_RTC_SHIFT_SUB1S(SEL) (((SEL) == RTC_SHIFT_SUB1S_DISABLE) || ((SEL) == RTC_SHIFT_SUB1S_ENABLE))
+/**
+ * @}
+ */
+/** @addtogroup RTC_Substract_1_Second_Parameter_Definitions
+ * @{
+ */
+#define IS_RTC_SHIFT_ADFS(FS) ((FS) <= 0x00007FFF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Input_parameter_format_definitions
+ * @{
+ */
+#define RTC_FORMAT_BIN ((uint32_t)0x000000000)
+#define RTC_FORMAT_BCD ((uint32_t)0x000000001)
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Flags_Definitions
+ * @{
+ */
+#define RTC_FLAG_RECPF ((uint32_t)0x00010000)
+#define RTC_FLAG_TISOVF ((uint32_t)0x00001000)
+#define RTC_FLAG_TISF ((uint32_t)0x00000800)
+#define RTC_FLAG_WTF ((uint32_t)0x00000400)
+#define RTC_FLAG_ALBF ((uint32_t)0x00000200)
+#define RTC_FLAG_ALAF ((uint32_t)0x00000100)
+#define RTC_FLAG_INITF ((uint32_t)0x00000040)
+#define RTC_FLAG_RSYF ((uint32_t)0x00000020)
+#define RTC_FLAG_INITSF ((uint32_t)0x00000010)
+#define RTC_FLAG_SHOPF ((uint32_t)0x00000008)
+#define RTC_FLAG_WTWF ((uint32_t)0x00000004)
+#define RTC_FLAG_ALBWF ((uint32_t)0x00000002)
+#define RTC_FLAG_ALAWF ((uint32_t)0x00000001)
+#define IS_RTC_GET_FLAG(FLAG) \
+ (((FLAG) == RTC_FLAG_TISOVF) || ((FLAG) == RTC_FLAG_TISF) || ((FLAG) == RTC_FLAG_WTF) || ((FLAG) == RTC_FLAG_ALBF) \
+ || ((FLAG) == RTC_FLAG_ALAF) || ((FLAG) == RTC_FLAG_INITF) || ((FLAG) == RTC_FLAG_RSYF) \
+ || ((FLAG) == RTC_FLAG_WTWF) || ((FLAG) == RTC_FLAG_ALBWF) || ((FLAG) == RTC_FLAG_ALAWF) \
+ || ((FLAG) == RTC_FLAG_RECPF) || ((FLAG) == RTC_FLAG_SHOPF) || ((FLAG) == RTC_FLAG_INITSF))
+#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG)&0x00011fff) == (uint32_t)SET))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Interrupts_Definitions
+ * @{
+ */
+
+#define RTC_INT_WUT ((uint32_t)0x00004000)
+#define RTC_INT_ALRB ((uint32_t)0x00002000)
+#define RTC_INT_ALRA ((uint32_t)0x00001000)
+
+#define IS_RTC_CONFIG_INT(IT) (((IT) != (uint32_t)RESET) && (((IT)&0xFFFF0FFB) == (uint32_t)RESET))
+#define IS_RTC_GET_INT(IT) \
+ (((IT) == RTC_INT_WUT) || ((IT) == RTC_INT_ALRB) || ((IT) == RTC_INT_ALRA))
+#define IS_RTC_CLEAR_INT(IT) (((IT) != (uint32_t)RESET) && (((IT)&0x00007000) == (uint32_t)SET))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Legacy
+ * @{
+ */
+#define RTC_DigitalCalibConfig RTC_CoarseCalibConfig
+#define RTC_DigitalCalibCmd RTC_CoarseCalibCmd
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Function used to set the RTC configuration to the default reset state *****/
+ErrorStatus RTC_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+ErrorStatus RTC_Init(RTC_InitType* RTC_InitStruct);
+void RTC_StructInit(RTC_InitType* RTC_InitStruct);
+void RTC_EnableWriteProtection(FunctionalState Cmd);
+ErrorStatus RTC_EnterInitMode(void);
+void RTC_ExitInitMode(void);
+ErrorStatus RTC_WaitForSynchro(void);
+ErrorStatus RTC_EnableRefClock(FunctionalState Cmd);
+void RTC_EnableBypassShadow(FunctionalState Cmd);
+
+/* Time and Date configuration functions **************************************/
+ErrorStatus RTC_ConfigTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct);
+void RTC_TimeStructInit(RTC_TimeType* RTC_TimeStruct);
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct);
+uint32_t RTC_GetSubSecond(void);
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct);
+void RTC_DateStructInit(RTC_DateType* RTC_DateStruct);
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct);
+
+/* Alarms (Alarm A and Alarm B) configuration functions **********************/
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct);
+void RTC_AlarmStructInit(RTC_AlarmType* RTC_AlarmStruct);
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct);
+ErrorStatus RTC_EnableAlarm(uint32_t RTC_Alarm, FunctionalState Cmd);
+void RTC_ConfigAlarmSubSecond(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask);
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
+
+/* WakeUp Timer configuration functions ***************************************/
+void RTC_ConfigWakeUpClock(uint32_t RTC_WakeUpClock);
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);
+uint32_t RTC_GetWakeUpCounter(void);
+ErrorStatus RTC_EnableWakeUp(FunctionalState Cmd);
+
+/* Daylight Saving configuration functions ************************************/
+void RTC_ConfigDayLightSaving(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
+uint32_t RTC_GetStoreOperation(void);
+
+/* Output pin Configuration function ******************************************/
+void RTC_ConfigOutput(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
+
+/* Coarse and Smooth Calibration configuration functions **********************/
+void RTC_EnableCalibOutput(FunctionalState Cmd);
+void RTC_ConfigCalibOutput(uint32_t RTC_CalibOutput);
+ErrorStatus RTC_ConfigSmoothCalib(uint32_t RTC_SmoothCalibPeriod,
+ uint32_t RTC_SmoothCalibPlusPulses,
+ uint32_t RTC_SmouthCalibMinusPulsesValue);
+
+/* TimeStamp configuration functions ******************************************/
+void RTC_EnableTimeStamp(uint32_t RTC_TimeStampEdge, FunctionalState Cmd);
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeType* RTC_StampTimeStruct, RTC_DateType* RTC_StampDateStruct);
+uint32_t RTC_GetTimeStampSubSecond(void);
+
+/* Output Type Config configuration functions *********************************/
+void RTC_ConfigOutputType(uint32_t RTC_OutputType);
+
+/* RTC_Shift_control_synchonisation_functions *********************************/
+ErrorStatus RTC_ConfigSynchroShift(uint32_t RTC_ShiftAddFS, uint32_t RTC_ShiftSub1s);
+
+/* Interrupts and flags management functions **********************************/
+void RTC_ConfigInt(uint32_t RTC_INT, FunctionalState Cmd);
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
+void RTC_ClrFlag(uint32_t RTC_FLAG);
+INTStatus RTC_GetITStatus(uint32_t RTC_INT);
+void RTC_ClrIntPendingBit(uint32_t RTC_INT);
+/* WakeUp TSC function **********************************/
+void RTC_EnableWakeUpTsc(uint32_t count);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32WB452_RTC_H__ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_sdio.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_sdio.h
new file mode 100644
index 0000000000..a04151e30c
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_sdio.h
@@ -0,0 +1,494 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_sdio.h
+ * @author Nations
+ * @version v1.0.1
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32WB452_SDIO_H__
+#define __N32WB452_SDIO_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32wb452.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup SDIO
+ * @{
+ */
+
+/** @addtogroup SDIO_Exported_Types
+ * @{
+ */
+
+typedef struct
+{
+ uint32_t ClkEdge; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref SDIO_Clock_Edge */
+
+ uint32_t ClkBypass; /*!< Specifies whether the SDIO Clock divider bypass is
+ enabled or disabled.
+ This parameter can be a value of @ref SDIO_Clock_Bypass */
+
+ uint32_t ClkPwrSave; /*!< Specifies whether SDIO Clock output is enabled or
+ disabled when the bus is idle.
+ This parameter can be a value of @ref SDIO_Clock_Power_Save */
+
+ uint32_t BusWidth; /*!< Specifies the SDIO bus width.
+ This parameter can be a value of @ref SDIO_Bus_Wide */
+
+ uint32_t HardwareClkCtrl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
+ This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
+
+ uint8_t ClkDiv; /*!< Specifies the clock frequency of the SDIO controller.
+ This parameter can be a value between 0x00 and 0xFF. */
+
+} SDIO_InitType;
+
+typedef struct
+{
+ uint32_t CmdArgument; /*!< Specifies the SDIO command argument which is sent
+ to a card as part of a command message. If a command
+ contains an argument, it must be loaded into this register
+ before writing the command to the command register */
+
+ uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */
+
+ uint32_t ResponseType; /*!< Specifies the SDIO response type.
+ This parameter can be a value of @ref SDIO_Response_Type */
+
+ uint32_t WaitType; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
+ This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
+
+ uint32_t CPSMConfig; /*!< Specifies whether SDIO Command path state machine (CPSM)
+ is enabled or disabled.
+ This parameter can be a value of @ref SDIO_CPSM_State */
+} SDIO_CmdInitType;
+
+typedef struct
+{
+ uint32_t DatTimeout; /*!< Specifies the data timeout period in card bus clock periods. */
+
+ uint32_t DatLen; /*!< Specifies the number of data bytes to be transferred. */
+
+ uint32_t DatBlkSize; /*!< Specifies the data block size for block transfer.
+ This parameter can be a value of @ref SDIO_Data_Block_Size */
+
+ uint32_t TransferDirection; /*!< Specifies the data transfer direction, whether the transfer
+ is a read or write.
+ This parameter can be a value of @ref SDIO_Transfer_Direction */
+
+ uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
+ This parameter can be a value of @ref SDIO_Transfer_Type */
+
+ uint32_t DPSMConfig; /*!< Specifies whether SDIO Data path state machine (DPSM)
+ is enabled or disabled.
+ This parameter can be a value of @ref SDIO_DPSM_State */
+} SDIO_DataInitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup SDIO_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup SDIO_Clock_Edge
+ * @{
+ */
+
+#define SDIO_CLKEDGE_RISING ((uint32_t)0x00000000)
+#define SDIO_CLKEDGE_FALLING ((uint32_t)0x00002000)
+#define IS_SDIO_CLK_EDGE(EDGE) (((EDGE) == SDIO_CLKEDGE_RISING) || ((EDGE) == SDIO_CLKEDGE_FALLING))
+/**
+ * @}
+ */
+
+/** @addtogroup SDIO_Clock_Bypass
+ * @{
+ */
+
+#define SDIO_ClkBYPASS_DISABLE ((uint32_t)0x00000000)
+#define SDIO_ClkBYPASS_ENABLE ((uint32_t)0x00000400)
+#define IS_SDIO_CLK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClkBYPASS_DISABLE) || ((BYPASS) == SDIO_ClkBYPASS_ENABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup SDIO_Clock_Power_Save
+ * @{
+ */
+
+#define SDIO_CLKPOWERSAVE_DISABLE ((uint32_t)0x00000000)
+#define SDIO_CLKPOWERSAVE_ENABLE ((uint32_t)0x00000200)
+#define IS_SDIO_CLK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLKPOWERSAVE_DISABLE) || ((SAVE) == SDIO_CLKPOWERSAVE_ENABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup SDIO_Bus_Wide
+ * @{
+ */
+
+#define SDIO_BUSWIDTH_1B ((uint32_t)0x00000000)
+#define SDIO_BUSWIDTH_4B ((uint32_t)0x00000800)
+#define SDIO_BUSWIDTH_8B ((uint32_t)0x00001000)
+#define IS_SDIO_BUS_WIDTH(WIDE) \
+ (((WIDE) == SDIO_BUSWIDTH_1B) || ((WIDE) == SDIO_BUSWIDTH_4B) || ((WIDE) == SDIO_BUSWIDTH_8B))
+
+/**
+ * @}
+ */
+
+/** @addtogroup SDIO_Hardware_Flow_Control
+ * @{
+ */
+
+#define SDIO_HARDWARE_CLKCTRL_DISABLE ((uint32_t)0x00000000)
+#define SDIO_HARDWARE_CLKCTRL_ENABLE ((uint32_t)0x00004000)
+#define IS_SDIO_HARDWARE_CLKCTRL(CONTROL) \
+ (((CONTROL) == SDIO_HARDWARE_CLKCTRL_DISABLE) || ((CONTROL) == SDIO_HARDWARE_CLKCTRL_ENABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup SDIO_Power_State
+ * @{
+ */
+
+#define SDIO_POWER_CTRL_OFF ((uint32_t)0x00000000)
+#define SDIO_POWER_CTRL_ON ((uint32_t)0x00000003)
+#define IS_SDIO_POWER_CTRL(STATE) (((STATE) == SDIO_POWER_CTRL_OFF) || ((STATE) == SDIO_POWER_CTRL_ON))
+/**
+ * @}
+ */
+
+/** @addtogroup SDIO_Interrupt_sources
+ * @{
+ */
+
+#define SDIO_INT_CCRCERR ((uint32_t)0x00000001)
+#define SDIO_INT_DCRCERR ((uint32_t)0x00000002)
+#define SDIO_INT_CMDTIMEOUT ((uint32_t)0x00000004)
+#define SDIO_INT_DATTIMEOUT ((uint32_t)0x00000008)
+#define SDIO_INT_TXURERR ((uint32_t)0x00000010)
+#define SDIO_INT_RXORERR ((uint32_t)0x00000020)
+#define SDIO_INT_CMDRESPRECV ((uint32_t)0x00000040)
+#define SDIO_INT_CMDSEND ((uint32_t)0x00000080)
+#define SDIO_INT_DATEND ((uint32_t)0x00000100)
+#define SDIO_INT_SBERR ((uint32_t)0x00000200)
+#define SDIO_INT_DATBLKEND ((uint32_t)0x00000400)
+#define SDIO_INT_CMDRUN ((uint32_t)0x00000800)
+#define SDIO_INT_TXRUN ((uint32_t)0x00001000)
+#define SDIO_INT_RXRUN ((uint32_t)0x00002000)
+#define SDIO_INT_TFIFOHE ((uint32_t)0x00004000)
+#define SDIO_INT_RFIFOHF ((uint32_t)0x00008000)
+#define SDIO_INT_TFIFOF ((uint32_t)0x00010000)
+#define SDIO_INT_RFIFOF ((uint32_t)0x00020000)
+#define SDIO_INT_TFIFOE ((uint32_t)0x00040000)
+#define SDIO_INT_RFIFOE ((uint32_t)0x00080000)
+#define SDIO_INT_TDATVALID ((uint32_t)0x00100000)
+#define SDIO_INT_RDATVALID ((uint32_t)0x00200000)
+#define SDIO_INT_SDIOINT ((uint32_t)0x00400000)
+#define SDIO_INT_CEATAF ((uint32_t)0x00800000)
+#define IS_SDIO_INT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
+/**
+ * @}
+ */
+
+/** @addtogroup SDIO_Command_Index
+ * @{
+ */
+
+#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
+/**
+ * @}
+ */
+
+/** @addtogroup SDIO_Response_Type
+ * @{
+ */
+
+#define SDIO_RESP_NO ((uint32_t)0x00000000)
+#define SDIO_RESP_SHORT ((uint32_t)0x00000040)
+#define SDIO_RESP_LONG ((uint32_t)0x000000C0)
+#define IS_SDIO_RESP(RESPONSE) \
+ (((RESPONSE) == SDIO_RESP_NO) || ((RESPONSE) == SDIO_RESP_SHORT) || ((RESPONSE) == SDIO_RESP_LONG))
+/**
+ * @}
+ */
+
+/** @addtogroup SDIO_Wait_Interrupt_State
+ * @{
+ */
+
+#define SDIO_WAIT_NO ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
+#define SDIO_WAIT_INT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
+#define SDIO_WAIT_PEND ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
+#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || ((WAIT) == SDIO_WAIT_INT) || ((WAIT) == SDIO_WAIT_PEND))
+/**
+ * @}
+ */
+
+/** @addtogroup SDIO_CPSM_State
+ * @{
+ */
+
+#define SDIO_CPSM_DISABLE ((uint32_t)0x00000000)
+#define SDIO_CPSM_ENABLE ((uint32_t)0x00000400)
+#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_ENABLE) || ((CPSM) == SDIO_CPSM_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup SDIO_Response_Registers
+ * @{
+ */
+
+#define SDIO_RESPONSE_1 ((uint32_t)0x00000000)
+#define SDIO_RESPONSE_2 ((uint32_t)0x00000004)
+#define SDIO_RESPONSE_3 ((uint32_t)0x00000008)
+#define SDIO_RESPONSE_4 ((uint32_t)0x0000000C)
+#define IS_SDIO_RESPONSE(RESP) \
+ (((RESP) == SDIO_RESPONSE_1) || ((RESP) == SDIO_RESPONSE_2) || ((RESP) == SDIO_RESPONSE_3) \
+ || ((RESP) == SDIO_RESPONSE_4))
+/**
+ * @}
+ */
+
+/** @addtogroup SDIO_Data_Length
+ * @{
+ */
+
+#define IS_SDIO_DAT_LEN(LENGTH) ((LENGTH) <= 0x01FFFFFF)
+/**
+ * @}
+ */
+
+/** @addtogroup SDIO_Data_Block_Size
+ * @{
+ */
+
+#define SDIO_DATBLK_SIZE_1B ((uint32_t)0x00000000)
+#define SDIO_DATBLK_SIZE_2B ((uint32_t)0x00000010)
+#define SDIO_DATBLK_SIZE_4B ((uint32_t)0x00000020)
+#define SDIO_DATBLK_SIZE_8B ((uint32_t)0x00000030)
+#define SDIO_DATBLK_SIZE_16B ((uint32_t)0x00000040)
+#define SDIO_DATBLK_SIZE_32B ((uint32_t)0x00000050)
+#define SDIO_DATBLK_SIZE_64B ((uint32_t)0x00000060)
+#define SDIO_DATBLK_SIZE_128B ((uint32_t)0x00000070)
+#define SDIO_DATBLK_SIZE_256B ((uint32_t)0x00000080)
+#define SDIO_DATBLK_SIZE_512B ((uint32_t)0x00000090)
+#define SDIO_DATBLK_SIZE_1024B ((uint32_t)0x000000A0)
+#define SDIO_DATBLK_SIZE_2048B ((uint32_t)0x000000B0)
+#define SDIO_DATBLK_SIZE_4096B ((uint32_t)0x000000C0)
+#define SDIO_DATBLK_SIZE_8192B ((uint32_t)0x000000D0)
+#define SDIO_DATBLK_SIZE_16384B ((uint32_t)0x000000E0)
+#define IS_SDIO_BLK_SIZE(SIZE) \
+ (((SIZE) == SDIO_DATBLK_SIZE_1B) || ((SIZE) == SDIO_DATBLK_SIZE_2B) || ((SIZE) == SDIO_DATBLK_SIZE_4B) \
+ || ((SIZE) == SDIO_DATBLK_SIZE_8B) || ((SIZE) == SDIO_DATBLK_SIZE_16B) || ((SIZE) == SDIO_DATBLK_SIZE_32B) \
+ || ((SIZE) == SDIO_DATBLK_SIZE_64B) || ((SIZE) == SDIO_DATBLK_SIZE_128B) || ((SIZE) == SDIO_DATBLK_SIZE_256B) \
+ || ((SIZE) == SDIO_DATBLK_SIZE_512B) || ((SIZE) == SDIO_DATBLK_SIZE_1024B) || ((SIZE) == SDIO_DATBLK_SIZE_2048B) \
+ || ((SIZE) == SDIO_DATBLK_SIZE_4096B) || ((SIZE) == SDIO_DATBLK_SIZE_8192B) \
+ || ((SIZE) == SDIO_DATBLK_SIZE_16384B))
+/**
+ * @}
+ */
+
+/** @addtogroup SDIO_Transfer_Direction
+ * @{
+ */
+
+#define SDIO_TRANSDIR_TOCARD ((uint32_t)0x00000000)
+#define SDIO_TRANSDIR_TOSDIO ((uint32_t)0x00000002)
+#define IS_SDIO_TRANSFER_DIRECTION(DIR) (((DIR) == SDIO_TRANSDIR_TOCARD) || ((DIR) == SDIO_TRANSDIR_TOSDIO))
+/**
+ * @}
+ */
+
+/** @addtogroup SDIO_Transfer_Type
+ * @{
+ */
+
+#define SDIO_TRANSMODE_BLOCK ((uint32_t)0x00000000)
+#define SDIO_TRANSMODE_STREAM ((uint32_t)0x00000004)
+#define IS_SDIO_TRANS_MODE(MODE) (((MODE) == SDIO_TRANSMODE_STREAM) || ((MODE) == SDIO_TRANSMODE_BLOCK))
+/**
+ * @}
+ */
+
+/** @addtogroup SDIO_DPSM_State
+ * @{
+ */
+
+#define SDIO_DPSM_DISABLE ((uint32_t)0x00000000)
+#define SDIO_DPSM_ENABLE ((uint32_t)0x00000001)
+#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_ENABLE) || ((DPSM) == SDIO_DPSM_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup SDIO_Flags
+ * @{
+ */
+
+#define SDIO_FLAG_CCRCERR ((uint32_t)0x00000001)
+#define SDIO_FLAG_DCRCERR ((uint32_t)0x00000002)
+#define SDIO_FLAG_CMDTIMEOUT ((uint32_t)0x00000004)
+#define SDIO_FLAG_DATTIMEOUT ((uint32_t)0x00000008)
+#define SDIO_FLAG_TXURERR ((uint32_t)0x00000010)
+#define SDIO_FLAG_RXORERR ((uint32_t)0x00000020)
+#define SDIO_FLAG_CMDRESPRECV ((uint32_t)0x00000040)
+#define SDIO_FLAG_CMDSEND ((uint32_t)0x00000080)
+#define SDIO_FLAG_DATEND ((uint32_t)0x00000100)
+#define SDIO_FLAG_SBERR ((uint32_t)0x00000200)
+#define SDIO_FLAG_DATBLKEND ((uint32_t)0x00000400)
+#define SDIO_FLAG_CMDRUN ((uint32_t)0x00000800)
+#define SDIO_FLAG_TXRUN ((uint32_t)0x00001000)
+#define SDIO_FLAG_RXRUN ((uint32_t)0x00002000)
+#define SDIO_FLAG_TFIFOHE ((uint32_t)0x00004000)
+#define SDIO_FLAG_RFIFOHF ((uint32_t)0x00008000)
+#define SDIO_FLAG_TFIFOF ((uint32_t)0x00010000)
+#define SDIO_FLAG_RFIFOF ((uint32_t)0x00020000)
+#define SDIO_FLAG_TFIFOE ((uint32_t)0x00040000)
+#define SDIO_FLAG_RFIFOE ((uint32_t)0x00080000)
+#define SDIO_FLAG_TDATVALID ((uint32_t)0x00100000)
+#define SDIO_FLAG_RDATVALID ((uint32_t)0x00200000)
+#define SDIO_FLAG_SDIOINT ((uint32_t)0x00400000)
+#define SDIO_FLAG_CEATAF ((uint32_t)0x00800000)
+#define IS_SDIO_FLAG(FLAG) \
+ (((FLAG) == SDIO_FLAG_CCRCERR) || ((FLAG) == SDIO_FLAG_DCRCERR) || ((FLAG) == SDIO_FLAG_CMDTIMEOUT) \
+ || ((FLAG) == SDIO_FLAG_DATTIMEOUT) || ((FLAG) == SDIO_FLAG_TXURERR) || ((FLAG) == SDIO_FLAG_RXORERR) \
+ || ((FLAG) == SDIO_FLAG_CMDRESPRECV) || ((FLAG) == SDIO_FLAG_CMDSEND) || ((FLAG) == SDIO_FLAG_DATEND) \
+ || ((FLAG) == SDIO_FLAG_SBERR) || ((FLAG) == SDIO_FLAG_DATBLKEND) || ((FLAG) == SDIO_FLAG_CMDRUN) \
+ || ((FLAG) == SDIO_FLAG_TXRUN) || ((FLAG) == SDIO_FLAG_RXRUN) || ((FLAG) == SDIO_FLAG_TFIFOHE) \
+ || ((FLAG) == SDIO_FLAG_RFIFOHF) || ((FLAG) == SDIO_FLAG_TFIFOF) || ((FLAG) == SDIO_FLAG_RFIFOF) \
+ || ((FLAG) == SDIO_FLAG_TFIFOE) || ((FLAG) == SDIO_FLAG_RFIFOE) || ((FLAG) == SDIO_FLAG_TDATVALID) \
+ || ((FLAG) == SDIO_FLAG_RDATVALID) || ((FLAG) == SDIO_FLAG_SDIOINT) || ((FLAG) == SDIO_FLAG_CEATAF))
+
+#define IS_SDIO_CLR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
+
+#define IS_SDIO_GET_INT(IT) \
+ (((IT) == SDIO_INT_CCRCERR) || ((IT) == SDIO_INT_DCRCERR) || ((IT) == SDIO_INT_CMDTIMEOUT) \
+ || ((IT) == SDIO_INT_DATTIMEOUT) || ((IT) == SDIO_INT_TXURERR) || ((IT) == SDIO_INT_RXORERR) \
+ || ((IT) == SDIO_INT_CMDRESPRECV) || ((IT) == SDIO_INT_CMDSEND) || ((IT) == SDIO_INT_DATEND) \
+ || ((IT) == SDIO_INT_SBERR) || ((IT) == SDIO_INT_DATBLKEND) || ((IT) == SDIO_INT_CMDRUN) \
+ || ((IT) == SDIO_INT_TXRUN) || ((IT) == SDIO_INT_RXRUN) || ((IT) == SDIO_INT_TFIFOHE) \
+ || ((IT) == SDIO_INT_RFIFOHF) || ((IT) == SDIO_INT_TFIFOF) || ((IT) == SDIO_INT_RFIFOF) \
+ || ((IT) == SDIO_INT_TFIFOE) || ((IT) == SDIO_INT_RFIFOE) || ((IT) == SDIO_INT_TDATVALID) \
+ || ((IT) == SDIO_INT_RDATVALID) || ((IT) == SDIO_INT_SDIOINT) || ((IT) == SDIO_INT_CEATAF))
+
+#define IS_SDIO_CLR_INT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
+
+/**
+ * @}
+ */
+
+/** @addtogroup SDIO_Read_Wait_Mode
+ * @{
+ */
+
+#define SDIO_RDWAIT_MODE_CLK ((uint32_t)0x00000001)
+#define SDIO_RDWAIT_MODE_DAT2 ((uint32_t)0x00000000)
+#define IS_SDIO_RDWAIT_MODE(MODE) (((MODE) == SDIO_RDWAIT_MODE_CLK) || ((MODE) == SDIO_RDWAIT_MODE_DAT2))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SDIO_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SDIO_Exported_Functions
+ * @{
+ */
+
+void SDIO_DeInit(void);
+void SDIO_Init(SDIO_InitType* SDIO_InitStruct);
+void SDIO_InitStruct(SDIO_InitType* SDIO_InitStruct);
+void SDIO_EnableClock(FunctionalState Cmd);
+void SDIO_SetPower(uint32_t SDIO_PowerState);
+uint32_t SDIO_GetPower(void);
+void SDIO_ConfigInt(uint32_t SDIO_IT, FunctionalState Cmd);
+void SDIO_DMACmd(FunctionalState Cmd);
+void SDIO_SendCmd(SDIO_CmdInitType* SDIO_CmdInitStruct);
+void SDIO_InitCmdStruct(SDIO_CmdInitType* SDIO_CmdInitStruct);
+uint8_t SDIO_GetCmdResp(void);
+uint32_t SDIO_GetResp(uint32_t SDIO_RESP);
+void SDIO_ConfigData(SDIO_DataInitType* SDIO_DataInitStruct);
+void SDIO_InitDataStruct(SDIO_DataInitType* SDIO_DataInitStruct);
+uint32_t SDIO_GetDataCountValue(void);
+uint32_t SDIO_ReadData(void);
+void SDIO_WriteData(uint32_t Data);
+uint32_t SDIO_GetFifoCounter(void);
+void SDIO_EnableReadWait(FunctionalState Cmd);
+void SDIO_DisableReadWait(FunctionalState Cmd);
+void SDIO_EnableSdioReadWaitMode(uint32_t SDIO_ReadWaitMode);
+void SDIO_EnableSdioOperation(FunctionalState Cmd);
+void SDIO_EnableSendSdioSuspend(FunctionalState Cmd);
+void SDIO_EnableCommandCompletion(FunctionalState Cmd);
+void SDIO_EnableCEATAInt(FunctionalState Cmd);
+void SDIO_EnableSendCEATA(FunctionalState Cmd);
+FlagStatus SDIO_GetFlag(uint32_t SDIO_FLAG);
+void SDIO_ClrFlag(uint32_t SDIO_FLAG);
+INTStatus SDIO_GetIntStatus(uint32_t SDIO_IT);
+void SDIO_ClrIntPendingBit(uint32_t SDIO_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32WB452_SDIO_H__ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_spi.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_spi.h
new file mode 100644
index 0000000000..b997239cda
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_spi.h
@@ -0,0 +1,471 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_spi.h
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32WB452_SPI_H__
+#define __N32WB452_SPI_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32wb452.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @{
+ */
+
+/** @addtogroup SPI_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief SPI Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t DataDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
+ This parameter can be a value of @ref SPI_data_direction */
+
+ uint16_t SpiMode; /*!< Specifies the SPI operating mode.
+ This parameter can be a value of @ref SPI_mode */
+
+ uint16_t DataLen; /*!< Specifies the SPI data size.
+ This parameter can be a value of @ref SPI_data_size */
+
+ uint16_t CLKPOL; /*!< Specifies the serial clock steady state.
+ This parameter can be a value of @ref SPI_Clock_Polarity */
+
+ uint16_t CLKPHA; /*!< Specifies the clock active edge for the bit capture.
+ This parameter can be a value of @ref SPI_Clock_Phase */
+
+ uint16_t NSS; /*!< Specifies whether the NSS signal is managed by
+ hardware (NSS pin) or by software using the SSI bit.
+ This parameter can be a value of @ref SPI_Slave_Select_management */
+
+ uint16_t BaudRatePres; /*!< Specifies the Baud Rate prescaler value which will be
+ used to configure the transmit and receive SCK clock.
+ This parameter can be a value of @ref SPI_BaudRate_Prescaler.
+ @note The communication clock is derived from the master
+ clock. The slave clock does not need to be set. */
+
+ uint16_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+ uint16_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. */
+} SPI_InitType;
+
+/**
+ * @brief I2S Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t I2sMode; /*!< Specifies the I2S operating mode.
+ This parameter can be a value of @ref I2sMode */
+
+ uint16_t Standard; /*!< Specifies the standard used for the I2S communication.
+ This parameter can be a value of @ref Standard */
+
+ uint16_t DataFormat; /*!< Specifies the data format for the I2S communication.
+ This parameter can be a value of @ref I2S_Data_Format */
+
+ uint16_t MCLKEnable; /*!< Specifies whether the I2S MCLK output is enabled or not.
+ This parameter can be a value of @ref I2S_MCLK_Output */
+
+ uint32_t AudioFrequency; /*!< Specifies the frequency selected for the I2S communication.
+ This parameter can be a value of @ref I2S_Audio_Frequency */
+
+ uint16_t CLKPOL; /*!< Specifies the idle state of the I2S clock.
+ This parameter can be a value of @ref I2S_Clock_Polarity */
+} I2S_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Exported_Constants
+ * @{
+ */
+
+#define IS_SPI_PERIPH(PERIPH) (((PERIPH) == SPI1) || ((PERIPH) == SPI2) || ((PERIPH) == SPI3))
+
+#define IS_SPI_2OR3_PERIPH(PERIPH) (((PERIPH) == SPI2) || ((PERIPH) == SPI3))
+
+/** @addtogroup SPI_data_direction
+ * @{
+ */
+
+#define SPI_DIR_DOUBLELINE_FULLDUPLEX ((uint16_t)0x0000)
+#define SPI_DIR_DOUBLELINE_RONLY ((uint16_t)0x0400)
+#define SPI_DIR_SINGLELINE_RX ((uint16_t)0x8000)
+#define SPI_DIR_SINGLELINE_TX ((uint16_t)0xC000)
+#define IS_SPI_DIR_MODE(MODE) \
+ (((MODE) == SPI_DIR_DOUBLELINE_FULLDUPLEX) || ((MODE) == SPI_DIR_DOUBLELINE_RONLY) \
+ || ((MODE) == SPI_DIR_SINGLELINE_RX) || ((MODE) == SPI_DIR_SINGLELINE_TX))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_mode
+ * @{
+ */
+
+#define SPI_MODE_MASTER ((uint16_t)0x0104)
+#define SPI_MODE_SLAVE ((uint16_t)0x0000)
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_MASTER) || ((MODE) == SPI_MODE_SLAVE))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_data_size
+ * @{
+ */
+
+#define SPI_DATA_SIZE_16BITS ((uint16_t)0x0800)
+#define SPI_DATA_SIZE_8BITS ((uint16_t)0x0000)
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATA_SIZE_16BITS) || ((DATASIZE) == SPI_DATA_SIZE_8BITS))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Clock_Polarity
+ * @{
+ */
+
+#define SPI_CLKPOL_LOW ((uint16_t)0x0000)
+#define SPI_CLKPOL_HIGH ((uint16_t)0x0002)
+#define IS_SPI_CLKPOL(CPOL) (((CPOL) == SPI_CLKPOL_LOW) || ((CPOL) == SPI_CLKPOL_HIGH))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Clock_Phase
+ * @{
+ */
+
+#define SPI_CLKPHA_FIRST_EDGE ((uint16_t)0x0000)
+#define SPI_CLKPHA_SECOND_EDGE ((uint16_t)0x0001)
+#define IS_SPI_CLKPHA(CPHA) (((CPHA) == SPI_CLKPHA_FIRST_EDGE) || ((CPHA) == SPI_CLKPHA_SECOND_EDGE))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Slave_Select_management
+ * @{
+ */
+
+#define SPI_NSS_SOFT ((uint16_t)0x0200)
+#define SPI_NSS_HARD ((uint16_t)0x0000)
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || ((NSS) == SPI_NSS_HARD))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_BaudRate_Prescaler
+ * @{
+ */
+
+#define SPI_BR_PRESCALER_2 ((uint16_t)0x0000)
+#define SPI_BR_PRESCALER_4 ((uint16_t)0x0008)
+#define SPI_BR_PRESCALER_8 ((uint16_t)0x0010)
+#define SPI_BR_PRESCALER_16 ((uint16_t)0x0018)
+#define SPI_BR_PRESCALER_32 ((uint16_t)0x0020)
+#define SPI_BR_PRESCALER_64 ((uint16_t)0x0028)
+#define SPI_BR_PRESCALER_128 ((uint16_t)0x0030)
+#define SPI_BR_PRESCALER_256 ((uint16_t)0x0038)
+#define IS_SPI_BR_PRESCALER(PRESCALER) \
+ (((PRESCALER) == SPI_BR_PRESCALER_2) || ((PRESCALER) == SPI_BR_PRESCALER_4) || ((PRESCALER) == SPI_BR_PRESCALER_8) \
+ || ((PRESCALER) == SPI_BR_PRESCALER_16) || ((PRESCALER) == SPI_BR_PRESCALER_32) \
+ || ((PRESCALER) == SPI_BR_PRESCALER_64) || ((PRESCALER) == SPI_BR_PRESCALER_128) \
+ || ((PRESCALER) == SPI_BR_PRESCALER_256))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_MSB_LSB_transmission
+ * @{
+ */
+
+#define SPI_FB_MSB ((uint16_t)0x0000)
+#define SPI_FB_LSB ((uint16_t)0x0080)
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FB_MSB) || ((BIT) == SPI_FB_LSB))
+/**
+ * @}
+ */
+
+/** @addtogroup I2sMode
+ * @{
+ */
+
+#define I2S_MODE_SlAVE_TX ((uint16_t)0x0000)
+#define I2S_MODE_SlAVE_RX ((uint16_t)0x0100)
+#define I2S_MODE_MASTER_TX ((uint16_t)0x0200)
+#define I2S_MODE_MASTER_RX ((uint16_t)0x0300)
+#define IS_I2S_MODE(MODE) \
+ (((MODE) == I2S_MODE_SlAVE_TX) || ((MODE) == I2S_MODE_SlAVE_RX) || ((MODE) == I2S_MODE_MASTER_TX) \
+ || ((MODE) == I2S_MODE_MASTER_RX))
+/**
+ * @}
+ */
+
+/** @addtogroup Standard
+ * @{
+ */
+
+#define I2S_STD_PHILLIPS ((uint16_t)0x0000)
+#define I2S_STD_MSB_ALIGN ((uint16_t)0x0010)
+#define I2S_STD_LSB_ALIGN ((uint16_t)0x0020)
+#define I2S_STD_PCM_SHORTFRAME ((uint16_t)0x0030)
+#define I2S_STD_PCM_LONGFRAME ((uint16_t)0x00B0)
+#define IS_I2S_STANDARD(STANDARD) \
+ (((STANDARD) == I2S_STD_PHILLIPS) || ((STANDARD) == I2S_STD_MSB_ALIGN) || ((STANDARD) == I2S_STD_LSB_ALIGN) \
+ || ((STANDARD) == I2S_STD_PCM_SHORTFRAME) || ((STANDARD) == I2S_STD_PCM_LONGFRAME))
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Data_Format
+ * @{
+ */
+
+#define I2S_DATA_FMT_16BITS ((uint16_t)0x0000)
+#define I2S_DATA_FMT_16BITS_EXTENDED ((uint16_t)0x0001)
+#define I2S_DATA_FMT_24BITS ((uint16_t)0x0003)
+#define I2S_DATA_FMT_32BITS ((uint16_t)0x0005)
+#define IS_I2S_DATA_FMT(FORMAT) \
+ (((FORMAT) == I2S_DATA_FMT_16BITS) || ((FORMAT) == I2S_DATA_FMT_16BITS_EXTENDED) \
+ || ((FORMAT) == I2S_DATA_FMT_24BITS) || ((FORMAT) == I2S_DATA_FMT_32BITS))
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_MCLK_Output
+ * @{
+ */
+
+#define I2S_MCLK_ENABLE ((uint16_t)0x0200)
+#define I2S_MCLK_DISABLE ((uint16_t)0x0000)
+#define IS_I2S_MCLK_ENABLE(OUTPUT) (((OUTPUT) == I2S_MCLK_ENABLE) || ((OUTPUT) == I2S_MCLK_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Audio_Frequency
+ * @{
+ */
+
+#define I2S_AUDIO_FREQ_192K ((uint32_t)192000)
+#define I2S_AUDIO_FREQ_96K ((uint32_t)96000)
+#define I2S_AUDIO_FREQ_48K ((uint32_t)48000)
+#define I2S_AUDIO_FREQ_44K ((uint32_t)44100)
+#define I2S_AUDIO_FREQ_32K ((uint32_t)32000)
+#define I2S_AUDIO_FREQ_22K ((uint32_t)22050)
+#define I2S_AUDIO_FREQ_16K ((uint32_t)16000)
+#define I2S_AUDIO_FREQ_11K ((uint32_t)11025)
+#define I2S_AUDIO_FREQ_8K ((uint32_t)8000)
+#define I2S_AUDIO_FREQ_DEFAULT ((uint32_t)2)
+
+#define IS_I2S_AUDIO_FREQ(FREQ) \
+ ((((FREQ) >= I2S_AUDIO_FREQ_8K) && ((FREQ) <= I2S_AUDIO_FREQ_192K)) || ((FREQ) == I2S_AUDIO_FREQ_DEFAULT))
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Clock_Polarity
+ * @{
+ */
+
+#define I2S_CLKPOL_LOW ((uint16_t)0x0000)
+#define I2S_CLKPOL_HIGH ((uint16_t)0x0008)
+#define IS_I2S_CLKPOL(CPOL) (((CPOL) == I2S_CLKPOL_LOW) || ((CPOL) == I2S_CLKPOL_HIGH))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_I2S_DMA_transfer_requests
+ * @{
+ */
+
+#define SPI_I2S_DMA_TX ((uint16_t)0x0002)
+#define SPI_I2S_DMA_RX ((uint16_t)0x0001)
+#define IS_SPI_I2S_DMA(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_NSS_internal_software_management
+ * @{
+ */
+
+#define SPI_NSS_HIGH ((uint16_t)0x0100)
+#define SPI_NSS_LOW ((uint16_t)0xFEFF)
+#define IS_SPI_NSS_LEVEL(INTERNAL) (((INTERNAL) == SPI_NSS_HIGH) || ((INTERNAL) == SPI_NSS_LOW))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_CRC_Transmit_Receive
+ * @{
+ */
+
+#define SPI_CRC_TX ((uint8_t)0x00)
+#define SPI_CRC_RX ((uint8_t)0x01)
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_TX) || ((CRC) == SPI_CRC_RX))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_direction_transmit_receive
+ * @{
+ */
+
+#define SPI_BIDIRECTION_RX ((uint16_t)0xBFFF)
+#define SPI_BIDIRECTION_TX ((uint16_t)0x4000)
+#define IS_SPI_BIDIRECTION(DIRECTION) (((DIRECTION) == SPI_BIDIRECTION_RX) || ((DIRECTION) == SPI_BIDIRECTION_TX))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_I2S_interrupts_definition
+ * @{
+ */
+
+#define SPI_I2S_INT_TE ((uint8_t)0x71)
+#define SPI_I2S_INT_RNE ((uint8_t)0x60)
+#define SPI_I2S_INT_ERR ((uint8_t)0x50)
+#define IS_SPI_I2S_CONFIG_INT(IT) (((IT) == SPI_I2S_INT_TE) || ((IT) == SPI_I2S_INT_RNE) || ((IT) == SPI_I2S_INT_ERR))
+#define SPI_I2S_INT_OVER ((uint8_t)0x56)
+#define SPI_INT_MODERR ((uint8_t)0x55)
+#define SPI_INT_CRCERR ((uint8_t)0x54)
+#define I2S_INT_UNDER ((uint8_t)0x53)
+#define IS_SPI_I2S_CLR_INT(IT) (((IT) == SPI_INT_CRCERR))
+#define IS_SPI_I2S_GET_INT(IT) \
+ (((IT) == SPI_I2S_INT_RNE) || ((IT) == SPI_I2S_INT_TE) || ((IT) == I2S_INT_UNDER) || ((IT) == SPI_INT_CRCERR) \
+ || ((IT) == SPI_INT_MODERR) || ((IT) == SPI_I2S_INT_OVER))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_I2S_flags_definition
+ * @{
+ */
+
+#define SPI_I2S_RNE_FLAG ((uint16_t)0x0001)
+#define SPI_I2S_TE_FLAG ((uint16_t)0x0002)
+#define I2S_CHSIDE_FLAG ((uint16_t)0x0004)
+#define I2S_UNDER_FLAG ((uint16_t)0x0008)
+#define SPI_CRCERR_FLAG ((uint16_t)0x0010)
+#define SPI_MODERR_FLAG ((uint16_t)0x0020)
+#define SPI_I2S_OVER_FLAG ((uint16_t)0x0040)
+#define SPI_I2S_BUSY_FLAG ((uint16_t)0x0080)
+#define IS_SPI_I2S_CLR_FLAG(FLAG) (((FLAG) == SPI_CRCERR_FLAG))
+#define IS_SPI_I2S_GET_FLAG(FLAG) \
+ (((FLAG) == SPI_I2S_BUSY_FLAG) || ((FLAG) == SPI_I2S_OVER_FLAG) || ((FLAG) == SPI_MODERR_FLAG) \
+ || ((FLAG) == SPI_CRCERR_FLAG) || ((FLAG) == I2S_UNDER_FLAG) || ((FLAG) == I2S_CHSIDE_FLAG) \
+ || ((FLAG) == SPI_I2S_TE_FLAG) || ((FLAG) == SPI_I2S_RNE_FLAG))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_CRC_polynomial
+ * @{
+ */
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Exported_Functions
+ * @{
+ */
+
+void SPI_I2S_DeInit(SPI_Module* SPIx);
+void SPI_Init(SPI_Module* SPIx, SPI_InitType* SPI_InitStruct);
+void I2S_Init(SPI_Module* SPIx, I2S_InitType* I2S_InitStruct);
+void SPI_InitStruct(SPI_InitType* SPI_InitStruct);
+void I2S_InitStruct(I2S_InitType* I2S_InitStruct);
+void SPI_Enable(SPI_Module* SPIx, FunctionalState Cmd);
+void I2S_Enable(SPI_Module* SPIx, FunctionalState Cmd);
+void SPI_I2S_EnableInt(SPI_Module* SPIx, uint8_t SPI_I2S_IT, FunctionalState Cmd);
+void SPI_I2S_EnableDma(SPI_Module* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState Cmd);
+void SPI_I2S_TransmitData(SPI_Module* SPIx, uint16_t Data);
+uint16_t SPI_I2S_ReceiveData(SPI_Module* SPIx);
+void SPI_SetNssLevel(SPI_Module* SPIx, uint16_t SPI_NSSInternalSoft);
+void SPI_SSOutputEnable(SPI_Module* SPIx, FunctionalState Cmd);
+void SPI_ConfigDataLen(SPI_Module* SPIx, uint16_t DataLen);
+void SPI_TransmitCrcNext(SPI_Module* SPIx);
+void SPI_EnableCalculateCrc(SPI_Module* SPIx, FunctionalState Cmd);
+uint16_t SPI_GetCRCDat(SPI_Module* SPIx, uint8_t SPI_CRC);
+uint16_t SPI_GetCRCPoly(SPI_Module* SPIx);
+void SPI_ConfigBidirectionalMode(SPI_Module* SPIx, uint16_t DataDirection);
+FlagStatus SPI_I2S_GetStatus(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG);
+void SPI_I2S_ClrCRCErrFlag(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG);
+INTStatus SPI_I2S_GetIntStatus(SPI_Module* SPIx, uint8_t SPI_I2S_IT);
+void SPI_I2S_ClrITPendingBit(SPI_Module* SPIx, uint8_t SPI_I2S_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32WB452_SPI_H__ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_tim.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_tim.h
new file mode 100644
index 0000000000..0222ad9146
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_tim.h
@@ -0,0 +1,1113 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_tim.h
+ * @author Nations
+ * @version v1.0.2
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32WB452_TIM_H__
+#define __N32WB452_TIM_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32wb452.h"
+#include "stdbool.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup TIM
+ * @{
+ */
+
+/** @addtogroup TIM_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief TIM Time Base Init structure definition
+ * @note This structure is used with all TIMx except for TIM6 and TIM7.
+ */
+
+typedef struct
+{
+ uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
+ This parameter can be a number between 0x0000 and 0xFFFF */
+
+ uint16_t CntMode; /*!< Specifies the counter mode.
+ This parameter can be a value of @ref TIM_Counter_Mode */
+
+ uint16_t Period; /*!< Specifies the period value to be loaded into the active
+ Auto-Reload Register at the next update event.
+ This parameter must be a number between 0x0000 and 0xFFFF. */
+
+ uint16_t ClkDiv; /*!< Specifies the clock division.
+ This parameter can be a value of @ref TIM_Clock_Division_CKD */
+
+ uint8_t RepetCnt; /*!< Specifies the repetition counter value. Each time the REPCNT downcounter
+ reaches zero, an update event is generated and counting restarts
+ from the REPCNT value (N).
+ This means in PWM mode that (N+1) corresponds to:
+ - the number of PWM periods in edge-aligned mode
+ - the number of half PWM period in center-aligned mode
+ This parameter must be a number between 0x00 and 0xFF.
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ bool CapCh1FromCompEn; /*!< channel 1 select capture in from comp if 1, from IOM if 0
+ Tim1,Tim8,Tim2,Tim3,Tim4,Tim5 valid*/
+ bool CapCh2FromCompEn; /*!< channel 2 select capture in from comp if 1, from IOM if 0
+ Tim2,Tim3,Tim4,Tim5 valid*/
+ bool CapCh3FromCompEn; /*!< channel 3 select capture in from comp if 1, from IOM if 0
+ Tim2,Tim3,Tim4,Tim5 valid*/
+ bool CapCh4FromCompEn; /*!< channel 4 select capture in from comp if 1, from IOM if 0
+ Tim2,Tim3,Tim4 valid*/
+ bool CapEtrClrFromCompEn; /*!< etr clearref select from comp if 1, from ETR IOM if 0
+ Tim2,Tim3,Tim4 valid*/
+ bool CapEtrSelFromTscEn; /*!< etr select from TSC if 1, from IOM if 0
+ Tim2,Tim4 valid*/
+} TIM_TimeBaseInitType;
+
+/**
+ * @brief TIM Output Compare Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t OcMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+ uint16_t OutputState; /*!< Specifies the TIM Output Compare state.
+ This parameter can be a value of @ref TIM_Output_Compare_state */
+
+ uint16_t OutputNState; /*!< Specifies the TIM complementary Output Compare state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_state
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint16_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between 0x0000 and 0xFFFF */
+
+ uint16_t OcPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+ uint16_t OcNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint16_t OcIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint16_t OcNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+} OCInitType;
+
+/**
+ * @brief TIM Input Capture Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t Channel; /*!< Specifies the TIM channel.
+ This parameter can be a value of @ref Channel */
+
+ uint16_t IcPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint16_t IcSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint16_t IcPrescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint16_t IcFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between 0x0 and 0xF */
+} TIM_ICInitType;
+
+/**
+ * @brief BKDT structure definition
+ * @note This structure is used only with TIM1 and TIM8.
+ */
+
+typedef struct
+{
+ uint16_t OssrState; /*!< Specifies the Off-State selection used in Run mode.
+ This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
+
+ uint16_t OssiState; /*!< Specifies the Off-State used in Idle state.
+ This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
+
+ uint16_t LockLevel; /*!< Specifies the LOCK level parameters.
+ This parameter can be a value of @ref Lock_level */
+
+ uint16_t DeadTime; /*!< Specifies the delay time between the switching-off and the
+ switching-on of the outputs.
+ This parameter can be a number between 0x00 and 0xFF */
+
+ uint16_t Break; /*!< Specifies whether the TIM Break input is enabled or not.
+ This parameter can be a value of @ref Break_Input_enable_disable */
+
+ uint16_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
+ This parameter can be a value of @ref Break_Polarity */
+
+ uint16_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+ bool IomBreakEn; /*!< EXTEND Mode valid, open iom as break in*/
+ bool LockUpBreakEn; /*!< EXTEND Mode valid, open lockup(haldfault) as break in*/
+ bool PvdBreakEn; /*!< EXTEND Mode valid, open pvd(sys voltage too high or too low) as break in*/
+} TIM_BDTRInitType;
+
+/** @addtogroup TIM_Exported_constants
+ * @{
+ */
+
+#define IsTimAllModule(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) \
+ || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8))
+
+/* LIST1: TIM 1 and 8 */
+#define IsTimList1Module(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM8))
+
+/* LIST2: TIM 1, 8 */
+#define IsTimList2Module(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM8))
+
+/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */
+#define IsTimList3Module(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) \
+ || ((PERIPH) == TIM8))
+
+/* LIST4: TIM 1, 2, 3, 4, 5, 8 */
+#define IsTimList4Module(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) \
+ || ((PERIPH) == TIM8))
+
+/* LIST5: TIM 1, 2, 3, 4, 5, 8 */
+#define IsTimList5Module(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) \
+ || ((PERIPH) == TIM8))
+
+/* LIST6: TIM 1, 2, 3, 4, 5, 8 */
+#define IsTimList6Module(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) \
+ || ((PERIPH) == TIM8))
+
+/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8 */
+#define IsTimList7Module(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) \
+ || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8))
+
+/* LIST8: TIM 1, 2, 3, 4, 5, 8 */
+#define IsTimList8Module(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) \
+ || ((PERIPH) == TIM8))
+
+/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8 */
+#define IsTimList9Module(PERIPH) \
+ (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) \
+ || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8))
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_and_PWM_modes
+ * @{
+ */
+
+#define TIM_OCMODE_TIMING ((uint16_t)0x0000)
+#define TIM_OCMODE_ACTIVE ((uint16_t)0x0010)
+#define TIM_OCMODE_INACTIVE ((uint16_t)0x0020)
+#define TIM_OCMODE_TOGGLE ((uint16_t)0x0030)
+#define TIM_OCMODE_PWM1 ((uint16_t)0x0060)
+#define TIM_OCMODE_PWM2 ((uint16_t)0x0070)
+#define IsTimOcMode(MODE) \
+ (((MODE) == TIM_OCMODE_TIMING) || ((MODE) == TIM_OCMODE_ACTIVE) || ((MODE) == TIM_OCMODE_INACTIVE) \
+ || ((MODE) == TIM_OCMODE_TOGGLE) || ((MODE) == TIM_OCMODE_PWM1) || ((MODE) == TIM_OCMODE_PWM2))
+#define IsTimOc(MODE) \
+ (((MODE) == TIM_OCMODE_TIMING) || ((MODE) == TIM_OCMODE_ACTIVE) || ((MODE) == TIM_OCMODE_INACTIVE) \
+ || ((MODE) == TIM_OCMODE_TOGGLE) || ((MODE) == TIM_OCMODE_PWM1) || ((MODE) == TIM_OCMODE_PWM2) \
+ || ((MODE) == TIM_FORCED_ACTION_ACTIVE) || ((MODE) == TIM_FORCED_ACTION_INACTIVE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_One_Pulse_Mode
+ * @{
+ */
+
+#define TIM_OPMODE_SINGLE ((uint16_t)0x0008)
+#define TIM_OPMODE_REPET ((uint16_t)0x0000)
+#define IsTimOpMOde(MODE) (((MODE) == TIM_OPMODE_SINGLE) || ((MODE) == TIM_OPMODE_REPET))
+/**
+ * @}
+ */
+
+/** @addtogroup Channel
+ * @{
+ */
+
+#define TIM_CH_1 ((uint16_t)0x0000)
+#define TIM_CH_2 ((uint16_t)0x0004)
+#define TIM_CH_3 ((uint16_t)0x0008)
+#define TIM_CH_4 ((uint16_t)0x000C)
+#define IsTimCh(CHANNEL) \
+ (((CHANNEL) == TIM_CH_1) || ((CHANNEL) == TIM_CH_2) || ((CHANNEL) == TIM_CH_3) || ((CHANNEL) == TIM_CH_4))
+#define IsTimPwmInCh(CHANNEL) (((CHANNEL) == TIM_CH_1) || ((CHANNEL) == TIM_CH_2))
+#define IsTimComplementaryCh(CHANNEL) (((CHANNEL) == TIM_CH_1) || ((CHANNEL) == TIM_CH_2) || ((CHANNEL) == TIM_CH_3))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Clock_Division_CKD
+ * @{
+ */
+
+#define TIM_CLK_DIV1 ((uint16_t)0x0000)
+#define TIM_CLK_DIV2 ((uint16_t)0x0100)
+#define TIM_CLK_DIV4 ((uint16_t)0x0200)
+#define IsTimClkDiv(DIV) (((DIV) == TIM_CLK_DIV1) || ((DIV) == TIM_CLK_DIV2) || ((DIV) == TIM_CLK_DIV4))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Counter_Mode
+ * @{
+ */
+
+#define TIM_CNT_MODE_UP ((uint16_t)0x0000)
+#define TIM_CNT_MODE_DOWN ((uint16_t)0x0010)
+#define TIM_CNT_MODE_CENTER_ALIGN1 ((uint16_t)0x0020)
+#define TIM_CNT_MODE_CENTER_ALIGN2 ((uint16_t)0x0040)
+#define TIM_CNT_MODE_CENTER_ALIGN3 ((uint16_t)0x0060)
+#define IsTimCntMode(MODE) \
+ (((MODE) == TIM_CNT_MODE_UP) || ((MODE) == TIM_CNT_MODE_DOWN) || ((MODE) == TIM_CNT_MODE_CENTER_ALIGN1) \
+ || ((MODE) == TIM_CNT_MODE_CENTER_ALIGN2) || ((MODE) == TIM_CNT_MODE_CENTER_ALIGN3))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_Polarity
+ * @{
+ */
+
+#define TIM_OC_POLARITY_HIGH ((uint16_t)0x0000)
+#define TIM_OC_POLARITY_LOW ((uint16_t)0x0002)
+#define IsTimOcPolarity(POLARITY) (((POLARITY) == TIM_OC_POLARITY_HIGH) || ((POLARITY) == TIM_OC_POLARITY_LOW))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_N_Polarity
+ * @{
+ */
+
+#define TIM_OCN_POLARITY_HIGH ((uint16_t)0x0000)
+#define TIM_OCN_POLARITY_LOW ((uint16_t)0x0008)
+#define IsTimOcnPolarity(POLARITY) (((POLARITY) == TIM_OCN_POLARITY_HIGH) || ((POLARITY) == TIM_OCN_POLARITY_LOW))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_state
+ * @{
+ */
+
+#define TIM_OUTPUT_STATE_DISABLE ((uint16_t)0x0000)
+#define TIM_OUTPUT_STATE_ENABLE ((uint16_t)0x0001)
+#define IsTimOutputState(STATE) (((STATE) == TIM_OUTPUT_STATE_DISABLE) || ((STATE) == TIM_OUTPUT_STATE_ENABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_N_state
+ * @{
+ */
+
+#define TIM_OUTPUT_NSTATE_DISABLE ((uint16_t)0x0000)
+#define TIM_OUTPUT_NSTATE_ENABLE ((uint16_t)0x0004)
+#define IsTimOutputNState(STATE) (((STATE) == TIM_OUTPUT_NSTATE_DISABLE) || ((STATE) == TIM_OUTPUT_NSTATE_ENABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Capture_Compare_state
+ * @{
+ */
+
+#define TIM_CAP_CMP_ENABLE ((uint16_t)0x0001)
+#define TIM_CAP_CMP_DISABLE ((uint16_t)0x0000)
+#define IsTimCapCmpState(CCX) (((CCX) == TIM_CAP_CMP_ENABLE) || ((CCX) == TIM_CAP_CMP_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Capture_Compare_N_state
+ * @{
+ */
+
+#define TIM_CAP_CMP_N_ENABLE ((uint16_t)0x0004)
+#define TIM_CAP_CMP_N_DISABLE ((uint16_t)0x0000)
+#define IsTimCapCmpNState(CCXN) (((CCXN) == TIM_CAP_CMP_N_ENABLE) || ((CCXN) == TIM_CAP_CMP_N_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup Break_Input_enable_disable
+ * @{
+ */
+
+#define TIM_BREAK_IN_ENABLE ((uint16_t)0x1000)
+#define TIM_BREAK_IN_DISABLE ((uint16_t)0x0000)
+#define IsTimBreakInState(STATE) (((STATE) == TIM_BREAK_IN_ENABLE) || ((STATE) == TIM_BREAK_IN_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup Break_Polarity
+ * @{
+ */
+
+#define TIM_BREAK_POLARITY_LOW ((uint16_t)0x0000)
+#define TIM_BREAK_POLARITY_HIGH ((uint16_t)0x2000)
+#define IsTimBreakPalarity(POLARITY) (((POLARITY) == TIM_BREAK_POLARITY_LOW) || ((POLARITY) == TIM_BREAK_POLARITY_HIGH))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_AOE_Bit_Set_Reset
+ * @{
+ */
+
+#define TIM_AUTO_OUTPUT_ENABLE ((uint16_t)0x4000)
+#define TIM_AUTO_OUTPUT_DISABLE ((uint16_t)0x0000)
+#define IsTimAutoOutputState(STATE) (((STATE) == TIM_AUTO_OUTPUT_ENABLE) || ((STATE) == TIM_AUTO_OUTPUT_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup Lock_level
+ * @{
+ */
+
+#define TIM_LOCK_LEVEL_OFF ((uint16_t)0x0000)
+#define TIM_LOCK_LEVEL_1 ((uint16_t)0x0100)
+#define TIM_LOCK_LEVEL_2 ((uint16_t)0x0200)
+#define TIM_LOCK_LEVEL_3 ((uint16_t)0x0300)
+#define IsTimLockLevel(LEVEL) \
+ (((LEVEL) == TIM_LOCK_LEVEL_OFF) || ((LEVEL) == TIM_LOCK_LEVEL_1) || ((LEVEL) == TIM_LOCK_LEVEL_2) \
+ || ((LEVEL) == TIM_LOCK_LEVEL_3))
+/**
+ * @}
+ */
+
+/** @addtogroup OSSI_Off_State_Selection_for_Idle_mode_state
+ * @{
+ */
+
+#define TIM_OSSI_STATE_ENABLE ((uint16_t)0x0400)
+#define TIM_OSSI_STATE_DISABLE ((uint16_t)0x0000)
+#define IsTimOssiState(STATE) (((STATE) == TIM_OSSI_STATE_ENABLE) || ((STATE) == TIM_OSSI_STATE_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup OSSR_Off_State_Selection_for_Run_mode_state
+ * @{
+ */
+
+#define TIM_OSSR_STATE_ENABLE ((uint16_t)0x0800)
+#define TIM_OSSR_STATE_DISABLE ((uint16_t)0x0000)
+#define IsTimOssrState(STATE) (((STATE) == TIM_OSSR_STATE_ENABLE) || ((STATE) == TIM_OSSR_STATE_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_Idle_State
+ * @{
+ */
+
+#define TIM_OC_IDLE_STATE_SET ((uint16_t)0x0100)
+#define TIM_OC_IDLE_STATE_RESET ((uint16_t)0x0000)
+#define IsTimOcIdleState(STATE) (((STATE) == TIM_OC_IDLE_STATE_SET) || ((STATE) == TIM_OC_IDLE_STATE_RESET))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_N_Idle_State
+ * @{
+ */
+
+#define TIM_OCN_IDLE_STATE_SET ((uint16_t)0x0200)
+#define TIM_OCN_IDLE_STATE_RESET ((uint16_t)0x0000)
+#define IsTimOcnIdleState(STATE) (((STATE) == TIM_OCN_IDLE_STATE_SET) || ((STATE) == TIM_OCN_IDLE_STATE_RESET))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Input_Capture_Polarity
+ * @{
+ */
+
+#define TIM_IC_POLARITY_RISING ((uint16_t)0x0000)
+#define TIM_IC_POLARITY_FALLING ((uint16_t)0x0002)
+#define TIM_IC_POLARITY_BOTHEDGE ((uint16_t)0x000A)
+#define IsTimIcPalaritySingleEdge(POLARITY) \
+ (((POLARITY) == TIM_IC_POLARITY_RISING) || ((POLARITY) == TIM_IC_POLARITY_FALLING))
+#define IsTimIcPolarityAnyEdge(POLARITY) \
+ (((POLARITY) == TIM_IC_POLARITY_RISING) || ((POLARITY) == TIM_IC_POLARITY_FALLING) \
+ || ((POLARITY) == TIM_IC_POLARITY_BOTHEDGE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Input_Capture_Selection
+ * @{
+ */
+
+#define TIM_IC_SELECTION_DIRECTTI \
+ ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be \
+ connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_IC_SELECTION_INDIRECTTI \
+ ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be \
+ connected to IC2, IC1, IC4 or IC3, respectively. */
+#define TIM_IC_SELECTION_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
+#define IsTimIcSelection(SELECTION) \
+ (((SELECTION) == TIM_IC_SELECTION_DIRECTTI) || ((SELECTION) == TIM_IC_SELECTION_INDIRECTTI) \
+ || ((SELECTION) == TIM_IC_SELECTION_TRC))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Input_Capture_Prescaler
+ * @{
+ */
+
+#define TIM_IC_PSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. \
+ */
+#define TIM_IC_PSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
+#define TIM_IC_PSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
+#define TIM_IC_PSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
+#define IsTimIcPrescaler(PRESCALER) \
+ (((PRESCALER) == TIM_IC_PSC_DIV1) || ((PRESCALER) == TIM_IC_PSC_DIV2) || ((PRESCALER) == TIM_IC_PSC_DIV4) \
+ || ((PRESCALER) == TIM_IC_PSC_DIV8))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_interrupt_sources
+ * @{
+ */
+
+#define TIM_INT_UPDATE ((uint16_t)0x0001)
+#define TIM_INT_CC1 ((uint16_t)0x0002)
+#define TIM_INT_CC2 ((uint16_t)0x0004)
+#define TIM_INT_CC3 ((uint16_t)0x0008)
+#define TIM_INT_CC4 ((uint16_t)0x0010)
+#define TIM_INT_COM ((uint16_t)0x0020)
+#define TIM_INT_TRIG ((uint16_t)0x0040)
+#define TIM_INT_BREAK ((uint16_t)0x0080)
+#define IsTimInt(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
+
+#define IsTimGetInt(IT) \
+ (((IT) == TIM_INT_UPDATE) || ((IT) == TIM_INT_CC1) || ((IT) == TIM_INT_CC2) || ((IT) == TIM_INT_CC3) \
+ || ((IT) == TIM_INT_CC4) || ((IT) == TIM_INT_COM) || ((IT) == TIM_INT_TRIG) || ((IT) == TIM_INT_BREAK))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_DMA_Base_address
+ * @{
+ */
+
+#define TIM_DMABASE_CTRL1 ((uint16_t)0x0000)
+#define TIM_DMABASE_CTRL2 ((uint16_t)0x0001)
+#define TIM_DMABASE_SMCTRL ((uint16_t)0x0002)
+#define TIM_DMABASE_DMAINTEN ((uint16_t)0x0003)
+#define TIM_DMABASE_STS ((uint16_t)0x0004)
+#define TIM_DMABASE_EVTGEN ((uint16_t)0x0005)
+#define TIM_DMABASE_CAPCMPMOD1 ((uint16_t)0x0006)
+#define TIM_DMABASE_CAPCMPMOD2 ((uint16_t)0x0007)
+#define TIM_DMABASE_CAPCMPEN ((uint16_t)0x0008)
+#define TIM_DMABASE_CNT ((uint16_t)0x0009)
+#define TIM_DMABASE_PSC ((uint16_t)0x000A)
+#define TIM_DMABASE_AR ((uint16_t)0x000B)
+#define TIM_DMABASE_REPCNT ((uint16_t)0x000C)
+#define TIM_DMABASE_CAPCMPDAT1 ((uint16_t)0x000D)
+#define TIM_DMABASE_CAPCMPDAT2 ((uint16_t)0x000E)
+#define TIM_DMABASE_CAPCMPDAT3 ((uint16_t)0x000F)
+#define TIM_DMABASE_CAPCMPDAT4 ((uint16_t)0x0010)
+#define TIM_DMABASE_BKDT ((uint16_t)0x0011)
+#define TIM_DMABASE_DMACTRL ((uint16_t)0x0012)
+
+
+#define IsTimDmaBase(BASE) \
+ (((BASE) == TIM_DMABASE_CTRL1) || ((BASE) == TIM_DMABASE_CTRL2) || ((BASE) == TIM_DMABASE_SMCTRL) \
+ || ((BASE) == TIM_DMABASE_DMAINTEN) || ((BASE) == TIM_DMABASE_STS) || ((BASE) == TIM_DMABASE_EVTGEN) \
+ || ((BASE) == TIM_DMABASE_CAPCMPMOD1) || ((BASE) == TIM_DMABASE_CAPCMPMOD2) \
+ || ((BASE) == TIM_DMABASE_CAPCMPEN) || ((BASE) == TIM_DMABASE_CNT) || ((BASE) == TIM_DMABASE_PSC) \
+ || ((BASE) == TIM_DMABASE_AR) || ((BASE) == TIM_DMABASE_REPCNT) || ((BASE) == TIM_DMABASE_CAPCMPDAT1) \
+ || ((BASE) == TIM_DMABASE_CAPCMPDAT2) || ((BASE) == TIM_DMABASE_CAPCMPDAT3) || ((BASE) == TIM_DMABASE_CAPCMPDAT4) \
+ || ((BASE) == TIM_DMABASE_BKDT)|| ((BASE) == TIM_DMABASE_DMACTRL))
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_DMA_Burst_Length
+ * @{
+ */
+
+#define TIM_DMABURST_LENGTH_1TRANSFER ((uint16_t)0x0000)
+#define TIM_DMABURST_LENGTH_2TRANSFERS ((uint16_t)0x0100)
+#define TIM_DMABURST_LENGTH_3TRANSFERS ((uint16_t)0x0200)
+#define TIM_DMABURST_LENGTH_4TRANSFERS ((uint16_t)0x0300)
+#define TIM_DMABURST_LENGTH_5TRANSFERS ((uint16_t)0x0400)
+#define TIM_DMABURST_LENGTH_6TRANSFERS ((uint16_t)0x0500)
+#define TIM_DMABURST_LENGTH_7TRANSFERS ((uint16_t)0x0600)
+#define TIM_DMABURST_LENGTH_8TRANSFERS ((uint16_t)0x0700)
+#define TIM_DMABURST_LENGTH_9TRANSFERS ((uint16_t)0x0800)
+#define TIM_DMABURST_LENGTH_10TRANSFERS ((uint16_t)0x0900)
+#define TIM_DMABURST_LENGTH_11TRANSFERS ((uint16_t)0x0A00)
+#define TIM_DMABURST_LENGTH_12TRANSFERS ((uint16_t)0x0B00)
+#define TIM_DMABURST_LENGTH_13TRANSFERS ((uint16_t)0x0C00)
+#define TIM_DMABURST_LENGTH_14TRANSFERS ((uint16_t)0x0D00)
+#define TIM_DMABURST_LENGTH_15TRANSFERS ((uint16_t)0x0E00)
+#define TIM_DMABURST_LENGTH_16TRANSFERS ((uint16_t)0x0F00)
+#define TIM_DMABURST_LENGTH_17TRANSFERS ((uint16_t)0x1000)
+#define TIM_DMABURST_LENGTH_18TRANSFERS ((uint16_t)0x1100)
+#define TIM_DMABURST_LENGTH_19TRANSFERS ((uint16_t)0x1200)
+#define TIM_DMABURST_LENGTH_20TRANSFERS ((uint16_t)0x1300)
+#define TIM_DMABURST_LENGTH_21TRANSFERS ((uint16_t)0x1400)
+#define IsTimDmaLength(LENGTH) \
+ (((LENGTH) == TIM_DMABURST_LENGTH_1TRANSFER) || ((LENGTH) == TIM_DMABURST_LENGTH_2TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_3TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_4TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_5TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_6TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_7TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_8TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_9TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_10TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_11TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_12TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_13TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_14TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_15TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_16TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_17TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_18TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_19TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_20TRANSFERS) \
+ || ((LENGTH) == TIM_DMABURST_LENGTH_21TRANSFERS))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_DMA_sources
+ * @{
+ */
+
+#define TIM_DMA_UPDATE ((uint16_t)0x0100)
+#define TIM_DMA_CC1 ((uint16_t)0x0200)
+#define TIM_DMA_CC2 ((uint16_t)0x0400)
+#define TIM_DMA_CC3 ((uint16_t)0x0800)
+#define TIM_DMA_CC4 ((uint16_t)0x1000)
+#define TIM_DMA_COM ((uint16_t)0x2000)
+#define TIM_DMA_TRIG ((uint16_t)0x4000)
+#define IsTimDmaSrc(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_External_Trigger_Prescaler
+ * @{
+ */
+
+#define TIM_EXT_TRG_PSC_OFF ((uint16_t)0x0000)
+#define TIM_EXT_TRG_PSC_DIV2 ((uint16_t)0x1000)
+#define TIM_EXT_TRG_PSC_DIV4 ((uint16_t)0x2000)
+#define TIM_EXT_TRG_PSC_DIV8 ((uint16_t)0x3000)
+#define IsTimExtPreDiv(PRESCALER) \
+ (((PRESCALER) == TIM_EXT_TRG_PSC_OFF) || ((PRESCALER) == TIM_EXT_TRG_PSC_DIV2) \
+ || ((PRESCALER) == TIM_EXT_TRG_PSC_DIV4) || ((PRESCALER) == TIM_EXT_TRG_PSC_DIV8))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Internal_Trigger_Selection
+ * @{
+ */
+
+#define TIM_TRIG_SEL_IN_TR0 ((uint16_t)0x0000)
+#define TIM_TRIG_SEL_IN_TR1 ((uint16_t)0x0010)
+#define TIM_TRIG_SEL_IN_TR2 ((uint16_t)0x0020)
+#define TIM_TRIG_SEL_IN_TR3 ((uint16_t)0x0030)
+#define TIM_TRIG_SEL_TI1F_ED ((uint16_t)0x0040)
+#define TIM_TRIG_SEL_TI1FP1 ((uint16_t)0x0050)
+#define TIM_TRIG_SEL_TI2FP2 ((uint16_t)0x0060)
+#define TIM_TRIG_SEL_ETRF ((uint16_t)0x0070)
+#define IsTimTrigSel(SELECTION) \
+ (((SELECTION) == TIM_TRIG_SEL_IN_TR0) || ((SELECTION) == TIM_TRIG_SEL_IN_TR1) \
+ || ((SELECTION) == TIM_TRIG_SEL_IN_TR2) || ((SELECTION) == TIM_TRIG_SEL_IN_TR3) \
+ || ((SELECTION) == TIM_TRIG_SEL_TI1F_ED) || ((SELECTION) == TIM_TRIG_SEL_TI1FP1) \
+ || ((SELECTION) == TIM_TRIG_SEL_TI2FP2) || ((SELECTION) == TIM_TRIG_SEL_ETRF))
+#define IsTimInterTrigSel(SELECTION) \
+ (((SELECTION) == TIM_TRIG_SEL_IN_TR0) || ((SELECTION) == TIM_TRIG_SEL_IN_TR1) \
+ || ((SELECTION) == TIM_TRIG_SEL_IN_TR2) || ((SELECTION) == TIM_TRIG_SEL_IN_TR3))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_TIx_External_Clock_Source
+ * @{
+ */
+
+#define TIM_EXT_CLK_SRC_TI1 ((uint16_t)0x0050)
+#define TIM_EXT_CLK_SRC_TI2 ((uint16_t)0x0060)
+#define TIM_EXT_CLK_SRC_TI1ED ((uint16_t)0x0040)
+#define IsTimExtClkSrc(SOURCE) \
+ (((SOURCE) == TIM_EXT_CLK_SRC_TI1) || ((SOURCE) == TIM_EXT_CLK_SRC_TI2) || ((SOURCE) == TIM_EXT_CLK_SRC_TI1ED))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_External_Trigger_Polarity
+ * @{
+ */
+#define TIM_EXT_TRIG_POLARITY_INVERTED ((uint16_t)0x8000)
+#define TIM_EXT_TRIG_POLARITY_NONINVERTED ((uint16_t)0x0000)
+#define IsTimExtTrigPolarity(POLARITY) \
+ (((POLARITY) == TIM_EXT_TRIG_POLARITY_INVERTED) || ((POLARITY) == TIM_EXT_TRIG_POLARITY_NONINVERTED))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Prescaler_Reload_Mode
+ * @{
+ */
+
+#define TIM_PSC_RELOAD_MODE_UPDATE ((uint16_t)0x0000)
+#define TIM_PSC_RELOAD_MODE_IMMEDIATE ((uint16_t)0x0001)
+#define IsTimPscReloadMode(RELOAD) \
+ (((RELOAD) == TIM_PSC_RELOAD_MODE_UPDATE) || ((RELOAD) == TIM_PSC_RELOAD_MODE_IMMEDIATE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Forced_Action
+ * @{
+ */
+
+#define TIM_FORCED_ACTION_ACTIVE ((uint16_t)0x0050)
+#define TIM_FORCED_ACTION_INACTIVE ((uint16_t)0x0040)
+#define IsTimForceActive(OPERATE) (((OPERATE) == TIM_FORCED_ACTION_ACTIVE) || ((OPERATE) == TIM_FORCED_ACTION_INACTIVE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Encoder_Mode
+ * @{
+ */
+
+#define TIM_ENCODE_MODE_TI1 ((uint16_t)0x0001)
+#define TIM_ENCODE_MODE_TI2 ((uint16_t)0x0002)
+#define TIM_ENCODE_MODE_TI12 ((uint16_t)0x0003)
+#define IsTimEncodeMode(MODE) \
+ (((MODE) == TIM_ENCODE_MODE_TI1) || ((MODE) == TIM_ENCODE_MODE_TI2) || ((MODE) == TIM_ENCODE_MODE_TI12))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Event_Source
+ * @{
+ */
+
+#define TIM_EVT_SRC_UPDATE ((uint16_t)0x0001)
+#define TIM_EVT_SRC_CC1 ((uint16_t)0x0002)
+#define TIM_EVT_SRC_CC2 ((uint16_t)0x0004)
+#define TIM_EVT_SRC_CC3 ((uint16_t)0x0008)
+#define TIM_EVT_SRC_CC4 ((uint16_t)0x0010)
+#define TIM_EVT_SRC_COM ((uint16_t)0x0020)
+#define TIM_EVT_SRC_TRIG ((uint16_t)0x0040)
+#define TIM_EVT_SRC_BREAK ((uint16_t)0x0080)
+#define IsTimEvtSrc(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Update_Source
+ * @{
+ */
+
+#define TIM_UPDATE_SRC_GLOBAL \
+ ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow \
+ or the setting of UG bit, or an update generation \
+ through the slave mode controller. */
+#define TIM_UPDATE_SRC_REGULAr ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
+#define IsTimUpdateSrc(SOURCE) (((SOURCE) == TIM_UPDATE_SRC_GLOBAL) || ((SOURCE) == TIM_UPDATE_SRC_REGULAr))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_Preload_State
+ * @{
+ */
+
+#define TIM_OC_PRE_LOAD_ENABLE ((uint16_t)0x0008)
+#define TIM_OC_PRE_LOAD_DISABLE ((uint16_t)0x0000)
+#define IsTimOcPreLoadState(STATE) (((STATE) == TIM_OC_PRE_LOAD_ENABLE) || ((STATE) == TIM_OC_PRE_LOAD_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_Fast_State
+ * @{
+ */
+
+#define TIM_OC_FAST_ENABLE ((uint16_t)0x0004)
+#define TIM_OC_FAST_DISABLE ((uint16_t)0x0000)
+#define IsTimOcFastState(STATE) (((STATE) == TIM_OC_FAST_ENABLE) || ((STATE) == TIM_OC_FAST_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_Clear_State
+ * @{
+ */
+
+#define TIM_OC_CLR_ENABLE ((uint16_t)0x0080)
+#define TIM_OC_CLR_DISABLE ((uint16_t)0x0000)
+#define IsTimOcClrState(STATE) (((STATE) == TIM_OC_CLR_ENABLE) || ((STATE) == TIM_OC_CLR_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Trigger_Output_Source
+ * @{
+ */
+
+#define TIM_TRGO_SRC_RESET ((uint16_t)0x0000)
+#define TIM_TRGO_SRC_ENABLE ((uint16_t)0x0010)
+#define TIM_TRGO_SRC_UPDATE ((uint16_t)0x0020)
+#define TIM_TRGO_SRC_OC1 ((uint16_t)0x0030)
+#define TIM_TRGO_SRC_OC1REF ((uint16_t)0x0040)
+#define TIM_TRGO_SRC_OC2REF ((uint16_t)0x0050)
+#define TIM_TRGO_SRC_OC3REF ((uint16_t)0x0060)
+#define TIM_TRGO_SRC_OC4REF ((uint16_t)0x0070)
+#define IsTimTrgoSrc(SOURCE) \
+ (((SOURCE) == TIM_TRGO_SRC_RESET) || ((SOURCE) == TIM_TRGO_SRC_ENABLE) || ((SOURCE) == TIM_TRGO_SRC_UPDATE) \
+ || ((SOURCE) == TIM_TRGO_SRC_OC1) || ((SOURCE) == TIM_TRGO_SRC_OC1REF) || ((SOURCE) == TIM_TRGO_SRC_OC2REF) \
+ || ((SOURCE) == TIM_TRGO_SRC_OC3REF) || ((SOURCE) == TIM_TRGO_SRC_OC4REF))
+/**
+ * @}
+ */
+
+/** @defgroup ETR selection
+ * @{
+ */
+#define TIM_ETR_Seletct_ExtGpio ((uint16_t)0x0000)
+#define TIM_ETR_Seletct_innerTsc ((uint16_t)0x0100)
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Slave_Mode
+ * @{
+ */
+
+#define TIM_SLAVE_MODE_RESET ((uint16_t)0x0004)
+#define TIM_SLAVE_MODE_GATED ((uint16_t)0x0005)
+#define TIM_SLAVE_MODE_TRIG ((uint16_t)0x0006)
+#define TIM_SLAVE_MODE_EXT1 ((uint16_t)0x0007)
+#define IsTimSlaveMode(MODE) \
+ (((MODE) == TIM_SLAVE_MODE_RESET) || ((MODE) == TIM_SLAVE_MODE_GATED) || ((MODE) == TIM_SLAVE_MODE_TRIG) \
+ || ((MODE) == TIM_SLAVE_MODE_EXT1))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Master_Slave_Mode
+ * @{
+ */
+
+#define TIM_MASTER_SLAVE_MODE_ENABLE ((uint16_t)0x0080)
+#define TIM_MASTER_SLAVE_MODE_DISABLE ((uint16_t)0x0000)
+#define IsTimMasterSlaveMode(STATE) \
+ (((STATE) == TIM_MASTER_SLAVE_MODE_ENABLE) || ((STATE) == TIM_MASTER_SLAVE_MODE_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Flags
+ * @{
+ */
+
+#define TIM_FLAG_UPDATE ((uint32_t)0x0001)
+#define TIM_FLAG_CC1 ((uint32_t)0x0002)
+#define TIM_FLAG_CC2 ((uint32_t)0x0004)
+#define TIM_FLAG_CC3 ((uint32_t)0x0008)
+#define TIM_FLAG_CC4 ((uint32_t)0x0010)
+#define TIM_FLAG_COM ((uint32_t)0x0020)
+#define TIM_FLAG_TRIG ((uint32_t)0x0040)
+#define TIM_FLAG_BREAK ((uint32_t)0x0080)
+#define TIM_FLAG_CC1OF ((uint32_t)0x0200)
+#define TIM_FLAG_CC2OF ((uint32_t)0x0400)
+#define TIM_FLAG_CC3OF ((uint32_t)0x0800)
+#define TIM_FLAG_CC4OF ((uint32_t)0x1000)
+#define TIM_FLAG_CC5 ((uint32_t)0x010000)
+#define TIM_FLAG_CC6 ((uint32_t)0x020000)
+
+#define IsTimGetFlag(FLAG) \
+ (((FLAG) == TIM_FLAG_UPDATE) || ((FLAG) == TIM_FLAG_CC1) || ((FLAG) == TIM_FLAG_CC2) || ((FLAG) == TIM_FLAG_CC3) \
+ || ((FLAG) == TIM_FLAG_CC4) || ((FLAG) == TIM_FLAG_COM) || ((FLAG) == TIM_FLAG_TRIG) \
+ || ((FLAG) == TIM_FLAG_BREAK) || ((FLAG) == TIM_FLAG_CC1OF) || ((FLAG) == TIM_FLAG_CC2OF) \
+ || ((FLAG) == TIM_FLAG_CC3OF) || ((FLAG) == TIM_FLAG_CC4OF) || ((FLAG) == TIM_FLAG_CC5) \
+ || ((FLAG) == TIM_FLAG_CC6))
+
+#define IsTimClrFlag(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Input_Capture_Filer_Value
+ * @{
+ */
+
+#define IsTimInCapFilter(ICFILTER) ((ICFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_External_Trigger_Filter
+ * @{
+ */
+
+#define IsTimExtTrigFilter(EXTFILTER) ((EXTFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+#define TIM_CC1EN ((uint32_t)1<<0)
+#define TIM_CC1NEN ((uint32_t)1<<2)
+#define TIM_CC2EN ((uint32_t)1<<4)
+#define TIM_CC2NEN ((uint32_t)1<<6)
+#define TIM_CC3EN ((uint32_t)1<<8)
+#define TIM_CC3NEN ((uint32_t)1<<10)
+#define TIM_CC4EN ((uint32_t)1<<12)
+#define TIM_CC5EN ((uint32_t)1<<16)
+#define TIM_CC6EN ((uint32_t)1<<20)
+
+#define IsAdvancedTimCCENFlag(FLAG) \
+ (((FLAG) == TIM_CC1EN) || ((FLAG) == TIM_CC1NEN) || ((FLAG) == TIM_CC2EN) || ((FLAG) == TIM_CC2NEN) \
+ || ((FLAG) == TIM_CC3EN) || ((FLAG) == TIM_CC3NEN) \
+ || ((FLAG) == TIM_CC4EN) || ((FLAG) == TIM_CC5EN) || ((FLAG) == TIM_CC6EN) )
+#define IsGeneralTimCCENFlag(FLAG) \
+ (((FLAG) == TIM_CC1EN) || ((FLAG) == TIM_CC2EN) \
+ || ((FLAG) == TIM_CC3EN) \
+ || ((FLAG) == TIM_CC4EN) )
+
+/** @addtogroup TIM_Legacy
+ * @{
+ */
+
+#define TIM_DMA_BURST_LEN_1BYTE TIM_DMABURST_LENGTH_1TRANSFER
+#define TIM_DMA_BURST_LEN_2BYTES TIM_DMABURST_LENGTH_2TRANSFERS
+#define TIM_DMA_BURST_LEN_3BYTES TIM_DMABURST_LENGTH_3TRANSFERS
+#define TIM_DMA_BURST_LEN_4BYTES TIM_DMABURST_LENGTH_4TRANSFERS
+#define TIM_DMA_BURST_LEN_5BYTES TIM_DMABURST_LENGTH_5TRANSFERS
+#define TIM_DMA_BURST_LEN_6BYTES TIM_DMABURST_LENGTH_6TRANSFERS
+#define TIM_DMA_BURST_LEN_7BYTES TIM_DMABURST_LENGTH_7TRANSFERS
+#define TIM_DMA_BURST_LEN_8BYTES TIM_DMABURST_LENGTH_8TRANSFERS
+#define TIM_DMA_BURST_LEN_9BYTES TIM_DMABURST_LENGTH_9TRANSFERS
+#define TIM_DMA_BURST_LEN_10BYTES TIM_DMABURST_LENGTH_10TRANSFERS
+#define TIM_DMA_BURST_LEN_11BYTES TIM_DMABURST_LENGTH_11TRANSFERS
+#define TIM_DMA_BURST_LEN_12BYTES TIM_DMABURST_LENGTH_12TRANSFERS
+#define TIM_DMA_BURST_LEN_13BYTES TIM_DMABURST_LENGTH_13TRANSFERS
+#define TIM_DMA_BURST_LEN_14BYTES TIM_DMABURST_LENGTH_14TRANSFERS
+#define TIM_DMA_BURST_LEN_15BYTES TIM_DMABURST_LENGTH_15TRANSFERS
+#define TIM_DMA_BURST_LEN_16BYTES TIM_DMABURST_LENGTH_16TRANSFERS
+#define TIM_DMA_BURST_LEN_17BYTES TIM_DMABURST_LENGTH_17TRANSFERS
+#define TIM_DMA_BURST_LEN_18BYTES TIM_DMABURST_LENGTH_18TRANSFERS
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions
+ * @{
+ */
+
+void TIM_DeInit(TIM_Module* TIMx);
+void TIM_InitTimeBase(TIM_Module* TIMx, TIM_TimeBaseInitType* TIM_TimeBaseInitStruct);
+void TIM_InitOc1(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
+void TIM_InitOc2(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
+void TIM_InitOc3(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
+void TIM_InitOc4(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
+void TIM_InitOc5(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
+void TIM_InitOc6(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
+void TIM_ICInit(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct);
+void TIM_ConfigPwmIc(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct);
+void TIM_ConfigBkdt(TIM_Module* TIMx, TIM_BDTRInitType* TIM_BDTRInitStruct);
+void TIM_InitTimBaseStruct(TIM_TimeBaseInitType* TIM_TimeBaseInitStruct);
+void TIM_InitOcStruct(OCInitType* TIM_OCInitStruct);
+void TIM_InitIcStruct(TIM_ICInitType* TIM_ICInitStruct);
+void TIM_InitBkdtStruct(TIM_BDTRInitType* TIM_BDTRInitStruct);
+void TIM_Enable(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_EnableCtrlPwmOutputs(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_ConfigInt(TIM_Module* TIMx, uint16_t TIM_IT, FunctionalState Cmd);
+void TIM_GenerateEvent(TIM_Module* TIMx, uint16_t TIM_EventSource);
+void TIM_ConfigDma(TIM_Module* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
+void TIM_EnableDma(TIM_Module* TIMx, uint16_t TIM_DMASource, FunctionalState Cmd);
+void TIM_ConfigInternalClk(TIM_Module* TIMx);
+void TIM_ConfigInternalTrigToExt(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_ConfigExtTrigAsClk(TIM_Module* TIMx,
+ uint16_t TIM_TIxExternalCLKSource,
+ uint16_t IcPolarity,
+ uint16_t ICFilter);
+void TIM_ConfigExtClkMode1(TIM_Module* TIMx,
+ uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter);
+void TIM_ConfigExtClkMode2(TIM_Module* TIMx,
+ uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter);
+void TIM_ConfigExtTrig(TIM_Module* TIMx,
+ uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter);
+void TIM_ConfigPrescaler(TIM_Module* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
+void TIM_ConfigCntMode(TIM_Module* TIMx, uint16_t CntMode);
+void TIM_SelectInputTrig(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_ConfigEncoderInterface(TIM_Module* TIMx,
+ uint16_t TIM_EncoderMode,
+ uint16_t TIM_IC1Polarity,
+ uint16_t TIM_IC2Polarity);
+void TIM_ConfigForcedOc1(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ConfigForcedOc2(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ConfigForcedOc3(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ConfigForcedOc4(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ConfigForcedOc5(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ConfigForcedOc6(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ConfigArPreload(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_SelectComEvt(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_SelectCapCmpDmaSrc(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_EnableCapCmpPreloadControl(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_ConfigOc1Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload);
+void TIM_ConfigOc2Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload);
+void TIM_ConfigOc3Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload);
+void TIM_ConfigOc4Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload);
+void TIM_ConfigOc5Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload);
+void TIM_ConfigOc6Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload);
+void TIM_ConfigOc1Fast(TIM_Module* TIMx, uint16_t TIM_OCFast);
+void TIM_ConfigOc2Fast(TIM_Module* TIMx, uint16_t TIM_OCFast);
+void TIM_ConfigOc3Fast(TIM_Module* TIMx, uint16_t TIM_OCFast);
+void TIM_ConfigOc4Fast(TIM_Module* TIMx, uint16_t TIM_OCFast);
+void TIM_ConfigOc5Fast(TIM_Module* TIMx, uint16_t TIM_OCFast);
+void TIM_ConfigOc6Fast(TIM_Module* TIMx, uint16_t TIM_OCFast);
+void TIM_ClrOc1Ref(TIM_Module* TIMx, uint16_t TIM_OCClear);
+void TIM_ClrOc2Ref(TIM_Module* TIMx, uint16_t TIM_OCClear);
+void TIM_ClrOc3Ref(TIM_Module* TIMx, uint16_t TIM_OCClear);
+void TIM_ClrOc4Ref(TIM_Module* TIMx, uint16_t TIM_OCClear);
+void TIM_ClrOc5Ref(TIM_Module* TIMx, uint16_t TIM_OCClear);
+void TIM_ClrOc6Ref(TIM_Module* TIMx, uint16_t TIM_OCClear);
+void TIM_ConfigOc1Polarity(TIM_Module* TIMx, uint16_t OcPolarity);
+void TIM_ConfigOc1NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity);
+void TIM_ConfigOc2Polarity(TIM_Module* TIMx, uint16_t OcPolarity);
+void TIM_ConfigOc2NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity);
+void TIM_ConfigOc3Polarity(TIM_Module* TIMx, uint16_t OcPolarity);
+void TIM_ConfigOc3NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity);
+void TIM_ConfigOc4Polarity(TIM_Module* TIMx, uint16_t OcPolarity);
+void TIM_ConfigOc5Polarity(TIM_Module* TIMx, uint16_t OcPolarity);
+void TIM_ConfigOc6Polarity(TIM_Module* TIMx, uint16_t OcPolarity);
+void TIM_EnableCapCmpCh(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCx);
+void TIM_EnableCapCmpChN(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCxN);
+void TIM_SelectOcMode(TIM_Module* TIMx, uint16_t Channel, uint16_t OcMode);
+void TIM_EnableUpdateEvt(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_ConfigUpdateRequestIntSrc(TIM_Module* TIMx, uint16_t TIM_UpdateSource);
+void TIM_SelectHallSensor(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_SelectOnePulseMode(TIM_Module* TIMx, uint16_t TIM_OPMode);
+void TIM_SelectOutputTrig(TIM_Module* TIMx, uint16_t TIM_TRGOSource);
+void TIM_SelectExtSignalSource(TIM_Module* TIMx, uint16_t ExtSigalSource);
+void TIM_SelectSlaveMode(TIM_Module* TIMx, uint16_t TIM_SlaveMode);
+void TIM_SelectMasterSlaveMode(TIM_Module* TIMx, uint16_t TIM_MasterSlaveMode);
+void TIM_SetCnt(TIM_Module* TIMx, uint16_t Counter);
+void TIM_SetAutoReload(TIM_Module* TIMx, uint16_t Autoreload);
+void TIM_SetCmp1(TIM_Module* TIMx, uint16_t Compare1);
+void TIM_SetCmp2(TIM_Module* TIMx, uint16_t Compare2);
+void TIM_SetCmp3(TIM_Module* TIMx, uint16_t Compare3);
+void TIM_SetCmp4(TIM_Module* TIMx, uint16_t Compare4);
+void TIM_SetCmp5(TIM_Module* TIMx, uint16_t Compare5);
+void TIM_SetCmp6(TIM_Module* TIMx, uint16_t Compare6);
+void TIM_SetInCap1Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetInCap2Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetInCap3Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetInCap4Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetClkDiv(TIM_Module* TIMx, uint16_t TIM_CKD);
+uint16_t TIM_GetCap1(TIM_Module* TIMx);
+uint16_t TIM_GetCap2(TIM_Module* TIMx);
+uint16_t TIM_GetCap3(TIM_Module* TIMx);
+uint16_t TIM_GetCap4(TIM_Module* TIMx);
+uint16_t TIM_GetCap5(TIM_Module* TIMx);
+uint16_t TIM_GetCap6(TIM_Module* TIMx);
+uint16_t TIM_GetCnt(TIM_Module* TIMx);
+uint16_t TIM_GetPrescaler(TIM_Module* TIMx);
+uint16_t TIM_GetAutoReload(TIM_Module* TIMx);
+FlagStatus TIM_GetCCENStatus(TIM_Module* TIMx, uint32_t TIM_CCEN);
+FlagStatus TIM_GetFlagStatus(TIM_Module* TIMx, uint32_t TIM_FLAG);
+void TIM_ClearFlag(TIM_Module* TIMx, uint32_t TIM_FLAG);
+INTStatus TIM_GetIntStatus(TIM_Module* TIMx, uint32_t TIM_IT);
+void TIM_ClrIntPendingBit(TIM_Module* TIMx, uint32_t TIM_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32WB452_TIM_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_tsc.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_tsc.h
new file mode 100644
index 0000000000..f820e3cc0b
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_tsc.h
@@ -0,0 +1,576 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_tsc.h
+ * @author Nations
+ * @version v1.0.3
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32WB452_TSC_H__
+#define __N32WB452_TSC_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "n32wb452.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup TSC
+ * @{
+ */
+
+/**
+ * @brief TSC error code
+ */
+ typedef enum {
+ TSC_ERROR_OK = 0x00U, /*!< No error */
+ TSC_ERROR_CLOCK = 0x01U, /*!< clock config error */
+ TSC_ERROR_PARAMETER = 0x02U, /*!< parameter error */
+ TSC_ERROR_HW_MODE = 0x02U, /*!< Exit hw mode timeout */
+
+ }TSC_ErrorTypeDef;
+ /**
+ * @
+ */
+
+/**
+ * @brief TSC clock source
+ */
+#define TSC_CLK_SRC_LSI (0x00000000) /*!< LSI*/
+#define TSC_CLK_SRC_LSE (RCC_LSE_ENABLE) /*!< LSE */
+#define TSC_CLK_SRC_LSE_BYPASS (RCC_LSE_BYPASS) /*!< LSE bypass */
+/**
+ * @
+ */
+
+
+/**
+ * @defgroup Detect_Period
+ */
+#define TSC_DET_PERIOD_8 (0x00000000U) /*!< DET_PERIOD[3:0] = 8/TSC_CLOCK */
+#define TSC_DET_PERIOD_16 (0x01UL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x00000001U DET_PERIOD[3:0] = 16/TSC_CLOCK */
+#define TSC_DET_PERIOD_24 (0x02UL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x00000002U DET_PERIOD[3:0] = 24/TSC_CLOCK */
+#define TSC_DET_PERIOD_32 (0x03UL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x00000003U DET_PERIOD[3:0] = 32/TSC_CLOCK(default) */
+#define TSC_DET_PERIOD_40 (0x04UL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x00000004U DET_PERIOD[3:0] = 40/TSC_CLOCK */
+#define TSC_DET_PERIOD_48 (0x05UL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x00000005U DET_PERIOD[3:0] = 48/TSC_CLOCK */
+#define TSC_DET_PERIOD_56 (0x06UL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x00000006U DET_PERIOD[3:0] = 56/TSC_CLOCK */
+#define TSC_DET_PERIOD_64 (0x07UL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x00000007U DET_PERIOD[3:0] = 64/TSC_CLOCK */
+#define TSC_DET_PERIOD_72 (0x08UL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x00000008U DET_PERIOD[3:0] = 72/TSC_CLOCK */
+#define TSC_DET_PERIOD_80 (0x09UL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x00000009U DET_PERIOD[3:0] = 80/TSC_CLOCK */
+#define TSC_DET_PERIOD_88 (0x0AUL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x0000000AU DET_PERIOD[3:0] = 88/TSC_CLOCK */
+#define TSC_DET_PERIOD_96 (0x0BUL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x0000000BU DET_PERIOD[3:0] = 96/TSC_CLOCK */
+#define TSC_DET_PERIOD_104 (0x0CUL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x0000000CU DET_PERIOD[3:0] = 104/TSC_CLOCK */
+
+#define TSC_DET_PERIOD_8_32KHZ ((uint8_t)TSC_DET_PERIOD_8)
+#define TSC_DET_PERIOD_16_32KHZ ((uint8_t)TSC_DET_PERIOD_16)
+#define TSC_DET_PERIOD_24_32KHZ ((uint8_t)TSC_DET_PERIOD_24)
+#define TSC_DET_PERIOD_32_32KHZ ((uint8_t)TSC_DET_PERIOD_32)
+#define TSC_DET_PERIOD_40_32KHZ ((uint8_t)TSC_DET_PERIOD_40)
+#define TSC_DET_PERIOD_48_32KHZ ((uint8_t)TSC_DET_PERIOD_48)
+#define TSC_DET_PERIOD_56_32KHZ ((uint8_t)TSC_DET_PERIOD_56)
+#define TSC_DET_PERIOD_64_32KHZ ((uint8_t)TSC_DET_PERIOD_64)
+#define TSC_DET_PERIOD_72_32KHZ ((uint8_t)TSC_DET_PERIOD_72)
+#define TSC_DET_PERIOD_80_32KHZ ((uint8_t)TSC_DET_PERIOD_80)
+#define TSC_DET_PERIOD_88_32KHZ ((uint8_t)TSC_DET_PERIOD_88)
+#define TSC_DET_PERIOD_96_32KHZ ((uint8_t)TSC_DET_PERIOD_96)
+#define TSC_DET_PERIOD_104_32KHZ ((uint8_t)TSC_DET_PERIOD_104)
+/**
+ * @
+ */
+
+/**
+ * @defgroup Detect_Filter
+ */
+#define TSC_DET_FILTER_1 (0x00000000U) /*!< DET_FILTER[3:0] = 1 sample */
+#define TSC_DET_FILTER_2 (0x01UL << TSC_CTRL_DET_FILTER_SHIFT) /*!< 0x00000010U DET_FILTER[3:0] = 2 samples */
+#define TSC_DET_FILTER_3 (0x02UL << TSC_CTRL_DET_FILTER_SHIFT) /*!< 0x00000020U DET_FILTER[3:0] = 3 samples */
+#define TSC_DET_FILTER_4 (0x03UL << TSC_CTRL_DET_FILTER_SHIFT) /*!< 0x00000030U DET_FILTER[3:0] = 4 samples */
+
+#define TSC_HW_DET_FILTER_1 ((uint8_t)TSC_DET_FILTER_1)
+#define TSC_HW_DET_FILTER_2 ((uint8_t)TSC_DET_FILTER_2)
+#define TSC_HW_DET_FILTER_3 ((uint8_t)TSC_DET_FILTER_3)
+#define TSC_HW_DET_FILTER_4 ((uint8_t)TSC_DET_FILTER_4)
+
+/**
+ * @
+ */
+
+/**
+ * @defgroup HW_Detect_Mode
+ */
+#define TSC_HW_DET_MODE_DISABLE (0x00000000U) /*!< Hardware detect mode disable */
+#define TSC_HW_DET_MODE_ENABLE (0x01UL << TSC_CTRL_HW_DET_MODE_SHIFT) /*!< 0x00000040U Hardware detect mode enable */
+
+#define TSC_HW_DET_ENABLE TSC_HW_DET_MODE_ENABLE
+/**
+ * @
+ */
+
+/**
+ * @defgroup Detect_Type
+ */
+#define TSC_DET_TYPE_MASK (TSC_CTRL_LESS_DET_SEL_MASK|TSC_CTRL_GREAT_DET_SEL_MASK)
+#define TSC_DET_TYPE_SHIFT (TSC_CTRL_LESS_DET_SEL_SHIFT)
+
+#define TSC_DET_TYPE_NONE (0UL) /*!< 0x00000000U Disable detect */
+#define TSC_DET_TYPE_LESS (0x01UL << TSC_DET_TYPE_SHIFT) /*!< 0x00000100U Less detect enable */
+#define TSC_DET_TYPE_GREAT (0x02UL << TSC_DET_TYPE_SHIFT) /*!< 0x00000200U Great detect enable */
+#define TSC_DET_TYPE_PERIOD (0x03UL << TSC_DET_TYPE_SHIFT) /*!< 0x00000300U Both great and less detct enable */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_Interrupt
+ */
+#define TSC_IT_DET_ENABLE (TSC_CTRL_DET_INTEN) /*!< Enable TSC detect interrupt */
+#define TSC_IT_DET_DISABLE (0UL) /*!< Disable TSC detect interrupt */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_Out
+ */
+#define TSC_OUT_PIN (0x00000000U) /*!< TSC output to TSC_OUT pin */
+#define TSC_OUT_TIM4_ETR (0x1UL << TSC_CTRL_TM4_ETR_SHIFT) /*!< TSC output to TIM4 ETR */
+#define TSC_OUT_TIM2_ETR (0x2UL << TSC_CTRL_TM4_ETR_SHIFT) /*!< TSC output to TIM2 ETR and TIM2 CH1*/
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_Flag
+ */
+#define TSC_FLAG_HW (0x1UL << TSC_CTRL_HW_DET_ST_SHIFT) /*!< Flag of hardware detect mode */
+
+#define TSC_FLAG_GREAT_DET (0x1UL << TSC_STS_GREAT_DET_SHIFT) /*!< Flag of great detect type */
+#define TSC_FLAG_LESS_DET (0x1UL << TSC_STS_LESS_DET_SHIFT) /*!< Flag of less detect type */
+#define TSC_FLAG_PERIOD_DET (TSC_FLAG_GREAT_DET|TSC_FLAG_LESS_DET) /*!< Flag of period detect type */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_SW_Detect
+ */
+#define TSC_SW_MODE_DISABLE (0x00000000U) /*!< Disable software detect mode */
+#define TSC_SW_MODE_ENABLE (0x1UL << TSC_ANA_CTRL_SW_TSC_EN_SHIFT) /*!< Enable software detect mode */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_PadOption
+ */
+#define TSC_PAD_INTERNAL_RES (0x00000000U) /*!< Use internal resistor */
+#define TSC_PAD_EXTERNAL_RES (0x1UL << TSC_ANA_SEL_PAD_OPT_SHIFT) /*!< Use external resistor */
+
+#define TSC_INNER_RESIST TSC_PAD_INTERNAL_RES
+
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_PadSpeed
+ */
+#define TSC_PAD_SPEED_0 (0x00000000U) /*!< Low speed,about 100K */
+#define TSC_PAD_SPEED_1 (0x1UL << TSC_ANA_SEL_SP_OPT_SHIFT) /*!< Middle spped */
+#define TSC_PAD_SPEED_2 (0x2UL << TSC_ANA_SEL_SP_OPT_SHIFT) /*!< Middle spped */
+#define TSC_PAD_SPEED_3 (0x3UL << TSC_ANA_SEL_SP_OPT_SHIFT) /*!< Middle spped */
+
+#define TSC_CMP_MASK (0x03UL) // comparator offset bit mask
+#define TSC_CMP_OFFSET TSC_ANA_SEL_SP_OPT_SHIFT // offset of comparator speed configuration
+#define TSC_CMP_SPEED_0 TSC_PAD_SPEED_0 // 100KHZ~200KHZ
+#define TSC_CMP_SPEED_1 TSC_PAD_SPEED_1 // 300KHZ~700KHZ
+#define TSC_CMP_SPEED_2 TSC_PAD_SPEED_2 // 300KHZ~700KHZ
+#define TSC_CMP_SPEED_3 TSC_PAD_SPEED_3 // 300KHZ~700KHZ
+
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_Touch_Lib
+ */
+#define TSC_RESIST_1M TSC_RESR_CHN_RESIST_1M
+#define TSC_RESIST_875K TSC_RESR_CHN_RESIST_875K
+#define TSC_RESIST_750K TSC_RESR_CHN_RESIST_750K
+#define TSC_RESIST_625K TSC_RESR_CHN_RESIST_625K
+#define TSC_RESIST_500K TSC_RESR_CHN_RESIST_500K
+#define TSC_RESIST_375K TSC_RESR_CHN_RESIST_375K
+#define TSC_RESIST_250K TSC_RESR_CHN_RESIST_250K
+#define TSC_RESIST_125K TSC_RESR_CHN_RESIST_125K
+
+#define TSC_HW_CHN_MASK (0x00FFFFFF)
+#define TSC_CHN_ADDR_WIDTH (4)
+
+#define TSC_HW_BASE_BITS_OFFSET (0)
+#define TSC_HW_DELTA_BITS_OFFSET (16)
+
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_Constant
+ */
+#define TSC_CHN_SEL_ALL (TSC_CHNEN_CHN_SEL_MASK)
+#define MAX_TSC_HW_CHN (24) /*Maximum number of tsc pin*/
+#define TSC_DET_MAX_CHN_COUNT MAX_TSC_HW_CHN
+#define MAX_TSC_THRESHOLD_BASE (2047) /*Maximum detect base value of threshold*/
+#define MAX_TSC_THRESHOLD_DELTA (255) /*Maximum detect delta value of threshold*/
+#define TSC_TIMEOUT (0x01000000) /*TSC normal timeout */
+/**
+ * @
+ */
+
+/* TSC Exported macros -----------------------------------------------------------*/
+/** @defgroup TSC_Exported_Macros
+ * @{
+ */
+
+/** @brief Enable the TSC HW detect mode
+ * @param None
+ * @retval None
+ */
+#define __TSC_HW_ENABLE() SET_BIT(TSC->CTRL, TSC_HW_DET_MODE_ENABLE)
+
+/** @brief Disable the TSC HW detect mode
+ * @param None
+ * @retval None
+ */
+#define __TSC_HW_DISABLE() CLEAR_BIT(TSC->CTRL, TSC_HW_DET_MODE_ENABLE)
+
+/** @brief Config TSC detect period for HW detect mode
+ * @param __PERIOD__ specifies the TSC detect period during HW detect mode
+ * @arg TSC_DET_PERIOD_8: Detect period = 8/TSC_CLK
+ * @arg TSC_DET_PERIOD_16: Detect Period = 1/TSC_CLK
+ * @arg TSC_DET_PERIOD_24: Detect Period = 2/TSC_CLK
+ * @arg TSC_DET_PERIOD_32: Detect Period = 3/TSC_CLK
+ * @arg TSC_DET_PERIOD_40: Detect Period = 4/TSC_CLK
+ * @arg TSC_DET_PERIOD_48: Detect Period = 5/TSC_CLK
+ * @arg TSC_DET_PERIOD_56: Detect Period = 6/TSC_CLK
+ * @arg TSC_DET_PERIOD_64: Detect Period = 7/TSC_CLK
+ * @arg TSC_DET_PERIOD_72: Detect Period = 7/TSC_CLK
+ * @arg TSC_DET_PERIOD_80: Detect Period = 7/TSC_CLK
+ * @arg TSC_DET_PERIOD_88: Detect Period = 7/TSC_CLK
+ * @arg TSC_DET_PERIOD_96: Detect Period = 7/TSC_CLK
+ * @arg TSC_DET_PERIOD_104:Detect Period = 7/TSC_CLK
+ * @retval None
+ */
+#define __TSC_PERIOD_CONFIG(__PERIOD__) MODIFY_REG(TSC->CTRL, TSC_CTRL_DET_PERIOD_MASK,__PERIOD__)
+
+/** @brief Config TSC detect filter for HW detect mode
+ * @param __FILTER__ specifies the least usefull continuous samples during HW detect mode
+ * @arg TSC_DET_FILTER_1: Detect filter = 1 pulse
+ * @arg TSC_DET_FILTER_2: Detect filter = 2 pulse
+ * @arg TSC_DET_FILTER_3: Detect filter = 3 pulse
+ * @arg TSC_DET_FILTER_4: Detect filter = 4 pulse
+ * @retval None
+ */
+#define __TSC_FILTER_CONFIG(__FILTER__) MODIFY_REG(TSC->CTRL, TSC_CTRL_DET_FILTER_MASK,__FILTER__)
+
+/** @brief Config TSC detect type for HW detect mode,less great or both
+ * @param __TYPE__ specifies the detect type of a sample during HW detect mode
+ * @arg TSC_DET_TYPE_NONE: Detect disable
+ * @arg TSC_DET_TYPE_LESS: Pulse number must be greater than the threshold(basee-delta) during a sample time
+ * @arg TSC_DET_TYPE_GREAT: Pulse number must be less than the threshold(basee+delta) during a sample time
+ * @arg TSC_DET_TYPE_PERIOD:Pulse number must be greater than (basee-delta)
+ and also be less than (basee+delta) during a sample time
+ * @retval None
+ */
+#define __TSC_LESS_GREAT_CONFIG(__TYPE__) MODIFY_REG(TSC->CTRL, \
+ (TSC_CTRL_LESS_DET_SEL_MASK|TSC_CTRL_GREAT_DET_SEL_MASK), \
+ __TYPE__)
+
+/** @brief Enable TSC interrupt
+ * @param None
+ * @retval None
+ */
+#define __TSC_INT_ENABLE() SET_BIT(TSC->CTRL, TSC_IT_DET_ENABLE)
+
+/** @brief Disable TSC interrupt
+ * @param None
+ * @retval None
+ */
+#define __TSC_INT_DISABLE() CLEAR_BIT(TSC->CTRL, TSC_IT_DET_ENABLE)
+
+/** @brief Config the TSC output
+ * @param __OUT__ specifies where the TSC output should go
+ * @arg TSC_OUT_PIN: TSC output to the TSC_OUT pin
+ * @arg TSC_OUT_TIM4_ETR: TSC output to TIM4 as ETR
+ * @arg TSC_OUT_TIM2_ETR: TSC output to TIM2 as ETR
+ * @retval None
+ */
+#define __TSC_OUT_CONFIG(__OUT__) MODIFY_REG( TSC->CTRL, \
+ (TSC_CTRL_TM4_ETR_MASK|TSC_CTRL_TM2_ETR_CH1_MASK),\
+ __OUT__)
+
+/** @brief Config the TSC channel
+ * @param __CHN__ specifies the pin of channels used for detect
+ * This parameter:bit[0:23] used,bit[24:31] must be 0
+ * bitx: TSC channel x
+ * @retval None
+ */
+#define __TSC_CHN_CONFIG(__CHN__) WRITE_REG(TSC->CHNEN, __CHN__)
+
+/** @brief Enable the TSC SW detect mode
+ * @param None
+ * @retval None
+ */
+#define __TSC_SW_ENABLE() SET_BIT(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_TSC_EN)
+
+/** @brief Disable the TSC SW detect mode
+ * @param None
+ * @retval None
+ */
+#define __TSC_SW_DISABLE() CLEAR_BIT(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_TSC_EN)
+
+/** @brief Config the detect channel number during SW detect mode
+ * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN
+ * @retval None
+ */
+#define __TSC_SW_CHN_NUM_CONFIG(__NUM__) MODIFY_REG(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_PAD_MUX_MASK,__NUM__)
+
+/** @brief Config the pad charge type
+ * @param __OPT__ specifies which resistor is used for charge
+ * @arg TSC_PAD_INTERNAL_RES: Internal resistor is used
+ * @arg TSC_PAD_EXTERNAL_RES: External resistor is used
+ * @retval None
+ */
+#define __TSC_PAD_OPT_CONFIG(__OPT__) MODIFY_REG(TSC->ANA_SEL, TSC_ANA_SEL_PAD_OPT_MASK,__OPT__)
+
+/** @brief Config TSC speed
+ * @param __SPEED__ specifies the TSC speed range
+ * @arg TSC_PAD_SPEED_0: Low speed
+ * @arg TSC_PAD_SPEED_1: Middle speed
+ * @arg TSC_PAD_SPEED_2: Middle speed
+ * @arg TSC_PAD_SPEED_3: High speed
+ * @retval None
+ */
+#define __TSC_PAD_SPEED_CONFIG(__SPEED__) MODIFY_REG(TSC->ANA_SEL, TSC_ANA_SEL_SP_OPT_MASK,__SPEED__)
+
+
+/** @brief Check if the HW detect mode is enable
+ * @param None
+ * @retval Current state of HW detect mode
+ */
+#define __TSC_GET_HW_MODE() (((TSC->CTRL) & TSC_FLAG_HW) == (TSC_FLAG_HW))
+
+/** @brief Check the detect type during HW detect mode
+ * @param __FLAG__ specifies the flag of detect type
+ * @arg TSC_FLAG_LESS_DET: Flag of less detect type
+ * @arg TSC_FLAG_GREAT_DET: Flag of great detect type
+ * @arg TSC_FLAG_PERIOD_DET: Flag of priod detect type
+ * @retval Current state of flag
+ */
+#define __TSC_GET_HW_DET_TYPE(__FLAG__) (((TSC->STS) & (__FLAG__))==(__FLAG__))
+
+/** @brief Get the number of channel which is detected now
+ * @param None
+ * @retval Current channel number
+ */
+#define __TSC_GET_CHN_NUMBER() (((TSC->STS) & TSC_STS_CHN_NUM_MASK) >> TSC_STS_CHN_NUM_SHIFT )
+
+/** @brief Get the count value of pulse
+ * @param None
+ * @retval Pulse count of current channel
+ */
+#define __TSC_GET_CHN_CNT() (((TSC->STS) & TSC_STS_CNT_VAL_MASK ) >> TSC_STS_CNT_VAL_SHIFT )
+
+/** @brief Get the base value of one channel
+ * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN
+ * @retval base value of the channel
+ */
+#define __TSC_GET_CHN_BASE(__NUM__) ((*((&(TSC->THRHD0))+(__NUM__)) & TSC_THRHD_BASE_MASK ) >> TSC_THRHD_BASE_SHIFT)
+
+/** @brief Get the delta value of one channel
+ * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN
+ * @retval delta value of the channel
+ */
+#define __TSC_GET_CHN_DELTA(__NUM__) ((*((&(TSC->THRHD0))+(__NUM__)) & TSC_THRHD_DELTA_MASK ) >> TSC_THRHD_DELTA_SHIFT )
+
+/** @brief Get the internal resist value of one channel
+ * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN
+ * @retval resist value of the channel
+ */
+#define __TSC_GET_CHN_RESIST(__NUM__) (((*((&(TSC->RESR0))+((__NUM__)>>3))) >>(((__NUM__) & 0x7UL)*4)) & TSC_RESR_CHN_RESIST_MASK)
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TSC_Private_Macros
+ * @{
+ */
+#define IS_TSC_DET_PERIOD(_PERIOD_) \
+ (((_PERIOD_)==TSC_DET_PERIOD_8) ||((_PERIOD_)==TSC_DET_PERIOD_16)||((_PERIOD_)==TSC_DET_PERIOD_24) \
+ ||((_PERIOD_)==TSC_DET_PERIOD_32)||((_PERIOD_)==TSC_DET_PERIOD_40)||((_PERIOD_)==TSC_DET_PERIOD_48) \
+ ||((_PERIOD_)==TSC_DET_PERIOD_56)||((_PERIOD_)==TSC_DET_PERIOD_64)||((_PERIOD_)==TSC_DET_PERIOD_72) \
+ ||((_PERIOD_)==TSC_DET_PERIOD_80)||((_PERIOD_)==TSC_DET_PERIOD_88)||((_PERIOD_)==TSC_DET_PERIOD_96) \
+ ||((_PERIOD_)==TSC_DET_PERIOD_104) )
+
+#define IS_TSC_FILTER(_FILTER_) \
+ ( ((_FILTER_)==TSC_DET_FILTER_1) ||((_FILTER_)==TSC_DET_FILTER_2)\
+ ||((_FILTER_)==TSC_DET_FILTER_3) ||((_FILTER_)==TSC_DET_FILTER_4) )
+
+#define IS_TSC_DET_MODE(_MODE_) \
+ ( ((_MODE_)==TSC_HW_DETECT_MODE) ||((_MODE_)==TSC_SW_DETECT_MODE) )
+
+#define IS_TSC_DET_TYPE(_TYPE_) \
+ ( ((_TYPE_)==TSC_DET_TYPE_GREAT) ||((_TYPE_)==TSC_DET_TYPE_LESS) \
+ ||((_TYPE_)==TSC_DET_TYPE_PERIOD)|| ((_TYPE_)==TSC_DET_TYPE_NONE) )
+
+#define IS_TSC_INT(_INT_) (((_INT_)==TSC_IT_DET_ENABLE)||((_INT_)==TSC_IT_DET_DISABLE))
+
+#define IS_TSC_OUT(_ETR_) (((_ETR_)==TSC_OUT_PIN)||((_ETR_)==TSC_OUT_TIM2_ETR)||((_ETR_)==TSC_OUT_TIM4_ETR))
+
+#define IS_TSC_CHN(_CHN_) (0==((_CHN_)&(~TSC_CHNEN_CHN_SEL_MASK)))
+
+#define IS_TSC_CHN_NUMBER(_NUM_) ((uint32_t)(_NUM_)BaudRate)))
+ - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
+
+ uint16_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref USART_Word_Length */
+
+ uint16_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref USART_Stop_Bits */
+
+ uint16_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint16_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref Mode */
+
+ uint16_t HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
+ or disabled.
+ This parameter can be a value of @ref USART_Hardware_Flow_Control */
+} USART_InitType;
+
+/**
+ * @brief USART Clock Init Structure definition
+ */
+
+typedef struct
+{
+ uint16_t Clock; /*!< Specifies whether the USART clock is enabled or disabled.
+ This parameter can be a value of @ref Clock */
+
+ uint16_t Polarity; /*!< Specifies the steady state value of the serial clock.
+ This parameter can be a value of @ref USART_Clock_Polarity */
+
+ uint16_t Phase; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref USART_Clock_Phase */
+
+ uint16_t LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref USART_Last_Bit */
+} USART_ClockInitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Exported_Constants
+ * @{
+ */
+
+#define IS_USART_ALL_PERIPH(PERIPH) \
+ (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3) || ((PERIPH) == UART4) \
+ || ((PERIPH) == UART5) || ((PERIPH) == UART6) || ((PERIPH) == UART7))
+
+#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3))
+
+#define IS_USART_1234_PERIPH(PERIPH) \
+ (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3) || ((PERIPH) == UART4))
+/** @addtogroup USART_Word_Length
+ * @{
+ */
+
+#define USART_WL_8B ((uint16_t)0x0000)
+#define USART_WL_9B ((uint16_t)0x1000)
+
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WL_8B) || ((LENGTH) == USART_WL_9B))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Stop_Bits
+ * @{
+ */
+
+#define USART_STPB_1 ((uint16_t)0x0000)
+#define USART_STPB_0_5 ((uint16_t)0x1000)
+#define USART_STPB_2 ((uint16_t)0x2000)
+#define USART_STPB_1_5 ((uint16_t)0x3000)
+#define IS_USART_STOPBITS(STOPBITS) \
+ (((STOPBITS) == USART_STPB_1) || ((STOPBITS) == USART_STPB_0_5) || ((STOPBITS) == USART_STPB_2) \
+ || ((STOPBITS) == USART_STPB_1_5))
+/**
+ * @}
+ */
+
+/** @addtogroup Parity
+ * @{
+ */
+
+#define USART_PE_NO ((uint16_t)0x0000)
+#define USART_PE_EVEN ((uint16_t)0x0400)
+#define USART_PE_ODD ((uint16_t)0x0600)
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PE_NO) || ((PARITY) == USART_PE_EVEN) || ((PARITY) == USART_PE_ODD))
+/**
+ * @}
+ */
+
+/** @addtogroup Mode
+ * @{
+ */
+
+#define USART_MODE_RX ((uint16_t)0x0004)
+#define USART_MODE_TX ((uint16_t)0x0008)
+#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Hardware_Flow_Control
+ * @{
+ */
+#define USART_HFCTRL_NONE ((uint16_t)0x0000)
+#define USART_HFCTRL_RTS ((uint16_t)0x0100)
+#define USART_HFCTRL_CTS ((uint16_t)0x0200)
+#define USART_HFCTRL_RTS_CTS ((uint16_t)0x0300)
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL) \
+ (((CONTROL) == USART_HFCTRL_NONE) || ((CONTROL) == USART_HFCTRL_RTS) || ((CONTROL) == USART_HFCTRL_CTS) \
+ || ((CONTROL) == USART_HFCTRL_RTS_CTS))
+/**
+ * @}
+ */
+
+/** @addtogroup Clock
+ * @{
+ */
+#define USART_CLK_DISABLE ((uint16_t)0x0000)
+#define USART_CLK_ENABLE ((uint16_t)0x0800)
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLK_DISABLE) || ((CLOCK) == USART_CLK_ENABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Clock_Polarity
+ * @{
+ */
+
+#define USART_CLKPOL_LOW ((uint16_t)0x0000)
+#define USART_CLKPOL_HIGH ((uint16_t)0x0400)
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CLKPOL_LOW) || ((CPOL) == USART_CLKPOL_HIGH))
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Clock_Phase
+ * @{
+ */
+
+#define USART_CLKPHA_1EDGE ((uint16_t)0x0000)
+#define USART_CLKPHA_2EDGE ((uint16_t)0x0200)
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CLKPHA_1EDGE) || ((CPHA) == USART_CLKPHA_2EDGE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Last_Bit
+ * @{
+ */
+
+#define USART_CLKLB_DISABLE ((uint16_t)0x0000)
+#define USART_CLKLB_ENABLE ((uint16_t)0x0100)
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_CLKLB_DISABLE) || ((LASTBIT) == USART_CLKLB_ENABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Interrupt_definition
+ * @{
+ */
+
+#define USART_INT_PEF ((uint16_t)0x0028)
+#define USART_INT_TXDE ((uint16_t)0x0727)
+#define USART_INT_TXC ((uint16_t)0x0626)
+#define USART_INT_RXDNE ((uint16_t)0x0525)
+#define USART_INT_IDLEF ((uint16_t)0x0424)
+#define USART_INT_LINBD ((uint16_t)0x0846)
+#define USART_INT_CTSF ((uint16_t)0x096A)
+#define USART_INT_ERRF ((uint16_t)0x0060)
+#define USART_INT_OREF ((uint16_t)0x0360)
+#define USART_INT_NEF ((uint16_t)0x0260)
+#define USART_INT_FEF ((uint16_t)0x0160)
+#define IS_USART_CFG_INT(IT) \
+ (((IT) == USART_INT_PEF) || ((IT) == USART_INT_TXDE) || ((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE) \
+ || ((IT) == USART_INT_IDLEF) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF) \
+ || ((IT) == USART_INT_ERRF))
+#define IS_USART_GET_INT(IT) \
+ (((IT) == USART_INT_PEF) || ((IT) == USART_INT_TXDE) || ((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE) \
+ || ((IT) == USART_INT_IDLEF) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF) || ((IT) == USART_INT_OREF) \
+ || ((IT) == USART_INT_NEF) || ((IT) == USART_INT_FEF))
+#define IS_USART_CLR_INT(IT) \
+ (((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_DMA_Requests
+ * @{
+ */
+
+#define USART_DMAREQ_TX ((uint16_t)0x0080)
+#define USART_DMAREQ_RX ((uint16_t)0x0040)
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_WakeUp_methods
+ * @{
+ */
+
+#define USART_WUM_IDLELINE ((uint16_t)0x0000)
+#define USART_WUM_ADDRMASK ((uint16_t)0x0800)
+#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WUM_IDLELINE) || ((WAKEUP) == USART_WUM_ADDRMASK))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_LIN_Break_Detection_Length
+ * @{
+ */
+
+#define USART_LINBDL_10B ((uint16_t)0x0000)
+#define USART_LINBDL_11B ((uint16_t)0x0020)
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == USART_LINBDL_10B) || ((LENGTH) == USART_LINBDL_11B))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_IrDA_Low_Power
+ * @{
+ */
+
+#define USART_IRDAMODE_LOWPPWER ((uint16_t)0x0004)
+#define USART_IRDAMODE_NORMAL ((uint16_t)0x0000)
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IRDAMODE_LOWPPWER) || ((MODE) == USART_IRDAMODE_NORMAL))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Flags
+ * @{
+ */
+
+#define USART_FLAG_CTSF ((uint16_t)0x0200)
+#define USART_FLAG_LINBD ((uint16_t)0x0100)
+#define USART_FLAG_TXDE ((uint16_t)0x0080)
+#define USART_FLAG_TXC ((uint16_t)0x0040)
+#define USART_FLAG_RXDNE ((uint16_t)0x0020)
+#define USART_FLAG_IDLEF ((uint16_t)0x0010)
+#define USART_FLAG_OREF ((uint16_t)0x0008)
+#define USART_FLAG_NEF ((uint16_t)0x0004)
+#define USART_FLAG_FEF ((uint16_t)0x0002)
+#define USART_FLAG_PEF ((uint16_t)0x0001)
+#define IS_USART_FLAG(FLAG) \
+ (((FLAG) == USART_FLAG_PEF) || ((FLAG) == USART_FLAG_TXDE) || ((FLAG) == USART_FLAG_TXC) \
+ || ((FLAG) == USART_FLAG_RXDNE) || ((FLAG) == USART_FLAG_IDLEF) || ((FLAG) == USART_FLAG_LINBD) \
+ || ((FLAG) == USART_FLAG_CTSF) || ((FLAG) == USART_FLAG_OREF) || ((FLAG) == USART_FLAG_NEF) \
+ || ((FLAG) == USART_FLAG_FEF))
+
+#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
+#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) \
+ ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) && ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \
+ || ((USART_FLAG) != USART_FLAG_CTSF))
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))
+#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
+#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Exported_Functions
+ * @{
+ */
+
+void USART_DeInit(USART_Module* USARTx);
+void USART_Init(USART_Module* USARTx, USART_InitType* USART_InitStruct);
+void USART_StructInit(USART_InitType* USART_InitStruct);
+void USART_ClockInit(USART_Module* USARTx, USART_ClockInitType* USART_ClockInitStruct);
+void USART_ClockStructInit(USART_ClockInitType* USART_ClockInitStruct);
+void USART_Enable(USART_Module* USARTx, FunctionalState Cmd);
+void USART_ConfigInt(USART_Module* USARTx, uint16_t USART_INT, FunctionalState Cmd);
+void USART_EnableDMA(USART_Module* USARTx, uint16_t USART_DMAReq, FunctionalState Cmd);
+void USART_SetAddr(USART_Module* USARTx, uint8_t USART_Addr);
+void USART_ConfigWakeUpMode(USART_Module* USARTx, uint16_t USART_WakeUpMode);
+void USART_EnableRcvWakeUp(USART_Module* USARTx, FunctionalState Cmd);
+void USART_ConfigLINBreakDetectLength(USART_Module* USARTx, uint16_t USART_LINBreakDetectLength);
+void USART_EnableLIN(USART_Module* USARTx, FunctionalState Cmd);
+void USART_SendData(USART_Module* USARTx, uint16_t Data);
+uint16_t USART_ReceiveData(USART_Module* USARTx);
+void USART_SendBreak(USART_Module* USARTx);
+void USART_SetGuardTime(USART_Module* USARTx, uint8_t USART_GuardTime);
+void USART_SetPrescaler(USART_Module* USARTx, uint8_t USART_Prescaler);
+void USART_EnableSmartCard(USART_Module* USARTx, FunctionalState Cmd);
+void USART_SetSmartCardNACK(USART_Module* USARTx, FunctionalState Cmd);
+void USART_EnableHalfDuplex(USART_Module* USARTx, FunctionalState Cmd);
+void USART_ConfigIrDAMode(USART_Module* USARTx, uint16_t USART_IrDAMode);
+void USART_EnableIrDA(USART_Module* USARTx, FunctionalState Cmd);
+FlagStatus USART_GetFlagStatus(USART_Module* USARTx, uint16_t USART_FLAG);
+void USART_ClrFlag(USART_Module* USARTx, uint16_t USART_FLAG);
+INTStatus USART_GetIntStatus(USART_Module* USARTx, uint16_t USART_INT);
+void USART_ClrIntPendingBit(USART_Module* USARTx, uint16_t USART_INT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32WB452_USART_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_wwdg.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_wwdg.h
new file mode 100644
index 0000000000..b24533208f
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_wwdg.h
@@ -0,0 +1,122 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_wwdg.h
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32WB452_WWDG_H__
+#define __N32WB452_WWDG_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32wb452.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup WWDG
+ * @{
+ */
+
+/** @addtogroup WWDG_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup WWDG_Prescaler
+ * @{
+ */
+
+#define WWDG_PRESCALER_DIV1 ((uint32_t)0x00000000)
+#define WWDG_PRESCALER_DIV2 ((uint32_t)0x00000080)
+#define WWDG_PRESCALER_DIV4 ((uint32_t)0x00000100)
+#define WWDG_PRESCALER_DIV8 ((uint32_t)0x00000180)
+#define IS_WWDG_PRESCALER_DIV(PRESCALER) \
+ (((PRESCALER) == WWDG_PRESCALER_DIV1) || ((PRESCALER) == WWDG_PRESCALER_DIV2) \
+ || ((PRESCALER) == WWDG_PRESCALER_DIV4) || ((PRESCALER) == WWDG_PRESCALER_DIV8))
+#define IS_WWDG_WVALUE(VALUE) ((VALUE) <= 0x7F)
+#define IS_WWDG_CNT(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Exported_Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Exported_Functions
+ * @{
+ */
+
+void WWDG_DeInit(void);
+void WWDG_SetPrescalerDiv(uint32_t WWDG_Prescaler);
+void WWDG_SetWValue(uint8_t WindowValue);
+void WWDG_EnableInt(void);
+void WWDG_SetCnt(uint8_t Counter);
+void WWDG_Enable(uint8_t Counter);
+FlagStatus WWDG_GetEWINTF(void);
+void WWDG_ClrEWINTF(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32WB452__WWDG_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32xx_tsc_alg_api.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32xx_tsc_alg_api.h
new file mode 100644
index 0000000000..87e8f1fdff
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32xx_tsc_alg_api.h
@@ -0,0 +1,302 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @brief 触控算法头文件.
+ * 大概æµç¨‹:(é…ç½®TIMER->定义回调API->åˆå§‹åŒ–->å¯åŠ¨)
+ * @file n32xx_tsc_alg_api.h
+ * @author Nations
+ * @version v1.0.1
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32XX_TSC_ALG_API__
+#define __N32XX_TSC_ALG_API__
+
+#ifdef __cplusplus
+extern "C" {
+#endif // defined __cplusplus
+
+#define TSC_ALG_VERSION_NUMBER "Ver1.0.4" //算法库版本å·
+
+#define TSC_ALG_HANDLER_STOP2_DATA_SIZE (144) //用于在STOP2模å¼ä¸‹ä¿å˜è§¦æŽ§å”¤é†’功能相关的TSCæ•°æ®ã€‚
+#define TSC_ALG_HANDLER_PERIOD_PER_CHN (400) //触控算法å•é€šé“的处ç†å‘¨æœŸå› å。
+#define TSC_ALG_WAKEUP_TIMES (1000) //有关TSC唤醒功能的时间é…置，ä¸è¦éšæ„修改
+#define TSC_ALG_DEBUG_BUF_SIZE (260) //定义调试模å¼ä¸‹çš„BUF大å°
+#define TSC_ALG_REF_SIZE_PER_CHN (430) //触控æ¯é€šé“çš„å‚考大å°ï¼Œå®žé™…大å°ä»¥tsc_alg_need_sramsize()计算为准
+
+/**
+ * @brief 定义触控类型
+ */
+typedef enum tsc_alg_type_e
+{
+ TSC_ALG_BUTTON_TYPE = 0, ///< tsc application of simple button
+ TSC_ALG_TYPE_MAX ///<
+} tsc_alg_type;
+
+/**
+ * @brief 按键事件
+ */
+typedef enum tsc_press_key_event_e
+{
+ TSC_PRESS_KEY_NORMAL = 0, //æ£å¸¸çŸæŒ‰äº‹ä»¶
+ TSC_PRESS_KEY_MAX ///<
+} tsc_press_key_event;
+
+/**
+ * @brief 错误类型定义
+ */
+typedef enum tsc_ret_code_e
+{
+ TSC_SUCCESS = 0, ///< æˆåŠŸ
+ TSC_NOT_INIT_ERR, ///< 模å—未åˆå§‹åŒ–错误
+ TSC_NOT_REG_CHN_ERR, ///< 模å—æ³¨å†Œæ— æ•ˆçš„è§¦æŽ§é€šé“错误
+ TSC_NOT_ACCORD_LIB_ERR, ///< 算法库版本错误
+ TSC_POINTER_NULL_ERR, ///< 指针为空错误
+ TSC_PARAM_ZERO_ERR, ///< å‚数错误
+ TSC_REPEAT_REG_ERR, ///< é‡å¤æ³¨å†Œé”™è¯¯
+ TSC_CHN_NUM_ERR, ///< 与åˆå§‹åŒ–的通é“总数ä¸ä¸€è‡´é”™è¯¯
+ TSC_REG_CHANNEL_ENOUGH_ERR, ///< 注册的通é“å·é”™è¯¯æˆ–超出系统总通é“æ•°
+ TSC_REG_TIMX_ERR, ///< 注册的Timer资æºé”™è¯¯
+ TSC_REG_DMA_ERR, ///< 注册的DMA资æºé”™è¯¯
+ TSC_SOURCE_NOT_ENOUGH_ERR, ///< 资æºä¸è¶³é”™è¯¯
+ TSC_NOT_SUPPORT_ERR, ///< 未实现或æ“作ä¸æ”¯æŒé”™è¯¯
+ TSC_LEVEL_CFG_ERR, ///< 通é“çš„çµæ˜Žåº¦é…置错误
+ TSC_AUTO_CALIB_TIMER_ERR, ///< è‡ªåŠ¨æ ¡å‡†æ—¶é—´å°äºŽ2å€é€šé“按键ä¿æŒæ—¶é—´.
+ TSC_DISTURB_ERR, ///< 干扰错误.
+ TSC_CHN_RAM_NOT_ENOUGH_ERR, ///< æ供的TSC通é“RAM为NULL或空间ä¸è¶³é”™è¯¯
+ TSC_STOP2_NULL_OR_INVALID_ERR, ///< æ供的Stop2Dataæ•°æ®ç©ºé—´ä¸ºNULL或ä¸åœ¨16K retention区域内。
+ TSC_DEBUG_BUF_ENOUGH_ERR ///< æ供的调试缓å˜ç©ºé—´ä¸è¶³é”™è¯¯
+} tsc_ret_code;
+
+/**
+ * @brief 触控按键æŒç»ç‰çº§
+ * æŒç»ç‰çº§è¶Šå°:å应速度越快，抗瞬间的干扰也越弱；
+ * æŒç»ç‰çº§è¶Šå¤§:å应速度相对弱，抗瞬间干扰能力越强
+ */
+typedef enum tsc_hld_lev_e
+{
+ TSC_HOLD_LEV1 = 1, // HOLDç‰çº§1(5ms)
+ TSC_HOLD_LEV2 = 2, // HOLDç‰çº§2(7ms)
+ TSC_HOLD_LEV3 = 3, // HOLDç‰çº§3(11ms)
+ TSC_HOLD_LEV4 = 4, // HOLDç‰çº§4(17ms)
+ TSC_HOLD_LEV5 = 5, // HOLDç‰çº§5(25ms)
+ TSC_HOLD_LEV6 = 6, // HOLDç‰çº§6(35ms)
+ TSC_HOLD_LEV7 = 7, // HOLDç‰çº§7(47ms)
+ TSC_HOLD_LEV8 = 8, // HOLDç‰çº§8(61ms)
+ TSC_HOLD_LEV9 = 9, // HOLDç‰çº§9(77ms)
+ TSC_HOLD_LEV10 = 10, // HOLDç‰çº§10(95ms)
+ TSC_HOLD_LEV11 = 11, // HOLDç‰çº§11(115ms)
+ TSC_HOLD_LEV12 = 12, // HOLDç‰çº§12(137ms)
+ TSC_HOLD_LEV13 = 13, // HOLDç‰çº§13(161ms)
+ TSC_HOLD_LEV14 = 14, // HOLDç‰çº§14(187ms)
+ TSC_HOLD_LEV15 = 15, // HOLDç‰çº§15(215ms)
+ TSC_HOLD_LEV16 = 16, // HOLDç‰çº§16(245ms)
+ TSC_HOLD_LEV17 = 17, // HOLDç‰çº§17(277ms)
+ TSC_HOLD_LEV18 = 18, // HOLDç‰çº§18(311ms)
+ TSC_HOLD_LEV19 = 19, // HOLDç‰çº§19(347ms)
+ TSC_HOLD_LEV20 = 20, // HOLDç‰çº§20(385ms)
+ TSC_HOLD_MAX ///< æ— æ•ˆ
+} tsc_hld_lev;
+
+/**
+ * @brief 在低功耗模å¼ä¸‹ï¼ŒéšçŽ¯å¢ƒå˜åŒ–而更新唤醒门é™ã€‚
+ * å› æ¤è®¾ç½®ä¸€ä¸ªå˜åŒ–é‡å› å。
+ * å°äºŽæ¤å˜åŒ–é‡å› åçš„delta则认为是有效å˜åŒ–，则通过æ¤æŽ¥å£æ›´æ–°TSC唤醒门é™ï¼›
+ * 大于æ¤å˜åŒ–é‡å› åçš„deltaåˆ™è®¤ä¸ºæ˜¯æ— æ•ˆå˜åŒ–，则æ¤æŽ¥å£å¿½ç•¥ä¹‹ï¼Œä¸æ›´æ–°å”¤é†’é—¨é™ã€‚
+ * å˜åŒ–é‡å› å越大，则表示å˜åŒ–é‡è¶Šå¤§ã€‚一般设置为LEV15。
+ */
+typedef enum tsc_delta_limit_lev_e
+{
+ TSC_DELTA_LIMIT_LEV1 = 1, //
+ TSC_DELTA_LIMIT_LEV2 = 2, //
+ TSC_DELTA_LIMIT_LEV3 = 3, //
+ TSC_DELTA_LIMIT_LEV4 = 4, //
+ TSC_DELTA_LIMIT_LEV5 = 5, //
+ TSC_DELTA_LIMIT_LEV6 = 6, //
+ TSC_DELTA_LIMIT_LEV7 = 7, //
+ TSC_DELTA_LIMIT_LEV8 = 8, //
+ TSC_DELTA_LIMIT_LEV9 = 9, //
+ TSC_DELTA_LIMIT_LEV10 = 10, //
+ TSC_DELTA_LIMIT_LEV11 = 11, //
+ TSC_DELTA_LIMIT_LEV12 = 12, //
+ TSC_DELTA_LIMIT_LEV13 = 13, //
+ TSC_DELTA_LIMIT_LEV14 = 14, //
+ TSC_DELTA_LIMIT_LEV15 = 15, //
+ TSC_DELTA_LIMIT_LEV16 = 16, //
+ TSC_DELTA_LIMIT_LEV17 = 17, //
+ TSC_DELTA_LIMIT_LEV18 = 18, //
+ TSC_DELTA_LIMIT_LEV19 = 19, //
+ TSC_DELTA_LIMIT_LEV20 = 20, //
+ TSC_DELTA_LIMIT_MAX ///< æ— æ•ˆ
+} tsc_delta_limit_lev;
+
+/**
+ * @brief 抗干扰ç‰çº§
+ * 抗干扰ç‰çº§,ç‰çº§è¶Šé«˜æŠ—干扰越强，但也对æ¿çº§çŽ¯å¢ƒè¦æ±‚越严苛.
+ */
+typedef enum tsc_resist_disturb_lev_e
+{
+ TSC_RESIST_DIS_LEV0 = 0, //默认ç‰çº§ï¼ŒæŠ—外部干扰一般。支æŒPCBA&亚克力触摸。
+ TSC_RESIST_DIS_LEV1 = 1, //增强ç‰çº§ï¼ŒæŠ—外部干扰增强。亚克力情况下体验更好。
+ TSC_RESIST_DIS_LEV2 = 2, //æš‚ä¿ç•™ã€‚
+ TSC_RESIST_DIS_MAX ///< æ— æ•ˆ
+} tsc_resist_disturb_lev;
+
+/**
+ * @brief TSC触控通é“åˆå§‹é—¨é™å€¼é…ç½®
+ */
+typedef struct TSC_AlgInitThreValue_t
+{
+ uint16_t hold_level; /* 按键触å‘æŒç»ç‰çº§ */
+ uint16_t rate_of_change; /* 该通é“按键å˜åŒ–率(å¦‚æ— åŽ‹ä¸‹ä¸º70,压下为77，则å˜åŒ–率为(77-70)/70 = 0.1å³%10(注æ„:适当é™ä½Žä¸º8%)。默认为5,则å˜åŒ–率%5 */
+ uint32_t chn; /* é€šé“ */
+} TSC_AlgInitThreValue;
+
+/**
+ * @brief TSCåˆå§‹åŒ–é…ç½®å‚æ•°
+ */
+typedef struct TSC_AlgInitTypeDef_t
+{
+ TIM_Module* TIMx; /* 触控算法使用的TIMER资æº(仅支æŒTIMER2) */
+ DMA_ChannelType* DMAyChx; /* 触控算法使用的DMA资æº(仅支æŒDMA1_CH5) */
+ uint32_t DMARemapEnable; /* 是å¦ä½¿èƒ½DMA 全局REMAP功能(如DMA1ä¸å…¶ä»–通é“有使能REMAP功能，则æ¤å¤„需é…置为1) */
+ TSC_AlgInitThreValue* pTScChannelList; /* 由触控通é“组æˆåˆ—表的数组。目å‰æš‚支æŒ1个列(å¯é€šè¿‡ä½æˆ–è¿ç®—,将多个TSC通é“组æˆä¸€ä¸ªåˆ—表)。 */
+ uint32_t AutoCalibrateTimer; /* é…ç½®æœ‰è¦†ç›–ç‰©æƒ…å†µä¸‹çš„è‡ªåŠ¨æ ¡å‡†æ—¶é—´(æ— è¦†ç›–ç‰©æˆ–å¹²æ‰°æ—¶ä¸ä¼šæ ¡å‡†),一般设置1000mså³å¯,最大65535。å•ä½ms。æ¤å€¼å¿…须大于按键ä¿æŒæ—¶é—´çš„2å€ä»¥ä¸Šï¼Œå¦åˆ™åˆå§‹åŒ–错误 */
+ uint32_t ResistDisturbLev; /* 抗干扰ç‰çº§(tsc_resist_disturb_lev),ç‰çº§è¶Šé«˜æŠ—干扰越强，但也对æ¿çº§è£…é…环境è¦æ±‚越高. */
+ uint8_t* pTscSramAddr; /* 应用程åºæ供给TSC驱动库的触控通é“RAM空间地å€*/
+ uint32_t TscSramSize; /* 应用程åºæ供给TSC驱动库的触控通é“RAM空间大å°.å•ä½(bytes) */
+ uint16_t* LogBuf; /* 用于调试模å¼ä¸‹çš„buf缓å˜,éžè°ƒè¯•æ¨¡å¼ä¸‹åˆ™ä¸º0 */
+ uint16_t LogBufSize; /* æ¯é€šé“大å°ä¸ºu16 * 256.å•ä½(bytes) */
+ uint8_t* Stop2Data; /* 用于在STOP2模å¼ä¸‹ä¿å˜è§¦æŽ§å”¤é†’功能相关的TSCæ•°æ®BUF。 */
+ uint16_t Stop2DataSize; /* 用于在STOP2模å¼ä¸‹ä¿å˜è§¦æŽ§å”¤é†’功能相关的TSCæ•°æ®BUF大å°ã€‚å•ä½(bytes) */
+} TSC_AlgInitTypeDef;
+
+/**
+ * @brief 触控算法实时分æžå¤„ç†å‡½æ•°(必须放在TIMERä¸æ–函数ä¸)
+ * @TIMER定时周期å‚è€ƒå‘¨æœŸå› å，定时器周期å‚考DEMO范例.
+ * @param void
+ * @return void
+ */
+void tsc_alg_analyze_handler(void);
+
+/**
+ * @brief ä½ŽåŠŸè€—æ ¡å‡†
+ * @param uint32_t delta_limit_level å˜åŒ–é‡é™å€¼ç‰çº§tsc_delta_limit_lev
+ * @uint32_t hse_or_hsi 0:HSI, 1:HSE;
+ * @return
+ * - `TSC_SUCCESS： 表示æ“作æˆåŠŸ
+ * - 其它值表示出错
+ * - 注æ„：用于在STOP2低功耗模å¼ä¸‹ï¼Œå®šæ—¶æ ¡å‡†ã€‚
+ */
+int32_t tsc_alg_set_powerdown_calibrate(tsc_delta_limit_lev delta_limit_level, uint32_t hse_or_hsi);
+
+/**
+ * @brief 低功耗模å¼ä¸‹,检测是å¦è¢«å¹²æ‰°å”¤é†’
+ * @param void
+ * @return 0:æ£å¸¸å”¤é†’ï¼›1:干扰唤醒
+ */
+int32_t tsc_alg_wakeup_disturb_check(uint32_t* wakeup_src);
+
+/**
+ * @brief 获å–算法版本
+ * @param void
+ * @return void
+ */
+char* tsc_alg_get_version(void);
+
+/**
+ * @brief 触控算法系统滴ç”,默认1ms
+ * @param void
+ * @return void
+ */
+void tsc_alg_tick_count(void);
+
+/**
+ * @brief 获å–TSC触控算法需è¦çš„SRAM大å°
+ * uint32_t chn_totals; // 使用的TSC触控通é“æ•°
+ * @return
+ * - 0: 表示失败
+ * - éž0: 表示æˆåŠŸ
+ */
+uint32_t tsc_alg_need_sramsize(uint32_t chn_totals);
+
+/**
+ * @brief 触控算法åˆå§‹åŒ–
+ * @param tsc_init_parameter *ptsc_init_parameter 触控算法åˆå§‹åŒ–结构体地å€.
+ * @param void
+ * @return
+ * - `TSC_SUCCESS： 表示æ“作æˆåŠŸ
+ * - 其它值表示出错
+ */
+int32_t tsc_alg_init(TSC_AlgInitTypeDef* TSC_AlgInitStruct);
+
+/**
+ * @brief å¯åŠ¨è§¦æŽ§å¼€å§‹å·¥ä½œ
+ * @param void
+ * @return
+ * - `TSC_SUCCESS： 表示æ“作æˆåŠŸ
+ * - 其它值表示出错
+ */
+int32_t tsc_alg_start(void);
+
+/**
+ * @brief 设置TSC进入低功耗(用于低功耗唤醒模å¼)
+ * @param uint32_t TScChannelList ä¿ç•™å‚数。设置为0表示使能已注册的所有通é“
+ * @return
+ * - `TSC_SUCCESS： 表示æ“作æˆåŠŸ
+ * - 其它值表示出错
+ * - 注æ„：STOP2低功耗模å¼ä½¿ç”¨ï¼Œæ£å¸¸æ¨¡å¼ä¸‹ä¸å…³æ³¨ã€‚
+ */
+int32_t tsc_alg_set_powerdown(uint32_t TscChannelList);
+
+////////////////////////////////////////////////////////////
+
+/*****************上层应用æ供的按键回调处ç†å‡½æ•°*********
+ * @brief 注册按钮型ã€æ»‘æ¡åž‹ã€è½¬è½®åž‹è§¦æŽ§çš„回调函数
+ * @param tsc_touch_type type 产生的触控类型(æš‚åªæ”¯æŒæŒ‰é”®åž‹)
+ * @param uint32_t event 0:æ£å¸¸è§¦æ‘¸äº‹ä»¶ï¼›
+ * @param uint32_t chn 表示触摸通é“å·ï¼›
+ * @param uint32_t value 触摸状æ€ï¼š1压下；0æ¾å¼€ï¼›
+ * @return
+ * - `TSC_SUCCESS： 表示æ“作æˆåŠŸ
+ * - 其它值表示出错
+ * 注æ„:æ¤å›žè°ƒå‡½æ•°å°†åœ¨ä¸æ–ä¸è°ƒç”¨ï¼Œå› æ¤å°½é‡å‡å°‘回调函数的处ç†æ—¶é—´ã€‚
+ ********************************************************/
+int32_t tsc_alg_isr_callback(tsc_alg_type type, uint32_t event, uint32_t chn, uint32_t value);
+
+/**
+ * @brief 触控数æ®è¾“出到PC的接å£ï¼Œä»¥ä¾¿äºŽPC端工具观察，设定åˆç†çš„触控阈值
+ * @param uint32_t chn 触控通é“
+ * @return uint8_t data 该触控通é“æ•°æ®
+ */
+void tsc_alg_debug_output(uint32_t chn, uint8_t data);
+
+#ifdef __cplusplus
+}
+#endif // defined __cplusplus
+
+#endif //__N32XX_TSC_ALG_API__
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/misc.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/misc.c
new file mode 100644
index 0000000000..3632b70f14
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/misc.c
@@ -0,0 +1,228 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file misc.c
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "misc.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup MISC
+ * @brief MISC driver modules
+ * @{
+ */
+
+/** @addtogroup MISC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Private_Defines
+ * @{
+ */
+
+#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Configures the priority grouping: pre-emption priority and subpriority.
+ * @param NVIC_PriorityGroup specifies the priority grouping bits length.
+ * This parameter can be one of the following values:
+ * @arg NVIC_PriorityGroup_0 0 bits for pre-emption priority
+ * 4 bits for subpriority
+ * @arg NVIC_PriorityGroup_1 1 bits for pre-emption priority
+ * 3 bits for subpriority
+ * @arg NVIC_PriorityGroup_2 2 bits for pre-emption priority
+ * 2 bits for subpriority
+ * @arg NVIC_PriorityGroup_3 3 bits for pre-emption priority
+ * 1 bits for subpriority
+ * @arg NVIC_PriorityGroup_4 4 bits for pre-emption priority
+ * 0 bits for subpriority
+ */
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
+
+ /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
+ SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
+}
+
+/**
+ * @brief Initializes the NVIC peripheral according to the specified
+ * parameters in the NVIC_InitStruct.
+ * @param NVIC_InitStruct pointer to a NVIC_InitType structure that contains
+ * the configuration information for the specified NVIC peripheral.
+ */
+void NVIC_Init(NVIC_InitType* NVIC_InitStruct)
+{
+ uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
+
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
+ assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
+
+ if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+ {
+ /* Compute the Corresponding IRQ Priority --------------------------------*/
+ tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700)) >> 0x08;
+ tmppre = (0x4 - tmppriority);
+ tmpsub = tmpsub >> tmppriority;
+
+ tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
+ tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
+ tmppriority = tmppriority << 0x04;
+
+ NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
+
+ /* Enable the Selected IRQ Channels --------------------------------------*/
+ NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = (uint32_t)0x01
+ << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+ }
+ else
+ {
+ /* Disable the Selected IRQ Channels -------------------------------------*/
+ NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = (uint32_t)0x01
+ << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+ }
+}
+
+/**
+ * @brief Sets the vector table location and Offset.
+ * @param NVIC_VectTab specifies if the vector table is in RAM or FLASH memory.
+ * This parameter can be one of the following values:
+ * @arg NVIC_VectTab_RAM
+ * @arg NVIC_VectTab_FLASH
+ * @param Offset Vector Table base offset field. This value must be a multiple
+ * of 0x200.
+ */
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
+ assert_param(IS_NVIC_OFFSET(Offset));
+
+ SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
+}
+
+/**
+ * @brief Selects the condition for the system to enter low power mode.
+ * @param LowPowerMode Specifies the new mode for the system to enter low power mode.
+ * This parameter can be one of the following values:
+ * @arg NVIC_LP_SEVONPEND
+ * @arg NVIC_LP_SLEEPDEEP
+ * @arg NVIC_LP_SLEEPONEXIT
+ * @param Cmd new state of LP condition. This parameter can be: ENABLE or DISABLE.
+ */
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_LP(LowPowerMode));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ SCB->SCR |= LowPowerMode;
+ }
+ else
+ {
+ SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
+ }
+}
+
+/**
+ * @brief Configures the SysTick clock source.
+ * @param SysTick_CLKSource specifies the SysTick clock source.
+ * This parameter can be one of the following values:
+ * @arg SysTick_CLKSource_HCLK AHB clock selected as SysTick clock source.
+ */
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
+ if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
+ {
+ SysTick->CTRL |= SysTick_CLKSource_HCLK;
+ }
+// else
+// {
+// SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
+// }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_adc.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_adc.c
new file mode 100644
index 0000000000..a94bf20bf4
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_adc.c
@@ -0,0 +1,1468 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_adc.c
+ * @author Nations
+ * @version v1.0.4
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32wb452_adc.h"
+#include "n32wb452_rcc.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @brief ADC driver modules
+ * @{
+ */
+
+/** @addtogroup ADC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Private_Defines
+ * @{
+ */
+
+/* ADC DISC_NUM mask */
+#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF)
+
+/* ADC DISC_EN mask */
+#define CTRL1_DISC_EN_SET ((uint32_t)0x00000800)
+#define CTRL1_DISC_EN_RESET ((uint32_t)0xFFFFF7FF)
+
+/* ADC INJ_AUTO mask */
+#define CR1_JAUTO_Set ((uint32_t)0x00000400)
+#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF)
+
+/* ADC INJ_DISC_EN mask */
+#define CTRL1_INJ_DISC_EN_SET ((uint32_t)0x00001000)
+#define CTRL1_INJ_DISC_EN_RESET ((uint32_t)0xFFFFEFFF)
+
+/* ADC AWDG_CH mask */
+#define CTRL1_AWDG_CH_RESET ((uint32_t)0xFFFFFFE0)
+
+/* ADC Analog watchdog enable mode mask */
+#define CTRL1_AWDG_MODE_RESET ((uint32_t)0xFF3FFDFF)
+
+/* CTRL1 register Mask */
+#define CTRL1_CLR_MASK ((uint32_t)0xFFF0FEFF)
+
+/* ADC AD_ON mask */
+#define CTRL2_AD_ON_SET ((uint32_t)0x00000001)
+#define CTRL2_AD_ON_RESET ((uint32_t)0xFFFFFFFE)
+
+/* ADC DMA mask */
+#define CTRL2_DMA_SET ((uint32_t)0x00000100)
+#define CTRL2_DMA_RESET ((uint32_t)0xFFFFFEFF)
+
+/* ADC RST_CALI mask */
+#define CTRL2_RST_CALI_SET ((uint32_t)0x00000008)
+
+/* ADC CAL mask */
+#define CTRL2_CAL_SET ((uint32_t)0x00000004)
+
+/* ADC SOFT_START mask */
+#define CTRL2_SOFT_START_SET ((uint32_t)0x00400000)
+
+/* ADC EXT_TRIG mask */
+#define CTRL2_EXT_TRIG_SET ((uint32_t)0x00100000)
+#define CTRL2_EXT_TRIG_RESET ((uint32_t)0xFFEFFFFF)
+
+/* ADC Software start mask */
+#define CTRL2_EXT_TRIG_SWSTART_SET ((uint32_t)0x00500000)
+#define CTRL2_EXT_TRIG_SWSTART_RESET ((uint32_t)0xFFAFFFFF)
+
+/* ADC INJ_EXT_SEL mask */
+#define CTRL2_INJ_EXT_SEL_RESET ((uint32_t)0xFFFF8FFF)
+
+/* ADC INJ_EXT_TRIG mask */
+#define CTRL2_INJ_EXT_TRIG_SET ((uint32_t)0x00008000)
+#define CTRL2_INJ_EXT_TRIG_RESET ((uint32_t)0xFFFF7FFF)
+
+/* ADC INJ_SWSTART mask */
+#define CTRL2_INJ_SWSTART_SET ((uint32_t)0x00200000)
+
+/* ADC injected software start mask */
+#define CTRL2_INJ_EXT_TRIG_JSWSTART_SET ((uint32_t)0x00208000)
+#define CTRL2_INJ_EXT_TRIG_JSWSTART_RESET ((uint32_t)0xFFDF7FFF)
+
+/* ADC TSPD mask */
+#define CTRL2_TSVREFE_SET ((uint32_t)0x00800000)
+#define CTRL2_TSVREFE_RESET ((uint32_t)0xFF7FFFFF)
+
+/* CTRL2 register Mask */
+#define CTRL2_CLR_MASK ((uint32_t)0xFFF1F7FD)
+
+/* ADC SQx mask */
+#define SQR4_SEQ_SET ((uint32_t)0x0000001F)
+#define SQR3_SEQ_SET ((uint32_t)0x0000001F)
+#define SQR2_SEQ_SET ((uint32_t)0x0000001F)
+#define SQR1_SEQ_SET ((uint32_t)0x0000001F)
+
+/* RSEQ1 register Mask */
+#define RSEQ1_CLR_MASK ((uint32_t)0xFF0FFFFF)
+
+/* ADC JSQx mask */
+#define JSEQ_JSQ_SET ((uint32_t)0x0000001F)
+
+/* ADC INJ_LEN mask */
+#define JSEQ_INJ_LEN_SET ((uint32_t)0x00300000)
+#define JSEQ_INJ_LEN_RESET ((uint32_t)0xFFCFFFFF)
+
+/* ADC SAMPTx mask */
+#define SAMPT1_SMP_SET ((uint32_t)0x00000007)
+#define SAMPT2_SMP_SET ((uint32_t)0x00000007)
+
+/* ADC JDATx registers offset */
+#define JDAT_OFFSET ((uint8_t)0x28)
+
+/* ADC1 DAT register base address */
+#define DAT_ADDR ((uint32_t)0x4001244C)
+
+/* ADC STS register mask */
+#define ADC_STS_RESERVE_MASK ((uint32_t)0x0000007F)
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the ADCx peripheral registers to their default reset values.
+ * @param ADCx where x can be 1, 2 to select the ADC peripheral.
+ */
+void ADC_DeInit(ADC_Module* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+
+ if (ADCx == ADC1)
+ {
+ /* Enable ADC1 reset state */
+ RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_ADC1, ENABLE);
+ /* Release ADC1 from reset state */
+ RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_ADC1, DISABLE);
+ }
+ else if (ADCx == ADC2)
+ {
+ /* Enable ADC2 reset state */
+ RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_ADC2, ENABLE);
+ /* Release ADC2 from reset state */
+ RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_ADC2, DISABLE);
+ }
+}
+
+/**
+ * @brief Initializes the ADCx peripheral according to the specified parameters
+ * in the ADC_InitStruct.
+ * @param ADCx where x can be 1, 2 to select the ADC peripheral.
+ * @param ADC_InitStruct pointer to an ADC_InitType structure that contains
+ * the configuration information for the specified ADC peripheral.
+ */
+void ADC_Init(ADC_Module* ADCx, ADC_InitType* ADC_InitStruct)
+{
+ uint32_t tmpreg1 = 0;
+ uint8_t tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcWorkMode(ADC_InitStruct->WorkMode));
+ assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->MultiChEn));
+ assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ContinueConvEn));
+ assert_param(IsAdcExtTrig(ADC_InitStruct->ExtTrigSelect));
+ assert_param(IsAdcDatAlign(ADC_InitStruct->DatAlign));
+ assert_param(IsAdcSeqLenValid(ADC_InitStruct->ChsNumber));
+
+ /*---------------------------- ADCx CTRL1 Configuration -----------------*/
+ /* Get the ADCx CTRL1 value */
+ tmpreg1 = ADCx->CTRL1;
+ /* Clear DUALMOD and SCAN bits */
+ tmpreg1 &= CTRL1_CLR_MASK;
+ /* Configure ADCx: Dual mode and scan conversion mode */
+ /* Set DUALMOD bits according to WorkMode value */
+ /* Set SCAN bit according to MultiChEn value */
+ tmpreg1 |= (uint32_t)(ADC_InitStruct->WorkMode | ((uint32_t)ADC_InitStruct->MultiChEn << 8));
+ /* Write to ADCx CTRL1 */
+ ADCx->CTRL1 = tmpreg1;
+
+ /*---------------------------- ADCx CTRL2 Configuration -----------------*/
+ /* Get the ADCx CTRL2 value */
+ tmpreg1 = ADCx->CTRL2;
+ /* Clear CONT, ALIGN and EXTSEL bits */
+ tmpreg1 &= CTRL2_CLR_MASK;
+ /* Configure ADCx: external trigger event and continuous conversion mode */
+ /* Set ALIGN bit according to DatAlign value */
+ /* Set EXTSEL bits according to ExtTrigSelect value */
+ /* Set CONT bit according to ContinueConvEn value */
+ tmpreg1 |= (uint32_t)(ADC_InitStruct->DatAlign | ADC_InitStruct->ExtTrigSelect
+ | ((uint32_t)ADC_InitStruct->ContinueConvEn << 1));
+ /* Write to ADCx CTRL2 */
+ ADCx->CTRL2 = tmpreg1;
+
+ /*---------------------------- ADCx RSEQ1 Configuration -----------------*/
+ /* Get the ADCx RSEQ1 value */
+ tmpreg1 = ADCx->RSEQ1;
+ /* Clear L bits */
+ tmpreg1 &= RSEQ1_CLR_MASK;
+ /* Configure ADCx: regular channel sequence length */
+ /* Set L bits according to ChsNumber value */
+ tmpreg2 |= (uint8_t)(ADC_InitStruct->ChsNumber - (uint8_t)1);
+ tmpreg1 |= (uint32_t)tmpreg2 << 20;
+ /* Write to ADCx RSEQ1 */
+ ADCx->RSEQ1 = tmpreg1;
+}
+
+/**
+ * @brief Fills each ADC_InitStruct member with its default value.
+ * @param ADC_InitStruct pointer to an ADC_InitType structure which will be initialized.
+ */
+void ADC_InitStruct(ADC_InitType* ADC_InitStruct)
+{
+ /* Reset ADC init structure parameters values */
+ /* Initialize the WorkMode member */
+ ADC_InitStruct->WorkMode = ADC_WORKMODE_INDEPENDENT;
+ /* initialize the MultiChEn member */
+ ADC_InitStruct->MultiChEn = DISABLE;
+ /* Initialize the ContinueConvEn member */
+ ADC_InitStruct->ContinueConvEn = DISABLE;
+ /* Initialize the ExtTrigSelect member */
+ ADC_InitStruct->ExtTrigSelect = ADC_EXT_TRIGCONV_T1_CC1;
+ /* Initialize the DatAlign member */
+ ADC_InitStruct->DatAlign = ADC_DAT_ALIGN_R;
+ /* Initialize the ChsNumber member */
+ ADC_InitStruct->ChsNumber = 1;
+}
+
+/**
+ * @brief Enables or disables the specified ADC peripheral.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the ADCx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_Enable(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set the AD_ON bit to wake up the ADC from power down mode */
+ ADCx->CTRL2 |= CTRL2_AD_ON_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC peripheral */
+ ADCx->CTRL2 &= CTRL2_AD_ON_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified ADC DMA request.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC DMA transfer.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableDMA(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcDmaModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC DMA request */
+ ADCx->CTRL2 |= CTRL2_DMA_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC DMA request */
+ ADCx->CTRL2 &= CTRL2_DMA_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified ADC interrupts.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_IT specifies the ADC interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg ADC_INT_ENDC End of conversion interrupt mask
+ * @arg ADC_INT_AWD Analog watchdog interrupt mask
+ * @arg ADC_INT_JENDC End of injected conversion interrupt mask
+ * @param Cmd new state of the specified ADC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_ConfigInt(ADC_Module* ADCx, uint16_t ADC_IT, FunctionalState Cmd)
+{
+ uint8_t itmask = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ assert_param(IsAdcInt(ADC_IT));
+ /* Get the ADC IT index */
+ itmask = (uint8_t)ADC_IT;
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC interrupts */
+ ADCx->CTRL1 |= itmask;
+ }
+ else
+ {
+ /* Disable the selected ADC interrupts */
+ ADCx->CTRL1 &= (~(uint32_t)itmask);
+ }
+}
+
+
+/**
+ * @brief Starts the selected ADC calibration process.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ */
+void ADC_StartCalibration(ADC_Module* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ /* Enable the selected ADC calibration process */
+ if (ADCx->CALFACT==0)
+ ADCx->CTRL2 |= CTRL2_CAL_SET;
+}
+
+/**
+ * @brief Gets the selected ADC calibration status.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @return The new state of ADC calibration (SET or RESET).
+ */
+FlagStatus ADC_GetCalibrationStatus(ADC_Module* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ /* Check the status of CAL bit */
+ if ((ADCx->CTRL2 & CTRL2_CAL_SET) != (uint32_t)RESET)
+ {
+ /* CAL bit is set: calibration on going */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAL bit is reset: end of calibration */
+ bitstatus = RESET;
+ }
+ if (ADCx->CALFACT!=0)
+ bitstatus = RESET;
+ /* Return the CAL bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Enables or disables the selected ADC software start conversion .
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC software start conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableSoftwareStartConv(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC conversion on external event and start the selected
+ ADC conversion */
+ ADCx->CTRL2 |= CTRL2_EXT_TRIG_SWSTART_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC conversion on external event and stop the selected
+ ADC conversion */
+ ADCx->CTRL2 &= CTRL2_EXT_TRIG_SWSTART_RESET;
+ }
+}
+
+/**
+ * @brief Gets the selected ADC Software start conversion Status.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @return The new state of ADC software start conversion (SET or RESET).
+ */
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_Module* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ /* Check the status of SOFT_START bit */
+ if ((ADCx->CTRL2 & CTRL2_SOFT_START_SET) != (uint32_t)RESET)
+ {
+ /* SOFT_START bit is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* SOFT_START bit is reset */
+ bitstatus = RESET;
+ }
+ /* Return the SOFT_START bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Configures the discontinuous mode for the selected ADC regular
+ * group channel.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Number specifies the discontinuous mode regular channel
+ * count value. This number must be between 1 and 8.
+ */
+void ADC_ConfigDiscModeChannelCount(ADC_Module* ADCx, uint8_t Number)
+{
+ uint32_t tmpreg1 = 0;
+ uint32_t tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcSeqDiscNumberValid(Number));
+ /* Get the old register value */
+ tmpreg1 = ADCx->CTRL1;
+ /* Clear the old discontinuous mode channel count */
+ tmpreg1 &= CR1_DISCNUM_Reset;
+ /* Set the discontinuous mode channel count */
+ tmpreg2 = Number - 1;
+ tmpreg1 |= tmpreg2 << 13;
+ /* Store the new register value */
+ ADCx->CTRL1 = tmpreg1;
+}
+
+/**
+ * @brief Enables or disables the discontinuous mode on regular group
+ * channel for the specified ADC
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC discontinuous mode
+ * on regular group channel.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableDiscMode(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC regular discontinuous mode */
+ ADCx->CTRL1 |= CTRL1_DISC_EN_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC regular discontinuous mode */
+ ADCx->CTRL1 &= CTRL1_DISC_EN_RESET;
+ }
+}
+
+/**
+ * @brief Configures for the selected ADC regular channel its corresponding
+ * rank in the sequencer and its sample time.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_Channel the ADC channel to configure.
+ * This parameter can be one of the following values:
+ * @arg ADC_CH_0 ADC Channel0 selected
+ * @arg ADC_CH_1 ADC Channel1 selected
+ * @arg ADC_CH_2 ADC Channel2 selected
+ * @arg ADC_CH_3 ADC Channel3 selected
+ * @arg ADC_CH_4 ADC Channel4 selected
+ * @arg ADC_CH_5 ADC Channel5 selected
+ * @arg ADC_CH_6 ADC Channel6 selected
+ * @arg ADC_CH_7 ADC Channel7 selected
+ * @arg ADC_CH_8 ADC Channel8 selected
+ * @arg ADC_CH_9 ADC Channel9 selected
+ * @arg ADC_CH_10 ADC Channel10 selected
+ * @arg ADC_CH_11 ADC Channel11 selected
+ * @arg ADC_CH_12 ADC Channel12 selected
+ * @arg ADC_CH_13 ADC Channel13 selected
+ * @arg ADC_CH_14 ADC Channel14 selected
+ * @arg ADC_CH_15 ADC Channel15 selected
+ * @arg ADC_CH_16 ADC Channel16 selected
+ * @arg ADC_CH_17 ADC Channel17 selected
+ * @arg ADC_CH_18 ADC Channel18 selected
+ * @param Rank The rank in the regular group sequencer. This parameter must be between 1 to 16.
+ * @param ADC_SampleTime The sample time value to be set for the selected channel.
+ * This parameter can be one of the following values:
+ * @arg ADC_SAMP_TIME_1CYCLES5 Sample time equal to 1.5 cycles
+ * @arg ADC_SAMP_TIME_7CYCLES5 Sample time equal to 7.5 cycles
+ * @arg ADC_SAMP_TIME_13CYCLES5 Sample time equal to 13.5 cycles
+ * @arg ADC_SAMP_TIME_28CYCLES5 Sample time equal to 28.5 cycles
+ * @arg ADC_SAMP_TIME_41CYCLES5 Sample time equal to 41.5 cycles
+ * @arg ADC_SAMP_TIME_55CYCLES5 Sample time equal to 55.5 cycles
+ * @arg ADC_SAMP_TIME_71CYCLES5 Sample time equal to 71.5 cycles
+ * @arg ADC_SAMP_TIME_239CYCLES5 Sample time equal to 239.5 cycles
+ */
+void ADC_ConfigRegularChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcChannel(ADC_Channel));
+ assert_param(IsAdcReqRankValid(Rank));
+ assert_param(IsAdcSampleTime(ADC_SampleTime));
+
+ if (ADC_Channel == ADC_CH_18)
+ {
+ tmpreg1 = ADCx->SAMPT3;
+ tmpreg1 &= (~0x00000007);
+ tmpreg1 |= ADC_SampleTime;
+ ADCx->SAMPT3 = tmpreg1;
+ }
+ else if (ADC_Channel > ADC_CH_9) /* if ADC_CH_10 ... ADC_CH_17 is selected */
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SAMPT1;
+ /* Calculate the mask to clear */
+ tmpreg2 = SAMPT1_SMP_SET << (3 * (ADC_Channel - 10));
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SAMPT1 = tmpreg1;
+ }
+ else /* ADC_Channel include in ADC_Channel_[0..9] */
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SAMPT2;
+ /* Calculate the mask to clear */
+ tmpreg2 = SAMPT2_SMP_SET << (3 * ADC_Channel);
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SAMPT2 = tmpreg1;
+ }
+ /* For Rank 1 to 6 */
+ if (Rank < 7)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->RSEQ3;
+ /* Calculate the mask to clear */
+ tmpreg2 = SQR3_SEQ_SET << (5 * (Rank - 1));
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->RSEQ3 = tmpreg1;
+ }
+ /* For Rank 7 to 12 */
+ else if (Rank < 13)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->RSEQ2;
+ /* Calculate the mask to clear */
+ tmpreg2 = SQR2_SEQ_SET << (5 * (Rank - 7));
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->RSEQ2 = tmpreg1;
+ }
+ /* For Rank 13 to 16 */
+ else
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->RSEQ1;
+ /* Calculate the mask to clear */
+ tmpreg2 = SQR1_SEQ_SET << (5 * (Rank - 13));
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->RSEQ1 = tmpreg1;
+ }
+}
+
+/**
+ * @brief Enables or disables the ADCx conversion through external trigger.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC external trigger start of conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableExternalTrigConv(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC conversion on external event */
+ ADCx->CTRL2 |= CTRL2_EXT_TRIG_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC conversion on external event */
+ ADCx->CTRL2 &= CTRL2_EXT_TRIG_RESET;
+ }
+}
+
+/**
+ * @brief Returns the last ADCx conversion result data for regular channel.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @return The Data conversion value.
+ */
+uint16_t ADC_GetDat(ADC_Module* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ /* Return the selected ADC conversion value */
+ return (uint16_t)ADCx->DAT;
+}
+
+/**
+ * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode.
+ * @return The Data conversion value.
+ */
+uint32_t ADC_GetDualModeConversionDat(ADC_Module* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ /* Return the dual mode conversion value */
+ if ((ADCx==ADC1) | (ADCx==ADC2))
+ return (uint32_t)ADC1->DAT;
+ else
+ return (uint32_t)ADC1->DAT;
+}
+
+/**
+ * @brief Enables or disables the selected ADC automatic injected group
+ * conversion after regular one.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC auto injected conversion
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableAutoInjectedConv(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC automatic injected group conversion */
+ ADCx->CTRL1 |= CR1_JAUTO_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC automatic injected group conversion */
+ ADCx->CTRL1 &= CR1_JAUTO_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the discontinuous mode for injected group
+ * channel for the specified ADC
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC discontinuous mode
+ * on injected group channel.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableInjectedDiscMode(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC injected discontinuous mode */
+ ADCx->CTRL1 |= CTRL1_INJ_DISC_EN_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC injected discontinuous mode */
+ ADCx->CTRL1 &= CTRL1_INJ_DISC_EN_RESET;
+ }
+}
+
+/**
+ * @brief Configures the ADCx external trigger for injected channels conversion.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_ExternalTrigInjecConv specifies the ADC trigger to start injected conversion.
+ * This parameter can be one of the following values:
+ * @arg ADC_EXT_TRIG_INJ_CONV_T1_TRGO Timer1 TRGO event selected (for ADC1, ADC2)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T1_CC4 Timer1 capture compare4 selected (for ADC1, ADC2)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T2_TRGO Timer2 TRGO event selected (for ADC1 and ADC2)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T2_CC1 Timer2 capture compare1 selected (for ADC1 and ADC2)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T3_CC4 Timer3 capture compare4 selected (for ADC1 and ADC2)
+ * @arg ADC_EXT_TRIG_INJ_CONV_T4_TRGO Timer4 TRGO event selected (for ADC1 and ADC2)
+ * @arg ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4 External interrupt line 15 or Timer8
+ * capture compare4 event selected (for ADC1 and ADC2)
+ */
+void ADC_ConfigExternalTrigInjectedConv(ADC_Module* ADCx, uint32_t ADC_ExternalTrigInjecConv)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcExtInjTrig(ADC_ExternalTrigInjecConv));
+ /* Get the old register value */
+ tmpregister = ADCx->CTRL2;
+ /* Clear the old external event selection for injected group */
+ tmpregister &= CTRL2_INJ_EXT_SEL_RESET;
+ /* Set the external event selection for injected group */
+ tmpregister |= ADC_ExternalTrigInjecConv;
+ /* Store the new register value */
+ ADCx->CTRL2 = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the ADCx injected channels conversion through
+ * external trigger
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC external trigger start of
+ * injected conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableExternalTrigInjectedConv(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC external event selection for injected group */
+ ADCx->CTRL2 |= CTRL2_INJ_EXT_TRIG_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC external event selection for injected group */
+ ADCx->CTRL2 &= CTRL2_INJ_EXT_TRIG_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the selected ADC start of the injected
+ * channels conversion.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC software start injected conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableSoftwareStartInjectedConv(ADC_Module* ADCx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected ADC conversion for injected group on external event and start the selected
+ ADC injected conversion */
+ ADCx->CTRL2 |= CTRL2_INJ_EXT_TRIG_JSWSTART_SET;
+ }
+ else
+ {
+ /* Disable the selected ADC conversion on external event for injected group and stop the selected
+ ADC injected conversion */
+ ADCx->CTRL2 &= CTRL2_INJ_EXT_TRIG_JSWSTART_RESET;
+ }
+}
+
+/**
+ * @brief Gets the selected ADC Software start injected conversion Status.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @return The new state of ADC software start injected conversion (SET or RESET).
+ */
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_Module* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ /* Check the status of INJ_SWSTART bit */
+ if ((ADCx->CTRL2 & CTRL2_INJ_SWSTART_SET) != (uint32_t)RESET)
+ {
+ /* INJ_SWSTART bit is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* INJ_SWSTART bit is reset */
+ bitstatus = RESET;
+ }
+ /* Return the INJ_SWSTART bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Configures for the selected ADC injected channel its corresponding
+ * rank in the sequencer and its sample time.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_Channel the ADC channel to configure.
+ * This parameter can be one of the following values:
+ * @arg ADC_CH_0 ADC Channel0 selected
+ * @arg ADC_CH_1 ADC Channel1 selected
+ * @arg ADC_CH_2 ADC Channel2 selected
+ * @arg ADC_CH_3 ADC Channel3 selected
+ * @arg ADC_CH_4 ADC Channel4 selected
+ * @arg ADC_CH_5 ADC Channel5 selected
+ * @arg ADC_CH_6 ADC Channel6 selected
+ * @arg ADC_CH_7 ADC Channel7 selected
+ * @arg ADC_CH_8 ADC Channel8 selected
+ * @arg ADC_CH_9 ADC Channel9 selected
+ * @arg ADC_CH_10 ADC Channel10 selected
+ * @arg ADC_CH_11 ADC Channel11 selected
+ * @arg ADC_CH_12 ADC Channel12 selected
+ * @arg ADC_CH_13 ADC Channel13 selected
+ * @arg ADC_CH_14 ADC Channel14 selected
+ * @arg ADC_CH_15 ADC Channel15 selected
+ * @arg ADC_CH_16 ADC Channel16 selected
+ * @arg ADC_CH_17 ADC Channel17 selected
+ * @arg ADC_CH_18 ADC Channel18 selected
+ * @param Rank The rank in the injected group sequencer. This parameter must be between 1 and 4.
+ * @param ADC_SampleTime The sample time value to be set for the selected channel.
+ * This parameter can be one of the following values:
+ * @arg ADC_SAMP_TIME_1CYCLES5 Sample time equal to 1.5 cycles
+ * @arg ADC_SAMP_TIME_7CYCLES5 Sample time equal to 7.5 cycles
+ * @arg ADC_SAMP_TIME_13CYCLES5 Sample time equal to 13.5 cycles
+ * @arg ADC_SAMP_TIME_28CYCLES5 Sample time equal to 28.5 cycles
+ * @arg ADC_SAMP_TIME_41CYCLES5 Sample time equal to 41.5 cycles
+ * @arg ADC_SAMP_TIME_55CYCLES5 Sample time equal to 55.5 cycles
+ * @arg ADC_SAMP_TIME_71CYCLES5 Sample time equal to 71.5 cycles
+ * @arg ADC_SAMP_TIME_239CYCLES5 Sample time equal to 239.5 cycles
+ */
+void ADC_ConfigInjectedChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcChannel(ADC_Channel));
+ assert_param(IsAdcInjRankValid(Rank));
+ assert_param(IsAdcSampleTime(ADC_SampleTime));
+
+ if (ADC_Channel == ADC_CH_18)
+ {
+ tmpreg1 = ADCx->SAMPT3;
+ tmpreg1 &= (~0x00000007);
+ tmpreg1 |= ADC_SampleTime;
+ ADCx->SAMPT3 = tmpreg1;
+ }
+ else if (ADC_Channel > ADC_CH_9) /* if ADC_CH_10 ... ADC_CH_17 is selected */
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SAMPT1;
+ /* Calculate the mask to clear */
+ tmpreg2 = SAMPT1_SMP_SET << (3 * (ADC_Channel - 10));
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SAMPT1 = tmpreg1;
+ }
+ else /* ADC_Channel include in ADC_Channel_[0..9] */
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SAMPT2;
+ /* Calculate the mask to clear */
+ tmpreg2 = SAMPT2_SMP_SET << (3 * ADC_Channel);
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SAMPT2 = tmpreg1;
+ }
+ /* Rank configuration */
+ /* Get the old register value */
+ tmpreg1 = ADCx->JSEQ;
+ /* Get INJ_LEN value: Number = INJ_LEN+1 */
+ tmpreg3 = (tmpreg1 & JSEQ_INJ_LEN_SET) >> 20;
+ /* Calculate the mask to clear: ((Rank-1)+(4-INJ_LEN-1)) */
+ tmpreg2 = JSEQ_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+ /* Clear the old JSQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set: ((Rank-1)+(4-INJ_LEN-1)) */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+ /* Set the JSQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->JSEQ = tmpreg1;
+}
+
+/**
+ * @brief Configures the sequencer length for injected channels
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Length The sequencer length.
+ * This parameter must be a number between 1 to 4.
+ */
+void ADC_ConfigInjectedSequencerLength(ADC_Module* ADCx, uint8_t Length)
+{
+ uint32_t tmpreg1 = 0;
+ uint32_t tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcInjLenValid(Length));
+
+ /* Get the old register value */
+ tmpreg1 = ADCx->JSEQ;
+ /* Clear the old injected sequnence lenght INJ_LEN bits */
+ tmpreg1 &= JSEQ_INJ_LEN_RESET;
+ /* Set the injected sequnence lenght INJ_LEN bits */
+ tmpreg2 = Length - 1;
+ tmpreg1 |= tmpreg2 << 20;
+ /* Store the new register value */
+ ADCx->JSEQ = tmpreg1;
+}
+
+/**
+ * @brief Set the injected channels conversion value offset
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_InjectedChannel the ADC injected channel to set its offset.
+ * This parameter can be one of the following values:
+ * @arg ADC_INJ_CH_1 Injected Channel1 selected
+ * @arg ADC_INJ_CH_2 Injected Channel2 selected
+ * @arg ADC_INJ_CH_3 Injected Channel3 selected
+ * @arg ADC_INJ_CH_4 Injected Channel4 selected
+ * @param Offset the offset value for the selected ADC injected channel
+ * This parameter must be a 12bit value.
+ */
+void ADC_SetInjectedOffsetDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcInjCh(ADC_InjectedChannel));
+ assert_param(IsAdcOffsetValid(Offset));
+
+ tmp = (uint32_t)ADCx;
+ tmp += ADC_InjectedChannel;
+
+ /* Set the selected injected channel data offset */
+ *(__IO uint32_t*)tmp = (uint32_t)Offset;
+}
+
+/**
+ * @brief Returns the ADC injected channel conversion result
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_InjectedChannel the converted ADC injected channel.
+ * This parameter can be one of the following values:
+ * @arg ADC_INJ_CH_1 Injected Channel1 selected
+ * @arg ADC_INJ_CH_2 Injected Channel2 selected
+ * @arg ADC_INJ_CH_3 Injected Channel3 selected
+ * @arg ADC_INJ_CH_4 Injected Channel4 selected
+ * @return The Data conversion value.
+ */
+uint16_t ADC_GetInjectedConversionDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcInjCh(ADC_InjectedChannel));
+
+ tmp = (uint32_t)ADCx;
+ tmp += ADC_InjectedChannel + JDAT_OFFSET;
+
+ /* Returns the selected injected channel conversion data value */
+ return (uint16_t)(*(__IO uint32_t*)tmp);
+}
+
+/**
+ * @brief Enables or disables the analog watchdog on single/all regular
+ * or injected channels
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_AnalogWatchdog the ADC analog watchdog configuration.
+ * This parameter can be one of the following values:
+ * @arg ADC_ANALOG_WTDG_SINGLEREG_ENABLE Analog watchdog on a single regular channel
+ * @arg ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE Analog watchdog on a single injected channel
+ * @arg ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE Analog watchdog on a single regular or injected channel
+ * @arg ADC_ANALOG_WTDG_ALLREG_ENABLE Analog watchdog on all regular channel
+ * @arg ADC_ANALOG_WTDG_ALLINJEC_ENABLE Analog watchdog on all injected channel
+ * @arg ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE Analog watchdog on all regular and injected channels
+ * @arg ADC_ANALOG_WTDG_NONE No channel guarded by the analog watchdog
+ */
+void ADC_ConfigAnalogWatchdogWorkChannelType(ADC_Module* ADCx, uint32_t ADC_AnalogWatchdog)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcAnalogWatchdog(ADC_AnalogWatchdog));
+ /* Get the old register value */
+ tmpregister = ADCx->CTRL1;
+ /* Clear AWDEN, AWDENJ and AWDSGL bits */
+ tmpregister &= CTRL1_AWDG_MODE_RESET;
+ /* Set the analog watchdog enable mode */
+ tmpregister |= ADC_AnalogWatchdog;
+ /* Store the new register value */
+ ADCx->CTRL1 = tmpregister;
+}
+
+/**
+ * @brief Configures the high and low thresholds of the analog watchdog.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param HighThreshold the ADC analog watchdog High threshold value.
+ * This parameter must be a 12bit value.
+ * @param LowThreshold the ADC analog watchdog Low threshold value.
+ * This parameter must be a 12bit value.
+ */
+void ADC_ConfigAnalogWatchdogThresholds(ADC_Module* ADCx, uint16_t HighThreshold, uint16_t LowThreshold)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcValid(HighThreshold));
+ assert_param(IsAdcValid(LowThreshold));
+ /* Set the ADCx high threshold */
+ ADCx->WDGHIGH = HighThreshold;
+ /* Set the ADCx low threshold */
+ ADCx->WDGLOW = LowThreshold;
+}
+
+/**
+ * @brief Configures the analog watchdog guarded single channel
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_Channel the ADC channel to configure for the analog watchdog.
+ * This parameter can be one of the following values:
+ * @arg ADC_CH_0 ADC Channel0 selected
+ * @arg ADC_CH_1 ADC Channel1 selected
+ * @arg ADC_CH_2 ADC Channel2 selected
+ * @arg ADC_CH_3 ADC Channel3 selected
+ * @arg ADC_CH_4 ADC Channel4 selected
+ * @arg ADC_CH_5 ADC Channel5 selected
+ * @arg ADC_CH_6 ADC Channel6 selected
+ * @arg ADC_CH_7 ADC Channel7 selected
+ * @arg ADC_CH_8 ADC Channel8 selected
+ * @arg ADC_CH_9 ADC Channel9 selected
+ * @arg ADC_CH_10 ADC Channel10 selected
+ * @arg ADC_CH_11 ADC Channel11 selected
+ * @arg ADC_CH_12 ADC Channel12 selected
+ * @arg ADC_CH_13 ADC Channel13 selected
+ * @arg ADC_CH_14 ADC Channel14 selected
+ * @arg ADC_CH_15 ADC Channel15 selected
+ * @arg ADC_CH_16 ADC Channel16 selected
+ * @arg ADC_CH_17 ADC Channel17 selected
+ * @arg ADC_CH_18 ADC Channel18 selected
+ */
+void ADC_ConfigAnalogWatchdogSingleChannel(ADC_Module* ADCx, uint8_t ADC_Channel)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcChannel(ADC_Channel));
+ /* Get the old register value */
+ tmpregister = ADCx->CTRL1;
+ /* Clear the Analog watchdog channel select bits */
+ tmpregister &= CTRL1_AWDG_CH_RESET;
+ /* Set the Analog watchdog channel */
+ tmpregister |= ADC_Channel;
+ /* Store the new register value */
+ ADCx->CTRL1 = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the temperature sensor and Vrefint channel.
+ * @param Cmd new state of the temperature sensor.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableTempSensorVrefint(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the temperature sensor and Vrefint channel*/
+ ADC1->CTRL2 |= CTRL2_TSVREFE_SET;
+ _EnVref1p2()
+ }
+ else
+ {
+ /* Disable the temperature sensor and Vrefint channel*/
+ ADC1->CTRL2 &= CTRL2_TSVREFE_RESET;
+ _DisVref1p2()
+ }
+}
+
+/**
+ * @brief Checks whether the specified ADC flag is set or not.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_FLAG specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg ADC_FLAG_AWDG Analog watchdog flag
+ * @arg ADC_FLAG_ENDC End of conversion flag
+ * @arg ADC_FLAG_JENDC End of injected group conversion flag
+ * @arg ADC_FLAG_JSTR Start of injected group conversion flag
+ * @arg ADC_FLAG_STR Start of regular group conversion flag
+ * @return The new state of ADC_FLAG (SET or RESET).
+ */
+FlagStatus ADC_GetFlagStatus(ADC_Module* ADCx, uint8_t ADC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcGetFlag(ADC_FLAG));
+ /* Check the status of the specified ADC flag */
+ if ((ADCx->STS & ADC_FLAG) != (uint8_t)RESET)
+ {
+ /* ADC_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* ADC_FLAG is reset */
+ bitstatus = RESET;
+ }
+ /* Return the ADC_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the ADCx's pending flags.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_FLAG specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg ADC_FLAG_AWDG Analog watchdog flag
+ * @arg ADC_FLAG_ENDC End of conversion flag
+ * @arg ADC_FLAG_JENDC End of injected group conversion flag
+ * @arg ADC_FLAG_JSTR Start of injected group conversion flag
+ * @arg ADC_FLAG_STR Start of regular group conversion flag
+ */
+void ADC_ClearFlag(ADC_Module* ADCx, uint8_t ADC_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcClrFlag(ADC_FLAG));
+ /* Clear the selected ADC flags */
+ ADCx->STS = (~(uint32_t)ADC_FLAG & ADC_STS_RESERVE_MASK);
+}
+
+/**
+ * @brief Checks whether the specified ADC interrupt has occurred or not.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_IT specifies the ADC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg ADC_INT_ENDC End of conversion interrupt mask
+ * @arg ADC_INT_AWD Analog watchdog interrupt mask
+ * @arg ADC_INT_JENDC End of injected conversion interrupt mask
+ * @return The new state of ADC_IT (SET or RESET).
+ */
+INTStatus ADC_GetIntStatus(ADC_Module* ADCx, uint16_t ADC_IT)
+{
+ INTStatus bitstatus = RESET;
+ uint32_t itmask = 0, enablestatus = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcGetInt(ADC_IT));
+ /* Get the ADC IT index */
+ itmask = ADC_IT >> 8;
+ /* Get the ADC_IT enable bit status */
+ enablestatus = (ADCx->CTRL1 & (uint8_t)ADC_IT);
+ /* Check the status of the specified ADC interrupt */
+ if (((ADCx->STS & itmask) != (uint32_t)RESET) && enablestatus)
+ {
+ /* ADC_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* ADC_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the ADC_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the ADCx's interrupt pending bits.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_IT specifies the ADC interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg ADC_INT_ENDC End of conversion interrupt mask
+ * @arg ADC_INT_AWD Analog watchdog interrupt mask
+ * @arg ADC_INT_JENDC End of injected conversion interrupt mask
+ */
+void ADC_ClearIntPendingBit(ADC_Module* ADCx, uint16_t ADC_IT)
+{
+ uint8_t itmask = 0;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcInt(ADC_IT));
+ /* Get the ADC IT index */
+ itmask = (uint8_t)(ADC_IT >> 8);
+ /* Clear the selected ADC interrupt pending bits */
+ ADCx->STS = (~(uint32_t)itmask & ADC_STS_RESERVE_MASK);
+}
+
+
+/**
+ * @brief Initializes the ADCx peripheral according to the specified parameters
+ * in the ADC_InitStructEx.
+ * @param ADCx where x can be 1, 2 to select the ADC peripheral.
+ * @param ADC_InitStructEx pointer to an ADC_InitTypeEx structure that contains
+ * the configuration information for the specified ADC peripheral.
+ */
+void ADC_InitEx(ADC_Module* ADCx, ADC_InitTypeEx* ADC_InitStructEx)
+{
+ uint32_t tmpregister = 0;
+ /*ADC_SAMPT3 samp time sele ,as sam 103 or 303 style*/
+ if (ADC_InitStructEx->Samp303Style)
+ ADCx->SAMPT3 |= ADC_SAMPT3_SAMPSEL_MSK;
+ else
+ ADCx->SAMPT3 &= (~ADC_SAMPT3_SAMPSEL_MSK);
+
+ /*intial ADC_CTRL3 once initiall config*/
+ tmpregister = ADCx->CTRL3;
+ if (ADC_InitStructEx->VbatMinitEn)
+ {
+ tmpregister |= ADC_CTRL3_VABTMEN_MSK;
+ _EnVref1p2()
+ }
+ else
+ {
+ tmpregister &= (~ADC_CTRL3_VABTMEN_MSK);
+ _DisVref1p2()
+ }
+
+ if (ADC_InitStructEx->DeepPowerModEn)
+ tmpregister |= ADC_CTRL3_DPWMOD_MSK;
+ else
+ tmpregister &= (~ADC_CTRL3_DPWMOD_MSK);
+
+ if (ADC_InitStructEx->JendcIntEn)
+ tmpregister |= ADC_CTRL3_JENDCAIEN_MSK;
+ else
+ tmpregister &= (~ADC_CTRL3_JENDCAIEN_MSK);
+
+ if (ADC_InitStructEx->EndcIntEn)
+ tmpregister |= ADC_CTRL3_ENDCAIEN_MSK;
+ else
+ tmpregister &= (~ADC_CTRL3_ENDCAIEN_MSK);
+
+ if (ADC_InitStructEx->CalAtuoLoadEn)
+ tmpregister |= ADC_CTRL3_CALALD_MSK;
+ else
+ tmpregister &= (~ADC_CTRL3_CALALD_MSK);
+
+ if (ADC_InitStructEx->DifModCal)
+ tmpregister |= ADC_CTRL3_CALDIF_MSK;
+ else
+ tmpregister &= (~ADC_CTRL3_CALDIF_MSK);
+
+ tmpregister &= (~ADC_CTRL3_RES_MSK);
+ tmpregister |= ADC_InitStructEx->ResBit;
+
+ tmpregister &= (~ADC_CTRL3_CKMOD_MSK);
+ if (ADC_InitStructEx->ClkMode==ADC_CTRL3_CKMOD_PLL)
+ tmpregister |= ADC_CTRL3_CKMOD_MSK;
+
+ ADCx->CTRL3 = tmpregister;
+}
+/**
+ * @brief Configure differential channels enable.
+ * @param ADCx where x can be 1, 2 to select the ADC peripheral.
+ * @param DifChs differential channels,see @ADC_dif_sel_ch_definition. eg: ADC_DIFSEL_CHS_3|ADC_DIFSEL_CHS_4
+ */
+void ADC_SetDifChs(ADC_Module* ADCx,uint32_t DifChs)
+{
+ ADCx->DIFSEL = DifChs;
+}
+/**
+ * @brief Checks whether the specified ADC flag is set or not.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_FLAG_NEW specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg ADC_FLAG_RDY ADC ready flag
+ * @arg ADC_FLAG_PD_RDY ADC powerdown ready flag
+ * @return The new state of ADC_FLAG_NEW (SET or RESET).
+ */
+FlagStatus ADC_GetFlagStatusNew(ADC_Module* ADCx, uint8_t ADC_FLAG_NEW)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IsAdcModule(ADCx));
+ assert_param(IsAdcGetFlag(ADC_FLAG_NEW));
+ /* Check the status of the specified ADC flag */
+ if ((ADCx->CTRL3 & ADC_FLAG_NEW) != (uint8_t)RESET)
+ {
+ /* ADC_FLAG_NEW is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* ADC_FLAG_NEW is reset */
+ bitstatus = RESET;
+ }
+ /* Return the ADC_FLAG_NEW status */
+ return bitstatus;
+}
+/**
+ * @brief Set Adc calibration bypass or enable.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param en enable bypass calibration.
+ * This parameter can be one of the following values:
+ * @arg true bypass calibration
+ * @arg false not bypass calibration
+ */
+void ADC_SetBypassCalibration(ADC_Module* ADCx, FunctionalState en)
+{
+ uint32_t tmpregister = 0;
+
+ tmpregister = ADCx->CTRL3;
+ if (en)
+ tmpregister |= ADC_CTRL3_BPCAL_MSK;
+ else
+ tmpregister &= (~ADC_CTRL3_BPCAL_MSK);
+ ADCx->CTRL3 = tmpregister;
+}
+/**
+ * @brief Set Adc trans bits width.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ResultBitNum specifies num with adc trans width.
+ * This parameter can be one of the following values:
+ * @arg ADC_RST_BIT_12 12 bit trans
+ * @arg ADC_RST_BIT_10 10 bit trans
+ * @arg ADC_RST_BIT_8 8 bit trans
+ * @arg ADC_RESULT_BIT_6 6 bit trans
+ */
+void ADC_SetConvResultBitNum(ADC_Module* ADCx, uint32_t ResultBitNum)
+{
+ uint32_t tmpregister = 0;
+
+ tmpregister = ADCx->CTRL3;
+ tmpregister &= 0xFFFFFFFC;
+ tmpregister |= ResultBitNum;
+ ADCx->CTRL3 = tmpregister;
+ return;
+}
+/**
+ * @brief Set Adc Clock bits for AHB .
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ */
+void ADC_AHB_Clock_Mode_Config(ADC_Module* ADCx)
+{
+ ADCx->CTRL3 &= ADC_CLOCK_AHB;
+}
+
+/**
+ * @brief Set Adc Clock bits for PLL .
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ */
+void ADC_PLL_Clock_Mode_Config(ADC_Module* ADCx)
+{
+ ADCx->CTRL3 |= ADC_CLOCK_PLL;
+}
+/**
+ * @brief Configures the ADCHCLK prescaler.
+ * @param RCC_ADCHCLKPrescaler specifies the ADCHCLK prescaler.
+ * This parameter can be on of the following values:
+ * @arg RCC_ADCHCLK_DIV1 ADCHCLKPRE[3:0] = 0000, HCLK Clock Divided By 1
+ * @arg RCC_ADCHCLK_DIV2 ADCHCLKPRE[3:0] = 0001, HCLK Clock Divided By 2
+ * @arg RCC_ADCHCLK_DIV4 ADCHCLKPRE[3:0] = 0010, HCLK Clock Divided By 4
+ * @arg RCC_ADCHCLK_DIV6 ADCHCLKPRE[3:0] = 0011, HCLK Clock Divided By 6
+ * @arg RCC_ADCHCLK_DIV8 ADCHCLKPRE[3:0] = 0100, HCLK Clock Divided By 8
+ * @arg RCC_ADCHCLK_DIV10 ADCHCLKPRE[3:0] = 0101, HCLK Clock Divided By 10
+ * @arg RCC_ADCHCLK_DIV12 ADCHCLKPRE[3:0] = 0110, HCLK Clock Divided By 12
+ * @arg RCC_ADCHCLK_DIV16 ADCHCLKPRE[3:0] = 0111, HCLK Clock Divided By 16
+ * @arg RCC_ADCHCLK_DIV32 ADCHCLKPRE[3:0] = 1000, HCLK Clock Divided By 32
+ * @arg RCC_ADCHCLK_DIV32 ADCHCLKPRE[3:0] = others, HCLK Clock Divided By 32
+
+ * @arg RCC_ADCPLLCLK_DISABLE ADCPLLCLKPRES[4:0] = 0xxxx, ADC Pll Clock Disable
+ * @arg RCC_ADCPLLCLK_DIV1 ADCPLLCLKPRES[4:0] = 10000, Pll Clock Divided By 1
+ * @arg RCC_ADCPLLCLK_DIV2 ADCPLLCLKPRES[4:0] = 10001, Pll Clock Divided By 2
+ * @arg RCC_ADCPLLCLK_DIV4 ADCPLLCLKPRES[4:0] = 10010, Pll Clock Divided By 4
+ * @arg RCC_ADCPLLCLK_DIV6 ADCPLLCLKPRES[4:0] = 10011, Pll Clock Divided By 6
+ * @arg RCC_ADCPLLCLK_DIV8 ADCPLLCLKPRES[4:0] = 10100, Pll Clock Divided By 8
+ * @arg RCC_ADCPLLCLK_DIV10 ADCPLLCLKPRES[4:0] = 10101, Pll Clock Divided By 10
+ * @arg RCC_ADCPLLCLK_DIV12 ADCPLLCLKPRES[4:0] = 10110, Pll Clock Divided By 12
+ * @arg RCC_ADCPLLCLK_DIV16 ADCPLLCLKPRES[4:0] = 10111, Pll Clock Divided By 16
+ * @arg RCC_ADCPLLCLK_DIV32 ADCPLLCLKPRES[4:0] = 11000, Pll Clock Divided By 32
+ * @arg RCC_ADCPLLCLK_DIV64 ADCPLLCLKPRES[4:0] = 11001, Pll Clock Divided By 64
+ * @arg RCC_ADCPLLCLK_DIV128 ADCPLLCLKPRES[4:0] = 11010, Pll Clock Divided By 128
+ * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = 11011, Pll Clock Divided By 256
+ * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = others, Pll Clock Divided By 256
+ */
+void ADC_ConfigClk(ADC_CTRL3_CKMOD ADC_ClkMode, uint32_t RCC_ADCHCLKPrescaler)
+{
+ if (ADC_ClkMode==ADC_CTRL3_CKMOD_AHB){
+ RCC_ConfigAdcPllClk(RCC_ADCPLLCLK_DIV1, DISABLE);
+ RCC_ConfigAdcHclk(RCC_ADCHCLKPrescaler);
+ ADC_AHB_Clock_Mode_Config(ADC1);
+ ADC_AHB_Clock_Mode_Config(ADC2);
+ }else{
+ RCC_ConfigAdcPllClk(RCC_ADCHCLKPrescaler, ENABLE);
+ RCC_ConfigAdcHclk(RCC_ADCHCLK_DIV1);
+ ADC_PLL_Clock_Mode_Config(ADC1);
+ ADC_PLL_Clock_Mode_Config(ADC2);
+ }
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_bkp.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_bkp.c
new file mode 100644
index 0000000000..8659e6680d
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_bkp.c
@@ -0,0 +1,252 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_bkp.c
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32wb452_bkp.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup BKP
+ * @brief BKP driver modules
+ * @{
+ */
+
+/** @addtogroup BKP_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup BKP_Private_Defines
+ * @{
+ */
+
+/* ------------ BKP registers bit address in the alias region --------------- */
+#define BKP_OFFSET (BKP_BASE - PERIPH_BASE)
+
+/* --- CTRL Register ----*/
+
+/* Alias word address of TP_ALEV bit */
+#define CTRL_OFFSET (BKP_OFFSET + 0x30)
+#define TP_ALEV_BIT 0x01
+#define CTRL_TP_ALEV_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (TP_ALEV_BIT * 4))
+
+/* Alias word address of TP_EN bit */
+#define TP_EN_BIT 0x00
+#define CTRL_TP_EN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (TP_EN_BIT * 4))
+
+/* --- CTRLSTS Register ---*/
+
+/* Alias word address of TPINT_EN bit */
+#define CTRLSTS_OFFSET (BKP_OFFSET + 0x34)
+#define TPINT_EN_BIT 0x02
+#define CTRLSTS_TPINT_EN_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (TPINT_EN_BIT * 4))
+
+/* Alias word address of TINTF bit */
+#define TINTF_BIT 0x09
+#define CTRLSTS_TINTF_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (TINTF_BIT * 4))
+
+/* Alias word address of TEF bit */
+#define TEF_BIT 0x08
+#define CTRLSTS_TEF_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (TEF_BIT * 4))
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup BKP_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup BKP_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup BKP_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup BKP_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the BKP peripheral registers to their default reset values.
+ */
+void BKP_DeInit(void)
+{
+ RCC_EnableBackupReset(ENABLE);
+ RCC_EnableBackupReset(DISABLE);
+}
+
+/**
+ * @brief Configures the Tamper Pin active level.
+ * @param BKP_TamperPinLevel specifies the Tamper Pin active level.
+ * This parameter can be one of the following values:
+ * @arg BKP_TP_HIGH Tamper pin active on high level
+ * @arg BKP_TP_LOW Tamper pin active on low level
+ */
+void BKP_ConfigTPLevel(uint16_t BKP_TamperPinLevel)
+{
+ /* Check the parameters */
+ assert_param(IS_BKP_TP_LEVEL(BKP_TamperPinLevel));
+ *(__IO uint32_t*)CTRL_TP_ALEV_BB = BKP_TamperPinLevel;
+}
+
+/**
+ * @brief Enables or disables the Tamper Pin activation.
+ * @param Cmd new state of the Tamper Pin activation.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void BKP_TPEnable(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)CTRL_TP_EN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Enables or disables the Tamper Pin Interrupt.
+ * @param Cmd new state of the Tamper Pin Interrupt.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void BKP_TPIntEnable(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)CTRLSTS_TPINT_EN_BB = (uint32_t)Cmd;
+}
+
+
+/**
+ * @brief Writes user data to the specified Data Backup Register.
+ * @param BKP_DAT specifies the Data Backup Register.
+ * This parameter can be BKP_DATx where x:[1, 42]
+ * @param Data data to write
+ */
+void BKP_WriteBkpData(uint16_t BKP_DAT, uint16_t Data)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_BKP_DAT(BKP_DAT));
+
+ tmp = (uint32_t)BKP_BASE;
+ tmp += BKP_DAT;
+
+ *(__IO uint32_t*)tmp = Data;
+}
+
+/**
+ * @brief Reads data from the specified Data Backup Register.
+ * @param BKP_DAT specifies the Data Backup Register.
+ * This parameter can be BKP_DATx where x:[1, 42]
+ * @return The content of the specified Data Backup Register
+ */
+uint16_t BKP_ReadBkpData(uint16_t BKP_DAT)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_BKP_DAT(BKP_DAT));
+
+ tmp = (uint32_t)BKP_BASE;
+ tmp += BKP_DAT;
+
+ return (*(__IO uint16_t*)tmp);
+}
+
+/**
+ * @brief Checks whether the Tamper Pin Event flag is set or not.
+ * @return The new state of the Tamper Pin Event flag (SET or RESET).
+ */
+FlagStatus BKP_GetTEFlag(void)
+{
+ return (FlagStatus)(*(__IO uint32_t*)CTRLSTS_TEF_BB);
+}
+
+/**
+ * @brief Clears Tamper Pin Event pending flag.
+ */
+void BKP_ClrTEFlag(void)
+{
+ /* Set CTE bit to clear Tamper Pin Event flag */
+ BKP->CTRLSTS |= BKP_CTRLSTS_CLRTE;
+}
+
+/**
+ * @brief Checks whether the Tamper Pin Interrupt has occurred or not.
+ * @return The new state of the Tamper Pin Interrupt (SET or RESET).
+ */
+INTStatus BKP_GetTINTFlag(void)
+{
+ return (INTStatus)(*(__IO uint32_t*)CTRLSTS_TINTF_BB);
+}
+
+/**
+ * @brief Clears Tamper Pin Interrupt pending bit.
+ */
+void BKP_ClrTINTFlag(void)
+{
+ /* Set CTI bit to clear Tamper Pin Interrupt pending bit */
+ BKP->CTRLSTS |= BKP_CTRLSTS_CLRTINT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_can.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_can.c
new file mode 100644
index 0000000000..1c727b66b5
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_can.c
@@ -0,0 +1,1478 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_can.c
+ * @author Nations
+ * @version v1.0.1
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32wb452_can.h"
+#include "n32wb452_rcc.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CAN
+ * @brief CAN driver modules
+ * @{
+ */
+
+/** @addtogroup CAN_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Private_Defines
+ * @{
+ */
+
+/* CAN Master Control Register bits */
+#define MCTRL_DBGF ((uint32_t)0x00010000) /* Debug freeze */
+#define MCTRL_MRST ((uint32_t)0x00010000) /* software master reset */
+
+/* CAN Mailbox Transmit Request */
+#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */
+
+/* CAN Filter Master Register bits */
+#define FMC_FINITM ((uint32_t)0x00000001) /* Filter init mode */
+
+/* Time out for INAK bit */
+#define INIAK_TIMEOUT ((uint32_t)0x0000FFFF)
+/* Time out for SLAK bit */
+#define SLPAK_TIMEOUT ((uint32_t)0x0000FFFF)
+
+/* Flags in TSTS register */
+#define CAN_FLAGS_TSTS ((uint32_t)0x08000000)
+/* Flags in RFF1 register */
+#define CAN_FLAGS_RFF1 ((uint32_t)0x04000000)
+/* Flags in RFF0 register */
+#define CAN_FLAGS_RFF0 ((uint32_t)0x02000000)
+/* Flags in MSTS register */
+#define CAN_FLAGS_MSTS ((uint32_t)0x01000000)
+/* Flags in ESTS register */
+#define CAN_FLAGS_ESTS ((uint32_t)0x00F00000)
+
+/* Mailboxes definition */
+#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
+#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
+#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
+
+#define CAN_MODE_MASK ((uint32_t)0x00000003)
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Private_FunctionPrototypes
+ * @{
+ */
+
+static INTStatus CheckINTStatus(uint32_t CAN_Reg, uint32_t Int_Bit);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the CAN peripheral registers to their default reset values.
+ * @param CANx where x can be 1 or 2 to select the CAN peripheral.
+ */
+void CAN_DeInit(CAN_Module* CANx)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ if (CANx == CAN1)
+ {
+ /* Enable CAN1 reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_CAN1, ENABLE);
+ /* Release CAN1 from reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_CAN1, DISABLE);
+ }
+ else
+ {
+ /* Enable CAN2 reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_CAN2, ENABLE);
+ /* Release CAN2 from reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_CAN2, DISABLE);
+ }
+}
+
+/**
+ * @brief Initializes the CAN peripheral according to the specified
+ * parameters in the CAN_InitParam.
+ * @param CANx where x can be 1 or 2 to to select the CAN
+ * peripheral.
+ * @param CAN_InitParam pointer to a CAN_InitType structure that
+ * contains the configuration information for the
+ * CAN peripheral.
+ * @return Constant indicates initialization succeed which will be
+ * CAN_InitSTS_Failed or CAN_InitSTS_Success.
+ */
+uint8_t CAN_Init(CAN_Module* CANx, CAN_InitType* CAN_InitParam)
+{
+ uint8_t InitStatus = CAN_InitSTS_Failed;
+ uint32_t wait_ack = 0x00000000;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->TTCM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->ABOM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->AWKUM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->NART));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->RFLM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->TXFP));
+ assert_param(IS_CAN_MODE(CAN_InitParam->OperatingMode));
+ assert_param(IS_CAN_RSJW(CAN_InitParam->RSJW));
+ assert_param(IS_CAN_TBS1(CAN_InitParam->TBS1));
+ assert_param(IS_CAN_TBS2(CAN_InitParam->TBS2));
+ assert_param(IS_CAN_BAUDRATEPRESCALER(CAN_InitParam->BaudRatePrescaler));
+
+ /* Exit from sleep mode */
+ CANx->MCTRL &= (~(uint32_t)CAN_MCTRL_SLPRQ);
+
+ /* Request initialisation */
+ CANx->MCTRL |= CAN_MCTRL_INIRQ;
+
+ /* Wait the acknowledge */
+ while (((CANx->MSTS & CAN_MSTS_INIAK) != CAN_MSTS_INIAK) && (wait_ack != INIAK_TIMEOUT))
+ {
+ wait_ack++;
+ }
+
+ /* Check acknowledge */
+ if ((CANx->MSTS & CAN_MSTS_INIAK) != CAN_MSTS_INIAK)
+ {
+ InitStatus = CAN_InitSTS_Failed;
+ }
+ else
+ {
+ /* Set the time triggered communication mode */
+ if (CAN_InitParam->TTCM == ENABLE)
+ {
+ CANx->MCTRL |= CAN_MCTRL_TTCM;
+ }
+ else
+ {
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_TTCM;
+ }
+
+ /* Set the automatic bus-off management */
+ if (CAN_InitParam->ABOM == ENABLE)
+ {
+ CANx->MCTRL |= CAN_MCTRL_ABOM;
+ }
+ else
+ {
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_ABOM;
+ }
+
+ /* Set the automatic wake-up mode */
+ if (CAN_InitParam->AWKUM == ENABLE)
+ {
+ CANx->MCTRL |= CAN_MCTRL_AWKUM;
+ }
+ else
+ {
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_AWKUM;
+ }
+
+ /* Set the no automatic retransmission */
+ if (CAN_InitParam->NART == ENABLE)
+ {
+ CANx->MCTRL |= CAN_MCTRL_NART;
+ }
+ else
+ {
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_NART;
+ }
+
+ /* Set the receive DATFIFO locked mode */
+ if (CAN_InitParam->RFLM == ENABLE)
+ {
+ CANx->MCTRL |= CAN_MCTRL_RFLM;
+ }
+ else
+ {
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_RFLM;
+ }
+
+ /* Set the transmit DATFIFO priority */
+ if (CAN_InitParam->TXFP == ENABLE)
+ {
+ CANx->MCTRL |= CAN_MCTRL_TXFP;
+ }
+ else
+ {
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_TXFP;
+ }
+
+ /* Set the bit timing register */
+ CANx->BTIM = (uint32_t)((uint32_t)CAN_InitParam->OperatingMode << 30) | ((uint32_t)CAN_InitParam->RSJW << 24)
+ | ((uint32_t)CAN_InitParam->TBS1 << 16) | ((uint32_t)CAN_InitParam->TBS2 << 20)
+ | ((uint32_t)CAN_InitParam->BaudRatePrescaler - 1);
+
+ /* Request leave initialisation */
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_INIRQ;
+
+ /* Wait the acknowledge */
+ wait_ack = 0;
+
+ while (((CANx->MSTS & CAN_MSTS_INIAK) == CAN_MSTS_INIAK) && (wait_ack != INIAK_TIMEOUT))
+ {
+ wait_ack++;
+ }
+
+ /* ...and check acknowledged */
+ if ((CANx->MSTS & CAN_MSTS_INIAK) == CAN_MSTS_INIAK)
+ {
+ InitStatus = CAN_InitSTS_Failed;
+ }
+ else
+ {
+ InitStatus = CAN_InitSTS_Success;
+ }
+ }
+
+ /* At this step, return the status of initialization */
+ return InitStatus;
+}
+
+/**
+ * @brief Initializes the CAN1 peripheral according to the specified
+ * parameters in the CAN_InitFilterStruct.
+ * @param CAN_InitFilterStruct pointer to a CAN_FilterInitType
+ * structure that contains the configuration
+ * information.
+ */
+void CAN1_InitFilter(CAN_FilterInitType* CAN_InitFilterStruct)
+{
+ uint32_t filter_number_bit_pos = 0;
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_NUM(CAN_InitFilterStruct->Filter_Num));
+ assert_param(IS_CAN_FILTER_MODE(CAN_InitFilterStruct->Filter_Mode));
+ assert_param(IS_CAN_FILTER_SCALE(CAN_InitFilterStruct->Filter_Scale));
+ assert_param(IS_CAN_FILTER_FIFO(CAN_InitFilterStruct->Filter_FIFOAssignment));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitFilterStruct->Filter_Act));
+
+ filter_number_bit_pos = ((uint32_t)1) << CAN_InitFilterStruct->Filter_Num;
+
+ /* Initialisation mode for the filter */
+ CAN1->FMC |= FMC_FINITM;
+
+ /* Filter Deactivation */
+ CAN1->FA1 &= ~(uint32_t)filter_number_bit_pos;
+
+ /* Filter Scale */
+ if (CAN_InitFilterStruct->Filter_Scale == CAN_Filter_16bitScale)
+ {
+ /* 16-bit scale for the filter */
+ CAN1->FS1 &= ~(uint32_t)filter_number_bit_pos;
+
+ /* First 16-bit identifier and First 16-bit mask */
+ /* Or First 16-bit identifier and Second 16-bit identifier */
+ CAN1->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR1 =
+ ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_LowId) << 16)
+ | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_LowId);
+
+ /* Second 16-bit identifier and Second 16-bit mask */
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+ CAN1->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR2 =
+ ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_HighId) << 16)
+ | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_HighId);
+ }
+
+ if (CAN_InitFilterStruct->Filter_Scale == CAN_Filter_32bitScale)
+ {
+ /* 32-bit scale for the filter */
+ CAN1->FS1 |= filter_number_bit_pos;
+ /* 32-bit identifier or First 32-bit identifier */
+ CAN1->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR1 =
+ ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_HighId) << 16)
+ | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_LowId);
+ /* 32-bit mask or Second 32-bit identifier */
+ CAN1->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR2 =
+ ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_HighId) << 16)
+ | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_LowId);
+ }
+
+ /* Filter Mode */
+ if (CAN_InitFilterStruct->Filter_Mode == CAN_Filter_IdMaskMode)
+ {
+ /*Id/Mask mode for the filter*/
+ CAN1->FM1 &= ~(uint32_t)filter_number_bit_pos;
+ }
+ else /* CAN_InitFilterStruct->Filter_Mode == CAN_Filter_IdListMode */
+ {
+ /*Identifier list mode for the filter*/
+ CAN1->FM1 |= (uint32_t)filter_number_bit_pos;
+ }
+
+ /* Filter DATFIFO assignment */
+ if (CAN_InitFilterStruct->Filter_FIFOAssignment == CAN_Filter_FIFO0)
+ {
+ /* DATFIFO 0 assignation for the filter */
+ CAN1->FFA1 &= ~(uint32_t)filter_number_bit_pos;
+ }
+
+ if (CAN_InitFilterStruct->Filter_FIFOAssignment == CAN_Filter_FIFO1)
+ {
+ /* DATFIFO 1 assignation for the filter */
+ CAN1->FFA1 |= (uint32_t)filter_number_bit_pos;
+ }
+
+ /* Filter activation */
+ if (CAN_InitFilterStruct->Filter_Act == ENABLE)
+ {
+ CAN1->FA1 |= filter_number_bit_pos;
+ }
+
+ /* Leave the initialisation mode for the filter */
+ CAN1->FMC &= ~FMC_FINITM;
+}
+
+/**
+ * @brief Initializes the CAN2 peripheral according to the specified
+ * parameters in the CAN_InitFilterStruct.
+ * @param CAN_InitFilterStruct pointer to a CAN_FilterInitType
+ * structure that contains the configuration
+ * information.
+ */
+void CAN2_InitFilter(CAN_FilterInitType* CAN_InitFilterStruct)
+{
+ uint32_t filter_number_bit_pos = 0;
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_NUM(CAN_InitFilterStruct->Filter_Num));
+ assert_param(IS_CAN_FILTER_MODE(CAN_InitFilterStruct->Filter_Mode));
+ assert_param(IS_CAN_FILTER_SCALE(CAN_InitFilterStruct->Filter_Scale));
+ assert_param(IS_CAN_FILTER_FIFO(CAN_InitFilterStruct->Filter_FIFOAssignment));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitFilterStruct->Filter_Act));
+
+ filter_number_bit_pos = ((uint32_t)1) << CAN_InitFilterStruct->Filter_Num;
+
+ /* Initialisation mode for the filter */
+ CAN2->FMC |= FMC_FINITM;
+
+ /* Filter Deactivation */
+ CAN2->FA1 &= ~(uint32_t)filter_number_bit_pos;
+
+ /* Filter Scale */
+ if (CAN_InitFilterStruct->Filter_Scale == CAN_Filter_16bitScale)
+ {
+ /* 16-bit scale for the filter */
+ CAN2->FS1 &= ~(uint32_t)filter_number_bit_pos;
+
+ /* First 16-bit identifier and First 16-bit mask */
+ /* Or First 16-bit identifier and Second 16-bit identifier */
+ CAN2->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR1 =
+ ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_LowId) << 16)
+ | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_LowId);
+
+ /* Second 16-bit identifier and Second 16-bit mask */
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+ CAN2->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR2 =
+ ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_HighId) << 16)
+ | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_HighId);
+ }
+
+ if (CAN_InitFilterStruct->Filter_Scale == CAN_Filter_32bitScale)
+ {
+ /* 32-bit scale for the filter */
+ CAN2->FS1 |= filter_number_bit_pos;
+ /* 32-bit identifier or First 32-bit identifier */
+ CAN2->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR1 =
+ ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_HighId) << 16)
+ | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_LowId);
+ /* 32-bit mask or Second 32-bit identifier */
+ CAN2->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR2 =
+ ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_HighId) << 16)
+ | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_LowId);
+ }
+
+ /* Filter Mode */
+ if (CAN_InitFilterStruct->Filter_Mode == CAN_Filter_IdMaskMode)
+ {
+ /*Id/Mask mode for the filter*/
+ CAN2->FM1 &= ~(uint32_t)filter_number_bit_pos;
+ }
+ else /* CAN_InitFilterStruct->Filter_Mode == CAN_Filter_IdListMode */
+ {
+ /*Identifier list mode for the filter*/
+ CAN2->FM1 |= (uint32_t)filter_number_bit_pos;
+ }
+
+ /* Filter DATFIFO assignment */
+ if (CAN_InitFilterStruct->Filter_FIFOAssignment == CAN_Filter_FIFO0)
+ {
+ /* DATFIFO 0 assignation for the filter */
+ CAN2->FFA1 &= ~(uint32_t)filter_number_bit_pos;
+ }
+
+ if (CAN_InitFilterStruct->Filter_FIFOAssignment == CAN_Filter_FIFO1)
+ {
+ /* DATFIFO 1 assignation for the filter */
+ CAN2->FFA1 |= (uint32_t)filter_number_bit_pos;
+ }
+
+ /* Filter activation */
+ if (CAN_InitFilterStruct->Filter_Act == ENABLE)
+ {
+ CAN2->FA1 |= filter_number_bit_pos;
+ }
+
+ /* Leave the initialisation mode for the filter */
+ CAN2->FMC &= ~FMC_FINITM;
+}
+
+/**
+ * @brief Fills each CAN_InitParam member with its default value.
+ * @param CAN_InitParam pointer to a CAN_InitType structure which
+ * will be initialized.
+ */
+void CAN_InitStruct(CAN_InitType* CAN_InitParam)
+{
+ /* Reset CAN init structure parameters values */
+
+ /* Initialize the time triggered communication mode */
+ CAN_InitParam->TTCM = DISABLE;
+
+ /* Initialize the automatic bus-off management */
+ CAN_InitParam->ABOM = DISABLE;
+
+ /* Initialize the automatic wake-up mode */
+ CAN_InitParam->AWKUM = DISABLE;
+
+ /* Initialize the no automatic retransmission */
+ CAN_InitParam->NART = DISABLE;
+
+ /* Initialize the receive DATFIFO locked mode */
+ CAN_InitParam->RFLM = DISABLE;
+
+ /* Initialize the transmit DATFIFO priority */
+ CAN_InitParam->TXFP = DISABLE;
+
+ /* Initialize the OperatingMode member */
+ CAN_InitParam->OperatingMode = CAN_Normal_Mode;
+
+ /* Initialize the RSJW member */
+ CAN_InitParam->RSJW = CAN_RSJW_1tq;
+
+ /* Initialize the TBS1 member */
+ CAN_InitParam->TBS1 = CAN_TBS1_4tq;
+
+ /* Initialize the TBS2 member */
+ CAN_InitParam->TBS2 = CAN_TBS2_3tq;
+
+ /* Initialize the BaudRatePrescaler member */
+ CAN_InitParam->BaudRatePrescaler = 1;
+}
+
+/**
+ * @brief Enables or disables the DBG Freeze for CAN.
+ * @param CANx where x can be 1 or 2 to to select the CAN peripheral.
+ * @param Cmd new state of the CAN peripheral. This parameter can
+ * be: ENABLE or DISABLE.
+ */
+void CAN_DebugFreeze(CAN_Module* CANx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable Debug Freeze */
+ CANx->MCTRL |= MCTRL_DBGF;
+ }
+ else
+ {
+ /* Disable Debug Freeze */
+ CANx->MCTRL &= ~MCTRL_DBGF;
+ }
+}
+
+/**
+ * @brief Enables or disabes the CAN Time TriggerOperation communication mode.
+ * @param CANx where x can be 1 or 2 to to select the CAN peripheral.
+ * @param Cmd Mode new state , can be one of @ref FunctionalState.
+ * @note when enabled, Time stamp (TIME[15:0]) value is sent in the last
+ * two data bytes of the 8-byte message: TIME[7:0] in data byte 6
+ * and TIME[15:8] in data byte 7
+ * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be
+ * sent over the CAN bus.
+ */
+void CAN_EnTTComMode(CAN_Module* CANx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the TTCM mode */
+ CANx->MCTRL |= CAN_MCTRL_TTCM;
+
+ /* Set TGT bits */
+ CANx->sTxMailBox[0].TMDT |= ((uint32_t)CAN_TMDT0_TGT);
+ CANx->sTxMailBox[1].TMDT |= ((uint32_t)CAN_TMDT1_TGT);
+ CANx->sTxMailBox[2].TMDT |= ((uint32_t)CAN_TMDT2_TGT);
+ }
+ else
+ {
+ /* Disable the TTCM mode */
+ CANx->MCTRL &= (uint32_t)(~(uint32_t)CAN_MCTRL_TTCM);
+
+ /* Reset TGT bits */
+ CANx->sTxMailBox[0].TMDT &= ((uint32_t)~CAN_TMDT0_TGT);
+ CANx->sTxMailBox[1].TMDT &= ((uint32_t)~CAN_TMDT1_TGT);
+ CANx->sTxMailBox[2].TMDT &= ((uint32_t)~CAN_TMDT2_TGT);
+ }
+}
+/**
+ * @brief Initiates the transmission of a message.
+ * @param CANx where x can be 1 or 2 to to select the CAN peripheral.
+ * @param TxMessage pointer to a structure which contains CAN Id, CAN
+ * DLC and CAN data.
+ * @return The number of the mailbox that is used for transmission
+ * or CAN_TxSTS_NoMailBox if there is no empty mailbox.
+ */
+uint8_t CAN_TransmitMessage(CAN_Module* CANx, CanTxMessage* TxMessage)
+{
+ uint8_t transmit_mailbox = 0;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_ID(TxMessage->IDE));
+ assert_param(IS_CAN_RTRQ(TxMessage->RTR));
+ assert_param(IS_CAN_DLC(TxMessage->DLC));
+
+ /* Select one empty transmit mailbox */
+ if ((CANx->TSTS & CAN_TSTS_TMEM0) == CAN_TSTS_TMEM0)
+ {
+ transmit_mailbox = 0;
+ }
+ else if ((CANx->TSTS & CAN_TSTS_TMEM1) == CAN_TSTS_TMEM1)
+ {
+ transmit_mailbox = 1;
+ }
+ else if ((CANx->TSTS & CAN_TSTS_TMEM2) == CAN_TSTS_TMEM2)
+ {
+ transmit_mailbox = 2;
+ }
+ else
+ {
+ transmit_mailbox = CAN_TxSTS_NoMailBox;
+ }
+
+ if (transmit_mailbox != CAN_TxSTS_NoMailBox)
+ {
+ /* Set up the Id */
+ CANx->sTxMailBox[transmit_mailbox].TMI &= TMIDxR_TXRQ;
+ if (TxMessage->IDE == CAN_Standard_Id)
+ {
+ assert_param(IS_CAN_STDID(TxMessage->StdId));
+ CANx->sTxMailBox[transmit_mailbox].TMI |= ((TxMessage->StdId << 21) | TxMessage->RTR);
+ }
+ else
+ {
+ assert_param(IS_CAN_EXTID(TxMessage->ExtId));
+ CANx->sTxMailBox[transmit_mailbox].TMI |= ((TxMessage->ExtId << 3) | TxMessage->IDE | TxMessage->RTR);
+ }
+
+ /* Set up the DLC */
+ TxMessage->DLC &= (uint8_t)0x0000000F;
+ CANx->sTxMailBox[transmit_mailbox].TMDT &= (uint32_t)0xFFFFFFF0;
+ CANx->sTxMailBox[transmit_mailbox].TMDT |= TxMessage->DLC;
+
+ /* Set up the data field */
+ CANx->sTxMailBox[transmit_mailbox].TMDL =
+ (((uint32_t)TxMessage->Data[3] << 24) | ((uint32_t)TxMessage->Data[2] << 16)
+ | ((uint32_t)TxMessage->Data[1] << 8) | ((uint32_t)TxMessage->Data[0]));
+ CANx->sTxMailBox[transmit_mailbox].TMDH =
+ (((uint32_t)TxMessage->Data[7] << 24) | ((uint32_t)TxMessage->Data[6] << 16)
+ | ((uint32_t)TxMessage->Data[5] << 8) | ((uint32_t)TxMessage->Data[4]));
+ /* Request transmission */
+ CANx->sTxMailBox[transmit_mailbox].TMI |= TMIDxR_TXRQ;
+ }
+ return transmit_mailbox;
+}
+
+/**
+ * @brief Checks the transmission of a message.
+ * @param CANx where x can be 1 or 2 to to select the
+ * CAN peripheral.
+ * @param TransmitMailbox the number of the mailbox that is used for
+ * transmission.
+ * @return CAN_TxSTS_Ok if the CAN driver transmits the message, CAN_TxSTS_Failed
+ * in an other case.
+ */
+uint8_t CAN_TransmitSTS(CAN_Module* CANx, uint8_t TransmitMailbox)
+{
+ uint32_t state = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
+
+ switch (TransmitMailbox)
+ {
+ case (CAN_TXMAILBOX_0):
+ state = CANx->TSTS & (CAN_TSTS_RQCPM0 | CAN_TSTS_TXOKM0 | CAN_TSTS_TMEM0);
+ break;
+ case (CAN_TXMAILBOX_1):
+ state = CANx->TSTS & (CAN_TSTS_RQCPM1 | CAN_TSTS_TXOKM1 | CAN_TSTS_TMEM1);
+ break;
+ case (CAN_TXMAILBOX_2):
+ state = CANx->TSTS & (CAN_TSTS_RQCPM2 | CAN_TSTS_TXOKM2 | CAN_TSTS_TMEM2);
+ break;
+ default:
+ state = CAN_TxSTS_Failed;
+ break;
+ }
+ switch (state)
+ {
+ /* transmit pending */
+ case (0x0):
+ state = CAN_TxSTS_Pending;
+ break;
+ /* transmit failed */
+ case (CAN_TSTS_RQCPM0 | CAN_TSTS_TMEM0):
+ state = CAN_TxSTS_Failed;
+ break;
+ case (CAN_TSTS_RQCPM1 | CAN_TSTS_TMEM1):
+ state = CAN_TxSTS_Failed;
+ break;
+ case (CAN_TSTS_RQCPM2 | CAN_TSTS_TMEM2):
+ state = CAN_TxSTS_Failed;
+ break;
+ /* transmit succeeded */
+ case (CAN_TSTS_RQCPM0 | CAN_TSTS_TXOKM0 | CAN_TSTS_TMEM0):
+ state = CAN_TxSTS_Ok;
+ break;
+ case (CAN_TSTS_RQCPM1 | CAN_TSTS_TXOKM1 | CAN_TSTS_TMEM1):
+ state = CAN_TxSTS_Ok;
+ break;
+ case (CAN_TSTS_RQCPM2 | CAN_TSTS_TXOKM2 | CAN_TSTS_TMEM2):
+ state = CAN_TxSTS_Ok;
+ break;
+ default:
+ state = CAN_TxSTS_Failed;
+ break;
+ }
+ return (uint8_t)state;
+}
+
+/**
+ * @brief Cancels a transmit request.
+ * @param CANx where x can be 1 or 2 to to select the CAN peripheral.
+ * @param Mailbox Mailbox number.
+ */
+void CAN_CancelTransmitMessage(CAN_Module* CANx, uint8_t Mailbox)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));
+ /* abort transmission */
+ switch (Mailbox)
+ {
+ case (CAN_TXMAILBOX_0):
+ CANx->TSTS |= CAN_TSTS_ABRQM0;
+ break;
+ case (CAN_TXMAILBOX_1):
+ CANx->TSTS |= CAN_TSTS_ABRQM1;
+ break;
+ case (CAN_TXMAILBOX_2):
+ CANx->TSTS |= CAN_TSTS_ABRQM2;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Receives a message.
+ * @param CANx where x can be 1 or 2 to to select the CAN peripheral.
+ * @param FIFONum Receive DATFIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @param RxMessage pointer to a structure receive message which contains
+ * CAN Id, CAN DLC, CAN datas and FMI number.
+ */
+void CAN_ReceiveMessage(CAN_Module* CANx, uint8_t FIFONum, CanRxMessage* RxMessage)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FIFO(FIFONum));
+ /* Get the Id */
+ RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONum].RMI;
+ if (RxMessage->IDE == CAN_Standard_Id)
+ {
+ RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONum].RMI >> 21);
+ }
+ else
+ {
+ RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONum].RMI >> 3);
+ }
+
+ RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONum].RMI;
+ /* Get the DLC */
+ RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONum].RMDT;
+ /* Get the FMI */
+ RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDT >> 8);
+ /* Get the data field */
+ RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONum].RMDL;
+ RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDL >> 8);
+ RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDL >> 16);
+ RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDL >> 24);
+ RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONum].RMDH;
+ RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDH >> 8);
+ RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDH >> 16);
+ RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDH >> 24);
+ /* Release the DATFIFO */
+ /* Release FIFO0 */
+ if (FIFONum == CAN_FIFO0)
+ {
+ CANx->RFF0 |= CAN_RFF0_RFFOM0;
+ }
+ /* Release FIFO1 */
+ else /* FIFONum == CAN_FIFO1 */
+ {
+ CANx->RFF1 |= CAN_RFF1_RFFOM1;
+ }
+}
+
+/**
+ * @brief Releases the specified DATFIFO.
+ * @param CANx where x can be 1 or 2 to to select the CAN peripheral.
+ * @param FIFONum DATFIFO to release, CAN_FIFO0 or CAN_FIFO1.
+ */
+void CAN_ReleaseFIFO(CAN_Module* CANx, uint8_t FIFONum)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FIFO(FIFONum));
+ /* Release FIFO0 */
+ if (FIFONum == CAN_FIFO0)
+ {
+ CANx->RFF0 |= CAN_RFF0_RFFOM0;
+ }
+ /* Release FIFO1 */
+ else /* FIFONum == CAN_FIFO1 */
+ {
+ CANx->RFF1 |= CAN_RFF1_RFFOM1;
+ }
+}
+
+/**
+ * @brief Returns the number of pending messages.
+ * @param CANx where x can be 1 or 2 to to select the CAN peripheral.
+ * @param FIFONum Receive DATFIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @return NbMessage : which is the number of pending message.
+ */
+uint8_t CAN_PendingMessage(CAN_Module* CANx, uint8_t FIFONum)
+{
+ uint8_t message_pending = 0;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FIFO(FIFONum));
+ if (FIFONum == CAN_FIFO0)
+ {
+ message_pending = (uint8_t)(CANx->RFF0 & (uint32_t)0x03);
+ }
+ else if (FIFONum == CAN_FIFO1)
+ {
+ message_pending = (uint8_t)(CANx->RFF1 & (uint32_t)0x03);
+ }
+ else
+ {
+ message_pending = 0;
+ }
+ return message_pending;
+}
+
+/**
+ * @brief Select the CAN Operation mode.
+ * @param CANx where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_OperatingMode CAN Operating Mode. This parameter can be one
+ * of @ref CAN_operating_mode enumeration.
+ * @return status of the requested mode which can be
+ * - CAN_ModeSTS_Failed CAN failed entering the specific mode
+ * - CAN_ModeSTS_Success CAN Succeed entering the specific mode
+
+ */
+uint8_t CAN_OperatingModeReq(CAN_Module* CANx, uint8_t CAN_OperatingMode)
+{
+ uint8_t status = CAN_ModeSTS_Failed;
+
+ /* Timeout for INAK or also for SLAK bits*/
+ uint32_t timeout = INIAK_TIMEOUT;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode));
+
+ if (CAN_OperatingMode == CAN_Operating_InitMode)
+ {
+ /* Request initialisation */
+ CANx->MCTRL = (uint32_t)((CANx->MCTRL & (uint32_t)(~(uint32_t)CAN_MCTRL_SLPRQ)) | CAN_MCTRL_INIRQ);
+
+ /* Wait the acknowledge */
+ while (((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_INIAK) && (timeout != 0))
+ {
+ timeout--;
+ }
+ if ((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_INIAK)
+ {
+ status = CAN_ModeSTS_Failed;
+ }
+ else
+ {
+ status = CAN_ModeSTS_Success;
+ }
+ }
+ else if (CAN_OperatingMode == CAN_Operating_NormalMode)
+ {
+ /* Request leave initialisation and sleep mode and enter Normal mode */
+ CANx->MCTRL &= (uint32_t)(~(CAN_MCTRL_SLPRQ | CAN_MCTRL_INIRQ));
+
+ /* Wait the acknowledge */
+ while (((CANx->MSTS & CAN_MODE_MASK) != 0) && (timeout != 0))
+ {
+ timeout--;
+ }
+ if ((CANx->MSTS & CAN_MODE_MASK) != 0)
+ {
+ status = CAN_ModeSTS_Failed;
+ }
+ else
+ {
+ status = CAN_ModeSTS_Success;
+ }
+ }
+ else if (CAN_OperatingMode == CAN_Operating_SleepMode)
+ {
+ /* Request Sleep mode */
+ CANx->MCTRL = (uint32_t)((CANx->MCTRL & (uint32_t)(~(uint32_t)CAN_MCTRL_INIRQ)) | CAN_MCTRL_SLPRQ);
+
+ /* Wait the acknowledge */
+ while (((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_SLPAK) && (timeout != 0))
+ {
+ timeout--;
+ }
+ if ((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_SLPAK)
+ {
+ status = CAN_ModeSTS_Failed;
+ }
+ else
+ {
+ status = CAN_ModeSTS_Success;
+ }
+ }
+ else
+ {
+ status = CAN_ModeSTS_Failed;
+ }
+
+ return (uint8_t)status;
+}
+
+/**
+ * @brief Enters the low power mode.
+ * @param CANx where x can be 1 or 2 to to select the CAN peripheral.
+ * @return status: CAN_SLEEP_Ok if sleep entered, CAN_SLEEP_Failed in an
+ * other case.
+ */
+uint8_t CAN_EnterSleep(CAN_Module* CANx)
+{
+ uint8_t sleepstatus = CAN_SLEEP_Failed;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Request Sleep mode */
+ CANx->MCTRL = (((CANx->MCTRL) & (uint32_t)(~(uint32_t)CAN_MCTRL_INIRQ)) | CAN_MCTRL_SLPRQ);
+
+ /* Sleep mode status */
+ if ((CANx->MSTS & (CAN_MSTS_SLPAK | CAN_MSTS_INIAK)) == CAN_MSTS_SLPAK)
+ {
+ /* Sleep mode not entered */
+ sleepstatus = CAN_SLEEP_Ok;
+ }
+ /* return sleep mode status */
+ return (uint8_t)sleepstatus;
+}
+
+/**
+ * @brief Wakes the CAN up.
+ * @param CANx where x can be 1 or 2 to to select the CAN peripheral.
+ * @return status: CAN_WKU_Ok if sleep mode left, CAN_WKU_Failed in an
+ * other case.
+ */
+uint8_t CAN_WakeUp(CAN_Module* CANx)
+{
+ uint32_t wait_slak = SLPAK_TIMEOUT;
+ uint8_t wakeupstatus = CAN_WKU_Failed;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Wake up request */
+ CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_SLPRQ;
+
+ /* Sleep mode status */
+ while (((CANx->MSTS & CAN_MSTS_SLPAK) == CAN_MSTS_SLPAK) && (wait_slak != 0x00))
+ {
+ wait_slak--;
+ }
+ if ((CANx->MSTS & CAN_MSTS_SLPAK) != CAN_MSTS_SLPAK)
+ {
+ /* wake up done : Sleep mode exited */
+ wakeupstatus = CAN_WKU_Ok;
+ }
+ /* return wakeup status */
+ return (uint8_t)wakeupstatus;
+}
+
+/**
+ * @brief Returns the CANx's last error code (LEC).
+ * @param CANx where x can be 1 or 2 to to select the CAN peripheral.
+ * @return CAN_ErrorCode: specifies the Error code :
+ * - CAN_ERRORCODE_NoErr No Error
+ * - CAN_ERRORCODE_StuffErr Stuff Error
+ * - CAN_ERRORCODE_FormErr Form Error
+ * - CAN_ERRORCODE_ACKErr Acknowledgment Error
+ * - CAN_ERRORCODE_BitRecessiveErr Bit Recessive Error
+ * - CAN_ERRORCODE_BitDominantErr Bit Dominant Error
+ * - CAN_ERRORCODE_CRCErr CRC Error
+ * - CAN_ERRORCODE_SoftwareSetErr Software Set Error
+ */
+
+uint8_t CAN_GetLastErrCode(CAN_Module* CANx)
+{
+ uint8_t errorcode = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Get the error code*/
+ errorcode = (((uint8_t)CANx->ESTS) & (uint8_t)CAN_ESTS_LEC);
+
+ /* Return the error code*/
+ return errorcode;
+}
+/**
+ * @brief Returns the CANx Receive Error Counter (REC).
+ * @note In case of an error during reception, this counter is incremented
+ * by 1 or by 8 depending on the error condition as defined by the CAN
+ * standard. After every successful reception, the counter is
+ * decremented by 1 or reset to 120 if its value was higher than 128.
+ * When the counter value exceeds 127, the CAN controller enters the
+ * error passive state.
+ * @param CANx where x can be 1 or 2 to to select the CAN peripheral.
+ * @return CAN Receive Error Counter.
+ */
+uint8_t CAN_GetReceiveErrCounter(CAN_Module* CANx)
+{
+ uint8_t counter = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Get the Receive Error Counter*/
+ counter = (uint8_t)((CANx->ESTS & CAN_ESTS_RXEC) >> 24);
+
+ /* Return the Receive Error Counter*/
+ return counter;
+}
+
+/**
+ * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
+ * @param CANx where x can be 1 or 2 to to select the CAN peripheral.
+ * @return LSB of the 9-bit CAN Transmit Error Counter.
+ */
+uint8_t CAN_GetLSBTransmitErrCounter(CAN_Module* CANx)
+{
+ uint8_t counter = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
+ counter = (uint8_t)((CANx->ESTS & CAN_ESTS_TXEC) >> 16);
+
+ /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
+ return counter;
+}
+
+/**
+ * @brief Enables or disables the specified CANx interrupts.
+ * @param CANx where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_INT specifies the CAN interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * - CAN_INT_TME,
+ * - CAN_INT_FMP0,
+ * - CAN_INT_FF0,
+ * - CAN_INT_FOV0,
+ * - CAN_INT_FMP1,
+ * - CAN_INT_FF1,
+ * - CAN_INT_FOV1,
+ * - CAN_INT_EWG,
+ * - CAN_INT_EPV,
+ * - CAN_INT_LEC,
+ * - CAN_INT_ERR,
+ * - CAN_INT_WKU or
+ * - CAN_INT_SLK.
+ * @param Cmd new state of the CAN interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void CAN_INTConfig(CAN_Module* CANx, uint32_t CAN_INT, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_INT(CAN_INT));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected CANx interrupt */
+ CANx->INTE |= CAN_INT;
+ }
+ else
+ {
+ /* Disable the selected CANx interrupt */
+ CANx->INTE &= ~CAN_INT;
+ }
+}
+/**
+ * @brief Checks whether the specified CAN flag is set or not.
+ * @param CANx where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_FLAG specifies the flag to check.
+ * This parameter can be one of the following flags:
+ * - CAN_FLAG_EWGFL
+ * - CAN_FLAG_EPVFL
+ * - CAN_FLAG_BOFFL
+ * - CAN_FLAG_RQCPM0
+ * - CAN_FLAG_RQCPM1
+ * - CAN_FLAG_RQCPM2
+ * - CAN_FLAG_FFMP1
+ * - CAN_FLAG_FFULL1
+ * - CAN_FLAG_FFOVR1
+ * - CAN_FLAG_FFMP0
+ * - CAN_FLAG_FFULL0
+ * - CAN_FLAG_FFOVR0
+ * - CAN_FLAG_WKU
+ * - CAN_FLAG_SLAK
+ * - CAN_FLAG_LEC
+ * @return The new state of CAN_FLAG (SET or RESET).
+ */
+FlagStatus CAN_GetFlagSTS(CAN_Module* CANx, uint32_t CAN_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_GET_FLAG(CAN_FLAG));
+
+ if ((CAN_FLAG & CAN_FLAGS_ESTS) != (uint32_t)RESET)
+ {
+ /* Check the status of the specified CAN flag */
+ if ((CANx->ESTS & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ else if ((CAN_FLAG & CAN_FLAGS_MSTS) != (uint32_t)RESET)
+ {
+ /* Check the status of the specified CAN flag */
+ if ((CANx->MSTS & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ else if ((CAN_FLAG & CAN_FLAGS_TSTS) != (uint32_t)RESET)
+ {
+ /* Check the status of the specified CAN flag */
+ if ((CANx->TSTS & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ else if ((CAN_FLAG & CAN_FLAGS_RFF0) != (uint32_t)RESET)
+ {
+ /* Check the status of the specified CAN flag */
+ if ((CANx->RFF0 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ else /* if (CAN_FLAG & CAN_FLAGS_RFF1 != (uint32_t)RESET) */
+ {
+ /* Check the status of the specified CAN flag */
+ if ((uint32_t)(CANx->RFF1 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ /* Return the CAN_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the CAN's pending flags.
+ * @param CANx where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_FLAG specifies the flag to clear.
+ * This parameter can be one of the following flags:
+ * - CAN_FLAG_RQCPM0
+ * - CAN_FLAG_RQCPM1
+ * - CAN_FLAG_RQCPM2
+ * - CAN_FLAG_FFULL1
+ * - CAN_FLAG_FFOVR1
+ * - CAN_FLAG_FFULL0
+ * - CAN_FLAG_FFOVR0
+ * - CAN_FLAG_WKU
+ * - CAN_FLAG_SLAK
+ * - CAN_FLAG_LEC
+ */
+void CAN_ClearFlag(CAN_Module* CANx, uint32_t CAN_FLAG)
+{
+ uint32_t flagtmp = 0;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));
+
+ if (CAN_FLAG == CAN_FLAG_LEC) /* ESTS register */
+ {
+ /* Clear the selected CAN flags */
+ CANx->ESTS = (uint32_t)RESET;
+ }
+ else /* MSTS or TSTS or RFF0 or RFF1 */
+ {
+ flagtmp = CAN_FLAG & 0x000FFFFF;
+
+ if ((CAN_FLAG & CAN_FLAGS_RFF0) != (uint32_t)RESET)
+ {
+ /* Receive Flags */
+ CANx->RFF0 = (uint32_t)(flagtmp);
+ }
+ else if ((CAN_FLAG & CAN_FLAGS_RFF1) != (uint32_t)RESET)
+ {
+ /* Receive Flags */
+ CANx->RFF1 = (uint32_t)(flagtmp);
+ }
+ else if ((CAN_FLAG & CAN_FLAGS_TSTS) != (uint32_t)RESET)
+ {
+ /* Transmit Flags */
+ CANx->TSTS = (uint32_t)(flagtmp);
+ }
+ else /* if ((CAN_FLAG & CAN_FLAGS_MSTS)!=(uint32_t)RESET) */
+ {
+ /* Operating mode Flags */
+ CANx->MSTS = (uint32_t)(flagtmp);
+ }
+ }
+}
+
+/**
+ * @brief Checks whether the specified CANx interrupt has occurred or not.
+ * @param CANx where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_INT specifies the CAN interrupt source to check.
+ * This parameter can be one of the following flags:
+ * - CAN_INT_TME
+ * - CAN_INT_FMP0
+ * - CAN_INT_FF0
+ * - CAN_INT_FOV0
+ * - CAN_INT_FMP1
+ * - CAN_INT_FF1
+ * - CAN_INT_FOV1
+ * - CAN_INT_WKU
+ * - CAN_INT_SLK
+ * - CAN_INT_EWG
+ * - CAN_INT_EPV
+ * - CAN_INT_BOF
+ * - CAN_INT_LEC
+ * - CAN_INT_ERR
+ * @return The current state of CAN_INT (SET or RESET).
+ */
+INTStatus CAN_GetIntStatus(CAN_Module* CANx, uint32_t CAN_INT)
+{
+ INTStatus itstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_INT(CAN_INT));
+
+ /* check the enable interrupt bit */
+ if ((CANx->INTE & CAN_INT) != RESET)
+ {
+ /* in case the Interrupt is enabled, .... */
+ switch (CAN_INT)
+ {
+ case CAN_INT_TME:
+ /* Check CAN_TSTS_RQCPx bits */
+ itstatus = CheckINTStatus(CANx->TSTS, CAN_TSTS_RQCPM0 | CAN_TSTS_RQCPM1 | CAN_TSTS_RQCPM2);
+ break;
+ case CAN_INT_FMP0:
+ /* Check CAN_RFF0_FFMP0 bit */
+ itstatus = CheckINTStatus(CANx->RFF0, CAN_RFF0_FFMP0);
+ break;
+ case CAN_INT_FF0:
+ /* Check CAN_RFF0_FFULL0 bit */
+ itstatus = CheckINTStatus(CANx->RFF0, CAN_RFF0_FFULL0);
+ break;
+ case CAN_INT_FOV0:
+ /* Check CAN_RFF0_FFOVR0 bit */
+ itstatus = CheckINTStatus(CANx->RFF0, CAN_RFF0_FFOVR0);
+ break;
+ case CAN_INT_FMP1:
+ /* Check CAN_RFF1_FFMP1 bit */
+ itstatus = CheckINTStatus(CANx->RFF1, CAN_RFF1_FFMP1);
+ break;
+ case CAN_INT_FF1:
+ /* Check CAN_RFF1_FFULL1 bit */
+ itstatus = CheckINTStatus(CANx->RFF1, CAN_RFF1_FFULL1);
+ break;
+ case CAN_INT_FOV1:
+ /* Check CAN_RFF1_FFOVR1 bit */
+ itstatus = CheckINTStatus(CANx->RFF1, CAN_RFF1_FFOVR1);
+ break;
+ case CAN_INT_WKU:
+ /* Check CAN_MSTS_WKUINT bit */
+ itstatus = CheckINTStatus(CANx->MSTS, CAN_MSTS_WKUINT);
+ break;
+ case CAN_INT_SLK:
+ /* Check CAN_MSTS_SLAKINT bit */
+ itstatus = CheckINTStatus(CANx->MSTS, CAN_MSTS_SLAKINT);
+ break;
+ case CAN_INT_EWG:
+ /* Check CAN_ESTS_EWGFL bit */
+ itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_EWGFL);
+ break;
+ case CAN_INT_EPV:
+ /* Check CAN_ESTS_EPVFL bit */
+ itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_EPVFL);
+ break;
+ case CAN_INT_BOF:
+ /* Check CAN_ESTS_BOFFL bit */
+ itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_BOFFL);
+ break;
+ case CAN_INT_LEC:
+ /* Check CAN_ESTS_LEC bit */
+ itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_LEC);
+ break;
+ case CAN_INT_ERR:
+ /* Check CAN_MSTS_ERRINT bit */
+ itstatus = CheckINTStatus(CANx->MSTS, CAN_MSTS_ERRINT);
+ break;
+ default:
+ /* in case of error, return RESET */
+ itstatus = RESET;
+ break;
+ }
+ }
+ else
+ {
+ /* in case the Interrupt is not enabled, return RESET */
+ itstatus = RESET;
+ }
+
+ /* Return the CAN_INT status */
+ return itstatus;
+}
+
+/**
+ * @brief Clears the CANx's interrupt pending bits.
+ * @param CANx where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_INT specifies the interrupt pending bit to clear.
+ * - CAN_INT_TME
+ * - CAN_INT_FF0
+ * - CAN_INT_FOV0
+ * - CAN_INT_FF1
+ * - CAN_INT_FOV1
+ * - CAN_INT_WKU
+ * - CAN_INT_SLK
+ * - CAN_INT_EWG
+ * - CAN_INT_EPV
+ * - CAN_INT_BOF
+ * - CAN_INT_LEC
+ * - CAN_INT_ERR
+ */
+void CAN_ClearINTPendingBit(CAN_Module* CANx, uint32_t CAN_INT)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_CLEAR_INT(CAN_INT));
+
+ switch (CAN_INT)
+ {
+ case CAN_INT_TME:
+ /* Clear CAN_TSTS_RQCPx (rc_w1)*/
+ CANx->TSTS = CAN_TSTS_RQCPM0 | CAN_TSTS_RQCPM1 | CAN_TSTS_RQCPM2;
+ break;
+ case CAN_INT_FF0:
+ /* Clear CAN_RFF0_FFULL0 (rc_w1)*/
+ CANx->RFF0 = CAN_RFF0_FFULL0;
+ break;
+ case CAN_INT_FOV0:
+ /* Clear CAN_RFF0_FFOVR0 (rc_w1)*/
+ CANx->RFF0 = CAN_RFF0_FFOVR0;
+ break;
+ case CAN_INT_FF1:
+ /* Clear CAN_RFF1_FFULL1 (rc_w1)*/
+ CANx->RFF1 = CAN_RFF1_FFULL1;
+ break;
+ case CAN_INT_FOV1:
+ /* Clear CAN_RFF1_FFOVR1 (rc_w1)*/
+ CANx->RFF1 = CAN_RFF1_FFOVR1;
+ break;
+ case CAN_INT_WKU:
+ /* Clear CAN_MSTS_WKUINT (rc_w1)*/
+ CANx->MSTS = CAN_MSTS_WKUINT;
+ break;
+ case CAN_INT_SLK:
+ /* Clear CAN_MSTS_SLAKINT (rc_w1)*/
+ CANx->MSTS = CAN_MSTS_SLAKINT;
+ break;
+ case CAN_INT_EWG:
+ /* Clear CAN_MSTS_ERRINT (rc_w1) */
+ CANx->MSTS = CAN_MSTS_ERRINT;
+ /* Note : the corresponding Flag is cleared by hardware depending
+ of the CAN Bus status*/
+ break;
+ case CAN_INT_EPV:
+ /* Clear CAN_MSTS_ERRINT (rc_w1) */
+ CANx->MSTS = CAN_MSTS_ERRINT;
+ /* Note : the corresponding Flag is cleared by hardware depending
+ of the CAN Bus status*/
+ break;
+ case CAN_INT_BOF:
+ /* Clear CAN_MSTS_ERRINT (rc_w1) */
+ CANx->MSTS = CAN_MSTS_ERRINT;
+ /* Note : the corresponding Flag is cleared by hardware depending
+ of the CAN Bus status*/
+ break;
+ case CAN_INT_LEC:
+ /* Clear LEC bits */
+ CANx->ESTS = RESET;
+ /* Clear CAN_MSTS_ERRINT (rc_w1) */
+ CANx->MSTS = CAN_MSTS_ERRINT;
+ break;
+ case CAN_INT_ERR:
+ /*Clear LEC bits */
+ CANx->ESTS = RESET;
+ /* Clear CAN_MSTS_ERRINT (rc_w1) */
+ CANx->MSTS = CAN_MSTS_ERRINT;
+ /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending
+ of the CAN Bus status*/
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Checks whether the CAN interrupt has occurred or not.
+ * @param CAN_Reg specifies the CAN interrupt register to check.
+ * @param Int_Bit specifies the interrupt source bit to check.
+ * @return The new state of the CAN Interrupt (SET or RESET).
+ */
+static INTStatus CheckINTStatus(uint32_t CAN_Reg, uint32_t Int_Bit)
+{
+ INTStatus pendingbitstatus = RESET;
+
+ if ((CAN_Reg & Int_Bit) != (uint32_t)RESET)
+ {
+ /* CAN_INT is set */
+ pendingbitstatus = SET;
+ }
+ else
+ {
+ /* CAN_INT is reset */
+ pendingbitstatus = RESET;
+ }
+ return pendingbitstatus;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_crc.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_crc.c
new file mode 100644
index 0000000000..786fe6b0c0
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_crc.c
@@ -0,0 +1,228 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_crc.c
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32wb452_crc.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CRC
+ * @brief CRC driver modules
+ * @{
+ */
+
+/** @addtogroup CRC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Private_Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Resets the CRC Data register (DAT).
+ */
+void CRC32_ResetCrc(void)
+{
+ /* Reset CRC generator */
+ CRC->CRC32CTRL = CRC32_CTRL_RESET;
+}
+
+/**
+ * @brief Computes the 32-bit CRC of a given data word(32-bit).
+ * @param Data data word(32-bit) to compute its CRC
+ * @return 32-bit CRC
+ */
+uint32_t CRC32_CalcCrc(uint32_t Data)
+{
+ CRC->CRC32DAT = Data;
+
+ return (CRC->CRC32DAT);
+}
+
+/**
+ * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
+ * @param pBuffer pointer to the buffer containing the data to be computed
+ * @param BufferLength length of the buffer to be computed
+ * @return 32-bit CRC
+ */
+uint32_t CRC32_CalcBufCrc(uint32_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t index = 0;
+
+ for (index = 0; index < BufferLength; index++)
+ {
+ CRC->CRC32DAT = pBuffer[index];
+ }
+ return (CRC->CRC32DAT);
+}
+
+/**
+ * @brief Returns the current CRC value.
+ * @return 32-bit CRC
+ */
+uint32_t CRC32_GetCrc(void)
+{
+ return (CRC->CRC32DAT);
+}
+
+/**
+ * @brief Stores a 8-bit data in the Independent Data(ID) register.
+ * @param IDValue 8-bit value to be stored in the ID register
+ */
+void CRC32_SetIDat(uint8_t IDValue)
+{
+ CRC->CRC32IDAT = IDValue;
+}
+
+/**
+ * @brief Returns the 8-bit data stored in the Independent Data(ID) register
+ * @return 8-bit value of the ID register
+ */
+uint8_t CRC32_GetIDat(void)
+{
+ return (CRC->CRC32IDAT);
+}
+
+// CRC16 add
+void __CRC16_SetLittleEndianFmt(void)
+{
+ CRC->CRC16CTRL = CRC16_CTRL_LITTLE | CRC->CRC16CTRL;
+}
+void __CRC16_SetBigEndianFmt(void)
+{
+ CRC->CRC16CTRL = CRC16_CTRL_BIG & CRC->CRC16CTRL;
+}
+void __CRC16_SetCleanEnable(void)
+{
+ CRC->CRC16CTRL = CRC16_CTRL_RESET | CRC->CRC16CTRL;
+}
+void __CRC16_SetCleanDisable(void)
+{
+ CRC->CRC16CTRL = CRC16_CTRL_NO_RESET & CRC->CRC16CTRL;
+}
+
+uint16_t __CRC16_CalcCrc(uint8_t Data)
+{
+ CRC->CRC16DAT = Data;
+ return (CRC->CRC16D);
+}
+
+void __CRC16_SetCrc(uint8_t Data)
+{
+ CRC->CRC16DAT = Data;
+}
+
+uint16_t __CRC16_GetCrc(void)
+{
+ return (CRC->CRC16D);
+}
+
+void __CRC16_SetLRC(uint8_t Data)
+{
+ CRC->LRC = Data;
+}
+
+uint8_t __CRC16_GetLRC(void)
+{
+ return (CRC->LRC);
+}
+
+uint16_t CRC16_CalcBufCrc(uint8_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t index = 0;
+
+ CRC->CRC16D = 0x00;
+ // CRC16_SetCleanEnable();
+ for (index = 0; index < BufferLength; index++)
+ {
+ CRC->CRC16DAT = pBuffer[index];
+ }
+ return (CRC->CRC16D);
+}
+
+uint16_t CRC16_CalcCRC(uint8_t Data)
+{
+ CRC->CRC16DAT = Data;
+
+ return (CRC->CRC16D);
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_dac.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_dac.c
new file mode 100644
index 0000000000..c8fb140866
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_dac.c
@@ -0,0 +1,425 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_dac.c
+ * @author Nations
+ * @version v1.0.1
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32wb452_dac.h"
+#include "n32wb452_rcc.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DAC
+ * @brief DAC driver modules
+ * @{
+ */
+
+/** @addtogroup DAC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Private_Defines
+ * @{
+ */
+
+/* CTRL register Mask */
+#define CTRL_CLEAR_MASK ((uint32_t)0x00000FFE)
+
+/* DAC Dual Channels SWTRIG masks */
+#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)
+#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)
+
+/* DCH registers offsets */
+#define DR12CH1_OFFSET ((uint32_t)0x00000008)
+#define DR12CH2_OFFSET ((uint32_t)0x00000014)
+#define DR12DCH_OFFSET ((uint32_t)0x00000020)
+
+/* DATO register offset */
+#define DATO1_OFFSET ((uint32_t)0x0000002C)
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the DAC peripheral registers to their default reset values.
+ */
+void DAC_DeInit(void)
+{
+ /* Enable DAC reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_DAC, ENABLE);
+ /* Release DAC from reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_DAC, DISABLE);
+}
+
+/**
+ * @brief Initializes the DAC peripheral according to the specified
+ * parameters in the DAC_InitStruct.
+ * @param DAC_Channel the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1 DAC Channel1 selected
+ * @arg DAC_CHANNEL_2 DAC Channel2 selected
+ * @param DAC_InitStruct pointer to a DAC_InitType structure that
+ * contains the configuration information for the specified DAC channel.
+ */
+void DAC_Init(uint32_t DAC_Channel, DAC_InitType* DAC_InitStruct)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;
+ /* Check the DAC parameters */
+ assert_param(IS_DAC_TRIGGER(DAC_InitStruct->Trigger));
+ assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->WaveGen));
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->LfsrUnMaskTriAmp));
+ assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->BufferOutput));
+ /*---------------------------- DAC CTRL Configuration --------------------------*/
+ /* Get the DAC CTRL value */
+ tmpreg1 = DAC->CTRL;
+ /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
+ tmpreg1 &= ~(CTRL_CLEAR_MASK << DAC_Channel);
+ /* Configure for the selected DAC channel: buffer output, trigger, wave generation,
+ mask/amplitude for wave generation */
+ /* Set TSELx and TENx bits according to Trigger value */
+ /* Set WAVEx bits according to WaveGen value */
+ /* Set MAMPx bits according to LfsrUnMaskTriAmp value */
+ /* Set BOFFx bit according to BufferOutput value */
+ tmpreg2 = (DAC_InitStruct->Trigger | DAC_InitStruct->WaveGen | DAC_InitStruct->LfsrUnMaskTriAmp
+ | DAC_InitStruct->BufferOutput);
+ /* Calculate CTRL register value depending on DAC_Channel */
+ tmpreg1 |= tmpreg2 << DAC_Channel;
+ /* Write to DAC CTRL */
+ DAC->CTRL = tmpreg1;
+}
+
+/**
+ * @brief Fills each DAC_InitStruct member with its default value.
+ * @param DAC_InitStruct pointer to a DAC_InitType structure which will
+ * be initialized.
+ */
+void DAC_ClearStruct(DAC_InitType* DAC_InitStruct)
+{
+ /*--------------- Reset DAC init structure parameters values -----------------*/
+ /* Initialize the Trigger member */
+ DAC_InitStruct->Trigger = DAC_TRG_NONE;
+ /* Initialize the WaveGen member */
+ DAC_InitStruct->WaveGen = DAC_WAVEGEN_NONE;
+ /* Initialize the LfsrUnMaskTriAmp member */
+ DAC_InitStruct->LfsrUnMaskTriAmp = DAC_UNMASK_LFSRBIT0;
+ /* Initialize the BufferOutput member */
+ DAC_InitStruct->BufferOutput = DAC_BUFFOUTPUT_ENABLE;
+}
+
+/**
+ * @brief Enables or disables the specified DAC channel.
+ * @param DAC_Channel the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1 DAC Channel1 selected
+ * @arg DAC_CHANNEL_2 DAC Channel2 selected
+ * @param Cmd new state of the DAC channel.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DAC_Enable(uint32_t DAC_Channel, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected DAC channel */
+ DAC->CTRL |= (DAC_CTRL_CH1EN << DAC_Channel);
+ }
+ else
+ {
+ /* Disable the selected DAC channel */
+ DAC->CTRL &= ~(DAC_CTRL_CH1EN << DAC_Channel);
+ }
+}
+
+/**
+ * @brief Enables or disables the specified DAC channel DMA request.
+ * @param DAC_Channel the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1 DAC Channel1 selected
+ * @arg DAC_CHANNEL_2 DAC Channel2 selected
+ * @param Cmd new state of the selected DAC channel DMA request.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DAC_DmaEnable(uint32_t DAC_Channel, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected DAC channel DMA request */
+ DAC->CTRL |= (DAC_CTRL_DMA1EN << DAC_Channel);
+ }
+ else
+ {
+ /* Disable the selected DAC channel DMA request */
+ DAC->CTRL &= ~(DAC_CTRL_DMA1EN << DAC_Channel);
+ }
+}
+
+/**
+ * @brief Enables or disables the selected DAC channel software trigger.
+ * @param DAC_Channel the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1 DAC Channel1 selected
+ * @arg DAC_CHANNEL_2 DAC Channel2 selected
+ * @param Cmd new state of the selected DAC channel software trigger.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DAC_SoftTrgEnable(uint32_t DAC_Channel, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable software trigger for the selected DAC channel */
+ DAC->SOTTR |= (uint32_t)DAC_SOTTR_TR1EN << (DAC_Channel >> 4);
+ }
+ else
+ {
+ /* Disable software trigger for the selected DAC channel */
+ DAC->SOTTR &= ~((uint32_t)DAC_SOTTR_TR1EN << (DAC_Channel >> 4));
+ }
+}
+
+/**
+ * @brief Enables or disables simultaneously the two DAC channels software
+ * triggers.
+ * @param Cmd new state of the DAC channels software triggers.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DAC_DualSoftwareTrgEnable(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable software trigger for both DAC channels */
+ DAC->SOTTR |= DUAL_SWTRIG_SET;
+ }
+ else
+ {
+ /* Disable software trigger for both DAC channels */
+ DAC->SOTTR &= DUAL_SWTRIG_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the selected DAC channel wave generation.
+ * @param DAC_Channel the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1 DAC Channel1 selected
+ * @arg DAC_CHANNEL_2 DAC Channel2 selected
+ * @param DAC_Wave Specifies the wave type to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg DAC_WAVE_NOISE noise wave generation
+ * @arg DAC_WAVE_TRIANGLE triangle wave generation
+ * @param Cmd new state of the selected DAC channel wave generation.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DAC_WaveGenerationEnable(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ __IO uint32_t tmp = 0;
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_DAC_WAVE(DAC_Wave));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ tmp=DAC->CTRL;
+ tmp&=~(3<<(DAC_Channel+6));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected wave generation for the selected DAC channel */
+ tmp |= DAC_Wave << DAC_Channel;
+ }
+ else
+ {
+ /* Disable the selected wave generation for the selected DAC channel */
+ tmp &=~(3<<(DAC_Channel+6));
+ }
+ DAC->CTRL = tmp;
+}
+
+/**
+ * @brief Set the specified data holding register value for DAC channel1.
+ * @param DAC_Align Specifies the data alignment for DAC channel1.
+ * This parameter can be one of the following values:
+ * @arg DAC_ALIGN_R_8BIT 8bit right data alignment selected
+ * @arg DAC_ALIGN_L_12BIT 12bit left data alignment selected
+ * @arg DAC_ALIGN_R_12BIT 12bit right data alignment selected
+ * @param Data Data to be loaded in the selected data holding register.
+ */
+void DAC_SetCh1Data(uint32_t DAC_Align, uint16_t Data)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALIGN(DAC_Align));
+ assert_param(IS_DAC_DATA(Data));
+
+ tmp = (uint32_t)DAC_BASE;
+ tmp += DR12CH1_OFFSET + DAC_Align;
+
+ /* Set the DAC channel1 selected data holding register */
+ *(__IO uint32_t*)tmp = Data;
+}
+
+/**
+ * @brief Set the specified data holding register value for DAC channel2.
+ * @param DAC_Align Specifies the data alignment for DAC channel2.
+ * This parameter can be one of the following values:
+ * @arg DAC_ALIGN_R_8BIT 8bit right data alignment selected
+ * @arg DAC_ALIGN_L_12BIT 12bit left data alignment selected
+ * @arg DAC_ALIGN_R_12BIT 12bit right data alignment selected
+ * @param Data Data to be loaded in the selected data holding register.
+ */
+void DAC_SetCh2Data(uint32_t DAC_Align, uint16_t Data)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALIGN(DAC_Align));
+ assert_param(IS_DAC_DATA(Data));
+
+ tmp = (uint32_t)DAC_BASE;
+ tmp += DR12CH2_OFFSET + DAC_Align;
+
+ /* Set the DAC channel2 selected data holding register */
+ *(__IO uint32_t*)tmp = Data;
+}
+
+/**
+ * @brief Set the specified data holding register value for dual channel
+ * DAC.
+ * @param DAC_Align Specifies the data alignment for dual channel DAC.
+ * This parameter can be one of the following values:
+ * @arg DAC_ALIGN_R_8BIT 8bit right data alignment selected
+ * @arg DAC_ALIGN_L_12BIT 12bit left data alignment selected
+ * @arg DAC_ALIGN_R_12BIT 12bit right data alignment selected
+ * @param Data2 Data for DAC Channel2 to be loaded in the selected data
+ * holding register.
+ * @param Data1 Data for DAC Channel1 to be loaded in the selected data
+ * holding register.
+ */
+void DAC_SetDualChData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
+{
+ uint32_t data = 0, tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALIGN(DAC_Align));
+ assert_param(IS_DAC_DATA(Data1));
+ assert_param(IS_DAC_DATA(Data2));
+
+ /* Calculate and set dual DAC data holding register value */
+ if (DAC_Align == DAC_ALIGN_R_8BIT)
+ {
+ data = ((uint32_t)Data2 << 8) | Data1;
+ }
+ else
+ {
+ data = ((uint32_t)Data2 << 16) | Data1;
+ }
+
+ tmp = (uint32_t)DAC_BASE;
+ tmp += DR12DCH_OFFSET + DAC_Align;
+
+ /* Set the dual DAC selected data holding register */
+ *(__IO uint32_t*)tmp = data;
+}
+
+/**
+ * @brief Returns the last data output value of the selected DAC channel.
+ * @param DAC_Channel the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1 DAC Channel1 selected
+ * @arg DAC_CHANNEL_2 DAC Channel2 selected
+ * @return The selected DAC channel data output value.
+ */
+uint16_t DAC_GetOutputDataVal(uint32_t DAC_Channel)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+
+ tmp = (uint32_t)DAC_BASE;
+ tmp += DATO1_OFFSET + ((uint32_t)DAC_Channel >> 2);
+
+ /* Returns the DAC channel data output register value */
+ return (uint16_t)(*(__IO uint32_t*)tmp);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_dbg.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_dbg.c
new file mode 100644
index 0000000000..bab526d691
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_dbg.c
@@ -0,0 +1,263 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_dbg.c
+ * @author Nations
+ * @version v1.0.2
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32wb452_dbg.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DBG
+ * @brief DBG driver modules
+ * @{
+ */
+
+/** @addtogroup DBGMCU_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Private_Defines
+ * @{
+ */
+
+#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Returns the UCID.
+ * @return UCID
+ */
+
+void GetUCID(uint8_t *UCIDbuf)
+{
+ uint8_t num = 0;
+ uint32_t* ucid_addr = (uint32_t*)0;
+ uint32_t temp = 0;
+
+ if (0xFFFFFFFF == *(uint32_t*)(0x1FFFF260))
+ {
+ ucid_addr = (uint32_t*)UCID_BASE;
+ }
+ else
+ {
+ ucid_addr = (uint32_t*)(0x1FFFF260);
+ }
+
+ for (num = 0; num < UCID_LENGTH;)
+ {
+ temp = *(__IO uint32_t*)(ucid_addr++);
+ UCIDbuf[num++] = (temp & 0xFF);
+ UCIDbuf[num++] = (temp & 0xFF00) >> 8;
+ UCIDbuf[num++] = (temp & 0xFF0000) >> 16;
+ UCIDbuf[num++] = (temp & 0xFF000000) >> 24;
+ }
+}
+
+/**
+ * @brief Returns the UID.
+ * @return UID
+ */
+
+void GetUID(uint8_t *UIDbuf)
+{
+ uint8_t num = 0;
+ uint32_t* uid_addr = (uint32_t*)0;
+ uint32_t temp = 0;
+
+ if (0xFFFFFFFF == *(uint32_t*)(0x1FFFF270))
+ {
+ uid_addr = (uint32_t*)UID_BASE;
+ }
+ else
+ {
+ uid_addr = (uint32_t*)(0x1FFFF270);
+ }
+
+ for (num = 0; num < UID_LENGTH;)
+ {
+ temp = *(__IO uint32_t*)(uid_addr++);
+ UIDbuf[num++] = (temp & 0xFF);
+ UIDbuf[num++] = (temp & 0xFF00) >> 8;
+ UIDbuf[num++] = (temp & 0xFF0000) >> 16;
+ UIDbuf[num++] = (temp & 0xFF000000) >> 24;
+ }
+}
+
+/**
+ * @brief Returns the DBGMCU_ID.
+ * @return DBGMCU_ID
+ */
+
+void GetDBGMCU_ID(uint8_t *DBGMCU_IDbuf)
+{
+ uint8_t num = 0;
+ uint32_t* dbgid_addr = (uint32_t*)0;
+ uint32_t temp = 0;
+
+ dbgid_addr = (uint32_t*)DBGMCU_ID_BASE;
+ for (num = 0; num < DBGMCU_ID_LENGTH;)
+ {
+ temp = *(__IO uint32_t*)(dbgid_addr++);
+ DBGMCU_IDbuf[num++] = (temp & 0xFF);
+ DBGMCU_IDbuf[num++] = (temp & 0xFF00) >> 8;
+ DBGMCU_IDbuf[num++] = (temp & 0xFF0000) >> 16;
+ DBGMCU_IDbuf[num++] = (temp & 0xFF000000) >> 24;
+ }
+}
+
+/**
+ * @brief Returns the device revision number.
+ * @return Device revision identifier
+ */
+uint32_t DBG_GetRevNum(void)
+{
+ return (DBG->ID & 0x00FF);
+}
+
+/**
+ * @brief Returns the device identifier.
+ * @return Device identifier
+ */
+uint32_t DBG_GetDevNum(void)
+{
+ uint32_t id = DBG->ID;
+ return ((id & 0x00F00000) >> 20) | ((id & 0xFF00) >> 4);
+}
+
+/**
+ * @brief Configures the specified peripheral and low power mode behavior
+ * when the MCU under Debug mode.
+ * @param DBG_Periph specifies the peripheral and low power mode.
+ * This parameter can be any combination of the following values:
+ * @arg DBG_SLEEP Keep debugger connection during SLEEP mode
+ * @arg DBG_STOP Keep debugger connection during STOP mode
+ * @arg DBG_STDBY Keep debugger connection during STANDBY mode
+ * @arg DBG_IWDG_STOP Debug IWDG stopped when Core is halted
+ * @arg DBG_WWDG_STOP Debug WWDG stopped when Core is halted
+ * @arg DBG_TIM1_STOP TIM1 counter stopped when Core is halted
+ * @arg DBG_TIM2_STOP TIM2 counter stopped when Core is halted
+ * @arg DBG_TIM3_STOP TIM3 counter stopped when Core is halted
+ * @arg DBG_TIM4_STOP TIM4 counter stopped when Core is halted
+ * @arg DBG_CAN1_STOP Debug CAN2 stopped when Core is halted
+ * @arg DBG_I2C1SMBUS_TIMEOUT I2C1 SMBUS timeout mode stopped when Core is halted
+ * @arg DBG_I2C2SMBUS_TIMEOUT I2C2 SMBUS timeout mode stopped when Core is halted
+ * @arg DBG_TIM8_STOP TIM8 counter stopped when Core is halted
+ * @arg DBG_TIM5_STOP TIM5 counter stopped when Core is halted
+ * @arg DBG_TIM6_STOP TIM6 counter stopped when Core is halted
+ * @arg DBG_TIM7_STOP TIM7 counter stopped when Core is halted
+ * @arg DBG_CAN2_STOP Debug CAN2 stopped when Core is halted
+ * @param Cmd new state of the specified peripheral in Debug mode.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DBG_ConfigPeriph(uint32_t DBG_Periph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_DBGMCU_PERIPH(DBG_Periph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ DBG->CTRL |= DBG_Periph;
+ }
+ else
+ {
+ DBG->CTRL &= ~DBG_Periph;
+ }
+}
+
+/**
+ * @brief Get FLASH size of this chip.
+ *
+ * @return FLASH size in bytes.
+ */
+uint32_t DBG_GetFlashSize(void)
+{
+ return (DBG->ID & 0x000F0000);
+}
+
+/**
+ * @brief Get SRAM size of this chip.
+ *
+ * @return SRAM size in bytes.
+ */
+uint32_t DBG_GetSramSize(void)
+{
+ return (((DBG->ID & 0xF0000000) >> 28) + 1) << 14;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_dma.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_dma.c
new file mode 100644
index 0000000000..d31dccbac4
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_dma.c
@@ -0,0 +1,884 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_dma.c
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32wb452_dma.h"
+#include "n32wb452_rcc.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @brief DMA driver modules
+ * @{
+ */
+
+/** @addtogroup DMA_Private_TypesDefinitions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Defines
+ * @{
+ */
+
+/* DMA1 Channelx interrupt pending bit masks */
+#define DMA1_CH1_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF1 | DMA_INTSTS_TXCF1 | DMA_INTSTS_HTXF1 | DMA_INTSTS_ERRF1))
+#define DMA1_CH2_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF2 | DMA_INTSTS_TXCF2 | DMA_INTSTS_HTXF2 | DMA_INTSTS_ERRF2))
+#define DMA1_CH3_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF3 | DMA_INTSTS_TXCF3 | DMA_INTSTS_HTXF3 | DMA_INTSTS_ERRF3))
+#define DMA1_CH4_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF4 | DMA_INTSTS_TXCF4 | DMA_INTSTS_HTXF4 | DMA_INTSTS_ERRF4))
+#define DMA1_CH5_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF5 | DMA_INTSTS_TXCF5 | DMA_INTSTS_HTXF5 | DMA_INTSTS_ERRF5))
+#define DMA1_CH6_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF6 | DMA_INTSTS_TXCF6 | DMA_INTSTS_HTXF6 | DMA_INTSTS_ERRF6))
+#define DMA1_CH7_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF7 | DMA_INTSTS_TXCF7 | DMA_INTSTS_HTXF7 | DMA_INTSTS_ERRF7))
+#define DMA1_CH8_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF8 | DMA_INTSTS_TXCF8 | DMA_INTSTS_HTXF8 | DMA_INTSTS_ERRF8))
+
+/* DMA2 Channelx interrupt pending bit masks */
+#define DMA2_CH1_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF1 | DMA_INTSTS_TXCF1 | DMA_INTSTS_HTXF1 | DMA_INTSTS_ERRF1))
+#define DMA2_CH2_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF2 | DMA_INTSTS_TXCF2 | DMA_INTSTS_HTXF2 | DMA_INTSTS_ERRF2))
+#define DMA2_CH3_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF3 | DMA_INTSTS_TXCF3 | DMA_INTSTS_HTXF3 | DMA_INTSTS_ERRF3))
+#define DMA2_CH4_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF4 | DMA_INTSTS_TXCF4 | DMA_INTSTS_HTXF4 | DMA_INTSTS_ERRF4))
+#define DMA2_CH5_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF5 | DMA_INTSTS_TXCF5 | DMA_INTSTS_HTXF5 | DMA_INTSTS_ERRF5))
+#define DMA2_CH6_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF6 | DMA_INTSTS_TXCF6 | DMA_INTSTS_HTXF6 | DMA_INTSTS_ERRF6))
+#define DMA2_CH7_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF7 | DMA_INTSTS_TXCF7 | DMA_INTSTS_HTXF7 | DMA_INTSTS_ERRF7))
+#define DMA2_CH8_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF8 | DMA_INTSTS_TXCF8 | DMA_INTSTS_HTXF8 | DMA_INTSTS_ERRF8))
+
+/* DMA registers Masks */
+#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the DMAy Channelx registers to their default reset
+ * values.
+ * @param DMAyChx where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 8 for DMA1 and 1 to 8 for DMA2 to select the DMA Channel.
+ */
+void DMA_DeInit(DMA_ChannelType* DMAyChx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAyChx));
+
+ /* Disable the selected DMAy Channelx */
+ DMAyChx->CHCFG &= (uint16_t)(~DMA_CHCFG1_CHEN);
+
+ /* Reset DMAy Channelx control register */
+ DMAyChx->CHCFG = 0;
+
+ /* Reset DMAy Channelx remaining bytes register */
+ DMAyChx->TXNUM = 0;
+
+ /* Reset DMAy Channelx peripheral address register */
+ DMAyChx->PADDR = 0;
+
+ /* Reset DMAy Channelx memory address register */
+ DMAyChx->MADDR = 0;
+
+ if (DMAyChx == DMA1_CH1)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel1 */
+ DMA1->INTCLR |= DMA1_CH1_INT_MASK;
+ }
+ else if (DMAyChx == DMA1_CH2)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel2 */
+ DMA1->INTCLR |= DMA1_CH2_INT_MASK;
+ }
+ else if (DMAyChx == DMA1_CH3)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel3 */
+ DMA1->INTCLR |= DMA1_CH3_INT_MASK;
+ }
+ else if (DMAyChx == DMA1_CH4)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel4 */
+ DMA1->INTCLR |= DMA1_CH4_INT_MASK;
+ }
+ else if (DMAyChx == DMA1_CH5)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel5 */
+ DMA1->INTCLR |= DMA1_CH5_INT_MASK;
+ }
+ else if (DMAyChx == DMA1_CH6)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel6 */
+ DMA1->INTCLR |= DMA1_CH6_INT_MASK;
+ }
+ else if (DMAyChx == DMA1_CH7)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel7 */
+ DMA1->INTCLR |= DMA1_CH7_INT_MASK;
+ }
+ else if (DMAyChx == DMA1_CH8)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel8 */
+ DMA1->INTCLR |= DMA1_CH8_INT_MASK;
+ }
+ else if (DMAyChx == DMA2_CH1)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel1 */
+ DMA2->INTCLR |= DMA2_CH1_INT_MASK;
+ }
+ else if (DMAyChx == DMA2_CH2)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel2 */
+ DMA2->INTCLR |= DMA2_CH2_INT_MASK;
+ }
+ else if (DMAyChx == DMA2_CH3)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel3 */
+ DMA2->INTCLR |= DMA2_CH3_INT_MASK;
+ }
+ else if (DMAyChx == DMA2_CH4)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel4 */
+ DMA2->INTCLR |= DMA2_CH4_INT_MASK;
+ }
+ else if (DMAyChx == DMA2_CH5)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel5 */
+ DMA2->INTCLR |= DMA2_CH5_INT_MASK;
+ }
+ else if (DMAyChx == DMA2_CH6)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel6 */
+ DMA2->INTCLR |= DMA2_CH6_INT_MASK;
+ }
+ else if (DMAyChx == DMA2_CH7)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel7 */
+ DMA2->INTCLR |= DMA2_CH7_INT_MASK;
+ }
+ else
+ {
+ if (DMAyChx == DMA2_CH8)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel8 */
+ DMA2->INTCLR |= DMA2_CH8_INT_MASK;
+ }
+ }
+}
+
+/**
+ * @brief Initializes the DMAy Channelx according to the specified
+ * parameters in the DMA_InitParam.
+ * @param DMAyChx where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 8 for DMA1 and 1 to 8 for DMA2 to select the DMA Channel.
+ * @param DMA_InitParam pointer to a DMA_InitType structure that
+ * contains the configuration information for the specified DMA Channel.
+ */
+void DMA_Init(DMA_ChannelType* DMAyChx, DMA_InitType* DMA_InitParam)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAyChx));
+ assert_param(IS_DMA_DIR(DMA_InitParam->Direction));
+ assert_param(IS_DMA_BUF_SIZE(DMA_InitParam->BufSize));
+ assert_param(IS_DMA_PERIPH_INC_STATE(DMA_InitParam->PeriphInc));
+ assert_param(IS_DMA_MEM_INC_STATE(DMA_InitParam->DMA_MemoryInc));
+ assert_param(IS_DMA_PERIPH_DATA_SIZE(DMA_InitParam->PeriphDataSize));
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitParam->MemDataSize));
+ assert_param(IS_DMA_MODE(DMA_InitParam->CircularMode));
+ assert_param(IS_DMA_PRIORITY(DMA_InitParam->Priority));
+ assert_param(IS_DMA_M2M_STATE(DMA_InitParam->Mem2Mem));
+
+ /*--------------------------- DMAy Channelx CHCFG Configuration -----------------*/
+ /* Get the DMAyChx CHCFG value */
+ tmpregister = DMAyChx->CHCFG;
+ /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
+ tmpregister &= CCR_CLEAR_Mask;
+ /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
+ /* Set DIR bit according to Direction value */
+ /* Set CIRC bit according to CircularMode value */
+ /* Set PINC bit according to PeriphInc value */
+ /* Set MINC bit according to DMA_MemoryInc value */
+ /* Set PSIZE bits according to PeriphDataSize value */
+ /* Set MSIZE bits according to MemDataSize value */
+ /* Set PL bits according to Priority value */
+ /* Set the MEM2MEM bit according to Mem2Mem value */
+ tmpregister |= DMA_InitParam->Direction | DMA_InitParam->CircularMode | DMA_InitParam->PeriphInc
+ | DMA_InitParam->DMA_MemoryInc | DMA_InitParam->PeriphDataSize | DMA_InitParam->MemDataSize
+ | DMA_InitParam->Priority | DMA_InitParam->Mem2Mem;
+
+ /* Write to DMAy Channelx CHCFG */
+ DMAyChx->CHCFG = tmpregister;
+
+ /*--------------------------- DMAy Channelx TXNUM Configuration ---------------*/
+ /* Write to DMAy Channelx TXNUM */
+ DMAyChx->TXNUM = DMA_InitParam->BufSize;
+
+ /*--------------------------- DMAy Channelx PADDR Configuration ----------------*/
+ /* Write to DMAy Channelx PADDR */
+ DMAyChx->PADDR = DMA_InitParam->PeriphAddr;
+
+ /*--------------------------- DMAy Channelx MADDR Configuration ----------------*/
+ /* Write to DMAy Channelx MADDR */
+ DMAyChx->MADDR = DMA_InitParam->MemAddr;
+}
+
+/**
+ * @brief Fills each DMA_InitParam member with its default value.
+ * @param DMA_InitParam pointer to a DMA_InitType structure which will
+ * be initialized.
+ */
+void DMA_StructInit(DMA_InitType* DMA_InitParam)
+{
+ /*-------------- Reset DMA init structure parameters values ------------------*/
+ /* Initialize the PeriphAddr member */
+ DMA_InitParam->PeriphAddr = 0;
+ /* Initialize the MemAddr member */
+ DMA_InitParam->MemAddr = 0;
+ /* Initialize the Direction member */
+ DMA_InitParam->Direction = DMA_DIR_PERIPH_SRC;
+ /* Initialize the BufSize member */
+ DMA_InitParam->BufSize = 0;
+ /* Initialize the PeriphInc member */
+ DMA_InitParam->PeriphInc = DMA_PERIPH_INC_DISABLE;
+ /* Initialize the DMA_MemoryInc member */
+ DMA_InitParam->DMA_MemoryInc = DMA_MEM_INC_DISABLE;
+ /* Initialize the PeriphDataSize member */
+ DMA_InitParam->PeriphDataSize = DMA_PERIPH_DATA_SIZE_BYTE;
+ /* Initialize the MemDataSize member */
+ DMA_InitParam->MemDataSize = DMA_MemoryDataSize_Byte;
+ /* Initialize the CircularMode member */
+ DMA_InitParam->CircularMode = DMA_MODE_NORMAL;
+ /* Initialize the Priority member */
+ DMA_InitParam->Priority = DMA_PRIORITY_LOW;
+ /* Initialize the Mem2Mem member */
+ DMA_InitParam->Mem2Mem = DMA_M2M_DISABLE;
+}
+
+/**
+ * @brief Enables or disables the specified DMAy Channelx.
+ * @param DMAyChx where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 8 for DMA1 and 1 to 8 for DMA2 to select the DMA Channel.
+ * @param Cmd new state of the DMAy Channelx.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DMA_EnableChannel(DMA_ChannelType* DMAyChx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAyChx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected DMAy Channelx */
+ DMAyChx->CHCFG |= DMA_CHCFG1_CHEN;
+ }
+ else
+ {
+ /* Disable the selected DMAy Channelx */
+ DMAyChx->CHCFG &= (uint16_t)(~DMA_CHCFG1_CHEN);
+ }
+}
+
+/**
+ * @brief Enables or disables the specified DMAy Channelx interrupts.
+ * @param DMAyChx where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 8 for DMA1 and 1 to 8 for DMA2 to select the DMA Channel.
+ * @param DMAInt specifies the DMA interrupts sources to be enabled
+ * or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_INT_TXC Transfer complete interrupt mask
+ * @arg DMA_INT_HTX Half transfer interrupt mask
+ * @arg DMA_INT_ERR Transfer error interrupt mask
+ * @param Cmd new state of the specified DMA interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DMA_ConfigInt(DMA_ChannelType* DMAyChx, uint32_t DMAInt, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAyChx));
+ assert_param(IS_DMA_CONFIG_INT(DMAInt));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected DMA interrupts */
+ DMAyChx->CHCFG |= DMAInt;
+ }
+ else
+ {
+ /* Disable the selected DMA interrupts */
+ DMAyChx->CHCFG &= ~DMAInt;
+ }
+}
+
+/**
+ * @brief Sets the number of data units in the current DMAy Channelx transfer.
+ * @param DMAyChx where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 8 for DMA1 and 1 to 8 for DMA2 to select the DMA Channel.
+ * @param DataNumber The number of data units in the current DMAy Channelx
+ * transfer.
+ * @note This function can only be used when the DMAyChx is disabled.
+ */
+void DMA_SetCurrDataCounter(DMA_ChannelType* DMAyChx, uint16_t DataNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAyChx));
+
+ /*--------------------------- DMAy Channelx TXNUM Configuration ---------------*/
+ /* Write to DMAy Channelx TXNUM */
+ DMAyChx->TXNUM = DataNumber;
+}
+
+/**
+ * @brief Returns the number of remaining data units in the current
+ * DMAy Channelx transfer.
+ * @param DMAyChx where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 8 for DMA1 and 1 to 8 for DMA2 to select the DMA Channel.
+ * @return The number of remaining data units in the current DMAy Channelx
+ * transfer.
+ */
+uint16_t DMA_GetCurrDataCounter(DMA_ChannelType* DMAyChx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAyChx));
+ /* Return the number of remaining data units for DMAy Channelx */
+ return ((uint16_t)(DMAyChx->TXNUM));
+}
+
+/**
+ * @brief Checks whether the specified DMAy Channelx flag is set or not.
+ * @param DMAyFlag specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg DMA1_FLAG_GL1 DMA1 Channel1 global flag.
+ * @arg DMA1_FLAG_TC1 DMA1 Channel1 transfer complete flag.
+ * @arg DMA1_FLAG_HT1 DMA1 Channel1 half transfer flag.
+ * @arg DMA1_FLAG_TE1 DMA1 Channel1 transfer error flag.
+ * @arg DMA1_FLAG_GL2 DMA1 Channel2 global flag.
+ * @arg DMA1_FLAG_TC2 DMA1 Channel2 transfer complete flag.
+ * @arg DMA1_FLAG_HT2 DMA1 Channel2 half transfer flag.
+ * @arg DMA1_FLAG_TE2 DMA1 Channel2 transfer error flag.
+ * @arg DMA1_FLAG_GL3 DMA1 Channel3 global flag.
+ * @arg DMA1_FLAG_TC3 DMA1 Channel3 transfer complete flag.
+ * @arg DMA1_FLAG_HT3 DMA1 Channel3 half transfer flag.
+ * @arg DMA1_FLAG_TE3 DMA1 Channel3 transfer error flag.
+ * @arg DMA1_FLAG_GL4 DMA1 Channel4 global flag.
+ * @arg DMA1_FLAG_TC4 DMA1 Channel4 transfer complete flag.
+ * @arg DMA1_FLAG_HT4 DMA1 Channel4 half transfer flag.
+ * @arg DMA1_FLAG_TE4 DMA1 Channel4 transfer error flag.
+ * @arg DMA1_FLAG_GL5 DMA1 Channel5 global flag.
+ * @arg DMA1_FLAG_TC5 DMA1 Channel5 transfer complete flag.
+ * @arg DMA1_FLAG_HT5 DMA1 Channel5 half transfer flag.
+ * @arg DMA1_FLAG_TE5 DMA1 Channel5 transfer error flag.
+ * @arg DMA1_FLAG_GL6 DMA1 Channel6 global flag.
+ * @arg DMA1_FLAG_TC6 DMA1 Channel6 transfer complete flag.
+ * @arg DMA1_FLAG_HT6 DMA1 Channel6 half transfer flag.
+ * @arg DMA1_FLAG_TE6 DMA1 Channel6 transfer error flag.
+ * @arg DMA1_FLAG_GL7 DMA1 Channel7 global flag.
+ * @arg DMA1_FLAG_TC7 DMA1 Channel7 transfer complete flag.
+ * @arg DMA1_FLAG_HT7 DMA1 Channel7 half transfer flag.
+ * @arg DMA1_FLAG_TE7 DMA1 Channel7 transfer error flag.
+ * @arg DMA1_FLAG_GL8 DMA1 Channel7 global flag.
+ * @arg DMA1_FLAG_TC8 DMA1 Channel7 transfer complete flag.
+ * @arg DMA1_FLAG_HT8 DMA1 Channel7 half transfer flag.
+ * @arg DMA1_FLAG_TE8 DMA1 Channel7 transfer error flag.
+ * @arg DMA2_FLAG_GL1 DMA2 Channel1 global flag.
+ * @arg DMA2_FLAG_TC1 DMA2 Channel1 transfer complete flag.
+ * @arg DMA2_FLAG_HT1 DMA2 Channel1 half transfer flag.
+ * @arg DMA2_FLAG_TE1 DMA2 Channel1 transfer error flag.
+ * @arg DMA2_FLAG_GL2 DMA2 Channel2 global flag.
+ * @arg DMA2_FLAG_TC2 DMA2 Channel2 transfer complete flag.
+ * @arg DMA2_FLAG_HT2 DMA2 Channel2 half transfer flag.
+ * @arg DMA2_FLAG_TE2 DMA2 Channel2 transfer error flag.
+ * @arg DMA2_FLAG_GL3 DMA2 Channel3 global flag.
+ * @arg DMA2_FLAG_TC3 DMA2 Channel3 transfer complete flag.
+ * @arg DMA2_FLAG_HT3 DMA2 Channel3 half transfer flag.
+ * @arg DMA2_FLAG_TE3 DMA2 Channel3 transfer error flag.
+ * @arg DMA2_FLAG_GL4 DMA2 Channel4 global flag.
+ * @arg DMA2_FLAG_TC4 DMA2 Channel4 transfer complete flag.
+ * @arg DMA2_FLAG_HT4 DMA2 Channel4 half transfer flag.
+ * @arg DMA2_FLAG_TE4 DMA2 Channel4 transfer error flag.
+ * @arg DMA2_FLAG_GL5 DMA2 Channel5 global flag.
+ * @arg DMA2_FLAG_TC5 DMA2 Channel5 transfer complete flag.
+ * @arg DMA2_FLAG_HT5 DMA2 Channel5 half transfer flag.
+ * @arg DMA2_FLAG_TE5 DMA2 Channel5 transfer error flag.
+ * @arg DMA2_FLAG_GL6 DMA1 Channel6 global flag.
+ * @arg DMA2_FLAG_TC6 DMA1 Channel6 transfer complete flag.
+ * @arg DMA2_FLAG_HT6 DMA1 Channel6 half transfer flag.
+ * @arg DMA2_FLAG_TE6 DMA1 Channel6 transfer error flag.
+ * @arg DMA2_FLAG_GL7 DMA1 Channel7 global flag.
+ * @arg DMA2_FLAG_TC7 DMA1 Channel7 transfer complete flag.
+ * @arg DMA2_FLAG_HT7 DMA1 Channel7 half transfer flag.
+ * @arg DMA2_FLAG_TE7 DMA1 Channel7 transfer error flag.
+ * @arg DMA2_FLAG_GL8 DMA1 Channel7 global flag.
+ * @arg DMA2_FLAG_TC8 DMA1 Channel7 transfer complete flag.
+ * @arg DMA2_FLAG_HT8 DMA1 Channel7 half transfer flag.
+ * @arg DMA2_FLAG_TE8 DMA1 Channel7 transfer error flag.
+ * @param DMAy DMA1 or DMA2.
+ * This parameter can be one of the following values:
+ * @arg DMA1 .
+ * @arg DMA2 .
+ * @return The new state of DMAyFlag (SET or RESET).
+ */
+FlagStatus DMA_GetFlagStatus(uint32_t DMAyFlag, DMA_Module* DMAy)
+{
+ FlagStatus bitstatus = RESET;
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_GET_FLAG(DMAyFlag));
+
+ /* Calculate the used DMAy */
+ /* Get DMAy INTSTS register value */
+ tmpregister = DMAy->INTSTS;
+
+ /* Check the status of the specified DMAy flag */
+ if ((tmpregister & DMAyFlag) != (uint32_t)RESET)
+ {
+ /* DMAyFlag is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DMAyFlag is reset */
+ bitstatus = RESET;
+ }
+
+ /* Return the DMAyFlag status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the DMAy Channelx's pending flags.
+ * @param DMAyFlag specifies the flag to clear.
+ * This parameter can be any combination (for the same DMA) of the following values:
+ * @arg DMA1_FLAG_GL1 DMA1 Channel1 global flag.
+ * @arg DMA1_FLAG_TC1 DMA1 Channel1 transfer complete flag.
+ * @arg DMA1_FLAG_HT1 DMA1 Channel1 half transfer flag.
+ * @arg DMA1_FLAG_TE1 DMA1 Channel1 transfer error flag.
+ * @arg DMA1_FLAG_GL2 DMA1 Channel2 global flag.
+ * @arg DMA1_FLAG_TC2 DMA1 Channel2 transfer complete flag.
+ * @arg DMA1_FLAG_HT2 DMA1 Channel2 half transfer flag.
+ * @arg DMA1_FLAG_TE2 DMA1 Channel2 transfer error flag.
+ * @arg DMA1_FLAG_GL3 DMA1 Channel3 global flag.
+ * @arg DMA1_FLAG_TC3 DMA1 Channel3 transfer complete flag.
+ * @arg DMA1_FLAG_HT3 DMA1 Channel3 half transfer flag.
+ * @arg DMA1_FLAG_TE3 DMA1 Channel3 transfer error flag.
+ * @arg DMA1_FLAG_GL4 DMA1 Channel4 global flag.
+ * @arg DMA1_FLAG_TC4 DMA1 Channel4 transfer complete flag.
+ * @arg DMA1_FLAG_HT4 DMA1 Channel4 half transfer flag.
+ * @arg DMA1_FLAG_TE4 DMA1 Channel4 transfer error flag.
+ * @arg DMA1_FLAG_GL5 DMA1 Channel5 global flag.
+ * @arg DMA1_FLAG_TC5 DMA1 Channel5 transfer complete flag.
+ * @arg DMA1_FLAG_HT5 DMA1 Channel5 half transfer flag.
+ * @arg DMA1_FLAG_TE5 DMA1 Channel5 transfer error flag.
+ * @arg DMA1_FLAG_GL6 DMA1 Channel6 global flag.
+ * @arg DMA1_FLAG_TC6 DMA1 Channel6 transfer complete flag.
+ * @arg DMA1_FLAG_HT6 DMA1 Channel6 half transfer flag.
+ * @arg DMA1_FLAG_TE6 DMA1 Channel6 transfer error flag.
+ * @arg DMA1_FLAG_GL7 DMA1 Channel7 global flag.
+ * @arg DMA1_FLAG_TC7 DMA1 Channel7 transfer complete flag.
+ * @arg DMA1_FLAG_HT7 DMA1 Channel7 half transfer flag.
+ * @arg DMA1_FLAG_TE7 DMA1 Channel7 transfer error flag.
+ * @arg DMA1_FLAG_GL8 DMA1 Channel8 global flag.
+ * @arg DMA1_FLAG_TC8 DMA1 Channel8 transfer complete flag.
+ * @arg DMA1_FLAG_HT8 DMA1 Channel8 half transfer flag.
+ * @arg DMA1_FLAG_TE8 DMA1 Channel8 transfer error flag.
+ * @arg DMA2_FLAG_GL1 DMA2 Channel1 global flag.
+ * @arg DMA2_FLAG_TC1 DMA2 Channel1 transfer complete flag.
+ * @arg DMA2_FLAG_HT1 DMA2 Channel1 half transfer flag.
+ * @arg DMA2_FLAG_TE1 DMA2 Channel1 transfer error flag.
+ * @arg DMA2_FLAG_GL2 DMA2 Channel2 global flag.
+ * @arg DMA2_FLAG_TC2 DMA2 Channel2 transfer complete flag.
+ * @arg DMA2_FLAG_HT2 DMA2 Channel2 half transfer flag.
+ * @arg DMA2_FLAG_TE2 DMA2 Channel2 transfer error flag.
+ * @arg DMA2_FLAG_GL3 DMA2 Channel3 global flag.
+ * @arg DMA2_FLAG_TC3 DMA2 Channel3 transfer complete flag.
+ * @arg DMA2_FLAG_HT3 DMA2 Channel3 half transfer flag.
+ * @arg DMA2_FLAG_TE3 DMA2 Channel3 transfer error flag.
+ * @arg DMA2_FLAG_GL4 DMA2 Channel4 global flag.
+ * @arg DMA2_FLAG_TC4 DMA2 Channel4 transfer complete flag.
+ * @arg DMA2_FLAG_HT4 DMA2 Channel4 half transfer flag.
+ * @arg DMA2_FLAG_TE4 DMA2 Channel4 transfer error flag.
+ * @arg DMA2_FLAG_GL5 DMA2 Channel5 global flag.
+ * @arg DMA2_FLAG_TC5 DMA2 Channel5 transfer complete flag.
+ * @arg DMA2_FLAG_HT5 DMA2 Channel5 half transfer flag.
+ * @arg DMA2_FLAG_TE5 DMA2 Channel5 transfer error flag.
+ * @arg DMA2_FLAG_GL6 DMA2 Channel6 global flag.
+ * @arg DMA2_FLAG_TC6 DMA2 Channel6 transfer complete flag.
+ * @arg DMA2_FLAG_HT6 DMA2 Channel6 half transfer flag.
+ * @arg DMA2_FLAG_TE6 DMA2 Channel6 transfer error flag.
+ * @arg DMA2_FLAG_GL7 DMA2 Channel7 global flag.
+ * @arg DMA2_FLAG_TC7 DMA2 Channel7 transfer complete flag.
+ * @arg DMA2_FLAG_HT7 DMA2 Channel7 half transfer flag.
+ * @arg DMA2_FLAG_TE7 DMA2 Channel7 transfer error flag.
+ * @arg DMA2_FLAG_GL8 DMA2 Channel8 global flag.
+ * @arg DMA2_FLAG_TC8 DMA2 Channel8 transfer complete flag.
+ * @arg DMA2_FLAG_HT8 DMA2 Channel8 half transfer flag.
+ * @arg DMA2_FLAG_TE8 DMA2 Channel8 transfer error flag.
+ * @param DMAy DMA1 or DMA2.
+ * This parameter can be one of the following values:
+ * @arg DMA1 .
+ * @arg DMA2 .
+ */
+void DMA_ClearFlag(uint32_t DMAyFlag, DMA_Module* DMAy)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_CLEAR_FLAG(DMAyFlag));
+
+ /* Calculate the used DMAy */
+ /* Clear the selected DMAy flags */
+ DMAy->INTCLR = DMAyFlag;
+}
+
+/**
+ * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
+ * @param DMAy_IT specifies the DMAy interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DMA1_INT_GLB1 DMA1 Channel1 global interrupt.
+ * @arg DMA1_INT_TXC1 DMA1 Channel1 transfer complete interrupt.
+ * @arg DMA1_INT_HTX1 DMA1 Channel1 half transfer interrupt.
+ * @arg DMA1_INT_ERR1 DMA1 Channel1 transfer error interrupt.
+ * @arg DMA1_INT_GLB2 DMA1 Channel2 global interrupt.
+ * @arg DMA1_INT_TXC2 DMA1 Channel2 transfer complete interrupt.
+ * @arg DMA1_INT_HTX2 DMA1 Channel2 half transfer interrupt.
+ * @arg DMA1_INT_ERR2 DMA1 Channel2 transfer error interrupt.
+ * @arg DMA1_INT_GLB3 DMA1 Channel3 global interrupt.
+ * @arg DMA1_INT_TXC3 DMA1 Channel3 transfer complete interrupt.
+ * @arg DMA1_INT_HTX3 DMA1 Channel3 half transfer interrupt.
+ * @arg DMA1_INT_ERR3 DMA1 Channel3 transfer error interrupt.
+ * @arg DMA1_INT_GLB4 DMA1 Channel4 global interrupt.
+ * @arg DMA1_INT_TXC4 DMA1 Channel4 transfer complete interrupt.
+ * @arg DMA1_INT_HTX4 DMA1 Channel4 half transfer interrupt.
+ * @arg DMA1_INT_ERR4 DMA1 Channel4 transfer error interrupt.
+ * @arg DMA1_INT_GLB5 DMA1 Channel5 global interrupt.
+ * @arg DMA1_INT_TXC5 DMA1 Channel5 transfer complete interrupt.
+ * @arg DMA1_INT_HTX5 DMA1 Channel5 half transfer interrupt.
+ * @arg DMA1_INT_ERR5 DMA1 Channel5 transfer error interrupt.
+ * @arg DMA1_INT_GLB6 DMA1 Channel6 global interrupt.
+ * @arg DMA1_INT_TXC6 DMA1 Channel6 transfer complete interrupt.
+ * @arg DMA1_INT_HTX6 DMA1 Channel6 half transfer interrupt.
+ * @arg DMA1_INT_ERR6 DMA1 Channel6 transfer error interrupt.
+ * @arg DMA1_INT_GLB7 DMA1 Channel7 global interrupt.
+ * @arg DMA1_INT_TXC7 DMA1 Channel7 transfer complete interrupt.
+ * @arg DMA1_INT_HTX7 DMA1 Channel7 half transfer interrupt.
+ * @arg DMA1_INT_ERR7 DMA1 Channel7 transfer error interrupt.
+ * @arg DMA1_INT_GLB8 DMA1 Channel8 global interrupt.
+ * @arg DMA1_INT_TXC8 DMA1 Channel8 transfer complete interrupt.
+ * @arg DMA1_INT_HTX8 DMA1 Channel8 half transfer interrupt.
+ * @arg DMA1_INT_ERR8 DMA1 Channel8 transfer error interrupt.
+ * @arg DMA2_INT_GLB1 DMA2 Channel1 global interrupt.
+ * @arg DMA2_INT_TXC1 DMA2 Channel1 transfer complete interrupt.
+ * @arg DMA2_INT_HTX1 DMA2 Channel1 half transfer interrupt.
+ * @arg DMA2_INT_ERR1 DMA2 Channel1 transfer error interrupt.
+ * @arg DMA2_INT_GLB2 DMA2 Channel2 global interrupt.
+ * @arg DMA2_INT_TXC2 DMA2 Channel2 transfer complete interrupt.
+ * @arg DMA2_INT_HTX2 DMA2 Channel2 half transfer interrupt.
+ * @arg DMA2_INT_ERR2 DMA2 Channel2 transfer error interrupt.
+ * @arg DMA2_INT_GLB3 DMA2 Channel3 global interrupt.
+ * @arg DMA2_INT_TXC3 DMA2 Channel3 transfer complete interrupt.
+ * @arg DMA2_INT_HTX3 DMA2 Channel3 half transfer interrupt.
+ * @arg DMA2_INT_ERR3 DMA2 Channel3 transfer error interrupt.
+ * @arg DMA2_INT_GLB4 DMA2 Channel4 global interrupt.
+ * @arg DMA2_INT_TXC4 DMA2 Channel4 transfer complete interrupt.
+ * @arg DMA2_INT_HTX4 DMA2 Channel4 half transfer interrupt.
+ * @arg DMA2_INT_ERR4 DMA2 Channel4 transfer error interrupt.
+ * @arg DMA2_INT_GLB5 DMA2 Channel5 global interrupt.
+ * @arg DMA2_INT_TXC5 DMA2 Channel5 transfer complete interrupt.
+ * @arg DMA2_INT_HTX5 DMA2 Channel5 half transfer interrupt.
+ * @arg DMA2_INT_ERR5 DMA2 Channel5 transfer error interrupt.
+ * @arg DMA2_INT_GLB6 DMA2 Channel6 global interrupt.
+ * @arg DMA2_INT_TXC6 DMA2 Channel6 transfer complete interrupt.
+ * @arg DMA2_INT_HTX6 DMA2 Channel6 half transfer interrupt.
+ * @arg DMA2_INT_ERR6 DMA2 Channel6 transfer error interrupt.
+ * @arg DMA2_INT_GLB7 DMA2 Channel7 global interrupt.
+ * @arg DMA2_INT_TXC7 DMA2 Channel7 transfer complete interrupt.
+ * @arg DMA2_INT_HTX7 DMA2 Channel7 half transfer interrupt.
+ * @arg DMA2_INT_ERR7 DMA2 Channel7 transfer error interrupt.
+ * @arg DMA2_INT_GLB8 DMA2 Channel8 global interrupt.
+ * @arg DMA2_INT_TXC8 DMA2 Channel8 transfer complete interrupt.
+ * @arg DMA2_INT_HTX8 DMA2 Channel8 half transfer interrupt.
+ * @arg DMA2_INT_ERR8 DMA2 Channel8 transfer error interrupt.
+ * @param DMAy DMA1 or DMA2.
+ * This parameter can be one of the following values:
+ * @arg DMA1 .
+ * @arg DMA2 .
+ * @return The new state of DMAy_IT (SET or RESET).
+ */
+INTStatus DMA_GetIntStatus(uint32_t DMAy_IT, DMA_Module* DMAy)
+{
+ INTStatus bitstatus = RESET;
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_GET_IT(DMAy_IT));
+
+ /* Calculate the used DMA */
+ /* Get DMAy INTSTS register value */
+ tmpregister = DMAy->INTSTS;
+
+ /* Check the status of the specified DMAy interrupt */
+ if ((tmpregister & DMAy_IT) != (uint32_t)RESET)
+ {
+ /* DMAy_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DMAy_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the DMAInt status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the DMAy Channelx's interrupt pending bits.
+ * @param DMAy_IT specifies the DMAy interrupt pending bit to clear.
+ * This parameter can be any combination (for the same DMA) of the following values:
+ * @arg DMA1_INT_GLB1 DMA1 Channel1 global interrupt.
+ * @arg DMA1_INT_TXC1 DMA1 Channel1 transfer complete interrupt.
+ * @arg DMA1_INT_HTX1 DMA1 Channel1 half transfer interrupt.
+ * @arg DMA1_INT_ERR1 DMA1 Channel1 transfer error interrupt.
+ * @arg DMA1_INT_GLB2 DMA1 Channel2 global interrupt.
+ * @arg DMA1_INT_TXC2 DMA1 Channel2 transfer complete interrupt.
+ * @arg DMA1_INT_HTX2 DMA1 Channel2 half transfer interrupt.
+ * @arg DMA1_INT_ERR2 DMA1 Channel2 transfer error interrupt.
+ * @arg DMA1_INT_GLB3 DMA1 Channel3 global interrupt.
+ * @arg DMA1_INT_TXC3 DMA1 Channel3 transfer complete interrupt.
+ * @arg DMA1_INT_HTX3 DMA1 Channel3 half transfer interrupt.
+ * @arg DMA1_INT_ERR3 DMA1 Channel3 transfer error interrupt.
+ * @arg DMA1_INT_GLB4 DMA1 Channel4 global interrupt.
+ * @arg DMA1_INT_TXC4 DMA1 Channel4 transfer complete interrupt.
+ * @arg DMA1_INT_HTX4 DMA1 Channel4 half transfer interrupt.
+ * @arg DMA1_INT_ERR4 DMA1 Channel4 transfer error interrupt.
+ * @arg DMA1_INT_GLB5 DMA1 Channel5 global interrupt.
+ * @arg DMA1_INT_TXC5 DMA1 Channel5 transfer complete interrupt.
+ * @arg DMA1_INT_HTX5 DMA1 Channel5 half transfer interrupt.
+ * @arg DMA1_INT_ERR5 DMA1 Channel5 transfer error interrupt.
+ * @arg DMA1_INT_GLB6 DMA1 Channel6 global interrupt.
+ * @arg DMA1_INT_TXC6 DMA1 Channel6 transfer complete interrupt.
+ * @arg DMA1_INT_HTX6 DMA1 Channel6 half transfer interrupt.
+ * @arg DMA1_INT_ERR6 DMA1 Channel6 transfer error interrupt.
+ * @arg DMA1_INT_GLB7 DMA1 Channel7 global interrupt.
+ * @arg DMA1_INT_TXC7 DMA1 Channel7 transfer complete interrupt.
+ * @arg DMA1_INT_HTX7 DMA1 Channel7 half transfer interrupt.
+ * @arg DMA1_INT_ERR7 DMA1 Channel7 transfer error interrupt.
+ * @arg DMA1_INT_GLB8 DMA1 Channel8 global interrupt.
+ * @arg DMA1_INT_TXC8 DMA1 Channel8 transfer complete interrupt.
+ * @arg DMA1_INT_HTX8 DMA1 Channel8 half transfer interrupt.
+ * @arg DMA1_INT_ERR8 DMA1 Channel8 transfer error interrupt.
+ * @arg DMA2_INT_GLB1 DMA2 Channel1 global interrupt.
+ * @arg DMA2_INT_TXC1 DMA2 Channel1 transfer complete interrupt.
+ * @arg DMA2_INT_HTX1 DMA2 Channel1 half transfer interrupt.
+ * @arg DMA2_INT_ERR1 DMA2 Channel1 transfer error interrupt.
+ * @arg DMA2_INT_GLB2 DMA2 Channel2 global interrupt.
+ * @arg DMA2_INT_TXC2 DMA2 Channel2 transfer complete interrupt.
+ * @arg DMA2_INT_HTX2 DMA2 Channel2 half transfer interrupt.
+ * @arg DMA2_INT_ERR2 DMA2 Channel2 transfer error interrupt.
+ * @arg DMA2_INT_GLB3 DMA2 Channel3 global interrupt.
+ * @arg DMA2_INT_TXC3 DMA2 Channel3 transfer complete interrupt.
+ * @arg DMA2_INT_HTX3 DMA2 Channel3 half transfer interrupt.
+ * @arg DMA2_INT_ERR3 DMA2 Channel3 transfer error interrupt.
+ * @arg DMA2_INT_GLB4 DMA2 Channel4 global interrupt.
+ * @arg DMA2_INT_TXC4 DMA2 Channel4 transfer complete interrupt.
+ * @arg DMA2_INT_HTX4 DMA2 Channel4 half transfer interrupt.
+ * @arg DMA2_INT_ERR4 DMA2 Channel4 transfer error interrupt.
+ * @arg DMA2_INT_GLB5 DMA2 Channel5 global interrupt.
+ * @arg DMA2_INT_TXC5 DMA2 Channel5 transfer complete interrupt.
+ * @arg DMA2_INT_HTX5 DMA2 Channel5 half transfer interrupt.
+ * @arg DMA2_INT_ERR5 DMA2 Channel5 transfer error interrupt.
+ * @arg DMA2_INT_GLB6 DMA2 Channel6 global interrupt.
+ * @arg DMA2_INT_TXC6 DMA2 Channel6 transfer complete interrupt.
+ * @arg DMA2_INT_HTX6 DMA2 Channel6 half transfer interrupt.
+ * @arg DMA2_INT_ERR6 DMA2 Channel6 transfer error interrupt.
+ * @arg DMA2_INT_GLB7 DMA2 Channel7 global interrupt.
+ * @arg DMA2_INT_TXC7 DMA2 Channel7 transfer complete interrupt.
+ * @arg DMA2_INT_HTX7 DMA2 Channel7 half transfer interrupt.
+ * @arg DMA2_INT_ERR7 DMA2 Channel7 transfer error interrupt.
+ * @arg DMA2_INT_GLB8 DMA2 Channel8 global interrupt.
+ * @arg DMA2_INT_TXC8 DMA2 Channel8 transfer complete interrupt.
+ * @arg DMA2_INT_HTX8 DMA2 Channel8 half transfer interrupt.
+ * @arg DMA2_INT_ERR8 DMA2 Channel8 transfer error interrupt.
+ * @param DMAy DMA1 or DMA2.
+ * This parameter can be one of the following values:
+ * @arg DMA1 .
+ * @arg DMA2 .
+ */
+void DMA_ClrIntPendingBit(uint32_t DMAy_IT, DMA_Module* DMAy)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_CLR_INT(DMAy_IT));
+
+ /* Calculate the used DMAy */
+ /* Clear the selected DMAy interrupt pending bits */
+ DMAy->INTCLR = DMAy_IT;
+}
+
+/**
+ * @brief Set the DMAy Channelx's remap request.
+ * @param DMAy_REMAP specifies the DMAy request.
+ * This parameter can be set by the following values:
+ * @arg DMA1_REMAP_ADC1 DMA1 Request For ADC1.
+ * @arg DMA1_REMAP_UART5_TX DMA1 Request For UART5_TX.
+ * @arg DMA1_REMAP_I2C3_TX DMA1 Request For I2C3_TX.
+ * @arg DMA1_REMAP_TIM2_CH3 DMA1 Request For TIM2_CH3.
+ * @arg DMA1_REMAP_TIM4_CH1 DMA1 Request For TIM4_CH1.
+ * @arg DMA1_REMAP_USART3_TX DMA1 Request For USART3_TX.
+ * @arg DMA1_REMAP_I2C3_RX DMA1 Request For I2C3_RX.
+ * @arg DMA1_REMAP_TIM1_CH1 DMA1 Request For TIM1_CH1.
+ * @arg DMA1_REMAP_TIM2_UP DMA1 Request For TIM2_UP.
+ * @arg DMA1_REMAP_TIM3_CH3 DMA1 Request For TIM3_CH3.
+ * @arg DMA1_REMAP_SPI1_RX DMA1 Request For SPI1_RX.
+ * @arg DMA1_REMAP_USART3_RX DMA1 Request For USART3_RX.
+ * @arg DMA1_REMAP_TIM1_CH2 DMA1 Request For TIM1_CH2.
+ * @arg DMA1_REMAP_TIM3_CH4 DMA1 Request For TIM3_CH4.
+ * @arg DMA1_REMAP_TIM3_UP DMA1 Request For TIM3_UP.
+ * @arg DMA1_REMAP_SPI1_TX DMA1 Request For SPI1_TX.
+ * @arg DMA1_REMAP_USART1_TX DMA1 Request For USART1_TX.
+ * @arg DMA1_REMAP_TIM1_CH4 DMA1 Request For TIM1_CH4.
+ * @arg DMA1_REMAP_TIM1_TRIG DMA1 Request For TIM1_TRIG.
+ * @arg DMA1_REMAP_TIM1_COM DMA1 Request For TIM1_COM.
+ * @arg DMA1_REMAP_TIM4_CH2 DMA1 Request For TIM4_CH2.
+ * @arg DMA1_REMAP_SPI_I2S2_RX DMA1 Request For SPI_I2S2_RX.
+ * @arg DMA1_REMAP_I2C2_TX DMA1 Request For I2C2_TX.
+ * @arg DMA1_REMAP_USART1_RX DMA1 Request For USART1_RX.
+ * @arg DMA1_REMAP_TIM1_UP DMA1 Request For TIM1_UP.
+ * @arg DMA1_REMAP_SPI_I2S2_TX DMA1 Request For SPI_I2S2_TX.
+ * @arg DMA1_REMAP_TIM4_CH3 DMA1 Request For TIM4_CH3.
+ * @arg DMA1_REMAP_I2C2_RX DMA1 Request For I2C2_RX.
+ * @arg DMA1_REMAP_TIM2_CH1 DMA1 Request For TIM2_CH1.
+ * @arg DMA1_REMAP_USART2_RX DMA1 Request For USART2_RX.
+ * @arg DMA1_REMAP_TIM1_CH3 DMA1 Request For TIM1_CH3.
+ * @arg DMA1_REMAP_TIM3_CH1 DMA1 Request For TIM3_CH1.
+ * @arg DMA1_REMAP_TIM3_TRIG DMA1 Request For TIM3_TRIG.
+ * @arg DMA1_REMAP_I2C1_TX DMA1 Request For I2C1_TX.
+ * @arg DMA1_REMAP_USART2_TX DMA1 Request For USART2_TX.
+ * @arg DMA1_REMAP_TIM2_CH2 DMA1 Request For TIM2_CH2.
+ * @arg DMA1_REMAP_TIM2_CH4 DMA1 Request For TIM2_CH4.
+ * @arg DMA1_REMAP_TIM4_UP DMA1 Request For TIM4_UP.
+ * @arg DMA1_REMAP_I2C1_RX DMA1 Request For I2C1_RX.
+ * @arg DMA1_REMAP_ADC2 DMA1 Request For ADC2.
+ * @arg DMA1_REMAP_UART5_RX DMA1 Request For UART5_RX.
+ * @arg DMA2_REMAP_TIM5_CH4 DMA2 Request For TIM5_CH4.
+ * @arg DMA2_REMAP_TIM5_TRIG DMA2 Request For TIM5_TRIG.
+ * @arg DMA2_REMAP_TIM8_CH3 DMA2 Request For TIM8_CH3.
+ * @arg DMA2_REMAP_TIM8_UP DMA2 Request For TIM8_UP.
+ * @arg DMA2_REMAP_SPI_I2S3_RX DMA2 Request For SPI_I2S3_RX.
+ * @arg DMA2_REMAP_UART6_RX DMA2 Request For UART6_RX.
+ * @arg DMA2_REMAP_TIM8_CH4 DMA2 Request For TIM8_CH4.
+ * @arg DMA2_REMAP_TIM8_TRIG DMA2 Request For TIM8_TRIG.
+ * @arg DMA2_REMAP_TIM8_COM DMA2 Request For TIM8_COM.
+ * @arg DMA2_REMAP_TIM5_CH3 DMA2 Request For TIM5_CH3.
+ * @arg DMA2_REMAP_TIM5_UP DMA2 Request For TIM5_UP.
+ * @arg DMA2_REMAP_SPI_I2S3_TX DMA2 Request For SPI_I2S3_TX.
+ * @arg DMA2_REMAP_UART6_TX DMA2 Request For UART6_TX.
+ * @arg DMA2_REMAP_TIM8_CH1 DMA2 Request For TIM8_CH1.
+ * @arg DMA2_REMAP_UART4_RX DMA2 Request For UART4_RX.
+ * @arg DMA2_REMAP_TIM6_UP DMA2 Request For TIM6_UP.
+ * @arg DMA2_REMAP_DAC1 DMA2 Request For DAC1.
+ * @arg DMA2_REMAP_TIM5_CH2 DMA2 Request For TIM5_CH2.
+ * @arg DMA2_REMAP_SDIO DMA2 Request For SDIO.
+ * @arg DMA2_REMAP_TIM7_UP DMA2 Request For TIM7_UP.
+ * @arg DMA2_REMAP_DAC2 DMA2 Request For DAC2.
+ * @arg DMA2_REMAP_TIM8_CH2 DMA2 Request For TIM8_CH2.
+ * @arg DMA2_REMAP_TIM5_CH1 DMA2 Request For TIM5_CH1.
+ * @arg DMA2_REMAP_UART4_TX DMA2 Request For UART4_TX.
+ * @arg DMA2_REMAP_I2C4_TX DMA2 Request For I2C4_TX.
+ * @arg DMA2_REMAP_UART7_RX DMA2 Request For UART7_RX.
+ * @arg DMA2_REMAP_I2C4_RX DMA2 Request For I2C4_RX.
+ * @arg DMA2_REMAP_UART7_TX DMA2 Request For UART7_TX.
+ * @arg DMA2_REMAP_DVP DMA2 Request For DVP.
+ * @param DMAy DMA1 or DMA2.
+ * This parameter can be one of the following values:
+ * @arg DMA1 .
+ * @arg DMA2 .
+ * @param DMAyChx where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 8 for DMA1 and 1 to 8 for DMA2 to select the DMA Channel.
+ * @param Cmd new state of the DMAy Channelx.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void DMA_RequestRemap(uint32_t DMAy_REMAP, DMA_Module* DMAy, DMA_ChannelType* DMAyChx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_REMAP(DMAy_REMAP));
+
+ if (Cmd != DISABLE)
+ {
+ /* Calculate the used DMAy */
+ /* Set the selected DMAy remap request */
+ DMAyChx->CHSEL = DMAy_REMAP;
+ DMAy->CHMAPEN = 1;
+ }
+ else
+ {
+ DMAy->CHMAPEN = 0;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_dvp.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_dvp.c
new file mode 100644
index 0000000000..d1f90e1c8c
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_dvp.c
@@ -0,0 +1,166 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_dvp.c
+ * @author Nations
+ * @version v1.0.2
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32wb452_dvp.h"
+#include "n32wb452_rcc.h"
+
+/**
+ * @brief Deinitializes the DVP peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void DVP_ResetReg(void)
+{
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_DVP, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_DVP, DISABLE);
+}
+
+/**
+ * @brief Initializes the DVP peripheral according to the specified
+ * parameters in the DVP_InitStruct .
+ * @param DVP_InitStruct pointer to a DVP_InitType structure
+ * that contains the configuration information for the specified DVP
+ * peripheral.
+ * @retval None
+ */
+void DVP_Init( DVP_InitType* DVP_InitStruct)
+{
+ uint32_t tmpregister = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_DVP_LINE_CAPTURE(DVP_InitStruct->LineCapture));
+ assert_param(IS_DVP_BYTE_CAPTURE(DVP_InitStruct->ByteCapture));
+ assert_param(IS_DVP_DATA_INVERT(DVP_InitStruct->DataInvert));
+ assert_param(IS_DVP_PIXEL_POLARITY(DVP_InitStruct->PixelClkPolarity));
+ assert_param(IS_DVP_VSYNC_POLARITY(DVP_InitStruct->VsyncPolarity));
+ assert_param(IS_DVP_HSYNC_POLARITY(DVP_InitStruct->HsyncPolarity));
+ assert_param(IS_DVP_CAPTURE_MODE(DVP_InitStruct->CaptureMode));
+ assert_param(IS_DVP_FIFOWATERMARK(DVP_InitStruct->FifoWatermark));
+
+ /*---------------------------- DVP CTRL Configuration -----------------------*/
+ tmpregister = 0;
+ tmpregister |= DVP_InitStruct->LineCapture | DVP_InitStruct->ByteCapture
+ | DVP_InitStruct->DataInvert | DVP_InitStruct->PixelClkPolarity
+ | DVP_InitStruct->VsyncPolarity | DVP_InitStruct->HsyncPolarity
+ | DVP_InitStruct->CaptureMode | DVP_InitStruct->FifoWatermark;
+ DVP->CTRL = tmpregister;
+
+ /*---------------------------- DVP WST Configuration -----------------------*/
+ if (DVP_InitStruct->RowStart)
+ DVP_InitStruct->RowStart--;
+
+ if (DVP_InitStruct->ColumnStart)
+ DVP_InitStruct->ColumnStart--;
+
+ DVP->WST = ( (((uint32_t)(DVP_InitStruct->RowStart)) << DVP_WST_VST_SHIFT) \
+ | (((uint32_t)(DVP_InitStruct->ColumnStart))<< DVP_WST_HST_SHIFT) );
+
+ /*---------------------------- DVP WSIZE Configuration -----------------------*/
+ DVP->WSIZE = ( (((uint32_t)(DVP_InitStruct->ImageHeight-1)) << DVP_WSIZE_VLINE_SHIFT) \
+ | (((uint32_t)(DVP_InitStruct->ImageWidth-1)) << DVP_WSIZE_HCNT_SHIFT) );
+}
+
+/**
+ * @brief Fills DVP_InitStruct member with its default value.
+ * @param DVP_InitStruct pointer to a DVP_InitType structure
+ * which will be initialized.
+ * @retval None
+ */
+void DVP_DafaultInitParam(DVP_InitType* DVP_InitStruct)
+{
+ /* DVP_InitStruct members default value */
+ DVP_InitStruct->FifoWatermark = DVP_WATER_MARK_1;
+ DVP_InitStruct->LineCapture = DVP_LINE_CAPTURE_ALL;
+ DVP_InitStruct->ByteCapture = DVP_BYTE_CAPTURE_ALL;
+ DVP_InitStruct->DataInvert = DVP_DATA_NOTINVERT;
+ DVP_InitStruct->PixelClkPolarity = DVP_PIXEL_POLARITY_FALLING;
+ DVP_InitStruct->VsyncPolarity = DVP_VSYNC_POLARITY_LOW;
+ DVP_InitStruct->HsyncPolarity = DVP_HSYNC_POLARITY_HIGH;
+ DVP_InitStruct->CaptureMode = DVP_CAPTURE_MODE_SINGLE;
+ DVP_InitStruct->RowStart = 0;
+ DVP_InitStruct->ColumnStart = 0;
+ DVP_InitStruct->ImageHeight = 240;
+ DVP_InitStruct->ImageWidth = 320;
+}
+
+/**
+ * @brief Enables or disables the DVP DMA interface.
+ * @param Cmd New state of the DMA Request.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DVP_ConfigDma( FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* When DMA is enable, the FWM in CTRL1 should be set 1*/
+ __DVP_SetFifoWatermark(DVP_WATER_MARK_1);
+
+ __DVP_EnableDMA();
+ }
+ else
+ {
+ __DVP_DisableDMA();
+ }
+}
+
+/**
+ * @brief Get the data length in FIFO.
+ * @param None.
+ * @retval Current date length in FIFO
+ */
+uint32_t DVP_GetFifoCount(void)
+{
+ if (__FIFOIsNotEmpty())
+ return ((DVP->STS & DVP_STS_FCNT_MASK)>>DVP_STS_FCNT_SHIFT);
+ else
+ return 0;
+}
+
+/**
+ * @brief Software Reset FIFO
+ * @param None.
+ * @retval None.
+ */
+void DVP_ResetFifo(void)
+{
+ __DVP_StopCapture();
+
+ DVP->CTRL |= DVP_FIFO_SOFT_RESET;
+
+ while (DVP->CTRL & DVP_FIFO_SOFT_RESET);
+}
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_exti.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_exti.c
new file mode 100644
index 0000000000..c337e89cac
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_exti.c
@@ -0,0 +1,286 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_exti.c
+ * @author Nations
+ * @version v1.0.1
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32wb452_exti.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup EXTI
+ * @brief EXTI driver modules
+ * @{
+ */
+
+/** @addtogroup EXTI_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Private_Defines
+ * @{
+ */
+
+#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the EXTI peripheral registers to their default reset values.
+ */
+void EXTI_DeInit(void)
+{
+ EXTI->IMASK = 0x00000000;
+ EXTI->EMASK = 0x00000000;
+ EXTI->RT_CFG = 0x00000000;
+ EXTI->FT_CFG = 0x00000000;
+ EXTI->PEND = 0x003FFFFF;
+}
+
+/**
+ * @brief Initializes the EXTI peripheral according to the specified
+ * parameters in the EXTI_InitStruct.
+ * @param EXTI_InitStruct pointer to a EXTI_InitType structure
+ * that contains the configuration information for the EXTI peripheral.
+ */
+void EXTI_InitPeripheral(EXTI_InitType* EXTI_InitStruct)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
+ assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
+ assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
+ assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
+
+ tmp = (uint32_t)EXTI_BASE;
+
+ if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
+ {
+ /* Clear EXTI line configuration */
+ EXTI->IMASK &= ~EXTI_InitStruct->EXTI_Line;
+ EXTI->EMASK &= ~EXTI_InitStruct->EXTI_Line;
+
+ tmp += EXTI_InitStruct->EXTI_Mode;
+
+ *(__IO uint32_t*)tmp |= EXTI_InitStruct->EXTI_Line;
+
+ /* Clear Rising Falling edge configuration */
+ EXTI->RT_CFG &= ~EXTI_InitStruct->EXTI_Line;
+ EXTI->FT_CFG &= ~EXTI_InitStruct->EXTI_Line;
+
+ /* Select the trigger for the selected external interrupts */
+ if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
+ {
+ /* Rising Falling edge */
+ EXTI->RT_CFG |= EXTI_InitStruct->EXTI_Line;
+ EXTI->FT_CFG |= EXTI_InitStruct->EXTI_Line;
+ }
+ else
+ {
+ tmp = (uint32_t)EXTI_BASE;
+ tmp += EXTI_InitStruct->EXTI_Trigger;
+
+ *(__IO uint32_t*)tmp |= EXTI_InitStruct->EXTI_Line;
+ }
+ }
+ else
+ {
+ tmp += EXTI_InitStruct->EXTI_Mode;
+
+ /* Disable the selected external lines */
+ *(__IO uint32_t*)tmp &= ~EXTI_InitStruct->EXTI_Line;
+ }
+}
+
+/**
+ * @brief Fills each EXTI_InitStruct member with its reset value.
+ * @param EXTI_InitStruct pointer to a EXTI_InitType structure which will
+ * be initialized.
+ */
+void EXTI_InitStruct(EXTI_InitType* EXTI_InitStruct)
+{
+ EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
+ EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
+ EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
+ EXTI_InitStruct->EXTI_LineCmd = DISABLE;
+}
+
+/**
+ * @brief Generates a Software interrupt.
+ * @param EXTI_Line specifies the EXTI lines to be enabled or disabled.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..19).
+ */
+void EXTI_TriggerSWInt(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(EXTI_Line));
+
+ EXTI->SWIE |= EXTI_Line;
+}
+
+/**
+ * @brief Checks whether the specified EXTI line flag is set or not.
+ * @param EXTI_Line specifies the EXTI line flag to check.
+ * This parameter can be:
+ * @arg EXTI_Linex External interrupt line x where x(0..19)
+ * @return The new state of EXTI_Line (SET or RESET).
+ */
+FlagStatus EXTI_GetStatusFlag(uint32_t EXTI_Line)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+ if ((EXTI->PEND & EXTI_Line) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the EXTI's line pending flags.
+ * @param EXTI_Line specifies the EXTI lines flags to clear.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..19).
+ */
+void EXTI_ClrStatusFlag(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(EXTI_Line));
+
+ EXTI->PEND = EXTI_Line;
+}
+
+/**
+ * @brief Checks whether the specified EXTI line is asserted or not.
+ * @param EXTI_Line specifies the EXTI line to check.
+ * This parameter can be:
+ * @arg EXTI_Linex External interrupt line x where x(0..19)
+ * @return The new state of EXTI_Line (SET or RESET).
+ */
+INTStatus EXTI_GetITStatus(uint32_t EXTI_Line)
+{
+ INTStatus bitstatus = RESET;
+ uint32_t enablestatus = 0;
+ /* Check the parameters */
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+ enablestatus = EXTI->IMASK & EXTI_Line;
+ if (((EXTI->PEND & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the EXTI's line pending bits.
+ * @param EXTI_Line specifies the EXTI lines to clear.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..19).
+ */
+void EXTI_ClrITPendBit(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(EXTI_Line));
+
+ EXTI->PEND = EXTI_Line;
+}
+
+/**
+ * @brief Select one of EXTI inputs to the RTC TimeStamp event.
+ * @param EXTI_TSSEL_Line specifies the EXTI lines to select.
+ * This parameter can be any combination of EXTI_TSSEL_Line where x can be (0..15).
+ */
+void EXTI_RTCTimeStampSel(uint32_t EXTI_TSSEL_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_TSSEL_LINE(EXTI_TSSEL_Line));
+
+ EXTI->TSSEL &= EXTI_TSSEL_TSSEL_ALL;
+ EXTI->TSSEL |= EXTI_TSSEL_Line;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_flash.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_flash.c
new file mode 100644
index 0000000000..b62d8dcf13
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_flash.c
@@ -0,0 +1,1123 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_flash.c
+ * @author Nations
+ * @version v1.0.3
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32wb452_flash.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @brief FLASH driver modules
+ * @{
+ */
+
+/** @addtogroup FLASH_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Defines
+ * @{
+ */
+
+/* Flash Access Control Register bits */
+#define AC_LATENCY_MSK ((uint32_t)0x000000F8)
+#define AC_PRFTBE_MSK ((uint32_t)0xFFFFFFEF)
+#define AC_ICAHEN_MSK ((uint32_t)0xFFFFFF7F)
+
+/* Flash Access Control Register bits */
+#define AC_PRFTBS_MSK ((uint32_t)0x00000020)
+#define AC_ICAHRST_MSK ((uint32_t)0x00000040)
+
+/* Flash Control Register bits */
+#define CTRL_Set_PG ((uint32_t)0x00000001)
+#define CTRL_Reset_PG ((uint32_t)0x00003FFE)
+#define CTRL_Set_PER ((uint32_t)0x00000002)
+#define CTRL_Reset_PER ((uint32_t)0x00003FFD)
+#define CTRL_Set_MER ((uint32_t)0x00000004)
+#define CTRL_Reset_MER ((uint32_t)0x00003FFB)
+#define CTRL_Set_OPTPG ((uint32_t)0x00000010)
+#define CTRL_Reset_OPTPG ((uint32_t)0x00003FEF)
+#define CTRL_Set_OPTER ((uint32_t)0x00000020)
+#define CTRL_Reset_OPTER ((uint32_t)0x00003FDF)
+#define CTRL_Set_START ((uint32_t)0x00000040)
+#define CTRL_Set_LOCK ((uint32_t)0x00000080)
+#define CTRL_Reset_SMPSEL ((uint32_t)0x00003EFF)
+#define CTRL_SMPSEL_SMP1 ((uint32_t)0x00000000)
+#define CTRL_SMPSEL_SMP2 ((uint32_t)0x00000100)
+
+/* FLASH Mask */
+#define RDPRTL1_MSK ((uint32_t)0x00000002)
+#define RDPRTL2_MSK ((uint32_t)0x80000000)
+#define OBR_USER_MSK ((uint32_t)0x0000001C)
+#define WRP0_MSK ((uint32_t)0x000000FF)
+#define WRP1_MSK ((uint32_t)0x0000FF00)
+#define WRP2_MSK ((uint32_t)0x00FF0000)
+#define WRP3_MSK ((uint32_t)0xFF000000)
+
+/* FLASH Keys */
+#define L1_RDP_Key ((uint32_t)0xFFFF00A5)
+#define RDP_USER_Key ((uint32_t)0xFFF800A5)
+#define L2_RDP_Key ((uint32_t)0xFFFF33CC)
+#define FLASH_KEY1 ((uint32_t)0x45670123)
+#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
+
+/* Delay definition */
+#define EraseTimeout ((uint32_t)0x000B0000)
+#define ProgramTimeout ((uint32_t)0x00002000)
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Sets the code latency value.
+ * @note This function can be used for N32WB452 devices.
+ * @param FLASH_Latency specifies the FLASH Latency value.
+ * This parameter can be one of the following values:
+ * @arg FLASH_LATENCY_0 FLASH Zero Latency cycle
+ * @arg FLASH_LATENCY_1 FLASH One Latency cycle
+ * @arg FLASH_LATENCY_2 FLASH Two Latency cycles
+ * @arg FLASH_LATENCY_3 FLASH Three Latency cycles
+ * @arg FLASH_LATENCY_4 FLASH Four Latency cycles
+ */
+void FLASH_SetLatency(uint32_t FLASH_Latency)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_LATENCY(FLASH_Latency));
+
+ /* Read the AC register */
+ tmpregister = FLASH->AC;
+
+ /* Sets the Latency value */
+ tmpregister &= AC_LATENCY_MSK;
+ tmpregister |= FLASH_Latency;
+
+ /* Write the AC register */
+ FLASH->AC = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the Prefetch Buffer.
+ * @note This function can be used for N32WB452 devices.
+ * @param FLASH_PrefetchBuf specifies the Prefetch buffer status.
+ * This parameter can be one of the following values:
+ * @arg FLASH_PrefetchBuf_EN FLASH Prefetch Buffer Enable
+ * @arg FLASH_PrefetchBuf_DIS FLASH Prefetch Buffer Disable
+ */
+void FLASH_PrefetchBufSet(uint32_t FLASH_PrefetchBuf)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_PREFETCHBUF_STATE(FLASH_PrefetchBuf));
+
+ /* Enable or disable the Prefetch Buffer */
+ FLASH->AC &= AC_PRFTBE_MSK;
+ FLASH->AC |= FLASH_PrefetchBuf;
+}
+
+/**
+ * @brief ICache Reset.
+ * @note This function can be used for N32WB452 devices.
+ */
+void FLASH_iCacheRST(void)
+{
+ /* ICache Reset */
+ FLASH->AC |= FLASH_AC_ICAHRST;
+}
+
+/**
+ * @brief Enables or disables the iCache.
+ * @note This function can be used for N32WB452 devices.
+ * @param FLASH_iCache specifies the iCache status.
+ * This parameter can be one of the following values:
+ * @arg FLASH_iCache_EN FLASH iCache Enable
+ * @arg FLASH_iCache_DIS FLASH iCache Disable
+ */
+void FLASH_iCacheCmd(uint32_t FLASH_iCache)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_ICACHE_STATE(FLASH_iCache));
+
+ /* Enable or disable the iCache */
+ FLASH->AC &= AC_ICAHEN_MSK;
+ FLASH->AC |= FLASH_iCache;
+}
+
+/**
+ * @brief Checks whether the FLASH SMPSEL is SMP1 or SMP2.
+ * @note This function can be used for N32WB452 devices.
+ * @param FLASH_smpsel FLASH_SMP1 or FLASH_SMP2
+ * @return FLASH SMPSEL (FLASH_SMPSEL_SMP1 or FLASH_SMPSEL_SMP2).
+ */
+void FLASH_SetSMPSELStatus(uint32_t FLASH_smpsel)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_SMPSEL_STATE(FLASH_smpsel));
+
+ /* SMP1 or SMP2 */
+ FLASH->CTRL &= CTRL_Reset_SMPSEL;
+ FLASH->CTRL |= FLASH_smpsel;
+}
+
+/**
+ * @brief Unlocks the FLASH Program Erase Controller.
+ * @note This function can be used for N32WB452 devices.
+ * - For N32WB452 devices this function unlocks Bank1.
+ * to FLASH_UnlockBank1 function..
+ */
+void FLASH_Unlock(void)
+{
+ /* Authorize the FPEC of Bank1 Access */
+ FLASH->KEY = FLASH_KEY1;
+ FLASH->KEY = FLASH_KEY2;
+}
+
+/**
+ * @brief Locks the FLASH Program Erase Controller.
+ * @note This function can be used for N32WB452 devices.
+ * - For N32WB452 devices this function Locks Bank1.
+ * to FLASH_LockBank1 function.
+ */
+void FLASH_Lock(void)
+{
+ /* Set the Lock Bit to lock the FPEC and the CTRL of Bank1 */
+ FLASH->CTRL |= CTRL_Set_LOCK;
+}
+
+/**
+ * @brief Erases a specified FLASH page.
+ * @note This function can be used for N32WB452 devices.
+ * @param Page_Address The page address to be erased.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_EraseOnePage(uint32_t Page_Address)
+{
+ FLASH_STS status = FLASH_COMPL;
+ /* Check the parameters */
+ assert_param(IS_FLASH_ADDRESS(Page_Address));
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* if the previous operation is completed, proceed to erase the page */
+ FLASH->CTRL |= CTRL_Set_PER;
+ FLASH->ADD = Page_Address;
+ FLASH->CTRL |= CTRL_Set_START;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ /* Disable the PER Bit */
+ FLASH->CTRL &= CTRL_Reset_PER;
+ }
+
+ /* Return the Erase Status */
+ return status;
+}
+
+/**
+ * @brief Erases all FLASH pages.
+ * @note This function can be used for all N32WB452 devices.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_MassErase(void)
+{
+ FLASH_STS status = FLASH_COMPL;
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* if the previous operation is completed, proceed to erase all pages */
+ FLASH->CTRL |= CTRL_Set_MER;
+ FLASH->CTRL |= CTRL_Set_START;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ /* Disable the MER Bit */
+ FLASH->CTRL &= CTRL_Reset_MER;
+ }
+
+ /* Return the Erase Status */
+ return status;
+}
+
+/**
+ * @brief Erases the FLASH option bytes.
+ * @note This functions erases all option bytes except the Read protection (RDP).
+ * @note This function can be used for N32WB452 devices.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_EraseOB(void)
+{
+ uint32_t rdptmp = L1_RDP_Key;
+
+ FLASH_STS status = FLASH_COMPL;
+
+ /* Get the actual read protection L2 Option Byte value */
+ if (FLASH_GetReadOutProtectionL2STS() != RESET)
+ {
+ status = FLASH_ERR_RDP2;
+ return status;
+ }
+
+ /* Get the actual read protection Option Byte value */
+ if (FLASH_GetReadOutProtectionSTS() != RESET)
+ {
+ rdptmp = (L1_RDP_Key & FLASH_USER_USER);
+ }
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Authorize the small information block programming */
+ FLASH->OPTKEY = FLASH_KEY1;
+ FLASH->OPTKEY = FLASH_KEY2;
+
+ /* if the previous operation is completed, proceed to erase the option bytes */
+ FLASH->CTRL |= CTRL_Set_OPTER;
+ FLASH->CTRL |= CTRL_Set_START;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* if the erase operation is completed, disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CTRL |= CTRL_Set_OPTPG;
+ /* Restore the last read protection Option Byte value */
+ OB->USER_RDP = (uint32_t)rdptmp;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTPG;
+ }
+ }
+ else
+ {
+ if (status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+ }
+ }
+ }
+ /* Return the erase status */
+ return status;
+}
+
+/**
+ * @brief Programs a word at a specified address.
+ * @note This function can be used for N32WB452 devices.
+ * @param Address specifies the address to be programmed.
+ * @param Data specifies the data to be programmed.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_ADD or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ProgramWord(uint32_t Address, uint32_t Data)
+{
+ FLASH_STS status = FLASH_COMPL;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_ADDRESS(Address));
+
+ if ((Address & (uint32_t)0x3) != 0)
+ {
+ /* The programming address is not a multiple of 4 */
+ status = FLASH_ERR_ADD;
+ return status;
+ }
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* if the previous operation is completed, proceed to program the new word */
+ FLASH->CTRL |= CTRL_Set_PG;
+
+ *(__IO uint32_t*)Address = (uint32_t)Data;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ /* Disable the PG Bit */
+ FLASH->CTRL &= CTRL_Reset_PG;
+ }
+
+ /* Return the Program Status */
+ return status;
+}
+
+/**
+ * @brief Programs a half word at a specified Option Byte Data address.
+ * @note This function can be used for N32WB452 devices.
+ * @param Address specifies the address to be programmed.
+ * This parameter can be 0x1FFFF804.
+ * @param Data specifies the data to be programmed(Data0 and Data1).
+ * @return FLASH Status: The returned value can be: FLASH_BUSY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ProgramOBData(uint32_t Address, uint32_t Data)
+{
+ FLASH_STS status = FLASH_COMPL;
+ /* Check the parameters */
+ assert_param(IS_OB_DATA_ADDRESS(Address));
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ /* Get the actual read protection L2 Option Byte value */
+ if (FLASH_GetReadOutProtectionL2STS() != RESET)
+ {
+ status = FLASH_ERR_RDP2;
+ return status;
+ }
+
+ if (status == FLASH_COMPL)
+ {
+ /* Authorize the small information block programming */
+ FLASH->OPTKEY = FLASH_KEY1;
+ FLASH->OPTKEY = FLASH_KEY2;
+ /* Enables the Option Bytes Programming operation */
+ FLASH->CTRL |= CTRL_Set_OPTPG;
+ *(__IO uint32_t*)Address = (uint32_t)Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+ if (status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTPG;
+ }
+ }
+ /* Return the Option Byte Data Program Status */
+ return status;
+}
+
+/**
+ * @brief Write protects the desired pages
+ * @note This function can be used for N32WB452 devices.
+ * @param FLASH_Pages specifies the address of the pages to be write protected.
+ * This parameter can be:
+ * @arg For @b N32WB452_devices: value between FLASH_WRP_Pages0to1 and
+ * FLASH_WRP_Pages60to61 or FLASH_WRP_Pages62to255
+ * @arg FLASH_WRP_AllPages
+ * @return FLASH Status: The returned value can be: FLASH_BUSY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_EnWriteProtection(uint32_t FLASH_Pages)
+{
+ uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
+
+ FLASH_STS status = FLASH_COMPL;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_WRP_PAGE(FLASH_Pages));
+
+ /* Get the actual read protection L2 Option Byte value */
+ if (FLASH_GetReadOutProtectionL2STS() != RESET)
+ {
+ status = FLASH_ERR_RDP2;
+ return status;
+ }
+
+ FLASH_Pages = (uint32_t)(~FLASH_Pages);
+ WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_MSK);
+ WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_MSK) >> 8);
+ WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_MSK) >> 16);
+ WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_MSK) >> 24);
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Authorizes the small information block programming */
+ FLASH->OPTKEY = FLASH_KEY1;
+ FLASH->OPTKEY = FLASH_KEY2;
+ FLASH->CTRL |= CTRL_Set_OPTPG;
+
+ if ((WRP0_Data != 0xFF) || (WRP1_Data != 0xFF))
+ {
+ OB->WRP1_WRP0 = (((uint32_t)WRP0_Data) | (((uint32_t)WRP1_Data) << 16));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+ }
+
+ if (((WRP2_Data != 0xFF) || (WRP3_Data != 0xFF)) && (status == FLASH_COMPL))
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ OB->WRP3_WRP2 = (((uint32_t)WRP2_Data) | (((uint32_t)WRP3_Data) << 16));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+ }
+
+ if (status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTPG;
+ }
+ }
+ /* Return the write protection operation Status */
+ return status;
+}
+
+/**
+ * @brief Enables or disables the read out protection.
+ * @note If the user has already programmed the other option bytes before calling
+ * this function, he must re-program them since this function erases all option bytes.
+ * @note This function can be used for N32WB452 devices.
+ * @param Cmd new state of the ReadOut Protection.
+ * This parameter can be: ENABLE or DISABLE.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ReadOutProtectionL1(FunctionalState Cmd)
+{
+ uint32_t usertmp;
+ FLASH_STS status = FLASH_COMPL;
+
+ usertmp = ((OBR_USER_MSK & FLASH->OBR) << 0x0E);
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ /* Get the actual read protection L2 Option Byte value */
+ if (FLASH_GetReadOutProtectionL2STS() != RESET)
+ {
+ status = FLASH_ERR_RDP2;
+ return status;
+ }
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Authorizes the small information block programming */
+ FLASH->OPTKEY = FLASH_KEY1;
+ FLASH->OPTKEY = FLASH_KEY2;
+ FLASH->CTRL |= CTRL_Set_OPTER;
+ FLASH->CTRL |= CTRL_Set_START;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* if the erase operation is completed, disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CTRL |= CTRL_Set_OPTPG;
+ if (Cmd != DISABLE)
+ {
+ OB->USER_RDP = (FLASH_USER_USER & usertmp);
+ }
+ else
+ {
+ OB->USER_RDP = ((L1_RDP_Key & FLASH_RDP_RDP1) | usertmp);
+ }
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTPG;
+ }
+ }
+ else
+ {
+ if (status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+ }
+ }
+ }
+ /* Return the protection operation Status */
+ return status;
+}
+
+/**
+ * @brief Enables or disables the read out protection L2.
+ * @note If the user has already programmed the other option bytes before calling
+ * this function, he must re-program them since this function erases all option bytes.
+ * @note This function can be used for N32WB452 devices.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ReadOutProtectionL2_ENABLE(void)
+{
+ uint32_t usertmp;
+ FLASH_STS status = FLASH_COMPL;
+
+ usertmp = ((OBR_USER_MSK & FLASH->OBR) << 0x0E);
+
+ /* Get the actual read protection L1 Option Byte value */
+ if (FLASH_GetReadOutProtectionSTS() == RESET)
+ {
+ usertmp |= (L1_RDP_Key & FLASH_RDP_RDP1);
+ }
+ /* Get the actual read protection L2 Option Byte value */
+ if (FLASH_GetReadOutProtectionL2STS() != RESET)
+ {
+ status = FLASH_ERR_RDP2;
+ return status;
+ }
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Authorizes the small information block programming */
+ FLASH->OPTKEY = FLASH_KEY1;
+ FLASH->OPTKEY = FLASH_KEY2;
+ FLASH->CTRL |= CTRL_Set_OPTER;
+ FLASH->CTRL |= CTRL_Set_START;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* if the erase operation is completed, disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CTRL |= CTRL_Set_OPTPG;
+
+ OB->USER_RDP = usertmp;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* Enables the read out protection L2 */
+ OB->RDP2 = L2_RDP_Key;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+ }
+
+ if (status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTPG;
+ }
+ }
+ else
+ {
+ if (status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+ }
+ }
+ }
+ /* Return the protection operation Status */
+ return status;
+}
+
+/**
+ * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
+ * @note This function can be used for N32WB452 devices.
+ * @param OB_IWDG Selects the IWDG mode
+ * This parameter can be one of the following values:
+ * @arg OB_IWDG_SW Software IWDG selected
+ * @arg OB_IWDG_HW Hardware IWDG selected
+ * @param OB_STOP Reset event when entering STOP mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STOP0_NORST No reset generated when entering in STOP
+ * @arg OB_STOP0_RST Reset generated when entering in STOP
+ * @param OB_STDBY Reset event when entering Standby mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STDBY_NORST No reset generated when entering in STANDBY
+ * @arg OB_STDBY_RST Reset generated when entering in STANDBY
+ * @return FLASH Status: The returned value can be: FLASH_BUSY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ConfigUserOB(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)
+{
+ uint32_t rdptmp = RDP_USER_Key;
+
+ FLASH_STS status = FLASH_COMPL;
+
+ /* Check the parameters */
+ assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
+ assert_param(IS_OB_STOP0_SOURCE(OB_STOP));
+ assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
+
+ /* Get the actual read protection L2 Option Byte value */
+ if (FLASH_GetReadOutProtectionL2STS() != RESET)
+ {
+ status = FLASH_ERR_RDP2;
+ return status;
+ }
+
+ /* Get the actual read protection Option Byte value */
+ if (FLASH_GetReadOutProtectionSTS() != RESET)
+ {
+ rdptmp = 0xFFF80000;
+ }
+
+ /* Authorize the small information block programming */
+ FLASH->OPTKEY = FLASH_KEY1;
+ FLASH->OPTKEY = FLASH_KEY2;
+
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* if the previous operation is completed, proceed to erase the option bytes */
+ FLASH->CTRL |= CTRL_Set_OPTER;
+ FLASH->CTRL |= CTRL_Set_START;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(EraseTimeout);
+
+ if (status == FLASH_COMPL)
+ {
+ /* Clears the FLASH's pending flags */
+ FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+ /* if the erase operation is completed, disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CTRL |= CTRL_Set_OPTPG;
+ /* Restore the last read protection Option Byte value */
+ OB->USER_RDP =
+ (uint32_t)rdptmp
+ | ((uint32_t)(OB_IWDG | (uint32_t)(OB_STOP | (uint32_t)(OB_STDBY | ((uint32_t)0xF8)))) << 16);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+ if (status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTPG;
+ }
+ }
+ else
+ {
+ if (status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTER Bit */
+ FLASH->CTRL &= CTRL_Reset_OPTER;
+ }
+ }
+ }
+
+ /* Return the Option Byte program Status */
+ return status;
+}
+
+/**
+ * @brief Returns the FLASH User Option Bytes values.
+ * @note This function can be used for N32WB452 devices.
+ * @return The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
+ * and RST_STDBY(Bit2).
+ */
+uint32_t FLASH_GetUserOB(void)
+{
+ /* Return the User Option Byte */
+ return (uint32_t)((FLASH->OBR << 27) >> 29);
+}
+
+/**
+ * @brief Returns the FLASH Write Protection Option Bytes Register value.
+ * @note This function can be used for N32WB452 devices.
+ * @return The FLASH Write Protection Option Bytes Register value
+ */
+uint32_t FLASH_GetWriteProtectionOB(void)
+{
+ /* Return the Flash write protection Register value */
+ return (uint32_t)(FLASH->WRP);
+}
+
+/**
+ * @brief Checks whether the FLASH Read Out Protection Status is set or not.
+ * @note This function can be used for N32WB452 devices.
+ * @return FLASH ReadOut Protection Status(SET or RESET)
+ */
+FlagStatus FLASH_GetReadOutProtectionSTS(void)
+{
+ FlagStatus readoutstatus = RESET;
+ if ((FLASH->OBR & RDPRTL1_MSK) != (uint32_t)RESET)
+ {
+ readoutstatus = SET;
+ }
+ else
+ {
+ readoutstatus = RESET;
+ }
+ return readoutstatus;
+}
+
+/**
+ * @brief Checks whether the FLASH Read Out Protection L2 Status is set or not.
+ * @note This function can be used for N32WB452 devices.
+ * @return FLASH ReadOut Protection L2 Status(SET or RESET)
+ */
+FlagStatus FLASH_GetReadOutProtectionL2STS(void)
+{
+ FlagStatus readoutstatus = RESET;
+ if ((FLASH->OBR & RDPRTL2_MSK) != (uint32_t)RESET)
+ {
+ readoutstatus = SET;
+ }
+ else
+ {
+ readoutstatus = RESET;
+ }
+ return readoutstatus;
+}
+
+/**
+ * @brief Checks whether the FLASH Prefetch Buffer status is set or not.
+ * @note This function can be used for N32WB452 devices.
+ * @return FLASH Prefetch Buffer Status (SET or RESET).
+ */
+FlagStatus FLASH_GetPrefetchBufSTS(void)
+{
+ FlagStatus bitstatus = RESET;
+
+ if ((FLASH->AC & AC_PRFTBS_MSK) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */
+ return bitstatus;
+}
+
+/**
+ * @brief Checks whether the FLASH SMPSEL is SMP1 or SMP2.
+ * @note This function can be used for N32WB452 devices.
+ * @return FLASH SMPSEL (FLASH_SMP1 or FLASH_SMP2).
+ */
+FLASH_SMPSEL FLASH_GetSMPSELStatus(void)
+{
+ FLASH_SMPSEL bitstatus = FLASH_SMP1;
+
+ if ((FLASH->CTRL & CTRL_Reset_SMPSEL) != (uint32_t)FLASH_SMP1)
+ {
+ bitstatus = FLASH_SMP2;
+ }
+ else
+ {
+ bitstatus = FLASH_SMP1;
+ }
+ /* Return the new state of FLASH SMPSEL (FLASH_SMP1 or FLASH_SMP2) */
+ return bitstatus;
+}
+
+/**
+ * @brief Enables or disables the specified FLASH interrupts.
+ * @note This function can be used for N32WB452 devices.
+ * @param FLASH_INT specifies the FLASH interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_ERROR FLASH Error Interrupt
+ * @arg FLASH_INT_FERR EVERR PVERR Interrupt
+ * @arg FLASH_INT_EOP FLASH end of operation Interrupt
+ * @param Cmd new state of the specified Flash interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void FLASH_INTConfig(uint32_t FLASH_INT, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_INT(FLASH_INT));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the interrupt sources */
+ FLASH->CTRL |= FLASH_INT;
+ }
+ else
+ {
+ /* Disable the interrupt sources */
+ FLASH->CTRL &= ~(uint32_t)FLASH_INT;
+ }
+}
+
+/**
+ * @brief Checks whether the specified FLASH flag is set or not.
+ * @note This function can be used for N32WB452 devices.
+ * @param FLASH_FLAG specifies the FLASH flag to check.
+ * This parameter can be one of the following values:
+ * @arg FLASH_FLAG_BUSY FLASH Busy flag
+ * @arg FLASH_FLAG_PGERR FLASH Program error flag
+ * @arg FLASH_FLAG_PVERR FLASH Program Verify ERROR flag
+ * @arg FLASH_FLAG_WRPERR FLASH Write protected error flag
+ * @arg FLASH_FLAG_EOP FLASH End of Operation flag
+ * @arg FLASH_FLAG_EVERR FLASH Erase Verify ERROR flag
+ * @arg FLASH_FLAG_OBERR FLASH Option Byte error flag
+ * @return The new state of FLASH_FLAG (SET or RESET).
+ */
+FlagStatus FLASH_GetFlagSTS(uint32_t FLASH_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));
+ if (FLASH_FLAG == FLASH_FLAG_OBERR)
+ {
+ if ((FLASH->OBR & FLASH_FLAG_OBERR) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+ else
+ {
+ if ((FLASH->STS & FLASH_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+
+ /* Return the new state of FLASH_FLAG (SET or RESET) */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the FLASH's pending flags.
+ * @note This function can be used for N32WB452 devices.
+ * @param FLASH_FLAG specifies the FLASH flags to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_FLAG_PGERR FLASH Program error flag
+ * @arg FLASH_FLAG_PVERR FLASH Program Verify ERROR flag
+ * @arg FLASH_FLAG_WRPERR FLASH Write protected error flag
+ * @arg FLASH_FLAG_EOP FLASH End of Operation flag
+ * @arg FLASH_FLAG_EVERR FLASH Erase Verify ERROR flag
+ */
+void FLASH_ClearFlag(uint32_t FLASH_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));
+
+ /* Clear the flags */
+ FLASH->STS |= FLASH_FLAG;
+}
+
+/**
+ * @brief Returns the FLASH Status.
+ * @note This function can be used for N32WB452 devices, it is equivalent
+ * to FLASH_GetBank1Status function.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_GetSTS(void)
+{
+ FLASH_STS flashstatus = FLASH_COMPL;
+
+ if ((FLASH->STS & FLASH_FLAG_BUSY) == FLASH_FLAG_BUSY)
+ {
+ flashstatus = FLASH_BUSY;
+ }
+ else
+ {
+ if ((FLASH->STS & FLASH_FLAG_PGERR) != 0)
+ {
+ flashstatus = FLASH_ERR_PG;
+ }
+ else
+ {
+ if ((FLASH->STS & FLASH_FLAG_PVERR) != 0)
+ {
+ flashstatus = FLASH_ERR_PV;
+ }
+ else
+ {
+ if ((FLASH->STS & FLASH_FLAG_WRPERR) != 0)
+ {
+ flashstatus = FLASH_ERR_WRP;
+ }
+ else
+ {
+ if ((FLASH->STS & FLASH_FLAG_EVERR) != 0)
+ {
+ flashstatus = FLASH_ERR_EV;
+ }
+ else
+ {
+ flashstatus = FLASH_COMPL;
+ }
+ }
+ }
+ }
+ }
+
+ /* Return the Flash Status */
+ return flashstatus;
+}
+
+/**
+ * @brief Waits for a Flash operation to complete or a TIMEOUT to occur.
+ * @note This function can be used for N32WB452 devices,
+ * it is equivalent to FLASH_WaitForLastBank1Operation..
+ * @param Timeout FLASH programming Timeout
+ * @return FLASH Status: The returned value can be: FLASH_BUSY,
+ * FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ * FLASH_ERR_EV or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_WaitForLastOpt(uint32_t Timeout)
+{
+ FLASH_STS status = FLASH_COMPL;
+
+ /* Check for the Flash Status */
+ status = FLASH_GetSTS();
+ /* Wait for a Flash operation to complete or a TIMEOUT to occur */
+ while ((status == FLASH_BUSY) && (Timeout != 0x00))
+ {
+ status = FLASH_GetSTS();
+ Timeout--;
+ }
+ if (Timeout == 0x00)
+ {
+ status = FLASH_TIMEOUT;
+ }
+ /* Return the operation status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_gpio.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_gpio.c
new file mode 100644
index 0000000000..97a9c48048
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_gpio.c
@@ -0,0 +1,828 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_gpio.c
+ * @author Nations
+ * @version v1.0.2
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32wb452_gpio.h"
+#include "n32wb452_rcc.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @brief GPIO driver modules
+ * @{
+ */
+
+/** @addtogroup GPIO_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Private_Defines
+ * @{
+ */
+
+/* ------------ RCC registers bit address in the alias region ----------------*/
+#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)
+
+/* --- Event control register -----*/
+
+/* Alias word address of EVOE bit */
+#define EVCR_OFFSET (AFIO_OFFSET + 0x00)
+#define EVOE_BitNumber ((uint8_t)0x07)
+#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
+
+/* --- RMP_CFG Register ---*/
+/* Alias word address of MII_RMII_SEL bit */
+#define MAPR_OFFSET (AFIO_OFFSET + 0x04)
+#define MII_RMII_SEL_BitNumber ((u8)0x17)
+#define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
+
+#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80)
+#define LSB_MASK ((uint16_t)0xFFFF)
+#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)
+#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF)
+#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
+#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
+#define DBGAFR_NUMBITS_MAPR3_MASK ((uint32_t)0x40000000)
+#define DBGAFR_NUMBITS_MAPR4_MASK ((uint32_t)0x20000000)
+#define DBGAFR_NUMBITS_MAPR5_MASK ((uint32_t)0x10000000)
+#define DBGAFR_NUMBITS_SPI1_MASK ((uint32_t)0x01000000)
+#define DBGAFR_NUMBITS_USART2_MASK ((uint32_t)0x04000000)
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the GPIOx peripheral registers to their default reset values.
+ * @param GPIOx where x can be (A..G) to select the GPIO peripheral.
+ */
+void GPIO_DeInit(GPIO_Module* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ if (GPIOx == GPIOA)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOA, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOA, DISABLE);
+ }
+ else if (GPIOx == GPIOB)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOB, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOB, DISABLE);
+ }
+ else if (GPIOx == GPIOC)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOC, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOC, DISABLE);
+ }
+ else if (GPIOx == GPIOD)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOD, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOD, DISABLE);
+ }
+ else if (GPIOx == GPIOE)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOE, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOE, DISABLE);
+ }
+ else
+ {
+ }
+}
+
+/**
+ * @brief Deinitializes the Alternate Functions (remap, event control
+ * and EXTI configuration) registers to their default reset values.
+ */
+void GPIO_AFIOInitDefault(void)
+{
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_AFIO, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_AFIO, DISABLE);
+}
+
+/**
+ * @brief Initializes the GPIOx peripheral according to the specified
+ * parameters in the GPIO_InitStruct.
+ * @param GPIOx where x can be (A..G) to select the GPIO peripheral.
+ * @param GPIO_InitStruct pointer to a GPIO_InitType structure that
+ * contains the configuration information for the specified GPIO peripheral.
+ */
+void GPIO_InitPeripheral(GPIO_Module* GPIOx, GPIO_InitType* GPIO_InitStruct)
+{
+ uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
+ uint32_t tmpregister = 0x00, pinmask = 0x00;
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
+ assert_param(IS_GPIO_PIN(GPIO_InitStruct->Pin));
+
+ /*---------------------------- GPIO Mode Configuration -----------------------*/
+ currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
+ if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
+ {
+ /* Check the parameters */
+ assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
+ /* Output mode */
+ currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
+ }
+ /*---------------------------- GPIO PL_CFG Configuration ------------------------*/
+ /* Configure the eight low port pins */
+ if (((uint32_t)GPIO_InitStruct->Pin & ((uint32_t)0x00FF)) != 0x00)
+ {
+ tmpregister = GPIOx->PL_CFG;
+ for (pinpos = 0x00; pinpos < 0x08; pinpos++)
+ {
+ pos = ((uint32_t)0x01) << pinpos;
+ /* Get the port pins position */
+ currentpin = (GPIO_InitStruct->Pin) & pos;
+ if (currentpin == pos)
+ {
+ pos = pinpos << 2;
+ /* Clear the corresponding low control register bits */
+ pinmask = ((uint32_t)0x0F) << pos;
+ tmpregister &= ~pinmask;
+ /* Write the mode configuration in the corresponding bits */
+ tmpregister |= (currentmode << pos);
+ /* Reset the corresponding POD bit */
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
+ {
+ GPIOx->PBC = (((uint32_t)0x01) << pinpos);
+ }
+ else
+ {
+ /* Set the corresponding POD bit */
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
+ {
+ GPIOx->PBSC = (((uint32_t)0x01) << pinpos);
+ }
+ }
+ }
+ }
+ GPIOx->PL_CFG = tmpregister;
+ }
+ /*---------------------------- GPIO PH_CFG Configuration ------------------------*/
+ /* Configure the eight high port pins */
+ if (GPIO_InitStruct->Pin > 0x00FF)
+ {
+ tmpregister = GPIOx->PH_CFG;
+ for (pinpos = 0x00; pinpos < 0x08; pinpos++)
+ {
+ pos = (((uint32_t)0x01) << (pinpos + 0x08));
+ /* Get the port pins position */
+ currentpin = ((GPIO_InitStruct->Pin) & pos);
+ if (currentpin == pos)
+ {
+ pos = pinpos << 2;
+ /* Clear the corresponding high control register bits */
+ pinmask = ((uint32_t)0x0F) << pos;
+ tmpregister &= ~pinmask;
+ /* Write the mode configuration in the corresponding bits */
+ tmpregister |= (currentmode << pos);
+ /* Reset the corresponding POD bit */
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
+ {
+ GPIOx->PBC = (((uint32_t)0x01) << (pinpos + 0x08));
+ }
+ /* Set the corresponding POD bit */
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
+ {
+ GPIOx->PBSC = (((uint32_t)0x01) << (pinpos + 0x08));
+ }
+ }
+ }
+ GPIOx->PH_CFG = tmpregister;
+ }
+}
+
+/**
+ * @brief Fills each GPIO_InitStruct member with its default value.
+ * @param GPIO_InitStruct pointer to a GPIO_InitType structure which will
+ * be initialized.
+ */
+void GPIO_InitStruct(GPIO_InitType* GPIO_InitStruct)
+{
+ /* Reset GPIO init structure parameters values */
+ GPIO_InitStruct->Pin = GPIO_PIN_ALL;
+ GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
+}
+
+/**
+ * @brief Reads the specified input port pin.
+ * @param GPIOx where x can be (A..G) to select the GPIO peripheral.
+ * @param Pin specifies the port bit to read.
+ * This parameter can be GPIO_Pin_x where x can be (0..15).
+ * @return The input port pin value.
+ */
+uint8_t GPIO_ReadInputDataBit(GPIO_Module* GPIOx, uint16_t Pin)
+{
+ uint8_t bitstatus = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(Pin));
+
+ if ((GPIOx->PID & Pin) != (uint32_t)Bit_RESET)
+ {
+ bitstatus = (uint8_t)Bit_SET;
+ }
+ else
+ {
+ bitstatus = (uint8_t)Bit_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Reads the specified GPIO input data port.
+ * @param GPIOx where x can be (A..G) to select the GPIO peripheral.
+ * @return GPIO input data port value.
+ */
+uint16_t GPIO_ReadInputData(GPIO_Module* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ return ((uint16_t)GPIOx->PID);
+}
+
+/**
+ * @brief Reads the specified output data port bit.
+ * @param GPIOx where x can be (A..G) to select the GPIO peripheral.
+ * @param Pin specifies the port bit to read.
+ * This parameter can be GPIO_Pin_x where x can be (0..15).
+ * @return The output port pin value.
+ */
+uint8_t GPIO_ReadOutputDataBit(GPIO_Module* GPIOx, uint16_t Pin)
+{
+ uint8_t bitstatus = 0x00;
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(Pin));
+
+ if ((GPIOx->POD & Pin) != (uint32_t)Bit_RESET)
+ {
+ bitstatus = (uint8_t)Bit_SET;
+ }
+ else
+ {
+ bitstatus = (uint8_t)Bit_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Reads the specified GPIO output data port.
+ * @param GPIOx where x can be (A..G) to select the GPIO peripheral.
+ * @return GPIO output data port value.
+ */
+uint16_t GPIO_ReadOutputData(GPIO_Module* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ return ((uint16_t)GPIOx->POD);
+}
+
+/**
+ * @brief Sets the selected data port bits.
+ * @param GPIOx where x can be (A..G) to select the GPIO peripheral.
+ * @param Pin specifies the port bits to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ */
+void GPIO_SetBits(GPIO_Module* GPIOx, uint16_t Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(Pin));
+
+ GPIOx->PBSC = Pin;
+}
+void GPIO_SetBitsHigh16(GPIO_Module* GPIOx, uint32_t Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ // assert_param(IS_GPIO_PIN(Pin));
+
+ GPIOx->PBSC = Pin;
+}
+
+/**
+ * @brief Clears the selected data port bits.
+ * @param GPIOx where x can be (A..G) to select the GPIO peripheral.
+ * @param Pin specifies the port bits to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ */
+void GPIO_ResetBits(GPIO_Module* GPIOx, uint16_t Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(Pin));
+
+ GPIOx->PBC = Pin;
+}
+
+/**
+ * @brief Sets or clears the selected data port bit.
+ * @param GPIOx where x can be (A..G) to select the GPIO peripheral.
+ * @param Pin specifies the port bit to be written.
+ * This parameter can be one of GPIO_Pin_x where x can be (0..15).
+ * @param BitCmd specifies the value to be written to the selected bit.
+ * This parameter can be one of the Bit_OperateType enum values:
+ * @arg Bit_RESET to clear the port pin
+ * @arg Bit_SET to set the port pin
+ */
+void GPIO_WriteBit(GPIO_Module* GPIOx, uint16_t Pin, Bit_OperateType BitCmd)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(Pin));
+ assert_param(IS_GPIO_BIT_OPERATE(BitCmd));
+
+ if (BitCmd != Bit_RESET)
+ {
+ GPIOx->PBSC = Pin;
+ }
+ else
+ {
+ GPIOx->PBC = Pin;
+ }
+}
+
+/**
+ * @brief Writes data to the specified GPIO data port.
+ * @param GPIOx where x can be (A..G) to select the GPIO peripheral.
+ * @param PortVal specifies the value to be written to the port output data register.
+ */
+void GPIO_Write(GPIO_Module* GPIOx, uint16_t PortVal)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ GPIOx->POD = PortVal;
+}
+
+/**
+ * @brief Locks GPIO Pins configuration registers.
+ * @param GPIOx where x can be (A..G) to select the GPIO peripheral.
+ * @param Pin specifies the port bit to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ */
+void GPIO_ConfigPinLock(GPIO_Module* GPIOx, uint16_t Pin)
+{
+ uint32_t tmp = 0x00010000;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(Pin));
+
+ tmp |= Pin;
+ /* Set LCKK bit */
+ GPIOx->PLOCK_CFG = tmp;
+ /* Reset LCKK bit */
+ GPIOx->PLOCK_CFG = Pin;
+ /* Set LCKK bit */
+ GPIOx->PLOCK_CFG = tmp;
+ /* Read LCKK bit*/
+ tmp = GPIOx->PLOCK_CFG;
+ /* Read LCKK bit*/
+ tmp = GPIOx->PLOCK_CFG;
+}
+
+/**
+ * @brief Selects the GPIO pin used as Event output.
+ * @param PortSource selects the GPIO port to be used as source
+ * for Event output.
+ * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
+ * @param PinSource specifies the pin for the Event output.
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).
+ */
+void GPIO_ConfigEventOutput(uint8_t PortSource, uint8_t PinSource)
+{
+ uint32_t tmpregister = 0x00;
+ /* Check the parameters */
+ assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(PortSource));
+ assert_param(IS_GPIO_PIN_SOURCE(PinSource));
+
+ tmpregister = AFIO->ECTRL;
+ /* Clear the PORT[6:4] and PIN[3:0] bits */
+ tmpregister &= EVCR_PORTPINCONFIG_MASK;
+ tmpregister |= (uint32_t)PortSource << 0x04;
+ tmpregister |= PinSource;
+ AFIO->ECTRL = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the Event Output.
+ * @param Cmd new state of the Event output.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void GPIO_CtrlEventOutput(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ *(__IO uint32_t*)EVCR_EVOE_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Changes the mapping of the specified pin.
+ * @param RmpPin selects the pin to remap.
+ * This parameter can be one of the following values:
+ * @arg GPIO_RMP_SPI1 SPI1 Alternate Function mapping
+ * @arg GPIO_RMP_I2C1 I2C1 Alternate Function mapping
+ * @arg GPIO_RMP_USART1 USART1 Alternate Function mapping
+ * @arg GPIO_RMP_USART2 USART2 Alternate Function mapping
+ * @arg GPIO_PART_RMP_USART3 USART3 Partial Alternate Function mapping
+ * @arg GPIO_ALL_RMP_USART3 USART3 Full Alternate Function mapping
+ * @arg GPIO_PART1_RMP_TIM1 TIM1 Partial Alternate Function mapping
+ * @arg GPIO_PART2_RMP_TIM1 TIM1 Partial Alternate Function mapping
+ * @arg GPIO_ALL_RMP_TIM1 TIM1 Full Alternate Function mapping
+ * @arg GPIO_PartialRemap1_TIM2 TIM2 Partial1 Alternate Function mapping
+ * @arg GPIO_PART2_RMP_TIM2 TIM2 Partial2 Alternate Function mapping
+ * @arg GPIO_ALL_RMP_TIM2 TIM2 Full Alternate Function mapping
+ * @arg GPIO_PART1_RMP_TIM3 TIM3 Partial Alternate Function mapping
+ * @arg GPIO_ALL_RMP_TIM3 TIM3 Full Alternate Function mapping
+ * @arg GPIO_RMP_TIM4 TIM4 Alternate Function mapping
+ * @arg GPIO_RMP1_CAN1 CAN1 Alternate Function mapping
+ * @arg GPIO_RMP2_CAN1 CAN1 Alternate Function mapping
+ * @arg GPIO_RMP3_CAN1 CAN1 Alternate Function mapping
+ * @arg GPIO_RMP_PD01 PD01 Alternate Function mapping
+ * @arg GPIO_RMP_TIM5CH4 LSI connected to TIM5 Channel4 input capture for calibration
+ * @arg GPIO_RMP_ADC1_ETRI ADC1 External Trigger Injected Conversion remapping
+ * @arg GPIO_RMP_ADC1_ETRR ADC1 External Trigger Regular Conversion remapping
+ * @arg GPIO_RMP_ADC2_ETRI ADC2 External Trigger Injected Conversion remapping
+ * @arg GPIO_RMP_ADC2_ETRR ADC2 External Trigger Regular Conversion remapping
+ * @arg GPIO_RMP_SW_JTAG_NO_NJTRST Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST
+ * @arg GPIO_RMP_SW_JTAG_SW_ENABLE JTAG-DP Disabled and SW-DP Enabled
+ * @arg GPIO_RMP_SW_JTAG_DISABLE Full SWJ Disabled (JTAG-DP + SW-DP)
+ * @arg GPIO_RMP_SDIO SDIO Alternate Function mapping
+ * @arg GPIO_RMP1_CAN2 CAN2 Alternate Function mapping
+ * @arg GPIO_RMP3_CAN2 CAN2 Alternate Function mapping
+ * @arg GPIO_RMP1_I2C2 I2C2 Alternate Function mapping
+ * @arg GPIO_RMP3_I2C2 I2C2 Alternate Function mapping
+ * @arg GPIO_RMP2_I2C3 I2C3 Alternate Function mapping
+ * @arg GPIO_RMP3_I2C3 I2C3 Alternate Function mapping
+ * @arg GPIO_RMP1_I2C4 I2C4 Alternate Function mapping
+ * @arg GPIO_RMP3_I2C4 I2C4 Alternate Function mapping
+ * @arg GPIO_RMP1_SPI2 SPI2 Alternate Function mapping
+ * @arg GPIO_RMP2_SPI2 SPI2 Alternate Function mapping
+ * @arg GPIO_RMP1_SPI3 SPI3 Alternate Function mapping
+ * @arg GPIO_RMP2_SPI3 SPI3 Alternate Function mapping
+ * @arg GPIO_RMP1_ETH ETH Alternate Function mapping
+ * @arg GPIO_RMP2_ETH ETH Alternate Function mapping
+ * @arg GPIO_RMP3_ETH ETH Alternate Function mapping
+ * @arg GPIO_RMP1_SPI1 SPI1 Alternate Function mapping
+ * @arg GPIO_RMP2_SPI1 SPI1 Alternate Function mapping
+ * @arg GPIO_RMP3_SPI1 SPI1 Alternate Function mapping
+ * @arg GPIO_RMP1_USART2 USART2 Alternate Function mapping
+ * @arg GPIO_RMP2_USART2 USART2 Alternate Function mapping
+ * @arg GPIO_RMP3_USART2 USART2 Alternate Function mapping
+ * @arg GPIO_RMP1_UART4 UART4 Alternate Function mapping
+ * @arg GPIO_RMP2_UART4 UART4 Alternate Function mapping
+ * @arg GPIO_RMP3_UART4 UART4 Alternate Function mapping
+ * @arg GPIO_RMP1_UART5 UART5 Alternate Function mapping
+ * @arg GPIO_RMP2_UART5 UART5 Alternate Function mapping
+ * @arg GPIO_RMP3_UART5 UART5 Alternate Function mapping
+ * @arg GPIO_RMP2_UART6 UART6 Alternate Function mapping
+ * @arg GPIO_RMP3_UART6 UART6 Alternate Function mapping
+ * @arg GPIO_RMP1_UART7 UART7 Alternate Function mapping
+ * @arg GPIO_RMP3_UART7 UART7 Alternate Function mapping
+ * @arg GPIO_RMP1_TIM8 TIM8 Alternate Function mapping
+ * @arg GPIO_RMP3_TIM8 TIM8 Alternate Function mapping
+ * @arg GPIO_RMP1_COMP1 COMP1 Alternate Function mapping
+ * @arg GPIO_RMP2_COMP1 COMP1 Alternate Function mapping
+ * @arg GPIO_RMP3_COMP1 COMP1 Alternate Function mapping
+ * @arg GPIO_RMP1_COMP2 COMP2 Alternate Function mapping
+ * @arg GPIO_RMP2_COMP2 COMP2 Alternate Function mapping
+ * @arg GPIO_RMP3_COMP2 COMP2 Alternate Function mapping
+ * @arg GPIO_RMP1_COMP3 COMP3 Alternate Function mapping
+ * @arg GPIO_RMP3_COMP3 COMP3 Alternate Function mapping
+ * @arg GPIO_RMP1_COMP4 COMP4 Alternate Function mapping
+ * @arg GPIO_RMP3_COMP4 COMP4 Alternate Function mapping
+ * @arg GPIO_RMP1_COMP5 COMP5 Alternate Function mapping
+ * @arg GPIO_RMP2_COMP5 COMP5 Alternate Function mapping
+ * @arg GPIO_RMP3_COMP5 COMP5 Alternate Function mapping
+ * @arg GPIO_RMP3_UART5 UART5 Alternate Function mapping
+ * @arg GPIO_RMP1_COMP6 COMP6 Alternate Function mapping
+ * @arg GPIO_RMP3_COMP6 COMP6 Alternate Function mapping
+ * @arg GPIO_RMP_COMP7 COMP7 Alternate Function mapping
+ * @arg GPIO_RMP_TSC_OUT_CTRL TSC_OUT_CTRL Alternate Function mapping
+ * @arg GPIO_RMP1_DVP DVP Alternate Function mapping
+ * @arg GPIO_RMP3_DVP DVP Alternate Function mapping
+ * @arg GPIO_Remap_SPI1_NSS SPI1 NSS Alternate Function mapping
+ * @arg GPIO_Remap_SPI2_NSS SPI2 NSS Alternate Function mapping
+ * @arg GPIO_Remap_SPI3_NSS SPI3 NSS Alternate Function mapping
+ * @arg GPIO_Remap_DET_EN_EGB4 EGB4 Detect Alternate Function mapping
+ * @arg GPIO_Remap_DET_EN_EGB3 EGB3 Detect Alternate Function mapping
+ * @arg GPIO_Remap_DET_EN_EGB2 EGB2 Detect Alternate Function mapping
+ * @arg GPIO_Remap_DET_EN_EGB1 EGB1 Detect Alternate Function mapping
+ * @arg GPIO_Remap_DET_EN_EGBN4 EGBN4 Detect Alternate Function mapping
+ * @arg GPIO_Remap_DET_EN_EGBN3 EGBN3 Detect Alternate Function mapping
+ * @arg GPIO_Remap_DET_EN_EGBN2 EGBN2 Detect Alternate Function mapping
+ * @arg GPIO_Remap_DET_EN_EGBN1 EGBN1 Detect Alternate Function mapping
+ * @arg GPIO_Remap_DET_EN_ECLAMP4 ECLAMP4 Detect Alternate Function mapping
+ * @arg GPIO_Remap_DET_EN_ECLAMP3 ECLAMP3 Detect Alternate Function mapping
+ * @arg GPIO_Remap_DET_EN_ECLAMP2 ECLAMP2 Detect Alternate Function mapping
+ * @arg GPIO_Remap_DET_EN_ECLAMP1 ECLAMP1 Detect Alternate Function mapping
+ * @arg GPIO_Remap_RST_EN_EGB4 EGB4 Reset Alternate Function mapping
+ * @arg GPIO_Remap_RST_EN_EGB3 EGB3 Reset Alternate Function mapping
+ * @arg GPIO_Remap_RST_EN_EGB2 EGB2 Reset Alternate Function mapping
+ * @arg GPIO_Remap_RST_EN_EGB1 EGB1 Reset Alternate Function mapping
+ * @arg GPIO_Remap_RST_EN_EGBN4 EGBN4 Reset Alternate Function mapping
+ * @arg GPIO_Remap_RST_EN_EGBN3 EGBN3 Reset Alternate Function mapping
+ * @arg GPIO_Remap_RST_EN_EGBN2 EGBN2 Reset Alternate Function mapping
+ * @arg GPIO_Remap_RST_EN_EGBN1 EGBN1 Reset Alternate Function mapping
+ * @arg GPIO_Remap_RST_EN_ECLAMP4 ECLAMP4 Reset Alternate Function mapping
+ * @arg GPIO_Remap_RST_EN_ECLAMP3 ECLAMP3 Reset Alternate Function mapping
+ * @arg GPIO_Remap_RST_EN_ECLAMP2 ECLAMP2 Reset Alternate Function mapping
+ * @arg GPIO_Remap_RST_EN_ECLAMP1 ECLAMP1 Reset Alternate Function mapping
+ * @param Cmd new state of the port pin remapping.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void GPIO_ConfigPinRemap(uint32_t RmpPin, FunctionalState Cmd)
+{
+ uint32_t tmp = 0x00, tmp1 = 0x00, tmpregister = 0x00, tmpmask = 0x00, tmp2 = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_REMAP(RmpPin));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ /* Check RmpPin relate AFIO RMP_CFG */
+ if ((RmpPin & 0x40000000) == 0x40000000)
+ {
+ tmpregister = AFIO->RMP_CFG3;
+ }
+ else if ((RmpPin & 0x20000000) == 0x20000000)
+ {
+ tmpregister = AFIO->RMP_CFG4;
+ }
+ else if ((RmpPin & 0x10000000) == 0x10000000)
+ {
+ tmpregister = AFIO->RMP_CFG5;
+ }
+ else
+ {
+ tmpregister = AFIO->RMP_CFG;
+ }
+
+ tmpmask = (RmpPin & DBGAFR_POSITION_MASK) >> 16;
+ tmp = RmpPin & LSB_MASK;
+
+ if ((RmpPin
+ & (DBGAFR_NUMBITS_MAPR5_MASK | DBGAFR_NUMBITS_MAPR4_MASK | DBGAFR_NUMBITS_MAPR3_MASK | DBGAFR_LOCATION_MASK
+ | DBGAFR_NUMBITS_MASK))
+ == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))
+ {
+ tmpregister &= DBGAFR_SWJCFG_MASK;
+ AFIO->RMP_CFG &= DBGAFR_SWJCFG_MASK;
+ }
+ else if ((RmpPin & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)
+ {
+ if ((RmpPin & DBGAFR_LOCATION_MASK) == DBGAFR_LOCATION_MASK)
+ {
+ tmp1 = (((uint32_t)0x03) << tmpmask) << 16;
+ }
+ else
+ {
+ tmp1 = ((uint32_t)0x03) << tmpmask;
+ }
+ tmpregister &= ~tmp1;
+ if ((RmpPin & 0x70000000) == 0x00000000)
+ {
+ tmpregister |= ~DBGAFR_SWJCFG_MASK;
+ }
+ }
+ else
+ {/*configuration AFIO RMP_CFG*/
+ if ((RmpPin & DBGAFR_NUMBITS_SPI1_MASK) == DBGAFR_NUMBITS_SPI1_MASK)
+ {
+ if ((RmpPin & 0x00000004) == 0x00000004)
+ {
+ if ((RmpPin & 0x02000000) == 0x02000000) // GPIO_RMP3_SPI1
+ {
+ tmpregister &= ~(tmp << (((RmpPin & 0x00200000) >> 21) * 16));
+ if (Cmd != DISABLE)
+ {
+ tmp2 = AFIO->RMP_CFG;
+ tmp2 |= 0x00000001;
+ tmp2 |= ~DBGAFR_SWJCFG_MASK;
+ AFIO->RMP_CFG = tmp2; // Remap_SPI1 ENABLE
+ }
+ else
+ {
+ tmp2 = AFIO->RMP_CFG;
+ tmp2 &= 0xFFFFFFFE;
+ tmp2 |= ~DBGAFR_SWJCFG_MASK;
+ AFIO->RMP_CFG = tmp2; // Remap_SPI1 DISABLE
+ }
+ }
+ else
+ {
+ tmpregister &= ~(tmp << (((RmpPin & 0x00200000) >> 21) * 16)); // GPIO_RMP2_SPI1
+
+ tmp2 = AFIO->RMP_CFG;
+ tmp2 &= 0xFFFFFFFE;
+ tmp2 |= ~DBGAFR_SWJCFG_MASK;
+ AFIO->RMP_CFG = tmp2; // Remap_SPI1 DISABLE
+ }
+ }
+ else
+ {
+ tmpregister &= ~((tmp | 0x00000004) << (((RmpPin & 0x00200000) >> 21) * 16)); // clear
+ if (Cmd != DISABLE) // GPIO_RMP1_SPI1
+ {
+ tmp2 = AFIO->RMP_CFG;
+ tmp2 |= 0x00000001;
+ tmp2 |= ~DBGAFR_SWJCFG_MASK;
+ AFIO->RMP_CFG = tmp2; // Remap_SPI1 ENABLE
+ }
+ else
+ {
+ tmp2 = AFIO->RMP_CFG;
+ tmp2 &= 0xFFFFFFFE;
+ tmp2 |= ~DBGAFR_SWJCFG_MASK;
+ AFIO->RMP_CFG = tmp2; // Remap_SPI1 DISABLE
+ }
+ }
+ }
+ else if ((RmpPin & DBGAFR_NUMBITS_USART2_MASK) == DBGAFR_NUMBITS_USART2_MASK)
+ {
+ if ((RmpPin & 0x00000008) == 0x00000008)
+ {
+ if ((RmpPin & 0x02000000) == 0x02000000) // GPIO_RMP3_USART2
+ {
+ tmpregister &= ~(tmp << (((RmpPin & 0x00200000) >> 21) * 16));
+ if (Cmd != DISABLE)
+ {
+ tmp2 = AFIO->RMP_CFG;
+ tmp2 |= 0x00000008;
+ tmp2 |= ~DBGAFR_SWJCFG_MASK;
+ AFIO->RMP_CFG = tmp2; // Remap_USART2 ENABLE
+ }
+ else
+ {
+ tmp2 = AFIO->RMP_CFG;
+ tmp2 &= 0xFFFFFFF7;
+ tmp2 |= ~DBGAFR_SWJCFG_MASK;
+ AFIO->RMP_CFG = tmp2; // Remap_USART2 DISABLE
+ }
+ }
+ else
+ {
+ tmpregister &= ~(tmp << (((RmpPin & 0x00200000) >> 21) * 16)); // GPIO_RMP2_USART2
+
+ tmp2 = AFIO->RMP_CFG;
+ tmp2 &= 0xFFFFFFF7;
+ tmp2 |= ~DBGAFR_SWJCFG_MASK;
+ AFIO->RMP_CFG = tmp2; // Remap_USART2 DISABLE
+ }
+ }
+ else // GPIO_RMP1_USART2
+ {
+ tmpregister &= ~((tmp | 0x00000008) << (((RmpPin & 0x00200000) >> 21) * 16)); // clear
+ if (Cmd != DISABLE)
+ {
+ tmp2 = AFIO->RMP_CFG;
+ tmp2 |= 0x00000008;
+ tmp2 |= ~DBGAFR_SWJCFG_MASK;
+ AFIO->RMP_CFG = tmp2; // Remap_USART2 ENABLE
+ }
+ else
+ {
+ tmp2 = AFIO->RMP_CFG;
+ tmp2 &= 0xFFFFFFF7;
+ tmp2 |= ~DBGAFR_SWJCFG_MASK;
+ AFIO->RMP_CFG = tmp2; // Remap_USART2 DISABLE
+ }
+ }
+ }
+ else
+ {
+ tmpregister &= ~(tmp << (((RmpPin & 0x00200000) >> 21) * 16));
+ if ((RmpPin & 0x70000000) == 0x00000000)
+ {
+ tmpregister |= ~DBGAFR_SWJCFG_MASK;
+ }
+ }
+ }
+
+ /*configuration AFIO RMP_CFG~RMP_CFG5*/
+ if (Cmd != DISABLE)
+ {
+ tmpregister |= (tmp << (((RmpPin & 0x00200000) >> 21) * 16));
+ }
+
+ if ((RmpPin & 0x40000000) == 0x40000000)
+ {
+ AFIO->RMP_CFG3 = tmpregister;
+ }
+ else if ((RmpPin & 0x20000000) == 0x20000000)
+ {
+ AFIO->RMP_CFG4 = tmpregister;
+ }
+ else if ((RmpPin & 0x10000000) == 0x10000000)
+ {
+ AFIO->RMP_CFG5 = tmpregister;
+ }
+ else
+ {
+ AFIO->RMP_CFG = tmpregister;
+ }
+}
+
+/**
+ * @brief Selects the GPIO pin used as EXTI Line.
+ * @param PortSource selects the GPIO port to be used as source for EXTI lines.
+ * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
+ * @param PinSource specifies the EXTI line to be configured.
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).
+ */
+void GPIO_ConfigEXTILine(uint8_t PortSource, uint8_t PinSource)
+{
+ uint32_t tmp = 0x00;
+ /* Check the parameters */
+ assert_param(IS_GPIO_EXTI_PORT_SOURCE(PortSource));
+ assert_param(IS_GPIO_PIN_SOURCE(PinSource));
+
+ tmp = ((uint32_t)0x0F) << (0x04 * (PinSource & (uint8_t)0x03));
+ AFIO->EXTI_CFG[PinSource >> 0x02] &= ~tmp;
+ AFIO->EXTI_CFG[PinSource >> 0x02] |= (((uint32_t)PortSource) << (0x04 * (PinSource & (uint8_t)0x03)));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_i2c.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_i2c.c
new file mode 100644
index 0000000000..994091a98a
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_i2c.c
@@ -0,0 +1,1324 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_i2c.c
+ * @author Nations
+ * @version v1.0.2
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32wb452_i2c.h"
+#include "n32wb452_rcc.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @brief I2C driver modules
+ * @{
+ */
+
+/** @addtogroup I2C_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_Defines
+ * @{
+ */
+
+/* I2C SPE mask */
+#define CTRL1_SPEN_SET ((uint16_t)0x0001)
+#define CTRL1_SPEN_RESET ((uint16_t)0xFFFE)
+
+/* I2C START mask */
+#define CTRL1_START_SET ((uint16_t)0x0100)
+#define CTRL1_START_RESET ((uint16_t)0xFEFF)
+
+/* I2C STOP mask */
+#define CTRL1_STOP_SET ((uint16_t)0x0200)
+#define CTRL1_STOP_RESET ((uint16_t)0xFDFF)
+
+/* I2C ACK mask */
+#define CTRL1_ACK_SET ((uint16_t)0x0400)
+#define CTRL1_ACK_RESET ((uint16_t)0xFBFF)
+
+/* I2C ENGC mask */
+#define CTRL1_GCEN_SET ((uint16_t)0x0040)
+#define CTRL1_GCEN_RESET ((uint16_t)0xFFBF)
+
+/* I2C SWRST mask */
+#define CTRL1_SWRESET_SET ((uint16_t)0x8000)
+#define CTRL1_SWRESET_RESET ((uint16_t)0x7FFF)
+
+/* I2C PEC mask */
+#define CTRL1_PEC_SET ((uint16_t)0x1000)
+#define CTRL1_PEC_RESET ((uint16_t)0xEFFF)
+
+/* I2C ENPEC mask */
+#define CTRL1_PECEN_SET ((uint16_t)0x0020)
+#define CTRL1_PECEN_RESET ((uint16_t)0xFFDF)
+
+/* I2C ENARP mask */
+#define CTRL1_ARPEN_SET ((uint16_t)0x0010)
+#define CTRL1_ARPEN_RESET ((uint16_t)0xFFEF)
+
+/* I2C NOSTRETCH mask */
+#define CTRL1_NOEXTEND_SET ((uint16_t)0x0080)
+#define CTRL1_NOEXTEND_RESET ((uint16_t)0xFF7F)
+
+/* I2C registers Masks */
+#define CTRL1_CLR_MASK ((uint16_t)0xFBF5)
+
+/* I2C DMAEN mask */
+#define CTRL2_DMAEN_SET ((uint16_t)0x0800)
+#define CTRL2_DMAEN_RESET ((uint16_t)0xF7FF)
+
+/* I2C LAST mask */
+#define CTRL2_DMALAST_SET ((uint16_t)0x1000)
+#define CTRL2_DMALAST_RESET ((uint16_t)0xEFFF)
+
+/* I2C FREQ mask */
+#define CTRL2_CLKFREQ_RESET ((uint16_t)0xFFC0)
+
+/* I2C ADD0 mask */
+#define OADDR1_ADDR0_SET ((uint16_t)0x0001)
+#define OADDR1_ADDR0_RESET ((uint16_t)0xFFFE)
+
+/* I2C ENDUAL mask */
+#define OADDR2_DUALEN_SET ((uint16_t)0x0001)
+#define OADDR2_DUALEN_RESET ((uint16_t)0xFFFE)
+
+/* I2C ADD2 mask */
+#define OADDR2_ADDR2_RESET ((uint16_t)0xFF01)
+
+/* I2C F/S mask */
+#define CLKCTRL_FSMODE_SET ((uint16_t)0x8000)
+
+/* I2C CHCFG mask */
+#define CLKCTRL_CLKCTRL_SET ((uint16_t)0x0FFF)
+
+/* I2C FLAG mask */
+#define FLAG_MASK ((uint32_t)0x00FFFFFF)
+
+/* I2C Interrupt Enable mask */
+#define INTEN_MASK ((uint32_t)0x07000000)
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the I2Cx peripheral registers to their default reset values.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ */
+void I2C_DeInit(I2C_Module* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+
+ if (I2Cx == I2C1)
+ {
+ /* Enable I2C1 reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C1, ENABLE);
+ /* Release I2C1 from reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C1, DISABLE);
+ }
+ else if (I2Cx == I2C2)
+ {
+ /* Enable I2C2 reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C2, ENABLE);
+ /* Release I2C2 from reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C2, DISABLE);
+ }
+ else if (I2Cx == I2C3)
+ {
+ /* Enable I2C3 reset state */
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_I2C3, ENABLE);
+ /* Release I2C3 from reset state */
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_I2C3, DISABLE);
+ }
+ else if (I2Cx == I2C4)
+ {
+ /* Enable I2C4 reset state */
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_I2C4, ENABLE);
+ /* Release I2C4 from reset state */
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_I2C4, DISABLE);
+ }
+ else
+ {
+
+ }
+}
+
+/**
+ * @brief Initializes the I2Cx peripheral according to the specified
+ * parameters in the I2C_InitStruct.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_InitStruct pointer to a I2C_InitType structure that
+ * contains the configuration information for the specified I2C peripheral.
+ */
+void I2C_Init(I2C_Module* I2Cx, I2C_InitType* I2C_InitStruct)
+{
+ uint16_t tmpregister = 0, freqrange = 0;
+ uint16_t result = 0x04;
+ uint32_t pclk = 8000000;
+ RCC_ClocksType rcc_clocks;
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_CLK_SPEED(I2C_InitStruct->ClkSpeed));
+ assert_param(IS_I2C_BUS_MODE(I2C_InitStruct->BusMode));
+ assert_param(IS_I2C_FM_DUTY_CYCLE(I2C_InitStruct->FmDutyCycle));
+ assert_param(IS_I2C_OWN_ADDR1(I2C_InitStruct->OwnAddr1));
+ assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->AckEnable));
+ assert_param(IS_I2C_ADDR_MODE(I2C_InitStruct->AddrMode));
+
+ /*---------------------------- I2Cx CTRL2 Configuration ------------------------*/
+ /* Get the I2Cx CTRL2 value */
+ tmpregister = I2Cx->CTRL2;
+ /* Clear frequency FREQ[5:0] bits */
+ tmpregister &= CTRL2_CLKFREQ_RESET;
+ /* Get APB1/2 frequency value */
+ RCC_GetClocksFreqValue(&rcc_clocks);
+
+ if ((I2Cx == I2C1) || (I2Cx == I2C2))
+ {
+ pclk = rcc_clocks.Pclk1Freq;
+ }
+ else if ((I2Cx == I2C3) || (I2Cx == I2C4))
+ {
+ pclk = rcc_clocks.Pclk2Freq;
+ }
+
+ /* Set frequency bits depending on pclk1 value */
+ freqrange = (uint16_t)(pclk / 1000000);
+ if (tmpregister > 36)
+ {
+ tmpregister = 36;
+ }
+ /* Write to I2Cx CTRL2 */
+ tmpregister |= freqrange;
+ I2Cx->CTRL2 = tmpregister;
+
+ /*---------------------------- I2Cx CHCFG Configuration ------------------------*/
+ /* Disable the selected I2C peripheral to configure TMRISE */
+ I2Cx->CTRL1 &= CTRL1_SPEN_RESET;
+ /* Reset tmpregister value */
+ /* Clear F/S, DUTY and CHCFG[11:0] bits */
+ tmpregister = 0;
+
+ /* Configure speed in standard mode */
+ if (I2C_InitStruct->ClkSpeed <= 100000)
+ {
+ /* Standard mode speed calculate */
+ result = (uint16_t)(pclk / (I2C_InitStruct->ClkSpeed << 1));
+ /* Test if CHCFG value is under 0x4*/
+ if (result < 0x04)
+ {
+ /* Set minimum allowed value */
+ result = 0x04;
+ }
+ /* Set speed value for standard mode */
+ tmpregister |= result;
+ /* Set Maximum Rise Time for standard mode */
+ I2Cx->TMRISE = freqrange + 1;
+ }
+ /* Configure speed in fast mode */
+ else
+ {
+ if (I2C_InitStruct->FmDutyCycle == I2C_FMDUTYCYCLE_2)
+ {
+ /* Fast mode speed calculate: Tlow/Thigh = 2 */
+ result = (uint16_t)(pclk / (I2C_InitStruct->ClkSpeed * 3));
+ }
+ else /*I2C_InitStruct->FmDutyCycle == I2C_FMDUTYCYCLE_16_9*/
+ {
+ /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
+ result = (uint16_t)(pclk / (I2C_InitStruct->ClkSpeed * 25));
+ /* Set DUTY bit */
+ result |= I2C_FMDUTYCYCLE_16_9;
+ }
+
+ /* Test if CHCFG value is under 0x1*/
+ if ((result & CLKCTRL_CLKCTRL_SET) == 0)
+ {
+ /* Set minimum allowed value */
+ result |= (uint16_t)0x0001;
+ }
+ /* Set speed value and set F/S bit for fast mode */
+ tmpregister |= (uint16_t)(result | CLKCTRL_FSMODE_SET);
+
+ /* Set Maximum Rise Time for fast mode */
+ I2Cx->TMRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
+ }
+ /* Write to I2Cx CHCFG */
+ I2Cx->CLKCTRL = tmpregister;
+ /* Enable the selected I2C peripheral */
+ I2Cx->CTRL1 |= CTRL1_SPEN_SET;
+
+ /*---------------------------- I2Cx CTRL1 Configuration ------------------------*/
+ /* Get the I2Cx CTRL1 value */
+ tmpregister = I2Cx->CTRL1;
+ /* Clear ACK, SMBTYPE and SMBUS bits */
+ tmpregister &= CTRL1_CLR_MASK;
+ /* Configure I2Cx: mode and acknowledgement */
+ /* Set SMBTYPE and SMBUS bits according to BusMode value */
+ /* Set ACK bit according to AckEnable value */
+ tmpregister |= (uint16_t)((uint32_t)I2C_InitStruct->BusMode | I2C_InitStruct->AckEnable);
+ /* Write to I2Cx CTRL1 */
+ I2Cx->CTRL1 = tmpregister;
+
+ /*---------------------------- I2Cx OADDR1 Configuration -----------------------*/
+ /* Set I2Cx Own Address1 and acknowledged address */
+ I2Cx->OADDR1 = (I2C_InitStruct->AddrMode | I2C_InitStruct->OwnAddr1);
+}
+
+/**
+ * @brief Fills each I2C_InitStruct member with its default value.
+ * @param I2C_InitStruct pointer to an I2C_InitType structure which will be initialized.
+ */
+void I2C_InitStruct(I2C_InitType* I2C_InitStruct)
+{
+ /*---------------- Reset I2C init structure parameters values ----------------*/
+ /* initialize the ClkSpeed member */
+ I2C_InitStruct->ClkSpeed = 5000;
+ /* Initialize the BusMode member */
+ I2C_InitStruct->BusMode = I2C_BUSMODE_I2C;
+ /* Initialize the FmDutyCycle member */
+ I2C_InitStruct->FmDutyCycle = I2C_FMDUTYCYCLE_2;
+ /* Initialize the OwnAddr1 member */
+ I2C_InitStruct->OwnAddr1 = 0;
+ /* Initialize the AckEnable member */
+ I2C_InitStruct->AckEnable = I2C_ACKDIS;
+ /* Initialize the AddrMode member */
+ I2C_InitStruct->AddrMode = I2C_ADDR_MODE_7BIT;
+}
+
+/**
+ * @brief Enables or disables the specified I2C peripheral.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2Cx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_Enable(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected I2C peripheral */
+ I2Cx->CTRL1 |= CTRL1_SPEN_SET;
+ }
+ else
+ {
+ /* Disable the selected I2C peripheral */
+ I2Cx->CTRL1 &= CTRL1_SPEN_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C DMA requests.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C DMA transfer.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableDMA(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected I2C DMA requests */
+ I2Cx->CTRL2 |= CTRL2_DMAEN_SET;
+ }
+ else
+ {
+ /* Disable the selected I2C DMA requests */
+ I2Cx->CTRL2 &= CTRL2_DMAEN_RESET;
+ }
+}
+
+/**
+ * @brief Specifies if the next DMA transfer will be the last one.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C DMA last transfer.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableDmaLastSend(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Next DMA transfer is the last transfer */
+ I2Cx->CTRL2 |= CTRL2_DMALAST_SET;
+ }
+ else
+ {
+ /* Next DMA transfer is not the last transfer */
+ I2Cx->CTRL2 &= CTRL2_DMALAST_RESET;
+ }
+}
+
+/**
+ * @brief Generates I2Cx communication START condition.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C START condition generation.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_GenerateStart(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Generate a START condition */
+ I2Cx->CTRL1 |= CTRL1_START_SET;
+ }
+ else
+ {
+ /* Disable the START condition generation */
+ I2Cx->CTRL1 &= CTRL1_START_RESET;
+ }
+}
+
+/**
+ * @brief Generates I2Cx communication STOP condition.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C STOP condition generation.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_GenerateStop(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Generate a STOP condition */
+ I2Cx->CTRL1 |= CTRL1_STOP_SET;
+ }
+ else
+ {
+ /* Disable the STOP condition generation */
+ I2Cx->CTRL1 &= CTRL1_STOP_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C acknowledge feature.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C Acknowledgement.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_ConfigAck(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the acknowledgement */
+ I2Cx->CTRL1 |= CTRL1_ACK_SET;
+ }
+ else
+ {
+ /* Disable the acknowledgement */
+ I2Cx->CTRL1 &= CTRL1_ACK_RESET;
+ }
+}
+
+/**
+ * @brief Configures the specified I2C own address2.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Address specifies the 7bit I2C own address2.
+ */
+void I2C_ConfigOwnAddr2(I2C_Module* I2Cx, uint8_t Address)
+{
+ uint16_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+
+ /* Get the old register value */
+ tmpregister = I2Cx->OADDR2;
+
+ /* Reset I2Cx Own address2 bit [7:1] */
+ tmpregister &= OADDR2_ADDR2_RESET;
+
+ /* Set I2Cx Own address2 */
+ tmpregister |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
+
+ /* Store the new register value */
+ I2Cx->OADDR2 = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the specified I2C dual addressing mode.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C dual addressing mode.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableDualAddr(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable dual addressing mode */
+ I2Cx->OADDR2 |= OADDR2_DUALEN_SET;
+ }
+ else
+ {
+ /* Disable dual addressing mode */
+ I2Cx->OADDR2 &= OADDR2_DUALEN_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C general call feature.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C General call.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableGeneralCall(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable generall call */
+ I2Cx->CTRL1 |= CTRL1_GCEN_SET;
+ }
+ else
+ {
+ /* Disable generall call */
+ I2Cx->CTRL1 &= CTRL1_GCEN_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C interrupts.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT specifies the I2C interrupts sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_INT_BUF Buffer interrupt mask
+ * @arg I2C_INT_EVENT Event interrupt mask
+ * @arg I2C_INT_ERR Error interrupt mask
+ * @param Cmd new state of the specified I2C interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_ConfigInt(I2C_Module* I2Cx, uint16_t I2C_IT, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ assert_param(IS_I2C_CFG_INT(I2C_IT));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected I2C interrupts */
+ I2Cx->CTRL2 |= I2C_IT;
+ }
+ else
+ {
+ /* Disable the selected I2C interrupts */
+ I2Cx->CTRL2 &= (uint16_t)~I2C_IT;
+ }
+}
+
+/**
+ * @brief Sends a data byte through the I2Cx peripheral.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Data Byte to be transmitted..
+ */
+void I2C_SendData(I2C_Module* I2Cx, uint8_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ /* Write in the DAT register the data to be sent */
+ I2Cx->DAT = Data;
+}
+
+/**
+ * @brief Returns the most recent received data by the I2Cx peripheral.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @return The value of the received data.
+ */
+uint8_t I2C_RecvData(I2C_Module* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ /* Return the data in the DAT register */
+ return (uint8_t)I2Cx->DAT;
+}
+
+/**
+ * @brief Transmits the address byte to select the slave device.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Address specifies the slave address which will be transmitted
+ * @param I2C_Direction specifies whether the I2C device will be a
+ * Transmitter or a Receiver. This parameter can be one of the following values
+ * @arg I2C_DIRECTION_SEND Transmitter mode
+ * @arg I2C_DIRECTION_RECV Receiver mode
+ */
+void I2C_SendAddr7bit(I2C_Module* I2Cx, uint8_t Address, uint8_t I2C_Direction)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_DIRECTION(I2C_Direction));
+ /* Test on the direction to set/reset the read/write bit */
+ if (I2C_Direction != I2C_DIRECTION_SEND)
+ {
+ /* Set the address bit0 for read */
+ Address |= OADDR1_ADDR0_SET;
+ }
+ else
+ {
+ /* Reset the address bit0 for write */
+ Address &= OADDR1_ADDR0_RESET;
+ }
+ /* Send the address */
+ I2Cx->DAT = Address;
+}
+
+/**
+ * @brief Reads the specified I2C register and returns its value.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_Register specifies the register to read.
+ * This parameter can be one of the following values:
+ * @arg I2C_REG_CTRL1 CTRL1 register.
+ * @arg I2C_REG_CTRL2 CTRL2 register.
+ * @arg I2C_REG_OADDR1 OADDR1 register.
+ * @arg I2C_REG_OADDR2 OADDR2 register.
+ * @arg I2C_REG_DAT DAT register.
+ * @arg I2C_REG_STS1 STS1 register.
+ * @arg I2C_REG_STS2 STS2 register.
+ * @arg I2C_REG_CLKCTRL CHCFG register.
+ * @arg I2C_REG_TMRISE TMRISE register.
+ * @return The value of the read register.
+ */
+uint16_t I2C_GetRegister(I2C_Module* I2Cx, uint8_t I2C_Register)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_REG(I2C_Register));
+
+ tmp = (uint32_t)I2Cx;
+ tmp += I2C_Register;
+
+ /* Return the selected register value */
+ return (*(__IO uint16_t*)tmp);
+}
+
+/**
+ * @brief Enables or disables the specified I2C software reset.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C software reset.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableSoftwareReset(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Peripheral under reset */
+ I2Cx->CTRL1 |= CTRL1_SWRESET_SET;
+ }
+ else
+ {
+ /* Peripheral not under reset */
+ I2Cx->CTRL1 &= CTRL1_SWRESET_RESET;
+ }
+}
+
+/**
+ * @brief Selects the specified I2C NACK position in master receiver mode.
+ * This function is useful in I2C Master Receiver mode when the number
+ * of data to be received is equal to 2. In this case, this function
+ * should be called (with parameter I2C_NACK_POS_NEXT) before data
+ * reception starts,as described in the 2-byte reception procedure
+ * recommended in Reference Manual in Section: Master receiver.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_NACKPosition specifies the NACK position.
+ * This parameter can be one of the following values:
+ * @arg I2C_NACK_POS_NEXT indicates that the next byte will be the last
+ * received byte.
+ * @arg I2C_NACK_POS_CURRENT indicates that current byte is the last
+ * received byte.
+ *
+ * @note This function configures the same bit (POS) as I2C_ConfigPecLocation()
+ * but is intended to be used in I2C mode while I2C_ConfigPecLocation()
+ * is intended to used in SMBUS mode.
+ *
+ */
+void I2C_ConfigNackLocation(I2C_Module* I2Cx, uint16_t I2C_NACKPosition)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_NACK_POS(I2C_NACKPosition));
+
+ /* Check the input parameter */
+ if (I2C_NACKPosition == I2C_NACK_POS_NEXT)
+ {
+ /* Next byte in shift register is the last received byte */
+ I2Cx->CTRL1 |= I2C_NACK_POS_NEXT;
+ }
+ else
+ {
+ /* Current byte in shift register is the last received byte */
+ I2Cx->CTRL1 &= I2C_NACK_POS_CURRENT;
+ }
+}
+
+/**
+ * @brief Drives the SMBusAlert pin high or low for the specified I2C.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_SMBusAlert specifies SMBAlert pin level.
+ * This parameter can be one of the following values:
+ * @arg I2C_SMBALERT_LOW SMBAlert pin driven low
+ * @arg I2C_SMBALERT_HIGH SMBAlert pin driven high
+ */
+void I2C_ConfigSmbusAlert(I2C_Module* I2Cx, uint16_t I2C_SMBusAlert)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_SMB_ALERT(I2C_SMBusAlert));
+ if (I2C_SMBusAlert == I2C_SMBALERT_LOW)
+ {
+ /* Drive the SMBusAlert pin Low */
+ I2Cx->CTRL1 |= I2C_SMBALERT_LOW;
+ }
+ else
+ {
+ /* Drive the SMBusAlert pin High */
+ I2Cx->CTRL1 &= I2C_SMBALERT_HIGH;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C PEC transfer.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C PEC transmission.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_SendPEC(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected I2C PEC transmission */
+ I2Cx->CTRL1 |= CTRL1_PEC_SET;
+ }
+ else
+ {
+ /* Disable the selected I2C PEC transmission */
+ I2Cx->CTRL1 &= CTRL1_PEC_RESET;
+ }
+}
+
+/**
+ * @brief Selects the specified I2C PEC position.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_PECPosition specifies the PEC position.
+ * This parameter can be one of the following values:
+ * @arg I2C_PEC_POS_NEXT indicates that the next byte is PEC
+ * @arg I2C_PEC_POS_CURRENT indicates that current byte is PEC
+ *
+ * @note This function configures the same bit (POS) as I2C_ConfigNackLocation()
+ * but is intended to be used in SMBUS mode while I2C_ConfigNackLocation()
+ * is intended to used in I2C mode.
+ *
+ */
+void I2C_ConfigPecLocation(I2C_Module* I2Cx, uint16_t I2C_PECPosition)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_PEC_POS(I2C_PECPosition));
+ if (I2C_PECPosition == I2C_PEC_POS_NEXT)
+ {
+ /* Next byte in shift register is PEC */
+ I2Cx->CTRL1 |= I2C_PEC_POS_NEXT;
+ }
+ else
+ {
+ /* Current byte in shift register is PEC */
+ I2Cx->CTRL1 &= I2C_PEC_POS_CURRENT;
+ }
+}
+
+/**
+ * @brief Enables or disables the PEC value calculation of the transferred bytes.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2Cx PEC value calculation.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_ComputePec(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected I2C PEC calculation */
+ I2Cx->CTRL1 |= CTRL1_PECEN_SET;
+ }
+ else
+ {
+ /* Disable the selected I2C PEC calculation */
+ I2Cx->CTRL1 &= CTRL1_PECEN_RESET;
+ }
+}
+
+/**
+ * @brief Returns the PEC value for the specified I2C.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @return The PEC value.
+ */
+uint8_t I2C_GetPec(I2C_Module* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ /* Return the selected I2C PEC value */
+ return ((I2Cx->STS2) >> 8);
+}
+
+/**
+ * @brief Enables or disables the specified I2C ARP.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2Cx ARP.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableArp(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected I2C ARP */
+ I2Cx->CTRL1 |= CTRL1_ARPEN_SET;
+ }
+ else
+ {
+ /* Disable the selected I2C ARP */
+ I2Cx->CTRL1 &= CTRL1_ARPEN_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C Clock stretching.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2Cx Clock stretching.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableExtendClk(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd == DISABLE)
+ {
+ /* Enable the selected I2C Clock stretching */
+ I2Cx->CTRL1 |= CTRL1_NOEXTEND_SET;
+ }
+ else
+ {
+ /* Disable the selected I2C Clock stretching */
+ I2Cx->CTRL1 &= CTRL1_NOEXTEND_RESET;
+ }
+}
+
+/**
+ * @brief Selects the specified I2C fast mode duty cycle.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param FmDutyCycle specifies the fast mode duty cycle.
+ * This parameter can be one of the following values:
+ * @arg I2C_FMDUTYCYCLE_2 I2C fast mode Tlow/Thigh = 2
+ * @arg I2C_FMDUTYCYCLE_16_9 I2C fast mode Tlow/Thigh = 16/9
+ */
+void I2C_ConfigFastModeDutyCycle(I2C_Module* I2Cx, uint16_t FmDutyCycle)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_FM_DUTY_CYCLE(FmDutyCycle));
+ if (FmDutyCycle != I2C_FMDUTYCYCLE_16_9)
+ {
+ /* I2C fast mode Tlow/Thigh=2 */
+ I2Cx->CLKCTRL &= I2C_FMDUTYCYCLE_2;
+ }
+ else
+ {
+ /* I2C fast mode Tlow/Thigh=16/9 */
+ I2Cx->CLKCTRL |= I2C_FMDUTYCYCLE_16_9;
+ }
+}
+
+/**
+ * @brief
+ ****************************************************************************************
+ *
+ * I2C State Monitoring Functions
+ *
+ ****************************************************************************************
+ * This I2C driver provides three different ways for I2C state monitoring
+ * depending on the application requirements and constraints:
+ *
+ *
+ * 1) Basic state monitoring:
+ * Using I2C_CheckEvent() function:
+ * It compares the status registers (STS1 and STS2) content to a given event
+ * (can be the combination of one or more flags).
+ * It returns SUCCESS if the current status includes the given flags
+ * and returns ERROR if one or more flags are missing in the current status.
+ * - When to use:
+ * - This function is suitable for most applications as well as for startup
+ * activity since the events are fully described in the product reference manual
+ * (RM0008).
+ * - It is also suitable for users who need to define their own events.
+ * - Limitations:
+ * - If an error occurs (ie. error flags are set besides to the monitored flags),
+ * the I2C_CheckEvent() function may return SUCCESS despite the communication
+ * hold or corrupted real state.
+ * In this case, it is advised to use error interrupts to monitor the error
+ * events and handle them in the interrupt IRQ handler.
+ *
+ * @note
+ * For error management, it is advised to use the following functions:
+ * - I2C_ConfigInt() to configure and enable the error interrupts (I2C_INT_ERR).
+ * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
+ * Where x is the peripheral instance (I2C1, I2C2 ...)
+ * - I2C_GetFlag() or I2C_GetIntStatus() to be called into I2Cx_ER_IRQHandler()
+ * in order to determine which error occured.
+ * - I2C_ClrFlag() or I2C_ClrIntPendingBit() and/or I2C_EnableSoftwareReset()
+ * and/or I2C_GenerateStop() in order to clear the error flag and source,
+ * and return to correct communication status.
+ *
+ *
+ * 2) Advanced state monitoring:
+ * Using the function I2C_GetLastEvent() which returns the image of both status
+ * registers in a single word (uint32_t) (Status Register 2 value is shifted left
+ * by 16 bits and concatenated to Status Register 1).
+ * - When to use:
+ * - This function is suitable for the same applications above but it allows to
+ * overcome the mentioned limitation of I2C_GetFlag() function.
+ * The returned value could be compared to events already defined in the
+ * library (n32wb452_i2c.h) or to custom values defined by user.
+ * - This function is suitable when multiple flags are monitored at the same time.
+ * - At the opposite of I2C_CheckEvent() function, this function allows user to
+ * choose when an event is accepted (when all events flags are set and no
+ * other flags are set or just when the needed flags are set like
+ * I2C_CheckEvent() function).
+ * - Limitations:
+ * - User may need to define his own events.
+ * - Same remark concerning the error management is applicable for this
+ * function if user decides to check only regular communication flags (and
+ * ignores error flags).
+ *
+ *
+ * 3) Flag-based state monitoring:
+ * Using the function I2C_GetFlag() which simply returns the status of
+ * one single flag (ie. I2C_FLAG_RXDATNE ...).
+ * - When to use:
+ * - This function could be used for specific applications or in debug phase.
+ * - It is suitable when only one flag checking is needed (most I2C events
+ * are monitored through multiple flags).
+ * - Limitations:
+ * - When calling this function, the Status register is accessed. Some flags are
+ * cleared when the status register is accessed. So checking the status
+ * of one Flag, may clear other ones.
+ * - Function may need to be called twice or more in order to monitor one
+ * single event.
+ *
+ * For detailed description of Events, please refer to section I2C_Events in
+ * n32wb452_i2c.h file.
+ *
+ */
+
+/**
+ * @brief Checks whether the last I2Cx Event is equal to the one passed
+ * as parameter.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_EVENT specifies the event to be checked.
+ * This parameter can be one of the following values:
+ * @arg I2C_EVT_SLAVE_SEND_ADDR_MATCHED EV1
+ * @arg I2C_EVT_SLAVE_RECV_ADDR_MATCHED EV1
+ * @arg I2C_EVT_SLAVE_SEND_ADDR2_MATCHED EV1
+ * @arg I2C_EVT_SLAVE_RECV_ADDR2_MATCHED EV1
+ * @arg I2C_EVT_SLAVE_GCALLADDR_MATCHED EV1
+ * @arg I2C_EVT_SLAVE_DATA_RECVD EV2
+ * @arg (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_DUALFLAG) EV2
+ * @arg (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_GCALLADDR) EV2
+ * @arg I2C_EVT_SLAVE_DATA_SENDED EV3
+ * @arg (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_DUALFLAG) EV3
+ * @arg (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_GCALLADDR) EV3
+ * @arg I2C_EVT_SLAVE_ACK_MISS EV3_2
+ * @arg I2C_EVT_SLAVE_STOP_RECVD EV4
+ * @arg I2C_EVT_MASTER_MODE_FLAG EV5
+ * @arg I2C_EVT_MASTER_TXMODE_FLAG EV6
+ * @arg I2C_EVT_MASTER_RXMODE_FLAG EV6
+ * @arg I2C_EVT_MASTER_DATA_RECVD_FLAG EV7
+ * @arg I2C_EVT_MASTER_DATA_SENDING EV8
+ * @arg I2C_EVT_MASTER_DATA_SENDED EV8_2
+ * @arg I2C_EVT_MASTER_MODE_ADDRESS10_FLAG EV9
+ *
+ * @note: For detailed description of Events, please refer to section
+ * I2C_Events in n32wb452_i2c.h file.
+ *
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: Last event is equal to the I2C_EVENT
+ * - ERROR: Last event is different from the I2C_EVENT
+ */
+ErrorStatus I2C_CheckEvent(I2C_Module* I2Cx, uint32_t I2C_EVENT)
+{
+ uint32_t lastevent = 0;
+ uint32_t flag1 = 0, flag2 = 0;
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_EVT(I2C_EVENT));
+
+ /* Read the I2Cx status register */
+ flag1 = I2Cx->STS1;
+ flag2 = I2Cx->STS2;
+ flag2 = flag2 << 16;
+
+ /* Get the last event value from I2C status register */
+ lastevent = (flag1 | flag2) & FLAG_MASK;
+
+ /* Check whether the last event contains the I2C_EVENT */
+ if ((lastevent & I2C_EVENT) == I2C_EVENT)
+ {
+ /* SUCCESS: last event is equal to I2C_EVENT */
+ status = SUCCESS;
+ }
+ else
+ {
+ /* ERROR: last event is different from I2C_EVENT */
+ status = ERROR;
+ }
+ /* Return status */
+ return status;
+}
+
+/**
+ * @brief Returns the last I2Cx Event.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ *
+ * @note: For detailed description of Events, please refer to section
+ * I2C_Events in n32wb452_i2c.h file.
+ *
+ * @return The last event
+ */
+uint32_t I2C_GetLastEvent(I2C_Module* I2Cx)
+{
+ uint32_t lastevent = 0;
+ uint32_t flag1 = 0, flag2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+
+ /* Read the I2Cx status register */
+ flag1 = I2Cx->STS1;
+ flag2 = I2Cx->STS2;
+ flag2 = flag2 << 16;
+
+ /* Get the last event value from I2C status register */
+ lastevent = (flag1 | flag2) & FLAG_MASK;
+
+ /* Return status */
+ return lastevent;
+}
+
+/**
+ * @brief Checks whether the specified I2C flag is set or not.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_FLAG specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg I2C_FLAG_DUALFLAG Dual flag (Slave mode)
+ * @arg I2C_FLAG_SMBHADDR SMBus host header (Slave mode)
+ * @arg I2C_FLAG_SMBDADDR SMBus default header (Slave mode)
+ * @arg I2C_FLAG_GCALLADDR General call header flag (Slave mode)
+ * @arg I2C_FLAG_TRF Transmitter/Receiver flag
+ * @arg I2C_FLAG_BUSY Bus busy flag
+ * @arg I2C_FLAG_MSMODE Master/Slave flag
+ * @arg I2C_FLAG_SMBALERT SMBus Alert flag
+ * @arg I2C_FLAG_TIMOUT Timeout or Tlow error flag
+ * @arg I2C_FLAG_PECERR PEC error in reception flag
+ * @arg I2C_FLAG_OVERRUN Overrun/Underrun flag (Slave mode)
+ * @arg I2C_FLAG_ACKFAIL Acknowledge failure flag
+ * @arg I2C_FLAG_ARLOST Arbitration lost flag (Master mode)
+ * @arg I2C_FLAG_BUSERR Bus error flag
+ * @arg I2C_FLAG_TXDATE Data register empty flag (Transmitter)
+ * @arg I2C_FLAG_RXDATNE Data register not empty (Receiver) flag
+ * @arg I2C_FLAG_STOPF Stop detection flag (Slave mode)
+ * @arg I2C_FLAG_ADDR10F 10-bit header sent flag (Master mode)
+ * @arg I2C_FLAG_BYTEF Byte transfer finished flag
+ * @arg I2C_FLAG_ADDRF Address sent flag (Master mode) "ADSL"
+ * Address matched flag (Slave mode)"ENDA"
+ * @arg I2C_FLAG_STARTBF Start bit flag (Master mode)
+ * @return The new state of I2C_FLAG (SET or RESET).
+ */
+FlagStatus I2C_GetFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ __IO uint32_t i2creg = 0, i2cxbase = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
+
+ /* Get the I2Cx peripheral base address */
+ i2cxbase = (uint32_t)I2Cx;
+
+ /* Read flag register index */
+ i2creg = I2C_FLAG >> 28;
+
+ /* Get bit[23:0] of the flag */
+ I2C_FLAG &= FLAG_MASK;
+
+ if (i2creg != 0)
+ {
+ /* Get the I2Cx STS1 register address */
+ i2cxbase += 0x14;
+ }
+ else
+ {
+ /* Flag in I2Cx STS2 Register */
+ I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
+ /* Get the I2Cx STS2 register address */
+ i2cxbase += 0x18;
+ }
+
+ if (((*(__IO uint32_t*)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
+ {
+ /* I2C_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* I2C_FLAG is reset */
+ bitstatus = RESET;
+ }
+
+ /* Return the I2C_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the I2Cx's pending flags.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_FLAG specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_FLAG_SMBALERT SMBus Alert flag
+ * @arg I2C_FLAG_TIMOUT Timeout or Tlow error flag
+ * @arg I2C_FLAG_PECERR PEC error in reception flag
+ * @arg I2C_FLAG_OVERRUN Overrun/Underrun flag (Slave mode)
+ * @arg I2C_FLAG_ACKFAIL Acknowledge failure flag
+ * @arg I2C_FLAG_ARLOST Arbitration lost flag (Master mode)
+ * @arg I2C_FLAG_BUSERR Bus error flag
+ *
+ * @note
+ * - STOPF (STOP detection) is cleared by software sequence: a read operation
+ * to I2C_STS1 register (I2C_GetFlag()) followed by a write operation
+ * to I2C_CTRL1 register (I2C_Enable() to re-enable the I2C peripheral).
+ * - ADD10 (10-bit header sent) is cleared by software sequence: a read
+ * operation to I2C_STS1 (I2C_GetFlag()) followed by writing the
+ * second byte of the address in DAT register.
+ * - BTF (Byte Transfer Finished) is cleared by software sequence: a read
+ * operation to I2C_STS1 register (I2C_GetFlag()) followed by a
+ * read/write to I2C_DAT register (I2C_SendData()).
+ * - ADDR (Address sent) is cleared by software sequence: a read operation to
+ * I2C_STS1 register (I2C_GetFlag()) followed by a read operation to
+ * I2C_STS2 register ((void)(I2Cx->STS2)).
+ * - SB (Start Bit) is cleared software sequence: a read operation to I2C_STS1
+ * register (I2C_GetFlag()) followed by a write operation to I2C_DAT
+ * register (I2C_SendData()).
+ */
+void I2C_ClrFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG)
+{
+ uint32_t flagpos = 0;
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_CLR_FLAG(I2C_FLAG));
+ /* Get the I2C flag position */
+ flagpos = I2C_FLAG & FLAG_MASK;
+ /* Clear the selected I2C flag */
+ I2Cx->STS1 = (uint16_t)~flagpos;
+}
+
+/**
+ * @brief Checks whether the specified I2C interrupt has occurred or not.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT specifies the interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg I2C_INT_SMBALERT SMBus Alert flag
+ * @arg I2C_INT_TIMOUT Timeout or Tlow error flag
+ * @arg I2C_INT_PECERR PEC error in reception flag
+ * @arg I2C_INT_OVERRUN Overrun/Underrun flag (Slave mode)
+ * @arg I2C_INT_ACKFAIL Acknowledge failure flag
+ * @arg I2C_INT_ARLOST Arbitration lost flag (Master mode)
+ * @arg I2C_INT_BUSERR Bus error flag
+ * @arg I2C_INT_TXDATE Data register empty flag (Transmitter)
+ * @arg I2C_INT_RXDATNE Data register not empty (Receiver) flag
+ * @arg I2C_INT_STOPF Stop detection flag (Slave mode)
+ * @arg I2C_INT_ADDR10F 10-bit header sent flag (Master mode)
+ * @arg I2C_INT_BYTEF Byte transfer finished flag
+ * @arg I2C_INT_ADDRF Address sent flag (Master mode) "ADSL"
+ * Address matched flag (Slave mode)"ENDAD"
+ * @arg I2C_INT_STARTBF Start bit flag (Master mode)
+ * @return The new state of I2C_IT (SET or RESET).
+ */
+INTStatus I2C_GetIntStatus(I2C_Module* I2Cx, uint32_t I2C_IT)
+{
+ INTStatus bitstatus = RESET;
+ uint32_t enablestatus = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_GET_INT(I2C_IT));
+
+ /* Check if the interrupt source is enabled or not */
+ enablestatus = (uint32_t)(((I2C_IT & INTEN_MASK) >> 16) & (I2Cx->CTRL2));
+
+ /* Get bit[23:0] of the flag */
+ I2C_IT &= FLAG_MASK;
+
+ /* Check the status of the specified I2C flag */
+ if (((I2Cx->STS1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
+ {
+ /* I2C_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* I2C_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the I2C_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the I2Cx's interrupt pending bits.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_INT_SMBALERT SMBus Alert interrupt
+ * @arg I2C_INT_TIMOUT Timeout or Tlow error interrupt
+ * @arg I2C_INT_PECERR PEC error in reception interrupt
+ * @arg I2C_INT_OVERRUN Overrun/Underrun interrupt (Slave mode)
+ * @arg I2C_INT_ACKFAIL Acknowledge failure interrupt
+ * @arg I2C_INT_ARLOST Arbitration lost interrupt (Master mode)
+ * @arg I2C_INT_BUSERR Bus error interrupt
+ *
+ * @note
+ * - STOPF (STOP detection) is cleared by software sequence: a read operation
+ * to I2C_STS1 register (I2C_GetIntStatus()) followed by a write operation to
+ * I2C_CTRL1 register (I2C_Enable() to re-enable the I2C peripheral).
+ * - ADD10 (10-bit header sent) is cleared by software sequence: a read
+ * operation to I2C_STS1 (I2C_GetIntStatus()) followed by writing the second
+ * byte of the address in I2C_DAT register.
+ * - BTF (Byte Transfer Finished) is cleared by software sequence: a read
+ * operation to I2C_STS1 register (I2C_GetIntStatus()) followed by a
+ * read/write to I2C_DAT register (I2C_SendData()).
+ * - ADDR (Address sent) is cleared by software sequence: a read operation to
+ * I2C_STS1 register (I2C_GetIntStatus()) followed by a read operation to
+ * I2C_STS2 register ((void)(I2Cx->STS2)).
+ * - SB (Start Bit) is cleared by software sequence: a read operation to
+ * I2C_STS1 register (I2C_GetIntStatus()) followed by a write operation to
+ * I2C_DAT register (I2C_SendData()).
+ */
+void I2C_ClrIntPendingBit(I2C_Module* I2Cx, uint32_t I2C_IT)
+{
+ uint32_t flagpos = 0;
+ /* Check the parameters */
+ assert_param(IS_I2C_PERIPH(I2Cx));
+ assert_param(IS_I2C_CLR_INT(I2C_IT));
+ /* Get the I2C flag position */
+ flagpos = I2C_IT & FLAG_MASK;
+ /* Clear the selected I2C flag */
+ I2Cx->STS1 = (uint16_t)~flagpos;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_iwdg.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_iwdg.c
new file mode 100644
index 0000000000..e57630968b
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_iwdg.c
@@ -0,0 +1,193 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_iwdg.c
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32wb452_iwdg.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup IWDG
+ * @brief IWDG driver modules
+ * @{
+ */
+
+/** @addtogroup IWDG_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Private_Defines
+ * @{
+ */
+
+/* ---------------------- IWDG registers bit mask ----------------------------*/
+
+/* KEY register bit mask */
+#define KEY_ReloadKey ((uint16_t)0xAAAA)
+#define KEY_EnableKey ((uint16_t)0xCCCC)
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
+ * @param IWDG_WriteAccess new state of write access to IWDG_PR and IWDG_RLR registers.
+ * This parameter can be one of the following values:
+ * @arg IWDG_WRITE_ENABLE Enable write access to IWDG_PR and IWDG_RLR registers
+ * @arg IWDG_WRITE_DISABLE Disable write access to IWDG_PR and IWDG_RLR registers
+ */
+void IWDG_WriteConfig(uint16_t IWDG_WriteAccess)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_WRITE(IWDG_WriteAccess));
+ IWDG->KEY = IWDG_WriteAccess;
+}
+
+/**
+ * @brief Sets IWDG Prescaler value.
+ * @param IWDG_Prescaler specifies the IWDG Prescaler value.
+ * This parameter can be one of the following values:
+ * @arg IWDG_PRESCALER_DIV4 IWDG prescaler set to 4
+ * @arg IWDG_PRESCALER_DIV8 IWDG prescaler set to 8
+ * @arg IWDG_PRESCALER_DIV16 IWDG prescaler set to 16
+ * @arg IWDG_PRESCALER_DIV32 IWDG prescaler set to 32
+ * @arg IWDG_PRESCALER_DIV64 IWDG prescaler set to 64
+ * @arg IWDG_PRESCALER_DIV128 IWDG prescaler set to 128
+ * @arg IWDG_PRESCALER_DIV256 IWDG prescaler set to 256
+ */
+void IWDG_SetPrescalerDiv(uint8_t IWDG_Prescaler)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_PRESCALER_DIV(IWDG_Prescaler));
+ IWDG->PREDIV = IWDG_Prescaler;
+}
+
+/**
+ * @brief Sets IWDG Reload value.
+ * @param Reload specifies the IWDG Reload value.
+ * This parameter must be a number between 0 and 0x0FFF.
+ */
+void IWDG_CntReload(uint16_t Reload)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_RELOAD(Reload));
+ IWDG->RELV = Reload;
+}
+
+/**
+ * @brief Reloads IWDG counter with value defined in the reload register
+ * (write access to IWDG_PR and IWDG_RLR registers disabled).
+ */
+void IWDG_ReloadKey(void)
+{
+ IWDG->KEY = KEY_ReloadKey;
+}
+
+/**
+ * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
+ */
+void IWDG_Enable(void)
+{
+ IWDG->KEY = KEY_EnableKey;
+}
+
+/**
+ * @brief Checks whether the specified IWDG flag is set or not.
+ * @param IWDG_FLAG specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg IWDG_PVU_FLAG Prescaler Value Update on going
+ * @arg IWDG_CRVU_FLAG Reload Value Update on going
+ * @return The new state of IWDG_FLAG (SET or RESET).
+ */
+FlagStatus IWDG_GetStatus(uint16_t IWDG_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_IWDG_FLAG(IWDG_FLAG));
+ if ((IWDG->STS & IWDG_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_pwr.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_pwr.c
new file mode 100644
index 0000000000..bfe9e00dc9
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_pwr.c
@@ -0,0 +1,399 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_pwr.c
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32wb452_pwr.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup PWR
+ * @brief PWR driver modules
+ * @{
+ */
+
+/** @addtogroup PWR_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Private_Defines
+ * @{
+ */
+
+/* --------- PWR registers bit address in the alias region ---------- */
+#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
+
+/* --- CTRL Register ---*/
+
+/* Alias word address of DBKP bit */
+#define CTRL_OFFSET (PWR_OFFSET + 0x00)
+#define DBKP_BITN 0x08
+#define CTRL_DBKP_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (DBKP_BITN * 4))
+
+/* Alias word address of PVDEN bit */
+#define PVDEN_BITN 0x04
+#define CTRL_PVDEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (PVDEN_BITN * 4))
+
+/* --- CTRLSTS Register ---*/
+
+/* Alias word address of WKUPEN bit */
+#define CTRLSTS_OFFSET (PWR_OFFSET + 0x04)
+#define WKUPEN_BITN 0x08
+#define CTRLSTS_WKUPEN_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (WKUPEN_BITN * 4))
+
+/* ------------------ PWR registers bit mask ------------------------ */
+
+/* CTRL register bit mask */
+#define CTRL_DS_MASK ((uint32_t)0xFFFFFFFC)
+#define CTRL_PRS_MASK ((uint32_t)0xFFFFFD1F)
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the PWR peripheral registers to their default reset values.
+ */
+void PWR_DeInit(void)
+{
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_PWR, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_PWR, DISABLE);
+}
+
+/**
+ * @brief Enables or disables access to the RTC and backup registers.
+ * @param Cmd new state of the access to the RTC and backup registers.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void PWR_BackupAccessEnable(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)CTRL_DBKP_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Enables or disables the Power Voltage Detector(PVD).
+ * @param Cmd new state of the PVD.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void PWR_PvdEnable(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)CTRL_PVDEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+ * @param PWR_PVDLevel specifies the PVD detection level
+ * This parameter can be one of the following values:
+ * @arg PWR_PVDRANGRE_2V2 PVD detection level set to 2.2V
+ * @arg PWR_PVDRANGRE_2V3 PVD detection level set to 2.3V
+ * @arg PWR_PVDRANGRE_2V4 PVD detection level set to 2.4V
+ * @arg PWR_PVDRANGRE_2V5 PVD detection level set to 2.5V
+ * @arg PWR_PVDRANGRE_2V6 PVD detection level set to 2.6V
+ * @arg PWR_PVDRANGRE_2V7 PVD detection level set to 2.7V
+ * @arg PWR_PVDRANGRE_2V8 PVD detection level set to 2.8V
+ * @arg PWR_PVDRANGRE_2V9 PVD detection level set to 2.9V
+ */
+void PWR_PvdRangeConfig(uint32_t PWR_PVDLevel)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
+ tmpregister = PWR->CTRL;
+ /* Clear PRS[7:5] bits */
+ tmpregister &= CTRL_PRS_MASK;
+ /* Set PRS[7:5] bits according to PWR_PVDLevel value */
+ tmpregister |= PWR_PVDLevel;
+ /* Store the new value */
+ PWR->CTRL = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the WakeUp Pin functionality.
+ * @param Cmd new state of the WakeUp Pin functionality.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void PWR_WakeUpPinEnable(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)CTRLSTS_WKUPEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Enters SLEEP mode.
+ * @param SLEEPONEXIT specifies the SLEEPONEXIT state in SLEEP mode.
+ * This parameter can be one of the following values:
+ * @arg 0 SLEEP mode with SLEEPONEXIT disable
+ * @arg 1 SLEEP mode with SLEEPONEXIT enable
+ * @param PWR_STOPEntry specifies if SLEEP mode in entered with WFI or WFE instruction.
+ * This parameter can be one of the following values:
+ * @arg PWR_STOPENTRY_WFI enter SLEEP mode with WFI instruction
+ * @arg PWR_STOPENTRY_WFE enter SLEEP mode with WFE instruction
+ */
+void PWR_EnterSLEEPMode(uint8_t SLEEPONEXIT, uint8_t PWR_STOPEntry)
+{
+ // uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
+
+ /* CLEAR SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR &= (uint32_t) ~((uint32_t)SCB_SCR_SLEEPDEEP);
+
+ /* Select SLEEPONEXIT mode entry --------------------------------------------------*/
+ if (SLEEPONEXIT == 1)
+ {
+ /* the MCU enters Sleep mode as soon as it exits the lowest priority INTSTS */
+ SCB->SCR |= SCB_SCR_SLEEPONEXIT;
+ }
+ else if (SLEEPONEXIT == 0)
+ {
+ /* Sleep-now */
+ SCB->SCR &= (uint32_t) ~((uint32_t)SCB_SCR_SLEEPONEXIT);
+ }
+
+ /* Select SLEEP mode entry --------------------------------------------------*/
+ if (PWR_STOPEntry == PWR_STOPENTRY_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+}
+
+/**
+ * @brief Enters STOP mode.
+ * @param PWR_Regulator specifies the regulator state in STOP mode.
+ * This parameter can be one of the following values:
+ * @arg PWR_REGULATOR_ON STOP mode with regulator ON
+ * @arg PWR_REGULATOR_LOWPOWER STOP mode with regulator in low power mode
+ * @param PWR_STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
+ * This parameter can be one of the following values:
+ * @arg PWR_STOPENTRY_WFI enter STOP mode with WFI instruction
+ * @arg PWR_STOPENTRY_WFE enter STOP mode with WFE instruction
+ */
+void PWR_EnterStopState(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_PWR_REGULATOR(PWR_Regulator));
+ assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
+
+ /* Select the regulator state in STOP mode ---------------------------------*/
+ tmpregister = PWR->CTRL;
+ /* Clear PDS and LPS bits */
+ tmpregister &= CTRL_DS_MASK;
+ /* Set LPS bit according to PWR_Regulator value */
+ tmpregister |= PWR_Regulator;
+ /* Store the new value */
+ PWR->CTRL = tmpregister;
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP;
+
+ /* Select STOP mode entry --------------------------------------------------*/
+ if (PWR_STOPEntry == PWR_STOPENTRY_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR &= (uint32_t) ~((uint32_t)SCB_SCR_SLEEPDEEP);
+}
+
+/**
+ * @brief Enters STOP2 mode.
+ * @param PWR_STOPEntry specifies if STOP2 mode in entered with WFI or WFE instruction.
+ * This parameter can be one of the following values:
+ * @arg PWR_STOPENTRY_WFI enter STOP2 mode with WFI instruction
+ * @arg PWR_STOPENTRY_WFE enter STOP2 mode with WFE instruction
+ */
+void PWR_EnterSTOP2Mode(uint8_t PWR_STOPEntry)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
+
+ /* Select the regulator state in STOP2 mode ---------------------------------*/
+ tmpregister = PWR->CTRL;
+ /* Clear PDS and LPS bits */
+ tmpregister &= CTRL_DS_MASK;
+ /* Store the new value */
+ PWR->CTRL = tmpregister;
+ /*STOP2 sleep mode control-stop2s*/
+ PWR->CTRL2 |= PWR_CTRL2_STOP2S;
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP;
+ // PWR_CTRL2.BIT0 STOP2S need?
+ /* Select STOP mode entry --------------------------------------------------*/
+ if (PWR_STOPEntry == PWR_STOPENTRY_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR &= (uint32_t) ~((uint32_t)SCB_SCR_SLEEPDEEP);
+}
+
+/**
+ * @brief Enters STANDBY mode.
+ */
+void PWR_EnterStandbyState(void)
+{
+ /* Clear Wake-up flag */
+ PWR->CTRL |= PWR_CTRL_CWKUP;
+ /* Clear PDS and LPS bits */
+ PWR->CTRL &= CTRL_DS_MASK;
+ /* Select STANDBY mode */
+ PWR->CTRL |= PWR_CTRL_PDS;
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP;
+/* This option is used to ensure that store operations are completed */
+#if defined(__CC_ARM)
+ __force_stores();
+#endif
+ /* Request Wait For Interrupt */
+ __WFI();
+}
+
+/**
+ * @brief Checks whether the specified PWR flag is set or not.
+ * @param PWR_FLAG specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg PWR_WU_FLAG Wake Up flag
+ * @arg PWR_SB_FLAG StandBy flag
+ * @arg PWR_PVDO_FLAG PVD Output
+ * @arg PWR_VBATF_FLAG VBAT flag
+ * @return The new state of PWR_FLAG (SET or RESET).
+ */
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
+
+ if ((PWR->CTRLSTS & PWR_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the PWR's pending flags.
+ * @param PWR_FLAG specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg PWR_WU_FLAG Wake Up flag
+ * @arg PWR_SB_FLAG StandBy and VBAT flag
+ */
+void PWR_ClearFlag(uint32_t PWR_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
+
+ PWR->CTRL |= PWR_FLAG << 2;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_rcc.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_rcc.c
new file mode 100644
index 0000000000..6be2d4a82b
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_rcc.c
@@ -0,0 +1,1435 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_rcc.c
+ * @author Nations
+ * @version v1.0.3
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32wb452_rcc.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RCC
+ * @brief RCC driver modules
+ * @{
+ */
+
+/** @addtogroup RCC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_Defines
+ * @{
+ */
+
+/* ------------ RCC registers bit address in the alias region ----------- */
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
+
+/* --- CTRL Register ---*/
+
+/* Alias word address of HSIEN bit */
+#define CTRL_OFFSET (RCC_OFFSET + 0x00)
+#define HSIEN_BITN 0x00
+#define CTRL_HSIEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (HSIEN_BITN * 4))
+
+/* Alias word address of PLLEN bit */
+#define PLLEN_BITN 0x18
+#define CTRL_PLLEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (PLLEN_BITN * 4))
+
+/* Alias word address of CLKSSEN bit */
+#define CLKSSEN_BITN 0x13
+#define CTRL_CLKSSEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (CLKSSEN_BITN * 4))
+
+/* --- CFG Register ---*/
+
+/* Alias word address of USBPRES bit */
+#define CFG_OFFSET (RCC_OFFSET + 0x04)
+
+#define USBPRES_BITN 0x16
+#define CFG_USBPRES_BB (PERIPH_BB_BASE + (CFG_OFFSET * 32) + (USBPRES_BITN * 4))
+
+#define USBPRE_Bit1Number 0x17
+#define CFGR_USBPRE_BB_BIT1 (PERIPH_BB_BASE + (CFG_OFFSET * 32) + (USBPRE_Bit1Number * 4))
+
+/* --- BDCTRL Register ---*/
+
+/* Alias word address of RTCEN bit */
+#define BDCTRL_OFFSET (RCC_OFFSET + 0x20)
+#define RTCEN_BITN 0x0F
+#define BDCTRL_RTCEN_BB (PERIPH_BB_BASE + (BDCTRL_OFFSET * 32) + (RTCEN_BITN * 4))
+
+/* Alias word address of BDSFTRST bit */
+#define BDSFTRST_BITN 0x10
+#define BDCTRL_BDSFTRST_BB (PERIPH_BB_BASE + (BDCTRL_OFFSET * 32) + (BDSFTRST_BITN * 4))
+
+/* --- CTRLSTS Register ---*/
+
+/* Alias word address of LSIEN bit */
+#define CTRLSTS_OFFSET (RCC_OFFSET + 0x24)
+#define LSIEN_BITNUMBER 0x00
+#define CTRLSTS_LSIEN_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (LSIEN_BITNUMBER * 4))
+
+/* ---------------------- RCC registers bit mask ------------------------ */
+
+/* CTRL register bit mask */
+#define CTRL_HSEBP_RESET ((uint32_t)0xFFFBFFFF)
+#define CTRL_HSEBP_SET ((uint32_t)0x00040000)
+#define CTRL_HSEEN_RESET ((uint32_t)0xFFFEFFFF)
+#define CTRL_HSEEN_SET ((uint32_t)0x00010000)
+#define CTRL_HSITRIM_MASK ((uint32_t)0xFFFFFF07)
+
+/* CFG register bit mask */
+#define CFG_PLL_MASK ((uint32_t)0xF7C0FFFF)
+
+#define CFG_PLLMULFCT_MASK ((uint32_t)0x083C0000)
+#define CFG_PLLSRC_MASK ((uint32_t)0x00010000)
+#define CFG_PLLHSEPRES_MASK ((uint32_t)0x00020000)
+#define CFG_SCLKSTS_MASK ((uint32_t)0x0000000C)
+#define CFG_SCLKSW_MASK ((uint32_t)0xFFFFFFFC)
+#define CFG_AHBPRES_RESET_MASK ((uint32_t)0xFFFFFF0F)
+#define CFG_AHBPRES_SET_MASK ((uint32_t)0x000000F0)
+#define CFG_APB1PRES_RESET_MASK ((uint32_t)0xFFFFF8FF)
+#define CFG_APB1PRES_SET_MASK ((uint32_t)0x00000700)
+#define CFG_APB2PRES_RESET_MASK ((uint32_t)0xFFFFC7FF)
+#define CFG_APB2PRES_SET_MASK ((uint32_t)0x00003800)
+
+/* CFG2 register bit mask */
+#define CFG2_TIM18CLKSEL_SET_MASK ((uint32_t)0x20000000)
+#define CFG2_TIM18CLKSEL_RESET_MASK ((uint32_t)0xDFFFFFFF)
+#define CFG2_RNGCPRES_SET_MASK ((uint32_t)0x1F000000)
+#define CFG2_RNGCPRES_RESET_MASK ((uint32_t)0xE0FFFFFF)
+#define CFG2_ADC1MSEL_SET_MASK ((uint32_t)0x00000400)
+#define CFG2_ADC1MSEL_RESET_MASK ((uint32_t)0xFFFFFBFF)
+#define CFG2_ADC1MPRES_SET_MASK ((uint32_t)0x0000F800)
+#define CFG2_ADC1MPRES_RESET_MASK ((uint32_t)0xFFFF07FF)
+#define CFG2_ADCPLLPRES_SET_MASK ((uint32_t)0x000001F0)
+#define CFG2_ADCPLLPRES_RESET_MASK ((uint32_t)0xFFFFFE0F)
+#define CFG2_ADCHPRES_SET_MASK ((uint32_t)0x0000000F)
+#define CFG2_ADCHPRES_RESET_MASK ((uint32_t)0xFFFFFFF0)
+
+/* CFG3 register bit mask */
+#define CFGR3_TRNG1MSEL_SET_MASK ((uint32_t)0x00020000)
+#define CFGR3_TRNG1MSEL_RESET_MASK ((uint32_t)0xFFFDFFFF)
+#define CFGR3_TRNG1MPRES_SET_MASK ((uint32_t)0x0000F800)
+#define CFGR3_TRNG1MPRES_RESET_MASK ((uint32_t)0xFFFF07FF)
+
+/* CTRLSTS register bit mask */
+#define CSR_RMRSTF_SET ((uint32_t)0x01000000)
+#define CSR_RMVF_Reset ((uint32_t)0xfeffffff)
+
+/* RCC Flag Mask */
+#define FLAG_MASK ((uint8_t)0x1F)
+
+/* CLKINT register byte 2 (Bits[15:8]) base address */
+#define CLKINT_BYTE2_ADDR ((uint32_t)0x40021009)
+
+/* CLKINT register byte 3 (Bits[23:16]) base address */
+#define CLKINT_BYTE3_ADDR ((uint32_t)0x4002100A)
+
+/* CFG register byte 4 (Bits[31:24]) base address */
+#define CFG_BYTE4_ADDR ((uint32_t)0x40021007)
+
+/* BDCTRL register base address */
+#define BDCTRL_ADDR (PERIPH_BASE + BDCTRL_OFFSET)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_Variables
+ * @{
+ */
+
+static const uint8_t s_ApbAhbPresTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+static const uint8_t s_AdcHclkPresTable[16] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 32, 32, 32, 32, 32, 32, 32};
+static const uint16_t s_AdcPllClkPresTable[16] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256, 256, 256, 256, 256};
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Resets the RCC clock configuration to the default reset state.
+ */
+void RCC_DeInit(void)
+{
+ /* Set HSIEN bit */
+ RCC->CTRL |= (uint32_t)0x00000001;
+
+ /* Reset SW, HPRE, PPRE1, PPRE2 and MCO bits */
+ RCC->CFG &= (uint32_t)0xF8FFC000;
+
+ /* Reset HSEON, CLKSSEN and PLLEN bits */
+ RCC->CTRL &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CTRL &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRES/OTGFSPRE bits */
+ RCC->CFG &= (uint32_t)0xF700FFFF;
+
+ /* Reset CFG2 register */
+ RCC->CFG2 = 0x00003800;
+
+ /* Reset CFG3 register */
+ RCC->CFG3 = 0x00003840;
+
+ /* Disable all interrupts and clear pending bits */
+ RCC->CLKINT = 0x009F0000;
+}
+
+/**
+ * @brief Configures the External High Speed oscillator (HSE).
+ * @note HSE can not be stopped if it is used directly or through the PLL as system clock.
+ * @param RCC_HSE specifies the new state of the HSE.
+ * This parameter can be one of the following values:
+ * @arg RC_HSE_DISABLE HSE oscillator OFF
+ * @arg RCC_HSE_ENABLE HSE oscillator ON
+ * @arg RCC_HSE_BYPASS HSE oscillator bypassed with external clock
+ */
+void RCC_ConfigHse(uint32_t RCC_HSE)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_HSE(RCC_HSE));
+ /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
+ /* Reset HSEON bit */
+ RCC->CTRL &= CTRL_HSEEN_RESET;
+ /* Reset HSEBYP bit */
+ RCC->CTRL &= CTRL_HSEBP_RESET;
+ /* Configure HSE (RC_HSE_DISABLE is already covered by the code section above) */
+ switch (RCC_HSE)
+ {
+ case RCC_HSE_ENABLE:
+ /* Set HSEON bit */
+ RCC->CTRL |= CTRL_HSEEN_SET;
+ break;
+
+ case RCC_HSE_BYPASS:
+ /* Set HSEBYP and HSEON bits */
+ RCC->CTRL |= CTRL_HSEBP_SET | CTRL_HSEEN_SET;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Waits for HSE start-up.
+ * @return An ErrorStatus enumuration value:
+ * - SUCCESS: HSE oscillator is stable and ready to use
+ * - ERROR: HSE oscillator not yet ready
+ */
+ErrorStatus RCC_WaitHseStable(void)
+{
+ __IO uint32_t StartUpCounter = 0;
+ ErrorStatus status = ERROR;
+ FlagStatus HSEStatus = RESET;
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERD);
+ StartUpCounter++;
+ } while ((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
+
+ if (RCC_GetFlagStatus(RCC_FLAG_HSERD) != RESET)
+ {
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+ return (status);
+}
+
+/**
+ * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
+ * @param HSICalibrationValue specifies the calibration trimming value.
+ * This parameter must be a number between 0 and 0x1F.
+ */
+void RCC_SetHsiCalibValue(uint8_t HSICalibrationValue)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_CALIB_VALUE(HSICalibrationValue));
+ tmpregister = RCC->CTRL;
+ /* Clear HSITRIM[4:0] bits */
+ tmpregister &= CTRL_HSITRIM_MASK;
+ /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
+ tmpregister |= (uint32_t)HSICalibrationValue << 3;
+ /* Store the new value */
+ RCC->CTRL = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the Internal High Speed oscillator (HSI).
+ * @note HSI can not be stopped if it is used directly or through the PLL as system clock.
+ * @param Cmd new state of the HSI. This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableHsi(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)CTRL_HSIEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Configures the PLL clock source and multiplication factor.
+ * @note This function must be used only when the PLL is disabled.
+ * @param RCC_PLLSource specifies the PLL entry clock source.
+ * this parameter can be one of the following values:
+ * @arg RCC_PLL_SRC_HSI_DIV2 HSI oscillator clock divided by 2 selected as PLL clock entry
+ * @arg RCC_PLL_SRC_HSE_DIV1 HSE oscillator clock selected as PLL clock entry
+ * @arg RCC_PLL_SRC_HSE_DIV2 HSE oscillator clock divided by 2 selected as PLL clock entry
+ * @param RCC_PLLMul specifies the PLL multiplication factor.
+ * this parameter can be RCC_PLLMul_x where x:[2,32]
+ */
+void RCC_ConfigPll(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL_SRC(RCC_PLLSource));
+ assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
+
+ tmpregister = RCC->CFG;
+ /* Clear PLLSRC, PLLXTPRE and PLLMUL[4:0] bits */
+ tmpregister &= CFG_PLL_MASK;
+ /* Set the PLL configuration bits */
+ tmpregister |= RCC_PLLSource | RCC_PLLMul;
+ /* Store the new value */
+ RCC->CFG = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the PLL.
+ * @note The PLL can not be disabled if it is used as system clock.
+ * @param Cmd new state of the PLL. This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnablePll(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ *(__IO uint32_t*)CTRL_PLLEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Configures the system clock (SYSCLK).
+ * @param RCC_SYSCLKSource specifies the clock source used as system clock.
+ * This parameter can be one of the following values:
+ * @arg RCC_SYSCLK_SRC_HSI HSI selected as system clock
+ * @arg RCC_SYSCLK_SRC_HSE HSE selected as system clock
+ * @arg RCC_SYSCLK_SRC_PLLCLK PLL selected as system clock
+ */
+void RCC_ConfigSysclk(uint32_t RCC_SYSCLKSource)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_SYSCLK_SRC(RCC_SYSCLKSource));
+ tmpregister = RCC->CFG;
+ /* Clear SW[1:0] bits */
+ tmpregister &= CFG_SCLKSW_MASK;
+ /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
+ tmpregister |= RCC_SYSCLKSource;
+ /* Store the new value */
+ RCC->CFG = tmpregister;
+}
+
+/**
+ * @brief Returns the clock source used as system clock.
+ * @return The clock source used as system clock. The returned value can
+ * be one of the following:
+ * - 0x00: HSI used as system clock
+ * - 0x04: HSE used as system clock
+ * - 0x08: PLL used as system clock
+ */
+uint8_t RCC_GetSysclkSrc(void)
+{
+ return ((uint8_t)(RCC->CFG & CFG_SCLKSTS_MASK));
+}
+
+/**
+ * @brief Configures the AHB clock (HCLK).
+ * @param RCC_SYSCLK defines the AHB clock divider. This clock is derived from
+ * the system clock (SYSCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_SYSCLK_DIV1 AHB clock = SYSCLK
+ * @arg RCC_SYSCLK_DIV2 AHB clock = SYSCLK/2
+ * @arg RCC_SYSCLK_DIV4 AHB clock = SYSCLK/4
+ * @arg RCC_SYSCLK_DIV8 AHB clock = SYSCLK/8
+ * @arg RCC_SYSCLK_DIV16 AHB clock = SYSCLK/16
+ * @arg RCC_SYSCLK_DIV64 AHB clock = SYSCLK/64
+ * @arg RCC_SYSCLK_DIV128 AHB clock = SYSCLK/128
+ * @arg RCC_SYSCLK_DIV256 AHB clock = SYSCLK/256
+ * @arg RCC_SYSCLK_DIV512 AHB clock = SYSCLK/512
+ */
+void RCC_ConfigHclk(uint32_t RCC_SYSCLK)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_SYSCLK_DIV(RCC_SYSCLK));
+ tmpregister = RCC->CFG;
+ /* Clear HPRE[3:0] bits */
+ tmpregister &= CFG_AHBPRES_RESET_MASK;
+ /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
+ tmpregister |= RCC_SYSCLK;
+ /* Store the new value */
+ RCC->CFG = tmpregister;
+}
+
+/**
+ * @brief Configures the Low Speed APB clock (PCLK1).
+ * @param RCC_HCLK defines the APB1 clock divider. This clock is derived from
+ * the AHB clock (HCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_HCLK_DIV1 APB1 clock = HCLK
+ * @arg RCC_HCLK_DIV2 APB1 clock = HCLK/2
+ * @arg RCC_HCLK_DIV4 APB1 clock = HCLK/4
+ * @arg RCC_HCLK_DIV8 APB1 clock = HCLK/8
+ * @arg RCC_HCLK_DIV16 APB1 clock = HCLK/16
+ */
+void RCC_ConfigPclk1(uint32_t RCC_HCLK)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_HCLK_DIV(RCC_HCLK));
+ tmpregister = RCC->CFG;
+ /* Clear PPRE1[2:0] bits */
+ tmpregister &= CFG_APB1PRES_RESET_MASK;
+ /* Set PPRE1[2:0] bits according to RCC_HCLK value */
+ tmpregister |= RCC_HCLK;
+ /* Store the new value */
+ RCC->CFG = tmpregister;
+}
+
+/**
+ * @brief Configures the High Speed APB clock (PCLK2).
+ * @param RCC_HCLK defines the APB2 clock divider. This clock is derived from
+ * the AHB clock (HCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_HCLK_DIV1 APB2 clock = HCLK
+ * @arg RCC_HCLK_DIV2 APB2 clock = HCLK/2
+ * @arg RCC_HCLK_DIV4 APB2 clock = HCLK/4
+ * @arg RCC_HCLK_DIV8 APB2 clock = HCLK/8
+ * @arg RCC_HCLK_DIV16 APB2 clock = HCLK/16
+ */
+void RCC_ConfigPclk2(uint32_t RCC_HCLK)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_HCLK_DIV(RCC_HCLK));
+ tmpregister = RCC->CFG;
+ /* Clear PPRE2[2:0] bits */
+ tmpregister &= CFG_APB2PRES_RESET_MASK;
+ /* Set PPRE2[2:0] bits according to RCC_HCLK value */
+ tmpregister |= RCC_HCLK << 3;
+ /* Store the new value */
+ RCC->CFG = tmpregister;
+}
+
+/**
+ * @brief Enables or disables the specified RCC interrupts.
+ * @param RccInt specifies the RCC interrupt sources to be enabled or disabled.
+ *
+ * this parameter can be any combination of the following values
+ * @arg RCC_INT_LSIRDIF LSI ready interrupt
+ * @arg RCC_INT_LSERDIF LSE ready interrupt
+ * @arg RCC_INT_HSIRDIF HSI ready interrupt
+ * @arg RCC_INT_HSERDIF HSE ready interrupt
+ * @arg RCC_INT_PLLRDIF PLL ready interrupt
+ *
+ * @param Cmd new state of the specified RCC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_ConfigInt(uint8_t RccInt, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_INT(RccInt));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Perform Byte access to RCC_CLKINT bits to enable the selected interrupts */
+ *(__IO uint8_t*)CLKINT_BYTE2_ADDR |= RccInt;
+ }
+ else
+ {
+ /* Perform Byte access to RCC_CLKINT bits to disable the selected interrupts */
+ *(__IO uint8_t*)CLKINT_BYTE2_ADDR &= (uint8_t)~RccInt;
+ }
+}
+
+/**
+ * @brief Configures the USB clock (USBCLK).
+ * @param RCC_USBCLKSource specifies the USB clock source. This clock is
+ * derived from the PLL output.
+ * This parameter can be one of the following values:
+ * @arg RCC_USBCLK_SRC_PLLCLK_DIV1_5 PLL clock divided by 1,5 selected as USB clock source
+ * @arg RCC_USBCLK_SRC_PLLCLK_DIV1 PLL clock selected as USB clock source
+ * @arg RCC_USBCLK_SRC_PLLCLK_DIV2 PLL clock divided by 2 selected as USB clock source
+ * @arg RCC_USBCLK_SRC_PLLCLK_DIV3 PLL clock divided by 3 selected as USB clock source
+ */
+void RCC_ConfigUsbClk(uint32_t RCC_USBCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_USBCLK_SRC(RCC_USBCLKSource));
+
+ *(__IO uint32_t*)CFG_USBPRES_BB = RCC_USBCLKSource;
+ *(__IO uint32_t*)CFGR_USBPRE_BB_BIT1 = RCC_USBCLKSource >> 1;
+}
+
+/**
+ * @brief Configures the TIM1/8 clock (TIM1/8CLK).
+ * @param RCC_TIM18CLKSource specifies the TIM1/8 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_TIM18CLK_SRC_TIM18CLK
+ * @arg RCC_TIM18CLKSource_AHBCLK
+ */
+void RCC_ConfigTim18Clk(uint32_t RCC_TIM18CLKSource)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_TIM18CLKSRC(RCC_TIM18CLKSource));
+
+ tmpregister = RCC->CFG2;
+ /* Clear TIMCLK_SEL bits */
+ tmpregister &= CFG2_TIM18CLKSEL_RESET_MASK;
+ /* Set TIMCLK_SEL bits according to RCC_TIM18CLKSource value */
+ tmpregister |= RCC_TIM18CLKSource;
+
+ /* Store the new value */
+ RCC->CFG2 = tmpregister;
+}
+
+/**
+ * @brief Configures the RNGCCLK prescaler.
+ * @param RCC_RNGCCLKPrescaler specifies the RNGCCLK prescaler.
+ * This parameter can be one of the following values:
+ * @arg RCC_RNGCCLK_SYSCLK_DIV1 RNGCPRE[24:28] = 00000, SYSCLK Divided By 1
+ * @arg RCC_RNGCCLK_SYSCLK_DIV2 RNGCPRE[24:28] = 00001, SYSCLK Divided By 2
+ * @arg RCC_RNGCCLK_SYSCLK_DIV3 RNGCPRE[24:28] = 00002, SYSCLK Divided By 3
+ * ...
+ * @arg RCC_RNGCCLK_SYSCLK_DIV31 RNGCPRE[24:28] = 11110, SYSCLK Divided By 31
+ * @arg RCC_RNGCCLK_SYSCLK_DIV32 RNGCPRE[24:28] = 11111, SYSCLK Divided By 32
+ */
+void RCC_ConfigRngcClk(uint32_t RCC_RNGCCLKPrescaler)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_RNGCCLKPRE(RCC_RNGCCLKPrescaler));
+
+ tmpregister = RCC->CFG2;
+ /* Clear RNGCPRE[3:0] bits */
+ tmpregister &= CFG2_RNGCPRES_RESET_MASK;
+ /* Set RNGCPRE[3:0] bits according to RCC_RNGCCLKPrescaler value */
+ tmpregister |= RCC_RNGCCLKPrescaler;
+
+ /* Store the new value */
+ RCC->CFG2 = tmpregister;
+}
+
+/**
+ * @brief Configures the ADCx 1M clock (ADC1MCLK).
+ * @param RCC_ADC1MCLKSource specifies the ADC1M clock source.
+ * This parameter can be on of the following values:
+ * @arg RCC_ADC1MCLK_SRC_HSI
+ * @arg RCC_ADC1MCLK_SRC_HSE
+ *
+ * @param RCC_ADC1MPrescaler specifies the ADC1M clock prescaler.
+ * This parameter can be on of the following values:
+ * @arg RCC_ADC1MCLK_DIV1 ADC1M clock = RCC_ADC1MCLKSource_xxx/1
+ * @arg RCC_ADC1MCLK_DIV2 ADC1M clock = RCC_ADC1MCLKSource_xxx/2
+ * @arg RCC_ADC1MCLK_DIV3 ADC1M clock = RCC_ADC1MCLKSource_xxx/3
+ * ...
+ * @arg RCC_ADC1MCLK_DIV31 ADC1M clock = RCC_ADC1MCLKSource_xxx/31
+ * @arg RCC_ADC1MCLK_DIV32 ADC1M clock = RCC_ADC1MCLKSource_xxx/32
+ */
+void RCC_ConfigAdc1mClk(uint32_t RCC_ADC1MCLKSource, uint32_t RCC_ADC1MPrescaler)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_ADC1MCLKSRC(RCC_ADC1MCLKSource));
+ assert_param(IS_RCC_ADC1MCLKPRE(RCC_ADC1MPrescaler));
+
+ tmpregister = RCC->CFG2;
+ /* Clear ADC1MSEL and ADC1MPRE[4:0] bits */
+ tmpregister &= CFG2_ADC1MSEL_RESET_MASK;
+ tmpregister &= CFG2_ADC1MPRES_RESET_MASK;
+ /* Set ADC1MSEL bits according to RCC_ADC1MCLKSource value */
+ tmpregister |= RCC_ADC1MCLKSource;
+ /* Set ADC1MPRE[4:0] bits according to RCC_ADC1MPrescaler value */
+ tmpregister |= RCC_ADC1MPrescaler;
+
+ /* Store the new value */
+ RCC->CFG2 = tmpregister;
+}
+
+/**
+ * @brief Configures the ADCPLLCLK prescaler, and enable/disable ADCPLLCLK.
+ * @param RCC_ADCPLLCLKPrescaler specifies the ADCPLLCLK prescaler.
+ * This parameter can be on of the following values:
+ * @arg RCC_ADCPLLCLK_DISABLE ADCPLLCLKPRES[4:0] = 0xxxx, ADC Pll Clock Disable
+ * @arg RCC_ADCPLLCLK_DIV1 ADCPLLCLKPRES[4:0] = 10000, Pll Clock Divided By 1
+ * @arg RCC_ADCPLLCLK_DIV2 ADCPLLCLKPRES[4:0] = 10001, Pll Clock Divided By 2
+ * @arg RCC_ADCPLLCLK_DIV4 ADCPLLCLKPRES[4:0] = 10010, Pll Clock Divided By 4
+ * @arg RCC_ADCPLLCLK_DIV6 ADCPLLCLKPRES[4:0] = 10011, Pll Clock Divided By 6
+ * @arg RCC_ADCPLLCLK_DIV8 ADCPLLCLKPRES[4:0] = 10100, Pll Clock Divided By 8
+ * @arg RCC_ADCPLLCLK_DIV10 ADCPLLCLKPRES[4:0] = 10101, Pll Clock Divided By 10
+ * @arg RCC_ADCPLLCLK_DIV12 ADCPLLCLKPRES[4:0] = 10110, Pll Clock Divided By 12
+ * @arg RCC_ADCPLLCLK_DIV16 ADCPLLCLKPRES[4:0] = 10111, Pll Clock Divided By 16
+ * @arg RCC_ADCPLLCLK_DIV32 ADCPLLCLKPRES[4:0] = 11000, Pll Clock Divided By 32
+ * @arg RCC_ADCPLLCLK_DIV64 ADCPLLCLKPRES[4:0] = 11001, Pll Clock Divided By 64
+ * @arg RCC_ADCPLLCLK_DIV128 ADCPLLCLKPRES[4:0] = 11010, Pll Clock Divided By 128
+ * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = 11011, Pll Clock Divided By 256
+ * @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = others, Pll Clock Divided By 256
+ *
+ * @param Cmd specifies the ADCPLLCLK enable/disable selection.
+ * This parameter can be on of the following values:
+ * @arg ENABLE enable ADCPLLCLK
+ * @arg DISABLE disable ADCPLLCLK
+ */
+void RCC_ConfigAdcPllClk(uint32_t RCC_ADCPLLCLKPrescaler, FunctionalState Cmd)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_ADCPLLCLKPRE(RCC_ADCPLLCLKPrescaler));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ tmpregister = RCC->CFG2;
+ /* Clear ADCPLLPRES[4:0] bits */
+ tmpregister &= CFG2_ADCPLLPRES_RESET_MASK;
+
+ if (Cmd != DISABLE)
+ {
+ tmpregister |= RCC_ADCPLLCLKPrescaler;
+ }
+ else
+ {
+ tmpregister |= RCC_ADCPLLCLKPrescaler;
+ tmpregister &= RCC_ADCPLLCLK_DISABLE;
+ }
+
+ /* Store the new value */
+ RCC->CFG2 = tmpregister;
+}
+
+/**
+ * @brief Configures the ADCHCLK prescaler.
+ * @param RCC_ADCHCLKPrescaler specifies the ADCHCLK prescaler.
+ * This parameter can be on of the following values:
+ * @arg RCC_ADCHCLK_DIV1 ADCHCLKPRE[3:0] = 0000, HCLK Clock Divided By 1
+ * @arg RCC_ADCHCLK_DIV2 ADCHCLKPRE[3:0] = 0001, HCLK Clock Divided By 2
+ * @arg RCC_ADCHCLK_DIV4 ADCHCLKPRE[3:0] = 0010, HCLK Clock Divided By 4
+ * @arg RCC_ADCHCLK_DIV6 ADCHCLKPRE[3:0] = 0011, HCLK Clock Divided By 6
+ * @arg RCC_ADCHCLK_DIV8 ADCHCLKPRE[3:0] = 0100, HCLK Clock Divided By 8
+ * @arg RCC_ADCHCLK_DIV10 ADCHCLKPRE[3:0] = 0101, HCLK Clock Divided By 10
+ * @arg RCC_ADCHCLK_DIV12 ADCHCLKPRE[3:0] = 0110, HCLK Clock Divided By 12
+ * @arg RCC_ADCHCLK_DIV16 ADCHCLKPRE[3:0] = 0111, HCLK Clock Divided By 16
+ * @arg RCC_ADCHCLK_DIV32 ADCHCLKPRE[3:0] = 1000, HCLK Clock Divided By 32
+ * @arg RCC_ADCHCLK_DIV32 ADCHCLKPRE[3:0] = others, HCLK Clock Divided By 32
+ */
+void RCC_ConfigAdcHclk(uint32_t RCC_ADCHCLKPrescaler)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_ADCHCLKPRE(RCC_ADCHCLKPrescaler));
+
+ tmpregister = RCC->CFG2;
+ /* Clear ADCHPRE[3:0] bits */
+ tmpregister &= CFG2_ADCHPRES_RESET_MASK;
+ /* Set ADCHPRE[3:0] bits according to RCC_ADCHCLKPrescaler value */
+ tmpregister |= RCC_ADCHCLKPrescaler;
+
+ /* Store the new value */
+ RCC->CFG2 = tmpregister;
+}
+
+/**
+ * @brief Configures the TRNG 1M clock (TRNG1MCLK).
+ * @param RCC_TRNG1MCLKSource specifies the TRNG1M clock source.
+ * This parameter can be on of the following values:
+ * @arg RCC_TRNG1MCLK_SRC_HSI
+ * @arg RCC_TRNG1MCLK_SRC_HSE
+ *
+ * @param RCC_TRNG1MPrescaler specifies the TRNG1M prescaler.
+ * This parameter can be on of the following values:
+ * @arg RCC_TRNG1MCLKDiv_2 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/2
+ * @arg RCC_TRNG1MCLKDiv_4 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/4
+ * @arg RCC_TRNG1MCLKDiv_6 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/6
+ * ...
+ * @arg RCC_TRNG1MCLKDiv_30 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/30
+ * @arg RCC_TRNG1MCLKDiv_32 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/32
+ */
+void RCC_ConfigTrng1mClk(uint32_t RCC_TRNG1MCLKSource, uint32_t RCC_TRNG1MPrescaler)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_TRNG1MCLK_SRC(RCC_TRNG1MCLKSource));
+ assert_param(IS_RCC_TRNG1MCLKPRE(RCC_TRNG1MPrescaler));
+
+ tmpregister = RCC->CFG3;
+ /* Clear TRNG1MSEL and TRNG1MPRE[4:0] bits */
+ tmpregister &= CFGR3_TRNG1MSEL_RESET_MASK;
+ tmpregister &= CFGR3_TRNG1MPRES_RESET_MASK;
+ /* Set TRNG1MSEL bits according to RCC_TRNG1MCLKSource value */
+ tmpregister |= RCC_TRNG1MCLKSource;
+ /* Set TRNG1MPRE[4:0] bits according to RCC_TRNG1MPrescaler value */
+ tmpregister |= RCC_TRNG1MPrescaler;
+
+ /* Store the new value */
+ RCC->CFG3 = tmpregister;
+}
+
+/**
+ * @brief Enable/disable TRNG clock (TRNGCLK).
+ * @param Cmd specifies the TRNGCLK enable/disable selection.
+ * This parameter can be on of the following values:
+ * @arg ENABLE enable TRNGCLK
+ * @arg DISABLE disable TRNGCLK
+ */
+void RCC_EnableTrng1mClk(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ RCC->CFG3 |= RCC_TRNG1MCLK_ENABLE;
+ }
+ else
+ {
+ RCC->CFG3 &= RCC_TRNG1MCLK_DISABLE;
+ }
+}
+
+/**
+ * @brief Configures the External Low Speed oscillator (LSE).
+ * @param RCC_LSE specifies the new state of the LSE.
+ * This parameter can be one of the following values:
+ * @arg RCC_LSE_DISABLE LSE oscillator OFF
+ * @arg RCC_LSE_ENABLE LSE oscillator ON
+ * @arg RCC_LSE_BYPASS LSE oscillator bypassed with external clock
+ */
+void RCC_ConfigLse(uint8_t RCC_LSE)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE(RCC_LSE));
+ /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
+ /* Reset LSEON bit */
+ *(__IO uint8_t*)BDCTRL_ADDR = RCC_LSE_DISABLE;
+ /* Reset LSEBYP bit */
+ *(__IO uint8_t*)BDCTRL_ADDR = RCC_LSE_DISABLE;
+ /* Configure LSE (RCC_LSE_DISABLE is already covered by the code section above) */
+ switch (RCC_LSE)
+ {
+ case RCC_LSE_ENABLE:
+ /* Set LSEON bit */
+ *(__IO uint8_t*)BDCTRL_ADDR = RCC_LSE_ENABLE;
+ break;
+
+ case RCC_LSE_BYPASS:
+ /* Set LSEBYP and LSEON bits */
+ *(__IO uint8_t*)BDCTRL_ADDR = RCC_LSE_BYPASS | RCC_LSE_ENABLE;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Enables or disables the Internal Low Speed oscillator (LSI).
+ * @note LSI can not be disabled if the IWDG is running.
+ * @param Cmd new state of the LSI. This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableLsi(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)CTRLSTS_LSIEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Configures the RTC clock (RTCCLK).
+ * @note Once the RTC clock is selected it can't be changed unless the Backup domain is reset.
+ * @param RCC_RTCCLKSource specifies the RTC clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_RTCCLK_SRC_LSE LSE selected as RTC clock
+ * @arg RCC_RTCCLK_SRC_LSI LSI selected as RTC clock
+ * @arg RCC_RTCCLK_SRC_HSE_DIV128 HSE clock divided by 128 selected as RTC clock
+ */
+void RCC_ConfigRtcClk(uint32_t RCC_RTCCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_RTCCLK_SRC(RCC_RTCCLKSource));
+
+ /* Clear the RTC clock source */
+ RCC->BDCTRL &= (~0x00000300);
+
+ /* Select the RTC clock source */
+ RCC->BDCTRL |= RCC_RTCCLKSource;
+}
+
+/**
+ * @brief Enables or disables the RTC clock.
+ * @note This function must be used only after the RTC clock was selected using the RCC_ConfigRtcClk function.
+ * @param Cmd new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableRtcClk(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)BDCTRL_RTCEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Returns the frequencies of different on chip clocks.
+ * @param RCC_Clocks pointer to a RCC_ClocksType structure which will hold
+ * the clocks frequencies.
+ * @note The result of this function could be not correct when using
+ * fractional value for HSE crystal.
+ */
+void RCC_GetClocksFreqValue(RCC_ClocksType* RCC_Clocks)
+{
+ uint32_t tmp = 0, pllclk = 0, pllmull = 0, pllsource = 0, presc = 0;
+
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFG & CFG_PLLMULFCT_MASK;
+ pllsource = RCC->CFG & CFG_PLLSRC_MASK;
+
+ if ((pllmull & RCC_CFG_PLLMULFCT_4) == 0)
+ {
+ pllmull = (pllmull >> 18) + 2; // PLLMUL[4]=0
+ }
+ else
+ {
+ pllmull = ((pllmull >> 18) - 496) + 1; // PLLMUL[4]=1
+ }
+
+ if (pllsource == 0x00)
+ { /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ pllclk = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ /* HSE selected as PLL clock entry */
+ if ((RCC->CFG & CFG_PLLHSEPRES_MASK) != (uint32_t)RESET)
+ { /* HSE oscillator clock divided by 2 */
+ pllclk = (HSE_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ pllclk = HSE_VALUE * pllmull;
+ }
+ }
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFG & CFG_SCLKSTS_MASK;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock */
+ RCC_Clocks->SysclkFreq = HSI_VALUE;
+ break;
+ case 0x04: /* HSE used as system clock */
+ RCC_Clocks->SysclkFreq = HSE_VALUE;
+ break;
+ case 0x08: /* PLL used as system clock */
+ RCC_Clocks->SysclkFreq = pllclk;
+ break;
+
+ default:
+ RCC_Clocks->SysclkFreq = HSI_VALUE;
+ break;
+ }
+
+ /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
+ /* Get HCLK prescaler */
+ tmp = RCC->CFG & CFG_AHBPRES_SET_MASK;
+ tmp = tmp >> 4;
+ presc = s_ApbAhbPresTable[tmp];
+ /* HCLK clock frequency */
+ RCC_Clocks->HclkFreq = RCC_Clocks->SysclkFreq >> presc;
+ /* Get PCLK1 prescaler */
+ tmp = RCC->CFG & CFG_APB1PRES_SET_MASK;
+ tmp = tmp >> 8;
+ presc = s_ApbAhbPresTable[tmp];
+ /* PCLK1 clock frequency */
+ RCC_Clocks->Pclk1Freq = RCC_Clocks->HclkFreq >> presc;
+ /* Get PCLK2 prescaler */
+ tmp = RCC->CFG & CFG_APB2PRES_SET_MASK;
+ tmp = tmp >> 11;
+ presc = s_ApbAhbPresTable[tmp];
+ /* PCLK2 clock frequency */
+ RCC_Clocks->Pclk2Freq = RCC_Clocks->HclkFreq >> presc;
+
+ /* Get ADCHCLK prescaler */
+ tmp = RCC->CFG2 & CFG2_ADCHPRES_SET_MASK;
+ presc = s_AdcHclkPresTable[tmp];
+ /* ADCHCLK clock frequency */
+ RCC_Clocks->AdcHclkFreq = RCC_Clocks->HclkFreq / presc;
+ /* Get ADCPLLCLK prescaler */
+ tmp = RCC->CFG2 & CFG2_ADCPLLPRES_SET_MASK;
+ tmp = tmp >> 4;
+ presc = s_AdcPllClkPresTable[(tmp & 0xF)]; // ignore BIT5
+ /* ADCPLLCLK clock frequency */
+ RCC_Clocks->AdcPllClkFreq = pllclk / presc;
+}
+
+/**
+ * @brief Enables or disables the AHB peripheral clock.
+ * @param RCC_AHBPeriph specifies the AHB peripheral to gates its clock.
+ *
+ * this parameter can be any combination of the following values:
+ * @arg RCC_AHB_PERIPH_DMA1
+ * @arg RCC_AHB_PERIPH_DMA2
+ * @arg RCC_AHB_PERIPH_SRAM
+ * @arg RCC_AHB_PERIPH_FLITF
+ * @arg RCC_AHB_PERIPH_CRC
+ * @arg RCC_AHB_PERIPH_RNGC
+ * @arg RCC_AHB_PERIPH_SDIO
+ * @arg RCC_AHB_PERIPH_SAC
+ * @arg RCC_AHB_PERIPH_ADC1
+ * @arg RCC_AHB_PERIPH_ADC2
+ *
+ * @note SRAM and FLITF clock can be disabled only during sleep mode.
+ * @param Cmd new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableAHBPeriphClk(uint32_t RCC_AHBPeriph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ RCC->AHBPCLKEN |= RCC_AHBPeriph;
+ }
+ else
+ {
+ RCC->AHBPCLKEN &= ~RCC_AHBPeriph;
+ }
+}
+
+/**
+ * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
+ * @param RCC_APB2Periph specifies the APB2 peripheral to gates its clock.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB2_PERIPH_AFIO, RCC_APB2_PERIPH_GPIOA, RCC_APB2_PERIPH_GPIOB,
+ * RCC_APB2_PERIPH_GPIOC, RCC_APB2_PERIPH_GPIOD, RCC_APB2_PERIPH_GPIOE,
+ * RCC_APB2_PERIPH_TIM1,
+ * RCC_APB2_PERIPH_SPI1, RCC_APB2_PERIPH_TIM8, RCC_APB2_PERIPH_USART1,
+ * RCC_APB2_PERIPH_DVP, RCC_APB2_PERIPH_UART6, RCC_APB2_PERIPH_UART7,
+ * RCC_APB2_PERIPH_I2C3, RCC_APB2_PERIPH_I2C4
+ * @param Cmd new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableAPB2PeriphClk(uint32_t RCC_APB2Periph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ RCC->APB2PCLKEN |= RCC_APB2Periph;
+ }
+ else
+ {
+ RCC->APB2PCLKEN &= ~RCC_APB2Periph;
+ }
+}
+
+/**
+ * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
+ * @param RCC_APB1Periph specifies the APB1 peripheral to gates its clock.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB1_PERIPH_TIM2, RCC_APB1_PERIPH_TIM3, RCC_APB1_PERIPH_TIM4,
+ * RCC_APB1_PERIPH_TIM5, RCC_APB1_PERIPH_TIM6, RCC_APB1_PERIPH_TIM7,
+ * RCC_APB1_PERIPH_COMP, RCC_APB1_PERIPH_COMP_FILT, RCC_APB1_PERIPH_TSC,
+ * RCC_APB1_PERIPH_WWDG, RCC_APB1_PERIPH_SPI2, RCC_APB1_PERIPH_SPI3,
+ * RCC_APB1_PERIPH_USART2, RCC_APB1_PERIPH_USART3, RCC_APB1_PERIPH_UART4,
+ * RCC_APB1_PERIPH_UART5, RCC_APB1_PERIPH_I2C1, RCC_APB1_PERIPH_I2C2,
+ * RCC_APB1_PERIPH_USB, RCC_APB1_PERIPH_CAN1, RCC_APB1_PERIPH_CAN2, RCC_APB1_PERIPH_BKP,
+ * RCC_APB1_PERIPH_PWR, RCC_APB1_PERIPH_DAC, RCC_APB1_PERIPH_OPAMP
+ *
+ * @param Cmd new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableAPB1PeriphClk(uint32_t RCC_APB1Periph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ RCC->APB1PCLKEN |= RCC_APB1Periph;
+ }
+ else
+ {
+ RCC->APB1PCLKEN &= ~RCC_APB1Periph;
+ }
+}
+
+/**
+ * @brief Forces or releases AHB peripheral reset.
+ * @param RCC_AHBPeriph specifies the AHB peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * RCC_AHB_PERIPH_ADC2.
+ * RCC_AHB_PERIPH_ADC1.
+ * RCC_AHB_PERIPH_SAC.
+ * RCC_AHB_PERIPH_RNGC.
+ * @param Cmd new state of the specified peripheral reset. This parameter can be ENABLE or DISABLE.
+ */
+void RCC_EnableAHBPeriphReset(uint32_t RCC_AHBPeriph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ RCC->AHBPRST |= RCC_AHBPeriph;
+ }
+ else
+ {
+ RCC->AHBPRST &= ~RCC_AHBPeriph;
+ }
+}
+
+/**
+ * @brief Forces or releases High Speed APB (APB2) peripheral reset.
+ * @param RCC_APB2Periph specifies the APB2 peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB2_PERIPH_AFIO, RCC_APB2_PERIPH_GPIOA, RCC_APB2_PERIPH_GPIOB,
+ * RCC_APB2_PERIPH_GPIOC, RCC_APB2_PERIPH_GPIOD, RCC_APB2_PERIPH_GPIOE,
+ * RCC_APB2_PERIPH_TIM1,
+ * RCC_APB2_PERIPH_SPI1, RCC_APB2_PERIPH_TIM8, RCC_APB2_PERIPH_USART1,
+ * RCC_APB2_PERIPH_DVP, RCC_APB2_PERIPH_UART6, RCC_APB2_PERIPH_UART7,
+ * RCC_APB2_PERIPH_I2C3, RCC_APB2_PERIPH_I2C4
+ * @param Cmd new state of the specified peripheral reset.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableAPB2PeriphReset(uint32_t RCC_APB2Periph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ RCC->APB2PRST |= RCC_APB2Periph;
+ }
+ else
+ {
+ RCC->APB2PRST &= ~RCC_APB2Periph;
+ }
+}
+
+/**
+ * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
+ * @param RCC_APB1Periph specifies the APB1 peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB1_PERIPH_TIM2, RCC_APB1_PERIPH_TIM3, RCC_APB1_PERIPH_TIM4,
+ * RCC_APB1_PERIPH_TIM5, RCC_APB1_PERIPH_TIM6, RCC_APB1_PERIPH_TIM7,
+ * RCC_APB1_PERIPH_TSC, RCC_APB1_PERIPH_WWDG, RCC_APB1_PERIPH_SPI2,
+ * RCC_APB1_PERIPH_SPI3, RCC_APB1_PERIPH_USART2, RCC_APB1_PERIPH_USART3,
+ * RCC_APB1_PERIPH_UART4, RCC_APB1_PERIPH_UART5, RCC_APB1_PERIPH_I2C1,
+ * RCC_APB1_PERIPH_I2C2, RCC_APB1_PERIPH_USB, RCC_APB1_PERIPH_CAN1,
+ * RCC_APB1_PERIPH_CAN2, RCC_APB1_PERIPH_BKP, RCC_APB1_PERIPH_PWR,
+ * RCC_APB1_PERIPH_DAC
+ * @param Cmd new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableAPB1PeriphReset(uint32_t RCC_APB1Periph, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ RCC->APB1PRST |= RCC_APB1Periph;
+ }
+ else
+ {
+ RCC->APB1PRST &= ~RCC_APB1Periph;
+ }
+}
+
+/**
+ * @brief BOR reset enable.
+ * @param Cmd new state of the BOR reset.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableBORReset(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ RCC->CFG3 |= RCC_BOR_RST_ENABLE;
+ }
+ else
+ {
+ RCC->CFG3 &= ~RCC_BOR_RST_ENABLE;
+ }
+}
+
+/**
+ * @brief Forces or releases the Backup domain reset.
+ * @param Cmd new state of the Backup domain reset.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableBackupReset(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)BDCTRL_BDSFTRST_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Enables or disables the Clock Security System.
+ * @param Cmd new state of the Clock Security System..
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableClockSecuritySystem(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ *(__IO uint32_t*)CTRL_CLKSSEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Configures the MCO PLL clock prescaler.
+ * @param RCC_MCOPLLCLKPrescaler specifies the MCO PLL clock prescaler.
+ * This parameter can be on of the following values:
+ * @arg RCC_MCO_PLLCLK_DIV2 MCOPRE[3:0] = 0010, PLL Clock Divided By 2
+ * @arg RCC_MCO_PLLCLK_DIV3 MCOPRE[3:0] = 0011, PLL Clock Divided By 3
+ * @arg RCC_MCO_PLLCLK_DIV4 MCOPRE[3:0] = 0100, PLL Clock Divided By 4
+ * @arg RCC_MCO_PLLCLK_DIV5 MCOPRE[3:0] = 0101, PLL Clock Divided By 5
+ * ...
+ * @arg RCC_MCO_PLLCLK_DIV13 MCOPRE[3:0] = 1101, PLL Clock Divided By 13
+ * @arg RCC_MCO_PLLCLK_DIV14 MCOPRE[3:0] = 1110, PLL Clock Divided By 14
+ * @arg RCC_MCO_PLLCLK_DIV15 MCOPRE[3:0] = 1111, PLL Clock Divided By 15
+ */
+void RCC_ConfigMcoPllClk(uint32_t RCC_MCOPLLCLKPrescaler)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_MCOPLLCLKPRE(RCC_MCOPLLCLKPrescaler));
+
+ tmpregister = RCC->CFG;
+ /* Clear MCOPRE[3:0] bits */
+ tmpregister &= ((uint32_t)0x0FFFFFFF);
+ /* Set MCOPRE[3:0] bits according to RCC_ADCHCLKPrescaler value */
+ tmpregister |= RCC_MCOPLLCLKPrescaler;
+
+ /* Store the new value */
+ RCC->CFG = tmpregister;
+}
+
+/**
+ * @brief Selects the clock source to output on MCO pin.
+ * @param RCC_MCO specifies the clock source to output.
+ *
+ * this parameter can be one of the following values:
+ * @arg RCC_MCO_NOCLK No clock selected
+ * @arg RCC_MCO_SYSCLK System clock selected
+ * @arg RCC_MCO_HSI HSI oscillator clock selected
+ * @arg RCC_MCO_HSE HSE oscillator clock selected
+ * @arg RCC_MCO_PLLCLK PLL clock divided by xx selected
+ *
+ */
+void RCC_ConfigMco(uint8_t RCC_MCO)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_MCO(RCC_MCO));
+
+ tmpregister = RCC->CFG;
+ /* Clear MCO[2:0] bits */
+ tmpregister &= ((uint32_t)0xF8FFFFFF);
+ /* Set MCO[2:0] bits according to RCC_MCO value */
+ tmpregister |= ((uint32_t)(RCC_MCO << 24));
+
+ /* Store the new value */
+ RCC->CFG = tmpregister;
+}
+
+/**
+ * @brief Checks whether the specified RCC flag is set or not.
+ * @param RCC_FLAG specifies the flag to check.
+ *
+ * this parameter can be one of the following values:
+ * @arg RCC_FLAG_HSIRD HSI oscillator clock ready
+ * @arg RCC_FLAG_HSERD HSE oscillator clock ready
+ * @arg RCC_FLAG_PLLRD PLL clock ready
+ * @arg RCC_FLAG_LSERD LSE oscillator clock ready
+ * @arg RCC_FLAG_LSIRD LSI oscillator clock ready
+ * @arg RCC_FLAG_BORRST BOR reset flag
+ * @arg RCC_FLAG_RETEMC Retention EMC reset flag
+ * @arg RCC_FLAG_BKPEMC BackUp EMC reset flag
+ * @arg RCC_FLAG_RAMRST RAM reset flag
+ * @arg RCC_FLAG_MMURST Mmu reset flag
+ * @arg RCC_FLAG_PINRST Pin reset
+ * @arg RCC_FLAG_PORRST POR/PDR reset
+ * @arg RCC_FLAG_SFTRST Software reset
+ * @arg RCC_FLAG_IWDGRST Independent Watchdog reset
+ * @arg RCC_FLAG_WWDGRST Window Watchdog reset
+ * @arg RCC_FLAG_LPWRRST Low Power reset
+ *
+ * @return The new state of RCC_FLAG (SET or RESET).
+ */
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
+{
+ uint32_t tmp = 0;
+ uint32_t statusreg = 0;
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_RCC_FLAG(RCC_FLAG));
+
+ /* Get the RCC register index */
+ tmp = RCC_FLAG >> 5;
+ if (tmp == 1) /* The flag to check is in CTRL register */
+ {
+ statusreg = RCC->CTRL;
+ }
+ else if (tmp == 2) /* The flag to check is in BDCTRL register */
+ {
+ statusreg = RCC->BDCTRL;
+ }
+ else /* The flag to check is in CTRLSTS register */
+ {
+ statusreg = RCC->CTRLSTS;
+ }
+
+ /* Get the flag position */
+ tmp = RCC_FLAG & FLAG_MASK;
+ if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RCC reset flags.
+ * @note The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
+ * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
+ */
+void RCC_ClrFlag(void)
+{
+ /* Set RMVF bit to clear the reset flags */
+ RCC->CTRLSTS |= CSR_RMRSTF_SET;
+ /* RMVF bit should be reset */
+ RCC->CTRLSTS &= CSR_RMVF_Reset;
+}
+
+/**
+ * @brief Checks whether the specified RCC interrupt has occurred or not.
+ * @param RccInt specifies the RCC interrupt source to check.
+ *
+ * this parameter can be one of the following values:
+ * @arg RCC_INT_LSIRDIF LSI ready interrupt
+ * @arg RCC_INT_LSERDIF LSE ready interrupt
+ * @arg RCC_INT_HSIRDIF HSI ready interrupt
+ * @arg RCC_INT_HSERDIF HSE ready interrupt
+ * @arg RCC_INT_PLLRDIF PLL ready interrupt
+ *
+ * @arg RCC_INT_CLKSSIF Clock Security System interrupt
+ *
+ * @return The new state of RccInt (SET or RESET).
+ */
+INTStatus RCC_GetIntStatus(uint8_t RccInt)
+{
+ INTStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_RCC_GET_INT(RccInt));
+
+ /* Check the status of the specified RCC interrupt */
+ if ((RCC->CLKINT & RccInt) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ /* Return the RccInt status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RCC's interrupt pending bits.
+ * @param RccInt specifies the interrupt pending bit to clear.
+ *
+ * this parameter can be any combination of the
+ * following values:
+ * @arg RCC_INT_LSIRDIF LSI ready interrupt
+ * @arg RCC_INT_LSERDIF LSE ready interrupt
+ * @arg RCC_INT_HSIRDIF HSI ready interrupt
+ * @arg RCC_INT_HSERDIF HSE ready interrupt
+ * @arg RCC_INT_PLLRDIF PLL ready interrupt
+ *
+ * @arg RCC_INT_CLKSSIF Clock Security System interrupt
+ */
+void RCC_ClrIntPendingBit(uint8_t RccInt)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_CLR_INT(RccInt));
+
+ /* Perform Byte access to RCC_CLKINT[23:16] bits to clear the selected interrupt
+ pending bits */
+ *(__IO uint8_t*)CLKINT_BYTE3_ADDR = RccInt;
+}
+
+/**
+ * @brief Configures system clock after wake-up from STOP: enable HSE, PLL
+ * and select PLL as system clock source.
+ * @param Rcc_PLLMul specifies the PLL multiplication factor.
+ * this parameter can be RCC_PLLMul_x where x:[2,32]
+ * @param FLASH_Latency specifies the FLASH Latency value.
+ * This parameter can be one of the following values:
+ * @arg FLASH_LATENCY_0 FLASH Zero Latency cycle
+ * @arg FLASH_LATENCY_1 FLASH One Latency cycle
+ * @arg FLASH_LATENCY_2 FLASH Two Latency cycles
+ * @arg FLASH_LATENCY_3 FLASH Three Latency cycles
+ * @arg FLASH_LATENCY_4 FLASH Four Latency cycles
+ */
+void RCC_SYSCLKConfigFromSTOP(uint32_t Rcc_PLLMul, uint32_t FLASH_Latency)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0, PLLStatus = 0, SYSCLKStatus = 0;
+ uint32_t tmpregister = 0;
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CTRL & RCC_CTRL_HSERDF;
+ StartUpCounter++;
+ } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CTRL & RCC_CTRL_HSERDF) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->AC |= FLASH_AC_PRFTBFEN;
+ /* Read the AC register */
+ tmpregister = FLASH->AC;
+ /* Sets the Latency value */
+ tmpregister &= (uint32_t)((uint32_t)~FLASH_AC_LATENCY);
+ tmpregister |= FLASH_Latency;
+ /* Write the AC register */
+ FLASH->AC = tmpregister;
+ /* HCLK = SYSCLK */
+ RCC->CFG |= (uint32_t)RCC_CFG_AHBPRES_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFG |= (uint32_t)RCC_CFG_APB2PRES_DIV2;
+ /* PCLK1 = HCLK */
+ RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV4;
+ /* PLL configuration: PLLCLK = HSE * 18 = 144 MHz */
+ RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_PLLSRC | RCC_CFG_PLLHSEPRES | RCC_CFG_PLLMULFCT));
+ RCC->CFG |= (uint32_t)(RCC_CFG_PLLSRC_HSE | Rcc_PLLMul);
+ /* Enable PLL */
+ RCC->CTRL |= RCC_CTRL_PLLEN;
+ /* Wait till PLL is ready and if Time out is reached exit */
+ do
+ {
+ PLLStatus = RCC->CTRL & RCC_CTRL_PLLRDF;
+ StartUpCounter++;
+ } while ((PLLStatus != RCC_CTRL_PLLRDF) && (StartUpCounter != PLL_STARTUP_TIMEOUT));
+ /* Select PLL as system clock source */
+ RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW));
+ RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_PLL;
+ /* Wait till PLL is used as system clock source */
+ do
+ {
+ SYSCLKStatus = RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS;
+ StartUpCounter++;
+ } while ((SYSCLKStatus != RCC_CFG_SCLKSTS_PLL) && (StartUpCounter != SYSCLK_STARTUP_TIMEOUT));
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_rtc.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_rtc.c
new file mode 100644
index 0000000000..089a027bc3
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_rtc.c
@@ -0,0 +1,2007 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_rtc.c
+ * @author Nations
+ * @version v1.0.1
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32wb452_rtc.h"
+#include "n32wb452_rcc.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RTC
+ * @brief RTC driver modules
+ * @{
+ */
+
+/* Masks Definition */
+#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
+#define RTC_DATE_RESERVED_MASK ((uint32_t)0x00FFFF3F)
+
+#define RTC_RSF_MASK ((uint32_t)0xFFFFFFDF)
+#define RTC_FLAGS_MASK \
+ ((uint32_t)(RTC_FLAG_TISOVF | RTC_FLAG_TISF | RTC_FLAG_WTF | RTC_FLAG_ALBF | RTC_FLAG_ALAF | RTC_FLAG_INITF \
+ | RTC_FLAG_RSYF | RTC_FLAG_INITSF | RTC_FLAG_WTWF | RTC_FLAG_ALBWF | RTC_FLAG_ALAWF | RTC_FLAG_RECPF \
+ | RTC_FLAG_SHOPF))
+
+#define INITMODE_TIMEOUT ((uint32_t)0x00002000)
+#define SYNCHRO_TIMEOUT ((uint32_t)0x00008000)
+#define RECALPF_TIMEOUT ((uint32_t)0x00001000)
+#define SHPF_TIMEOUT ((uint32_t)0x00002000)
+
+static uint8_t RTC_ByteToBcd2(uint8_t Value);
+static uint8_t RTC_Bcd2ToByte(uint8_t Value);
+
+/** @addtogroup RTC_Private_Functions
+ * @{
+ */
+
+/** @addtogroup RTC_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This section provide functions allowing to initialize and configure the
+ RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
+ RTC registers Write protection, enter and exit the RTC initialization mode,
+ RTC registers synchronization check and reference clock detection enable.
+ (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
+ It is split into 2 programmable prescalers to minimize power consumption.
+ (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler.
+ (++) When both prescalers are used, it is recommended to configure the
+ asynchronous prescaler to a high value to minimize consumption.
+ (#) All RTC registers are Write protected. Writing to the RTC registers
+ is enabled by writing a key into the Write Protection register, RTC_WRP.
+ (#) To Configure the RTC Calendar, user application should enter
+ initialization mode. In this mode, the calendar counter is stopped
+ and its value can be updated. When the initialization sequence is
+ complete, the calendar restarts counting after 4 RTCCLK cycles.
+ (#) To read the calendar through the shadow registers after Calendar
+ initialization, calendar update or after wakeup from low power modes
+ the software must first clear the RSYF flag. The software must then
+ wait until it is set again before reading the calendar, which means
+ that the calendar registers have been correctly copied into the
+ RTC_TSH and RTC_DATE shadow registers.The RTC_WaitForSynchro() function
+ implements the above software sequence (RSYF clear and RSYF check).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the RTC registers to their default reset values.
+ * @note This function doesn't reset the RTC Clock source
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are deinitialized
+ * - ERROR: RTC registers are not deinitialized
+ */
+ErrorStatus RTC_DeInit(void)
+{
+ __IO uint32_t wutcounter = 0x00;
+ uint32_t wutwfstatus = 0x00;
+ ErrorStatus status = ERROR;
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Set Initialization mode */
+ if (RTC_EnterInitMode() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ /* Reset TSH, DAT and CTRL registers */
+ RTC->TSH = (uint32_t)0x00000000;
+ RTC->DATE = (uint32_t)0x00002101;
+
+ /* Reset All CTRL bits except CTRL[2:0] */
+ RTC->CTRL &= (uint32_t)0x00000007;
+
+ /* Wait till RTC WTWF flag is set and if Time out is reached exit */
+ do
+ {
+ wutwfstatus = RTC->INITSTS & RTC_INITSTS_WTWF;
+ wutcounter++;
+ } while ((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
+
+ if ((RTC->INITSTS & RTC_INITSTS_WTWF) == RESET)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ /* Reset all RTC CTRL register bits */
+ RTC->CTRL &= (uint32_t)0x00000000;
+ RTC->WKUPT = (uint32_t)0x0000FFFF;
+ RTC->PRE = (uint32_t)0x007F00FF;
+ RTC->ALARMA = (uint32_t)0x00000000;
+ RTC->ALARMB = (uint32_t)0x00000000;
+ RTC->SCTRL = (uint32_t)0x00000000;
+ RTC->CALIB = (uint32_t)0x00000000;
+ RTC->ALRMASS = (uint32_t)0x00000000;
+ RTC->ALRMBSS = (uint32_t)0x00000000;
+
+ /* Reset INTSTS register and exit initialization mode */
+ RTC->INITSTS = (uint32_t)0x00000000;
+
+ RTC->OPT = (uint32_t)0x00000000;
+ RTC->TSCWKUPCTRL = (uint32_t)0x00000008;
+ RTC->TSCWKUPCNT = (uint32_t)0x000002FE;
+
+ /* Wait till the RTC RSYF flag is set */
+ if (RTC_WaitForSynchro() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+
+ return status;
+}
+
+/**
+ * @brief Initializes the RTC registers according to the specified parameters
+ * in RTC_InitStruct.
+ * @param RTC_InitStruct pointer to a RTC_InitType structure that contains
+ * the configuration information for the RTC peripheral.
+ * @note The RTC Prescaler register is write protected and can be written in
+ * initialization mode only.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are initialized
+ * - ERROR: RTC registers are not initialized
+ */
+ErrorStatus RTC_Init(RTC_InitType* RTC_InitStruct)
+{
+ ErrorStatus status = ERROR;
+ uint32_t i =0;
+ /* Check the parameters */
+ assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat));
+ assert_param(IS_RTC_PREDIV_ASYNCH(RTC_InitStruct->RTC_AsynchPrediv));
+ assert_param(IS_RTC_PREDIV_SYNCH(RTC_InitStruct->RTC_SynchPrediv));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Set Initialization mode */
+ if (RTC_EnterInitMode() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ /* Clear RTC CTRL HFMT Bit */
+ RTC->CTRL &= ((uint32_t) ~(RTC_CTRL_HFMT));
+ /* Set RTC_CTRL register */
+ RTC->CTRL |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat));
+
+ /* Configure the RTC PRE */
+ RTC->PRE = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv);
+ RTC->PRE |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16);
+
+ /* Exit Initialization mode */
+ RTC_ExitInitMode();
+
+ status = SUCCESS;
+ }
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+ /* Delay for the RTC prescale effect */
+ for(i=0;i<0x2FF;i++);
+ return status;
+}
+
+/**
+ * @brief Fills each RTC_InitStruct member with its default value.
+ * @param RTC_InitStruct pointer to a RTC_InitType structure which will be
+ * initialized.
+ */
+void RTC_StructInit(RTC_InitType* RTC_InitStruct)
+{
+ /* Initialize the RTC_HourFormat member */
+ RTC_InitStruct->RTC_HourFormat = RTC_24HOUR_FORMAT;
+
+ /* Initialize the RTC_AsynchPrediv member */
+ RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F;
+
+ /* Initialize the RTC_SynchPrediv member */
+ RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF;
+}
+
+/**
+ * @brief Enables or disables the RTC registers write protection.
+ * @note All the RTC registers are write protected except for RTC_INITSTS[13:8].
+ * @note Writing a wrong key reactivates the write protection.
+ * @note The protection mechanism is not affected by system reset.
+ * @param Cmd new state of the write protection.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RTC_EnableWriteProtection(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+ }
+ else
+ {
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+ }
+}
+
+/**
+ * @brief Enters the RTC Initialization mode.
+ * @note The RTC Initialization mode is write protected, use the
+ * RTC_EnableWriteProtection(DISABLE) before calling this function.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC is in Init mode
+ * - ERROR: RTC is not in Init mode
+ */
+ErrorStatus RTC_EnterInitMode(void)
+{
+ __IO uint32_t initcounter = 0x00;
+ ErrorStatus status = ERROR;
+ uint32_t initstatus = 0x00;
+
+ /* Check if the Initialization mode is set */
+ if ((RTC->INITSTS & RTC_INITSTS_INITF) == (uint32_t)RESET)
+ {
+ /* Set the Initialization mode */
+ RTC->INITSTS = (uint32_t)RTC_INITSTS_INITM;
+
+ /* Wait till RTC is in INIT state and if Time out is reached exit */
+ do
+ {
+ initstatus = RTC->INITSTS & RTC_INITSTS_INITF;
+ initcounter++;
+ } while ((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));
+
+ if ((RTC->INITSTS & RTC_INITSTS_INITF) != RESET)
+ {
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Exits the RTC Initialization mode.
+ * @note When the initialization sequence is complete, the calendar restarts
+ * counting after 4 RTCCLK cycles.
+ * @note The RTC Initialization mode is write protected, use the
+ * RTC_EnableWriteProtection(DISABLE) before calling this function.
+ */
+void RTC_ExitInitMode(void)
+{
+ /* Exit Initialization mode */
+ RTC->INITSTS &= (uint32_t)~RTC_INITSTS_INITM;
+}
+
+/**
+ * @brief Waits until the RTC Time and Date registers (RTC_TSH and RTC_DATE) are
+ * synchronized with RTC APB clock.
+ * @note The RTC Resynchronization mode is write protected, use the
+ * RTC_EnableWriteProtection(DISABLE) before calling this function.
+ * @note To read the calendar through the shadow registers after Calendar
+ * initialization, calendar update or after wakeup from low power modes
+ * the software must first clear the RSYF flag.
+ * The software must then wait until it is set again before reading
+ * the calendar, which means that the calendar registers have been
+ * correctly copied into the RTC_TSH and RTC_DATE shadow registers.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are synchronised
+ * - ERROR: RTC registers are not synchronised
+ */
+ErrorStatus RTC_WaitForSynchro(void)
+{
+ __IO uint32_t synchrocounter = 0;
+ ErrorStatus status = ERROR;
+ uint32_t synchrostatus = 0x00;
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Clear RSYF flag */
+ RTC->INITSTS &= (uint32_t)RTC_RSF_MASK;
+
+ /* Wait the registers to be synchronised */
+ do
+ {
+ synchrostatus = RTC->INITSTS & RTC_INITSTS_RSYF;
+ synchrocounter++;
+ } while ((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));
+
+ if ((RTC->INITSTS & RTC_INITSTS_RSYF) != RESET)
+ {
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+
+ return (status);
+}
+
+
+
+/**
+ * @brief Enables or Disables the Bypass Shadow feature.
+ * @note When the Bypass Shadow is enabled the calendar value are taken
+ * directly from the Calendar counter.
+ * @param Cmd new state of the Bypass Shadow feature.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RTC_EnableBypassShadow(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ if (Cmd != DISABLE)
+ {
+ /* Set the BYPS bit */
+ RTC->CTRL |= (uint8_t)RTC_CTRL_BYPS;
+ }
+ else
+ {
+ /* Reset the BYPS bit */
+ RTC->CTRL &= (uint8_t)~RTC_CTRL_BYPS;
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group2 Time and Date configuration functions
+ * @brief Time and Date configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Time and Date configuration functions #####
+ ===============================================================================
+ [..] This section provide functions allowing to program and read the RTC
+ Calendar (Time and Date).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set the RTC current time.
+ * @param RTC_Format specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN Binary data format.
+ * @arg RTC_FORMAT_BCD BCD data format.
+ * @param RTC_TimeStruct pointer to a RTC_TimeType structure that contains
+ * the time configuration information for the RTC.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Time register is configured
+ * - ERROR: RTC Time register is not configured
+ */
+ErrorStatus RTC_ConfigTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct)
+{
+ uint32_t tmpregister = 0;
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+
+ if (RTC_Format == RTC_FORMAT_BIN)
+ {
+ if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET)
+ {
+ assert_param(IS_RTC_12HOUR(RTC_TimeStruct->Hours));
+ assert_param(IS_RTC_H12(RTC_TimeStruct->H12));
+ }
+ else
+ {
+ RTC_TimeStruct->H12 = 0x00;
+ assert_param(IS_RTC_24HOUR(RTC_TimeStruct->Hours));
+ }
+ assert_param(IS_RTC_MINUTES(RTC_TimeStruct->Minutes));
+ assert_param(IS_RTC_SECONDS(RTC_TimeStruct->Seconds));
+ }
+ else
+ {
+ if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET)
+ {
+ tmpregister = RTC_Bcd2ToByte(RTC_TimeStruct->Hours);
+ assert_param(IS_RTC_12HOUR(tmpregister));
+ assert_param(IS_RTC_H12(RTC_TimeStruct->H12));
+ }
+ else
+ {
+ RTC_TimeStruct->H12 = 0x00;
+ assert_param(IS_RTC_24HOUR(RTC_Bcd2ToByte(RTC_TimeStruct->Hours)));
+ }
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->Seconds)));
+ }
+
+ /* Check the input parameters format */
+ if (RTC_Format != RTC_FORMAT_BIN)
+ {
+ tmpregister = (((uint32_t)(RTC_TimeStruct->Hours) << 16) | ((uint32_t)(RTC_TimeStruct->Minutes) << 8)
+ | ((uint32_t)RTC_TimeStruct->Seconds) | ((uint32_t)(RTC_TimeStruct->H12) << 16));
+ }
+ else
+ {
+ tmpregister =
+ (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->Hours) << 16)
+ | ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->Minutes) << 8)
+ | ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->Seconds)) | (((uint32_t)RTC_TimeStruct->H12) << 16));
+ }
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Set Initialization mode */
+ if (RTC_EnterInitMode() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ /* Set the RTC_TSH register */
+ RTC->TSH = (uint32_t)(tmpregister & RTC_TR_RESERVED_MASK);
+
+ /* Exit Initialization mode */
+ RTC_ExitInitMode();
+
+ /* If RTC_CTRL_BYPS bit = 0, wait for synchro else this check is not needed */
+ if ((RTC->CTRL & RTC_CTRL_BYPS) == RESET)
+ {
+ if (RTC_WaitForSynchro() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+ /* Waits until the RTC Time and Date registers
+ (RTC_TSH and RTC_DATE) are synchronized with RTC APB clock. */
+ status=RTC_WaitForSynchro();
+ return status;
+}
+
+/**
+ * @brief Fills each RTC_TimeStruct member with its default value
+ * (Time = 00h:00min:00sec).
+ * @param RTC_TimeStruct pointer to a RTC_TimeType structure which will be
+ * initialized.
+ */
+void RTC_TimeStructInit(RTC_TimeType* RTC_TimeStruct)
+{
+ /* Time = 00h:00min:00sec */
+ RTC_TimeStruct->H12 = RTC_AM_H12;
+ RTC_TimeStruct->Hours = 0;
+ RTC_TimeStruct->Minutes = 0;
+ RTC_TimeStruct->Seconds = 0;
+}
+
+/**
+ * @brief Get the RTC current Time.
+ * @param RTC_Format specifies the format of the returned parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN Binary data format.
+ * @arg RTC_FORMAT_BCD BCD data format.
+ * @param RTC_TimeStruct pointer to a RTC_TimeType structure that will
+ * contain the returned current time configuration.
+ */
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+
+ /* Get the RTC_TSH register */
+ tmpregister = (uint32_t)(RTC->TSH & RTC_TR_RESERVED_MASK);
+
+ /* Fill the structure fields with the read parameters */
+ RTC_TimeStruct->Hours = (uint8_t)((tmpregister & (RTC_TSH_HOT | RTC_TSH_HOU)) >> 16);
+ RTC_TimeStruct->Minutes = (uint8_t)((tmpregister & (RTC_TSH_MIT | RTC_TSH_MIU)) >> 8);
+ RTC_TimeStruct->Seconds = (uint8_t)(tmpregister & (RTC_TSH_SCT | RTC_TSH_SCU));
+ RTC_TimeStruct->H12 = (uint8_t)((tmpregister & (RTC_TSH_APM)) >> 16);
+
+ /* Check the input parameters format */
+ if (RTC_Format == RTC_FORMAT_BIN)
+ {
+ /* Convert the structure parameters to Binary format */
+ RTC_TimeStruct->Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->Hours);
+ RTC_TimeStruct->Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->Minutes);
+ RTC_TimeStruct->Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->Seconds);
+ }
+}
+
+/**
+ * @brief Gets the RTC current Calendar Subseconds value.
+ * @return RTC current Calendar Subseconds value.
+ */
+uint32_t RTC_GetSubSecond(void)
+{
+ uint32_t tmpregister = 0;
+
+ /* Get subseconds values from the correspondent registers*/
+ tmpregister = (uint32_t)(RTC->SUBS);
+
+ return (tmpregister);
+}
+
+/**
+ * @brief Set the RTC current date.
+ * @param RTC_Format specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN Binary data format.
+ * @arg RTC_FORMAT_BCD BCD data format.
+ * @param RTC_DateStruct pointer to a RTC_DateType structure that contains
+ * the date configuration information for the RTC.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Date register is configured
+ * - ERROR: RTC Date register is not configured
+ */
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct)
+{
+ uint32_t tmpregister = 0;
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+
+ if ((RTC_Format == RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10) == 0x10))
+ {
+ RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint32_t) ~(0x10)) + 0x0A;
+ }
+ if (RTC_Format == RTC_FORMAT_BIN)
+ {
+ assert_param(IS_RTC_YEAR(RTC_DateStruct->Year));
+ assert_param(IS_RTC_MONTH(RTC_DateStruct->Month));
+ assert_param(IS_RTC_DATE(RTC_DateStruct->Date));
+ }
+ else
+ {
+ assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->Year)));
+ tmpregister = RTC_Bcd2ToByte(RTC_DateStruct->Month);
+ assert_param(IS_RTC_MONTH(tmpregister));
+ tmpregister = RTC_Bcd2ToByte(RTC_DateStruct->Date);
+ assert_param(IS_RTC_DATE(tmpregister));
+ }
+ assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->WeekDay));
+
+ /* Check the input parameters format */
+ if (RTC_Format != RTC_FORMAT_BIN)
+ {
+ tmpregister = ((((uint32_t)RTC_DateStruct->Year) << 16) | (((uint32_t)RTC_DateStruct->Month) << 8)
+ | ((uint32_t)RTC_DateStruct->Date) | (((uint32_t)RTC_DateStruct->WeekDay) << 13));
+ }
+ else
+ {
+ tmpregister = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->Year) << 16)
+ | ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->Month) << 8)
+ | ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->Date)) | ((uint32_t)RTC_DateStruct->WeekDay << 13));
+ }
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Set Initialization mode */
+ if (RTC_EnterInitMode() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ /* Set the RTC_DATE register */
+ RTC->DATE = (uint32_t)(tmpregister & RTC_DATE_RESERVED_MASK);
+
+ /* Exit Initialization mode */
+ RTC_ExitInitMode();
+
+ /* If RTC_CTRL_BYPS bit = 0, wait for synchro else this check is not needed */
+ if ((RTC->CTRL & RTC_CTRL_BYPS) == RESET)
+ {
+ if (RTC_WaitForSynchro() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+ /* Waits until the RTC Time and Date registers
+ (RTC_TSH and RTC_DATE) are synchronized with RTC APB clock. */
+ status=RTC_WaitForSynchro();
+ return status;
+}
+
+/**
+ * @brief Fills each RTC_DateStruct member with its default value
+ * (Monday, January 01 xx00).
+ * @param RTC_DateStruct pointer to a RTC_DateType structure which will be
+ * initialized.
+ */
+void RTC_DateStructInit(RTC_DateType* RTC_DateStruct)
+{
+ /* Monday, January 01 xx00 */
+ RTC_DateStruct->WeekDay = RTC_WEEKDAY_MONDAY;
+ RTC_DateStruct->Date = 1;
+ RTC_DateStruct->Month = RTC_MONTH_JANUARY;
+ RTC_DateStruct->Year = 0;
+}
+
+/**
+ * @brief Get the RTC current date.
+ * @param RTC_Format specifies the format of the returned parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN Binary data format.
+ * @arg RTC_FORMAT_BCD BCD data format.
+ * @param RTC_DateStruct pointer to a RTC_DateType structure that will
+ * contain the returned current date configuration.
+ */
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+
+ /* Get the RTC_TSH register */
+ tmpregister = (uint32_t)(RTC->DATE & RTC_DATE_RESERVED_MASK);
+
+ /* Fill the structure fields with the read parameters */
+ RTC_DateStruct->Year = (uint8_t)((tmpregister & (RTC_DATE_YRT | RTC_DATE_YRU)) >> 16);
+ RTC_DateStruct->Month = (uint8_t)((tmpregister & (RTC_DATE_MOT | RTC_DATE_MOU)) >> 8);
+ RTC_DateStruct->Date = (uint8_t)(tmpregister & (RTC_DATE_DAT | RTC_DATE_DAU));
+ RTC_DateStruct->WeekDay = (uint8_t)((tmpregister & (RTC_DATE_WDU)) >> 13);
+
+ /* Check the input parameters format */
+ if (RTC_Format == RTC_FORMAT_BIN)
+ {
+ /* Convert the structure parameters to Binary format */
+ RTC_DateStruct->Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->Year);
+ RTC_DateStruct->Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->Month);
+ RTC_DateStruct->Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->Date);
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group3 Alarms configuration functions
+ * @brief Alarms (Alarm A and Alarm B) configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Alarms (Alarm A and Alarm B) configuration functions #####
+ ===============================================================================
+ [..] This section provide functions allowing to program and read the RTC
+ Alarms.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set the specified RTC Alarm.
+ * @note The Alarm register can only be written when the corresponding Alarm
+ * is disabled (Use the RTC_EnableAlarm(DISABLE)).
+ * @param RTC_Format specifies the format of the returned parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN Binary data format.
+ * @arg RTC_FORMAT_BCD BCD data format.
+ * @param RTC_Alarm specifies the alarm to be configured.
+ * This parameter can be one of the following values:
+ * @arg RTC_A_ALARM to select Alarm A.
+ * @arg RTC_B_ALARM to select Alarm B.
+ * @param RTC_AlarmStruct pointer to a RTC_AlarmType structure that
+ * contains the alarm configuration parameters.
+ */
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+ assert_param(IS_RTC_ALARM_SEL(RTC_Alarm));
+ assert_param(IS_ALARM_MASK(RTC_AlarmStruct->AlarmMask));
+ assert_param(IS_RTC_ALARM_WEEKDAY_SEL(RTC_AlarmStruct->DateWeekMode));
+
+ if (RTC_Format == RTC_FORMAT_BIN)
+ {
+ if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET)
+ {
+ assert_param(IS_RTC_12HOUR(RTC_AlarmStruct->AlarmTime.Hours));
+ assert_param(IS_RTC_H12(RTC_AlarmStruct->AlarmTime.H12));
+ }
+ else
+ {
+ RTC_AlarmStruct->AlarmTime.H12 = 0x00;
+ assert_param(IS_RTC_24HOUR(RTC_AlarmStruct->AlarmTime.Hours));
+ }
+ assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
+ assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
+
+ if (RTC_AlarmStruct->DateWeekMode == RTC_ALARM_SEL_WEEKDAY_DATE)
+ {
+ assert_param(IS_RTC_ALARM_WEEKDAY_DATE(RTC_AlarmStruct->DateWeekValue));
+ }
+ else
+ {
+ assert_param(IS_RTC_ALARM_WEEKDAY_WEEKDAY(RTC_AlarmStruct->DateWeekValue));
+ }
+ }
+ else
+ {
+ if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET)
+ {
+ tmpregister = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Hours);
+ assert_param(IS_RTC_12HOUR(tmpregister));
+ assert_param(IS_RTC_H12(RTC_AlarmStruct->AlarmTime.H12));
+ }
+ else
+ {
+ RTC_AlarmStruct->AlarmTime.H12 = 0x00;
+ assert_param(IS_RTC_24HOUR(RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Hours)));
+ }
+
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Seconds)));
+
+ if (RTC_AlarmStruct->DateWeekMode == RTC_ALARM_SEL_WEEKDAY_DATE)
+ {
+ tmpregister = RTC_Bcd2ToByte(RTC_AlarmStruct->DateWeekValue);
+ assert_param(IS_RTC_ALARM_WEEKDAY_DATE(tmpregister));
+ }
+ else
+ {
+ tmpregister = RTC_Bcd2ToByte(RTC_AlarmStruct->DateWeekValue);
+ assert_param(IS_RTC_ALARM_WEEKDAY_WEEKDAY(tmpregister));
+ }
+ }
+
+ /* Check the input parameters format */
+ if (RTC_Format != RTC_FORMAT_BIN)
+ {
+ tmpregister =
+ (((uint32_t)(RTC_AlarmStruct->AlarmTime.Hours) << 16)
+ | ((uint32_t)(RTC_AlarmStruct->AlarmTime.Minutes) << 8) | ((uint32_t)RTC_AlarmStruct->AlarmTime.Seconds)
+ | ((uint32_t)(RTC_AlarmStruct->AlarmTime.H12) << 16) | ((uint32_t)(RTC_AlarmStruct->DateWeekValue) << 24)
+ | ((uint32_t)RTC_AlarmStruct->DateWeekMode) | ((uint32_t)RTC_AlarmStruct->AlarmMask));
+ }
+ else
+ {
+ tmpregister = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->AlarmTime.Hours) << 16)
+ | ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->AlarmTime.Minutes) << 8)
+ | ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->AlarmTime.Seconds))
+ | ((uint32_t)(RTC_AlarmStruct->AlarmTime.H12) << 16)
+ | ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->DateWeekValue) << 24)
+ | ((uint32_t)RTC_AlarmStruct->DateWeekMode) | ((uint32_t)RTC_AlarmStruct->AlarmMask));
+ }
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Configure the Alarm register */
+ if (RTC_Alarm == RTC_A_ALARM)
+ {
+ RTC->ALARMA = (uint32_t)tmpregister;
+ }
+ else
+ {
+ RTC->ALARMB = (uint32_t)tmpregister;
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Fills each RTC_AlarmStruct member with its default value
+ * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask =
+ * all fields are masked).
+ * @param RTC_AlarmStruct pointer to a @ref RTC_AlarmType structure which
+ * will be initialized.
+ */
+void RTC_AlarmStructInit(RTC_AlarmType* RTC_AlarmStruct)
+{
+ /* Alarm Time Settings : Time = 00h:00mn:00sec */
+ RTC_AlarmStruct->AlarmTime.H12 = RTC_AM_H12;
+ RTC_AlarmStruct->AlarmTime.Hours = 0;
+ RTC_AlarmStruct->AlarmTime.Minutes = 0;
+ RTC_AlarmStruct->AlarmTime.Seconds = 0;
+
+ /* Alarm Date Settings : Date = 1st day of the month */
+ RTC_AlarmStruct->DateWeekMode = RTC_ALARM_SEL_WEEKDAY_DATE;
+ RTC_AlarmStruct->DateWeekValue = 1;
+
+ /* Alarm Masks Settings : Mask = all fields are not masked */
+ RTC_AlarmStruct->AlarmMask = RTC_ALARMMASK_NONE;
+}
+
+/**
+ * @brief Get the RTC Alarm value and masks.
+ * @param RTC_Format specifies the format of the output parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN Binary data format.
+ * @arg RTC_FORMAT_BCD BCD data format.
+ * @param RTC_Alarm specifies the alarm to be read.
+ * This parameter can be one of the following values:
+ * @arg RTC_A_ALARM to select Alarm A.
+ * @arg RTC_B_ALARM to select Alarm B.
+ * @param RTC_AlarmStruct pointer to a RTC_AlarmType structure that will
+ * contains the output alarm configuration values.
+ */
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+ assert_param(IS_RTC_ALARM_SEL(RTC_Alarm));
+
+ /* Get the RTC_ALARMx register */
+ if (RTC_Alarm == RTC_A_ALARM)
+ {
+ tmpregister = (uint32_t)(RTC->ALARMA);
+ }
+ else
+ {
+ tmpregister = (uint32_t)(RTC->ALARMB);
+ }
+
+ /* Fill the structure with the read parameters */
+ RTC_AlarmStruct->AlarmTime.Hours = (uint32_t)((tmpregister & (RTC_ALARMA_HOT | RTC_ALARMA_HOU)) >> 16);
+ RTC_AlarmStruct->AlarmTime.Minutes = (uint32_t)((tmpregister & (RTC_ALARMA_MIT | RTC_ALARMA_MIU)) >> 8);
+ RTC_AlarmStruct->AlarmTime.Seconds = (uint32_t)(tmpregister & (RTC_ALARMA_SET | RTC_ALARMA_SEU));
+ RTC_AlarmStruct->AlarmTime.H12 = (uint32_t)((tmpregister & RTC_ALARMA_APM) >> 16);
+ RTC_AlarmStruct->DateWeekValue = (uint32_t)((tmpregister & (RTC_ALARMA_DTT | RTC_ALARMA_DTU)) >> 24);
+ RTC_AlarmStruct->DateWeekMode = (uint32_t)(tmpregister & RTC_ALARMA_WKDSEL);
+ RTC_AlarmStruct->AlarmMask = (uint32_t)(tmpregister & RTC_ALARMMASK_ALL);
+
+ if (RTC_Format == RTC_FORMAT_BIN)
+ {
+ RTC_AlarmStruct->AlarmTime.Hours = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Hours);
+ RTC_AlarmStruct->AlarmTime.Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Minutes);
+ RTC_AlarmStruct->AlarmTime.Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Seconds);
+ RTC_AlarmStruct->DateWeekValue = RTC_Bcd2ToByte(RTC_AlarmStruct->DateWeekValue);
+ }
+}
+
+/**
+ * @brief Enables or disables the specified RTC Alarm.
+ * @param RTC_Alarm specifies the alarm to be configured.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_A_ALARM to select Alarm A.
+ * @arg RTC_B_ALARM to select Alarm B.
+ * @param Cmd new state of the specified alarm.
+ * This parameter can be: ENABLE or DISABLE.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Alarm is enabled/disabled
+ * - ERROR: RTC Alarm is not enabled/disabled
+ */
+ErrorStatus RTC_EnableAlarm(uint32_t RTC_Alarm, FunctionalState Cmd)
+{
+ __IO uint32_t alarmcounter = 0x00;
+ uint32_t alarmstatus = 0x00;
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALARM_ENABLE(RTC_Alarm));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Configure the Alarm state */
+ if (Cmd != DISABLE)
+ {
+ RTC->CTRL |= (uint32_t)RTC_Alarm;
+
+ status = SUCCESS;
+ }
+ else
+ {
+ /* Disable the Alarm in RTC_CTRL register */
+ RTC->CTRL &= (uint32_t)~RTC_Alarm;
+
+ /* Wait till RTC ALxWF flag is set and if Time out is reached exit */
+ do
+ {
+ alarmstatus = RTC->INITSTS & (RTC_Alarm >> 8);
+ alarmcounter++;
+ } while ((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00));
+
+ if ((RTC->INITSTS & (RTC_Alarm >> 8)) == RESET)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+
+ return status;
+}
+
+/**
+ * @brief Configure the RTC AlarmA/B Subseconds value and mask.*
+ * @note This function is performed only when the Alarm is disabled.
+ * @param RTC_Alarm specifies the alarm to be configured.
+ * This parameter can be one of the following values:
+ * @arg RTC_A_ALARM to select Alarm A.
+ * @arg RTC_B_ALARM to select Alarm B.
+ * @param RTC_AlarmSubSecondValue specifies the Subseconds value.
+ * This parameter can be a value from 0 to 0x00007FFF.
+ * @param RTC_AlarmSubSecondMask specifies the Subseconds Mask.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_SUBS_MASK_ALL All Alarm SS fields are masked.
+ * There is no comparison on sub seconds for Alarm.
+ * @arg RTC_SUBS_MASK_SS14_1 SS[14:1] are don't care in Alarm comparison.
+ * Only SS[0] is compared
+ * @arg RTC_SUBS_MASK_SS14_2 SS[14:2] are don't care in Alarm comparison.
+ * Only SS[1:0] are compared
+ * @arg RTC_SUBS_MASK_SS14_3 SS[14:3] are don't care in Alarm comparison.
+ * Only SS[2:0] are compared
+ * @arg RTC_SUBS_MASK_SS14_4 SS[14:4] are don't care in Alarm comparison.
+ * Only SS[3:0] are compared
+ * @arg RTC_SUBS_MASK_SS14_5 SS[14:5] are don't care in Alarm comparison.
+ * Only SS[4:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_6 SS[14:6] are don't care in Alarm comparison.
+ * Only SS[5:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_7 SS[14:7] are don't care in Alarm comparison.
+ * Only SS[6:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_8 SS[14:8] are don't care in Alarm comparison.
+ * Only SS[7:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_9 SS[14:9] are don't care in Alarm comparison.
+ * Only SS[8:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_10 SS[14:10] are don't care in Alarm comparison.
+ * Only SS[9:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_11 SS[14:11] are don't care in Alarm comparison.
+ * Only SS[10:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_12 SS[14:12] are don't care in Alarm comparison.
+ * Only SS[11:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_13 SS[14:13] are don't care in Alarm comparison.
+ * Only SS[12:0] are compared.
+ * @arg RTC_SUBS_MASK_SS14_14 SS[14] is don't care in Alarm comparison.
+ * Only SS[13:0] are compared.
+ * @arg RTC_SUBS_MASK_NONE SS[14:0] are compared and must match
+ * to activate alarm.
+ */
+void RTC_ConfigAlarmSubSecond(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALARM_SEL(RTC_Alarm));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_MASK_MODE(RTC_AlarmSubSecondMask));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Configure the Alarm A or Alarm B SubSecond registers */
+ tmpregister = (uint32_t)(uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask);
+
+ if (RTC_Alarm == RTC_A_ALARM)
+ {
+ /* Configure the AlarmA SubSecond register */
+ RTC->ALRMASS = tmpregister;
+ }
+ else
+ {
+ /* Configure the Alarm B SubSecond register */
+ RTC->ALRMBSS = tmpregister;
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Gets the RTC Alarm Subseconds value.
+ * @param RTC_Alarm specifies the alarm to be read.
+ * This parameter can be one of the following values:
+ * @arg RTC_A_ALARM to select Alarm A.
+ * @arg RTC_B_ALARM to select Alarm B.
+ * @return RTC Alarm Subseconds value.
+ */
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm)
+{
+ uint32_t tmpregister = 0;
+
+ /* Get the RTC_ALARMx register */
+ if (RTC_Alarm == RTC_A_ALARM)
+ {
+ tmpregister = (uint32_t)((RTC->ALRMASS) & RTC_ALRMASS_SSV);
+ }
+ else
+ {
+ tmpregister = (uint32_t)((RTC->ALRMBSS) & RTC_ALRMBSS_SSV);
+ }
+
+ return (tmpregister);
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group4 WakeUp Timer configuration functions
+ * @brief WakeUp Timer configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### WakeUp Timer configuration functions #####
+ ===============================================================================
+ [..] This section provide functions allowing to program and read the RTC WakeUp.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the RTC Wakeup clock source.
+ * @note The WakeUp Clock source can only be changed when the RTC WakeUp
+ * is disabled (Use the RTC_EnableWakeUp(DISABLE)).
+ * @param RTC_WakeUpClock Wakeup Clock source.
+ * This parameter can be one of the following values:
+ * @arg RTC_WKUPCLK_RTCCLK_DIV16 RTC Wakeup Counter Clock = RTCCLK/16.
+ * @arg RTC_WKUPCLK_RTCCLK_DIV8 RTC Wakeup Counter Clock = RTCCLK/8.
+ * @arg RTC_WKUPCLK_RTCCLK_DIV4 RTC Wakeup Counter Clock = RTCCLK/4.
+ * @arg RTC_WKUPCLK_RTCCLK_DIV2 RTC Wakeup Counter Clock = RTCCLK/2.
+ * @arg RTC_WKUPCLK_CK_SPRE_16BITS RTC Wakeup Counter Clock = CK_SPRE.
+ */
+void RTC_ConfigWakeUpClock(uint32_t RTC_WakeUpClock)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_WKUP_CLOCK(RTC_WakeUpClock));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Clear the Wakeup Timer clock source bits in CTRL register */
+ RTC->CTRL &= (uint32_t)~RTC_CTRL_WKUPSEL;
+
+ /* Configure the clock source */
+ RTC->CTRL |= (uint32_t)RTC_WakeUpClock;
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Configures the RTC Wakeup counter.
+ * @note The RTC WakeUp counter can only be written when the RTC WakeUp.
+ * is disabled (Use the RTC_EnableWakeUp(DISABLE)).
+ * @param RTC_WakeUpCounter specifies the WakeUp counter.
+ * This parameter can be a value from 0x0000 to 0xFFFF.
+ */
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_WKUP_COUNTER(RTC_WakeUpCounter));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Configure the Wakeup Timer counter */
+ RTC->WKUPT = (uint32_t)RTC_WakeUpCounter;
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Returns the RTC WakeUp timer counter value.
+ * @return The RTC WakeUp Counter value.
+ */
+uint32_t RTC_GetWakeUpCounter(void)
+{
+ /* Get the counter value */
+ return ((uint32_t)(RTC->WKUPT & RTC_WKUPT_WKUPT));
+}
+
+/**
+ * @brief Enables or Disables the RTC WakeUp timer.
+ * @param Cmd new state of the WakeUp timer.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+ErrorStatus RTC_EnableWakeUp(FunctionalState Cmd)
+{
+ __IO uint32_t wutcounter = 0x00;
+ uint32_t wutwfstatus = 0x00;
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the Wakeup Timer */
+ RTC->CTRL |= (uint32_t)RTC_CTRL_WTEN;
+ status = SUCCESS;
+ }
+ else
+ {
+ /* Disable the Wakeup Timer */
+ RTC->CTRL &= (uint32_t)~RTC_CTRL_WTEN;
+ /* Wait till RTC WTWF flag is set and if Time out is reached exit */
+ do
+ {
+ wutwfstatus = RTC->INITSTS & RTC_INITSTS_WTWF;
+ wutcounter++;
+ } while ((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
+
+ if ((RTC->INITSTS & RTC_INITSTS_WTWF) == RESET)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group5 Daylight Saving configuration functions
+ * @brief Daylight Saving configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Daylight Saving configuration functions #####
+ ===============================================================================
+ [..] This section provide functions allowing to configure the RTC DayLight Saving.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Adds or substract one hour from the current time.
+ * @param RTC_DayLightSaving the value of hour adjustment.
+ * This parameter can be one of the following values:
+ * @arg RTC_DAYLIGHT_SAVING_SUB1H Substract one hour (winter time).
+ * @arg RTC_DAYLIGHT_SAVING_ADD1H Add one hour (summer time).
+ * @param RTC_StoreOperation Specifies the value to be written in the BCK bit
+ * in CTRL register to store the operation.
+ * This parameter can be one of the following values:
+ * @arg RTC_STORE_OPERATION_RESET BCK Bit Reset.
+ * @arg RTC_STORE_OPERATION_SET BCK Bit Set.
+ */
+void RTC_ConfigDayLightSaving(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving));
+ assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Clear the bits to be configured */
+ RTC->CTRL &= (uint32_t) ~(RTC_CTRL_BAKP);
+ /* Clear the SU1H and AD1H bits to be configured */
+ RTC->CTRL &= (uint32_t) ~(RTC_CTRL_SU1H & RTC_CTRL_AD1H);
+ /* Configure the RTC_CTRL register */
+ RTC->CTRL |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation);
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Returns the RTC Day Light Saving stored operation.
+ * @return RTC Day Light Saving stored operation.
+ * - RTC_STORE_OPERATION_RESET
+ * - RTC_STORE_OPERATION_SET
+ */
+uint32_t RTC_GetStoreOperation(void)
+{
+ return (RTC->CTRL & RTC_CTRL_BAKP);
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group6 Output pin Configuration function
+ * @brief Output pin Configuration function
+ *
+@verbatim
+ ===============================================================================
+ ##### Output pin Configuration function #####
+ ===============================================================================
+ [..] This section provide functions allowing to configure the RTC Output source.
+
+@endverbatim
+ * @{
+ */
+
+
+
+/**
+ * @brief Configures the RTC output source (AFO_ALARM).
+ * @param RTC_Output Specifies which signal will be routed to the RTC output.
+ * This parameter can be one of the following values:
+ * @arg RTC_OUTPUT_DIS No output selected
+ * @arg RTC_OUTPUT_ALA signal of AlarmA mapped to output.
+ * @arg RTC_OUTPUT_ALB signal of AlarmB mapped to output.
+ * @arg RTC_OUTPUT_WKUP signal of WakeUp mapped to output.
+ * @param RTC_OutputPolarity Specifies the polarity of the output signal.
+ * This parameter can be one of the following:
+ * @arg RTC_OUTPOL_HIGH The output pin is high when the
+ * ALRAF/ALRBF/WUTF is high (depending on OSEL).
+ * @arg RTC_OUTPOL_LOW The output pin is low when the
+ * ALRAF/ALRBF/WUTF is high (depending on OSEL).
+ */
+void RTC_ConfigOutput(uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_OUTPUT_MODE(RTC_Output));
+ assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Clear the bits to be configured */
+ RTC->CTRL &= (uint32_t) ~(RTC_CTRL_OUTSEL | RTC_CTRL_OPOL);
+
+ /* Configure the output selection and polarity */
+ RTC->CTRL |= (uint32_t)(RTC_Output | RTC_OutputPolarity);
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group7 Coarse and Smooth Calibrations configuration functions
+ * @brief Coarse and Smooth Calibrations configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Coarse and Smooth Calibrations configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the RTC clock to be output through the relative
+ * pin.
+ * @param Cmd new state of the coarse calibration Output.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RTC_EnableCalibOutput(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the RTC clock output */
+ RTC->CTRL |= (uint32_t)RTC_CTRL_COEN;
+ }
+ else
+ {
+ /* Disable the RTC clock output */
+ RTC->CTRL &= (uint32_t)~RTC_CTRL_COEN;
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ * @param RTC_CalibOutput Select the Calibration output Selection .
+ * This parameter can be one of the following values:
+ * @arg RTC_CALIB_OUTPUT_256HZ A signal has a regular waveform at 256Hz.
+ * @arg RTC_CALIB_OUTPUT_1HZ A signal has a regular waveform at 1Hz.
+ */
+void RTC_ConfigCalibOutput(uint32_t RTC_CalibOutput)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /*clear flags before config*/
+ RTC->CTRL &= (uint32_t) ~(RTC_CTRL_CALOSEL);
+
+ /* Configure the RTC_CTRL register */
+ RTC->CTRL |= (uint32_t)RTC_CalibOutput;
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Configures the Smooth Calibration Settings.
+ * @param RTC_SmoothCalibPeriod Select the Smooth Calibration Period.
+ * This parameter can be can be one of the following values:
+ * @arg SMOOTH_CALIB_32SEC The smooth calibration periode is 32s.
+ * @arg SMOOTH_CALIB_16SEC The smooth calibration periode is 16s.
+ * @arg SMOOTH_CALIB_8SEC The smooth calibartion periode is 8s.
+ * @param RTC_SmoothCalibPlusPulses Select to Set or reset the CALP bit.
+ * This parameter can be one of the following values:
+ * @arg RTC_SMOOTH_CALIB_PLUS_PULSES_SET Add one RTCCLK puls every 2**11 pulses.
+ * @arg RTC_SMOOTH_CALIB_PLUS_PULSES__RESET No RTCCLK pulses are added.
+ * @param RTC_SmouthCalibMinusPulsesValue Select the value of CALM[8:0] bits.
+ * This parameter can be one any value from 0 to 0x000001FF.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Calib registers are configured
+ * - ERROR: RTC Calib registers are not configured
+ */
+ErrorStatus RTC_ConfigSmoothCalib(uint32_t RTC_SmoothCalibPeriod,
+ uint32_t RTC_SmoothCalibPlusPulses,
+ uint32_t RTC_SmouthCalibMinusPulsesValue)
+{
+ ErrorStatus status = ERROR;
+ uint32_t recalpfcount = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_SMOOTH_CALIB_PERIOD_SEL(RTC_SmoothCalibPeriod));
+ assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses));
+ assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* check if a calibration is pending*/
+ if ((RTC->INITSTS & RTC_INITSTS_RECPF) != RESET)
+ {
+ /* wait until the Calibration is completed*/
+ while (((RTC->INITSTS & RTC_INITSTS_RECPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT))
+ {
+ recalpfcount++;
+ }
+ }
+
+ /* check if the calibration pending is completed or if there is no calibration operation at all*/
+ if ((RTC->INITSTS & RTC_INITSTS_RECPF) == RESET)
+ {
+ /* Configure the Smooth calibration settings */
+ RTC->CALIB = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses
+ | (uint32_t)RTC_SmouthCalibMinusPulsesValue);
+
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+
+ return (ErrorStatus)(status);
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group8 TimeStamp configuration functions
+ * @brief TimeStamp configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### TimeStamp configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or Disables the RTC TimeStamp functionality with the
+ * specified time stamp pin stimulating edge.
+ * @param RTC_TimeStampEdge Specifies the pin edge on which the TimeStamp is
+ * activated.
+ * This parameter can be one of the following:
+ * @arg RTC_TIMESTAMP_EDGE_RISING the Time stamp event occurs on the rising
+ * edge of the related pin.
+ * @arg RTC_TIMESTAMP_EDGE_FALLING the Time stamp event occurs on the
+ * falling edge of the related pin.
+ * @param Cmd new state of the TimeStamp.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RTC_EnableTimeStamp(uint32_t RTC_TimeStampEdge, FunctionalState Cmd)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_TIMESTAMP_EDGE_MODE(RTC_TimeStampEdge));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ /* Get the RTC_CTRL register and clear the bits to be configured */
+ tmpregister = (uint32_t)(RTC->CTRL & (uint32_t) ~(RTC_CTRL_TSPOL | RTC_CTRL_TSEN));
+
+ /* Get the new configuration */
+ if (Cmd != DISABLE)
+ {
+ tmpregister |= (uint32_t)(RTC_TimeStampEdge | RTC_CTRL_TSEN);
+ }
+ else
+ {
+ tmpregister |= (uint32_t)(RTC_TimeStampEdge);
+ }
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Configure the Time Stamp TSEDGE and Enable bits */
+ RTC->CTRL = (uint32_t)tmpregister;
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Get the RTC TimeStamp value and masks.
+ * @param RTC_Format specifies the format of the output parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN Binary data format
+ * @arg RTC_FORMAT_BCD BCD data format
+ * @param RTC_StampTimeStruct pointer to a RTC_TimeType structure that will
+ * contains the TimeStamp time values.
+ * @param RTC_StampDateStruct pointer to a RTC_DateType structure that will
+ * contains the TimeStamp date values.
+ */
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeType* RTC_StampTimeStruct, RTC_DateType* RTC_StampDateStruct)
+{
+ uint32_t tmptime = 0, tmpdate = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(RTC_Format));
+
+ /* Get the TimeStamp time and date registers values */
+ tmptime = (uint32_t)(RTC->TST & RTC_TR_RESERVED_MASK);
+ tmpdate = (uint32_t)(RTC->TSD & RTC_DATE_RESERVED_MASK);
+
+ /* Fill the Time structure fields with the read parameters */
+ RTC_StampTimeStruct->Hours = (uint8_t)((tmptime & (RTC_TSH_HOT | RTC_TSH_HOU)) >> 16);
+ RTC_StampTimeStruct->Minutes = (uint8_t)((tmptime & (RTC_TSH_MIT | RTC_TSH_MIU)) >> 8);
+ RTC_StampTimeStruct->Seconds = (uint8_t)(tmptime & (RTC_TSH_SCT | RTC_TSH_SCU));
+ RTC_StampTimeStruct->H12 = (uint8_t)((tmptime & (RTC_TSH_APM)) >> 16);
+
+ /* Fill the Date structure fields with the read parameters */
+ RTC_StampDateStruct->Year = (uint8_t)((tmpdate & (RTC_DATE_YRT | RTC_DATE_YRU)) >> 16);
+ RTC_StampDateStruct->Month = (uint8_t)((tmpdate & (RTC_DATE_MOT | RTC_DATE_MOU)) >> 8);
+ RTC_StampDateStruct->Date = (uint8_t)(tmpdate & (RTC_DATE_DAT | RTC_DATE_DAU));
+ RTC_StampDateStruct->WeekDay = (uint8_t)((tmpdate & (RTC_DATE_WDU)) >> 13);
+
+ /* Check the input parameters format */
+ if (RTC_Format == RTC_FORMAT_BIN)
+ {
+ /* Convert the Time structure parameters to Binary format */
+ RTC_StampTimeStruct->Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->Hours);
+ RTC_StampTimeStruct->Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->Minutes);
+ RTC_StampTimeStruct->Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->Seconds);
+
+ /* Convert the Date structure parameters to Binary format */
+ RTC_StampDateStruct->Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->Month);
+ RTC_StampDateStruct->Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->Date);
+ RTC_StampDateStruct->WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->WeekDay);
+ }
+}
+
+/**
+ * @brief Get the RTC timestamp Subseconds value.
+ * @return RTC current timestamp Subseconds value.
+ */
+uint32_t RTC_GetTimeStampSubSecond(void)
+{
+ /* Get timestamp subseconds values from the correspondent registers */
+ return (uint32_t)(RTC->TSSS);
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group11 Output Type Config configuration functions
+ * @brief Output Type Config configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Output Type Config configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the RTC Output Pin mode.
+ * @param RTC_OutputType specifies the RTC Output (PC13) pin mode.
+ * This parameter can be one of the following values:
+ * @arg RTC_OUTPUT_OPENDRAIN RTC Output (PC13) is configured in
+ * Open Drain mode.
+ * @arg RTC_OUTPUT_PUSHPULL RTC Output (PC13) is configured in
+ * Push Pull mode.
+ */
+void RTC_ConfigOutputType(uint32_t RTC_OutputType)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType));
+
+ RTC->OPT &= (uint32_t) ~(RTC_OPT_TYPE);
+ RTC->OPT |= (uint32_t)(RTC_OutputType);
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group12 Shift control synchronisation functions
+ * @brief Shift control synchronisation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Shift control synchronisation functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the Synchronization Shift Control Settings.
+ * @note When REFCKON is set, firmware must not write to Shift control register
+ * @param RTC_ShiftAdd1S Select to add or not 1 second to the time Calendar.
+ * This parameter can be one of the following values :
+ * @arg RTC_SHIFT_SUB1S_DISABLE Add one second to the clock calendar.
+ * @arg RTC_SHIFT_SUB1S_ENABLE No effect.
+ * @param RTC_ShiftAddFS Select the number of Second Fractions to Substitute.
+ * This parameter can be one any value from 0 to 0x7FFF.
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Shift registers are configured
+ * - ERROR: RTC Shift registers are not configured
+ */
+ErrorStatus RTC_ConfigSynchroShift(uint32_t RTC_ShiftAddFS, uint32_t RTC_ShiftSub1s)
+{
+ ErrorStatus status = ERROR;
+ uint32_t shpfcount = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_SHIFT_ADFS(RTC_ShiftAddFS));
+ assert_param(IS_RTC_SHIFT_SUB1S(RTC_ShiftSub1s));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ /* Check if a Shift is pending*/
+ if ((RTC->INITSTS & RTC_INITSTS_SHOPF) != RESET)
+ {
+ /* Wait until the shift is completed*/
+ while (((RTC->INITSTS & RTC_INITSTS_SHOPF) != RESET) && (shpfcount != SHPF_TIMEOUT))
+ {
+ shpfcount++;
+ }
+ }
+
+ /* Check if the Shift pending is completed or if there is no Shift operation at all*/
+ if ((RTC->INITSTS & RTC_INITSTS_SHOPF) == RESET)
+ {
+
+ {
+ /* Configure the Shift settings */
+ RTC->SCTRL = (uint32_t)(uint32_t)(RTC_ShiftAddFS) | (uint32_t)(RTC_ShiftSub1s);
+
+ if (RTC_WaitForSynchro() == ERROR)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+
+ return (ErrorStatus)(status);
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group13 Interrupts and flags management functions
+ * @brief Interrupts and flags management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupts and flags management functions #####
+ ===============================================================================
+ [..] All RTC interrupts are connected to the EXTI controller.
+ (+) To enable the RTC Alarm interrupt, the following sequence is required:
+ (+) Configure and enable the EXTI Line 17 in interrupt mode and select
+ the rising edge sensitivity using the EXTI_InitPeripheral() function.
+ (+) Configure and enable the RTC_Alarm IRQ channel in the NVIC using
+ the NVIC_Init() function.
+ (+) Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B)
+ using the RTC_SetAlarm() and RTC_EnableAlarm() functions.
+
+ (+) To enable the RTC Wakeup interrupt, the following sequence is required:
+ (+) Configure and enable the EXTI Line 20 in interrupt mode and select
+ the rising edge sensitivity using the EXTI_InitPeripheral() function.
+ (+) Configure and enable the RTC_WKUP IRQ channel in the NVIC using the
+ NVIC_Init() function.
+ (+) Configure the RTC to generate the RTC wakeup timer event using the
+ RTC_ConfigWakeUpClock(), RTC_SetWakeUpCounter() and RTC_EnableWakeUp()
+ functions.
+
+ (+) To enable the RTC Tamper interrupt, the following sequence is required:
+ (+) Configure and enable the EXTI Line 19 in interrupt mode and select
+ the rising edge sensitivity using the EXTI_InitPeripheral() function.
+ (+) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using
+ the NVIC_Init() function.
+ (+) Configure the RTC to detect the RTC tamper event using the
+ RTC_TamperTriggerConfig() and RTC_TamperCmd() functions.
+
+ (+) To enable the RTC TimeStamp interrupt, the following sequence is
+ required:
+ (+) Configure and enable the EXTI Line 19 in interrupt mode and select
+ the rising edge sensitivity using the EXTI_InitPeripheral() function.
+ (+) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using
+ the NVIC_Init() function.
+ (+) Configure the RTC to detect the RTC time-stamp event using the
+ RTC_EnableTimeStamp() functions.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the specified RTC interrupts.
+ * @param RTC_INT specifies the RTC interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_INT_WUT WakeUp Timer interrupt mask.
+ * @arg RTC_INT_ALRB Alarm B interrupt mask.
+ * @arg RTC_INT_ALRA Alarm A interrupt mask.
+ * @param Cmd new state of the specified RTC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void RTC_ConfigInt(uint32_t RTC_INT, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_CONFIG_INT(RTC_INT));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ /* Disable the write protection for RTC registers */
+ RTC->WRP = 0xCA;
+ RTC->WRP = 0x53;
+
+ if (Cmd != DISABLE)
+ {
+ /* Configure the Interrupts in the RTC_CTRL register */
+ RTC->CTRL |= RTC_INT ;
+ }
+ else
+ {
+ /* Configure the Interrupts in the RTC_CTRL register */
+ RTC->CTRL &= (uint32_t) ~(RTC_INT);
+ }
+ /* Enable the write protection for RTC registers */
+ RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief Checks whether the specified RTC flag is set or not.
+ * @param RTC_FLAG specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg RTC_FLAG_RECPF RECALPF event flag.
+ * @arg RTC_FLAG_TISOVF Time Stamp OverFlow flag.
+ * @arg RTC_FLAG_TISF Time Stamp event flag.
+ * @arg RTC_FLAG_WTF WakeUp Timer flag.
+ * @arg RTC_FLAG_ALBF Alarm B flag.
+ * @arg RTC_FLAG_ALAF Alarm A flag.
+ * @arg RTC_FLAG_INITF Initialization mode flag.
+ * @arg RTC_FLAG_RSYF Registers Synchronized flag.
+ * @arg RTC_FLAG_INITSF Registers Configured flag.
+ * @arg RTC_FLAG_SHOPF Shift operation pending flag.
+ * @arg RTC_FLAG_WTWF WakeUp Timer Write flag.
+ * @arg RTC_FLAG_ALBWF Alarm B Write flag.
+ * @arg RTC_FLAG_ALAWF Alarm A write flag.
+ * @return The new state of RTC_FLAG (SET or RESET).
+ */
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
+
+ /* Get all the flags */
+ tmpregister = (uint32_t)(RTC->INITSTS & RTC_FLAGS_MASK);
+
+ /* Return the status of the flag */
+ if ((tmpregister & RTC_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RTC's pending flags.
+ * @param RTC_FLAG specifies the RTC flag to clear.
+ * This parameter can be any combination of the following values:.
+ * @arg RTC_FLAG_TISOVF Time Stamp Overflow flag.
+ * @arg RTC_FLAG_TISF Time Stamp event flag.
+ * @arg RTC_FLAG_WTF WakeUp Timer flag.
+ * @arg RTC_FLAG_ALBF Alarm B flag.
+ * @arg RTC_FLAG_ALAF Alarm A flag.
+ * @arg RTC_FLAG_RSYF Registers Synchronized flag.
+ */
+void RTC_ClrFlag(uint32_t RTC_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
+
+ /* Clear the Flags in the RTC_INITSTS register */
+ RTC->INITSTS = (uint32_t)(
+ (uint32_t)(~((RTC_FLAG | RTC_INITSTS_INITM) & 0x00011FFF) | (uint32_t)(RTC->INITSTS & RTC_INITSTS_INITM)));
+}
+
+/**
+ * @brief Checks whether the specified RTC interrupt has occurred or not.
+ * @param RTC_INT specifies the RTC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg RTC_INT_WUT WakeUp Timer interrupt.
+ * @arg RTC_INT_ALRB Alarm B interrupt.
+ * @arg RTC_INT_ALRA Alarm A interrupt.
+ * @return The new state of RTC_INT (SET or RESET).
+ */
+INTStatus RTC_GetITStatus(uint32_t RTC_INT)
+{
+ INTStatus bitstatus = RESET;
+ uint32_t tmpregister = 0, enablestatus = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_GET_INT(RTC_INT));
+
+ /* Get the Interrupt enable Status */
+ enablestatus = (uint32_t)((RTC->CTRL & RTC_INT));
+
+ /* Get the Interrupt pending bit */
+ tmpregister = (uint32_t)((RTC->INITSTS & (uint32_t)(RTC_INT >> 4)));
+
+ /* Get the status of the Interrupt */
+ if ((enablestatus != (uint32_t)RESET) && ((tmpregister & 0x0000FFFF) != (uint32_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RTC's interrupt pending bits.
+ * @param RTC_INT specifies the RTC interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_INT_WUT WakeUp Timer interrupt
+ * @arg RTC_INT_ALRB Alarm B interrupt
+ * @arg RTC_INT_ALRA Alarm A interrupt
+ */
+void RTC_ClrIntPendingBit(uint32_t RTC_INT)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_CLEAR_INT(RTC_INT));
+
+ /* Get the RTC_INITSTS Interrupt pending bits mask */
+ tmpregister = (uint32_t)(RTC_INT >> 4);
+
+ /* Clear the interrupt pending bits in the RTC_INITSTS register */
+ RTC->INITSTS = (uint32_t)(
+ (uint32_t)(~((tmpregister | RTC_INITSTS_INITM) & 0x0000FFFF) | (uint32_t)(RTC->INITSTS & RTC_INITSTS_INITM)));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief Converts a 2 digit decimal to BCD format.
+ * @param Value Byte to be converted.
+ * @return Converted byte
+ */
+static uint8_t RTC_ByteToBcd2(uint8_t Value)
+{
+ uint8_t bcdhigh = 0;
+
+ while (Value >= 10)
+ {
+ bcdhigh++;
+ Value -= 10;
+ }
+
+ return ((uint8_t)(bcdhigh << 4) | Value);
+}
+
+/**
+ * @brief Convert from 2 digit BCD to Binary.
+ * @param Value BCD value to be converted.
+ * @return Converted word
+ */
+static uint8_t RTC_Bcd2ToByte(uint8_t Value)
+{
+ uint8_t tmp = 0;
+ tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
+ return (tmp + (Value & (uint8_t)0x0F));
+}
+/**
+ * @brief Enable wakeup tsc functionand wakeup by the set time
+ * @param count wakeup time.
+ */
+void RTC_EnableWakeUpTsc(uint32_t count)
+{
+ // Wait until bit RTC_TSCWKUPCTRL_WKUPOFF is 1
+ while (!(RTC->TSCWKUPCTRL & RTC_TSCWKUPCTRL_WKUPOFF))
+ {
+ }
+ // enter config wakeup cnt mode
+ RTC->TSCWKUPCTRL = RTC_TSCWKUPCTRL_WKUPCNF;
+ // config tsc wakeup cnt ,tsc wakeup module counting cycle = WAKUPCNT * LSE/LSI
+ RTC->TSCWKUPCNT = count;
+ // exit config wakeup cnt mode
+ RTC->TSCWKUPCTRL &= ~(RTC_TSCWKUPCTRL_WKUPCNF);
+ while (!(RTC->TSCWKUPCTRL & RTC_TSCWKUPCTRL_WKUPOFF))
+ {
+ }
+ // TSC wakeup enable
+ RTC->TSCWKUPCTRL = RTC_TSCWKUPCTRL_WKUPEN;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_sdio.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_sdio.c
new file mode 100644
index 0000000000..d4c9544f7a
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_sdio.c
@@ -0,0 +1,789 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_sdio.c
+ * @author Nations
+ * @version v1.0.1
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32wb452_sdio.h"
+#include "n32wb452_rcc.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup SDIO
+ * @brief SDIO driver modules
+ * @{
+ */
+
+/** @addtogroup SDIO_Private_TypesDefinitions
+ * @{
+ */
+
+/* ------------ SDIO registers bit address in the alias region ----------- */
+#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
+
+/* --- CLKCTRL Register ---*/
+
+/* Alias word address of CLKEN bit */
+#define CLKCTRL_OFFSET (SDIO_OFFSET + 0x04)
+#define CLKEN_BIT_NUMBER 0x08
+#define CLKCTRL_CLKEN_BB (PERIPH_BB_BASE + (CLKCTRL_OFFSET * 32) + (CLKEN_BIT_NUMBER * 4))
+
+/* --- CMDCTRL Register ---*/
+
+/* Alias word address of SDIOSUSPEND bit */
+#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
+#define SDIO_SUSPEND_BIT_NUMBER 0x0B
+#define CMD_SDIO_SUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIO_SUSPEND_BIT_NUMBER * 4))
+
+/* Alias word address of ENCMDCOMPL bit */
+#define EN_CMD_COMPL_BIT_NUMBER 0x0C
+#define EN_CMD_COMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (EN_CMD_COMPL_BIT_NUMBER * 4))
+
+/* Alias word address of NIEN bit */
+#define NIEN_BIT_NUMBER 0x0D
+#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BIT_NUMBER * 4))
+
+/* Alias word address of ATACMD bit */
+#define ATACMD_BIT_NUMBER 0x0E
+#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BIT_NUMBER * 4))
+
+/* --- DATCTRL Register ---*/
+
+/* Alias word address of DMAEN bit */
+#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
+#define DMAEN_BIT_NUMBER 0x03
+#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BIT_NUMBER * 4))
+
+/* Alias word address of RWSTART bit */
+#define RWSTART_BIT_NUMBER 0x08
+#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BIT_NUMBER * 4))
+
+/* Alias word address of RWSTOP bit */
+#define RWSTOP_BIT_NUMBER 0x09
+#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BIT_NUMBER * 4))
+
+/* Alias word address of RWMOD bit */
+#define RWMOD_BIT_NUMBER 0x0A
+#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BIT_NUMBER * 4))
+
+/* Alias word address of SDIOEN bit */
+#define SDIOEN_BIT_NUMBER 0x0B
+#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BIT_NUMBER * 4))
+
+/* ---------------------- SDIO registers bit mask ------------------------ */
+
+/* --- CLKCTRL Register ---*/
+
+/* CLKCTRL register clear mask */
+#define CLKCTRL_CLR_MASK ((uint32_t)0xFFFF8100)
+
+/* --- PWRCTRL Register ---*/
+
+/* SDIO PWRCTRL Mask */
+#define POWER_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
+
+/* --- DATCTRL Register ---*/
+
+/* SDIO DATCTRL Clear Mask */
+#define DATCTRL_CLR_MASK ((uint32_t)0xFFFFFF08)
+
+/* --- CMDCTRL Register ---*/
+
+/* CMDCTRL Register clear mask */
+#define CMD_CLR_MASK ((uint32_t)0xFFFFF800)
+
+/* SDIO RESP Registers Address */
+#define SDID_RESPONSE_ADDR ((uint32_t)(SDIO_BASE + 0x14))
+
+/**
+ * @}
+ */
+
+/** @addtogroup SDIO_Private_Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SDIO_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SDIO_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SDIO_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SDIO_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the SDIO peripheral registers to their default reset values.
+ */
+void SDIO_DeInit(void)
+{
+ SDIO->PWRCTRL = 0x00000000;
+ SDIO->CLKCTRL = 0x00000000;
+ SDIO->CMDARG = 0x00000000;
+ SDIO->CMDCTRL = 0x00000000;
+ SDIO->DTIMER = 0x00000000;
+ SDIO->DATLEN = 0x00000000;
+ SDIO->DATCTRL = 0x00000000;
+ SDIO->INTCLR = 0x00C007FF;
+ SDIO->INTEN = 0x00000000;
+}
+
+/**
+ * @brief Initializes the SDIO peripheral according to the specified
+ * parameters in the SDIO_InitStruct.
+ * @param SDIO_InitStruct pointer to a SDIO_InitType structure
+ * that contains the configuration information for the SDIO peripheral.
+ */
+void SDIO_Init(SDIO_InitType* SDIO_InitStruct)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_CLK_EDGE(SDIO_InitStruct->ClkEdge));
+ assert_param(IS_SDIO_CLK_BYPASS(SDIO_InitStruct->ClkBypass));
+ assert_param(IS_SDIO_CLK_POWER_SAVE(SDIO_InitStruct->ClkPwrSave));
+ assert_param(IS_SDIO_BUS_WIDTH(SDIO_InitStruct->BusWidth));
+ assert_param(IS_SDIO_HARDWARE_CLKCTRL(SDIO_InitStruct->HardwareClkCtrl));
+
+ /*---------------------------- SDIO CLKCTRL Configuration ------------------------*/
+ /* Get the SDIO CLKCTRL value */
+ tmpregister = SDIO->CLKCTRL;
+
+ /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
+ tmpregister &= CLKCTRL_CLR_MASK;
+
+ /* Set CLKDIV bits according to ClkDiv value */
+ /* Set PWRSAV bit according to ClkPwrSave value */
+ /* Set BYPASS bit according to ClkBypass value */
+ /* Set WIDBUS bits according to BusWidth value */
+ /* Set NEGEDGE bits according to ClkEdge value */
+ /* Set HWFC_EN bits according to HardwareClkCtrl value */
+ tmpregister |= (SDIO_InitStruct->ClkDiv | SDIO_InitStruct->ClkPwrSave | SDIO_InitStruct->ClkBypass
+ | SDIO_InitStruct->BusWidth | SDIO_InitStruct->ClkEdge | SDIO_InitStruct->HardwareClkCtrl);
+
+ /* Write to SDIO CLKCTRL */
+ SDIO->CLKCTRL = tmpregister;
+}
+
+/**
+ * @brief Fills each SDIO_InitStruct member with its default value.
+ * @param SDIO_InitStruct pointer to an SDIO_InitType structure which
+ * will be initialized.
+ */
+void SDIO_InitStruct(SDIO_InitType* SDIO_InitStruct)
+{
+ /* SDIO_InitStruct members default value */
+ SDIO_InitStruct->ClkDiv = 0x00;
+ SDIO_InitStruct->ClkEdge = SDIO_CLKEDGE_RISING;
+ SDIO_InitStruct->ClkBypass = SDIO_ClkBYPASS_DISABLE;
+ SDIO_InitStruct->ClkPwrSave = SDIO_CLKPOWERSAVE_DISABLE;
+ SDIO_InitStruct->BusWidth = SDIO_BUSWIDTH_1B;
+ SDIO_InitStruct->HardwareClkCtrl = SDIO_HARDWARE_CLKCTRL_DISABLE;
+}
+
+/**
+ * @brief Enables or disables the SDIO Clock.
+ * @param Cmd new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.
+ */
+void SDIO_EnableClock(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ *(__IO uint32_t*)CLKCTRL_CLKEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Sets the power status of the controller.
+ * @param SDIO_PowerState new state of the Power state.
+ * This parameter can be one of the following values:
+ * @arg SDIO_POWER_CTRL_OFF
+ * @arg SDIO_POWER_CTRL_ON
+ */
+void SDIO_SetPower(uint32_t SDIO_PowerState)
+{
+ /* Check the parameters */
+ assert_param(IS_SDIO_POWER_CTRL(SDIO_PowerState));
+
+ SDIO->PWRCTRL &= POWER_PWRCTRL_MASK;
+ SDIO->PWRCTRL |= SDIO_PowerState;
+}
+
+/**
+ * @brief Gets the power status of the controller.
+ * @return Power status of the controller. The returned value can
+ * be one of the following:
+ * - 0x00: Power OFF
+ * - 0x02: Power UP
+ * - 0x03: Power ON
+ */
+uint32_t SDIO_GetPower(void)
+{
+ return (SDIO->PWRCTRL & (~POWER_PWRCTRL_MASK));
+}
+
+/**
+ * @brief Enables or disables the SDIO interrupts.
+ * @param SDIO_IT specifies the SDIO interrupt sources to be enabled or disabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_INT_CCRCERR Command response received (CRC check failed) interrupt
+ * @arg SDIO_INT_DCRCERR Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_INT_CMDTIMEOUT Command response timeout interrupt
+ * @arg SDIO_INT_DATTIMEOUT Data timeout interrupt
+ * @arg SDIO_INT_TXURERR Transmit DATFIFO underrun error interrupt
+ * @arg SDIO_INT_RXORERR Received DATFIFO overrun error interrupt
+ * @arg SDIO_INT_CMDRESPRECV Command response received (CRC check passed) interrupt
+ * @arg SDIO_INT_CMDSEND Command sent (no response required) interrupt
+ * @arg SDIO_INT_DATEND Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_INT_SBERR Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_INT_DATBLKEND Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_INT_CMDRUN Command transfer in progress interrupt
+ * @arg SDIO_INT_TXRUN Data transmit in progress interrupt
+ * @arg SDIO_INT_RXRUN Data receive in progress interrupt
+ * @arg SDIO_INT_TFIFOHE Transmit DATFIFO Half Empty interrupt
+ * @arg SDIO_INT_RFIFOHF Receive DATFIFO Half Full interrupt
+ * @arg SDIO_INT_TFIFOF Transmit DATFIFO full interrupt
+ * @arg SDIO_INT_RFIFOF Receive DATFIFO full interrupt
+ * @arg SDIO_INT_TFIFOE Transmit DATFIFO empty interrupt
+ * @arg SDIO_INT_RFIFOE Receive DATFIFO empty interrupt
+ * @arg SDIO_INT_TDATVALID Data available in transmit DATFIFO interrupt
+ * @arg SDIO_INT_RDATVALID Data available in receive DATFIFO interrupt
+ * @arg SDIO_INT_SDIOINT SD I/O interrupt received interrupt
+ * @arg SDIO_INT_CEATAF CE-ATA command completion signal received for CMD61 interrupt
+ * @param Cmd new state of the specified SDIO interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void SDIO_ConfigInt(uint32_t SDIO_IT, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_SDIO_INT(SDIO_IT));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the SDIO interrupts */
+ SDIO->INTEN |= SDIO_IT;
+ }
+ else
+ {
+ /* Disable the SDIO interrupts */
+ SDIO->INTEN &= ~SDIO_IT;
+ }
+}
+
+/**
+ * @brief Enables or disables the SDIO DMA request.
+ * @param Cmd new state of the selected SDIO DMA request.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void SDIO_DMACmd(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ *(__IO uint32_t*)DCTRL_DMAEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Initializes the SDIO Command according to the specified
+ * parameters in the SDIO_CmdInitStruct and send the command.
+ * @param SDIO_CmdInitStruct pointer to a SDIO_CmdInitType
+ * structure that contains the configuration information for the SDIO command.
+ */
+void SDIO_SendCmd(SDIO_CmdInitType* SDIO_CmdInitStruct)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->CmdIndex));
+ assert_param(IS_SDIO_RESP(SDIO_CmdInitStruct->ResponseType));
+ assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->WaitType));
+ assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->CPSMConfig));
+
+ /*---------------------------- SDIO CMDARG Configuration ------------------------*/
+ /* Set the SDIO Argument value */
+ SDIO->CMDARG = SDIO_CmdInitStruct->CmdArgument;
+
+ /*---------------------------- SDIO CMDCTRL Configuration ------------------------*/
+ /* Get the SDIO CMDCTRL value */
+ tmpregister = SDIO->CMDCTRL;
+ /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
+ tmpregister &= CMD_CLR_MASK;
+ /* Set CMDINDEX bits according to CmdIndex value */
+ /* Set WAITRESP bits according to ResponseType value */
+ /* Set WAITINT and WAITPEND bits according to WaitType value */
+ /* Set CPSMEN bits according to CPSMConfig value */
+ tmpregister |= (uint32_t)SDIO_CmdInitStruct->CmdIndex | SDIO_CmdInitStruct->ResponseType
+ | SDIO_CmdInitStruct->WaitType | SDIO_CmdInitStruct->CPSMConfig;
+
+ /* Write to SDIO CMDCTRL */
+ SDIO->CMDCTRL = tmpregister;
+}
+
+/**
+ * @brief Fills each SDIO_CmdInitStruct member with its default value.
+ * @param SDIO_CmdInitStruct pointer to an SDIO_CmdInitType
+ * structure which will be initialized.
+ */
+void SDIO_InitCmdStruct(SDIO_CmdInitType* SDIO_CmdInitStruct)
+{
+ /* SDIO_CmdInitStruct members default value */
+ SDIO_CmdInitStruct->CmdArgument = 0x00;
+ SDIO_CmdInitStruct->CmdIndex = 0x00;
+ SDIO_CmdInitStruct->ResponseType = SDIO_RESP_NO;
+ SDIO_CmdInitStruct->WaitType = SDIO_WAIT_NO;
+ SDIO_CmdInitStruct->CPSMConfig = SDIO_CPSM_DISABLE;
+}
+
+/**
+ * @brief Returns command index of last command for which response received.
+ * @return Returns the command index of the last command response received.
+ */
+uint8_t SDIO_GetCmdResp(void)
+{
+ return (uint8_t)(SDIO->CMDRESP);
+}
+
+/**
+ * @brief Returns response received from the card for the last command.
+ * @param SDIO_RESP Specifies the SDIO response register.
+ * This parameter can be one of the following values:
+ * @arg SDIO_RESPONSE_1 Response Register 1
+ * @arg SDIO_RESPONSE_2 Response Register 2
+ * @arg SDIO_RESPONSE_3 Response Register 3
+ * @arg SDIO_RESPONSE_4 Response Register 4
+ * @return The Corresponding response register value.
+ */
+uint32_t SDIO_GetResp(uint32_t SDIO_RESP)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_RESPONSE(SDIO_RESP));
+
+ tmp = SDID_RESPONSE_ADDR + SDIO_RESP;
+
+ return (*(__IO uint32_t*)tmp);
+}
+
+/**
+ * @brief Initializes the SDIO data path according to the specified
+ * parameters in the SDIO_DataInitStruct.
+ * @param SDIO_DataInitStruct pointer to a SDIO_DataInitType structure that
+ * contains the configuration information for the SDIO command.
+ */
+void SDIO_ConfigData(SDIO_DataInitType* SDIO_DataInitStruct)
+{
+ uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_DAT_LEN(SDIO_DataInitStruct->DatLen));
+ assert_param(IS_SDIO_BLK_SIZE(SDIO_DataInitStruct->DatBlkSize));
+ assert_param(IS_SDIO_TRANSFER_DIRECTION(SDIO_DataInitStruct->TransferDirection));
+ assert_param(IS_SDIO_TRANS_MODE(SDIO_DataInitStruct->TransferMode));
+ assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->DPSMConfig));
+
+ /*---------------------------- SDIO DATTIMEOUT Configuration ---------------------*/
+ /* Set the SDIO Data TimeOut value */
+ SDIO->DTIMER = SDIO_DataInitStruct->DatTimeout;
+
+ /*---------------------------- SDIO DATLEN Configuration -----------------------*/
+ /* Set the SDIO DataLength value */
+ SDIO->DATLEN = SDIO_DataInitStruct->DatLen;
+
+ /*---------------------------- SDIO DATCTRL Configuration ----------------------*/
+ /* Get the SDIO DATCTRL value */
+ tmpregister = SDIO->DATCTRL;
+ /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
+ tmpregister &= DATCTRL_CLR_MASK;
+ /* Set DEN bit according to DPSMConfig value */
+ /* Set DTMODE bit according to TransferMode value */
+ /* Set DTDIR bit according to TransferDirection value */
+ /* Set DBCKSIZE bits according to DatBlkSize value */
+ tmpregister |= (uint32_t)SDIO_DataInitStruct->DatBlkSize | SDIO_DataInitStruct->TransferDirection
+ | SDIO_DataInitStruct->TransferMode | SDIO_DataInitStruct->DPSMConfig;
+
+ if (SDIO_DataInitStruct->TransferDirection)
+ {
+ tmpregister &= ~(1<<12);
+ }
+ else
+ {
+ tmpregister |= 1<<12;
+ }
+
+ /* Write to SDIO DATCTRL */
+ SDIO->DATCTRL = tmpregister;
+}
+
+/**
+ * @brief Fills each SDIO_DataInitStruct member with its default value.
+ * @param SDIO_DataInitStruct pointer to an SDIO_DataInitType structure which
+ * will be initialized.
+ */
+void SDIO_InitDataStruct(SDIO_DataInitType* SDIO_DataInitStruct)
+{
+ /* SDIO_DataInitStruct members default value */
+ SDIO_DataInitStruct->DatTimeout = 0xFFFFFFFF;
+ SDIO_DataInitStruct->DatLen = 0x00;
+ SDIO_DataInitStruct->DatBlkSize = SDIO_DATBLK_SIZE_1B;
+ SDIO_DataInitStruct->TransferDirection = SDIO_TRANSDIR_TOCARD;
+ SDIO_DataInitStruct->TransferMode = SDIO_TRANSMODE_BLOCK;
+ SDIO_DataInitStruct->DPSMConfig = SDIO_DPSM_DISABLE;
+}
+
+/**
+ * @brief Returns number of remaining data bytes to be transferred.
+ * @return Number of remaining data bytes to be transferred
+ */
+uint32_t SDIO_GetDataCountValue(void)
+{
+ return SDIO->DATCOUNT;
+}
+
+/**
+ * @brief Read one data word from Rx DATFIFO.
+ * @return Data received
+ */
+uint32_t SDIO_ReadData(void)
+{
+ return SDIO->DATFIFO;
+}
+
+/**
+ * @brief Write one data word to Tx DATFIFO.
+ * @param Data 32-bit data word to write.
+ */
+void SDIO_WriteData(uint32_t Data)
+{
+ SDIO->DATFIFO = Data;
+}
+
+/**
+ * @brief Returns the number of words left to be written to or read from DATFIFO.
+ * @return Remaining number of words.
+ */
+uint32_t SDIO_GetFifoCounter(void)
+{
+ return SDIO->FIFOCOUNT;
+}
+
+/**
+ * @brief Starts the SD I/O Read Wait operation.
+ * @param Cmd new state of the Start SDIO Read Wait operation.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void SDIO_EnableReadWait(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ *(__IO uint32_t*)DCTRL_RWSTART_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Stops the SD I/O Read Wait operation.
+ * @param Cmd new state of the Stop SDIO Read Wait operation.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void SDIO_DisableReadWait(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ *(__IO uint32_t*)DCTRL_RWSTOP_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Sets one of the two options of inserting read wait interval.
+ * @param SDIO_ReadWaitMode SD I/O Read Wait operation mode.
+ * This parameter can be:
+ * @arg SDIO_RDWAIT_MODE_CLK Read Wait control by stopping SDIOCLK
+ * @arg SDIO_RDWAIT_MODE_DAT2 Read Wait control using SDIO_DATA2
+ */
+void SDIO_EnableSdioReadWaitMode(uint32_t SDIO_ReadWaitMode)
+{
+ /* Check the parameters */
+ assert_param(IS_SDIO_RDWAIT_MODE(SDIO_ReadWaitMode));
+
+ *(__IO uint32_t*)DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
+}
+
+/**
+ * @brief Enables or disables the SD I/O Mode Operation.
+ * @param Cmd new state of SDIO specific operation.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void SDIO_EnableSdioOperation(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ *(__IO uint32_t*)DCTRL_SDIOEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Enables or disables the SD I/O Mode suspend command sending.
+ * @param Cmd new state of the SD I/O Mode suspend command.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void SDIO_EnableSendSdioSuspend(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ *(__IO uint32_t*)CMD_SDIO_SUSPEND_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Enables or disables the command completion signal.
+ * @param Cmd new state of command completion signal.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void SDIO_EnableCommandCompletion(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ *(__IO uint32_t*)EN_CMD_COMPL_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Enables or disables the CE-ATA interrupt.
+ * @param Cmd new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.
+ */
+void SDIO_EnableCEATAInt(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ *(__IO uint32_t*)CMD_NIEN_BB = (uint32_t)((~((uint32_t)Cmd)) & ((uint32_t)0x1));
+}
+
+/**
+ * @brief Sends CE-ATA command (CMD61).
+ * @param Cmd new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.
+ */
+void SDIO_EnableSendCEATA(FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ *(__IO uint32_t*)CMD_ATACMD_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief Checks whether the specified SDIO flag is set or not.
+ * @param SDIO_FLAG specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SDIO_FLAG_CCRCERR Command response received (CRC check failed)
+ * @arg SDIO_FLAG_DCRCERR Data block sent/received (CRC check failed)
+ * @arg SDIO_FLAG_CMDTIMEOUT Command response timeout
+ * @arg SDIO_FLAG_DATTIMEOUT Data timeout
+ * @arg SDIO_FLAG_TXURERR Transmit DATFIFO underrun error
+ * @arg SDIO_FLAG_RXORERR Received DATFIFO overrun error
+ * @arg SDIO_FLAG_CMDRESPRECV Command response received (CRC check passed)
+ * @arg SDIO_FLAG_CMDSEND Command sent (no response required)
+ * @arg SDIO_FLAG_DATEND Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_SBERR Start bit not detected on all data signals in wide
+ * bus mode.
+ * @arg SDIO_FLAG_DATBLKEND Data block sent/received (CRC check passed)
+ * @arg SDIO_FLAG_CMDRUN Command transfer in progress
+ * @arg SDIO_FLAG_TXRUN Data transmit in progress
+ * @arg SDIO_FLAG_RXRUN Data receive in progress
+ * @arg SDIO_FLAG_TFIFOHE Transmit DATFIFO Half Empty
+ * @arg SDIO_FLAG_RFIFOHF Receive DATFIFO Half Full
+ * @arg SDIO_FLAG_TFIFOF Transmit DATFIFO full
+ * @arg SDIO_FLAG_RFIFOF Receive DATFIFO full
+ * @arg SDIO_FLAG_TFIFOE Transmit DATFIFO empty
+ * @arg SDIO_FLAG_RFIFOE Receive DATFIFO empty
+ * @arg SDIO_FLAG_TDATVALID Data available in transmit DATFIFO
+ * @arg SDIO_FLAG_RDATVALID Data available in receive DATFIFO
+ * @arg SDIO_FLAG_SDIOINT SD I/O interrupt received
+ * @arg SDIO_FLAG_CEATAF CE-ATA command completion signal received for CMD61
+ * @return The new state of SDIO_FLAG (SET or RESET).
+ */
+FlagStatus SDIO_GetFlag(uint32_t SDIO_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_FLAG(SDIO_FLAG));
+
+ if ((SDIO->STS & SDIO_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the SDIO's pending flags.
+ * @param SDIO_FLAG specifies the flag to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_FLAG_CCRCERR Command response received (CRC check failed)
+ * @arg SDIO_FLAG_DCRCERR Data block sent/received (CRC check failed)
+ * @arg SDIO_FLAG_CMDTIMEOUT Command response timeout
+ * @arg SDIO_FLAG_DATTIMEOUT Data timeout
+ * @arg SDIO_FLAG_TXURERR Transmit DATFIFO underrun error
+ * @arg SDIO_FLAG_RXORERR Received DATFIFO overrun error
+ * @arg SDIO_FLAG_CMDRESPRECV Command response received (CRC check passed)
+ * @arg SDIO_FLAG_CMDSEND Command sent (no response required)
+ * @arg SDIO_FLAG_DATEND Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_SBERR Start bit not detected on all data signals in wide
+ * bus mode
+ * @arg SDIO_FLAG_DATBLKEND Data block sent/received (CRC check passed)
+ * @arg SDIO_FLAG_SDIOINT SD I/O interrupt received
+ * @arg SDIO_FLAG_CEATAF CE-ATA command completion signal received for CMD61
+ */
+void SDIO_ClrFlag(uint32_t SDIO_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_SDIO_CLR_FLAG(SDIO_FLAG));
+
+ SDIO->INTCLR = SDIO_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified SDIO interrupt has occurred or not.
+ * @param SDIO_IT specifies the SDIO interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SDIO_INT_CCRCERR Command response received (CRC check failed) interrupt
+ * @arg SDIO_INT_DCRCERR Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_INT_CMDTIMEOUT Command response timeout interrupt
+ * @arg SDIO_INT_DATTIMEOUT Data timeout interrupt
+ * @arg SDIO_INT_TXURERR Transmit DATFIFO underrun error interrupt
+ * @arg SDIO_INT_RXORERR Received DATFIFO overrun error interrupt
+ * @arg SDIO_INT_CMDRESPRECV Command response received (CRC check passed) interrupt
+ * @arg SDIO_INT_CMDSEND Command sent (no response required) interrupt
+ * @arg SDIO_INT_DATEND Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_INT_SBERR Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_INT_DATBLKEND Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_INT_CMDRUN Command transfer in progress interrupt
+ * @arg SDIO_INT_TXRUN Data transmit in progress interrupt
+ * @arg SDIO_INT_RXRUN Data receive in progress interrupt
+ * @arg SDIO_INT_TFIFOHE Transmit DATFIFO Half Empty interrupt
+ * @arg SDIO_INT_RFIFOHF Receive DATFIFO Half Full interrupt
+ * @arg SDIO_INT_TFIFOF Transmit DATFIFO full interrupt
+ * @arg SDIO_INT_RFIFOF Receive DATFIFO full interrupt
+ * @arg SDIO_INT_TFIFOE Transmit DATFIFO empty interrupt
+ * @arg SDIO_INT_RFIFOE Receive DATFIFO empty interrupt
+ * @arg SDIO_INT_TDATVALID Data available in transmit DATFIFO interrupt
+ * @arg SDIO_INT_RDATVALID Data available in receive DATFIFO interrupt
+ * @arg SDIO_INT_SDIOINT SD I/O interrupt received interrupt
+ * @arg SDIO_INT_CEATAF CE-ATA command completion signal received for CMD61 interrupt
+ * @return The new state of SDIO_IT (SET or RESET).
+ */
+INTStatus SDIO_GetIntStatus(uint32_t SDIO_IT)
+{
+ INTStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_GET_INT(SDIO_IT));
+ if ((SDIO->STS & SDIO_IT) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the SDIO's interrupt pending bits.
+ * @param SDIO_IT specifies the interrupt pending bit to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_INT_CCRCERR Command response received (CRC check failed) interrupt
+ * @arg SDIO_INT_DCRCERR Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_INT_CMDTIMEOUT Command response timeout interrupt
+ * @arg SDIO_INT_DATTIMEOUT Data timeout interrupt
+ * @arg SDIO_INT_TXURERR Transmit DATFIFO underrun error interrupt
+ * @arg SDIO_INT_RXORERR Received DATFIFO overrun error interrupt
+ * @arg SDIO_INT_CMDRESPRECV Command response received (CRC check passed) interrupt
+ * @arg SDIO_INT_CMDSEND Command sent (no response required) interrupt
+ * @arg SDIO_INT_DATEND Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_INT_SBERR Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_INT_SDIOINT SD I/O interrupt received interrupt
+ * @arg SDIO_INT_CEATAF CE-ATA command completion signal received for CMD61
+ */
+void SDIO_ClrIntPendingBit(uint32_t SDIO_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_SDIO_CLR_INT(SDIO_IT));
+
+ SDIO->INTCLR = SDIO_IT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_spi.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_spi.c
new file mode 100644
index 0000000000..9ea5a6f625
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_spi.c
@@ -0,0 +1,862 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_spi.c
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32wb452_spi.h"
+#include "n32wb452_rcc.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @brief SPI driver modules
+ * @{
+ */
+
+/** @addtogroup SPI_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_Defines
+ * @{
+ */
+
+/* SPI SPE mask */
+#define CTRL1_SPIEN_ENABLE ((uint16_t)0x0040)
+#define CTRL1_SPIEN_DISABLE ((uint16_t)0xFFBF)
+
+/* I2S I2SE mask */
+#define I2SCFG_I2SEN_ENABLE ((uint16_t)0x0400)
+#define I2SCFG_I2SEN_DISABLE ((uint16_t)0xFBFF)
+
+/* SPI CRCNext mask */
+#define CTRL1_CRCNEXT_ENABLE ((uint16_t)0x1000)
+
+/* SPI CRCEN mask */
+#define CTRL1_CRCEN_ENABLE ((uint16_t)0x2000)
+#define CTRL1_CRCEN_DISABLE ((uint16_t)0xDFFF)
+
+/* SPI SSOE mask */
+#define CTRL2_SSOEN_ENABLE ((uint16_t)0x0004)
+#define CTRL2_SSOEN_DISABLE ((uint16_t)0xFFFB)
+
+/* SPI registers Masks */
+#define CTRL1_CLR_MASK ((uint16_t)0x3040)
+#define I2SCFG_CLR_MASK ((uint16_t)0xF040)
+
+/* SPI or I2S mode selection masks */
+#define SPI_MODE_ENABLE ((uint16_t)0xF7FF)
+#define I2S_MODE_ENABLE ((uint16_t)0x0800)
+
+/* I2S clock source selection masks */
+#define I2S2_CLKSRC ((uint32_t)(0x00020000))
+#define I2S3_CLKSRC ((uint32_t)(0x00040000))
+#define I2S_MUL_MASK ((uint32_t)(0x0000F000))
+#define I2S_DIV_MASK ((uint32_t)(0x000000F0))
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the SPIx peripheral registers to their default
+ * reset values (Affects also the I2Ss).
+ * @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral.
+ */
+void SPI_I2S_DeInit(SPI_Module* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+
+ if (SPIx == SPI1)
+ {
+ /* Enable SPI1 reset state */
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI1, ENABLE);
+ /* Release SPI1 from reset state */
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI1, DISABLE);
+ }
+ else if (SPIx == SPI2)
+ {
+ /* Enable SPI2 reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_SPI2, ENABLE);
+ /* Release SPI2 from reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_SPI2, DISABLE);
+ }
+ else
+ {
+ if (SPIx == SPI3)
+ {
+ /* Enable SPI3 reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_SPI3, ENABLE);
+ /* Release SPI3 from reset state */
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_SPI3, DISABLE);
+ }
+ }
+}
+
+/**
+ * @brief Initializes the SPIx peripheral according to the specified
+ * parameters in the SPI_InitStruct.
+ * @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param SPI_InitStruct pointer to a SPI_InitType structure that
+ * contains the configuration information for the specified SPI peripheral.
+ */
+void SPI_Init(SPI_Module* SPIx, SPI_InitType* SPI_InitStruct)
+{
+ uint16_t tmpregister = 0;
+
+ /* check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+
+ /* Check the SPI parameters */
+ assert_param(IS_SPI_DIR_MODE(SPI_InitStruct->DataDirection));
+ assert_param(IS_SPI_MODE(SPI_InitStruct->SpiMode));
+ assert_param(IS_SPI_DATASIZE(SPI_InitStruct->DataLen));
+ assert_param(IS_SPI_CLKPOL(SPI_InitStruct->CLKPOL));
+ assert_param(IS_SPI_CLKPHA(SPI_InitStruct->CLKPHA));
+ assert_param(IS_SPI_NSS(SPI_InitStruct->NSS));
+ assert_param(IS_SPI_BR_PRESCALER(SPI_InitStruct->BaudRatePres));
+ assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->FirstBit));
+ assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
+
+ /*---------------------------- SPIx CTRL1 Configuration ------------------------*/
+ /* Get the SPIx CTRL1 value */
+ tmpregister = SPIx->CTRL1;
+ /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
+ tmpregister &= CTRL1_CLR_MASK;
+ /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
+ master/salve mode, CPOL and CPHA */
+ /* Set BIDImode, BIDIOE and RxONLY bits according to DataDirection value */
+ /* Set SSM, SSI and MSTR bits according to SpiMode and NSS values */
+ /* Set LSBFirst bit according to FirstBit value */
+ /* Set BR bits according to BaudRatePres value */
+ /* Set CPOL bit according to CLKPOL value */
+ /* Set CPHA bit according to CLKPHA value */
+ tmpregister |= (uint16_t)((uint32_t)SPI_InitStruct->DataDirection | SPI_InitStruct->SpiMode
+ | SPI_InitStruct->DataLen | SPI_InitStruct->CLKPOL | SPI_InitStruct->CLKPHA
+ | SPI_InitStruct->NSS | SPI_InitStruct->BaudRatePres | SPI_InitStruct->FirstBit);
+ /* Write to SPIx CTRL1 */
+ SPIx->CTRL1 = tmpregister;
+
+ /* Activate the SPI mode (Reset I2SMOD bit in I2SCFG register) */
+ SPIx->I2SCFG &= SPI_MODE_ENABLE;
+
+ /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
+ /* Write to SPIx CRCPOLY */
+ SPIx->CRCPOLY = SPI_InitStruct->CRCPoly;
+}
+
+/**
+ * @brief Initializes the SPIx peripheral according to the specified
+ * parameters in the I2S_InitStruct.
+ * @param SPIx where x can be 2 or 3 to select the SPI peripheral
+ * (configured in I2S mode).
+ * @param I2S_InitStruct pointer to an I2S_InitType structure that
+ * contains the configuration information for the specified SPI peripheral
+ * configured in I2S mode.
+ * @note
+ * The function calculates the optimal prescaler needed to obtain the most
+ * accurate audio frequency (depending on the I2S clock source, the PLL values
+ * and the product configuration). But in case the prescaler value is greater
+ * than 511, the default value (0x02) will be configured instead. *
+ */
+void I2S_Init(SPI_Module* SPIx, I2S_InitType* I2S_InitStruct)
+{
+ uint16_t tmpregister = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
+ uint32_t tmp = 0;
+ RCC_ClocksType RCC_Clocks;
+ uint32_t sourceclock = 0;
+
+ /* Check the I2S parameters */
+ assert_param(IS_SPI_2OR3_PERIPH(SPIx));
+ assert_param(IS_I2S_MODE(I2S_InitStruct->I2sMode));
+ assert_param(IS_I2S_STANDARD(I2S_InitStruct->Standard));
+ assert_param(IS_I2S_DATA_FMT(I2S_InitStruct->DataFormat));
+ assert_param(IS_I2S_MCLK_ENABLE(I2S_InitStruct->MCLKEnable));
+ assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFrequency));
+ assert_param(IS_I2S_CLKPOL(I2S_InitStruct->CLKPOL));
+
+ /*----------------------- SPIx I2SCFG & I2SPREDIV Configuration -----------------*/
+ /* Clear I2SMOD, I2SE, MODCFG, PCMSYNC, STDSEL, CKPOL, TDATLEN and CHLEN bits */
+ SPIx->I2SCFG &= I2SCFG_CLR_MASK;
+ SPIx->I2SPREDIV = 0x0002;
+
+ /* Get the I2SCFG register value */
+ tmpregister = SPIx->I2SCFG;
+
+ /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
+ if (I2S_InitStruct->AudioFrequency == I2S_AUDIO_FREQ_DEFAULT)
+ {
+ i2sodd = (uint16_t)0;
+ i2sdiv = (uint16_t)2;
+ }
+ /* If the requested audio frequency is not the default, compute the prescaler */
+ else
+ {
+ /* Check the frame length (For the Prescaler computing) */
+ if (I2S_InitStruct->DataFormat == I2S_DATA_FMT_16BITS)
+ {
+ /* Packet length is 16 bits */
+ packetlength = 1;
+ }
+ else
+ {
+ /* Packet length is 32 bits */
+ packetlength = 2;
+ }
+
+ /* Get the I2S clock source mask depending on the peripheral number */
+ if (((uint32_t)SPIx) == SPI2_BASE)
+ {
+ /* The mask is relative to I2S2 */
+ tmp = I2S2_CLKSRC;
+ }
+ else
+ {
+ /* The mask is relative to I2S3 */
+ tmp = I2S3_CLKSRC;
+ }
+
+ /* I2S Clock source is System clock: Get System Clock frequency */
+ RCC_GetClocksFreqValue(&RCC_Clocks);
+
+ /* Get the source clock value: based on System Clock value */
+ sourceclock = RCC_Clocks.SysclkFreq;
+
+ /* Compute the Real divider depending on the MCLK output state with a floating point */
+ if (I2S_InitStruct->MCLKEnable == I2S_MCLK_ENABLE)
+ {
+ /* MCLK output is enabled */
+ tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->AudioFrequency)) + 5);
+ }
+ else
+ {
+ /* MCLK output is disabled */
+ tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) * 10) / I2S_InitStruct->AudioFrequency)) + 5);
+ }
+
+ /* Remove the floating point */
+ tmp = tmp / 10;
+
+ /* Check the parity of the divider */
+ i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
+
+ /* Compute the i2sdiv prescaler */
+ i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
+
+ /* Get the Mask for the Odd bit (SPI_I2SPREDIV[8]) register */
+ i2sodd = (uint16_t)(i2sodd << 8);
+ }
+
+ /* Test if the divider is 1 or 0 or greater than 0xFF */
+ if ((i2sdiv < 2) || (i2sdiv > 0xFF))
+ {
+ /* Set the default values */
+ i2sdiv = 2;
+ i2sodd = 0;
+ }
+
+ /* Write to SPIx I2SPREDIV register the computed value */
+ SPIx->I2SPREDIV = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->MCLKEnable));
+
+ /* Configure the I2S with the SPI_InitStruct values */
+ tmpregister |= (uint16_t)(
+ I2S_MODE_ENABLE
+ | (uint16_t)(I2S_InitStruct->I2sMode
+ | (uint16_t)(I2S_InitStruct->Standard
+ | (uint16_t)(I2S_InitStruct->DataFormat | (uint16_t)I2S_InitStruct->CLKPOL))));
+
+ /* Write to SPIx I2SCFG */
+ SPIx->I2SCFG = tmpregister;
+}
+
+/**
+ * @brief Fills each SPI_InitStruct member with its default value.
+ * @param SPI_InitStruct pointer to a SPI_InitType structure which will be initialized.
+ */
+void SPI_InitStruct(SPI_InitType* SPI_InitStruct)
+{
+ /*--------------- Reset SPI init structure parameters values -----------------*/
+ /* Initialize the DataDirection member */
+ SPI_InitStruct->DataDirection = SPI_DIR_DOUBLELINE_FULLDUPLEX;
+ /* initialize the SpiMode member */
+ SPI_InitStruct->SpiMode = SPI_MODE_SLAVE;
+ /* initialize the DataLen member */
+ SPI_InitStruct->DataLen = SPI_DATA_SIZE_8BITS;
+ /* Initialize the CLKPOL member */
+ SPI_InitStruct->CLKPOL = SPI_CLKPOL_LOW;
+ /* Initialize the CLKPHA member */
+ SPI_InitStruct->CLKPHA = SPI_CLKPHA_FIRST_EDGE;
+ /* Initialize the NSS member */
+ SPI_InitStruct->NSS = SPI_NSS_HARD;
+ /* Initialize the BaudRatePres member */
+ SPI_InitStruct->BaudRatePres = SPI_BR_PRESCALER_2;
+ /* Initialize the FirstBit member */
+ SPI_InitStruct->FirstBit = SPI_FB_MSB;
+ /* Initialize the CRCPoly member */
+ SPI_InitStruct->CRCPoly = 7;
+}
+
+/**
+ * @brief Fills each I2S_InitStruct member with its default value.
+ * @param I2S_InitStruct pointer to a I2S_InitType structure which will be initialized.
+ */
+void I2S_InitStruct(I2S_InitType* I2S_InitStruct)
+{
+ /*--------------- Reset I2S init structure parameters values -----------------*/
+ /* Initialize the I2sMode member */
+ I2S_InitStruct->I2sMode = I2S_MODE_SlAVE_TX;
+
+ /* Initialize the Standard member */
+ I2S_InitStruct->Standard = I2S_STD_PHILLIPS;
+
+ /* Initialize the DataFormat member */
+ I2S_InitStruct->DataFormat = I2S_DATA_FMT_16BITS;
+
+ /* Initialize the MCLKEnable member */
+ I2S_InitStruct->MCLKEnable = I2S_MCLK_DISABLE;
+
+ /* Initialize the AudioFrequency member */
+ I2S_InitStruct->AudioFrequency = I2S_AUDIO_FREQ_DEFAULT;
+
+ /* Initialize the CLKPOL member */
+ I2S_InitStruct->CLKPOL = I2S_CLKPOL_LOW;
+}
+
+/**
+ * @brief Enables or disables the specified SPI peripheral.
+ * @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param Cmd new state of the SPIx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void SPI_Enable(SPI_Module* SPIx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected SPI peripheral */
+ SPIx->CTRL1 |= CTRL1_SPIEN_ENABLE;
+ }
+ else
+ {
+ /* Disable the selected SPI peripheral */
+ SPIx->CTRL1 &= CTRL1_SPIEN_DISABLE;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified SPI peripheral (in I2S mode).
+ * @param SPIx where x can be 2 or 3 to select the SPI peripheral.
+ * @param Cmd new state of the SPIx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void I2S_Enable(SPI_Module* SPIx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_2OR3_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected SPI peripheral (in I2S mode) */
+ SPIx->I2SCFG |= I2SCFG_I2SEN_ENABLE;
+ }
+ else
+ {
+ /* Disable the selected SPI peripheral (in I2S mode) */
+ SPIx->I2SCFG &= I2SCFG_I2SEN_DISABLE;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified SPI/I2S interrupts.
+ * @param SPIx where x can be
+ * - 1, 2 or 3 in SPI mode
+ * - 2 or 3 in I2S mode
+ * @param SPI_I2S_IT specifies the SPI/I2S interrupt source to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg SPI_I2S_INT_TE Tx buffer empty interrupt mask
+ * @arg SPI_I2S_INT_RNE Rx buffer not empty interrupt mask
+ * @arg SPI_I2S_INT_ERR Error interrupt mask
+ * @param Cmd new state of the specified SPI/I2S interrupt.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void SPI_I2S_EnableInt(SPI_Module* SPIx, uint8_t SPI_I2S_IT, FunctionalState Cmd)
+{
+ uint16_t itpos = 0, itmask = 0;
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ assert_param(IS_SPI_I2S_CONFIG_INT(SPI_I2S_IT));
+
+ /* Get the SPI/I2S IT index */
+ itpos = SPI_I2S_IT >> 4;
+
+ /* Set the IT mask */
+ itmask = (uint16_t)1 << (uint16_t)itpos;
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected SPI/I2S interrupt */
+ SPIx->CTRL2 |= itmask;
+ }
+ else
+ {
+ /* Disable the selected SPI/I2S interrupt */
+ SPIx->CTRL2 &= (uint16_t)~itmask;
+ }
+}
+
+/**
+ * @brief Enables or disables the SPIx/I2Sx DMA interface.
+ * @param SPIx where x can be
+ * - 1, 2 or 3 in SPI mode
+ * - 2 or 3 in I2S mode
+ * @param SPI_I2S_DMAReq specifies the SPI/I2S DMA transfer request to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg SPI_I2S_DMA_TX Tx buffer DMA transfer request
+ * @arg SPI_I2S_DMA_RX Rx buffer DMA transfer request
+ * @param Cmd new state of the selected SPI/I2S DMA transfer request.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void SPI_I2S_EnableDma(SPI_Module* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ assert_param(IS_SPI_I2S_DMA(SPI_I2S_DMAReq));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected SPI/I2S DMA requests */
+ SPIx->CTRL2 |= SPI_I2S_DMAReq;
+ }
+ else
+ {
+ /* Disable the selected SPI/I2S DMA requests */
+ SPIx->CTRL2 &= (uint16_t)~SPI_I2S_DMAReq;
+ }
+}
+
+/**
+ * @brief Transmits a Data through the SPIx/I2Sx peripheral.
+ * @param SPIx where x can be
+ * - 1, 2 or 3 in SPI mode
+ * - 2 or 3 in I2S mode
+ * @param Data Data to be transmitted.
+ */
+void SPI_I2S_TransmitData(SPI_Module* SPIx, uint16_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+
+ /* Write in the DAT register the data to be sent */
+ SPIx->DAT = Data;
+}
+
+/**
+ * @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
+ * @param SPIx where x can be
+ * - 1, 2 or 3 in SPI mode
+ * - 2 or 3 in I2S mode
+ * @return The value of the received data.
+ */
+uint16_t SPI_I2S_ReceiveData(SPI_Module* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+
+ /* Return the data in the DAT register */
+ return SPIx->DAT;
+}
+
+/**
+ * @brief Configures internally by software the NSS pin for the selected SPI.
+ * @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param SPI_NSSInternalSoft specifies the SPI NSS internal state.
+ * This parameter can be one of the following values:
+ * @arg SPI_NSS_HIGH Set NSS pin internally
+ * @arg SPI_NSS_LOW Reset NSS pin internally
+ */
+void SPI_SetNssLevel(SPI_Module* SPIx, uint16_t SPI_NSSInternalSoft)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_NSS_LEVEL(SPI_NSSInternalSoft));
+ if (SPI_NSSInternalSoft != SPI_NSS_LOW)
+ {
+ /* Set NSS pin internally by software */
+ SPIx->CTRL1 |= SPI_NSS_HIGH;
+ }
+ else
+ {
+ /* Reset NSS pin internally by software */
+ SPIx->CTRL1 &= SPI_NSS_LOW;
+ }
+}
+
+/**
+ * @brief Enables or disables the SS output for the selected SPI.
+ * @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param Cmd new state of the SPIx SS output.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void SPI_SSOutputEnable(SPI_Module* SPIx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected SPI SS output */
+ SPIx->CTRL2 |= CTRL2_SSOEN_ENABLE;
+ }
+ else
+ {
+ /* Disable the selected SPI SS output */
+ SPIx->CTRL2 &= CTRL2_SSOEN_DISABLE;
+ }
+}
+
+/**
+ * @brief Configures the data size for the selected SPI.
+ * @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param DataLen specifies the SPI data size.
+ * This parameter can be one of the following values:
+ * @arg SPI_DATA_SIZE_16BITS Set data frame format to 16bit
+ * @arg SPI_DATA_SIZE_8BITS Set data frame format to 8bit
+ */
+void SPI_ConfigDataLen(SPI_Module* SPIx, uint16_t DataLen)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_DATASIZE(DataLen));
+ /* Clear DFF bit */
+ SPIx->CTRL1 &= (uint16_t)~SPI_DATA_SIZE_16BITS;
+ /* Set new DFF bit value */
+ SPIx->CTRL1 |= DataLen;
+}
+
+/**
+ * @brief Transmit the SPIx CRC value.
+ * @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral.
+ */
+void SPI_TransmitCrcNext(SPI_Module* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+
+ /* Enable the selected SPI CRC transmission */
+ SPIx->CTRL1 |= CTRL1_CRCNEXT_ENABLE;
+}
+
+/**
+ * @brief Enables or disables the CRC value calculation of the transferred bytes.
+ * @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param Cmd new state of the SPIx CRC value calculation.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void SPI_EnableCalculateCrc(SPI_Module* SPIx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected SPI CRC calculation */
+ SPIx->CTRL1 |= CTRL1_CRCEN_ENABLE;
+ }
+ else
+ {
+ /* Disable the selected SPI CRC calculation */
+ SPIx->CTRL1 &= CTRL1_CRCEN_DISABLE;
+ }
+}
+
+/**
+ * @brief Returns the transmit or the receive CRC register value for the specified SPI.
+ * @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param SPI_CRC specifies the CRC register to be read.
+ * This parameter can be one of the following values:
+ * @arg SPI_CRC_TX Selects Tx CRC register
+ * @arg SPI_CRC_RX Selects Rx CRC register
+ * @return The selected CRC register value..
+ */
+uint16_t SPI_GetCRCDat(SPI_Module* SPIx, uint8_t SPI_CRC)
+{
+ uint16_t crcreg = 0;
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_CRC(SPI_CRC));
+ if (SPI_CRC != SPI_CRC_RX)
+ {
+ /* Get the Tx CRC register */
+ crcreg = SPIx->CRCTDAT;
+ }
+ else
+ {
+ /* Get the Rx CRC register */
+ crcreg = SPIx->CRCRDAT;
+ }
+ /* Return the selected CRC register */
+ return crcreg;
+}
+
+/**
+ * @brief Returns the CRC Polynomial register value for the specified SPI.
+ * @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @return The CRC Polynomial register value.
+ */
+uint16_t SPI_GetCRCPoly(SPI_Module* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+
+ /* Return the CRC polynomial register */
+ return SPIx->CRCPOLY;
+}
+
+/**
+ * @brief Selects the data transfer direction in bi-directional mode for the specified SPI.
+ * @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param DataDirection specifies the data transfer direction in bi-directional mode.
+ * This parameter can be one of the following values:
+ * @arg SPI_BIDIRECTION_TX Selects Tx transmission direction
+ * @arg SPI_BIDIRECTION_RX Selects Rx receive direction
+ */
+void SPI_ConfigBidirectionalMode(SPI_Module* SPIx, uint16_t DataDirection)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_BIDIRECTION(DataDirection));
+ if (DataDirection == SPI_BIDIRECTION_TX)
+ {
+ /* Set the Tx only mode */
+ SPIx->CTRL1 |= SPI_BIDIRECTION_TX;
+ }
+ else
+ {
+ /* Set the Rx only mode */
+ SPIx->CTRL1 &= SPI_BIDIRECTION_RX;
+ }
+}
+
+/**
+ * @brief Checks whether the specified SPI/I2S flag is set or not.
+ * @param SPIx where x can be
+ * - 1, 2 or 3 in SPI mode
+ * - 2 or 3 in I2S mode
+ * @param SPI_I2S_FLAG specifies the SPI/I2S flag to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_I2S_TE_FLAG Transmit buffer empty flag.
+ * @arg SPI_I2S_RNE_FLAG Receive buffer not empty flag.
+ * @arg SPI_I2S_BUSY_FLAG Busy flag.
+ * @arg SPI_I2S_OVER_FLAG Overrun flag.
+ * @arg SPI_MODERR_FLAG Mode Fault flag.
+ * @arg SPI_CRCERR_FLAG CRC Error flag.
+ * @arg I2S_UNDER_FLAG Underrun Error flag.
+ * @arg I2S_CHSIDE_FLAG Channel Side flag.
+ * @return The new state of SPI_I2S_FLAG (SET or RESET).
+ */
+FlagStatus SPI_I2S_GetStatus(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
+ /* Check the status of the specified SPI/I2S flag */
+ if ((SPIx->STS & SPI_I2S_FLAG) != (uint16_t)RESET)
+ {
+ /* SPI_I2S_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* SPI_I2S_FLAG is reset */
+ bitstatus = RESET;
+ }
+ /* Return the SPI_I2S_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the SPIx CRC Error (CRCERR) flag.
+ * @param SPIx where x can be
+ * - 1, 2 or 3 in SPI mode
+ * @param SPI_I2S_FLAG specifies the SPI flag to clear.
+ * This function clears only CRCERR flag.
+ * @note
+ * - OVR (OverRun error) flag is cleared by software sequence: a read
+ * operation to SPI_DAT register (SPI_I2S_ReceiveData()) followed by a read
+ * operation to SPI_STS register (SPI_I2S_GetStatus()).
+ * - UDR (UnderRun error) flag is cleared by a read operation to
+ * SPI_STS register (SPI_I2S_GetStatus()).
+ * - MODF (Mode Fault) flag is cleared by software sequence: a read/write
+ * operation to SPI_STS register (SPI_I2S_GetStatus()) followed by a
+ * write operation to SPI_CTRL1 register (SPI_Enable() to enable the SPI).
+ */
+void SPI_I2S_ClrCRCErrFlag(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_CLR_FLAG(SPI_I2S_FLAG));
+
+ /* Clear the selected SPI CRC Error (CRCERR) flag */
+ SPIx->STS = (uint16_t)~SPI_I2S_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified SPI/I2S interrupt has occurred or not.
+ * @param SPIx where x can be
+ * - 1, 2 or 3 in SPI mode
+ * - 2 or 3 in I2S mode
+ * @param SPI_I2S_IT specifies the SPI/I2S interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_I2S_INT_TE Transmit buffer empty interrupt.
+ * @arg SPI_I2S_INT_RNE Receive buffer not empty interrupt.
+ * @arg SPI_I2S_INT_OVER Overrun interrupt.
+ * @arg SPI_INT_MODERR Mode Fault interrupt.
+ * @arg SPI_INT_CRCERR CRC Error interrupt.
+ * @arg I2S_INT_UNDER Underrun Error interrupt.
+ * @return The new state of SPI_I2S_IT (SET or RESET).
+ */
+INTStatus SPI_I2S_GetIntStatus(SPI_Module* SPIx, uint8_t SPI_I2S_IT)
+{
+ INTStatus bitstatus = RESET;
+ uint16_t itpos = 0, itmask = 0, enablestatus = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_GET_INT(SPI_I2S_IT));
+
+ /* Get the SPI/I2S IT index */
+ itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+
+ /* Get the SPI/I2S IT mask */
+ itmask = SPI_I2S_IT >> 4;
+
+ /* Set the IT mask */
+ itmask = 0x01 << itmask;
+
+ /* Get the SPI_I2S_IT enable bit status */
+ enablestatus = (SPIx->CTRL2 & itmask);
+
+ /* Check the status of the specified SPI/I2S interrupt */
+ if (((SPIx->STS & itpos) != (uint16_t)RESET) && enablestatus)
+ {
+ /* SPI_I2S_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* SPI_I2S_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the SPI_I2S_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
+ * @param SPIx where x can be
+ * - 1, 2 or 3 in SPI mode
+ * @param SPI_I2S_IT specifies the SPI interrupt pending bit to clear.
+ * This function clears only CRCERR interrupt pending bit.
+ * @note
+ * - OVR (OverRun Error) interrupt pending bit is cleared by software
+ * sequence: a read operation to SPI_DAT register (SPI_I2S_ReceiveData())
+ * followed by a read operation to SPI_STS register (SPI_I2S_GetIntStatus()).
+ * - UDR (UnderRun Error) interrupt pending bit is cleared by a read
+ * operation to SPI_STS register (SPI_I2S_GetIntStatus()).
+ * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
+ * a read/write operation to SPI_STS register (SPI_I2S_GetIntStatus())
+ * followed by a write operation to SPI_CTRL1 register (SPI_Enable() to enable
+ * the SPI).
+ */
+void SPI_I2S_ClrITPendingBit(SPI_Module* SPIx, uint8_t SPI_I2S_IT)
+{
+ uint16_t itpos = 0;
+ /* Check the parameters */
+ assert_param(IS_SPI_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_CLR_INT(SPI_I2S_IT));
+
+ /* Get the SPI IT index */
+ itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+
+ /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
+ SPIx->STS = (uint16_t)~itpos;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_tim.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_tim.c
new file mode 100644
index 0000000000..c2836b15d1
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_tim.c
@@ -0,0 +1,3306 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_tim.c
+ * @author Nations
+ * @version v1.0.3
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32wb452_tim.h"
+#include "n32wb452_rcc.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup TIM
+ * @brief TIM driver modules
+ * @{
+ */
+
+/** @addtogroup TIM_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Defines
+ * @{
+ */
+
+/* ---------------------- TIM registers bit mask ------------------------ */
+#define SMCTRL_ETR_MASK ((uint16_t)0x00FF)
+#define CAPCMPMOD_OFFSET ((uint16_t)0x0018)
+#define CAPCMPEN_CCE_SET ((uint16_t)0x0001)
+#define CAPCMPEN_CCNE_SET ((uint16_t)0x0004)
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_FunctionPrototypes
+ * @{
+ */
+
+static void ConfigTI1(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter);
+static void ConfigTI2(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter);
+static void ConfigTI3(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter);
+static void ConfigTI4(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the TIMx peripheral registers to their default reset values.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ */
+void TIM_DeInit(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+
+ if (TIMx == TIM1)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM1, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM1, DISABLE);
+ }
+ else if (TIMx == TIM2)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM2, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM2, DISABLE);
+ }
+ else if (TIMx == TIM3)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM3, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM3, DISABLE);
+ }
+ else if (TIMx == TIM4)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM4, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM4, DISABLE);
+ }
+ else if (TIMx == TIM5)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM5, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM5, DISABLE);
+ }
+ else if (TIMx == TIM6)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM6, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM6, DISABLE);
+ }
+ else if (TIMx == TIM7)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM7, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM7, DISABLE);
+ }
+ else if (TIMx == TIM8)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM8, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM8, DISABLE);
+ }
+}
+
+/**
+ * @brief Initializes the TIMx Time Base Unit peripheral according to
+ * the specified parameters in the TIM_TimeBaseInitStruct.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_TimeBaseInitStruct pointer to a TIM_TimeBaseInitType
+ * structure that contains the configuration information for the
+ * specified TIM peripheral.
+ */
+void TIM_InitTimeBase(TIM_Module* TIMx, TIM_TimeBaseInitType* TIM_TimeBaseInitStruct)
+{
+ uint32_t tmpcr1 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimCntMode(TIM_TimeBaseInitStruct->CntMode));
+ assert_param(IsTimClkDiv(TIM_TimeBaseInitStruct->ClkDiv));
+
+ tmpcr1 = TIMx->CTRL1;
+
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5))
+ {
+ /* Select the Counter Mode */
+ tmpcr1 &= (uint32_t)(~((uint32_t)(TIM_CTRL1_DIR | TIM_CTRL1_CAMSEL)));
+ tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->CntMode;
+ }
+
+ if ((TIMx != TIM6) && (TIMx != TIM7))
+ {
+ /* Set the clock division */
+ tmpcr1 &= (uint32_t)(~((uint32_t)TIM_CTRL1_CLKD));
+ tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->ClkDiv;
+ }
+
+ TIMx->CTRL1 = tmpcr1;
+
+ /* Set the Autoreload value */
+ TIMx->AR = TIM_TimeBaseInitStruct->Period;
+
+ /* Set the Prescaler value */
+ TIMx->PSC = TIM_TimeBaseInitStruct->Prescaler;
+
+ if ((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ /* Set the Repetition Counter value */
+ TIMx->REPCNT = TIM_TimeBaseInitStruct->RepetCnt;
+ }
+
+ /* Generate an update event to reload the Prescaler and the Repetition counter
+ values immediately */
+ TIMx->EVTGEN = TIM_PSC_RELOAD_MODE_IMMEDIATE;
+
+ /*channel input from comp or iom*/
+ tmpcr1 = TIMx->CTRL1;
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5))
+ {
+ if (TIM_TimeBaseInitStruct->CapCh1FromCompEn)
+ tmpcr1 |= (0x01L << 11);
+ else
+ tmpcr1 &= ~(0x01L << 11);
+ }
+ if ((TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5))
+ {
+ if (TIM_TimeBaseInitStruct->CapCh2FromCompEn)
+ tmpcr1 |= (0x01L << 12);
+ else
+ tmpcr1 &= ~(0x01L << 12);
+ if (TIM_TimeBaseInitStruct->CapCh3FromCompEn)
+ tmpcr1 |= (0x01L << 13);
+ else
+ tmpcr1 &= ~(0x01L << 13);
+ }
+ if ((TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4))
+ {
+ if (TIM_TimeBaseInitStruct->CapCh4FromCompEn)
+ tmpcr1 |= (0x01L << 14);
+ else
+ tmpcr1 &= ~(0x01L << 14);
+ }
+ /*etr input from comp or iom*/
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4))
+ {
+ if (TIM_TimeBaseInitStruct->CapEtrClrFromCompEn)
+ tmpcr1 |= (0x01L << 15);
+ else
+ tmpcr1 &= ~(0x01L << 15);
+ }
+ TIMx->CTRL1 = tmpcr1;
+ /*sel etr from iom or tsc*/
+ tmpcr1 = TIMx->CTRL2;
+ if ((TIMx == TIM2) || (TIMx == TIM4))
+ {
+ if (TIM_TimeBaseInitStruct->CapEtrSelFromTscEn)
+ tmpcr1 |= (0x01L << 8);
+ else
+ tmpcr1 &= ~(0x01L << 8);
+ }
+ TIMx->CTRL2 = tmpcr1;
+}
+
+/**
+ * @brief Initializes the TIMx Channel1 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_InitOc1(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0;
+ uint32_t tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode));
+ assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState));
+ assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity));
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCEN &= (uint32_t)(~(uint32_t)TIM_CCEN_CC1EN);
+ /* Get the TIMx CCEN register value */
+ tmpccer = TIMx->CCEN;
+ /* Get the TIMx CTRL2 register value */
+ tmpcr2 = TIMx->CTRL2;
+
+ /* Get the TIMx CCMOD1 register value */
+ tmpccmrx = TIMx->CCMOD1;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_OC1M));
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_CC1SEL));
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= TIM_OCInitStruct->OcMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC1P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= TIM_OCInitStruct->OcPolarity;
+
+ /* Set the Output State */
+ tmpccer |= TIM_OCInitStruct->OutputState;
+
+ if ((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IsTimOutputNState(TIM_OCInitStruct->OutputNState));
+ assert_param(IsTimOcnPolarity(TIM_OCInitStruct->OcNPolarity));
+ assert_param(IsTimOcnIdleState(TIM_OCInitStruct->OcNIdleState));
+ assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC1NP));
+ /* Set the Output N Polarity */
+ tmpccer |= TIM_OCInitStruct->OcNPolarity;
+
+ /* Reset the Output N State */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC1NEN));
+ /* Set the Output N State */
+ tmpccer |= TIM_OCInitStruct->OutputNState;
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI1));
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI1N));
+
+ /* Set the Output Idle state */
+ tmpcr2 |= TIM_OCInitStruct->OcIdleState;
+ /* Set the Output N Idle state */
+ tmpcr2 |= TIM_OCInitStruct->OcNIdleState;
+ }
+ /* Write to TIMx CTRL2 */
+ TIMx->CTRL2 = tmpcr2;
+
+ /* Write to TIMx CCMOD1 */
+ TIMx->CCMOD1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCDAT1 = TIM_OCInitStruct->Pulse;
+
+ /* Write to TIMx CCEN */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel2 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select
+ * the TIM peripheral.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_InitOc2(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0;
+ uint32_t tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode));
+ assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState));
+ assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity));
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC2EN));
+
+ /* Get the TIMx CCEN register value */
+ tmpccer = TIMx->CCEN;
+ /* Get the TIMx CTRL2 register value */
+ tmpcr2 = TIMx->CTRL2;
+
+ /* Get the TIMx CCMOD1 register value */
+ tmpccmrx = TIMx->CCMOD1;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_OC2M));
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_CC2SEL));
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC2P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 4);
+
+ /* Set the Output State */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 4);
+
+ if ((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IsTimOutputNState(TIM_OCInitStruct->OutputNState));
+ assert_param(IsTimOcnPolarity(TIM_OCInitStruct->OcNPolarity));
+ assert_param(IsTimOcnIdleState(TIM_OCInitStruct->OcNIdleState));
+ assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC2NP));
+ /* Set the Output N Polarity */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OcNPolarity << 4);
+
+ /* Reset the Output N State */
+ tmpccer &= (uint32_t)(~((uint16_t)TIM_CCEN_CC2NEN));
+ /* Set the Output N State */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputNState << 4);
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI2));
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI2N));
+
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 2);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcNIdleState << 2);
+ }
+ /* Write to TIMx CTRL2 */
+ TIMx->CTRL2 = tmpcr2;
+
+ /* Write to TIMx CCMOD1 */
+ TIMx->CCMOD1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCDAT2 = TIM_OCInitStruct->Pulse;
+
+ /* Write to TIMx CCEN */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel3 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_InitOc3(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0;
+ uint32_t tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode));
+ assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState));
+ assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity));
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC3EN));
+
+ /* Get the TIMx CCEN register value */
+ tmpccer = TIMx->CCEN;
+ /* Get the TIMx CTRL2 register value */
+ tmpcr2 = TIMx->CTRL2;
+
+ /* Get the TIMx CCMOD2 register value */
+ tmpccmrx = TIMx->CCMOD2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_OC3MD));
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_CC3SEL));
+ /* Select the Output Compare Mode */
+ tmpccmrx |= TIM_OCInitStruct->OcMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)(~((uint16_t)TIM_CCEN_CC3P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 8);
+
+ /* Set the Output State */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 8);
+
+ if ((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IsTimOutputNState(TIM_OCInitStruct->OutputNState));
+ assert_param(IsTimOcnPolarity(TIM_OCInitStruct->OcNPolarity));
+ assert_param(IsTimOcnIdleState(TIM_OCInitStruct->OcNIdleState));
+ assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC3NP));
+ /* Set the Output N Polarity */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OcNPolarity << 8);
+ /* Reset the Output N State */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC3NEN));
+
+ /* Set the Output N State */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputNState << 8);
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI3));
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI3N));
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 4);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcNIdleState << 4);
+ }
+ /* Write to TIMx CTRL2 */
+ TIMx->CTRL2 = tmpcr2;
+
+ /* Write to TIMx CCMOD2 */
+ TIMx->CCMOD2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCDAT3 = TIM_OCInitStruct->Pulse;
+
+ /* Write to TIMx CCEN */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel4 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_InitOc4(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0;
+ uint32_t tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode));
+ assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState));
+ assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity));
+ /* Disable the Channel 2: Reset the CC4E Bit */
+ TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC4EN));
+
+ /* Get the TIMx CCEN register value */
+ tmpccer = TIMx->CCEN;
+ /* Get the TIMx CTRL2 register value */
+ tmpcr2 = TIMx->CTRL2;
+
+ /* Get the TIMx CCMOD2 register value */
+ tmpccmrx = TIMx->CCMOD2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_OC4MD));
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_CC4SEL));
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC4P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 12);
+
+ /* Set the Output State */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 12);
+
+ if ((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState));
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI4));
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 6);
+ }
+ /* Write to TIMx CTRL2 */
+ TIMx->CTRL2 = tmpcr2;
+
+ /* Write to TIMx CCMOD2 */
+ TIMx->CCMOD2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCDAT4 = TIM_OCInitStruct->Pulse;
+
+ /* Write to TIMx CCEN */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel5 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_InitOc5(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0;
+ uint32_t tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode));
+ assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState));
+ assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity));
+ /* Disable the Channel 5: Reset the CC5E Bit */
+ TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC5EN));
+
+ /* Get the TIMx CCEN register value */
+ tmpccer = TIMx->CCEN;
+ /* Get the TIMx CTRL2 register value */
+ tmpcr2 = TIMx->CTRL2;
+
+ /* Get the TIMx CCMOD3 register value */
+ tmpccmrx = TIMx->CCMOD3;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD3_OC5MD));
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC5P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 16);
+
+ /* Set the Output State */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 16);
+
+ if ((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState));
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI5));
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 8);
+ }
+ /* Write to TIMx CTRL2 */
+ TIMx->CTRL2 = tmpcr2;
+
+ /* Write to TIMx CCMOD3 */
+ TIMx->CCMOD3 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCDAT5 = TIM_OCInitStruct->Pulse;
+
+ /* Write to TIMx CCEN */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel6 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_InitOc6(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0;
+ uint32_t tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode));
+ assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState));
+ assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity));
+ /* Disable the Channel 6: Reset the CC6E Bit */
+ TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC6EN));
+
+ /* Get the TIMx CCEN register value */
+ tmpccer = TIMx->CCEN;
+ /* Get the TIMx CTRL2 register value */
+ tmpcr2 = TIMx->CTRL2;
+
+ /* Get the TIMx CCMOD3 register value */
+ tmpccmrx = TIMx->CCMOD3;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD3_OC6MD));
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC6P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 20);
+
+ /* Set the Output State */
+ tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 20);
+
+ if ((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState));
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI6));
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 10);
+ }
+ /* Write to TIMx CTRL2 */
+ TIMx->CTRL2 = tmpcr2;
+
+ /* Write to TIMx CCMOD3 */
+ TIMx->CCMOD3 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCDAT6 = TIM_OCInitStruct->Pulse;
+
+ /* Write to TIMx CCEN */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIM peripheral according to the specified
+ * parameters in the TIM_ICInitStruct.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_ICInitStruct pointer to a TIM_ICInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_ICInit(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IsTimCh(TIM_ICInitStruct->Channel));
+ assert_param(IsTimIcSelection(TIM_ICInitStruct->IcSelection));
+ assert_param(IsTimIcPrescaler(TIM_ICInitStruct->IcPrescaler));
+ assert_param(IsTimInCapFilter(TIM_ICInitStruct->IcFilter));
+
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5))
+ {
+ assert_param(IsTimIcPalaritySingleEdge(TIM_ICInitStruct->IcPolarity));
+ }
+ else
+ {
+ assert_param(IsTimIcPolarityAnyEdge(TIM_ICInitStruct->IcPolarity));
+ }
+ if (TIM_ICInitStruct->Channel == TIM_CH_1)
+ {
+ assert_param(IsTimList8Module(TIMx));
+ /* TI1 Configuration */
+ ConfigTI1(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap1Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ }
+ else if (TIM_ICInitStruct->Channel == TIM_CH_2)
+ {
+ assert_param(IsTimList6Module(TIMx));
+ /* TI2 Configuration */
+ ConfigTI2(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap2Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ }
+ else if (TIM_ICInitStruct->Channel == TIM_CH_3)
+ {
+ assert_param(IsTimList3Module(TIMx));
+ /* TI3 Configuration */
+ ConfigTI3(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap3Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ }
+ else
+ {
+ assert_param(IsTimList3Module(TIMx));
+ /* TI4 Configuration */
+ ConfigTI4(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap4Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ }
+}
+
+/**
+ * @brief Configures the TIM peripheral according to the specified
+ * parameters in the TIM_ICInitStruct to measure an external PWM signal.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param TIM_ICInitStruct pointer to a TIM_ICInitType structure
+ * that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_ConfigPwmIc(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct)
+{
+ uint16_t icoppositepolarity = TIM_IC_POLARITY_RISING;
+ uint16_t icoppositeselection = TIM_IC_SELECTION_DIRECTTI;
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ /* Select the Opposite Input Polarity */
+ if (TIM_ICInitStruct->IcPolarity == TIM_IC_POLARITY_RISING)
+ {
+ icoppositepolarity = TIM_IC_POLARITY_FALLING;
+ }
+ else
+ {
+ icoppositepolarity = TIM_IC_POLARITY_RISING;
+ }
+ /* Select the Opposite Input */
+ if (TIM_ICInitStruct->IcSelection == TIM_IC_SELECTION_DIRECTTI)
+ {
+ icoppositeselection = TIM_IC_SELECTION_INDIRECTTI;
+ }
+ else
+ {
+ icoppositeselection = TIM_IC_SELECTION_DIRECTTI;
+ }
+ if (TIM_ICInitStruct->Channel == TIM_CH_1)
+ {
+ /* TI1 Configuration */
+ ConfigTI1(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap1Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ /* TI2 Configuration */
+ ConfigTI2(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap2Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ }
+ else
+ {
+ /* TI2 Configuration */
+ ConfigTI2(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap2Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ /* TI1 Configuration */
+ ConfigTI1(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->IcFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetInCap1Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+ }
+}
+
+/**
+ * @brief Configures the: Break feature, dead time, Lock level, the OSSI,
+ * the OSSR State and the AOE(automatic output enable).
+ * @param TIMx where x can be 1 or 8 to select the TIM
+ * @param TIM_BDTRInitStruct pointer to a TIM_BDTRInitType structure that
+ * contains the BKDT Register configuration information for the TIM peripheral.
+ */
+void TIM_ConfigBkdt(TIM_Module* TIMx, TIM_BDTRInitType* TIM_BDTRInitStruct)
+{
+ uint32_t tmp;
+ /* Check the parameters */
+ assert_param(IsTimList2Module(TIMx));
+ assert_param(IsTimOssrState(TIM_BDTRInitStruct->OssrState));
+ assert_param(IsTimOssiState(TIM_BDTRInitStruct->OssiState));
+ assert_param(IsTimLockLevel(TIM_BDTRInitStruct->LockLevel));
+ assert_param(IsTimBreakInState(TIM_BDTRInitStruct->Break));
+ assert_param(IsTimBreakPalarity(TIM_BDTRInitStruct->BreakPolarity));
+ assert_param(IsTimAutoOutputState(TIM_BDTRInitStruct->AutomaticOutput));
+ /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */
+ TIMx->BKDT = (uint32_t)TIM_BDTRInitStruct->OssrState | TIM_BDTRInitStruct->OssiState | TIM_BDTRInitStruct->LockLevel
+ | TIM_BDTRInitStruct->DeadTime | TIM_BDTRInitStruct->Break | TIM_BDTRInitStruct->BreakPolarity
+ | TIM_BDTRInitStruct->AutomaticOutput;
+
+ /*cofigure other break in*/
+ tmp = TIMx->CTRL1;
+ /*IOMBKPEN 0 meaning iom as break enable*/
+ if (TIM_BDTRInitStruct->IomBreakEn)
+ tmp &= ~(0x01L << 10);
+ else
+ tmp |= (0x01L << 10);
+ if (TIM_BDTRInitStruct->LockUpBreakEn)
+ tmp |= (0x01L << 16);
+ else
+ tmp &= ~(0x01L << 16);
+ if (TIM_BDTRInitStruct->PvdBreakEn)
+ tmp |= (0x01L << 17);
+ else
+ tmp &= ~(0x01L << 17);
+ TIMx->CTRL1 = tmp;
+}
+
+/**
+ * @brief Fills each TIM_TimeBaseInitStruct member with its default value.
+ * @param TIM_TimeBaseInitStruct pointer to a TIM_TimeBaseInitType
+ * structure which will be initialized.
+ */
+void TIM_InitTimBaseStruct(TIM_TimeBaseInitType* TIM_TimeBaseInitStruct)
+{
+ /* Set the default configuration */
+ TIM_TimeBaseInitStruct->Period = 0xFFFF;
+ TIM_TimeBaseInitStruct->Prescaler = 0x0000;
+ TIM_TimeBaseInitStruct->ClkDiv = TIM_CLK_DIV1;
+ TIM_TimeBaseInitStruct->CntMode = TIM_CNT_MODE_UP;
+ TIM_TimeBaseInitStruct->RepetCnt = 0x0000;
+
+ TIM_TimeBaseInitStruct->CapCh1FromCompEn = false;
+ TIM_TimeBaseInitStruct->CapCh2FromCompEn = false;
+ TIM_TimeBaseInitStruct->CapCh3FromCompEn = false;
+ TIM_TimeBaseInitStruct->CapCh4FromCompEn = false;
+ TIM_TimeBaseInitStruct->CapEtrClrFromCompEn = false;
+ TIM_TimeBaseInitStruct->CapEtrSelFromTscEn = false;
+}
+
+/**
+ * @brief Fills each TIM_OCInitStruct member with its default value.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure which will
+ * be initialized.
+ */
+void TIM_InitOcStruct(OCInitType* TIM_OCInitStruct)
+{
+ /* Set the default configuration */
+ TIM_OCInitStruct->OcMode = TIM_OCMODE_TIMING;
+ TIM_OCInitStruct->OutputState = TIM_OUTPUT_STATE_DISABLE;
+ TIM_OCInitStruct->OutputNState = TIM_OUTPUT_NSTATE_DISABLE;
+ TIM_OCInitStruct->Pulse = 0x0000;
+ TIM_OCInitStruct->OcPolarity = TIM_OC_POLARITY_HIGH;
+ TIM_OCInitStruct->OcNPolarity = TIM_OC_POLARITY_HIGH;
+ TIM_OCInitStruct->OcIdleState = TIM_OC_IDLE_STATE_RESET;
+ TIM_OCInitStruct->OcNIdleState = TIM_OCN_IDLE_STATE_RESET;
+}
+
+/**
+ * @brief Fills each TIM_ICInitStruct member with its default value.
+ * @param TIM_ICInitStruct pointer to a TIM_ICInitType structure which will
+ * be initialized.
+ */
+void TIM_InitIcStruct(TIM_ICInitType* TIM_ICInitStruct)
+{
+ /* Set the default configuration */
+ TIM_ICInitStruct->Channel = TIM_CH_1;
+ TIM_ICInitStruct->IcPolarity = TIM_IC_POLARITY_RISING;
+ TIM_ICInitStruct->IcSelection = TIM_IC_SELECTION_DIRECTTI;
+ TIM_ICInitStruct->IcPrescaler = TIM_IC_PSC_DIV1;
+ TIM_ICInitStruct->IcFilter = 0x00;
+}
+
+/**
+ * @brief Fills each TIM_BDTRInitStruct member with its default value.
+ * @param TIM_BDTRInitStruct pointer to a TIM_BDTRInitType structure which
+ * will be initialized.
+ */
+void TIM_InitBkdtStruct(TIM_BDTRInitType* TIM_BDTRInitStruct)
+{
+ /* Set the default configuration */
+ TIM_BDTRInitStruct->OssrState = TIM_OSSR_STATE_DISABLE;
+ TIM_BDTRInitStruct->OssiState = TIM_OSSI_STATE_DISABLE;
+ TIM_BDTRInitStruct->LockLevel = TIM_LOCK_LEVEL_OFF;
+ TIM_BDTRInitStruct->DeadTime = 0x00;
+ TIM_BDTRInitStruct->Break = TIM_BREAK_IN_DISABLE;
+ TIM_BDTRInitStruct->BreakPolarity = TIM_BREAK_POLARITY_LOW;
+ TIM_BDTRInitStruct->AutomaticOutput = TIM_AUTO_OUTPUT_DISABLE;
+}
+
+/**
+ * @brief Enables or disables the specified TIM peripheral.
+ * @param TIMx where x can be 1 to 8 to select the TIMx peripheral.
+ * @param Cmd new state of the TIMx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_Enable(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the TIM Counter */
+ TIMx->CTRL1 |= TIM_CTRL1_CNTEN;
+ }
+ else
+ {
+ /* Disable the TIM Counter */
+ TIMx->CTRL1 &= (uint32_t)(~((uint32_t)TIM_CTRL1_CNTEN));
+ }
+}
+
+/**
+ * @brief Enables or disables the TIM peripheral Main Outputs.
+ * @param TIMx where x can be 1, 8 to select the TIMx peripheral.
+ * @param Cmd new state of the TIM peripheral Main Outputs.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_EnableCtrlPwmOutputs(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimList2Module(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the TIM Main Output */
+ TIMx->BKDT |= TIM_BKDT_MOEN;
+ }
+ else
+ {
+ /* Disable the TIM Main Output */
+ TIMx->BKDT &= (uint16_t)(~((uint16_t)TIM_BKDT_MOEN));
+ }
+}
+
+/**
+ * @brief Enables or disables the specified TIM interrupts.
+ * @param TIMx where x can be 1 to 8 to select the TIMx peripheral.
+ * @param TIM_IT specifies the TIM interrupts sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_INT_UPDATE TIM update Interrupt source
+ * @arg TIM_INT_CC1 TIM Capture Compare 1 Interrupt source
+ * @arg TIM_INT_CC2 TIM Capture Compare 2 Interrupt source
+ * @arg TIM_INT_CC3 TIM Capture Compare 3 Interrupt source
+ * @arg TIM_INT_CC4 TIM Capture Compare 4 Interrupt source
+ * @arg TIM_INT_COM TIM Commutation Interrupt source
+ * @arg TIM_INT_TRIG TIM Trigger Interrupt source
+ * @arg TIM_INT_BREAK TIM Break Interrupt source
+ * @note
+ * - TIM6 and TIM7 can only generate an update interrupt.
+ * - TIM_INT_BREAK is used only with TIM1, TIM8.
+ * - TIM_INT_COM is used only with TIM1, TIM8.
+ * @param Cmd new state of the TIM interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_ConfigInt(TIM_Module* TIMx, uint16_t TIM_IT, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimInt(TIM_IT));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the Interrupt sources */
+ TIMx->DINTEN |= TIM_IT;
+ }
+ else
+ {
+ /* Disable the Interrupt sources */
+ TIMx->DINTEN &= (uint16_t)~TIM_IT;
+ }
+}
+
+/**
+ * @brief Configures the TIMx event to be generate by software.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_EventSource specifies the event source.
+ * This parameter can be one or more of the following values:
+ * @arg TIM_EVT_SRC_UPDATE Timer update Event source
+ * @arg TIM_EVT_SRC_CC1 Timer Capture Compare 1 Event source
+ * @arg TIM_EVT_SRC_CC2 Timer Capture Compare 2 Event source
+ * @arg TIM_EVT_SRC_CC3 Timer Capture Compare 3 Event source
+ * @arg TIM_EVT_SRC_CC4 Timer Capture Compare 4 Event source
+ * @arg TIM_EVT_SRC_COM Timer COM event source
+ * @arg TIM_EVT_SRC_TRIG Timer Trigger Event source
+ * @arg TIM_EVT_SRC_BREAK Timer Break event source
+ * @note
+ * - TIM6 and TIM7 can only generate an update event.
+ * - TIM_EVT_SRC_COM and TIM_EVT_SRC_BREAK are used only with TIM1 and TIM8.
+ */
+void TIM_GenerateEvent(TIM_Module* TIMx, uint16_t TIM_EventSource)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimEvtSrc(TIM_EventSource));
+
+ /* Set the event sources */
+ TIMx->EVTGEN = TIM_EventSource;
+}
+
+/**
+ * @brief Configures the TIMx's DMA interface.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select
+ * the TIM peripheral.
+ * @param TIM_DMABase DMA Base address.
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABase_CR, TIM_DMABASE_CTRL2, TIM_DMABASE_SMCTRL,
+ * TIM_DMABASE_DMAINTEN, TIM1_DMABase_SR, TIM_DMABASE_EVTGEN,
+ * TIM_DMABASE_CAPCMPMOD1, TIM_DMABASE_CAPCMPMOD2, TIM_DMABASE_CAPCMPEN,
+ * TIM_DMABASE_CNT, TIM_DMABASE_PSC, TIM_DMABASE_AR,
+ * TIM_DMABASE_REPCNT, TIM_DMABASE_CAPCMPDAT1, TIM_DMABASE_CAPCMPDAT2,
+ * TIM_DMABASE_CAPCMPDAT3, TIM_DMABASE_CAPCMPDAT4, TIM_DMABASE_BKDT,
+ * TIM_DMABASE_DMACTRL.
+ * @param TIM_DMABurstLength DMA Burst length.
+ * This parameter can be one value between:
+ * TIM_DMABURST_LENGTH_1TRANSFER and TIM_DMABURST_LENGTH_18TRANSFERS.
+ */
+void TIM_ConfigDma(TIM_Module* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
+{
+ /* Check the parameters */
+ assert_param(IsTimList4Module(TIMx));
+ assert_param(IsTimDmaBase(TIM_DMABase));
+ assert_param(IsTimDmaLength(TIM_DMABurstLength));
+ /* Set the DMA Base and the DMA Burst Length */
+ TIMx->DCTRL = TIM_DMABase | TIM_DMABurstLength;
+}
+
+/**
+ * @brief Enables or disables the TIMx's DMA Requests.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 6, 7, 8
+ * to select the TIM peripheral.
+ * @param TIM_DMASource specifies the DMA Request sources.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_DMA_UPDATE TIM update Interrupt source
+ * @arg TIM_DMA_CC1 TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2 TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3 TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4 TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM TIM Commutation DMA source
+ * @arg TIM_DMA_TRIG TIM Trigger DMA source
+ * @param Cmd new state of the DMA Request sources.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_EnableDma(TIM_Module* TIMx, uint16_t TIM_DMASource, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimList9Module(TIMx));
+ assert_param(IsTimDmaSrc(TIM_DMASource));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the DMA sources */
+ TIMx->DINTEN |= TIM_DMASource;
+ }
+ else
+ {
+ /* Disable the DMA sources */
+ TIMx->DINTEN &= (uint16_t)~TIM_DMASource;
+ }
+}
+
+/**
+ * @brief Configures the TIMx internal Clock
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8
+ * to select the TIM peripheral.
+ */
+void TIM_ConfigInternalClk(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ /* Disable slave mode to clock the prescaler directly with the internal clock */
+ TIMx->SMCTRL &= (uint16_t)(~((uint16_t)TIM_SMCTRL_SMSEL));
+}
+
+/**
+ * @brief Configures the TIMx Internal Trigger as External Clock
+ * @param TIMx where x can be 1, 2, 3, 4, 5 to select the TIM peripheral.
+ * @param TIM_InputTriggerSource Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TRIG_SEL_IN_TR0 Internal Trigger 0
+ * @arg TIM_TRIG_SEL_IN_TR1 Internal Trigger 1
+ * @arg TIM_TRIG_SEL_IN_TR2 Internal Trigger 2
+ * @arg TIM_TRIG_SEL_IN_TR3 Internal Trigger 3
+ */
+void TIM_ConfigInternalTrigToExt(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimInterTrigSel(TIM_InputTriggerSource));
+ /* Select the Internal Trigger */
+ TIM_SelectInputTrig(TIMx, TIM_InputTriggerSource);
+ /* Select the External clock mode1 */
+ TIMx->SMCTRL |= TIM_SLAVE_MODE_EXT1;
+}
+
+/**
+ * @brief Configures the TIMx Trigger as External Clock
+ * @param TIMx where x can be 1, 2, 3, 4, 5 to select the TIM peripheral.
+ * @param TIM_TIxExternalCLKSource Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_EXT_CLK_SRC_TI1ED TI1 Edge Detector
+ * @arg TIM_EXT_CLK_SRC_TI1 Filtered Timer Input 1
+ * @arg TIM_EXT_CLK_SRC_TI2 Filtered Timer Input 2
+ * @param IcPolarity specifies the TIx Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_POLARITY_RISING
+ * @arg TIM_IC_POLARITY_FALLING
+ * @param ICFilter specifies the filter value.
+ * This parameter must be a value between 0x0 and 0xF.
+ */
+void TIM_ConfigExtTrigAsClk(TIM_Module* TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t IcPolarity, uint16_t ICFilter)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimExtClkSrc(TIM_TIxExternalCLKSource));
+ assert_param(IsTimIcPalaritySingleEdge(IcPolarity));
+ assert_param(IsTimInCapFilter(ICFilter));
+ /* Configure the Timer Input Clock Source */
+ if (TIM_TIxExternalCLKSource == TIM_EXT_CLK_SRC_TI2)
+ {
+ ConfigTI2(TIMx, IcPolarity, TIM_IC_SELECTION_DIRECTTI, ICFilter);
+ }
+ else
+ {
+ ConfigTI1(TIMx, IcPolarity, TIM_IC_SELECTION_DIRECTTI, ICFilter);
+ }
+ /* Select the Trigger source */
+ TIM_SelectInputTrig(TIMx, TIM_TIxExternalCLKSource);
+ /* Select the External clock mode1 */
+ TIMx->SMCTRL |= TIM_SLAVE_MODE_EXT1;
+}
+
+/**
+ * @brief Configures the External clock Mode1
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_EXT_TRG_PSC_OFF ETRP Prescaler OFF.
+ * @arg TIM_EXT_TRG_PSC_DIV2 ETRP frequency divided by 2.
+ * @arg TIM_EXT_TRG_PSC_DIV4 ETRP frequency divided by 4.
+ * @arg TIM_EXT_TRG_PSC_DIV8 ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_EXT_TRIG_POLARITY_INVERTED active low or falling edge active.
+ * @arg TIM_EXT_TRIG_POLARITY_NONINVERTED active high or rising edge active.
+ * @param ExtTRGFilter External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ */
+void TIM_ConfigExtClkMode1(TIM_Module* TIMx,
+ uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter)
+{
+ uint16_t tmpsmcr = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimExtPreDiv(TIM_ExtTRGPrescaler));
+ assert_param(IsTimExtTrigPolarity(TIM_ExtTRGPolarity));
+ assert_param(IsTimExtTrigFilter(ExtTRGFilter));
+ /* Configure the ETR Clock source */
+ TIM_ConfigExtTrig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+
+ /* Get the TIMx SMCTRL register value */
+ tmpsmcr = TIMx->SMCTRL;
+ /* Reset the SMS Bits */
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_SMSEL));
+ /* Select the External clock mode1 */
+ tmpsmcr |= TIM_SLAVE_MODE_EXT1;
+ /* Select the Trigger selection : ETRF */
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_TSEL));
+ tmpsmcr |= TIM_TRIG_SEL_ETRF;
+ /* Write to TIMx SMCTRL */
+ TIMx->SMCTRL = tmpsmcr;
+}
+
+/**
+ * @brief Configures the External clock Mode2
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_EXT_TRG_PSC_OFF ETRP Prescaler OFF.
+ * @arg TIM_EXT_TRG_PSC_DIV2 ETRP frequency divided by 2.
+ * @arg TIM_EXT_TRG_PSC_DIV4 ETRP frequency divided by 4.
+ * @arg TIM_EXT_TRG_PSC_DIV8 ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_EXT_TRIG_POLARITY_INVERTED active low or falling edge active.
+ * @arg TIM_EXT_TRIG_POLARITY_NONINVERTED active high or rising edge active.
+ * @param ExtTRGFilter External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ */
+void TIM_ConfigExtClkMode2(TIM_Module* TIMx,
+ uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter)
+{
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimExtPreDiv(TIM_ExtTRGPrescaler));
+ assert_param(IsTimExtTrigPolarity(TIM_ExtTRGPolarity));
+ assert_param(IsTimExtTrigFilter(ExtTRGFilter));
+ /* Configure the ETR Clock source */
+ TIM_ConfigExtTrig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+ /* Enable the External clock mode2 */
+ TIMx->SMCTRL |= TIM_SMCTRL_EXCEN;
+}
+
+/**
+ * @brief Configures the TIMx External Trigger (ETR).
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_EXT_TRG_PSC_OFF ETRP Prescaler OFF.
+ * @arg TIM_EXT_TRG_PSC_DIV2 ETRP frequency divided by 2.
+ * @arg TIM_EXT_TRG_PSC_DIV4 ETRP frequency divided by 4.
+ * @arg TIM_EXT_TRG_PSC_DIV8 ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_EXT_TRIG_POLARITY_INVERTED active low or falling edge active.
+ * @arg TIM_EXT_TRIG_POLARITY_NONINVERTED active high or rising edge active.
+ * @param ExtTRGFilter External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ */
+void TIM_ConfigExtTrig(TIM_Module* TIMx,
+ uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter)
+{
+ uint16_t tmpsmcr = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimExtPreDiv(TIM_ExtTRGPrescaler));
+ assert_param(IsTimExtTrigPolarity(TIM_ExtTRGPolarity));
+ assert_param(IsTimExtTrigFilter(ExtTRGFilter));
+ tmpsmcr = TIMx->SMCTRL;
+ /* Reset the ETR Bits */
+ tmpsmcr &= SMCTRL_ETR_MASK;
+ /* Set the Prescaler, the Filter value and the Polarity */
+ tmpsmcr |=
+ (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
+ /* Write to TIMx SMCTRL */
+ TIMx->SMCTRL = tmpsmcr;
+}
+
+/**
+ * @brief Configures the TIMx Prescaler.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param Prescaler specifies the Prescaler Register value
+ * @param TIM_PSCReloadMode specifies the TIM Prescaler Reload mode
+ * This parameter can be one of the following values:
+ * @arg TIM_PSC_RELOAD_MODE_UPDATE The Prescaler is loaded at the update event.
+ * @arg TIM_PSC_RELOAD_MODE_IMMEDIATE The Prescaler is loaded immediately.
+ */
+void TIM_ConfigPrescaler(TIM_Module* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimPscReloadMode(TIM_PSCReloadMode));
+ /* Set the Prescaler value */
+ TIMx->PSC = Prescaler;
+ /* Set or reset the UG Bit */
+ TIMx->EVTGEN = TIM_PSCReloadMode;
+}
+
+/**
+ * @brief Specifies the TIMx Counter Mode to be used.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param CntMode specifies the Counter Mode to be used
+ * This parameter can be one of the following values:
+ * @arg TIM_CNT_MODE_UP TIM Up Counting Mode
+ * @arg TIM_CNT_MODE_DOWN TIM Down Counting Mode
+ * @arg TIM_CNT_MODE_CENTER_ALIGN1 TIM Center Aligned Mode1
+ * @arg TIM_CNT_MODE_CENTER_ALIGN2 TIM Center Aligned Mode2
+ * @arg TIM_CNT_MODE_CENTER_ALIGN3 TIM Center Aligned Mode3
+ */
+void TIM_ConfigCntMode(TIM_Module* TIMx, uint16_t CntMode)
+{
+ uint32_t tmpcr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimCntMode(CntMode));
+ tmpcr1 = TIMx->CTRL1;
+ /* Reset the CMS and DIR Bits */
+ tmpcr1 &= (uint32_t)(~((uint32_t)(TIM_CTRL1_DIR | TIM_CTRL1_CAMSEL)));
+ /* Set the Counter Mode */
+ tmpcr1 |= CntMode;
+ /* Write to TIMx CTRL1 register */
+ TIMx->CTRL1 = tmpcr1;
+}
+
+/**
+ * @brief Selects the Input Trigger source
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param TIM_InputTriggerSource The Input Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TRIG_SEL_IN_TR0 Internal Trigger 0
+ * @arg TIM_TRIG_SEL_IN_TR1 Internal Trigger 1
+ * @arg TIM_TRIG_SEL_IN_TR2 Internal Trigger 2
+ * @arg TIM_TRIG_SEL_IN_TR3 Internal Trigger 3
+ * @arg TIM_TRIG_SEL_TI1F_ED TI1 Edge Detector
+ * @arg TIM_TRIG_SEL_TI1FP1 Filtered Timer Input 1
+ * @arg TIM_TRIG_SEL_TI2FP2 Filtered Timer Input 2
+ * @arg TIM_TRIG_SEL_ETRF External Trigger input
+ */
+void TIM_SelectInputTrig(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource)
+{
+ uint16_t tmpsmcr = 0;
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimTrigSel(TIM_InputTriggerSource));
+ /* Get the TIMx SMCTRL register value */
+ tmpsmcr = TIMx->SMCTRL;
+ /* Reset the TS Bits */
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_TSEL));
+ /* Set the Input Trigger source */
+ tmpsmcr |= TIM_InputTriggerSource;
+ /* Write to TIMx SMCTRL */
+ TIMx->SMCTRL = tmpsmcr;
+}
+
+/**
+ * @brief Configures the TIMx Encoder Interface.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_EncoderMode specifies the TIMx Encoder Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_ENCODE_MODE_TI1 Counter counts on TI1FP1 edge depending on TI2FP2 level.
+ * @arg TIM_ENCODE_MODE_TI2 Counter counts on TI2FP2 edge depending on TI1FP1 level.
+ * @arg TIM_ENCODE_MODE_TI12 Counter counts on both TI1FP1 and TI2FP2 edges depending
+ * on the level of the other input.
+ * @param TIM_IC1Polarity specifies the IC1 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_POLARITY_FALLING IC Falling edge.
+ * @arg TIM_IC_POLARITY_RISING IC Rising edge.
+ * @param TIM_IC2Polarity specifies the IC2 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_POLARITY_FALLING IC Falling edge.
+ * @arg TIM_IC_POLARITY_RISING IC Rising edge.
+ */
+void TIM_ConfigEncoderInterface(TIM_Module* TIMx,
+ uint16_t TIM_EncoderMode,
+ uint16_t TIM_IC1Polarity,
+ uint16_t TIM_IC2Polarity)
+{
+ uint16_t tmpsmcr = 0;
+ uint16_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList5Module(TIMx));
+ assert_param(IsTimEncodeMode(TIM_EncoderMode));
+ assert_param(IsTimIcPalaritySingleEdge(TIM_IC1Polarity));
+ assert_param(IsTimIcPalaritySingleEdge(TIM_IC2Polarity));
+
+ /* Get the TIMx SMCTRL register value */
+ tmpsmcr = TIMx->SMCTRL;
+
+ /* Get the TIMx CCMOD1 register value */
+ tmpccmr1 = TIMx->CCMOD1;
+
+ /* Get the TIMx CCEN register value */
+ tmpccer = TIMx->CCEN;
+
+ /* Set the encoder Mode */
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_SMSEL));
+ tmpsmcr |= TIM_EncoderMode;
+
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+ tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD1_CC1SEL)) & (uint16_t)(~((uint16_t)TIM_CCMOD1_CC2SEL)));
+ tmpccmr1 |= TIM_CCMOD1_CC1SEL_0 | TIM_CCMOD1_CC2SEL_0;
+
+ /* Set the TI1 and the TI2 Polarities */
+ tmpccer &= (uint32_t)(((uint32_t) ~((uint32_t)TIM_CCEN_CC1P)) & ((uint32_t) ~((uint32_t)TIM_CCEN_CC2P)));
+ tmpccer |= (uint32_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
+
+ /* Write to TIMx SMCTRL */
+ TIMx->SMCTRL = tmpsmcr;
+ /* Write to TIMx CCMOD1 */
+ TIMx->CCMOD1 = tmpccmr1;
+ /* Write to TIMx CCEN */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Forces the TIMx output 1 waveform to active or inactive level.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC1REF
+ * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC1REF.
+ */
+void TIM_ConfigForcedOc1(TIM_Module* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimForceActive(TIM_ForcedAction));
+ tmpccmr1 = TIMx->CCMOD1;
+ /* Reset the OC1M Bits */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1M);
+ /* Configure The Forced output Mode */
+ tmpccmr1 |= TIM_ForcedAction;
+ /* Write to TIMx CCMOD1 register */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Forces the TIMx output 2 waveform to active or inactive level.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC2REF
+ * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC2REF.
+ */
+void TIM_ConfigForcedOc2(TIM_Module* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimForceActive(TIM_ForcedAction));
+ tmpccmr1 = TIMx->CCMOD1;
+ /* Reset the OC2M Bits */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2M);
+ /* Configure The Forced output Mode */
+ tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
+ /* Write to TIMx CCMOD1 register */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Forces the TIMx output 3 waveform to active or inactive level.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC3REF
+ * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC3REF.
+ */
+void TIM_ConfigForcedOc3(TIM_Module* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimForceActive(TIM_ForcedAction));
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC1M Bits */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3MD);
+ /* Configure The Forced output Mode */
+ tmpccmr2 |= TIM_ForcedAction;
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Forces the TIMx output 4 waveform to active or inactive level.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC4REF
+ * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC4REF.
+ */
+void TIM_ConfigForcedOc4(TIM_Module* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimForceActive(TIM_ForcedAction));
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC2M Bits */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4MD);
+ /* Configure The Forced output Mode */
+ tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Forces the TIMx output 5 waveform to active or inactive level.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC5REF
+ * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC5REF.
+ */
+void TIM_ConfigForcedOc5(TIM_Module* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimForceActive(TIM_ForcedAction));
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC2M Bits */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5MD);
+ /* Configure The Forced output Mode */
+ tmpccmr3 |= (uint16_t)(TIM_ForcedAction);
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Forces the TIMx output 6 waveform to active or inactive level.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC6REF
+ * @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC6REF.
+ */
+void TIM_ConfigForcedOc6(TIM_Module* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimForceActive(TIM_ForcedAction));
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC2M Bits */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6MD);
+ /* Configure The Forced output Mode */
+ tmpccmr3 |= (uint16_t)(TIM_ForcedAction << 8);
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Enables or disables TIMx peripheral Preload register on AR.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param Cmd new state of the TIMx peripheral Preload register
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_ConfigArPreload(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set the AR Preload Bit */
+ TIMx->CTRL1 |= TIM_CTRL1_ARPEN;
+ }
+ else
+ {
+ /* Reset the AR Preload Bit */
+ TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_ARPEN);
+ }
+}
+
+/**
+ * @brief Selects the TIM peripheral Commutation event.
+ * @param TIMx where x can be 1, 8 to select the TIMx peripheral
+ * @param Cmd new state of the Commutation event.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_SelectComEvt(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimList2Module(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set the COM Bit */
+ TIMx->CTRL2 |= TIM_CTRL2_CCUSEL;
+ }
+ else
+ {
+ /* Reset the COM Bit */
+ TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_CCUSEL);
+ }
+}
+
+/**
+ * @brief Selects the TIMx peripheral Capture Compare DMA source.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select
+ * the TIM peripheral.
+ * @param Cmd new state of the Capture Compare DMA source
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_SelectCapCmpDmaSrc(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimList4Module(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set the CCDS Bit */
+ TIMx->CTRL2 |= TIM_CTRL2_CCDSEL;
+ }
+ else
+ {
+ /* Reset the CCDS Bit */
+ TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_CCDSEL);
+ }
+}
+
+/**
+ * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8
+ * to select the TIMx peripheral
+ * @param Cmd new state of the Capture Compare Preload Control bit
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_EnableCapCmpPreloadControl(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimList5Module(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set the CCPC Bit */
+ TIMx->CTRL2 |= TIM_CTRL2_CCPCTL;
+ }
+ else
+ {
+ /* Reset the CCPC Bit */
+ TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_CCPCTL);
+ }
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCDAT1.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_OCPreload new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_PRE_LOAD_ENABLE
+ * @arg TIM_OC_PRE_LOAD_DISABLE
+ */
+void TIM_ConfigOc1Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimOcPreLoadState(TIM_OCPreload));
+ tmpccmr1 = TIMx->CCMOD1;
+ /* Reset the OC1PE Bit */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1PEN);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr1 |= TIM_OCPreload;
+ /* Write to TIMx CCMOD1 register */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCDAT2.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select
+ * the TIM peripheral.
+ * @param TIM_OCPreload new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_PRE_LOAD_ENABLE
+ * @arg TIM_OC_PRE_LOAD_DISABLE
+ */
+void TIM_ConfigOc2Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimOcPreLoadState(TIM_OCPreload));
+ tmpccmr1 = TIMx->CCMOD1;
+ /* Reset the OC2PE Bit */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2PEN);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
+ /* Write to TIMx CCMOD1 register */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCDAT3.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_PRE_LOAD_ENABLE
+ * @arg TIM_OC_PRE_LOAD_DISABLE
+ */
+void TIM_ConfigOc3Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcPreLoadState(TIM_OCPreload));
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC3PE Bit */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3PEN);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr2 |= TIM_OCPreload;
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCDAT4.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_PRE_LOAD_ENABLE
+ * @arg TIM_OC_PRE_LOAD_DISABLE
+ */
+void TIM_ConfigOc4Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcPreLoadState(TIM_OCPreload));
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC4PE Bit */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4PEN);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCDAT5.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_PRE_LOAD_ENABLE
+ * @arg TIM_OC_PRE_LOAD_DISABLE
+ */
+void TIM_ConfigOc5Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcPreLoadState(TIM_OCPreload));
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC5PE Bit */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5PEN);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr3 |= (uint16_t)(TIM_OCPreload);
+ /* Write to TIMx CCMOD3 register */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCDAT6.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_PRE_LOAD_ENABLE
+ * @arg TIM_OC_PRE_LOAD_DISABLE
+ */
+void TIM_ConfigOc6Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcPreLoadState(TIM_OCPreload));
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC6PE Bit */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6PEN);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr3 |= (uint16_t)(TIM_OCPreload << 8);
+ /* Write to TIMx CCMOD3 register */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 1 Fast feature.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_OCFast new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable
+ * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable
+ */
+void TIM_ConfigOc1Fast(TIM_Module* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimOcFastState(TIM_OCFast));
+ /* Get the TIMx CCMOD1 register value */
+ tmpccmr1 = TIMx->CCMOD1;
+ /* Reset the OC1FE Bit */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1FEN);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr1 |= TIM_OCFast;
+ /* Write to TIMx CCMOD1 */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 2 Fast feature.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select
+ * the TIM peripheral.
+ * @param TIM_OCFast new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable
+ * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable
+ */
+void TIM_ConfigOc2Fast(TIM_Module* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimOcFastState(TIM_OCFast));
+ /* Get the TIMx CCMOD1 register value */
+ tmpccmr1 = TIMx->CCMOD1;
+ /* Reset the OC2FE Bit */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2FEN);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
+ /* Write to TIMx CCMOD1 */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 3 Fast feature.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable
+ * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable
+ */
+void TIM_ConfigOc3Fast(TIM_Module* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcFastState(TIM_OCFast));
+ /* Get the TIMx CCMOD2 register value */
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC3FE Bit */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3FEN);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr2 |= TIM_OCFast;
+ /* Write to TIMx CCMOD2 */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 4 Fast feature.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable
+ * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable
+ */
+void TIM_ConfigOc4Fast(TIM_Module* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcFastState(TIM_OCFast));
+ /* Get the TIMx CCMOD2 register value */
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC4FE Bit */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4FEN);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
+ /* Write to TIMx CCMOD2 */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 5 Fast feature.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable
+ * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable
+ */
+void TIM_ConfigOc5Fast(TIM_Module* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcFastState(TIM_OCFast));
+ /* Get the TIMx CCMOD2 register value */
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC4FE Bit */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5FEN);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr3 |= (uint16_t)(TIM_OCFast);
+ /* Write to TIMx CCMOD3 */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 6 Fast feature.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_FAST_ENABLE TIM output compare fast enable
+ * @arg TIM_OC_FAST_DISABLE TIM output compare fast disable
+ */
+void TIM_ConfigOc6Fast(TIM_Module* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcFastState(TIM_OCFast));
+ /* Get the TIMx CCMOD2 register value */
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC4FE Bit */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6FEN);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr3 |= (uint16_t)(TIM_OCFast << 8);
+ /* Write to TIMx CCMOD3 */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF1 signal on an external event
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_CLR_ENABLE TIM Output clear enable
+ * @arg TIM_OC_CLR_DISABLE TIM Output clear disable
+ */
+void TIM_ClrOc1Ref(TIM_Module* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcClrState(TIM_OCClear));
+
+ tmpccmr1 = TIMx->CCMOD1;
+
+ /* Reset the OC1CE Bit */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1CEN);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr1 |= TIM_OCClear;
+ /* Write to TIMx CCMOD1 register */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF2 signal on an external event
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_CLR_ENABLE TIM Output clear enable
+ * @arg TIM_OC_CLR_DISABLE TIM Output clear disable
+ */
+void TIM_ClrOc2Ref(TIM_Module* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcClrState(TIM_OCClear));
+ tmpccmr1 = TIMx->CCMOD1;
+ /* Reset the OC2CE Bit */
+ tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2CEN);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
+ /* Write to TIMx CCMOD1 register */
+ TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF3 signal on an external event
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_CLR_ENABLE TIM Output clear enable
+ * @arg TIM_OC_CLR_DISABLE TIM Output clear disable
+ */
+void TIM_ClrOc3Ref(TIM_Module* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcClrState(TIM_OCClear));
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC3CE Bit */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3CEN);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr2 |= TIM_OCClear;
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF4 signal on an external event
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_CLR_ENABLE TIM Output clear enable
+ * @arg TIM_OC_CLR_DISABLE TIM Output clear disable
+ */
+void TIM_ClrOc4Ref(TIM_Module* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcClrState(TIM_OCClear));
+ tmpccmr2 = TIMx->CCMOD2;
+ /* Reset the OC4CE Bit */
+ tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4CEN);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
+ /* Write to TIMx CCMOD2 register */
+ TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF5 signal on an external event
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_CLR_ENABLE TIM Output clear enable
+ * @arg TIM_OC_CLR_DISABLE TIM Output clear disable
+ */
+void TIM_ClrOc5Ref(TIM_Module* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcClrState(TIM_OCClear));
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC4CE Bit */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5CEN);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr3 |= (uint16_t)(TIM_OCClear);
+ /* Write to TIMx CCMOD3 register */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF6 signal on an external event
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_CLR_ENABLE TIM Output clear enable
+ * @arg TIM_OC_CLR_DISABLE TIM Output clear disable
+ */
+void TIM_ClrOc6Ref(TIM_Module* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr3 = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcClrState(TIM_OCClear));
+ tmpccmr3 = TIMx->CCMOD3;
+ /* Reset the OC4CE Bit */
+ tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6CEN);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr3 |= (uint16_t)(TIM_OCClear << 8);
+ /* Write to TIMx CCMOD3 register */
+ TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief Configures the TIMx channel 1 polarity.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param OcPolarity specifies the OC1 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OC_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc1Polarity(TIM_Module* TIMx, uint16_t OcPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimOcPolarity(OcPolarity));
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC1P Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC1P);
+ tmpccer |= OcPolarity;
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx Channel 1N polarity.
+ * @param TIMx where x can be 1, 8 to select the TIM peripheral.
+ * @param OcNPolarity specifies the OC1N Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCN_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OCN_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc1NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList2Module(TIMx));
+ assert_param(IsTimOcnPolarity(OcNPolarity));
+
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC1NP Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC1NP);
+ tmpccer |= OcNPolarity;
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 2 polarity.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param OcPolarity specifies the OC2 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OC_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc2Polarity(TIM_Module* TIMx, uint16_t OcPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimOcPolarity(OcPolarity));
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC2P Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC2P);
+ tmpccer |= (uint32_t)(OcPolarity << 4);
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx Channel 2N polarity.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param OcNPolarity specifies the OC2N Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCN_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OCN_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc2NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcnPolarity(OcNPolarity));
+
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC2NP Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC2NP);
+ tmpccer |= (uint32_t)(OcNPolarity << 4);
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 3 polarity.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param OcPolarity specifies the OC3 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OC_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc3Polarity(TIM_Module* TIMx, uint16_t OcPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcPolarity(OcPolarity));
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC3P Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC3P);
+ tmpccer |= (uint32_t)(OcPolarity << 8);
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx Channel 3N polarity.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param OcNPolarity specifies the OC3N Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCN_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OCN_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc3NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity)
+{
+ uint32_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcnPolarity(OcNPolarity));
+
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC3NP Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC3NP);
+ tmpccer |= (uint32_t)(OcNPolarity << 8);
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 4 polarity.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param OcPolarity specifies the OC4 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OC_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc4Polarity(TIM_Module* TIMx, uint16_t OcPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimOcPolarity(OcPolarity));
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC4P Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC4P);
+ tmpccer |= (uint32_t)(OcPolarity << 12);
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 5 polarity.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param OcPolarity specifies the OC5 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OC_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc5Polarity(TIM_Module* TIMx, uint16_t OcPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcPolarity(OcPolarity));
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC5P Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC5P);
+ tmpccer |= (uint32_t)(OcPolarity << 16);
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 6 polarity.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param OcPolarity specifies the OC6 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OC_POLARITY_HIGH Output Compare active high
+ * @arg TIM_OC_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc6Polarity(TIM_Module* TIMx, uint16_t OcPolarity)
+{
+ uint32_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ assert_param(IsTimOcPolarity(OcPolarity));
+ tmpccer = TIMx->CCEN;
+ /* Set or Reset the CC6P Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC6P);
+ tmpccer |= (uint32_t)(OcPolarity << 20);
+ /* Write to TIMx CCEN register */
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel x.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CH_1 TIM Channel 1
+ * @arg TIM_CH_2 TIM Channel 2
+ * @arg TIM_CH_3 TIM Channel 3
+ * @arg TIM_CH_4 TIM Channel 4
+ * @param TIM_CCx specifies the TIM Channel CCxE bit new state.
+ * This parameter can be: TIM_CAP_CMP_ENABLE or TIM_CAP_CMP_DISABLE.
+ */
+void TIM_EnableCapCmpCh(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCx)
+{
+ uint16_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimCh(Channel));
+ assert_param(IsTimCapCmpState(TIM_CCx));
+
+ tmp = CAPCMPEN_CCE_SET << Channel;
+
+ /* Reset the CCxE Bit */
+ TIMx->CCEN &= (uint32_t)~tmp;
+
+ /* Set or reset the CCxE Bit */
+ TIMx->CCEN |= (uint32_t)(TIM_CCx << Channel);
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel xN.
+ * @param TIMx where x can be 1, 8 to select the TIM peripheral.
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CH_1 TIM Channel 1
+ * @arg TIM_CH_2 TIM Channel 2
+ * @arg TIM_CH_3 TIM Channel 3
+ * @param TIM_CCxN specifies the TIM Channel CCxNE bit new state.
+ * This parameter can be: TIM_CAP_CMP_N_ENABLE or TIM_CAP_CMP_N_DISABLE.
+ */
+void TIM_EnableCapCmpChN(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCxN)
+{
+ uint16_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList2Module(TIMx));
+ assert_param(IsTimComplementaryCh(Channel));
+ assert_param(IsTimCapCmpNState(TIM_CCxN));
+
+ tmp = CAPCMPEN_CCNE_SET << Channel;
+
+ /* Reset the CCxNE Bit */
+ TIMx->CCEN &= (uint32_t)~tmp;
+
+ /* Set or reset the CCxNE Bit */
+ TIMx->CCEN |= (uint32_t)(TIM_CCxN << Channel);
+}
+
+/**
+ * @brief Selects the TIM Output Compare Mode.
+ * @note This function disables the selected channel before changing the Output
+ * Compare Mode.
+ * User has to enable this channel using TIM_EnableCapCmpCh and TIM_EnableCapCmpChN functions.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CH_1 TIM Channel 1
+ * @arg TIM_CH_2 TIM Channel 2
+ * @arg TIM_CH_3 TIM Channel 3
+ * @arg TIM_CH_4 TIM Channel 4
+ * @param OcMode specifies the TIM Output Compare Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCMODE_TIMING
+ * @arg TIM_OCMODE_ACTIVE
+ * @arg TIM_OCMODE_TOGGLE
+ * @arg TIM_OCMODE_PWM1
+ * @arg TIM_OCMODE_PWM2
+ * @arg TIM_FORCED_ACTION_ACTIVE
+ * @arg TIM_FORCED_ACTION_INACTIVE
+ */
+void TIM_SelectOcMode(TIM_Module* TIMx, uint16_t Channel, uint16_t OcMode)
+{
+ uint32_t tmp = 0;
+ uint16_t tmp1 = 0;
+
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimCh(Channel));
+ assert_param(IsTimOc(OcMode));
+
+ tmp = (uint32_t)TIMx;
+ tmp += CAPCMPMOD_OFFSET;
+
+ tmp1 = CAPCMPEN_CCE_SET << (uint16_t)Channel;
+
+ /* Disable the Channel: Reset the CCxE Bit */
+ TIMx->CCEN &= (uint16_t)~tmp1;
+
+ if ((Channel == TIM_CH_1) || (Channel == TIM_CH_3))
+ {
+ tmp += (Channel >> 1);
+
+ /* Reset the OCxM bits in the CCMRx register */
+ *(__IO uint32_t*)tmp &= (uint32_t) ~((uint32_t)TIM_CCMOD1_OC1M);
+
+ /* Configure the OCxM bits in the CCMRx register */
+ *(__IO uint32_t*)tmp |= OcMode;
+ }
+ else
+ {
+ tmp += (uint16_t)(Channel - (uint16_t)4) >> (uint16_t)1;
+
+ /* Reset the OCxM bits in the CCMRx register */
+ *(__IO uint32_t*)tmp &= (uint32_t) ~((uint32_t)TIM_CCMOD1_OC2M);
+
+ /* Configure the OCxM bits in the CCMRx register */
+ *(__IO uint32_t*)tmp |= (uint16_t)(OcMode << 8);
+ }
+}
+
+/**
+ * @brief Enables or Disables the TIMx Update event.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param Cmd new state of the TIMx UDIS bit
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_EnableUpdateEvt(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set the Update Disable Bit */
+ TIMx->CTRL1 |= TIM_CTRL1_UPDIS;
+ }
+ else
+ {
+ /* Reset the Update Disable Bit */
+ TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_UPDIS);
+ }
+}
+
+/**
+ * @brief Configures the TIMx Update Request Interrupt source.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_UpdateSource specifies the Update source.
+ * This parameter can be one of the following values:
+ * @arg TIM_UPDATE_SRC_REGULAr Source of update is the counter overflow/underflow
+ or the setting of UG bit, or an update generation
+ through the slave mode controller.
+ * @arg TIM_UPDATE_SRC_GLOBAL Source of update is counter overflow/underflow.
+ */
+void TIM_ConfigUpdateRequestIntSrc(TIM_Module* TIMx, uint16_t TIM_UpdateSource)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimUpdateSrc(TIM_UpdateSource));
+ if (TIM_UpdateSource != TIM_UPDATE_SRC_GLOBAL)
+ {
+ /* Set the URS Bit */
+ TIMx->CTRL1 |= TIM_CTRL1_UPRS;
+ }
+ else
+ {
+ /* Reset the URS Bit */
+ TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_UPRS);
+ }
+}
+
+/**
+ * @brief Enables or disables the TIMx's Hall sensor interface.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param Cmd new state of the TIMx Hall sensor interface.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_SelectHallSensor(TIM_Module* TIMx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Set the TI1S Bit */
+ TIMx->CTRL2 |= TIM_CTRL2_TI1SEL;
+ }
+ else
+ {
+ /* Reset the TI1S Bit */
+ TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_TI1SEL);
+ }
+}
+
+/**
+ * @brief Selects the TIMx's One Pulse Mode.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_OPMode specifies the OPM Mode to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_OPMODE_SINGLE
+ * @arg TIM_OPMODE_REPET
+ */
+void TIM_SelectOnePulseMode(TIM_Module* TIMx, uint16_t TIM_OPMode)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimOpMOde(TIM_OPMode));
+ /* Reset the OPM Bit */
+ TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_ONEPM);
+ /* Configure the OPM Mode */
+ TIMx->CTRL1 |= TIM_OPMode;
+}
+
+/**
+ * @brief Selects the TIMx Trigger Output Mode.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 6, 7, 8 to select the TIM peripheral.
+ * @param TIM_TRGOSource specifies the Trigger Output source.
+ * This paramter can be one of the following values:
+ *
+ * - For all TIMx
+ * @arg TIM_TRGO_SRC_RESET The UG bit in the TIM_EVTGEN register is used as the trigger output (TRGO).
+ * @arg TIM_TRGO_SRC_ENABLE The Counter Enable CEN is used as the trigger output (TRGO).
+ * @arg TIM_TRGO_SRC_UPDATE The update event is selected as the trigger output (TRGO).
+ *
+ * - For all TIMx except TIM6 and TIM7
+ * @arg TIM_TRGO_SRC_OC1 The trigger output sends a positive pulse when the CC1IF flag
+ * is to be set, as soon as a capture or compare match occurs (TRGO).
+ * @arg TIM_TRGO_SRC_OC1REF OC1REF signal is used as the trigger output (TRGO).
+ * @arg TIM_TRGO_SRC_OC2REF OC2REF signal is used as the trigger output (TRGO).
+ * @arg TIM_TRGO_SRC_OC3REF OC3REF signal is used as the trigger output (TRGO).
+ * @arg TIM_TRGO_SRC_OC4REF OC4REF signal is used as the trigger output (TRGO).
+ *
+ */
+void TIM_SelectOutputTrig(TIM_Module* TIMx, uint16_t TIM_TRGOSource)
+{
+ /* Check the parameters */
+ assert_param(IsTimList7Module(TIMx));
+ assert_param(IsTimTrgoSrc(TIM_TRGOSource));
+ /* Reset the MMS Bits */
+ TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_MMSEL);
+ /* Select the TRGO source */
+ TIMx->CTRL2 |= TIM_TRGOSource;
+}
+
+
+/**
+ * @brief Selects the TIMx Ext Source.
+ * @param Source: 0:selection external ETR(from IOM) signal.1:selection internal ETR(fromo TSC) signal.
+ * @retval None
+ */
+void TIM_SelectExtSignalSource(TIM_Module* TIMx, uint16_t ExtSigalSource)
+{
+ /* Select Ext Signal Source Bits */
+ TIMx->CTRL2 &= (uint32_t)~((uint32_t)TIM_ETR_Seletct_innerTsc);
+ /* Select the TRGO source */
+ TIMx->CTRL2 |= ExtSigalSource;
+}
+
+
+/**
+ * @brief Selects the TIMx Slave Mode.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param TIM_SlaveMode specifies the Timer Slave Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_SLAVE_MODE_RESET Rising edge of the selected trigger signal (TRGI) re-initializes
+ * the counter and triggers an update of the registers.
+ * @arg TIM_SLAVE_MODE_GATED The counter clock is enabled when the trigger signal (TRGI) is high.
+ * @arg TIM_SLAVE_MODE_TRIG The counter starts at a rising edge of the trigger TRGI.
+ * @arg TIM_SLAVE_MODE_EXT1 Rising edges of the selected trigger (TRGI) clock the counter.
+ */
+void TIM_SelectSlaveMode(TIM_Module* TIMx, uint16_t TIM_SlaveMode)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimSlaveMode(TIM_SlaveMode));
+ /* Reset the SMS Bits */
+ TIMx->SMCTRL &= (uint16_t) ~((uint16_t)TIM_SMCTRL_SMSEL);
+ /* Select the Slave Mode */
+ TIMx->SMCTRL |= TIM_SlaveMode;
+}
+
+/**
+ * @brief Sets or Resets the TIMx Master/Slave Mode.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param TIM_MasterSlaveMode specifies the Timer Master Slave Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_MASTER_SLAVE_MODE_ENABLE synchronization between the current timer
+ * and its slaves (through TRGO).
+ * @arg TIM_MASTER_SLAVE_MODE_DISABLE No action
+ */
+void TIM_SelectMasterSlaveMode(TIM_Module* TIMx, uint16_t TIM_MasterSlaveMode)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimMasterSlaveMode(TIM_MasterSlaveMode));
+ /* Reset the MSM Bit */
+ TIMx->SMCTRL &= (uint16_t) ~((uint16_t)TIM_SMCTRL_MSMD);
+
+ /* Set or Reset the MSM Bit */
+ TIMx->SMCTRL |= TIM_MasterSlaveMode;
+}
+
+/**
+ * @brief Sets the TIMx Counter Register value
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param Counter specifies the Counter register new value.
+ */
+void TIM_SetCnt(TIM_Module* TIMx, uint16_t Counter)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ /* Set the Counter Register value */
+ TIMx->CNT = Counter;
+}
+
+/**
+ * @brief Sets the TIMx Autoreload Register value
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param Autoreload specifies the Autoreload register new value.
+ */
+void TIM_SetAutoReload(TIM_Module* TIMx, uint16_t Autoreload)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ /* Set the Autoreload Register value */
+ TIMx->AR = Autoreload;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare1 Register value
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param Compare1 specifies the Capture Compare1 register new value.
+ */
+void TIM_SetCmp1(TIM_Module* TIMx, uint16_t Compare1)
+{
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ /* Set the Capture Compare1 Register value */
+ TIMx->CCDAT1 = Compare1;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare2 Register value
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param Compare2 specifies the Capture Compare2 register new value.
+ */
+void TIM_SetCmp2(TIM_Module* TIMx, uint16_t Compare2)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ /* Set the Capture Compare2 Register value */
+ TIMx->CCDAT2 = Compare2;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare3 Register value
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param Compare3 specifies the Capture Compare3 register new value.
+ */
+void TIM_SetCmp3(TIM_Module* TIMx, uint16_t Compare3)
+{
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ /* Set the Capture Compare3 Register value */
+ TIMx->CCDAT3 = Compare3;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare4 Register value
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param Compare4 specifies the Capture Compare4 register new value.
+ */
+void TIM_SetCmp4(TIM_Module* TIMx, uint16_t Compare4)
+{
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ /* Set the Capture Compare4 Register value */
+ TIMx->CCDAT4 = Compare4;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare5 Register value
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param Compare5 specifies the Capture Compare5 register new value.
+ */
+void TIM_SetCmp5(TIM_Module* TIMx, uint16_t Compare5)
+{
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ /* Set the Capture Compare4 Register value */
+ TIMx->CCDAT5 = Compare5;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare4 Register value
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param Compare6 specifies the Capture Compare6 register new value.
+ */
+void TIM_SetCmp6(TIM_Module* TIMx, uint16_t Compare6)
+{
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ /* Set the Capture Compare4 Register value */
+ TIMx->CCDAT6 = Compare6;
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 1 prescaler.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_ICPSC specifies the Input Capture1 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_PSC_DIV1 no prescaler
+ * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events
+ * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events
+ * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events
+ */
+void TIM_SetInCap1Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimIcPrescaler(TIM_ICPSC));
+ /* Reset the IC1PSC Bits */
+ TIMx->CCMOD1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_IC1PSC);
+ /* Set the IC1PSC value */
+ TIMx->CCMOD1 |= TIM_ICPSC;
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 2 prescaler.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param TIM_ICPSC specifies the Input Capture2 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_PSC_DIV1 no prescaler
+ * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events
+ * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events
+ * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events
+ */
+void TIM_SetInCap2Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ assert_param(IsTimIcPrescaler(TIM_ICPSC));
+ /* Reset the IC2PSC Bits */
+ TIMx->CCMOD1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_IC2PSC);
+ /* Set the IC2PSC value */
+ TIMx->CCMOD1 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 3 prescaler.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPSC specifies the Input Capture3 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_PSC_DIV1 no prescaler
+ * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events
+ * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events
+ * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events
+ */
+void TIM_SetInCap3Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimIcPrescaler(TIM_ICPSC));
+ /* Reset the IC3PSC Bits */
+ TIMx->CCMOD2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_IC3PSC);
+ /* Set the IC3PSC value */
+ TIMx->CCMOD2 |= TIM_ICPSC;
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 4 prescaler.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPSC specifies the Input Capture4 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_PSC_DIV1 no prescaler
+ * @arg TIM_IC_PSC_DIV2 capture is done once every 2 events
+ * @arg TIM_IC_PSC_DIV4 capture is done once every 4 events
+ * @arg TIM_IC_PSC_DIV8 capture is done once every 8 events
+ */
+void TIM_SetInCap4Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ assert_param(IsTimIcPrescaler(TIM_ICPSC));
+ /* Reset the IC4PSC Bits */
+ TIMx->CCMOD2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_IC4PSC);
+ /* Set the IC4PSC value */
+ TIMx->CCMOD2 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/**
+ * @brief Sets the TIMx Clock Division value.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select
+ * the TIM peripheral.
+ * @param TIM_CKD specifies the clock division value.
+ * This parameter can be one of the following value:
+ * @arg TIM_CLK_DIV1 TDTS = Tck_tim
+ * @arg TIM_CLK_DIV2 TDTS = 2*Tck_tim
+ * @arg TIM_CLK_DIV4 TDTS = 4*Tck_tim
+ */
+void TIM_SetClkDiv(TIM_Module* TIMx, uint16_t TIM_CKD)
+{
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ assert_param(IsTimClkDiv(TIM_CKD));
+ /* Reset the CKD Bits */
+ TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_CLKD);
+ /* Set the CKD value */
+ TIMx->CTRL1 |= TIM_CKD;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 1 value.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @return Capture Compare 1 Register value.
+ */
+uint16_t TIM_GetCap1(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimList8Module(TIMx));
+ /* Get the Capture 1 Register value */
+ return TIMx->CCDAT1;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 2 value.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @return Capture Compare 2 Register value.
+ */
+uint16_t TIM_GetCap2(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimList6Module(TIMx));
+ /* Get the Capture 2 Register value */
+ return TIMx->CCDAT2;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 3 value.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @return Capture Compare 3 Register value.
+ */
+uint16_t TIM_GetCap3(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ /* Get the Capture 3 Register value */
+ return TIMx->CCDAT3;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 4 value.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @return Capture Compare 4 Register value.
+ */
+uint16_t TIM_GetCap4(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+ /* Get the Capture 4 Register value */
+ return TIMx->CCDAT4;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 5 value.
+ * @param TIMx where x can be 1 8 to select the TIM peripheral.
+ * @return Capture Compare 5 Register value.
+ */
+uint16_t TIM_GetCap5(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ /* Get the Capture 5 Register value */
+ return TIMx->CCDAT5;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 6 value.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @return Capture Compare 6 Register value.
+ */
+uint16_t TIM_GetCap6(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimList1Module(TIMx));
+ /* Get the Capture 6 Register value */
+ return TIMx->CCDAT6;
+}
+
+/**
+ * @brief Gets the TIMx Counter value.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @return Counter Register value.
+ */
+uint16_t TIM_GetCnt(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ /* Get the Counter Register value */
+ return TIMx->CNT;
+}
+
+/**
+ * @brief Gets the TIMx Prescaler value.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @return Prescaler Register value.
+ */
+uint16_t TIM_GetPrescaler(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ /* Get the Prescaler Register value */
+ return TIMx->PSC;
+}
+
+/**
+ * @brief Gets the TIMx Prescaler value.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @return Prescaler Register value.
+ */
+uint16_t TIM_GetAutoReload(TIM_Module* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ /* Get the Prescaler Register value */
+ return TIMx->AR;
+}
+
+/**
+ * @brief Checks whether the specified TIM flag is set or not.
+ * @param TIMx where x can be 1 to 5 , 8 to select the TIM peripheral.
+ * @param TIM_CCEN specifies the Bit to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_CC1EN CC1EN Bit
+ * @arg TIM_CC1NEN CC1NEN Bit
+ * @arg TIM_CC2EN CC2EN Bit
+ * @arg TIM_CC2NEN CC2NEN Bit
+ * @arg TIM_CC3EN CC3EN Bit
+ * @arg TIM_CC3NEN CC3NEN Bit
+ * @arg TIM_CC4EN CC4EN Bit
+ * @arg TIM_CC5EN CC5EN Bit
+ * @arg TIM_CC6EN CC6EN Bit
+ * @note
+ * - TIM_CC1NEN TIM_CC2NEN TIM_CC3NEN is used only with TIM1, TIM8.
+ * @return The new state of TIM_FLAG (SET or RESET).
+ */
+FlagStatus TIM_GetCCENStatus(TIM_Module* TIMx, uint32_t TIM_CCEN)
+{
+ INTStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IsTimList3Module(TIMx));
+
+ if (TIMx==TIM1 || TIMx==TIM8)
+ {
+ assert_param(IsAdvancedTimCCENFlag(TIM_CCEN));
+ if ((TIMx->CCEN & TIM_CCEN) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+ else if (TIMx==TIM2 || TIMx==TIM3 || TIMx==TIM4 || TIMx==TIM5 )
+ {
+ assert_param(IsGeneralTimCCENFlag(TIM_CCEN));
+ if ((TIMx->CCEN & TIM_CCEN) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+
+ return bitstatus;
+}
+
+/**
+ * @brief Checks whether the specified TIM flag is set or not.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_FLAG specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_FLAG_UPDATE TIM update Flag
+ * @arg TIM_FLAG_CC1 TIM Capture Compare 1 Flag
+ * @arg TIM_FLAG_CC2 TIM Capture Compare 2 Flag
+ * @arg TIM_FLAG_CC3 TIM Capture Compare 3 Flag
+ * @arg TIM_FLAG_CC4 TIM Capture Compare 4 Flag
+ * @arg TIM_FLAG_COM TIM Commutation Flag
+ * @arg TIM_FLAG_TRIG TIM Trigger Flag
+ * @arg TIM_FLAG_BREAK TIM Break Flag
+ * @arg TIM_FLAG_CC1OF TIM Capture Compare 1 overcapture Flag
+ * @arg TIM_FLAG_CC2OF TIM Capture Compare 2 overcapture Flag
+ * @arg TIM_FLAG_CC3OF TIM Capture Compare 3 overcapture Flag
+ * @arg TIM_FLAG_CC4OF TIM Capture Compare 4 overcapture Flag
+ * @arg TIM_FLAG_CC5 TIM Capture Compare 5 Flag
+ * @arg TIM_FLAG_CC6 TIM Capture Compare 6 Flag
+ * @note
+ * - TIM6 and TIM7 can have only one update flag.
+ * - TIM_FLAG_BREAK is used only with TIM1, TIM8.
+ * - TIM_FLAG_COM is used only with TIM1, TIM8.
+ * @return The new state of TIM_FLAG (SET or RESET).
+ */
+FlagStatus TIM_GetFlagStatus(TIM_Module* TIMx, uint32_t TIM_FLAG)
+{
+ INTStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimGetFlag(TIM_FLAG));
+
+ if ((TIMx->STS & TIM_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the TIMx's pending flags.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_FLAG specifies the flag bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_FLAG_UPDATE TIM update Flag
+ * @arg TIM_FLAG_CC1 TIM Capture Compare 1 Flag
+ * @arg TIM_FLAG_CC2 TIM Capture Compare 2 Flag
+ * @arg TIM_FLAG_CC3 TIM Capture Compare 3 Flag
+ * @arg TIM_FLAG_CC4 TIM Capture Compare 4 Flag
+ * @arg TIM_FLAG_COM TIM Commutation Flag
+ * @arg TIM_FLAG_TRIG TIM Trigger Flag
+ * @arg TIM_FLAG_BREAK TIM Break Flag
+ * @arg TIM_FLAG_CC1OF TIM Capture Compare 1 overcapture Flag
+ * @arg TIM_FLAG_CC2OF TIM Capture Compare 2 overcapture Flag
+ * @arg TIM_FLAG_CC3OF TIM Capture Compare 3 overcapture Flag
+ * @arg TIM_FLAG_CC4OF TIM Capture Compare 4 overcapture Flag
+ * @note
+ * - TIM6 and TIM7 can have only one update flag.
+ * - TIM_FLAG_BREAK is used only with TIM1, TIM8.
+ * - TIM_FLAG_COM is used only with TIM1, TIM8.
+ */
+void TIM_ClearFlag(TIM_Module* TIMx, uint32_t TIM_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimClrFlag(TIM_FLAG));
+
+ /* Clear the flags */
+ TIMx->STS = (uint32_t)~TIM_FLAG;
+}
+
+/**
+ * @brief Checks whether the TIM interrupt has occurred or not.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_IT specifies the TIM interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_INT_UPDATE TIM update Interrupt source
+ * @arg TIM_INT_CC1 TIM Capture Compare 1 Interrupt source
+ * @arg TIM_INT_CC2 TIM Capture Compare 2 Interrupt source
+ * @arg TIM_INT_CC3 TIM Capture Compare 3 Interrupt source
+ * @arg TIM_INT_CC4 TIM Capture Compare 4 Interrupt source
+ * @arg TIM_INT_COM TIM Commutation Interrupt source
+ * @arg TIM_INT_TRIG TIM Trigger Interrupt source
+ * @arg TIM_INT_BREAK TIM Break Interrupt source
+ * @note
+ * - TIM6 and TIM7 can generate only an update interrupt.
+ * - TIM_INT_BREAK is used only with TIM1, TIM8.
+ * - TIM_INT_COM is used only with TIM1, TIM8.
+ * @return The new state of the TIM_IT(SET or RESET).
+ */
+INTStatus TIM_GetIntStatus(TIM_Module* TIMx, uint32_t TIM_IT)
+{
+ INTStatus bitstatus = RESET;
+ uint32_t itstatus = 0x0, itenable = 0x0;
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimGetInt(TIM_IT));
+
+ itstatus = TIMx->STS & TIM_IT;
+
+ itenable = TIMx->DINTEN & TIM_IT;
+ if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the TIMx's interrupt pending bits.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_IT specifies the pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_INT_UPDATE TIM1 update Interrupt source
+ * @arg TIM_INT_CC1 TIM Capture Compare 1 Interrupt source
+ * @arg TIM_INT_CC2 TIM Capture Compare 2 Interrupt source
+ * @arg TIM_INT_CC3 TIM Capture Compare 3 Interrupt source
+ * @arg TIM_INT_CC4 TIM Capture Compare 4 Interrupt source
+ * @arg TIM_INT_COM TIM Commutation Interrupt source
+ * @arg TIM_INT_TRIG TIM Trigger Interrupt source
+ * @arg TIM_INT_BREAK TIM Break Interrupt source
+ * @note
+ * - TIM6 and TIM7 can generate only an update interrupt.
+ * - TIM_INT_BREAK is used only with TIM1, TIM8.
+ * - TIM_INT_COM is used only with TIM1, TIM8.
+ */
+void TIM_ClrIntPendingBit(TIM_Module* TIMx, uint32_t TIM_IT)
+{
+ /* Check the parameters */
+ assert_param(IsTimAllModule(TIMx));
+ assert_param(IsTimInt(TIM_IT));
+ /* Clear the IT pending Bit */
+ TIMx->STS = (uint32_t)~TIM_IT;
+}
+
+/**
+ * @brief Configure the TI1 as Input.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param IcPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_POLARITY_RISING
+ * @arg TIM_IC_POLARITY_FALLING
+ * @param IcSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 1 is selected to be connected to IC1.
+ * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 1 is selected to be connected to IC2.
+ * @arg TIM_IC_SELECTION_TRC TIM Input 1 is selected to be connected to TRC.
+ * @param IcFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ */
+static void ConfigTI1(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter)
+{
+ uint16_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0;
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC1EN);
+ tmpccmr1 = TIMx->CCMOD1;
+ tmpccer = TIMx->CCEN;
+ /* Select the Input and set the filter */
+ tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD1_CC1SEL)) & ((uint16_t) ~((uint16_t)TIM_CCMOD1_IC1F)));
+ tmpccmr1 |= (uint16_t)(IcSelection | (uint16_t)(IcFilter << (uint16_t)4));
+
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5))
+ {
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC1P));
+ tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC1EN);
+ }
+ else
+ {
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC1P | TIM_CCEN_CC1NP));
+ tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC1EN);
+ }
+
+ /* Write to TIMx CCMOD1 and CCEN registers */
+ TIMx->CCMOD1 = tmpccmr1;
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configure the TI2 as Input.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param IcPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_POLARITY_RISING
+ * @arg TIM_IC_POLARITY_FALLING
+ * @param IcSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 2 is selected to be connected to IC2.
+ * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 2 is selected to be connected to IC1.
+ * @arg TIM_IC_SELECTION_TRC TIM Input 2 is selected to be connected to TRC.
+ * @param IcFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ */
+static void ConfigTI2(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter)
+{
+ uint16_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0, tmp = 0;
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC2EN);
+ tmpccmr1 = TIMx->CCMOD1;
+ tmpccer = TIMx->CCEN;
+ tmp = (uint32_t)(IcPolarity << 4);
+ /* Select the Input and set the filter */
+ tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD1_CC2SEL)) & ((uint16_t) ~((uint16_t)TIM_CCMOD1_IC2F)));
+ tmpccmr1 |= (uint16_t)(IcFilter << 12);
+ tmpccmr1 |= (uint16_t)(IcSelection << 8);
+
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5))
+ {
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC2P));
+ tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCEN_CC2EN);
+ }
+ else
+ {
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC2P | TIM_CCEN_CC2NP));
+ tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC2EN);
+ }
+
+ /* Write to TIMx CCMOD1 and CCEN registers */
+ TIMx->CCMOD1 = tmpccmr1;
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configure the TI3 as Input.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param IcPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_POLARITY_RISING
+ * @arg TIM_IC_POLARITY_FALLING
+ * @param IcSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 3 is selected to be connected to IC3.
+ * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 3 is selected to be connected to IC4.
+ * @arg TIM_IC_SELECTION_TRC TIM Input 3 is selected to be connected to TRC.
+ * @param IcFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ */
+static void ConfigTI3(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter)
+{
+ uint16_t tmpccmr2 = 0;
+ uint32_t tmpccer = 0, tmp = 0;
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC3EN);
+ tmpccmr2 = TIMx->CCMOD2;
+ tmpccer = TIMx->CCEN;
+ tmp = (uint32_t)(IcPolarity << 8);
+ /* Select the Input and set the filter */
+ tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD2_CC3SEL)) & ((uint16_t) ~((uint16_t)TIM_CCMOD2_IC3F)));
+ tmpccmr2 |= (uint16_t)(IcSelection | (uint16_t)(IcFilter << (uint16_t)4));
+
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5))
+ {
+ /* Select the Polarity and set the CC3E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC3P));
+ tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCEN_CC3EN);
+ }
+ else
+ {
+ /* Select the Polarity and set the CC3E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC3P | TIM_CCEN_CC3NP));
+ tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC3EN);
+ }
+
+ /* Write to TIMx CCMOD2 and CCEN registers */
+ TIMx->CCMOD2 = tmpccmr2;
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief Configure the TI4 as Input.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param IcPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_POLARITY_RISING
+ * @arg TIM_IC_POLARITY_FALLING
+ * @param IcSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_IC_SELECTION_DIRECTTI TIM Input 4 is selected to be connected to IC4.
+ * @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 4 is selected to be connected to IC3.
+ * @arg TIM_IC_SELECTION_TRC TIM Input 4 is selected to be connected to TRC.
+ * @param IcFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ */
+static void ConfigTI4(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter)
+{
+ uint16_t tmpccmr2 = 0;
+ uint32_t tmpccer = 0, tmp = 0;
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC4EN);
+ tmpccmr2 = TIMx->CCMOD2;
+ tmpccer = TIMx->CCEN;
+ tmp = (uint32_t)(IcPolarity << 12);
+ /* Select the Input and set the filter */
+ tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMOD2_CC4SEL) & ((uint16_t) ~((uint16_t)TIM_CCMOD2_IC4F)));
+ tmpccmr2 |= (uint16_t)(IcSelection << 8);
+ tmpccmr2 |= (uint16_t)(IcFilter << 12);
+
+ if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5))
+ {
+ /* Select the Polarity and set the CC4E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC4P));
+ tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCEN_CC4EN);
+ }
+ else
+ {
+ /* Select the Polarity and set the CC4E Bit */
+ tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC4P));
+ tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC4EN);
+ }
+ /* Write to TIMx CCMOD2 and CCEN registers */
+ TIMx->CCMOD2 = tmpccmr2;
+ TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_tsc.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_tsc.c
new file mode 100644
index 0000000000..c842d16dc5
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_tsc.c
@@ -0,0 +1,500 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_tsc.c
+ * @author Nations
+ * @version v1.0.3
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32wb452.h"
+#include "n32wb452_tsc.h"
+
+/**
+ * @brief Init TSC config for hardware detect mode.
+ * @param TSC_Def Pointer of TSC register.
+ * @param CtrlCfg configurations.
+ */
+TSC_ErrorTypeDef TSC_Init(TSC_Module* TSC_Def, TSC_InitType* CtrlCfg)
+{
+ uint32_t tempreg,timeout;
+
+ assert_param(IS_TSC_FILTER(CtrlCfg->TSC_FilterCount));
+ assert_param(IS_TSC_DET_PERIOD(CtrlCfg->TSC_DetPeriod));
+
+ if (TSC_Def != TSC)
+ return TSC_ERROR_PARAMETER;
+
+ /* waiting tsc hw for idle status.*/
+ timeout = 0;
+ do
+ {
+ __TSC_HW_DISABLE();
+
+ if (++timeout > TSC_TIMEOUT)
+ return TSC_ERROR_HW_MODE;
+ }while (__TSC_GET_HW_MODE());
+
+ /*TSC_CTRL config*/
+ tempreg = 0;
+ if (CtrlCfg->TSC_DetIntEnable)
+ tempreg |= TSC_IT_DET_ENABLE;
+
+ if (CtrlCfg->TSC_GreatEnable)
+ tempreg |= TSC_DET_TYPE_GREAT;
+
+ if (CtrlCfg->TSC_LessEnable)
+ tempreg |= TSC_DET_TYPE_LESS;
+
+ tempreg |= CtrlCfg->TSC_FilterCount;
+ tempreg |= CtrlCfg->TSC_DetPeriod;
+
+ TSC_Def->CTRL = tempreg;
+
+ return TSC_ERROR_OK;
+}
+
+/**
+ * @brief Config the clock source of TSC
+ * @param TSC_ClkSource specifies the clock source of TSC
+ * This parameter can be one of the following values:
+ * @arg TSC_CLK_SRC_LSI: TSC clock source is LSI(default)
+ * @arg TSC_CLK_SRC_LSE: TSC clock source is LSE,and LSE is oscillator
+ * @arg TSC_CLK_SRC_LSE_BYPASS: TSC clock source is LSE,and LSE is extennal clock
+ * @retval TSC error code
+ */
+TSC_ErrorTypeDef TSC_ClockConfig(uint32_t TSC_ClkSource)
+{
+ uint32_t timeout;
+
+ /*Enable PWR peripheral Clock*/
+ RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR,ENABLE);
+
+ if (TSC_CLK_SRC_LSI == TSC_ClkSource)
+ {
+ /*enable LSI clock*/
+ RCC_EnableLsi(ENABLE);
+
+ /*Wait LSI stable*/
+ timeout = 0;
+ while (RCC_GetFlagStatus(RCC_FLAG_LSIRD) == RESET)
+ {
+ if (++timeout >TSC_TIMEOUT)
+ return TSC_ERROR_CLOCK;
+ }
+ }
+ else if ((TSC_CLK_SRC_LSE_BYPASS==TSC_ClkSource)||(TSC_CLK_SRC_LSE==TSC_ClkSource))
+ {
+ if (RCC_GetFlagStatus(RCC_FLAG_LSERD)==RESET)
+ {
+ // Set bit 8 of PWR_CTRL1.Open PWR DBP.
+ PWR_BackupAccessEnable(ENABLE);
+ RCC_ConfigLse(TSC_ClkSource);
+ timeout = 0;
+ while (RCC_GetFlagStatus(RCC_FLAG_LSERD) == RESET)
+ {
+ if (++timeout >TSC_TIMEOUT)
+ return TSC_ERROR_CLOCK;
+ }
+ }
+ }
+ else
+ return TSC_ERROR_PARAMETER;
+
+ /*Enable TSC clk*/
+ RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TSC,ENABLE);
+
+ return TSC_ERROR_OK;
+}
+
+/**
+ * @brief Configure internal charge resistor for some channels
+ * @param TSC_Def Pointer of TSC register.
+ * @param res: internal resistor selecte
+ * This parameter can be one of the following values:
+ * @arg TSC_RESR_CHN_RESIST_0: 1M OHM
+ * @arg TSC_RESR_CHN_RESIST_1: 882K OHM
+ * @arg TSC_RESR_CHN_RESIST_2: 756K OHM
+ * @arg TSC_RESR_CHN_RESIST_3: 630K OHM
+ * @arg TSC_RESR_CHN_RESIST_4: 504K OHM
+ * @arg TSC_RESR_CHN_RESIST_5: 378K OHM
+ * @arg TSC_RESR_CHN_RESIST_6: 252K OHM
+ * @arg TSC_RESR_CHN_RESIST_7: 126K OHM
+ * @param Channels: channels to be configed, as TSC_CHNEN defined
+ * This parameter:bit[0:23] used,bit[24:31] must be 0
+ * bitx: TSC channel x
+ * @return: none
+ */
+TSC_ErrorTypeDef TSC_ConfigInternalResistor(TSC_Module* TSC_Def,uint32_t Channels, uint32_t res )
+{
+ uint32_t i,chn,timeout,*pReg,nPos;
+
+ assert_param(IS_TSC_CHN(Channels));
+ assert_param(IS_TSC_RESISTOR_VALUE(res));
+
+ if (TSC_Def != TSC)
+ return TSC_ERROR_PARAMETER;
+
+ /*Check charge resistor value */
+ if (res > TSC_RESR_CHN_RESIST_125K)
+ return TSC_ERROR_PARAMETER;
+
+ /* waiting tsc hw for idle status.*/
+ timeout = 0;
+ do
+ {
+ __TSC_HW_DISABLE();
+
+ if (++timeout > TSC_TIMEOUT)
+ return TSC_ERROR_HW_MODE;
+ }while (__TSC_GET_HW_MODE());
+
+ /* Mask invalie bits*/
+ chn = Channels & TSC_CHNEN_CHN_SEL_MASK;
+
+ /* Set resistance for each channel one by one*/
+ for (i = 0; iRESR0));
+ pReg += (i/8);
+ nPos = (i & 0x7UL)*4;
+ MODIFY_REG(*pReg,TSC_RESR_CHN_RESIST_MASK<>= 1;
+ }
+
+ return TSC_ERROR_OK;
+}
+
+/**
+ * @brief Configure threshold value for some channels
+ * @param TSC_Def Pointer of TSC register.
+ * @param Channels: channels to be configed, as TSC_CHNEN defined
+ * This parameter:bit[0:23] used,bit[24:31] must be 0
+ * bitx: TSC channel x
+ * @param base: base value of threshold, 0-MAX_TSC_THRESHOLD_BASE
+ * @param delta: delta value of threshold,0-MAX_TSC_THRESHOLD_DELRA
+ * @return: None
+ */
+TSC_ErrorTypeDef TSC_ConfigThreshold( TSC_Module* TSC_Def, uint32_t Channels, uint32_t base, uint32_t delta)
+{
+ uint32_t i, chn,timeout,*pReg;
+
+ assert_param(IS_TSC_CHN(Channels));
+ assert_param(IS_TSC_THRESHOLD_BASE(base));
+ assert_param(IS_TSC_THRESHOLD_DELTA(delta));
+
+ if (TSC_Def != TSC)
+ return TSC_ERROR_PARAMETER;
+
+ /*Check the base and delta value*/
+ if ( (base>MAX_TSC_THRESHOLD_BASE)||(delta>MAX_TSC_THRESHOLD_DELTA))
+ return TSC_ERROR_PARAMETER;
+
+ /* waiting tsc hw for idle status.*/
+ timeout = 0;
+ do
+ {
+ __TSC_HW_DISABLE();
+
+ if (++timeout > TSC_TIMEOUT)
+ return TSC_ERROR_HW_MODE;
+ }while (__TSC_GET_HW_MODE());
+
+ pReg = (uint32_t *)(&(TSC_Def->THRHD0));
+
+ /*Mask invalie bits*/
+ chn = Channels & TSC_CHNEN_CHN_SEL_MASK;
+
+ /* Set the base and delta for each channnel one by one*/
+ for (i = 0; i>= 1;
+ }
+
+ return TSC_ERROR_OK;
+}
+
+
+/**
+ * @brief Get parameters of one channel.
+ * @param TSC_Def Pointer of TSC register.
+ * @param ChnCfg: Pointer of TSC_ChnCfg structure.
+ * @param Channels: channels to be configed, as TSC_CHNEN defined
+ * This parameter:bit[0:23] used,bit[24:31] must be 0
+ * bitx: TSC channel x
+ * @return: None
+ */
+TSC_ErrorTypeDef TSC_GetChannelCfg( TSC_Module* TSC_Def, TSC_ChnCfg* ChnCfg, uint32_t Channels)
+{
+ uint32_t i,chn, *pReg;
+
+ if (TSC_Def != TSC)
+ return TSC_ERROR_PARAMETER;
+
+ /*Check channel number*/
+ if (!(IS_TSC_CHN(Channels)))
+ return TSC_ERROR_PARAMETER;
+
+ chn = Channels & TSC_CHNEN_CHN_SEL_MASK;
+
+ for (i = 0; iTHRHD0));
+ pReg += i;
+ ChnCfg->TSC_Base = (uint16_t)(((*pReg) & TSC_THRHD_BASE_MASK) >> TSC_THRHD_BASE_SHIFT);
+ ChnCfg->TSC_Delta = (uint8_t)(((*pReg) & TSC_THRHD_DELTA_MASK)>> TSC_THRHD_DELTA_SHIFT);
+
+ pReg = (uint32_t *)(&(TSC->RESR0));
+ pReg += (i/8);
+ ChnCfg->TSC_ResisValue = (uint8_t)(((*pReg) >> ((i & 0x7UL)*4)) & TSC_RESR_CHN_RESIST_MASK);
+ break;
+ }
+
+ chn >>= 1;
+ }
+
+ return TSC_ERROR_OK;
+}
+
+
+/**
+ * @brief Get TSC status value.
+ * @param TSC_Def Pointer of TSC register.
+ * @param type TSC status type.
+ */
+uint32_t TSC_GetStatus(TSC_Module* TSC_Def, uint32_t type)
+{
+ uint32_t value = 0;
+
+ if (TSC_Def != TSC)
+ return 0;
+
+ switch (type)
+ {
+ case TSC_GET_STS_CNTVALUE:
+ value = __TSC_GET_CHN_CNT();
+ break;
+
+ case TSC_GET_STS_LESS_DET:
+ value = __TSC_GET_HW_DET_TYPE(TSC_FLAG_LESS_DET);
+ break;
+
+ case TSC_GET_STS_GREAT_DET:
+ value = __TSC_GET_HW_DET_TYPE(TSC_FLAG_GREAT_DET);
+ break;
+
+ case TSC_GET_STS_CHN_NUM:
+ value = __TSC_GET_CHN_NUMBER();
+ break;
+
+ case TSC_GET_STS_DET_ST:
+ value = __TSC_GET_HW_MODE();
+ break;
+
+ default:
+ break;
+ }
+
+ return value;
+}
+
+/**
+ * @brief Enable/Disable hardware detection.
+ * @param TSC_Def Pointer of TSC register.
+ * @param Channels: channels to be configed, as TSC_CHNEN defined
+ * This parameter:bit[0:23] used,bit[24:31] must be 0
+ * bitx: TSC channel x
+ * @param Cmd ENABLE:Enable hardware detection,DISALBE:Disable hardware detection.
+ * @note You can only output one channel at a time.
+ */
+TSC_ErrorTypeDef TSC_Cmd(TSC_Module* TSC_Def, uint32_t Channels, FunctionalState Cmd)
+{
+ uint32_t timeout;
+
+ if (TSC_Def != TSC)
+ return TSC_ERROR_PARAMETER;
+
+ if (Cmd != DISABLE)
+ {
+ // enable tsc channel
+ Channels &= TSC_CHNEN_CHN_SEL_MASK;
+ __TSC_CHN_CONFIG(Channels );
+
+ /* Enable the TSC */
+ __TSC_HW_ENABLE();
+ }
+ else
+ {
+ /* Disable the TSC */
+ timeout = 0;
+ do
+ {
+ __TSC_HW_DISABLE();
+
+ if (++timeout > TSC_TIMEOUT)
+ return TSC_ERROR_HW_MODE;
+ }while (__TSC_GET_HW_MODE());
+
+ __TSC_CHN_CONFIG(0);
+ }
+
+ return TSC_ERROR_OK;
+}
+
+/**
+ * @brief Toggle channels to output to TIMER2/TIMER4 by software mode.
+ * @param TSC_Def Pointer of TSC register.
+ * @param Channels: channels to be configed, as TSC_CHNEN defined
+ * This parameter:bit[0:23] used,bit[24:31] must be 0
+ * bitx: TSC channel x
+ * @param TIMx Select timer.
+ * @param Cmd ENABLE:Enable hardware detection,DISALBE:Disable hardware detection.
+ * @note It can only output to TIMER2/TIMER4 by software mode.Other channels are not valid.
+ */
+TSC_ErrorTypeDef TSC_SW_SwtichChn(TSC_Module* TSC_Def, uint32_t Channel, TIM_Module* TIMx, FunctionalState Cmd)
+{
+ uint32_t i, timeout;
+
+ if (TSC_Def != TSC)
+ return TSC_ERROR_PARAMETER;
+
+ if ((TIMx != TIM2) && (TIMx != TIM4))
+ return TSC_ERROR_PARAMETER;
+
+
+ /* Disable the TSC HW MODE */
+ timeout = 0;
+ do
+ {
+ __TSC_HW_DISABLE();
+
+ if (++timeout > TSC_TIMEOUT)
+ return TSC_ERROR_HW_MODE;
+ }while (__TSC_GET_HW_MODE());
+
+ if (Cmd == DISABLE) // Close output by software mode
+ {
+ __TSC_OUT_CONFIG(TSC_OUT_PIN);
+ __TSC_SW_DISABLE();
+ }
+ else
+ {
+ for (i = 0; i < MAX_TSC_HW_CHN; i++)
+ {
+ if (Channel & 0x00000001)
+ {
+ __TSC_SW_CHN_NUM_CONFIG(i);
+ break;
+ }
+
+ Channel >>= 1;
+ }
+
+ // Select to output to specified TIMER.
+ if (TIMx == TIM4)
+ {
+ __TSC_OUT_CONFIG(TSC_OUT_TIM4_ETR);
+ }
+ else
+ {
+ __TSC_OUT_CONFIG(TSC_OUT_TIM2_ETR);
+ }
+
+ __TSC_SW_ENABLE();
+ }
+
+ // delay time for tsc channel stabilize output
+ for (i = 0; i < 2000; i++)
+ {
+ }
+
+ return TSC_ERROR_OK;
+}
+
+/**
+ * @brief Configure analog signal parameters.
+ * @param TSC_Def Pointer of TSC register.
+ * @param AnaoCfg Pointer of analog parameter structure.
+ */
+TSC_ErrorTypeDef TSC_SetAnaoCfg(TSC_Module* TSC_Def, TSC_AnaoCfg* AnaoCfg)
+{
+ if (TSC_Def != TSC)
+ return TSC_ERROR_PARAMETER;
+
+ if (AnaoCfg == 0)
+ return TSC_ERROR_PARAMETER;
+
+ assert_param(IS_TSC_PAD_OPTION(AnaoCfg->TSC_AnaoptrResisOption));
+ assert_param(IS_TSC_PAD_SPEED(AnaoCfg->TSC_AnaoptrSpeedOption));
+
+ __TSC_PAD_OPT_CONFIG(AnaoCfg->TSC_AnaoptrResisOption);
+ __TSC_PAD_SPEED_CONFIG(AnaoCfg->TSC_AnaoptrSpeedOption);
+
+ return TSC_ERROR_OK;
+}
+
+/**
+ * @brief Configure channel parameters by channel or operation.Support configure several channels at the same time.
+ * @param TSC_Def Pointer of TSC register.
+ * @param ChnCfg Channel parameters.
+ * @param Channels: channels to be configed, as TSC_CHNEN defined
+ * This parameter:bit[0:23] used,bit[24:31] must be 0
+ * bitx: TSC channel x
+ */
+TSC_ErrorTypeDef TSC_SetChannelCfg(TSC_Module* TSC_Def, TSC_ChnCfg* ChnCfg, uint32_t Channels)
+{
+ TSC_ErrorTypeDef err;
+
+ if (TSC_Def != TSC)
+ return TSC_ERROR_PARAMETER;
+
+ if (0 == ChnCfg)
+ return TSC_ERROR_PARAMETER;
+
+ // Set resistance
+ err = TSC_ConfigInternalResistor(TSC_Def, Channels, ChnCfg->TSC_ResisValue);
+ if (err != TSC_ERROR_OK)
+ return err;
+
+ // Set the threshold of base and delta.
+ err = TSC_ConfigThreshold(TSC_Def, Channels, ChnCfg->TSC_Base, ChnCfg->TSC_Delta);
+ return err;
+}
+
+
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_usart.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_usart.c
new file mode 100644
index 0000000000..745deeef27
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_usart.c
@@ -0,0 +1,974 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_usart.c
+ * @author Nations
+ * @version v1.0.1
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32wb452_usart.h"
+#include "n32wb452_rcc.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup USART
+ * @brief USART driver modules
+ * @{
+ */
+
+/** @addtogroup USART_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Private_Defines
+ * @{
+ */
+
+#define CTRL1_UEN_SET ((uint16_t)0x2000) /*!< USART Enable Mask */
+#define CTRL1_UEN_RESET ((uint16_t)0xDFFF) /*!< USART Disable Mask */
+
+#define CTRL1_WUM_MASK ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */
+
+#define CTRL1_RCVWU_SET ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */
+#define CTRL1_RCVWU_RESET ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */
+#define CTRL1_SDBRK_SET ((uint16_t)0x0001) /*!< USART Break Character send Mask */
+#define CTRL1_CLR_MASK ((uint16_t)0xE9F3) /*!< USART CTRL1 Mask */
+#define CTRL2_ADDR_MASK ((uint16_t)0xFFF0) /*!< USART address Mask */
+
+#define CTRL2_LINMEN_SET ((uint16_t)0x4000) /*!< USART LIN Enable Mask */
+#define CTRL2_LINMEN_RESET ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */
+
+#define CTRL2_LINBDL_MASK ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */
+#define CTRL2_STPB_CLR_MASK ((uint16_t)0xCFFF) /*!< USART CTRL2 STOP Bits Mask */
+#define CTRL2_CLOCK_CLR_MASK ((uint16_t)0xF0FF) /*!< USART CTRL2 Clock Mask */
+
+#define CTRL3_SCMEN_SET ((uint16_t)0x0020) /*!< USART SC Enable Mask */
+#define CTRL3_SCMEN_RESET ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */
+
+#define CTRL3_SCNACK_SET ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */
+#define CTRL3_SCNACK_RESET ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */
+
+#define CTRL3_HDMEN_SET ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */
+#define CTRL3_HDMEN_RESET ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */
+
+#define CTRL3_IRDALP_MASK ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */
+#define CTRL3_CLR_MASK ((uint16_t)0xFCFF) /*!< USART CTRL3 Mask */
+
+#define CTRL3_IRDAMEN_SET ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */
+#define CTRL3_IRDAMEN_RESET ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */
+#define GTP_LSB_MASK ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */
+#define GTP_MSB_MASK ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */
+#define INT_MASK ((uint16_t)0x001F) /*!< USART Interrupt Mask */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the USARTx peripheral registers to their default reset values.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ */
+void USART_DeInit(USART_Module* USARTx)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ if (USARTx == USART1)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_USART1, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_USART1, DISABLE);
+ }
+ else if (USARTx == USART2)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART2, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART2, DISABLE);
+ }
+ else if (USARTx == USART3)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART3, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART3, DISABLE);
+ }
+ else if (USARTx == UART4)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_UART4, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_UART4, DISABLE);
+ }
+ else if (USARTx == UART5)
+ {
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_UART5, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_UART5, DISABLE);
+ }
+ else if (USARTx == UART6)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART6, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART6, DISABLE);
+ }
+ else
+ {
+ if (USARTx == UART7)
+ {
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART7, ENABLE);
+ RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART7, DISABLE);
+ }
+ }
+}
+
+/**
+ * @brief Initializes the USARTx peripheral according to the specified
+ * parameters in the USART_InitStruct .
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_InitStruct pointer to a USART_InitType structure
+ * that contains the configuration information for the specified USART
+ * peripheral.
+ */
+void USART_Init(USART_Module* USARTx, USART_InitType* USART_InitStruct)
+{
+ uint32_t tmpregister = 0x00, apbclock = 0x00;
+ uint32_t integerdivider = 0x00;
+ uint32_t fractionaldivider = 0x00;
+ uint32_t usartxbase = 0;
+ RCC_ClocksType RCC_ClocksStatus;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_BAUDRATE(USART_InitStruct->BaudRate));
+ assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->WordLength));
+ assert_param(IS_USART_STOPBITS(USART_InitStruct->StopBits));
+ assert_param(IS_USART_PARITY(USART_InitStruct->Parity));
+ assert_param(IS_USART_MODE(USART_InitStruct->Mode));
+ assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->HardwareFlowControl));
+ /* The hardware flow control is available only for USART1, USART2 and USART3 */
+ if (USART_InitStruct->HardwareFlowControl != USART_HFCTRL_NONE)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ usartxbase = (uint32_t)USARTx;
+
+ /*---------------------------- USART CTRL2 Configuration -----------------------*/
+ tmpregister = USARTx->CTRL2;
+ /* Clear STOP[13:12] bits */
+ tmpregister &= CTRL2_STPB_CLR_MASK;
+ /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
+ /* Set STOP[13:12] bits according to StopBits value */
+ tmpregister |= (uint32_t)USART_InitStruct->StopBits;
+
+ /* Write to USART CTRL2 */
+ USARTx->CTRL2 = (uint16_t)tmpregister;
+
+ /*---------------------------- USART CTRL1 Configuration -----------------------*/
+ tmpregister = USARTx->CTRL1;
+ /* Clear M, PCE, PS, TE and RE bits */
+ tmpregister &= CTRL1_CLR_MASK;
+ /* Configure the USART Word Length, Parity and mode ----------------------- */
+ /* Set the M bits according to WordLength value */
+ /* Set PCE and PS bits according to Parity value */
+ /* Set TE and RE bits according to Mode value */
+ tmpregister |= (uint32_t)USART_InitStruct->WordLength | USART_InitStruct->Parity | USART_InitStruct->Mode;
+ /* Write to USART CTRL1 */
+ USARTx->CTRL1 = (uint16_t)tmpregister;
+
+ /*---------------------------- USART CTRL3 Configuration -----------------------*/
+ tmpregister = USARTx->CTRL3;
+ /* Clear CTSE and RTSE bits */
+ tmpregister &= CTRL3_CLR_MASK;
+ /* Configure the USART HFC -------------------------------------------------*/
+ /* Set CTSE and RTSE bits according to HardwareFlowControl value */
+ tmpregister |= USART_InitStruct->HardwareFlowControl;
+ /* Write to USART CTRL3 */
+ USARTx->CTRL3 = (uint16_t)tmpregister;
+
+ /*---------------------------- USART PBC Configuration -----------------------*/
+ /* Configure the USART Baud Rate -------------------------------------------*/
+ RCC_GetClocksFreqValue(&RCC_ClocksStatus);
+ if ((usartxbase == USART1_BASE) || (usartxbase == UART6_BASE) || (usartxbase == UART7_BASE))
+ {
+ apbclock = RCC_ClocksStatus.Pclk2Freq;
+ }
+ else
+ {
+ apbclock = RCC_ClocksStatus.Pclk1Freq;
+ }
+
+ /* Determine the integer part */
+ integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->BaudRate)));
+ tmpregister = (integerdivider / 100) << 4;
+
+ /* Determine the fractional part */
+ fractionaldivider = (((((integerdivider - (100 * (tmpregister >> 4))) * 16) + 50) / 100));
+
+ /*Determine whether the fractional part needs to carried*/
+ if ((fractionaldivider >> 4) == 1){
+ tmpregister = ((integerdivider / 100) + 1) << 4;
+ }
+
+ /* Implement the fractional part in the register */
+ tmpregister |= fractionaldivider & ((uint8_t)0x0F);
+
+ /* Write to USART PBC */
+ USARTx->BRCF = (uint16_t)tmpregister;
+}
+
+/**
+ * @brief Fills each USART_InitStruct member with its default value.
+ * @param USART_InitStruct pointer to a USART_InitType structure
+ * which will be initialized.
+ */
+void USART_StructInit(USART_InitType* USART_InitStruct)
+{
+ /* USART_InitStruct members default value */
+ USART_InitStruct->BaudRate = 9600;
+ USART_InitStruct->WordLength = USART_WL_8B;
+ USART_InitStruct->StopBits = USART_STPB_1;
+ USART_InitStruct->Parity = USART_PE_NO;
+ USART_InitStruct->Mode = USART_MODE_RX | USART_MODE_TX;
+ USART_InitStruct->HardwareFlowControl = USART_HFCTRL_NONE;
+}
+
+/**
+ * @brief Initializes the USARTx peripheral Clock according to the
+ * specified parameters in the USART_ClockInitStruct .
+ * @param USARTx where x can be 1, 2, 3 to select the USART peripheral.
+ * @param USART_ClockInitStruct pointer to a USART_ClockInitType
+ * structure that contains the configuration information for the specified
+ * USART peripheral.
+ * @note The Smart Card and Synchronous modes are not available for UART4/UART5/UART6/UART7.
+ */
+void USART_ClockInit(USART_Module* USARTx, USART_ClockInitType* USART_ClockInitStruct)
+{
+ uint32_t tmpregister = 0x00;
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ assert_param(IS_USART_CLOCK(USART_ClockInitStruct->Clock));
+ assert_param(IS_USART_CPOL(USART_ClockInitStruct->Polarity));
+ assert_param(IS_USART_CPHA(USART_ClockInitStruct->Phase));
+ assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->LastBit));
+
+ /*---------------------------- USART CTRL2 Configuration -----------------------*/
+ tmpregister = USARTx->CTRL2;
+ /* Clear CLKEN, CPOL, CPHA and LBCL bits */
+ tmpregister &= CTRL2_CLOCK_CLR_MASK;
+ /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/
+ /* Set CLKEN bit according to Clock value */
+ /* Set CPOL bit according to Polarity value */
+ /* Set CPHA bit according to Phase value */
+ /* Set LBCL bit according to LastBit value */
+ tmpregister |= (uint32_t)USART_ClockInitStruct->Clock | USART_ClockInitStruct->Polarity
+ | USART_ClockInitStruct->Phase | USART_ClockInitStruct->LastBit;
+ /* Write to USART CTRL2 */
+ USARTx->CTRL2 = (uint16_t)tmpregister;
+}
+
+/**
+ * @brief Fills each USART_ClockInitStruct member with its default value.
+ * @param USART_ClockInitStruct pointer to a USART_ClockInitType
+ * structure which will be initialized.
+ */
+void USART_ClockStructInit(USART_ClockInitType* USART_ClockInitStruct)
+{
+ /* USART_ClockInitStruct members default value */
+ USART_ClockInitStruct->Clock = USART_CLK_DISABLE;
+ USART_ClockInitStruct->Polarity = USART_CLKPOL_LOW;
+ USART_ClockInitStruct->Phase = USART_CLKPHA_1EDGE;
+ USART_ClockInitStruct->LastBit = USART_CLKLB_DISABLE;
+}
+
+/**
+ * @brief Enables or disables the specified USART peripheral.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, UART6 or UART7.
+ * @param Cmd new state of the USARTx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void USART_Enable(USART_Module* USARTx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the selected USART by setting the UE bit in the CTRL1 register */
+ USARTx->CTRL1 |= CTRL1_UEN_SET;
+ }
+ else
+ {
+ /* Disable the selected USART by clearing the UE bit in the CTRL1 register */
+ USARTx->CTRL1 &= CTRL1_UEN_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified USART interrupts.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, UART6 or UART7.
+ * @param USART_INT specifies the USART interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg USART_INT_CTSF CTS change interrupt (not available for UART4 and UART5)
+ * @arg USART_INT_LINBD LIN Break detection interrupt
+ * @arg USART_INT_TXDE Transmit Data Register empty interrupt
+ * @arg USART_INT_TXC Transmission complete interrupt
+ * @arg USART_INT_RXDNE Receive Data register not empty interrupt
+ * @arg USART_INT_IDLEF Idle line detection interrupt
+ * @arg USART_INT_PEF Parity Error interrupt
+ * @arg USART_INT_ERRF Error interrupt(Frame error, noise error, overrun error)
+ * @param Cmd new state of the specified USARTx interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void USART_ConfigInt(USART_Module* USARTx, uint16_t USART_INT, FunctionalState Cmd)
+{
+ uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
+ uint32_t usartxbase = 0x00;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_CFG_INT(USART_INT));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ /* The CTS interrupt is not available for UART4/UART5/UART6/UART7 */
+ if (USART_INT == USART_INT_CTSF)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ usartxbase = (uint32_t)USARTx;
+
+ /* Get the USART register index */
+ usartreg = (((uint8_t)USART_INT) >> 0x05);
+
+ /* Get the interrupt position */
+ itpos = USART_INT & INT_MASK;
+ itmask = (((uint32_t)0x01) << itpos);
+
+ if (usartreg == 0x01) /* The IT is in CTRL1 register */
+ {
+ usartxbase += 0x0C;
+ }
+ else if (usartreg == 0x02) /* The IT is in CTRL2 register */
+ {
+ usartxbase += 0x10;
+ }
+ else /* The IT is in CTRL3 register */
+ {
+ usartxbase += 0x14;
+ }
+ if (Cmd != DISABLE)
+ {
+ *(__IO uint32_t*)usartxbase |= itmask;
+ }
+ else
+ {
+ *(__IO uint32_t*)usartxbase &= ~itmask;
+ }
+}
+
+/**
+ * @brief Enables or disables the USART's DMA interface.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, UART6 or UART7.
+ * @param USART_DMAReq specifies the DMA request.
+ * This parameter can be any combination of the following values:
+ * @arg USART_DMAREQ_TX USART DMA transmit request
+ * @arg USART_DMAREQ_RX USART DMA receive request
+ * @param Cmd new state of the DMA Request sources.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void USART_EnableDMA(USART_Module* USARTx, uint16_t USART_DMAReq, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_DMAREQ(USART_DMAReq));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the DMA transfer for selected requests by setting the DMAT and/or
+ DADDR bits in the USART CTRL3 register */
+ USARTx->CTRL3 |= USART_DMAReq;
+ }
+ else
+ {
+ /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
+ DADDR bits in the USART CTRL3 register */
+ USARTx->CTRL3 &= (uint16_t)~USART_DMAReq;
+ }
+}
+
+/**
+ * @brief Sets the address of the USART node.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, UART6 or UART7.
+ * @param USART_Addr Indicates the address of the USART node.
+ */
+void USART_SetAddr(USART_Module* USARTx, uint8_t USART_Addr)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_ADDRESS(USART_Addr));
+
+ /* Clear the USART address */
+ USARTx->CTRL2 &= CTRL2_ADDR_MASK;
+ /* Set the USART address node */
+ USARTx->CTRL2 |= USART_Addr;
+}
+
+/**
+ * @brief Selects the USART WakeUp method.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, UART6 or UART7.
+ * @param USART_WakeUpMode specifies the USART wakeup method.
+ * This parameter can be one of the following values:
+ * @arg USART_WUM_IDLELINE WakeUp by an idle line detection
+ * @arg USART_WUM_ADDRMASK WakeUp by an address mark
+ */
+void USART_ConfigWakeUpMode(USART_Module* USARTx, uint16_t USART_WakeUpMode)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_WAKEUP(USART_WakeUpMode));
+
+ USARTx->CTRL1 &= CTRL1_WUM_MASK;
+ USARTx->CTRL1 |= USART_WakeUpMode;
+}
+
+/**
+ * @brief Determines if the USART is in mute mode or not.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, UART6 or UART7.
+ * @param Cmd new state of the USART mute mode.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void USART_EnableRcvWakeUp(USART_Module* USARTx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the USART mute mode by setting the RWU bit in the CTRL1 register */
+ USARTx->CTRL1 |= CTRL1_RCVWU_SET;
+ }
+ else
+ {
+ /* Disable the USART mute mode by clearing the RWU bit in the CTRL1 register */
+ USARTx->CTRL1 &= CTRL1_RCVWU_RESET;
+ }
+}
+
+/**
+ * @brief Sets the USART LIN Break detection length.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, UART6 or UART7.
+ * @param USART_LINBreakDetectLength specifies the LIN break detection length.
+ * This parameter can be one of the following values:
+ * @arg USART_LINBDL_10B 10-bit break detection
+ * @arg USART_LINBDL_11B 11-bit break detection
+ */
+void USART_ConfigLINBreakDetectLength(USART_Module* USARTx, uint16_t USART_LINBreakDetectLength)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
+
+ USARTx->CTRL2 &= CTRL2_LINBDL_MASK;
+ USARTx->CTRL2 |= USART_LINBreakDetectLength;
+}
+
+/**
+ * @brief Enables or disables the USART's LIN mode.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, UART6 or UART7.
+ * @param Cmd new state of the USART LIN mode.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void USART_EnableLIN(USART_Module* USARTx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the LIN mode by setting the LINEN bit in the CTRL2 register */
+ USARTx->CTRL2 |= CTRL2_LINMEN_SET;
+ }
+ else
+ {
+ /* Disable the LIN mode by clearing the LINEN bit in the CTRL2 register */
+ USARTx->CTRL2 &= CTRL2_LINMEN_RESET;
+ }
+}
+
+/**
+ * @brief Transmits single data through the USARTx peripheral.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, UART6 or UART7.
+ * @param Data the data to transmit.
+ */
+void USART_SendData(USART_Module* USARTx, uint16_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_DATA(Data));
+
+ /* Transmit Data */
+ USARTx->DAT = (Data & (uint16_t)0x01FF);
+}
+
+/**
+ * @brief Returns the most recent received data by the USARTx peripheral.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, UART6 or UART7.
+ * @return The received data.
+ */
+uint16_t USART_ReceiveData(USART_Module* USARTx)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ /* Receive Data */
+ return (uint16_t)(USARTx->DAT & (uint16_t)0x01FF);
+}
+
+/**
+ * @brief Transmits break characters.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, UART6 or UART7.
+ */
+void USART_SendBreak(USART_Module* USARTx)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ /* Send break characters */
+ USARTx->CTRL1 |= CTRL1_SDBRK_SET;
+}
+
+/**
+ * @brief Sets the specified USART guard time.
+ * @param USARTx where x can be 1, 2 or 3 to select the USART peripheral.
+ * @param USART_GuardTime specifies the guard time.
+ * @note The guard time bits are not available for UART4/UART5/UART6/UART7.
+ */
+void USART_SetGuardTime(USART_Module* USARTx, uint8_t USART_GuardTime)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+
+ /* Clear the USART Guard time */
+ USARTx->GTP &= GTP_LSB_MASK;
+ /* Set the USART guard time */
+ USARTx->GTP |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
+}
+
+/**
+ * @brief Sets the system clock prescaler.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, UART6 or UART7.
+ * @param USART_Prescaler specifies the prescaler clock.
+ * @note The function is used for IrDA mode with UART4 and UART5.
+ */
+void USART_SetPrescaler(USART_Module* USARTx, uint8_t USART_Prescaler)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ /* Clear the USART prescaler */
+ USARTx->GTP &= GTP_MSB_MASK;
+ /* Set the USART prescaler */
+ USARTx->GTP |= USART_Prescaler;
+}
+
+/**
+ * @brief Enables or disables the USART's Smart Card mode.
+ * @param USARTx where x can be 1, 2 or 3 to select the USART peripheral.
+ * @param Cmd new state of the Smart Card mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note The Smart Card mode is not available for UART4/UART5/UART6/UART7.
+ */
+void USART_EnableSmartCard(USART_Module* USARTx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the SC mode by setting the SCEN bit in the CTRL3 register */
+ USARTx->CTRL3 |= CTRL3_SCMEN_SET;
+ }
+ else
+ {
+ /* Disable the SC mode by clearing the SCEN bit in the CTRL3 register */
+ USARTx->CTRL3 &= CTRL3_SCMEN_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables NACK transmission.
+ * @param USARTx where x can be 1, 2 or 3 to select the USART peripheral.
+ * @param Cmd new state of the NACK transmission.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note The Smart Card mode is not available for UART4/UART5/UART6/UART7.
+ */
+void USART_SetSmartCardNACK(USART_Module* USARTx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+ if (Cmd != DISABLE)
+ {
+ /* Enable the NACK transmission by setting the NACK bit in the CTRL3 register */
+ USARTx->CTRL3 |= CTRL3_SCNACK_SET;
+ }
+ else
+ {
+ /* Disable the NACK transmission by clearing the NACK bit in the CTRL3 register */
+ USARTx->CTRL3 &= CTRL3_SCNACK_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the USART's Half Duplex communication.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, UART6 or UART7.
+ * @param Cmd new state of the USART Communication.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void USART_EnableHalfDuplex(USART_Module* USARTx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CTRL3 register */
+ USARTx->CTRL3 |= CTRL3_HDMEN_SET;
+ }
+ else
+ {
+ /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CTRL3 register */
+ USARTx->CTRL3 &= CTRL3_HDMEN_RESET;
+ }
+}
+
+/**
+ * @brief Configures the USART's IrDA interface.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, UART6 or UART7.
+ * @param USART_IrDAMode specifies the IrDA mode.
+ * This parameter can be one of the following values:
+ * @arg USART_IRDAMODE_LOWPPWER
+ * @arg USART_IRDAMODE_NORMAL
+ */
+void USART_ConfigIrDAMode(USART_Module* USARTx, uint16_t USART_IrDAMode)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
+
+ USARTx->CTRL3 &= CTRL3_IRDALP_MASK;
+ USARTx->CTRL3 |= USART_IrDAMode;
+}
+
+/**
+ * @brief Enables or disables the USART's IrDA interface.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, UART6 or UART7.
+ * @param Cmd new state of the IrDA mode.
+ * This parameter can be: ENABLE or DISABLE.
+ */
+void USART_EnableIrDA(USART_Module* USARTx, FunctionalState Cmd)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+ if (Cmd != DISABLE)
+ {
+ /* Enable the IrDA mode by setting the IREN bit in the CTRL3 register */
+ USARTx->CTRL3 |= CTRL3_IRDAMEN_SET;
+ }
+ else
+ {
+ /* Disable the IrDA mode by clearing the IREN bit in the CTRL3 register */
+ USARTx->CTRL3 &= CTRL3_IRDAMEN_RESET;
+ }
+}
+
+/**
+ * @brief Checks whether the specified USART flag is set or not.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, UART6 or UART7.
+ * @param USART_FLAG specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg USART_FLAG_CTSF CTS Change flag (not available for UART4 and UART5)
+ * @arg USART_FLAG_LINBD LIN Break detection flag
+ * @arg USART_FLAG_TXDE Transmit data register empty flag
+ * @arg USART_FLAG_TXC Transmission Complete flag
+ * @arg USART_FLAG_RXDNE Receive data register not empty flag
+ * @arg USART_FLAG_IDLEF Idle Line detection flag
+ * @arg USART_FLAG_OREF OverRun Error flag
+ * @arg USART_FLAG_NEF Noise Error flag
+ * @arg USART_FLAG_FEF Framing Error flag
+ * @arg USART_FLAG_PEF Parity Error flag
+ * @return The new state of USART_FLAG (SET or RESET).
+ */
+FlagStatus USART_GetFlagStatus(USART_Module* USARTx, uint16_t USART_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_FLAG(USART_FLAG));
+ /* The CTS flag is not available for UART4/UART5/UART6/UART7 */
+ if (USART_FLAG == USART_FLAG_CTSF)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ if ((USARTx->STS & USART_FLAG) != (uint16_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the USARTx's pending flags.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, UART6 or UART7.
+ * @param USART_FLAG specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg USART_FLAG_CTSF CTS Change flag (not available for UART4 and UART5).
+ * @arg USART_FLAG_LINBD LIN Break detection flag.
+ * @arg USART_FLAG_TXC Transmission Complete flag.
+ * @arg USART_FLAG_RXDNE Receive data register not empty flag.
+ *
+ * @note
+ * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ * error) and IDLE (Idle line detected) flags are cleared by software
+ * sequence: a read operation to USART_SR register (USART_GetFlagStatus())
+ * followed by a read operation to USART_DR register (USART_ReceiveData()).
+ * - RXNE flag can be also cleared by a read to the USART_DR register
+ * (USART_ReceiveData()).
+ * - TC flag can be also cleared by software sequence: a read operation to
+ * USART_SR register (USART_GetFlagStatus()) followed by a write operation
+ * to USART_DR register (USART_SendData()).
+ * - TXE flag is cleared only by a write to the USART_DR register
+ * (USART_SendData()).
+ */
+void USART_ClrFlag(USART_Module* USARTx, uint16_t USART_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
+ /* The CTS flag is not available for UART4/UART5/UART6/UART7 */
+ if ((USART_FLAG & USART_FLAG_CTSF) == USART_FLAG_CTSF)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ USARTx->STS = (uint16_t)~USART_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified USART interrupt has occurred or not.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, UART6 or UART7.
+ * @param USART_INT specifies the USART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg USART_INT_CTSF CTS change interrupt (not available for UART4 and UART5)
+ * @arg USART_INT_LINBD LIN Break detection interrupt
+ * @arg USART_INT_TXDE Tansmit Data Register empty interrupt
+ * @arg USART_INT_TXC Transmission complete interrupt
+ * @arg USART_INT_RXDNE Receive Data register not empty interrupt
+ * @arg USART_INT_IDLEF Idle line detection interrupt
+ * @arg USART_INT_OREF OverRun Error interrupt
+ * @arg USART_INT_NEF Noise Error interrupt
+ * @arg USART_INT_FEF Framing Error interrupt
+ * @arg USART_INT_PEF Parity Error interrupt
+ * @return The new state of USART_INT (SET or RESET).
+ */
+INTStatus USART_GetIntStatus(USART_Module* USARTx, uint16_t USART_INT)
+{
+ uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
+ INTStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_GET_INT(USART_INT));
+ /* The CTS interrupt is not available for UART4/UART5/UART6/UART7 */
+ if (USART_INT == USART_INT_CTSF)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ /* Get the USART register index */
+ usartreg = (((uint8_t)USART_INT) >> 0x05);
+ /* Get the interrupt position */
+ itmask = USART_INT & INT_MASK;
+ itmask = (uint32_t)0x01 << itmask;
+
+ if (usartreg == 0x01) /* The IT is in CTRL1 register */
+ {
+ itmask &= USARTx->CTRL1;
+ }
+ else if (usartreg == 0x02) /* The IT is in CTRL2 register */
+ {
+ itmask &= USARTx->CTRL2;
+ }
+ else /* The IT is in CTRL3 register */
+ {
+ itmask &= USARTx->CTRL3;
+ }
+
+ bitpos = USART_INT >> 0x08;
+ bitpos = (uint32_t)0x01 << bitpos;
+ bitpos &= USARTx->STS;
+ if ((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the USARTx's interrupt pending bits.
+ * @param USARTx Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, UART6 or UART7.
+ * @param USART_INT specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg USART_INT_CTSF CTS change interrupt (not available for UART4 and UART5)
+ * @arg USART_INT_LINBD LIN Break detection interrupt
+ * @arg USART_INT_TXC Transmission complete interrupt.
+ * @arg USART_INT_RXDNE Receive Data register not empty interrupt.
+ *
+ * @note
+ * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ * error) and IDLE (Idle line detected) pending bits are cleared by
+ * software sequence: a read operation to USART_SR register
+ * (USART_GetIntStatus()) followed by a read operation to USART_DR register
+ * (USART_ReceiveData()).
+ * - RXNE pending bit can be also cleared by a read to the USART_DR register
+ * (USART_ReceiveData()).
+ * - TC pending bit can be also cleared by software sequence: a read
+ * operation to USART_SR register (USART_GetIntStatus()) followed by a write
+ * operation to USART_DR register (USART_SendData()).
+ * - TXE pending bit is cleared only by a write to the USART_DR register
+ * (USART_SendData()).
+ */
+void USART_ClrIntPendingBit(USART_Module* USARTx, uint16_t USART_INT)
+{
+ uint16_t bitpos = 0x00, itmask = 0x00;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_CLR_INT(USART_INT));
+ /* The CTS interrupt is not available for UART4/UART5/UART6/UART7 */
+ if (USART_INT == USART_INT_CTSF)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ bitpos = USART_INT >> 0x08;
+ itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
+ USARTx->STS = (uint16_t)~itmask;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_wwdg.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_wwdg.c
new file mode 100644
index 0000000000..06d9d40380
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_wwdg.c
@@ -0,0 +1,223 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32wb452_wwdg.c
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32wb452_wwdg.h"
+#include "n32wb452_rcc.h"
+
+/** @addtogroup N32WB452_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup WWDG
+ * @brief WWDG driver modules
+ * @{
+ */
+
+/** @addtogroup WWDG_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Private_Defines
+ * @{
+ */
+
+/* ----------- WWDG registers bit address in the alias region ----------- */
+#define WWDG_OFFADDR (WWDG_BASE - PERIPH_BASE)
+
+/* Alias word address of EWI bit */
+#define CFG_OFFADDR (WWDG_OFFADDR + 0x04)
+#define EWINT_BIT 0x09
+#define CFG_EWINT_BB (PERIPH_BB_BASE + (CFG_OFFADDR * 32) + (EWINT_BIT * 4))
+
+/* --------------------- WWDG registers bit mask ------------------------ */
+
+/* CTRL register bit mask */
+#define CTRL_ACTB_SET ((uint32_t)0x00000080)
+
+/* CFG register bit mask */
+#define CFG_TIMERB_MASK ((uint32_t)0xFFFFFE7F)
+#define CFG_W_MASK ((uint32_t)0xFFFFFF80)
+#define BIT_MASK ((uint8_t)0x7F)
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the WWDG peripheral registers to their default reset values.
+ */
+void WWDG_DeInit(void)
+{
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_WWDG, ENABLE);
+ RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_WWDG, DISABLE);
+}
+
+/**
+ * @brief Sets the WWDG Prescaler.
+ * @param WWDG_Prescaler specifies the WWDG Prescaler.
+ * This parameter can be one of the following values:
+ * @arg WWDG_PRESCALER_DIV1 WWDG counter clock = (PCLK1/4096)/1
+ * @arg WWDG_PRESCALER_DIV2 WWDG counter clock = (PCLK1/4096)/2
+ * @arg WWDG_PRESCALER_DIV4 WWDG counter clock = (PCLK1/4096)/4
+ * @arg WWDG_PRESCALER_DIV8 WWDG counter clock = (PCLK1/4096)/8
+ */
+void WWDG_SetPrescalerDiv(uint32_t WWDG_Prescaler)
+{
+ uint32_t tmpregister = 0;
+ /* Check the parameters */
+ assert_param(IS_WWDG_PRESCALER_DIV(WWDG_Prescaler));
+ /* Clear WDGTB[1:0] bits */
+ tmpregister = WWDG->CFG & CFG_TIMERB_MASK;
+ /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
+ tmpregister |= WWDG_Prescaler;
+ /* Store the new value */
+ WWDG->CFG = tmpregister;
+}
+
+/**
+ * @brief Sets the WWDG window value.
+ * @param WindowValue specifies the window value to be compared to the downcounter.
+ * This parameter value must be lower than 0x80.
+ */
+void WWDG_SetWValue(uint8_t WindowValue)
+{
+ __IO uint32_t tmpregister = 0;
+
+ /* Check the parameters */
+ assert_param(IS_WWDG_WVALUE(WindowValue));
+ /* Clear W[6:0] bits */
+
+ tmpregister = WWDG->CFG & CFG_W_MASK;
+
+ /* Set W[6:0] bits according to WindowValue value */
+ tmpregister |= WindowValue & (uint32_t)BIT_MASK;
+
+ /* Store the new value */
+ WWDG->CFG = tmpregister;
+}
+
+/**
+ * @brief Enables the WWDG Early Wakeup interrupt(EWI).
+ */
+void WWDG_EnableInt(void)
+{
+ *(__IO uint32_t*)CFG_EWINT_BB = (uint32_t)ENABLE;
+}
+
+/**
+ * @brief Sets the WWDG counter value.
+ * @param Counter specifies the watchdog counter value.
+ * This parameter must be a number between 0x40 and 0x7F.
+ */
+void WWDG_SetCnt(uint8_t Counter)
+{
+ /* Check the parameters */
+ assert_param(IS_WWDG_CNT(Counter));
+ /* Write to T[6:0] bits to configure the counter value, no need to do
+ a read-modify-write; writing a 0 to WDGA bit does nothing */
+ WWDG->CTRL = Counter & BIT_MASK;
+}
+
+/**
+ * @brief Enables WWDG and load the counter value.
+ * @param Counter specifies the watchdog counter value.
+ * This parameter must be a number between 0x40 and 0x7F.
+ */
+void WWDG_Enable(uint8_t Counter)
+{
+ /* Check the parameters */
+ assert_param(IS_WWDG_CNT(Counter));
+ WWDG->CTRL = CTRL_ACTB_SET | Counter;
+}
+
+/**
+ * @brief Checks whether the Early Wakeup interrupt flag is set or not.
+ * @return The new state of the Early Wakeup interrupt flag (SET or RESET)
+ */
+FlagStatus WWDG_GetEWINTF(void)
+{
+ return (FlagStatus)(WWDG->STS);
+}
+
+/**
+ * @brief Clears Early Wakeup interrupt flag.
+ */
+void WWDG_ClrEWINTF(void)
+{
+ WWDG->STS = (uint32_t)RESET;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_core.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_core.h
new file mode 100644
index 0000000000..39d57920aa
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_core.h
@@ -0,0 +1,264 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_core.h
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_CORE_H__
+#define __USB_CORE_H__
+
+#include "n32wb452.h"
+
+/**
+ * @addtogroup N32WB452_USB_Driver
+ * @brief N32WB452 USB low level driver
+ * @{
+ */
+
+typedef enum _CONTROL_STATE
+{
+ WaitSetup, /* 0 */
+ SettingUp, /* 1 */
+ InData, /* 2 */
+ OutData, /* 3 */
+ LastInData, /* 4 */
+ LastOutData, /* 5 */
+ WaitStatusIn, /* 7 */
+ WaitStatusOut, /* 8 */
+ Stalled, /* 9 */
+ Pause /* 10 */
+} USB_ControlState; /* The state machine states of a control pipe */
+
+typedef struct OneDescriptor
+{
+ uint8_t* Descriptor;
+ uint16_t Descriptor_Size;
+} USB_OneDescriptor, *PONE_DESCRIPTOR;
+/* All the request process routines return a value of this type
+ If the return value is not SUCCESS or NOT_READY,
+ the software will STALL the correspond endpoint */
+typedef enum _RESULT
+{
+ Success = 0, /* Process successfully */
+ Error,
+ UnSupport,
+ Not_Ready /* The process has not been finished, endpoint will be
+ NAK to further request */
+} USB_Result;
+
+/*-*-*-*-*-*-*-*-*-*-* Definitions for endpoint level -*-*-*-*-*-*-*-*-*-*-*-*/
+typedef struct _ENDPOINT_INFO
+{
+ /* When send data out of the device,
+ CopyData() is used to get data buffer 'Length' bytes data
+ if Length is 0,
+ CopyData() returns the total length of the data
+ if the request is not supported, returns 0
+ (NEW Feature )
+ if CopyData() returns -1, the calling routine should not proceed
+ further and will resume the SETUP process by the class device
+ if Length is not 0,
+ CopyData() returns a pointer to indicate the data location
+ Usb_wLength is the data remain to be sent,
+ Usb_wOffset is the Offset of original data
+ When receive data from the host,
+ CopyData() is used to get user data buffer which is capable
+ of Length bytes data to copy data from the endpoint buffer.
+ if Length is 0,
+ CopyData() returns the available data length,
+ if Length is not 0,
+ CopyData() returns user buffer address
+ Usb_rLength is the data remain to be received,
+ Usb_rPointer is the Offset of data buffer
+ */
+ uint16_t Usb_wLength;
+ uint16_t Usb_wOffset;
+ uint16_t PacketSize;
+ uint8_t* (*CopyData)(uint16_t Length);
+} USB_EndpointMess;
+
+/*-*-*-*-*-*-*-*-*-*-*-* Definitions for device level -*-*-*-*-*-*-*-*-*-*-*-*/
+
+typedef struct _DEVICE
+{
+ uint8_t TotalEndpoint; /* Number of endpoints that are used */
+ uint8_t TotalConfiguration; /* Number of configuration available */
+} USB_Device;
+
+typedef union
+{
+ uint16_t w;
+ struct BW
+ {
+ uint8_t bb1;
+ uint8_t bb0;
+ } bw;
+} uint16_t_uint8_t;
+
+typedef struct _DEVICE_INFO
+{
+ uint8_t bmRequestType; /* bmRequestType */
+ uint8_t bRequest; /* bRequest */
+ uint16_t_uint8_t wValues; /* wValue */
+ uint16_t_uint8_t wIndexs; /* wIndex */
+ uint16_t_uint8_t wLengths; /* wLength */
+
+ uint8_t CtrlState; /* of type USB_ControlState */
+ uint8_t CurrentFeature;
+ uint8_t CurrentConfiguration; /* Selected configuration */
+ uint8_t CurrentInterface; /* Selected interface of current configuration */
+ uint8_t CurrentAlternateSetting; /* Selected Alternate Setting of current
+ interface*/
+
+ USB_EndpointMess Ctrl_Info;
+} USB_DeviceMess;
+
+typedef struct _DEVICE_PROP
+{
+ void (*Init)(void); /* Initialize the device */
+ void (*Reset)(void); /* Reset routine of this device */
+
+ /* Device dependent process after the status stage */
+ void (*Process_Status_IN)(void);
+ void (*Process_Status_OUT)(void);
+
+ /* Procedure of process on setup stage of a class specified request with data stage */
+ /* All class specified requests with data stage are processed in Class_Data_Setup
+ Class_Data_Setup()
+ responses to check all special requests and fills USB_EndpointMess
+ according to the request
+ If IN tokens are expected, then wLength & wOffset will be filled
+ with the total transferring bytes and the starting position
+ If OUT tokens are expected, then rLength & rOffset will be filled
+ with the total expected bytes and the starting position in the buffer
+
+ If the request is valid, Class_Data_Setup returns SUCCESS, else UNSUPPORT
+
+ CAUTION:
+ Since GET_CONFIGURATION & GET_INTERFACE are highly related to
+ the individual classes, they will be checked and processed here.
+ */
+ USB_Result (*Class_Data_Setup)(uint8_t RequestNo);
+
+ /* Procedure of process on setup stage of a class specified request without data stage */
+ /* All class specified requests without data stage are processed in Class_NoData_Setup
+ Class_NoData_Setup
+ responses to check all special requests and perform the request
+
+ CAUTION:
+ Since SET_CONFIGURATION & SET_INTERFACE are highly related to
+ the individual classes, they will be checked and processed here.
+ */
+ USB_Result (*Class_NoData_Setup)(uint8_t RequestNo);
+
+ /*Class_Get_Interface_Setting
+ This function is used by the file usb_core.c to test if the selected Interface
+ and Alternate Setting (uint8_t Interface, uint8_t AlternateSetting) are supported by
+ the application.
+ This function is writing by user. It should return "SUCCESS" if the Interface
+ and Alternate Setting are supported by the application or "UNSUPPORT" if they
+ are not supported. */
+
+ USB_Result (*Class_Get_Interface_Setting)(uint8_t Interface, uint8_t AlternateSetting);
+
+ uint8_t* (*GetDeviceDescriptor)(uint16_t Length);
+ uint8_t* (*GetConfigDescriptor)(uint16_t Length);
+ uint8_t* (*GetStringDescriptor)(uint16_t Length);
+
+ /* This field is not used in current library version. It is kept only for
+ compatibility with previous versions */
+ void* RxEP_buffer;
+
+ uint8_t MaxPacketSize;
+
+} DEVICE_PROP;
+
+typedef struct _USER_STANDARD_REQUESTS
+{
+ void (*User_GetConfiguration)(void); /* Get Configuration */
+ void (*User_SetConfiguration)(void); /* Set Configuration */
+ void (*User_GetInterface)(void); /* Get Interface */
+ void (*User_SetInterface)(void); /* Set Interface */
+ void (*User_GetStatus)(void); /* Get Status */
+ void (*User_ClearFeature)(void); /* Clear Feature */
+ void (*User_SetEndPointFeature)(void); /* Set Endpoint Feature */
+ void (*User_SetDeviceFeature)(void); /* Set Device Feature */
+ void (*User_SetDeviceAddress)(void); /* Set Device Address */
+} USER_STANDARD_REQUESTS;
+
+#define Type_Recipient (pInformation->bmRequestType & (REQUEST_TYPE | RECIPIENT))
+
+#define Usb_rLength Usb_wLength
+#define Usb_rOffset Usb_wOffset
+
+#define USBwValue wValues.w
+#define USBwValue0 wValues.bw.bb0
+#define USBwValue1 wValues.bw.bb1
+#define USBwIndex wIndexs.w
+#define USBwIndex0 wIndexs.bw.bb0
+#define USBwIndex1 wIndexs.bw.bb1
+#define USBwLength wLengths.w
+#define USBwLength0 wLengths.bw.bb0
+#define USBwLength1 wLengths.bw.bb1
+
+uint8_t USB_ProcessSetup0(void);
+uint8_t USB_ProcessPost0(void);
+uint8_t USB_ProcessOut0(void);
+uint8_t USB_ProcessIn0(void);
+
+USB_Result Standard_SetEndPointFeature(void);
+USB_Result Standard_SetDeviceFeature(void);
+
+uint8_t* Standard_GetConfiguration(uint16_t Length);
+USB_Result Standard_SetConfiguration(void);
+uint8_t* Standard_GetInterface(uint16_t Length);
+USB_Result Standard_SetInterface(void);
+uint8_t* Standard_GetDescriptorData(uint16_t Length, PONE_DESCRIPTOR pDesc);
+
+uint8_t* Standard_GetStatus(uint16_t Length);
+USB_Result Standard_ClearFeature(void);
+void USB_SetDeviceAddress(uint8_t);
+void USB_ProcessNop(void);
+
+extern DEVICE_PROP Device_Property;
+extern USER_STANDARD_REQUESTS User_Standard_Requests;
+extern USB_Device Device_Table;
+extern USB_DeviceMess Device_Info;
+
+/* cells saving status during interrupt servicing */
+extern __IO uint16_t SaveRState;
+extern __IO uint16_t SaveTState;
+
+/**
+ * @}
+ */
+
+#endif /* __USB_CORE_H__ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_def.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_def.h
new file mode 100644
index 0000000000..8d61b5b72d
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_def.h
@@ -0,0 +1,98 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_def.h
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_DEF_H__
+#define __USB_DEF_H__
+
+/**
+ * @addtogroup N32WB452_USB_Driver
+ * @{
+ */
+
+typedef enum _RECIPIENT_TYPE
+{
+ DEVICE_RECIPIENT, /* Recipient device */
+ INTERFACE_RECIPIENT, /* Recipient interface */
+ ENDPOINT_RECIPIENT, /* Recipient endpoint */
+ OTHER_RECIPIENT
+} RECIPIENT_TYPE;
+
+typedef enum _STANDARD_REQUESTS
+{
+ GET_STATUS = 0,
+ CLR_FEATURE,
+ RESERVED1,
+ SET_FEATURE,
+ RESERVED2,
+ SET_ADDRESS,
+ GET_DESCRIPTOR,
+ SET_DESCRIPTOR,
+ GET_CONFIGURATION,
+ SET_CONFIGURATION,
+ GET_INTERFACE,
+ SET_INTERFACE,
+ TOTAL_SREQUEST, /* Total number of Standard request */
+ SYNCH_FRAME = 12
+} STANDARD_REQUESTS;
+
+/* Definition of "USBwValue" */
+typedef enum _DESCRIPTOR_TYPE
+{
+ DEVICE_DESCRIPTOR = 1,
+ CONFIG_DESCRIPTOR,
+ STRING_DESCRIPTOR,
+ INTERFACE_DESCRIPTOR,
+ ENDPOINT_DESCRIPTOR
+} DESCRIPTOR_TYPE;
+
+/* Feature selector of a SET_FEATURE or CLR_FEATURE */
+typedef enum _FEATURE_SELECTOR
+{
+ ENDPOINT_STALL,
+ DEVICE_REMOTE_WAKEUP
+} FEATURE_SELECTOR;
+
+/* Definition of "bmRequestType" */
+#define REQUEST_TYPE 0x60 /* Mask to get request type */
+#define STANDARD_REQUEST 0x00 /* Standard request */
+#define CLASS_REQUEST 0x20 /* Class request */
+#define VENDOR_REQUEST 0x40 /* Vendor request */
+
+#define RECIPIENT 0x1F /* Mask to get recipient */
+
+/**
+ * @}
+ */
+
+#endif /* __USB_DEF_H__ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_init.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_init.h
new file mode 100644
index 0000000000..90be64be98
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_init.h
@@ -0,0 +1,71 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_init.h
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_INIT_H__
+#define __USB_INIT_H__
+
+#include "n32wb452.h"
+#include "usb_core.h"
+
+/**
+ * @addtogroup N32WB452_USB_Driver
+ * @{
+ */
+
+void USB_Init(void);
+
+/* The number of current endpoint, it will be used to specify an endpoint */
+extern uint8_t EPindex;
+/* The number of current device, it is an index to the Device_Table */
+/*extern uint8_t Device_no; */
+/* Points to the USB_DeviceMess structure of current device */
+/* The purpose of this register is to speed up the execution */
+extern USB_DeviceMess* pInformation;
+/* Points to the DEVICE_PROP structure of current device */
+/* The purpose of this register is to speed up the execution */
+extern DEVICE_PROP* pProperty;
+/* Temporary save the state of Rx & Tx status. */
+/* Whenever the Rx or Tx state is changed, its value is saved */
+/* in this variable first and will be set to the EPRB or EPRA */
+/* at the end of interrupt process */
+extern USER_STANDARD_REQUESTS* pUser_Standard_Requests;
+
+extern uint16_t SaveState;
+extern uint16_t wInterrupt_Mask;
+
+/**
+ * @}
+ */
+
+#endif /* __USB_INIT_H__ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_int.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_int.h
new file mode 100644
index 0000000000..f6d70d3d59
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_int.h
@@ -0,0 +1,50 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_int.h
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_INT_H__
+#define __USB_INT_H__
+
+/**
+ * @addtogroup N32WB452_USB_Driver
+ * @{
+ */
+
+void USB_CorrectTransferLp(void);
+void USB_CorrectTransferHp(void);
+
+/**
+ * @}
+ */
+
+#endif /* __USB_INT_H__ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_lib.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_lib.h
new file mode 100644
index 0000000000..3bd907dcac
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_lib.h
@@ -0,0 +1,47 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_lib.h
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_LIB_H__
+#define __USB_LIB_H__
+
+#include "usb_type.h"
+#include "usb_regs.h"
+#include "usb_def.h"
+#include "usb_core.h"
+#include "usb_init.h"
+#include "usb_sil.h"
+#include "usb_mem.h"
+#include "usb_int.h"
+
+#endif /* __USB_LIB_H__ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_mem.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_mem.h
new file mode 100644
index 0000000000..f0ceea7713
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_mem.h
@@ -0,0 +1,52 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_mem.h
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_MEM_H__
+#define __USB_MEM_H__
+
+#include "n32wb452.h"
+
+/**
+ * @addtogroup N32WB452_USB_Driver
+ * @{
+ */
+
+void USB_CopyUserToPMABuf(uint8_t* pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+void USB_CopyPMAToUserBuf(uint8_t* pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+
+/**
+ * @}
+ */
+
+#endif /*__USB_MEM_H__*/
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_regs.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_regs.h
new file mode 100644
index 0000000000..e08790bf8c
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_regs.h
@@ -0,0 +1,715 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_regs.h
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_REGS_H__
+#define __USB_REGS_H__
+
+#include "n32wb452.h"
+
+/**
+ * @addtogroup N32WB452_USB_Driver
+ * @{
+ */
+
+typedef enum _EP_DBUF_DIR
+{
+ /* double buffered endpoint direction */
+ EP_DBUF_ERR,
+ EP_DBUF_OUT,
+ EP_DBUF_IN
+} EP_DBUF_DIR;
+
+/* endpoint buffer number */
+enum EP_BUF_NUM
+{
+ EP_NOBUF,
+ EP_BUF0,
+ EP_BUF1
+};
+
+#define RegBase (0x40005C00L) /* USB_IP Peripheral Registers base address */
+#define PMAAddr (0x40006000L) /* USB_IP Packet Memory Area base address */
+
+/******************************************************************************/
+/* Special registers */
+/******************************************************************************/
+/* Pull up controller register */
+#define DP_CTRL ((__IO unsigned*)(0x40001820))
+
+#define _EnPortPullup() (*DP_CTRL = (*DP_CTRL) | 0x10000000);
+#define _DisPortPullup() (*DP_CTRL = (*DP_CTRL) & 0xEFFFFFFF);
+
+/******************************************************************************/
+/* General registers */
+/******************************************************************************/
+
+/* Control register */
+#define USB_CTRL ((__IO unsigned*)(RegBase + 0x40))
+/* Interrupt status register */
+#define USB_STS ((__IO unsigned*)(RegBase + 0x44))
+/* Frame number register */
+#define USB_FN ((__IO unsigned*)(RegBase + 0x48))
+/* Device address register */
+#define USB_ADDR ((__IO unsigned*)(RegBase + 0x4C))
+/* Buffer Table address register */
+#define USB_BUFTAB ((__IO unsigned*)(RegBase + 0x50))
+/******************************************************************************/
+/* Endpoint registers */
+/******************************************************************************/
+#define EP0REG ((__IO unsigned*)(RegBase)) /* endpoint 0 register address */
+
+/* Endpoint Addresses (w/direction) */
+#define EP0_OUT ((uint8_t)0x00)
+#define EP0_IN ((uint8_t)0x80)
+#define EP1_OUT ((uint8_t)0x01)
+#define EP1_IN ((uint8_t)0x81)
+#define EP2_OUT ((uint8_t)0x02)
+#define EP2_IN ((uint8_t)0x82)
+#define EP3_OUT ((uint8_t)0x03)
+#define EP3_IN ((uint8_t)0x83)
+#define EP4_OUT ((uint8_t)0x04)
+#define EP4_IN ((uint8_t)0x84)
+#define EP5_OUT ((uint8_t)0x05)
+#define EP5_IN ((uint8_t)0x85)
+#define EP6_OUT ((uint8_t)0x06)
+#define EP6_IN ((uint8_t)0x86)
+#define EP7_OUT ((uint8_t)0x07)
+#define EP7_IN ((uint8_t)0x87)
+
+/* endpoints enumeration */
+#define ENDP0 ((uint8_t)0)
+#define ENDP1 ((uint8_t)1)
+#define ENDP2 ((uint8_t)2)
+#define ENDP3 ((uint8_t)3)
+#define ENDP4 ((uint8_t)4)
+#define ENDP5 ((uint8_t)5)
+#define ENDP6 ((uint8_t)6)
+#define ENDP7 ((uint8_t)7)
+
+/******************************************************************************/
+/* USB_STS interrupt events */
+/******************************************************************************/
+#define STS_CTRS (0x8000) /* Correct TRansfer (clear-only bit) */
+#define STS_DOVR (0x4000) /* DMA OVeR/underrun (clear-only bit) */
+#define STS_ERROR (0x2000) /* ERRor (clear-only bit) */
+#define STS_WKUP (0x1000) /* WaKe UP (clear-only bit) */
+#define STS_SUSPD (0x0800) /* SUSPend (clear-only bit) */
+#define STS_RST (0x0400) /* RESET (clear-only bit) */
+#define STS_SOF (0x0200) /* Start Of Frame (clear-only bit) */
+#define STS_ESOF (0x0100) /* Expected Start Of Frame (clear-only bit) */
+
+#define STS_DIR (0x0010) /* DIRection of transaction (read-only bit) */
+#define STS_EP_ID (0x000F) /* EndPoint IDentifier (read-only bit) */
+
+#define CLR_CTRS (~STS_CTRS) /* clear Correct TRansfer bit */
+#define CLR_DOVR (~STS_DOVR) /* clear DMA OVeR/underrun bit*/
+#define CLR_ERROR (~STS_ERROR) /* clear ERRor bit */
+#define CLR_WKUP (~STS_WKUP) /* clear WaKe UP bit */
+#define CLR_SUSPD (~STS_SUSPD) /* clear SUSPend bit */
+#define CLR_RST (~STS_RST) /* clear RESET bit */
+#define CLR_SOF (~STS_SOF) /* clear Start Of Frame bit */
+#define CLR_ESOF (~STS_ESOF) /* clear Expected Start Of Frame bit */
+
+/******************************************************************************/
+/* USB_CTRL control register bits definitions */
+/******************************************************************************/
+#define CTRL_CTRSM (0x8000) /* Correct TRansfer Mask */
+#define CTRL_DOVRM (0x4000) /* DMA OVeR/underrun Mask */
+#define CTRL_ERRORM (0x2000) /* ERRor Mask */
+#define CTRL_WKUPM (0x1000) /* WaKe UP Mask */
+#define CTRL_SUSPDM (0x0800) /* SUSPend Mask */
+#define CTRL_RSTM (0x0400) /* RESET Mask */
+#define CTRL_SOFM (0x0200) /* Start Of Frame Mask */
+#define CTRL_ESOFM (0x0100) /* Expected Start Of Frame Mask */
+
+#define CTRL_RESUM (0x0010) /* RESUME request */
+#define CTRL_FSUSPD (0x0008) /* Force SUSPend */
+#define CTRL_LP_MODE (0x0004) /* Low-power MODE */
+#define CTRL_PD (0x0002) /* Power DoWN */
+#define CTRL_FRST (0x0001) /* Force USB RESet */
+
+/******************************************************************************/
+/* USB_FN Frame Number Register bit definitions */
+/******************************************************************************/
+#define FN_RXDP (0x8000) /* status of D+ data line */
+#define FN_RXDM (0x4000) /* status of D- data line */
+#define FN_LCK (0x2000) /* LoCKed */
+#define FN_LSOF (0x1800) /* Lost SOF */
+#define FN_FNUM (0x07FF) /* Frame Number */
+/******************************************************************************/
+/* USB_ADDR Device ADDRess bit definitions */
+/******************************************************************************/
+#define ADDR_EFUC (0x80)
+#define ADDR_ADDR (0x7F)
+/******************************************************************************/
+/* Endpoint register */
+/******************************************************************************/
+/* bit positions */
+#define EP_CTRS_RX (0x8000) /* EndPoint Correct TRansfer RX */
+#define EP_DATTOG_RX (0x4000) /* EndPoint Data TOGGLE RX */
+#define EPRX_STS (0x3000) /* EndPoint RX STATus bit field */
+#define EP_SETUP (0x0800) /* EndPoint SETUP */
+#define EP_T_FIELD (0x0600) /* EndPoint TYPE */
+#define EP_KIND (0x0100) /* EndPoint KIND */
+#define EP_CTRS_TX (0x0080) /* EndPoint Correct TRansfer TX */
+#define EP_DATTOG_TX (0x0040) /* EndPoint Data TOGGLE TX */
+#define EPTX_STS (0x0030) /* EndPoint TX STATus bit field */
+#define EPADDR_FIELD (0x000F) /* EndPoint ADDRess FIELD */
+
+/* EndPoint REGister INTEN (no toggle fields) */
+#define EPREG_MASK (EP_CTRS_RX | EP_SETUP | EP_T_FIELD | EP_KIND | EP_CTRS_TX | EPADDR_FIELD)
+
+/* EP_TYPE[1:0] EndPoint TYPE */
+#define EP_TYPE_MASK (0x0600) /* EndPoint TYPE Mask */
+#define EP_BULK (0x0000) /* EndPoint BULK */
+#define EP_CONTROL (0x0200) /* EndPoint CONTROL */
+#define EP_ISOCHRONOUS (0x0400) /* EndPoint ISOCHRONOUS */
+#define EP_INTERRUPT (0x0600) /* EndPoint INTERRUPT */
+#define EP_T_MASK (~EP_T_FIELD & EPREG_MASK)
+
+/* EP_KIND EndPoint KIND */
+#define EPKIND_MASK (~EP_KIND & EPREG_MASK)
+
+/* STAT_TX[1:0] STATus for TX transfer */
+#define EP_TX_DIS (0x0000) /* EndPoint TX DISabled */
+#define EP_TX_STALL (0x0010) /* EndPoint TX STALLed */
+#define EP_TX_NAK (0x0020) /* EndPoint TX NAKed */
+#define EP_TX_VALID (0x0030) /* EndPoint TX VALID */
+#define EPTX_DATTOG1 (0x0010) /* EndPoint TX Data TOGgle bit1 */
+#define EPTX_DATTOG2 (0x0020) /* EndPoint TX Data TOGgle bit2 */
+#define EPTX_DATTOGMASK (EPTX_STS | EPREG_MASK)
+
+/* STAT_RX[1:0] STATus for RX transfer */
+#define EP_RX_DIS (0x0000) /* EndPoint RX DISabled */
+#define EP_RX_STALL (0x1000) /* EndPoint RX STALLed */
+#define EP_RX_NAK (0x2000) /* EndPoint RX NAKed */
+#define EP_RX_VALID (0x3000) /* EndPoint RX VALID */
+#define EPRX_DATTOG1 (0x1000) /* EndPoint RX Data TOGgle bit1 */
+#define EPRX_DATTOG2 (0x2000) /* EndPoint RX Data TOGgle bit1 */
+#define EPRX_DATTOGMASK (EPRX_STS | EPREG_MASK)
+
+/* USB_SetCtrl */
+#define _SetCNTR(wRegValue) (*USB_CTRL = (uint16_t)wRegValue)
+
+/* USB_SetSts */
+#define _SetISTR(wRegValue) (*USB_STS = (uint16_t)wRegValue)
+
+/* USB_SetAddr */
+#define _SetDADDR(wRegValue) (*USB_ADDR = (uint16_t)wRegValue)
+
+/* USB_SetBuftab */
+#define _SetBTABLE(wRegValue) (*USB_BUFTAB = (uint16_t)(wRegValue & 0xFFF8))
+
+/* USB_GetCtrl */
+#define _GetCNTR() ((uint16_t)*USB_CTRL)
+
+/* USB_GetSts */
+#define _GetISTR() ((uint16_t)*USB_STS)
+
+/* USB_GetFn */
+#define _GetFNR() ((uint16_t)*USB_FN)
+
+/* USB_GetAddr */
+#define _GetDADDR() ((uint16_t)*USB_ADDR)
+
+/* USB_GetBTABLE */
+#define _GetBTABLE() ((uint16_t)*USB_BUFTAB)
+
+/* USB_SetEndPoint */
+#define _SetENDPOINT(bEpNum, wRegValue) (*(EP0REG + bEpNum) = (uint16_t)wRegValue)
+
+/* USB_GetEndPoint */
+#define _GetENDPOINT(bEpNum) ((uint16_t)(*(EP0REG + bEpNum)))
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpType
+ * Description : sets the type in the endpoint register(bits EP_TYPE[1:0])
+ * Input : bEpNum: Endpoint Number.
+ * wType
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPType(bEpNum, wType) (_SetENDPOINT(bEpNum, ((_GetENDPOINT(bEpNum) & EP_T_MASK) | wType)))
+
+/*******************************************************************************
+ * Macro Name : USB_GetEpType
+ * Description : gets the type in the endpoint register(bits EP_TYPE[1:0])
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : Endpoint Type
+ *******************************************************************************/
+#define _GetEPType(bEpNum) (_GetENDPOINT(bEpNum) & EP_T_FIELD)
+
+/*******************************************************************************
+ * Macro Name : SetEPTxStatus
+ * Description : sets the status for tx transfer (bits STAT_TX[1:0]).
+ * Input : bEpNum: Endpoint Number.
+ * wState: new state
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPTxStatus(bEpNum, wState) \
+ { \
+ register uint16_t _wRegVal; \
+ _wRegVal = _GetENDPOINT(bEpNum) & EPTX_DATTOGMASK; \
+ /* toggle first bit ? */ \
+ if ((EPTX_DATTOG1 & wState) != 0) \
+ _wRegVal ^= EPTX_DATTOG1; \
+ /* toggle second bit ? */ \
+ if ((EPTX_DATTOG2 & wState) != 0) \
+ _wRegVal ^= EPTX_DATTOG2; \
+ _SetENDPOINT(bEpNum, (_wRegVal | EP_CTRS_RX | EP_CTRS_TX)); \
+ } /* _SetEPTxStatus */
+
+/*******************************************************************************
+ * Macro Name : SetEPRxStatus
+ * Description : sets the status for rx transfer (bits STAT_TX[1:0])
+ * Input : bEpNum: Endpoint Number.
+ * wState: new state.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPRxStatus(bEpNum, wState) \
+ { \
+ register uint16_t _wRegVal; \
+ \
+ _wRegVal = _GetENDPOINT(bEpNum) & EPRX_DATTOGMASK; \
+ /* toggle first bit ? */ \
+ if ((EPRX_DATTOG1 & wState) != 0) \
+ _wRegVal ^= EPRX_DATTOG1; \
+ /* toggle second bit ? */ \
+ if ((EPRX_DATTOG2 & wState) != 0) \
+ _wRegVal ^= EPRX_DATTOG2; \
+ _SetENDPOINT(bEpNum, (_wRegVal | EP_CTRS_RX | EP_CTRS_TX)); \
+ } /* _SetEPRxStatus */
+
+/*******************************************************************************
+ * Macro Name : SetEPRxTxStatus
+ * Description : sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
+ * Input : bEpNum: Endpoint Number.
+ * wStaterx: new state.
+ * wStatetx: new state.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPRxTxStatus(bEpNum, wStaterx, wStatetx) \
+ { \
+ register uint32_t _wRegVal; \
+ \
+ _wRegVal = _GetENDPOINT(bEpNum) & (EPRX_DATTOGMASK | EPTX_STS); \
+ /* toggle first bit ? */ \
+ if ((EPRX_DATTOG1 & wStaterx) != 0) \
+ _wRegVal ^= EPRX_DATTOG1; \
+ /* toggle second bit ? */ \
+ if ((EPRX_DATTOG2 & wStaterx) != 0) \
+ _wRegVal ^= EPRX_DATTOG2; \
+ /* toggle first bit ? */ \
+ if ((EPTX_DATTOG1 & wStatetx) != 0) \
+ _wRegVal ^= EPTX_DATTOG1; \
+ /* toggle second bit ? */ \
+ if ((EPTX_DATTOG2 & wStatetx) != 0) \
+ _wRegVal ^= EPTX_DATTOG2; \
+ _SetENDPOINT(bEpNum, _wRegVal | EP_CTRS_RX | EP_CTRS_TX); \
+ } /* _SetEPRxTxStatus */
+/*******************************************************************************
+ * Macro Name : USB_GetEpTxSts / USB_GetEpRxSts
+ * Description : gets the status for tx/rx transfer (bits STAT_TX[1:0]
+ * /STAT_RX[1:0])
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : status .
+ *******************************************************************************/
+#define _GetEPTxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EPTX_STS)
+
+#define _GetEPRxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EPRX_STS)
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpTxValid / USB_SetEpRxValid
+ * Description : sets directly the VALID tx/rx-status into the enpoint register
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPTxValid(bEpNum) (_SetEPTxStatus(bEpNum, EP_TX_VALID))
+
+#define _SetEPRxValid(bEpNum) (_SetEPRxStatus(bEpNum, EP_RX_VALID))
+
+/*******************************************************************************
+ * Macro Name : USB_GetTxStallSts / USB_GetRxStallSts.
+ * Description : checks stall condition in an endpoint.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : TRUE = endpoint in stall condition.
+ *******************************************************************************/
+#define _GetTxStallStatus(bEpNum) (_GetEPTxStatus(bEpNum) == EP_TX_STALL)
+#define _GetRxStallStatus(bEpNum) (_GetEPRxStatus(bEpNum) == EP_RX_STALL)
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpKind / USB_ClrEpKind.
+ * Description : set & clear EP_KIND bit.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEP_KIND(bEpNum) \
+ (_SetENDPOINT(bEpNum, (EP_CTRS_RX | EP_CTRS_TX | ((_GetENDPOINT(bEpNum) | EP_KIND) & EPREG_MASK))))
+#define _ClearEP_KIND(bEpNum) (_SetENDPOINT(bEpNum, (EP_CTRS_RX | EP_CTRS_TX | (_GetENDPOINT(bEpNum) & EPKIND_MASK))))
+
+/*******************************************************************************
+ * Macro Name : USB_SetStsOut / USB_ClrStsOut.
+ * Description : Sets/clears directly STATUS_OUT bit in the endpoint register.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _Set_Status_Out(bEpNum) _SetEP_KIND(bEpNum)
+#define _Clear_Status_Out(bEpNum) _ClearEP_KIND(bEpNum)
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpDoubleBufer / USB_ClrEpDoubleBufer.
+ * Description : Sets/clears directly EP_KIND bit in the endpoint register.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPDoubleBuff(bEpNum) _SetEP_KIND(bEpNum)
+#define _ClearEPDoubleBuff(bEpNum) _ClearEP_KIND(bEpNum)
+
+/*******************************************************************************
+ * Macro Name : USB_ClrEpCtrsRx / USB_ClrEpCtrsTx.
+ * Description : Clears bit CTR_RX / CTR_TX in the endpoint register.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _ClearEP_CTR_RX(bEpNum) (_SetENDPOINT(bEpNum, _GetENDPOINT(bEpNum) & 0x7FFF & EPREG_MASK))
+#define _ClearEP_CTR_TX(bEpNum) (_SetENDPOINT(bEpNum, _GetENDPOINT(bEpNum) & 0xFF7F & EPREG_MASK))
+
+/*******************************************************************************
+ * Macro Name : USB_DattogRx / USB_DattogTx .
+ * Description : Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _ToggleDTOG_RX(bEpNum) \
+ (_SetENDPOINT(bEpNum, EP_CTRS_RX | EP_CTRS_TX | EP_DATTOG_RX | (_GetENDPOINT(bEpNum) & EPREG_MASK)))
+#define _ToggleDTOG_TX(bEpNum) \
+ (_SetENDPOINT(bEpNum, EP_CTRS_RX | EP_CTRS_TX | EP_DATTOG_TX | (_GetENDPOINT(bEpNum) & EPREG_MASK)))
+
+/*******************************************************************************
+ * Macro Name : USB_ClrDattogRx / USB_ClrDattogTx.
+ * Description : Clears DTOG_RX / DTOG_TX bit in the endpoint register.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _ClearDTOG_RX(bEpNum) \
+ if ((_GetENDPOINT(bEpNum) & EP_DATTOG_RX) != 0) \
+ _ToggleDTOG_RX(bEpNum)
+#define _ClearDTOG_TX(bEpNum) \
+ if ((_GetENDPOINT(bEpNum) & EP_DATTOG_TX) != 0) \
+ _ToggleDTOG_TX(bEpNum)
+/*******************************************************************************
+ * Macro Name : USB_SetEpAddress.
+ * Description : Sets address in an endpoint register.
+ * Input : bEpNum: Endpoint Number.
+ * bAddr: Address.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPAddress(bEpNum, bAddr) \
+ _SetENDPOINT(bEpNum, EP_CTRS_RX | EP_CTRS_TX | (_GetENDPOINT(bEpNum) & EPREG_MASK) | bAddr)
+
+/*******************************************************************************
+ * Macro Name : USB_GetEpAddress.
+ * Description : Gets address in an endpoint register.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _GetEPAddress(bEpNum) ((uint8_t)(_GetENDPOINT(bEpNum) & EPADDR_FIELD))
+
+#define _pEPTxAddr(bEpNum) ((uint32_t*)((_GetBTABLE() + bEpNum * 8) * 2 + PMAAddr))
+#define _pEPTxCount(bEpNum) ((uint32_t*)((_GetBTABLE() + bEpNum * 8 + 2) * 2 + PMAAddr))
+#define _pEPRxAddr(bEpNum) ((uint32_t*)((_GetBTABLE() + bEpNum * 8 + 4) * 2 + PMAAddr))
+#define _pEPRxCount(bEpNum) ((uint32_t*)((_GetBTABLE() + bEpNum * 8 + 6) * 2 + PMAAddr))
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpTxAddr / USB_SetEpRxAddr.
+ * Description : sets address of the tx/rx buffer.
+ * Input : bEpNum: Endpoint Number.
+ * wAddr: address to be set (must be word aligned).
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPTxAddr(bEpNum, wAddr) (*_pEPTxAddr(bEpNum) = ((wAddr >> 1) << 1))
+#define _SetEPRxAddr(bEpNum, wAddr) (*_pEPRxAddr(bEpNum) = ((wAddr >> 1) << 1))
+
+/*******************************************************************************
+ * Macro Name : USB_GetEpTxAddr / USB_GetEpRxAddr.
+ * Description : Gets address of the tx/rx buffer.
+ * Input : bEpNum: Endpoint Number.
+ * Output : None.
+ * Return : address of the buffer.
+ *******************************************************************************/
+#define _GetEPTxAddr(bEpNum) ((uint16_t)*_pEPTxAddr(bEpNum))
+#define _GetEPRxAddr(bEpNum) ((uint16_t)*_pEPRxAddr(bEpNum))
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpCntRxReg.
+ * Description : Sets counter of rx buffer with no. of blocks.
+ * Input : pdwReg: pointer to counter.
+ * wCount: Counter.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _BlocksOf32(dwReg, wCount, wNBlocks) \
+ { \
+ wNBlocks = wCount >> 5; \
+ if ((wCount & 0x1f) == 0) \
+ wNBlocks--; \
+ *pdwReg = (uint32_t)((wNBlocks << 10) | 0x8000); \
+ } /* _BlocksOf32 */
+
+#define _BlocksOf2(dwReg, wCount, wNBlocks) \
+ { \
+ wNBlocks = wCount >> 1; \
+ if ((wCount & 0x1) != 0) \
+ wNBlocks++; \
+ *pdwReg = (uint32_t)(wNBlocks << 10); \
+ } /* _BlocksOf2 */
+
+#define _SetEPCountRxReg(dwReg, wCount) \
+ { \
+ uint16_t wNBlocks; \
+ if (wCount > 62) \
+ { \
+ _BlocksOf32(dwReg, wCount, wNBlocks); \
+ } \
+ else \
+ { \
+ _BlocksOf2(dwReg, wCount, wNBlocks); \
+ } \
+ } /* _SetEPCountRxReg */
+
+#define _SetEPRxDblBuf0Count(bEpNum, wCount) \
+ { \
+ uint32_t* pdwReg = _pEPTxCount(bEpNum); \
+ _SetEPCountRxReg(pdwReg, wCount); \
+ }
+/*******************************************************************************
+ * Macro Name : USB_SetEpTxCnt / USB_SetEpRxCnt.
+ * Description : sets counter for the tx/rx buffer.
+ * Input : bEpNum: endpoint number.
+ * wCount: Counter value.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPTxCount(bEpNum, wCount) (*_pEPTxCount(bEpNum) = wCount)
+#define _SetEPRxCount(bEpNum, wCount) \
+ { \
+ uint32_t* pdwReg = _pEPRxCount(bEpNum); \
+ _SetEPCountRxReg(pdwReg, wCount); \
+ }
+/*******************************************************************************
+ * Macro Name : USB_GetEpTxCnt / USB_GetEpRxCnt.
+ * Description : gets counter of the tx buffer.
+ * Input : bEpNum: endpoint number.
+ * Output : None.
+ * Return : Counter value.
+ *******************************************************************************/
+#define _GetEPTxCount(bEpNum) ((uint16_t)(*_pEPTxCount(bEpNum)) & 0x3ff)
+#define _GetEPRxCount(bEpNum) ((uint16_t)(*_pEPRxCount(bEpNum)) & 0x3ff)
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpDblBuf0Addr / USB_SetEpDblBuf1Addr.
+ * Description : Sets buffer 0/1 address in a double buffer endpoint.
+ * Input : bEpNum: endpoint number.
+ * : wBuf0Addr: buffer 0 address.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPDblBuf0Addr(bEpNum, wBuf0Addr) \
+ { \
+ _SetEPTxAddr(bEpNum, wBuf0Addr); \
+ }
+#define _SetEPDblBuf1Addr(bEpNum, wBuf1Addr) \
+ { \
+ _SetEPRxAddr(bEpNum, wBuf1Addr); \
+ }
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpDblBuferAddr.
+ * Description : Sets addresses in a double buffer endpoint.
+ * Input : bEpNum: endpoint number.
+ * : wBuf0Addr: buffer 0 address.
+ * : wBuf1Addr = buffer 1 address.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPDblBuffAddr(bEpNum, wBuf0Addr, wBuf1Addr) \
+ { \
+ _SetEPDblBuf0Addr(bEpNum, wBuf0Addr); \
+ _SetEPDblBuf1Addr(bEpNum, wBuf1Addr); \
+ } /* _SetEPDblBuffAddr */
+
+/*******************************************************************************
+ * Macro Name : USB_GetEpDblBuf0Addr / USB_GetEpDblBuf1Addr.
+ * Description : Gets buffer 0/1 address of a double buffer endpoint.
+ * Input : bEpNum: endpoint number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _GetEPDblBuf0Addr(bEpNum) (_GetEPTxAddr(bEpNum))
+#define _GetEPDblBuf1Addr(bEpNum) (_GetEPRxAddr(bEpNum))
+
+/*******************************************************************************
+ * Macro Name : USB_SetEpDblBuferCnt / USB_SetEpDblBuf0Cnt / USB_SetEpDblBuf1Cnt.
+ * Description : Gets buffer 0/1 address of a double buffer endpoint.
+ * Input : bEpNum: endpoint number.
+ * : bDir: endpoint dir EP_DBUF_OUT = OUT
+ * EP_DBUF_IN = IN
+ * : wCount: Counter value
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _SetEPDblBuf0Count(bEpNum, bDir, wCount) \
+ { \
+ if (bDir == EP_DBUF_OUT) \
+ /* OUT endpoint */ \
+ { \
+ _SetEPRxDblBuf0Count(bEpNum, wCount); \
+ } \
+ else if (bDir == EP_DBUF_IN) \
+ /* IN endpoint */ \
+ *_pEPTxCount(bEpNum) = (uint32_t)wCount; \
+ } /* USB_SetEpDblBuf0Cnt*/
+
+#define _SetEPDblBuf1Count(bEpNum, bDir, wCount) \
+ { \
+ if (bDir == EP_DBUF_OUT) \
+ /* OUT endpoint */ \
+ { \
+ _SetEPRxCount(bEpNum, wCount); \
+ } \
+ else if (bDir == EP_DBUF_IN) \
+ /* IN endpoint */ \
+ *_pEPRxCount(bEpNum) = (uint32_t)wCount; \
+ } /* USB_SetEpDblBuf1Cnt */
+
+#define _SetEPDblBuffCount(bEpNum, bDir, wCount) \
+ { \
+ _SetEPDblBuf0Count(bEpNum, bDir, wCount); \
+ _SetEPDblBuf1Count(bEpNum, bDir, wCount); \
+ } /* _SetEPDblBuffCount */
+
+/*******************************************************************************
+ * Macro Name : USB_GetEpDblBuf0Cnt / USB_GetEpDblBuf1Cnt.
+ * Description : Gets buffer 0/1 rx/tx counter for double buffering.
+ * Input : bEpNum: endpoint number.
+ * Output : None.
+ * Return : None.
+ *******************************************************************************/
+#define _GetEPDblBuf0Count(bEpNum) (_GetEPTxCount(bEpNum))
+#define _GetEPDblBuf1Count(bEpNum) (_GetEPRxCount(bEpNum))
+
+extern __IO uint16_t wIstr; /* USB_STS register last read value */
+
+void USB_SetCtrl(uint16_t /*wRegValue*/);
+void USB_SetSts(uint16_t /*wRegValue*/);
+void USB_SetAddr(uint16_t /*wRegValue*/);
+void USB_SetBuftab(uint16_t /*wRegValue*/);
+void USB_SetBuftab(uint16_t /*wRegValue*/);
+uint16_t USB_GetCtrl(void);
+uint16_t USB_GetSts(void);
+uint16_t USB_GetFn(void);
+uint16_t USB_GetAddr(void);
+uint16_t USB_GetBTABLE(void);
+void USB_SetEndPoint(uint8_t /*bEpNum*/, uint16_t /*wRegValue*/);
+uint16_t USB_GetEndPoint(uint8_t /*bEpNum*/);
+void USB_SetEpType(uint8_t /*bEpNum*/, uint16_t /*wType*/);
+uint16_t USB_GetEpType(uint8_t /*bEpNum*/);
+void SetEPTxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/);
+void SetEPRxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/);
+void USB_SetDouBleBuferEpStall(uint8_t /*bEpNum*/, uint8_t bDir);
+uint16_t USB_GetEpTxSts(uint8_t /*bEpNum*/);
+uint16_t USB_GetEpRxSts(uint8_t /*bEpNum*/);
+void USB_SetEpTxValid(uint8_t /*bEpNum*/);
+void USB_SetEpRxValid(uint8_t /*bEpNum*/);
+uint16_t USB_GetTxStallSts(uint8_t /*bEpNum*/);
+uint16_t USB_GetRxStallSts(uint8_t /*bEpNum*/);
+void USB_SetEpKind(uint8_t /*bEpNum*/);
+void USB_ClrEpKind(uint8_t /*bEpNum*/);
+void USB_SetStsOut(uint8_t /*bEpNum*/);
+void USB_ClrStsOut(uint8_t /*bEpNum*/);
+void USB_SetEpDoubleBufer(uint8_t /*bEpNum*/);
+void USB_ClrEpDoubleBufer(uint8_t /*bEpNum*/);
+void USB_ClrEpCtrsRx(uint8_t /*bEpNum*/);
+void USB_ClrEpCtrsTx(uint8_t /*bEpNum*/);
+void USB_DattogRx(uint8_t /*bEpNum*/);
+void USB_DattogTx(uint8_t /*bEpNum*/);
+void USB_ClrDattogRx(uint8_t /*bEpNum*/);
+void USB_ClrDattogTx(uint8_t /*bEpNum*/);
+void USB_SetEpAddress(uint8_t /*bEpNum*/, uint8_t /*bAddr*/);
+uint8_t USB_GetEpAddress(uint8_t /*bEpNum*/);
+void USB_SetEpTxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/);
+void USB_SetEpRxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/);
+uint16_t USB_GetEpTxAddr(uint8_t /*bEpNum*/);
+uint16_t USB_GetEpRxAddr(uint8_t /*bEpNum*/);
+void USB_SetEpCntRxReg(uint32_t* /*pdwReg*/, uint16_t /*wCount*/);
+void USB_SetEpTxCnt(uint8_t /*bEpNum*/, uint16_t /*wCount*/);
+void USB_SetEpRxCnt(uint8_t /*bEpNum*/, uint16_t /*wCount*/);
+uint16_t USB_GetEpTxCnt(uint8_t /*bEpNum*/);
+uint16_t USB_GetEpRxCnt(uint8_t /*bEpNum*/);
+void USB_SetEpDblBuf0Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/);
+void USB_SetEpDblBuf1Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf1Addr*/);
+void USB_SetEpDblBuferAddr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/, uint16_t /*wBuf1Addr*/);
+uint16_t USB_GetEpDblBuf0Addr(uint8_t /*bEpNum*/);
+uint16_t USB_GetEpDblBuf1Addr(uint8_t /*bEpNum*/);
+void USB_SetEpDblBuferCnt(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
+void USB_SetEpDblBuf0Cnt(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
+void USB_SetEpDblBuf1Cnt(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
+uint16_t USB_GetEpDblBuf0Cnt(uint8_t /*bEpNum*/);
+uint16_t USB_GetEpDblBuf1Cnt(uint8_t /*bEpNum*/);
+EP_DBUF_DIR GetEPDblBufDir(uint8_t /*bEpNum*/);
+void USB_FreeUserBuf(uint8_t bEpNum /*bEpNum*/, uint8_t bDir);
+uint16_t USB_ToWord(uint8_t, uint8_t);
+uint16_t USB_ByteSwap(uint16_t);
+
+/**
+ * @}
+ */
+
+#endif /* __USB_REGS_H__ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_sil.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_sil.h
new file mode 100644
index 0000000000..f457b4554b
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_sil.h
@@ -0,0 +1,53 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_sil.h
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_SIL_H__
+#define __USB_SIL_H__
+
+#include "n32wb452.h"
+
+/**
+ * @addtogroup N32WB452_USB_Driver
+ * @{
+ */
+
+uint32_t USB_SilInit(void);
+uint32_t USB_SilWrite(uint8_t bEpAddr, uint8_t* pBufferPointer, uint32_t wBufferSize);
+uint32_t USB_SilRead(uint8_t bEpAddr, uint8_t* pBufferPointer);
+
+/**
+ * @}
+ */
+
+#endif /* __USB_SIL_H__ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_type.h b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_type.h
new file mode 100644
index 0000000000..9ab0db6989
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_type.h
@@ -0,0 +1,54 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_type.h
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_TYPE_H__
+#define __USB_TYPE_H__
+
+#include "usb_conf.h"
+#include
+
+/**
+ * @addtogroup N32WB452_USB_Driver
+ * @{
+ */
+
+#ifndef NULL
+#define NULL ((void*)0)
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* __USB_TYPE_H__ */
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_core.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_core.c
new file mode 100644
index 0000000000..ee7f4e74ca
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_core.c
@@ -0,0 +1,950 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_core.c
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "usb_lib.h"
+
+#define ValBit(VAR, Place) (VAR & (1 << Place))
+#define SetBit(VAR, Place) (VAR |= (1 << Place))
+#define ClrBit(VAR, Place) (VAR &= ((1 << Place) ^ 255))
+
+#define Send0LengthData() \
+ { \
+ _SetEPTxCount(ENDP0, 0); \
+ vSetEPTxStatus(EP_TX_VALID); \
+ }
+
+#define vSetEPRxStatus(st) (SaveRState = st)
+#define vSetEPTxStatus(st) (SaveTState = st)
+
+#define USB_StatusIn() Send0LengthData()
+#define USB_StatusOut() vSetEPRxStatus(EP_RX_VALID)
+
+#define StatusInfo0 StatusInfo.bw.bb1 /* Reverse bb0 & bb1 */
+#define StatusInfo1 StatusInfo.bw.bb0
+
+uint16_t_uint8_t StatusInfo;
+
+bool Data_Mul_MaxPacketSize = false;
+
+static void DataStageOut(void);
+static void DataStageIn(void);
+static void NoData_Setup0(void);
+static void Data_Setup0(void);
+
+/**
+ * @brief Return the current configuration variable address.
+ * Input : Length - How many bytes are needed.
+ * @return Return 1 , if the request is invalid when "Length" is 0.
+ * Return "Buffer" if the "Length" is not 0.
+ */
+uint8_t* Standard_GetConfiguration(uint16_t Length)
+{
+ if (Length == 0)
+ {
+ pInformation->Ctrl_Info.Usb_wLength = sizeof(pInformation->CurrentConfiguration);
+ return 0;
+ }
+ pUser_Standard_Requests->User_GetConfiguration();
+ return (uint8_t*)&pInformation->CurrentConfiguration;
+}
+
+/**
+ * @brief This routine is called to set the configuration value
+ * Then each class should configure device itself.
+ * @return
+ * - Success, if the request is performed.
+ * - UnSupport, if the request is invalid.
+ */
+USB_Result Standard_SetConfiguration(void)
+{
+ if ((pInformation->USBwValue0 <= Device_Table.TotalConfiguration) && (pInformation->USBwValue1 == 0)
+ && (pInformation->USBwIndex == 0)) /*call Back usb spec 2.0*/
+ {
+ pInformation->CurrentConfiguration = pInformation->USBwValue0;
+ pUser_Standard_Requests->User_SetConfiguration();
+ return Success;
+ }
+ else
+ {
+ return UnSupport;
+ }
+}
+
+/**
+ * @brief Return the Alternate Setting of the current interface.
+ * Input : Length - How many bytes are needed.
+ * @return
+ * - NULL, if the request is invalid when "Length" is 0.
+ * - "Buffer" if the "Length" is not 0.
+ */
+uint8_t* Standard_GetInterface(uint16_t Length)
+{
+ if (Length == 0)
+ {
+ pInformation->Ctrl_Info.Usb_wLength = sizeof(pInformation->CurrentAlternateSetting);
+ return 0;
+ }
+ pUser_Standard_Requests->User_GetInterface();
+ return (uint8_t*)&pInformation->CurrentAlternateSetting;
+}
+
+/**
+ * @brief This routine is called to set the interface.
+ * Then each class should configure the interface them self.
+ * @return
+ * - Success, if the request is performed.
+ * - UnSupport, if the request is invalid.
+ */
+USB_Result Standard_SetInterface(void)
+{
+ USB_Result Re;
+ /*Test if the specified Interface and Alternate Setting are supported by
+ the application Firmware*/
+ Re = (*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, pInformation->USBwValue0);
+
+ if (pInformation->CurrentConfiguration != 0)
+ {
+ if ((Re != Success) || (pInformation->USBwIndex1 != 0) || (pInformation->USBwValue1 != 0))
+ {
+ return UnSupport;
+ }
+ else if (Re == Success)
+ {
+ pUser_Standard_Requests->User_SetInterface();
+ pInformation->CurrentInterface = pInformation->USBwIndex0;
+ pInformation->CurrentAlternateSetting = pInformation->USBwValue0;
+ return Success;
+ }
+ }
+
+ return UnSupport;
+}
+
+/**
+ * @brief Copy the device request data to "StatusInfo buffer".
+ * Input : - Length - How many bytes are needed.
+ * @return Return 0, if the request is at end of data block,
+ * or is invalid when "Length" is 0.
+ */
+uint8_t* Standard_GetStatus(uint16_t Length)
+{
+ if (Length == 0)
+ {
+ pInformation->Ctrl_Info.Usb_wLength = 2;
+ return 0;
+ }
+
+ /* Reset Status Information */
+ StatusInfo.w = 0;
+
+ if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+ {
+ /*Get Device Status */
+ uint8_t Feature = pInformation->CurrentFeature;
+
+ /* Remote Wakeup enabled */
+ if (ValBit(Feature, 5))
+ {
+ SetBit(StatusInfo0, 1);
+ }
+ else
+ {
+ ClrBit(StatusInfo0, 1);
+ }
+
+ /* Bus-powered */
+ if (ValBit(Feature, 6))
+ {
+ SetBit(StatusInfo0, 0);
+ }
+ else /* Self-powered */
+ {
+ ClrBit(StatusInfo0, 0);
+ }
+ }
+ /*Interface Status*/
+ else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
+ {
+ return (uint8_t*)&StatusInfo;
+ }
+ /*Get EndPoint Status*/
+ else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+ {
+ uint8_t Related_Endpoint;
+ uint8_t wIndex0 = pInformation->USBwIndex0;
+
+ Related_Endpoint = (wIndex0 & 0x0f);
+ if (ValBit(wIndex0, 7))
+ {
+ /* IN endpoint */
+ if (_GetTxStallStatus(Related_Endpoint))
+ {
+ SetBit(StatusInfo0, 0); /* IN Endpoint stalled */
+ }
+ }
+ else
+ {
+ /* OUT endpoint */
+ if (_GetRxStallStatus(Related_Endpoint))
+ {
+ SetBit(StatusInfo0, 0); /* OUT Endpoint stalled */
+ }
+ }
+ }
+ else
+ {
+ return NULL;
+ }
+ pUser_Standard_Requests->User_GetStatus();
+ return (uint8_t*)&StatusInfo;
+}
+
+/**
+ * @brief Clear or disable a specific feature.
+ * @return - Return Success, if the request is performed.
+ * - Return UnSupport, if the request is invalid.
+ */
+USB_Result Standard_ClearFeature(void)
+{
+ uint32_t Type_Rec = Type_Recipient;
+ uint32_t Status;
+
+ if (Type_Rec == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+ { /*Device Clear Feature*/
+ ClrBit(pInformation->CurrentFeature, 5);
+ return Success;
+ }
+ else if (Type_Rec == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+ { /*EndPoint Clear Feature*/
+ USB_Device* pDev;
+ uint32_t Related_Endpoint;
+ uint32_t wIndex0;
+ uint32_t rEP;
+
+ if ((pInformation->USBwValue != ENDPOINT_STALL) || (pInformation->USBwIndex1 != 0))
+ {
+ return UnSupport;
+ }
+
+ pDev = &Device_Table;
+ wIndex0 = pInformation->USBwIndex0;
+ rEP = wIndex0 & ~0x80;
+ Related_Endpoint = ENDP0 + rEP;
+
+ if (ValBit(pInformation->USBwIndex0, 7))
+ {
+ /*Get Status of endpoint & stall the request if the related_ENdpoint
+ is Disabled*/
+ Status = _GetEPTxStatus(Related_Endpoint);
+ }
+ else
+ {
+ Status = _GetEPRxStatus(Related_Endpoint);
+ }
+
+ if ((rEP >= pDev->TotalEndpoint) || (Status == 0) || (pInformation->CurrentConfiguration == 0))
+ {
+ return UnSupport;
+ }
+
+ if (wIndex0 & 0x80)
+ {
+ /* IN endpoint */
+ if (_GetTxStallStatus(Related_Endpoint))
+ {
+ USB_ClrDattogTx(Related_Endpoint);
+ SetEPTxStatus(Related_Endpoint, EP_TX_VALID);
+ }
+ }
+ else
+ {
+ /* OUT endpoint */
+ if (_GetRxStallStatus(Related_Endpoint))
+ {
+ if (Related_Endpoint == ENDP0)
+ {
+ /* After clear the STALL, enable the default endpoint receiver */
+ USB_SetEpRxCnt(Related_Endpoint, Device_Property.MaxPacketSize);
+ _SetEPRxStatus(Related_Endpoint, EP_RX_VALID);
+ }
+ else
+ {
+ USB_ClrDattogRx(Related_Endpoint);
+ _SetEPRxStatus(Related_Endpoint, EP_RX_VALID);
+ }
+ }
+ }
+ pUser_Standard_Requests->User_ClearFeature();
+ return Success;
+ }
+
+ return UnSupport;
+}
+
+/**
+ * @brief Set or enable a specific feature of EndPoint
+ * @return - Return Success, if the request is performed.
+ * - Return UnSupport, if the request is invalid.
+ */
+USB_Result Standard_SetEndPointFeature(void)
+{
+ uint32_t wIndex0;
+ uint32_t Related_Endpoint;
+ uint32_t rEP;
+ uint32_t Status;
+
+ wIndex0 = pInformation->USBwIndex0;
+ rEP = wIndex0 & ~0x80;
+ Related_Endpoint = ENDP0 + rEP;
+
+ if (ValBit(pInformation->USBwIndex0, 7))
+ {
+ /* get Status of endpoint & stall the request if the related_ENdpoint
+ is Disabled*/
+ Status = _GetEPTxStatus(Related_Endpoint);
+ }
+ else
+ {
+ Status = _GetEPRxStatus(Related_Endpoint);
+ }
+
+ if (Related_Endpoint >= Device_Table.TotalEndpoint || pInformation->USBwValue != 0 || Status == 0
+ || pInformation->CurrentConfiguration == 0)
+ {
+ return UnSupport;
+ }
+ else
+ {
+ if (wIndex0 & 0x80)
+ {
+ /* IN endpoint */
+ _SetEPTxStatus(Related_Endpoint, EP_TX_STALL);
+ }
+
+ else
+ {
+ /* OUT endpoint */
+ _SetEPRxStatus(Related_Endpoint, EP_RX_STALL);
+ }
+ }
+ pUser_Standard_Requests->User_SetEndPointFeature();
+ return Success;
+}
+
+/**
+ * @brief Set or enable a specific feature of Device.
+ * @return - Return Success, if the request is performed.
+ * - Return UnSupport, if the request is invalid.
+ */
+USB_Result Standard_SetDeviceFeature(void)
+{
+ SetBit(pInformation->CurrentFeature, 5);
+ pUser_Standard_Requests->User_SetDeviceFeature();
+ return Success;
+}
+
+/**
+ * @brief Standard_GetDescriptorData is used for descriptors transfer.
+ * : This routine is used for the descriptors resident in Flash
+ * or RAM
+ * pDesc can be in either Flash or RAM
+ * The purpose of this routine is to have a versatile way to
+ * response descriptors request. It allows user to generate
+ * certain descriptors with software or read descriptors from
+ * external storage part by part.
+ * Input : - Length - Length of the data in this transfer.
+ * - pDesc - A pointer points to descriptor struct.
+ * The structure gives the initial address of the descriptor and
+ * its original size.
+ * @return Address of a part of the descriptor pointed by the Usb_
+ * wOffset The buffer pointed by this address contains at least
+ * Length bytes.
+ */
+uint8_t* Standard_GetDescriptorData(uint16_t Length, USB_OneDescriptor* pDesc)
+{
+ uint32_t wOffset;
+
+ wOffset = pInformation->Ctrl_Info.Usb_wOffset;
+ if (Length == 0)
+ {
+ pInformation->Ctrl_Info.Usb_wLength = pDesc->Descriptor_Size - wOffset;
+ return 0;
+ }
+
+ return pDesc->Descriptor + wOffset;
+}
+
+/**
+ * @brief Data stage of a Control Write Transfer.
+ */
+void DataStageOut(void)
+{
+ USB_EndpointMess* pEPinfo = &pInformation->Ctrl_Info;
+ uint32_t save_rLength;
+
+ save_rLength = pEPinfo->Usb_rLength;
+
+ if (pEPinfo->CopyData && save_rLength)
+ {
+ uint8_t* Buffer;
+ uint32_t Length;
+
+ Length = pEPinfo->PacketSize;
+ if (Length > save_rLength)
+ {
+ Length = save_rLength;
+ }
+
+ Buffer = (*pEPinfo->CopyData)(Length);
+ pEPinfo->Usb_rLength -= Length;
+ pEPinfo->Usb_rOffset += Length;
+
+ USB_CopyPMAToUserBuf(Buffer, USB_GetEpRxAddr(ENDP0), Length);
+ }
+
+ if (pEPinfo->Usb_rLength != 0)
+ {
+ vSetEPRxStatus(EP_RX_VALID); /* re-enable for next data reception */
+ USB_SetEpTxCnt(ENDP0, 0);
+ vSetEPTxStatus(EP_TX_VALID); /* Expect the host to abort the data OUT stage */
+ }
+ /* Set the next State*/
+ if (pEPinfo->Usb_rLength >= pEPinfo->PacketSize)
+ {
+ pInformation->CtrlState = OutData;
+ }
+ else
+ {
+ if (pEPinfo->Usb_rLength > 0)
+ {
+ pInformation->CtrlState = LastOutData;
+ }
+ else if (pEPinfo->Usb_rLength == 0)
+ {
+ pInformation->CtrlState = WaitStatusIn;
+ USB_StatusIn();
+ }
+ }
+}
+
+/**
+ * @brief Data stage of a Control Read Transfer.
+ */
+void DataStageIn(void)
+{
+ USB_EndpointMess* pEPinfo = &pInformation->Ctrl_Info;
+ uint32_t save_wLength = pEPinfo->Usb_wLength;
+ uint32_t CtrlState = pInformation->CtrlState;
+
+ uint8_t* DataBuffer;
+ uint32_t Length;
+
+ if ((save_wLength == 0) && (CtrlState == LastInData))
+ {
+ if (Data_Mul_MaxPacketSize == true)
+ {
+ /* No more data to send and empty packet */
+ Send0LengthData();
+ CtrlState = LastInData;
+ Data_Mul_MaxPacketSize = false;
+ }
+ else
+ {
+ /* No more data to send so STALL the TX Status*/
+ CtrlState = WaitStatusOut;
+ vSetEPTxStatus(EP_TX_STALL);
+ }
+
+ goto Expect_Status_Out;
+ }
+
+ Length = pEPinfo->PacketSize;
+ CtrlState = (save_wLength <= Length) ? LastInData : InData;
+
+ if (Length > save_wLength)
+ {
+ Length = save_wLength;
+ }
+
+ DataBuffer = (*pEPinfo->CopyData)(Length);
+
+ USB_CopyUserToPMABuf(DataBuffer, USB_GetEpTxAddr(ENDP0), Length);
+
+ USB_SetEpTxCnt(ENDP0, Length);
+
+ pEPinfo->Usb_wLength -= Length;
+ pEPinfo->Usb_wOffset += Length;
+ vSetEPTxStatus(EP_TX_VALID);
+
+ USB_StatusOut(); /* Expect the host to abort the data IN stage */
+
+Expect_Status_Out:
+ pInformation->CtrlState = CtrlState;
+}
+
+/**
+ * @brief Proceed the processing of setup request without data stage.
+ */
+void NoData_Setup0(void)
+{
+ USB_Result Result = UnSupport;
+ uint32_t RequestNo = pInformation->bRequest;
+ uint32_t CtrlState;
+
+ if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+ {
+ /* Device Request*/
+ /* SET_CONFIGURATION*/
+ if (RequestNo == SET_CONFIGURATION)
+ {
+ Result = Standard_SetConfiguration();
+ }
+
+ /*SET ADDRESS*/
+ else if (RequestNo == SET_ADDRESS)
+ {
+ if ((pInformation->USBwValue0 > 127) || (pInformation->USBwValue1 != 0) || (pInformation->USBwIndex != 0)
+ || (pInformation->CurrentConfiguration != 0))
+ /* Device Address should be 127 or less*/
+ {
+ CtrlState = Stalled;
+ goto exit_NoData_Setup0;
+ }
+ else
+ {
+ Result = Success;
+ }
+ }
+ /*SET FEATURE for Device*/
+ else if (RequestNo == SET_FEATURE)
+ {
+ if ((pInformation->USBwValue0 == DEVICE_REMOTE_WAKEUP) && (pInformation->USBwIndex == 0))
+ {
+ Result = Standard_SetDeviceFeature();
+ }
+ else
+ {
+ Result = UnSupport;
+ }
+ }
+ /*Clear FEATURE for Device */
+ else if (RequestNo == CLR_FEATURE)
+ {
+ if (pInformation->USBwValue0 == DEVICE_REMOTE_WAKEUP && pInformation->USBwIndex == 0
+ && ValBit(pInformation->CurrentFeature, 5))
+ {
+ Result = Standard_ClearFeature();
+ }
+ else
+ {
+ Result = UnSupport;
+ }
+ }
+ }
+
+ /* Interface Request*/
+ else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
+ {
+ /*SET INTERFACE*/
+ if (RequestNo == SET_INTERFACE)
+ {
+ Result = Standard_SetInterface();
+ }
+ }
+
+ /* EndPoint Request*/
+ else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+ {
+ /*CLEAR FEATURE for EndPoint*/
+ if (RequestNo == CLR_FEATURE)
+ {
+ Result = Standard_ClearFeature();
+ }
+ /* SET FEATURE for EndPoint*/
+ else if (RequestNo == SET_FEATURE)
+ {
+ Result = Standard_SetEndPointFeature();
+ }
+ }
+ else
+ {
+ Result = UnSupport;
+ }
+
+ if (Result != Success)
+ {
+ Result = (*pProperty->Class_NoData_Setup)(RequestNo);
+ if (Result == Not_Ready)
+ {
+ CtrlState = Pause;
+ goto exit_NoData_Setup0;
+ }
+ }
+
+ if (Result != Success)
+ {
+ CtrlState = Stalled;
+ goto exit_NoData_Setup0;
+ }
+
+ CtrlState = WaitStatusIn; /* After no data stage SETUP */
+
+ USB_StatusIn();
+
+exit_NoData_Setup0:
+ pInformation->CtrlState = CtrlState;
+ return;
+}
+
+/**
+ * @brief Proceed the processing of setup request with data stage.
+ */
+void Data_Setup0(void)
+{
+ uint8_t* (*CopyRoutine)(uint16_t);
+ USB_Result Result;
+ uint32_t Request_No = pInformation->bRequest;
+
+ uint32_t Related_Endpoint, Reserved;
+ uint32_t wOffset, Status;
+
+ CopyRoutine = NULL;
+ wOffset = 0;
+
+ /*GET DESCRIPTOR*/
+ if (Request_No == GET_DESCRIPTOR)
+ {
+ if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+ {
+ uint8_t wValue1 = pInformation->USBwValue1;
+ if (wValue1 == DEVICE_DESCRIPTOR)
+ {
+ CopyRoutine = pProperty->GetDeviceDescriptor;
+ }
+ else if (wValue1 == CONFIG_DESCRIPTOR)
+ {
+ CopyRoutine = pProperty->GetConfigDescriptor;
+ }
+ else if (wValue1 == STRING_DESCRIPTOR)
+ {
+ CopyRoutine = pProperty->GetStringDescriptor;
+ } /* End of GET_DESCRIPTOR */
+ }
+ }
+
+ /*GET STATUS*/
+ else if ((Request_No == GET_STATUS) && (pInformation->USBwValue == 0) && (pInformation->USBwLength == 0x0002)
+ && (pInformation->USBwIndex1 == 0))
+ {
+ /* GET STATUS for Device*/
+ if ((Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)) && (pInformation->USBwIndex == 0))
+ {
+ CopyRoutine = Standard_GetStatus;
+ }
+
+ /* GET STATUS for Interface*/
+ else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
+ {
+ if (((*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, 0) == Success)
+ && (pInformation->CurrentConfiguration != 0))
+ {
+ CopyRoutine = Standard_GetStatus;
+ }
+ }
+
+ /* GET STATUS for EndPoint*/
+ else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+ {
+ Related_Endpoint = (pInformation->USBwIndex0 & 0x0f);
+ Reserved = pInformation->USBwIndex0 & 0x70;
+
+ if (ValBit(pInformation->USBwIndex0, 7))
+ {
+ /*Get Status of endpoint & stall the request if the related_ENdpoint
+ is Disabled*/
+ Status = _GetEPTxStatus(Related_Endpoint);
+ }
+ else
+ {
+ Status = _GetEPRxStatus(Related_Endpoint);
+ }
+
+ if ((Related_Endpoint < Device_Table.TotalEndpoint) && (Reserved == 0) && (Status != 0))
+ {
+ CopyRoutine = Standard_GetStatus;
+ }
+ }
+ }
+
+ /*GET CONFIGURATION*/
+ else if (Request_No == GET_CONFIGURATION)
+ {
+ if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+ {
+ CopyRoutine = Standard_GetConfiguration;
+ }
+ }
+ /*GET INTERFACE*/
+ else if (Request_No == GET_INTERFACE)
+ {
+ if ((Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT)) && (pInformation->CurrentConfiguration != 0)
+ && (pInformation->USBwValue == 0) && (pInformation->USBwIndex1 == 0) && (pInformation->USBwLength == 0x0001)
+ && ((*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, 0) == Success))
+ {
+ CopyRoutine = Standard_GetInterface;
+ }
+ }
+
+ if (CopyRoutine)
+ {
+ pInformation->Ctrl_Info.Usb_wOffset = wOffset;
+ pInformation->Ctrl_Info.CopyData = CopyRoutine;
+ /* sb in the original the cast to word was directly */
+ /* now the cast is made step by step */
+ (*CopyRoutine)(0);
+ Result = Success;
+ }
+ else
+ {
+ Result = (*pProperty->Class_Data_Setup)(pInformation->bRequest);
+ if (Result == Not_Ready)
+ {
+ pInformation->CtrlState = Pause;
+ return;
+ }
+ }
+
+ if (pInformation->Ctrl_Info.Usb_wLength == 0xFFFF)
+ {
+ /* Data is not ready, wait it */
+ pInformation->CtrlState = Pause;
+ return;
+ }
+ if ((Result == UnSupport) || (pInformation->Ctrl_Info.Usb_wLength == 0))
+ {
+ /* Unsupported request */
+ pInformation->CtrlState = Stalled;
+ return;
+ }
+
+ if (ValBit(pInformation->bmRequestType, 7))
+ {
+ /* Device ==> Host */
+ __IO uint32_t wLength = pInformation->USBwLength;
+
+ /* Restrict the data length to be the one host asks for */
+ if (pInformation->Ctrl_Info.Usb_wLength > wLength)
+ {
+ pInformation->Ctrl_Info.Usb_wLength = wLength;
+ }
+
+ else if (pInformation->Ctrl_Info.Usb_wLength < pInformation->USBwLength)
+ {
+ if (pInformation->Ctrl_Info.Usb_wLength < pProperty->MaxPacketSize)
+ {
+ Data_Mul_MaxPacketSize = false;
+ }
+ else if ((pInformation->Ctrl_Info.Usb_wLength % pProperty->MaxPacketSize) == 0)
+ {
+ Data_Mul_MaxPacketSize = true;
+ }
+ }
+
+ pInformation->Ctrl_Info.PacketSize = pProperty->MaxPacketSize;
+ DataStageIn();
+ }
+ else
+ {
+ pInformation->CtrlState = OutData;
+ vSetEPRxStatus(EP_RX_VALID); /* enable for next data reception */
+ }
+
+ return;
+}
+
+/**
+ * @brief Get the device request data and dispatch to individual process.
+ * @return USB_ProcessPost0.
+ */
+uint8_t USB_ProcessSetup0(void)
+{
+ union
+ {
+ uint8_t* b;
+ uint16_t* w;
+ } pBuf;
+
+ uint16_t offset = 1;
+
+ pBuf.b = PMAAddr + (uint8_t*)(_GetEPRxAddr(ENDP0) * 2); /* *2 for 32 bits addr */
+
+ if (pInformation->CtrlState != Pause)
+ {
+ pInformation->bmRequestType = *pBuf.b++; /* bmRequestType */
+ pInformation->bRequest = *pBuf.b++; /* bRequest */
+ pBuf.w += offset; /* word not accessed because of 32 bits addressing */
+ pInformation->USBwValue = USB_ByteSwap(*pBuf.w++); /* wValue */
+ pBuf.w += offset; /* word not accessed because of 32 bits addressing */
+ pInformation->USBwIndex = USB_ByteSwap(*pBuf.w++); /* wIndex */
+ pBuf.w += offset; /* word not accessed because of 32 bits addressing */
+ pInformation->USBwLength = *pBuf.w; /* wLength */
+ }
+
+ pInformation->CtrlState = SettingUp;
+ if (pInformation->USBwLength == 0)
+ {
+ /* Setup with no data stage */
+ NoData_Setup0();
+ }
+ else
+ {
+ /* Setup with data stage */
+ Data_Setup0();
+ }
+ return USB_ProcessPost0();
+}
+
+/**
+ * @brief Process the IN token on all default endpoint.
+ * @return USB_ProcessPost0.
+ */
+uint8_t USB_ProcessIn0(void)
+{
+ uint32_t CtrlState = pInformation->CtrlState;
+
+ if ((CtrlState == InData) || (CtrlState == LastInData))
+ {
+ DataStageIn();
+ /* CtrlState may be changed outside the function */
+ CtrlState = pInformation->CtrlState;
+ }
+
+ else if (CtrlState == WaitStatusIn)
+ {
+ if ((pInformation->bRequest == SET_ADDRESS) && (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)))
+ {
+ USB_SetDeviceAddress(pInformation->USBwValue0);
+ pUser_Standard_Requests->User_SetDeviceAddress();
+ }
+ (*pProperty->Process_Status_IN)();
+ CtrlState = Stalled;
+ }
+
+ else
+ {
+ CtrlState = Stalled;
+ }
+
+ pInformation->CtrlState = CtrlState;
+
+ return USB_ProcessPost0();
+}
+
+/**
+ * @brief Process the OUT token on all default endpoint.
+ * @return USB_ProcessPost0.
+ */
+uint8_t USB_ProcessOut0(void)
+{
+ uint32_t CtrlState = pInformation->CtrlState;
+
+ if ((CtrlState == InData) || (CtrlState == LastInData))
+ {
+ /* host aborts the transfer before finish */
+ CtrlState = Stalled;
+ }
+ else if ((CtrlState == OutData) || (CtrlState == LastOutData))
+ {
+ DataStageOut();
+ CtrlState = pInformation->CtrlState; /* may be changed outside the function */
+ }
+
+ else if (CtrlState == WaitStatusOut)
+ {
+ (*pProperty->Process_Status_OUT)();
+ CtrlState = Stalled;
+ }
+
+ /* Unexpect state, STALL the endpoint */
+ else
+ {
+ CtrlState = Stalled;
+ }
+
+ pInformation->CtrlState = CtrlState;
+
+ return USB_ProcessPost0();
+}
+
+/**
+ * @brief Stall the Endpoint 0 in case of error.
+ * @return
+ * - 0 if the control State is in Pause
+ * - 1 if not.
+ */
+uint8_t USB_ProcessPost0(void)
+{
+ USB_SetEpRxCnt(ENDP0, Device_Property.MaxPacketSize);
+
+ if (pInformation->CtrlState == Stalled)
+ {
+ vSetEPRxStatus(EP_RX_STALL);
+ vSetEPTxStatus(EP_TX_STALL);
+ }
+ return (pInformation->CtrlState == Pause);
+}
+
+/**
+ * @brief Set the device and all the used Endpoints addresses.
+ * @param Val device address.
+ */
+void USB_SetDeviceAddress(uint8_t Val)
+{
+ uint32_t i;
+ uint32_t nEP = Device_Table.TotalEndpoint;
+
+ /* set address in every used endpoint */
+ for (i = 0; i < nEP; i++)
+ {
+ _SetEPAddress((uint8_t)i, (uint8_t)i);
+ } /* for */
+ _SetDADDR(Val | ADDR_EFUC); /* set device address and enable function */
+}
+
+/**
+ * @brief No operation function.
+ */
+void USB_ProcessNop(void)
+{
+}
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_init.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_init.c
new file mode 100644
index 0000000000..016aec225c
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_init.c
@@ -0,0 +1,69 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_init.c
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "usb_lib.h"
+
+/* The number of current endpoint, it will be used to specify an endpoint */
+uint8_t EPindex;
+/* The number of current device, it is an index to the Device_Table */
+/* uint8_t Device_no; */
+/* Points to the USB_DeviceMess structure of current device */
+/* The purpose of this register is to speed up the execution */
+USB_DeviceMess* pInformation;
+/* Points to the DEVICE_PROP structure of current device */
+/* The purpose of this register is to speed up the execution */
+DEVICE_PROP* pProperty;
+/* Temporary save the state of Rx & Tx status. */
+/* Whenever the Rx or Tx state is changed, its value is saved */
+/* in this variable first and will be set to the EPRB or EPRA */
+/* at the end of interrupt process */
+uint16_t SaveState;
+uint16_t wInterrupt_Mask;
+USB_DeviceMess Device_Info;
+USER_STANDARD_REQUESTS* pUser_Standard_Requests;
+
+/**
+ * @brief USB system initialization
+ */
+void USB_Init(void)
+{
+ pInformation = &Device_Info;
+ pInformation->CtrlState = 2;
+ pProperty = &Device_Property;
+ pUser_Standard_Requests = &User_Standard_Requests;
+ /* Initialize devices one by one */
+ pProperty->Init();
+ /*Pull up DP*/
+ _EnPortPullup();
+}
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_int.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_int.c
new file mode 100644
index 0000000000..859d1f9ec8
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_int.c
@@ -0,0 +1,179 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_int.c
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "usb_lib.h"
+
+__IO uint16_t SaveRState;
+__IO uint16_t SaveTState;
+
+extern void (*pEpInt_IN[7])(void); /* Handles IN interrupts */
+extern void (*pEpInt_OUT[7])(void); /* Handles OUT interrupts */
+
+/**
+ * @brief Low priority Endpoint Correct Transfer interrupt's service routine.
+ */
+void USB_CorrectTransferLp(void)
+{
+ __IO uint16_t wEPVal = 0;
+ /* stay in loop while pending interrupts */
+ while (((wIstr = _GetISTR()) & STS_CTRS) != 0)
+ {
+ /* extract highest priority endpoint number */
+ EPindex = (uint8_t)(wIstr & STS_EP_ID);
+ if (EPindex == 0)
+ {
+ /* Decode and service control endpoint interrupt */
+ /* calling related service routine */
+ /* (USB_ProcessSetup0, USB_ProcessIn0, USB_ProcessOut0) */
+
+ /* save RX & TX status */
+ /* and set both to NAK */
+
+ SaveRState = _GetENDPOINT(ENDP0);
+ SaveTState = SaveRState & EPTX_STS;
+ SaveRState &= EPRX_STS;
+ _SetEPRxTxStatus(ENDP0, EP_RX_NAK, EP_TX_NAK);
+
+ /* DIR bit = origin of the interrupt */
+
+ if ((wIstr & STS_DIR) == 0)
+ {
+ /* DIR = 0 */
+
+ /* DIR = 0 => IN int */
+ /* DIR = 0 implies that (EP_CTRS_TX = 1) always */
+
+ _ClearEP_CTR_TX(ENDP0);
+ USB_ProcessIn0();
+
+ /* before terminate set Tx & Rx status */
+
+ _SetEPRxTxStatus(ENDP0, SaveRState, SaveTState);
+ return;
+ }
+ else
+ {
+ /* DIR = 1 */
+
+ /* DIR = 1 & CTR_RX => SETUP or OUT int */
+ /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
+
+ wEPVal = _GetENDPOINT(ENDP0);
+
+ if ((wEPVal & EP_SETUP) != 0)
+ {
+ _ClearEP_CTR_RX(ENDP0); /* SETUP bit kept frozen while CTR_RX = 1 */
+ USB_ProcessSetup0();
+ /* before terminate set Tx & Rx status */
+
+ _SetEPRxTxStatus(ENDP0, SaveRState, SaveTState);
+ return;
+ }
+
+ else if ((wEPVal & EP_CTRS_RX) != 0)
+ {
+ _ClearEP_CTR_RX(ENDP0);
+ USB_ProcessOut0();
+ /* before terminate set Tx & Rx status */
+
+ _SetEPRxTxStatus(ENDP0, SaveRState, SaveTState);
+ return;
+ }
+ }
+ } /* if (EPindex == 0) */
+ else
+ {
+ /* Decode and service non control endpoints interrupt */
+
+ /* process related endpoint register */
+ wEPVal = _GetENDPOINT(EPindex);
+ if ((wEPVal & EP_CTRS_RX) != 0)
+ {
+ /* clear int flag */
+ _ClearEP_CTR_RX(EPindex);
+
+ /* call OUT service function */
+ (*pEpInt_OUT[EPindex - 1])();
+
+ } /* if ((wEPVal & EP_CTRS_RX) */
+
+ if ((wEPVal & EP_CTRS_TX) != 0)
+ {
+ /* clear int flag */
+ _ClearEP_CTR_TX(EPindex);
+
+ /* call IN service function */
+ (*pEpInt_IN[EPindex - 1])();
+ } /* if ((wEPVal & EP_CTRS_TX) != 0) */
+
+ } /* if (EPindex == 0) else */
+
+ } /* while (...) */
+}
+
+/**
+ * @brief High Priority Endpoint Correct Transfer interrupt's service routine.
+ */
+void USB_CorrectTransferHp(void)
+{
+ uint32_t wEPVal = 0;
+
+ while (((wIstr = _GetISTR()) & STS_CTRS) != 0)
+ {
+ _SetISTR((uint16_t)CLR_CTRS); /* clear CTR flag */
+ /* extract highest priority endpoint number */
+ EPindex = (uint8_t)(wIstr & STS_EP_ID);
+ /* process related endpoint register */
+ wEPVal = _GetENDPOINT(EPindex);
+ if ((wEPVal & EP_CTRS_RX) != 0)
+ {
+ /* clear int flag */
+ _ClearEP_CTR_RX(EPindex);
+
+ /* call OUT service function */
+ (*pEpInt_OUT[EPindex - 1])();
+
+ } /* if ((wEPVal & EP_CTRS_RX) */
+ else if ((wEPVal & EP_CTRS_TX) != 0)
+ {
+ /* clear int flag */
+ _ClearEP_CTR_TX(EPindex);
+
+ /* call IN service function */
+ (*pEpInt_IN[EPindex - 1])();
+
+ } /* if ((wEPVal & EP_CTRS_TX) != 0) */
+
+ } /* while (...) */
+}
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_mem.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_mem.c
new file mode 100644
index 0000000000..539a76b7cc
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_mem.c
@@ -0,0 +1,81 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_mem.c
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "usb_lib.h"
+u8* EpOutDataPtrTmp;
+u8* EpInDataPtrTmp;
+
+/**
+ * @brief Copy a buffer from user memory area to packet memory area (PMA)
+ * @param pbUsrBuf pointer to user memory area.
+ * @param wPMABufAddr address into PMA.
+ * @param wNBytes no. of bytes to be copied.
+ */
+void USB_CopyUserToPMABuf(uint8_t* pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+ uint32_t n = (wNBytes + 1) >> 1; /* n = (wNBytes + 1) / 2 */
+ uint32_t i, temp1, temp2;
+ uint16_t* pdwVal;
+ pdwVal = (uint16_t*)(wPMABufAddr * 2 + PMAAddr);
+ for (i = n; i != 0; i--)
+ {
+ temp1 = (uint16_t)*pbUsrBuf;
+ pbUsrBuf++;
+ temp2 = temp1 | (uint16_t)*pbUsrBuf << 8;
+ *pdwVal++ = temp2;
+ pdwVal++;
+ pbUsrBuf++;
+ EpInDataPtrTmp = pbUsrBuf;
+ }
+}
+
+/**
+ * @brief Copy a buffer from user memory area to packet memory area (PMA)
+ * @param pbUsrBuf pointer to user memory area.
+ * @param wPMABufAddr address into PMA.
+ * @param wNBytes no. of bytes to be copied.
+ */
+void USB_CopyPMAToUserBuf(uint8_t* pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+ uint32_t n = (wNBytes + 1) >> 1; /* /2*/
+ uint32_t i;
+ uint32_t* pdwVal;
+ pdwVal = (uint32_t*)(wPMABufAddr * 2 + PMAAddr);
+ for (i = n; i != 0; i--)
+ {
+ *(uint16_t*)pbUsrBuf++ = *pdwVal++;
+ pbUsrBuf++;
+ EpOutDataPtrTmp = pbUsrBuf;
+ }
+}
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_regs.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_regs.c
new file mode 100644
index 0000000000..9dc97c4db7
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_regs.c
@@ -0,0 +1,598 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_regs.c
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "usb_lib.h"
+
+/**
+ * @brief Set the CTRL register value.
+ * @param wRegValue new register value.
+ */
+void USB_SetCtrl(uint16_t wRegValue)
+{
+ _SetCNTR(wRegValue);
+}
+
+/**
+ * @brief returns the CTRL register value.
+ * @return CTRL register Value.
+ */
+uint16_t USB_GetCtrl(void)
+{
+ return (_GetCNTR());
+}
+
+/**
+ * @brief Set the STS register value.
+ * @param wRegValue new register value.
+ */
+void USB_SetSts(uint16_t wRegValue)
+{
+ _SetISTR(wRegValue);
+}
+
+/**
+ * @brief Returns the STS register value.
+ * @return STS register Value
+ */
+uint16_t USB_GetSts(void)
+{
+ return (_GetISTR());
+}
+
+/**
+ * @brief Returns the FN register value.
+ * @return FN register Value
+ */
+uint16_t USB_GetFn(void)
+{
+ return (_GetFNR());
+}
+
+/**
+ * @brief Set the ADDR register value.
+ * @param wRegValue new register value.
+ */
+void USB_SetAddr(uint16_t wRegValue)
+{
+ _SetDADDR(wRegValue);
+}
+
+/**
+ * @brief Returns the ADDR register value.
+ * @return ADDR register Value
+ */
+uint16_t USB_GetAddr(void)
+{
+ return (_GetDADDR());
+}
+
+/**
+ * @brief Set the BUFTAB.
+ * @param wRegValue New register value.
+ */
+void USB_SetBuftab(uint16_t wRegValue)
+{
+ _SetBTABLE(wRegValue);
+}
+
+/**
+ * @brief Returns the BUFTAB register value.
+ * @return BUFTAB address.
+ */
+uint16_t USB_GetBTABLE(void)
+{
+ return (_GetBTABLE());
+}
+
+/**
+ * @brief Set the Endpoint register value.
+ * @param bEpNum Endpoint Number.
+ * @param wRegValue New register value.
+ */
+void USB_SetEndPoint(uint8_t bEpNum, uint16_t wRegValue)
+{
+ _SetENDPOINT(bEpNum, wRegValue);
+}
+
+/**
+ * @brief Return the Endpoint register value.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint register value.
+ */
+uint16_t USB_GetEndPoint(uint8_t bEpNum)
+{
+ return (_GetENDPOINT(bEpNum));
+}
+
+/**
+ * @brief sets the type in the endpoint register.
+ * @param bEpNum Endpoint Number.
+ * @param wType type definition.
+ */
+void USB_SetEpType(uint8_t bEpNum, uint16_t wType)
+{
+ _SetEPType(bEpNum, wType);
+}
+
+/**
+ * @brief Returns the endpoint type.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint Type
+ */
+uint16_t USB_GetEpType(uint8_t bEpNum)
+{
+ return (_GetEPType(bEpNum));
+}
+
+/**
+ * @brief Set the status of Tx endpoint.
+ * @param bEpNum Endpoint Number.
+ * @param wState new state.
+ */
+void SetEPTxStatus(uint8_t bEpNum, uint16_t wState)
+{
+ _SetEPTxStatus(bEpNum, wState);
+}
+
+/**
+ * @brief Set the status of Rx endpoint.
+ * @param bEpNum Endpoint Number.
+ * @param wState new state.
+ */
+void SetEPRxStatus(uint8_t bEpNum, uint16_t wState)
+{
+ _SetEPRxStatus(bEpNum, wState);
+}
+
+/**
+ * @brief sets the status for Double Buffer Endpoint to STALL
+ * @param bEpNum Endpoint Number.
+ * @param bDir Endpoint direction.
+ */
+void USB_SetDouBleBuferEpStall(uint8_t bEpNum, uint8_t bDir)
+{
+ uint16_t Endpoint_DTOG_Status;
+ Endpoint_DTOG_Status = USB_GetEndPoint(bEpNum);
+ if (bDir == EP_DBUF_OUT)
+ { /* OUT double buffered endpoint */
+ _SetENDPOINT(bEpNum, Endpoint_DTOG_Status & ~EPRX_DATTOG1);
+ }
+ else if (bDir == EP_DBUF_IN)
+ { /* IN double buffered endpoint */
+ _SetENDPOINT(bEpNum, Endpoint_DTOG_Status & ~EPTX_DATTOG1);
+ }
+}
+
+/**
+ * @brief Returns the endpoint Tx status.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint TX Status
+ */
+uint16_t USB_GetEpTxSts(uint8_t bEpNum)
+{
+ return (_GetEPTxStatus(bEpNum));
+}
+
+/**
+ * @brief Returns the endpoint Rx status.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint RX Status
+ */
+uint16_t USB_GetEpRxSts(uint8_t bEpNum)
+{
+ return (_GetEPRxStatus(bEpNum));
+}
+
+/**
+ * @brief Valid the endpoint Tx Status.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_SetEpTxValid(uint8_t bEpNum)
+{
+ _SetEPTxStatus(bEpNum, EP_TX_VALID);
+}
+
+/**
+ * @brief Valid the endpoint Rx Status.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_SetEpRxValid(uint8_t bEpNum)
+{
+ _SetEPRxStatus(bEpNum, EP_RX_VALID);
+}
+
+/**
+ * @brief Clear the EP_KIND bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_SetEpKind(uint8_t bEpNum)
+{
+ _SetEP_KIND(bEpNum);
+}
+
+/**
+ * @brief set the EP_KIND bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrEpKind(uint8_t bEpNum)
+{
+ _ClearEP_KIND(bEpNum);
+}
+/**
+ * @brief Clear the Status Out of the related Endpoint
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrStsOut(uint8_t bEpNum)
+{
+ _ClearEP_KIND(bEpNum);
+}
+/**
+ * @brief Set the Status Out of the related Endpoint
+ * @param bEpNum Endpoint Number.
+ */
+void USB_SetStsOut(uint8_t bEpNum)
+{
+ _SetEP_KIND(bEpNum);
+}
+/**
+ * @brief Enable the double buffer feature for the endpoint.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_SetEpDoubleBufer(uint8_t bEpNum)
+{
+ _SetEP_KIND(bEpNum);
+}
+/**
+ * @brief Disable the double buffer feature for the endpoint.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrEpDoubleBufer(uint8_t bEpNum)
+{
+ _ClearEP_KIND(bEpNum);
+}
+/**
+ * @brief Returns the Stall status of the Tx endpoint.
+ * @param bEpNum Endpoint Number.
+ * @return Tx Stall status.
+ */
+uint16_t USB_GetTxStallSts(uint8_t bEpNum)
+{
+ return (_GetTxStallStatus(bEpNum));
+}
+/**
+ * @brief Returns the Stall status of the Rx endpoint.
+ * @param bEpNum Endpoint Number.
+ * @return Rx Stall status.
+ */
+uint16_t USB_GetRxStallSts(uint8_t bEpNum)
+{
+ return (_GetRxStallStatus(bEpNum));
+}
+/**
+ * @brief Clear the CTR_RX bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrEpCtrsRx(uint8_t bEpNum)
+{
+ _ClearEP_CTR_RX(bEpNum);
+}
+/**
+ * @brief Clear the CTR_TX bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrEpCtrsTx(uint8_t bEpNum)
+{
+ _ClearEP_CTR_TX(bEpNum);
+}
+/**
+ * @brief Toggle the DTOG_RX bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_DattogRx(uint8_t bEpNum)
+{
+ _ToggleDTOG_RX(bEpNum);
+}
+/**
+ * @brief Toggle the DTOG_TX bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_DattogTx(uint8_t bEpNum)
+{
+ _ToggleDTOG_TX(bEpNum);
+}
+/**
+ * @brief Clear the DTOG_RX bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrDattogRx(uint8_t bEpNum)
+{
+ _ClearDTOG_RX(bEpNum);
+}
+/**
+ * @brief Clear the DTOG_TX bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrDattogTx(uint8_t bEpNum)
+{
+ _ClearDTOG_TX(bEpNum);
+}
+/**
+ * @brief Set the endpoint address.
+ * @param bEpNum Endpoint Number.
+ * @param bAddr New endpoint address.
+ */
+void USB_SetEpAddress(uint8_t bEpNum, uint8_t bAddr)
+{
+ _SetEPAddress(bEpNum, bAddr);
+}
+/**
+ * @brief Get the endpoint address.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint address.
+ */
+uint8_t USB_GetEpAddress(uint8_t bEpNum)
+{
+ return (_GetEPAddress(bEpNum));
+}
+/**
+ * @brief Set the endpoint Tx buffer address.
+ * @param bEpNum Endpoint Number.
+ * @param wAddr new address.
+ */
+void USB_SetEpTxAddr(uint8_t bEpNum, uint16_t wAddr)
+{
+ _SetEPTxAddr(bEpNum, wAddr);
+}
+/**
+ * @brief Set the endpoint Rx buffer address.
+ * @param bEpNum Endpoint Number.
+ * @param wAddr new address.
+ */
+void USB_SetEpRxAddr(uint8_t bEpNum, uint16_t wAddr)
+{
+ _SetEPRxAddr(bEpNum, wAddr);
+}
+/**
+ * @brief Returns the endpoint Tx buffer address.
+ * @param bEpNum Endpoint Number.
+ * @return Rx buffer address.
+ */
+uint16_t USB_GetEpTxAddr(uint8_t bEpNum)
+{
+ return (_GetEPTxAddr(bEpNum));
+}
+/**
+ * @brief Returns the endpoint Rx buffer address.
+ * @param bEpNum Endpoint Number.
+ * @return Rx buffer address.
+ */
+uint16_t USB_GetEpRxAddr(uint8_t bEpNum)
+{
+ return (_GetEPRxAddr(bEpNum));
+}
+/**
+ * @brief Set the Tx count.
+ * @param bEpNum Endpoint Number.
+ * @param wCount new count value.
+ */
+void USB_SetEpTxCnt(uint8_t bEpNum, uint16_t wCount)
+{
+ _SetEPTxCount(bEpNum, wCount);
+}
+/**
+ * @brief Set the Count Rx Register value.
+ * @param pdwReg point to the register.
+ * @param wCount the new register value.
+ */
+void USB_SetEpCntRxReg(uint32_t* pdwReg, uint16_t wCount)
+{
+ _SetEPCountRxReg(dwReg, wCount);
+}
+/**
+ * @brief Set the Rx count.
+ * @param bEpNum Endpoint Number.
+ * @param wCount the new count value.
+ */
+void USB_SetEpRxCnt(uint8_t bEpNum, uint16_t wCount)
+{
+ _SetEPRxCount(bEpNum, wCount);
+}
+/**
+ * @brief Get the Tx count.
+ * @param bEpNum Endpoint Number.
+ * @return Tx count value.
+ */
+uint16_t USB_GetEpTxCnt(uint8_t bEpNum)
+{
+ return (_GetEPTxCount(bEpNum));
+}
+/**
+ * @brief Get the Rx count.
+ * @param bEpNum Endpoint Number.
+ * @return Rx count value.
+ */
+uint16_t USB_GetEpRxCnt(uint8_t bEpNum)
+{
+ return (_GetEPRxCount(bEpNum));
+}
+/**
+ * @brief Set the addresses of the buffer 0 and 1.
+ * @param bEpNum Endpoint Number.
+ * @param wBuf0Addr new address of buffer 0.
+ * @param wBuf1Addr new address of buffer 1.
+ */
+void USB_SetEpDblBuferAddr(uint8_t bEpNum, uint16_t wBuf0Addr, uint16_t wBuf1Addr)
+{
+ _SetEPDblBuffAddr(bEpNum, wBuf0Addr, wBuf1Addr);
+}
+/**
+ * @brief Set the Buffer 1 address.
+ * @param bEpNum Endpoint Number
+ * @param wBuf0Addr new address.
+ */
+void USB_SetEpDblBuf0Addr(uint8_t bEpNum, uint16_t wBuf0Addr)
+{
+ _SetEPDblBuf0Addr(bEpNum, wBuf0Addr);
+}
+/**
+ * @brief Set the Buffer 1 address.
+ * @param bEpNum Endpoint Number
+ * @param wBuf1Addr new address.
+ */
+void USB_SetEpDblBuf1Addr(uint8_t bEpNum, uint16_t wBuf1Addr)
+{
+ _SetEPDblBuf1Addr(bEpNum, wBuf1Addr);
+}
+/**
+ * @brief Returns the address of the Buffer 0.
+ * @param bEpNum Endpoint Number.
+ */
+uint16_t USB_GetEpDblBuf0Addr(uint8_t bEpNum)
+{
+ return (_GetEPDblBuf0Addr(bEpNum));
+}
+/**
+ * @brief Returns the address of the Buffer 1.
+ * @param bEpNum Endpoint Number.
+ * @return Address of the Buffer 1.
+ */
+uint16_t USB_GetEpDblBuf1Addr(uint8_t bEpNum)
+{
+ return (_GetEPDblBuf1Addr(bEpNum));
+}
+/**
+ * @brief Set the number of bytes for a double Buffer endpoint.
+ * @param bEpNum
+ * @param bDir
+ * @param wCount
+ */
+void USB_SetEpDblBuferCnt(uint8_t bEpNum, uint8_t bDir, uint16_t wCount)
+{
+ _SetEPDblBuffCount(bEpNum, bDir, wCount);
+}
+/**
+ * @brief Set the number of bytes in the buffer 0 of a double Buffer endpoint.
+ * @param bEpNum
+ * @param bDir
+ * @param wCount
+ */
+void USB_SetEpDblBuf0Cnt(uint8_t bEpNum, uint8_t bDir, uint16_t wCount)
+{
+ _SetEPDblBuf0Count(bEpNum, bDir, wCount);
+}
+/**
+ * @brief Set the number of bytes in the buffer 0 of a double Buffer endpoint.
+ * @param bEpNum
+ * @param bDir
+ * @param wCount
+ */
+void USB_SetEpDblBuf1Cnt(uint8_t bEpNum, uint8_t bDir, uint16_t wCount)
+{
+ _SetEPDblBuf1Count(bEpNum, bDir, wCount);
+}
+/**
+ * @brief Returns the number of byte received in the buffer 0 of a double Buffer endpoint.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint Buffer 0 count
+ */
+uint16_t USB_GetEpDblBuf0Cnt(uint8_t bEpNum)
+{
+ return (_GetEPDblBuf0Count(bEpNum));
+}
+/**
+ * @brief Returns the number of data received in the buffer 1 of a double Buffer endpoint.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint Buffer 1 count.
+ */
+uint16_t USB_GetEpDblBuf1Cnt(uint8_t bEpNum)
+{
+ return (_GetEPDblBuf1Count(bEpNum));
+}
+/**
+ * @brief gets direction of the double buffered endpoint
+ * @param bEpNum Endpoint Number.
+ * @return EP_DBUF_OUT, EP_DBUF_IN, EP_DBUF_ERR if the endpoint counter not yet programmed.
+ */
+EP_DBUF_DIR GetEPDblBufDir(uint8_t bEpNum)
+{
+ if ((uint16_t)(*_pEPRxCount(bEpNum) & 0xFC00) != 0)
+ return (EP_DBUF_OUT);
+ else if (((uint16_t)(*_pEPTxCount(bEpNum)) & 0x03FF) != 0)
+ return (EP_DBUF_IN);
+ else
+ return (EP_DBUF_ERR);
+}
+/**
+ * @brief free buffer used from the application realizing it to the line toggles
+ * bit SW_BUF in the double buffered endpoint register
+ * @param bEpNum
+ * @param bDir
+ */
+void USB_FreeUserBuf(uint8_t bEpNum, uint8_t bDir)
+{
+ if (bDir == EP_DBUF_OUT)
+ { /* OUT double buffered endpoint */
+ _ToggleDTOG_TX(bEpNum);
+ }
+ else if (bDir == EP_DBUF_IN)
+ { /* IN double buffered endpoint */
+ _ToggleDTOG_RX(bEpNum);
+ }
+}
+
+/**
+ * @brief merge two byte in a word.
+ * @param bh byte high
+ * @param bl bytes low.
+ * @return resulted word.
+ */
+uint16_t USB_ToWord(uint8_t bh, uint8_t bl)
+{
+ uint16_t wRet;
+ wRet = (uint16_t)bl | ((uint16_t)bh << 8);
+ return (wRet);
+}
+/**
+ * @brief Swap two byte in a word.
+ * @param wSwW word to Swap.
+ * @return resulted word.
+ */
+uint16_t USB_ByteSwap(uint16_t wSwW)
+{
+ uint8_t bTemp;
+ uint16_t wRet;
+ bTemp = (uint8_t)(wSwW & 0xff);
+ wRet = (wSwW >> 8) | ((uint16_t)bTemp << 8);
+ return (wRet);
+}
diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_sil.c b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_sil.c
new file mode 100644
index 0000000000..930e661c83
--- /dev/null
+++ b/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_sil.c
@@ -0,0 +1,83 @@
+/*****************************************************************************
+ * Copyright (c) 2019, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_sil.c
+ * @author Nations
+ * @version v1.0.0
+ *
+ * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ */
+#include "usb_lib.h"
+
+/**
+ * @brief Initialize the USB Device IP and the Endpoint 0.
+ * @return Status.
+ */
+uint32_t USB_SilInit(void)
+{
+ /* USB interrupts initialization */
+ /* clear pending interrupts */
+ _SetISTR(0);
+ wInterrupt_Mask = IMR_MSK;
+ /* set interrupts mask */
+ _SetCNTR(wInterrupt_Mask);
+ return 0;
+}
+
+/**
+ * @brief Write a buffer of data to a selected endpoint.
+ * @param bEpAddr The address of the non control endpoint.
+ * @param pBufferPointer The pointer to the buffer of data to be written to the endpoint.
+ * @param wBufferSize Number of data to be written (in bytes).
+ * @return Status.
+ */
+uint32_t USB_SilWrite(uint8_t bEpAddr, uint8_t* pBufferPointer, uint32_t wBufferSize)
+{
+ /* Use the memory interface function to write to the selected endpoint */
+ USB_CopyUserToPMABuf(pBufferPointer, USB_GetEpTxAddr(bEpAddr & 0x7F), wBufferSize);
+ /* Update the data length in the control register */
+ USB_SetEpTxCnt((bEpAddr & 0x7F), wBufferSize);
+ return 0;
+}
+
+/**
+ * @brief Write a buffer of data to a selected endpoint.
+ * @param bEpAddr The address of the non control endpoint.
+ * @param pBufferPointer The pointer to which will be saved the received data buffer.
+ * @return Number of received data (in Bytes).
+ */
+uint32_t USB_SilRead(uint8_t bEpAddr, uint8_t* pBufferPointer)
+{
+ uint32_t DataLength = 0;
+ /* Get the number of received data on the selected Endpoint */
+ DataLength = USB_GetEpRxCnt(bEpAddr & 0x7F);
+ /* Use the memory interface function to write to the selected endpoint */
+ USB_CopyPMAToUserBuf(pBufferPointer, USB_GetEpRxAddr(bEpAddr & 0x7F), DataLength);
+ /* Return the number of received data */
+ return DataLength;
+}
diff --git a/bsp/n32/libraries/n32_drivers/SConscript b/bsp/n32/libraries/n32_drivers/SConscript
index 05af78d93a..98d4d616a6 100644
--- a/bsp/n32/libraries/n32_drivers/SConscript
+++ b/bsp/n32/libraries/n32_drivers/SConscript
@@ -30,7 +30,6 @@ if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']):
if GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2') or GetDepend('BSP_USING_I2C3') or GetDepend('BSP_USING_I2C4'):
src += ['drv_i2c.c']
-
if GetDepend(['RT_USING_ADC']):
src += Glob('drv_adc.c')
diff --git a/bsp/n32/libraries/n32_drivers/drv_adc.c b/bsp/n32/libraries/n32_drivers/drv_adc.c
index 3ac797a847..abf0555adf 100644
--- a/bsp/n32/libraries/n32_drivers/drv_adc.c
+++ b/bsp/n32/libraries/n32_drivers/drv_adc.c
@@ -1,73 +1,56 @@
-/*****************************************************************************
- * Copyright (c) 2019, Nations Technologies Inc.
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
*
- * All rights reserved.
- * ****************************************************************************
+ * SPDX-License-Identifier: Apache-2.0
*
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Nations' name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ****************************************************************************/
-
-/**
- * @file drv_adc.c
- * @author Nations
- * @version v1.0.0
- *
- * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ * Change Logs:
+ * Date Author Notes
+ * 2022-10-19 Nations first version
*/
-#include "board.h"
#include "drv_adc.h"
#ifdef RT_USING_ADC
-#if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3) || defined(BSP_USING_ADC4)
- /* this driver can be disabled at menuconfig -> Hardware Drivers Config -> On-chip Peripheral Drivers -> Enable ADC */
-
+#if defined(BSP_USING_ADC) || defined(BSP_USING_ADC1) || \
+ defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3) || \
+ defined(BSP_USING_ADC4)
static struct n32_adc_config adc_config[] =
{
+#if defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
+#ifdef BSP_USING_ADC
+ {
+ "adc",
+ ADC,
+ },
+#endif
+#endif
+
#ifdef BSP_USING_ADC1
{
- "adc1",
- ADC1,
+ "adc1",
+ ADC1,
},
#endif
#ifdef BSP_USING_ADC2
{
- "adc2",
- ADC2,
+ "adc2",
+ ADC2,
},
#endif
#ifdef BSP_USING_ADC3
{
- "adc3",
- ADC3,
+ "adc3",
+ ADC3,
},
#endif
#ifdef BSP_USING_ADC4
{
- "adc4",
- ADC4,
+ "adc4",
+ ADC4,
},
#endif
};
@@ -77,8 +60,14 @@ static struct n32_adc adc_obj[sizeof(adc_config) / sizeof(adc_config[0])] = {0};
static void n32_adc_init(struct n32_adc_config *config)
{
ADC_InitType ADC_InitStructure;
- /* ADC configuration ------------------------------------------------------*/
+
+ ADC_DeInit((ADC_Module*)config->adc_periph);
+
+ /* ADC configuration */
+#if defined(SOC_N32G45X) || defined(SOC_N32WB452)
ADC_InitStructure.WorkMode = ADC_WORKMODE_INDEPENDENT;
+#endif
+
ADC_InitStructure.MultiChEn = DISABLE;
ADC_InitStructure.ContinueConvEn = DISABLE;
ADC_InitStructure.ExtTrigSelect = ADC_EXT_TRIGCONV_NONE;
@@ -88,14 +77,15 @@ static void n32_adc_init(struct n32_adc_config *config)
/* Enable ADC */
ADC_Enable((ADC_Module*)config->adc_periph, ENABLE);
+
/* Check ADC Ready */
- while(ADC_GetFlagStatusNew((ADC_Module*)config->adc_periph, ADC_FLAG_RDY) == RESET)
- ;
+ while (ADC_GetFlagStatusNew((ADC_Module*)config->adc_periph, ADC_FLAG_RDY) == RESET);
+
/* Start ADC calibration */
ADC_StartCalibration((ADC_Module*)config->adc_periph);
+
/* Check the end of ADC calibration */
- while (ADC_GetCalibrationStatus((ADC_Module*)config->adc_periph))
- ;
+ while (ADC_GetCalibrationStatus((ADC_Module*)config->adc_periph));
}
static rt_err_t n32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
@@ -123,12 +113,13 @@ static rt_err_t n32_adc_convert(struct rt_adc_device *device, rt_uint32_t channe
/* Start ADC Software Conversion */
ADC_EnableSoftwareStartConv((ADC_Module*)config->adc_periph, ENABLE);
- while(ADC_GetFlagStatus((ADC_Module*)config->adc_periph, ADC_FLAG_ENDC)==0)
+ while (ADC_GetFlagStatus((ADC_Module*)config->adc_periph, ADC_FLAG_ENDC)==0)
{
}
+
ADC_ClearFlag((ADC_Module*)config->adc_periph, ADC_FLAG_ENDC);
ADC_ClearFlag((ADC_Module*)config->adc_periph, ADC_FLAG_STR);
- *value=ADC_GetDat((ADC_Module*)config->adc_periph);
+ *value = ADC_GetDat((ADC_Module*)config->adc_periph);
return RT_EOK;
}
@@ -141,35 +132,76 @@ static struct rt_adc_ops n32_adc_ops =
int rt_hw_adc_init(void)
{
+ GPIO_InitType GPIO_InitStructure;
+
int i = 0;
int result = RT_EOK;
-#if defined(BSP_USING_ADC1)
+#if defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
+#ifdef BSP_USING_ADC
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
+ RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC, ENABLE);
+
+ GPIO_InitStruct(&GPIO_InitStructure);
+ /* Configure PA.01 PA.02 as analog input */
+ GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Analog;
+ GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure);
+#endif
+#endif
+
+#ifdef BSP_USING_ADC1
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC1, ENABLE);
- /* Configure PC.00 PC.01 as analog input -------------------------*/
- GPIOInit(GPIOC, GPIO_Mode_AIN, GPIO_Speed_50MHz, GPIO_PIN_0 | GPIO_PIN_1);
+
+ GPIO_InitStruct(&GPIO_InitStructure);
+ /* Configure PA.01 PA.03 as analog input */
+ GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_3;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure);
#endif /* BSP_USING_ADC1 */
-#if defined(BSP_USING_ADC2)
+#ifdef BSP_USING_ADC2
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC2, ENABLE);
- /* Configure PC.02 PC.03 as analog input -------------------------*/
- GPIOInit(GPIOC, GPIO_Mode_AIN, GPIO_Speed_50MHz, GPIO_PIN_2 | GPIO_PIN_3);
- #endif /* BSP_USING_ADC2 */
-#if defined(BSP_USING_ADC3)
+ GPIO_InitStruct(&GPIO_InitStructure);
+ /* Configure PA.04 PA.05 as analog input */
+ GPIO_InitStructure.Pin = GPIO_PIN_4 | GPIO_PIN_5;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure);
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC3, ENABLE);
- /* Configure PD.10 PD.11 as analog input -------------------------*/
- GPIOInit(GPIOD, GPIO_Mode_AIN, GPIO_Speed_50MHz, GPIO_PIN_10 | GPIO_PIN_11);
+
+ GPIO_InitStruct(&GPIO_InitStructure);
+ /* Configure PB.11 PB.13 as analog input */
+ GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitPeripheral(GPIOB, &GPIO_InitStructure);
#endif /* BSP_USING_ADC3 */
-#if defined(BSP_USING_ADC4)
+#ifdef BSP_USING_ADC4
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC4, ENABLE);
- /* Configure PD.12 PD.13 as analog input -------------------------*/
- GPIOInit(GPIOD, GPIO_Mode_AIN, GPIO_Speed_50MHz, GPIO_PIN_12 | GPIO_PIN_13);
+
+ GPIO_InitStruct(&GPIO_InitStructure);
+ /* Configure PB.14 PB.15 as analog input */
+ GPIO_InitStructure.Pin = GPIO_PIN_14 | GPIO_PIN_15;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitPeripheral(GPIOB, &GPIO_InitStructure);
#endif /* BSP_USING_ADC4 */
/* RCC_ADCHCLK_DIV16*/
ADC_ConfigClk(ADC_CTRL3_CKMOD_AHB, RCC_ADCHCLK_DIV16);
+ /* Selsect HSE as RCC ADC1M CLK Source */
+ RCC_ConfigAdc1mClk(RCC_ADC1MCLK_SRC_HSE, RCC_ADC1MCLK_DIV8);
for (i = 0; i < sizeof(adc_obj) / sizeof(adc_obj[0]); i++)
{
@@ -180,7 +212,6 @@ int rt_hw_adc_init(void)
}
return result;
}
-
INIT_DEVICE_EXPORT(rt_hw_adc_init);
#endif /* defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3) || defined(BSP_USING_ADC4) */
diff --git a/bsp/n32/libraries/n32_drivers/drv_adc.h b/bsp/n32/libraries/n32_drivers/drv_adc.h
index 19d26b1165..01301f6c16 100644
--- a/bsp/n32/libraries/n32_drivers/drv_adc.h
+++ b/bsp/n32/libraries/n32_drivers/drv_adc.h
@@ -1,47 +1,25 @@
-/*****************************************************************************
- * Copyright (c) 2019, Nations Technologies Inc.
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
*
- * All rights reserved.
- * ****************************************************************************
+ * SPDX-License-Identifier: Apache-2.0
*
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Nations' name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ****************************************************************************/
-
-/**
- * @file drv_adc.h
- * @author Nations
- * @version v1.0.0
- *
- * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ * Change Logs:
+ * Date Author Notes
+ * 2022-10-19 Nations first version
*/
#ifndef __DRV_ADC__
#define __DRV_ADC__
+#include
#include
#include
-#include
-#include "n32g45x.h"
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
-/* n32g45x config class */
struct n32_adc_config
{
const char *name;
@@ -56,4 +34,8 @@ struct n32_adc
int rt_hw_adc_init(void);
+#ifdef __cplusplus
+}
#endif
+
+#endif /* __DRV_ADC__ */
diff --git a/bsp/n32/libraries/n32_drivers/drv_can.c b/bsp/n32/libraries/n32_drivers/drv_can.c
index f24aa5c923..6c63c02ae7 100644
--- a/bsp/n32/libraries/n32_drivers/drv_can.c
+++ b/bsp/n32/libraries/n32_drivers/drv_can.c
@@ -1,54 +1,34 @@
-/*****************************************************************************
- * Copyright (c) 2019, Nations Technologies Inc.
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
*
- * All rights reserved.
- * ****************************************************************************
+ * SPDX-License-Identifier: Apache-2.0
*
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Nations' name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ****************************************************************************/
-
-/**
- * @file drv_can.c
- * @author Nations
- * @version v1.0.0
- *
- * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ * Change Logs:
+ * Date Author Notes
+ * 2022-10-19 Nations first version
*/
#include
-#include "board.h"
#ifdef RT_USING_CAN
-#if defined(BSP_USING_CAN1) || defined(BSP_USING_CAN2)
- /* this driver can be disabled at menuconfig -> Hardware Drivers Config -> On-chip Peripheral Drivers -> Enable ADC */
+#if defined(BSP_USING_CAN) || defined(BSP_USING_CAN1) || defined(BSP_USING_CAN2)
-
-CanRxMessage RxMessage;
+#if defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
+#ifdef BSP_USING_CAN
+static struct n32_can drv_can =
+{
+ .name = "bxcan",
+ .CANx = CAN,
+};
+#endif
+#endif
#ifdef BSP_USING_CAN1
static struct n32_can drv_can1 =
{
.name = "bxcan1",
- .CanHandle.Instance = CAN1,
+ .CANx = CAN1,
};
#endif
@@ -56,160 +36,241 @@ static struct n32_can drv_can1 =
static struct n32_can drv_can2 =
{
.name = "bxcan2",
- .CanHandle.Instance = CAN2,
+ .CANx = CAN2,
};
#endif
-static rt_err_t setfilter(struct n32_can *pbxcan, CAN_FilterInitType *pconfig)
+#if defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
+#ifdef BSP_USING_CAN
+static void bxcan_hw_init(void)
{
- CAN_FilterInitType CAN_FilterInitStruct;
+ GPIO_InitType GPIO_InitStructure;
- CAN_Module* CANx;
- CANx = pbxcan->CanHandle.Instance;
+ RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_CAN, ENABLE);
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB | RCC_APB2_PERIPH_AFIO, ENABLE);
- CAN_FilterInitStruct.Filter_Num = pconfig->Filter_Num;
- CAN_FilterInitStruct.Filter_Mode = pconfig->Filter_Mode;
- CAN_FilterInitStruct.Filter_Scale = pconfig->Filter_Scale;
- CAN_FilterInitStruct.Filter_HighId = pconfig->Filter_HighId;
- CAN_FilterInitStruct.Filter_LowId = pconfig->Filter_LowId;
- CAN_FilterInitStruct.FilterMask_HighId = pconfig->FilterMask_HighId;;
- CAN_FilterInitStruct.FilterMask_LowId = pconfig->FilterMask_LowId;;
- CAN_FilterInitStruct.Filter_FIFOAssignment = pconfig->Filter_FIFOAssignment;;
- CAN_FilterInitStruct.Filter_Act = pconfig->Filter_Act;
- if(CANx == CAN1)
+ GPIO_InitStruct(&GPIO_InitStructure);
+
+ /* Configure CAN_TX PB9 and CAN_RX PB8 */
+ GPIO_InitStructure.Pin = GPIO_PIN_9;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitStructure.GPIO_Pull = GPIO_Pull_Up;
+ GPIO_InitStructure.GPIO_Alternate = GPIO_AF5_CAN;
+ GPIO_InitPeripheral(GPIOB, &GPIO_InitStructure);
+
+ GPIO_InitStructure.Pin = GPIO_PIN_8;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Input;
+ GPIO_InitPeripheral(GPIOB, &GPIO_InitStructure);
+}
+#endif
+#endif
+
+#ifdef BSP_USING_CAN1
+static void bxcan1_hw_init(void)
+{
+ GPIO_InitType GPIO_InitStructure;
+
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB | RCC_APB2_PERIPH_AFIO, ENABLE);
+ RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_CAN1, ENABLE);
+
+ GPIO_InitStruct(&GPIO_InitStructure);
+ /* Configure CAN1_TX PB9 and CAN1_RX PB8 */
+ GPIO_InitStructure.Pin = GPIO_PIN_8;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitPeripheral(GPIOB, &GPIO_InitStructure);
+
+ GPIO_InitStructure.Pin = GPIO_PIN_9;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitPeripheral(GPIOB, &GPIO_InitStructure);
+
+ /* Remap CAN1 GPIOs */
+ GPIO_ConfigPinRemap(GPIO_RMP2_CAN1, ENABLE);
+}
+#endif /* BSP_USING_CAN1 */
+
+#ifdef BSP_USING_CAN2
+static void bxcan2_hw_init(void)
+{
+ GPIO_InitType GPIO_InitStructure;
+
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
+ RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_CAN2, ENABLE);
+
+ GPIO_InitStruct(&GPIO_InitStructure);
+ /* Configure CAN2_TX PB13 and CAN2_RX PB12 */
+ GPIO_InitStructure.Pin = GPIO_PIN_12;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitPeripheral(GPIOB, &GPIO_InitStructure);
+
+ GPIO_InitStructure.Pin = GPIO_PIN_13;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitPeripheral(GPIOB, &GPIO_InitStructure);
+}
+#endif /* BSP_USING_CAN2 */
+
+
+/* baud calculation example: Tclk / ((ss + bs1 + bs2) * brp), 36 / ((1 + 8 + 3) * 3) = 1MHz*/
+#if defined(SOC_N32G45X) || defined(SOC_N32WB452) /* APB1 36MHz(max) */
+static const struct n32_baud_rate_tab can_baud_rate_tab[] =
+{
+ N32_CAN_BAUD_DEF(CAN1MBaud, CAN_RSJW_1tq, CAN_TBS1_5tq, CAN_TBS2_3tq, 4),
+ N32_CAN_BAUD_DEF(CAN800kBaud, CAN_RSJW_1tq, CAN_TBS1_5tq, CAN_TBS2_3tq, 5),
+ N32_CAN_BAUD_DEF(CAN500kBaud, CAN_RSJW_1tq, CAN_TBS1_5tq, CAN_TBS2_3tq, 8),
+ N32_CAN_BAUD_DEF(CAN250kBaud, CAN_RSJW_1tq, CAN_TBS1_5tq, CAN_TBS2_3tq, 16),
+ N32_CAN_BAUD_DEF(CAN125kBaud, CAN_RSJW_1tq, CAN_TBS1_5tq, CAN_TBS2_3tq, 32),
+ N32_CAN_BAUD_DEF(CAN100kBaud, CAN_RSJW_2tq, CAN_TBS1_9tq, CAN_TBS2_8tq, 20),
+ N32_CAN_BAUD_DEF(CAN50kBaud, CAN_RSJW_2tq, CAN_TBS1_9tq, CAN_TBS2_8tq, 40),
+ N32_CAN_BAUD_DEF(CAN20kBaud, CAN_RSJW_2tq, CAN_TBS1_9tq, CAN_TBS2_8tq, 100),
+ N32_CAN_BAUD_DEF(CAN10kBaud, CAN_RSJW_2tq, CAN_TBS1_9tq, CAN_TBS2_8tq, 200),
+};
+#endif /* SOC_N32G45X SOC_N32WB452 */
+
+#if defined(SOC_N32L43X) || defined(SOC_N32G43X) /* APB1 27MHz(max) */
+static const struct n32_baud_rate_tab can_baud_rate_tab[] =
+{
+ N32_CAN_BAUD_DEF(CAN1MBaud, CAN_RSJW_1tq, CAN_TBS1_6tq, CAN_TBS2_2tq, 3),
+ N32_CAN_BAUD_DEF(CAN500kBaud, CAN_RSJW_1tq, CAN_TBS1_6tq, CAN_TBS2_2tq, 6),
+ N32_CAN_BAUD_DEF(CAN250kBaud, CAN_RSJW_1tq, CAN_TBS1_9tq, CAN_TBS2_8tq, 6),
+ N32_CAN_BAUD_DEF(CAN125kBaud, CAN_RSJW_1tq, CAN_TBS1_9tq, CAN_TBS2_8tq, 12),
+ N32_CAN_BAUD_DEF(CAN100kBaud, CAN_RSJW_2tq, CAN_TBS1_5tq, CAN_TBS2_3tq, 30),
+ N32_CAN_BAUD_DEF(CAN50kBaud, CAN_RSJW_2tq, CAN_TBS1_5tq, CAN_TBS2_3tq, 60),
+ N32_CAN_BAUD_DEF(CAN20kBaud, CAN_RSJW_2tq, CAN_TBS1_5tq, CAN_TBS2_3tq, 150),
+ N32_CAN_BAUD_DEF(CAN10kBaud, CAN_RSJW_1tq, CAN_TBS1_9tq, CAN_TBS2_8tq, 150),
+};
+#endif /* SOC_N32L43X */
+
+#if defined(SOC_N32L40X) /* APB1 16MHz(max) */
+static const struct n32_baud_rate_tab can_baud_rate_tab[] =
+{
+ N32_CAN_BAUD_DEF(CAN1MBaud, CAN_RSJW_1tq, CAN_TBS1_5tq, CAN_TBS2_2tq, 2),
+ N32_CAN_BAUD_DEF(CAN800kBaud, CAN_RSJW_1tq, CAN_TBS1_2tq, CAN_TBS2_1tq, 5),
+ N32_CAN_BAUD_DEF(CAN500kBaud, CAN_RSJW_1tq, CAN_TBS1_5tq, CAN_TBS2_2tq, 4),
+ N32_CAN_BAUD_DEF(CAN250kBaud, CAN_RSJW_1tq, CAN_TBS1_5tq, CAN_TBS2_2tq, 8),
+ N32_CAN_BAUD_DEF(CAN125kBaud, CAN_RSJW_1tq, CAN_TBS1_5tq, CAN_TBS2_2tq, 16),
+ N32_CAN_BAUD_DEF(CAN100kBaud, CAN_RSJW_1tq, CAN_TBS1_5tq, CAN_TBS2_2tq, 20),
+ N32_CAN_BAUD_DEF(CAN50kBaud, CAN_RSJW_1tq, CAN_TBS1_5tq, CAN_TBS2_2tq, 40),
+ N32_CAN_BAUD_DEF(CAN20kBaud, CAN_RSJW_1tq, CAN_TBS1_5tq, CAN_TBS2_2tq, 100),
+ N32_CAN_BAUD_DEF(CAN10kBaud, CAN_RSJW_1tq, CAN_TBS1_9tq, CAN_TBS2_6tq, 100),
+};
+#endif /* SOC_N32L40X */
+
+static rt_uint32_t get_can_baud_index(rt_uint32_t baud)
+{
+ rt_uint32_t len, index;
+
+ len = sizeof(can_baud_rate_tab) / sizeof(can_baud_rate_tab[0]);
+ for(index = 0; index < len; index++)
{
- CAN1_InitFilter(&CAN_FilterInitStruct);
+ if (can_baud_rate_tab[index].baud_rate == baud)
+ return index;
}
+
+ return 0; /* default baud is CAN1MBaud */
+}
+
+static rt_err_t setfilter(struct n32_can *drv_can)
+{
+#if defined(SOC_N32G45X) || defined(SOC_N32WB452)
+ if (drv_can->CANx == CAN1)
+ {
+ CAN1_InitFilter(&(drv_can->FilterConfig));
+ }
+#ifdef CAN2
+ else if (drv_can->CANx == CAN2)
+ {
+ CAN2_InitFilter(&(drv_can->FilterConfig));
+ }
+#endif
+#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
+ if (drv_can->CANx == CAN)
+ {
+ CAN_InitFilter(&(drv_can->FilterConfig));
+ }
+#endif
else
{
- CAN2_InitFilter(&CAN_FilterInitStruct);
+ rt_kprintf("Can filter config error\n");
+ return -RT_EINVAL;
}
return RT_EOK;
}
-static void bxcan_init(struct rt_can_device *can, struct can_configure *cfg)
+static rt_err_t bxcan_init(struct rt_can_device *can, struct can_configure *cfg)
{
- CAN_InitType CAN_InitStructure;
-
struct n32_can *drv_can;
- CAN_Module *pbxcan;
+ rt_uint32_t baud_index;
+ RT_ASSERT(can);
+ RT_ASSERT(cfg);
drv_can = (struct n32_can *)can->parent.user_data;
- pbxcan = drv_can->CanHandle.Instance;
-
- uint32_t bps ;
-
- /* CAN register init */
- CAN_DeInit(pbxcan);
+ RT_ASSERT(drv_can);
/* Struct init*/
- CAN_InitStruct(&CAN_InitStructure);
- switch(cfg->baud_rate)
- {
- case CAN1MBaud:
- bps = CAN_BAUDRATE_1M;
- break;
- case CAN500kBaud:
- bps = CAN_BAUDRATE_500K;
- break;
- case CAN250kBaud:
- bps = CAN_BAUDRATE_250K;
- break;
- case CAN125kBaud:
- bps = CAN_BAUDRATE_125K;
- break;
- case CAN100kBaud:
- bps = CAN_BAUDRATE_100K;
- break;
- case CAN50kBaud:
- bps = CAN_BAUDRATE_50K;
- break;
- case CAN20kBaud:
- bps = CAN_BAUDRATE_20K;
- break;
- case CAN10kBaud:
- bps = CAN_BAUDRATE_10K;
- break;
+ CAN_InitStruct(&(drv_can->can_init));
- default:
- bps = CAN_BAUDRATE_100K;
- break;
- }
-
- CAN_InitStructure.BaudRatePrescaler = (uint32_t)(CAN_BTR_CALCULATE / bps);
+ drv_can->can_init.TTCM = DISABLE;
+ drv_can->can_init.ABOM = DISABLE;
+ drv_can->can_init.AWKUM = DISABLE;
+ drv_can->can_init.NART = DISABLE;
+ drv_can->can_init.RFLM = DISABLE;
+ drv_can->can_init.TXFP = ENABLE;
+ // Mode
switch (cfg->mode)
{
case RT_CAN_MODE_NORMAL:
- CAN_InitStructure.OperatingMode = CAN_Normal_Mode;
- break;
- case RT_CAN_MODE_LISEN:
- CAN_InitStructure.OperatingMode = CAN_Silent_Mode;
- break;
+ drv_can->can_init.OperatingMode = CAN_Normal_Mode;
+ break;
+
+ case RT_CAN_MODE_LISTEN:
+ drv_can->can_init.OperatingMode = CAN_Silent_Mode;
+ break;
+
case RT_CAN_MODE_LOOPBACK:
- CAN_InitStructure.OperatingMode = CAN_LoopBack_Mode;
- break;
- case RT_CAN_MODE_LOOPBACKANLISEN:
- CAN_InitStructure.OperatingMode = CAN_Silent_LoopBack_Mode;
- break;
+ drv_can->can_init.OperatingMode = CAN_LoopBack_Mode;
+ break;
+
+ case RT_CAN_MODE_LOOPBACKANLISTEN:
+ drv_can->can_init.OperatingMode = CAN_Silent_LoopBack_Mode;
+ break;
default:
- CAN_InitStructure.OperatingMode = CAN_Normal_Mode;
- break;
+ drv_can->can_init.OperatingMode = CAN_Normal_Mode;
+ break;
}
- CAN_InitStructure.TTCM = DISABLE;
- CAN_InitStructure.ABOM = DISABLE;
- CAN_InitStructure.AWKUM = DISABLE;
- CAN_InitStructure.NART = DISABLE;
- CAN_InitStructure.RFLM = DISABLE;
- CAN_InitStructure.TXFP = ENABLE;
+ // Baud
+ baud_index = get_can_baud_index(cfg->baud_rate);
+ drv_can->can_init.RSJW = can_baud_rate_tab[baud_index].RSJW;
+ drv_can->can_init.TBS1 = can_baud_rate_tab[baud_index].TBS1;
+ drv_can->can_init.TBS2 = can_baud_rate_tab[baud_index].TBS2;
+ drv_can->can_init.BaudRatePrescaler = can_baud_rate_tab[baud_index].PRESCALE;
- CAN_InitStructure.RSJW = CAN_RSJW_1tq;
- CAN_InitStructure.TBS1 = CAN_TBS1_3tq;
- CAN_InitStructure.TBS2 = CAN_TBS2_2tq;
+ /* init can */
+ if (CAN_Init(drv_can->CANx, &(drv_can->can_init)) != CAN_InitSTS_Success)
+ {
+ rt_kprintf("Can init error\n");
+ return -RT_ERROR;
+ }
- /*Initializes the CAN */
- CAN_Init(pbxcan, &CAN_InitStructure);
-
- /* CAN filter init */
- setfilter(drv_can, &drv_can->FilterConfig);
+ /* default filter config */
+ setfilter(drv_can);
+ return RT_EOK;
}
-#ifdef BSP_USING_CAN1
-static void bxcan1_hw_init(void)
-{
- /* Enable CAN1 reset state */
- RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_CAN1, ENABLE);
- RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
- GPIOInit(GPIOD, GPIO_Mode_IPU, GPIO_Speed_50MHz, GPIO_PIN_8);
- GPIOInit(GPIOD, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, GPIO_PIN_9);
- /* Remap CAN1 GPIOs */
- GPIO_ConfigPinRemap(GPIO_RMP1_CAN1, ENABLE);
-}
-#endif
-
-#ifdef BSP_USING_CAN2
-static void bxcan2_hw_init(void)
-{
- /* Enable CAN2 reset state */
- RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_CAN2, ENABLE);
- RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
- GPIOInit(GPIOB, GPIO_Mode_IPU, GPIO_Speed_50MHz, GPIO_PIN_12);
- GPIOInit(GPIOB, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, GPIO_PIN_13);
-}
-#endif
-
static rt_err_t configure(struct rt_can_device *can, struct can_configure *cfg)
{
struct n32_can *drv_can;
CAN_Module *pbxcan;
drv_can = (struct n32_can *)can->parent.user_data;
- pbxcan = drv_can->CanHandle.Instance;
+ pbxcan = drv_can->CANx;
+#if defined(SOC_N32G45X) || defined(SOC_N32WB452)
if (pbxcan == CAN1)
{
#ifdef BSP_USING_CAN1
@@ -224,6 +285,17 @@ static rt_err_t configure(struct rt_can_device *can, struct can_configure *cfg)
bxcan_init(&drv_can->device, &drv_can->device.config);
#endif
}
+#endif
+
+#if defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
+ if (pbxcan == CAN)
+ {
+#ifdef BSP_USING_CAN
+ bxcan_hw_init();
+ bxcan_init(&drv_can->device, &drv_can->device.config);
+#endif
+ }
+#endif
return RT_EOK;
}
@@ -236,9 +308,9 @@ void CAN_NVIC_Config(IRQn_Type IRQn, uint8_t PreemptionPriority, uint8_t SubPrio
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
- NVIC_InitStructure.NVIC_IRQChannel = IRQn;
- NVIC_InitStructure.NVIC_IRQChannelCmd = cmd;
- if(cmd)
+ NVIC_InitStructure.NVIC_IRQChannel = IRQn;
+ NVIC_InitStructure.NVIC_IRQChannelCmd = cmd;
+ if (cmd)
{
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = PreemptionPriority;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = SubPriority;
@@ -258,165 +330,265 @@ static rt_err_t control(struct rt_can_device *can, int cmd, void *arg)
switch (cmd)
{
- case RT_DEVICE_CTRL_CLR_INT:
- argval = (rt_uint32_t) arg;
+ case RT_DEVICE_CTRL_CLR_INT:
+ argval = (rt_uint32_t) arg;
if (argval == RT_DEVICE_FLAG_INT_RX)
{
- if (CAN1 == drv_can->CanHandle.Instance)
+#if defined(SOC_N32G45X) || defined(SOC_N32WB452)
+ if (CAN1 == drv_can->CANx)
{
- CAN_NVIC_Config(USB_LP_CAN1_RX0_IRQn, 1, 0, ENABLE);
- CAN_NVIC_Config(CAN1_RX1_IRQn, 1, 0, ENABLE);
+ NVIC_DisableIRQ(USB_LP_CAN1_RX0_IRQn);
+ NVIC_DisableIRQ(CAN1_RX1_IRQn);
}
#ifdef CAN2
- if (CAN2 == drv_can->CanHandle.Instance)
+ if (CAN2 == drv_can->CANx)
{
- CAN_NVIC_Config(CAN2_RX0_IRQn, 0, 0, DISABLE);
- CAN_NVIC_Config(CAN2_RX1_IRQn, 0, 0, DISABLE);
+ NVIC_DisableIRQ(CAN2_RX0_IRQn);
+ NVIC_DisableIRQ(CAN2_RX1_IRQn);
}
#endif
- CAN_INTConfig(drv_can->CanHandle.Instance, CAN_INT_FMP0, DISABLE);
- CAN_INTConfig(drv_can->CanHandle.Instance, CAN_INT_FF0, DISABLE);
- CAN_INTConfig(drv_can->CanHandle.Instance, CAN_INT_FOV0, DISABLE);
- CAN_INTConfig(drv_can->CanHandle.Instance, CAN_INT_FMP1, DISABLE);
- CAN_INTConfig(drv_can->CanHandle.Instance, CAN_INT_FF1, DISABLE);
- CAN_INTConfig(drv_can->CanHandle.Instance, CAN_INT_FOV1, DISABLE);
+#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
+ if (CAN == drv_can->CANx)
+ {
+ NVIC_DisableIRQ(CAN_RX0_IRQn);
+ NVIC_DisableIRQ(CAN_RX1_IRQn);
+ }
+#endif
+ CAN_INTConfig(drv_can->CANx, CAN_INT_FMP0, DISABLE); /* DATFIFO 0 message pending Interrupt */
+ CAN_INTConfig(drv_can->CANx, CAN_INT_FF0, DISABLE); /* DATFIFO 0 full Interrupt */
+ CAN_INTConfig(drv_can->CANx, CAN_INT_FOV0, DISABLE); /* DATFIFO 0 overrun Interrupt */
+ CAN_INTConfig(drv_can->CANx, CAN_INT_FMP1, DISABLE); /* DATFIFO 1 message pending Interrupt */
+ CAN_INTConfig(drv_can->CANx, CAN_INT_FF1, DISABLE); /* DATFIFO 1 full Interrupt */
+ CAN_INTConfig(drv_can->CANx, CAN_INT_FOV1, DISABLE); /* DATFIFO 1 overrun Interrupt */
}
else if (argval == RT_DEVICE_FLAG_INT_TX)
{
- if (CAN1 == drv_can->CanHandle.Instance)
+#if defined(SOC_N32G45X) || defined(SOC_N32WB452)
+ if (CAN1 == drv_can->CANx)
{
- CAN_NVIC_Config(USB_HP_CAN1_TX_IRQn, 0, 0, DISABLE);
+ NVIC_DisableIRQ(USB_HP_CAN1_TX_IRQn);
}
#ifdef CAN2
- if (CAN2 == drv_can->CanHandle.Instance)
+ if (CAN2 == drv_can->CANx)
{
- CAN_NVIC_Config(CAN2_TX_IRQn, 0, 0, DISABLE);
+ NVIC_DisableIRQ(CAN2_TX_IRQn);
}
#endif
- CAN_INTConfig(drv_can->CanHandle.Instance, CAN_INT_TME, DISABLE);
+#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
+ if (CAN == drv_can->CANx)
+ {
+ NVIC_DisableIRQ(CAN_TX_IRQn);
+ }
+#endif
+ CAN_INTConfig(drv_can->CANx, CAN_INT_TME, DISABLE); /* Transmit mailbox empty Interrupt */
}
else if (argval == RT_DEVICE_CAN_INT_ERR)
{
- if (CAN1 == drv_can->CanHandle.Instance)
+#if defined(SOC_N32G45X) || defined(SOC_N32WB452)
+ if (CAN1 == drv_can->CANx)
{
- CAN_NVIC_Config(CAN1_SCE_IRQn, 0, 0, DISABLE);
-
+ NVIC_DisableIRQ(CAN1_SCE_IRQn);
}
#ifdef CAN2
- if (CAN2 == drv_can->CanHandle.Instance)
+ if (CAN2 == drv_can->CANx)
{
- CAN_NVIC_Config(CAN2_SCE_IRQn, 0, 0, DISABLE);
+ NVIC_DisableIRQ(CAN2_SCE_IRQn);
}
#endif
- CAN_ClearFlag(drv_can->CanHandle.Instance, CAN_FLAG_EWGFL);
- CAN_ClearFlag(drv_can->CanHandle.Instance, CAN_FLAG_EPVFL);
- CAN_ClearFlag(drv_can->CanHandle.Instance, CAN_FLAG_BOFFL);
- CAN_ClearFlag(drv_can->CanHandle.Instance, CAN_FLAG_LEC);
- CAN_ClearINTPendingBit(drv_can->CanHandle.Instance, CAN_INT_ERR);
+#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
+ if (CAN == drv_can->CANx)
+ {
+ NVIC_DisableIRQ(CAN_SCE_IRQn);
+ }
+#endif
+ CAN_INTConfig(drv_can->CANx, CAN_INT_EWG, DISABLE); /* Error warning Interrupt */
+ CAN_INTConfig(drv_can->CANx, CAN_INT_EPV, DISABLE); /* Error passive Interrupt */
+ CAN_INTConfig(drv_can->CANx, CAN_INT_BOF, DISABLE); /* Bus-off Interrupt */
+ CAN_INTConfig(drv_can->CANx, CAN_INT_LEC, DISABLE); /* Last error code Interrupt */
+ CAN_INTConfig(drv_can->CANx, CAN_INT_ERR, DISABLE); /* Error Interrupt */
}
break;
- case RT_DEVICE_CTRL_SET_INT:
+
+ case RT_DEVICE_CTRL_SET_INT:
argval = (rt_uint32_t) arg;
if (argval == RT_DEVICE_FLAG_INT_RX)
{
- CAN_INTConfig(drv_can->CanHandle.Instance, CAN_INT_FMP0, ENABLE);
- CAN_INTConfig(drv_can->CanHandle.Instance, CAN_INT_FF0, ENABLE);
- CAN_INTConfig(drv_can->CanHandle.Instance, CAN_INT_FOV0, ENABLE);
- CAN_INTConfig(drv_can->CanHandle.Instance, CAN_INT_FMP1, ENABLE);
- CAN_INTConfig(drv_can->CanHandle.Instance, CAN_INT_FF1, ENABLE);
- CAN_INTConfig(drv_can->CanHandle.Instance, CAN_INT_FOV1, ENABLE);
+ CAN_INTConfig(drv_can->CANx, CAN_INT_FMP0, ENABLE); /* DATFIFO 0 message pending Interrupt */
+ CAN_INTConfig(drv_can->CANx, CAN_INT_FF0, ENABLE); /* DATFIFO 0 full Interrupt */
+ CAN_INTConfig(drv_can->CANx, CAN_INT_FOV0, ENABLE); /* DATFIFO 0 overrun Interrupt */
+ CAN_INTConfig(drv_can->CANx, CAN_INT_FMP1, ENABLE); /* DATFIFO 1 message pending Interrupt */
+ CAN_INTConfig(drv_can->CANx, CAN_INT_FF1, ENABLE); /* DATFIFO 1 full Interrupt */
+ CAN_INTConfig(drv_can->CANx, CAN_INT_FOV1, ENABLE); /* DATFIFO 1 overrun Interrupt */
- if (CAN1 == drv_can->CanHandle.Instance)
+#if defined(SOC_N32G45X) || defined(SOC_N32WB452)
+ if (CAN1 == drv_can->CANx)
{
CAN_NVIC_Config(USB_LP_CAN1_RX0_IRQn, 1, 0, ENABLE);
CAN_NVIC_Config(CAN1_RX1_IRQn, 1, 0, ENABLE);
}
#ifdef CAN2
- if (CAN2 == drv_can->CanHandle.Instance)
+ if (CAN2 == drv_can->CANx)
{
CAN_NVIC_Config(CAN2_RX0_IRQn, 1, 0, ENABLE);
CAN_NVIC_Config(CAN2_RX1_IRQn, 1, 0, ENABLE);
}
+#endif
+#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
+ if (CAN == drv_can->CANx)
+ {
+ CAN_NVIC_Config(CAN_RX0_IRQn, 1, 0, ENABLE);
+ CAN_NVIC_Config(CAN_RX1_IRQn, 1, 0, ENABLE);
+ }
#endif
}
else if (argval == RT_DEVICE_FLAG_INT_TX)
{
- CAN_INTConfig(drv_can->CanHandle.Instance, CAN_INT_TME, ENABLE);
+ CAN_INTConfig(drv_can->CANx, CAN_INT_TME, ENABLE); /* Transmit mailbox empty Interrupt */
- if (CAN1 == drv_can->CanHandle.Instance)
+#if defined(SOC_N32G45X) || defined(SOC_N32WB452)
+ if (CAN1 == drv_can->CANx)
{
CAN_NVIC_Config(USB_HP_CAN1_TX_IRQn, 1, 0, ENABLE);
}
#ifdef CAN2
- if (CAN2 == drv_can->CanHandle.Instance)
+ if (CAN2 == drv_can->CANx)
{
CAN_NVIC_Config(CAN2_TX_IRQn, 1, 0, ENABLE);
}
+#endif
+#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
+ if (CAN == drv_can->CANx)
+ {
+ CAN_NVIC_Config(CAN_TX_IRQn, 1, 0, ENABLE);
+ }
#endif
}
else if (argval == RT_DEVICE_CAN_INT_ERR)
{
- CAN_INTConfig(drv_can->CanHandle.Instance, CAN_INT_EWG, ENABLE);
- CAN_INTConfig(drv_can->CanHandle.Instance, CAN_INT_EPV, ENABLE);
- CAN_INTConfig(drv_can->CanHandle.Instance, CAN_INT_BOF, ENABLE);
- CAN_INTConfig(drv_can->CanHandle.Instance, CAN_INT_LEC, ENABLE);
- CAN_INTConfig(drv_can->CanHandle.Instance, CAN_INT_ERR, ENABLE);
+ CAN_INTConfig(drv_can->CANx, CAN_INT_EWG, ENABLE); /* Error warning Interrupt */
+ CAN_INTConfig(drv_can->CANx, CAN_INT_EPV, ENABLE); /* Error passive Interrupt */
+ CAN_INTConfig(drv_can->CANx, CAN_INT_BOF, ENABLE); /* Bus-off Interrupt */
+ CAN_INTConfig(drv_can->CANx, CAN_INT_LEC, ENABLE); /* Last error code Interrupt */
+ CAN_INTConfig(drv_can->CANx, CAN_INT_ERR, ENABLE); /* Error Interrupt */
- if (CAN1 == drv_can->CanHandle.Instance)
+#if defined(SOC_N32G45X) || defined(SOC_N32WB452)
+ if (CAN1 == drv_can->CANx)
{
CAN_NVIC_Config(CAN1_SCE_IRQn, 1, 0, ENABLE);
}
#ifdef CAN2
- if (CAN2 == drv_can->CanHandle.Instance)
+ if (CAN2 == drv_can->CANx)
{
CAN_NVIC_Config(CAN2_SCE_IRQn, 1, 0, ENABLE);
}
#endif
- }
- break;
- case RT_CAN_CMD_SET_FILTER:
- if (RT_NULL == arg)
- {
- /* default filter config */
- setfilter(drv_can, &drv_can->FilterConfig);
- }
- else
- {
- filter_cfg = (struct rt_can_filter_config *)arg;
- /* get default filter */
- for (int i = 0; i < filter_cfg->count; i++)
+#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
+ if (CAN == drv_can->CANx)
{
- drv_can->FilterConfig.Filter_Num = filter_cfg->items[i].hdr;
- drv_can->FilterConfig.Filter_HighId = (filter_cfg->items[i].id >> 13) & 0xFFFF;
- drv_can->FilterConfig.Filter_LowId = ((filter_cfg->items[i].id << 3) |
- (filter_cfg->items[i].ide << 2) |
- (filter_cfg->items[i].rtr << 1)) & 0xFFFF;
- drv_can->FilterConfig.FilterMask_HighId = (filter_cfg->items[i].mask >> 16) & 0xFFFF;
- drv_can->FilterConfig.FilterMask_LowId = filter_cfg->items[i].mask & 0xFFFF;
- drv_can->FilterConfig.Filter_Mode = filter_cfg->items[i].mode;
- /* Filter conf */
- setfilter(drv_can, &drv_can->FilterConfig);
+ CAN_NVIC_Config(CAN_SCE_IRQn, 1, 0, ENABLE);
}
+#endif
}
break;
- case RT_CAN_CMD_SET_MODE:
- argval = (rt_uint32_t) arg;
- if (argval != RT_CAN_MODE_NORMAL &&
- argval != RT_CAN_MODE_LISEN &&
+
+ case RT_CAN_CMD_SET_FILTER:
+ {
+ rt_uint32_t id_h = 0;
+ rt_uint32_t id_l = 0;
+ rt_uint32_t mask_h = 0;
+ rt_uint32_t mask_l = 0;
+ rt_uint32_t mask_l_tail = 0; //CAN_FxR2 bit [2:0]
+
+ if (RT_NULL == arg)
+ {
+ /* Default filter config */
+ setfilter(drv_can);
+ }
+ else
+ {
+ filter_cfg = (struct rt_can_filter_config *)arg;
+ /* Get default filter */
+ for(int i = 0; i < filter_cfg->count; i++)
+ {
+ if (filter_cfg->items[i].hdr == -1)
+ {
+ /* Can banks 0~13 */
+ drv_can->FilterConfig.Filter_Num = i;
+ }
+ else
+ {
+ /* Use user-defined filter bank settings */
+ drv_can->FilterConfig.Filter_Num = filter_cfg->items[i].hdr;
+ }
+
+ /* Filter groups work in identifier masking bit mode */
+ if (filter_cfg->items[i].mode == CAN_Filter_IdMaskMode)
+ {
+ /* make sure the IDE and RTR work */
+ mask_l_tail = 0x06;
+ drv_can->FilterConfig.Filter_Mode = CAN_Filter_IdMaskMode;
+ }
+ /* Filter groups work in identifier list mode */
+ else if (filter_cfg->items[i].mode == CAN_Filter_IdListMode)
+ {
+ mask_l_tail = (filter_cfg->items[i].ide << 2) | (filter_cfg->items[i].rtr << 1);
+ drv_can->FilterConfig.Filter_Mode = CAN_Filter_IdListMode;
+ }
+
+ if (filter_cfg->items[i].ide == RT_CAN_STDID)
+ {
+ id_h = ((filter_cfg->items[i].id << 18) >> 13) & 0xFFFF;
+ id_l = ((filter_cfg->items[i].id << 18) |
+ (filter_cfg->items[i].ide << 2) |
+ (filter_cfg->items[i].rtr << 1)) & 0xFFFF;
+ mask_h = ((filter_cfg->items[i].mask << 21) >> 16) & 0xFFFF;
+ mask_l = ((filter_cfg->items[i].mask << 21) | mask_l_tail) & 0xFFFF;
+ }
+ else if (filter_cfg->items[i].ide == RT_CAN_EXTID)
+ {
+ id_h = (filter_cfg->items[i].id >> 13) & 0xFFFF;
+ id_l = ((filter_cfg->items[i].id << 3) |
+ (filter_cfg->items[i].ide << 2) |
+ (filter_cfg->items[i].rtr << 1)) & 0xFFFF;
+ mask_h = ((filter_cfg->items[i].mask << 3) >> 16) & 0xFFFF;
+ mask_l = ((filter_cfg->items[i].mask << 3) | mask_l_tail) & 0xFFFF;
+ }
+
+ drv_can->FilterConfig.Filter_HighId = id_h;
+ drv_can->FilterConfig.Filter_LowId = id_l;
+ drv_can->FilterConfig.FilterMask_HighId = mask_h;
+ drv_can->FilterConfig.FilterMask_LowId = mask_l;
+ drv_can->FilterConfig.Filter_FIFOAssignment = CAN_FIFO0;
+ drv_can->FilterConfig.Filter_Scale = CAN_Filter_32bitScale;
+ drv_can->FilterConfig.Filter_Act = ENABLE;
+
+ /* Filter conf */
+ setfilter(drv_can);
+ }
+ }
+ break;
+ }
+
+ case RT_CAN_CMD_SET_MODE:
+ argval = (rt_uint32_t) arg;
+ if (argval != RT_CAN_MODE_NORMAL &&
+ argval != RT_CAN_MODE_LISTEN &&
argval != RT_CAN_MODE_LOOPBACK &&
- argval != RT_CAN_MODE_LOOPBACKANLISEN)
- {
- return -RT_ERROR;
- }
- if (argval != drv_can->device.config.mode)
- {
- drv_can->device.config.mode = argval;
- return configure(&drv_can->device, &drv_can->device.config);
- }
+ argval != RT_CAN_MODE_LOOPBACKANLISTEN)
+ {
+ return -RT_ERROR;
+ }
+ if (argval != drv_can->device.config.mode)
+ {
+ drv_can->device.config.mode = argval;
+ return configure(&drv_can->device, &drv_can->device.config);
+ }
break;
- case RT_CAN_CMD_SET_BAUD:
- argval = (rt_uint32_t) arg;
- if (argval != CAN1MBaud &&
+
+ case RT_CAN_CMD_SET_BAUD:
+ argval = (rt_uint32_t) arg;
+ if (argval != CAN1MBaud &&
+ argval != CAN800kBaud &&
argval != CAN500kBaud &&
argval != CAN250kBaud &&
argval != CAN125kBaud &&
@@ -424,97 +596,280 @@ static rt_err_t control(struct rt_can_device *can, int cmd, void *arg)
argval != CAN50kBaud &&
argval != CAN20kBaud &&
argval != CAN10kBaud)
- {
- return -RT_ERROR;
- }
- if (argval != drv_can->device.config.baud_rate)
- {
- drv_can->device.config.baud_rate = argval;
- return configure(&drv_can->device, &drv_can->device.config);
- }
- break;
- case RT_CAN_CMD_SET_PRIV:
- argval = (rt_uint32_t) arg;
- if (argval != RT_CAN_MODE_PRIV &&
+ {
+ return -RT_ERROR;
+ }
+ if (argval != drv_can->device.config.baud_rate)
+ {
+ drv_can->device.config.baud_rate = argval;
+ return configure(&drv_can->device, &drv_can->device.config);
+ }
+ break;
+
+ case RT_CAN_CMD_SET_PRIV:
+ argval = (rt_uint32_t) arg;
+ if (argval != RT_CAN_MODE_PRIV &&
argval != RT_CAN_MODE_NOPRIV)
+ {
+ return -RT_ERROR;
+ }
+ if (argval != drv_can->device.config.privmode)
+ {
+ drv_can->device.config.privmode = argval;
+ return configure(&drv_can->device, &drv_can->device.config);
+ }
+ break;
+
+ case RT_CAN_CMD_GET_STATUS:
+ {
+ rt_uint32_t errtype;
+ errtype = drv_can->CANx->ESTS;
+ drv_can->device.status.rcverrcnt = errtype >> 24;
+ drv_can->device.status.snderrcnt = (errtype >> 16 & 0xFF);
+ drv_can->device.status.lasterrtype = errtype & 0x70;
+ drv_can->device.status.errcode = errtype & 0x07;
+
+ rt_memcpy(arg, &drv_can->device.status, sizeof(drv_can->device.status));
+ }
+ break;
+ }
+ return RT_EOK;
+}
+
+/* CAN Mailbox Transmit Request */
+#define TMIDxR_TXRQ ((uint32_t)0x00000001)
+
+static int can_sendmsg_rtmsg(CAN_Module *CANx, struct rt_can_msg *pmsg, uint32_t mailbox_index)
+{
+ CanTxMessage CAN_TxMessage = {0};
+ CanTxMessage *TxMessage = &CAN_TxMessage;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ if (RT_CAN_STDID == pmsg->ide)
+ {
+ TxMessage->IDE = CAN_Standard_Id;
+ RT_ASSERT(IS_CAN_STDID(pmsg->id));
+ TxMessage->StdId = pmsg->id;
+ }
+ else
+ {
+ TxMessage->IDE = CAN_Extended_Id;
+ RT_ASSERT(IS_CAN_EXTID(pmsg->id));
+ TxMessage->ExtId = pmsg->id;
+ }
+
+ if (RT_CAN_DTR == pmsg->rtr)
+ {
+ TxMessage->RTR = CAN_RTRQ_DATA;
+ }
+ else
+ {
+ TxMessage->RTR = CAN_RTRQ_REMOTE;
+ }
+
+ if (mailbox_index != CAN_TxSTS_NoMailBox)
+ {
+ /* Set up the Id */
+ CANx->sTxMailBox[mailbox_index].TMI &= TMIDxR_TXRQ;
+ if (TxMessage->IDE == CAN_Standard_Id)
+ {
+ assert_param(IS_CAN_STDID(TxMessage->StdId));
+ CANx->sTxMailBox[mailbox_index].TMI |= ((TxMessage->StdId << 21) | TxMessage->RTR);
+ }
+ else
+ {
+ assert_param(IS_CAN_EXTID(TxMessage->ExtId));
+ CANx->sTxMailBox[mailbox_index].TMI |= ((TxMessage->ExtId << 3) | TxMessage->IDE | TxMessage->RTR);
+ }
+
+ /* Set up the DLC */
+ TxMessage->DLC = pmsg->len & 0x0FU;
+ CANx->sTxMailBox[mailbox_index].TMDT &= (uint32_t)0xFFFFFFF0;
+ CANx->sTxMailBox[mailbox_index].TMDT |= TxMessage->DLC;
+
+ /* Set up the data field */
+ CANx->sTxMailBox[mailbox_index].TMDH = (((uint32_t)pmsg->data[7] << 24) |
+ ((uint32_t)pmsg->data[6] << 16) |
+ ((uint32_t)pmsg->data[5] << 8) |
+ ((uint32_t)pmsg->data[4]));
+ CANx->sTxMailBox[mailbox_index].TMDL = (((uint32_t)pmsg->data[3] << 24) |
+ ((uint32_t)pmsg->data[2] << 16) |
+ ((uint32_t)pmsg->data[1] << 8) |
+ ((uint32_t)pmsg->data[0]));
+ /* Request transmission */
+ CANx->sTxMailBox[mailbox_index].TMI |= TMIDxR_TXRQ;
+
+ return RT_EOK;
+ }
+ return -RT_ERROR;
+}
+
+static int sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num)
+{
+ struct n32_can *drv_can;
+
+ RT_ASSERT(can != RT_NULL);
+ RT_ASSERT(buf != RT_NULL);
+ drv_can = (struct n32_can *)can->parent.user_data;
+ RT_ASSERT(drv_can != RT_NULL);
+
+ /* Select one empty transmit mailbox */
+ switch (box_num)
+ {
+ case 0:
+ if ((drv_can->CANx->TSTS & CAN_TSTS_TMEM0) != CAN_TSTS_TMEM0)
+ {
+ /* Return function status */
+ return -RT_ERROR;
+ }
+ break;
+ case 1:
+ if ((drv_can->CANx->TSTS & CAN_TSTS_TMEM1) != CAN_TSTS_TMEM1)
+ {
+ /* Return function status */
+ return -RT_ERROR;
+ }
+ break;
+ case 2:
+ if ((drv_can->CANx->TSTS & CAN_TSTS_TMEM2) != CAN_TSTS_TMEM2)
+ {
+ /* Return function status */
+ return -RT_ERROR;
+ }
+ break;
+ default:
+ RT_ASSERT(0);
+ break;
+ }
+
+ // Start send msg
+ return can_sendmsg_rtmsg(drv_can->CANx, ((struct rt_can_msg *)buf), box_num);
+}
+
+static int can_recvmsg_rtmsg(CAN_Module *CANx, struct rt_can_msg *pmsg, uint32_t FIFONum)
+{
+ CanRxMessage CAN_RxMessage = {0};
+ CanRxMessage *RxMessage = &CAN_RxMessage;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FIFO(FIFONum));
+
+ /* Check the Rx FIFO */
+ if (FIFONum == CAN_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
+ {
+ /* Check that the Rx FIFO 0 is not empty */
+ if ((CANx->RFF0 & CAN_RFF0_FFMP0) == 0U)
{
return -RT_ERROR;
}
- if (argval != drv_can->device.config.privmode)
+ }
+ else /* Rx element is assigned to Rx FIFO 1 */
+ {
+ /* Check that the Rx FIFO 1 is not empty */
+ if ((CANx->RFF1 & CAN_RFF1_FFMP1) == 0U)
{
- drv_can->device.config.privmode = argval;
- return configure(&drv_can->device, &drv_can->device.config);
+ return -RT_ERROR;
}
- break;
- case RT_CAN_CMD_GET_STATUS:
- {
- rt_uint32_t errtype;
- errtype = drv_can->CanHandle.Instance->ESTS;
- drv_can->device.status.rcverrcnt = errtype >> 24;
- drv_can->device.status.snderrcnt = (errtype >> 16 & 0xFF);
- drv_can->device.status.lasterrtype = errtype & 0x70;
- drv_can->device.status.errcode = errtype & 0x07;
-
- rt_memcpy(arg, &drv_can->device.status, sizeof(drv_can->device.status));
- }
- break;
}
- return RT_EOK;
-}
-
-static int sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno)
-{
- CAN_Module *pbxcan;
- CanTxMessage TxMessage;
- struct rt_can_msg *pmsg = (struct rt_can_msg *) buf;
- int i;
-
- pbxcan = ((struct n32_can *) can->parent.user_data)->CanHandle.Instance;
-
- if(pmsg->ide)
+ /* Get the Id */
+ RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONum].RMI;
+ if (RxMessage->IDE == CAN_Standard_Id)
{
- TxMessage.ExtId = pmsg->id;
- TxMessage.StdId = 0;
+ RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONum].RMI >> 21);
}
else
{
- TxMessage.StdId = pmsg->id;
- TxMessage.ExtId = 0;
+ RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONum].RMI >> 3);
}
- TxMessage.RTR = pmsg->rtr;
- TxMessage.IDE = pmsg->ide;
- TxMessage.DLC = pmsg->len;
- for( i=0; iRTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONum].RMI;
+ /* Get the DLC */
+ RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONum].RMDT;
+ /* Get the FMI */
+ RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDT >> 8);
+
+ /* Get the data field */
+ pmsg->data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONum].RMDL;
+ pmsg->data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDL >> 8);
+ pmsg->data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDL >> 16);
+ pmsg->data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDL >> 24);
+ pmsg->data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONum].RMDH;
+ pmsg->data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDH >> 8);
+ pmsg->data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDH >> 16);
+ pmsg->data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDH >> 24);
+
+ /* get len */
+ pmsg->len = RxMessage->DLC;
+
+ /* get id */
+ if (RxMessage->IDE == CAN_Standard_Id)
{
- TxMessage.Data[i] = pmsg->data[i];
+ pmsg->ide = RT_CAN_STDID;
+ pmsg->id = RxMessage->StdId;
+ }
+ else
+ {
+ pmsg->ide = RT_CAN_EXTID;
+ pmsg->id = RxMessage->ExtId;
+ }
+ /* get type */
+ if (CAN_RTRQ_Data == RxMessage->RTR)
+ {
+ pmsg->rtr = RT_CAN_DTR;
+ }
+ else
+ {
+ pmsg->rtr = RT_CAN_RTR;
}
- CAN_TransmitMessage(pbxcan, &TxMessage);
+ /* get hdr */
+#if defined(SOC_N32G45X) || defined(SOC_N32WB452)
+ if (CANx == CAN1)
+ {
+ pmsg->hdr = (RxMessage->FMI + 1) >> 1;
+ }
+#ifdef CAN2
+ else if (CANx == CAN2)
+ {
+ pmsg->hdr = (RxMessage->FMI + 1) >> 1;
+ }
+#endif
+#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
+ if (CANx == CAN)
+ {
+ pmsg->hdr = (RxMessage->FMI + 1) >> 1;
+ }
+#endif
+
+ /* Release the DATFIFO */
+ /* Release FIFO0 */
+ if (FIFONum == CAN_FIFO0)
+ {
+ CANx->RFF0 |= CAN_RFF0_RFFOM0;
+ }
+ /* Release FIFO1 */
+ else /* FIFONum == CAN_FIFO1 */
+ {
+ CANx->RFF1 |= CAN_RFF1_RFFOM1;
+ }
return RT_EOK;
}
-static int recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno)
+static int recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo)
{
- struct rt_can_msg *pmsg = (struct rt_can_msg *) buf;
- int i;
+ struct n32_can *drv_can;
- pmsg->ide = (rt_uint32_t) RxMessage.IDE;
- if(RxMessage.IDE == 1)
- pmsg->id = RxMessage.ExtId;
- else
- pmsg->id = RxMessage.StdId;
- pmsg->len = RxMessage.DLC;
- pmsg->rtr = RxMessage.RTR;
- pmsg->hdr = 0;
- for(i= 0;i< RxMessage.DLC; i++)
- {
- pmsg->data[i] = RxMessage.Data[i];
- }
+ RT_ASSERT(can != RT_NULL);
+ RT_ASSERT(buf != RT_NULL);
+ drv_can = (struct n32_can *)can->parent.user_data;
+ RT_ASSERT(drv_can != RT_NULL);
-
- return RT_EOK;
+ /* Get data */
+ return can_recvmsg_rtmsg(drv_can->CANx, ((struct rt_can_msg *)buf), fifo);
}
static const struct rt_can_ops canops =
@@ -525,46 +880,79 @@ static const struct rt_can_ops canops =
recvmsg,
};
-#ifdef BSP_USING_CAN1
-
-struct rt_can_device bxcan1;
-
-void n32_can1_irqhandler(void *param)
+static void can_rx_isr(struct rt_can_device *can, rt_uint32_t fifo)
{
- CAN_Module* CANx;
+ struct n32_can *drv_can;
+ RT_ASSERT(can != RT_NULL);
+ drv_can = (struct n32_can *)can->parent.user_data;
+ RT_ASSERT(drv_can != RT_NULL);
- CANx = CAN1;
+ switch (fifo)
+ {
+ case CAN_FIFO0:
+ /* save to user list */
+ if (CAN_GetFlagSTS(drv_can->CANx, CAN_FLAG_FFMP0) && CAN_PendingMessage(drv_can->CANx, CAN_FIFO0))
+ {
+ rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8);
+ }
+ /* Check FULL flag for FIFO0 */
+ if (CAN_GetFlagSTS(drv_can->CANx, CAN_FLAG_FFULL0))
+ {
+ /* Clear FIFO0 FULL Flag */
+ CAN_ClearFlag(drv_can->CANx, CAN_FLAG_FFULL0);
+ }
+ /* Check Overrun flag for FIFO0 */
+ if (CAN_GetFlagSTS(drv_can->CANx, CAN_FLAG_FFOVR0))
+ {
+ /* Clear FIFO0 Overrun Flag */
+ CAN_ClearFlag(drv_can->CANx, CAN_FLAG_FFOVR0);
+ rt_hw_can_isr(can, RT_CAN_EVENT_RXOF_IND | fifo << 8);
+ }
+ break;
- /* receive data interrupt */
- if (CAN_GetIntStatus(CANx, CAN_INT_FMP0))
- {
- CAN_ReceiveMessage(CANx, CAN_FIFO0, &RxMessage);
- rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_RX_IND);
- CAN_ClearINTPendingBit(CANx, CAN_INT_FMP0);
- rt_kprintf("\r\nCan1 int RX happened!\r\n");
- }
- /* send data interrupt */
- else if (CAN_GetFlagSTS(CANx, CAN_FLAG_RQCPM0))
- {
- rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_DONE | 0 << 8);
- CAN_ClearFlag(CANx, CAN_FLAG_RQCPM0);
- }
- /* data overflow interrupt */
- else if (CAN_GetIntStatus(CANx, CAN_INT_FOV0))
- {
- rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_RXOF_IND);
- rt_kprintf("\r\nCan1 int RX OF happened!\r\n");
+ case CAN_FIFO1:
+ /* save to user list */
+ if (CAN_GetFlagSTS(drv_can->CANx, CAN_FLAG_FFMP1) && CAN_PendingMessage(drv_can->CANx, CAN_FIFO1))
+ {
+ rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8);
+ }
+ /* Check FULL flag for FIFO1 */
+ if (CAN_GetFlagSTS(drv_can->CANx, CAN_FLAG_FFULL1))
+ {
+ /* Clear FIFO1 FULL Flag */
+ CAN_ClearFlag(drv_can->CANx, CAN_FLAG_FFULL1);
+ }
+ /* Check Overrun flag for FIFO1 */
+ if (CAN_GetFlagSTS(drv_can->CANx, CAN_FLAG_FFOVR1))
+ {
+ /* Clear FIFO1 Overrun Flag */
+ CAN_ClearFlag(drv_can->CANx, CAN_FLAG_FFOVR1);
+ rt_hw_can_isr(can, RT_CAN_EVENT_RXOF_IND | fifo << 8);
+ }
+ break;
}
}
+#ifdef BSP_USING_CAN1
void USB_HP_CAN1_TX_IRQHandler(void)
{
- /* enter interrupt */
rt_interrupt_enter();
- n32_can1_irqhandler(&drv_can1.device);
-
- /* leave interrupt */
+ if (CAN_GetFlagSTS(drv_can1.CANx, CAN_FLAG_RQCPM0))
+ {
+ rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_DONE | (0x00 << 8));
+ CAN_ClearFlag(drv_can1.CANx, CAN_FLAG_RQCPM0);
+ }
+ if (CAN_GetFlagSTS(drv_can1.CANx, CAN_FLAG_RQCPM1))
+ {
+ rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_DONE | (0x01 << 8));
+ CAN_ClearFlag(drv_can1.CANx, CAN_FLAG_RQCPM1);
+ }
+ if (CAN_GetFlagSTS(drv_can1.CANx, CAN_FLAG_RQCPM2))
+ {
+ rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_DONE | (0x02 << 8));
+ CAN_ClearFlag(drv_can1.CANx, CAN_FLAG_RQCPM2);
+ }
rt_interrupt_leave();
}
@@ -573,123 +961,341 @@ void USB_LP_CAN1_RX0_IRQHandler(void)
/* enter interrupt */
rt_interrupt_enter();
- n32_can1_irqhandler(&drv_can1.device);
+ can_rx_isr(&drv_can1.device, CAN_FIFO0);
/* leave interrupt */
rt_interrupt_leave();
}
-#endif /*BSP_USING_CAN1*/
-
-#ifdef BSP_USING_CAN2
-struct rt_can_device bxcan2;
-void n32_can2_irqhandler(void *param)
-{
- CAN_Module* CANx;
-
- CANx = CAN2;
-
- /* receive data interrupt */
- if (CAN_GetIntStatus(CANx, CAN_INT_FMP0))
- {
- CAN_ReceiveMessage(CANx, CAN_FIFO0, &RxMessage);
- rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_RX_IND);
- CAN_ClearINTPendingBit(CANx, CAN_INT_FMP0);
- rt_kprintf("\r\nCan2 int RX happened!\r\n");
- }
- /* send data interrupt */
- else if (CAN_GetFlagSTS(CANx, CAN_FLAG_RQCPM0))
- {
- rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_DONE | 0 << 8);
- CAN_ClearFlag(CANx, CAN_FLAG_RQCPM0);
- }
- /* data overflow interrupt */
- else if (CAN_GetIntStatus(CANx, CAN_INT_FOV0))
- {
- rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_RXOF_IND);
- rt_kprintf("\r\nCan2 int RX OF happened!\r\n");
- }
-}
-
-void CAN2_TX_IRQHandler(void)
+void CAN1_RX1_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
- n32_can2_irqhandler(&drv_can2.device);
+ can_rx_isr(&drv_can1.device, CAN_FIFO1);
/* leave interrupt */
rt_interrupt_leave();
}
+void CAN1_SCE_IRQHandler(void)
+{
+ uint32_t errtype;
+ rt_interrupt_enter();
+
+ if (CAN_GetIntStatus(drv_can1.CANx, CAN_INT_ERR))
+ {
+ errtype = drv_can1.CANx->ESTS;
+ /* ESTS -> LEC */
+ switch ((errtype & 0x70) >> 4)
+ {
+ case RT_CAN_BUS_BIT_PAD_ERR:
+ break;
+
+ case RT_CAN_BUS_FORMAT_ERR:
+ drv_can1.device.status.formaterrcnt++;
+ break;
+
+ case RT_CAN_BUS_ACK_ERR:
+ drv_can1.device.status.ackerrcnt++;
+ if (!READ_BIT(drv_can1.CANx->TSTS, CAN_TSTS_TXOKM0))
+ {
+ rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 0 << 8);
+ }
+ else if (!READ_BIT(drv_can1.CANx->TSTS, CAN_TSTS_TXOKM1))
+ {
+ rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 1 << 8);
+ }
+ else if (!READ_BIT(drv_can1.CANx->TSTS, CAN_TSTS_TXOKM2))
+ {
+ rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 2 << 8);
+ }
+ break;
+
+ case RT_CAN_BUS_IMPLICIT_BIT_ERR:
+ case RT_CAN_BUS_EXPLICIT_BIT_ERR:
+ drv_can1.device.status.biterrcnt++;
+ break;
+
+ case RT_CAN_BUS_CRC_ERR:
+ drv_can1.device.status.crcerrcnt++;
+ break;
+ }
+
+ drv_can1.device.status.lasterrtype = errtype & 0x70;
+ drv_can1.device.status.rcverrcnt = errtype >> 24;
+ drv_can1.device.status.snderrcnt = (errtype >> 16 & 0xFF);
+ drv_can1.device.status.errcode = errtype & 0x07;
+
+ CAN_ClearINTPendingBit(drv_can1.CANx, CAN_INT_ERR);
+ }
+ rt_interrupt_leave();
+}
+#endif /*BSP_USING_CAN1*/
+
+#ifdef BSP_USING_CAN2
+void CAN2_TX_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ if (CAN_GetFlagSTS(drv_can2.CANx, CAN_FLAG_RQCPM0))
+ {
+ CAN_ClearFlag(drv_can2.CANx, CAN_FLAG_RQCPM0);
+ rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_DONE | (0x00 << 8));
+ }
+ if (CAN_GetFlagSTS(drv_can2.CANx, CAN_FLAG_RQCPM1))
+ {
+ CAN_ClearFlag(drv_can2.CANx, CAN_FLAG_RQCPM1);
+ rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_DONE | (0x01 << 8));
+ }
+ if (CAN_GetFlagSTS(drv_can2.CANx, CAN_FLAG_RQCPM2))
+ {
+ CAN_ClearFlag(drv_can2.CANx, CAN_FLAG_RQCPM2);
+ rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_DONE | (0x02 << 8));
+ }
+ rt_interrupt_leave();
+}
+
void CAN2_RX0_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
- n32_can2_irqhandler(&drv_can2.device);
+ can_rx_isr(&drv_can2.device, CAN_FIFO0);
/* leave interrupt */
rt_interrupt_leave();
}
-#endif /*BSP_USING_CAN2*/
+void CAN2_RX1_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
-#define CANCONFIG \
-{\
- CAN500kBaud,\
- RT_CANMSG_BOX_SZ,\
- RT_CANSND_BOX_NUM,\
- RT_CAN_MODE_LOOPBACK,\
-};
+ can_rx_isr(&drv_can2.device, CAN_FIFO1);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+
+void CAN2_SCE_IRQHandler(void)
+{
+ uint32_t errtype;
+ rt_interrupt_enter();
+
+ if (CAN_GetIntStatus(drv_can2.CANx, CAN_INT_ERR))
+ {
+ errtype = drv_can2.CANx->ESTS;
+ /* ESTS -> LEC */
+ switch ((errtype & 0x70) >> 4)
+ {
+ case RT_CAN_BUS_BIT_PAD_ERR:
+ break;
+
+ case RT_CAN_BUS_FORMAT_ERR:
+ drv_can2.device.status.formaterrcnt++;
+ break;
+
+ case RT_CAN_BUS_ACK_ERR:
+ drv_can2.device.status.ackerrcnt++;
+ if (!READ_BIT(drv_can2.CANx->TSTS, CAN_TSTS_TXOKM0))
+ {
+ rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 0 << 8);
+ }
+ else if (!READ_BIT(drv_can2.CANx->TSTS, CAN_TSTS_TXOKM1))
+ {
+ rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 1 << 8);
+ }
+ else if (!READ_BIT(drv_can2.CANx->TSTS, CAN_TSTS_TXOKM2))
+ {
+ rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 2 << 8);
+ }
+ break;
+
+ case RT_CAN_BUS_IMPLICIT_BIT_ERR:
+ case RT_CAN_BUS_EXPLICIT_BIT_ERR:
+ drv_can2.device.status.biterrcnt++;
+ break;
+
+ case RT_CAN_BUS_CRC_ERR:
+ drv_can2.device.status.crcerrcnt++;
+ break;
+ }
+
+ drv_can2.device.status.lasterrtype = errtype & 0x70;
+ drv_can2.device.status.rcverrcnt = errtype >> 24;
+ drv_can2.device.status.snderrcnt = (errtype >> 16 & 0xFF);
+ drv_can2.device.status.errcode = errtype & 0x07;
+
+ CAN_ClearINTPendingBit(drv_can2.CANx, CAN_INT_ERR);
+ }
+ rt_interrupt_leave();
+}
+#endif /* BSP_USING_CAN2 */
+
+#if defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
+#ifdef BSP_USING_CAN
+void CAN_TX_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ if (CAN_GetFlagSTS(drv_can.CANx, CAN_FLAG_RQCPM0))
+ {
+ CAN_ClearFlag(drv_can.CANx, CAN_FLAG_RQCPM0);
+ rt_hw_can_isr(&drv_can.device, RT_CAN_EVENT_TX_DONE | (0x00 << 8));
+ }
+ if (CAN_GetFlagSTS(drv_can.CANx, CAN_FLAG_RQCPM1))
+ {
+ CAN_ClearFlag(drv_can.CANx, CAN_FLAG_RQCPM1);
+ rt_hw_can_isr(&drv_can.device, RT_CAN_EVENT_TX_DONE | (0x01 << 8));
+ }
+ if (CAN_GetFlagSTS(drv_can.CANx, CAN_FLAG_RQCPM2))
+ {
+ CAN_ClearFlag(drv_can.CANx, CAN_FLAG_RQCPM2);
+ rt_hw_can_isr(&drv_can.device, RT_CAN_EVENT_TX_DONE | (0x02 << 8));
+ }
+ rt_interrupt_leave();
+}
+
+void CAN_RX0_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ can_rx_isr(&drv_can.device, CAN_FIFO0);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+
+void CAN_RX1_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ can_rx_isr(&drv_can.device, CAN_FIFO1);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+
+void CAN_SCE_IRQHandler(void)
+{
+ uint32_t errtype;
+ rt_interrupt_enter();
+
+ if (CAN_GetIntStatus(drv_can.CANx, CAN_INT_ERR))
+ {
+ errtype = drv_can.CANx->ESTS;
+ /* ESTS -> LEC */
+ switch ((errtype & 0x70) >> 4)
+ {
+ case RT_CAN_BUS_BIT_PAD_ERR:
+ break;
+
+ case RT_CAN_BUS_FORMAT_ERR:
+ drv_can.device.status.formaterrcnt++;
+ break;
+
+ case RT_CAN_BUS_ACK_ERR:
+ drv_can.device.status.ackerrcnt++;
+ if (!READ_BIT(drv_can.CANx->TSTS, CAN_TSTS_TXOKM0))
+ {
+ rt_hw_can_isr(&drv_can.device, RT_CAN_EVENT_TX_FAIL | 0 << 8);
+ }
+ else if (!READ_BIT(drv_can.CANx->TSTS, CAN_TSTS_TXOKM1))
+ {
+ rt_hw_can_isr(&drv_can.device, RT_CAN_EVENT_TX_FAIL | 1 << 8);
+ }
+ else if (!READ_BIT(drv_can.CANx->TSTS, CAN_TSTS_TXOKM2))
+ {
+ rt_hw_can_isr(&drv_can.device, RT_CAN_EVENT_TX_FAIL | 2 << 8);
+ }
+ break;
+
+ case RT_CAN_BUS_IMPLICIT_BIT_ERR:
+ case RT_CAN_BUS_EXPLICIT_BIT_ERR:
+ drv_can.device.status.biterrcnt++;
+ break;
+
+ case RT_CAN_BUS_CRC_ERR:
+ drv_can.device.status.crcerrcnt++;
+ break;
+ }
+
+ drv_can.device.status.lasterrtype = errtype & 0x70;
+ drv_can.device.status.rcverrcnt = errtype >> 24;
+ drv_can.device.status.snderrcnt = (errtype >> 16 & 0xFF);
+ drv_can.device.status.errcode = errtype & 0x07;
+
+ CAN_ClearINTPendingBit(drv_can.CANx, CAN_INT_ERR);
+ }
+ rt_interrupt_leave();
+}
+#endif /* BSP_USING_CAN */
+#endif
int rt_hw_can_init(void)
{
- struct can_configure config = CANCONFIG;
+ struct can_configure config = CANDEFAULTCONFIG;
config.privmode = RT_CAN_MODE_NOPRIV;
config.ticks = 50;
+
#ifdef RT_CAN_USING_HDR
config.maxhdr = 14;
-#ifdef CAN2
- config.maxhdr = 28;
#endif
-#endif
- /* config default filter */
- CAN_FilterInitType filterConf = {0};
- filterConf.Filter_HighId = 0x0000;
- filterConf.Filter_LowId = 0x0000;
- filterConf.FilterMask_HighId = 0x0000;
- filterConf.FilterMask_LowId = 0x0000;
- filterConf.Filter_FIFOAssignment = CAN_FIFO0;
- filterConf.Filter_Num = CAN_FILTERNUM0;
- filterConf.Filter_Mode = CAN_Filter_IdMaskMode;
- filterConf.Filter_Scale = CAN_Filter_32bitScale;
- filterConf.Filter_Act = ENABLE;
#ifdef BSP_USING_CAN1
- filterConf.Filter_Num = 0;
+ /* config default filter */
+ drv_can1.FilterConfig.Filter_Num = 0;
+ drv_can1.FilterConfig.Filter_Mode = CAN_Filter_IdMaskMode;
+ drv_can1.FilterConfig.Filter_Scale = CAN_Filter_32bitScale;
+ drv_can1.FilterConfig.Filter_HighId = 0x0000;
+ drv_can1.FilterConfig.Filter_LowId = 0x0000;
+ drv_can1.FilterConfig.FilterMask_HighId = 0;
+ drv_can1.FilterConfig.FilterMask_LowId = 0;
+ drv_can1.FilterConfig.Filter_FIFOAssignment = CAN_FIFO0; // CAN_FIFO1 CAN_FIFO0
+ drv_can1.FilterConfig.Filter_Act = ENABLE;
- drv_can1.FilterConfig = filterConf;
drv_can1.device.config = config;
/* register CAN1 device */
- rt_hw_can_register(&drv_can1.device,
- drv_can1.name,
- &canops,
- &drv_can1);
+ rt_hw_can_register(&drv_can1.device, drv_can1.name, &canops, &drv_can1);
#endif /* BSP_USING_CAN1 */
#ifdef BSP_USING_CAN2
- filterConf.Filter_Num = 0;
+ /* config default filter */
+ drv_can2.FilterConfig.Filter_Num = 0;
+ drv_can2.FilterConfig.Filter_Mode = CAN_Filter_IdMaskMode;
+ drv_can2.FilterConfig.Filter_Scale = CAN_Filter_32bitScale;
+ drv_can2.FilterConfig.Filter_HighId = 0x0000;
+ drv_can2.FilterConfig.Filter_LowId = 0x0000;
+ drv_can2.FilterConfig.FilterMask_HighId = 0;
+ drv_can2.FilterConfig.FilterMask_LowId = 0;
+ drv_can2.FilterConfig.Filter_FIFOAssignment = CAN_FIFO0;
+ drv_can2.FilterConfig.Filter_Act = ENABLE;
- drv_can2.FilterConfig = filterConf;
drv_can2.device.config = config;
/* register CAN2 device */
- rt_hw_can_register(&drv_can2.device,
- drv_can2.name,
- &canops,
- &drv_can2);
+ rt_hw_can_register(&drv_can2.device, drv_can2.name, &canops, &drv_can2);
#endif /* BSP_USING_CAN2 */
+#if defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
+#ifdef BSP_USING_CAN
+ /* config default filter */
+ drv_can.FilterConfig.Filter_Num = 0;
+ drv_can.FilterConfig.Filter_Mode = CAN_Filter_IdMaskMode;
+ drv_can.FilterConfig.Filter_Scale = CAN_Filter_32bitScale;
+ drv_can.FilterConfig.Filter_HighId = 0x0000;
+ drv_can.FilterConfig.Filter_LowId = 0x0000;
+ drv_can.FilterConfig.FilterMask_HighId = 0;
+ drv_can.FilterConfig.FilterMask_LowId = 0;
+ drv_can.FilterConfig.Filter_FIFOAssignment = CAN_FIFO0;
+ drv_can.FilterConfig.Filter_Act = ENABLE;
+
+ drv_can.device.config = config;
+ /* register CAN2 device */
+ rt_hw_can_register(&drv_can.device, drv_can.name, &canops, &drv_can);
+#endif /* BSP_USING_CAN2 */
+#endif
+
return 0;
}
diff --git a/bsp/n32/libraries/n32_drivers/drv_can.h b/bsp/n32/libraries/n32_drivers/drv_can.h
index 0dafab3b3b..4f73e68cca 100644
--- a/bsp/n32/libraries/n32_drivers/drv_can.h
+++ b/bsp/n32/libraries/n32_drivers/drv_can.h
@@ -1,36 +1,11 @@
-/*****************************************************************************
- * Copyright (c) 2019, Nations Technologies Inc.
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
*
- * All rights reserved.
- * ****************************************************************************
+ * SPDX-License-Identifier: Apache-2.0
*
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Nations' name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ****************************************************************************/
-
-/**
- * @file drv_can.h
- * @author Nations
- * @version v1.0.0
- *
- * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
+ * Change Logs:
+ * Date Author Notes
+ * 2022-10-19 Nations first version
*/
#ifndef __DRV_CAN_H__
@@ -38,78 +13,45 @@
#include
#include
-#include "n32g45x_can.h"
+#include